R5F71242N50NP

REJ09B0243-0400 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7125 Group, SH7124 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family SH7125 SH7124 R5F7125 R5F7124 Rev.4.00 Revision Date: Jul. 25, 2008 Rev. 4.00 Jul. 25, 2008 Page ii of xx Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 4.00 Jul. 25, 2008 Page iii of xx General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 4.00 Jul. 25, 2008 Page iv of xx Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 4.00 Jul. 25, 2008 Page v of xx Preface The SH7125 Group and SH7124 Group RISC (Reduced Instruction Set Computer) microcomputer include a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the SH7125 Group and SH7124 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7125 Group and SH7124 Group to the target users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. • In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual. • In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 4.00 Jul. 25, 2008 Page vi of xx SH7125 Group and SH7124 Group manuals: Document Title SH7125 Group, SH7124 Group Hardware Manual SH-1/SH-2/SH-DSP Software Manual Document No. This manual REJ09B0171 User's manuals for development tools: Document Title SuperH RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.00 User's Manual SuperHTM RISC engine High-performance Embedded Workshop 3 User's Manual SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial TM Document No. REJ10B0152 REJ10B0025 REJ10B0023 Application note: Document Title SuperH RISC engine C/C++ Compiler Package Application Note Document No. REJ05B0463 All trademarks and registered trademarks are the property of their respective owners. Rev. 4.00 Jul. 25, 2008 Page vii of xx Rev. 4.00 Jul. 25, 2008 Page viii of xx Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features of SH7125 and SH7124........................................................................................... 1 Block Diagram....................................................................................................................... 6 Pin Assignments .................................................................................................................... 7 Pin Functions ....................................................................................................................... 11 Section 2 CPU......................................................................................................17 2.1 2.2 Features................................................................................................................................ 17 Register Configuration......................................................................................................... 18 2.2.1 General Registers (Rn)............................................................................................ 19 2.2.2 Control Registers .................................................................................................... 19 2.2.3 System Registers..................................................................................................... 21 2.2.4 Initial Values of Registers....................................................................................... 21 Data Formats........................................................................................................................ 22 2.3.1 Register Data Format .............................................................................................. 22 2.3.2 Memory Data Formats ............................................................................................ 22 2.3.3 Immediate Data Formats......................................................................................... 23 Features of Instructions........................................................................................................ 23 2.4.1 RISC Type .............................................................................................................. 23 2.4.2 Addressing Modes .................................................................................................. 26 2.4.3 Instruction Formats ................................................................................................. 29 Instruction Set ...................................................................................................................... 33 2.5.1 Instruction Set by Type........................................................................................... 33 2.5.2 Data Transfer Instructions ...................................................................................... 37 2.5.3 Arithmetic Operation Instructions .......................................................................... 39 2.5.4 Logic Operation Instructions .................................................................................. 41 2.5.5 Shift Instructions..................................................................................................... 42 2.5.6 Branch Instructions ................................................................................................. 43 2.5.7 System Control Instructions.................................................................................... 44 Processing States.................................................................................................................. 46 2.3 2.4 2.5 2.6 Section 3 MCU Operating Modes .......................................................................49 3.1 3.2 3.3 Selection of Operating Modes ............................................................................................. 49 Input/Output Pins................................................................................................................. 50 Operating Modes.................................................................................................................. 50 3.3.1 Mode 3 (Single Chip Mode) ................................................................................... 50 Rev. 4.00 Jul. 25, 2008 Page ix of xx 3.4 3.5 3.6 Address Map ........................................................................................................................ 51 Initial State in This LSI........................................................................................................ 54 Note on Changing Operating Mode ..................................................................................... 54 Section 4 Clock Pulse Generator (CPG) .............................................................55 4.1 4.2 4.3 4.4 Features................................................................................................................................ 55 Input/Output Pins................................................................................................................. 58 Clock Operating Mode......................................................................................................... 59 Register Descriptions ........................................................................................................... 61 4.4.1 Frequency Control Register (FRQCR) ................................................................... 61 4.4.2 Oscillation Stop Detection Control Register (OSCCR) .......................................... 64 Changing Frequency ............................................................................................................ 65 Oscillator.............................................................................................................................. 66 4.6.1 Connecting Crystal Resonator ................................................................................ 66 4.6.2 External Clock Input Method.................................................................................. 67 Function for Detecting Oscillator Stop ................................................................................ 68 Usage Notes ......................................................................................................................... 69 4.8.1 Note on Crystal Resonator...................................................................................... 69 4.8.2 Notes on Board Design ........................................................................................... 69 4.5 4.6 4.7 4.8 Section 5 Exception Handling .............................................................................71 5.1 Overview.............................................................................................................................. 71 5.1.1 Types of Exception Handling and Priority ............................................................. 71 5.1.2 Exception Handling Operations.............................................................................. 72 5.1.3 Exception Handling Vector Table .......................................................................... 73 Resets................................................................................................................................... 75 5.2.1 Types of Resets....................................................................................................... 75 5.2.2 Power-On Reset ...................................................................................................... 75 5.2.3 Manual Reset .......................................................................................................... 76 Address Errors ..................................................................................................................... 77 5.3.1 Address Error Sources ............................................................................................ 77 5.3.2 Address Error Exception Source............................................................................. 78 Interrupts.............................................................................................................................. 79 5.4.1 Interrupt Sources..................................................................................................... 79 5.4.2 Interrupt Priority ..................................................................................................... 80 5.4.3 Interrupt Exception Handling ................................................................................. 80 Exceptions Triggered by Instructions .................................................................................. 81 5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 81 5.5.2 Trap Instructions..................................................................................................... 81 5.5.3 Illegal Slot Instructions........................................................................................... 82 5.2 5.3 5.4 5.5 Rev. 4.00 Jul. 25, 2008 Page x of xx 5.6 5.7 5.8 5.5.4 General Illegal Instructions..................................................................................... 82 Cases when Exceptions are Accepted .................................................................................. 83 Stack States after Exception Handling Ends........................................................................ 84 Usage Notes ......................................................................................................................... 86 5.8.1 Value of Stack Pointer (SP) .................................................................................... 86 5.8.2 Value of Vector Base Register (VBR).................................................................... 86 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling.......... 86 5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 87 Section 6 Interrupt Controller (INTC) .................................................................89 6.1 6.2 6.3 Features................................................................................................................................ 89 Input/Output Pins................................................................................................................. 91 Register Descriptions ........................................................................................................... 92 6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 93 6.3.2 IRQ Control Register (IRQCR) .............................................................................. 94 6.3.3 IRQ Status register (IRQSR) .................................................................................. 96 6.3.4 Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM) ....................................................................... 99 Interrupt Sources................................................................................................................ 102 6.4.1 External Interrupts ................................................................................................ 102 6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 103 6.4.3 User Break Interrupt ............................................................................................. 103 Interrupt Exception Handling Vector Table....................................................................... 104 Interrupt Operation ............................................................................................................ 107 6.6.1 Interrupt Sequence ................................................................................................ 107 6.6.2 Stack after Interrupt Exception Handling ............................................................. 110 Interrupt Response Time.................................................................................................... 110 Usage Note......................................................................................................................... 112 6.4 6.5 6.6 6.7 6.8 Section 7 User Break Controller (UBC) ............................................................113 7.1 7.2 Features.............................................................................................................................. 113 Register Descriptions ......................................................................................................... 115 7.2.1 Break Address Register A (BARA) ...................................................................... 116 7.2.2 Break Address Mask Register A (BAMRA)......................................................... 116 7.2.3 Break Bus Cycle Register A (BBRA)................................................................... 117 7.2.4 Break Data Register A (BDRA) ........................................................................... 119 7.2.5 Break Data Mask Register A (BDMRA) .............................................................. 120 7.2.6 Break Address Register B (BARB) ...................................................................... 121 7.2.7 Break Address Mask Register B (BAMRB) ......................................................... 122 7.2.8 Break Data Register B (BDRB)............................................................................ 123 Rev. 4.00 Jul. 25, 2008 Page xi of xx 7.3 7.4 7.2.9 Break Data Mask Register B (BDMRB)............................................................... 124 7.2.10 Break Bus Cycle Register B (BBRB) ................................................................... 125 7.2.11 Break Control Register (BRCR) ........................................................................... 127 7.2.12 Execution Times Break Register (BETR)............................................................. 131 7.2.13 Branch Source Register (BRSR)........................................................................... 132 7.2.14 Branch Destination Register (BRDR)................................................................... 133 Operation ........................................................................................................................... 134 7.3.1 Flow of the User Break Operation ........................................................................ 134 7.3.2 Break on Instruction Fetch Cycle ......................................................................... 135 7.3.3 Break on Data Access Cycle................................................................................. 135 7.3.4 Sequential Break................................................................................................... 137 7.3.5 Value of Saved Program Counter ......................................................................... 137 7.3.6 PC Trace ............................................................................................................... 138 7.3.7 Usage Examples.................................................................................................... 139 Usage Notes ....................................................................................................................... 144 Section 8 Bus State Controller (BSC) ...............................................................147 8.1 8.2 8.3 8.4 Features.............................................................................................................................. 147 Address Map ...................................................................................................................... 147 Access to on-chip FLASH and on-chip RAM ................................................................... 147 Access to on-chip Peripheral I/O Register ......................................................................... 148 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2).....................................151 9.1 9.2 9.3 Features.............................................................................................................................. 151 Input/Output Pins............................................................................................................... 157 Register Descriptions ......................................................................................................... 158 9.3.1 Timer Control Register (TCR).............................................................................. 162 9.3.2 Timer Mode Register (TMDR)............................................................................. 166 9.3.3 Timer I/O Control Register (TIOR)...................................................................... 169 9.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 188 9.3.5 Timer Interrupt Enable Register (TIER)............................................................... 189 9.3.6 Timer Status Register (TSR)................................................................................. 194 9.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 202 9.3.8 Timer Input Capture Control Register (TICCR)................................................... 203 9.3.9 Timer A/D Converter Start Request Control Register (TADCR) ......................... 205 9.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4)...................................................................... 208 9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) ................................................................ 208 9.3.12 Timer Counter (TCNT)......................................................................................... 209 Rev. 4.00 Jul. 25, 2008 Page xii of xx 9.4 9.5 9.6 9.7 9.3.13 Timer General Register (TGR) ............................................................................. 209 9.3.14 Timer Start Register (TSTR) ................................................................................ 210 9.3.15 Timer Synchronous Register (TSYR)................................................................... 212 9.3.16 Timer Read/Write Enable Register (TRWER) ..................................................... 214 9.3.17 Timer Output Master Enable Register (TOER) .................................................... 215 9.3.18 Timer Output Control Register 1 (TOCR1).......................................................... 216 9.3.19 Timer Output Control Register 2 (TOCR2).......................................................... 219 9.3.20 Timer Output Level Buffer Register (TOLBR) .................................................... 222 9.3.21 Timer Gate Control Register (TGCR) .................................................................. 223 9.3.22 Timer Subcounter (TCNTS) ................................................................................. 225 9.3.23 Timer Dead Time Data Register (TDDR)............................................................. 226 9.3.24 Timer Cycle Data Register (TCDR) ..................................................................... 226 9.3.25 Timer Cycle Buffer Register (TCBR)................................................................... 227 9.3.26 Timer Interrupt Skipping Set Register (TITCR)................................................... 227 9.3.27 Timer Interrupt Skipping Counter (TITCNT)....................................................... 229 9.3.28 Timer Buffer Transfer Set Register (TBTER) ...................................................... 230 9.3.29 Timer Dead Time Enable Register (TDER) ......................................................... 232 9.3.30 Timer Waveform Control Register (TWCR) ........................................................ 233 9.3.31 Bus Master Interface............................................................................................. 234 Operation ........................................................................................................................... 235 9.4.1 Basic Functions..................................................................................................... 235 9.4.2 Synchronous Operation......................................................................................... 241 9.4.3 Buffer Operation................................................................................................... 243 9.4.4 Cascaded Operation .............................................................................................. 247 9.4.5 PWM Modes......................................................................................................... 252 9.4.6 Phase Counting Mode........................................................................................... 257 9.4.7 Reset-Synchronized PWM Mode ......................................................................... 264 9.4.8 Complementary PWM Mode................................................................................ 267 9.4.9 A/D Converter Start Request Delaying Function.................................................. 308 9.4.10 External Pulse Width Measurement...................................................................... 312 9.4.11 Dead Time Compensation .................................................................................... 313 9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 315 Interrupt Sources................................................................................................................ 316 9.5.1 Interrupt Sources and Priorities ............................................................................ 316 9.5.2 A/D Converter Activation..................................................................................... 319 Operation Timing............................................................................................................... 321 9.6.1 Input/Output Timing ............................................................................................. 321 9.6.2 Interrupt Signal Timing ........................................................................................ 328 Usage Notes ....................................................................................................................... 332 9.7.1 Module Standby Mode Setting ............................................................................. 332 Rev. 4.00 Jul. 25, 2008 Page xiii of xx 9.7.2 9.7.3 9.7.4 9.7.5 9.7.6 9.7.7 9.7.8 9.7.9 9.7.10 9.7.11 9.7.12 9.7.13 9.7.14 9.7.15 9.7.16 9.7.17 9.7.18 9.7.19 9.8 Input Clock Restrictions ....................................................................................... 332 Caution on Period Setting ..................................................................................... 333 Contention between TCNT Write and Clear Operations...................................... 333 Contention between TCNT Write and Increment Operations............................... 334 Contention between TGR Write and Compare Match .......................................... 335 Contention between Buffer Register Write and Compare Match ......................... 336 Contention between Buffer Register Write and TCNT Clear ............................... 337 Contention between TGR Read and Input Capture............................................... 338 Contention between TGR Write and Input Capture.............................................. 339 Contention between Buffer Register Write and Input Capture ............................. 340 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection .... 340 Counter Value during Complementary PWM Mode Stop .................................... 342 Buffer Operation Setting in Complementary PWM Mode ................................... 342 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .................. 343 Overflow Flags in Reset Synchronous PWM Mode ............................................. 344 Contention between Overflow/Underflow and Counter Clearing......................... 345 Contention between TCNT Write and Overflow/Underflow................................ 346 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode ..................................................................... 346 9.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode................................................................... 347 9.7.21 Interrupts in Module Standby Mode ..................................................................... 347 9.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection............ 347 MTU2 Output Pin Initialization......................................................................................... 348 9.8.1 Operating Modes .................................................................................................. 348 9.8.2 Reset Start Operation ............................................................................................ 348 9.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. ................. 349 9.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. ............................. 350 Section 10 Port Output Enable (POE) ...............................................................381 10.1 Features.............................................................................................................................. 381 10.2 Input/Output Pins............................................................................................................... 383 10.3 Register Descriptions ......................................................................................................... 384 10.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 385 10.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 388 10.3.3 Input Level Control/Status Register 3 (ICSR3) .................................................... 389 10.3.4 Software Port Output Enable Register (SPOER) .................................................. 391 10.3.5 Port Output Enable Control Register 1 (POECR1)............................................... 393 10.3.6 Port Output Enable Control Register 2 (POECR2)............................................... 394 Rev. 4.00 Jul. 25, 2008 Page xiv of xx 10.4 Operation ........................................................................................................................... 396 10.4.1 Input Level Detection Operation .......................................................................... 396 10.4.2 Output-Level Compare Operation ........................................................................ 398 10.4.3 Release from High-Impedance State .................................................................... 398 10.5 Interrupts............................................................................................................................ 399 10.6 Usage Note......................................................................................................................... 400 10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer ............... 400 Section 11 Watchdog Timer (WDT) .................................................................401 11.1 Features.............................................................................................................................. 401 11.2 Input/Output Pin for WDT................................................................................................. 403 11.3 Register Descriptions ......................................................................................................... 404 11.3.1 Watchdog Timer Counter (WTCNT).................................................................... 404 11.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 405 11.3.3 Notes on Register Access ..................................................................................... 407 11.4 Operation ........................................................................................................................... 408 11.4.1 Canceling Software Standbys ............................................................................... 408 11.4.2 Using Watchdog Timer Mode .............................................................................. 408 11.4.3 Using Interval Timer Mode .................................................................................. 409 11.5 Usage Note......................................................................................................................... 410 Section 12 Serial Communication Interface (SCI) ............................................411 12.1 Features.............................................................................................................................. 411 12.2 Input/Output Pins............................................................................................................... 413 12.3 Register Descriptions ......................................................................................................... 414 12.3.1 Receive Shift Register (SCRSR) .......................................................................... 415 12.3.2 Receive Data Register (SCRDR) .......................................................................... 415 12.3.3 Transmit Shift Register (SCTSR) ......................................................................... 415 12.3.4 Transmit Data Register (SCTDR)......................................................................... 416 12.3.5 Serial Mode Register (SCSMR)............................................................................ 416 12.3.6 Serial Control Register (SCSCR).......................................................................... 419 12.3.7 Serial Status Register (SCSSR) ............................................................................ 422 12.3.8 Serial Port Register (SCSPTR) ............................................................................. 428 12.3.9 Serial Direction Control Register (SCSDCR)....................................................... 430 12.3.10 Bit Rate Register (SCBRR) .................................................................................. 431 12.4 Operation ........................................................................................................................... 442 12.4.1 Overview .............................................................................................................. 442 12.4.2 Operation in Asynchronous Mode ........................................................................ 444 12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)............... 454 12.4.4 Multiprocessor Communication Function ............................................................ 463 Rev. 4.00 Jul. 25, 2008 Page xv of xx 12.4.5 Multiprocessor Serial Data Transmission ............................................................. 465 12.4.6 Multiprocessor Serial Data Reception .................................................................. 466 12.5 SCI Interrupt Sources......................................................................................................... 469 12.6 Serial Port Register (SCSPTR) and SCI Pins .................................................................... 470 12.7 Usage Notes ....................................................................................................................... 471 12.7.1 SCTDR Writing and TDRE Flag.......................................................................... 471 12.7.2 Multiple Receive Error Occurrence ...................................................................... 471 12.7.3 Break Detection and Processing ........................................................................... 472 12.7.4 Sending a Break Signal......................................................................................... 472 12.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 472 12.7.6 Note on Using External Clock in Clock Synchronous Mode................................ 474 12.7.7 Module Standby Mode Setting ............................................................................. 474 Section 13 A/D Converter (ADC) .....................................................................475 13.1 Features.............................................................................................................................. 475 13.2 Input/Output Pins............................................................................................................... 477 13.3 Register Descriptions ......................................................................................................... 478 13.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7).................................................. 479 13.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) .................. 479 13.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ................................. 482 13.3.4 A/D Trigger Select Register_0 (ADTSR_0)......................................................... 485 13.4 Operation ........................................................................................................................... 489 13.4.1 Single Mode.......................................................................................................... 489 13.4.2 Continuous Scan Mode......................................................................................... 489 13.4.3 Single-Cycle Scan Mode ...................................................................................... 490 13.4.4 Input Sampling and A/D Conversion Time .......................................................... 490 13.4.5 A/D Converter Activation by MTU2 .................................................................... 493 13.4.6 External Trigger Input Timing.............................................................................. 493 13.4.7 2-Channel Scanning.............................................................................................. 494 13.5 Interrupt Sources................................................................................................................ 495 13.6 Definitions of A/D Conversion Accuracy.......................................................................... 496 13.7 Usage Notes ....................................................................................................................... 499 13.7.1 Module Standby Mode Setting ............................................................................. 499 13.7.2 Permissible Signal Source Impedance .................................................................. 499 13.7.3 Influences on Absolute Accuracy ......................................................................... 499 13.7.4 Range of Analog Power Supply and Other Pin Settings....................................... 500 13.7.5 Notes on Board Design ......................................................................................... 500 13.7.6 Notes on Noise Countermeasures ......................................................................... 501 Rev. 4.00 Jul. 25, 2008 Page xvi of xx Section 14 Compare Match Timer (CMT) ........................................................503 14.1 Features.............................................................................................................................. 503 14.2 Register Descriptions ......................................................................................................... 504 14.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 505 14.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 505 14.2.3 Compare Match Counter (CMCNT) ..................................................................... 507 14.2.4 Compare Match Constant Register (CMCOR) ..................................................... 507 14.3 Operation ........................................................................................................................... 508 14.3.1 Interval Count Operation ...................................................................................... 508 14.3.2 CMCNT Count Timing......................................................................................... 508 14.4 Interrupts............................................................................................................................ 509 14.4.1 CMT Interrupt Sources ......................................................................................... 509 14.4.2 Timing of Setting Compare Match Flag ............................................................... 509 14.4.3 Timing of Clearing Compare Match Flag............................................................. 509 14.5 Usage Notes ....................................................................................................................... 510 14.5.1 Module Standby Mode Setting ............................................................................. 510 14.5.2 Conflict between Write and Compare-Match Processes of CMCNT ................... 510 14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 511 14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 512 14.5.5 Compare Match between CMCNT and CMCOR ................................................. 512 Section 15 Pin Function Controller (PFC).........................................................513 15.1 Register Descriptions ......................................................................................................... 521 15.1.1 Port A I/O Register L (PAIORL).......................................................................... 522 15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4).................................. 522 15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)........................................ 533 15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1) ... 534 15.1.5 Port E I/O Register L (PEIORL)........................................................................... 539 15.1.6 Port E Control Registers L1 to L4 (PECRL1 to PECRL4) ................................... 539 15.1.7 IRQOUT Function Control Register (IFCR) ........................................................ 549 15.2 Usage Notes ....................................................................................................................... 550 Section 16 I/O Ports...........................................................................................551 16.1 Port A................................................................................................................................. 552 16.1.1 Register Descriptions............................................................................................ 553 16.1.2 Port A Data Register L (PADRL)......................................................................... 553 16.1.3 Port A Port Register L (PAPRL) .......................................................................... 557 16.2 Port B ................................................................................................................................. 559 16.2.1 Register Descriptions............................................................................................ 559 Rev. 4.00 Jul. 25, 2008 Page xvii of xx 16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 560 16.2.3 Port B Port Registers H and L (PBPRH and PBPRL) .......................................... 563 16.3 Port E ................................................................................................................................. 566 16.3.1 Register Descriptions............................................................................................ 568 16.3.2 Port E Data Register L (PEDRL).......................................................................... 568 16.3.3 Port E Port Register L (PEPRL) ........................................................................... 571 16.4 Port F ................................................................................................................................. 573 16.4.1 Register Descriptions............................................................................................ 573 16.4.2 Port F Data Register L (PFDRL) .......................................................................... 574 Section 17 Flash Memory..................................................................................575 17.1 Features.............................................................................................................................. 575 17.2 Overview............................................................................................................................ 577 17.2.1 Block Diagram...................................................................................................... 577 17.2.2 Operating Mode .................................................................................................... 578 17.2.3 Mode Comparison ................................................................................................ 579 17.2.4 Flash Memory Configuration................................................................................ 580 17.2.5 Block Division ...................................................................................................... 580 17.2.6 Programming/Erasing Interface ............................................................................ 581 17.3 Input/Output Pins............................................................................................................... 583 17.4 Register Descriptions ......................................................................................................... 583 17.4.1 Registers ............................................................................................................... 583 17.4.2 Programming/Erasing Interface Registers ............................................................ 586 17.4.3 Programming/Erasing Interface Parameters ......................................................... 592 17.5 On-Board Programming Mode .......................................................................................... 607 17.5.1 Boot Mode ............................................................................................................ 607 17.5.2 User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version) ................................ 611 17.6 Protection........................................................................................................................... 620 17.6.1 Hardware Protection ............................................................................................. 620 17.6.2 Software Protection............................................................................................... 621 17.6.3 Error Protection .................................................................................................... 621 17.7 Usage Notes ....................................................................................................................... 623 17.7.1 Interrupts during Programming/Erasing ............................................................... 623 17.7.2 Other Notes........................................................................................................... 625 17.8 Supplementary Information ............................................................................................... 627 17.8.1 Specifications of the Standard Serial Communications Interface in Boot Mode ........................................................................................................ 627 17.8.2 Areas for Storage of the Procedural Program and Data for Programming............ 654 17.9 Off-Board Programming Mode.......................................................................................... 658 Rev. 4.00 Jul. 25, 2008 Page xviii of xx Section 18 RAM ................................................................................................659 18.1 Usage Notes ....................................................................................................................... 660 18.1.1 Module Standby Mode Setting ............................................................................. 660 18.1.2 Address Error........................................................................................................ 660 18.1.3 Initial Values in RAM........................................................................................... 660 Section 19 Power-Down Modes ........................................................................661 19.1 Features.............................................................................................................................. 661 19.1.1 Types of Power-Down Modes .............................................................................. 661 19.2 Input/Output Pins............................................................................................................... 663 19.3 Register Descriptions ......................................................................................................... 663 19.3.1 Standby Control Register 1 (STBCR1)................................................................. 664 19.3.2 Standby Control Register 2 (STBCR2)................................................................. 665 19.3.3 Standby Control Register 3 (STBCR3)................................................................. 666 19.3.4 Standby Control Register 4 (STBCR4)................................................................. 667 19.3.5 Standby Control Register 5 (STBCR5)................................................................. 668 19.3.6 Standby Control Register 6 (STBCR6)................................................................. 669 19.3.7 RAM Control Register (RAMCR)........................................................................ 670 19.4 Sleep Mode ........................................................................................................................ 671 19.4.1 Transition to Sleep Mode...................................................................................... 671 19.4.2 Canceling Sleep Mode .......................................................................................... 671 19.5 Software Standby Mode..................................................................................................... 672 19.5.1 Transition to Software Standby Mode .................................................................. 672 19.5.2 Canceling Software Standby Mode ...................................................................... 673 19.6 Module Standby Mode....................................................................................................... 674 19.6.1 Transition to Module Standby Mode .................................................................... 674 19.6.2 Canceling Module Standby Function.................................................................... 674 19.7 Usage Note......................................................................................................................... 674 19.7.1 Current Consumption while Waiting for Oscillation to be Stabilized .................. 674 19.7.2 Executing the SLEEP Instruction ......................................................................... 674 Section 20 List of Registers ...............................................................................675 20.1 Register Address Table (In the Order from Lower Addresses).......................................... 676 20.2 Register Bit List ................................................................................................................. 684 20.3 Register States in Each Operating Mode ........................................................................... 698 Section 21 Electrical Characteristics .................................................................707 21.1 Absolute Maximum Ratings .............................................................................................. 707 21.2 DC Characteristics ............................................................................................................. 708 21.3 AC Characteristics ............................................................................................................. 711 Rev. 4.00 Jul. 25, 2008 Page xix of xx 21.3.1 Clock Timing ........................................................................................................ 712 21.3.2 Control Signal Timing .......................................................................................... 714 21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) Timing............................................ 717 21.3.4 I/O Port Timing..................................................................................................... 719 21.3.5 Watchdog Timer (WDT) Timing.......................................................................... 720 21.3.6 Serial Communication Interface (SCI) Timing..................................................... 721 21.3.7 Port Output Enable (POE) Timing........................................................................ 723 21.3.8 A/D Converter Timing.......................................................................................... 724 21.3.9 Conditions for Testing AC Characteristics ........................................................... 725 21.4 A/D Converter Characteristics ........................................................................................... 726 21.5 Flash Memory Characteristics ........................................................................................... 727 21.6 Usage Note......................................................................................................................... 728 21.6.1 Notes on Connecting VCL Capacitor...................................................................... 728 Appendix A. B. C. .........................................................................................................729 Pin States ........................................................................................................................... 729 Product Code Lineup ......................................................................................................... 733 Package Dimensions .......................................................................................................... 734 Main Revisions and Additions in this Edition.....................................................739 Index .........................................................................................................745 Rev. 4.00 Jul. 25, 2008 Page xx of xx Section 1 Overview Section 1 Overview 1.1 Features of SH7125 and SH7124 This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a ROM, a RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. The version of the on-chip ROM is F-ZTATTM (Flexible Zero Turn Around Time)* that includes flash memory. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board. The features of this LSI are listed in table 1.1. Note: * F-ZTATTM is a trademark of Renesas Technology Corp. Rev. 4.00 Jul. 25, 2008 Page 1 of 750 REJ09B0243-0400 Section 1 Overview Table 1.1 Items CPU Features Specification • • • • • • • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles C language-oriented 62 basic instructions Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. For details, see section 5.8.4, Notes on Slot Illegal Instruction Exception Handling. Note: Operating modes • • Operating modes  Single chip mode Operating states  Program execution state  Exception handling state • Power-down modes  Sleep mode  Software standby mode  Module standby mode User break controller (UBC) • • • Addresses, data values, type of access, and data size can all be set as break conditions Supports a sequential break function Two break channels 128 kbytes (SH71253, SH71243) 64 kbytes (SH71252, SH71242) 32 kbytes (SH71241) 8 kbytes On-chip ROM • • • On-chip RAM • Rev. 4.00 Jul. 25, 2008 Page 2 of 750 REJ09B0243-0400 Section 1 Overview Items Interrupt controller (INTC) Specification • External interrupt pins  SH7125: Five pins (NMI and IRQ3 to IRQ0)  SH7124: Four pins (NMI and IRQ3 to IRQ1) • • On-chip peripheral interrupts: Priority level set for each module Vector addresses: A vector address for each interrupt source E10A emulator support Clock mode: Input clock can be selected from external input or crystal resonator Four types of clocks generated:  CPU clock: Maximum 50 MHz  Bus clock: Maximum 40 MHz  Peripheral clock: Maximum 40 MHz  MTU2 clock: Maximum 40 MHz User debugging interface (H-UDI) Clock pulse generator (CPG) • • • Watchdog timer (WDT) • • On-chip one-channel watchdog timer Interrupt generation is supported. Rev. 4.00 Jul. 25, 2008 Page 3 of 750 REJ09B0243-0400 Section 1 Overview Items Multi-function timer pulse unit 2 (MTU2) Specification • • • • • • • Maximum 16 lines of pulse input/output and three lines of pulse input based on six channels of 16-bit timers (SH7125) Maximum 12 lines of pulse input/output and three lines of pulse input based on six channels of 16-bit timers (SH7124) 21 output compare and input capture registers A total of 21 independent comparators Selection of eight counter input clocks Input capture function Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes • • Synchronization of multiple counters Complementary PWM output mode  Non-overlapping waveforms output for 6-phase inverter control  Automatic dead time setting  0% to 100% PWM duty cycle specifiable  Output suppression  A/D conversion delaying function  Dead time compensation  Interrupt skipping at crest or trough • Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty cycle • Phase counting mode Two-phase encoder pulse counting available High-impedance control of waveform output pins and channel 0 pins in MTU2 16-bit counters Compare match interrupts can be generated Two channels Clock synchronous or asynchronous mode Three channels Port output enable (POE) • Compare match timer • (CMT) • • Serial communication interface (SCI) • • Rev. 4.00 Jul. 25, 2008 Page 4 of 750 REJ09B0243-0400 Section 1 Overview Items A/D converter (ADC) Specification • • • 10 bits × 8 channels Conversion request by external triggers or MTU2 Two sample-and-hold function units (two channels can be sampled simultaneously) 37 general input/output pins and eight general input pins (SH7125) 23 general input/output pins and eight general input pins (SH7124) Input or output can be selected for each bit QFP-64 (0.8 pitch) (SH7125) LQFP-64 (0.5 pitch) (SH7125) LQFP-48 (0.65 pitch) (SH7124) VQFN-64 (0.4 pitch) (SH7125) VQFN-52 (0.4 pitch) (SH7124) Vcc: 4.0 to 5.5 V AVcc: 4.0 to 5.5 V I/O ports • • • Packages • • • • • Power supply voltage • • Rev. 4.00 Jul. 25, 2008 Page 5 of 750 REJ09B0243-0400 Section 1 Overview 1.2 Block Diagram The block diagram of this LSI is shown in figure 1.1. SH2 CPU UBC L bus (Iφ) Internal bus controller ROM RAM I bus (Bφ) Peripheral bus controller Peripheral bus (Pφ) I/O port (PFC) SCI CMT H-UDI INTC Powerdown mode control WDT CPG MTU2 POE ADC [Legend] ROM: RAM: UBC: H-UDI: INTC: CPG: WDT: CPU: On-chip ROM On-chip RAM User break controller User debugging interface Interrupt controller Clock pulse generator Watchdog timer Central processing unit PFC: MTU2: POE: SCI: CMT: ADC: Pin function controller Multi-function timer pulse unit 2 Port output enable Serial communication interface Compare match timer A/D converter Figure 1.1 Block Diagram Rev. 4.00 Jul. 25, 2008 Page 6 of 750 REJ09B0243-0400 Section 1 Overview 1.3 Pin Assignments PB5/IRQ3/TIC5U PLLVSS MD1 FWE/ASEBRK/ASEBRKAK NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/RXD0 VCL PA1/POE1/TXD0 VCC PA2/IRQ0/SCK0 VSS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PB3/IRQ1/POE1/TIC5V PB2/IRQ0/POE0 PB1/TIC5W AVSS PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 AVCC PB16/POE3 PE15/TIOC4D/IRQOUT PE14/TIOC4C QFP-64 LQFP-64 (Top view) PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA5/IRQ3/SCK1 PA6/TCLKA PA7/TCLKB/SCK2/TCK PA8/TCLKC/RXD2/TDI PA9/TCLKD/TXD2/TDO/POE8 PA10/RXD0 VSS PA11/TXD0/ADTRG VCC PA12/SCK0 PA13/SCK1 PA14/RXD1 PA15/TXD1 PE0/TIOC0A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 1.2 (1) Pin Assignments of SH7125 PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D VCC PE9/TIOC3B VSS PE10/TIOC3C VCL PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A/SCK1 PE5/TIOC1B/TXD1 PE4/TIOC1A/RXD1 PE3/TIOC0D/SCK0 PE2/TIOC0C/TXD0 PE1/TIOC0B/RXD0 Pins for the system development tool. When these pins are used for an on-chip debugger, they are not available. Rev. 4.00 Jul. 25, 2008 Page 7 of 750 REJ09B0243-0400 Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PB3/IRQ1/POE1/TIC5V 49 PB2/IRQ0/POE0 50 PB1/TIC5W 51 AVSS 52 PF7/AN7 53 PF6/AN6 54 PF5/AN5 55 PF4/AN4 56 PF3/AN3 57 PF2/AN2 58 PF1/AN1 59 PF0/AN0 60 AVCC 61 PB16/POE3 62 PB15/TIOC4D/IRQOUT 63 PE14/TIOC4C 64 32 PA3/IRQ1/RXD1/TRST 31 PA4/IRQ2/TXD1/TMS 30 PA5/IRQ3/SCK1 29 PA6/TCLKA 28 PA7/TCLKB/SCK2/TCK 27 PA8/TCLKC/RXD2/TDI 26 PA9/TCLKD/TXD2/TDO/POE8 25 PA10/RXD0 24 VSS 23 PA11/TXD0/ADTRG 22 VCC 21 PA12/SCK0 20 PA13/SCK1 19 PA14/RXD1 18 PA15/TXD1 17 PE0/TIOC0A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D VCC PE9/TIOC3B VSS PE10/TIOC3C VCL PE8/TIOC3A PE7/TIOC2B PE6/TIOC2A/SCK1 PE5/TIOC1B/TXD1 PE4/TIOC1A/RXD1 PE3/TIOC0D/SCK0 PE2/TIOC0C/TXD0 PE1/TIOC0B/RXD0 Figure 1.2 (2) Pin Assignments of SH7125 Rev. 4.00 Jul. 25, 2008 Page 8 of 750 REJ09B0243-0400 PB5/IRQ3/TIC5U PLLVSS MD1 FWE/ASEBRK/ASEBRKAK NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/RXD0 VCL PA1/POE1/TXD0 VCC PA2/IRQ0/SCK0 VSS VQFN-64 (Top view) Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 25 PB3/IRQ1/POE1/TIC5V PB1/TIC5W AVSS PF7/AN7 PF6/AN6 PF5/AN5 PF4/AN4 PF3/AN3 PF2/AN2 PF1/AN1 PF0/AN0 AVCC 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 PB5/IRQ3/TIC5U PLLVSS MD1 FWE/ASEBRK/ASEBRKAK NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/RXD0 VCL LQFP-48 (Top view) PA1/POE1/TXD0 PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA6/TCLKA PA7/TCLKB/SCK2/TCK VSS PA8/TCLKC/RXD2/TDI VCC PA9/TCLKD/TXD2/TDO/POE8 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 Figure 1.3 (1) Pin Assignments of SH7124 PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES VCC PE12/TIOC4A VSS PE11/TIOC3D VCL PE9/TIOC3B PE10/TIOC3C PE8/TIOC3A PE3/TIOC0D/SCK0 Pins for the system development tool. When these pins are used for an on-chip debugger, they are not available. Rev. 4.00 Jul. 25, 2008 Page 9 of 750 REJ09B0243-0400 Section 1 Overview 39 38 37 36 35 34 33 32 31 30 29 28 27 PB3/IRQ1/POE1/TIC5V 40 PB1/TIC5W 41 AVss 42 PF7/AN7 43 PF6/AN6 44 PF5/AN5 45 PF4/AN4 46 PF3/AN3 47 PF2/AN2 48 PF1/AN1 49 PF0/AN0 50 AVcc 51 NC 52 26 25 24 23 22 21 20 19 18 17 16 15 14 PA1/POE1/TXD0 PA3/IRQ1/RXD1/TRST PA4/IRQ2/TXD1/TMS PA6/TCLKA PA7/TCLKB/SCK2/TCK VSS VSS PA8/TCLKC/RXD2/TDI VCC PA9/TCLKD/TXD2/TDO/POE8 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 Figure 1.3 (2) Pin Assignments of SH7124 Rev. 4.00 Jul. 25, 2008 Page 10 of 750 REJ09B0243-0400 PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES VCC PE12/TIOC4A VSS PE11/TIOC3D VCL PE9/TIOC3B PE10/TIOC3C PE8/TIOC3A PE3/TIOC0D/SCK0 NC PB5/IRQ3/TIC5U VSS PLLVSS MD1 FWE/ASEBRK/ASEBRKAK NMI ASEMD0 EXTAL XTAL WDTOVF RES PA0/POE0/TXD0 VCL VQFN-52 (Top view) Section 1 Overview 1.4 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Symbol Vcc I/O I Name Power supply Function Power supply pin Connect all Vcc pins to the system. There will be no operation if any pins are open. Vss I Ground Ground pin Connect all Vss pins to the system power supply (0V). There will be no operation if any pins are open. VCL O Power supply for External capacitance pins for internal internal powerpower-down power supply down Connect these pins to Vss via a 0.1 to 0.47 µF capacitor (placed close to the pins). PLL ground External clock Ground pin for the on-chip PLL oscillator Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. Connected to a crystal resonator. Sets the operating mode. Do not change values on this pin during operation. Pin for flash memory Flash memory can be protected against programming or erasure through this pin. Classification Power supply Clock PLLVss EXTAL I I XTAL Operating mode control MD1 O I Crystal Mode set FWE I Flash memory write enable Rev. 4.00 Jul. 25, 2008 Page 11 of 750 REJ09B0243-0400 Section 1 Overview Classification System control Symbol RES MRES WDTOVF I/O I I O Name Power-on reset Manual reset Watchdog timer overflow Function When low, this LSI enters the poweron reset state. When low, this LSI enters the manual reset state. Output signal for the watchdog timer overflow If this pin needs to be pulled down, use the resistor larger than 1 MΩ to pull this pin down. Interrupts NMI I Non-maskable interrupt Non-maskable interrupt request pin Fix to high or low level when not in use. IRQ3 to IRQ0 I (SH7125) IRQ3 to IRQ1 (SH7124) IRQOUT O Interrupt requests Maskable interrupt request pins 3 to 0 Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. Interrupt request Shows that an interrupt cause has output occurred. The interrupt cause can be recognized even in the bus release state. MTU2 timer clock External clock input pins for the timer input Multi function timer- TCLKA, pulse unit 2 (MTU2) TCLKB, TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B (only in SH7125) TIOC2A, TIOC2B (only in SH7125) I I/O MTU2 input capture/output compare (channel 0) MTU2 input capture/output compare (channel 1) MTU2 input capture/output compare (channel 2) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins The TGRA_2 to TGRB_2 input capture input/output compare output/PWM output pins I/O I/O Rev. 4.00 Jul. 25, 2008 Page 12 of 750 REJ09B0243-0400 Section 1 Overview Classification Symbol I/O I/O Name MTU2 input capture/output compare (channel 3) MTU2 input capture/output compare (channel 4) MTU2 input capture (channel 5) Port output enable Function The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins The TGRA_4 to TGRD_4 input capture input/output compare output/PWM output pins The TGRU_5, TGRV_5, and TGRW_5 input capture input pins Request signal input to place the waveform output pins and channel 0 pins of MTU2 in high impedance state. In the SH7125, while POE3 function is selected in the PFC, the pin is pulled up inside this LSI if no signals are input to them. Multi function timer- TIOC3A, pulse unit 2 (MTU2) TIOC3B, TIOC3C, TIOC3D TIOC4A, TIOC4B, TIOC4C, TIOC4D TIC5U, TIC5V, TIC5W Port output enable (POE) I/O I POE8, POE3, I POE1, POE0 (SH7125) POE8, POE1, POE0 (SH7124) Serial communication interface (SCI) TXD2 to TXD0 RXD2 to RXD0 SCK2 to SCK0 (SH7125) SCK2, SCK0 (SH7124) O I I/O Transmit data Receive data Serial clock Transmit data output pins Receive data input pins Clock input/output pins A/D converter (ADC) AN7 to AN0 ADTRG (only in SH7125) AVcc I I Analog input pins Analog input pins A/D conversion trigger input Analog power supply External trigger input pin for starting A/D conversion Power supply pin for the A/D converter Connect all AVcc pins to the system power supply (Vcc) when the A/D converter is not used. The A/D converter does not work if any pin is open. I Rev. 4.00 Jul. 25, 2008 Page 13 of 750 REJ09B0243-0400 Section 1 Overview Classification A/D converter Symbol AVss I/O I Name Analog ground Function Ground pin for the A/D converter Connect it to the system ground (0 V). Connect all AVss pins to the system ground (0 V) correctly. The A/D converter does not work if any pin is open. I/O ports PA15 to PA0 I/O (SH7125) PA9 to PA6, PA4, PA3, PA1, PA0 (SH7124) PB16, PB5, PB3 to PB1 (SH7125) PB5, PB3, PB1 (SH7124) PE15 to PE0 I/O (SH7125) PE15 to PE8, PE3 to PE0 (SH7124) PF7 to PF0 I I I I O I I/O General port 16-bit input/output port pins 8-bit input/output port pins General port 5-bit input/output port pins 3-bit input/output port pins General port 16-bit input/output port pins 12-bit input/output port pins General port Test clock 8-bit input port pins Test-clock input pin User debugging interface (H-UDI) TCK TMS TDI TDO TRST Test mode select Inputs the test-mode select signal. Test data input Test data output Test reset Serial input pin for instructions and data Serial output pin for instructions and data Initialization-signal input pin Rev. 4.00 Jul. 25, 2008 Page 14 of 750 REJ09B0243-0400 Section 1 Overview Classification E10A interface Symbol ASEMD0 I/O I Name ASE mode Function Sets the ASE mode. When a low level is input, this LSI enters ASE mode. When a high level is input, this LSI enters the normal mode. The emulator functions are available in ASE mode. When no signal is input, this pin is pulled up inside this LSI. ASEBRK ASEBRKAK I O Break request Break mode acknowledge E10A emulator break input pin Indicates that the E10A emulator has entered its break mode. Note: The WDTOVF pin should not be pulled down. When absolutely necessary, pull it down through a resistor of 1 MΩ or larger. Rev. 4.00 Jul. 25, 2008 Page 15 of 750 REJ09B0243-0400 Section 1 Overview Rev. 4.00 Jul. 25, 2008 Page 16 of 750 REJ09B0243-0400 Section 2 CPU Section 2 CPU 2.1 Features • General registers: 32-bit register × 16 • Basic instructions: 62 • Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect (@R0, Rn) GBR indirect with displacement (@disp:8, GBR) Index GBR indirect (@R0, GBR) PC relative with displacement (@disp:8, PC) PC relative (disp:8/disp:12/Rn) Immediate (#imm:8) CPUS200C_000020020700 Rev. 4.00 Jul. 25, 2008 Page 17 of 750 REJ09B0243-0400 Section 2 CPU 2.2 Register Configuration There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and system registers (32-bit × 4). General register (Rn) 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0 Status register (SR) 31 9 8765 43 210 M Q I3 I2 I1 I0 ST Global base register (GBR) 31 GBR 0 Vector base register (VBR) 31 VBR 0 Multiply and accumulate register (MAC) 31 MACH MACL 0 Procedure register (PR) 31 PR 0 Program counter (PC) 31 PC 0 Notes: 1. R0 can be used as an index register in index register indirect or index GBR indirect addressing mode. For some instructions, only R0 is used as the source or destination register. 2. R15 is used as a hardware stack pointer during exception handling. Figure 2.1 CPU Internal Register Configuration Rev. 4.00 Jul. 25, 2008 Page 18 of 750 REJ09B0243-0400 Section 2 CPU 2.2.1 General Registers (Rn) There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. R0 is also used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the status register (SR) and program counter (PC) values. 2.2.2 Control Registers There are three 32-bit control registers, designated status register (SR), global base register (GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers. VBR is used as a base address of the exception handling (including interrupts) vector table. • Status register (SR) Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 14 - 0 R 13 - 0 R 12 - 0 R 11 - 0 R 10 - 0 R 9 M 0 R 8 Q 0 R 7 0 R 6 I[3:0] 0 R 5 0 R 4 0 R 3 - 0 R 2 - 0 R 1 S 0 R 0 T Bit: 15 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R R/W R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R 0 R R/W R/W Bit 31 to 10 Bit name  Default All 0 Read/ Write R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 to 4 3, 2 M Q I[3:0]  Undefined Undefined 1111 All 0 R/W R/W R/W R Used by the DIV0U, DIV0S, and DIV1 instructions. Used by the DIV0U, DIV0S, and DIV1 instructions. Interrupt Mask Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 19 of 750 REJ09B0243-0400 Section 2 CPU Bit 1 0 Bit name S T Default Undefined Undefined Read/ Write R/W R/W Description S Bit Used by the multiply and accumulate instruction. T Bit Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL • Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations. • Vector-base register (VBR) This register indicates the base address of the exception handling vector table. Rev. 4.00 Jul. 25, 2008 Page 20 of 750 REJ09B0243-0400 Section 2 CPU 2.2.3 System Registers There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC). • Multiply and accumulate registers (MACH and MACL) This register stores the results of multiplication and multiply-and-accumulate operation. • Procedure register (PR) This register stores the return-destination address from subroutine procedures. • Program counter (PC) The PC indicates the point which is four bytes (two instructions) after the current execution instruction. 2.2.4 Initial Values of Registers Table 2.1 lists the initial values of registers after a reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control register SR Default Undefined SP value set in the exception handling vector table I3 to I0: 1111 (H'F) Reserved bits: 0 Other bits: Undefined GBR VBR System register MACH, MACL, PR PC Undefined H'00000000 Undefined PC value set in the exception handling vector table Type of register General register Rev. 4.00 Jul. 25, 2008 Page 21 of 750 REJ09B0243-0400 Section 2 CPU 2.3 2.3.1 Data Formats Register Data Format The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register. 31 Longword 0 Figure 2.2 Register Data Format 2.3.2 Memory Data Formats Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword 23 Byte Address m + 3 Address m + 2 15 Byte Word 7 Byte 0 Figure 2.3 Memory Data Format Rev. 4.00 Jul. 25, 2008 Page 22 of 750 REJ09B0243-0400 Section 2 CPU 2.3.3 Immediate Data Formats Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zeroextended to longword and then calculated. Thus, if the immediate data is used for the AND instruction, the upper 24 bits in the destination register are always cleared. The immediate data of word or longword is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed by the MOV immediate data instruction in PC relative addressing mode with displacement. 2.4 2.4.1 Features of Instructions RISC Type The instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one cycle. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Byte or word data in memory is sign-extended to longword and then calculated. Immediate data is sign-extended to longword for arithmetic operations or zero-extended to longword size for logical operations. Table 2.2 Word Data Sign Extension Description Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. Example of Other CPUs ADD.W #H'1234,R0 CPU in this LSI MOV.W ADD @(disp,PC),R1 R1,R0 ........ .DATA.W H'1234 Note: * Immediate data is accessed by @(disp,PC). Rev. 4.00 Jul. 25, 2008 Page 23 of 750 REJ09B0243-0400 Section 2 CPU Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions means the delayed branch instructions. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. The conditional branch instructions have two types of instructions: conditional branch instructions and delayed branch instructions. Table 2.3 Delayed Branch Instructions Description ADD is executed before branch to TRGET. Example of Other CPUs ADD.W R1,R0 BRA TRGET CPU in this LSI BRA ADD TRGET R1,R0 Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-andaccumulate operation are each executed in two to four cycles. T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Table 2.4 T Bit Description When R0 ≥ R1, the T bit is set. Example of Other CPUs CMP.W R1,R0 TRGET0 TRGET1 TRGET CPU in this LSI CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #1,R0 #0,R0 TRGET When R0 ≥ R1, a branch is made to TRGET0. BGE When R0 < R1, a branch is made to TRGET1. BLT The T bit is not changed by ADD. When R0 = 0, the T bit is set. A branch is made when R0 = 0. BEQ SUB.W #1,R0 Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword immediate data is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed with the MOV immediate data instruction using PC relative addressing mode with displacement. Rev. 4.00 Jul. 25, 2008 Page 24 of 750 REJ09B0243-0400 Section 2 CPU Table 2.5 Type Access to Immediate Data This LSI's CPU MOV #H'12,R0 ........ .DATA.W H'1234 Example of Other CPU MOV.B #H'12,R0 8-bit immediate 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 32-bit immediate MOV.L @(disp,PC),R0 ........ MOV.L #H'12345678,R0 .DATA.L H'12345678 Note: * Immediate data is accessed by @(disp,PC). Absolute Addresses: When data is accessed by absolute address, place the absolute address value in a table in memory beforehand. The absolute address value is transferred to a register using the method whereby immediate data is loaded when an instruction is executed, and the data is accessed using the register indirect addressing mode. Table 2.6 Type Absolute address Access to Absolute Address CPU in this LSI MOV.L MOV.B @(disp,PC),R1 @R1,R0 ........ .DATA.L H'12345678 Example of Other CPUs MOV.B @H'12345678,R0 Note: * Immediate data is referenced by @(disp,PC). 16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement addressing mode, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is accessed using index register indirect addressing mode. Rev. 4.00 Jul. 25, 2008 Page 25 of 750 REJ09B0243-0400 Section 2 CPU Table 2.7 Type Access with Displacement CPU in this LSI MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 ........ .DATA.W H'1234 Example of Other CPUs MOV.W @(H'1234,R1),R2 16-bit displacement Note: * Immediate data is referenced by @(disp,PC). 2.4.2 Addressing Modes Table 2.8 lists addressing modes and effective address calculation methods. Table 2.8 Addressing Mode Register direct Register indirect Register indirect with post-increment Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Method Rn @Rn @Rn+ Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Calculation Formula  Rn Rn After instruction execution Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation) Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn + 1/2/4 + 1/2/4 Rn Register indirect with pre-decrement @–Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 1/2/4 Rn - 1/2/4 Rev. 4.00 Jul. 25, 2008 Page 26 of 750 REJ09B0243-0400 Section 2 CPU Addressing Mode Register indirect with displacement Instruction Format Effective Address Calculation Method @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) × 1/2/4 Calculation Formula Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 + Rn + disp × 1/2/4 Index @(R0, Rn) Effective address is sum of register Rn and R0 register indirect contents. Rn Rn + R0 + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) × 1/2/4 Byte: GBR + disp Word: GBR + disp × 2 Longword: GBR + disp × 4 + GBR + disp × 1/2/4 Index GBR indirect @(R0, GBR) Effective address is sum of register GBR and R0 contents. GBR GBR + R0 + R0 GBR + R0 Rev. 4.00 Jul. 25, 2008 Page 27 of 750 REJ09B0243-0400 Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Method Effective address is PC with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC & H'FFFFFFFC disp (zero-extended) * PC + disp × 2 or PC& H'FFFFFFFC + disp × 4 *With longword operand Calculation Formula Word: PC + disp ×2 Longword: PC&H'FFFFFFFC + disp × 4 PC relative with @(disp:8, displacement PC) + × 2/4 PC relative disp:8 Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) × 2 PC + disp × 2 + PC + disp × 2 disp:12 Effective address is PC with 12-bit displacement PC + disp × 2 disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) × 2 + PC + disp × 2 Rev. 4.00 Jul. 25, 2008 Page 28 of 750 REJ09B0243-0400 Section 2 CPU Addressing Mode PC relative Instruction Format Effective Address Calculation Method Rn Effective address is sum of PC and Rn. PC Calculation Formula PC + Rn + Rn PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.    2.4.3 Instruction Formats This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Rev. 4.00 Jul. 25, 2008 Page 29 of 750 REJ09B0243-0400 Section 2 CPU Table 2.9 Instruction Formats Source Operand  Destination Operand  Sample Instruction NOP Instruction Format 0 type 15 0 xxxx xxxx xxxx xxxx n type 15 0 xxxx nnnn xxxx xxxx  nnnn: register direct MOVT Rn STS MACH,Rn Control register or nnnn: register system register direct Control register or nnnn: preSTC.L SR,@-Rn system register decrement register indirect m type 15 0 xxxx mmmm xxxx xxxx mmmm: register direct Control register or LDC Rm,SR system register mmmm: postControl register or LDC.L @Rm+,SR increment register system register indirect mmmm: register indirect PC relative using Rm   JMP @Rm BRAF Rm Rev. 4.00 Jul. 25, 2008 Page 30 of 750 REJ09B0243-0400 Section 2 CPU Instruction Format nm type 15 0 xxxx nnnn mmmm xxxx Source Operand mmmm: register direct mmmm: register direct Destination Operand nnnn: register direct nnnn: register indirect Sample Instruction ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: postMACH, MACL increment register indirect (multiplyand-accumulate operation) nnnn: * postincrement register indirect (multiplyand-accumulate operation) mmmm: postnnnn: register increment register direct indirect mmmm: register direct mmmm: register direct md type 15 0 xxxx xxxx mmmm dddd MOV.L @Rm+,Rn nnnn: preMOV.L Rm,@-Rn decrement register indirect nnnn: index register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: register indirect with displacement R0 (register direct) MOV.B @(disp,Rm),R0 nd4 type 15 0 xxxx xxxx nnnn dddd R0 (register direct) nnnndddd: register indirect with displacement mmmm: register direct mmmmdddd: register indirect with displacement nnnndddd: register indirect with displacement nnnn: register direct MOV.B R0,@(disp,Rn) nmd type 15 0 xxxx nnnn mmmm dddd MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Rev. 4.00 Jul. 25, 2008 Page 31 of 750 REJ09B0243-0400 Section 2 CPU Instruction Format d type 15 0 xxxx xxxx dddd dddd Source Operand dddddddd: GBR indirect with displacement Destination Operand Sample Instruction R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement dddddddd: PC relative with displacement  d12 type 15 0 xxxx dddd dddd dddd MOV.L R0,@(disp,GBR) R0 (register direct) MOVA @(disp,PC),R0 dddddddd: PC relative dddddddddddd: PC relative nnnn: register direct BF label BRA label (label=disp+PC) MOV.L @(disp,PC),Rn  nd8 type 15 0 xxxx nnnn dddd dddd dddddddd: PC relative with displacement iiiiiiii: immediate iiiiiiii: immediate iiiiiiii: immediate i type 15 0 xxxx xxxx iiii iiii Index GBR indirect AND.B #imm,@(R0,GBR) R0 (register direct) AND #imm,R0  nnnn: register direct TRAPA #imm ADD #imm,Rn ni type 15 0 xxxx nnnn iiii iiii iiiiiiii: immediate Note: * In multiply and accumulate instructions, nnnn is the source register. Rev. 4.00 Jul. 25, 2008 Page 32 of 750 REJ09B0243-0400 Section 2 CPU 2.5 2.5.1 Instruction Set Instruction Set by Type Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Type Data transfer instructions Kinds of Instruction 5 Op Code MOV Function Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA MOVT SWAP XTRCT Arithmetic operation instructions 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL Effective address transfer T bit transfer Upper/lower swap Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow Comparison Division Signed division initialization Unsigned division initialization Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, doubleprecision multiply-and-accumulate Double-precision multiplication 33 Number of Instructions 39 Rev. 4.00 Jul. 25, 2008 Page 33 of 750 REJ09B0243-0400 Section 2 CPU Type Arithmetic operation instructions Kinds of Instruction 21 Op Code MULS MULU NEG NEGC SUB SUBC SUBV Function Signed multiplication Unsigned multiplication Sign inversion Sign inversion with borrow Binary subtraction Binary subtraction with carry Binary subtraction with underflow Logical AND Bit inversion Logical OR Memory test and bit setting T bit setting for logical AND Exclusive logical OR 1-bit left shift 1-bit right shift 1-bit left shift with T bit 1-bit right shift with T bit Arithmetic 1-bit left shift Arithmetic 1-bit right shift Logical 1-bit left shift Logical n-bit left shift Logical 1-bit right shift Logical n-bit right shift Number of Instructions 33 Logic operation instructions 6 AND NOT OR TAS TST XOR 14 Shift instructions 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn 14 Rev. 4.00 Jul. 25, 2008 Page 34 of 750 REJ09B0243-0400 Section 2 CPU Type Branch instructions Kinds of Instruction 9 Op Code BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Number of Instructions Conditional branch, delayed conditional 11 branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure T bit clear MAC register clear Load into control register Load into system register No operation Return from exception handling T bit setting Transition to power-down mode Store from control register Store from system register Trap exception handling 142 31 System control instructions 11 CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 Rev. 4.00 Jul. 25, 2008 Page 35 of 750 REJ09B0243-0400 Section 2 CPU The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Instruction Instruction Code Summary of Operation Indicates summary of operation. Execution Cycles T Bit Value when no Value of T bit after wait cycles are instruction is executed 1 inserted* Explanation of Symbols : No change Indicated by mnemonic. Indicated in MSB ↔ LSB order. Explanation of Symbols Explanation of Symbols Explanation of Symbols mmmm: Source register OP.Sz SRC, DEST OP: Operation code nnnn: Destination Sz: Size register SRC: Source 0000: R0 DEST: Destination 0001: R1 ......... Rm: Source register 1111: R15 Rn: Destination register iiii: Immediate data imm: Immediate data disp: Displacement* 2 →, ←: (xx): Transfer direction Memory operand M/Q/T: Flag bits in SR &: |: ^: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit –: Logical NOT of each bit dddd: Displacement n: n-bit right shift Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following: • When there is contention between an instruction fetch and a data access • When the destination register of a load instruction (memory → register) is also used by the following instruction 2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc. For details, see SH-1/SH-2/SH-DSP Software Manual. Rev. 4.00 Jul. 25, 2008 Page 36 of 750 REJ09B0243-0400 Section 2 CPU 2.5.2 Data Transfer Instructions Table 2.11 Data Transfer Instructions Instruction MOV #imm,Rn Operation imm → Sign extension → Rn extension → Rn Code 1110nnnniiiiiiii Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit                       MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn MOV Rm,Rn R m → Rn Rm → (Rn) Rm → (Rn) Rm → (Rn) (Rm) → Sign extension → Rn (Rm) → Sign extension → Rn (Rm) → Rn Rn–1 → Rn, Rm → (Rn) Rn–2 → Rn, Rm → (Rn) Rn–4 → Rn, Rm → (Rn) (Rm) → Sign extension → Rn, Rm + 1 → Rm (Rm) → Sign extension → Rn, Rm + 2 → Rm 1001nnnndddddddd 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd MOV.B R0,@(disp,Rn) R0 → (disp + Rn) MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) MOV.B @(disp,Rm),R0 (disp + Rm) → Sign extension → R0 MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign extension → R0 10000101mmmmdddd MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd Rev. 4.00 Jul. 25, 2008 Page 37 of 750 REJ09B0243-0400 Section 2 CPU Instruction MOV.B Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B MOV.W MOV.L MOV.B Operation Rm → (R0 + Rn) Rm → (R0 + Rn) Rm → (R0 + Rn) (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Sign extension → Rn (R0 + Rm) → Rn Code 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit                  0000nnnnmmmm1101 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd R0,@(disp,GBR) R0 → (disp + GBR) R0,@(disp,GBR) R0 → (disp × 2 + GBR) R0,@(disp,GBR) R0 → (disp × 4 + GBR) @(disp,GBR),R0 (disp + GBR) → Sign extension → R0 @(disp,GBR),R0 (disp × 2 + GBR) → Sign extension → R0 @(disp,GBR),R0 (disp × 4 + GBR) → R0 MOV.W 11000101dddddddd MOV.L 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 MOVA MOVT @(disp,PC),R0 disp × 4 + PC → R0 Rn T → Rn Rm → Swap lowest two bytes → Rn Rm → Swap two consecutive words → Rn Rm: Middle 32 bits of Rn → Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn 0110nnnnmmmm1001 0010nnnnmmmm1101 Rev. 4.00 Jul. 25, 2008 Page 38 of 750 REJ09B0243-0400 Section 2 CPU 2.5.3 Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PZ CMP/PL Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Operation Rn + Rm → Rn Rn + imm → Rn Rn + Rm + T → Rn, Carry → T Rn + Rm → Rn, Overflow → T If R0 = imm, 1 → T If Rn = Rm, 1 → T If Rn ≥ Rm with unsigned data, 1 → T If Rn ≥ Rm with signed data, 1 → T If Rn > Rm with unsigned data, 1 → T If Rn > Rm with signed data, 1 → T If Rn ≥ 0, 1 → T If Rn > 0, 1 → T If Rn and Rm have an equivalent byte, 1 → T Single-step division (Rn/Rm) MSB of Rn → Q, MSB of Rm → M, M^ Q → T 0 → M/Q/T Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 to 5* T Bit   Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 0011nnnnmmmm0011 0011nnnnmmmm0110 0011nnnnmmmm0111 0100nnnn00010001 0100nnnn00010101 CMP/STR Rm,Rn DIV1 DIV0S DIV0U DMULS.L Rm,Rn Rm,Rn Rm,Rn 0010nnnnmmmm1100 0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 0  Rev. 4.00 Jul. 25, 2008 Page 39 of 750 REJ09B0243-0400 Section 2 CPU Instruction DMULU.L Rm,Rn Operation Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rn - 1 → Rn, if Rn = 0, 1 → T, else 0 → T A byte in Rm is signextended → Rn A word in Rm is signextended → Rn A byte in Rm is zeroextended → Rn A word in Rm is zeroextended → Rn Signed operation of (Rn) × (Rm) + MAC → MAC, 32 × 32 + 64 → 64 bits Signed operation of (Rn) × (Rm) + MAC → MAC, 16 × 16 + 64 → 64 bits Rn × Rm → MACL 32 × 32 → 32 bits Signed operation of Rn × Rm → MAC 16 × 16 → 32 bits Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bits 0-Rm → Rn 0-Rm-T → Rn, Borrow → T Rn-Rm → Rn Rn-Rm–T → Rn, Borrow → T Rn-Rm → Rn, Underflow → T Code 0011nnnnmmmm0101 Execution Cycles 2 to 5* T Bit  DT EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn @Rm+,@Rn+ 0100nnnn00010000 1 1 1 1 1 2 to 5* Comparison result 0110nnnnmmmm1110      0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 2 to 4*  MUL.L MULS.W Rm,Rn Rm,Rn 0000nnnnmmmm0111 2 to 5* 1 to 3*   0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 1 to 3*  NEG NEGC Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 1 1 1 1 1  Borrow  Borrow Underflow SUB SUBC SUBV Note: * Rm,Rn Rm,Rn Rm,Rn 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 Indicates the number of execution cycles for normal operation. Rev. 4.00 Jul. 25, 2008 Page 40 of 750 REJ09B0243-0400 Section 2 CPU 2.5.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Instruction AND AND Rm,Rn #imm,R0 Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) Code Execution Cycles T Bit        Test result Test result Test result Test result 0010nnnnmmmm1001 1 11001001iiiiiiii 1 11001101iiiiiiii 3 0110nnnnmmmm0111 1 0010nnnnmmmm1011 1 11001011iiiiiiii 1 11001111iiiiiiii 3 0100nnnn00011011 4 0010nnnnmmmm1000 1 11001000iiiiiiii 1 11001100iiiiiiii 3 0010nnnnmmmm1010 1 11001010iiiiiiii 1 11001110iiiiiiii 3 AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → NOT OR OR Rm,Rn Rm,Rn #imm,R0 ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → TAS.B @Rn TST TST Rm,Rn #imm,R0 If (Rn) is 0, 1 → T; 1 → MSB of (Rn) Rn & Rm; if the result is 0, 1 → T R0 & imm; if the result is 0, 1 → T if the result is 0, 1 → T TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; XOR XOR Rm,Rn #imm,R0 Rn ^ Rm → Rn R0 ^ imm → R0 (R0 + GBR)    XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm → Rev. 4.00 Jul. 25, 2008 Page 41 of 750 REJ09B0243-0400 Section 2 CPU 2.5.5 Shift Instructions Table 2.14 Shift Instructions Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T T ← Rn ← 0 MSB → Rn → T T ← Rn ← 0 0 → Rn → T Rn > 2 → Rn Rn > 8 → Rn Rn > 16 → Rn Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Execution Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit MSB LSB MSB LSB MSB LSB MSB LSB       SHLL16 Rn SHLR16 Rn Rev. 4.00 Jul. 25, 2008 Page 42 of 750 REJ09B0243-0400 Section 2 CPU 2.5.6 Branch Instructions Table 2.15 Branch Instructions Instruction BF label Operation If T = 0, disp × 2 + PC → PC; if T = 1, nop Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop If T = 1, disp × 2 + PC → PC; if T = 0, nop Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop Delayed branch, disp × 2 + PC → PC Delayed branch, Rm + PC → PC Delayed branch, PC → PR, disp × 2 + PC → PC Delayed branch, PC → PR, Rm + PC → PC Delayed branch, Rm → PC Delayed branch, PC → PR, Rm → PC Delayed branch, PR → PC Code 10001011dddddddd Execution Cycles 3/1* T Bit  BF/S label 10001111dddddddd 2/1*  BT label 10001001dddddddd 3/1*  BT/S label 10001101dddddddd 2/1*  BRA label 1010dddddddddddd 2 2 2 2 2 2 2        BRAF Rm BSR label 0000mmmm00100011 1011dddddddddddd BSRF Rm JMP JSR RTS Note: * @Rm @Rm 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 One cycle when the branch is not executed. Rev. 4.00 Jul. 25, 2008 Page 43 of 750 REJ09B0243-0400 Section 2 CPU 2.5.7 System Control Instructions Table 2.16 System Control Instructions Instruction CLRT CLRMAC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Operation 0→T 0 → MACH, MACL Rm → SR Rm → GBR Rm → VBR (Rm) → GBR, Rm + 4 → Rm (Rm) → VBR, Rm + 4 → Rm Rm → MACH Rm → MACL Rm → PR (Rm) → MACH, Rm + 4 → Rm (Rm) → MACL, Rm + 4 → Rm Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 Execution Cycles 1 1 1 1 1 3 3 3 1 1 1 1 1 1 1 5 1 4* 1 1 1 1 1 1 T Bit 0  LSB   LSB           1        LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDS LDS LDS Rm,MACH Rm,MACL Rm,PR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR NOP RTE SETT SLEEP STC STC STC SR,Rn GBR,Rn VBR,Rn 0100mmmm00010110 (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 No operation Delayed branch, Stack area → PC/SR 1→T Sleep S R → Rn GBR → Rn VBR → Rn Rn–4 → Rn, SR → (Rn) Rn–4 → Rn, GBR → (Rn) Rn–4 → Rn, VBR → (Rn) 0000000000001001 0000000000101011 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 STC.L SR,@–Rn STC.L GBR,@–Rn STC.L VBR,@–Rn Rev. 4.00 Jul. 25, 2008 Page 44 of 750 REJ09B0243-0400 Section 2 CPU Instruction STS STS STS MACH,Rn MACL,Rn PR,Rn Operation MACH → Rn MACL → Rn P R → Rn Code 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 Execution Cycles 1 1 1 1 1 1 8 T Bit        STS.L MACH,@–Rn STS.L MACL,@–Rn STS.L PR,@–Rn TRAPA #imm Note: * Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 Rn–4 → Rn, PR → (Rn) PC/SR → Stack area, (imm × 4 + VBR) → PC 0100nnnn00100010 11000011iiiiiiii Number of execution cycles until this LSI enters sleep mode. About the number of execution cycles: The table lists the minimum number of execution cycles. In practice, the number of execution cycles will be increased depending on the conditions such as: • When there is a conflict between instruction fetch and data access • When the destination register of a load instruction (memory → register) is also used by the instruction immediately after the load instruction. Rev. 4.00 Jul. 25, 2008 Page 45 of 750 REJ09B0243-0400 Section 2 CPU 2.6 Processing States The CPU has the five processing states: reset, exception handling, program execution, and powerdown. Figure 2.4 shows the CPU state transition. From any state when RES = 0 From any state when RES = 1 and MRES = 0 Power-on reset state RES = 0 Manual reset state RES = 1 When internal power-on reset by WDT or internal manual reset by WDT occurs. RES = 1, MRES = 1 Reset state Exception handling state NMI interrupt or IRQ interrupt occurs Exception processing source occurs Exception processing ends Program execution state SSBY bit = 0 for SLEEP instruction SSBY bit = 1 and STBYMD bit = 1 for SLEEP instruction Sleep mode Software standby mode Power-down mode Figure 2.4 Transitions between Processing States Rev. 4.00 Jul. 25, 2008 Page 46 of 750 REJ09B0243-0400 Section 2 CPU • Reset state The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state. • Exception handling state This state is a transitional state in which the CPU processing state changes due to a request for exception handling such as a reset or an interrupt. When a reset occurs, the execution start address as the initial value of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table. Then, a branch is made for the start address to execute a program. When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to by SP. The start address of an exception handling routine is fetched from the exception handling vector table and a branch to the address is made to execute a program. Then the processing state enters the program execution state. • Program execution state The CPU executes programs sequentially. • Power-down state The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter sleep mode or software standby mode. Rev. 4.00 Jul. 25, 2008 Page 47 of 750 REJ09B0243-0400 Section 2 CPU Rev. 4.00 Jul. 25, 2008 Page 48 of 750 REJ09B0243-0400 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows the allowable combinations of these pin settings; do not set these pins in the other way than the shown combinations. When power is applied to the system, be sure to conduct power-on reset. The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip mode. For the on-chip flash memory programming mode, boot mode, user boot mode, and user program mode, which are on-chip programming modes are available. Table 3.1 Selection of Operating Modes Pin Setting Mode No. Mode 3 Mode 4* Mode 6* 1 2 FWE 0 1 1 MD1 1 0 1 Mode Name Single chip mode Boot mode User program mode On-Chip ROM Active Active Active Notes: 1. Flash memory programming mode. 2. Prohibited in SH71241. Rev. 4.00 Jul. 25, 2008 Page 49 of 750 REJ09B0243-0400 Section 3 MCU Operating Modes 3.2 Input/Output Pins Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Name MD1 FWE Pin Configuration Input/Output Input Input Function Designates operating mode through the level applied to this pin Enables, by hardware, programming/erasing of the on-chip flash memory 3.3 3.3.1 Operating Modes Mode 3 (Single Chip Mode) All ports can be used in this mode, however the external address cannot be used. Rev. 4.00 Jul. 25, 2008 Page 50 of 750 REJ09B0243-0400 Section 3 MCU Operating Modes 3.4 Address Map The address map for the operating modes are shown in figures 3.1 to 3.3. Mode 3 Single chip mode H'00000000 On-chip ROM (128 kbytes) H'0001FFFF H'00020000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF Figure 3.1 Address Map in SH7125, SH7124 (128 Kbytes Flash Memory Version) Rev. 4.00 Jul. 25, 2008 Page 51 of 750 REJ09B0243-0400 Section 3 MCU Operating Modes Mode 3 Single chip mode H'00000000 On-chip ROM (64 kbytes) H'0000FFFF H'00010000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF Figure 3.2 Address Map in SH7125, SH7124 (64 Kbytes Flash Memory Version) Rev. 4.00 Jul. 25, 2008 Page 52 of 750 REJ09B0243-0400 Section 3 MCU Operating Modes Mode 3 Single chip mode H'00000000 On-chip ROM (32 kbytes) H'00007FFF H'00008000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF Figure 3.3 Address Map in SH7124 (32 Kbytes Flash Memory Version) Rev. 4.00 Jul. 25, 2008 Page 53 of 750 REJ09B0243-0400 Section 3 MCU Operating Modes 3.5 Initial State in This LSI In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section 19, Power-Down Modes. 3.6 Note on Changing Operating Mode When changing operating mode while power is applied to this LSI, make sure to do it in the power-on reset state (that is, the low level is applied to the RES pin). MD1 tMDS* RES Note: * See section 21.3.2, Control Signal Timing. Figure 3.4 Reset Input Timing when Changing Operating Mode Rev. 4.00 Jul. 25, 2008 Page 54 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a bus clock (Bφ), a peripheral clock (Pφ), and a clock (MPφ) for the MTU2 module. The CPG also controls powerdown modes. 4.1 Features • Five clocks generated independently An internal clock (Iφ) for the CPU; a peripheral clock (Pφ) for the on-chip peripheral modules; a bus clock (Bφ = CK) for the external bus interface; and a MTU2 clock (MPφ) for the on-chip MTU2 module. • Frequency change function Frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ) can be changed independently using the divider circuit within the CPG. Frequencies are changed by software using the frequency control register (FRQCR) setting. • Power-down mode control The clock can be stopped in sleep mode and standby mode and specific modules can be stopped using the module standby function. • Oscillation stop detection If the clock supplied through the clock input pin stops for any reason, the timer pins can be automatically placed in the high-impedance state. CPGS301C_000020030900 Rev. 4.00 Jul. 25, 2008 Page 55 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Figure 4.1 shows a block diagram of the CPG. Oscillator unit Divider XTAL EXTAL Crystal oscillator ×1/2 ×1/4 ×1/8 MTU2 clock (MPφ) PLL circuit (×8) Internal clock (Iφ) Oscillation stop detection Oscillation stop detection circuit Peripheral clock (Pφ) Bus clock (Bφ = CK) CPG control unit Clock frequency control circuit Standby control circuit OSCCR FRQCR STBCR1 STBCR2 STBCR3 STBCR4 STBCR5 STBCR6 Bus interface [Legend] FRQCR: OSCCR: STBCR1: STBCR2: STBCR3: STBCR4: STBCR5: STBCR6: Internal bus Frequency control register Oscillation stop detection control register Standby control register 1 Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 Figure 4.1 Block Diagram of CPG Rev. 4.00 Jul. 25, 2008 Page 56 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or the EXTAL pin by 8. The multiplication ratio is fixed at ×8. Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is connected to the XTAL and EXTAL pins. Divider: The divider generates clocks with the frequencies to be used by the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). The frequencies can be selected from 1/2, 1/4 (initial value), and 1/8 times the frequency output from the PLL circuit. The division ratio should be specified in the frequency control register (FRQCR). Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal oscillator. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency according to the setting in the frequency control register (FRQCR). Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator circuit and other modules in sleep or standby mode. Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control bits for the frequency division ratios of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output through an external pin. Standby Control Registers 1 to 6 (STBCR1 to STBCR6): The standby control register (STBCR) has bits for controlling the power-down modes. For details, see section 19, Power-Down Modes. Rev. 4.00 Jul. 25, 2008 Page 57 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating Module CPU UBC ROM RAM Bus clock (Bφ)  MTU2 clock (MPφ) Operating Clock Peripheral clock (Pφ) Operating Module POE SCI A/D CMT WDT MTU2 Operating Clock Internal clock (Iφ) 4.2 Input/Output Pins Table 4.2 shows the CPG pin configuration. Table 4.2 Pin Name Pin Configuration Abbr. I/O Output Input Description Connects a crystal resonator. Connects a crystal resonator or an external clock. Crystal input/output XTAL pins EXTAL (clock input pins) Rev. 4.00 Jul. 25, 2008 Page 58 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.3 Clock Operating Mode Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Source EXTAL input or crystal resonator Clock Operating Mode PLL Circuit ON (×8) Input to Divider ×8 The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10 MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 50 MHz. Maximum operating frequencies: Iφ = 50 MHz, Bφ = 40 MHz, Pφ = 40 MHz, and MPφ = 40 MHz Table 4.4 shows the frequency division ratios that can be specified with FRQCR. Rev. 4.00 Jul. 25, 2008 Page 59 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Table 4.4 PLL Multiplication Ratio ×8 Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio Setting Iφ 1/8 1/4 1/4 1/2 1/2 1/8 1/4 1/4 1/2 Bφ 1/8 1/8 1/4 1/4 1/2 1/8 1/8 1/4 1/4 Pφ 1/8 1/8 1/4 1/4 1/2 1/8 1/8 1/4 1/4 MP φ 1/8 1/8 1/4 1/4 1/2 1/8 1/8 1/4 1/4 Iφ 1 2 2 4 4 1 2 2 4 Clock Ratio Bφ 1 1 2 2 4 1 1 2 2 Pφ 1 1 2 2 4 1 1 2 2 MP φ 1 1 2 2 4 1 1 2 2 Input Clock 10 10 10 10 10 12.5 12.5 12.5 12.5 Clock Frequency (MHz)* Iφ 10 20 20 40 40 12.5 25 25 50 Bφ 10 10 20 20 40 12.5 12.5 25 25 Pφ 10 10 20 20 40 12.5 12.5 25 25 MP φ 10 10 20 20 40 12.5 12.5 25 25 Notes: * 1. 2. 3. 4. 5. 6. 7. 8. Clock frequencies when the input clock frequency is assumed to be the shown value. The internal clock (Iφ) frequency must be 10 to 50 MHz and the peripheral clock (Pφ) frequency must be 10 to 40 MHz. The bus clock (Bφ) frequency must be equal to the peripheral clock (Pφ) frequency. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1/2, ×1/4, and ×1/8 for each clock by the setting in the frequency control register. The output frequency of the PLL circuit is the product of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. The input to the divider is always the output from the PLL circuit. The internal clock (Iφ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 50 MHz (maximum operating frequency). The peripheral clock (Pφ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 40 MHz. When using the MTU2, the MTU2 clock (MPφ) frequency must be equal to or higher than the peripheral clock frequency (Pφ). The MTU2 clock (MPφ) frequency are the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The frequency of the CK pin is always be equal to the bus clock (Bφ) frequency. The bus clock (Bφ) frequency must be equal to the peripheral clock (Pφ) frequency. Rev. 4.00 Jul. 25, 2008 Page 60 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.4 Register Descriptions The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers Table 4.5 Register Configuration Abbreviation FRQCR OSCCR R/W R/W R/W Initial Value H'36DB H'00 Address H'FFFFE800 H'FFFFE814 Access Size 16 8 Register Name Frequency control register Oscillation stop detection control register 4.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). FRQCR can be accessed only in words. FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT overflow). Before making changes to FRQCR, stop clock supply to each module except the CPU, on-chip ROM, and on-chip-RAM. Bit: 15 - 14 13 IFC[2:0] 12 11 10 BFC[2:0] 9 8 7 PFC[2:0] 6 5 - 4 - 3 - 2 1 MPFC[2:0] 0 Initial value: 0 R/W: R 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W Rev. 4.00 Jul. 25, 2008 Page 61 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IFC[2:0] 011 R/W Internal Clock (Iφ) Frequency Division Ratio Specify the division ratio of the internal clock (Iφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited 11 to 9 BFC[2:0] 011 R/W Bus Clock (Bφ) Frequency Division Ratio Specify the division ratio of the bus clock (Bφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 62 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Bit 8 to 6 Bit Name PFC[2:0] Initial Value 011 R/W R/W Description Peripheral Clock (Pφ) Frequency Division Ratio Specify the division ratio of the peripheral clock (Pφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited 5 to 3  011 R/W Reserved These bits are always read as B'011. The write value should always be B'011. 2 to 0 MPFC[2:0] 011 R/W MTU2 Clock (MPφ) Frequency Division Ratio Specify the division ratio of the MTU2 clock (MPφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: Setting prohibited 001: ×1/2 010: Setting prohibited 011: ×1/4 (initial value) 100: ×1/8 Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 63 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.4.2 Oscillation Stop Detection Control Register (OSCCR) OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in bytes. Bit: 7 - 6 - 5 - 4 - 3 - 2 OSC STOP 1 - 0 OSC ERS Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 7 to 3 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 OSCSTOP 0 R Oscillation Stop Detection Flag [Setting condition] • When a stop in the clock input is detected during normal operation By a power-on reset input through the RES pin [Clearing condition] • 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 OSCERS 0 R/W Oscillation Stop Detection Flag Output Select Selects whether to output the oscillation stop detection flag signal through the WDTOVF pin. 0: Outputs only the WDT overflow signal through the WDTOVF pin 1: Outputs the WDT overflow signal and the oscillation stop detection flag signal through the WDTOVF pin Rev. 4.00 Jul. 25, 2008 Page 64 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.5 Changing Frequency Selecting division ratios for the frequency divider can change the frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software through the frequency control register (FRQCR). The following describes how to specify the frequencies. 1. In the initial state, IFC2 to IFC0 = H'011 (×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to PFC0 = H'011 (×1/4), and MPFC2 to MPFC0 = H'011 (×1/4). 2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM. 3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, and MPFC2 to MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at ×8, the frequencies are determined only be selecting division ratios. When specifying the frequencies, satisfy the following condition: internal clock (Iφ) ≥ bus clock (Bφ) = peripheral clock (Pφ). When using the MTU2 clock, specify the frequencies to satisfy the following condition: internal clock (Iφ) ≥ MTU2 clock (MPφ) ≥ peripheral clock (Pφ). 4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will change after (1 to 24n) cyc + 11Bφ + 7Pφ. n: Division ratio specified by the BFC bit in FRQCR (1/2, 1/4, or 1/8) cyc: Clock obtained by dividing EXTAL by 8 with the PLL. Note: (1 to 24n) depends on the internal state. Rev. 4.00 Jul. 25, 2008 Page 65 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.6 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.6.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.6. Use a crystal resonator that has a resonance frequency of 10 to 12.5 MHz. It is recommended to consult the crystal resonator manufacturer concerning the compatibility of the crystal resonator and the LSI. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 18 to 22 pF (Reference values) Figure 4.2 Connection of Crystal Resonator (Example) Table 4.6 Damping Resistance Values (Reference Values) 10 0 12.5 0 Frequency (MHz) Rd (Ω) (Reference Values) Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.7. CL L XTAL C0 Rs EXTAL Figure 4.3 Crystal Resonator Equivalent Circuit Rev. 4.00 Jul. 25, 2008 Page 66 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) Table 4.7 Crystal Resonator Characteristics 10 60 12.5 50 7 Frequency (MHz) Rs Max. (Ω) (Reference Values) C0 Max. (pF) (Reference Values) 7 4.6.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it when in software standby mode. During operation, make the external input clock frequency 10 to 12.5 MHz. When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing software standby mode, in order to ensure the PLL stabilization time. EXTAL XTAL Open state External clock input Figure 4.4 Example of External Clock Connection Rev. 4.00 Jul. 25, 2008 Page 67 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.7 Function for Detecting Oscillator Stop This CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or software standby mode is canceled. If the OSCERS bit is set to 1 at this time, an oscillation stop detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (pins to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2 are assigned) are always placed in high-impedance state regardless of the PFC setting. For details, refer to appendix A, Pin States. Even in software standby mode, these pins are always placed in high-impedance state. For details, refer to appendix A, Pin States. These pins enter the normal state after software standby mode is canceled. Under an abnormal condition where oscillation stops while the LSI is not in software standby mode, LSI operations other than the oscillation stop detection function become unpredictable. In this case, even after oscillation is restarted, LSI operations including the above high-current pins become unpredictable. Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and operating voltage). Rev. 4.00 Jul. 25, 2008 Page 68 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) 4.8 4.8.1 Usage Notes Note on Crystal Resonator A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user’s board design. As the oscillator circuit's circuit constant will depend on the resonator and the floating capacitance of the mounting circuit, the value of each external circuit’s component should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 4.8.2 Notes on Board Design Measures against radiation noise are taken in this LSI. If further reduction in radiation noise is needed, it is recommended to use a multiple layer board and provide a layer exclusive to the system ground. When using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 4.5 Cautions for Oscillator Circuit Board Design Rev. 4.00 Jul. 25, 2008 Page 69 of 750 REJ09B0243-0400 Section 4 Clock Pulse Generator (CPG) A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. PLLVSS VCL CPB = 0.1 µF* VCC CB = 0.1 µF* VSS (Recommended values are shown.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry around PLL Rev. 4.00 Jul. 25, 2008 Page 70 of 750 REJ09B0243-0400 Section 5 Exception Handling Section 5 Exception Handling 5.1 5.1.1 Overview Types of Exception Handling and Priority Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected at once, they are processed according to the priority. Table 5.1 Exception Reset Types of Exceptions and Priority Exception Source Power-on reset Manual reset Priority High Interrupt Address error Instruction User break (break before instruction execution) CPU address error (instruction fetch) General illegal instructions (undefined code) Illegal slot instruction (undefined code placed immediately after a delayed branch instruction*1 or instruction that changes the PC value*2) Trap instruction (TRAPA instruction) Address error Interrupt CPU address error (data access) User break (break after instruction execution or operand break) NMI IRQ On-chip peripheral modules Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR. Rev. 4.00 Jul. 25, 2008 Page 71 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.1.2 Exception Handling Operations The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Exception Reset Power-on reset Manual reset Address error Interrupt Instruction Trap instruction General illegal instructions Illegal slot instructions Timing for Exception Detection and Start of Exception Handling Timing of Source Detection and Start of Exception Handling Started when the RES pin changes from low to high or when the WDT overflows. Started when the MRES pin changes from low to high or when the WDT overflows. Detected during the instruction decode stage and started after the execution of the current instruction is completed. Started by the execution of the TRAPA instruction. Started when an undefined code placed at other than a delay slot (immediately after a delayed branch instruction) is decoded. Started when an undefined code placed at a delay slot (immediately after a delayed branch instruction) or an instruction that changes the PC value is detected. When exception handling starts, the CPU operates Exception Handling Triggered by Reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC from the address H'00000000 and SP from the address H'00000004 when a power-on reset. PC from the address H'00000008 and SP from the address H'0000000C when a manual reset.). For details, see section 5.1.3, Exception Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program starts from the PC address fetched from the exception handling vector table. Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception handling, bits I3 to I0 are not affected. The start address is then fetched from the exception handling vector table and the program starts from that address. Rev. 4.00 Jul. 25, 2008 Page 72 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.1.3 Exception Handling Vector Table Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception handling, the start addresses of the exception handling routines are fetched from the exception handling vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Vector Numbers and Vector Table Address Offsets Vector Number 0 1 2 3 4 5 6 7 8 CPU address error (Reserved for system use) Interrupt NMI User break (Reserved for system use) 9 10 11 12 13 : 31 Trap instruction (user vector) 32 : 63 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF Exception Handling Source Power-on reset PC SP Manual reset PC SP General illegal instruction (Reserved for system use) Illegal slot instruction (Reserved for system use) Rev. 4.00 Jul. 25, 2008 Page 73 of 750 REJ09B0243-0400 Section 5 Exception Handling Exception Handling Source Interrupt IRQ0 (SH7125) IRQ1 IRQ2 IRQ3 (Reserved for system use) Vector Number 64 65 66 67 68 : 71 Vector Table Address Offset H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 : H'0000011C to H'0000011F H'00000120 to H'00000123 : H'000003FC to H'000003FF On-chip peripheral module* 72 : 255 Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral module interrupts, see table 6.3 in section 6, Interrupt Controller (INTC). Table 5.4 Calculating Exception Handling Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) × 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Rev. 4.00 Jul. 25, 2008 Page 74 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.2 5.2.1 Resets Types of Resets Resets have priority over any exception source. There are two types of resets: power-on resets and manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset State WDT Overflow  Overflow Internal State On-Chip Peripheral Module Initialized Initialized POE, PFC, I/O Port Initialized Initialized Type Power-on reset RES Low High MRES  High CPU, INTC Initialized Initialized Initialized Initialized Manual reset High High Not overflowed Low Overflow High Not initialized Not initialized Not initialized Not initialized 5.2.2 Power-On Reset Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during power-on reset mode. In the power-on reset state, power-on reset exception handling starts when driving the RES pin high after driving the pin low for the given time. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). Rev. 4.00 Jul. 25, 2008 Page 75 of 750 REJ09B0243-0400 Section 5 Exception Handling 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts. Be certain to always perform power-on reset exception handling when turning the system power on. Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-on reset state. The frequency control register (FRQCR) in the clock pulse generator (CPG) and the watchdog timer (WDT) registers are not initialized by a reset generated by the WDT (these registers are only initialized by a power-on reset from the RES pin). If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When the power-on reset exception handling caused by the WDT is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in the PC and SP, then the program starts. 5.2.3 Manual Reset When the RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the oscillation settling time that is set in WDT when in software standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. See appendix A, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets. Rev. 4.00 Jul. 25, 2008 Page 76 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.3 5.3.1 Address Errors Address Error Sources Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from a space other than on-chip peripheral module space Instruction fetched from on-chip peripheral module space Data read/write CPU Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space Longword data accessed in 16-bit on-chip peripheral module space Longword data accessed in 8-bit on-chip peripheral module space Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) None (normal) Rev. 4.00 Jul. 25, 2008 Page 77 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.3.2 Address Error Exception Source When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address of the instruction which caused an address error exception. When the instruction that caused the exception is placed in the delay slot, the address of the delayed branch instruction which is placed immediately before the delay slot. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the generated address error, and the program starts executing from that address. This branch is not a delayed branch. Rev. 4.00 Jul. 25, 2008 Page 78 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.4 5.4.1 Interrupts Interrupt Sources Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, IRQ, and on-chip peripheral modules. Table 5.7 Type NMI User break IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) User break controller (UBC) IRQ0 to IRQ3 pins (external input) Multi-function timer pulse unit 2 (MTU2) Watchdog timer (WDT) A/D converter (A/D_0 and A/D_1) Compare match timer (CMT_0 and CMT_1) Serial communication interface (SCI_0, SCI_1, and SCI_2) Port output enable (POE) Number of Sources 1 1 4 (SH7125) 3 (SH7124) 28 1 2 2 12 2 All interrupt sources are given different vector numbers and vector table address offsets. For details on vector numbers and vector table address offsets, see table 6.3 in section 6, Interrupt Controller (INTC). Rev. 4.00 Jul. 25, 2008 Page 79 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.4.2 Interrupt Priority The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM) of the INTC as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRF, see section 6.3.4, Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). Table 5.8 Type NMI User break IRQ On-chip peripheral module Interrupt Priority Priority Level 16 15 0 to 15 Comment Fixed priority level. Cannot be masked. Fixed priority level. Can be masked. Set with interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). 5.4.3 Interrupt Exception Handling When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception handling begins. In interrupt exception handling, the CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched from the exception handling vector table for the accepted interrupt, and program execution branches to that address and the program starts. For details on the interrupt exception handling, see section 6.6, Interrupt Operation. Rev. 4.00 Jul. 25, 2008 Page 80 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.5 5.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Type Trap instruction Illegal slot instructions* Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that changes the PC value Comment  Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that changes the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR  General illegal instructions* Note: * Undefined code anywhere besides in a delay slot The operation is not guaranteed when undefined instructions other than H'F000 to H'FFFF are decoded. 5.5.2 Trap Instructions When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start address of the exception handling routine from the exception handling vector table that corresponds to the vector number specified in the TRAPA instruction, program execution branches to that address, and then the program starts. This branch is not a delayed branch. Rev. 4.00 Jul. 25, 2008 Page 81 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the undefined code is decoded. Illegal slot exception handling also starts when an instruction that changes the program counter (PC) value is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the exception that occurred. Program execution branches to that address and the program starts. This branch is not a delayed branch. 5.5.4 General Illegal Instructions When an undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. Rev. 4.00 Jul. 25, 2008 Page 82 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.6 Cases when Exceptions are Accepted When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the exception is accepted. Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions Exception Address Error ×* 2 Occurrence Timing Instruction in delay slot General Illegal Instruction  √ Slot Illegal Instruction ×* √ 2 Trap Instruction  √ Interrupt × *3 ×*4 Immediately after interrupt √ disabled instruction*1 [Legend] √: Accepted ×: Not accepted : Does not occur Notes: 1. Interrupt disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 2. An exception is accepted before the execution of a delayed branch instruction. However, when an address error or a slot illegal instruction exception occurs in the delay slot of the RTE instruction, correct operation is not guaranteed. 3. An exception is accepted after a delayed branch (between instructions in the delay slot and the branch destination). 4. An exception is accepted after the execution of the next instruction of an interrupt disabled instruction (before the execution two instructions after an interrupt disabled instruction). Rev. 4.00 Jul. 25, 2008 Page 83 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.7 Stack States after Exception Handling Ends The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Address error (when the instruction that caused an exception is placed in the delay slot) Stack State SP → Address of delayed branch instruction SR 32 bits 32 bits Address error (other than above) SP → Address of instruction that caused exception SR 32 bits 32 bits Interrupt SP → Address of instruction after executed instruction SR 32 bits 32 bits Trap instruction SP → Address of instruction after TRAPA instruction SR 32 bits 32 bits Rev. 4.00 Jul. 25, 2008 Page 84 of 750 REJ09B0243-0400 Section 5 Exception Handling Types Illegal slot instruction Stack State SP → Address of delayed branch instruction SR 32 bits 32 bits General illegal instruction SP → Address of general illegal instruction SR 32 bits 32 bits Rev. 4.00 Jul. 25, 2008 Page 85 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.8 5.8.1 Usage Notes Value of Stack Pointer (SP) The SP value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.2 Value of Vector Base Register (VBR) The VBR value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling When the SP value is not a multiple of 4, an address error will occur when stacking for exception handling (interrupts, etc.) and address error exception handling will start after the first exception handling is ended. Address errors will also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be passed to the handling routine for address error exception and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. When stacking the SR and PC values, the SP values for both are subtracted by 4, therefore, the SP value is still not a multiple of 4 after the stacking. The address value output during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is undefined. Rev. 4.00 Jul. 25, 2008 Page 86 of 750 REJ09B0243-0400 Section 5 Exception Handling 5.8.4 Notes on Slot Illegal Instruction Exception Handling Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. • Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot illegal instructions. • This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal instructions. The supporting status on our software products regarding this note is as follows: Compiler This instruction is not allocated in the delay slot in the compiler V.4 and its subsequent versions. Real-time OS for µITRON specifications 1. HI7000/4, HI-SH7 This instruction does not exist in the delay slot within the OS. 2. HI7000 This instruction is in part allocated to the delay slot within the OS, which may cause the slot illegal instruction exception handling in this LSI. 3. Others The slot illegal instruction exception handling may be generated in this LSI in a case where the instruction is described in assembler or when the middleware of the object is introduced. Note that a check-up program (checker) to pick up this instruction is available on our website. Download and utilize this checker as needed. Rev. 4.00 Jul. 25, 2008 Page 87 of 750 REJ09B0243-0400 Section 5 Exception Handling Rev. 4.00 Jul. 25, 2008 Page 88 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features • 16 levels of interrupt priority • NMI noise canceller function • Occurrence of interrupt can be reported externally (IRQOUT pin) Rev. 4.00 Jul. 25, 2008 Page 89 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ0 * IRQ1 IRQ2 IRQ3 Input control CPU request determination Priority determination Comparator Interrupt request SR I3 I2 I1 I0 UBC WDT CMT MTU2 A/D SCI POE (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) CPU ICR0 IRQCR IRQSR IPR IPRA to IPRF, IPRH to IPRM Module bus INTC Bus interface [Legend] UBC: WDT: CMT: SCI: MTU2: A/D: POE: User break controller Watchdog timer Compare match timer Serial communication interface Multi-function timer pulse unit 2 A/D converter Port output enable ICR0: IRQCR: IRQSR: IPRA to IPRF, IPRH to IPRM: SR: Interrupt control register 0 IRQ control register IRQ status register Interrupt priority registers A to F and H to M Status register Note: Supported only by the SH7125. Figure 6.1 Block Diagram of INTC Rev. 4.00 Jul. 25, 2008 Page 90 of 750 REJ09B0243-0400 Internal bus Section 6 Interrupt Controller (INTC) 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin Pin Configuration Abbr. NMI IRQ0 to IRQ3 IRQOUT I/O Input Input Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals Output Output of notification signal when an interrupt has occurred Rev. 4.00 Jul. 25, 2008 Page 91 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.3 Register Descriptions The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. Table 6.2 Register Configuration Abbreviation ICR0 IRQCR IRQSR IPRA IPRB IPRC IPRD IPRE IPRF IPRH IPRI IPRJ IPRK IPRL IPRM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'x000 H'0000 H'Fx00 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFFE900 H'FFFFE902 H'FFFFE904 H'FFFFE906 H'FFFFE908 H'FFFFE980 H'FFFFE982 H'FFFFE984 H'FFFFE986 H'FFFFE98A H'FFFFE98C H'FFFFE98E H'FFFFE990 H'FFFFE992 H'FFFFE994 Access Size 8, 16 8, 16 8, 16 8, 16 8, 16 16 16 16 16 16 16 16 16 16 16 Register Name Interrupt control register 0 IRQ control register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt priority register M Rev. 4.00 Jul. 25, 2008 Page 92 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit: 15 NMIL 14 - 13 - 12 - 11 - 10 - 9 - 8 NMIE 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: * R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: * The initial value is 1 when the level on the NMI pin is high, and 0 when the level on the pin is low. Bit 15 Initial Bit Name Value NMIL * R/W R Description NMI Input Level Indicates the state of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: State of the NMI input is low 1: State of the NMI input is high 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select 0: Interrupt request is detected on the falling edge of the NMI input 1: Interrupt request is detected on the rising edge of the NMI input 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 93 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.3.2 IRQ Control Register (IRQCR) IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ3. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 8 Bit Name  Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 IRQ31S IRQ30S 0 0 R/W R/W IRQ3 Sense Select Set the interrupt request detection mode for pin IRQ3. 00: Interrupt request is detected at the low level of pin IRQ3 01: Interrupt request is detected at the falling edge of pin IRQ3 10: Interrupt request is detected at the rising edge of pin IRQ3 11: Interrupt request is detected at both the falling and rising edges of pin IRQ3 5 4 IRQ21S IRQ20S 0 0 R/W R/W IRQ2 Sense Select Set the interrupt request detection mode for pin IRQ2. 00: Interrupt request is detected at the low level of pin IRQ2 01: Interrupt request is detected at the falling edge of pin IRQ2 10: Interrupt request is detected at the rising edge of pin IRQ2 11: Interrupt request is detected at both the falling and rising edges of pin IRQ2 Rev. 4.00 Jul. 25, 2008 Page 94 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Bit 3 2 Bit Name IRQ11S IRQ10S Initial Value 0 0 R/W R/W R/W Description IRQ1 Sense Select Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the low level of pin IRQ1 01: Interrupt request is detected at the falling edge of pin IRQ1 10: Interrupt request is detected at the rising edge of pin IRQ1 11: Interrupt request is detected at both the falling and rising edges of pin IRQ1 1 0 IRQ01S IRQ00S 0 0 R/W R/W IRQ0 Sense Select (SH7125) Set the interrupt request detection mode for pin IRQ0. 00: Interrupt request is detected at the low level of pin IRQ0 01: Interrupt request is detected at the falling edge of pin IRQ0 10: Interrupt request is detected at the rising edge of pin IRQ0 11: Interrupt request is detected at both the falling and rising edges of pin IRQ0 Reserved (SH7124) These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 95 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.3.3 IRQ Status register (IRQSR) IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ3 and the status of interrupt request. Bit: 15 - 14 - 13 - 12 - 11 10 9 8 7 - 6 - 5 - 4 - 3 2 1 0 IRQ3L IRQ2L IRQ1L IRQ0L IRQ3F IRQ2F IRQ1F IRQ0F Initial value: 1 R/W: R 1 R 1 R 1 R * R * R * R * R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low. Bit 15 to 12 11 Bit Name  IRQ3L Initial Value All 1 * R/W R R Description Reserved These bits are always read as 1. Indicates the state of pin IRQ3. 0: State of pin IRQ3 is low 1: State of pin IRQ3 is high 10 IRQ2L * R Indicates the state of pin IRQ2. 0: State of pin IRQ2 is low 1: State of pin IRQ2 is high 9 IRQ1L * R Indicates the state of pin IRQ1. 0: State of pin IRQ1 is low 1: State of pin IRQ1 is high 8 IRQ0L * R Indicates the state of pin IRQ0. 0: State of pin IRQ0 is low 1: State of pin IRQ0 is high 7to 4  All 0  Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 96 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Bit 3 Bit Name IRQ3F Initial Value 0 R/W R/W Description Indicates the status of an IRQ3 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ3 high 1: An IRQ3 interrupt has been detected [Setting condition] Driving pin IRQ3 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ3F = 1  Accepting an IRQ3 interrupt 1: An IRQ3 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ3 0: An IRQ3 interrupt has not been detected 0: An IRQ3 interrupt has not been detected Rev. 4.00 Jul. 25, 2008 Page 97 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Bit 2 Bit Name IRQ2F Initial Value 0 R/W R/W Description Indicates the status of an IRQ2 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ2 high 1: An IRQ2 interrupt has been detected [Setting condition] Driving pin IRQ2 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ2F = 1  Accepting an IRQ2 interrupt 1: An IRQ2 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ2 0: An IRQ2 interrupt has not been detected 0: An IRQ2 interrupt has not been detected 1 IRQ1F 0 R/W Indicates the status of an IRQ1 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ1 high 1: An IRQ1 interrupt has been detected [Setting condition] Driving pin IRQ1 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ1F = 1  Accepting an IRQ1 interrupt 1: An IRQ1 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ1 0: An IRQ1 interrupt has not been detected 0: An IRQ1 interrupt has not been detected Rev. 4.00 Jul. 25, 2008 Page 98 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Bit 0 Bit Name IRQ0F Initial Value 0 R/W R/W Description Indicates the status of an IRQ0 interrupt request. • When level detection mode is selected [Clearing condition] Driving pin IRQ0 high 1: An IRQ0 interrupt has been detected [Setting condition] Driving pin IRQ0 low • When edge detection mode is selected [Clearing conditions]  Writing 0 after reading IRQ0F = 1  Accepting an IRQ0 interrupt 1: An IRQ0 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ0 0: An IRQ0 interrupt has not been detected 0: An IRQ0 interrupt has not been detected Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low. 6.3.4 Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM) Interrupt priority registers are twelve 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPR[15:12] IPR[11:8] IPR[7:4] IPR[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 4.00 Jul. 25, 2008 Page 99 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Bit 15 to 12 Bit Name IPR[15:12] Initial Value 0000 R/W R/W Description Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 11 to 8 IPR[11:8] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) Rev. 4.00 Jul. 25, 2008 Page 100 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Bit 7 to 4 Bit Name IPR[7:4] Initial Value 0000 R/W R/W Description Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 3 to 0 IPR[3:0] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name. Rev. 4.00 Jul. 25, 2008 Page 101 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.4 6.4.1 Interrupt Sources External Interrupts There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15. IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ3. Use the IRQ sense select bits (IRQ31S, IRQ30S to IRQ01S, and IRQ00S) in the IRQ control register (IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority register A (IPRA). In the case that the low level detection is selected, an interrupt request signal is sent to the INTC while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when the following change on the IRQ pin is detected: from high to low in falling edge detection mode, from low to high in rising edge detection mode, and from low to high or from high to low in both edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been detected by reading the IRQ flags (IRQ3F to IRQ0F) in the IRQ status register (IRQSR). An IRQ interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag after reading 1. In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of the IRQ3 to IRQ0 interrupts. Rev. 4.00 Jul. 25, 2008 Page 102 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) IRQSR.IRQnL IRQCR.IRQn1S IRQCR.IRQn0S IRQSR.IRQnF Selection IRQn pins Level detection Edge detection S Q Distribution CPU interrupt request RESIRQn (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) R n = 3 to 0 Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. Since a different interrupt vector is allocated to each interrupt source, the exception handling routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be allocated to individual on-chip peripheral modules in interrupt priority registers C to F and H to M (IPRC to IPRF and IPRH to IPRM). On-chip peripheral module interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.4.3 User Break Interrupt A user break interrupt has a priority level of 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see section 7, User Break Controller (UBC). Rev. 4.00 Jul. 25, 2008 Page 103 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Handling Vector Table Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated from the vector numbers and vector table address offsets. For interrupt exception handling, the start address of the exception handling routine is fetched from the vector table address in the vector table. For the details on calculation of vector table addresses, see table 5.4 in section 5, Exception Handling. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). However, when interrupt sources whose priority levels are allocated with the same IPR are requested, the interrupt of the smaller vector number has priority. This priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order shown in table 6.3. Rev. 4.00 Jul. 25, 2008 Page 104 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Table 6.3 Interrupt Source User break External pin Interrupt Exception Handling Vectors and Priorities Name Vector No. 12 NMI 11 Vector Table Starting Address IPR H'00000030 H'0000002C H'00000100 H'00000104 H'00000108 H'0000010C H'00000160 H'00000164 H'00000168 H'0000016C H'00000170 H'00000174 H'00000178 H'00000180 H'00000184 H'00000190 H'00000194 H'000001A0 H'000001A4 H'000001B0 H'000001B4 H'000001C0 H'000001C4 H'000001C8 H'000001CC H'000001D0 IPRE3 to IPRE0 Low IPRE7 to IPRE4 IPRE11 to IPRE8 IPRE15 to IPRE12 IPRD3 to IPRD0 IPRD7 to IPRD4 IPRD11 to IPRD8   IPRA15 to IPRA12 IPRA11 to IPRA8 IPRA7 to IPRA4 IPRA3 to IPRA0 IPRD15 to IPRD12 Default Priority High IRQ0 (only SH7125) 64 IRQ1 IRQ2 IRQ3 MTU2_0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 TGIE_0 TGIF_0 MTU2_1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 MTU2_2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 MTU2_3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 65 66 67 88 89 90 91 92 93 94 96 97 100 101 104 105 108 109 112 113 114 115 116 Rev. 4.00 Jul. 25, 2008 Page 105 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Interrupt Source MTU2_4 Name TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 Vector No. 120 121 122 123 124 128 129 130 132 133 184 188 196 200 201 216 217 218 219 220 221 222 223 224 225 226 227 Vector Table Starting Address IPR H'000001E0 H'000001E4 H'000001E8 H'000001EC H'000001F0 H'00000200 H'00000204 H'00000208 H'00000210 H'00000214 H'000002E0 H'000002F0 H'00000310 H'00000320 H'00000324 H'00000360 H'00000364 H'00000368 H'0000036C H'00000370 H'00000374 H'00000378 H'0000037C H'00000380 H'00000384 H'00000388 H'0000038C IPRL7 to IPRL4 IPRL11 to IPRL8 IPRL15 to IPRL12 IPRJ15 to IPRJ12 IPRJ11 to IPRJ8 IPRJ3 to IPRJ0 IPRK15 to IPRK12 IPRF3 to IPRF0 IPRF11 to IPRF8 IPRF7 to IPRF4 IPRF15 to IPRF12 Default Priority High MTU2_5 TGIU_5 TGIV_5 TGIW_5 POE (MTU2) OEI1 OEI3 CMT_0 CMT_1 WDT A/D_0 and A/D_1 SCI_0 CMI_0 CMI_1 ITI ADI_0 ADI_1 ERI_0 RXI_0 TXI_0 TEI_0 SCI_1 ERI_1 RXI_1 TXI_1 TEI_1 SCI_2 ERI_2 RXI_2 TXI_2 TEI_2 Low Rev. 4.00 Jul. 25, 2008 Page 106 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.6 6.6.1 Interrupt Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from interrupt requests sent, according to the priority levels set in interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority shown in table 6.3. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling. 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR. 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in 5. above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the IRQOUT pin holds low level. 9. The CPU reads the start address of the exception handling routine from the exception vector table for the accepted interrupt, branches to that address, and starts executing the program. This branch is not a delayed branch. Rev. 4.00 Jul. 25, 2008 Page 107 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Notes: The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (IRQSR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. Rev. 4.00 Jul. 25, 2008 Page 108 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Program execution state Interrupt? Yes User break? Yes No No NMI? Yes No Level 15 interrupt? Yes I3 to I0 ≤ level 14? Yes Yes No I3 to I0 ≤ level 14? No Yes No Level 14 interrupt? Yes I3 to I0 ≤ level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No IRQOUT = low Save SR to stack Save PC to stack Copy interrupt level to I3 to I0 IRQOUT = high Read exception vector table Branch to exception handling routine * 1 *3 *2 *3 Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU 1. IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1). Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR. 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the CPU, the IRQOUT pin holds low level. 3. The IRQOUT pin change timing depends on a frequency dividing ratio between the internal (Iφ) and bus (Bφ) clocks. This flowchart shows that the frequency dividing ratios of the internal (Iφ) and bus (Bφ) clocks are the same. Figure 6.3 Interrupt Sequence Flowchart Rev. 4.00 Jul. 25, 2008 Page 109 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Handling Figure 6.4 shows the stack after interrupt exception handling. Address 4n – 8 4n – 4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Handling 6.7 Interrupt Response Time Table 6.4 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Rev. 4.00 Jul. 25, 2008 Page 110 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) Table 6.4 Interrupt Response Time Number of Cycles Item Interrupt priority decision and comparison with mask bits in SR Wait for completion of sequence currently being executed by CPU NMI 1 × Icyc + 2 × Pcyc X (≥ 0) IRQ 1 × Icyc + 1 × Pcyc X (≥ 0) Peripheral Modules 1 × Icyc + 2 × Pcyc X (≥ 0) Remarks The longest sequence is for interrupt or addresserror exception handling (X = 7 × Icyc + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Performs the saving PC and SR, and vector address fetch. Time from start of interrupt exception handling until fetch of first instruction of exception handling routine starts Interrupt response time Total: 8 × Icyc + m 1 + m2 + m3 8 × Icyc + m 1 + m2 + m3 8 × Icyc + m 1 + m2 + m3 9 × Icyc + 2 × 9 × Icyc + 1 × 9 × Icyc + 2 × Pcyc + m1 + m2 Pcyc + m1 + m2 Pcyc + m1 + m2 + m3 + X + m3 + X + m3 + X 12 × Icyc + 2 × Pcyc 16 × Icyc + 2 × Pcyc + 2 × (m1 + m2 + m3) + m4 12 × Icyc + 1 × Pcyc 16 × Icyc + 1 × Pcyc + 2 (m1 + m2 + m3) + m4 12 × Icyc + 2 × Pcyc 16 × Icyc + 2 × Pcyc + 2 (m1 + m2 + m3) + m4 SR, PC, and vector table are all in on-chip RAM. Minimum*: Maximum: Notes: * In the case that m1 = m2 = m3 = m4 = 1 × Icyc. m1 to m4 are the number of cycles needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev. 4.00 Jul. 25, 2008 Page 111 of 750 REJ09B0243-0400 Section 6 Interrupt Controller (INTC) 6.8 Usage Note The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction. Rev. 4.00 Jul. 25, 2008 Page 112 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. 7.1 Features The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle). • Address Comparison bits are maskable in 1-bit units. One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected. • Data 32-bit maskable. One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected. • Bus cycle Instruction fetch or data access • Read/write • Operand size Byte, word, and longword 2. A user-designed user-break condition interrupt exception processing routine can be run. 3. In an instruction fetch cycle, it can be selected that a user-break is set before or after an instruction is executed. 4. Maximum repeat times for the break condition (only for channel B): 212 – 1 times. 5. Four pairs of branch source/destination buffers. Rev. 4.00 Jul. 25, 2008 Page 113 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Figure 7.1 shows a block diagram of the UBC. LDB Access IDB control IAB LAB Access comparator BBRA BARA Address comparator BAMRA BDRA BDMRA Internal bus Data comparator Channel A Access comparator BBRB BARB Address comparator BAMRB Data comparator Channel B BDRB BDMRB BETR BRSR PC trace BRDR Control BRCR CPU state signals [Legend] BBRA: BARA: BAMRA: BDRA: BDMRA: BBRB: BARB: BAMRB: User break interrupt request Break bus cycle register A Break address register A Break address mask register A Break data register A Break data mask register A Break bus cycle register B Break address register B Break address mask register B BDRB: BDMRB: BETR: BRSR: BRDR: BRCR: Break data register B Break data mask register B Execution times break register Branch source register Branch destination register Break control register Figure 7.1 Block Diagram of UBC Rev. 4.00 Jul. 25, 2008 Page 114 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2 Register Descriptions The user break controller has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 7.1 Register Configuration Abbreviation BARA R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W Initial Value H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 H'00000000 H'0000 H'00000000 H'00000000 H'00000000 H'0xxxxxxx H'0xxxxxxx H'0000 Address H'FFFFF300 H'FFFFF304 H'FFFFF308 H'FFFFF310 H'FFFFF314 H'FFFFF320 H'FFFFF324 H'FFFFF328 H'FFFFF330 H'FFFFF334 H'FFFFF3C0 H'FFFFF3D0 H'FFFFF3D4 H'FFFFF3DC Access Size 32 32 16 32 32 32 32 16 32 32 32 32 32 16 Register Name Break address register A Break address mask register A BAMRA Break bus cycle register A Break data register A Break data mask register A Break address register B BBRA BDRA BDMRA BARB Break address mask register B BAMRB Break bus cycle register B Break data register B Break data mask register B Break control register Branch source register Branch destination register BBRB BDRB BDMRB BRCR BRSR BRDR Execution times break register BETR Rev. 4.00 Jul. 25, 2008 Page 115 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.1 Break Address Register A (BARA) BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 BAA9 0 R/W 8 BAA8 0 R/W 7 BAA7 0 R/W 6 BAA6 0 R/W 5 BAA5 0 R/W 4 BAA4 0 R/W 3 BAA3 0 R/W 2 BAA2 0 R/W 1 BAA1 0 R/W 0 BAA0 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name BAA31 to BAA 0 Initial Value All 0 R/W R/W Description Break Address A Store the address on the LAB or IAB specifying break conditions of channel A. 7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BAMA8 0 R/W 7 BAMA7 0 R/W 6 BAMA6 0 R/W 5 BAMA5 0 R/W 4 BAMA4 0 R/W 3 BAMA3 0 R/W 2 BAMA2 0 R/W 1 BAMA1 0 R/W 0 BAMA0 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 4.00 Jul. 25, 2008 Page 116 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 BAMA31 to All 0 BAMA 0 7.2.3 Break Bus Cycle Register A (BBRA) BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel A. Bit: 15 - 14 - 13 - 12 - 11 - 10 9 CPA[2:0] 8 7 6 5 4 3 2 1 0 CDA[1:0] IDA[1:0] RWA[1:0] SZA[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 11  10 to 8 CPA[2:0] 000 R/W Bus Master Select A for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel A break condition. However, when the L bus is selected as the bus cycle, the setting of the CPA2 to CPA0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: Setting prohibited 1xx: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 117 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bit 7, 6 Bit Name CDA[1:0] Initial Value 00 R/W R/W Description L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle 5, 4 IDA[1:0] 00 R/W Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3, 2 RWA[1:0] 00 R/W Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1, 0 SZA[1:0] 00 R/W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care. Rev. 4.00 Jul. 25, 2008 Page 118 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.4 Break Data Register A (BDRA) BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select one of two data buses for break condition A. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 BDA9 0 R/W 8 BDA8 0 R/W 7 BDA7 0 R/W 6 BDA6 0 R/W 5 BDA5 0 R/W 4 BDA4 0 R/W 3 BDA3 0 R/W 2 BDA2 0 R/W 1 BDA1 0 R/W 0 BDA0 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name BDA31 to BDA0 Initial Value All 0 R/W R/W Description Break Data Bit A Stores data, which specifies a break condition in channel A. If the I bus is selected in BBRA, the break data on IDB is set in BDA31 to BDA0. If the L bus is selected in BBRA, the break data on LDB is set in BDA31 to BDA0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRA as the break data. Rev. 4.00 Jul. 25, 2008 Page 119 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.5 Break Data Mask Register A (BDMRA) BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data specified by BDRA. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BDMA8 0 R/W 7 BDMA7 0 R/W 6 BDMA6 0 R/W 5 BDMA5 0 R/W 4 BDMA4 0 R/W 3 BDMA3 0 R/W 2 BDMA2 0 R/W 1 BDMA1 0 R/W 0 BDMA0 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Data Mask A Specifies bits masked in the break data of channel A specified by BDRA (BDA31 to BDA0). 0: Break data BDAn of channel A is included in the break condition 1: Break data BDAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 BDMA31 to All 0 BDMA 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRA as the break mask data in BDRA. Rev. 4.00 Jul. 25, 2008 Page 120 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.6 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for break condition B. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 BAB9 0 R/W 8 BAB8 0 R/W 7 BAB7 0 R/W 6 BAB6 0 R/W 5 BAB5 0 R/W 4 BAB4 0 R/W 3 BAB3 0 R/W 2 BAB2 0 R/W 1 BAB1 0 R/W 0 BAB0 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name BAB31 to BAB 0 Initial Value All 0 R/W R/W Description Break Address B Stores an address, which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0. Rev. 4.00 Jul. 25, 2008 Page 121 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.7 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BAMB8 0 R/W 7 BAMB7 0 R/W 6 BAMB6 0 R/W 5 BAMB5 0 R/W 4 BAMB4 0 R/W 3 BAMB3 0 R/W 2 BAMB2 0 R/W 1 BAMB1 0 R/W 0 BAMB0 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 BAMB31 to All 0 BAMB 0 Rev. 4.00 Jul. 25, 2008 Page 122 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.8 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select one of the two data buses for break condition B. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BDB8 0 R/W 7 BDB7 0 R/W 6 BDB6 0 R/W 5 BDB5 0 R/W 4 BDB4 0 R/W 3 BDB3 0 R/W 2 BDB2 0 R/W 1 BDB1 0 R/W 0 BDB0 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name BDB31 to BDB0 Initial Value All 0 R/W R/W Description Break Data Bit B Stores data which specifies a break condition in channel B. If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data. Rev. 4.00 Jul. 25, 2008 Page 123 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.9 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 BDMB8 0 R/W 7 BDMB7 0 R/W 6 BDMB6 0 R/W 5 BDMB5 0 R/W 4 BDMB4 0 R/W 3 BDMB3 0 R/W 2 BDMB2 0 R/W 1 BDMB1 0 R/W 0 BDMB0 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 BDMB31 to All 0 BDMB 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRB as the break mask data in BDRB. Rev. 4.00 Jul. 25, 2008 Page 124 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.10 Break Bus Cycle Register B (BBRB) BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit: 15 - 14 - 13 - 12 - 11 - 10 9 CPB[2:0] 8 7 6 5 4 3 2 1 0 CDB[1:0] IDB[1:0] RWB[1:0] SZB[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 11 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 CPB[2:0] 000 R/W Bus Master Select B for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel B break condition. However, when the L bus is selected as the bus cycle, the setting of the CPB2 to CPB0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: Setting prohibited 1xx: Setting prohibited 7, 6 CDB[1:0] 00 R/W L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle Rev. 4.00 Jul. 25, 2008 Page 125 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bit 5, 4 Bit Name IDB[1:0] Initial Value 00 R/W R/W Description Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3, 2 RWB[1:0] 00 R/W Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1, 0 SZB[1:0] 0 R/W Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care. Rev. 4.00 Jul. 25, 2008 Page 126 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.11 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channels A and B in comparison conditions. 5. Enable PC trace. 6. Specify whether to request the user break interrupt when channels A and B match with comparison conditions. BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 UBIDB 18 - 17 UBIDA 16 - Initial value: R/W: 0 R 0 R 14 SCM FCB 0 R 13 SCM FDA 0 R 12 SCM FDB 0 R 11 PCTE 0 R 10 PCBA 0 R 9 - 0 R 8 - 0 R 7 DBEA 0 R 6 PCBB 0 R 5 DBEB 0 R 4 - 0 R/W 3 SEQ 0 R 2 - 0 R/W 1 - 0 R 0 ETBE Bit: 15 SCM FCA Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R 0 R 0 R/W Bit 31 to 20 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 19 UBIDB 0 R/W User Break Disable B Enables or disables the user break interrupt request when the channel B break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied Rev. 4.00 Jul. 25, 2008 Page 127 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bit 18 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 17 UBIDA 0 R/W User Break Disable A Enables or disables the user break interrupt request when the channel A break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied 16  0 R Reserved This bit is always read as 0. The write value should always be 0. 15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches 14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches 13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches Rev. 4.00 Jul. 25, 2008 Page 128 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bit 12 Bit Name SCMFDB Initial Value 0 R/W R/W Description I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches 11 PCTE 0 R/W PC Trace Enable 0: Disables PC trace 1: Enables PC trace 10 PCBA 0 R/W PC Break Select A Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9, 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 DBEA 0 R/W Data Break Enable A Selects whether or not the data bus condition is included in the break condition of channel A. 0: No data bus condition is included in the condition of channel A 1: The data bus condition is included in the condition of channel A 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution Rev. 4.00 Jul. 25, 2008 Page 129 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bit 5 Bit Name DBEB Initial Value 0 R/W R/W Description Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 SEQ 0 R/W Sequence Condition Select Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2, 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ETBE 0 R/W Number of Execution Times Break Enable Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is requested when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B Rev. 4.00 Jul. 25, 2008 Page 130 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.12 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 – 1 times. When a break condition is satisfied, it decreases BETR. A userbreak interrupt is requested when the break condition is satisfied after BETR becomes H'0001. Bit: 15 - 14 - 13 - 12 - 11 10 9 8 7 6 BET[11:0] 5 4 3 2 1 0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 to 12 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET[11:0] All 0 R/W Number of Execution Times Rev. 4.00 Jul. 25, 2008 Page 131 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.13 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 by a power-on reset or manual reset when BRSR is read or the setting to enable PC trace is made. Other bits are not initialized by a power-on reset. The eight BRSR registers have a queue structure and a stored register is shifted at every branch. Bit: 31 SVF 30 - 29 - 28 - 27 26 25 24 23 22 21 20 19 18 17 16 BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 Initial value: R/W: 0 R 0 R 14 0 R 13 0 R 12 R 11 R 10 R 9 BSA9 R 8 BSA8 R 7 BSA7 R 6 BSA6 R 5 BSA5 R 4 BSA4 R 3 BSA3 R 2 BSA2 R 1 BSA1 R 0 BSA0 Bit: 15 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 Initial value: R/W: R R R R R R R R R R R R R R R R Bit 31 Bit Name SVF Initial Value 0 R/W R Description BRSR Valid Flag Indicates whether the branch source address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 Undefined R Branch Source Address Store bits 27 to 0 of the branch source address. Rev. 4.00 Jul. 25, 2008 Page 132 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.2.14 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 by a power-on reset or manual reset when BRDR is read or the setting to enable PC trace is made. Other bits are not initialized by a power-on reset. The eight BRDR registers have a queue structure and a stored register is shifted at every branch. Bit: 31 DVF 30 - 29 - 28 - 27 26 25 24 23 22 21 20 19 18 17 16 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 Initial value: R/W: 0 R 0 R 14 0 R 13 0 R 12 R 11 R 10 R 9 BDA9 R 8 BDA8 R 7 BDA7 R 6 BDA6 R 5 BDA5 R 4 BDA4 R 3 BDA3 R 2 BDA2 R 1 BDA1 R 0 BDA0 Bit: 15 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 Initial value: R/W: R R R R R R R R R R R R R R R R Bit 31 Bit Name DVF Initial Value 0 R/W R Description BRDR Valid Flag Indicates whether a branch destination address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 Undefined R Branch Destination Address Store bits 27 to 0 of the branch destination address. Rev. 4.00 Jul. 25, 2008 Page 133 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.3 7.3.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRA or BDRB). The masked data is set in the break data mask register (BDMRA or BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with B'00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. Before using them again, 0 must first be written to them and then reset flags. 4. There may be an occasion when a break condition match occurs both in channels A and B around the same time. In this case, the flags for both conditions matches will be set even though only one user-break interrupt request is issued to the CPU. 5. When selecting the I bus as the break condition, note the following:  The CPU is connected to the I bus. The UBC monitors bus cycles generated by all bus masters that are selected by the CPA2 to CPA0 bits in BBRA or the CPB2 to CPB0 bits in BBRB, and compares the condition match.  I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles.  If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the userbreak is to be accepted cannot be clearly defined. Rev. 4.00 Jul. 25, 2008 Page 134 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.3.2 Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit in the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A break cannot be generated as long as this bit is set to 1. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the condition is specified to be occur after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDRA or BDRB) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 7.3.1, Flow of the User Break Operation. 7.3.3 Break on Data Access Cycle 1. If the L bus is specified as a break condition for data access break, condition comparison is performed for the address (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 7.3.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 7.2. Rev. 4.00 Jul. 25, 2008 Page 135 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Table 7.2 Access Size Longword Word Byte Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register (BBRA or BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register (BDRA or BDRB) and break data mask register (BDMRA or BDMRB). When word or byte is set, bits 31 to 16 of BDRA or BDRB and BDMRA or BDMRB are ignored. 4. If the L bus is selected, a break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the break will occur cannot be determined. When this kind of break occurs at a delayed branch instruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. Rev. 4.00 Jul. 25, 2008 Page 136 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.3.4 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0 and clear also the condition match flag to 0 in channel A. 2. In sequential break specification, the L or I bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched. 7.3.5 Value of Saved Program Counter When a break occurs, the address of the instruction from where execution is to be resumed is saved in the stack, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the stack. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the stack. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However, when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the stack. 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the stack. Rev. 4.00 Jul. 25, 2008 Page 137 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the stack. At which instruction the break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the stack. If the instruction following the instruction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the stack. 7.3.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch.  If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR.  If a branch occurs due to an interrupt or exception, the value saved in stack due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. 3. BRSR and BRDR have four pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. Rev. 4.00 Jul. 25, 2008 Page 138 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.3.7 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) • Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode Address: H'00000404, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2) • Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Rev. 4.00 Jul. 25, 2008 Page 139 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed. (Example 1-3) • Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000 Specified conditions: Channel A/channel B independent mode Address: H'00027128, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. (Example 1-4) • Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word Rev. 4.00 Jul. 25, 2008 Page 140 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs. (Example 1-5) • Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode Address: H'00000500, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword On channel A, a user break occurs after the instruction of address H'00000500 is executed four times and before the fifth time. On channel B, a user break occurs before an instruction of address H'00001000 is executed. (Example 1-6) • Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode Address: H'00008404, Address mask: H'00000FFF Data: H'00000000, Data mask: H'00000000 Rev. 4.00 Jul. 25, 2008 Page 141 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. Break Condition Specified for L Bus Data Access Cycle: (Example 2-1) • Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'00123456, Address mask: H'00000000 Data: H'12345678, Data mask: H'FFFFFFFF Bus cycle: L bus/data access/read (operand size is not included in the condition) Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Rev. 4.00 Jul. 25, 2008 Page 142 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) • Register specifications BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'01A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode Address: H'00314154, Address mask: H'00000000 Data: H'12345678, Data mask: H'FFFFFFFF Bus cycle: I bus (CPU cycle)/instruction fetch/read (operand size is not included in the condition) Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus (CPU cycle)/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314154 in the external memory space. On channel B, a user break occurs when byte data H'7x is written in address H'00055555 in the external memory space by the CPU. Rev. 4.00 Jul. 25, 2008 Page 143 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 7.4 Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, Exception Handling. If an exception with higher priority occurs, the user break is not generated.  Pre-execution break has the highest priority.  When a post-execution break or data access break occurs simultaneously with a reexecution-type exception (including pre-execution break) that has higher priority, the reexecution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended.  When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a break does not occur, the condition match flag is set. 5. Note the following exception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error by data access, the CPU address error is given priority to the break. Note that the UBC condition match flag is set in this case. 6. Note the following when a break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the break does not occur until the branch destination of the RTE instruction. 7. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. Rev. 4.00 Jul. 25, 2008 Page 144 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) 8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a SLEEP instruction or one or two instructions before a SLEEP instruction. Rev. 4.00 Jul. 25, 2008 Page 145 of 750 REJ09B0243-0400 Section 7 User Break Controller (UBC) Rev. 4.00 Jul. 25, 2008 Page 146 of 750 REJ09B0243-0400 Section 8 Bus State Controller (BSC) Section 8 Bus State Controller (BSC) The bus state controller (BSC) controls data transmission and reception between the internal buses (L bus, I bus, and peripheral bus) and also controls the CPU’s access to the on-chip FLASH, onchip RAM, and on-chip peripheral I/O. 8.1 Features • On-chip FLASH and RAM interface  32-bit data access per one clock cycle (I φ synchronous) 8.2 Address Map The address map is listed in table 8.1. Table 8.1 Address Map Size Address H'00000000 to H'00007FFF H'00008000 to H'0000FFFF H'00010000 to H'0001FFFF H'00020000 to H'FFFF9FFF Reserved  8 Kbytes Reserved  8 Kbytes  8 Kbytes 64 Kbytes  32 8/16 Type of Memory On-chip FLASH 128 Kbytes 64 Kbytes Version Version 128 Kbytes 64 Kbytes 32 Kbytes Version 32 Kbytes Reserved Bus Width 32 H'FFFFA000 to H'FFFFBFFF On-chip RAM H'FFFFC000 to H'FFFFFFFF On-chip peripheral 128 Kbytes 64 Kbytes I/O 8.3 Access to on-chip FLASH and on-chip RAM Access to the on-chip FLASH for read is synchronized with I φ clock and is executed in one clock cycle. For details on programming and erasing, see section 17, Flash Memory. Access to the on-chip RAM for read/write is synchronized with I φ clock and is executed in one clock cycle. For details, see section 18, RAM. Rev. 4.00 Jul. 25, 2008 Page 147 of 750 REJ09B0243-0400 Section 8 Bus State Controller (BSC) 8.4 Access to on-chip Peripheral I/O Register The on-chip peripheral I/O register is accessed by the bus state controller (BSC) as described in table 8.2. Table 8.2 Connection Bus Width of on-chip Peripheral Module and the Number of Access Cycles INTC 16 UBC 16 MTU2 16 POE2 16 WDT 16 SCI 8 ADC 16 CMT 16 PFC, Port 16 On-chip Peripheral Module Connection Bus Width Number of Access Cycles Write (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk Read (3 + n) × Iclk + (1 + m) × Bclk + 2 × Pclk + 2 × Iclk Note: When m = 0 to 3, Bclk:Pclk = 4:1 When n = 0 to 3, lclk:Bclk = 4:1 When m = 0, 1, Bclk:Pclk = 2:1 When n = 0, 1, lclk:Bclk = 2:1 When m = 0, Bclk:Pclk = 1:1 When n = 0, lclk:Bclk = 1:1 This LSI adopts synchronous logic, and data of each bus is input and output in synchronization with the rising edge of the corresponding clock. The L bus access takes one Iclk cycle, I bus access takes one Bclk cycle, and peripheral bus access takes two Pclk cycles. When the on-chip peripheral I/O register is accessed by the CPU, the period required for preparation for data transfer to the I bus is a period of 3 Iclk cycles. Figure 8.1 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk = 4:1:1. From the L bus, to which the CPU is connected, data is output in synchronization with Iclk. Since there are four Iclk cycles in a single Bclk cycle when Iclk:Bclk = 4:1, data can be output onto the L bus in four possible timings within one Bclk cycle. Accordingly, a maximum of four Iclk cycles of period (four Iclk cycles in the example shown in the figure) is required before the rising edge of Bclk, on which data is transferred from the L bus to the I bus. Because of this, data is transferred from the L bus to the I bus in a period of (3 + n) × Iclk (n = 0 to 3) when Iclk:Bclk = 4:1. The relation of the timing of data output to the L bus and the rising edge of Bclk depends on the state of program execution. In the case shown in figure 8.1, where Bclk = Pclk = 1:1, the period required for access by the CPU is (3 + n) × Iclk + 1 × Bclk + 2 × Pclk. Rev. 4.00 Jul. 25, 2008 Page 148 of 750 REJ09B0243-0400 Section 8 Bus State Controller (BSC) Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8.1 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:1:1) Figure 8.2 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk = 4:4:1. From the L bus, to which the CPU is connected, data is output in synchronization with Iclk. When Iclk:Bclk = 1:1, a period of 3 Iclk + Bclk is required to transfer data from the L bus to the I bus. In data transfer from the I bus to the peripheral bus, there are four BIclk cycles in a single Pclk cycle when Bclk:Pclk = 4:1, and data can therefore be output onto the peripheral bus in four possible timings within one Pclk cycle. Accordingly, a maximum of four Bclk cycles of period (four Bclk cycles in the example shown in the figure) is required before the rising edge of Pclk, on which data is transferred from the I bus to the peripheral bus. Because of this, data is transferred from the I bus to the peripheral bus in a period of (1 + m) × Bclk (m = 0 to 3) when Bclk:Pclk = 4:1. The relation of the timing of data output to the I bus and the rising edge of Pclk depends on the state of program execution. In the case shown in figure 8.2, where Iclk = Bclk = 1:1, the period required for access by the CPU is 3 × Iclk + (1 + m) × Bclk + 2 × Pclk. Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8.2 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:4:1) Figure 8.3 shows an example of timing of read access to the peripheral bus when Iclk:Bclk:Pclk = 4:2:1. Transfer from the L bus to the peripheral bus is performed in the same way as for write access. In the case of reading, however, values output onto the peripheral bus must be transferred to the CPU. Transfers from the external bus to the I bus and from the I bus to the L bus are again performed in synchronization with rising edges of the respective bus clocks. 2 × Iclk cycles of Rev. 4.00 Jul. 25, 2008 Page 149 of 750 REJ09B0243-0400 Section 8 Bus State Controller (BSC) period is required because Iclk ≥ Bclk ≥ Pclk. In the case shown in figure 8.3, where n = 0 and m = 1, the period required for access by the CPU is 3 × Iclk + 2 × Bclk + 2 × Pclk + 2 × Iclk. Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8.3 Timing of Read Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:2:1) Rev. 4.00 Jul. 25, 2008 Page 150 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels. 9.1 Features • Maximum 16 (SH7125) or 12 (SH7124) pulse input/output lines and three pulse input lines • Selection of eight counter input clocks for each channel (four clocks for channel 5) • The following operations can be set for channels 0 to 4:  Waveform output at compare match  Input capture function  Counter clear operation  Multiple timer counters (TCNT) can be written to simultaneously  Simultaneous clearing by compare match and input capture is possible  Register simultaneous input/output is possible by synchronous counter operation  A maximum 12-phase PWM output is possible in combination with synchronous operation • Buffer operation settable for channels 0, 3, and 4 • Phase counting mode settable independently for each of channels 1 and 2 • Cascade connection operation • Fast access via internal 16-bit bus • 28 interrupt sources • Automatic transfer of register data • A/D converter start trigger can be generated • Module standby mode can be settable • A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible. • AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible. • Dead time compensation counter available in channel 5 • In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped. TIMMTU1A_020020030800 Rev. 4.00 Jul. 25, 2008 Page 151 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.1 Item Count clock MTU2 Functions Channel 0 MPφ/1 MPφ/4 MPφ/16 MPφ/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRE_0 TGRC_0 TGRD_0 TGRF_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture Channel 1 MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 TCLKA TCLKB TGRA_1 TGRB_1 — Channel 2 MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 — Channel 3 MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 1 Channel 4 MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D TGR compare match or input capture √ √ √ √ √ √ — √ √ √ Channel 5 MPφ/1 MPφ/4 MPφ/16 MPφ/64 General registers TGRU_5 TGRV_5 TGRW_5 — General registers/ buffer registers I/O pins TIOC1A* 1 TIOC1B* 1 TIOC2A* 1 TIOC2B* TIOC3A TIOC3B TIOC3C TIOC3D TGR compare match or input capture √ √ √ √ √ √ — √ √ √ Input pins TIC5U TIC5V TIC5W TGR compare match or input capture — — — √ — — — — — — Counter clear function TGR compare match or input capture √ √ √ √ √ √ √ — — — TGR compare match or input capture √ √ √ √ √ √ √ — — — Compare 0 output √ match 1 output √ output Toggle √ output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset PWM mode AC synchronous motor drive mode √ √ √ √ — — √ Rev. 4.00 Jul. 25, 2008 Page 152 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Item Phase counting mode Buffer operation Dead time compensation counter function Channel 0 — √ — Channel 1 √ — — Channel 2 √ — — Channel 3 — √ — Channel 4 — √ — Channel 5 — — √ A/D converter start TGRA_0 trigger compare match or input capture TGRE_0 compare match TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TCNT_4 underflow (trough) in complementary PWM mode — Rev. 4.00 Jul. 25, 2008 Page 153 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Item Interrupt sources Channel 0 7 sources • Channel 1 4 sources Compare match or input capture 1A* 2 Channel 2 4 sources • Channel 3 5 sources Channel 4 5 sources Channel 5 3 sources Compare match or input capture 5U Compare match or input capture 5V Compare match or input capture 5W Compare • match or input capture 0A Compare • match or input capture 2A* 2 Compare • match or input capture 3A Compare • match or input capture 3B Compare • match or input capture 4A Compare • match or input capture 4B Compare • match or input capture 4C Compare match or input capture 4D • Compare • match or input capture 0B Compare match or input capture 1B* 2 • Compare • match or input capture 2B* 2 • Compare • match or input capture 0C • Overflow • Overflow Underflow • Compare • match or input capture 3C Underflow • • Compare match or input capture 0D • Compare • match or input capture 3D • • • Compare match 0E Compare match 0F Overflow • Overflow • Overflow or underflow Rev. 4.00 Jul. 25, 2008 Page 154 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 — Channel 2 — Channel 3 — Channel 4 • A/D converter start request at a match between TADCOR A_4 and TCNT_4 • A/D converter start request at a match between TADCOR B_4 and TCNT_4 Channel 5 — A/D converter start — request delaying function Interrupt skipping function — — — • Skips TGRA_3 compare match interrupts • Skips TCIV_4 interrupts — [Legend] √: Possible —: Not possible Notes: 1. This pin is supported only by the SH7125. 2. Input capture is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 155 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.1 shows a block diagram of the MTU2. TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Control logic for channels 3 and 4 Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 TIORH TIORL TMDR Channel 4 TSR TIER TCR TIORH TOCR TGCR TIER TCR TCNTS TCDR Channel 2 TGRA TGRB TCNT Clock input Internal clock: MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 External clock: TCLKA TCLKB TCLKC TCLKD Control logic for channels 0 to 2 Module data bus Input pins Channel 5: TIC5U TIC5V TIC5W Channel 5 TOER TDDR TCNTW TCBR TGRC TGRD TGRA TGRB TCNT Channel 5: TGIU_5 TGIV_5 TGIW_5 TCNTU TCNTV TGRW TGRU TGRV TIOR TIER TCR TSR Control logic Common TSYR Internal data bus BUS I/F TMDR TSR A/D conversion start signals Channels 0 to 4: TRGAN Channel 0: TRG0N Channel 4: TRG4AN TRG4BN TSTR TIORL TMDR Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A * TIOC1B * Channel 2: TIOC2A * TIOC2B * TIORH Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2 TIOR TMDR Channel 1 TSR TIER TCR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TCNT TGRD TGRA TGRB TGRE [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter Note: * Supported only by the SH7125. TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: TGRU: TGRV: TGRW: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer general register U Timer general register V Timer general register W Figure 9.1 Block Diagram of MTU2 Rev. 4.00 Jul. 25, 2008 Page 156 of 750 REJ09B0243-0400 TIER TCR TGRF TCNT Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.2 Table 9.2 Channel Input/Output Pins Pin Configuration Pin Name I/O Function Common TCLKA TCLKB TCLKC TCLKD 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 TIOC1A* TIOC1B* 2 TIOC2A* TIOC2B* 3 TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D 5 TIC5U TIC5V TIC5W Note: * Input External clock A input pin (Channel 1 phase counting mode A phase input) Input External clock B input pin (Channel 1 phase counting mode B phase input) Input External clock C input pin (Channel 2 phase counting mode A phase input) Input External clock D input pin (Channel 2 phase counting mode B phase input) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin Input TGRU_5 input capture input/external pulse input pin Input TGRV_5 input capture input/external pulse input pin Input TGRW_5 input capture input/external pulse input pin Supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 157 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3 Register Descriptions The MTU2 has the following registers. For details on register addresses and register states during each process, see section 20, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 9.3 Register Configuration Abbreviation TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'C0 H'80 H'00 H'00 H'0000 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF Address H'FFFFC200 H'FFFFC201 H'FFFFC202 H'FFFFC203 H'FFFFC204 H'FFFFC205 H'FFFFC206 H'FFFFC207 H'FFFFC208 H'FFFFC209 H'FFFFC20A H'FFFFC20D H'FFFFC20E H'FFFFC20F H'FFFFC210 H'FFFFC212 H'FFFFC214 H'FFFFC216 H'FFFFC218 H'FFFFC21A H'FFFFC21C H'FFFFC21E Access Size 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8 8 8 8, 16 8 16, 32 16 16, 32 16 16, 32 16 16, 32 16 Register Name Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_3 Timer interrupt enable register_4 Timer output master enable register Timer gate control register Timer output control register 1 Timer output control register 2 Timer counter_3 Timer counter_4 Timer cycle data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Rev. 4.00 Jul. 25, 2008 Page 158 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Register Name Timer subcounter Timer cycle buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 Timer interrupt skipping set register Timer interrupt skipping counter Timer buffer transfer set register Timer dead time enable register Timer output level buffer register Abbreviation TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TITCR TITCNT TBTER TDER TOLBR R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF H'C0 H'C0 H'00 H'00 H'00 H'01 H'00 H'00 H'00 H'0000 H'FFFF H'FFFF H'FFFF Address H'FFFFC220 H'FFFFC222 H'FFFFC224 H'FFFFC226 H'FFFFC228 H'FFFFC22A H'FFFFC22C H'FFFFC22D H'FFFFC230 H'FFFFC231 H'FFFFC232 H'FFFFC234 H'FFFFC236 H'FFFFC238 H'FFFFC239 H'FFFFC240 H'FFFFC244 H'FFFFC246 H'FFFFC248 Access Size 16, 32 16 16, 32 16 16, 32 16 8, 16 8 8, 16 8 8 8 8 8, 16 8 16 16, 32 16 16, 32 Timer buffer operation transfer TBTM_3 mode register_3 Timer buffer operation transfer TBTM_4 mode register_4 Timer A/D converter start request control register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4 TADCR TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 R/W H'FFFF H'FFFFC24A 16 Rev. 4.00 Jul. 25, 2008 Page 159 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Register Name Timer waveform control register Timer start register Timer synchronous register Timer read/write enable register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer general register E_0 Timer general register F_0 Timer interrupt enable register 2_0 Timer status register 2_0 Abbreviation TWCR TSTR TSYR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'00 H'00 H'00 H'01 H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'00 H'00 H'00 H'00 H'C0 Address H'FFFFC260 H'FFFFC280 H'FFFFC281 H'FFFFC284 H'FFFFC300 H'FFFFC301 H'FFFFC302 H'FFFFC303 H'FFFFC304 H'FFFFC305 H'FFFFC306 H'FFFFC308 H'FFFFC30A H'FFFFC30C H'FFFFC30E H'FFFFC320 H'FFFFC322 H'FFFFC324 H'FFFFC325 H'FFFFC326 H'FFFFC380 H'FFFFC381 H'FFFFC382 H'FFFFC384 H'FFFFC385 Access Size 8 8, 16 8 8 8, 16, 32 8 8, 16 8 8, 16, 32 8 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 8 8, 16 8 8 8, 16, 32 8 Timer buffer operation transfer TBTM_0 mode register_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 Rev. 4.00 Jul. 25, 2008 Page 160 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Register Name Timer counter_1 Timer general register A_1 Timer general register B_1 Timer input capture control register Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer counter U_5 Timer general register U_5 Timer control register U_5 Timer I/O control register U_5 Timer counter V_5 Timer general register V_5 Timer control register V_5 Timer I/O control register V_5 Timer counter W_5 Timer general register W_5 Timer control register W_5 Timer I/O control register W_5 Timer status register_5 Timer interrupt enable register_5 Timer start register_5 Timer compare match clear register Abbreviation TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 TIORV_5 TCNTW_5 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 TCNTCMPCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value H'0000 H'FFFF H'FFFF H'00 H'00 H'00 H'00 H'00 H'C0 H'0000 H'FFFF H'FFFF H'0000 H'FFFF H'00 H'00 H'0000 H'FFFF H'00 H'00 H'0000 H'FFFF H'00 H'00 H'00 H'00 H'00 H'00 Address H'FFFFC386 H'FFFFC388 H'FFFFC38A H'FFFFC390 H'FFFFC400 H'FFFFC401 H'FFFFC402 H'FFFFC404 H'FFFFC405 H'FFFFC406 H'FFFFC408 H'FFFFC40A H'FFFFC480 H'FFFFC482 H'FFFFC484 H'FFFFC486 H'FFFFC490 H'FFFFC492 H'FFFFC494 H'FFFFC496 H'FFFFC4A0 H'FFFFC4A2 H'FFFFC4A4 H'FFFFC4A6 H'FFFFC4B0 H'FFFFC4B2 H'FFFFC4B4 H'FFFFC4B6 Access Size 16 16, 32 16 8 8, 16 8 8 8, 16, 32 8 16 16, 32 16 16, 32 16 8 8 16, 32 16 8 8 16, 32 16 8 8 8 8 8 8 Rev. 4.00 Jul. 25, 2008 Page 161 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped. Bit: 7 6 CCLR[2:0] 5 4 3 2 1 TPSC[2:0] 0 CKEG[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 5 Bit Name CCLR[2:0] Initial Value 000 R/W R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 9.4 and 9.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. MPφ/4 both edges = MPφ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is MPφ/4 or slower. When MPφ/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 9.6 to 9.10 for details. [Legend] x: Don't care Rev. 4.00 Jul. 25, 2008 Page 162 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.4 Channel 0, 3, 4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 0 0 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 9.5 Channel 1, 2 CCLR0 to CCLR2 (Channels 1 and 2) Bit 6 Bit 7 2 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Rev. 4.00 Jul. 25, 2008 Page 163 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.6 Channel 0 TPSC0 to TPSC2 (Channel 0) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 9.7 Channel 1 TPSC0 to TPSC2 (Channel 1) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on MPφ/256 Counts on TCNT_2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 4.00 Jul. 25, 2008 Page 164 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.8 Channel 2 TPSC0 to TPSC2 (Channel 2) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on MPφ/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 9.9 Channel 3, 4 TPSC0 to TPSC2 (Channels 3 and 4) Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 Internal clock: counts on MPφ/256 Internal clock: counts on MPφ/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Rev. 4.00 Jul. 25, 2008 Page 165 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.10 TPSC1 and TPSC0 (Channel 5) Channel 5 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value should always be 0. 9.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: 7 - 6 BFE 5 BFB 4 BFA 3 2 1 0 MD[3:0] Initial value: R/W: 0 - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name — Initial Value 0 R/W — Description Reserved This bit is always read as 0. The write value should always be 0. 6 BFE 0 R/W Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. When TGRF is used as a buffer register, TGRF compare match is generated. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation Rev. 4.00 Jul. 25, 2008 Page 166 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name BFB Initial Value 0 R/W R/W Description Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode. Since the TGFD flag will be set if a compare match occurs during Tb interval in complementary PWM mode, the TGIED bit in timer interrupt enable register 3/4 (TIER_3/4) should be cleared to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode. Since the TGFD flag will be set if a compare match occurs during Tb interval in complementary PWM mode, the TGIED bit in timer interrupt enable register 3/4 (TIER_3/4) should be cleared to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 9.11 for details. Rev. 4.00 Jul. 25, 2008 Page 167 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 0 x 0 1 1 0 1 Description Normal operation Setting prohibited PWM mode 1 PWM mode 2*1 Phase counting mode 1*2 Phase counting mode 2*2 Phase counting mode 3*2 Phase counting mode 4*2 Reset synchronous PWM mode* Setting prohibited Setting prohibited Setting prohibited Complementary PWM mode 1 (transmit at crest)*3 Complementary PWM mode 2 (transmit at trough)*3 Complementary PWM mode 2 (transmit at crest and trough)*3 3 [Legend] x: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode and complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2. Rev. 4.00 Jul. 25, 2008 Page 168 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR is set when the setting of TMDR is in normal operation, PWM mode, and phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. • TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: 7 6 5 4 3 2 1 0 IOB[3:0] IOA[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 4 Bit Name IOB[3:0] Initial Value 0000 R/W R/W Description I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 9.12 Table 9.14 Table 9.15 Table 9.16 Table 9.18 3 to 0 IOA[3:0] 0000 R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 9.20 Table 9.22 Table 9.23 Table 9.24 Table 9.26 Rev. 4.00 Jul. 25, 2008 Page 169 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TIORL_0, TIORL_3, TIORL_4 Bit: 7 6 5 4 3 2 1 0 IOD[3:0] IOC[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 4 Bit Name IOD[3:0] Initial Value 0000 R/W R/W Description I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 9.13 TIORL_3: Table 9.17 TIORL_4: Table 9.19 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 9.21 TIORL_3: Table 9.25 TIORL_4: Table 9.27 • TIORU_5, TIORV_5, TIORW_5 Bit name: 7 - 6 - 5 - 4 3 2 IOC[4:0] 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 5 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 9.28. Rev. 4.00 Jul. 25, 2008 Page 170 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.12 TIORH_0 (Channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x TGRB_0 Function Output compare register TIOC0B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 4.00 Jul. 25, 2008 Page 171 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.13 TIORL_0 (Channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x TGRD_0 Function Output compare register*2 TIOC0D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Jul. 25, 2008 Page 172 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.14 TIOR_1 (Channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x TGRB_1 Function Output compare register TIOC1B Pin Function*2 Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC1B pin input/output function is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 173 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.15 TIOR_2 (Channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRB_2 Function Output compare register TIOC2B Pin Function*2 Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC2B pin input/output function is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 174 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.16 TIORH_3 (Channel 3) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRB_3 Function Output compare register TIOC3B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 4.00 Jul. 25, 2008 Page 175 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.17 TIORL_3 (Channel 3) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRD_3 Function Output compare 2 register* TIOC3D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Jul. 25, 2008 Page 176 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.18 TIORH_4 (Channel 4) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRB_4 Function Output compare register TIOC4B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 4.00 Jul. 25, 2008 Page 177 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.19 TIORL_4 (Channel 4) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRD_4 Function Output compare 2 register* TIOC4D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Jul. 25, 2008 Page 178 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.20 TIORH_0 (Channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x TGRA_0 Function Output compare register TIOC0A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 4.00 Jul. 25, 2008 Page 179 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.21 TIORL_0 (Channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x TGRC_0 Function Output compare 2 register* TIOC0C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge 2 register* Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Jul. 25, 2008 Page 180 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.22 TIOR_1 (Channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 x x x TGRA_1 Function Output compare register TIOC1A Pin Function*2 Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC1A pin input/output function is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 181 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.23 TIOR_2 (Channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRA_2 Function Output compare register TIOC2A Pin Function*2 Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. The TIOC2A pin input/output function is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 182 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.24 TIORH_3 (Channel 3) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRA_3 Function Output compare register TIOC3A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 4.00 Jul. 25, 2008 Page 183 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.25 TIORL_3 (Channel 3) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRC_3 Function Output compare 2 register* TIOC3C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Jul. 25, 2008 Page 184 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.26 TIORH_4 (Channel 4) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRA_4 Function Output compare register TIOC4A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register Input capture at falling edge Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Rev. 4.00 Jul. 25, 2008 Page 185 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.27 TIORL_4 (Channel 4) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 x TGRC_4 Function Output compare 2 register* TIOC4C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output retained Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Input capture at rising edge register*2 Input capture at falling edge Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Jul. 25, 2008 Page 186 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) Description TGRU_5, TGRV_5, and TGRW_5 Function TIC5U, TIC5V, and TIC5W Pin Function Compare Compare match match register Setting prohibited Setting prohibited Setting prohibited Setting prohibited Input capture register Setting prohibited Input capture at rising edge Input capture at falling edge Input capture at both edges Setting prohibited Setting prohibited Measurement of low pulse width of external input signal Capture at trough in complementary PWM mode 1 0 Measurement of low pulse width of external input signal Capture at crest in complementary PWM mode 1 Measurement of low pulse width of external input signal Capture at crest and trough in complementary PWM mode 1 0 0 1 Setting prohibited Measurement of high pulse width of external input signal Capture at trough in complementary PWM mode 1 0 Measurement of high pulse width of external input signal Capture at crest in complementary PWM mode 1 Measurement of high pulse width of external input signal Capture at crest and trough in complementary PWM mode Bit 4 IOC4 0 Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 1 1 1 0 x 0 x x 0 x x x 0 1 1 0 1 1 1 0 x 0 x 0 1 [Legend] x: Don't care Rev. 4.00 Jul. 25, 2008 Page 187 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 CMP CMP CMP CLR5U CLR5V CLR5W Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CMPCLR5U 0 R/W TCNT Compare Clear 5U Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1 CMPCLR5V 0 R/W TCNT Compare Clear 5V Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture Rev. 4.00 Jul. 25, 2008 Page 188 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name Initial Value R/W R/W Description TCNT Compare Clear 5W Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture CMPCLR5W 0 9.3.5 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5. • TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 Bit: 7 6 5 4 3 2 1 0 TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name TTGE Initial Value 0 R/W R/W Description A/D Converter Start Request Enable Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled Rev. 4.00 Jul. 25, 2008 Page 189 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 6 Bit Name TTGE2 Initial Value 0 R/W R/W Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 4.00 Jul. 25, 2008 Page 190 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 Bit Name TGIEC Initial Value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 4.00 Jul. 25, 2008 Page 191 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TIER2_0 Bit: 7 TTGE2 6 - 5 - 4 - 3 - 2 - 1 0 TGIEF TGIEE Initial value: 0 R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 7 Bit Name TTGE2 Initial Value 0 R/W R/W Description A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGIEF 0 R/W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled 0 TGIEE 0 R/W TGR Interrupt Enable E Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled Rev. 4.00 Jul. 25, 2008 Page 192 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TIER_5 Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 TGIE5U TGIE5V TGIE5W Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 TGIE5U 0 R/W TGR Interrupt Enable 5U Enables or disables interrupt requests (TGIU_5) issued when the CMFU5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled 1 TGIE5V 0 R/W TGR Interrupt Enable 5V Enables or disables interrupt requests (TGIV_5) issued when the CMFV5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled 0 TGIE5W 0 R/W TGR Interrupt Enable 5W Enables or disables interrupt requests (TGIW_5) issued when the CMFW5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled Rev. 4.00 Jul. 25, 2008 Page 193 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.6 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5. • TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: 7 TCFD 6 - 5 TCFU 4 TCFV 3 TGFD 2 TGFC 1 TGFB 0 TGFA Initial value: R/W: 1 R 1 R 0 0 0 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7 Bit Name TCFD Initial Value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 R/(W)*1 Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Setting condition] • When the TCNT value underflows (changes from H'0000 to H'FFFF) When 0 is written to TCFU after reading TCFU = 1* 2 [Clearing condition] • Rev. 4.00 Jul. 25, 2008 Page 194 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 4 Bit Name TCFV Initial Value 0 R/W 1 Description R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] • When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. When 0 is written to TCFV after reading TCFV = 2 1* [Clearing condition] • 3 TGFD 0 R/(W)*1 Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions] • • When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When 0 is written to TGFD after reading TGFD = 2 1* [Clearing condition] • Rev. 4.00 Jul. 25, 2008 Page 195 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 Bit Name TGFC Initial Value 0 R/W 1 Description R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions] • • When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When 0 is written to TGFC after reading TGFC = 2 1* [Clearing condition] • 1 TGFB 0 R/(W)*1 Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] • • When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When 0 is written to TGFB after reading TGFB = 2 1* [Clearing condition] • Rev. 4.00 Jul. 25, 2008 Page 196 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name TGFA Initial Value 0 R/W 1 Description R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] • • When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When 0 is written to TGFA after reading TGFA = 2 1* [Clearing condition] • Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it. Rev. 4.00 Jul. 25, 2008 Page 197 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TSR2_0 Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 TGFF 0 TGFE Initial value: R/W: 1 R 1 R 0 R 0 R 0 R 0 R 0 0 R/(W)*1 R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7, 6 Bit Name — Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGFF 0 R/(W)*1 Compare Match Flag F Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Setting condition] • When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register When 0 is written to TGFF after reading TGFF = 2 1* [Clearing condition] • 0 TGFE 0 R/(W)*1 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Setting condition] • When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register When 0 is written to TGFE after reading TGFE = 2 1* [Clearing condition] • Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it. Rev. 4.00 Jul. 25, 2008 Page 198 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TSR_5 Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 CMFU5 CMFV5 CMFW5 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)*1 R/(W)*1 R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7 to 3 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CMFU5 0 R/(W)*1 Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. [Setting conditions] • • When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control 2 register U_5 (TIORU_5)* When 0 is written to CMFU5 after reading CMFU5 = 1 • [Clearing condition] • Rev. 4.00 Jul. 25, 2008 Page 199 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 1 Bit Name CMFV5 Initial Value 0 R/W 1 Description R/(W)* Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Setting conditions] • • When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control 2 register V_5 (TIORV_5)* When 0 is written to CMFV5 after reading CMFV5 = 1 • [Clearing condition] • Rev. 4.00 Jul. 25, 2008 Page 200 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name CMFW5 Initial Value 0 R/W 1 Description R/(W)* Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Setting conditions] • • When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register When TCNTW_5 value is transferred to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O 2 control register W_5 (TIORW_5)* When 0 is written to CMFW5 after reading CMFW5 = 1 • [Clearing condition] • Notes: 1 Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. The transfer timing is specified by the IOC bit in the timer I/O control register U_5/V_5/W_5 (TIORU_5, TIORV_5, TIORW_5). Rev. 4.00 Jul. 25, 2008 Page 201 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.7 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4. Bit: 7 - 6 - 5 - 4 - 3 - 2 TTSE 1 TTSB 0 TTSA Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 TTSE 0 R/W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared 1 TTSB 0 R/W Timing Select B Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel Rev. 4.00 Jul. 25, 2008 Page 202 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name TTSA Initial Value 0 R/W R/W Description Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel 9.3.8 Timer Input Capture Control Register (TICCR) TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1. Bit: 7 - 6 - 5 - 4 - 3 I2BE 2 I2AE 1 I1BE 0 I1AE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 4 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 I2BE 0 R/W Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions Rev. 4.00 Jul. 25, 2008 Page 203 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 Bit Name I2AE Initial Value 0 R/W R/W Description Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions 1 I1BE 0 R/W Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions 0 I1AE 0 R/W Input Capture Enable Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions Note: This function is supported only by the SH7125. In the SH7124, write value should always be H'00. Rev. 4.00 Jul. 25, 2008 Page 204 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.9 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4. Bit: 15 14 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 BF[1:0] UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0* R/W 0 R/W 0* R/W 0* R/W 0* R/W 0* R/W 0* R/W Note: * Do not set to 1 when complementary PWM mode is not selected. Bit 15, 14 Bit Name BF[1:0] Initial Value 00 R/W R/W Description TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 9.29. 13 to 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 UT4AE 0 R/W Up-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation 6 DT4AE 0* R/W Down-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation Rev. 4.00 Jul. 25, 2008 Page 205 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name UT4BE Initial Value 0 R/W R/W Description Up-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation 4 DT4BE 0* R/W Down-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation 3 ITA3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping 2 ITA4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping 1 ITB3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping Rev. 4.00 Jul. 25, 2008 Page 206 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name ITB4VE Initial Value 0* R/W R/W Description TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 9.29 Setting of Transfer Timing by BF1 and BF0 Bits Bit 7 BF1 0 0 1 1 Bit 6 BF0 0 1 0 1 Description Does not transfer data from the cycle set buffer register to the cycle set register. Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.*1 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.*2 Transfers data from the cycle set buffer register to the cycle set 2 register at the crest and trough of the TCNT_4 count.* Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected. Rev. 4.00 Jul. 25, 2008 Page 207 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. 9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. Rev. 4.00 Jul. 25, 2008 Page 208 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.12 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R/W Note: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. 9.3.13 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF. Rev. 4.00 Jul. 25, 2008 Page 209 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.14 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. • TSTR Bit: 7 CST4 6 CST3 5 - 4 - 3 - 2 CST2 1 CST1 0 CST0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 6 Bit Name CST4 CST3 Initial Value 0 0 R/W R/W R/W Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 210 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 1 0 Bit Name CST2 CST1 CST0 Initial Value 0 0 0 R/W R/W R/W R/W Description Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation • TSTR_5 Bit: 7 - 6 - 5 - 4 - 3 - 2 1 0 CSTU5 CSTV5 CSTW5 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 to 3 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 2 CSTU5 0 R/W Counter Start U5 Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation 1 CSTV5 0 R/W Counter Start V5 Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation 0 CSTW5 0 R/W Counter Start W5 Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation Rev. 4.00 Jul. 25, 2008 Page 211 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.15 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: 7 6 5 - 4 - 3 - 2 1 0 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 6 Bit Name SYNC4 SYNC3 Initial Value 0 0 R/W R/W R/W Description Timer Synchronous operation 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 212 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 1 0 Bit Name SYNC2 SYNC1 SYNC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Timer Synchronous operation 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Rev. 4.00 Jul. 25, 2008 Page 213 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.16 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 RWE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W Bit 7 to 1 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RWE 1 R/W Read/Write Enable Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition] • When 0 is written to the RWE bit after reading RWE = 1 • Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT_4. Rev. 4.00 Jul. 25, 2008 Page 214 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.17 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of channel 3 and channel 4 prior to setting TIOR of channel 3 and channel 4. Bit: 7 - 6 - 5 OE4D 4 OE4C 3 OE3D 2 OE4B 1 OE4A 0 OE3B Initial value: R/W: 1 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7, 6 Bit Name — Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Rev. 4.00 Jul. 25, 2008 Page 215 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name OE3B Initial Value 0 R/W R/W Description Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 9.3.18, Timer Output Control Register 1 (TOCR1), and section 9.3.19, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or resetsynchronized PWM mode. When these bits are set to 0, low level is output. 9.3.18 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: 7 - 6 PSYE 5 - 4 - 3 TOCL 2 TOCS 1 OLSN 0 OLSP Initial value: R/W: 0 R 0 R/W 0 R 0 R 0 0 R/(W)* R/W 0 R/W 0 R/W Note: * This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit. Bit 7 Bit Name — Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 216 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 3 Bit Name TOCL Initial Value 0 R/W 1 Description 2 R/(W)* TOC Register Write Protection* This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled 2 TOCS 0 R/W TOC Select This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected 1 OLSN 0 R/W Output Level Select N*3 This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 9.30. 0 OLSP 0 R/W Output Level Select P*3 This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 9.31. Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be written to the bit. 2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 3. Clearing the TOCS bit to 0 makes this bit setting valid. Table 9.30 Output Level Select Function Bit 1 Function Compare Match Output OLSN 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Rev. 4.00 Jul. 25, 2008 Page 217 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level Figure 9.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1 and OLSP = 1. TCNT_3 and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Time Positive phase output Reverse phase output Figure 9.2 Complementary PWM Mode Output Level Example Rev. 4.00 Jul. 25, 2008 Page 218 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.19 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 6 BF[1:0] 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7, 6 Bit Name BF[1:0] Initial value 00 R/W R/W Description TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 9.32. 5 OLS3N 0 R/W Output Level Select 3N* This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode. See table 9.33. 4 OLS3P 0 R/W Output Level Select 3P* This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode. See table 9.34. 3 OLS2N 0 R/W Output Level Select 2N* This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode. See table 9.35. 2 OLS2P 0 R/W Output Level Select 2P* This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode. See table 9.36. 1 OLS1N 0 R/W Output Level Select 1N* This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode. See table 9.37. Rev. 4.00 Jul. 25, 2008 Page 219 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name OLS1P Initial value 0 R/W R/W Description Output Level Select 1P* This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode. See table 9.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 9.32 Setting of Bits BF1 and BF0 Bit 7 BF1 0 0 Bit 6 BF0 0 1 Complementary PWM Mode Description Reset-Synchronized PWM Mode Does not transfer data from the Does not transfer data from the buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2. Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared Setting prohibited 1 0 1 1 Setting prohibited Table 9.33 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Rev. 4.00 Jul. 25, 2008 Page 220 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level Table 9.35 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 9.36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level Table 9.37 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N 0 1 Initial Output High level Low level Active Level Low level High level Up Count High level Low level Down Count Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Rev. 4.00 Jul. 25, 2008 Page 221 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.38 TIOC3B Output Level Select Function Bit 0 Function Compare Match Output OLS1P 0 1 Initial Output High level Low level Active Level Low level High level Up Count Low level High level Down Count High level Low level 9.3.20 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 - 6 - 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7, 6 Bit Name — Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2. Specifies the buffer value to be transferred to the OLS3P bit in TOCR2. Specifies the buffer value to be transferred to the OLS2N bit in TOCR2. Specifies the buffer value to be transferred to the OLS2P bit in TOCR2. Specifies the buffer value to be transferred to the OLS1N bit in TOCR2. Specifies the buffer value to be transferred to the OLS1P bit in TOCR2. Rev. 4.00 Jul. 25, 2008 Page 222 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS [1] [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. Set TOCR2 [2] [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Set TOLBR [3] Figure 9.3 PWM Output Level Setting Procedure in Buffer Operation 9.3.21 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit: 7 - 6 BDC 5 N 4 P 3 FB 2 WF 1 VF 0 UF Initial value: R/W: 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name — Initial value 1 R/W R Description Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective Rev. 4.00 Jul. 25, 2008 Page 223 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 5 Bit Name N Initial value 0 R/W R/W Description Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings). 2 1 0 WF VF UF 0 0 0 R/W R/W R/W Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 9.39. Rev. 4.00 Jul. 25, 2008 Page 224 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.39 Output level Select Function Function Bit 2 WF 0 Bit 1 VF 0 Bit 0 UF 0 1 1 0 1 1 0 0 1 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B TIOC3D TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF W Phase U Phase OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF 9.3.22 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R Note: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. Rev. 4.00 Jul. 25, 2008 Page 225 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.23 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 9.3.24 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. Rev. 4.00 Jul. 25, 2008 Page 226 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.25 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W Note: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 9.3.26 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR. Bit: 7 T3AEN 6 5 3ACOR[2:0] 4 3 T4VEN 2 1 4VCOR[2:0] 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name T3AEN Initial value 0 R/W R/W Description T3AEN Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 9.40. T4VEN Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled 3 T4VEN 0 R/W Rev. 4.00 Jul. 25, 2008 Page 227 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 2 to 0 Bit Name Initial value R/W R/W Description These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 9.41. 4VCOR[2:0] 000 Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TITCNT). Table 9.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 3ACOR2 0 0 0 0 1 1 1 1 Bit 5 3ACOR1 0 0 1 1 0 0 1 1 Bit 4 3ACOR0 0 1 0 1 0 1 0 1 Description Does not skip TGIA_3 interrupts. Sets the TGIA_3 interrupt skipping count to 1. Sets the TGIA_3 interrupt skipping count to 2. Sets the TGIA_3 interrupt skipping count to 3. Sets the TGIA_3 interrupt skipping count to 4. Sets the TGIA_3 interrupt skipping count to 5. Sets the TGIA_3 interrupt skipping count to 6. Sets the TGIA_3 interrupt skipping count to 7. Table 9.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 4VCOR2 0 0 0 0 1 1 1 1 Bit 1 4VCOR1 0 0 1 1 0 0 1 1 Bit 0 4VCOR0 0 1 0 1 0 1 0 1 Description Does not skip TCIV_4 interrupts. Sets the TCIV_4 interrupt skipping count to 1. Sets the TCIV_4 interrupt skipping count to 2. Sets the TCIV_4 interrupt skipping count to 3. Sets the TCIV_4 interrupt skipping count to 4. Sets the TCIV_4 interrupt skipping count to 5. Sets the TCIV_4 interrupt skipping count to 6. Sets the TCIV_4 interrupt skipping count to 7. Rev. 4.00 Jul. 25, 2008 Page 228 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.27 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. Bit: 7 - 6 5 3ACNT[2:0] 4 3 - 2 1 4VCNT[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 7 6 to 4 Bit Name — 3ACNT[2:0] Initial Value 0 000 R/W R R Description Reserved This bit is always read as 0. TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions] • • • When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR When the T3AEN bit in TITCR is cleared to 0 When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 2 to 0 — 4VCNT[2:0] 0 000 R R Reserved This bit is always read as 0. TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions] • • • When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR When the T4VEN bit in TITCR is cleared to 0 When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Rev. 4.00 Jul. 25, 2008 Page 229 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.28 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 0 BTE[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 7 to 2 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 9.42. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR Rev. 4.00 Jul. 25, 2008 Page 230 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.42 Setting of Bits BTE1 and BTE0 Bit 1 BTE1 0 0 1 1 Bit 0 BTE0 0 1 0 1 Description Enables transfer from the buffer registers to the temporary registers*1 and does not link the transfer with interrupt skipping operation. Disables transfer from the buffer registers to the temporary registers. Links transfer from the buffer registers to the temporary registers with interrupt skipping operation.*2 Setting prohibited Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 9.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed. Rev. 4.00 Jul. 25, 2008 Page 231 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.29 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 TDER Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W) Bit 7 to 1 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TDER 1 R/(W) Dead Time Enable Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition] • When 0 is written to TDER after reading TDER = 1 Note: * TDDR must be set to 1 or a larger value. Rev. 4.00 Jul. 25, 2008 Page 232 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.30 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: 7 CCE 6 - 5 - 4 - 3 - 2 - 1 - 0 WRE Initial value: 0* R/W: R/(W) 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W) Note: * Do not set to 1 when complementary PWM mode is not selected. Bit 7 Bit Name CCE Initial Value 0* R/W R/(W) Description Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition] • When 1 is written to CCE after reading CCE = 0 6 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 233 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit 0 Bit Name WRE Initial Value 0 R/W R/(W) Description Waveform Retain Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The output waveform is retained only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 9.40. 0: Outputs the initial value specified in TOCR 1: Retains the waveform output immediately before synchronous clearing [Setting condition] • When 1 is written to WRE after reading WRE = 0 Note: * Do not set to 1 when complementary PWM mode is not selected. 9.3.31 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. Rev. 4.00 Jul. 25, 2008 Page 234 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4 9.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). Counter Operation: When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of Count Operation Setting Procedure Figure 9.4 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Operation selection Select counter clock [1] Periodic counter Select counter clearing source Select output compare register Set period [2] [3] [4] Start count operation [5] Figure 9.4 Example of Counter Operation Setting Procedure Rev. 4.00 Jul. 25, 2008 Page 235 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU2’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU2 requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 9.5 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 9.5 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the MTU2 requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Rev. 4.00 Jul. 25, 2008 Page 236 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.6 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software TGF Figure 9.6 Periodic Counter Operation Waveform Output by Compare Match: The MTU2 can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of Setting Procedure for Waveform Output by Compare Match Figure 9.7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 9.7 Example of Setting Procedure for Waveform Output by Compare Match Rev. 4.00 Jul. 25, 2008 Page 237 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Examples of Waveform Output Operation: Figure 9.8 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB No change No change Time No change No change 1 output 0 output Figure 9.8 Example of 0 Output/1 Output Operation Figure 9.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle output Toggle output Figure 9.9 Example of Toggle Output Operation Rev. 4.00 Jul. 25, 2008 Page 238 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, MPφ/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if MPφ/1 is selected. 1. Example of Input Capture Operation Setting Procedure Figure 9.10 shows an example of the input capture operation setting procedure. [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Input selection Select input capture input [1] Start count [2] Figure 9.10 Example of Input Capture Operation Setting Procedure Rev. 4.00 Jul. 25, 2008 Page 239 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Example of Input Capture Operation: Figure 9.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 9.11 Example of Input Capture Operation Rev. 4.00 Jul. 25, 2008 Page 240 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 9.12 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 9.12 Example of Synchronous Operation Setting Procedure Rev. 4.00 Jul. 25, 2008 Page 241 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Synchronous Operation in SH7125: Figure 9.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 9.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOC0A TIOC1A TIOC2A Time Figure 9.13 Example of Synchronous Operation Rev. 4.00 Jul. 25, 2008 Page 242 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 9.43 shows the register combinations used in buffer operation. Table 9.43 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 TGRE_0 3 TGRA_3 TGRB_3 4 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRF_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.14. Compare match signal Buffer register Timer general register Comparator TCNT Figure 9.14 Compare Match Buffer Operation Rev. 4.00 Jul. 25, 2008 Page 243 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9.15. Input capture signal Buffer register Timer general register TCNT Figure 9.15 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 9.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Buffer operation Select TGR function Start count [3] Figure 9.16 Example of Buffer Operation Setting Procedure Rev. 4.00 Jul. 25, 2008 Page 244 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 9.17 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. In this example, the TTSA bit in TBTM is cleared to 0. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 9.4.5, PWM Modes. TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 9.17 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 9.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 4.00 Jul. 25, 2008 Page 245 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'0532 H'09FB H'0F07 TGRC Figure 9.18 Example of Buffer Operation (2) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation: The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer timing is one of the following cases. • When TCNT overflows (H'FFFF to H'0000) • When H'0000 is written to TCNT during counting • When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note: TBTM must be modified only while TCNT stops. Figure 9.19 shows an operation example in which PWM mode 1 is designated for channel 0 and buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. The TTSA bit in TBTM_0 is set to 1. Rev. 4.00 Jul. 25, 2008 Page 246 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value TGRB_0 H'0450 TGRA_0 H'0000 H'0200 Time H'0520 TGRC_0 H'0200 H'0450 Transfer H'0520 TGRA_0 H'0200 H'0450 H'0520 TIOCA Figure 9.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing 9.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 9.44 Cascaded Combinations Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 9.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection. Rev. 4.00 Jul. 25, 2008 Page 247 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.45 shows the TICCR setting and input capture input pins. Table 9.45 TICCR Setting and Input Capture Input Pins Target Input Capture Input capture from TCNT_1 to TGRA_1 Input capture from TCNT_1 to TGRB_1 Input capture from TCNT_2 to TGRA_2 Input capture from TCNT_2 to TGRB_2 TICCR Setting I2AE bit = 0 (initial value) I2AE bit = 1 I2BE bit = 0 (initial value) I2BE bit = 1 I1AE bit = 0 (initial value) I1AE bit = 1 I1BE bit = 0 (initial value) I1BE bit = 1 Input Capture Input Pins TIOC1A TIOC1A, TIOC2A TIOC1B TIOC1B, TIOC2B TIOC2A TIOC2A, TIOC1A TIOC2B TIOC2B, TIOC1B Example of Cascaded Operation Setting Procedure: Figure 9.20 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Cascaded operation Set cascading Start count [2] Figure 9.20 Cascaded Operation Setting Procedure Cascaded Operation Example (a): Figure 9.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. Rev. 4.00 Jul. 25, 2008 Page 248 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 9.21 Cascaded Operation Example (a) Cascaded Operation Example (b) in SH7125: Figure 9.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used. TCNT_2 value H'FFFF H'C256 H'6128 H'0000 Time TCNT_1 H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 H'0512 H'0513 TGRA_2 H'C256 As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing. Figure 9.22 Cascaded Operation Example (b) Rev. 4.00 Jul. 25, 2008 Page 249 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Cascaded Operation Example (c) in SH7125: Figure 9.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'FFFF H'C256 H'9192 H'6128 H'2064 H'0000 Time TCNT_1 H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 H'0512 H'0513 H'0514 TGRA_2 H'6128 H'2064 H'C256 H'9192 Figure 9.23 Cascaded Operation Example (c) Cascaded Operation Example (d) in SH7125: Figure 9.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1. Rev. 4.00 Jul. 25, 2008 Page 250 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value TGRA_0 Compare match between TCNT_0 and TGRA_0 H'0000 TCNT_2 value H'FFFF H'D000 Time H'0000 Time TCNT_1 H'0512 H'0513 TIOC1A TIOC2A TGRA_1 H'0513 TGRA_2 H'D000 Figure 9.24 Cascaded Operation Example (d) Rev. 4.00 Jul. 25, 2008 Page 251 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 9.46. Rev. 4.00 Jul. 25, 2008 Page 252 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.46 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A* TIOC1A* TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A* TIOC1B* TIOC2A* TIOC2B* Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Notes: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. * Supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 253 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of PWM Mode Setting Procedure: Figure 9.25 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [3] [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level Set TGR [4] Start count [6] Figure 9.25 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 9.26 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 9.26 Example of PWM Mode Operation (1) Rev. 4.00 Jul. 25, 2008 Page 254 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.27 shows an example of PWM mode 2 operation in the SH7125. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 9.27 Example of PWM Mode Operation (2) Rev. 4.00 Jul. 25, 2008 Page 255 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 9.28 Example of PWM Mode Operation (3) Rev. 4.00 Jul. 25, 2008 Page 256 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 9.47 shows the correspondence between external clock pins and channels. Table 9.47 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 9.29 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 9.29 Example of Phase Counting Mode Setting Procedure Rev. 4.00 Jul. 25, 2008 Page 257 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 9.30 shows an example of phase counting mode 1 operation, and table 9.48 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 9.30 Example of Phase Counting Mode 1 Operation Table 9.48 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 4.00 Jul. 25, 2008 Page 258 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Phase counting mode 2 Figure 9.31 shows an example of phase counting mode 2 operation, and table 9.49 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 9.31 Example of Phase Counting Mode 2 Operation Table 9.49 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 4.00 Jul. 25, 2008 Page 259 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Phase counting mode 3 Figure 9.32 shows an example of phase counting mode 3 operation, and table 9.50 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 9.32 Example of Phase Counting Mode 3 Operation Table 9.50 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 4.00 Jul. 25, 2008 Page 260 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 4. Phase counting mode 4 Figure 9.33 shows an example of phase counting mode 4 operation, and table 9.51 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 9.33 Example of Phase Counting Mode 4 Operation Table 9.51 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 4.00 Jul. 25, 2008 Page 261 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Phase Counting Mode Application Example: Figure 9.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Rev. 4.00 Jul. 25, 2008 Page 262 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 + + - TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 9.34 Phase Counting Mode Application Example Rev. 4.00 Jul. 25, 2008 Page 263 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT_3 functions as an upcounter. Table 9.52 shows the PWM output pins used. Table 9.53 shows the settings of the registers. Table 9.52 Output Pins for Reset-Synchronized PWM Mode Channel 3 Output Pin TIOC3B TIOC3D 4 TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3) Table 9.53 Register Settings for Reset-Synchronized PWM Mode Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Rev. 4.00 Jul. 25, 2008 Page 264 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 9.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. [1] [2] Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. [5] [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X ≤ TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR2, see figure 9.3. [7] Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Reset-synchronized PWM mode Stop counting Select counter clock and counter clear source [2] Brushless DC motor control setting [3] Set TCNT [4] Set TGR PWM cycle output enabling, PWM output level setting [6] Set reset-synchronized PWM mode [7] Enable waveform output [8] PFC setting [9] Start count operation Reset-synchronized PWM mode [10] Figure 9.35 Procedure for Selecting Reset-Synchronized PWM Mode Rev. 4.00 Jul. 25, 2008 Page 265 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Reset-Synchronized PWM Mode Operation: Figure 9.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT_3 and TCNT_4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 9.36 Reset-Synchronized PWM Mode Operation Example (When TOCR’s OLSN = 1 and OLSP = 1) Rev. 4.00 Jul. 25, 2008 Page 266 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval is also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 9.54 shows the PWM output pins used. Table 9.55 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 9.54 Output Pins for Complementary PWM Mode Channel 3 Output Pin TIOC3A TIOC3B TIOC3C TIOC3D Description Toggle output synchronized with PWM period (or I/O port) PWM output pin 1 I/O port* PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) PWM output pin 2 PWM output pin 3 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) 4 TIOC4A TIOC4B TIOC4C TIOC4D Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. Rev. 4.00 Jul. 25, 2008 Page 267 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.55 Register Settings for Complementary PWM Mode Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by TRWER setting* Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Always readable/writable Maskable by TRWER setting* Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Always readable/writable Maskable by TRWER setting* Maskable by TRWER setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register). Rev. 4.00 Jul. 25, 2008 Page 268 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGRA_3 comparematch interrupt TCNT_4 underflow interrupt TGRC_3 TCBR TDDR TGRA_3 TCDR Comparator Output controller Match signal PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE3 Comparator Match signal TGRB_3 TGRA_4 TGRD_3 TGRC_4 TGRD_4 TGRB_4 Temp 2 Temp 3 Temp 1 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 9.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode Rev. 4.00 Jul. 25, 2008 Page 269 of 750 REJ09B0243-0400 Output protection circuit TCNT_3 TCNTS TCNT_4 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 9.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. [1] [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting [2] [3] TCNT setting [4] Inter-channel synchronization setting [5] TGR setting [6] [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 9.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. Enable/disable dead time generation Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting [7] [8] [9] [10] Enable waveform output [11] StartPFC setting count operation [12] Start count operation [13] [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Figure 9.38 Example of Complementary PWM Mode Setting Procedure Rev. 4.00 Jul. 25, 2008 Page 270 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 9.39 illustrates counter operation in complementary PWM mode, and figure 9.40 shows an example of complementary PWM mode operation. 1. Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, downcounting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Time TCNT_3 TCNT_4 TCNTS TCNTS Figure 9.39 Complementary PWM Mode Counter Operation Rev. 4.00 Jul. 25, 2008 Page 271 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 9.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 9.40 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 9.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS—and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly. Rev. 4.00 Jul. 25, 2008 Page 272 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 TGRA_3 Ta Tb1 Ta Tb2 Ta TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 H'6400 H'0080 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 9.40 Example of Complementary PWM Mode Operation Rev. 4.00 Jul. 25, 2008 Page 273 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 9.56 Registers and Counters Requiring Initialization Register/Counter TGRC_3 Set Value 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Dead time Td (1 when dead time generation is disabled by TDER) 1/2 PWM carrier cycle Initial PWM duty value for each phase H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1. Rev. 4.00 Jul. 25, 2008 Page 274 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 4. PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. 5. Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. 6. Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 9.41 shows an example of operation without dead time. Rev. 4.00 Jul. 25, 2008 Page 275 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register to compare register Transfer from temporary register to compare register Ta TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 Tb1 Ta Tb2 Ta TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Temporary register TEMP2 Data1 Data2 Compare register TGRA_4 Data1 Data2 Output waveform Initial output Output waveform Initial output Output waveform is active-low. Figure 9.41 Example of Operation without Dead Time Rev. 4.00 Jul. 25, 2008 Page 276 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 7. PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 9.42 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 9.42 Example of PWM Cycle Updating Rev. 4.00 Jul. 25, 2008 Page 277 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 8. Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 9.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Rev. 4.00 Jul. 25, 2008 Page 278 of 750 REJ09B0243-0400 Data update timing: counter crest and trough Transfer from temporary register to compare register Counter value Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register : Compare register : Buffer register Transfer from temporary register to compare register TGRA_3 TGRC_4 TGRA_4 H'0000 Time BR Temp_R data1 data1 data2 data2 GR data3 data1 data2 data3 data4 data4 data3 data5 data5 data4 data6 data6 data6 Figure 9.43 Example of Data Update in Complementary PWM Mode Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 4.00 Jul. 25, 2008 Page 279 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9. Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 9.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 9.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TCNT_3 TCNT_4 TGRA_4 TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level Complementary PWM mode (TMDR setting) TCNT_3 and TCNT_4 count start (TSTR setting) Figure 9.44 Example of Initial Output in Complementary PWM Mode (1) Rev. 4.00 Jul. 25, 2008 Page 280 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TCNT_3 TCNT_4 TDDR TGRA_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3 and TCNT_4 count start (TSTR setting) Figure 9.45 Example of Initial Output in Complementary PWM Mode (2) Rev. 4.00 Jul. 25, 2008 Page 281 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 10. Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off comparematch occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 9.46 to 9.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solidline counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as shown in figure 9.46. If compare-matches deviate from the a → b → c → d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 9.47, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 9.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. Rev. 4.00 Jul. 25, 2008 Page 282 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period TGRA_3 c TCDR d T2 period T1 period a b a' b' TDDR H'0000 Positive phase Negative phase Figure 9.46 Example of Complementary PWM Mode Waveform Output (1) T1 period TGRA_3 c TCDR a b d T2 period T1 period a b TDDR H'0000 Positive phase Negative phase Figure 9.47 Example of Complementary PWM Mode Waveform Output (2) Rev. 4.00 Jul. 25, 2008 Page 283 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period TGRA_3 T2 period T1 period TCDR a b TDDR c a' H'0000 Positive phase b' d Negative phase Figure 9.48 Example of Complementary PWM Mode Waveform Output (3) T1 period TGRA_3 c d T2 period T1 period TCDR a b a' TDDR b' H'0000 Positive phase Negative phase Figure 9.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) Rev. 4.00 Jul. 25, 2008 Page 284 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period TGRA_3 T2 period T1 period TCDR a b a TDDR b H'0000 Positive phase c d Negative phase Figure 9.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period TGRA_3 c d T2 period T1 period TCDR a b TDDR H'0000 Positive phase Negative phase Figure 9.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Rev. 4.00 Jul. 25, 2008 Page 285 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 Positive phase Negative phase c b' d a' Figure 9.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 c ad b T2 period T1 period TCDR TDDR H'0000 Positive phase Negative phase Figure 9.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Rev. 4.00 Jul. 25, 2008 Page 286 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 11. Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 9.49 to 9.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turnoff compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. 12. Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 9.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a comparematch between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 9.54 Example of Toggle Output Waveform Synchronized with PWM Output Rev. 4.00 Jul. 25, 2008 Page 287 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 13. Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 9.55 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNTS TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 9.55 Counter Clearing Synchronized with Another Channel Rev. 4.00 Jul. 25, 2008 Page 288 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 9.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 9.56) immediately after the counters start operation, initial value output is not suppressed. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing. Counter start Tb interval Tb interval Tb interval TGRA_3 TCDR TCNT_3 TGRB_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Figure 9.56 Timing for Synchronous Counter Clearing Rev. 4.00 Jul. 25, 2008 Page 289 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 9.57. Output waveform control at synchronous counter clearing Stop count operation [1] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. Set TWCR and complementary PWM mode [2] [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Start count operation [3] Output waveform control at synchronous counter clearing Figure 9.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode  Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 9.58 to 9.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 9.58 to 9.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 9.56, respectively. Rev. 4.00 Jul. 25, 2008 Page 290 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 9.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 9.56; Bit WRE of TWCR in MTU2 is 1) Rev. 4.00 Jul. 25, 2008 Page 291 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 9.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 9.56; Bit WRE of TWCR in MTU2 is 1) Rev. 4.00 Jul. 25, 2008 Page 292 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 9.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 9.56; Bit WRE of TWCR is 1) Rev. 4.00 Jul. 25, 2008 Page 293 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Bit WRE = 1 TGRA_3 TCDR Synchronous clearing TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 9.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 9.56; Bit WRE of TWCR is 1) Rev. 4.00 Jul. 25, 2008 Page 294 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 15. Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 9.62 illustrates an operation example. Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest) 2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to SYNC4 bits in the timer synchronous register (TSYR) to 1 or the CE0A, CE0B, CE0C, CE0D, CE1A, CE1B, CE1C, and CE1D bits in the timer synchronous clear register (TSYCR) to 1). 3. Do not set the PWM duty value to H'0000. 4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1. Counter cleared by TGRA_3 compare match TGRA_3 TCDR TGRB_3 TDDR H'0000 Output waveform Output waveform Output waveform is active-high. Figure 9.62 Example of Counter Clearing Operation by TGRA_3 Compare Match Rev. 4.00 Jul. 25, 2008 Page 295 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 16. Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 9.63 to 9.66 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 9.63 Example of Output Phase Switching by External Input (1) Rev. 4.00 Jul. 25, 2008 Page 296 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 1, FB = 0, output active level = high Figure 9.64 Example of Output Phase Switching by External Input (2) Rev. 4.00 Jul. 25, 2008 Page 297 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 9.65 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) Rev. 4.00 Jul. 25, 2008 Page 298 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 1, FB = 1, output active level = high Figure 9.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) Rev. 4.00 Jul. 25, 2008 Page 299 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 17. A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1. Interrupt Skipping in Complementary PWM Mode: Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER). For the linkage with buffer registers, refer to description 3, Buffer Transfer Control Linked with Interrupt Skipping, below. A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in coordination with interrupt skipping by making settings in the timer A/D converter request control register (TADCR). For the linkage with the A/D converter start request delaying function, refer to section 9.4.9, A/D Converter Start Request Delaying Function. The setting of the timer interrupt skipping setting register (TITCR) must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of registers TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. 1. Example of Interrupt Skipping Operation Setting Procedure Figure 9.67 shows an example of the interrupt skipping operation setting procedure. Figure 9.68 shows the periods during which interrupt skipping count can be changed. Rev. 4.00 Jul. 25, 2008 Page 300 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Interrupt skipping [1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register (TITCR) to 0 to clear the skipping counter. [2] Specify the interrupt skipping count within the range from 0 to 7 times in bits 3ACOR2 to 3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and enable interrupt skipping through bits T3AEN and T4VEN. Note: The setting of TITCR must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of registers TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. Clear interrupt skipping counter [1] Set skipping count and enable interrupt skipping [2] Figure 9.67 Example of Interrupt Skipping Operation Setting Procedure TCNT_3 TCNT_4 Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Figure 9.68 Periods during which Interrupt Skipping Count can be Changed 2. Example of Interrupt Skipping Operation Figure 9.69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR). Rev. 4.00 Jul. 25, 2008 Page 301 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Interrupt skipping period TGIA_3 interrupt flag set signal Interrupt skipping period Skipping counter 00 01 02 03 00 01 02 03 TGFA_3 flag Figure 9.69 Example of Interrupt Skipping Operation Rev. 4.00 Jul. 25, 2008 Page 302 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER). Figure 9.70 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the temporary register. Figure 9.71 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer register outside the buffer transfer-enabled period. The data transfer timing is two types. That is, from the buffer register to the temporary register and from the temporary register to the buffer register. These timings depend on a programming timing to the buffer register after an interrupt is generated. Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register (TITCR). Figure 9.72 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period. Note: This function must always be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never performed. Rev. 4.00 Jul. 25, 2008 Page 303 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Buffer register Data1 (1) Data2 (3) Data* (2) Data2 Temporary register General register Data* Buffer transfer is suppressed Data2 [Legend] (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. Note: * When buffer transfer at the crest is selected. Figure 9.70 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1) Rev. 4.00 Jul. 25, 2008 Page 304 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) (1) When rewriting a buffer register within a carrier cycle after TGIA_3 interrupt occurred. TGIA_3 interrupt occurred TGIA_3 interrupt occurred TCNT_3 TCNT_4 Buffer register rewriting timing Buffer transfer-enabled period TITCR[6:4] 2 Buffer register rewriting timing TITCNT[6:4] 0 1 2 0 1 Buffer register Data Data1 Data2 Temporary register Data Data1 Data2 Compare register Data Data1 Data2 (2) When rewriting a buffer register after a carrier cycle passed from occurring TGIA_3 interrupt. TGIA_3 interrupt occurred TGIA_3 interrupt occurred TCNT_3 TCNT_4 Buffer register rewriting timing Buffer transfer-enabled period TITCR[6:4] 2 TITCNT[6:4] 0 1 2 0 1 Buffer register Data Data1 Temporary register Data Data1 Compare register Note: * Buffer transfer at the crest is selected. The skipping count is set to two. T3AEN is set to 1. Data Data1 Figure 9.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) Rev. 4.00 Jul. 25, 2008 Page 305 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Skipping counter 3ACNT 0 1 2 3 0 1 2 3 0 Skipping counter 4VCNT Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) 0 1 2 3 0 1 2 3 Note: * The skipping count is set to three. Figure 9.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer TransferEnabled Period Rev. 4.00 Jul. 25, 2008 Page 306 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. 1. Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following:  TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. 2. Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 10, Port Output Enable (POE), for details. 3. Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. See section 4.7, Function for Detecting Oscillator Stop. Rev. 4.00 Jul. 25, 2008 Page 307 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR. 1. Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 9.73 shows an example of procedure for specifying the A/D converter start request delaying function. [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register. • Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE. • Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. A/D converter start request delaying function Set A/D converter start request cycle [1] • Set the timing of transfer from cycle set buffer register • Set linkage with interrupt skipping • Enable A/D converter start request delaying function [2] A/D converter start request delaying function Figure 9.73 Example of Procedure for Specifying A/D Converter Start Request Delaying Function Rev. 4.00 Jul. 25, 2008 Page 308 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Basic Operation Example of A/D Converter Start Request Delaying Function Figure 9.74 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting. Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register TADCORA_4 TCNT_4 TADCOBRA_4 A/D converter start request (TRG4AN) (Complementary PWM mode) Figure 9.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation 3. Buffer Transfer The data in the timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D converter start request control register (TADCR_4). 4. A/D Converter Start Request Delaying Function Linked with Interrupt Skipping A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR). Figure 9.75 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D converter start requests are linked with interrupt skipping. Figure 9.76 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter start requests are linked with interrupt skipping. Rev. 4.00 Jul. 25, 2008 Page 309 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 00 01 01 02 02 00 00 01 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * When the interrupt skipping count is set to two. (UT4AE/DT4AE = 1) Figure 9.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Rev. 4.00 Jul. 25, 2008 Page 310 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 00 01 01 02 02 00 00 01 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * When the interrupt skipping count is set to two. UT4AE = 1 DT4AE = 0 Figure 9.76 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Rev. 4.00 Jul. 25, 2008 Page 311 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.10 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in channel 5. Example of External Pulse Width Measurement Setting Procedure: External pulse width measurement [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Select pulse width measuring conditions [2] Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR. Select counter clock [1] Start count operation [3] Figure 9.77 Example of External Pulse Width Measurement Setting Procedure Example of External Pulse Width Measurement: MPφ TIC5U TCNT5_U 0000 0001 0002 0003 0004 0005 0006 0007 0007 0008 0009 000A 000B Figure 9.78 Example of External Pulse Width Measurement (Measuring High Pulse Width) Rev. 4.00 Jul. 25, 2008 Page 312 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.11 Dead Time Compensation By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation. Tdead Upper arm signal Lower arm signal Inverter output detection signal Tdelay Dead time delay signal Figure 9.79 Delay in Dead Time in Complementary PWM Operation Rev. 4.00 Jul. 25, 2008 Page 313 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Dead Time Compensation Setting Procedure: Figure 9.80 shows an example of dead time compensation setting procedure by using three counters in channel 5. [1] Place channels 3 and 4 in complementary PWM mode. For details, refer to section 9.4.8, Complementary PWM Mode. Complementary PWM mode [1] [2] Specify the external pulse width measurement function for the target TIOR in channel 5. For details, refer to section 9.4.10, External Pulse Width Measurement. [2] [3] Set bits CST3 and CST4 in TSTR and bits CST5U, CST5V, and CST5W in TSTR2 to 1 to start count operation. Start count operation in channels 3 to 5 [3] [4] When the capture condition specified in TIOR is satisfied, the TCNT_5 value is captured in TGR_5. [5] For U-phase dead time compensation, when an interrupt is generated at the crest (TGIA_3) or trough (TCIV_4) in complementary PWM mode, read the TGRU_5 value, calculate the difference in time in TGRB_3, and write the corrected value to TGRD_3 in the interrupt processing. For the V phase and W phase, read the TGRV_5 and TGRW_5 values and write the corrected values to TGRC_4 and TGRD_4, respectively, in the same way as for U-phase compensation. The TCNT_5 value should be cleared through the TCNTCMPCLR setting or by software. Notes: The PFC settings must be completed in advance. * As an interrupt flag is set under the capture condition specified in TIOR, do not enable interrupt requests in TIER_5. External pulse width measurement TCNT_5 input capture occurs [4] * Interrupt processing [5] Figure 9.80 Example of Dead Time Compensation Setting Procedure MTU ch3/4 ch5 Complementary PWM output DC + Level conversion Dead time delay input W Inverter output monitor signals V U V U W U V W Motor ≠ Figure 9.81 Example of Motor Control Circuit Configuration Rev. 4.00 Jul. 25, 2008 Page 314 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 9.82 is an operating example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). TGRA_4 Tdead Upper arm signal Lower arm signal Inverter output monitor signal Tdelay Dead time delay signal Up-count/down-count signal (udflg) TCNT[15:0] TGR[15:0] 3DE7 3E5B 3DE7 3E5B 3ED3 3ED3 3F37 3F37 3FAF 3FAF Figure 9.82 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation Rev. 4.00 Jul. 25, 2008 Page 315 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.5 9.5.1 Interrupt Sources Interrupt Sources and Priorities There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 9.57 lists the MTU2 interrupt sources. Rev. 4.00 Jul. 25, 2008 Page 316 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.57 MTU2 Interrupts Channel Name Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRE_0 compare match TGRF_0 compare match TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TGRC_4 input capture/compare match TGRD_4 input capture/compare match TCNT_4 overflow/underflow TGRU_5 input capture/compare match TGRV_5 input capture/compare match TGRW_5 input capture/compare match Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFE_0 TGFF_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 TGFU_5 TGFV_5 TGFW_5 Priority High 0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 TGIE_0 TGIF_0 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 4 TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 5 TGIU_5 TGIV_5 TGIW_5 Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Rev. 4.00 Jul. 25, 2008 Page 317 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2. Rev. 4.00 Jul. 25, 2008 Page 318 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.5.2 A/D Converter Activation The A/D converter can be activated by one of the following three methods in the MTU2. Table 9.58 shows the relationship between interrupt sources and A/D converter start request signals. A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode: The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions. • When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1 • When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0: The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by A/D Converter Start Request Delaying Function: The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 9.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated. Rev. 4.00 Jul. 25, 2008 Page 319 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.58 Interrupt Sources and A/D Converter Start Request Signals Target Registers TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4 TGRE_0 and TCNT_0 TADCORA and TCNT_4 TADCORB and TCNT_4 TCNT_4 Trough in complementary PWM mode Compare match TRG0N TRG4AN TRG4BN Interrupt Source Input capture/compare match A/D Converter Start Request Signal TRGAN Rev. 4.00 Jul. 25, 2008 Page 320 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.6 9.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figures 9.83 and 9.84 show TCNT count timing in internal clock operation, and figure 9.85 shows TCNT count timing in external clock operation (normal mode), and figure 9.86 shows TCNT count timing in external clock operation (phase counting mode). MPφ Internal clock TCNT input clock TCNT Falling edge Rising edge N-1 N N+1 Figure 9.83 Count Timing in Internal Clock Operation (Channels 0 to 4) MPφ Internal clock TCNT input clock TCNT Rising edge N-1 N Figure 9.84 Count Timing in Internal Clock Operation (Channel 5) MPφ External clock TCNT input clock TCNT Falling edge Rising edge N-1 N N+1 Figure 9.85 Count Timing in External Clock Operation (Channels 0 to 4) Rev. 4.00 Jul. 25, 2008 Page 321 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ External clock TCNT input clock Rising edge Falling edge TCNT N-1 N N-1 Figure 9.86 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.87 shows output compare output timing (normal mode and PWM mode) and figure 9.88 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). MPφ TCNT input clock N N+1 TCNT TGR Compare match signal TIOC pin N Figure 9.87 Output Compare Output Timing (Normal Mode/PWM Mode) Rev. 4.00 Jul. 25, 2008 Page 322 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 9.88 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 9.89 shows input capture signal timing. MPφ Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 9.89 Input Capture Input Signal Timing Rev. 4.00 Jul. 25, 2008 Page 323 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Timing for Counter Clearing by Compare Match/Input Capture: Figures 9.90 and 9.91 show the timing when counter clearing on compare match is specified, and figure 9.92 shows the timing when counter clearing on input capture is specified. MPφ Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 9.90 Counter Clear Timing (Compare Match) MPφ Compare match signal Counter clear signal TCNT N-1 H'0000 TGR N Figure 9.91 Counter Clear Timing (Compare Match) (Channel 5) Rev. 4.00 Jul. 25, 2008 Page 324 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 9.92 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 9.93 to 9.95 show the timing in buffer operation. MPφ TCNT Compare match buffer signal TGRA, TGRB TGRC, TGRD n n+1 n N N Figure 9.93 Buffer Operation Timing (Compare Match) MPφ Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 9.94 Buffer Operation Timing (Input Capture) Rev. 4.00 Jul. 25, 2008 Page 325 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ TCNT n H'0000 TCNT clear signal Buffer transfer signal TGRA, TGRB, TGRE TGRC, TGRD, TGRF n N N Figure 9.95 Buffer Transfer Timing (when TCNT Cleared) Buffer Transfer Timing (Complementary PWM Mode): Figures 9.96 to 9.98 show the buffer transfer timing in complementary PWM mode. MPφ TCNTS H'0000 TGRD_4 write signal Temporary register transfer signal Buffer register Temporary register n N n N Figure 9.96 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) Rev. 4.00 Jul. 25, 2008 Page 326 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ TCNTS P-x P H'0000 TGRD_4 write signal Buffer register Temporary register n N n N Figure 9.97 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) MPφ TCNTS P-1 P H'0000 Buffer transfer signal Temporary register Compare register N n N Figure 9.98 Transfer Timing from Temporary Register to Compare Register Rev. 4.00 Jul. 25, 2008 Page 327 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figures 9.99 and 9.100 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. MPφ TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 9.99 TGI Interrupt Timing (Compare Match) (Channels 0 to 4) MPφ TCNT input clock TCNT N-1 N TGR Compare match signal TGF flag N TGI interrupt Figure 9.100 TGI Interrupt Timing (Compare Match) (Channel 5) Rev. 4.00 Jul. 25, 2008 Page 328 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGF Flag Setting Timing in Case of Input Capture: Figures 9.101 and 9.102 show the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. MPφ, Pφ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 9.101 TGI Interrupt Timing (Input Capture) (Channels 0 to 4) MPφ, Pφ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 9.102 TGI Interrupt Timing (Input Capture) (Channel 5) Rev. 4.00 Jul. 25, 2008 Page 329 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCFV Flag/TCFU Flag Setting Timing: Figure 9.103 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 9.104 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. MPφ, Pφ TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 9.103 TCIV Interrupt Setting Timing MPφ, Pφ TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF TCIU interrupt Figure 9.104 TCIU Interrupt Setting Timing Rev. 4.00 Jul. 25, 2008 Page 330 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figures 9.105 and 9.106 show the timing for status flag clearing by the CPU. TSR write cycle T1 T2 MPφ, Pφ Address TSR address Write signal Status flag Interrupt request signal Figure 9.105 Timing for Status Flag Clearing by CPU (Channels 0 to 4) TSR write cycle T1 T2 MPφ, Pφ Address TSR address Write signal Status flag Interrupt request signal Figure 9.106 Timing for Status Flag Clearing by CPU (Channel 5) Rev. 4.00 Jul. 25, 2008 Page 331 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7 9.7.1 Usage Notes Module Standby Mode Setting MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes. 9.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.107 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 9.107 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 4.00 Jul. 25, 2008 Page 332 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: • Channels 0 to 4 f= MPφ (N + 1) • Channel 5 f= Where MPφ N f: MPφ: N: Counter frequency MTU2 peripheral clock operating frequency TGR set value 9.7.4 Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.108 shows the timing in this case. TCNT write cycle T1 T2 MPφ Address Write signal Counter Counter clear signal TCNT TCNT address N H'0000 Figure 9.108 Contention between TCNT Write and Clear Operations Rev. 4.00 Jul. 25, 2008 Page 333 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.109 shows the timing in this case. TCNT write cycle T1 T2 MPφ Address TCNT address Write signal TCNT input clock TCNT N TCNT write data M Figure 9.109 Contention between TCNT Write and Increment Operations Rev. 4.00 Jul. 25, 2008 Page 334 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 9.110 shows the timing in this case. TGR write cycle T1 T2 MPφ Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address Figure 9.110 Contention between TGR Write and Compare Match Rev. 4.00 Jul. 25, 2008 Page 335 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 9.111 shows the timing in this case. TGR write cycle T1 T2 MPφ Address Buffer register address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M TGR N Figure 9.111 Contention between Buffer Register Write and Compare Match Rev. 4.00 Jul. 25, 2008 Page 336 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.8 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 9.112 shows the timing in this case. TGR write cycle T1 T2 MPφ Address Buffer register address Write signal TCNT clear signal Buffer transfer signal Buffer register N M Buffer register write data TGR N Figure 9.112 Contention between Buffer Register Write and TCNT Clear Rev. 4.00 Jul. 25, 2008 Page 337 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.9 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 9.113 and 9.114 show the timing in this case. TGR read cycle T1 T2 MPφ Address Read signal Input capture signal TGR Internal data bus N M TGR address N Figure 9.113 Contention between TGR Read and Input Capture (Channels 0 to 4) TGR read cycle T1 T2 MPφ Address Read signal Input capture signal TGR Internal data bus N M TGR address M Figure 9.114 Contention between TGR Read and Input Capture (Channel 5) Rev. 4.00 Jul. 25, 2008 Page 338 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 9.115 and 9.116 show the timing in this case. TGR write cycle T1 T2 MPφ Address Write signal Input capture signal TCNT TGR M M TGR address Figure 9.115 Contention between TGR Write and Input Capture (Channels 0 to 4) TGR write cycle T1 T2 MPφ Address Write signal Input capture signal TCNT TGR M TGR write data N TGR address Figure 9.116 Contention between TGR Write and Input Capture (Channel 5) Rev. 4.00 Jul. 25, 2008 Page 339 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.117 shows the timing in this case. Buffer register write cycle T2 T1 MPφ Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address Figure 9.117 Contention between Buffer Register Write and Input Capture 9.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to TGRD_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 9.118. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Rev. 4.00 Jul. 25, 2008 Page 340 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT write cycle T1 T2 MPφ Address Write signal TCNT_2 H'FFFE H'FFFF TCNT_2 write data TGRA_2 to TGRB_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D P N M M M Disabled H'FFFF N N+1 TCNT_2 address Q P Figure 9.118 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection Rev. 4.00 Jul. 25, 2008 Page 341 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 9.119. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Counter operation stop Complementary PWM mode operation Complementary PMW restart Figure 9.119 Counter Value during Complementary PWM Mode Stop 9.7.14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register. Rev. 4.00 Jul. 25, 2008 Page 342 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 9.120 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT3 TGRC_3 Point a Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRB_3, TGRA_4, TGRB_4 Point b TGRD_3, TGRC_4, TGRD_4 H'0000 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 9.120 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode Rev. 4.00 Jul. 25, 2008 Page 343 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit in TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 9.121 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 9.121 Reset Synchronous PWM Mode Overflow Flag Rev. 4.00 Jul. 25, 2008 Page 344 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.122 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. MPφ TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV Figure 9.122 Contention between Overflow and Counter Clearing Rev. 4.00 Jul. 25, 2008 Page 345 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.123 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 MPφ Address Write signal TCNT address TCNT write data TCNT H'FFFF Disabled M TCFV flag Figure 9.123 Contention between TCNT Write and Overflow 9.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode. Rev. 4.00 Jul. 25, 2008 Page 346 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00. 9.7.21 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source. Interrupts should therefore be disabled before entering module standby mode. 9.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. The MTU2 has a new function that allows simultaneous capture of TCNT_1 and TCNT_2 with a single input-capture input as the trigger. This function allows reading of the 32-bit counter such that TCNT_1 and TCNT_2 are captured at the same time. Rev. 4.00 Jul. 25, 2008 Page 347 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.8 9.8.1 MTU2 Output Pin Initialization Operating Modes The MTU2 has the following six operating modes. Waveform output is possible in all of these modes. • • • • • • Normal mode (channels 0 to 4) PWM mode 1 (channels 0 to 4) PWM mode 2 (channels 0 to 2) Phase counting modes 1 to 4 (channels 1 and 2) Complementary PWM mode (channels 3 and 4) Reset-synchronized PWM mode (channels 3 and 4) The MTU2 output pin initialization method for each of these modes is described in this section. 9.8.2 Reset Start Operation The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *. Rev. 4.00 Jul. 25, 2008 Page 348 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 9.59. Table 9.59 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode Rev. 4.00 Jul. 25, 2008 Page 349 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. • In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. • In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. • In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. • In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. • When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Rev. 4.00 Jul. 25, 2008 Page 350 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Pin initialization procedures are described below for the numbered combinations in table 9.59. The active level is assumed to be low. Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.124 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.124 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Not necessary when restarting in normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 351 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.125 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 9.125 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.124. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 352 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 9.126 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 9.126 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 9.124. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Rev. 4.00 Jul. 25, 2008 Page 353 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.127 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR (PCM) occurs (PORT) (0) 12 13 14 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.127 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 9.124. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev. 4.00 Jul. 25, 2008 Page 354 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.128 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after resetting. 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 13 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (normal) (1) (1 init (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (0 init (disabled) (0) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.128 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.124. 11. 12. 13. 14. 15. 16. 17. 18. Initialize the normal mode waveform generation section with TIOR. Disable operation of the normal mode waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 355 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.129 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 4 5 6 RESET TMDR TOER TIOR PFC TSTR (normal) (1) (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 11 12 14 15 16 17 18 13 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.129 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 9.124. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 356 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 9.130 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 9.130 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 357 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 9.131 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Not initialized (TIOC*B) Figure 9.131 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.130. 11. 12. 13. 14. Not necessary when restarting in PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 358 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 9.132 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Not initialized (cycle register) Figure 9.132 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 9.130. 11. 12. 13. 14. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. Rev. 4.00 Jul. 25, 2008 Page 359 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.133 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 5 4 6 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 9.133 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 9.130. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev. 4.00 Jul. 25, 2008 Page 360 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.134 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after resetting. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 9.134 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.130. 11. 12. 13. 14. 15. 16. 17. 18. 19. Set normal mode for initialization of the normal mode waveform generation section. Initialize the PWM mode 1 waveform generation section with TIOR. Disable operation of the PWM mode 1 waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 361 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.135 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 9.135 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 9.134. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 362 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 9.136 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 9.136 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU2 output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Rev. 4.00 Jul. 25, 2008 Page 363 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 9.137 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Not initialized (TIOC*B) Figure 9.137 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 9.136. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 364 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 9.138 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Not initialized (cycle register) Figure 9.138 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 9.136. 10. 11. 12. 13. Not necessary when restarting in PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 365 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.139 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. 1 2 3 5 4 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU2) (1) occurs (PORT) (0) (PCM) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 9.139 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 9.136. 10. 11. 12. 13. Set phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 366 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.140 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 3 5 4 6 7 8 9 10 11 12 13 TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (1 init (MTU2) (1) occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.140 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, MTU2 output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU2 output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. Set in normal mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 367 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.141 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 3 4 5 6 7 8 9 10 11 12 13 1 2 PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR PFC TSTR Match Error (PCM) (1 init (MTU2) (1) occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (TIOC*B) Figure 9.141 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 9.140. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 368 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 9.142 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 3 5 4 6 7 8 9 10 11 12 13 TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (1 init (MTU2) (1) occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Not initialized (cycle register) Figure 9.142 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 9.140. 10. 11. 12. 13. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 369 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.143 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 3 5 4 6 7 8 9 10 11 12 13 TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (1 init (MTU2) (1) occurs (PORT) (0) (PCM) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 High-Z High-Z Figure 9.143 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 9.140. 10. 11. 12. 13. Not necessary when restarting in phase counting mode. Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 370 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.144 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.144 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM output initial value.) Set normal mode. (MTU2 output goes low.) Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 371 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.145 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 9.145 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.144. 11. 12. 13. 14. Set PWM mode 1. (MTU2 output goes low.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 372 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.146 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.146 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.144. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. Rev. 4.00 Jul. 25, 2008 Page 373 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.147 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). 1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.147 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.144. 11. Set normal mode and make new settings. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 374 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.148 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) (RPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.148 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 9.144. 11. Set normal mode. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 375 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.149 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.149 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, MTU2 output is low and ports are in the high-impedance state. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronized PWM. Enable channel 3 and 4 output with TOER. Set MTU2 output with the PFC. The count operation is started by TSTR. The reset-synchronized PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized PWM output initial value.) Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 376 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.150 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Not initialized (TIOC3B) Not initialized (TIOC3D) Figure 9.150 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 9.149. 11. 12. 13. 14. Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set MTU2 output with the PFC. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 377 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.151 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 14 15 16 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.151 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 9.149. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU2 cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU2 output with the PFC. 16. Operation is restarted by TSTR. Rev. 4.00 Jul. 25, 2008 Page 378 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.152 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 9.152 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 9.149. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence. Rev. 4.00 Jul. 25, 2008 Page 379 of 750 REJ09B0243-0400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 4.00 Jul. 25, 2008 Page 380 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Section 10 Port Output Enable (POE) The port output enable (POE) can be used to place the high-current pins (pins multiplexed with TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2) and the pins for channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in high-impedance state, depending on the change on POE0, POE1, POE3*, and POE8 input pins and the output status of the high-current pins, or by modifying register settings. It can also simultaneously generate interrupt requests. 10.1 Features • Each of the POE0, POE1, POE3*, and POE8 input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or Pφ/128 × 16 low-level sampling. • High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by POE0, POE1, POE3*, and POE8 pin falling-edge or low-level sampling. • High-current pins can be placed in high-impedance state when the high-current pin output levels are compared and simultaneous active-level output continues for one cycle or more. • High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by modifying the POE register settings. • Interrupts can be generated by input-level sampling or output-level comparison results. The POE has input level detection circuits, output level comparison circuits, and a high-impedance request/interrupt request generating circuit as shown in figure 10.1, Block Diagram of POE. In addition to control by the POE, high-current pins can be placed in high-impedance state when the oscillator stops or in software standby state. For details, refer to appendix A, Pin States. Note: * The POE3 pin is supported only by the SH7125. TIMMTU1A_020020030800 Rev. 4.00 Jul. 25, 2008 Page 381 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Figure 10.1 shows a block diagram of the POE. POECR1, POECR2 Output level comparison circuit Output level comparison circuit High-impedance request/interrupt request generating circuit TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D OCSR1 Output level comparison circuit High-impedance request signal for MTU2 high-current pins High-impedance request signal for MTU2 channel 0 pins Interrupt request signal Input level detection circuit POE3 * POE1 POE0 ICSR1 Pφ/8 Pφ/16 Pφ/128 Frequency divider [Legend] ICSR1: ICSR3: OCSR1: POECR1: POECR2: SPOER: Pφ Input level control/status register 1 Input level control/status register 3 Output level control/status register 1 Port output enable control register 1 Port output enable control register 2 Software port output enable register ICSR3 Falling edge detection circuit Low level sampling circuit Input level detection circuit POE8 Falling edge detection circuit Low level sampling circuit SPOER Note: * This pin is supported only by the SH7125. Figure 10.1 Block Diagram of POE Rev. 4.00 Jul. 25, 2008 Page 382 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.2 Input/Output Pins Table 10.1 Pin Configuration Name Port output enable input pins 0, 1, 3 Abbreviation POE0, POE1, POE3* I/O Input Description Input request signals to place highcurrent pins for MTU2 in highimpedance state* Inputs a request signal to place pins for channel 0 in MTU2 in highimpedance state* Port output enable input pin 8 POE8 Input Note: * When the POE3 function is selected in the PFC, the pin is pulled up inside the LSI if nothing is input to it. The POE3 pin is supported only by the SH7125. Table 10.2 shows output-level comparisons with pin combinations. Table 10.2 Pin Combinations Pin Combination PE9/TIOC3B and PE11/TIOC3D PE12/TIOC4A and PE14/TIOC4C PE13/TIOC4B and PE15/TIOC4D I/O Description Output The high-current pins for the MTU2 are placed in high-impedance state when the pins simultaneously output an active level (low level when the output level select P (OLSP) bit of the timer output control register (TOCR) in the MTU2 is 0 or high level when the bit is 1) for one or more cycles of the peripheral clock (Pφ). This active level comparison is done when the MTU2 output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and highimpedance control can be selected by POE registers. Rev. 4.00 Jul. 25, 2008 Page 383 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.3 Register Descriptions The POE has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 10.3 Register Configuration Register Name Input level control/status register 1 Output level control/status register 1 Input level control/status register 3 Software port output enable register Port output enable control register 1 Port output enable control register 2 Abbreviation ICSR1 OCSR1 ICSR3 SPOER POECR1 POECR2 R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'00 H'00 H'7700 Address H'FFFFD000 H'FFFFD002 H'FFFFD008 H'FFFFD00A H'FFFFD00B H'FFFFD00C Access Size 8, 16, 32 8, 16 8, 16, 32 8 8 8, 16 Rev. 4.00 Jul. 25, 2008 Page 384 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.3.1 Input Level Control/Status Register 1 (ICSR1) ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1, and POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: 15 POE3F 14 - 13 12 11 - 10 - 9 - 8 PIE1 7 6 5 - 4 - 3 2 1 0 POE1F POE0F POE3M[1:0] POE1M[1:0] POE0M[1:0] Initial value: 0 0 0 0 R/W:R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 0 R 0 R 0 R 0 R/W 0 0 0 0 0 0 0 0 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit 15 Bit Name POE3F Initial value 0 R/W 1 Description R/(W)* POE3 Flag (Supported only by the SH7125.) This flag indicates that a high impedance request has been input to the POE3 pin. [Clearing conditions] • By writing 0 to POE3F after reading POE3F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR1) By writing 0 to POE3F after reading POE3F = 1 after a high level input to POE3 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR1) When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin • [Setting condition] • 14  0 R/(W)*1 Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 385 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 13 Bit Name POE1F Initial value 0 R/W 1 Description R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions] • By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1) By writing 0 to POE1F after reading POE1F = 1 after a high level input to POE1 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR1) When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin • [Setting condition] • 12 POE0F 0 R/(W)*1 POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin. [Clearing conditions] • By writing 0 to POE0F after reading POE0F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR1) By writing 0 to POE0F after reading POE0F = 1 after a high level input to POE0 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR1) When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin • [Setting condition] • 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 386 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 8 Bit Name PIE1 Initial value 0 R/W R/W Description Port Interrupt Enable 1 This bit enables/disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0] 00 R/W* 2 POE3 mode 1, 0 (Supported only by the SH7125. Write 00 to these bits in the SH7124.) These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE3 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE3 input has been sampled for 16 Pφ/128 clock pulses and all are low level. 5, 4  All 0 R/W*2 Reserved These bits are always read as 0. The write value should always be 0. 3, 2 POE1M[1:0] 00 R/W*2 POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE1 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE1 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Rev. 4.00 Jul. 25, 2008 Page 387 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 1, 0 Bit Name POE0M[1:0] Initial value 00 R/W R/W* 2 Description POE0 mode 1, 0 These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE0 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE0 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. 10.3.2 Output Level Control/Status Register 1 (OCSR1) OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: 15 OSF1 14 - 13 - 12 - 11 - 10 - 9 OCE1 8 OIE1 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 0 R/W:R/(W)*1 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Bit 15 Initial Bit Name value OSF1 0 R/W 1 Description R/(W)* Output Short Flag 1 This flag indicates that any one of the three pairs of MTU2 2-phase outputs to be compared has simultaneously become an active level. [Clearing condition] • • By writing 0 to OSF1 after reading OSF1 = 1 When any one of the three pairs of 2-phase outputs has simultaneously become an active level [Setting condition] Rev. 4.00 Jul. 25, 2008 Page 388 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit Initial Bit Name value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14 to 10  9 OCE1 0 R/W*2 Output Short High-Impedance Enable 1 This bit specifies whether to place the pins in highimpedance state when the OSF1 bit in OCSR1 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 OIE1 0 R/W Output Short Interrupt Enable 1 This bit enables or disables interrupt requests when the OSF1 bit in OCSR is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. 10.3.3 Input Level Control/Status Register 3 (ICSR3) ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the enable/disable of interrupts, and indicates status. Bit: 15 - 14 - 13 - 12 POE8F 11 - 10 - 9 POE8E 8 PIE3 7 - 6 - 5 - 4 - 3 - 2 - 1 0 POE8M[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R/(W)*1 0 R 0 R 0 0 R/W*2 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 0 R/W*2 R/W*2 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. Rev. 4.00 Jul. 25, 2008 Page 389 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 13 — 12 POE8F 0 R/(W)*1 POE8 Flag This flag indicates that a high impedance request has been input to the POE8 pin. [Clearing conditions] • By writing 0 to POE8F after reading POE8F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR3)· By writing 0 to POE8F after reading POE8F = 1 after a high level input to POE8 is sampled at Pf/8, Pf/16, or Pf/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR3) When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin • [Setting condition] • 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 POE8E 0 R/W*2 POE8 High-Impedance Enable This bit specifies whether to place the pins in highimpedance state when the POE8F bit in ICSR3 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state 8 PIE3 0 R/W Port Interrupt Enable 3 (Supported only by the SH7125. Write 0 to this bit in the SH7124.) This bit enables or disables interrupt requests when the POE8 bit in ICSR3 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled Rev. 4.00 Jul. 25, 2008 Page 390 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 7 to 2 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 POE8M[1:0] 00 R/W*2 POE8 mode 1 and 0 These bits select the input mode of the POE8 pin. 00: Accept request on falling edge of POE8 input 01: Accept request when POE8 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE8 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE8 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset. 10.3.4 Software Port Output Enable Register (SPOER) SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 0 MTU2 MTU2 CH0HIZ CH34HIZ Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 3 — 2 — 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 391 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 1 Bit Name MTU2CH0HIZ Initial value 0 R/W R/W Description MTU2 Channel 0 Output High-Impedance This bit specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] • • Power-on reset By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ = 1 1: Places the pins in high-impedance state [Setting condition] • 0 MTU2CH34HIZ 0 R/W By writing 1 to MTU2CH0HIZ MTU2 Channel 3 and 4 Output High-Impedance This bit specifies whether to place the high-current pins for the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] • • Power-on reset By writing 0 to MTU2CH34HIZ after reading MTU2CH34HIZ = 1 1: Places the pins in high-impedance state [Setting condition] • By writing 1 to MTU2CH34HIZ Rev. 4.00 Jul. 25, 2008 Page 392 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.3.5 Port Output Enable Control Register 1 (POECR1) POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: 7 - 6 - 5 - 4 - 3 MTU2 PE3ZE 2 MTU2 PE2ZE 1 MTU2 PE1ZE 0 MTU2 PE0ZE Initial value: R/W: 0 R 0 R 0 R 0 R 0 0 0 0 R/W* R/W* R/W* R/W* Note: * Can be modified only once after a power-on reset. Bit 7 to 4 Bit Name — Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 MTU2PE3ZE 0 R/W* MTU2 PE3 High-Impedance Enable This bit specifies whether to place the PE3/TIOC1D pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 2 MTU2PE2ZE 0 R/W* MTU2 PE2 High-Impedance Enable This bit specifies whether to place the PE2/TIOC1C pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state 1 MTU2PE1ZE 0 R/W* MTU2 PE1 High-Impedance Enable This bit specifies whether to place the PE1/TIOC1B pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state Rev. 4.00 Jul. 25, 2008 Page 393 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 0 Bit Name MTU2PE0ZE Initial value 0 R/W R/W* Description MTU2 PE0 High-Impedance Enable This bit specifies whether to place the PE0/TIOC1A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state Note: * Can be modified only once after a power-on reset. 10.3.6 Port Output Enable Control Register 2 (POECR2) POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins. Bit: 15 - 14 MTU2 P1CZE 13 MTU2 P2CZE 12 MTU2 P3CZE 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 1 1 1 R/W* R/W* R/W* 0 R 1 1 1 R/W* R/W* R/W* 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: * Can be modified only once after a power-on reset. Bit 15 Bit Name — Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 MTU2P1CZE 1 R/W* MTU2 Port 1 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE9/TIOC3B and PE11/TIOC3D pins and to place them in highimpedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Rev. 4.00 Jul. 25, 2008 Page 394 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Bit 13 Bit Name MTU2P2CZE Initial value 1 R/W R/W* Description MTU2 Port 2 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in highimpedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 12 MTU2P3CZE 1 R/W* MTU2 Port 3 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE13/TIOC4B and PE15/TIOC4D pins and to place them in highimpedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 11 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8  All 1 R/W* Reserved These bits are always read as 1. The write value should always be 1. 7 to 0 — 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * Can be modified only once after a power-on reset. Rev. 4.00 Jul. 25, 2008 Page 395 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.4 Operation Table 10.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 10.4 Target Pins and Conditions for High-Impedance Control Pins MTU2 high-current pins (PE9/TIOC3B and PE11/TIOC3D) MTU2 high-current pins (PE12/TIOC4A and PE14/TIOC4C) MTU2 high-current pins (PE13/TIOC4B and PE15/TIOC4D) MTU2 channel 0 pin (PE0/TIOC0A) MTU2 channel 0 pin (PE1/TIOC0B) MTU2 channel 0 pin (PE2/TIOC0C) MTU2 channel 0 pin (PE3/TIOC0D) Conditions Input level detection, output level comparison, or SPOER setting Input level detection, output level comparison, or SPOER setting Input level detection, output level comparison, or SPOER setting Input level detection or SPOER setting Input level detection or SPOER setting Input level detection or SPOER setting Input level detection or SPOER setting Detailed Conditions MTU2P1CZE • ((POE3F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2P2CZE • ((POE3F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2P3CZE • ((POE3F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2PE0ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2PE1ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2PE2ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2PE3ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) 10.4.1 Input Level Detection Operation If the input conditions set by ICSR1 occur on the POE0, POE1, POE3*, and POE8 pins, the highcurrent pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however, that these high-current and MTU2 pins enter high-impedance state only when general input/output function or MTU2 function is selected for these pins. (1) Falling Edge Detection When a change from a high to low level is input to the POE0, POE1, POE3*, and POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 10.2 shows a sample timing after the level changes in input to the POE0, POE1, POE3*, and POE8 pins until the respective pins enter high-impedance state. Note: * This pin is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 396 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) Pφ Pφ rising edge POE input Falling edge detection PE9/TIOC3B High-impedance state* Note: * The other high-current pins also enter the high-impedance state in the similar timing. Figure 10.2 Falling Edge Detection (2) Low-Level Detection Figure 10.3 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock selected by ICSR1. If even one high level is detected during this interval, the low level is not accepted. The timing when the high-current pins enter the high-impedance state after the sampling clock is input is the same in both falling-edge detection and in low-level detection. 8/16/128 clock cycles Pφ Sampling clock POE input PE9/ TIOC3B When low level is sampled at all points When high level is sampled at least once High-impedance state* 1 1 2 2 3 16 13 Flag set (POE received) Flag not set Note: * Other high-current pins also go to the high-impedance state at the same timing. Figure 10.3 Low-Level Detection Operation Rev. 4.00 Jul. 25, 2008 Page 397 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.4.2 Output-Level Compare Operation Figure 10.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. Pφ PE9/ TIOC3B PE11/ TIOC3D Low level overlapping detected High impedance state Figure 10.4 Output-Level Compare Operation 10.4.3 Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the flags in bits 12 to 15 (POE0F to POE3F and POE8F) in ICSR1. However, note that when lowlevel sampling is selected by bits 0 to 7 in ICSR1, just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to the POE pin and is sampled. High-current pins that have entered high-impedance state due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing the flag in bit 15 (OCF1) in OCSR1. However, note that just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the high-current pins. Inactive-level outputs can be achieved by setting the MTU2 internal registers. Rev. 4.00 Jul. 25, 2008 Page 398 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.5 Interrupts The POE issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 10.5 shows the interrupt sources and their conditions. Table 10.5 Interrupt Sources and Conditions Name OEI1 OEI3 Interrupt Source Output enable interrupt 1 Output enable interrupt 2 Interrupt Flag POE3F, POE1F, POE0F, and OSF1 POE8F Condition PIE1 • (POE3F + POE1F + POE0F) + OIE1 • OSF1 PIE3 • POE8F Rev. 4.00 Jul. 25, 2008 Page 399 of 750 REJ09B0243-0400 Section 10 Port Output Enable (POE) 10.6 10.6.1 Usage Note Pin State when a Power-On Reset is Issued from the Watchdog Timer When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function controller (PFC) sets initial values that select the general input function for the I/O ports. However, when a power-on reset is issued from the WDT while a pin is being handled as high impedance by the port output enable (POE), the pin is placed in the output state for one cycle of the peripheral clock (Pf), after which the function is switched to general input. This also occurs when a power-on reset is issued from the WDT for pins that are being handled as high impedance due to short-circuit detection by the MTU2. Figure 10.5 shows the state of a pin for which the POE input has selected high impedance handling with the timer output selected when a power-on reset is issued from the WDT. Pφ POE input Pin state Timer output High impedance state Timer output 1Pφ cycle General input PFC setting value Timer output General input Power-on reset by WDT Figure 10.5 Pin State when a Power-On Reset is Issued from the Watchdog Timer Rev. 4.00 Jul. 25, 2008 Page 400 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) Section 11 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT). This LSI can be reset by the overflow of the counter when the value of the counter has not been updated because of a system runaway. The watchdog timer (WDT) is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when clearing software standby mode. It can also be used as an interval timer. 11.1 • • • • Features Can be used to ensure the clock settling time: Use the WDT to revoke software standby mode. Can switch between watchdog timer mode and interval timer mode. Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. An interrupt is generated in interval timer mode An interval timer interrupt is generated when the counter overflows. • Choice of eight counter input clocks Eight clocks (×1 to ×1/4096) that are obtained by dividing the peripheral clock can be chosen. • Choice of two resets Power-on reset and manual reset are available. WDTS300B_000020030200 Rev. 4.00 Jul. 25, 2008 Page 401 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) Figure 11.1 shows a block diagram of the WDT. WDT Standby cancellation Standby mode Peripheral clock (Pφ) WDTOVF Internal reset request Interrupt request Reset control Clock selection Clock selector Interrupt control WTCSR Overflow Clock Divider Standby control WTCNT Bus interface Internal bus [Legend] WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 11.1 Block Diagram of WDT Rev. 4.00 Jul. 25, 2008 Page 402 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) 11.2 Input/Output Pin for WDT Table 11.1 lists the WDT pin configuration. Table 11.1 WDT Pin Configuration Pin Name Watchdog timer overflow Abbreviation I/O WDTOVF Description Output When an overflow occurs in watchdog timer mode, an internal reset is generated and this pin outputs the low level for one clock cycle specified by the CKS2 to CKS0 bits in WTCSR. Rev. 4.00 Jul. 25, 2008 Page 403 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) 11.3 Register Descriptions The WDT has the following two registers. Refer to section 20, List of Registers, for the details of the addresses of these registers and the state of registers in each operating mode. Table 11.2 Register Configuration Register Name Watchdog timer counter Watchdog timer control/status register Abbreviation WTCNT WTCSR R/W R/W R/W Initial Value H'00 H'00 Address H'FFFFE810 H'FFFFE812 Access Size 8, 16 8, 16 11.3.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The WTCNT counter is initialized to H'00 only by a power-on reset using the RES pin. Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT. Note: WTCNT differs from other registers in that it is more difficult to write to. See section 11.3.3, Notes on Register Access, for details. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 4.00 Jul. 25, 2008 Page 404 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) 11.3.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset using the RES pin. When used to count the clock settling time for canceling a software standby, it retains its value after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Note: WTCSR differs from other registers in that it is more difficult to write to. See section 11.3.3, Notes on Register Access, for details. Bit: 7 TME 6 WT/IT 5 RSTS 4 WOVF 3 IOVF 2 1 CKS[2:0] 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name TME Initial Value 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT to revoke software standby mode 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Interval timer mode 1: Watchdog timer mode Note: If WT/IT is modified when the WDT is operating, the up-count may not be performed correctly. Rev. 4.00 Jul. 25, 2008 Page 405 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) Bit 5 Bit Name RSTS Initial Value 0 R/W R/W Description Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode 2 to 0 CKS[2:0] 000 R/W Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pφ). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pφ) is 40 MHz. 000: Pφ (6.4 µs) 001: Pφ /4 (25.6 µs) 010: Pφ /16 (102.4 µs) 011: Pφ /32 (204.8 µs) 100: Pφ /64 (409.6 µs) 101: Pφ /256 (1.64 ms) 110: Pφ /1024 (6.55 ms) 111: Pφ /4096 (26.21 ms) Note: If bits CKS2 to CKS0 are modified when the WDT is operating, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not operating. Rev. 4.00 Jul. 25, 2008 Page 406 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) 11.3.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 11.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write 15 Address: H'FFFFE810 H'5A 8 7 Write data 0 WTCSR write Address: H'FFFFE812 15 H'A5 8 7 Write data 0 Figure 11.2 Writing to WTCNT and WTCSR Rev. 4.00 Jul. 25, 2008 Page 407 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) 11.4 11.4.1 Operation Canceling Software Standbys The WDT can be used to revoke software standby mode with an NMI interrupt or external interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RES pin low until the clock stabilizes.) 1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Transition to software standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin. 5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes operation. The WOVF flag in WTCSR is not set when this happens. 11.4.2 Using Watchdog Timer Mode While operating in watchdog timer mode, the WDT generates an internal reset of the type specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time the counter overflows. 1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0 bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes counting. Rev. 4.00 Jul. 25, 2008 Page 408 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) WTCNT value Overflow occurs H'FF H'00 WT/IT = 1 TME = 1 H'00 is written to WTCNT WOVF = 1 WDTOVF is asserted and an internal reset is generated Count starts WDTOVF signal 32 Pφ clock Internal reset signal (power-on reset selected) H'00 is written to WTCNT Time 3 Pφ + one cycle of count clock Internal reset signal (manual reset selected) 18 Pφ clock Figure 11.3 Operation in Watchdog Timer Mode (When WTCNT Count Clock is Specified to Pφ/32 by CKS2 to CKS0) 11.4.3 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting. Rev. 4.00 Jul. 25, 2008 Page 409 of 750 REJ09B0243-0400 Section 11 Watchdog Timer (WDT) 11.5 Usage Note If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT reaches the immediate H'00, but occurs when WTCNT changes from H'FF to H'00 after 257 cycles of count clock. Whereas if WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from H'FF to H'00 after one cycle of count clock. Rev. 4.00 Jul. 25, 2008 Page 410 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). 12.1 Features • Choice of asynchronous or clock synchronous serial communication mode • Asynchronous mode (channels 0 to 2 in the SH7125, channels 0 to 2 in the SH7124):  Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are twelve selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Multiprocessor communications  Receive error detection: Parity, overrun, and framing errors  Break detection: Break is detected by reading the RXD pin level directly when a framing error occurs. • Clock synchronous mode (channels 0 to 2 in the SH7125, channels 0 and 2 in the SH7124):  Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clock synchronous communication function.  Data length: 8 bits  Receive error detection: Overrun errors • Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so highspeed continuous data transfer is possible in both transmit and receive directions. • On-chip baud rate generator with selectable bit rates • Internal or external transmit/receive clock source: From either baud rate generator (internal clock) or SCK pin (external clock) • Choice of LSB-first or MSB-first data transfer (except for 7-bit data in asynchronous mode) Rev. 4.00 Jul. 25, 2008 Page 411 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) • Four types of interrupts: There are four interrupt sources, transmit-data-empty, transmit end, receive-data-full, and receive error interrupts, and each interrupt can be requested independently. • Module standby mode can be set Figure 12.1 shows a block diagram of the SCI. Module data bus Bus interface Internal data bus SCRDR SCTDR SCSSR SCSCR SCSMR SCSPTR SCBRR Baud rate generator RXD TXD SCRSR SCTSR SCSDCR Transmission/reception control Pφ Pφ/4 Pφ/16 Pφ/64 Parity generation Parity check SCK Clock External clock TEI TXI RXI ERI SCI [Legend] SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: SCSCR: SCSSR: SCBRR: SCSPTR: SCSDCR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial port register Serial direction control register Figure 12.1 Block Diagram of SCI Rev. 4.00 Jul. 25, 2008 Page 412 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.2 Input/Output Pins The SCI has the serial pins summarized in table 12.1. Table 12.1 Pin Configuration Channel 0 Pin Name*1 SCK0 RXD0 TXD0 1 SCK1* RXD1 TXD1 2 SCK2 RXD2 TXD2 2 I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Notes: 1. Pin names SCK, RXD, and TXD are used in the description for all channels, omitting the channel designation. 2. This pin is supported only by the SH7125. Channel 1 in the SH7124 is only for asynchronous mode. Rev. 4.00 Jul. 25, 2008 Page 413 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3 Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each processing, see section 20, List of Registers. Table 12.2 Register Configuration Channel Register Name 0 Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Serial direction control register_0 Serial port register_0 1 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Serial direction control register_1 Serial port register_1 2 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Serial direction control register_2 Serial port register_2 Abbreviation SCSMR_0 SCBRR_0 SCSCR_0 SCTDR_0 SCSSR_0 SCRDR_0 R/W R/W R/W R/W  R/W  Initial Value H'00 H'FF H'00  H'84  H'F2 H'01 H'00 H'FF H'00  H'84  H'F2 H'01 H'00 H'FF H'00  H'84  H'F2 H'01 Address H'FFFFC000 H'FFFFC002 H'FFFFC004 H'FFFFC006 H'FFFFC008 H'FFFFC00A H'FFFFC00C H'FFFFC00E H'FFFFC080 H'FFFFC082 H'FFFFC084 H'FFFFC086 H'FFFFC088 H'FFFFC08A H'FFFFC08C H'FFFFC08E H'FFFFC100 H'FFFFC102 H'FFFFC104 H'FFFFC106 H'FFFFC108 H'FFFFC10A H'FFFFC10C H'FFFFC10E Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 SCSDCR_0 R/W SCSPTR_0 R/W SCSMR_1 SCBRR_1 SCSCR_1 SCTDR_1 SCSSR_1 SCRDR_1 R/W R/W R/W  R/W  SCSDCR_1 R/W SCSPTR_1 R/W SCSMR_2 SCBRR_2 SCSCR_2 SCTDR_2 SCSSR_2 SCRDR_2 R/W R/W R/W  R/W  SCSDCR_2 R/W SCSPTR_2 R/W Rev. 4.00 Jul. 25, 2008 Page 414 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.1 Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - 12.3.2 Receive Data Register (SCRDR) SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and completes operation. After that, SCRSR is ready to receive data. Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously. SCRDR is a read-only register and cannot be written to by the CPU. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: R R R R R R R R 12.3.3 Transmit Shift Register (SCTSR) SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, and then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to SCTSR directly. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Rev. 4.00 Jul. 25, 2008 Page 415 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.4 Transmit Data Register (SCTDR) SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be written or read to by the CPU. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W 12.3.5 Serial Mode Register (SCSMR) SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. Bit: 7 C/A 6 CHR 5 PE 4 O/E 3 STOP 2 MP 1 0 CKS[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name C/A Initial value 0 R/W R/W Description Communication Mode Selects whether the SCI operates in asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode (Channel 1 in the SH7124 is not available.) Rev. 4.00 Jul. 25, 2008 Page 416 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 6 Bit Name CHR Initial value 0 R/W R/W Description Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. 0: 8-bit data 1: 7-bit data 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. 4 O/E 0 R/W Parity mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity 1: Odd parity If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev. 4.00 Jul. 25, 2008 Page 417 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 3 Bit Name STOP Initial value 0 R/W R/W Description Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. 0: One stop bit* 1 2 1: Two stop bits* When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1 bits are added at the end of each transmitted character. 2 MP 0 R/W Multiprocessor Mode (only in asynchronous mode) Enables or disables multiprocessor mode. The PE and O/E bit settings are ignored in multiprocessor mode. 0: Multiprocessor mode disabled 1: Multiprocessor mode enabled 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 12.3.10, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: Pφ: Peripheral clock Rev. 4.00 Jul. 25, 2008 Page 418 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.6 Serial Control Register (SCSCR) SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt requests and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: 7 TIE 6 RIE 5 TE 4 RE 3 MPIE 2 TEIE 1 0 CKE[1:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name TIE Initial value 0 R/W R/W Description Transmit Interrupt Enable Enables or disables a transmit-data-empty interrupt (TXI) to be issued when the TDRE flag in the serial status register (SCSSR) is set to 1 after serial transmit data is sent from the transmit data register (SCTDR) to the transmit shift register (SCTSR). TXI can be canceled by clearing the TDRE flag to 0 after reading TDRE = 1 or by clearing the TIE bit to 0. 0: Transmit-data-empty interrupt request (TXI) is disabled 1: Transmit-data-empty interrupt request (TXI) is enabled 6 RIE 0 R/W Receive Interrupt Enable Enables or disables a receive-data-full interrupt (RXI) and a receive error interrupt (ERI) to be issued when the RDRF flag in SCSSR is set to 1 after the serial data received is transferred from the receive shift register (SCRSR) to the receive data register (SCRDR). RXI can be canceled by clearing the RDRF flag after reading RDRF =1. ERI can be canceled by clearing the FER, PER, or ORER flag to 0 after reading 1 from the flag. Both RXI and ERI can also be canceled by clearing the RIE bit to 0. 0: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled 1: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled Rev. 4.00 Jul. 25, 2008 Page 419 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 5 Bit Name TE Initial value 0 R/W R/W Description Transmit Enable Enables or disables the SCI serial transmitter. 0: Transmitter disabled* 1: Transmitter enabled* 1 2 Notes: 1. The TDRE flag in SCSSR is fixed at 1. 2. Serial transmission starts after writing transmit data into SCTDR and clearing the TDRE flag in SCSSR to 0 while the transmitter is enabled. Select the transmit format in the serial mode register (SCSMR) before setting TE to 1. 4 RE 0 R/W Receive Enable Enables or disables the SCI serial receiver. 0: Receiver disabled* 1: Receiver enabled* 1 2 Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clock synchronous mode. Select the receive format in SCSMR before setting RE to 1. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (only when MP = 1 in SCSMR in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped and setting of the RDRF, FER, and ORER status flags in SCSSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared to 0 and normal receiving operation is resumed. For details, see section 12.4.4, Multiprocessor Communication Function. Rev. 4.00 Jul. 25, 2008 Page 420 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name TEIE Initial value 0 R/W R/W Description Transmit End Interrupt Enable Enables or disables a transmit end interrupt (TEI) to be issued when no valid transmit data is found in SCTDR during MSB data transmission. TEI can be canceled by clearing the TEND flag to 0 (by clearing the TDRE flag in SCSSR to 0 after reading TDRE = 1) or by clearing the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled 1: Transmit end interrupt request (TEI) is enabled 1, 0 CKE[1:0] 00 R/W Clock Enable 1 and 0 Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. When selecting the clock output in clock synchronous mode, set the C/A bit in SCSMR to 1 and then set bits CKE1 and CKE0. For details on clock source selection, see table 12.14 in section 12.4, Operation. • Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored.) 01: Internal clock, SCK pin used for clock output* 10: External clock, SCK pin used for clock input* Clock synchronous mode 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate. 2 2 1 11: External clock, SCK pin used for clock input* Rev. 4.00 Jul. 25, 2008 Page 421 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.7 Serial Status Register (SCSSR) SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF, ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The TEND flag is a read-only bit and cannot be modified. Bit: 7 TDRE 6 RDRF 5 ORER 4 FER 3 PER 2 TEND 1 MPB 0 MPBT Initial value: 1 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 1 R 0 R 0 R/W Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 7 Bit Name TDRE Initial value 1 R/W Description R/(W)* Transmit Data Register Empty Indicates whether data has been transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR) and SCTDR has become ready to be written with next serial transmit data. 0: Indicates that SCTDR holds valid transmit data [Clearing condition] • When 0 is written to TDRE after reading TDRE = 1 1: Indicates that SCTDR does not hold valid transmit data [Setting conditions] • • • By a power-on reset or in standby mode When the TE bit in SCSCR is 0 When data is transferred from SCTDR to SCTSR and data can be written to SCTDR Rev. 4.00 Jul. 25, 2008 Page 422 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 6 Bit Name RDRF Initial value 0 R/W Description R/(W)* Receive Data Register Full Indicates that the received data is stored in the receive data register (SCRDR). 0: Indicates that valid received data is not stored in SCRDR [Clearing conditions] • • By a power-on reset or in standby mode When 0 is written to RDRF after reading RDRF = 1 1: Indicates that valid received data is stored in SCRDR [Setting condition] • When serial reception ends normally and receive data is transferred from SCRSR to SCRDR Note: SCRDR and the RDRF flag are not affected and retain their previous states even if an error is detected during data reception or if the RE bit in the serial control register (SCSCR) is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the received data will be lost. Rev. 4.00 Jul. 25, 2008 Page 423 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial value 0 R/W Description R/(W)* Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully*1 [Clearing conditions] • • By a power-on reset or in standby mode When 0 is written to ORER after reading ORER = 1 1: Indicates that an overrun error occurred during reception*2 [Setting condition] • When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR, and the data received subsequently is lost. Subsequent serial reception cannot be continued while the ORER flag is set to 1. Rev. 4.00 Jul. 25, 2008 Page 424 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 4 Bit Name FER Initial value 0 R/W Description R/(W)* Framing Error Indicates that a framing error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was 1 completed successfully* [Clearing conditions] • • By a power-on reset or in standby mode When 0 is written to FER after reading FER = 1 1: Indicates that a framing error occurred during reception [Setting condition] • When the SCI founds that the stop bit at the end of the received data is 0 after completing reception*2 Notes: 1. The FER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the FER flag is set to 1. Rev. 4.00 Jul. 25, 2008 Page 425 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial value 0 R/W Description R/(W)* Parity Error Indicates that a parity error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was 1 completed successfully* [Clearing conditions] • • By a power-on reset or in standby mode When 0 is written to PER after reading PER = 1 1: Indicates that a parity error occurred during 2 reception* [Setting condition] • When the number of 1s in the received data and parity does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. The PER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the PER flag is set to 1. Rev. 4.00 Jul. 25, 2008 Page 426 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name TEND Initial value 1 R/W R Description Transmit End Indicates that no valid data was in SCTDR during transmission of the last bit of the transmit character and transmission has ended. The TEND flag is read-only and cannot be modified. 0: Indicates that transmission is in progress [Clearing condition] • When 0 is written to TDRE after reading TDRE = 1 1: Indicates that transmission has ended [Setting conditions] • • • By a power-on reset or in standby mode When the TE bit in SCSCR is 0 When TDRE = 1 during transmission of the last bit of a 1-byte serial transmit character 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit found in the receive data. When the RE bit in SCSCR is cleared to 0, its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer Specifies the multiprocessor bit value to be added to the transmit frame. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Rev. 4.00 Jul. 25, 2008 Page 427 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.8 Serial Port Register (SCSPTR) SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the SCI function pins. Data to be output through the TXD pin can be specified to control break of serial transfer. Through bits 3 and 2, data reading and writing through the SCK pin can be specified. Bit 7 enables or disables RXI interrupts. The CPU can always read and write to SCSPTR. When reading the value on the SCI pins, use the respective port register. For details, see section 16, I/O Ports. Bit: 7 EIO 6 - 5 - 4 - 3 2 1 - 0 SPB0DT SPB1IO SPB1DT Initial value: 0 R/W: R/W 0 - 0 - 0 - 0 R/W 0 R/W 0 - 1 W Bit 7 Bit Name EIO Initial value 0 R/W R/W Description Error Interrupt Only Enables or disables RXI interrupts. While the EIO bit is set to 1, the SCI does not request an RXI interrupt to the CPU even if the RIE bit is set to 1. 0: The RIE bit enables or disables RXI and ERI interrupts. While the RIE bit is 1, RXI and ERI interrupts are sent to the INTC. 1: While the RIE bit is 1, only the ERI interrupt is sent to the INTC. 6 to 4  All 0  Reserved These bits are always read as 0. The write value should always be 0. 3 SPB1IO 0 R/W Clock Port Input/Output in Serial Port Specifies the input/output direction of the SCK pin in the serial port. To output the data specified in the SPB1DT bit through the SCK pin as a port output pin, set the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0. 0: Does not output the SPB1DT bit value through the SCK pin. 1: Outputs the SPB1DT bit value through the SCK pin. Rev. 4.00 Jul. 25, 2008 Page 428 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Bit 2 Bit Name SPB1DT Initial value 0 R/W R/W Description Clock Port Data in Serial Port Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin. 0: Low level is output 1: High level is output 1  0  Reserved This bit is always read as 0. The write value should always be 0. 0 SPB0DT 1 W Serial Port Break Data Controls the TXD pins together with the TE bit in SCSCR. However, the TXD pin function should be selected with the Pin Function Controller (PFC). This bit is write-only bit. Undefined value is read. Setting value of TE bit in SCSCR 0 0 1 Setting value of SPB0DT bit 0 1 * TXD pin state Low output High output (initial state) Transmit data output in accord with serial core logic. Note: * Don't care Rev. 4.00 Jul. 25, 2008 Page 429 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.9 Serial Direction Control Register (SCSDCR) The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. Bit: 7 - 6 - 5 - 4 - 3 DIR 2 - 1 - 0 - Initial value: R/W: 1 R 1 R 1 R 1 R 0 R/W 0 R 1 R 0 R Bit Bit Name Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 7 to 4  3 DIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: SCTDR contents are transmitted in LSB-first order Receive data is stored in SCRDR in LSB-first 1: SCTDR contents are transmitted in MSB-first order Receive data is stored in SCRDR in MSB-first 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1  1 R Reserved This bit is always read as 1. The write value should always be 1. 0  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 430 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.3.10 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. The SCBRR setting is calculated as follows: Bit: 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W • Asynchronous mode: N= Pφ × 106 - 1 64 × 22n-1 × B • Clock synchronous mode: N= Pφ × 106 - 1 8 × 22n-1 × B B: N: Bit rate (bits/s) SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting value should satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 12.3.) Rev. 4.00 Jul. 25, 2008 Page 431 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.3 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source Pφ Pφ/4 Pφ/16 Pφ/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Note: The bit rate error in asynchronous is given by the following formula: Error (%) = Pφ × 106 -1 (N + 1) × B × 64 × 22n-1 × 100 Rev. 4.00 Jul. 25, 2008 Page 432 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Tables 12.4 to 12.6 show examples of SCBRR settings in asynchronous mode, and tables 12.7 to 12.9 show examples of SCBRR settings in clock synchronous mode. Table 12.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) Pφ (MHz) Bit Rate (bits/s) n N 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 10 Error (% ) nN 12 Error (% ) nN 14 Error (% ) nN 16 Error (% ) n N 18 Error (% ) n N 20 Error (% ) 2 177 -0.25 2 129 0.16 2 64 0.16 2 212 0.03 2 155 0.16 2 77 0.16 2 248 -0.17 2 181 0.16 2 90 0.16 3 70 0.03 3 79 -0.12 3 88 3 64 -0.25 0.16 2 207 0.16 2 103 0.16 1 207 0.16 1 103 0.16 0 207 0.16 0 103 0.16 0 51 0 34 0 25 0 16 0 15 0 12 0.16 -0.79 0.16 2.12 0.00 0.16 2 233 0.16 2 116 0.16 1 233 0.16 1 116 0.16 0 233 0.16 0 116 0.16 0 58 0 38 0 28 0 19 0 17 0 14 -0.69 0.16 1.02 -2.34 0.00 -2.34 2 129 0.16 2 64 0.16 1 129 0.16 1 64 0.16 1 155 0.16 1 77 0.16 1 181 0.16 1 90 0.16 1 129 0.16 1 64 0.16 0 129 0.16 0 64 0 32 0 21 0 15 0 10 09 07 0.16 -1.36 -1.36 1.73 -1.36 0.00 1.73 0 155 0.16 0 77 0 38 0 25 0 19 0 12 0 11 09 0.16 0.16 0.16 -2.34 0.16 0.00 -2.34 0 181 0.16 0 90 0 45 0 29 0 22 0 14 0 13 0 10 0.16 -0.93 1.27 -0.93 1.27 0.00 3.57 0 129 0.16 0 64 0 42 0 32 0 21 0 19 0 15 0.16 0.94 -1.36 -1.36 0.00 1.73 Rev. 4.00 Jul. 25, 2008 Page 433 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) Pφ (MHz) Bit Rate (bits/s) n N 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 3 97 3 71 22 Error (% ) nN 24 Error (% ) nN 26 Error (% ) nN 28 Error (% ) n N 30 Error (% ) n N 32 Error (% ) -0.35 -0.54 3 106 -0.44 3 77 0.16 3 114 0.36 3 84 -0.43 3 123 0.23 3 90 0.16 3 132 0.13 3 97 -0.35 3 141 0.03 3 103 0.16 2 207 0.16 2 103 0.16 1 207 0.16 1 103 0.16 0 207 0.16 0 103 0.16 0 68 0 51 0 34 0 31 0 25 0.64 0.16 -0.79 0.00 0.16 2 142 0.16 2 71 -0.54 2 155 0.16 2 77 0.16 2 168 0.16 2 84 -0.43 2 181 0.16 2 90 0.16 2 194 0.16 2 97 -0.35 1 142 0.16 1 71 -0.54 1 155 0.16 1 77 0.16 1 168 0.16 1 84 -0.43 1 181 0.16 1 90 0.16 1 194 0.16 1 97 -0.35 0 142 0.16 0 71 0 47 0 35 0 23 0 21 0 17 -0.54 -0.54 -0.54 -0.54 0.00 -0.54 0 155 0.16 0 77 0 51 0 38 0 25 0 23 0 19 0.16 0.16 0.16 0.16 0.00 -2.34 0 168 0.16 0 84 0 55 0 41 0 27 0 25 0 20 -0.43 0.76 0.76 0.76 0.00 0.76 0 181 0.16 0 90 0 60 0 45 0 29 0 27 0 22 0.16 -0.39 -0.93 1.27 0.00 -0.93 0 194 0.16 0 97 0 64 0 48 0 32 0 29 0 23 -0.35 0.16 -0.35 -1.36 0.00 1.73 Rev. 4.00 Jul. 25, 2008 Page 434 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) Pφ (MHz) Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 3 3 2 2 1 1 0 0 0 0 0 0 0 34 Error N (% ) n N 36 Error (% ) n N 38 Error (% ) n N 40 Error (% ) 150 110 220 110 220 110 220 110 73 54 36 33 27 -0.05 -0.29 0.16 -0.29 0.16 -0.29 0.16 -0.29 -0.29 0.62 -0.29 0.00 -1.18 3 3 2 2 1 1 0 0 0 0 0 0 0 159 116 233 116 233 116 233 116 77 58 38 35 28 -0.12 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 0.16 0.00 1.02 3 3 2 2 1 1 0 0 0 0 0 0 0 168 123 246 123 246 123 246 123 81 61 40 37 30 -0.19 -0.24 0.16 -0.24 0.16 -0.24 0.16 -0.24 0.57 -0.24 0.57 0.00 -0.24 3 3 3 2 2 1 1 0 0 0 0 0 0 177 129 64 129 64 129 64 129 86 64 42 39 32 -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.22 0.16 0.94 0.00 -1.36 Rev. 4.00 Jul. 25, 2008 Page 435 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) Pφ (MHz) Bit Rate (bits/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 10 n 3 3 2 1 1 0 0 0 0 0 0  0 N 155 77 155 249 124 249 99 49 24 9 4  0* n 3 3 2 2 1 1 0 0 0 0 0 0   12 N 187 93 187 74 149 74 119 59 29 11 5 2   n 3 3 2 2 1 1 0 0 0 0 0    14 N 218 108 218 87 174 87 139 69 34 13 6    n 3 3 2 2 1 1 0 0 0 0 0 0   16 N 249 124 249 99 199 99 159 79 39 15 7 3   3 3 2 1 1 0 0 0 0 0    140 69 112 224 112 179 89 44 17 8    3 3 2 1 1 0 0 0 0 0 0 0 0 155 77 124 249 124 199 99 49 19 9 4 1 0* n 18 N n 20 N Rev. 4.00 Jul. 25, 2008 Page 436 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) Pφ (MHz) Bit Rate (bits/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 3 3 2 2 1 0 0 0 0 0    171 85 137 68 137 219 109 54 21 10    3 3 2 2 1 0 0 0 0 0 0   187 93 149 74 149 239 119 59 23 11 5   3 3 2 2 1 1 0 0 0 0    202 101 162 80 162 64 129 64 25 12    3 3 2 2 1 1 0 0 0 0 0   218 108 174 87 174 69 139 69 27 13 6   3 3 2 2 1 1 0 0 0 0  0  233 116 187 93 187 74 149 74 29 14  2  3 3 2 2 1 1 0 0 0 0 0   249 124 199 99 199 79 159 79 31 15 7   22 n N n 24 N n 26 N n 28 N n 30 N n 32 N Rev. 4.00 Jul. 25, 2008 Page 437 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) Pφ (MHz) Bit Rate (bits/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 3 2 2 1 1 0 0 0 0    132 212 105 212 84 169 84 33 16    3 2 2 1 1 0 0 0 0 0   140 224 112 224 89 179 89 35 17 8   3 2 2 1 1 0 0 0 0    147 237 118 237 94 189 94 37 18    3 2 2 1 1 0 0 0 0 0 0 0 155 249 124 249 99 199 99 39 19 9 3 1 34 n N n 36 N n 38 N n 40 N [Legend] Blank: No setting possible : Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended. Rev. 4.00 Jul. 25, 2008 Page 438 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 12.11 and 12.12 list the maximum rates for external clock input. Table 12.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Maximum Bit Rate (bits/s) 312500 375000 437500 500000 562500 625000 687500 750000 812500 875000 937500 1000000 1062500 1125000 1187500 1250000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev. 4.00 Jul. 25, 2008 Page 439 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 External Input Clock (MHz) 2.5000 3.0000 3.5000 4.0000 4.5000 5.0000 5.5000 6.0000 6.5000 7.0000 7.5000 8.0000 8.5000 9.0000 9.5000 10.0000 Maximum Bit Rate (bits/s) 156250 187500 218750 250000 281250 312500 343750 375000 406250 437500 468750 500000 531250 562500 593750 625000 Rev. 4.00 Jul. 25, 2008 Page 440 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) Pφ (MHz) 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 External Input Clock (MHz) 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 3.6667 4.0000 4.3333 4.6667 5.0000 5.3333 5.6667 6.0000 6.3333 6.6667 Maximum Bit Rate (bits/s) 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 3666666.7 4000000.0 4333333.3 4666666.7 5000000.0 5333333.3 5666666.7 6000000.0 6333333.3 6666666.7 Rev. 4.00 Jul. 25, 2008 Page 441 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.4 12.4.1 Operation Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous or clock synchronous mode is selected and the transmit format is specified in the serial mode register (SCSMR) as shown in table 12.13. The SCI clock source is selected by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in the serial control register (SCSCR) as shown in table 12.14. (1) Asynchronous Mode (Channels 0 to 2 in the SH7125, Channels 0 to 2 in the SH7124) • Data length is selectable: 7 or 8 bits. • Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length. • In receiving, it is possible to detect framing errors, parity errors, overrun errors, and breaks. • An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the clock supplied by the onchip baud rate generator and can output a clock with a frequency 16 times the bit rate.  When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clock Synchronous Mode (Channels 0 to 2 in the SH7125, Channels 0 and 2 in the SH7124) • The transmission/reception format has a fixed 8-bit data length. • In receiving, it is possible to detect overrun errors. • An internal or external clock can be selected as the SCI clock source.  When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices.  When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev. 4.00 Jul. 25, 2008 Page 442 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Table 12.13 SCSMR Settings and SCI Communication Formats SCSMR Settings Bit 7 Bit 6 Bit 5 Bit 3 C/A CHR PE STOP Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 x x x Clock synchronous 8-bit Not set Set 7-bit Not set Set Asynchronous SCI Communication Format Data Length 8-bit Parity Bit Not set Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None [Legend] x: Don't care Table 12.14 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings Bit 7 C/A 0 Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clock synchronous Mode Clock Source SCK Pin Function SCI does not use the SCK pin. Clock with a frequency 16 times the bit rate is output. External Input a clock with frequency 16 times the bit rate. Internal Serial clock is output. Asynchronous Internal External Input the serial clock. Rev. 4.00 Jul. 25, 2008 Page 443 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idle state (mark state) 1 0/1 Parity bit 1 bit or none 1 1 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Stop bit Transmit/receive data 7 or 8 bits One unit of transfer data (character or frame) 1 or 2 bits Figure 12.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) Rev. 4.00 Jul. 25, 2008 Page 444 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) (1) Transmit/Receive Formats Table 12.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR settings. Table 12.15 Serial Transfer Formats (Asynchronous Mode) SCSMR Settings CHR 0 PE 0 MP 0 STOP 0 1 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 11 12 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 x 1 0 S 8-bit data MPB STOP 0 x 1 1 S 8-bit data MPB STOP STOP 1 x 1 0 S 7-bit data MPB STOP 1 x 1 1 S 7-bit data MPB STOP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit x: Don't care Rev. 4.00 Jul. 25, 2008 Page 445 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 12.14). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate. (3) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receives data register (SCRDR), which retains their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Rev. 4.00 Jul. 25, 2008 Page 446 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Start initialization [1] [2] [3] Clear RIE, TIE, TEIE, MPIE, TE, and RE bits in SCSCR to 0* [4] Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Set data transfer format in SCSMR, SCSDCR [1] [2] Set value in SCBRR Wait [3] [5] No 1-bit interval elapsed? Yes Set the PFC for the external pins to be used (SCK, TXD, RXD) Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR Set the clock selection in SCSCR. Set the data transfer format in SCSMR and SCSDCR. Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. Set the TE bit or RE bit in SCSCR to 1.* Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting, and RXD pin is in an idle state for waiting the start bit during receiving. [4] [5] < Initialization completed> Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 12.3 Sample Flowchart for SCI Initialization Rev. 4.00 Jul. 25, 2008 Page 447 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Transmitting Serial Data (Asynchronous Mode): Figure 12.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission [1] SCI status check and transmit data write: Read TDRE flag in SCSSR No Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR, and clear the TDRE flag to 0. [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. [3] Break output at the end of serial transmission: To output a break in serial transmission, clear the SPB0DT bit to 0 and set the SPB0IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. TDRE = 1? Yes Write transmit data in SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Yes Read TEND flag in SCSSR No TEND = 1? Yes Break output? Yes Clear SPB0DT to 0 and set SPB0IO to 1 Clear TE bit in SCSCR to 0 No No End of transmission Figure 12.4 Sample Flowchart for Transmitting Serial Data Rev. 4.00 Jul. 25, 2008 Page 448 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. (A format in which neither parity nor multiprocessor bit is output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated. Rev. 4.00 Jul. 25, 2008 Page 449 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Figure 12.5 shows an example of the operation for transmission. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Serial data 1 Idle state (mark state) TDRE TEND TXI interrupt TXI interrupt request request Data written to SCTDR and TDRE flag cleared to 0 by TXI interrupt handler One frame TEI interrupt request Figure 12.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Rev. 4.00 Jul. 25, 2008 Page 450 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Receiving Serial Data (Asynchronous Mode): Figure 12.6 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. [1] Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can also be detected by reading the value of the RXD pin. [2] SCI status check and receive data read: Read RDRF flag in SCSSR No Read SCSSR and check that RDRF = 1, then read the receive data in SCRDR clear the RDRF flag to 0. [3] Serial reception continuation procedure: To continue serial reception, clear the RDRF flag to 0 before the stop bit for the current frame is received. Start of reception Read ORER, PER, and FER flags in SCSSR PER, FER, or ORER = 1? No Yes Error handling RDRF = 1? Yes Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception Figure 12.6 Sample Flowchart for Receiving Serial Data Rev. 4.00 Jul. 25, 2008 Page 451 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 No PER = 1? Yes Parity error processing Clear ORER, PER, and FER flags in SCSSR to 0 Figure 12.6 Sample Flowchart for Receiving Serial Data (cont) Rev. 4.00 Jul. 25, 2008 Page 452 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. A. Parity check: The SCI counts the number of 1s in the received data and checks whether the count matches the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). B. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. C. Status check: The SCI checks whether the RDRF flag is 0 and the received data can be transferred from the receive shift register (SCRSR) to SCRDR. If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in SCRDR. If a receive error is detected, the SCI operates as shown in table 12.16. Note: When a receive error occurs, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0. 4. If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Table 12.16 Receive Errors and Error Conditions Receive Error Overrun error Abbreviation ORER Error Condition When the next data reception is completed while the RDRF flag in SCSSR is set to 1 When the stop bit is 0 Data Transfer The received data is not transferred from SCRSR to SCRDR. The received data is transferred from SCRSR to SCRDR. The received data is transferred from SCRSR to SCRDR. Framing error FER Parity error PER When the received data does not match the even or odd parity specified in SCSMR Rev. 4.00 Jul. 25, 2008 Page 453 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Figure 12.7 shows an example of the operation for reception. 1 Serial data Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 0/1 RDRF FER RXI interrupt request One frame Data read and RDRF flag cleared to 0 by RXI interrupt handler ERI interrupt request generated by framing error Figure 12.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit) 12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available) In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 12.8 shows the general format in clock synchronous serial communication. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High level except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 12.8 Data Format in Clock Synchronous Communication Rev. 4.00 Jul. 25, 2008 Page 454 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. (1) Communication Format The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source, see table 12.14. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only reception is performed, the synchronous clock continues to be output until an overrun error occurs or the RE bit is cleared to 0. For the reception of n characters, select the external clock as the clock source. If the internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the same time as receiving the n characters of data. (3) Transmitting and Receiving Data SCI Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Rev. 4.00 Jul. 25, 2008 Page 455 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Figure 12.9 shows a sample flowchart for initializing the SCI. Start initialization [1] [2] Set the clock selection in SCSCR. Set the data transfer format in SCSMR. Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. Set the TE bit or RE bit in SCR to 1.* Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting. When synchronous clock output (clock master) is set during receiving in clock synchronous mode, outputting clocks from the SCK pin starts. Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCSCR to 0* [3] Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Set data transfer format in SCSMR [1] [4] [2] [5] Set value in SCBRR Wait [3] No 1-bit interval elapsed? Yes Set the PFC for the external pins to be used (SCK, TXD, RXD) Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR [4] [5] Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 12.9 Sample Flowchart for SCI Initialization Rev. 4.00 Jul. 25, 2008 Page 456 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Transmitting Serial Data (Clock Synchronous Mode): Figure 12.10 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR, and clear the TDRE flag to 0. [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Read TDRE flag in SCSSR No TDRE = 1? Yes Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted? Yes Read TEND flag in SCSSR No TEND = 1? Yes Clear TE bit in SCSCR to 0 No End of transmission Figure 12.10 Sample Flowchart for Transmitting Serial Data Rev. 4.00 Jul. 25, 2008 Page 457 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the transmit-data-empty interrupt enable bit (TIE) in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is started, If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the MSB (bit 7) is sent, and then the TXD pin holds the states. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 12.11 shows an example of SCI transmit operation. Transfer direction Synchronization clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to SCTDR TXI interrupt and TDRE flag cleared request request to 0 by TXI interrupt handler One frame TEI interrupt request Figure 12.11 Example of SCI Transmit Operation Rev. 4.00 Jul. 25, 2008 Page 458 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Receiving Serial Data (Clock Synchronous Mode): Figure 12.12 shows a sample flowchart for receiving serial data. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching from asynchronous mode to clock synchronous mode, make sure that the ORER, PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not be set and data reception cannot be started. [1] Receive error handling: Read the ORER flag in SCSSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [2] SCI status check and receive data read: Read SCSSR and check that RDRF = 1, then read the receive data in SCRDR, and clear the RDRF flag to 0. The transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: RDRF = 1? Yes Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception To continue serial reception, read the receive data register (SCRDR) and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Start of reception Read ORER flag in SCSSR ORER = 1? No Read RDRF flag in SCSSR No Yes Error handling Figure 12.12 Sample Flowchart for Receiving Serial Data (1) Rev. 4.00 Jul. 25, 2008 Page 459 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCSSR to 0 End Figure 12.12 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the received data in SCRDR. If a receive error is detected, the SCI operates as shown in table 12.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the RDRF flag to 0. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI). Rev. 4.00 Jul. 25, 2008 Page 460 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Figure 12.13 shows an example of SCI receive operation. Transfer direction Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt Data read from SCRDR and RXI interrupt request RDRF flag cleared to 0 by RXI request interrupt handler One frame ERI interrupt request by overrun error Figure 12.13 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure 12.14 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for serial data transmission and reception after enabling the SCI for transmission and reception. Rev. 4.00 Jul. 25, 2008 Page 461 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Start of transmission and reception [1] Read TDRE flag in SCSSR No TDRE = 1? [2] Yes Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SCSSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading SCRDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to SCTDR and clear the TDRE flag to 0. Read ORER flag in SCSSR Yes [3] ORER = 1? No Error processing [4] Read RDRF flag in SCSSR No RDRF = 1? Yes Write transmit data to SCTDR, and clear TDRE flag in SCSSR to 0 No All data received? Yes Clear TE and RE bits in SCSCR to 0 End of transmission and reception Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 12.14 Sample Flowchart for Transmitting/Receiving Serial Data Rev. 4.00 Jul. 25, 2008 Page 462 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.4.4 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCSCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from SCRSR to SCRDR, error flag detection, and setting the SCSSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPB bit in SCSSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCSCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 4.00 Jul. 25, 2008 Page 463 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 12.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 4.00 Jul. 25, 2008 Page 464 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.4.5 Multiprocessor Serial Data Transmission Figure 12.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission. Note that the MPBT bit must be held 1 until when an ID is transmitted. All other SCI operations are the same as those in asynchronous mode. Initialization Start transmission [1] [1] Read TDRE flag in SCSSR [2] [2] No SCI initialization: Set the TXD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR. Set the MPBT bit in SCSSR to 0 or 1. Finally, clear the TDRE flag to 0. After initializing the SCI, when an ID is written to SCTDR register so as to transmit the ID, data is immediately transferred, and then the TDER flag is set to 1. The MPBT bit must be held 1 because the ID is not transmitted from the TXD pin at this time. When the TDRE flag is set to 1 after data following the ID is written to SCTDR, clear the MPBT bit to 0. TDRE = 1? Yes Write transmit data to SCTDR and set MPBT bit in SCSSR Clear TDRE flag to 0 No All data transmitted? Yes [3] Read TEND flag in SCSSR [3] No TEND = 1? Yes No Break output? Yes [4] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. [4] Clear DR to 0 Clear TE bit in SCSCR to 0; select the TXD pin as an output port with the PFC Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR and use the PFC to select the TXD pin as an output port. Figure 12.16 Sample Multiprocessor Serial Transmission Flowchart Rev. 4.00 Jul. 25, 2008 Page 465 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.4.6 Multiprocessor Serial Data Reception Figure 12.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.18 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 Data (ID1) MPB D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0 1 RXD 1 1 Idle state (mark state) MPIE RDRF SCRDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated ID1 SCRDR data read If not this station’s ID, and RDRF flag MPIE bit is set to 1 cleared to 0 in again RXI interrupt processing routine RXI interrupt request is not generated, and SCRDR retains its state (a) Data does not match station’s ID 1 RXD Start bit 0 D0 Data (ID2) D1 D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF SCRDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Data2 Matches this station’s ID, MPIE bit is set to 1 so reception continues, again and data is received in RXI interrupt processing routine (b) Data matches station’s ID Figure 12.17 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 4.00 Jul. 25, 2008 Page 466 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: Set the RXD pin using the PFC. ID reception cycle: Set the MPIE bit in SCSCR to 1. SCI status check, ID reception and comparison: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. SCI status check and data reception: Read SCSSR and check that the RDRF flag is set to 1, then read the data in SCRDR. Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD pin value. [2] [2] Set MPIE bit in SCSCR to 1 Read ORER and FER flags in SCSSR [3] Yes FER = 1? or ORER = 1? No Read RDRF flag in SCSSR No RDRF = 1? Yes Read receive data in SCRDR No This station’s ID? Yes Read ORER and FER flags in SCSSR Yes FER = 1? or ORER = 1? No Read RDRF flag in SCSSR No RDRF = 1? Yes Read receive data in SCRDR No All data received? Yes Clear RE bit in SCSCR to 0 (Continued on next page) [4] [5] [3] [4] [5] Error processing Figure 12.18 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 4.00 Jul. 25, 2008 Page 467 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 Clear ORER and FER flags in SCSSR to 0 Figure 12.18 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 4.00 Jul. 25, 2008 Page 468 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.5 SCI Interrupt Sources The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI) interrupt requests. Table 12.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt request is generated. When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated. When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that transmission has been completed. Table 12.17 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Interrupt caused by receive error (ORER, FER, or PER) Interrupt caused by receive data full (RDRF) Interrupt caused by transmit data empty (TDRE) Interrupt caused by transmit end (TENT) Rev. 4.00 Jul. 25, 2008 Page 469 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.6 Serial Port Register (SCSPTR) and SCI Pins The relationship between SCSPTR and the SCI pins is shown in figures 12.19 and 12.20. Reset R Q D SCKIO C SPTRW Reset SCK R Q D SCKDT C SPTRW Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* Bit 2 Internal data bus Bit 3 SPTRW: Note: SCSPTR write * These signals control the SCK pin according to the settings of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. Figure 12.19 SPB1IO bit, SPB1DT bit, and SCK Pin Reset TXD R Q D SPBDT C SPTRW Bit 0 Internal data bus Transmit enable signal Serial transmit data SPTRW: SCSPTR write Figure 12.20 SPB0DT bit and TXD Pin Rev. 4.00 Jul. 25, 2008 Page 470 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.7 12.7.1 Usage Notes SCTDR Writing and TDRE Flag The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that the TDRE flag is set to 1. 12.7.2 Multiple Receive Error Occurrence If multiple receive errors occur at the same time, the status flags in SCSSR are set as shown in table 12.18. When an overrun error occurs, data is not transferred from the receive shift register (SCRSR) to the receive data register (SCRDR) and the received data will be lost. Table 12.18 SCSSR Status Flag Values and Transfer of Received Data Receive Data Transfer from SCRSR to SCRDR Not transferred Transferred Transferred Not transferred Not transferred Transferred Not transferred SCSSR Status Flags Receive Errors Generated Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Rev. 4.00 Jul. 25, 2008 Page 471 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.7.3 Break Detection and Processing Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of received data to SCRDR is halted in the break state, the SCI receiver continues to operate. 12.7.4 Sending a Break Signal The I/O condition and level of the TXD pin are determined by the SPB0DT bit in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPB0DT bit. Therefore, the SPB0DT bit should be set to 1 at first (high level output). To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin. 12.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 12.21. Rev. 4.00 Jul. 25, 2008 Page 472 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks Receive data (RXD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = (0.5 D - 0.5 1 ) - (L - 0.5) F (1+F) × 100 % 2N N Where: M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 4.00 Jul. 25, 2008 Page 473 of 750 REJ09B0243-0400 Section 12 Serial Communication Interface (SCI) 12.7.6 Note on Using External Clock in Clock Synchronous Mode TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock after the SCK external clock is changed from 0 to 1. TE and RE must be set to 1 only while the SCK external clock is 1. 12.7.7 Module Standby Mode Setting SCI operation can be disabled or enabled using the standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, see section 19, Power-Down Modes. Rev. 4.00 Jul. 25, 2008 Page 474 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Section 13 A/D Converter (ADC) This LSI includes a successive approximation type 10-bit A/D converter. 13.1 Features • 10-bit resolution • Input channels  8 channels (two independent A/D conversion modules) • Conversion time: 2.0 µs per channel (preliminary value, operation when Pφ = 25 MHz) • Three operating modes  Single mode: Single-channel A/D conversion  Continuous scan mode: Repetitive A/D conversion on up to four channels  Single-cycle scan mode: Continuous A/D conversion on up to four channels • Data registers  Conversion results are held in a 16-bit data register for each channel • Sample-and-hold function • Three methods for conversion start  Software  Conversion start trigger from multifunction timer pulse unit 2 (MTU2)  External trigger signal • Interrupt request  An A/D conversion end interrupt request (ADI) can be generated • Module standby mode can be set ADCMS20C_000020020700 Rev. 4.00 Jul. 25, 2008 Page 475 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Figure 13.1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRm ADDRn ADCSR ADTSR ADCR • • • Internal data bus AVCC 10-bit D/A AVSS Successive approximations register + ANm • Pφ Pφ/2 Comparator Multiplexer Control circuit • • • • • Pφ/3 Pφ/4 Sample-andhold circuit ANn ADI interrupt signal Conversion start trigger from MTU2 ADTRG [Legend] ADCR: ADCSR: ADTSR: ADDRm to ADDRn: A/D control register A/D control/status register A/D trigger select register A/D data registers m to n Note: The register number corresponds to the channel number of the module. (m to n = 0 to 7) Figure 13.1 Block Diagram of A/D Converter (for One Module) Rev. 4.00 Jul. 25, 2008 Page 476 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.2 Input/Output Pins Table 13.1 summarizes the input pins used by the A/D converter. This LSI has two A/D conversion modules, each of which can be operated independently. The input channels of A/D modules 0 and 1 are divided into two channel groups. Table 13.1 Pin Configuration Module Type Common Symbol AVCC AVSS ADTRG A/D module 0 (A/D_0) AN0 AN1 AN2 AN3 A/D module 1 (A/D_1) AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply and reference voltage Analog block ground and reference voltage A/D external trigger input pin* Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Group 1 Group 0 Group 1 Group 0 Notes: The connected A/D module differs for each pin. The control registers of each module must be set. * This pin is supported only by the SH7125. Rev. 4.00 Jul. 25, 2008 Page 477 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.3 Register Descriptions The A/D converter has the following registers. For details on register addresses and register states in each processing state, refer to section 20, List of Registers. Table 13.2 Register Configuration Register Name A/D data register 0 A/D data register 1 A/D data register 2 A/D data register 3 A/D control/status register_0 A/D control register_0 A/D data register 4 A/D data register 5 A/D data register 6 A/D data register 7 A/D control/status register_1 A/D control register_1 A/D trigger select register_0 Abbreviation ADDR0 ADDR1 ADDR2 ADDR3 ADCSR_0 ADCR_0 ADDR4 ADDR5 ADDR6 ADDR7 ADCSR_1 ADCR_1 ADTSR_0 R/W R R R R R/W R/W R R R R R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFFC900 H'FFFFC902 H'FFFFC904 H'FFFFC906 H'FFFFC910 H'FFFFC912 H'FFFFC980 H'FFFFC982 H'FFFFC984 H'FFFFC986 H'FFFFC990 H'FFFFC992 H'FFFFE890 Access Size 16 16 16 16 16 16 16 16 16 16 16 16 8, 16 Rev. 4.00 Jul. 25, 2008 Page 478 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is stored in ADDR4.) The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 16 bits wide. When reading from ADDR, access must be performed in words. The initial value of ADDR is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 13.3.2 A/D Control/Status Registers_0 and _1 (ADCSR_0 and ADCSR_1) ADCSR for each module controls A/D conversion operations. Bit: 15 ADF 14 ADIE 13 - 12 - 11 TRGE 10 - 9 CONADF 8 STC 7 6 5 4 3 ADCS 2 1 CH[2:0] 0 CKSL[1:0] ADM[1:0] Initial value: 0 0 R/W: R/(W)* R/W 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit 15 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • • When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 [Clearing condition] • Rev. 4.00 Jul. 25, 2008 Page 479 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Bit 14 Bit Name ADIE Initial Value 0 R/W R/W Description A/D Interrupt Enable The A/D conversion end interrupt (ADI) request is enabled when 1 is set When changing the operating mode, first clear the ADST bit to 0. 13, 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 TRGE 0 R/W Trigger Enable Enables or disables triggering of A/D conversion by ADTRG and an MTU2 trigger. 0: A/D conversion triggering is disabled 1: A/D conversion triggering is enabled When changing the operating mode, first clear the ADST bit to 0. 10  0 R Reserved This bit is always read as 0. The write value should always be 0. 9 CONADF 0 R/W ADF Control Controls setting of the ADF bit in 2-channel scan mode. The setting of this bit is valid only when triggering of A/D conversion is enabled (TRGE = 1) in 2-channel scan mode. The setting of this bit is ignored in single mode or 4-channel scan mode. 0: The ADF bit is set when A/D conversion started by the group 0 trigger or group 1 trigger has finished. 1: The ADF bit is set when A/D conversion started by the group 0 trigger and A/D conversion started by the group 1 trigger have both finished. Note that the triggering order has no affect. When changing the operating mode, first clear the ADST bit to 0. Rev. 4.00 Jul. 25, 2008 Page 480 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Bit 8 Bit Name STC Initial Value 0 R/W R/W Description State Control Sets the A/D conversion time in combination with the CKSL1 and CKSL0 bits. 0: 50 states 1: 64 states When changing the A/D conversion time, first clear the ADST bit to 0. 7, 6 CKSL[1:0] 00 R/W Clock Select 1 and 0 Select the A/D conversion time. 00: Pφ/4 01: Pφ/3 10: Pφ/2 11: Pφ When changing the A/D conversion time, first clear the ADST bit to 0. CKSL[1:0] = B'11 can be set while Pφ ≤ 25 MHz. 5, 4 ADM[1:0] 00 R/W A/D Mode 1 and 0 Select the A/D conversion mode. 00: Single mode 01: 4-channel scan mode 10: Setting prohibited 11: 2-channel scan mode When changing the operating mode, first clear the ADST bit to 0. 3 ADCS 0 R/W A/D Continuous Scan Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. 0: Single-cycle scan 1: Continuous scan When changing the operating mode, first clear the ADST bit to 0. Rev. 4.00 Jul. 25, 2008 Page 481 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Bit 2 to 0 Bit Name CH[2:0] Initial Value 000 R/W R/W Description Channel Select 2 to 0 Select analog input channels. See table 13.3. When changing the operating mode, first clear the ADST bit to 0. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 13.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ADCR for each module controls A/D conversion. Bit: 15 - 14 - 13 ADST 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15, 14 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 ADST 0 R/W A/D Start Starts or stops A/D conversion. When this bit is set to 1, A/D conversion is started. When this bit is cleared to 0, A/D conversion is stopped and the A/D converter enters the idle state. In single or single-cycle scan mode, this bit is automatically cleared to 0 when A/D conversion ends on the selected single channel. In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode or module standby mode. 12 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 482 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Table 13.3 Channel Select List Analog Input Channels Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 A/D_0 AN0 AN1 AN2 AN3 Setting prohibited Single Mode A/D_1 AN4 AN5 AN6 AN7 Setting prohibited A/D_0 AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 Setting prohibited 4-Channel Scan Mode* A/D_1 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Setting prohibited Analog Input Channels Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 A/D_0 AN0 AN0, AN1 AN2 AN2, AN3 Setting prohibited 2-Channel Scan Mode* (Activated by software) A/D_1 AN4 AN4, AN5 AN6 AN6, AN7 Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 483 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Analog Input Channels Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 A/D_0 Group 0: AN0 Group 1: AN2 Group 0: AN0, AN1 Group 1: AN2, AN3 Setting prohibited 2-Channel Scan Mode* (Activated by Triggers MTU2 or etc.) A/D_1 Group 0: AN4 Group 1: AN6 Group 0: AN4, AN5 Group 1: AN6, AN7 Setting prohibited Note: * Continuous scan mode or single-scan mode can be selected with the ADCS bit. Rev. 4.00 Jul. 25, 2008 Page 484 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.3.4 A/D Trigger Select Register_0 (ADTSR_0) The ADTSR_0 enables an A/D conversion started by an external trigger signal. In particular, the four channels in A/D module 0 are divided into two groups (group 0 and group 1) and the A/D trigger can be specified for each group independently in 2-channel scan mode. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRG11S[3:0] TRG01S[3:0] TRG1S[3:0] TRG0S[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W R/W Description A/D Trigger 1 Group 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 1 when A/D module 1 is in 2channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. 15 to 12 TRG11S[3:0] 0000 Rev. 4.00 Jul. 25, 2008 Page 485 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Bit 11 to 8 Bit Name Initial Value R/W R/W Description A/D Trigger 0 Group 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 1 when A/D module 0 is in 2channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. TRG01S[3:0] 0000 Rev. 4.00 Jul. 25, 2008 Page 486 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Bit 7 to 4 Bit Name TRG1S[3:0] Initial Value 0000 R/W R/W Description A/D Trigger 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 0 when A/D module 1 is in single mode, 4-channel scan mode, or 2-channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. Rev. 4.00 Jul. 25, 2008 Page 487 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Bit 3 to 0 Bit Name TRG0S[3:0] Initial Value 0000 R/W R/W Description A/D Trigger 0 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 0 when A/D module 0 is in single mode, 4-channel scan mode, or 2-channel scan mode. 0000: External trigger pin (ADTRG) input 0001: TRGA input capture/compare match for each MTU2 channel or TCNT_4 underflow (trough) in complementary PWM mode (TRGAN) 0010: MTU2 channel 0 compare match (TRG0N) 0011: MTU2 A/D conversion start request delaying (TRG4AN) 0100: MTU2 A/D conversion start request delaying (TRG4BN) 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1xxx: Setting prohibited When switching the selector, first clear the ADST bit in the A/D control register (ADCR) to 0. Specify different trigger sources for the group 0 and group 1 conversion requests so that a group 0 conversion request is not generated simultaneously with a group 1 conversion request in 2-channel scan mode. [Legend] x: Don't care Rev. 4.00 Jul. 25, 2008 Page 488 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. 13.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU2, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D converion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. 13.4.2 Continuous Scan Mode In continuous scan mode, A/D conversion is to be performed sequentially on the specified channels. 1. When the ADST bit in ADCR is set to 1 by software, MTU2, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN3). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. Rev. 4.00 Jul. 25, 2008 Page 489 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.4.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (up to four channels). 1. When the ADST bit in ADCR is set to 1 by a software, MTU2, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN3). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. 13.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCR is set to 1, then starts conversion. Figure 13.2 shows the A/D conversion timing. Table 13.4 shows the A/D conversion time. As indicated in figure 13.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total conversion time therefore varies within the ranges indicated in table 13.4. In scan mode, the values given in table 13.4 apply to the first conversion time. The values given in table 13.5 apply to the second and subsequent conversions. Rev. 4.00 Jul. 25, 2008 Page 490 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) A/D conversion time (tCONV) Analog input A/D conversion start sampling time(tSPL) delay time(tD) Write cycle A/D synchronization time (2 states) (Up to 6 states) Pφ Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle state Sample-and-hold A/D conversion ADF End of A/D conversion Figure 13.2 A/D Conversion Timing Rev. 4.00 Jul. 25, 2008 Page 491 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Table 13.4 A/D Conversion Time (Single Mode) STC = 0 CKSL1 = 0 CKSL0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. Typ. Max. 2  202  24  6  206 CKSL0 = 1 Min. Typ. Max. 2  152  18  5  155 CKSL1 = 1 CKSL0 = 0 Min. Typ. Max. 2  102  12  4  104 CKSL0 = 1 Min. Typ. Max. 2  52  6  3  53 STC = 1 CKSL1 = 0 CKSL0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min. Typ. Max. 2  258  36  6  262 CKSL0 = 1 Min. Typ. Max. 2  194  27  5  197 CKSL1 = 1 CKSL0 = 0 Min. Typ. Max. 2  130  18  4  132 CKSL0 = 1 Min. Typ. Max. 2  66  9  3  67 Note: All values represent the number of states for Pφ. Table 13.5 A/D Conversion Time (Scan Mode) Conversion Time (State) 200 (Fixed) 150 (Fixed) 100 (Fixed) 50 (Fixed) 256 (Fixed) 192 (Fixed) 128 (Fixed) 64 (Fixed) Conversion Time Calculation Example Pφ = 25 MHz 8 µs 6 µs 4 µs 2 µs 10.2 µs 7.7 µs 5.1 µs 2.6 µs Pφ = 40 MHz 5 µs 3.8 µs 2.5 µs Setting prohibited 6.4 µs 4.8 µs 3.2 µs Setting prohibited STC 0 CKSL1 0 CKSL0 0 1 1 0 1 1 0 0 1 1 0 1 Rev. 4.00 Jul. 25, 2008 Page 492 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.4.5 A/D Converter Activation by MTU2 The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU2. To activate the A/D converter by the MTU2, first set the TRGE bit in the A/D control/status register (ADCSR) to 1, and then set the A/D trigger select register (ADTSR). After this register setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D conversion request from the interval timer of the MTU2 occurs. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 13.4.6 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit in the A/D control/status register (ADCSR) is set to 1 while the TRGS3 to TRGS0 bits in the A/D trigger select register_0 (ADTSR_0) is set to external trigger input, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 13.3 shows the timing. CK ADTRG External trigger signal ADST A/D conversion Figure 13.3 External Trigger Input Timing Rev. 4.00 Jul. 25, 2008 Page 493 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.4.7 2-Channel Scanning In 2-channel scan mode, since the four channels of analog input are divided into groups 0 and 1, triggers for activation of groups 0 and 1 are independently specifiable. Conversion end interrupts in 2-channel scan mode can be generated either on completion of group 0 or group 1 or on completion of group 0 and group 1. If conversion is to be started by triggers, the different sources for groups 0 and 1 are specified in ADTSR. A request for conversion by group 1 generated during conversion by group 0 is ignored. Figure 13.4 shows an example of operation when TRG4AN of the MTU2 has been specified as the A/D conversion start request by group 0 and TRG4BN of the MTU2 has been specified as the A/D conversion start request by group 1. TGRA_3 TADCORA_4 TCNT_4 TADCORB_4 H'0000 A/D conversion start request AN0 AN1 AN2 AN3 conversion conversion conversion conversion A/D conversion end (ADF) CONADF bit in ADCSR = 0 CONADF bit in ADCSR = 1 Figure 13.4 Example of 2-Channel Scanning Rev. 4.00 Jul. 25, 2008 Page 494 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.5 Interrupt Sources The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. Table 13.6 A/D Converter Interrupt Source Name ADI0 ADI1 Interrupt Source A/D_0 conversion completed A/D_1 conversion completed Interrupt Source Flag ADF in ADCSR_0 ADF in ADCSR_1 Rev. 4.00 Jul. 25, 2008 Page 495 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.6 Definitions of A/D Conversion Accuracy This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.5). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 13.6). • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 13.6). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error (see figure 13.6). • Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 4.00 Jul. 25, 2008 Page 496 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 13.5 Definitions of A/D Conversion Accuracy Rev. 4.00 Jul. 25, 2008 Page 497 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 13.6 Definitions of A/D Conversion Accuracy Rev. 4.00 Jul. 25, 2008 Page 498 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.7 13.7.1 Usage Notes Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes. 13.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 kΩ, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater) (see figure 13.7). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 13.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere in the accuracy by the printed circuit digital signals on the mounting board (i.e, acting as antennas). Rev. 4.00 Jul. 25, 2008 Page 499 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Sensor output impedance of up to 3 kΩ or up to 1 kΩ Sensor input Low-pass filter C to 0.1 µF This LSI A/D converter equivalent circuit 10 kΩ Cin = 20 pF 20 pF Figure 13.7 Example of Analog Input Circuit 13.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ VAN ≤ AVref. • Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 13.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. Rev. 4.00 Jul. 25, 2008 Page 500 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) 13.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN7), between AVcc and AVss, as shown in figure 13.8. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN7 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. AVcc Rin *2 *1 100 Ω AN0 to AN7 0.1 µF AVss Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 13.8 Example of Analog Input Protection Circuit Table 13.7 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min.    Max. 20 3 1 Unit pF kΩ kΩ Condition  Conversion time ≥ 4.0 µs Conversion time < 4.0 µs Rev. 4.00 Jul. 25, 2008 Page 501 of 750 REJ09B0243-0400 Section 13 A/D Converter (ADC) Rev. 4.00 Jul. 25, 2008 Page 502 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) Section 14 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals. 14.1 Features • Selection of four counter input clocks Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected independently for each channel. • Interrupt request on compare match • Module standby mode can be set. Figure 14.1 shows a block diagram of CMT. Pφ/32 Pφ/512 Pφ/128 Pφ/32 Pφ/512 Pφ/128 CMI0 Pφ/8 CMI1 Pφ/8 Control circuit Clock selection Control circuit Clock selection Comparator Comparator CMCOR_0 CMCOR_1 CMCSR_0 CMCSR_1 CMCNT_0 Channel 0 Module bus CMT [Legend] CMSTR: CMCSR: CMCOR: CMCNT: CMI: CMCNT_1 CMSTR Channel 1 Bus interface Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match counter Compare match interrupt Figure 14.1 Block Diagram of CMT TIMCMT3A_000020030900 Rev. 4.00 Jul. 25, 2008 Page 503 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.2 Register Descriptions The CMT has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Note that the channel number is omitted from the register name in this section. Table 14.1 Register Configuration Register Name Compare match timer start register Compare match timer control/status register_0 Compare match counter_0 Compare match constant register_0 Compare match timer control/status register_1 Compare match counter_1 Compare match constant register_1 Abbreviation CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'FFFF H'0000 H'0000 H'FFFF Address H'FFFFCE00 H'FFFFCE02 H'FFFFCE04 H'FFFFCE06 H'FFFFCE08 H'FFFFCE0A H'FFFFCE0C Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 Rev. 4.00 Jul. 25, 2008 Page 504 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.2.1 Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 STR1 0 STR0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 15 to 2 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Specifies whether compare match counter 1 operates or is stopped. 0: CMCNT_1 count is stopped 1: CMCNT_1 count is started 0 STR0 0 R/W Count Start 0 Specifies whether compare match counter 0 operates or is stopped. 0: CMCNT_0 count is stopped 1: CMCNT_0 count is started 14.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects the counter input clock. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CMF 6 CMIE 5 - 4 - 3 - 2 - 1 0 CKS[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 (R/W)*1 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Rev. 4.00 Jul. 25, 2008 Page 505 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) Bit 15 to 8 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)*1 Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition] • When 0 is written to this bit after reading CMF = 1* 2 [Setting condition] 1: CMCNT and CMCOR values match 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF=1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral operating clock (Pφ). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS1 and CKS0. 00: Pφ/8 01: Pφ/32 10: Pφ/128 11: Pφ/512 Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by simply writing 0 to it. In this case, read the bit as 1 once again and write 0 to it. Rev. 4.00 Jul. 25, 2008 Page 506 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. The initial value of CMCNT is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14.2.4 Compare Match Constant Register (CMCOR) CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. The initial value of CMCOR is H'FFFF. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Rev. 4.00 Jul. 25, 2008 Page 507 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.3 14.3.1 Operation Interval Count Operation When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 14.2 shows the operation of the compare match counter. CMCNT value Counter cleared by compare match with CMCOR CMCOR H'0000 Time Figure 14.2 Counter Operation 14.3.2 CMCNT Count Timing One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock can be selected with bits CKS1 and CKS0 in CMCSR. Figure 14.3 shows the timing. Peripheral operating clock (Pφ) Nth clock N (N + 1)th clock N+1 Count clock CMCNT Figure 14.3 Count Timing Rev. 4.00 Jul. 25, 2008 Page 508 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.4 14.4.1 Interrupts CMT Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 6, Interrupt Controller (INTC). 14.4.2 Timing of Setting Compare Match Flag When CMCOR and CMCNT match, a compare match signal is generated and the CMF bit in CMCSR is set to 1. The compare match signal is generated in the last cycle in which the values match (when the CMCNT value is updated to H'0000). That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 14.4 shows the timing of CMF bit setting. Peripheral operating clock (Pφ) Counter clock (N + 1)th clock CMCNT N 0 CMCOR N Compare match signal Figure 14.4 Timing of CMF Setting 14.4.3 Timing of Clearing Compare Match Flag The CMF bit in CMCSR is cleared by reading 1 from this bit, then writing 0. Rev. 4.00 Jul. 25, 2008 Page 509 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.5 14.5.1 Usage Notes Module Standby Mode Setting The CMT operation can be disabled or enabled using the standby control register. The initial setting is for CMT operation to be halted. Access to a register is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes. 14.5.2 Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows the timing to clear the CMCNT counter. CMCSR write cycle T1 Peripheral operating clock (Pφ) T2 Address CMCNT Internal write Counter clear CMCNT N H'0000 Figure 14.5 Conflict between Write and Compare-Match Processes of CMCNT Rev. 4.00 Jul. 25, 2008 Page 510 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the timing to write to CMCNT in words. CMCSR write cycle T1 Peripheral operating clock (Pφ) T2 Address CMCNT Internal write CMCNT count-up enable CMCNT N M (CMCNT write data) Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT Rev. 4.00 Jul. 25, 2008 Page 511 of 750 REJ09B0243-0400 Section 14 Compare Match Timer (CMT) 14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing has priority over the count-up. In this case, the count-up is not performed. The byte data on another side, which is not written to, is also not counted and the previous contents remain. Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT in bytes. CMCSR write cycle T1 Peripheral operating clock (Pφ) T2 Address CMCNTH Internal write CMCNT count-up enable CMCNTH N M (CMCNT write data) CMCNTL X X Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 14.5.5 Compare Match between CMCNT and CMCOR Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. If set, the CMF bit in CMCSR is set to 1 and CMCNT is cleared to H'0000. Rev. 4.00 Jul. 25, 2008 Page 512 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Section 15 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 15.1 and 15.2 list the multiplexed pins of this LSI. Tables 15.3 and 15.4 list the pin functions in each operating mode. Table 15.1 SH7125 Multiplexed Pins Port A Function 1 (Related Module) PA0 I/O (port) PA1 I/O (port) PA2 I/O (port) PA3 I/O (port) PA4 I/O (port) PA5 I/O (port) PA6 I/O (port) PA7 I/O (port) PA8 I/O (port) PA9 I/O (port) PA10 I/O (port) PA11 I/O (port) PA12 I/O (port) PA13 I/O (port) PA14 I/O (port) PA15 I/O (port) Function 2 (Related Module) POE0 input (POE) POE1 input (POE) IRQ0 input (INTC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) TCLKA input (MTU2) TCLKB input (MTU2) TCLKC input (MTU2) TCLKD input (MTU2) RXD0 input (SCI) TXD0 output (SCI) SCK0 I/O (SCI) SCK1 I/O (SCI) RXD1 input (SCI) TXD1 output (SCI) TIC5W input (MTU2) IRQ0 input (INTC) IRQ1 input (INTC) IRQ3 input (INTC) POE3 input (POE) Function 3 (Related Module) RXD0 input (SCI) TXD0 output (SCI) SCK0 I/O (SCI) RXD1 input (SCI) TXD1 output (SCI) SCK1 I/O (SCI)  SCK2 I/O (SCI) RXD2 input (SCI) TXD2 output (SCI)  ADTRG input (A/D)      POE0 input (POE) POE1 input (POE) TIC5U input (MTU2)  Function 4 Function 5 (Related Module) (Related Module)    TRST input (H-UDI) TMS input (H-UDI)   TCK input (H-UDI) TDI input (H-UDI) POE8 input (POE)         TIC5V input (MTU2)            TDO output (H-UDI)            B PB1 I/O (port) PB2 I/O (port) PB3 I/O (port) PB5 I/O (port) PB16 I/O (port) Rev. 4.00 Jul. 25, 2008 Page 513 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Port E Function 1 (Related Module) PE0 I/O (port) PE1 I/O (port) PE2 I/O (port) PE3 I/O (port) PE4 I/O (port) PE5 I/O (port) PE6 I/O (port) PE7 I/O (port) PE8 I/O (port) PE9 I/O (port) PE10 I/O (port) PE11 I/O (port) PE12 I/O (port) PE13 I/O (port) PE14 I/O (port) PE15 I/O (port) Function 2 (Related Module) TIOC0A I/O (MTU2) TIOC0B I/O (MTU2) TIOC0C I/O (MTU2) TIOC0D I/O (MTU2) TIOC1A I/O (MTU2) TIOC1B I/O (MTU2) TIOC2A I/O (MTU2) TIOC2B I/O (MTU2) TIOC3A I/O (MTU2) TIOC3B I/O (MTU2) TIOC3C I/O (MTU2) TIOC3D I/O (MTU2) TIOC4A I/O (MTU2) TIOC4B I/O (MTU2) TIOC4C I/O (MTU2) TIOC4D I/O (MTU2) AN0 input (A/D) AN1 input (A/D) AN2 input (A/D) AN3 input (A/D) AN4 input (A/D) AN5 input (A/D) AN6 input (A/D) AN7 input (A/D) Function 3 (Related Module)  RXD0 input (SCI) TXD0 output (SCI) SCK0 I/O (SCI) RXD1 input (SCI) TXD1 output (SCI) SCK1 I/O (SCI)       MRES input (INTC)  IRQOUT output (INTC)         Function 4 Function 5 (Related Module) (Related Module)                                                 F PF0 input (port) PF1 input (port) PF2 input (port) PF3 input (port) PF4 input (port) PF5 input (port) PF6 input (port) PF7 input (port) Note: During A/D conversion, the AN input function is enabled. Rev. 4.00 Jul. 25, 2008 Page 514 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Table 15.2 SH7124 Multiplexed Pins Port A Function 1 (Related Module) PA0 I/O (port) PA1 I/O (port) PA3 I/O (port) PA4 I/O (port) PA6 I/O (port) PA7 I/O (port) PA8 I/O (port) PA9 I/O (port) Function 2 (Related Module) POE0 input (POE) POE1 input (POE) IRQ1 input (INTC) IRQ2 input (INTC) TCLKA input (MTU2) TCLKB input (MTU2) TCLKC input (MTU2) TCLKD input (MTU2) TIC5W input (MTU2) IRQ1 input (INTC) IRQ3 input (INTC) TIOC0A I/O (MTU2) TIOC0B I/O (MTU2) TIOC0C I/O (MTU2) TIOC0D I/O (MTU2) TIOC3A I/O (MTU2) TIOC3B I/O (MTU2) TIOC3C I/O (MTU2) TIOC3D I/O (MTU2) TIOC4A I/O (MTU2) TIOC4B I/O (MTU2) TIOC4C I/O (MTU2) TIOC4D I/O (MTU2) Function 3 (Related Module) RXD0 input (SCI) TXD0 output (SCI) RXD1 input (SCI) TXD1 output (SCI)  SCK2 I/O (SCI) RXD2 input (SCI) TXD2 output (SCI)  POE1 input (POE) TIC5U input (MTU2)  RXD0 input (SCI) TXD0 output (SCI) SCK0 I/O (SCI)      MRES input (INTC)  IRQOUT output (INTC) Function 4 Function 5 (Related Module) (Related Module)   TRST input (H-UDI) TMS input (H-UDI)  TCK input (H-UDI) TDI input (H-UDI) POE8 input (POE)  TIC5V input (MTU2)                     TDO output (H-UDI)                B PB1 I/O (port) PB3 I/O (port) PB5 I/O (port) E PE0 I/O (port) PE1 I/O (port) PE2 I/O (port) PE3 I/O (port) PE8 I/O (port) PE9 I/O (port) PE10 I/O (port) PE11 I/O (port) PE12 I/O (port) PE13 I/O (port) PE14 I/O (port) PE15 I/O (port) Rev. 4.00 Jul. 25, 2008 Page 515 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Port F Function 1 (Related Module) PF0 input (port) PF1 input (port) PF2 input (port) PF3 input (port) PF4 input (port) PF5 input (port) PF6 input (port) PF7 input (port) Function 2 (Related Module) AN0 input (A/D) AN1 input (A/D) AN2 input (A/D) AN3 input (A/D) AN4 input (A/D) AN5 input (A/D) AN6 input (A/D) AN7 input (A/D) Function 3 (Related Module)         Function 4 Function 5 (Related Module) (Related Module)                 Note: During A/D conversion, the AN input function is enabled. Rev. 4.00 Jul. 25, 2008 Page 516 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Table 15.3 SH7125 Pin Functions in Each Operating Mode Pin Name Single-Chip Mode (MCU Mode 3) Pin No. 4, 22, 35 6, 24, 33 8, 37 61 52 47 42 41 46 45 Initial Function Vcc Vss VCL AVcc AVss PLLVss EXTAL XTAL MD1 FWE/(ASEBRKAK/ ASEBRK*) RES WDTOVF NMI ASEMD0 PA0 PA1 PA2 PA3/(TRST*) PA4/(TMS*) PA5 PA6 PA7/(TCK*) PA8/(TDI*) PA9/(TDO*) PA10 PA11 PA12 PA13 PFC Selected Function Possibilities Vcc Vss VCL AVcc AVss PLLVss EXTAL XTAL MD1 FWE RES WDTOVF NMI ASEMD0 PA0/POE0/RXD0 PA1/POE1/TXD0 PA2/IRQ0/SCK0 PA3/IRQ1/RXD1 PA4/IRQ2/TXD1 PA5/IRQ3/SCK1 PA6/TCLKA PA7/TCLKB/SCK2 PA8/TCLKC/RXD2 PA9/TCLKD/TXD2/POE8 PA10/RXD0 PA11/TXD0/ADTRG PA12/SCK0 PA13/SCK1 39 40 44 43 38 36 34 32 31 30 29 28 27 26 25 23 21 20 Rev. 4.00 Jul. 25, 2008 Page 517 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. 19 18 51 50 49 48 62 17 16 15 14 13 12 11 10 9 5 7 3 2 1 64 63 60 59 58 57 56 55 Initial Function PA14 PA15 PB1 PB2 PB3 PB5 POE3 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PFC Selected Function Possibilities PA14/RXD1 PA15/TXD1 PB1/TIC5W PB2/IRQ0/POE0 PB3/IRQ1/POE1/TIC5V PB5/IRQ3/TIC5U PB16/POE3 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 PE3/TIOC0D/SCK0 PE4/TIOC1A/RXD1 PE5/TIOC1B/TXD1 PE6/TIOC2A/SCK1 PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 Rev. 4.00 Jul. 25, 2008 Page 518 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. 54 53 Initial Function PF6/AN6 PF7/AN7 PFC Selected Function Possibilities PF6/AN6 PF7/AN7 Note: * Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low). Table 15.4 SH7124 Pin Functions in Each Operating Mode Pin Name Single-Chip Mode (MCU Mode 3) Pin No. 4, 17 6, 19 8, 25 48 39 35 30 29 34 33 Initial Function Vcc Vss VCL AVcc AVss PLLVss EXTAL XTAL MD1 FWE/(ASEBRKAK/ ASEBRK*) RES WDTOVF NMI ASEMD0 PA0 PA1 PA3/(TRST*) PA4/(TMS*) PA6 PA7/(TCK*) PFC Selected Function Possibilities Vcc Vss VCL AVcc AVss PLLVss EXTAL XTAL MD1 FWE RES WDTOVF NMI ASEMD0 PA0/POE0/RXD0 PA1/POE1/TXD0 PA3/IRQ1/RXD1 PA4/IRQ2/TXD1 PA6/TCLKA PA7/TCLKB/SCK2 27 28 32 31 26 24 23 22 21 20 Rev. 4.00 Jul. 25, 2008 Page 519 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. 18 16 38 37 36 15 14 13 12 11 9 10 7 5 3 2 1 47 46 45 44 43 42 41 40 Initial Function PA8/(TDI*) PA9/(TDO*) PB1 PB3 PB5 PE0 PE1 PE2 PE3 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 PFC Selected Function Possibilities PA8/TCLKC/RXD2 PA9/TCLKD/TXD2/POE8 PB1/TIC5W PB3/IRQ1/POE1/TIC5V PB5/IRQ3/TIC5U PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 PE3/TIOC0D/SCK0 PE8/TIOC3A PE9/TIOC3B PE10/TIOC3C PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 Note: * Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A (in ASEMD0 = low). Rev. 4.00 Jul. 25, 2008 Page 520 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) 15.1 Register Descriptions The PFC has the following registers. For details on register addresses and register states in each processing state, refer to section 20, List of Registers. Table 15.5 Register Configuration Register Name Port A I/O register L Port A control register L4 Port A control register L3 Port A control register L2 Port A control register L1 Port B I/O register H Port B I/O register L Port B control register H1 Port B control register L2 Port B control register L1 Port E I/O register L Port E control register L4 Port E control register L3 Port E control register L2 Port E control register L1 IRQOUT function control register Abbreviation PAIORL PACRL4 PACRL3 PACRL2 PACRL1 PBIORH PBIORL PBCRH1 PBCRL2 PBCRL1 PEIORL PECRL4 PECRL3 PECRL2 PECRL1 IFCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFFD106 H’FFFFD110 H’FFFFD112 H’FFFFD114 H’FFFFD116 H'FFFFD184 H'FFFFD186 H'FFFFD18E H'FFFFD194 H'FFFFD196 H'FFFFD306 H'FFFFD310 H'FFFFD312 H'FFFFD314 H'FFFFD316 H'FFFFD322 Access Size 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 Rev. 4.00 Jul. 25, 2008 Page 521 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) 15.1.1 Port A I/O Register L (PAIORL) PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0). In other states, PAIORL is disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 15 to 10, 5, and 2 of PAIORL are disabled in SH7124. The initial value of PAIORL is H'0000. Bit: 15 PA15 IOR 14 PA14 IOR 13 PA13 IOR 12 PA12 IOR 11 PA11 IOR 10 PA10 IOR 9 PA9 IOR 8 PA8 IOR 7 PA7 IOR 6 PA6 IOR 5 PA5 IOR 4 PA4 IOR 3 PA3 IOR 2 PA2 IOR 1 PA1 IOR 0 PA0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4) PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port A. SH7125: • Port A Control Register L4 (PACRL4) Bit: 15 - 14 PA15 MD2 13 PA15 MD1 12 PA15 MD0 11 - 10 PA14 MD2 9 PA14 MD1 8 PA14 MD0 7 - 6 PA13 MD2 5 PA13 MD1 4 PA13 MD0 3 - 2 PA12 MD2 1 PA12 MD1 0 PA12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 522 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 14 13 12 Bit Name PA15MD2 PA15MD1 PA15MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA15 Mode Select the function of the PA15/TXD1 pin. 000: PA15 I/O (port) 110: TXD1 output (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PA14MD2 PA14MD1 PA14MD0 0 0 0 R/W R/W R/W PA14 Mode Select the function of the PA14/RXD1 pin. 000: PA14 I/O (port) 110: RXD1 input (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PA13MD2 PA13MD1 PA13MD0 0 0 0 R/W R/W R/W PA13 Mode Select the function of the PA13/SCK1 pin. 000: PA13 I/O (port) 110: SCK1 I/O (SCI) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PA12MD2 PA12MD1 PA12MD0 0 0 0 R/W R/W R/W PA12 Mode Select the function of the PA12/SCK0 pin. 000: PA12 I/O (port) 110: SCK0 I/O (SCI) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 523 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) • Port A Control Register L3 (PACRL3) Bit: 15 - 14 PA11 MD2 13 PA11 MD1 12 PA11 MD0 11 - 10 PA10 MD2 9 PA10 MD1 8 PA10 MD0 7 - 6 PA9 MD2 5 PA9 MD1 4 PA9 MD0 3 - 2 PA8 MD2 1 PA8 MD1 0 PA8 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PA11MD2 PA11MD1 PA11MD0 0 0 0 R/W R/W R/W PA11 Mode Select the function of the PA11/TXD0/ADTRG pin. 000: PA11 I/O (port) 010: ADTRG input (A/D) 110: TXD0 output (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PA10MD2 PA10MD1 PA10MD0 0 0 0 R/W R/W R/W PA10 Mode Select the function of the PA10/RXD0 pin. 000: PA10 I/O (port) 110: RXD0 input (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 524 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 6 5 4 Bit Name PA9MD2 PA9MD1 PA9MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA9 Mode Select the function of the PA9/TCLKD/TXD2/TDO/POE8 pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDO output. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 110: TXD2 output (SCI) 111: POE8 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PA8MD2 PA8MD1 PA8MD0 0 0 0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/RXD2/TDI pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDI input. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 110: RXD2 input (SCI) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 525 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) • Port A Control Register L2 (PACRL2) Bit: 15 - 14 PA7 MD2 13 PA7 MD1 12 PA7 MD0 11 - 10 PA6 MD2 9 PA6 MD1 8 PA6 MD0 7 - 6 PA5 MD2 5 PA5 MD1 4 PA5 MD0 3 - 2 PA4 MD2 1 PA4 MD1 0 PA4 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PA7MD2 PA7MD1 PA7MD0 0 0 0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/SCK2/TCK pin. When the E10A is in use (ASEMD0 = low), function is fixed to TCK input. 000: PA7 I/O (port) 001: TCLKB input (MTU2) 110: SCK2 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PA6MD2 PA6MD1 PA6MD0 0 0 0 R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA pin. 000: PA6 I/O (port) 001: TCLKA input (MTU2) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PA5MD2 PA5MD1 PA5MD0 0 0 0 R/W R/W R/W PA5 Mode Select the function of the PA5/IRQ3/SCK1 pin. 000: PA5 I/O (port) 001: SCK1 I/O (SCI) 111: IRQ3 input (INTC) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 526 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 3 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PA4MD2 PA4MD1 PA4MD0 0 0 0 R/W R/W R/W PA4 Mode Select the function of the PA4/IRQ2/TXD1/TMS pin. When the E10A is in use (ASEMD0 = low), function is fixed to TCK input. 000: PA4 I/O (port) 001: TXD1 output (SCI) 111: IRQ2 input (INTC) Other than above: Setting prohibited • Port A Control Register L1 (PACRL1) Bit: 15 - 14 PA3 MD2 13 PA3 MD1 12 PA3 MD0 11 - 10 PA2 MD2 9 PA2 MD1 8 PA2 MD0 7 - 6 PA1 MD2 5 PA1 MD1 4 PA1 MD0 3 - 2 PA0 MD2 1 PA0 MD1 0 PA0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PA3MD2 PA3MD1 PA3MD0 0 0 0 R/W R/W R/W PA3 Mode Select the function of the PA3/IRQ1/RXD1/TRST pin. When the E10A is in use (ASEMD0 = low), function is fixed to TRST input. 000: PA3 I/O (port) 001: RXD1 input (SCI) 111: IRQ1 input (INTC) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 527 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 10 9 8 Bit Name PA2MD2 PA2MD1 PA2MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA2 Mode Select the function of the PA2/IRQ0/SCK0 pin. 000: PA2 I/O (port) 001: SCK0 I/O (SCI) 011: IRQ0 input (INTC) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PA1MD2 PA1MD1 PA1MD0 0 0 0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TXD0 pin. 000: PA1 I/O (port) 001: TXD0 output (SCI) 111: POE1 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PA0MD2 PA0MD1 PA0MD0 0 0 0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RXD0 pin. 000: PA0 I/O (port) 001: RXD0 input (SCI) 111: POE0 input (POE) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 528 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) SH7124: • Port A Control Register L4 (PACRL4) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 0 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. • Port A Control Register L3 (PACRL3) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 PA9 MD2 5 PA9 MD1 4 PA9 MD0 3 - 2 PA8 MD2 1 PA8 MD1 0 PA8 MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 to 7 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 6 5 4 PA9MD2 PA9MD1 PA9MD0 0 0 0 R/W R/W R/W PA9 Mode Select the function of the PA9/TCLKD/TXD2/TDO/POE8 pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDO output. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 110: TXD2 output (SCI) 111: POE8 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 529 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 2 1 0 Bit Name PA8MD2 PA8MD1 PA8MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA8 Mode Select the function of the PA8/TCLKC/RXD2/TDI pin. When the E10A is in use (ASEMD0 = low), function is fixed to TDI input. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 110: RXD2 input (SCI) Other than above: Setting prohibited • Port A Control Register L2 (PACRL2) Bit: 15 - 14 PA7 MD2 13 PA7 MD1 12 PA7 MD0 11 - 10 PA6 MD2 9 PA6 MD1 8 PA6 MD0 7 - 6 - 5 - 4 - 3 - 2 PA4 MD2 1 PA4 MD1 0 PA4 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PA7MD2 PA7MD1 PA7MD0 0 0 0 R/W R/W R/W PA7 Mode Select the function of the PA7/TCLKB/SCK2/TCK pin. When the E10A is in use (ASEMD0 = low), function is fixed to TCK input. 000: PA7 I/O (port) 001: TCLKB input (MTU2) 110: SCK2 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 530 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 10 9 8 Bit Name PA6MD2 PA6MD1 PA6MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA6 Mode Select the function of the PA6/TCLKA pin. 000: PA6 I/O (port) 001: TCLKA input (MTU2) Other than above: Setting prohibited 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 PA4MD2 PA4MD1 PA4MD0 0 0 0 R/W R/W R/W PA4 Mode Select the function of the PA4/IRQ2/TXD1/TMS pin. When the E10A is in use (ASEMD0 = low), function is fixed to TMS input. 000: PA4 I/O (port) 001: TXD1 output (SCI) 111: IRQ2 input (INTC) Other than above: Setting prohibited • Port A Control Register L1 (PACRL1) Bit: 15 - 14 PA3 MD2 13 PA3 MD1 12 PA3 MD0 11 - 10 - 9 - 8 - 7 - 6 PA1 MD2 5 PA1 MD1 4 PA1 MD0 3 - 2 PA0 MD2 1 PA0 MD1 0 PA0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 531 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 14 13 12 Bit Name PA3MD2 PA3MD1 PA3MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA3 Mode Select the function of the PA3/IRQ1/RXD1/TRST pin. When the E10A is in use (ASEMD0 = low), function is fixed to TRST input. 000: PA3 I/O (port) 001: RXD1 input (SCI) 111: IRQ1 input (INTC) Other than above: Setting prohibited 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 5 4 PA1MD2 PA1MD1 PA1MD0 0 0 0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TXD0 pin. 000: PA1 I/O (port) 001: TXD0 output (SCI) 111: POE1 input (POE) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PA0MD2 PA0MD1 PA0MD0 0 0 0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RXD0 pin. 000: PA0 I/O (port) 001: RXD0 input (SCI) 100: POE0 output (POE) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 532 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) 15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH) PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B as inputs or outputs. Bits PB16IOR, PB5IOR, and PB3IOR to PB1IOR correspond to pins PB16, PB5, and PB3 to PB1, respectively (names of multiplexed pins are here given as port names and pin numbers alone). PBIORL is enabled when the port B pins are functioning as general-purpose inputs/outputs (PB5 and PB3 to PB1), and the SCK pin is functioning as inputs/outputs of SCI. In other states, PBIORL is disabled. PBIORH is enabled when the port B pins are functioning as general-purpose inputs/outputs (PB16). In other states, PBIORH is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIORH or PBIORL is set to 1, and an input pin if the bit is cleared to 0. However, bit 2 of PBIORL and bit 0 of PBIORH are disabled in SH7124. Bits 15 to 6, 4, and 0 of PBIORL and bits 15 to 1 of PBIORH are reserved. These bits are always read as 0. The write value should always be 0. The initial value of PBIORL and PBIORH are H'0000, respectively. • Port B I/O Register H (PBIORH) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PB16 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W • Port B I/O Register L (PBIORL) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 PB5 IOR 4 - 3 PB3 IOR 2 PB2 IOR 1 PB1 IOR 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R Rev. 4.00 Jul. 25, 2008 Page 533 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) 15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1) PBCRL1, PBCRL2, and PBCRH1 are 16-bit readable/writable registers that are used to select the function of the multiplexed pins on port B. SH7125: • Port B Control Register H1 (PBCRH1) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PB16 MD Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W* Note: * After a power-on reset, write can be performed only once. Bit 15 to 1 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 PB16MD 1 R/W* PB16 Mode Select the function of the PB16/POE3 pin. 0: PB16 I/O (port) 1: POE3 input (POE) • Port B Control Register L2 (PBCRL2) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 PB5 MD2 5 PB5 MD1 4 PB5 MD0 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 15 to 7 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 534 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 6 5 4 Bit Name PB5MD2 PB5MD1 PB5MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PB5 Mode Select the function of the PB5/IRQ3/TIC5U pin. 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. • Port B Control Register L1 (PBCRL1) Bit: 15 - 14 PB3 MD2 13 PB3 MD1 12 PB3 MD0 11 - 10 PB2 MD2 9 PB2 MD1 8 PB2 MD0 7 - 6 PB1 MD2 5 PB1 MD1 4 PB1 MD0 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PB3MD2 PB3MD1 PB3MD0 0 0 0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1/TIC5V pin. 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 535 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 10 9 8 Bit Name PB2MD2 PB2MD1 PB2MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PB2 Mode Select the function of the PB2/IRQ0/POE0 pin. 000: PB2 I/O (port) 001: IRQ0 input (INTC) 010: POE0 input (POE) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PB1MD2 PB1MD1 PB1MD0 0 0 0 R/W R/W R/W PB1 Mode Select the function of the PB1/TIC5W pin. 000: PB1 I/O (port) 011: TIC5W input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. SH7124: • Port B Control Register H1 (PBCRH1) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 0 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 536 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) • Port B Control Register L2 (PBCRL2) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 PB5 MD2 5 PB5 MD1 4 PB5 MD0 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 15 to 7 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 6 5 4 PB5MD2 PB5MD1 PB5MD0 0 0 0 R/W R/W R/W PB5 Mode Select the function of the PB5/IRQ3/TIC5U pin. 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. • Port B Control Register L1 (PBCRL1) Bit: 15 - 14 PB3 MD2 13 PB3 MD1 12 PB3 MD0 11 - 10 - 9 - 8 - 7 - 6 PB1 MD2 5 PB1 MD1 4 PB1 MD0 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 537 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 14 13 12 Bit Name PB3MD2 PB3MD1 PB3MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PB3 Mode Select the function of the PB3/IRQ1/POE1/TIC5V pin. 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) Other than above: Setting prohibited 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 5 4 PB1MD2 PB1MD1 PB1MD0 0 0 0 R/W R/W R/W PB1 Mode Select the function of the PB1/TIC5W pin. 000: PB1 I/O (port) 011: TIC5W input (MTU2) Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 538 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) 15.1.5 Port E I/O Register L (PEIORL) PEIORL is a 16-bit readable/writable register that is used to set the pins on port E as inputs or outputs. PE15IOR to PE0IOR correspond to pins PE15 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PE0), and the TIOC pin is functioning as inputs/outputs of MTU2. In other states, PEIORL is disabled. A given pin on port E will be an output pin if the corresponding bit in PEIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 7 to 4 of PEIORL are disabled in SH7124. The initial value of PEIORL is H'0000. Bit: 15 PE15 IOR 14 PE14 IOR 13 PE13 IOR 12 PE12 IOR 11 PE11 IOR 10 PE10 IOR 9 PE9 IOR 8 PE8 IOR 7 PE7 IOR 6 PE6 IOR 5 PE5 IOR 4 PE4 IOR 3 PE3 IOR 2 PE2 IOR 1 PE1 IOR 0 PE0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15.1.6 Port E Control Registers L1 to L4 (PECRL1 to PECRL4) PECRL1 to PECRL4, are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port E. SH7125: • Port E Control Register L4 (PECRL4) Bit: 15 - 14 PE15 MD2 13 PE15 MD1 12 PE15 MD0 11 - 10 PE14 MD2 9 PE14 MD1 8 PE14 MD0 7 - 6 - 5 PE13 MD1 4 PE13 MD0 3 - 2 PE12 MD2 1 PE12 MD1 0 PE12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 539 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 14 13 12 Bit Name PE15MD2 PE15MD1 PE15MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE14MD2 PE14MD1 PE14MD0 0 0 0 R/W R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) Other than above: Setting prohibited 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 4 PE13MD1 PE13MD0 0 0 R/W R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (INTC) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PE12MD2 PE12MD1 PE12MD0 0 0 0 R/W R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 540 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) • Port E Control Register L3 (PECRL3) Bit: 15 - 14 PE11 MD2 13 PE11 MD1 12 PE11 MD0 11 - 10 PE10 MD2 9 PE10 MD1 8 PE10 MD0 7 - 6 PE9 MD2 5 PE9 MD1 4 PE9 MD0 3 - 2 PE8 MD2 1 PE8 MD1 0 PE8 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PE11MD2 PE11MD1 PE11MD0 0 0 0 R/W R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE10MD2 PE10MD1 PE10MD0 0 0 0 R/W R/W R/W PE10 Mode Select the function of the PE10/TIOC3C pin. 000: PE10 I/O (port) 001: TIOC3C I/O (MTU2) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PE9MD2 PE9MD1 PE9MD0 0 0 0 R/W R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 541 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 2 1 0 Bit Name PE8MD2 PE8MD1 PE8MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PE8 Mode Select the function of the PE8/TIOC3A pin. 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) Other than above: Setting prohibited • Port E Control Register L2 (PECRL2) Bit: 15 - 14 PE7 MD2 13 PE7 MD1 12 PE7 MD0 11 - 10 PE6 MD2 9 PE6 MD1 8 PE6 MD0 7 - 6 PE5 MD2 5 PE5 MD1 4 PE5 MD0 3 - 2 PE4 MD2 1 PE4 MD1 0 PE4 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PE7MD2 PE7MD1 PE7MD0 0 0 0 R/W R/W R/W PE7 Mode Select the function of the PE7/TIOC2B pin. 000: PE7 I/O (port) 001: TIOC2B I/O (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE6MD2 PE6MD1 PE6MD0 0 0 0 R/W R/W R/W PE6 Mode Select the function of the PE6/TIOC2A/SCK1 pin. 000: PE6 I/O (port) 001: TIOC2A I/O (MTU2) 110: SCK1 I/O (SCI) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 542 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 7 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PE5MD2 PE5MD1 PE5MD0 0 0 0 R/W R/W R/W PE5 Mode Select the function of the PE5/TIOC1B/TXD1 pin. 000: PE5 I/O (port) 001: TIOC1B I/O (MTU2) 110: TXD1 output (SCI) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PE4MD2 PE4MD1 PE4MD0 0 0 0 R/W R/W R/W PE4 Mode Select the function of the PE4/TIOC1A/RXD1 pin. 000: PE4 I/O (port) 001: TIOC1A I/O (MTU2) 110: RXD1 input (SCI) Other than above: Setting prohibited • Port E Control Register L1 (PECRL1) Bit: 15 - 14 PE3 MD2 13 PE3 MD1 12 PE3 MD0 11 - 10 PE2 MD2 9 PE2 MD1 8 PE2 MD0 7 - 6 PE1 MD2 5 PE1 MD1 4 PE1 MD0 3 - 2 - 1 PE0 MD1 0 PE0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 543 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 14 13 12 Bit Name PE3MD2 PE3MD1 PE3MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PE3 Mode Select the function of the PE3/TIOC0D/SCK0 pin. 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE2MD2 PE2MD1 PE2MD0 0 0 0 R/W R/W R/W PE2 Mode Select the function of the PE2/TIOC0C/TXD0 pin. 000: PE2 I/O (port) 001: TIOC0C I/O (MTU2) 110: TXD0 output (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PE1MD2 PE1MD1 PE1MD0 0 0 0 R/W R/W R/W PE1 Mode Select the function of the PE1/TIOC0B/RXD0 pin. 000: PE1 I/O (port) 001: TIOC0B I/O (MTU2) 110: RXD0 input (SCI) Other than above: Setting prohibited 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 PE0MD1 PE0MD0 0 0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 544 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) SH7124: • Port E Control Register L4 (PECRL4) Bit: 15 - 14 PE15 MD2 13 PE15 MD1 12 PE15 MD0 11 - 10 PE14 MD2 9 PE14 MD1 8 PE14 MD0 7 - 6 - 5 PE13 MD1 4 PE13 MD0 3 - 2 PE12 MD2 1 PE12 MD1 0 PE12 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PE15MD2 PE15MD1 PE15MD0 0 0 0 R/W R/W R/W PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE14MD2 PE14MD1 PE14MD0 0 0 0 R/W R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 000: PE14 I/O (port) 001: TIOC4C I/O (MTU2) Other than above: Setting prohibited 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 4 PE13MD1 PE13MD0 0 0 R/W R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 01: TIOC4B I/O (MTU2) 10: MRES input (INTC) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 545 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 3 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PE12MD2 PE12MD1 PE12MD0 0 0 0 R/W R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited • Port E Control Register L3 (PECRL3) Bit: 15 - 14 PE11 MD2 13 PE11 MD1 12 PE11 MD0 11 - 10 PE10 MD2 9 PE10 MD1 8 PE10 MD0 7 - 6 PE9 MD2 5 PE9 MD1 4 PE9 MD0 3 - 2 PE8 MD2 1 PE8 MD1 0 PE8 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PE11MD2 PE11MD1 PE11MD0 0 0 0 R/W R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 000: PE11 I/O (port) 001: TIOC3D I/O (MTU2) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE10MD2 PE10MD1 PE10MD0 0 0 0 R/W R/W R/W PE10 Mode Select the function of the PE10/TIOC3C pin. 000: PE10 I/O (port) 001: TIOC3C I/O (MTU2) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 546 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 7 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PE9MD2 PE9MD1 PE9MD0 0 0 0 R/W R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 1 0 PE8MD2 PE8MD1 PE8MD0 0 0 0 R/W R/W R/W PE8 Mode Select the function of the PE8/TIOC3A pin. 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) Other than above: Setting prohibited • Port E Control Register L2 (PECRL2) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 0 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 547 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) • Port E Control Register L1 (PECRL1) Bit: 15 - 14 PE3 MD2 13 PE3 MD1 12 PE3 MD0 11 - 10 PE2 MD2 9 PE2 MD1 8 PE2 MD0 7 - 6 PE1 MD2 5 PE1 MD1 4 PE1 MD0 3 - 2 - 1 PE0 MD1 0 PE0 MD0 Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit 15 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 PE3MD2 PE3MD1 PE3MD0 0 0 0 R/W R/W R/W PE3 Mode Select the function of the PE3/TIOC0D/SCK0 pin. 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 9 8 PE2MD2 PE2MD1 PE2MD0 0 0 0 R/W R/W R/W PE2 Mode Select the function of the PE2/TIOC0C/TXD0 pin. 000: PE2 I/O (port) 001: TIOC0C I/O (MTU2) 110: TXD0 output (SCI) Other than above: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 PE1MD2 PE1MD1 PE1MD0 0 0 0 R/W R/W R/W PE1 Mode Select the function of the PE1/TIOC0B/RXD0 pin. 000: PE1 I/O (port) 001: TIOC0B I/O (MTU2) 110: RXD0 input (SCI) Other than above: Setting prohibited Rev. 4.00 Jul. 25, 2008 Page 548 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) Bit 3, 2 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 0 PE0MD1 PE0MD0 0 0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited 15.1.7 IRQOUT Function Control Register (IFCR) IFCR is a 16-bit readable/writable register that is used to control the IRQOUT pin output when it is selected as the multiplexed pin function by port E control register L4 (PECRL4). When PECRL4 selects another function, the IFCR setting does not affect the pin function. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 IRQ MD1 0 IRQ MD0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 15 to 2 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 0 IRQMD1 IRQMD0 0 0 R/W R/W Port E IRQOUT Pin Function Select Select the IRQOUT pin function when bits 14 to 12 (PE15MD2 to PE15MD0) in PECRL4 are set to B'011. 00: Interrupt request accept signal output Other than above: Always high-level output Rev. 4.00 Jul. 25, 2008 Page 549 of 750 REJ09B0243-0400 Section 15 Pin Function Controller (PFC) 15.2 Usage Notes 1. In this LSI, the same function is available as a multiplexed function on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. If two or more pins are specified for one function, however, there are two cautions shown below.  When the pin function is input Signals input to several pins are formed as one signal through OR or AND logic and the signal is transmitted into the LSI. Therefore, a signal that differs from the input signals may be transmitted to the LSI depending on the input signals in other pins that have the same functions. Table 15.6 shows the transmit forms of input functions allocated to several pins. When using one of the functions shown below in multiple pins, use it with care of signal polarity considering the transmit forms. Table 15.6 Transmit Forms of Input Functions Allocated to Multiple Pins OR Type SCK0 to SCK2, RXD0 to RXD2, POE0, POE1, POE3*, POE8 Note: * AND Type IRQ0* to IRQ3 This pin is supported only by the SH7125. Signals input to several pins are formed as one signal through OR logic and the signal is transmitted into the LSI. AND type: Signals input to several pins are formed as one signal through AND logic and the signal is transmitted into the LSI.  When the pin function is output Each selected pin can output the same function. 2. When the port input is switched from a low level to the IRQ edge for the pins that are multiplexed with input/output and IRQ, the corresponding edge is detected. 3. Do not set functions other than those specified in tables 15.3 and 15.4. Otherwise, correct operation cannot be guaranteed. OR type: Rev. 4.00 Jul. 25, 2008 Page 550 of 750 REJ09B0243-0400 Section 16 I/O Ports Section 16 I/O Ports The SH7125 has four ports: A, B, E, and F. Port A is a 16-bit port, port B is a 5-bit port, and port E is a 16-bit port. Port F is an 8-bit input-only port. The SH7124 has four ports: A, B, E, and F. Port A is an 8-bit port, port B is a 3-bit port, and port E is a 12-bit port. Port F is an 8-bit input-only port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. Rev. 4.00 Jul. 25, 2008 Page 551 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.1 Port A Port A in the SH7125 is an input/output port with the 16 pins shown in figure 16.1. PA15 (I/O)/TXD1 (output) PA14 (I/O)/RXD1 (input) PA13 (I/O)/SCK1 (I/O) PA12 (I/O)/SCK0 (I/O) PA11 (I/O)/TXD0 (output)/ADTRG (input) PA10 (I/O)/RXD0 (input) PA9 (I/O)/TCLKD (input)/TXD2 (output)/TDO (output)/POE8 (input) PA8 (I/O)/TCLKC (input)/RXD2 (input)/TDI (input) Port A PA7 (I/O)/TCLKB (input)/SCK2 (I/O)/TCK (input) PA6 (I/O)/TCLKA (input) PA5 (I/O)/IRQ3 (input)/SCK1 (I/O) PA4 (I/O)/IRQ2 (input)/TXD1 (output)/TMS (input) PA3 (I/O)/IRQ1 (input)/RXD1 (input)/TRST (input) PA2 (I/O)/IRQ0 (input)/SCK0 (I/O) PA1 (I/O)/POE1 (input)/TXD0 (output) PA0 (I/O)/POE0 (input)/RXD0 (input) Figure 16.1 Port A (SH7125) Port A in the SH7124 is an input/output port with the eight pins shown in figure 16.2. PA9 (I/O)/TCLKD (input)/TXD2 (output)/TDO (output)/POE8 (input) PA8 (I/O)/TCLKC (input)/RXD2 (input)/TDI (input) PA7 (I/O)/TCLKB (input)/SCK2 (I/O)/TCK (input) PA6 (I/O)/TCLKA (input) Port A PA4 (I/O)/IRQ2 (input)/TXD1 (output)/TMS (input) PA3 (I/O)/IRQ1 (input)/RXD1 (input)/TRST (input) PA1 (I/O)/POE1 (input)/TXD0 (output) PA0 (I/O)/POE0 (input)/RXD0 (input) Figure 16.2 Port A (SH7124) Rev. 4.00 Jul. 25, 2008 Page 552 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.1.1 Register Descriptions Port A is a 16-bit input/output port in the SH7125 and an 8-bit input/output port in the SH7124. Port A has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.1 Register Configuration Register Name Port A data register L Port A port register L Abbreviation PADRL PAPRL R/W R/W R Initial Value H'0000  Address H'FFFFD102 H'FFFFD11E Access Size 8, 16 8, 16 16.1.2 Port A Data Register L (PADRL) PADRL is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here) in the SH7125. Bits PA9DR to PA6DR, PA4DR, PA3DR, PA1DR, and PA0DR correspond to pins PA9 to PA6, PA4, PA3, PA1, and PA0, respectively (multiplexed functions omitted here) in the SH7124. When a pin function is general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRL, although that value is written into PADRL, it does not affect the pin state. Table 16.2 summarizes port A data register read/write operations. Rev. 4.00 Jul. 25, 2008 Page 553 of 750 REJ09B0243-0400 Section 16 I/O Ports • PADRL (SH7125) Bit: 15 PA15 DR 14 PA14 DR 13 PA13 DR 12 PA12 DR 11 PA11 DR 10 PA10 DR 9 PA9 DR 8 PA8 DR 7 PA7 DR 6 PA6 DR 5 PA5 DR 4 PA4 DR 3 PA3 DR 2 PA2 DR 1 PA1 DR 0 PA0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 16.2. Rev. 4.00 Jul. 25, 2008 Page 554 of 750 REJ09B0243-0400 Section 16 I/O Ports • PADRL (SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PA9 DR 8 PA8 DR 7 PA7 DR 6 PA6 DR 5 - 4 PA4 DR 3 PA3 DR 2 - 1 PA1 DR 0 PA0 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W Bit 15 to 10 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 6 5 PA9DR PA8DR PA7DR PA6DR  0 0 0 0 0 R/W R/W R/W R/W R See table 16.2. Reserved This bit is always read as 0. The write value should always be 0. 4 3 2 PA4DR PA3DR  0 0 0 R/W R/W R See table 16.2. Reserved This bit is always read as 0. The write value should always be 0. 1 0 PA1DR PA0DR 0 0 R/W R/W See table 16.2. Rev. 4.00 Jul. 25, 2008 Page 555 of 750 REJ09B0243-0400 Section 16 I/O Ports Table 16.2 Port A Data Register L (PADRL) Read/Write Operations • PADRL Bits 15 to 0 PAIORH, PAIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADRL value PADRL value Write Can write to PADRL, but it has no effect on pin state Can write to PADRL, but it has no effect on pin state Value written is output from pin Can write to PADRL, but it has no effect on pin state Rev. 4.00 Jul. 25, 2008 Page 556 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.1.3 Port A Port Register L (PAPRL) PAPRL is a 16-bit read-only register that always return the states of the pins regardless of the PFC setting. Bits PA15PR to PA0PR correspond to pins PA15 to PA0 (multiplexed functions omitted here) in the SH7125. Bits PA9PR to PA6PR, PA4PR, PA3PR, PA1PR, and PA0PR correspond to pins PA9 to PA6, PA4, PA3, PA1, and PA0, respectively (multiplexed functions omitted here) in the SH7124. • PAPRL (SH7125) Bit: 15 PA15 PR 14 PA14 PR 13 PA13 PR 12 PA12 PR 11 PA11 PR 10 PA10 PR 9 PA9 PR 8 PA8 PR 7 PA7 PR 6 PA6 PR 5 PA5 PR 4 PA4 PR 3 PA3 PR 2 PA2 PR 1 PA1 PR 0 PA0 PR Initial value: * R/W: R * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PA15PR PA14PR PA13PR PA12PR PA11PR PA10PR PA9PR PA8PR PA7PR PA6PR PA5PR PA4PR PA3PR PA2PR PA1PR PA0PR Initial Value R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Rev. 4.00 Jul. 25, 2008 Page 557 of 750 REJ09B0243-0400 Section 16 I/O Ports • PAPRL (SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 PA9 PR 8 PA8 PR 7 PA7 PR 6 PA6 PR 5 - 4 PA4 PR 3 PA3 PR 2 - 1 PA1 PR 0 PA0 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R * R * R * R * R 0 R * R * R 0 R * R * R Bit 15 to 10 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 6 5 PA9PR PA8PR PA7PR PA6PR  Pin state R Pin state R Pin state R Pin state R 0 R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 4 3 2 PA4PR PA3PR  Pin state R Pin state R 0 R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 1 0 PA1PR PA0PR Pin state R Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Rev. 4.00 Jul. 25, 2008 Page 558 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.2 Port B Port B in the SH7125 is an input/output port with the five pins shown in figure 16.3. PB16 (I/O)/POE3 (input) PB5 (I/O)/IRQ3 (input)/TIC5U (input) Port B PB3 (I/O)/IRQ1 (input)/POE1 (input)/TIC5V (input) PB2 (I/O)/IRQ0 (input)/POE0 (input) PB1 (I/O)/TIC5W (input) Figure 16.3 Port B (SH7125) Port B in the SH7124 is an input/output port with the three pins shown in figure 16.4. PB5 (I/O)/IRQ3 (input)/TIC5U (input) Port B PB3 (I/O)/IRQ1 (input)/POE1 (input)/TIC5V (input) PB1 (I/O)/TIC5W (input) Figure 16.4 Port B (SH7124) 16.2.1 Register Descriptions Port B is a 5-bit input/output port in the SH7125 and a 3-bit input/output port in the SH7124. Port B has the following register. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.3 Register Configuration Register Name Port B data register H Port B data register L Port B port register H Port B port register L Abbreviation PBDRH PBDRL PBPRH PBPRL R/W R/W R/W R R Initial Value H'0000 H'0000   Address H'FFFFD180 H'FFFFD182 H'FFFFD19C H'FFFFD19E Access Size 8, 16, 32 8, 16 8, 16, 32 8, 16 Rev. 4.00 Jul. 25, 2008 Page 559 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) PBDRH and PBDRL are 16-bit readable/writable registers that store port B data. Bits PB16DR, PB5DR, and PB3DR to PB1DR correspond to pins PB16, PB5, and PB3 to PB1, respectively (multiplexed functions omitted here) in the SH7125. Bits PB5DR, PB3DR, and PB1DR correspond to pins PB5, PB3, and PB1, respectively (multiplexed functions omitted here) in the SH7124. When a pin function is general output, if a value is written to PBDRH or PBDRL, that value is output directly from the pin, and if PBDRH or PBDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PBDRH or PBDRL is read, the pin state, not the register value, is returned directly. If a value is written to PBDRH or PBDRL, although that value is written into PBDRH or PBDRL, it does not affect the pin state. Table 16.4 summarizes port B data register read/write operations. • PBDRH (SH7125) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PB16 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 15 to 1 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 PB16DR 0 R/W See table 16.4. Rev. 4.00 Jul. 25, 2008 Page 560 of 750 REJ09B0243-0400 Section 16 I/O Ports • PBDRH (SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 0 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. • PBDRL (SH7125) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 PB5 DR 4 - 3 PB3 DR 2 PB2 DR 1 PB1 DR 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R Bit 15 to 6 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 PB5DR — 0 0 R/W R See table 16.4. Reserved This bit is always read as 0. The write value should always be 0. 3 2 1 0 PB3DR PB2DR PB1DR — 0 0 0 0 R/W R/W R/W R See table 16.4. Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 561 of 750 REJ09B0243-0400 Section 16 I/O Ports • PBDRL (SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 PB5 DR 4 - 3 PB3 DR 2 - 1 PB1 DR 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R Bit 15 to 6 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 PB5DR — 0 0 R/W R See table 16.4. Reserved This bit is always read as 0. The write value should always be 0. 3 2 PB3DR — 0 0 R/W R See table 16.4. Reserved This bit is always read as 0. The write value should always be 0. 1 0 PB1DR — 0 0 R/W R See table 16.4. Reserved This bit is always read as 0. The write value should always be 0. Table 16.4 Port B Data Register (PBDR) Read/Write Operations • PBDRH Bit 0 and PBDRL Bits 5 and 3 to 1 PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDRH or PBDRL value PBDRH or PBDRL value Write Can write to PBDRH and PBDRL, but it has no effect on pin state Can write to PBDRH and PBDRL, but it has no effect on pin state Value written is output from pin Can write to PBDRH and PBDRL, but it has no effect on pin state Rev. 4.00 Jul. 25, 2008 Page 562 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.2.3 Port B Port Registers H and L (PBPRH and PBPRL) PBPRH and PBPRL are 16-bit read-only registers that always return the states of the pins regardless of the PFC setting. Bits PB16PR, PB5PR, and PB3PR to PB1PR correspond to pins PB16, PB5, and PB3 to PB31, respectively (multiplexed functions omitted here) in the SH7125. Bits PB5PR, PB3PR, and PB1PR correspond to pins PB5, PB3, and PB1, respectively (multiplexed functions omitted here) in the SH7124. • PBPRH (SH7125) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PB16 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R Bit 15 to 1 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 PB16PR Pin state R The pin state is returned regardless of the PFC setting. This bit cannot be modified. • PBPRH (SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 0 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 563 of 750 REJ09B0243-0400 Section 16 I/O Ports • PBPRL (SH7125) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 PB5 PR 4 - 3 PB3 PR 2 PB2 PR 1 PB1 PR 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R 0 R * R * R * R 0 R Bit 15 to 6 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 PB5PR  Pin state R 0 R The pin state is returned regardless of the PFC setting. This bit cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 3 2 1 0 PB3PR PB2PR PB1PR  Pin state R Pin state R Pin state R 0 R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 564 of 750 REJ09B0243-0400 Section 16 I/O Ports • PBPRL (SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 PB5 PR 4 - 3 PB3 PR 2 - 1 PB1 PR 0 - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R 0 R * R 0 R * R 0 R Bit 15 to 6 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 4 PB5PR  Pin state R 0 R The pin state is returned regardless of the PFC setting. This bit cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 3 2 PB3PR  Pin state R 0 R The pin state is returned regardless of the PFC setting. This bit cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. 1 0 PB1PR  Pin state R 0 R The pin state is returned regardless of the PFC setting. This bit cannot be modified. Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 565 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.3 Port E Port E in the SH7125 is an input/output port with the 16 pins shown in figure 16.5. PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O) PE13 (I/O)/TIOC4B (I/O)/MRES (input) PE12 (I/O)/TIOC4A (I/O) PE11 (I/O)/TIOC3D (I/O) PE10 (I/O)/TIOC3C (I/O) PE9 (I/O)/TIOC3B (I/O) Port E PE8 (I/O)/TIOC3A (I/O) PE7 (I/O)/TIOC2B (I/O) PE6 (I/O)/TIOC2A (I/O)/SCK1 (I/O) PE5 (I/O)/TIOC1B (I/O)/TXD1 (output) PE4 (I/O)/TIOC1A (I/O)/RXD1 (input) PE3 (I/O)/TIOC0D (I/O)/SCK0 (I/O) PE2 (I/O)/TIOC0C (I/O)/TXD0 (output) PE1 (I/O)/TIOC0B (I/O)/RXD0 (input) PE0 (I/O)/TIOC0A (I/O) Figure 16.5 Port E (SH7125) Rev. 4.00 Jul. 25, 2008 Page 566 of 750 REJ09B0243-0400 Section 16 I/O Ports Port E in the SH7124 is an input/output port with the 12 pins shown in figure 16.6. PE15 (I/O)/TIOC4D (I/O)/IRQOUT (output) PE14 (I/O)/TIOC4C (I/O) PE13 (I/O)/TIOC4B (I/O)/MRES (input) PE12 (I/O)/TIOC4A (I/O) PE11 (I/O)/TIOC3D (I/O) PE10 (I/O)/TIOC3C (I/O) Port E PE9 (I/O)/TIOC3B (I/O) PE8 (I/O)/TIOC3A (I/O) PE3 (I/O)/TIOC0D (I/O)/SCK0 (I/O) PE2 (I/O)/TIOC0C (I/O)/TXD0 (output) PE1 (I/O)/TIOC0B (I/O)/RXD0 (input) PE0 (I/O)/TIOC0A (I/O) Figure 16.6 Port E (SH7124) Rev. 4.00 Jul. 25, 2008 Page 567 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.3.1 Register Descriptions Port E is a 16-bit input/output port in the SH7125 and a 12-bit input/output port in the SH7124. Port E has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.5 Register Configuration Register Name Port E data register L Port E port register L Abbreviation PEDRL PEPRL R/W R/W R Initial Value H'0000  Address H'FFFFD302 H'FFFFD31E Access Size 8, 16 8, 16 16.3.2 Port E Data Register L (PEDRL) PEDRL is a 16-bit readable/writable register that stores port E data. Bits PE15DR to PE0DR correspond to pins PE15 to PE0 (multiplexed functions omitted here) in the SH7125. Bits PE15DR to PE8DR and PE3DR to PE0DR correspond to pins PE15 to PE8 and PE3 to PE0, respectively (multiplexed functions omitted here) in the SH7124. When a pin function is general output, if a value is written to PEDRL, that value is output directly from the pin, and if PEDRL is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRL, although that value is written into PEDRL, it does not affect the pin state. Table 16.6 summarizes port E data register read/write operations. Rev. 4.00 Jul. 25, 2008 Page 568 of 750 REJ09B0243-0400 Section 16 I/O Ports • PEDRL (SH7125) Bit: 15 PE15 DR 14 PE14 DR 13 PE13 DR 12 PE12 DR 11 PE11 DR 10 PE10 DR 9 PE9 DR 8 PE8 DR 7 PE7 DR 6 PE6 DR 5 PE5 DR 4 PE4 DR 3 PE3 DR 2 PE2 DR 1 PE1 DR 0 PE0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 16.6. Rev. 4.00 Jul. 25, 2008 Page 569 of 750 REJ09B0243-0400 Section 16 I/O Ports • PEDRL (SH7124) Bit: 15 PE15 DR 14 PE14 DR 13 PE13 DR 12 PE12 DR 11 PE11 DR 10 PE10 DR 9 PE9 DR 8 PE8 DR 7 - 6 - 5 - 4 - 3 PE3 DR 2 PE2 DR 1 PE1 DR 0 PE0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 to 4 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR  Initial Value 0 0 0 0 0 0 0 0 All 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R Description See table 16.6. Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 PE3DR PE2DR PE1DR PE0DR 0 0 0 0 R/W R/W R/W R/W See table 16.6. Table 16.6 Port E Data Register L (PEDRL) Read/Write Operations • PEDRL Bits 15 to 0 PEIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PEDRL value PEDRL value Write Can write to PEDRL, but it has no effect on pin state Can write to PEDRL, but it has no effect on pin state Value written is output from pin Can write to PEDRL, but it has no effect on pin state Rev. 4.00 Jul. 25, 2008 Page 570 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.3.3 Port E Port Register L (PEPRL) PEPRL is a 16-bit read-only register that always returns the states of the pins regardless of the PFC setting. Bits PE15PR to PE0PR correspond to pins PE15 to PE0 (multiplexed functions omitted here) in the SH7125. Bits PE15PR to PE8PR and PE3PR to PE0PR correspond to pins PE15 to PE8 and PE3 to PE0, respectively (multiplexed functions omitted here) in the SH7124. • PEPRL (SH7125) Bit: 15 PE15 PR 14 PE14 PR 13 PE13 PR 12 PE12 PR 11 PE11 PR 10 PE10 PR 9 PE9 PR 8 PE8 PR 7 PE7 PR 6 PE6 PR 5 PE5 PR 4 PE4 PR 3 PE3 PR 2 PE2 PR 1 PE1 PR 0 PE0 PR Initial value: * R/W: R * R * R * R * R * R * R * R * R * R * R * R * R * R * R * R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15PR PE14PR PE13PR PE12PR PE11PR PE10PR PE9PR PE8PR PE7PR PE6PR PE5PR PE4PR PE3PR PE2PR PE1PR PE0PR Initial Value R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Rev. 4.00 Jul. 25, 2008 Page 571 of 750 REJ09B0243-0400 Section 16 I/O Ports • PEPRL (SH7124) Bit: 15 PE15 PR 14 PE14 PR 13 PE13 PR 12 PE12 PR 11 PE11 PR 10 PE10 PR 9 PE9 PR 8 PE8 PR 7 - 6 - 5 - 4 - 3 PE3 PR 2 PE2 PR 1 PE1 PR 0 PE0 PR Initial value: * R/W: R * R * R * R * R * R * R * R 0 R 0 R 0 R 0 R * R * R * R * R Bit 15 14 13 12 11 10 9 8 7 to 4 Bit Name PE15PR PE14PR PE13PR PE12PR PE11PR PE10PR PE9PR PE8PR  Initial Value R/W Description The pin state is returned regardless of the PFC setting. These bits cannot be modified. Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 2 1 0 PE3PR PE2PR PE1PR PE0PR Pin state R Pin state R Pin state R Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. Rev. 4.00 Jul. 25, 2008 Page 572 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.4 Port F Port F in the SH7125 and SH7124 is an input-only port with the eight pins shown in figure 16.7. PF7 (input)/AN7 (input) PF6 (input)/AN6 (input) PF5 (input)/AN5 (input) PF4 (input)/AN4 (input) Port F PF3 (input)/AN3 (input) PF2 (input)/AN2 (input) PF1 (input)/AN1 (input) PF0 (input)/AN0 (input) Figure 16.7 Port F (SH7125, SH7124) 16.4.1 Register Descriptions Port F is an 8-bit input-only port in the SH7125 and SH7124. Port F has the following register. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 16.7 Register Configuration Register Name Port F data register L Abbreviation PFDRL R/W R Initial Value  Address H'FFFFD382 Access Size 8, 16 Rev. 4.00 Jul. 25, 2008 Page 573 of 750 REJ09B0243-0400 Section 16 I/O Ports 16.4.2 Port F Data Register L (PFDRL) The port F data register L (PFDRL) is a 16-bit read-only register that stores port F data. Bits PF7DR to PF0DR correspond to pins PF7 to PF0 (multiplexed functions omitted here) in the SH7125 and SH7124. Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read. Table 16.8 summarizes port F data register L read/write operations. • PFDRL (SH7125, SH7124) Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 PF7 DR 6 PF6 DR 5 PF5 DR 4 PF4 DR 3 PF3 DR 2 PF2 DR 1 PF1 DR 0 PF0 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R * R * R * R * R * R * R * R * R Bit 15 to 8 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R Pin state R See table 16.8. Table 16.8 Port F Data Register L (PFDRL) Read/Write Operations • PFDRL Bits 7 to 0 Pin Function General input ANn input Read Pin state 1 Write Ignored (no effect on pin state) Ignored (no effect on pin state) Rev. 4.00 Jul. 25, 2008 Page 574 of 750 REJ09B0243-0400 Section 17 Flash Memory Section 17 Flash Memory This LSI has 128-Kbyte, 64-Kbyte, or 32-Kbyte on-chip flash memory. The flash memory has the following features. 17.1 Features • Capacitance SH71253, SH71243: 128 Kbytes SH71252, SH71242: 64 Kbytes SH71241: 32 Kbytes • Two on-board programming modes and one off-board programming mode  On-board programming modes Boot Mode: This mode is a program mode that uses an on-chip SCI interface. The user MAT can be programmed. This mode can automatically adjust the bit rate between the host and this LSI. User Program Mode: The user MAT can be programmed by using the optional interface. This mode cannot be used in 32-Kbyte on-chip flash memory version.  Off-board programming mode This mode uses the dedicated socket adapter and PROM programmer. The user MAT can be programmed. • Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. The user branch is also supported.  User branch The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps. The user processing routine can be executed between the steps, this setting for which is called the user branch addition. • Protection modes There are two protection modes. Software protection by the register setting and hardware protection by the FWE pin. The protection state for flash memory programming/erasing can be set. When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended. Rev. 4.00 Jul. 25, 2008 Page 575 of 750 REJ09B0243-0400 Section 17 Flash Memory • Programming/erasing time The flash memory programming time is tP ms (Typ.) in 128-byte simultaneous programming and tP/128 ms per byte. The erasing time is tE s (Typ.) per block. • Number of programming The number of flash memory programming can be up to NWEC times. • Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 40 MHz (Pφ). Rev. 4.00 Jul. 25, 2008 Page 576 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.2 17.2.1 Overview Block Diagram Internal address bus Internal data bus (32 bits) FCCS Module bus FPCS FECS FKEY FTDAR Memory MAT unit Control unit User MAT: 128 kbytes 64 kbytes 32 kbytes Flash memory FWE pin Mode pins Operating mode [Legend] FCCS: FPCS: FECS: FKEY: FTDAR: Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash transfer destination address register Figure 17.1 Block Diagram of Flash Memory Rev. 4.00 Jul. 25, 2008 Page 577 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 17.2. For the setting of each mode pin and the FWE pin, see tables 17.1 to 17.4. • Flash memory can be read in user mode, but cannot be programmed or erased. • Flash memory can be read, programmed, or erased on the board only in user program mode and boot mode. Reset state =0 d mo es ett Us mo er p de rog se ram ttin g =0 RE S er ing Bo ot m od S RE = RE Us S e t se tin g 0 FWE = 0 User mode FWE = 1 User program mode Boot mode On-board programming mode Figure 17.2 Mode Transition of Flash Memory Table 17.1 Relationship between FWE and MD Pins and Operating Modes Pin RES FWE MD1 Reset State 0 0/1 0/1 User Mode 1 0 1 User Program Mode 1 1 1 Boot Mode 1 1 0 Rev. 4.00 Jul. 25, 2008 Page 578 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode and user program mode is shown in table 17.2. Table 17.2 Comparison of Programming Modes Off-Board Programming/erasing On-Board Programming 2 environment Boot Mode User Program Mode* Programming Programming/ erasing enable MAT Programming/ erasing control All erasure Block division erasure Program data transfer User branch function Reset initiation MAT User MAT Command method Possible (Automatic) Possible* 1 User MAT Programming/erasing interface Possible Possible From optional device via RAM Possible User MAT User MAT  Possible (Automatic) Impossible Via programmer Impossible Embedded program storage MAT  From host via SCI Not possible Embedded program storage MAT Transition to user mode Mode setting change and FWE setting change reset Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. Cannot be used in 32-kbyte on-chip flash memory version. • The user MAT is all erased in boot mode. Then, the user MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Rev. 4.00 Jul. 25, 2008 Page 579 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.2.4 Flash Memory Configuration This LSI's flash memory is configured by the 128-Kbyte, 64-Kbyte, or 32-Kbyte user MAT. • 128KB SH71253 SH71243 • 64KB SH71252 SH71242 • 32KB SH71241 128 kbytes, 64 kbytes, or 32 kbytes Address H'00000000 Address H'00007FFF (when the size of the user MAT is 32 kbytes) Address H'0000FFFF (when the size of the user MAT is 64 kbytes) Address H'0001FFFF (when the size of the user MAT is 128 kbytes) Figure 17.3 Flash Memory Configuration 17.2.5 Block Division The user MAT is divided into 64 Kbytes (128-kbyte version: one block), 32 Kbytes (one block), and 4 Kbytes (eight blocks) as shown in figure 17.4. The user MAT can be erased in this dividedblock units and the erase-block number of EB0 to EB9 is specified when erasing. The user MAT is divided into 16 Kbytes (two blocks) for 32-Kbyte ROM version. • 128 kbytes < User MAT > H'00000000 4 kbytes × 8 128 kbytes • 64 kbytes Erase block EB0 to EB7 32KB EB8 H'0000FFFF H'00000000 4 kbytes × 8 < User MAT > • 32 kbytes Erase block 32 kbytes < User MAT > H'00000000 EB0 64 kbytes to EB7 H'00007FFF 32KB EB8 64KB H'0001FFFF EB9 Figure 17.4 Block Division of User MAT Rev. 4.00 Jul. 25, 2008 Page 580 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode. The overview of the procedure is as follows. For details, see section 17.5.2, User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version). Start user procedure program for programming/erasing. Select on-chip program to be downloaded and set download destination Download on-chip program by setting VBR, FKEY, and SCO bits. Initialization execution (on-chip program execution) Programming (in 128-byte units) or erasing (in one-block units) (on-chip program execution) No Programming/ erasing completed? Yes End user procedure program Figure 17.5 Overview of User Procedure Program (1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface registers. The download destination can be specified by FTDAR. Rev. 4.00 Jul. 25, 2008 Page 581 of 750 REJ09B0243-0400 Section 17 Flash Memory (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'84000000 and then setting the SCO bit in the flash code control and status register (FCCS) and the flash key code register (FKEY), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Note that VBR can be changed after download is completed. (3) Initialization of Programming/Erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be in an area other than the user MAT area, which is in the middle of programming and the area where the on-chip program is downloaded. These settings are performed by using the programming/erasing interface parameters. (4) Programming/Erasing Execution To program or erase, the FWE pin must be brought high and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameters and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. There are limitations and notes on the interrupt processing during programming/erasing. For details, see section 17.7.1, Interrupts during Programming/Erasing. (5) When Programming/Erasing is Executed Consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. Rev. 4.00 Jul. 25, 2008 Page 582 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.3 Input/Output Pins Flash memory is controlled by the pins as shown in table 17.3. Table 17.3 Pin Configuration Pin Name Power-on reset Flash programming enable Mode 1 Transmit data Receive data Symbol RES FWE MD1 TXD1 (PA4) RXD1 (PA3) I/O Input Input Input Output Input Function Reset Hardware protection when programming flash memory Sets operating mode of this LSI Serial transmit data output (used in boot mode) Serial receive data input (used in boot mode) 17.4 17.4.1 Register Descriptions Registers The registers/parameters, which control flash memory when the on-chip flash memory is valid are shown in table 17.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. The correspondence of operating modes and registers/parameters for use is shown in table 17.5. Rev. 4.00 Jul. 25, 2008 Page 583 of 750 REJ09B0243-0400 Section 17 Flash Memory Table 17.4 (1) Register Name Register Configuration Abbreviation* FCCS FPCS FECS FKEY FTDAR 3 R/W Initial Value Address H'FFFFCC00 H'FFFFCC01 H'FFFFCC02 H'FFFFCC04 H'FFFFCC06 Access Size 8 8 8 8 8 Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash transfer destination address register R, W*1 H'00*2 2 H'80* R/W R/W R/W R/W H'00 H'00 H'00 H'00 Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value, which can be read is always 0.) 2. The initial value of the FWE bit is 0 when the FWE pin goes low. The initial value of the FWE bit is 1 when the FWE pin goes high. 3. All registers can be accessed only in bytes. Table 17.4 (2) Name Parameter Configuration Abbreviation DPFR FPFR FMPAR FMPDR FEBS FPEFEQ FUBRA R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Address Access Size Download pass/fail result Flash pass/fail result Flash multipurpose address area Flash multipurpose data destination area Flash erase block select Flash program and erase frequency control Flash user branch address set parameter Note: * On-chip RAM* 8, 16, 32 R0 of CPU R5 of CPU R4 of CPU R4 of CPU R4 of CPU R5 of CPU 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 One byte of the start address in the on-chip RAM area specified by FTDAR is valid. Rev. 4.00 Jul. 25, 2008 Page 584 of 750 REJ09B0243-0400 Section 17 Flash Memory Table 17.5 Register/Parameter and Target Mode Download Programming/ FCCS erasing interface FPCS registers PECS FKEY FTDAR Programming/ DPFR erasing interface FPFR parameters FPEFEQ FUBRA FMPAR FMPDR FEBS √ √ √ √ √ √ — — — — — — Initialization — — — — — — √ √ √ — — — Programming — — — √ — — √ — — √ √ — Erasure — — — √ — — √ — — — — √ Read — — — — — — — — — — — — Rev. 4.00 Jul. 25, 2008 Page 585 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.4.2 Programming/Erasing Interface Registers The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Bit: 7 FWE 6 - 5 - 4 FLER 3 - 2 - 1 - 0 SCO Initial value: 1/0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 (R)/W Bit 7 Bit Name FWE Initial Value 1/0 R/W R Description Flash Programming Enable Monitors the level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. 0: When the FWE pin goes low (in hardware protection state) 1: When the FWE pin goes high 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 586 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 4 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset signal must be released after the reset period of 100 µs, which is longer than normal. 0: Flash memory operates normally Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset 1: Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 17.6.3, Error Protection. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 587 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 0 Bit Name SCO Initial Value 0 R/W (R)/W Description Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, H'A5 must be written to FKEY and this operation must be in the on-chip RAM. Four NOP instructions must be executed immediately after setting this bit to 1. For interrupts during download, see section 17.7.1, Interrupts during Programming/Erasing. For the download time, see section 17.7.2, Other Notes. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on-chip program storage area. Therefore, before issuing a download request (SCO = 1), set VBR to H'84000000. Otherwise, the CPU gets out of control. Once download end is confirmed, VBR can be changed to any other value. The mode in which the FWE pin is high must be used when using the SCO function. 0: Download of the on-chip programming/erasing program to the on-chip RAM is not executed. [Clearing condition] When download is completed 1: Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is generated [Setting conditions] When all of the following conditions are satisfied and 1 is written to this bit • • FKEY is written to H'A5 During execution in the on-chip RAM Rev. 4.00 Jul. 25, 2008 Page 588 of 750 REJ09B0243-0400 Section 17 Flash Memory (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 PPVS Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 7 to 1 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 PPVS 0 R/W Program Pulse Single Selects the programming program. 0: On-chip programming program is not selected [Clearing condition] When transfer is completed 1: On-chip programming program is selected (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 EPVB Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 7 to 1 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 589 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 0 Bit Name EPVB Initial Value 0 R/W R/W Description Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected [Clearing condition] When transfer is completed 1: On-chip erasing program is selected (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the on-chip program or executing the downloaded programming/erasing program, these processings cannot be executed if the key code is not written. Bit: 7 6 5 4 K[7:0] 3 2 1 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 to 0 Bit Name K[7:0] Initial Value All 0 R/W R/W Description Key Code Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing of flash memory can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. H'A5: Writing to the SCO bit is enabled (The SCO bit cannot be set by a value other than H'A5.) H'5A: Programming/erasing is enabled (A value other than H'5A enables software protection state.) H'00: Initial value Rev. 4.00 Jul. 25, 2008 Page 590 of 750 REJ09B0243-0400 Section 17 Flash Memory (5) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00. Bit: 7 TDER 6 5 4 3 TDA[6:0] 2 1 0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name TDER Initial Value 0 R/W R/W Description Transfer Destination Address Setting Error This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is tested by checking whether the setting of TDA6 to TDA0 is between the range of H'02 to H'04 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'02 to H'04 as well as clearing this bit to 0. 0: Setting of TDA6 to TDA0 is normal 1: Setting of TDER and TDA6 to TDA0 is H'00 to H'01 and H'05 to H'FF and download has been aborted Rev. 4.00 Jul. 25, 2008 Page 591 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 6 to 0 Bit Name TDA[6:0] Initial Value All 0 R/W R/W Description Transfer Destination Address These bits specify the download start address. A value from H'02 to H'04 can be set to specify the download start address in on-chip RAM in 2-kbyte units. A value H'00, H'01, or H'05 to H'7F cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. H'02: Download start address is set to H'FFFFA000 H'03: Download start address is set to H'FFFFA800 H'04: Download start address is set to H'FFFFB000 H'00, H'01, H'05 to H'7F: Setting prohibited when downloading by the SCO bit with user program mode. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. When not using user program mode, setting H'00 to the TDA is no problem. 17.4.3 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined. At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.) Rev. 4.00 Jul. 25, 2008 Page 592 of 750 REJ09B0243-0400 Section 17 Flash Memory The programming/erasing interface parameters are used in the following four items. 1. 2. 3. 4. Download control Initialization before programming or erasing Programming Erasing These items use different parameters. The correspondence table is shown in table 17.6. The processing results of initialization, programming, and erasing are returned, but the bit contents have different meanings according to the processing program. See the description of FPFR for each processing. Table 17.6 Usable Parameters and Target Modes Name of Parameter ProAbbrevia- Down- Initiali- gramtion load zation ming Erasure R/W √ — — — √ √ — √ — — √ — R/W R/W R/W Initial Value Allocation Download pass/fail DPFR result Flash pass/fail result Flash programming/ erasing frequency control Flash user branch address set FPFR FPEFEQ Undefined On-chip RAM* Undefined R0 of CPU Undefined R4 of CPU FUBRA — — — √ — — — √ √ — — — R/W R/W R/W Undefined R5 of CPU Undefined R5 of CPU Undefined R4 of CPU Flash multipurpose FMPAR address area Flash multipurpose FMPDR data destination area Flash erase block select Note: * FEBS — — — √ R/W Undefined R4 of CPU One byte of start address of download destination specified by FTDAR Rev. 4.00 Jul. 25, 2008 Page 593 of 750 REJ09B0243-0400 Section 17 Flash Memory (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 17.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For the checking method of download results, see section 17.5.2 (2), Programming Procedure in User Program Mode. Bit: 7 - 6 - 5 - 4 - 3 - 2 SS 1 FK 0 SF Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 to 3 2 Bit Name  SS Initial Value R/W Description Unused Return 0. Source Select Error Detect The on-chip program which can be downloaded can be specified as only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs. 0: Download program can be selected normally 1: Download error occurs (Multi-selection or program which is not mapped is selected) Undefined R/W Undefined R/W Rev. 4.00 Jul. 25, 2008 Page 594 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 1 Bit Name FK Initial Value R/W Description Flash Key Register Error Detect Returns the check result whether the value of FKEY is set to H'A5. 0: FKEY setting is normal (FKEY = H'A5) 1: FKEY setting is abnormal (FKEY = value other than H'A5) Undefined R/W 0 SF Undefined R/W Success/Fail Returns the result whether download has ended normally or not. 0: Downloading on-chip program has ended normally (no error) 1: Downloading on-chip program has ended abnormally (error occurs) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see section 21.3.1, Clock Timing. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: R/W Bit: 15 F15 R/W 14 F14 R/W 13 F13 R/W 12 F12 R/W 11 F11 R/W 10 F10 R/W 9 F9 R/W 8 F8 R/W 7 F7 R/W 6 F6 R/W 5 F5 R/W 4 F4 R/W 3 F3 R/W 2 F2 R/W 1 F1 R/W 0 F0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Jul. 25, 2008 Page 595 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 31 to 16 Bit Name  Initial Value R/W Description Unused Return 0. Frequency Set Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency, which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4). For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows.  The number to three decimal places of 28.882 is rounded and the value is thus 28.88.  The formula that 28.88 × 100 = 2888 is converted to the binary digit and B'0000, B'1011, B'0100, B'1000 (H'0B48) is set to R4. Undefined R/W Undefined R/W 15 to 0 F15 to F0 (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit: 31 UA31 30 UA30 29 UA29 28 UA28 27 UA27 26 UA26 25 UA25 24 UA24 23 UA23 22 UA22 21 UA21 20 UA20 19 UA19 18 UA18 17 UA17 16 UA16 Initial value: R/W: R/W Bit: 15 UA15 R/W 14 UA14 R/W 13 UA13 R/W 12 UA12 R/W 11 UA11 R/W 10 UA10 R/W 9 UA9 R/W 8 UA8 R/W 7 UA7 R/W 6 UA6 R/W 5 UA5 R/W 4 UA4 R/W 3 UA3 R/W 2 UA2 R/W 1 UA1 R/W 0 UA0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Jul. 25, 2008 Page 596 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit Bit Name Initial Value R/W Description User Branch Destination Address When the user branch is not required, address 0 (H'84000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which on-chip program has been transferred, or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. The download of the on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. Store general registers R8 to R15. General registers R0 to R7 are available without storing them. Moreover, the programming/erasing interface registers must not be written to in the processing of the user branch destination. After the processing of the user branch has ended, the programming/erasing program must be returned to by using the RTS instruction. For the execution intervals of the user branch processing, see note 2 (User Branch Processing Intervals) in section 17.7.2, Other Notes. 31 to 0 UA31 to UA0 Undefined R/W Rev. 4.00 Jul. 25, 2008 Page 597 of 750 REJ09B0243-0400 Section 17 Flash Memory (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: R/W Bit: 15 - R/W 14 - R/W 13 - R/W 12 - R/W 11 - R/W 10 - R/W 9 - R/W 8 - R/W 7 - R/W 6 - R/W 5 - R/W 4 - R/W 3 - R/W 2 BR R/W 1 FQ R/W 0 SF Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description Unused Return 0. User Branch Error Detect Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded. 0: User branch address setting is normal 1: User branch address setting is abnormal 31 to 3  2 BR Undefined R/W Undefined R/W 1 FQ Undefined R/W Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF Undefined R/W Success/Fail Indicates whether initialization is completed normally. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs) Rev. 4.00 Jul. 25, 2008 Page 598 of 750 REJ09B0243-0400 Section 17 Flash Memory (3) Programming Execution When flash memory is programmed, the programming destination address and programming data on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register R4. This parameter is called FMPDR (flash multipurpose data destination area parameter). For details on the programming procedure, see section 17.5.2, User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version). (3.1) Flash multipurpose address area parameter (FMPAR: general register R5 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOA31 MOA30 MOA29 MOA28 MOA27 MOA26 MOA25 MOA24 MOA23 MOA22 MOA21 MOA20 MOA19 MOA18 MOA17 MOA16 Initial value: R/W: R/W Bit: 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 MOA8 R/W 7 MOA7 R/W 6 MOA6 R/W 5 MOA5 R/W 4 MOA4 R/W 3 MOA3 R/W 2 MOA2 R/W 1 MOA1 R/W 0 MOA0 MOA15 MOA14 MOA13 MOA12 MOA11 MOA10 MOA9 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Jul. 25, 2008 Page 599 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit Bit Name Initial Value R/W Description MOA31 to MOA0 Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. The MOA6 to MOA0 bits are always 0 because the start address of the programming destination is at the 128-byte boundary. 31 to 0 MOA31 to MOA0 Undefined R/W (3.2) Flash multipurpose data destination area parameter (FMPDR: general register R4 of CPU) This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MOD31 MOD30 MOD29 MOD28 MOD27 MOD26 MOD25 MOD24 MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16 Initial value: R/W: R/W Bit: 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 MOD15 MOD14 MOD13 MOD12 MOD11 MOD10 MOD9 MOD8 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description MOD31 to MOD0 Store the start address of the area which stores the program data for the user MAT. The consecutive 128byte data is programmed to the user MAT starting from the specified start address. 31 to 0 MOD31 to Undefined R/W MOD0 Rev. 4.00 Jul. 25, 2008 Page 600 of 750 REJ09B0243-0400 Section 17 Flash Memory (3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: R/W Bit: 15 - R/W 14 - R/W 13 - R/W 12 - R/W 11 - R/W 10 - R/W 9 - R/W 8 - R/W 7 - R/W 6 MD R/W 5 EE R/W 4 FK R/W 3 - R/W 2 WD R/W 1 WA R/W 0 SF Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description Unused Return 0. Programming Mode Related Setting Error Detect Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 17.6.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: FWE = 0 or FLER = 1, and programming cannot be performed 31 to 7  6 MD Undefined R/W Undefined R/W Rev. 4.00 Jul. 25, 2008 Page 601 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 5 Bit Name EE Initial Value R/W Description Programming Execution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed) Undefined R/W 4 FK Undefined R/W Flash Key Register Error Detect Returns the check result of the value of FKEY before the start of the programming processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A) 3 2  WD Undefined R/W Undefined R/W Unused Return 0. Write Data Address Error Detect When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. 0: Setting of write data address is normal 1: Setting of write data address is abnormal 1 WA Undefined R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. • • The programming destination address is an area other than flash memory The specified address is not at the 128-byte boundary (A6 to A0 are not 0) 0: Setting of programming destination address is normal 1: Setting of programming destination address is abnormal Rev. 4.00 Jul. 25, 2008 Page 602 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 0 Bit Name SF Initial Value R/W Description Success/Fail Indicates whether the program processing has ended normally or not. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) Undefined R/W (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register R4). One block is specified from the block number 0 to 15. For details on the erasing procedure, see section 17.5.2, User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version). (4.1) Flash erase block select parameter (FEBS: general register R4 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be specified. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: R/W Bit: 15 - R/W 14 - R/W 13 - R/W 12 - R/W 11 - R/W 10 - R/W 9 - R/W 8 - R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 EBS[7:0] Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 4.00 Jul. 25, 2008 Page 603 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit Bit Name Initial Value R/W Description Unused Return 0. • 31 to 8  7 to 0 EBS[7:0] Undefined R/W Undefined R/W 128-kbyte flash memory Set the erase-block number in the range from 0 to 9. 0 corresponds to the EB0 block and 9 corresponds to the EB9 block. An error occurs when a number other than 0 to 9 (H'00 to H'09) is set. • 64-kbyte flash memory Set the erase-block number in the range from 0 to 8. 0 corresponds to the EB0 block and 8 corresponds to the EB8 block. An error occurs when a number other than 0 to 8 (H'00 to H'08) is set. (4.2) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter returns the value of the erasing processing result. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: R/W Bit: 15 - R/W 14 - R/W 13 - R/W 12 - R/W 11 - R/W 10 - R/W 9 - R/W 8 - R/W 7 - R/W 6 MD R/W 5 EE R/W 4 FK R/W 3 EB R/W 2 - R/W 1 - R/W 0 SF Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description Unused Return 0. 31 to 7  Undefined R/W Rev. 4.00 Jul. 25, 2008 Page 604 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 6 Bit Name MD Initial Value R/W Description Erasure Mode Related Setting Error Detect Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 17.6.3, Error Protection. 0: FWE and FLER settings are normal (FWE = 1, FLER = 0) 1: FWE = 0 or FLER = 1, and erasure cannot be performed Undefined R/W 5 EE Undefined R/W Erasure Execution Error Detect 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. 0: Erasure has ended normally 1: Erasure has ended abnormally (erasure result is not guaranteed) 4 FK Undefined R/W Flash Key Register Error Detect Returns the check result of FKEY value before start of the erasing processing. 0: FKEY setting is normal (FKEY = H'5A) 1: FKEY setting is error (FKEY = value other than H'5A) 3 EB Undefined R/W Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal Rev. 4.00 Jul. 25, 2008 Page 605 of 750 REJ09B0243-0400 Section 17 Flash Memory Bit 2, 1 0 Bit Name  SF Initial Value R/W Description Unused Return 0. Success/Fail Indicates whether the erasing processing has ended normally or not. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) Undefined R/W Undefined R/W Rev. 4.00 Jul. 25, 2008 Page 606 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has two operating modes: user program mode and boot mode. For details on the pin setting for entering each mode, see table 17.1. For details on the state transition of each mode for flash memory, see figure 17.2. 17.5.1 Boot Mode Boot mode executes programming/erasing user MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The system configuration diagram in boot mode is shown in figure 17.6. For details on the pin setting in boot mode, see table 17.1. Although NMI and other interrupts are ignored in boot mode, do not generate them. This LSI Control command, analysis execution software (on-chip) Flash memory Host Boot programming tool and program data Control command, program data Reply response RXD1 On-chip SCI1 TXD1 On-chip RAM Figure 17.6 System Configuration in Boot Mode Rev. 4.00 Jul. 25, 2008 Page 607 of 750 REJ09B0243-0400 Section 17 Flash Memory (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCIcommunication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency, which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 17.7. Boot mode must be initiated in the range of this system clock. Note that the internal clock division ratio of ×1/3 is not supported in boot mode. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Measure low period (9 bits) (data is H'00) High period of at least 1 bit Figure 17.7 Automatic Adjustment Operation of SCI Bit Rate Table 17.7 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate of This LSI Host Bit Rate 9,600 bps 19,200 bps Peripheral Clock (Pφ) Frequency Which Can Automatically Adjust LSI's Bit Rate 20 to 25 MHz 20 to 25 MHz Note: The internal clock division ratio of ×1/3 is not supported in boot mode. Rev. 4.00 Jul. 25, 2008 Page 608 of 750 REJ09B0243-0400 Section 17 Flash Memory (2) State Transition Diagram Figure 17.8 gives an overview of the state transitions after the chip has been started up in boot mode. For details on boot mode, see section 17.8.1, Specifications of the Standard Serial Communications Interface in Boot Mode. 1. Bit-rate matching After the chip has been started up in boot mode, bit-rate matching between the SCI and the host proceeds. 2. Waiting for inquiry and selection commands The chip sends the requested information to the host in response to inquiries regarding the size and configuration of the user MAT, start addresses of the MATs, information on supported devices, etc. 3. Automatic erasure of the entire user MAT After all necessary inquiries and selections have been made and the command for transition to the programming/erasure state is sent by the host, the entire user MAT is automatically erased. 4. Waiting for programming/erasure command  On receiving the programming selection command, the chip waits for data to be programmed. To program data, the host transmits the programming command code followed by the address where programming should start and the data to be programmed. This is repeated as required while the chip is in the programming-selected state. To terminate programming, H'FFFFFFFF should be transmitted as the first address of the area for programming. This makes the chip return to the programming/erasure command waiting state from the programming data waiting state.  On receiving the erasure select command, the chip waits for the block number of a block to be erased. To erase a block, the host transmits the erasure command code followed by the number of the block to be erased. This is repeated as required while the chip is in the erasure-selected state. To terminate erasure, H'FF should be transmitted as the block number. This makes the chip return to the programming/erasure command waiting state from the erasure block number waiting state. Erasure should only be executed when a specific block is to be reprogrammed without executing a reset-start of the chip after the flash memory has been programmed in boot mode. If all desired programming is done in a single operation, such erasure processing is not necessary because all blocks are erased before the chip enters the programming/erasure/other command waiting state.  In addition to the programming and erasure commands, commands for sum checking and blank checking (checking for erasure) of the user MAT, reading data from the user MAT, and acquiring current state information are provided. Note that the command for reading from the user MAT can only read data that has been programmed after automatic erasure of the entire user MAT. Rev. 4.00 Jul. 25, 2008 Page 609 of 750 REJ09B0243-0400 Section 17 Flash Memory Start in boot mode (reset in boot mode) (Bit rate matching) Reception of H'00, …, H'00 f H'5 tion o 5 Bit rate matching 1. p Rece Reception of inquiry/selection command 2. Wait for inquiry/selection command Response to inquiry/selection command Execute processing in response to inquiry/ selection command 3. Erasure of entire user MAT and user boot MAT Reception of read/check command Response to command 4. Wait for programming/erasure command Execute processing in response to read/ check command Erasure block specification Erasure complete Programming complete Reception of programming select command Reception of erasure select command Wait for erasure block number Transmission of programming data by the host Wait for programming data Figure 17.8 State Transitions in Boot Mode Rev. 4.00 Jul. 25, 2008 Page 610 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.5.2 User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version) The user MAT can be programmed/erased in user program mode. Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 17.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset must not be executed. Doing so may cause damage or destroy flash memory. If reset is executed accidentally, the reset signal must be released after the reset input period, which is longer than the normal 100 µs. For details on the programming procedure, see the description in section 17.5.2 (2), Programming Procedure in User Program Mode. For details on the erasing procedure, see the description in section 17.5.2 (3), Erasing Procedure in User Program Mode. Programming/erasing start When programming, program data is prepared 1. Inputting high level to the FWE pin sets the FWE bit to 1. 2. Programming/erasing is executed only in the on-chip RAM. 3. After programming/erasing is finished, low level must be input to the FWE pin for protection. FWE = 1 ? Yes No Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end Figure 17.9 Programming/Erasing Overview Flow Rev. 4.00 Jul. 25, 2008 Page 611 of 750 REJ09B0243-0400 Section 17 Flash Memory (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. All of the on-chip program that is to be downloaded is in on-chip RAM. Note that onchip RAM must be controlled so that these parts do not overlap. Figure 17.10 shows the program area to be downloaded. Area that can be used by user Address RAMTOP (H'FFFFA000) Area to be downloaded (Size: 3 kbytes) Unusable area in programming/erasing processing period DPFR FTDAR setting (Return value: 1 byte) System use area (15 bytes) FTDAR setting + 16 Programming/ erasing entry Initialization process entry Initialization + programming program or Initialization + erasing program Area that can be used by user FTDAR setting + 3072 RAMEND (H'FFFFBFFF) FTDAR setting + 32 Figure 17.10 RAM Map after Download Rev. 4.00 Jul. 25, 2008 Page 612 of 750 REJ09B0243-0400 Section 17 Flash Memory (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 17.11. Start programming procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download Clear FKEY to 0 (2.1) Programming Set FKEY to H'5A (2.9) (2.10) (2.11) (2.12) No Clear FKEY and programming error processing (2.2) (2.3) (2.4) (2.5) No Set parameter to R4 and R5 (FMPAR and FMPDR) Programming JSR FTDAR setting + 16 Download FPFR = 0? Yes No Required data programming is completed? DPFR = 0? Yes Download error processing (2.13) (2.14) Set the FPEFEQ and FUBRA parameters (2.6) (2.7) (2.8) No Yes Clear FKEY to 0 Initialization Initialization JSR FTDAR setting + 32 End programming procedure program FPFR = 0? Yes Initialization error processing 1 Figure 17.11 Programming Procedure The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify 1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock (Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR). After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been executed, carry out erasing before writing. Rev. 4.00 Jul. 25, 2008 Page 613 of 750 REJ09B0243-0400 Section 17 Flash Memory 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shortened. (2.1) Select the on-chip program to be downloaded When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (2.2) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request. (2.3) VBR is set to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. VBR must always be set to H'84000000 before setting the SCO bit to 1. To write 1 to the SCO bit, the following conditions must be satisfied. • H'A5 is written to FKEY. • The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect decision must be prevented by setting the DPFR parameter, that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be set to H'84000000. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. • The user MAT space is switched to the on-chip program storage area. • After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting to the on-chip RAM address specified by FTDAR. • The SCO bits in FCCS, FPCS, and FECS are cleared to 0. • The return value is set to the DPFR parameter. Rev. 4.00 Jul. 25, 2008 Page 614 of 750 REJ09B0243-0400 Section 17 Flash Memory • After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed. The notes on download are as follows. In the download processing, the values of the general registers of the CPU are retained. During the download processing, interrupts must not be generated. For details on the relationship between download and interrupts, see section 17.7.1, Interrupts during Programming/Erasing. Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO bit to 1. (2.4) FKEY is cleared to H'00 for protection. (2.5) The value of the DPFR parameter must be checked to confirm the download result. A recommended procedure for confirming the download result is shown below. • Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. • If the value of the DPFR parameter is the same as before downloading (e.g. H’FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. • If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA parameter for initialization. • The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable range of the FPEFEQ parameter, see section 21.3.1, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in section 17.4.3 (2.1), Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU). Rev. 4.00 Jul. 25, 2008 Page 615 of 750 REJ09B0243-0400 Section 17 Flash Memory • The start address in the user branch destination is set to the FUBRA parameter (general register R5). When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. See the description in section 17.4.3 (2.2), Flash user branch address setting parameter (FUBRA: general register R5 of CPU). (2.7) Initialization When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L JSR NOP #DLTOP+32,R1 @R1 ; Set entry address to R1 ; Call initialization routine • The general registers other than R0 are saved in the initialization program. • R0 is a return value of the FPFR parameter. • Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved in RAM. • Interrupts can be accepted during the execution of the initialization program. However, the program storage area and stack area in on-chip RAM and register values must not be destroyed. (2.8) The return value of the initialization program, FPFR (general register R0) is checked. (2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming. (2.10) The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register R5. The start address of the program data storage area (FMPDR) is set to general register R4. • FMPAR setting FMPAR specifies the programming destination start address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value Rev. 4.00 Jul. 25, 2008 Page 616 of 750 REJ09B0243-0400 Section 17 Flash Memory parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80. • FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to on-chip RAM and then programming must be executed. (2.11) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,R1 @R1 ; Set entry address to R1 ; Call programming routine  The general registers other than R0 are saved in the programming program.  R0 is a return value of the FPFR parameter.  Since the stack area is used in the programming program, a stack area of maximum 128 bytes must be reserved in RAM. (2.12) The return value in the programming program, FPFR (general register R0) is checked. (2.13) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (2.14) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 µs. Rev. 4.00 Jul. 25, 2008 Page 617 of 750 REJ09B0243-0400 Section 17 Flash Memory (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 17.12. Start erasing procedure program Select on-chip program to be downloaded and set download destination by FTDAR Set FKEY to H'A5 After clearing VBR, set SCO to 1 and execute download Clear FKEY to 0 1 (3.1) Set FKEY to H'5A Set FEBS parameter Erasing JSR FTDAR setting + 16 (3.2) (3.3) (3.4) No Download Erasing FPFR = 0 ? Yes DPFR = 0? Clear FKEY and erasing error processing No Download error processing No Yes Required block erasing is completed? (3.5) (3.6) Set the FPEFEQ and FUBRA parameters Yes Clear FKEY to 0 Initialization Initialization JSR FTDAR setting + 32 End erasing procedure program FPFR = 0 ? No Yes Initialization error processing 1 Figure 17.12 Erasing Procedure The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. Specify 1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock (Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR). After the programming/erasing program has been downloaded and the SCO bit is cleared to 0, the setting of the frequency control register (FRQCR) can be changed to the desired value. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 17.10. Rev. 4.00 Jul. 25, 2008 Page 618 of 750 REJ09B0243-0400 Section 17 Flash Memory A single divided block is erased by one erasing processing. For block divisions, see figure 17.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see the description in section 17.5.2 (2), Programming Procedure in User Program Mode. (3.2) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter (FEBS: general register R4). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. (3.3) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L JSR NOP #DLTOP+16,R1 @R1 ; Set entry address to R1 ; Call erasing routine  The general registers other than R0 are saved in the erasing program.  R0 is a return value of the FPFR parameter.  Since the stack area is used in the erasing program, a stack area of maximum 128 bytes must be reserved in RAM. (3.4) The return value in the erasing program, FPFR (general register R0) is checked. (3.5) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to (3.5). Blocks that have already been erased can be erased again. (3.6) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 µs. Rev. 4.00 Jul. 25, 2008 Page 619 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.6 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 17.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR parameter. Table 17.8 Hardware Protection Function to be Protected Item Description Download — Programming/ Erasure √ FWE-pin protection The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming/erasing-protected state. Reset/standby protection • √ A power-on reset (including a power-on reset by the WDT) and entry to standby mode initializes the programming/erasing interface registers and the LSI enters a programming/erasing-protected state. Resetting by means of the RES pin after power is initially supplied will not make the LSI enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics. If the LSI is reset during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. √ • Rev. 4.00 Jul. 25, 2008 Page 620 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.6.2 Software Protection Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 17.9 Software Protection Function to be Protected Item Protection by the SCO bit Description Clearing the SCO bit in FCCS disables downloading of the programming/erasing program, thus making the LSI enter a programming/erasing-protected state. Download √ Programming/ Erasure √ Protection by FKEY Downloading and programming/erasing √ are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. √ 17.6.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or erasure. The FLER bit is set to 1 in the following conditions: • When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) • When a SLEEP instruction (including software standby mode) is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) only by a power-on reset. Rev. 4.00 Jul. 25, 2008 Page 621 of 750 REJ09B0243-0400 Section 17 Flash Memory Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 µs. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 17.13 shows transitions to and from the error protection state. Program mode Erase mode Read disabled Programming/erasing enabled FLER = 0 RES = 0 Er Reset or standby (Hardware protection) Read enabled Programming/erasing disabled FLER = 0 Programming/erasing interface register is in its initial state. ror (S Error occurred oc cu oft rred wa re sta RE S =0 RES = 0 nd by ) Error protection mode (Software standby) Error protection mode Read enabled Programming/erasing disabled FLER = 1 Software standby mode Read disabled Cancel Programming/erasing disabled software standby mode FLER = 1 Programming/erasing interface register is in its initial state. Figure 17.13 Transitions to and from Error Protection State Rev. 4.00 Jul. 25, 2008 Page 622 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.7 17.7.1 Usage Notes Interrupts during Programming/Erasing (1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'84000000. If VBR is set to a value other than H'84000000, the interrupt vector table is placed in the user MAT on setting H'84000000 to VBR. When VBR setting change conflicts with interrupt occurrence, whether the vector table before or after VBR is changed is referenced may cause an error. Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a vector table to be referenced when VBR is H'00000000 (initial value) at the start of the user MAT. (1.2) SCO download request and interrupt request Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover. Operation when the SCO download request and interrupt request conflicts is described below. 1. Contention between SCO download request and interrupt request Figure 17.14 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance. CPU cycle CPU operation for instruction that sets SCO bit to 1 n Fetch n+1 Decoding n+2 Execution n+3 Execution n+4 Execution Interrupt acceptance (a) (b) (a) When the interrupt is accepted at the (n + 1) cycle or before After the interrupt processing completes, the SCO bit is set to 1 and download is executed. (b) When the interrupt is accepted at the (n + 2) cycle or later The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated. Figure 17.14 Timing of Contention between SCO Download Request and Interrupt Request 2. Generation of interrupt requests during downloading Ensure that interrupts are not generated during downloading that is initiated by the SCO bit. Rev. 4.00 Jul. 25, 2008 Page 623 of 750 REJ09B0243-0400 Section 17 Flash Memory (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, the user MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the interrupt processing, temporarily save the new program data in another area. After confirming the completion of programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved. 3. Make sure the interrupt processing routine does not rewrite the contents of the flashmemory related registers or data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform download of the on-chip program by an SCO request or programming/erasing. 4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the interrupt processing, write the saved contents in the CPU registers again. 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 µs to reduce the damage to flash memory. Rev. 4.00 Jul. 25, 2008 Page 624 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.7.2 Other Notes 1. Download Time of On-Chip Program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum. 2. User Branch Processing Intervals The intervals for executing the user branch processing differ in programming and erasing. The processing phase also differs. Table 17.10 lists the maximum interval for initiating the user branch processing when the CPU clock frequency is 50 MHz. Table 17.10 Initiation Intervals of User Branch Processing Processing Name Programming Erasing Maximum Interval Approximately 4 ms Approximately 25 ms However, when operation is done with CPU clock of 50 MHz, maximum value of the time until first user branch processing is as shown in table 17.11. Table 17.11 Initial User Branch Processing Time Processing Name Programming Erasing Max. Approximately 4 ms Approximately 25 ms 3. State in which Interrupts are ignored In the following modes or period, interrupt requests are ignored; they are not executed and the interrupt sources are not retained.  Boot mode Rev. 4.00 Jul. 25, 2008 Page 625 of 750 REJ09B0243-0400 Section 17 Flash Memory 4. Compatibility with Programming/Erasing Program of Conventional F-ZTAT SH Microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 5. Monitoring Runaway by WDT Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. Rev. 4.00 Jul. 25, 2008 Page 626 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.8 17.8.1 Supplementary Information Specifications of the Standard Serial Communications Interface in Boot Mode The boot program activated in boot mode communicates with the host via the on-chip SCI of the LSI. The specifications of the serial communications interface between the host and the boot program are described below. • States of the boot program The boot program has three states. 1. Bit-rate matching state In this state, the boot program adjusts the bit rate to match that of the host. When the chip starts up in boot mode, the boot program is activated and enters the bit-rate matching state, in which it receives commands from the host and adjusts the bit rate accordingly. After bit-rate matching is complete, the boot program proceeds to the inquiry-and-selection state. 2. Inquiry-and-selection state In this state, the boot program responds to inquiry commands from the host. The device, clock mode, and bit rate are selected in this state. After making these selections, the boot program enters the programming/erasure state in response to the transition-to-programming/erasure state command. The boot program transfers the erasure program to RAM and executes erasure of the user MAT before it enters the programming/erasure state. 3. Programming/erasure state In this state, programming/erasure are executed. The boot program transfers the program for programming/erasure to RAM in line with the command received from the host and executes programming/erasure. It also performs sum checking and blank checking as directed by the respective commands. Figure 17.15 shows the flow of processing by the boot program. Rev. 4.00 Jul. 25, 2008 Page 627 of 750 REJ09B0243-0400 Section 17 Flash Memory Reset Bit rate matching state Bit rate matching Inquiry-and-selection state Wait for inquiry and selection Inquiry Inquiry processing Enter programming/erasure state Selection Selection processing Programming/erasure state Erase user MAT Wait for programming/erasure selection Programming Programming processing Erasure Erasure processing Checking Checking processing Figure 17.15 Flow of Processing by the Boot Program • Bit-rate matching state In bit-rate matching, the boot program measures the low-level intervals in a signal carrying H'00 data that is transmitted by the host, and calculates the bit rate from this. The bit rate can be changed by the new-bit-rate selection command. On completion of bit-rate matching, the boot program goes to the inquiry and selection state. The sequence of processing in bit-rate matching is shown in figure 17.16. Rev. 4.00 Jul. 25, 2008 Page 628 of 750 REJ09B0243-0400 Section 17 Flash Memory Host Boot program H'00 (max. 30 times) Measures the length of one bit H'00 (bit rate matching complete) H'55 H'E6 (response) H'FF (error) Figure 17.16 Sequence of Bit-Rate Matching • Communications protocol Formats in the communications protocol between the host and boot program after completion of the bit-rate matching are as follows. 1. One-character command or one-character response A command or response consisting of a single character used for an inquiry or the ACK code indicating normal completion. 2. n-character command or n-character response A command or response that requires n bytes of data, which is used as a selection command or response to an inquiry. The length of programming data is treated separately below. 3. Error response Response to a command in case of an error: two bytes, consisting of the error response and error code. 4. 128-byte programming command The command itself does not include data-size information. The data length is known from the response to the command for inquiring about the programming size. 5. Response to a memory reading command This response includes four bytes of size information. Rev. 4.00 Jul. 25, 2008 Page 629 of 750 REJ09B0243-0400 Section 17 Flash Memory One-character command or one-character response n-character command or n-character response Command or response Data Size Command or response Checksum Error response Error code Error response 128-byte programming command Address Command Data (n bytes) Checksum Data Checksum Response to memory read command Data size Response Figure 17.17 Formats in the Communications Protocol  Command (1 byte): Inquiry, selection, programming, erasure, checking, etc.  Response (1 byte): Response to an inquiry  Size (one or two bytes): The length of data for transfer, excluding the command/response code, size, and checksum.  Data (n bytes): Particular data for the command or response  Checksum (1 byte): Set so that the total sum of byte values from the command code to the checksum and change lower one byte to H'00.  Error response (1 byte): Error response to a command  Error code (1 byte): Indicates the type of error.  Address (4 bytes): Address for programming  Data (n bytes): Data to be programmed. "n" is known from the response to the command used to inquire about the programming size.  Data size (4 bytes): Four-byte field included in the response to a memory reading command. Rev. 4.00 Jul. 25, 2008 Page 630 of 750 REJ09B0243-0400 Section 17 Flash Memory • Inquiry-and-Selection State In this state, the boot program returns information on the flash ROM in response to inquiry commands sent from the host, and selects the device, clock mode, and bit rate in response to the respective selection commands. The inquiry and selection commands are listed in table 17.12. Table 17.12 Inquiry and Selection Commands Command H'20 H'10 H'21 H'11 H'22 Command Name Inquiry on supported devices Device selection Function Requests the device codes and their respective boot program names. Selects a device code. Inquiry on clock modes Requests the number of available clock modes and their respective values. Clock-mode selection Inquiry on frequency multipliers Selects a clock mode. Requests the number of clock signals for which frequency multipliers and divisors are selectable, the number of multiplier and divisor settings for the respective clocks, and the values of the multipliers and divisors. Requests the minimum and maximum values for operating frequency of the main clock and peripheral clock. Requests the number of user MAT areas along with their start and end addresses. Requests the number of erasure blocks along with their start and end addresses. Requests the unit of data for programming. Selects a new bit rate. On receiving this command, the boot program erases the user MAT and enters the programming/erasure state. Requests information on the current state of boot processing. H'23 H'25 H'26 H'27 H'3F H'40 Inquiry on operating frequency Inquiry on user MATs Inquiry on erasure blocks Inquiry on programming size New bit rate selection Transition to programming/erasure state Inquiry on boot program state H'4F The selection commands should be sent by the host in this order: device selection (H'10), clockmode selection (H'11), new bit rate selection (H'3F). These commands are mandatory. If the same selection command is sent two or more times, the command that is sent last is effective. Rev. 4.00 Jul. 25, 2008 Page 631 of 750 REJ09B0243-0400 Section 17 Flash Memory All commands in the above table, except for the boot program state inquiry command (H'4F), are valid until the boot program accepts the transition-to-programming/erasure state command (H'40). That is, until the transition command is accepted, the host can continue to send commands listed in the above table until it has made the necessary inquiries and selections. The host can send the boot program state inquiry command (H'4F) even after acceptance of the transition-toprogramming/erasure state command (H'40) by the boot program. (1) Inquiry on supported devices In response to the inquiry on supported devices, the boot program returns the device codes of the devices it supports and the product names of their respective boot programs. Command H'20  Command H'20 (1 byte): Inquiry on supported devices Response H'30 Number of characters … SUM Size Device code No. of devices Product name  Response H'30 (1 byte): Response to the inquiry on supported devices  Size (1 byte): The length of data for transfer excluding the command code, this field (size), and the checksum. Here, it is the total number of bytes taken up by the number of devices, number of characters, device code, and product name fields.  Number of devices (1 byte): The number of device models supported by the boot program embedded in the microcomputer.  Number of characters (1 byte): The number of characters in the device code and product name fields.  Device code (4 bytes): Device code of a supported device (ASCII encoded)  Product name (n bytes): Product code of the boot program (ASCII encoded)  SUM (1 byte): Checksum This is set so that the total sum of all bytes from the command code to the checksum is H'00. Rev. 4.00 Jul. 25, 2008 Page 632 of 750 REJ09B0243-0400 Section 17 Flash Memory (2) Device selection In response to the device selection command, the boot program sets the specified device as the selected device. The boot program will return the information on the selected device in response to subsequent inquiries. Command H'10 Size Device code SUM  Command H'10 (1 byte): Device selection  Size (1 byte): Number of characters in the device code (fixed at 4)  Device code (4 bytes): A device code that was returned in response to an inquiry on supported devices (ASCII encoded)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to device selection This is the ACK code and is returned when the specified device code matches one of the supported devices. Error response H'90 ERROR  Error response H'90 (1 byte): Error response to device selection  ERROR (1 byte): Error code H'11: Sum-check error H'21: Non-matching device code (3) Inquiry on clock modes In response to the inquiry on clock modes, the boot program returns the number of available clock modes. Command H'21  Command H'21 (1 byte): Inquiry on clock modes Response H'31 Size Mode … SUM Rev. 4.00 Jul. 25, 2008 Page 633 of 750 REJ09B0243-0400 Section 17 Flash Memory     (4) Response H'31 (1 byte): Response to the inquiry on clock modes Size (1 byte): The total length of the number of modes and mode data fields. Mode (1 byte): Selectable clock mode (example: H'01 denotes clock mode 1) SUM (1 byte): Checksum Clock-mode selection In response to the clock-mode selection command, the boot program sets the specified clock mode. The boot program will return the information on the selected clock mode in response to subsequent inquiries. Command H'11 Size Mode SUM     Command H'11 (1 byte): Clock mode selection Size (1 byte): Number of characters in the clock-mode field (fixed at 1) Mode (1 byte): A clock mode returned in response to the inquiry on clock modes SUM (1 byte): Checksum H'06 Response  Response H'06 (1 byte): Response to clock mode selection This is the ACK code and is returned when the specified clock-mode matches one of the available clock modes. Error response H'91 ERROR  Error response H'91 (1 byte): Error response to clock mode selection  ERROR (1 byte): Error code H'11: Sum-check error H'22: Non-matching clock mode Rev. 4.00 Jul. 25, 2008 Page 634 of 750 REJ09B0243-0400 Section 17 Flash Memory (5) Inquiry on frequency multipliers In response to the inquiry on frequency multipliers, the boot program returns information on the settable frequency multipliers or divisors. Command H'22  Command H'22 (1 byte): Inquiry on frequency multipliers Response H'32 Size No. of frequency types No. of multipliers Multiplier … … SUM  Response H'32 (1 byte): Response to the inquiry on frequency multipliers  Size (1 byte): The total length of the number of frequency types, number of multipliers, and multiplier fields.  Number of frequency types (1 byte): The number of operating clocks for which multipliers can be selected (for example, if frequency multiplier settings can be made for the frequencies of the main and peripheral operating clocks, the value should be H'02).  Number of multipliers (1 byte): The number of multipliers selectable for the operating frequency of the main or peripheral modules  Multiplier (1 byte): Multiplier: Numerical value in the case of frequency multiplication (e.g. H'04 for ×4) Divisor: Two’s complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for ×1/2) As many multiplier fields are included as there are multipliers or divisors, and combinations of the number of frequency types are repeated as many times as there are operating clocks.  SUM (1 byte): Checksum Rev. 4.00 Jul. 25, 2008 Page 635 of 750 REJ09B0243-0400 Section 17 Flash Memory (6) Inquiry on operating frequency In response to the inquiry on operating frequency, the boot program returns the number of operating frequencies and the maximum and minimum values. Command H'23  Command H'23 (1 byte): Inquiry on operating frequency Response H'33 Size No. of frequency types Operating freq. (max) Operating freq. (min) … SUM  Response H'33 (1 byte): Response to the inquiry on operating frequency  Size (1 byte): The total length of the number of frequency types, and maximum and minimum values of operating frequency fields.  Number of frequency types (1 byte): The number of operating clock frequencies required within the device. For example, the value two indicates main and peripheral operating clock frequencies.  Minimum value of operating frequency (2 bytes): The minimum frequency of a frequencymultiplied or -divided clock signal. The value in this field and in the maximum value field is the frequency in MHz to two decimal places, multiplied by 100 (for example, if the frequency is 20.00 MHz, the value multiplied by 100 is 2000, so H'07D0 is returned here).  Maximum value of operating frequency (2 bytes): The maximum frequency of a frequencymultiplied or -divided clock signal. As many pairs of minimum values are included as there are frequency types.  SUM (1 byte): Checksum Rev. 4.00 Jul. 25, 2008 Page 636 of 750 REJ09B0243-0400 Section 17 Flash Memory (7) Inquiry on user MATs In response to the inquiry on user MATs, the boot program returns the number of user MAT areas and their addresses. Command H'25  Command H'25 (1 byte): Inquiry on user MAT information Response H'35 Size No. of areas Last address of the area First address of the area … SUM  Response H'35 (1 byte): Response to the inquiry on user MATs  Size (1 byte): The total length of the number of areas and first and last address fields.  Number of areas (1 byte): The number of user MAT areas. H'01 is returned if the entire user MAT area is continuous.  First address of the area (4 bytes)  Last address of the area (4 bytes) As many pairs of first and last address field are included as there are areas.  SUM (1 byte): Checksum (8) Inquiry on erasure blocks In response to the inquiry on erasure blocks, the boot program returns the number of erasure blocks in the user MAT and the addresses where each block starts and ends. Command H'26  Command H'26 (1 byte): Inquiry on erasure blocks Response H'36 Size No. of blocks Last address of the block First address of the block … SUM Rev. 4.00 Jul. 25, 2008 Page 637 of 750 REJ09B0243-0400 Section 17 Flash Memory      Response H'36 (1 byte): Response to the inquiry on erasure blocks Size (2 bytes): The total length of the number of blocks and first and last address fields. Number of blocks (1 byte): The number of erasure blocks in flash memory First address of the block (4 bytes) Last address of the block (4 bytes) As many pairs of first and last address data are included as there are blocks.  SUM (1 byte): Checksum (9) Inquiry on programming size In response to the inquiry on programming size, the boot program returns the size, in bytes, of the unit for programming. Command H'27  Command H'27 (1 byte): Inquiry on programming size Response H'37 Size Programming size SUM  Response H'37 (1 byte): Response to the inquiry on programming size  Size (1 byte): The number of characters in the programming size field (fixed at 2)  Programming size (2 bytes): The size of the unit for programming This is the unit for the reception of data to be programmed.  SUM (1 byte): Checksum (10) New bit rate selection In response to the new-bit-rate selection command, the boot program changes the bit rate setting to the new bit rate and, if the setting was successful, responds to the ACK sent by the host by returning another ACK at the new bit rate. The new-bit-rate selection command should be sent after clock-mode selection. Command H'3F Size Bit rate Multiplier 2 Input frequency No. of multipliers Multiplier 1 SUM Rev. 4.00 Jul. 25, 2008 Page 638 of 750 REJ09B0243-0400 Section 17 Flash Memory  Command H'3F (1 byte): New bit rate selection  Size (1 byte): The total length of the bit rate, input frequency, number of multipliers, and multiplier fields  Bit rate (2 bytes): New bit rate The bit rate value divided by 100 should be set here (for example, to select 19200 bps, the set H'00C0, which is 192 in decimal notation).  Input frequency (2 bytes): The frequency of the clock signal fed to the boot program This should be the frequency in MHz to the second decimal place, multiplied by 100 (for example, if the frequency is 28.882 MHz, the values is truncated to the second decimal place and multiplied by 100, making 2888; so H'0B48 should be set in this field).  Number of multipliers (1 byte): The number of selectable frequency multipliers and divisors for the device. This is normally 2, which indicates the main operating frequency and the operating frequency of the peripheral modules.  Multiplier 1 (1 byte): Multiplier or divisor for the main operating frequency Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for ×4) Divisor: Two’s complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for ×1/2)  Multiplier 2 (1 byte): Multiplier or divisor for the peripheral operating frequency Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for ×4) Divisor: Two’s complement negative numerical value in the case of frequency division (e.g. H'FE [-2] for ×1/2)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to the new-bit-rate selection command This is the ACK code and is returned if the specified bit rate has been selected. Error response H'BF ERROR  Error response H'BF (1 byte): Error response to new bit rate selection  ERROR (1 byte): Error code H'11: Sum-check error H'24: Bit rate selection error (the specified bit rate is not selectable). H'25: Input frequency error (the specified input frequency is not within the range from the minimum to the maximum value). Rev. 4.00 Jul. 25, 2008 Page 639 of 750 REJ09B0243-0400 Section 17 Flash Memory H'26: Frequency multiplier error (the specified multiplier does not match an available one). H'27: Operating frequency error (the specified operating frequency is not within the range from the minimum to the maximum value). The received data are checked in the following ways. 1. Input frequency The value of the received input frequency is checked to see if it is within the range of the minimum and maximum values of input frequency for the selected clock mode of the selected device. A value outside the range generates an input frequency error. 2. Multiplier The value of the received multiplier is checked to see if it matches a multiplier or divisor that is available for the selected clock mode of the selected device. A value that does not match an available ratio generates a frequency multiplier error. 3. Operating frequency The operating frequency is calculated from the received input frequency and the frequency multiplier or divisor. The input frequency is the frequency of the clock signal supplied to the LSI, while the operating frequency is the frequency at which the LSI is actually driven. The following formulae are used for this calculation. Operating frequency = input frequency × multiplier, or Operating frequency = input frequency / divisor The calculated operating frequency is checked to see if it is within the range of the minimum and maximum values of the operating frequency for the selected clock mode of the selected device. A value outside the range generates an operating frequency error. 4. Bit rate From the peripheral operating frequency (Pφ) and the bit rate (B), the value (= n) of the clock select bits (CKS) in the serial mode register (SCSMR) and the value (= N) of the bit rate register (SCBRR) are calculated, after which the error in the bit rate is calculated. This error is checked to see if it is smaller than 4%. A result greater than or equal to 4% generates a bit rate selection error. The following formula is use to calculate the error. Error (%) = [ Pφ × 106 ]-1 (N + 1) × B × 64 × 22n-1 × 100 Rev. 4.00 Jul. 25, 2008 Page 640 of 750 REJ09B0243-0400 Section 17 Flash Memory When the new bit rate is selectable, the boot program returns an ACK code to the host and then makes the register setting to select the new bit rate. The host then sends an ACK code at the new bit rate, and the boot program responds to this with another ACK code, this time at the new bit rate. Acknowledge H'06  Acknowledge H'06 (1 byte): The ACK code sent by the host to acknowledge the new bit rate. Response H'06  Response H'06 (1 byte): The ACK code transferred in response to acknowledgement of the new bit rate The sequence of new bit rate selection is shown in figure 17.18. Host New bit rate setting Boot program Wait for one-bit period at the current bit rate setting Setting the new bit rate H'06 (ACK) New bit rate setting H'06 (ACK) at the new bit rate H'06 (ACK) at the new bit rate Figure 17.18 Sequence of New Bit Rate Selection Rev. 4.00 Jul. 25, 2008 Page 641 of 750 REJ09B0243-0400 Section 17 Flash Memory (11) Transition to the programming/erasure state In response to the transition to the programming/erasure state command, the boot program transfers the erasing program and runs it to erase any data in the user MAT. On completion of this erasure, the boot program returns the ACK code and enters the programming/erasure state. Before sending the programming selection command and data for programming, the host must select the device, clock mode, and new bit rate for the LSI by issuing the device selection command, clock-mode selection command, new-bit-rate selection command, and then initiate the transition to the programming/erasure state by sending the corresponding command to the boot program. Command H'40  Command H'40 (1 byte): Transition to programming/erasure state Response H'06  Response H'06 (1 byte): Response to the transition-to-programming/erasure state command This is returned as ACK when erasure of the user MAT has succeeded after transfer of the erasure program. Error response H'C0 H'51  Error response H'C0 (1 byte): Error response to the transition-to-programming/erasure state command  ERROR (1 byte): Error code H'51: Erasure error (Erasure did not succeed because of an error.) Rev. 4.00 Jul. 25, 2008 Page 642 of 750 REJ09B0243-0400 Section 17 Flash Memory • Command Error Command errors are generated by undefined commands, commands sent in an incorrect order, and the inability to accept a command. For example, sending the clock-mode selection command before device selection or an inquiry command after the transition-to-programming/erasure state command generates a command error. Error response H'80 H'xx  Error response H'80 (1 byte): Command error  Command H'xx (1 byte): Received command • Order of Commands In the inquiry-and-selection state, commands should be sent in the following order. 1. Send the inquiry on supported devices command (H'20) to get the list of supported devices. 2. Select a device from the returned device information, and send the device selection command (H'10) to select that device. 3. Send the inquiry on clock mode command (H'21) to get the available clock modes. 4. Select a clock mode from among the returned clock modes, and send the clock-mode selection command (H'11). 5. After selection of the device and clock mode, send the commands to inquire about frequency multipliers (H'22) and operating frequencies (H'23) to get the information required to select a new bit rate. 6. Taking into account the returned information on the frequency multipliers and operating frequencies, send a new-bit-rate selection command (H'3F). 7. After the device and clock mode have been selected, get the information required for programming and erasure of the user MAT by sending the commands to inquire about the user MAT (H'25), erasure block (H'26), and programming size (H'27). 8. After making all necessary inquiries and the new bit rate selection, send the transition-toprogramming/erasure state command (H'40) to place the boot program in the programming/erasure state. Rev. 4.00 Jul. 25, 2008 Page 643 of 750 REJ09B0243-0400 Section 17 Flash Memory • Programming/Erasure State In this state, the boot program must select the form of programming corresponding to the programming-selection command and then write data in response to 128-byte programming commands, or perform erasure in block units in response to the erasure-selection and blockerasure commands. The programming and erasure commands are listed in table 17.13. Table 17.13 Programming and Erasure Commands Command H'43 H'50 H'48 H'58 H'52 H'4B H'4D H'4F Command Name Selection of user MAT programming Function Selects transfer of the program for user MAT programming. 128-byte programming Executes 128-byte programming. Erasure selection Block erasure Memory read Sum checking of user MAT Selects transfer of the erasure program. Executes erasure of the specified block. Reads from memory. Executes sum checking of the user MAT. Blank checking of user Executes blank checking of the user MAT. MAT Inquiry on boot program state Requests information on the state of boot processing. • Programming Programming is performed by issuing a programming-selection command and the 128-byte programming command. Firstly, the host issues the programming-selection command to select the MAT to be programmed and programming by the method. Next, the host issues a 128-byte programming command. 128 bytes of data for programming by the method selected by the preceding programming selection command are expected to follow the command. To program more than 128 bytes, repeatedly issue 128-byte programming commands. To terminate programming, the host should send another 128-byte programming command with the address H'FFFFFFFF. On completion of programming, the boot program waits for the next programming/erasure selection command. To then program the other MAT, start by sending the programming select command. Rev. 4.00 Jul. 25, 2008 Page 644 of 750 REJ09B0243-0400 Section 17 Flash Memory The sequence of programming by programming-selection and 128-byte programming commands is shown in figure 17.19. Host Programming selection (H'42, H'43) Transfer the program that performs programming ACK 128-byte programming (address and data) Repeat ACK Programming Boot program 128-byte programming (H'FFFFFFFF) ACK Figure 17.19 Sequence of Programming (1) Selection of user MAT programming In response to the command for selecting programming of the user MAT, the boot program transfers the corresponding flash-writing program, i.e. the program for writing to the user MAT. Command H'43  Command H'43 (1 byte): Selects programming of the user MAT. Response H'06  Response H'06 (1 byte): Response to selection of user MAT programming This ACK code is returned after transfer of the program that performs writing to the user MAT. Error response H'C3 ERROR  Error response H'C3 (1 byte): Error response to selection of user MAT programming Rev. 4.00 Jul. 25, 2008 Page 645 of 750 REJ09B0243-0400 Section 17 Flash Memory  ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error) (2) 128-byte programming In response to the 128-byte programming command, the boot program executes the flash-writing program transferred in response to the command to program into the user MAT. Command H'50 Data … SUM Address for programming …  Command H'50 (1 byte): 128-byte programming  Address for programming (4 bytes): Address where programming starts Specify an address on a 128-byte boundary. [Example] H'00, H01, H'00, H'00: H'00010000  Programming data (n bytes): Data for programming The length of the programming data is the size returned in response to the programming size inquiry command.  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to 128-byte programming The ACK code is returned on completion of the requested programming. Error response H'D0 ERROR  Error response H'D0 (1 byte): Error response to 128-byte programming  ERROR (1 byte): Error code H'11: Sum-check error H'2A: Address error (the address is not within the range for the selected MAT) H'53: Programming error (programming failed because of an error in programming) Rev. 4.00 Jul. 25, 2008 Page 646 of 750 REJ09B0243-0400 Section 17 Flash Memory The specified address should be on a boundary corresponding to the unit of programming (programming size). For example, when programming 128 bytes of data, the lowest byte of the address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the host should transmit the data after padding the vacant bytes with H'FF. To terminate programming of a given MAT, send a 128-byte programming command with the address field H'FFFFFFFF. This informs the boot program that all data for the selected MAT have been sent; the boot program then waits for the next programming/erasure selection command. Command H'50 Address for programming SUM  Command H'50 (1 byte): 128-byte programming  Address for programming (4 bytes): Terminating code (H'FF, H'FF, H'FF, H'FF)  SUM (1 byte): Checksum Response H'06  Response H'06 (1 byte): Response to 128-byte programming This ACK code is returned on completion of the requested programming. Error response H'D0 ERROR  Error response H'D0 (1 byte): Error response to 128-byte programming  ERROR (1 byte): Error code H'11: Sum-check error H'53: Programming error Rev. 4.00 Jul. 25, 2008 Page 647 of 750 REJ09B0243-0400 Section 17 Flash Memory • Erasure Erasure is performed by issuing the erasure selection command and then one or more block erasure commands. Firstly, the host sends the erasure selection command to select erasure; after that, it sends a block erasure command to actually erase a specific block. To erase multiple blocks, send further block erasure commands. To terminate erasure, the host should send a block erasure command with the block number H'FF. After this, the boot program waits for the next programming/erasure selection command. The sequence of erasure by the erasure selection command and block erasure command is shown in figure 17.20. Host Erasure selection (H'48) Transfer the program that performs erasure ACK Boot program Erasure (block number) Repeat ACK Erasure Erasure (H'FF) ACK Figure 17.20 Sequence of Erasure Rev. 4.00 Jul. 25, 2008 Page 648 of 750 REJ09B0243-0400 Section 17 Flash Memory (1) Select erasure In response to the erasure selection command, the boot program transfers the program that performs erasure, i.e. erases data in the user MAT. Command H'48  Command H'48 (1 byte): Selects erasure. Response H'06  Response H'06 (1 byte): Response to selection of erasure This ACK code is returned after transfer of the program that performs erasure. Error response H'C8 ERROR  Error response H'C8 (1 byte): Error response to selection of erasure  ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error.) (2) Block erasure In response to the block erasure command, the boot program erases the data in a specified block of the user MAT. Command H'58 Size Block number SUM     Command H'58 (1 byte): Erasure of a block Size (1 byte): The number of characters in the block number field (fixed at 1) Block number (1 byte): Block number of the block to be erased SUM (1 byte): Checksum H'06 Response  Response H'06 (1 byte): Response to the block erasure command This ACK code is returned when the block has been erased. Rev. 4.00 Jul. 25, 2008 Page 649 of 750 REJ09B0243-0400 Section 17 Flash Memory Error response H'D8 ERROR  Error response H'D8 (1 byte): Error response to the block erasure command  ERROR (1 byte): Error code H'11: Sum-check error H'29: Block number error (the specified block number is incorrect.) H'51: Erasure error (an error occurred during erasure.) On receiving the command with H'FF as the block number, the boot program stops erasure processing and waits for the next programming/erasure selection command. Command H'58 Size Block number SUM     Command H'58 (1 byte): Erasure of a block Size (1 byte): The number of characters in the block number field (fixed at 1) Block number (1 byte): H'FF (erasure terminating code) SUM (1 byte): Checksum H'06 Response  Response H'06 (1 byte): ACK code to indicate response to the request for termination of erasure To perform erasure again after having issued the command with the block number specified as H'FF, execute the process from the selection of erasure. • Memory read In response to the memory read command, the boot program returns the data from the specified address. Command H'52 Amount to read Size Area First address for reading SUM  Command H'52 (1 byte): Memory read  Size (1 byte): The total length of the area, address for reading, and amount to read fields (fixed value of 9) Rev. 4.00 Jul. 25, 2008 Page 650 of 750 REJ09B0243-0400 Section 17 Flash Memory  Area (1 byte): H'01: User MAT An incorrect area specification will produce an address error.  Address where reading starts (4 bytes)  Amount to read (4 bytes): The amount of data to be read  SUM (1 byte): Checksum Response H'52 Data SUM Amount to read …     Error Response H'52 (1 byte): Response to the memory read command Amount to read (4 bytes): The amount to read as specified in the memory read command Data (n bytes): The specified amount of data read out from the specified address SUM (1 byte): Checksum response H'D2 ERROR  Error response H'D2 (1 byte): Error response to memory read command  ERROR (1 byte): Error code H'11: Sum-check error H'2A: Address error (the address specified for reading is beyond the range of the MAT) H'2B: Size error (the specified amount is greater than the size of the MAT, the last address for reading as calculated from the specified address for the start of reading and the amount to read is beyond the MAT area, or "0" was specified as the amount to read) Rev. 4.00 Jul. 25, 2008 Page 651 of 750 REJ09B0243-0400 Section 17 Flash Memory • Sum checking of the user MAT In response to the command for sum checking of the user MAT, the boot program adds all bytes of data in the user MAT and returns the result. Command H'4B  Command H'4B (1 byte): Sum checking of the user MAT Response H'5B Size Checksum for the MAT SUM  Response H'5B (1 byte): Response to sum checking of the user MAT  Size (1 byte): The number of characters in the checksum for the MAT (fixed to 4)  Checksum for the MAT (4 bytes): Result of checksum calculation for the user MAT: the total of all data in the MAT, in byte units.  SUM (1 byte): Checksum (for the transmitted data) • Blank checking of the user MAT In response to the command for blank checking of the user MAT, the boot program checks to see if the whole of the user MAT is blank; the value returned indicates the result. Command H'4D  Command H'4D (1 byte): Blank checking of the user MAT Response H'06  Response H'06 (1 byte): Response to blank checking of the user MAT The ACK code is returned when the whole area is blank (all bytes are H'FF). Error response H'CD H'52  Error response H'CD (1 byte): Error response to blank checking of the user MAT  Error code H'52 (1 byte): Non-erased error Rev. 4.00 Jul. 25, 2008 Page 652 of 750 REJ09B0243-0400 Section 17 Flash Memory • Inquiry on boot program state In response to the command for inquiry on the state of the boot program, the boot program returns an indicator of its current state and error information. This inquiry can be made in the inquiry-andselection state or the programming/erasure state. Command H'4F  Command H'4F (1 byte): Inquiry on boot program state Response H'5F Size STATUS ERROR SUM  Response H'5F (1 byte): Response to the inquiry regarding boot-program state  Size (1 byte): The number of characters in STATUS and ERROR (fixed at 2)  STATUS (1 byte): State of the standard boot program See table 17.14, Status Codes.  ERROR (1 byte): Error state (indicates whether the program is in normal operation or an error has occurred) ERROR = 0: Normal ERROR ≠ 0: Error See table 17.15, Error Codes.  SUM (1 byte): Checksum Table 17.14 Status Codes Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Waiting for device selection Waiting for clock-mode selection Waiting for bit-rate selection Waiting for transition to programming/erasure status (bit-rate selection complete) Erasing the user MAT Waiting for programming/erasure selection (erasure complete) Waiting to receive data for programming (programming complete) Waiting for erasure block specification (erasure complete) Rev. 4.00 Jul. 25, 2008 Page 653 of 750 REJ09B0243-0400 Section 17 Flash Memory Table 17.15 Error Codes Code H'00 H'11 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No error Sum check error Non-matching device code error Non-matching clock mode error Bit-rate selection failure Input frequency error Frequency multiplier error Operating frequency error Block number error Address error Data length error (size error) Erasure error Non-erased error Programming error Selection processing error Command error Bit-rate matching acknowledge error 17.8.2 Areas for Storage of the Procedural Program and Data for Programming In the descriptions in the previous section, storable areas for the programming/erasing procedure programs and program data are assumed to be in on-chip RAM. However, the procedure programs and data can be executed in other areas as long as the following conditions are satisfied. 1. The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. 2. The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure this area is reserved. 3. Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. 4. The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been decided. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, interrupt vector Rev. 4.00 Jul. 25, 2008 Page 654 of 750 REJ09B0243-0400 Section 17 Flash Memory table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. 5. The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip RAM. 6. After programming/erasing, access to flash memory is inhibited until FKEY is cleared. A reset state (RES = 0) for more than at least 100 µs must be taken when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state during programming/erasing are inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset state than usual (100 µs) is needed before the reset signal is released. 7. When the program data storage area indicated by the FMPDR parameter in the programming processing is within the flash memory area, an error will occur. Therefore, temporarily transfer the program data to on-chip RAM to change the address set in FMPDR to an address other than flash memory. Tables 17.16 and 17.17 show the areas in which the program data can be stored and executed according to the operation type and mode. Table 17.16 Executable MAT Initiated Mode Operation Programming Erasing User Program Mode Table 17.17 (1) Table 17.17 (2) Rev. 4.00 Jul. 25, 2008 Page 655 of 750 REJ09B0243-0400 Section 17 Flash Memory Table 17.17 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program Storage MAT — Item Program data storage area Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) Key register clearing Deciding download result Download error processing Setting initialization parameters Programming procedure Initialization Deciding initialization result Initialization error processing Interrupt processing routine Writing H'5A to key register On-Chip RAM √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ User MAT X* √ √ X √ √ √ √ X √ √ X √ X X X X X User MAT — √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Setting programming parameters √ Programming Deciding programming result Programming error processing Key register clearing Note: * If the data has been transferred to on-chip RAM in advance, this area can be used. Rev. 4.00 Jul. 25, 2008 Page 656 of 750 REJ09B0243-0400 Section 17 Flash Memory Table 17.17 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program Storage MAT Item Selecting on-chip program to be downloaded Writing H'A5 to key register Writing 1 to SCO in FCCS (download) Key register clearing Deciding download result Download error processing Setting initialization parameters Initialization Erasing Deciding initialization result proceInitialization error processing dure Interrupt processing routine Writing H'5A to key register Setting erasure parameters Erasure Deciding erasure result Erasing error processing Key register clearing On-Chip RAM √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ User MAT √ √ X √ √ √ √ X √ √ X √ X X X X X User MAT √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Rev. 4.00 Jul. 25, 2008 Page 657 of 750 REJ09B0243-0400 Section 17 Flash Memory 17.9 Off-Board Programming Mode A PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 128-Kbyte flash memory on-chip MCU device type (F-ZTAT128DV5). Rev. 4.00 Jul. 25, 2008 Page 658 of 750 REJ09B0243-0400 Section 18 RAM Section 18 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus (L bus), enabling 8, 16, or 32-bit width access to data in the on-chip RAM. The on-chip RAM is allocated to different addresses according to each product as shown in figure 18.1. The on-chip RAM can be accessed from the CPU (via the L bus). An access from the L bus (CPU) is a 1-cycle access. In addition, the contents of the on-chip RAM are retained in sleep mode or software standby mode, and at a power-on reset or manual reset. The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control register (RAMCR). For details on the RAM control register (RAMCR), refer to section 19.3.7, RAM Control Register (RAMCR). H'FFFFA000 H'FFFFBFFF Page 1 8 kbytes SH7125/SH7124 (8 kbytes) Figure 18.1 On-chip RAM Addresses RAM0200A_010020030800 Rev. 4.00 Jul. 25, 2008 Page 659 of 750 REJ09B0243-0400 Section 18 RAM 18.1 18.1.1 Usage Notes Module Standby Mode Setting RAM can be enabled/disabled by the standby control register. The initial value enables RAM operation. RAM access is disabled by setting the module standby mode. For details, see section 19, Power-Down Modes. 18.1.2 Address Error When an address error in write access to the on-chip RAM occurs, the contents of the on-chip RAM may be corrupted. 18.1.3 Initial Values in RAM After power has been supplied, initial values in RAM remain undefined until RAM is written. Rev. 4.00 Jul. 25, 2008 Page 660 of 750 REJ09B0243-0400 Section 19 Power-Down Modes Section 19 Power-Down Modes This LSI supports the following power-down modes: sleep mode, software standby mode, and module standby mode. 19.1 Features • Supports sleep mode, software standby mode, and module standby mode. 19.1.1 Types of Power-Down Modes This LSI has the following power-down modes. • Sleep mode • Software standby mode • Module standby mode Table 19.1 shows the methods to make a transition from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Rev. 4.00 Jul. 25, 2008 Page 661 of 750 REJ09B0243-0400 Section 19 Power-Down Modes Table 19.1 States of Power-Down Modes State CPU CPG CPU Register On-Chip Memory Runs On-Chip Peripheral Modules Canceling Procedure Run • Reset Mode Sleep Transition Method Execute SLEEP Runs Halts Held instruction with STBY bit in STBCR1 cleared to 0. Halts Halts Held Execute SLEEP instruction with STBY bit in STBCR1 and STBYMD bit in STBCR6 set to 1. Runs Runs Held Set MSTP bits in STBCR2 to STBCR5 to 1. Software standby Halts (contents retained) Halt • • Interrupt by NMI or IRQ Power-on reset by the RES pin Module standby Specified Specified module halts module halts (contents retained) • • Clear MSTP bit to 0 Power-on reset (for modules whose MSTP bit has an initial value of 0) Note: For details on the states of on-chip peripheral module registers in each mode, refer to section 20.3, Register States in Each Operating Mode. For details on the pin states in each mode, refer to appendix A, Pin States. Rev. 4.00 Jul. 25, 2008 Page 662 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.2 Input/Output Pins Table 19.2 lists the pins used for the power-down modes. Table 19.2 Pin Configuration Pin Name Power-on reset Manual reset Abbr. RES MRES I/O Input Input Description Power-on reset input signal. Power-on reset by low level. Manual reset input signal. Manual reset by low level. 19.3 Register Descriptions There are following registers used for the power-down modes. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. Table 19.3 Register Configuration Register Name Standby control register 1 Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 RAM control register Abbreviation STBCR1 STBCR2 STBCR3 STBCR4 STBCR5 STBCR6 RAMCR R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'38 H'FF H'FF H'03 H'00 H'10 Address H'FFFFE802 H'FFFFE804 H'FFFFE806 H'FFFFE808 H'FFFFE80A H'FFFFE80C H'FFFFE880 Access Size 8 8 8 8 8 8 8 Rev. 4.00 Jul. 25, 2008 Page 663 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.3.1 Standby Control Register 1 (STBCR1) STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode. Bit: 7 STBY 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 7 Bit Name STBY Initial Value 0 R/W R/W Description Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction makes this LSI sleep mode 1: Executing SLEEP instruction makes this LSI software standby mode 6 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 664 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.3.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the RAM operation in power-down mode. Bit: 7 MSTP 7 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: 0 R/W: R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 R 0 R 0 R Bit 7 Bit Name MSTP7 Initial Value 0 R/W R/W Description Module Stop Bit 7 When this bit is set to 1, the supply of the clock to the RAM is halted. 0: RAM operates 1: Clock supply to RAM halted 6  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 to 3  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. 2 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 665 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.3.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: 7 - 6 - 5 MSTP 13 4 MSTP 12 3 MSTP 11 2 - 1 - 0 - Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 7, 6 Bit Name  Initial Value All 1 R/W R/W Description Reserved These bits are always read as 1. The write value should always be 1. 5 MSTP13 1 R/W Module Stop Bit 13 When this bit is set to 1, the supply of the clock to the SCI_2 is halted. 0: SCI_2 operates 1: Clock supply to SCI_2 halted 4 MSTP12 1 R/W Module Stop Bit 12 When this bit is set to 1, the supply of the clock to the SCI_1 is halted. 0: SCI_1 operates 1: Clock supply to SCI_1 halted 3 MSTP11 1 R/W Module Stop Bit 11 When this bit is set to 1, the supply of the clock to the SCI_0 is halted. 0: SCI_0 operates 1: Clock supply to SCI_0 halted 2 to 0  All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. Rev. 4.00 Jul. 25, 2008 Page 666 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.3.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: 7 - 6 MSTP 22 5 MSTP 21 4 - 3 - 2 - 1 MSTP 17 0 MSTP 16 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R 1 R 1 R/W 1 R/W 1 R/W Bit 7 Bit Name  Initial Value 1 R/W R/W Description Reserved This bit is always read as 1. The write value should always be 1. 6 MSTP22 1 R/W Module Stop Bit 22 When this bit is set to 1, the supply of the clock to the MTU2 is halted. 0: MTU2 operates 1: Clock supply to MTU2 halted 5 MSTP21 1 R/W Module Stop Bit 21 When this bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT operates 1: Clock supply to CMT halted 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 2  1 R/W Reserved This bit is always read as 1. The write value should always be 1. 1 MSTP17 1 R/W Module Stop Bit 17 When this bit is set to 1, the supply of the clock to the A/D_1 is halted. 0: A/D_1 operates 1: Clock supply to A/D_1 halted Rev. 4.00 Jul. 25, 2008 Page 667 of 750 REJ09B0243-0400 Section 19 Power-Down Modes Bit 0 Bit Name MSTP16 Initial Value 1 R/W R/W Description Module Stop Bit 16 When this bit is set to 1, the supply of the clock to the A/D_0 is halted. 0: A/D_0 operates 1: Clock supply to A/D_0 halted 19.3.5 Standby Control Register 5 (STBCR5) STBCR5 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode. Bit: 7 - 6 - 5 - 4 - 3 - 2 - 1 0 MSTP[25:24] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 1 R/W Bit 7 to 2 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 MSTP[25:24] 11 R/W Module Stop Bit 25 and 24 When either or both of these bits are set to 1, the supply of the clock to the UBC is halted. 00: UBC operates 01: Setting prohibited 10: Setting prohibited 11: Clock supply to UBC halted Rev. 4.00 Jul. 25, 2008 Page 668 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.3.6 Standby Control Register 6 (STBCR6) STBCR6 is an 8-bit readable/writable register that specifies the state of the power-down modes. Bit: 7 UBC RST 6 HIZ 5 - 4 - 3 - 2 - 1 STBY MD 0 - Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R Bit 7 Bit Name UBCRST Initial Value 0 R/W R/W Description UBC Software Reset Resetting the PC trace unit of UBC is controlled by software. Clearing this bit to 0 puts the PC trace unit of the UBC module into the power-on reset state. 0: Puts the PC trace unit of UBC into the reset state 1: Releases reset in the PC trace unit of UBC 6 HIZ 0 R/W Port High-Impedance In software standby mode, this bit selects whether the pin state is retained or changed to high-impedance. 0: In software standby mode, the pin state is retained 1: In software standby mode, the pin state is changed to high-impedance 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 STBYMD 0 R/W Software Standby Mode Select If this bit is set to 1, executing SLEEP instruction with the STBY bit in STBCR1 is 1 and makes transition to software standby mode. 0: Setting prohibited 1: Makes transition to software standby mode 0  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 669 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.3.7 RAM Control Register (RAMCR) RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM. Bit: 7 - 6 - 5 - 4 RAME 3 - 2 - 1 - 0 - Initial value: R/W: 0 R 0 R 0 R 1 R/W 0 R 0 R 0 R 0 R Bit 7 to 5 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 RAME 1 R/W RAM Enable This bit enables/disables the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled When this bit is cleared to 0, the access to the on-chip RAM is disabled. In this case, an undefined value is returned when reading or fetching the data or instruction from the on-chip RAM, and writing to the onchip RAM is ignored. When RAME is cleared to 0 to disable the on-chip RAM, an instruction to access the on-chip RAM should not be set next to the instruction to write RAMCR. If such an instruction is set, normal access is not guaranteed. When RAME is set to 1 to enable the on-chip RAM, an instruction to read RAMCR should be set next to the instruction to write to RAMCR. If an instruction to access the on-chip RAM is set next to the instruction to write to RAMCR, normal access is not guaranteed. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Jul. 25, 2008 Page 670 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.4 19.4.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to operate. 19.4.2 Canceling Sleep Mode Sleep mode is canceled by a reset. (1) Canceling with Reset Sleep mode is canceled by a power-on reset with the RES pin, a manual reset with the MRES pin, or an internal power-on/manual reset by WDT. Do not cancel sleep mode with an interrupt. Rev. 4.00 Jul. 25, 2008 Page 671 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.5 19.5.1 Software Standby Mode Transition to Software Standby Mode This LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR1 and the STBYMD bit in STBCR6 are set to 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The contents of the CPU registers and the data of the on-chip RAM remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. For details on the states of onchip peripheral module registers in software standby mode, refer to section 20.3, Register States in Each Operating Mode. For details on the pin states in software standby mode, refer to appendix A, Pin States. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT. 2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY bit in STBCR1 and the STBYMD bit in STBCR6 to 1, execute the SLEEP instruction. 4. Software standby mode is entered and the clocks within this LSI are halted. Rev. 4.00 Jul. 25, 2008 Page 672 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.5.2 Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI, IRQ) or a reset. (1) Canceling with Interrupt The WDT can be used for hot starts. When an NMI or IRQ interrupt (edge detection) is detected, the clock will be supplied to the entire LSI and software standby mode will be canceled after the time set in the timer control/status register of the WDT has elapsed. Interrupt exception handling is then executed. When the priority level of an IRQ interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing software standby mode from being canceled. When falling-edge detection is selected for the NMI pin, drive the NMI pin high before making a transition to software standby mode. When rising-edge detection is selected for the NMI pin, drive the NMI pin low before making a transition to software standby mode. Similarly, when falling-edge detection is selected for the IRQ pin, drive the IRQ pin high before making a transition to software standby mode. When rising-edge detection is selected for the IRQ pin, drive the IRQ pin low before making a transition to software standby mode. (2) Canceling with Power-on Reset Software standby mode is canceled by a power-on reset with the RES pin. Keep the RES pin low until the clock oscillation settles. (3) Canceling with Manual Reset Note that software standby mode cannot be canceled with a manual reset in this LSI. Rev. 4.00 Jul. 25, 2008 Page 673 of 750 REJ09B0243-0400 Section 19 Power-Down Modes 19.6 19.6.1 Module Standby Mode Transition to Module Standby Mode Setting the MSTP bits in the standby control registers (STBCR2 to STBCR5) to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode. Do not access registers of an on-chip peripheral module, which has been set to enter module standby mode. For details on the states of on-chip peripheral module registers in module standby mode, refer to section 20.3, Register States in Each Operating Mode. 19.6.2 Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits in STBCR2 to STBCR5 to 0. The module standby function can be canceled by a power-on reset for modules whose MSTP bit has an initial value of 0. 19.7 19.7.1 Usage Note Current Consumption while Waiting for Oscillation to be Stabilized The current consumption while waiting for oscillation to be stabilized is higher than that while oscillation is stabilized. 19.7.2 Executing the SLEEP Instruction Apply either of the following measures before executing the SLEEP instruction to initiate the transition to sleep mode or software standby mode. Measure A: Stop the generation of interrupts from on-chip peripheral modules, IRQ interrupts, and the NMI interrupt before executing the SLEEP instruction. Measure B: Change the value in FRQCR to the initial value, H’36DB, and then dummy-read FRQCR twice before executing the SLEEP instruction. Rev. 4.00 Jul. 25, 2008 Page 674 of 750 REJ09B0243-0400 Section 20 List of Registers Section 20 List of Registers This section gives information on internal I/O registers. The contents of this section are as follows: 1. Register Address Table (in the order from a lower address) • Registers are listed in the order from lower allocated addresses. • As for reserved addresses, the register name column is indicated with . Do not access reserved addresses. • As for 16- or 32-bit address, the MSB addresses are shown. • The list is classified according to module names. • The numbers of access cycles are given. 2. • • • • Register Bit Table Bit configurations are shown in the order of the register address table. As for reserved bits, the bit name column is indicated with . As for the blank column of the bit names, the whole register is allocated to the counter or data. As for 16- or 32-bit registers, bits are indicated from the MSB. 3. Register State in Each Operating Mode • Register states are listed in the order of the register address table. • Register states in the basic operating mode are shown. As for modules including their specific states such as reset, see the sections of those modules. Rev. 4.00 Jul. 25, 2008 Page 675 of 750 REJ09B0243-0400 Section 20 List of Registers 20.1 Register Address Table (In the Order from Lower Addresses) Access sizes are indicated with the number of bits. Access states are indicated with the number of specified reference clock states. These values are those at 8-bit access (B), 16-bit access (W), or 32-bit access (L). Note: Access to undefined or reserved addresses is prohibited. Correct operation cannot be guaranteed if these addresses are accessed. Number of Register Name Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Serial direction control register_0 Serial port register_0 Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Serial direction control register_1 Serial port register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Serial direction control register_2 Serial port register_2 Abbreviation Bits SCSMR_0 SCBRR_0 SCSCR_0 SCTDR_0 SCSSR_0 SCRDR_0 SCSDCR_0 SCSPTR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCTDR_1 SCSSR_1 SCRDR_1 SCSDCR_1 SCSPTR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCTDR_2 SCSSR_2 SCRDR_2 SCSDCR_2 SCSPTR_2 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFFFC000 H'FFFFC002 H'FFFFC004 H'FFFFC006 H'FFFFC008 H'FFFFC00A H'FFFFC00C H'FFFFC00E H'FFFFC080 H'FFFFC082 H'FFFFC084 H'FFFFC086 H'FFFFC088 H'FFFFC08A H'FFFFC08C H'FFFFC08E H'FFFFC100 H'FFFFC102 H'FFFFC104 H'FFFFC106 H'FFFFC108 H'FFFFC10A H'FFFFC10C H'FFFFC10E SCI (Channel 2) SCI (Channel 1) Module SCI (Channel 0) Access Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Pφ reference B: 2 Pφ reference B: 2 Number of Access States Pφ reference B: 2 Rev. 4.00 Jul. 25, 2008 Page 676 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 Timer I/O control register H_4 Timer I/O control register L_4 Timer interrupt enable register_3 Timer interrupt enable register_4 Timer output master enable register Timer gate control register Timer output control register 1 Timer output control register 2 Timer counter_3 Timer counter_4 Timer cycle data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer sub-counter Timer cycle buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 Timer interrupt skipping set register Abbreviation Bits TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TITCR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 Address H'FFFFC200 H'FFFFC201 H'FFFFC202 H'FFFFC203 H'FFFFC204 H'FFFFC205 H'FFFFC206 H'FFFFC207 H'FFFFC208 H'FFFFC209 H'FFFFC20A H'FFFFC20D H'FFFFC20E H'FFFFC20F H'FFFFC210 H'FFFFC212 H'FFFFC214 H'FFFFC216 H'FFFFC218 H'FFFFC21A H'FFFFC21C H'FFFFC21E H'FFFFC220 H'FFFFC222 H'FFFFC224 H'FFFFC226 H'FFFFC228 H'FFFFC22A H'FFFFC22C H'FFFFC22D H'FFFFC230 Module MTU2 Access Size 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 8, 16 8 8 8 8, 16 8 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 8, 16 Number of Access States MPφ reference B: 2, W: 2, L: 4 Rev. 4.00 Jul. 25, 2008 Page 677 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Timer interrupt skipping counter Timer buffer transfer set register Timer dead time enable register Timer output level buffer register Timer buffer operation transfer mode register_3 Timer buffer operation transfer mode register_4 Timer A/D converter start request control register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4 Timer waveform control register Timer start register Timer synchronous register Timer read/write enable register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 TWCR TSTR TSYR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 8 8 8 8 8 8 8 8 8 8 16 16 16 H'FFFFC260 H'FFFFC280 H'FFFFC281 H'FFFFC284 H'FFFFC300 H'FFFFC301 H'FFFFC302 H'FFFFC303 H'FFFFC304 H'FFFFC305 H'FFFFC306 H'FFFFC308 H'FFFFC30A 8 8, 16 8 8 8, 16, 32 8 8, 16 8 8, 16, 32 8 16 16, 32 16 TADCOBRB_4 16 H'FFFFC24A 16 TADCOBRA_4 16 H'FFFFC248 16, 32 TADCORB_4 16 H'FFFFC246 16 TADCORA_4 16 H'FFFFC244 16, 32 TADCR 16 H'FFFFC240 16 TBTM_4 8 H'FFFFC239 8 Abbreviation TITCNT TBTER TDER TOLBR TBTM_3 Bits 8 8 8 8 8 Address H'FFFFC231 H'FFFFC232 H'FFFFC234 H'FFFFC236 H'FFFFC238 Module MTU2 Access Size 8 8 8 8 8, 16 Number of Access States MPφ reference B: 2, W: 2, L: 4 Rev. 4.00 Jul. 25, 2008 Page 678 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Timer general register C_0 Timer general register D_0 Timer general register E_0 Timer general register F_0 Timer interrupt enable register 2_0 Timer status register 2_0 Timer buffer operation transfer mode register_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer input capture control register Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer counter U_5 Timer general register U_5 Timer control register U_5 Timer I/O control register U_5 Timer counter V_5 Timer general register V_5 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 H'FFFFC380 H'FFFFC381 H'FFFFC382 H'FFFFC384 H'FFFFC385 H'FFFFC386 H'FFFFC388 H'FFFFC38A H'FFFFC390 H'FFFFC400 H'FFFFC401 H'FFFFC402 H'FFFFC404 H'FFFFC405 H'FFFFC406 H'FFFFC408 H'FFFFC40A H'FFFFC480 H'FFFFC482 H'FFFFC484 H'FFFFC486 H'FFFFC490 H'FFFFC492 8, 16 8 8 8, 16, 32 8 16 16, 32 16 8 8, 16 8 8 8, 16, 32 8 16 16, 32 16 16, 32 16 8 8 16, 32 16 Abbreviation TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0 Bits 16 16 16 16 8 8 8 Address H'FFFFC30C H'FFFFC30E H'FFFFC320 H'FFFFC322 H'FFFFC324 H'FFFFC325 H'FFFFC326 Module MTU2 Access Size 16, 32 16 16, 32 16 8, 16 8 8 Number of Access States MPφ reference B: 2, W: 2, L: 4 Rev. 4.00 Jul. 25, 2008 Page 679 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Timer control register V_5 Timer I/O control register V_5 Timer counter W_5 Timer general register W_5 Timer control register W_5 Timer I/O control register W_5 Timer status register_5 Timer interrupt enable register_5 Timer start register_5 Timer compare match clear register A/D data register 0 A/D data register 1 A/D data register 2 A/D data register 3 A/D control/status register_0 A/D control register_0 A/D data register 4 A/D data register 5 A/D data register 6 A/D data register 7 A/D control/status register_1 A/D control register_1 Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash transfer destination address register Abbreviation TCRV_5 TIORV_5 TCNTW_5 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 TCNTCMPCLR Number of Access Address H'FFFFC494 H'FFFFC496 H'FFFFC4A0 H'FFFFC4A2 H'FFFFC4A4 H'FFFFC4A6 H'FFFFC4B0 H'FFFFC4B2 H'FFFFC4B4 H'FFFFC4B6 H'FFFFC900 H'FFFFC902 H'FFFFC904 H'FFFFC906 H'FFFFC910 H'FFFFC912 H'FFFFC980 H'FFFFC982 H'FFFFC984 H'FFFFC986 H'FFFFC990 H'FFFFC992 H'FFFFCC00 H'FFFFCC01 H'FFFFCC02 H'FFFFCC04 H'FFFFCC06 FLASH A/D (Channel 1) A/D (Channel 0) Module MTU2 Access Size 8 8 16, 32 16 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 Pφ reference B: 5 Pφ reference B: 2, W: 2 Pφ reference B: 2, W: 2 States MPφ reference B: 2, W: 2, L: 4 Bits 8 8 16 16 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 ADDR0 ADDR1 ADDR2 ADDR3 ADCSR_0 ADCR_0 ADDR4 ADDR5 ADDR6 ADDR7 ADCSR_1 ADCR_1 FCCS FPCS FECS FKEY FTDAR Rev. 4.00 Jul. 25, 2008 Page 680 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Compare match timer start register Compare match timer control/status register_0 Compare match counter_0 Compare match constant register_0 Compare match timer control/status register_1 Compare match counter_1 Compare match constant register_1 Input level control/status register 1 Output level control/status register 1 Input level control/status register 3 Software port output enable register Port output enable control register 1 Port output enable control register 2 Port A data register L Port A I/O register L Port A control register L4 Port A control register L3 Port A control register L2 Port A control register L1 Port A port register L Port B data register H Port B data register L Port B I/O register H Port B I/O register L Port B control register H1 Port B control register L2 Port B control register L1 Port B port register H Port B port register L Port E data register L CMCNT_1 CMCOR_1 ICSR1 OCSR1 ICSR3 SPOER POECR1 POECR2 PADRL PAIORL PACRL4 PACRL3 PACRL2 PACRL1 PAPRL PBDRH PBDRL PBIORH PBIORL PBCRH1 PBCRL2 PBCRL1 PBPRH PBPRL PEDRL 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 H'FFFFCE0A H'FFFFCE0C H'FFFFD000 H'FFFFD002 H'FFFFD008 H'FFFFD00A H'FFFFD00B H'FFFFD00C H'FFFFD102 H'FFFFD106 H’FFFFD110 H’FFFFD112 H’FFFFD114 H’FFFFD116 H'FFFFD11E H’FFFFD180 H’FFFFD182 H'FFFFD184 H'FFFFD186 H'FFFFD18E H'FFFFD194 H'FFFFD196 H'FFFFD19C H'FFFFD19E H'FFFFD302 I/O PFC I/O I/O PFC POE 8, 16 8, 16, 32 8, 16, 32 8, 16 8, 16 8 8 8, 16 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 CMCNT_0 CMCOR_0 CMCSR_1 16 16 16 H'FFFFCE04 H'FFFFCE06 H'FFFFCE08 8, 16, 32 8, 16 8, 16, 32 Abbreviation CMSTR CMCSR_0 Bits 16 16 Address H'FFFFCE00 H'FFFFCE02 Module CMT Access Size 8, 16, 32 8, 16 Number of Access States Pφ reference B: 2, W: 2, L: 4 Pφ reference B: 2, W: 2, L: 4 Pφ reference B: 2, W: 2, L: 4 Rev. 4.00 Jul. 25, 2008 Page 681 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Port E I/O register L Port E control register L4 Port E control register L3 Port E control register L2 Port E control register L1 Port E port register L IRQOUT function control register Port F data register L Frequency control register Abbreviation PEIORL PECRL4 PECRL3 PECRL2 PECRL1 PEPRL IFCR PFDRL FRQCR Bits 16 16 16 16 16 16 16 16 16 Address H'FFFFD306 H'FFFFD310 H'FFFFD312 H'FFFFD314 H'FFFFD316 H'FFFFD31E H'FFFFD322 H'FFFFD382 H'FFFFE800 I/O PFC I/O CPG Module PFC Access Size 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 8, 16 8, 16 16 Number of Access States Pφ reference B: 2, W: 2, L: 4 Pφ reference W: 2 Standby control register 1 Standby control register 2 Standby control register 3 Standby control register 4 Standby control register 5 Standby control register 6 Watchdog timer counter STBCR1 STBCR2 STBCR3 STBCR4 STBCR5 STBCR6 WTCNT 8 8 8 8 8 8 8 8 H'FFFFE802 H'FFFFE804 H'FFFFE806 H'FFFFE808 H'FFFFE80A H'FFFFE80C H'FFFFE810 H'FFFFE812 Power-down modes 8 8 8 8 8 8 Pφ reference B: 2 WDT *1: Read *2: Write 8*1, 16*2 8* , 16* 1 2 Pφ reference B: 2*1, W: 2*2 Watchdog timer control/status register WTCSR Oscillation stop detection control register RAM control register OSCCR 8 H'FFFFE814 CPG 8 Pφ reference B: 2 RAMCR 8 H'FFFFE880 Power-down modes 8 Pφ reference B: 2 A/D trigger select register_0 ADTSR_0 16 H'FFFFE890 A/D 8, 16 Pφ reference B: 2, W: 2 Interrupt control register 0 IRQ control register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C ICR0 IRQCR IRQSR IPRA IPRB IPRC 16 16 16 16 16 16 H'FFFFE900 H'FFFFE902 H'FFFFE904 H'FFFFE906 H'FFFFE908 H'FFFFE980 INTC 8, 16 8, 16 8, 16 8, 16 8, 16 16 Pφ reference B: 2, W: 2 Rev. 4.00 Jul. 25, 2008 Page 682 of 750 REJ09B0243-0400 Section 20 List of Registers Number of Register Name Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt priority register M Break address register A Break address mask register A Break bus cycle register A Break data register A Break data mask register A Break address register B Break address mask register B Break bus cycle register B Break data register B Break data mask register B Break control register Branch source register Branch destination register Execution times break register Abbreviation IPRD IPRE IPRF IPRH IPRI IPRJ IPRK IPRL IPRM BARA BAMRA BBRA BDRA BDMRA BARB BAMRB BBRB BDRB BDMRB BRCR BRSR BRDR BETR Bits 16 16 16 16 16 16 16 16 16 32 32 16 32 32 32 32 16 32 32 32 32 32 16 Address H'FFFFE982 H'FFFFE984 H'FFFFE986 H'FFFFE98A H'FFFFE98C H'FFFFE98E H'FFFFE990 H'FFFFE992 H'FFFFE994 H'FFFFF300 H'FFFFF304 H'FFFFF308 H'FFFFF310 H'FFFFF314 H'FFFFF320 H'FFFFF324 H'FFFFF328 H'FFFFF330 H'FFFFF334 H'FFFFF3C0 H'FFFFF3D0 H'FFFFF3D4 H'FFFFF3DC UBC Module INTC Access Size 16 16 16 16 16 16 16 16 16 32 32 16 32 32 32 32 16 32 32 32 32 32 16 Number of Access States Pφ reference B: 2, W: 2 Bφ reference B: 2, W: 2, L: 2 Rev. 4.00 Jul. 25, 2008 Page 683 of 750 REJ09B0243-0400 Section 20 List of Registers 20.2 Register Bit List Addresses and bit names of each on-chip peripheral module are shown below. As for 16-bit or 32-bit registers, they are shown in two or four rows. Register Abbreviation SCSMR_0 SCBRR_0 SCSCR_0 SCTDR_0 SCSSR_0 SCRDR_0 SCSDCR_0 SCSPTR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCTDR_1 SCSSR_1 SCRDR_1 SCSDCR_1 SCSPTR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCTDR_2 SCSSR_2 SCRDR_2 SCSDCR_2 SCSPTR_2  EIO       DIR SPB1IO  SPB1DT  SPB0IO  SPB0DT TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE[1:0]  EIO C/A   CHR   PE   O/E DIR SPB1IO STOP  SPB1DT MP  SPB0IO  SPB0DT SCI (Channel 2) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE[1:0]  EIO C/A   CHR   PE   O/E DIR SPB1IO STOP  SPB1DT MP  SPB0IO  SPB0DT SCI (Channel 1) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE[1:0] Bit 31/23/15/7 C/A Bit 30/22/14/6 CHR Bit 29/21/13/5 PE Bit 28/20/12/4 O/E Bit 27/19/11/3 STOP Bit 26/18/10/2 MP Bit 25/17/9/1 Bit 24/16/8/0 Module SCI (Channel 0) CKS[1:0] CKS[1:0] CKS[1:0] Rev. 4.00 Jul. 25, 2008 Page 684 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 Bit 31/23/15/7 Bit 30/22/14/6 CCLR[2:0] CCLR[2:0]     Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 TPSC[2:0] TPSC[2:0] MD[3:0] MD[3:0] IOA[3:0] IOC[3:0] IOA[3:0] IOC[3:0] Bit 24/16/8/0 Module MTU2 CKEG[1:0] CKEG[1:0] BFB BFB BFA BFA IOB[3:0] IOD[3:0] IOB[3:0] IOD[3:0] TTGE TTGE    BF[1:0]  TTGE2  BDC PSYE   OE4D N  OLS3N TCIEV TCIEV OE4C P  OLS3P TGIED TGIED OE3D FB TOCL OLS2N TGIEC TGIEC OE4B WF TOCS OLS2P TGIEB TGIEB OE4A VF OLSN OLS1N TGIEA TGIEA OE3B UF OLSP OLS1P TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 Rev. 4.00 Jul. 25, 2008 Page 685 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TCNTS Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Module MTU2 TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TITCR TITCNT TBTER TDER TOLBR TBTM_3 TBTM_4 TADCR TCFD TCFD T3AEN       BF[1:0] UT4AE     3ACOR[2:0] 3ACNT[2:0] TCFV TCFV TGFD TGFD T4VEN  TGFC TGFC TGFB TGFB 4VCOR[2:0] 4VCNT[2:0] TGFA TGFA        OLS3N    UT4BE   OLS3P    DT4BE   OLS2N    ITA3AE   OLS2P    ITA4VE  BTE[1:0] TDER OLS1P TTSA TTSA  ITB4VE OLS1N TTSB TTSB  ITB3AE DT4AE TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 Rev. 4.00 Jul. 25, 2008 Page 686 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TWCR TSTR TSYR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 Bit 31/23/15/7 CCE CST4 SYNC4  Bit 30/22/14/6  CST3 SYNC3  CCLR[2:0]  BFE Bit 29/21/13/5     Bit 28/20/12/4     Bit 27/19/11/3     CKEG[1:0] Bit 26/18/10/2  CST2 SYNC2  Bit 25/17/9/1  CST1 SYNC1  TPSC[2:0] MD[3:0] IOA[3:0] IOC[3:0] Bit 24/16/8/0 WRE CST0 SYNC0 RWE Module MTU2 BFB IOB[3:0] IOD[3:0] BFA TTGE      TCIEV TCFV TGIED TGFD TGIEC TGFC TGIEB TGFB TGIEA TGFA TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0 TCR_1 TMDR_1 TIOR_1 TTGE2        CCLR[1:0]  IOB[3:0]       CKEG[1:0]      TTSE TGIEF TGFF TTSB TPSC[2:0] MD[3:0] IOA[3:0] TGIEE TGFE TTSA   Rev. 4.00 Jul. 25, 2008 Page 687 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TIER_1 TSR_1 TCNT_1 Bit 31/23/15/7 TTGE TCFD Bit 30/22/14/6   Bit 29/21/13/5 TCIEU TCFU Bit 28/20/12/4 TCIEV TCFV Bit 27/19/11/3   Bit 26/18/10/2   Bit 25/17/9/1 TGIEB TGFB Bit 24/16/8/0 TGIEA TGFA Module MTU2 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2     CCLR[1:0]  IOB[3:0]   I2BE CKEG[1:0] I2AE I1BE TPSC[2:0] MD[3:0] IOA[3:0] I1AE   TTGE TCFD   TCIEU TCFU TCIEV TCFV     TGIEB TGFB TGIEA TGFA TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5          IOC[4:0] TPSC[1:0] TGRV_5 TCRV_5       TPSC[1:0] Rev. 4.00 Jul. 25, 2008 Page 688 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TIORV_5 TCNTW_5 Bit 31/23/15/7  Bit 30/22/14/6  Bit 29/21/13/5  Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 IOC[4:0] Bit 25/17/9/1 Bit 24/16/8/0 Module MTU2 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR_5 TCNTCMPCLR ADDR0       AD9 AD1       AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE       AD7  AD7  AD7  AD7   ADM[1:0]    IOC[4:0] TPSC[1:0]     AD6  AD6  AD6  AD6       AD5  AD5  AD5  AD5  TRGE ADCS CMFU5 TGIE5U CSTU5 CMFV5 TGIE5V CSTV5 CMFW5 TGIE5W CSTW5 CMPCLR5U CMPCLR5V CMPCLR5W AD4  AD4  AD4  AD4   AD3  AD3  AD3  AD3  CONADF CH[2:0]   AD4  AD4  AD4  AD4    AD3  AD3  AD3  AD3    AD2  AD2  AD2  AD2  A/D (Channel 1) AD2  AD2  AD2  AD2  STC A/D (Channel 0) ADDR1 AD9 AD1 ADDR2 AD9 AD1 ADDR3 AD9 AD1 ADCSR_0 ADF CKSL[1:0] ADCR_0   ADDR4 AD9 AD1 ADDR5 AD9 AD1 ADDR6 AD9 AD1 ADDR7 AD9 AD1   AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADST  AD7  AD7  AD7  AD7    AD6  AD6  AD6  AD6    AD5  AD5  AD5  AD5  Rev. 4.00 Jul. 25, 2008 Page 689 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation ADCSR_1 Bit 31/23/15/7 ADF Bit 30/22/14/6 ADIE Bit 29/21/13/5  Bit 28/20/12/4  ADM[1:0] Bit 27/19/11/3 TRGE ADCS   FLER   K[7:0]      Bit 26/18/10/2  Bit 25/17/9/1 CONADF CH[2:0]           Bit 24/16/8/0 STC Module A/D (Channel 1) CKSL[1:0] ADCR_1   FCCS FPCS FECS FKEY FTDAR CMSTR TDER   CMCSR_0  CMF CMCNT_0    CMIE     FWE        ADST       SCO PPVS EPVB FLASH TDA[6:0]              STR1  CKS[1:0]  STR0  CMT CMCOR_0 CMCSR_1  CMF  CMIE          CKS[1:0]  CMCNT_1 CMCOR_1 ICSR1 POE3F  POE1F       POE0F    POE8F      PIE1 POE0M[1:0] POE POE3M[1:0] OCSR1 OSF1  ICSR3   SPOER       POE1M[1:0]           OCE1  POE8E OIE1  PIE3 POE8M[1:0] MTU2CH0HIZ MTU2CH34HIZ Rev. 4.00 Jul. 25, 2008 Page 690 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation POECR1 POECR2 Bit 31/23/15/7    Bit 30/22/14/6  MTU2P1CZE Bit 29/21/13/5  MTU2P2CZE Bit 28/20/12/4  MTU2P3CZE Bit 27/19/11/3 MTU2PE3ZE Bit 26/18/10/2 MTU2PE2ZE Bit 25/17/9/1 MTU2PE1ZE Bit 24/16/8/0 Module MTU2PE0ZE POE   PA8DR PA0DR PA8DR PA0DR PA8IOR PA0IOR PA8IOR PA0IOR PA14MD0 PA12MD0   PA10MD0 PA8MD0  PA8MD0 PA6MD0 PA4MD0 PA6MD0 PA4MD0 PA2MD0 PA0MD0  PA0MD0 PA8PR PA0PR PA8PR PA0PR I/O PFC I/O   PA11DR PA3DR  PA3DR PA11IOR PA3IOR  PA3IOR                 PA11PR PA3PR  PA3PR   PA10DR PA2DR   PA10IOR PA2IOR   PA14MD2 PA12MD2   PA10MD2 PA8MD2  PA8MD2 PA6MD2 PA4MD2 PA6MD2 PA4MD2 PA2MD2 PA0MD2  PA0MD2 PA10PR PA2PR     PA9DR PA1DR PA9DR PA1DR PA9IOR PA1IOR PA9IOR PA1IOR PA14MD1 PA12MD1   PA10MD1 PA8MD1  PA8MD1 PA6MD1 PA4MD1 PA6MD1 PA4MD1 PA2MD1 PA0MD1  PA0MD1 PA9PR PA1PR PA9PR PA1PR  PA14DR PA6DR  PA6DR PA14IOR PA6IOR  PA6IOR PA15MD2 PA13MD2   PA11MD2 PA9MD2  PA9MD2 PA7MD2 PA5MD2 PA7MD2  PA3MD2 PA1MD2 PA3MD2 PA1MD2 PA14PR PA6PR  PA6PR  PA13DR PA5DR   PA13IOR PA5IOR   PA15MD1 PA13MD1   PA11MD1 PA9MD1  PA9MD1 PA7MD1 PA5MD1 PA7MD1  PA3MD1 PA1MD1 PA3MD1 PA1MD1 PA13PR PA5PR    PA12DR PA4DR  PA4DR PA12IOR PA4IOR  PA4IOR PA15MD0 PA13MD0   PA11MD0 PA9MD0  PA9MD0 PA7MD0 PA5MD0 PA7MD0  PA3MD0 PA1MD0 PA3MD0 PA1MD0 PA12PR PA4PR  PA4PR PADRL (SH7125) PADRL (SH7124) PAIORL (SH7125) PAIORL (SH7124) PACRL4 (SH7125) PACRL4 (SH7124) PACRL3 (SH7125) PACRL3 (SH7124) PACRL2 (SH7125) PACRL2 (SH7124) PACRL1 (SH7125) PACRL1 (SH7124) PAPRL (SH7125) PAPRL (SH7124) PA15DR PA7DR  PA7DR PA15IOR PA7IOR  PA7IOR                 PA15PR PA7PR  PA7PR Rev. 4.00 Jul. 25, 2008 Page 691 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation PBDRH (SH7125) PBDRH (SH7124) PBDRL (SH7125) PBDRL (SH7124) PBIORH (SH7125) PBIORH (SH7124) PBIORL (SH7125) PBIORL (SH7124) PBCRH1 (SH7125) PBCRH1 (SH7124) PBCRL2 (SH7125) PBCRL2 (SH7124) PBCRL1 (SH7125) PBCRL1 (SH7124) Bit 31/23/15/7                             Bit 30/22/14/6                      PB5MD2  PB5MD2 PB3MD2 PB1MD2 PB3MD2 PB1MD2 Bit 29/21/13/5      PB5DR  PB5DR      PB5IOR  PB5IOR      PB5MD1  PB5MD1 PB3MD1 PB1MD1 PB3MD1 PB1MD1 Bit 28/20/12/4                      PB5MD0  PB5MD0 PB3MD0 PB1MD0 PB3MD0 PB1MD0 Bit 27/19/11/3      PB3DR  PB3DR      PB3IOR  PB3IOR             Bit 26/18/10/2      PB2DR        PB2IOR           PB2MD2    Bit 25/17/9/1      PB1DR  PB1DR      PB1IOR  PB1IOR         PB2MD1    Bit 24/16/8/0  PB16DR        PB16IOR        PB16MD       PB2MD0    PFC Module I/O Rev. 4.00 Jul. 25, 2008 Page 692 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation PBPRH (SH7125) PBPRH (SH7124) PBPRL (SH7125) PBPRL (SH7124) PEDRL (SH7125) PEDRL (SH7124) PEIORL (SH7125) PEIORL (SH7124) PECRL4 Bit 31/23/15/7         PE15DR PE7DR PE15DR  PE15IOR PE7IOR PE15IOR    Bit 30/22/14/6         PE14DR PE6DR PE14DR  PE14IOR PE6IOR PE14IOR  PE15MD2  PE11MD2 PE9MD2 PE7MD2 PE5MD2   PE3MD2 PE1MD2 PE14PR PE6PR PE14PR  Bit 29/21/13/5      PB5PR  PB5PR PE13DR PE5DR PE13DR  PE13IOR PE5IOR PE13IOR  PE15MD1 PE13MD1 PE11MD1 PE9MD1 PE7MD1 PE5MD1   PE3MD1 PE1MD1 PE13PR PE5PR PE13PR  Bit 28/20/12/4         PE12DR PE4DR PE12DR  PE12IOR PE4IOR PE12IOR  PE15MD0 PE13MD0 PE11MD0 PE9MD0 PE7MD0 PE5MD0   PE3MD0 PE1MD0 PE12PR PE4PR PE12PR  Bit 27/19/11/3      PB3PR  PB3PR PE11DR PE3DR PE11DR PE3DR PE11IOR PE3IOR PE11IOR PE3IOR           PE11PR PE3PR PE11PR PE3PR Bit 26/18/10/2      PB2PR   PE10DR PE2DR PE10DR PE2DR PE10IOR PE2IOR PE10IOR PE2IOR PE14MD2 PE12MD2 PE10MD2 PE8MD2 PE6MD2 PE4MD2   PE2MD2  PE10PR PE2PR PE10PR PE2PR Bit 25/17/9/1      PB1PR  PB1PR PE9DR PE1DR PE9DR PE1DR PE9IOR PE1IOR PE9IOR PE1IOR PE14MD1 PE12MD1 PE10MD1 PE8MD1 PE6MD1 PE4MD1   PE2MD1 PE0MD1 PE9PR PE1PR PE9PR PE1PR Bit 24/16/8/0  PB16PR       PE8DR PE0DR PE8DR PE0DR PE8IOR PE0IOR PE8IOR PE0IOR PE14MD0 PE12MD0 PE10MD0 PE8MD0 PE6MD0 PE4MD0   PE2MD0 PE0MD0 PE8PR PE0PR PE8PR PE0PR I/O PFC Module I/O PECRL3   PECRL2 (SH7125) PECRL2 (SH7124) PECRL1       PEPRL (SH7125) PEPRL (SH7124) PE15PR PE7PR PE15PR  Rev. 4.00 Jul. 25, 2008 Page 693 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation IFCR Bit 31/23/15/7   Bit 30/22/14/6    PF6DR Bit 29/21/13/5    PF5DR IFC[2:0] Bit 28/20/12/4    PF4DR Bit 27/19/11/3    PF3DR Bit 26/18/10/2    PF2DR BFC[2:0] Bit 25/17/9/1  IRQMD1  PF1DR Bit 24/16/8/0  IRQMD0  PF0DR PFC[2] CPG I/O Module PFC PFDRL  PF7DR FRQCR  PFC[1:0]       MSTP13 MSTP21      MSTP12       MSTP11          MPFC[2:0]    MSTP17    MSTP16 Power-down modes STBCR1 STBCR2 STBCR3 STBCR4 STBCR5 STBCR6 WTCNT WTCSR OSCCR RAMCR STBY MSTP7    UBCRST MSTP22  HIZ MSTP[25:24] STBYMD  WDT TME   WT/IT   RSTS   WOVF  RAME IOVF   OSCSTOP  CKS[2:0]   OSCERS  CPG Power-down modes ADTSR_0 TRG11S[3:0] TRG1S[3:0] TRG01S[3:0] TRG0S[3:0]    IRQ20S   IRQ0 IRQ2        IRQ11S IRQ3L IRQ3F IRQ1 IRQ3        IRQ10S IRQ2L IRQ2F IRQ1 IRQ3        IRQ01S IRQ1L IRQ1F IRQ1 IRQ3     NMIE   IRQ00S IRQ0L IRQ0F IRQ1 IRQ3     A/D ICR0 NMIL     IRQ30S   IRQ0 IRQ2        IRQ21S   IRQ0 IRQ2     INTC IRQCR  IRQ31S IRQSR   IPRA IRQ0 IRQ2 IPRB   IPRC   Rev. 4.00 Jul. 25, 2008 Page 694 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation IPRD Bit 31/23/15/7 MTU2_0 MTU2_1 Bit 30/22/14/6 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 MTU2_5     CMT_0  A/D_0,1  SCI_0 SCI_2   BAA30 BAA22 BAA14 BAA6 BAMA30 BAMA22 BAMA14 BAMA6  CDA[1:0] Bit 29/21/13/5 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 MTU2_5     CMT_0  A/D_0,1  SCI_0 SCI_2   BAA29 BAA21 BAA13 BAA5 BAMA29 BAMA21 BAMA13 BAMA5  Bit 28/20/12/4 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 MTU2_5     CMT_0  A/D_0,1  SCI_0 SCI_2   BAA28 BAA20 BAA12 BAA4 BAMA28 BAMA20 BAMA12 BAMA4  IDA[1:0] Bit 27/19/11/3 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 Bit 26/18/10/2 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 Bit 25/17/9/1 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 Bit 24/16/8/0 MTU2_0 MTU2_1 MTU2_2 MTU2_3 MTU2_4 Module INTC IPRE MTU2_2 MTU2_3 IPRF MTU2_4 MTU2_5 POE(MTU2) POE(MTU2) POE(MTU2) POE(MTU2)     CMT_1 WDT   SCI_1    BAA27 BAA19 BAA11 BAA3 BAMA27 BAMA19 BAMA11 BAMA3  RWA[1:0]     CMT_1 WDT   SCI_1    BAA26 BAA18 BAA10 BAA2 BAMA26 BAMA18 BAMA10 BAMA2     CMT_1 WDT   SCI_1    BAA25 BAA17 BAA9 BAA1 BAMA25 BAMA17 BAMA9 BAMA1 CPA[2:0] SZA[1:0]     CMT_1 WDT   SCI_1    BAA24 BAA16 BAA8 BAA0 BAMA24 BAMA16 BAMA8 BAMA0 UBC IPRH   IPRI   IPRJ CMT_0  IPRK A/D_0,1  IPRL SCI_0 SCI_2 IPRM   BARA BAA31 BAA23 BAA15 BAA7 BAMRA BAMA31 BAMA23 BAMA15 BAMA7 BBRA  Rev. 4.00 Jul. 25, 2008 Page 695 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation BDRA Bit 31/23/15/7 BDA31 BDA23 BDA15 BDA7 Bit 30/22/14/6 BDA30 BDA22 BDA14 BDA6 BDMA30 BDMA22 BDMA14 BDMA6 BAB30 BAB22 BAB14 BAB6 BAMB30 BAMB22 BAMB14 BAMB6  CDB[1:0] Bit 29/21/13/5 BDA29 BDA21 BDA13 BDA5 BDMA29 BDMA21 BDMA13 BDMA5 BAB29 BAB21 BAB13 BAB5 BAMB29 BAMB21 BAMB13 BAMB5  Bit 28/20/12/4 BDA28 BDA20 BDA12 BDA4 BDMA28 BDMA20 BDMA12 BDMA4 BAB28 BAB20 BAB12 BAB4 BAMB28 BAMB20 BAMB12 BAMB4  IDB[1:0] Bit 27/19/11/3 BDA27 BDA19 BDA11 BDA3 BDMA27 BDMA19 BDMA11 BDMA3 BAB27 BAB19 BAB11 BAB3 BAMB27 BAMB19 BAMB11 BAMB3  Bit 26/18/10/2 BDA26 BDA18 BDA10 BDA2 BDMA26 BDMA18 BDMA10 BDMA2 BAB26 BAB18 BAB10 BAB2 BAMB26 BAMB18 BAMB10 BAMB2 Bit 25/17/9/1 BDA25 BDA17 BDA9 BDA1 BDMA25 BDMA17 BDMA9 BDMA1 BAB25 BAB17 BAB9 BAB1 BAMB25 BAMB17 BAMB9 BAMB1 CPB[2:0] Bit 24/16/8/0 BDA24 BDA16 BDA8 BDA0 BDMA24 BDMA16 BDMA8 BDMA0 BAB24 BAB16 BAB8 BAB0 BAMB24 BAMB16 BAMB8 BAMB0 Module UBC BDMRA BDMA31 BDMA23 BDMA15 BDMA7 BARB BAB31 BAB23 BAB15 BAB7 BAMRB BAMB31 BAMB23 BAMB15 BAMB7 BBRB  RWB[1:0] BDB27 BDB19 BDB11 BDB3 BDMB27 BDMB19 BDMB11 BDMB3  UBIDB PCTE SEQ BDB26 BDB18 BDB10 BDB2 BDMB26 BDMB18 BDMB10 BDMB2   PCBA  SZB[1:0] BDB25 BDB17 BDB9 BDB1 BDMB25 BDMB17 BDMB9 BDMB1  UBIDA   BDB24 BDB16 BDB8 BDB0 BDMB24 BDMB16 BDMB8 BDMB0    ETBE BDRB BDB31 BDB23 BDB15 BDB7 BDB30 BDB22 BDB14 BDB6 BDMB30 BDMB22 BDMB14 BDMB6   SCMFCB PCBB BDB29 BDB21 BDB13 BDB5 BDMB29 BDMB21 BDMB13 BDMB5   SCMFDA DBEB BDB28 BDB20 BDB12 BDB4 BDMB28 BDMB20 BDMB12 BDMB4   SCMFDB  BDMRB BDMB31 BDMB23 BDMB15 BDMB7 BRCR   SCMFCA DBEA Rev. 4.00 Jul. 25, 2008 Page 696 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation BRSR Bit 31/23/15/7 SVF BSA23 BSA15 BSA7 Bit 30/22/14/6  BSA22 BSA14 BSA6  BDA22 BDA14 BDA6  Bit 29/21/13/5  BSA21 BSA13 BSA5  BDA21 BDA13 BDA5  Bit 28/20/12/4  BSA20 BSA12 BSA4  BDA20 BDA12 BDA4  Bit 27/19/11/3 BSA27 BSA19 BSA11 BSA3 BDA27 BDA19 BDA11 BDA3 Bit 26/18/10/2 BSA26 BSA18 BSA10 BSA2 BDA26 BDA18 BDA10 BDA2 Bit 25/17/9/1 BSA25 BSA17 BSA9 BSA1 BDA25 BDA17 BDA9 BDA1 Bit 24/16/8/0 BSA24 BSA16 BSA8 BSA0 BDA24 BDA16 BDA8 BDA0 Module UBC BRDR DVF BDA23 BDA15 BDA7 BETR  BET[11:8] BET[7:0] Rev. 4.00 Jul. 25, 2008 Page 697 of 750 REJ09B0243-0400 Section 20 List of Registers 20.3 Register Abbreviation SCSMR_0 SCBRR_0 SCSCR_0 SCTDR_0 SCSSR_0 SCRDR_0 SCSDCR_0 SCSPTR_0 SCSMR_1 SCBRR_1 SCSCR_1 SCTDR_1 SCSSR_1 SCRDR_1 SCSDCR_1 SCSPTR_1 SCSMR_2 SCBRR_2 SCSCR_2 SCTDR_2 SCSSR_2 SCRDR_2 SCSDCR_2 SCSPTR_2 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 Register States in Each Operating Mode Software Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained MTU2 SCI (Channel 2) SCI (Channel 1) Module SCI (Channel 0) Rev. 4.00 Jul. 25, 2008 Page 698 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TGCR TOCR1 TOCR2 TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TITCR TITCNT TBTER TDER TOLBR TBTM_3 Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module MTU2 Rev. 4.00 Jul. 25, 2008 Page 699 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TBTM_4 TADCR TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 TWCR TSTR TSYR TRWER TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 TIER2_0 TSR2_0 TBTM_0 TCR_1 TMDR_1 TIOR_1 TIER_1 Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module MTU2 Rev. 4.00 Jul. 25, 2008 Page 700 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation TSR_1 TCNT_1 TGRA_1 TGRB_1 TICCR TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCNTU_5 TGRU_5 TCRU_5 TIORU_5 TCNTV_5 TGRV_5 TCRV_5 TIORV_5 TCNTW_5 TGRW_5 TCRW_5 TIORW_5 TSR_5 TIER_5 TSTR5 TCNTCMPCLR Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module MTU2 Rev. 4.00 Jul. 25, 2008 Page 701 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation ADDR0 ADDR1 ADDR2 ADDR3 ADCSR_0 ADCR_0 ADDR4 ADDR5 ADDR6 ADDR7 ADCSR_1 ADCR_1 FCCS FPCS FECS FKEY FTDAR CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 ICSR1 OCSR1 ICSR3 SPOER POECR1 POECR2 Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized       Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained POE CMT FLASH A/D (Channel 1) Module A/D (Channel 0) Rev. 4.00 Jul. 25, 2008 Page 702 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation PADRL PAIORL PACRL4 PACRL3 PACRL2 PACRL1 PAPRL PBDRH PBDRL PBIORH PBIORL PBCRH1 PBCRL2 PBCRL1 PBPRH PBPRL PEDRL PEIORL PECRL4 PECRL3 PECRL2 PECRL1 PEPRL IFCR PFDRL FRQCR STBCR1 STBCR2 STBCR3 STBCR4 Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized* Initialized Initialized Initialized Initialized 1 Software Manual reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Module Standby                               Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained I/O PFC I/O CPG Power-down modes PFC I/O PFC I/O Module I/O PFC Rev. 4.00 Jul. 25, 2008 Page 703 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation STBCR5 STBCR6 WTCNT WTCSR OSCCR RAMCR Power-on reset Initialized Initialized Initialized*1 Initialized* Initialized* Initialized 1 Software Manual reset Retained Retained Retained Retained Retained Retained Standby Retained Retained Retained Retained Retained* Retained 3 Module Standby       Sleep Retained Retained Retained Retained Retained Retained CPG Power-down modes Module Power-down modes WDT 2 ADTSR_0 ICR0 IRQCR IRQSR IPRA IPRB IPRC IPRD IPRE IPRF IPRH IPRI IPRJ IPRK IPRL IPRM BARA BAMRA BBRA BDRA BDMRA BARB BAMRB BBRB Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained                Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained A/D INTC UBC Rev. 4.00 Jul. 25, 2008 Page 704 of 750 REJ09B0243-0400 Section 20 List of Registers Register Abbreviation BDRB BDMRB BRCR BRSR BRDR BETR Power-on reset Initialized Initialized Initialized Initialized Initialized Initialized Manual reset Retained Retained Retained Retained Retained Retained Software Standby Retained Retained Retained Retained Retained Retained Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Sleep Retained Retained Retained Retained Retained Retained Module UBC Notes: 1. Not initialized by a WDT power-on reset. 2. The OSCSTOP bit is not initialized by a WDT power-on reset. 3. The OSCSTOP bit is initialized. Rev. 4.00 Jul. 25, 2008 Page 705 of 750 REJ09B0243-0400 Section 20 List of Registers Rev. 4.00 Jul. 25, 2008 Page 706 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics Section 21 Electrical Characteristics All values for electrical characteristics are preliminary, and are subject to change without notice as a result of characteristics evaluation. 21.1 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except analog input) Analog power supply voltage Analog input voltage Operating temperature Consumer specifications Industrial specifications Storage temperature Tstg Symbol VCC Vin AVCC Van Topr Value −0.3 to + 7.0 −0.3 to VCC + 0.3 −0.3 to + 7.0 −0.3 to AVCC + 0.3 −20 to + 85 −40 to + 85 −55 to + 125 Unit V V V V °C °C °C [Operating Precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. Rev. 4.00 Jul. 25, 2008 Page 707 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.2 DC Characteristics Tables 21.2 and 21.3 list DC characteristics. Table 21.2 DC Characteristics Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Input high-level voltage (other than Schmitt trigger input voltage) Input low-level voltage (other than Schmitt trigger input voltage) Schmitt trigger input voltage Symbol VIH RES, MRES, NMI, FWE, MD1, ASEMD0, EXTAL Analog ports Other input pins RES, MRES, NMI, VIL FWE, MD1, ASEMD0, EXTAL Other input pins IRQ3 to IRQ0, POE8, POE3, POE1, POE0, TCLKA to TCLKD, TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D, TIC5U, TIC5V, TIC5WS, SCK0 to SCK3, RXD0 to RXD3 All input pins (except ASEMD0) ASEMD0, POE3 VT+ VT– VT+–VT– Min. VCC − 0.7 Typ. — Max. VCC + 0.3 Unit V Test Conditions 2.2 2.2 −0.3 — — — AVCC + 0.3 VCC + 0.3 0.5 V V V −0.3 VCC − 0.5 — 0.4 — — — — 0.8 — 1.0 — V V V V VCC = 4.5 V to 5.5 V Input leak current Input pull-up MOS current | Iin | –Ipu | Itsi | — —  — —  1.0 800 1.0 µA µA µA Vin = 0 V Tri-state Ports A, B, E leakage current (OFF state) Rev. 4.00 Jul. 25, 2008 Page 708 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics Test Conditions IOH = –5 mA, VCC = 4.5 V to 5.5 V IOH = –100 µA IOH = –200 µA IOH = –1 mA IOH = –2 mA (reference values) IOL = 15 mA, VCC = 4.5 V to 5.5 V IOL = 10 mA, VCC = 4.5 V to 5.5 V IOL = 8 mA, VCC = 4.5 V to 5.5 V IOL = 1.6 mA Vin = 0 V f = 1 MHz Ta = 25°C Supply current Normal operation Sleep Software standby ICC     Analog power supply current During A/D conversion Waiting for A/D conversion Standby AICC    52 33   3   70 50 5 15 5 2 15 mA mA mA mA mA mA µA Iφ = 50 MHz Iφ = 50 MHz Ta ≤ 50°C 50°C < Ta The value per module The value per module Item Output high voltage TIOC3B, TIOC3D, TIOC4A to TIOC4D WDTOVF All other output pins Symbol VOH Min. VCC − 0.8 Typ.  Max.  Unit V VCC − 0.5 VCC − 0.5 VCC − 1.0 VCC − 1.5         V V V V Output low voltage TIOC3B, TIOC3D, TIOC4A to TIOC4D VOL   1.0 V   0.6 V   0.44 V All other output pins Input capacitance All input pins Cin     0.4 20 V pF [Operating Precautions] 1. When the A/D converter is not used, do not leave the AVCC and AVSS pins open. 2. The supply current was measured when VIH (Min.) = VCC - 0.5 V, VIL (Max.) = 0.5 V, with all output pins unloaded. Rev. 4.00 Jul. 25, 2008 Page 709 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics Table 21.3 Permitted Output Current Values Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Symbol Σ IOL –IOH Σ –IOH Min.     Typ.     Max. 2.0* 80 2.0* 25 Unit mA mA mA mA Permissible current in low-level output (per pin) IOL Permissible current in low-level output (total) Permissible current in high-level output (per pin) Permissible current in high-level output (total) [Operating Precautions] To assure LSI reliability, do not exceed the output values listed in table 21.3. Note: * IOL = 15 mA (Max.)/–IOH = 5 mA (Max.) for pins PE9 and PE11 to PE15. However, at least three pins are permitted to have simultaneously IOL/–IOH > 2.0 mA among these pins. Rev. 4.00 Jul. 25, 2008 Page 710 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 21.4 Maximum Operating Frequency Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Operating frequency CPU (Iφ) Peripheral module (Pφ) Symbol Min. f 10 10 Typ. — — Max. 50 40 Unit MHz Remarks Rev. 4.00 Jul. 25, 2008 Page 711 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.1 Clock Timing Table 21.5 Clock Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rising time EXTAL clock input falling time CK (Bφ) clock frequency (reference values) CK (Bφ) clock cycle time (reference values) Power-on oscillation stabilization time Oscillation stabilization time on return from standby 1 Oscillation stabilization time on return from standby 2 Note: * Symbol fEX tEXcyc tEXL tEXH tEXr tEXf fOP tcyc tOSC1 tOSC2 tOSC3 Min. 10 80 20 20   10 25 10 10 10 Max. 12.5 100   5 5 40 100    Unit MHz ns ns ns ns ns MHz ns ms ms ms Figure 21.2 Figure 21.3 Figure 21.4 * Reference Figure Figure 21.1 Depends on the frequency control register (FRQCR). tEXcyc EXTAL (input) 1/2 VCC tEXH tEXL VIH 1/2 VCC tEXr VIH VIH VIL tEXf VIL Figure 21.1 Timing of EXTAL Input Clock Signal Rev. 4.00 Jul. 25, 2008 Page 712 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics Oscillation stabilized CK, internal clock VCC VCC (Min.) tOSC1 RES tRESW tRESS Note: Oscillation stabilization time when the on-chip oscillator is in use. Figure 21.2 Power-On Oscillation Stabilization Time Standby period CK, internal clock tRESW, tMRESW tOSC2 RES, MRES Note: Oscillation stabilization time when the on-chip oscillator is in use. Oscillation stabilized Figure 21.3 Oscillation Stabilization Time on Return from Standby (Return by Reset) Standby period CK, internal clock tOSC3 Oscillation stabilized NMI, IRQ Note: Oscillation stabilization time when the on-chip oscillator is in use. Figure 21.4 Oscillation Stabilization Time on Return from Standby (Return by NMI or IRQ) Rev. 4.00 Jul. 25, 2008 Page 713 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.2 Control Signal Timing Table 21.6 Control Signal Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item RES pulse width RES setup time* (reference values) 1 Symbol tRESW tRESS tRESH tMRESW 1 Min. 2 0* 65 15 20* 25 15 20 60 10 35 35 — 3 2 Max. — — — — — — — — — — — 100 Unit tBcyc* ns ns tBcyc* ns ns tBcyc* ns ns ns ns ns 4 4 4 Reference Figure Figures 21.2, 21.3, 21.5, 21.6 RES hold time (reference values) MRES pulse width MRES setup time* (reference values) MRES hold time (reference values) MD1, FWE setup time NMI setup time* (reference values) NMI hold time (reference values) IRQ3 to IRQ0 setup time* (reference values) IRQ3 to IRQ0 hold time (reference values) IRQOUT output delay time (reference values) 1 1 tMRESS tMRESH tMDS tNMIS tNMIH tIRQS tIRQH tIRQOD Figure 21.5 Figure 21.6 Figure 21.7 Notes: 1. The RES, MRES, NMI, and IRQ3 to IRQ0 signals are asynchronous signals. When the setup time is satisfied, change of signal level is detected at the rising edge of the clock. If not, the detection is delayed until the rising edge of the clock. 2. In standby mode, tRESW = tOSC2 (10 ms). 3. In standby mode, tMRESW = tOSC2 (10 ms). 4. tBcyc indicates the bus clock cycle time (Bφ = CK). Rev. 4.00 Jul. 25, 2008 Page 714 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics CK tRESS RES tRESW tRESS tMDS MD1, FWE tMRESS tMRESS MRES tMRESW Figure 21.5 Reset Input Timing CK tRESH RES tMRESH MRES tNMIH NMI tIRQH IRQ3 to IRQ0 VIL tRESS VIH VIL tMRESS VIH VIL tNMIS VIH VIL tIRQS VIH Figure 21.6 Interrupt Signal Input Timing Rev. 4.00 Jul. 25, 2008 Page 715 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics CK tIRQOD IRQOUT tIRQOD Figure 21.7 Interrupt Signal Output Timing Rev. 4.00 Jul. 25, 2008 Page 716 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) Timing Table 21.7 Multi Function Timer Pulse Unit 2 (MTU2) Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Output compare output delay time (reference values) Input capture input setup time (reference values) Input capture input pulse width (single edge) Input capture input pulse width (both edges) Timer input setup time (reference values) Symbol tTOCD tTICS tTICWH/L tTICWH/L tTCKS Min.  20 1.5 2.5 20 1.5 2.5 2.5 Max. 50        Unit ns ns tMPcyc tMPcyc ns tMPcyc tMPcyc tMPcyc Figure 21.9 Reference Figure Figure 21.8 Timer clock pulse width (single edge) tTCKWH/L Timer clock pulse width (both edges) Timer clock pulse width (phase counting mode) tTCKWH/L tTCKWH/L Note: tMPcyc indicates the MTU2 clock (MPφ) cycle. CK tTOCD Output compare output tTICS Input capture input tTICWH/L Figure 21.8 MTU2 Input/Output Timing Rev. 4.00 Jul. 25, 2008 Page 717 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics CK tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 21.9 MTU2 Clock Input Timing Rev. 4.00 Jul. 25, 2008 Page 718 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.4 I/O Port Timing Table 21.8 I/O Port Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Port output data delay time (reference values) Port input low pulse width Port input high pulse width Symbol tPWD tPRWL tPRWH Min.  2 2 Max. 50   Unit ns tPcyc tPcyc Reference Figure Figure 21.10 CK tPRWH/L Port (read) tPWD Port (write) Figure 21.10 I/O Port Input/Output Timing Rev. 4.00 Jul. 25, 2008 Page 719 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.5 Watchdog Timer (WDT) Timing Table 21.9 Watchdog Timer (WDT) Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item WDTOVF delay time (reference values) Symbol tWOVD Min. — Max. 50 Unit ns Reference Figure Figure 21.11 CK tWOVD tWOVD WDTOVF Figure 21.11 WDT Timing Rev. 4.00 Jul. 25, 2008 Page 720 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.6 Serial Communication Interface (SCI) Timing Table 21.10 Serial Communication Interface (SCI) Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Input clock cycle (asynchronous) Input clock cycle (clock synchronous) Input clock pulse width Input clock rising time Input clock falling time Transmit data delay time Receive data setup time Receive data hold time Transmit data delay time Receive data setup time Receive data hold time Clock synchronous Asynchronous Symbol tscyc tscyc tsckw tsckr tsckf tTXD tRXS tRXH tTXD tRXS tRXH Min. 4 6 0.4    4 tpcyc 4 tpcyc  Max.   0.6 1.5 1.5 4 tpcyc + 10   3 tpcyc + 10 Unit tpcyc tpcyc tscyc tpcyc tpcyc ns ns ns ns ns ns Figure 21.13 Reference Figure Figure 21.12 2 tpcyc + 50  2 tpcyc  Note: tpcyc indicates the peripheral clock (Pφ) cycle. tsckw VIH SCK0 to SCK2 VIH VIL VIL tsckr tsckf VIH VIH VIL tscyc Figure 21.12 Input Clock Timing Rev. 4.00 Jul. 25, 2008 Page 721 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics tscyc SCK0 to SCK2 (input/output) tTXD TXD0 to TXD2 (transmit data) tRXS RXD0 to RXD2 (receive data) SCI input/output timing (clock synchronous mode) tRXH T1 CK tTXD TXD0 to TXD2 (transmit data) tRXS RXD0 to RXD2 (receive data) SCI input/output timing (asynchronous mode) tRXH Tn Figure 21.13 SCI Input/Output Timing Rev. 4.00 Jul. 25, 2008 Page 722 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.7 Port Output Enable (POE) Timing Table 21.11 Port Output Enable (POE) Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item POE input setup time (reference values) POE input pulse width Symbol tPOES tPOEW Min. 50 1.5 Max.   Unit ns tpcyc Reference Figure Figure 21.14 Note: tpcyc indicates the peripheral clock (Pφ) cycle. CK tPOES POEn input tPOEW Figure 21.14 POE Input Timing Rev. 4.00 Jul. 25, 2008 Page 723 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.8 A/D Converter Timing Table 21.12 A/D Converter Timing Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item External trigger input start delay time (reference values) Symbol tTRGS Min. 25 Typ. — Max. — Unit ns Reference Figure Figure 21.15 CK ADTRG input tTRGS Figure 21.15 External Trigger Input Timing Rev. 4.00 Jul. 25, 2008 Page 724 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.3.9 Conditions for Testing AC Characteristics • Input signal level: VIL (Max.)/VIH (Min.) • Output signal reference level: 2.0 V (high level), 0.8 V (low level) IOL LSI output pin DUT output CL VREF IOH Notes: 1. CL is the total value that includes the capacitance of the measurement instrument and is set as follows for the respective pins. 30pF: All other output pins 2. IOL = 1.6 mA and IOH = -200 mA in the test conditions. Figure 21.16 Output Load Circuit Rev. 4.00 Jul. 25, 2008 Page 725 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.4 A/D Converter Characteristics Table 21.13 A/D Converter Characteristics Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Non-linear error Offset error Full-scale error Quantization error Absolute error Min. 10 — — — — — — — — Typ. 10 — — — — — — — — Max. 10 2.0 20 1* /3* 2 1 Unit bit µs pF kΩ 2 1 ±3.0* /±5.0* ±3.0* /±5.0* 1 LSB LSB LSB LSB 2 ±3.0* /±5.0* 1 2 ±0.5 ±4.0* /±6.0* 1 2 LSB Notes: 1. It is assumed that A/D conversion time ≥ 4.0 µs. 2. It is assumed that A/D conversion time < 4.0 µs. Rev. 4.00 Jul. 25, 2008 Page 726 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.5 Flash Memory Characteristics Table 21.14 Flash Memory Characteristics Conditions: VCC = AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = –20 to +85°C (consumer specifications), Ta = –40 to +85°C (industrial specifications) Item Programming time* * * Erase time*1*2*4 1 2 4 Symbol tP tE Min. — — — — Typ. 1 40 300 600 1.2 0.6 1.3 0.7 2.5 1.3 3 Max. 10 130 800 1500 3 1.5 3.5 2 6.5 3.5 — Unit ms/128 bytes ms/4 Kbytes block ms/32 Kbytes block ms/64 Kbytes block s/128 Kbytes s/64 Kbytes s/128 Kbytes s/64 Kbytes s/128 Kbytes s/64 Kbytes Times Programming time (total) *1*2*4 Erase time (total) * * * 1 2 4 Σ tP Σ tE — — — — Programming and erase time Σ tPE (total) *1*2*4 Reprogramming count NWEC — — 100* — Notes: 1. Programming/erasure time is data-dependent. 2. Programming/erasure time does not include data transfer time. 3. Minimum number to guarantee all the characteristics after reprogramming. (Guaranteed within the range from 1 to min. value) 4. Characteristics when reprogramming is performed within the specified number of times including min. value. Rev. 4.00 Jul. 25, 2008 Page 727 of 750 REJ09B0243-0400 Section 21 Electrical Characteristics 21.6 21.6.1 Usage Note Notes on Connecting VCL Capacitor This LSI includes an internal step-down circuit to automatically reduce the internal power supply voltage to an appropriate level. Between this internal stepped-down power supply (VCL pin) and the VSS pin, a capacitor (ranging from 0.1 to 0.47 µF) for stabilizing the internal voltage needs to be connected. Connection of the external capacitor is shown in figure 21.17. The external capacitor should be located near the pin. Do not apply any power supply voltage to the VCL pin. External power-supply stabilizing capacitor One capacitor ranging from 0.1 to 0.47 µF VCL VSS VSS VCL One capacitor ranging from 0.1 to 0.47 µF Note: Do not apply any power supply voltage to the VCL pin. Use multilayer ceramic capacitors (one capacitor ranging from 0.1 to 0.47 µF for each VCL pin), which should be located near the pin. Figure 21.17 Connection of VCL Capacitor Rev. 4.00 Jul. 25, 2008 Page 728 of 750 REJ09B0243-0400 Appendix Appendix A. Pin States Pin initial states differ according to MCU operating modes. See section 15, Pin Function Controller (PFC), for details. Table A.1 Pin States (SH7125) Pin State Reset State Power-Down State Software Type Clock Pin Name XTAL EXTAL System control RES MRES WDTOVF Operating mode MD1 control ASEMD0 FWE Interrupt NMI IRQ0 to IRQ3 IRQOUT MTU2 TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3C TIOC3B, TIOC3D MTU2 TIOC4A to TIOC4D Power-On Manual O I I Z O* I I* I I Z Z Z Z Z Z Z Z Z 3 2 Pin Function Oscillation Sleep O I I I O I POE Function Standby L I I Z O I Stop Detected Used O I I Z O I O I I I O I 3 O I I I O I I* I I I O I I/O I/O I/O I/O I/O I/O I I 3 I* I I I Z Z 3 I* I I I O I 1 3 I* I I I Z I I*3 I I I O I Z I/O I/O I/O Z Z I I K* K* K* K* Z Z Z Z I/O I/O I/O I/O I/O I/O I I I* 3 I/O I/O I/O I/O Z Z I I I* 3 1 1 1 TIC5U, TIC5V, TIC5W Z POE POE0, POE1, POE8 POE3 Z I* 3 I* 3 Z I*3 Rev. 4.00 Jul. 25, 2008 Page 729 of 750 REJ09B0243-0400 Appendix Pin Function Reset State Pin State Power-Down State Software Oscillation Sleep I/O I 1 POE Function Type SCI Pin Name SCK0 to SCK2 RXD0 to RXD2 TXD0 to TXD2 Power-On Manual Z Z Z Z Z Z Z I/O I O I I I/O I/O Standby Z Z O* Z Z K*1 K*1 Stop Detected Used I/O I O I I I/O I/O I/O I O I I I/O I/O O I I I/O I/O A/D Converter AN0 to AN7 ADTRG I/O Ports PA0 to PA15 PB1 to PB3, PB5, PB16 PE0 to PE3 PE4 to PE8, PE10 PE9, PE11 to PE15 PF0 to PF7 Z Z Z Z I/O I/O I/O I K*1 K* Z Z 1 I/O I/O I/O I I/O I/O Z I Z I/O Z I [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6 (STBCR6) is set to 1. 2. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pulldown with a resistance of at least 1 MΩ as required. 3. Pulled-up inside the LSI when there is no input. Rev. 4.00 Jul. 25, 2008 Page 730 of 750 REJ09B0243-0400 Appendix Table A.2 Pin States (SH7124) Pin State Reset State Power-Down State Software Oscillation Sleep O I I I O I 3 Pin Function POE Function Type Clock Pin Name XTAL EXTAL Power-On Manual O I I Z O* I I* I I Z Z Z Z Z Z Z 3 2 Standby L I I Z O I Stop Detected Used O I I Z O I O I I I O I 3 O I I I O I I* I I I O I I/O I/O I/O I/O I I I/O I O I 3 System control RES MRES WDTOVF Operating mode MD1 control ASEMD0 FWE Interrupt NMI IRQ1 to IRQ3 IRQOUT MTU2 TCLKA to TCLKD TIOC0A to TIOC0D TIOC3A, TIOC3C TIOC3B, TIOC3D TIOC4A to TIOC4D I* I I I Z Z I* I I I O I 1 3 I* I I I Z I I*3 I I I O I Z I/O Z Z I I I/O I O I K* K* Z Z Z Z Z Z I/O I/O I/O I/O I I I/O I I/O I/O Z Z I I I/O I O I 1 TIC5U, TIC5V, TIC5W Z POE SCI POE0, POE1, POE8 SCK0, SCK2 RXD0 to RXD2 TXD0 to TXD2 A/D Converter AN0 to AN7 Z Z Z Z Z O* Z 1 O I Rev. 4.00 Jul. 25, 2008 Page 731 of 750 REJ09B0243-0400 Appendix Pin Function Reset State Pin State Power-Down State Software Oscillation Sleep I/O POE Function Type I/O Ports Pin Name PA0, PA1, PA3, PA4, PA6 to PA9 PB1, PB3, PB5 PE0 to PE3 PE8, PE10 PE9, PE11 to PE15 PF0 to PF7 Power-On Manual Z I/O Standby K*1 Stop Detected Used I/O I/O Z Z Z Z Z I/O I/O I/O I/O I K*1 K* 1 I/O I/O I/O I/O I I/O I/O I/O Z I I/O Z I/O Z I K*1 Z Z [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6 (STBCR6) is set to 1. 2. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pulldown with a resistance of at least 1 MΩ as required. 3. Pulled-up inside the LSI when there is no input. Rev. 4.00 Jul. 25, 2008 Page 732 of 750 REJ09B0243-0400 Appendix B. Product Code Lineup Product Code Consumer product Industrial product Consumer product Industrial product Consumer product Industrial product Flash memory version (on-chip 64-kbyte) Consumer product Industrial product Consumer product Industrial product R5F71253N50FP R5F71253D50FP R5F71253N50FA R5F71253D50FA R5F71253N50NP R5F71253D50NP R5F71252N50FP R5F71252D50FP R5F71252N50FA R5F71252D50FA R5F71243N50FP R5F71243D50FP R5F71242N50FP R5F71242D50FP R5F71242N50NP R5F71242D50NP R5F71241N50FP R5F71241D50FP R5F71241N50NP R5F71241D50NP VQFN-52 LQFP-48 (FP-48F) VQFN-52 LQFP-48 (FP-48F) QFP-64 (FP-64H) LQFP-64 (FP-64K) VQFN-64 (TNP-64BV) QFP-64 (FP-64H) Package (Package Code) LQFP-64 (FP-64K) Product Type SH7125 Flash memory version (on-chip 128-kbyte) SH7124 Flash memory version (on-chip 128-kbyte) Flash memory version (on-chip 64-kbyte) Consumer product Industrial product Consumer product Industrial product Consumer product Industrial product Flash memory version (on-chip 32-kbyte) Consumer product Industrial product Consumer product Industrial product Rev. 4.00 Jul. 25, 2008 Page 733 of 750 REJ09B0243-0400 C. JEITA Package Code P-LQFP64-10x10-0.50 PLQP0064KB-A 64P6Q-A / FP-64K / FP-64KV 0.3g Appendix E HE *2 c1 c ZE c A A2 A1 REJ09B0243-0400 RENESAS Code Previous Code MASS[Typ.] HD *1 D 33 48 Package Dimensions Rev. 4.00 Jul. 25, 2008 Page 734 of 750 49 bp b1 Reference Symbol 32 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Min D 9.9 E 9.9 A2 HD 11.8 HE A A1 0.05 bp b1 c c1 0° 0.09 0.15 0.1 0.20 0.18 0.145 0.125 8° L L1 e x y 0.5 0.08 0.08 0.20 11.8 Nom 10.0 10.0 1.4 12.0 12.0 12.2 12.2 1.7 0.15 0.25 Max 10.1 10.1 Figure C.1 LQFP-64 64 17 Terminal cross section 1 Index mark ZD 16 F y e x Detail F *3 bp ZD ZE L L1 0.35 1.25 1.25 0.5 1.0 0.65 JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GB-A Previous Code FP-64H/FP-64HV MASS[Typ.] 1.2g HD *1 D 33 48 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 49 bp b1 32 Reference Symbol Dimension in Millimeters Min Nom Max c1 E HE c D E A2 14 14 2.70 *2 Terminal cross section ZE 17 64 HD HE A A1 bp 16.9 16.9 17.2 17.2 17.5 17.5 3.05 0.00 0.29 b1 c 0.12 0.10 0.37 0.35 0.17 0.22 0.25 0.45 A A2 c A1 Figure C.2 QFP-64 1 ZD F 16 e y bp *3 c1 0.15 θ L L1 θ e x 0° 0.8 8° 0.15 Detail F x M y ZD ZE L L1 0.5 1.0 1.0 0.8 1.6 0.10 1.1 Appendix Rev. 4.00 Jul. 25, 2008 Page 735 of 750 REJ09B0243-0400 Appendix E HE *2 c1 c ZE A A2 c e bp x y M *3 A1 REJ09B0243-0400 JEITA Package Code P-LQFP48-10x10-0.65 MASS[Typ.] 0.4g RENESAS Code PLQP0048JA-A Previous Code FP-48F/FP-48FV HD *1 D 25 36 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Rev. 4.00 Jul. 25, 2008 Page 736 of 750 37 24 bp b1 Reference Symbol Dimension in Millimeters Min D E Nom 10 10 A2 1.45 Max 48 13 Terminal cross section HD HE A A1 bp 11.8 11.8 12.0 12.0 12.2 12.2 1.70 0.05 0.27 b1 c c1 0.12 0.1 0.32 0.30 0.17 0.15 0.22 0.15 0.37 Figure C.3 LQFP-48 1 ZD Index mark F 12 θ L L1 θ e x 0° 0.65 8° 0.13 Detail F y ZD ZE L L1 0.4 1.425 1.425 0.5 1.0 0.10 0.6 JEITA Package Code P-VQFN64-8x8-0.40 RENESAS Code PVQN0064LB-A Previous Code TNP-64B/TNP-64BV MASS[Typ.] 0.12g HD D 48 33 49 32 HE E e Reference Symbol Dimension in Millimeters Min Lp Max 64 17 ZE Nom 8.0 8.0 0.89 b b1 xn 1 16 x4 t ZD c c1 A2 y A1 A Figure C.4 VQFN-64 y1 0.005 0.13 0.50 0.02 0.18 0.16 0.4 0.60 0.95 0.04 0.23 0.70 0.05 0.05 0.2 0.2 D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 0.17 Rev. 4.00 Jul. 25, 2008 Page 737 of 750 8.2 8.2 1.0 1.0 0.22 0.20 0.25 Appendix REJ09B0243-0400 Appendix 40 26 HE *2 E e 52 14 ZE Lp c c1 A2 y A1 A REJ09B0243-0400 JEITA Package Code P-VQFN52-7x7-0.40 RENESAS Code PVQN0052LE-A Previous Code MASS[Typ.] 0.095g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH. HD *1 D 27 Rev. 4.00 Jul. 25, 2008 Page 738 of 750 39 Reference Symbol Dimension in Millimeters Min Nom 7.0 7.0 0.89 b b1 xn Max 1 x4 t ZD Figure C.5 VQFN-52 13 y1 0.005 0.13 0.95 0.04 0.23 0.50 0.02 0.18 0.16 0.4 0.60 0.70 0.05 0.05 0.20 0.20 D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 0.17 7.2 7.2 1.1 1.1 0.22 0.20 0.25 Main Revisions and Additions in this Edition Item — Table 1.1 Features Page Revision (See Manual for Details) All 5 Deleted Description of the TCSYSTR register deleted. Deleted Item Packages Specification • • • • • QFP-64 (0.8 pitch) (SH7125) LQFP-64 (0.5 pitch) (SH7125) LQFP-48 (0.65 pitch) (SH7124) VQFN-64 (0.4 pitch) (SH7125 and SH7124) VQFN-52 (0.4 pitch) (SH7124) Table 3.1 Selection of Operating Modes 49 Deleted Pin Setting Mode No. FWE Mode 3 Mode 4* Mode 6* Notes: 1. 2. 1 MD1 1 0 1 Mode Name Single chip mode Boot mode User program mode On-Chip ROM Active Active Active 0 1 1 2 Flash memory programming mode. Prohibited in SH71241. Figure 4.1 Block Diagram of CPG 56 Amended Oscillator unit Divider MTU2 clock (MPφ) XTAL EXTAL Crystal oscillator PLL circuit (×8) ×1/2 ×1/4 ×1/8 Internal clock (Iφ) Oscillation stop detection Oscillation stop detection circuit Peripheral clock (Pφ) Bus clock (Bφ = CK) CPG control unit Rev. 4.00 Jul. 25, 2008 Page 739 of 750 REJ09B0243-0400 Item 4.4.2 Oscillation Stop Detection Control Register (OSCCR) Page Revision (See Manual for Details) 64 Deleted Initial Value R/W R Bit 2 Bit Name Description Oscillation Stop Detection Flag [Setting conditions] • When a stop in the clock input is detected during normal operation When software standby mode is entered By a power-on reset input through the RES pin When software standby mode is canceled OSCSTOP 0 • [Clearing conditions] • • 4.5 Changing Frequency 65 Deleted 4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will change after (1 to 24n) cyc + 11Bφ + 7Pφ. n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/4, or 1/8) cyc: Clock obtained by dividing EXTAL by 8 with the PLL. Rev. 4.00 Jul. 25, 2008 Page 740 of 750 REJ09B0243-0400 Item Table 5.6 Bus Cycles and Address Errors Page Revision (See Manual for Details) 77 Deleted Bus Cycle Bus Master Type Bus Cycle Description Address Errors Instruction fetched from Address error on-chip peripheral occurs module space Instruction fetched from Address error external memory space occurs in single chip mode Instruction CPU fetch Data CPU read/write Word data accessed from even address Longword data accessed in 8-bit onchip peripheral module space Reserved space accessed when in single chip mode None (normal) None (normal) Address error occurs Table 8.1 Address Map 147 Amended Size 128 Kbytes Address H'00020000 to H'FFFF9FFF H'84000000 to H'84007FFF H'84008000 to H'8400FFFF H'84010000 to H'8401FFFF H'84020000 to H'FFFF9FFF H'FFFFA000 to H'FFFFBFFF H'FFFFC000 to H'FFFFFFFF On-chip peripheral I/O 128 Kbytes 64 Kbytes 64 Kbytes 8/16 On-chip RAM 8 Kbytes 8 Kbytes 8 Kbytes 32 Reserved — — — — Reserved On-chip FLASH programming area Reserved 128 Kbytes 64 Kbytes 32 Kbytes 8 Type of Memory Reserved Version — 64 Kbytes Version — 32 Kbytes Version — Bus Width — Figure 9.64 Example of Output Phase Switching by External Input (2) 297 Amended Output waveform of the terminal amended. Amended Output waveform of the terminal amended. Figure 9.66 Example of Output 299 Phase Switching by Means of UF, VF, WF Bit Settings (2) Rev. 4.00 Jul. 25, 2008 Page 741 of 750 REJ09B0243-0400 Item 9.5.2 A/D Converter Activation Page Revision (See Manual for Details) 319 Amended A/D Converter Activation by A/D Converter Start Request Delaying Function: The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 9.4.9, A/D Converter Start Request Delaying Function. 12.7.4 Sending a Break Signal 472 Added …Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPB0DT bit. Therefore, the SPB0DT bit should be set to 1 at first (high level output)…. Table 13.3 Channel Select List 483 Amended Analog Input Channels Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 A/D_0 AN0 2-Channel Scan Mode* (Activated by software) A/D_1 AN4 484 Figure 13.4 Example of 2-Channel Scanning 494 Added Table of Activated by Triggers MTU2 or etc. Amended A/D conversion end (ADF) CONADF bit in ADCSR = 0 CONADF bit in ADCSR = 1 17.2.5 Block Division 580 Added The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB9 is specified when erasing. The user MAT is divided into 16 Kbytes (two blocks) for 32-Kbyte ROM version. Figure 17.4 Block Division of User 580 MAT Amended Rev. 4.00 Jul. 25, 2008 Page 742 of 750 REJ09B0243-0400 Item 17.4.2 (5) Flash Transfer Destination Address Register (FTDAR) Page Revision (See Manual for Details) 591 Amended FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00. which points to the start address (H'FFFFA000) in on-chip RAM. 592 Amended Initial Value R/W All 0 R/W Bit 6 to 0 Bit Name TDA[6:0] Description ••• H'00, H'01, H'05 to H'7F: Setting prohibited when downloading by the SCO bit with user program mode. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. When not using user program mode, set H'00 to the TDA bits. Table 21.1 Absolute Maximum Ratings 707 Deleted Item Analog power supply voltage Analog reference voltage Analog input voltage Symbol AVCC AVref Van Value -0.3 to + 7.0 -0.3 to AVCC + 0.3 -0.3 to AVCC + 0.3 Unit V V V Table 21.2 DC Characteristics 709 Amended Test Item Output high TIOC3B, TIOC3D, voltage Output low voltage TIOC4A to TIOC4D TIOC3B, TIOC3D, TIOC4A to TIOC4D VOL Symbol Min. VOH VCC - 0.8 Typ. — Max. — Unit V Conditions IOH = –5 mA, VCC = 4.5 V to 5.5 V — — 1.0 V IOL = 15 mA, VCC = 4.5 V to 5.5 V — — 0.6 V IOL = 10 mA, VCC = 4.5 V to 5.5 V — — 0.4 V IOL = 8 mA, VCC = 4.5 V to 5.5 V Rev. 4.00 Jul. 25, 2008 Page 743 of 750 REJ09B0243-0400 Rev. 4.00 Jul. 25, 2008 Page 744 of 750 REJ09B0243-0400 Index A A/D conversion time............................... 492 A/D converter (ADC) ............................. 475 A/D converter activation......................... 319 A/D converter characteristics.................. 726 A/D converter interrupt source ............... 495 A/D converter start request delaying function................................................... 308 Absolute accuracy................................... 496 Absolute maximum ratings..................... 707 AC characteristics................................... 711 AC characteristics measurement conditions ............................................... 725 Address error .............................. 77, 86, 660 Addressing modes..................................... 26 Arithmetic operation instructions ............. 39 Asynchronous mode ....................... 411, 444 Clock synchronous mode ................ 411, 454 Clock timing ........................................... 712 CMT interrupt sources ............................ 509 Compare match timer (CMT) ................. 503 Complementary PWM mode .................. 267 Connecting crystal resonator..................... 66 Continuous scan mode ............................ 489 Control signal timing .............................. 714 CPU........................................................... 17 Crystal oscillator ....................................... 57 D Data transfer instructions .......................... 37 DC Characteristics .................................. 708 Dead time compensation......................... 313 Divider ...................................................... 57 B Boot mode .............................................. 607 Branch instructions ................................... 43 Break comparison conditions ................. 113 Break detection and processing .............. 472 Break on data access cycle ..................... 135 Break on instruction fetch cycle ............. 135 Bus state controller (BSC) ...................... 147 E Error protection....................................... 621 Exception handling ................................... 71 Exception handling state ........................... 47 External clock input method ..................... 67 External pulse width measurement ......... 312 External trigger input timing................... 493 C Calculating exception handling vector table addresses ............................... 74 Changing frequency.................................. 65 Clock (MPφ) for the MTU2 module ......... 55 Clock frequency control circuit ................ 57 Clock operating mode............................... 59 Clock pulse generator (CPG).................... 55 F Features of instructions ............................. 23 Flash Memory ......................................... 575 Flash memory characteristics.................. 727 Flash memory configuration ................... 580 Flow of the user break operation............. 134 Full-scale error ........................................ 496 Function for detecting oscillator stop........ 68 Rev. 4.00 Jul. 25, 2008 Page 745 of 750 REJ09B0243-0400 G General illegal instructions ....................... 82 General registers ....................................... 19 Global-base register (GBR) ...................... 20 M Manual reset.............................................. 76 MCU operating modes.............................. 49 Module standby mode............................. 674 Module standby mode setting ........ 474, 499, ........................................................ 510, 660 MTU2 functions...................................... 152 MTU2 interrupts ..................................... 317 MTU2 output pin initialization ............... 348 Multi-function timer pulse unit 2 (MTU2)................................................... 151 Multiply and accumulate registers (MACH and MACL) ................................ 21 Multiprocessor communication function ................................................... 463 H Hardware protection ............................... 620 I I/O ports.................................................. 551 Illegal slot instructions.............................. 82 Immediate data formats ............................ 23 Influences on absolute accuracy ............. 499 Initial user branch processing time ......... 625 Initial values of control register................ 21 Initial values of general register ............... 21 Initial values of system register ................ 21 Initiation intervals of user branch processing ............................................... 625 Instruction formats.................................... 29 Instruction set ........................................... 33 Interrupt controller (INTC)....................... 89 Interrupt exception handling vector table ............................................. 104 Interrupt priority ....................................... 80 Interrupt response time ........................... 111 Interrupt sequence................................... 107 Interrupts .................................................. 79 IRQ interrupts......................................... 102 N NMI interrupt.......................................... 102 Nonlinearity error ................................... 496 Note on Changing Operating Mode .......... 54 Note on crystal resonator .......................... 69 Notes on board design....................... 69, 500 Notes on connecting VCL capacitor......... 728 Notes on noise countermeasures ............. 501 Notes on register access (WDT) ............. 407 Notes on slot illegal instruction exception handling.................................... 87 O Off-board programming mode ................ 658 Offset error.............................................. 496 On-board programming mode................. 607 On-chip peripheral module interrupts ..... 103 Operating clock for each module .............. 58 L List of registers ....................................... 675 Logic operation instructions ..................... 41 Rev. 4.00 Jul. 25, 2008 Page 746 of 750 REJ09B0243-0400 P Package dimensions................................ 734 PC trace .................................................. 138 Peripheral clock (Pφ) ................................ 55 Permissible signal source impedance ..... 499 Pin function controller (PFC) ................. 513 Pin states of this LSI in each processing state....................................... 729 Port output enable (POE)........................ 381 Power-down modes ................................ 661 Power-down state ..................................... 47 Power-on reset .......................................... 75 Procedure register (PR)............................. 21 Product code lineup ................................ 733 Program counter (PC) ............................... 21 Program execution state............................ 47 Q Quantization error................................... 496 R RAM ....................................................... 659 Range of analog power supply and other pin settings .............................. 500 Register ADCR ................................................. 482 ADCSR............................................... 479 ADDR0 to ADDR7............................. 479 ADTSR ............................................... 485 BAMRA ............................................. 116 BAMRB.............................................. 122 BARA ................................................. 116 BARB ................................................. 121 BBRA ................................................. 117 BBRB ................................................. 125 BDMRA ............................................. 120 BDMRB.............................................. 124 BDRA ................................................. 119 BDRB.................................................. 123 BETR .................................................. 131 BRCR.................................................. 127 BRDR.................................................. 133 BRSR .................................................. 132 CMCNT .............................................. 507 CMCOR .............................................. 507 CMCSR............................................... 505 CMSTR............................................... 505 DPFR .................................................. 594 FCCS................................................... 586 FEBS................................................... 603 FECS................................................... 589 FKEY .................................................. 590 FMPAR............................................... 599 FMPDR............................................... 600 FPCS ................................................... 589 FPEFEQ .............................................. 595 FPFR ................................... 598, 601, 604 FRQCR ................................................. 61 FTDAR ............................................... 591 FUBRA ............................................... 596 ICR0...................................................... 93 ICSR1.................................................. 385 ICSR3.................................................. 389 IFCR.................................................... 549 IPRA to IPRF and IPRH to IPRM ........ 99 IRQCR .................................................. 94 IRQSR................................................... 96 OCSR1 ................................................ 388 OSCCR ................................................. 64 PACRL1.............................................. 522 PACRL2.............................................. 522 PACRL3.............................................. 522 PACRL4.............................................. 522 PADRL ............................................... 553 PAIORL .............................................. 522 PAPRL ................................................ 557 PBCRH1 ............................................. 534 PBCRL1.............................................. 534 Rev. 4.00 Jul. 25, 2008 Page 747 of 750 REJ09B0243-0400 PBCRL2 ............................................. 534 PBDRH............................................... 560 PBDRL ............................................... 560 PBIORH ............................................. 533 PBIORL.............................................. 533 PBPRH ............................................... 563 PBPRL................................................ 563 PECRL1.............................................. 539 PECRL2.............................................. 539 PECRL3.............................................. 539 PECRL4.............................................. 539 PEDRL ............................................... 568 PEIORL .............................................. 539 PEPRL ................................................ 571 PFDRL................................................ 574 POECR1 ............................................. 393 POECR2 ............................................. 394 RAMCR.............................................. 670 SCBRR (SCI) ..................................... 431 SCRDR............................................... 415 SCRSR (SCI)...................................... 415 SCSCR (SCI)...................................... 419 SCSDCR............................................. 430 SCSMR (SCI)..................................... 416 SCSPTR (SCI).................................... 428 SCSSR ................................................ 422 SCTDR ............................................... 416 SCTSR (SCI) ...................................... 415 SPOER................................................ 391 STBCR1 ............................................. 664 STBCR2 ............................................. 665 STBCR3 ............................................. 666 STBCR4 ............................................. 667 STBCR5 ............................................. 668 STBCR6 ............................................. 669 TADCOBRA_4 .................................. 208 TADCOBRB_4 .................................. 208 TADCORA_4..................................... 208 TADCORB_4 ..................................... 208 TADCR .............................................. 205 Rev. 4.00 Jul. 25, 2008 Page 748 of 750 REJ09B0243-0400 TBTER................................................ 230 TBTM ................................................. 202 TCBR.................................................. 227 TCDR.................................................. 226 TCNT.................................................. 209 TCNTCMPCLR.................................. 188 TCNTS................................................ 225 TCR..................................................... 162 TDDR ................................................. 226 TDER.................................................. 232 TGCR.................................................. 223 TGR .................................................... 209 TICCR................................................. 203 TIER ................................................... 189 TIOR ................................................... 169 TITCNT .............................................. 229 TITCR................................................. 227 TMDR................................................. 166 TOCR1................................................ 216 TOCR2................................................ 219 TOER.................................................. 215 TOLBR ............................................... 222 TRWER .............................................. 214 TSR ..................................................... 194 TSTR................................................... 210 TSYR .................................................. 212 TWCR................................................. 233 WTCNT .............................................. 404 WTCSR............................................... 405 Register address table (in the order from lower addresses) ........ 676 Register bit list ........................................ 684 Register data format.................................. 22 Register states in each operating mode ... 698 Reset state ................................................. 47 Reset-synchronized PWM mode............. 264 RISC-type ................................................. 23 S SCI interrupt sources .............................. 469 SCSPTR and SCI pins ............................ 470 Sending a break signal ............................ 472 Sequential break ..................................... 137 Serial communication interface (SCI) .... 411 Shift instructions....................................... 42 Single chip mode ...................................... 50 Single mode ............................................ 489 Single-cycle scan mode .......................... 490 Sleep mode ............................................. 671 Software protection................................. 621 Software standby mode........................... 672 Stack after interrupt exception handling .................................................. 110 Stack states after exception handling ends............................................ 84 Status register (SR)................................... 19 System control instructions....................... 44 The address map for the operating modes. 51 Trap instructions ....................................... 81 U User break controller (UBC)................... 113 User break interrupt ................................ 103 User MAT ............................................... 580 User program mode................................. 611 Using interval timer mode....................... 409 Using watchdog timer mode ................... 408 V Vector numbers and vector table address offsets........................................... 73 Vector-base register (VBR) ...................... 20 W T Target pins and conditions for highimpedance control................................... 396 Watchdog timer (WDT) .......................... 401 Rev. 4.00 Jul. 25, 2008 Page 749 of 750 REJ09B0243-0400 Rev. 4.00 Jul. 25, 2008 Page 750 of 750 REJ09B0243-0400 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7125 Group, SH7124 Group Publication Date: Rev.1.00, Mar. 25, 2005 Rev.4.00, Jul. 25, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: (408) 382-7500, Fax: (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: (1628) 585-100, Fax: (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. 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