User's Manual
32
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
SH7280 Group, SH7243 Group
User’s Manual: Hardware
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine family
www.renesas.com
Rev.3.00 Mar 2011
Page ii of xxx
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and
"Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
Page iii of xxx
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
⎯ The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
⎯ The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
⎯ The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
⎯ When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
⎯ The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Page iv of xxx
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the SH7280 and SH7243 Groups. Before
using any of the documents, please visit our web site to verify that you have the most up-todate available version of the document.
Document Type
Contents
Document Title
Document No.
Data Sheet
Overview of hardware and electrical ⎯
characteristics
⎯
User’s Manual:
Hardware
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
SH7280 Group,
SH7243 Group
User’s Manual: Hardware
This manual
User’s Manual:
Software
Detailed descriptions of the CPU
and instruction set
SH-2A, SH2A-FPU
Software Manual
REJ09B0051
Application Note
Examples of applications and
sample programs
The latest versions are available from our
web site.
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.
Page v of xxx
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4)
(2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Page vi of xxx
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
[Bit Chart]
Bit:
Initial value:
R/W:
15
14
⎯
⎯
13
12
11
ASID2 ASID1 ASID0
10
9
8
7
6
5
4
⎯
⎯
⎯
⎯
⎯
⎯
Q
3
2
1
ACMP2 ACMP1 ACMP0
0
IFE
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(1)
[Table of Bits]
Bit
(2)
(3)
(4)
(5)
Bit Name
−
−
Initial Value R/W
Description
0
0
R
R
Reserved
These bits are always read as 0.
13 to 11
ASID2 to
ASID0
All 0
R/W
Address Identifier
These bits enable or disable the pin function.
10
−
0
R
Reserved
This bit is always read as 0.
9
−
1
R
Reserved
This bit is always read as 1.
−
0
15
14
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(1) Bit
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
(2) Bit name
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(3) Initial value
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(4) R/W
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W: The bit or field is readable and writable.
R/(W): The bit or field is readable and writable.
However, writing is only performed to flag clearing.
The bit or field is readable.
R:
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
The bit or field is writable.
W:
(5) Description
Describes the function of the bit or field and specifies the values for writing.
Page vii of xxx
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
•
Abbreviations specific to this product
Abbreviation
Description
BSC
Bus controller
CPG
DTC
INTC
SCI
WDT
Clock pulse generator
Data transfer controller
Interrupt controller
Serial communication interface
Watchdog timer
• Abbreviations other than those listed above
Abbreviation
Description
ACIA
Asynchronous communication interface adapter
bps
Bits per second
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
Cyclic redundancy check
Direct memory access
Direct memory access controller
Global System for Mobile Communications
High impedance
Inter Equipment Bus
Input/output
Infrared Data Association
Least significant bit
Most significant bit
No connection
Phase-locked loop
Pulse width modulation
Special function register
Subscriber Identity Module
UART
VCO
Universal asynchronous receiver/transmitter
Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Page viii of xxx
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
SH7286, SH7285, and SH7243 Features .............................................................................. 1
Block Diagram...................................................................................................................... 9
Pin Assignment ................................................................................................................... 11
Pin Functions ...................................................................................................................... 14
Section 2 CPU......................................................................................................23
2.1
2.2
2.3
2.4
2.5
Register Configuration........................................................................................................ 23
2.1.1
General Registers................................................................................................ 23
2.1.2
Control Registers ................................................................................................ 24
2.1.3
System Registers................................................................................................. 26
2.1.4
Register Banks .................................................................................................... 27
2.1.5
Initial Values of Registers................................................................................... 27
Data Formats....................................................................................................................... 28
2.2.1
Data Format in Registers .................................................................................... 28
2.2.2
Data Formats in Memory .................................................................................... 28
2.2.3
Immediate Data Format ...................................................................................... 29
Instruction Features............................................................................................................. 30
2.3.1
RISC-Type Instruction Set.................................................................................. 30
2.3.2
Addressing Modes .............................................................................................. 34
2.3.3
Instruction Format............................................................................................... 39
Instruction Set ..................................................................................................................... 43
2.4.1
Instruction Set by Classification ......................................................................... 43
2.4.2
Data Transfer Instructions................................................................................... 48
2.4.3
Arithmetic Operation Instructions ...................................................................... 52
2.4.4
Logic Operation Instructions .............................................................................. 55
2.4.5
Shift Instructions................................................................................................. 56
2.4.6
Branch Instructions ............................................................................................. 57
2.4.7
System Control Instructions................................................................................ 58
2.4.8
Bit Manipulation Instructions ............................................................................. 60
Processing States................................................................................................................. 61
Section 3 MCU Operating Modes .......................................................................63
3.1
3.2
3.3
Selection of Operating Modes ............................................................................................ 63
Input/Output Pins................................................................................................................ 64
Operating Modes................................................................................................................. 64
Page ix of xxx
3.4
3.5
3.6
3.3.1
Mode 0 (MCU Extension Mode 0) ..................................................................... 64
3.3.2
Mode 1 (MCU Extension Mode 1) ..................................................................... 64
3.3.3
Mode 2 (MCU Extension Mode 2) ..................................................................... 64
3.3.4
Mode 3 (Single Chip Mode) ............................................................................... 64
Address Map....................................................................................................................... 65
Initial State in This LSI....................................................................................................... 72
Note on Changing Operating Mode.................................................................................... 72
Section 4 Clock Pulse Generator (CPG) ............................................................. 73
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Features............................................................................................................................... 73
Input/Output Pins................................................................................................................ 77
Clock Operating Modes ...................................................................................................... 78
Register Descriptions.......................................................................................................... 81
4.4.1
Frequency Control Register (FRQCR) ............................................................... 81
4.4.2
MTU2S Clock Frequency Control Register (MCLKCR) ................................... 84
4.4.3
AD Clock Frequency Control Register (ACLKCR) ........................................... 85
4.4.4
Oscillation Stop Detection Control Register (OSCCR) ...................................... 86
Changing the Frequency ..................................................................................................... 87
Oscillator ............................................................................................................................ 88
4.6.1
Connecting Crystal Resonator ............................................................................ 88
4.6.2
External Clock Input Method.............................................................................. 89
Oscillation Stop Detection .................................................................................................. 90
USB Operating Clock (48 MHz) ........................................................................................ 91
4.8.1
Connecting a Ceramic Resonator........................................................................ 91
4.8.2
Input of an External 48-MHz Clock Signal ........................................................ 92
4.8.3
Handling of pins when a Ceramic Resonator is not Connected
(the Internal CPG is Selected or the USB is Not in Use) .................................... 93
Notes on Board Design ....................................................................................................... 94
4.9.1
Note on Using an External Crystal Resonator .................................................... 94
Section 5 Exception Handling ............................................................................. 95
5.1
5.2
5.3
Overview ............................................................................................................................ 95
5.1.1
Types of Exception Handling and Priority ......................................................... 95
5.1.2
Exception Handling Operations.......................................................................... 97
5.1.3
Exception Handling Vector Table ...................................................................... 99
Resets................................................................................................................................ 101
5.2.1
Types of Reset .................................................................................................. 101
5.2.2
Power-On Reset ................................................................................................ 102
5.2.3
Manual Reset .................................................................................................... 104
Address Errors .................................................................................................................. 105
Page x of xxx
5.4
5.5
5.6
5.7
5.8
5.9
5.3.1
Address Error Sources ...................................................................................... 105
5.3.2
Address Error Exception Handling ................................................................... 106
Register Bank Errors......................................................................................................... 107
5.4.1
Register Bank Error Sources............................................................................. 107
5.4.2
Register Bank Error Exception Handling ......................................................... 107
Interrupts........................................................................................................................... 108
5.5.1
Interrupt Sources............................................................................................... 108
5.5.2
Interrupt Priority Level ..................................................................................... 109
5.5.3
Interrupt Exception Handling ........................................................................... 110
Exceptions Triggered by Instructions ............................................................................... 111
5.6.1
Types of Exceptions Triggered by Instructions ................................................ 111
5.6.2
Trap Instructions ............................................................................................... 112
5.6.3
Slot Illegal Instructions ..................................................................................... 112
5.6.4
General Illegal Instructions............................................................................... 113
5.6.5
Integer Division Instructions............................................................................. 113
When Exception Sources Are Not Accepted .................................................................... 114
Stack Status after Exception Handling Ends..................................................................... 115
Usage Notes ...................................................................................................................... 117
5.9.1
Value of Stack Pointer (SP) .............................................................................. 117
5.9.2
Value of Vector Base Register (VBR) .............................................................. 117
5.9.3
Address Errors Caused by Stacking of Address Error Exception
Handling............................................................................................................ 117
5.9.4
Note When Changing Interrupt Mask Level (IMASK) of Status Register
(SR) in CPU ...................................................................................................... 117
Section 6 Interrupt Controller (INTC) ...............................................................119
6.1
6.2
6.3
6.4
Features............................................................................................................................. 119
Input/Output Pins.............................................................................................................. 121
Register Descriptions........................................................................................................ 122
6.3.1
Interrupt Priority Registers 01, 02, 05 to 18
(IPR01, IPR02, IPR05 to IPR18) ...................................................................... 123
6.3.2
Interrupt Control Register 0 (ICR0).................................................................. 125
6.3.3
Interrupt Control Register 1 (ICR1).................................................................. 126
6.3.4
IRQ Interrupt Request Register (IRQRR)......................................................... 127
6.3.5
Bank Control Register (IBCR).......................................................................... 129
6.3.6
Bank Number Register (IBNR)......................................................................... 130
6.3.7
USB-DTC Transfer Interrupt Request Register (USDTENDRR) .................... 132
Interrupt Sources............................................................................................................... 133
6.4.1
NMI Interrupt.................................................................................................... 133
6.4.2
User Break Interrupt ......................................................................................... 133
Page xi of xxx
6.5
6.6
6.7
6.8
6.9
6.10
6.4.3
H-UDI Interrupt ................................................................................................ 133
6.4.4
IRQ Interrupts................................................................................................... 134
6.4.5
On-Chip Peripheral Module Interrupts ............................................................. 135
Interrupt Exception Handling Vector Table and Priority.................................................. 136
Operation .......................................................................................................................... 145
6.6.1
Interrupt Operation Sequence ........................................................................... 145
6.6.2
Stack after Interrupt Exception Handling ......................................................... 148
Interrupt Response Time................................................................................................... 149
Register Banks .................................................................................................................. 155
6.8.1
Banked Register and Input/Output of Banks .................................................... 156
6.8.2
Bank Save and Restore Operations................................................................... 156
6.8.3
Save and Restore Operations after Saving to All Banks................................... 158
6.8.4
Register Bank Exception .................................................................................. 159
6.8.5
Register Bank Error Exception Handling ......................................................... 159
Data Transfer with Interrupt Request Signals................................................................... 160
6.9.1
Handling Interrupt Request Signals as DTC Activating Sources and
CPU Interrupt Sources but Not as DMAC Activating Sources......................... 162
6.9.2
Handling Interrupt Request Signals as DMAC Activating Sources but
Not as CPU Interrupt Sources ........................................................................... 162
6.9.3
Handling Interrupt Request Signals as DTC Activating Sources but Not as
CPU Interrupt Sources or DMAC Activating Sources...................................... 162
6.9.4
Handling Interrupt Request Signals as CPU Interrupt Sources but Not as
DTC Activating Sources or DMAC Activating Sources................................... 163
Usage Notes ...................................................................................................................... 163
6.10.1
Timing to Clear an Interrupt Source ................................................................. 163
6.10.2
In Case the NMI Pin is not in Use .................................................................... 163
6.10.3
Negate Timing of IRQOUT .............................................................................. 164
6.10.4 Notes on Canceling Software Standby Mode with an IRQx Interrupt
Request.............................................................................................................. 164
Section 7 User Break Controller (UBC)............................................................ 165
7.1
7.2
7.3
Features............................................................................................................................. 165
Input/Output Pin ............................................................................................................... 167
Register Descriptions........................................................................................................ 168
7.3.1
Break Address Register_0 (BAR_0)................................................................. 169
7.3.2
Break Address Mask Register_0 (BAMR_0) ................................................... 170
7.3.3
Break Bus Cycle Register_0 (BBR_0).............................................................. 171
7.3.4
Break Address Register_1 (BAR_1)................................................................. 173
7.3.5
Break Address Mask Register_1 (BAMR_1) ................................................... 174
7.3.6
Break Bus Cycle Register_1 (BBR_1).............................................................. 175
Page xii of xxx
7.4
7.5
7.6
7.3.7
Break Address Register_2 (BAR_2)................................................................. 177
7.3.8
Break Address Mask Register_2 (BAMR_2) ................................................... 178
7.3.9
Break Bus Cycle Register_2 (BBR_2).............................................................. 179
7.3.10
Break Address Register_3 (BAR_3)................................................................. 181
7.3.11
Break Address Mask Register_3 (BAMR_3) ................................................... 182
7.3.12
Break Bus Cycle Register_3 (BBR_3).............................................................. 183
7.3.13
Break Control Register (BRCR) ....................................................................... 185
Operation .......................................................................................................................... 189
7.4.1
Flow of the User Break Operation .................................................................... 189
7.4.2
Break on Instruction Fetch Cycle...................................................................... 190
7.4.3
Break on Data Access Cycle............................................................................. 191
7.4.4
Value of Saved Program Counter ..................................................................... 192
7.4.5
Usage Examples................................................................................................ 193
Interrupt Source ................................................................................................................ 195
Usage Notes ...................................................................................................................... 196
Section 8 Data Transfer Controller (DTC) ........................................................197
8.1
8.2
8.3
8.4
8.5
Features............................................................................................................................. 197
Register Descriptions........................................................................................................ 199
8.2.1
DTC Mode Register A (MRA) ......................................................................... 200
8.2.2
DTC Mode Register B (MRB).......................................................................... 201
8.2.3
DTC Source Address Register (SAR)............................................................... 203
8.2.4
DTC Destination Address Register (DAR)....................................................... 203
8.2.5
DTC Transfer Count Register A (CRA) ........................................................... 204
8.2.6
DTC Transfer Count Register B (CRB)............................................................ 205
8.2.7
DTC Enable Registers A to E (DTCERA to DTCERE) ................................... 206
8.2.8
DTC Control Register (DTCCR) ...................................................................... 207
8.2.9
DTC Vector Base Register (DTCVBR)............................................................ 209
8.2.10
Bus Function Extending Register (BSCEHR) .................................................. 209
Activation Sources............................................................................................................ 210
Location of Transfer Information and DTC Vector Table ................................................ 210
Operation .......................................................................................................................... 215
8.5.1
Transfer Information Read Skip Function ........................................................ 220
8.5.2
Transfer Information Write-Back Skip Function .............................................. 221
8.5.3
Normal Transfer Mode ..................................................................................... 221
8.5.4
Repeat Transfer Mode....................................................................................... 222
8.5.5
Block Transfer Mode ........................................................................................ 224
8.5.6
Chain Transfer .................................................................................................. 225
8.5.7
Operation Timing.............................................................................................. 227
8.5.8
Number of DTC Execution Cycles ................................................................... 230
Page xiii of xxx
8.6
8.7
8.8
8.9
8.5.9
DTC Bus Release Timing ................................................................................. 232
8.5.10
DTC Activation Priority Order ......................................................................... 235
DTC Activation by Interrupt............................................................................................. 237
Examples of Use of the DTC............................................................................................ 238
8.7.1
Normal Transfer Mode ..................................................................................... 238
8.7.2
Chain Transfer when Transfer Counter = 0 ...................................................... 239
Interrupt Sources............................................................................................................... 240
Usage Notes ...................................................................................................................... 241
8.9.1
Module Standby Mode Setting ......................................................................... 241
8.9.2
On-Chip RAM .................................................................................................. 241
8.9.3
DTCE Bit Setting.............................................................................................. 241
8.9.4
Chain Transfer .................................................................................................. 241
8.9.5
Transfer Information Start Address, Source Address, and Destination
Address ............................................................................................................. 241
8.9.6
Access to DTC Registers through DTC............................................................ 242
8.9.7
Note on IRQ Interrupt as DTC Activation Source............................................ 242
8.9.8
Note on SCI or SCIF as DTC Activation Sources ............................................ 242
8.9.9
Clearing Interrupt Source Flag.......................................................................... 242
8.9.10
Conflict between NMI Interrupt and DTC Activation ...................................... 242
8.9.11
Note on USB as DTC Activation Sources ........................................................ 242
8.9.12
Operation when a DTC Activation Request has been Cancelled...................... 243
8.9.13
Note on Writing to DTCER .............................................................................. 243
Section 9 Bus State Controller (BSC) ............................................................... 245
9.1
9.2
9.3
9.4
9.5
Features............................................................................................................................. 245
Input/Output Pins.............................................................................................................. 248
Area Overview.................................................................................................................. 250
9.3.1
Address Map..................................................................................................... 250
9.3.2
Setting Operating Modes .................................................................................. 253
Register Descriptions........................................................................................................ 255
9.4.1
Common Control Register (CMNCR) .............................................................. 256
9.4.2
CSn Space Bus Control Register (CSnBCR) (n = 0 to 7) ................................. 259
9.4.3
CSn Space Wait Control Register (CSnWCR) (n = 0 to 7) .............................. 264
9.4.4
SDRAM Control Register (SDCR)................................................................... 293
9.4.5
Refresh Timer Control/Status Register (RTCSR)............................................. 297
9.4.6
Refresh Timer Counter (RTCNT)..................................................................... 299
9.4.7
Refresh Time Constant Register (RTCOR) ...................................................... 300
9.4.8
Bus Function Extending Register (BSCEHR) .................................................. 301
Operation .......................................................................................................................... 305
9.5.1
Endian/Access Size and Data Alignment.......................................................... 305
Page xiv of xxx
9.6
9.5.2
Normal Space Interface..................................................................................... 310
9.5.3
Access Wait Control ......................................................................................... 315
9.5.4
CSn Assert Period Expansion ........................................................................... 317
9.5.5
MPX-I/O Interface ............................................................................................ 318
9.5.6
SDRAM Interface ............................................................................................. 322
9.5.7
Burst ROM (Clock Asynchronous) Interface ................................................... 364
9.5.8
SRAM Interface with Byte Selection................................................................ 367
9.5.9
Burst ROM (Clock Synchronous) Interface...................................................... 372
9.5.10
Wait between Access Cycles ............................................................................ 373
9.5.11
Bus Arbitration ................................................................................................. 380
9.5.12
Others................................................................................................................ 382
Interrupt Source ................................................................................................................ 385
Section 10 Direct Memory Access Controller (DMAC) ...................................387
10.1
10.2
10.3
10.4
10.5
10.6
Features............................................................................................................................. 387
Input/Output Pins.............................................................................................................. 389
Register Descriptions........................................................................................................ 390
10.3.1
DMA Source Address Registers (SAR)............................................................ 395
10.3.2
DMA Destination Address Registers (DAR).................................................... 396
10.3.3
DMA Transfer Count Registers (DMATCR) ................................................... 397
10.3.4
DMA Channel Control Registers (CHCR) ....................................................... 398
10.3.5
DMA Reload Source Address Registers (RSAR) ............................................. 406
10.3.6
DMA Reload Destination Address Registers (RDAR) ..................................... 407
10.3.7
DMA Reload Transfer Count Registers (RDMATCR)..................................... 408
10.3.8
DMA Operation Register (DMAOR) ............................................................... 409
10.3.9
DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).............. 413
Operation .......................................................................................................................... 415
10.4.1
Transfer Flow.................................................................................................... 415
10.4.2
DMA Transfer Requests ................................................................................... 417
10.4.3
Channel Priority................................................................................................ 421
10.4.4
DMA Transfer Types........................................................................................ 424
10.4.5
Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 433
Interrupt Sources............................................................................................................... 437
10.5.1
Interrupt Sources and Priority Order................................................................. 437
Usage Notes ...................................................................................................................... 439
10.6.1
Setting of the Half-End Flag and the Half-End Interrupt.................................. 439
10.6.2
Timing of DACK and TEND Outputs .............................................................. 439
10.6.3
CHCR Setting ................................................................................................... 439
10.6.4
Note on Activation of Multiple Channels ......................................................... 439
10.6.5
Note on Transfer Request Input ........................................................................ 439
Page xv of xxx
10.6.6
10.6.7
Conflict between NMI Interrupt and DMAC Activation .................................. 440
Number of On-Chip RAM Access Cycles from DMAC .................................. 440
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 441
11.1
11.2
11.3
Features............................................................................................................................. 441
Input/Output Pins.............................................................................................................. 447
Register Descriptions........................................................................................................ 448
11.3.1
Timer Control Register (TCR).......................................................................... 452
11.3.2
Timer Mode Register (TMDR)......................................................................... 456
11.3.3
Timer I/O Control Register (TIOR).................................................................. 459
11.3.4
Timer Compare Match Clear Register (TCNTCMPCLR)................................ 478
11.3.5
Timer Interrupt Enable Register (TIER)........................................................... 479
11.3.6
Timer Status Register (TSR)............................................................................. 484
11.3.7
Timer Buffer Operation Transfer Mode Register (TBTM)............................... 491
11.3.8
Timer Input Capture Control Register (TICCR)............................................... 493
11.3.9
Timer Synchronous Clear Register S (TSYCRS) ............................................. 494
11.3.10 Timer A/D Converter Start Request Control Register (TADCR) ..................... 496
11.3.11 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4) .................................................................. 499
11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4)............................................................. 499
11.3.13 Timer Counter (TCNT)..................................................................................... 500
11.3.14 Timer General Register (TGR) ......................................................................... 500
11.3.15 Timer Start Register (TSTR) ............................................................................ 501
11.3.16 Timer Synchronous Register (TSYR)............................................................... 503
11.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ................................. 505
11.3.18 Timer Read/Write Enable Register (TRWER) ................................................. 508
11.3.19 Timer Output Master Enable Register (TOER) ................................................ 509
11.3.20 Timer Output Control Register 1 (TOCR1)...................................................... 510
11.3.21 Timer Output Control Register 2 (TOCR2)...................................................... 513
11.3.22 Timer Output Level Buffer Register (TOLBR) ................................................ 516
11.3.23 Timer Gate Control Register (TGCR) .............................................................. 517
11.3.24 Timer Subcounter (TCNTS) ............................................................................. 519
11.3.25 Timer Dead Time Data Register (TDDR)......................................................... 520
11.3.26 Timer Cycle Data Register (TCDR) ................................................................. 520
11.3.27 Timer Cycle Buffer Register (TCBR)............................................................... 521
11.3.28 Timer Interrupt Skipping Set Register (TITCR)............................................... 521
11.3.29 Timer Interrupt Skipping Counter (TITCNT)................................................... 523
11.3.30 Timer Buffer Transfer Set Register (TBTER) .................................................. 524
11.3.31 Timer Dead Time Enable Register (TDER) ..................................................... 526
Page xvi of xxx
11.4
11.5
11.6
11.7
11.3.32 Timer Waveform Control Register (TWCR) .................................................... 527
11.3.33 Bus Master Interface ......................................................................................... 529
Operation .......................................................................................................................... 530
11.4.1
Basic Functions................................................................................................. 530
11.4.2
Synchronous Operation..................................................................................... 536
11.4.3
Buffer Operation ............................................................................................... 538
11.4.4
Cascaded Operation .......................................................................................... 542
11.4.5
PWM Modes ..................................................................................................... 547
11.4.6
Phase Counting Mode ....................................................................................... 552
11.4.7
Reset-Synchronized PWM Mode...................................................................... 559
11.4.8
Complementary PWM Mode............................................................................ 562
11.4.9
A/D Converter Start Request Delaying Function.............................................. 608
11.4.10 MTU2-MTU2S Synchronous Operation........................................................... 613
11.4.11 External Pulse Width Measurement.................................................................. 619
11.4.12 Dead Time Compensation................................................................................. 620
11.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ... 623
Interrupt Sources............................................................................................................... 624
11.5.1
Interrupt Sources and Priorities......................................................................... 624
11.5.2
DMAC and DTC Activation ............................................................................. 626
11.5.3
A/D Converter Activation................................................................................. 627
Operation Timing.............................................................................................................. 629
11.6.1
Input/Output Timing ......................................................................................... 629
11.6.2
Interrupt Signal Timing..................................................................................... 636
Usage Notes ...................................................................................................................... 642
11.7.1
Module Standby Mode Setting ......................................................................... 642
11.7.2
Input Clock Restrictions ................................................................................... 642
11.7.3
Caution on Period Setting ................................................................................. 643
11.7.4
Contention between TCNT Write and Clear Operations.................................. 643
11.7.5
Contention between TCNT Write and Increment Operations........................... 644
11.7.6
Contention between TGR Write and Compare Match ...................................... 645
11.7.7
Contention between Buffer Register Write and Compare Match ..................... 646
11.7.8
Contention between Buffer Register Write and TCNT Clear ........................... 647
11.7.9
Contention between TGR Read and Input Capture........................................... 648
11.7.10 Contention between TGR Write and Input Capture.......................................... 649
11.7.11 Contention between Buffer Register Write and Input Capture ......................... 650
11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade
Connection ........................................................................................................ 650
11.7.13 Counter Value during Complementary PWM Mode Stop ................................ 652
11.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 652
11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 653
Page xvii of xxx
11.8
11.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 654
11.7.17 Contention between Overflow/Underflow and Counter Clearing..................... 655
11.7.18 Contention between TCNT Write and Overflow/Underflow............................ 656
11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to
Reset-Synchronized PWM Mode...................................................................... 656
11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized
PWM Mode....................................................................................................... 657
11.7.21 Interrupts in Module Standby Mode ................................................................. 657
11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection........ 657
11.7.23 Note on Output Waveform Control at Synchronous Counter Clearing in
Complementary PWM Mode ............................................................................ 658
MTU2 Output Pin Initialization........................................................................................ 660
11.8.1
Operating Modes .............................................................................................. 660
11.8.2
Reset Start Operation ........................................................................................ 660
11.8.3
Operation in Case of Re-Setting Due to Error during Operation, etc. .............. 661
11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of
Error during Operation, etc. .............................................................................. 662
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) .............................. 693
12.1
12.2
Input/Output Pins.............................................................................................................. 696
Register Descriptions........................................................................................................ 697
Section 13 Port Output Enable 2 (POE2) .......................................................... 701
13.1
13.2
13.3
13.4
13.5
13.6
Features............................................................................................................................. 701
Input/Output Pins.............................................................................................................. 703
Register Descriptions........................................................................................................ 705
13.3.1
Input Level Control/Status Register 1 (ICSR1) ................................................ 706
13.3.2
Output Level Control/Status Register 1 (OCSR1) ............................................ 710
13.3.3
Input Level Control/Status Register 2 (ICSR2) ................................................ 711
13.3.4
Output Level Control/Status Register 2 (OCSR2) ............................................ 715
13.3.5
Input Level Control/Status Register 3 (ICSR3) ................................................ 716
13.3.6
Software Port Output Enable Register (SPOER) .............................................. 718
13.3.7
Port Output Enable Control Register 1 (POECR1)........................................... 720
13.3.8
Port Output Enable Control Register 2 (POECR2)........................................... 721
Operation .......................................................................................................................... 727
13.4.1
Input Level Detection Operation ...................................................................... 729
13.4.2
Output-Level Compare Operation .................................................................... 730
13.4.3
Release from High-Impedance State ................................................................ 731
Interrupts........................................................................................................................... 731
Usage Notes ...................................................................................................................... 732
Page xviii of xxx
13.6.1
Pins States when the Watchdog Timer has Issued a Power-on Reset ............... 732
Section 14 Compare Match Timer (CMT) ........................................................733
14.1
14.2
14.3
14.4
14.5
Features............................................................................................................................. 733
Register Descriptions........................................................................................................ 734
14.2.1
Compare Match Timer Start Register (CMSTR) .............................................. 735
14.2.2
Compare Match Timer Control/Status Register (CMCSR) .............................. 736
14.2.3
Compare Match Counter (CMCNT) ................................................................. 738
14.2.4
Compare Match Constant Register (CMCOR) ................................................. 738
Operation .......................................................................................................................... 739
14.3.1
Interval Count Operation .................................................................................. 739
14.3.2
CMCNT Count Timing..................................................................................... 739
Interrupts........................................................................................................................... 740
14.4.1
Interrupt Sources and DTC/DMA Transfer Requests ....................................... 740
14.4.2
Timing of Compare Match Flag Setting ........................................................... 740
14.4.3
Timing of Compare Match Flag Clearing......................................................... 741
Usage Notes ...................................................................................................................... 742
14.5.1
Conflict between Write and Compare-Match Processes of CMCNT ............... 742
14.5.2
Conflict between Word-Write and Count-Up Processes of CMCNT ............... 743
14.5.3
Conflict between Byte-Write and Count-Up Processes of CMCNT................. 744
14.5.4
Compare Match between CMCNT and CMCOR ............................................. 744
Section 15 Watchdog Timer (WDT)..................................................................745
15.1
15.2
15.3
15.4
15.5
15.6
Features............................................................................................................................. 745
Input/Output Pin ............................................................................................................... 747
Register Descriptions........................................................................................................ 748
15.3.1
Watchdog Timer Counter (WTCNT)................................................................ 748
15.3.2
Watchdog Timer Control/Status Register (WTCSR)........................................ 749
15.3.3
Watchdog Reset Control/Status Register (WRCSR) ........................................ 752
15.3.4
Notes on Register Access.................................................................................. 753
WDT Usage ...................................................................................................................... 755
15.4.1
Changing the Frequency ................................................................................... 755
15.4.2
Using Watchdog Timer Mode........................................................................... 756
15.4.3
Using Interval Timer Mode .............................................................................. 758
Interrupt Source ................................................................................................................ 759
Usage Notes ...................................................................................................................... 760
15.6.1
Timer Variation................................................................................................. 760
15.6.2
Prohibition against Setting H'FF to WTCNT.................................................... 760
15.6.3
System Reset by WDTOVF Signal................................................................... 760
15.6.4
Manual Reset in Watchdog Timer Mode .......................................................... 761
Page xix of xxx
15.6.5
Connection of the WDTOVF Pin ..................................................................... 761
Section 16 Serial Communication Interface (SCI)............................................ 763
16.1
16.2
16.3
16.4
16.5
16.6
16.7
Features............................................................................................................................. 763
Input/Output Pins.............................................................................................................. 765
Register Descriptions........................................................................................................ 766
16.3.1
Receive Shift Register (SCRSR) ...................................................................... 767
16.3.2
Receive Data Register (SCRDR) ...................................................................... 767
16.3.3
Transmit Shift Register (SCTSR) ..................................................................... 768
16.3.4
Transmit Data Register (SCTDR)..................................................................... 768
16.3.5
Serial Mode Register (SCSMR)........................................................................ 768
16.3.6
Serial Control Register (SCSCR)...................................................................... 772
16.3.7
Serial Status Register (SCSSR) ........................................................................ 775
16.3.8
Serial Port Register (SCSPTR) ......................................................................... 781
16.3.9
Serial Direction Control Register (SCSDCR)................................................... 783
16.3.10 Bit Rate Register (SCBRR) .............................................................................. 784
Operation .......................................................................................................................... 795
16.4.1
Overview .......................................................................................................... 795
16.4.2
Operation in Asynchronous Mode .................................................................... 797
16.4.3
Clock Synchronous Mode................................................................................. 808
16.4.4
Multiprocessor Communication Function ........................................................ 817
16.4.5
Multiprocessor Serial Data Transmission ......................................................... 819
16.4.6
Multiprocessor Serial Data Reception .............................................................. 820
SCI Interrupt Sources and DTC........................................................................................ 823
Serial Port Register (SCSPTR) and SCI Pins ................................................................... 824
Usage Notes ...................................................................................................................... 826
16.7.1
SCTDR Writing and TDRE Flag...................................................................... 826
16.7.2
Multiple Receive Error Occurrence .................................................................. 826
16.7.3
Break Detection and Processing ....................................................................... 827
16.7.4
Sending a Break Signal..................................................................................... 827
16.7.5 Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode)....................................................................................... 827
16.7.6
Note on Using DTC .......................................................................................... 829
16.7.7
Note on Using External Clock in Clock Synchronous Mode............................ 829
16.7.8
Module Standby Mode Setting ......................................................................... 829
Section 17 Serial Communication Interface with FIFO (SCIF)........................ 831
17.1
17.2
17.3
Features............................................................................................................................. 831
Input/Output Pins.............................................................................................................. 833
Register Descriptions........................................................................................................ 834
Page xx of xxx
17.4
17.5
17.6
17.3.1
Receive Shift Register (SCRSR)....................................................................... 834
17.3.2
Receive FIFO Data Register (SCFRDR) .......................................................... 835
17.3.3
Transmit Shift Register (SCTSR) ..................................................................... 835
17.3.4
Transmit FIFO Data Register (SCFTDR) ......................................................... 836
17.3.5
Serial Mode Register (SCSMR)........................................................................ 837
17.3.6
Serial Control Register (SCSCR)...................................................................... 840
17.3.7
Serial Status Register (SCFSR) ........................................................................ 844
17.3.8
Bit Rate Register (SCBRR) .............................................................................. 852
17.3.9
FIFO Control Register (SCFCR) ...................................................................... 859
17.3.10 FIFO Data Count Register (SCFDR) ................................................................ 861
17.3.11 Serial Port Register (SCSPTR) ......................................................................... 862
17.3.12 Line Status Register (SCLSR) .......................................................................... 863
17.3.13 Serial Extended Mode Register (SCSEMR) ..................................................... 865
Operation .......................................................................................................................... 866
17.4.1
Overview........................................................................................................... 866
17.4.2
Operation in Asynchronous Mode .................................................................... 868
17.4.3
Operation in Clocked Synchronous Mode ........................................................ 878
SCIF Interrupts ................................................................................................................. 887
Usage Notes ...................................................................................................................... 888
17.6.1
SCFTDR Writing and TDFE Flag .................................................................... 888
17.6.2
SCFRDR Reading and RDF Flag ..................................................................... 888
17.6.3
Restriction on DMAC and DTC Usage ............................................................ 889
17.6.4
Break Detection and Processing ....................................................................... 889
17.6.5
Sending a Break Signal..................................................................................... 889
17.6.6 Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode)....................................................................................... 890
17.6.7
FER Flag and PER Flag of Serial Status Register (SCFSR)............................. 891
Section 18 Synchronous Serial Communication Unit (SSU) ............................893
18.1
18.2
18.3
Features............................................................................................................................. 893
Input/Output Pins.............................................................................................................. 895
Register Descriptions........................................................................................................ 896
18.3.1
SS Control Register H (SSCRH) ...................................................................... 897
18.3.2
SS Control Register L (SSCRL) ....................................................................... 899
18.3.3
SS Mode Register (SSMR) ............................................................................... 900
18.3.4
SS Enable Register (SSER) .............................................................................. 901
18.3.5
SS Status Register (SSSR) ................................................................................ 903
18.3.6
SS Control Register 2 (SSCR2) ........................................................................ 906
18.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)............................... 908
18.3.8
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) ................................ 909
Page xxi of xxx
18.4
18.5
18.6
18.3.9
SS Shift Register (SSTRSR)............................................................................. 910
Operation .......................................................................................................................... 911
18.4.1
Transfer Clock .................................................................................................. 911
18.4.2
Relationship of Clock Phase, Polarity, and Data .............................................. 911
18.4.3
Relationship between Data Input/Output Pins and Shift Register .................... 912
18.4.4
Communication Modes and Pin Functions ....................................................... 914
18.4.5
SSU Mode......................................................................................................... 916
18.4.6
SCS Pin Control and Conflict Error.................................................................. 926
18.4.7
Clock Synchronous Communication Mode ...................................................... 928
SSU Interrupt Sources and DTC or DMAC...................................................................... 935
Usage Notes ...................................................................................................................... 936
18.6.1
Module Standby Mode Setting ......................................................................... 936
18.6.2
Access to SSTDR and SSRDR Registers ......................................................... 936
18.6.3
Continuous Transmission/Reception in SSU Slave Mode................................ 936
18.6.4
Note for Reception Operations in SSU Slave Mode ......................................... 936
18.6.5 Note on Master Transmission and Master Reception Operations in SSU
Mode ................................................................................................................. 937
18.6.6
Note on DTC Transfers..................................................................................... 937
Section 19 I2C Bus Interface 3 (IIC3)................................................................ 939
19.1
19.2
19.3
19.4
Features............................................................................................................................. 939
Input/Output Pins.............................................................................................................. 941
Register Descriptions........................................................................................................ 942
19.3.1
I2C Bus Control Register 1 (ICCR1)................................................................. 943
19.3.2
I2C Bus Control Register 2 (ICCR2)................................................................. 946
19.3.3
I2C Bus Mode Register (ICMR)........................................................................ 948
19.3.4
I2C Bus Interrupt Enable Register (ICIER)....................................................... 950
19.3.5
I2C Bus Status Register (ICSR)......................................................................... 952
19.3.6
Slave Address Register (SAR).......................................................................... 955
19.3.7
I2C Bus Transmit Data Register (ICDRT) ........................................................ 955
19.3.8
I2C Bus Receive Data Register (ICDRR).......................................................... 956
19.3.9
I2C Bus Shift Register (ICDRS)........................................................................ 956
19.3.10 NF2CYC Register (NF2CYC).......................................................................... 957
Operation .......................................................................................................................... 958
19.4.1
I2C Bus Format.................................................................................................. 958
19.4.2
Master Transmit Operation............................................................................... 959
19.4.3
Master Receive Operation ................................................................................ 961
19.4.4
Slave Transmit Operation ................................................................................. 963
19.4.5
Slave Receive Operation................................................................................... 966
19.4.6
Clocked Synchronous Serial Format ................................................................ 968
Page xxii of xxx
19.5
19.6
19.7
19.8
19.4.7
Noise Filter ....................................................................................................... 972
19.4.8
Using the IICRST Bit to Reset I2C Bus Interface 3 .......................................... 973
19.4.9
Example of Use................................................................................................. 974
Interrupt Requests ............................................................................................................. 978
Data Transfer Using DTC................................................................................................. 979
Bit Synchronous Circuit.................................................................................................... 980
Usage Notes ...................................................................................................................... 983
19.8.1
Setting for Multi-Master Operation .................................................................. 983
19.8.2
Note on Master Receive Mode.......................................................................... 983
19.8.3
Note on Setting ACKBT in Master Receive Mode........................................... 983
19.8.4
Note on the States of Bits MST and TRN when Arbitration Is Lost................. 983
19.8.5
Access to ICE and IICRST Bits during I2C Bus Operations ............................. 984
19.8.6
Using the IICRST Bit to Initialize the Registers............................................... 985
19.8.7
Operation of I2C Bus Interface 3 while ICE = 0 ............................................... 985
19.8.8
Note on Master Transmit Mode ........................................................................ 985
Section 20 A/D Converter (ADC)......................................................................987
20.1
20.2
20.3
20.4
20.5
20.6
20.7
Features............................................................................................................................. 987
Input/Output Pins.............................................................................................................. 990
Register Descriptions........................................................................................................ 991
20.3.1
A/D Control Registers 0 to 2 (ADCR_0 to ADCR_2)...................................... 993
20.3.2
A/D Status Registers 0 to 2 (ADSR_0 to ADSR_2) ......................................... 996
20.3.3
A/D Start Trigger Select Registers 0 to 2 (ADSTRGR_0 to ADSTRGR_2).... 997
20.3.4 A/D Analog Input Channel Select Registers 0 to 2
(ADANSR_0 to ADANSR_2) .......................................................................... 999
20.3.5
A/D Bypass Control Registers 0 to 2 (ADBYPSCR_0 to ADBYPSCR_2) ... 1000
20.3.6
A/D Data Registers 0 to 11 (ADDR0 to ADDR11) ........................................ 1001
Operation ........................................................................................................................ 1002
20.4.1
Single-Cycle Scan Mode................................................................................. 1003
20.4.2
Continuous Scan Mode ................................................................................... 1008
20.4.3
Input Sampling and A/D Conversion Time .................................................... 1013
20.4.4
A/D Converter Activation by MTU2 and MTU2S ......................................... 1016
20.4.5
External Trigger Input Timing........................................................................ 1017
20.4.6
Example of ADDR Auto-Clear Function........................................................ 1018
Interrupt Sources and DMAC or DTC Transfer Requests .............................................. 1020
Definitions of A/D Conversion Accuracy....................................................................... 1021
Usage Notes .................................................................................................................... 1023
20.7.1
Analog Input Voltage Range .......................................................................... 1023
20.7.2
Relationship between AVcc, AVss and Vcc, Vss........................................... 1023
20.7.3
Range of AVREF Pin Settings........................................................................ 1023
Page xxiii of xxx
20.7.4
20.7.5
20.7.6
20.7.7
20.7.8
Notes on Board Design ................................................................................... 1023
Notes on Noise Countermeasures ................................................................... 1024
Permissible Signal Source Impedance ............................................................ 1024
Influences on Absolute Precision.................................................................... 1025
Notes when Two A/D Modules Run Simultaneously ..................................... 1025
Section 21 D/A Converter (DAC) (SH7286 Only) ......................................... 1029
21.1
21.2
21.3
21.4
21.5
Features........................................................................................................................... 1029
Input/Output Pins............................................................................................................ 1030
Register Descriptions...................................................................................................... 1031
21.3.1
D/A Data Registers 0 and 1 (DADR0 and DADR1)....................................... 1031
21.3.2
D/A Control Register (DACR) ....................................................................... 1032
Operation ........................................................................................................................ 1034
Usage Notes .................................................................................................................... 1035
21.5.1
Module Standby Mode Setting ....................................................................... 1035
21.5.2
D/A Output Hold Function in Software Standby Mode.................................. 1035
21.5.3
Setting Analog Input Voltage ......................................................................... 1035
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only) ................ 1037
22.1
22.2
22.3
22.4
22.5
22.6
22.7
Summary......................................................................................................................... 1037
22.1.1
Overview ........................................................................................................ 1037
22.1.2
Scope .............................................................................................................. 1037
22.1.3
Audience......................................................................................................... 1037
22.1.4
References....................................................................................................... 1038
22.1.5
Features........................................................................................................... 1038
Architecture .................................................................................................................... 1039
Programming Model - Overview .................................................................................... 1042
22.3.1
Memory Map .................................................................................................. 1042
22.3.2
Mailbox Structure ........................................................................................... 1043
22.3.3
RCAN-ET Control Registers .......................................................................... 1051
22.3.4
RCAN-ET Mailbox Registers......................................................................... 1070
Application Note............................................................................................................. 1080
22.4.1
Test Mode Settings ......................................................................................... 1080
22.4.2
Configuration of RCAN-ET ........................................................................... 1081
22.4.3
Message Transmission Sequence.................................................................... 1087
22.4.4
Message Receive Sequence ............................................................................ 1090
22.4.5
Reconfiguration of Mailbox............................................................................ 1092
Interrupt Sources............................................................................................................. 1094
DTC Interface ................................................................................................................. 1095
DMAC Interface ............................................................................................................. 1096
Page xxiv of xxx
22.8
22.9
CAN Bus Interface.......................................................................................................... 1097
Usage Notes .................................................................................................................... 1098
22.9.1
Module Standby Mode.................................................................................... 1098
22.9.2
Reset ............................................................................................................... 1098
22.9.3
CAN Sleep Mode............................................................................................ 1098
22.9.4
Register Access............................................................................................... 1098
22.9.5
Interrupts......................................................................................................... 1099
Section 23 Pin Function Controller (PFC).......................................................1101
23.1
23.2
23.3
Register Descriptions...................................................................................................... 1126
23.1.1
Port A I/O Registers H and L (PAIORH and PAIORL) ................................. 1128
23.1.2
Port A Control Registers H2, L1 to L4 (PACRH2, PACRL1 to PACRL4).... 1129
23.1.3 Port A Pull-Up MOS Control Registers H and L
(PAPCRH and PAPCRL)................................................................................ 1156
23.1.4
Port B I/O Registers H and L (PBIORH and PBIORL).................................. 1161
23.1.5 Port B Control Registers H1 and L1 to L4
(PBCRH1 and PBCRL1 to PBCRL4)............................................................. 1162
23.1.6
Port B Pull-Up MOS Control Register H and L (PBPCRH and PBPCRL) .... 1186
23.1.7
Port C I/O Register L (PCIORL) .................................................................... 1190
23.1.8
Port C Control Register L1 to L4 (PCCRL1 to PCCRL4) .............................. 1190
23.1.9
Port C Pull-Up MOS Control Register L (PCPCRL)...................................... 1208
23.1.10 Port D I/O Registers H and L (PDIORH and PDIORL) ................................. 1209
23.1.11 Port D Control Registers H1 to H4 and L1 to L4
(PDCRH1 to PDCRH4 and PDCRL1 to PDCRL4) ........................................ 1209
23.1.12 Port D Pull-Up MOS Control Register H and L (PDPCRH and PDPCRL) ... 1255
23.1.13 Port E I/O Register L (PEIORL)..................................................................... 1259
23.1.14 Port E Control Register L1 to L4 (PECRL1 to PECRL4)............................... 1260
23.1.15 Port E Pull-Up MOS Control Register L (PEPCRL) ...................................... 1286
23.1.16 Large Current Port Control Register (HCPCR) .............................................. 1287
23.1.17 IRQOUT Function Control Register (IFCR) .................................................. 1289
Pull-Up MOS Control by Pin Function........................................................................... 1290
Usage Notes .................................................................................................................... 1293
Section 24 I/O Ports .........................................................................................1295
24.1
24.2
Port A.............................................................................................................................. 1295
24.1.1
Register Descriptions ...................................................................................... 1297
24.1.2
Port A Data Registers H and L (PADRH and PADRL).................................. 1298
24.1.3
Port A Port Registers H and L (PAPRH and PAPRL).................................... 1303
Port B .............................................................................................................................. 1308
24.2.1
Register Descriptions ...................................................................................... 1309
Page xxv of xxx
24.3
24.4
24.5
24.6
24.7
24.2.2
Port B Data Registers H and L (PBDRH and PBDRL) .................................. 1310
24.2.3
Port B Port Registers H and L (PBPRH and PBPRL) .................................... 1316
Port C.............................................................................................................................. 1320
24.3.1
Register Descriptions...................................................................................... 1321
24.3.2
Port C Data Register L (PCDRL) ................................................................... 1322
24.3.3
Port C Port Register L (PCPRL)..................................................................... 1324
Port D.............................................................................................................................. 1325
24.4.1
Register Descriptions...................................................................................... 1328
24.4.2
Port D Data Registers H and L (PDDRH and PDDRL).................................. 1328
24.4.3
Port D Port Registers H and L (PDPRH and PDPRL).................................... 1332
Port E .............................................................................................................................. 1336
24.5.1
Register Descriptions...................................................................................... 1338
24.5.2
Port E Data Register L (PEDRL).................................................................... 1338
24.5.3
Port E Port Register L (PEPRL) ..................................................................... 1340
Port F .............................................................................................................................. 1341
24.6.1
Register Descriptions...................................................................................... 1342
24.6.2
Port F Data Register L (PFDRL) .................................................................... 1342
Usage Notes .................................................................................................................... 1345
24.7.1
Handling of Unused Pins ................................................................................ 1345
Section 25 USB Function Module................................................................... 1347
25.1
25.2
25.3
Features........................................................................................................................... 1347
25.1.1
Block Diagram................................................................................................ 1348
Pin Configuration............................................................................................................ 1349
Register Descriptions...................................................................................................... 1350
25.3.1
USB Interrupt Flag Register 0 (USBIFR0)..................................................... 1351
25.3.2
USB Interrupt Flag Register 1 (USBIFR1)..................................................... 1353
25.3.3
USB Interrupt Select Register 0 (USBISR0) .................................................. 1354
25.3.4
USB Interrupt Select Register 1 (USBISR1) .................................................. 1355
25.3.5
USB Interrupt Enable Register 0 (USBIER0)................................................. 1356
25.3.6
USB Interrupt Enable Register 1 (USBIER1)................................................. 1357
25.3.7
USBEP0i Data Register (USBEPDR0i) ......................................................... 1358
25.3.8
USBEP0o Data Register (USBEPDR0o)........................................................ 1358
25.3.9
USBEP0s Data Register (USBEPDR0s)......................................................... 1359
25.3.10 USBEP1 Data Register (USBEPDR1)............................................................ 1360
25.3.11 USBEP2 Data Register (USBEPDR2)............................................................ 1361
25.3.12 USBEP3 Data Register (USBEPDR3)............................................................ 1362
25.3.13 USBEP0o Receive Data Size Register (USBEPSZ0o) ................................... 1362
25.3.14 USBEP1 Receive Data Size Register (USBEPSZ1)....................................... 1363
25.3.15 USB Trigger Register (USBTRG) .................................................................. 1364
Page xxvi of xxx
25.3.16 USB Data Status Register (USBDASTS) ....................................................... 1366
25.3.17 USBFIFO Clear Register (USBFCLR)........................................................... 1367
25.3.18 USBDMA Transfer Setting Register (USBDMAR) ....................................... 1368
25.3.19 USB Endpoint Stall Register (USBEPSTL) ................................................... 1370
25.4 Interrupt Sources............................................................................................................. 1371
25.5 Operation ........................................................................................................................ 1372
25.5.1
Initial Settings ................................................................................................. 1372
25.5.2
Cable Connection............................................................................................ 1373
25.5.3
Cable Disconnection ....................................................................................... 1374
25.5.4
Control Transfer.............................................................................................. 1375
25.5.5
EP1 Bulk-OUT Transfer (Dual FIFOs)........................................................... 1381
25.5.6
EP2 Bulk-IN Transfer (Dual FIFOs) .............................................................. 1382
25.5.7
EP3 Interrupt-IN Transfer............................................................................... 1384
25.6 Processing of USB Standard Commands and Class/Vendor Commands ....................... 1385
25.6.1
Processing of Commands Transmitted by Control Transfer ........................... 1385
25.7 Stall Operations............................................................................................................... 1386
25.7.1
Forcible Stall by Application .......................................................................... 1386
25.7.2
Automatic Stall by USB Function Module ..................................................... 1388
25.8 DMA Transfer................................................................................................................. 1389
25.8.1
DMA Transfer for Endpoint 1 ........................................................................ 1389
25.8.2
DMA Transfer for Endpoint 2 ........................................................................ 1392
25.9 DTC Transfer.................................................................................................................. 1395
25.9.1
DTC Transfer for Endpoint 1.......................................................................... 1395
25.9.2
DTC Transfer for Endpoint 2.......................................................................... 1398
25.10 Example of USB External Circuitry ............................................................................... 1401
25.11 Notes on Usage ............................................................................................................... 1402
25.11.1 Receiving Setup Data...................................................................................... 1402
25.11.2 Clearing FIFO ................................................................................................. 1402
25.11.3 Overreading or Overwriting Data Register ..................................................... 1402
25.11.4 Assigning Interrupt Source for EP0 ................................................................ 1403
25.11.5 Clearing FIFO when Setting DMA/DTC Transfer ......................................... 1403
25.11.6 Manual Reset for DMA/DTC Transfer ........................................................... 1403
25.11.7 USB Clock ...................................................................................................... 1403
25.11.8 Using TR Interrupt.......................................................................................... 1403
25.11.9 Handling of Unused USB Pins ....................................................................... 1404
Section 26 Flash Memory (ROM) ...................................................................1405
26.1
26.2
Features........................................................................................................................... 1405
Overview......................................................................................................................... 1407
26.2.1
Block Diagram................................................................................................ 1407
Page xxvii of xxx
26.3
26.4
26.5
26.6
26.7
26.8
26.9
26.2.2
Operating Mode .............................................................................................. 1408
26.2.3
Mode Comparison .......................................................................................... 1409
26.2.4
Flash Memory Configuration.......................................................................... 1411
26.2.5
Block Division ................................................................................................ 1412
26.2.6
Programming/Erasing Interface ...................................................................... 1413
Input/Output Pins............................................................................................................ 1415
Register Descriptions...................................................................................................... 1416
26.4.1
Registers ......................................................................................................... 1416
26.4.2
Programming/Erasing Interface Registers ...................................................... 1418
26.4.3
Programming/Erasing Interface Parameters ................................................... 1426
On-Board Programming Mode ....................................................................................... 1442
26.5.1
Boot Mode ...................................................................................................... 1442
26.5.2
USB Boot Mode (SH7286 and SH7285) ........................................................ 1446
26.5.3
User Program Mode........................................................................................ 1449
26.5.4
User Boot Mode (SH7286 and SH7285) ........................................................ 1461
Protection........................................................................................................................ 1466
26.6.1
Hardware Protection ....................................................................................... 1466
26.6.2
Software Protection......................................................................................... 1467
26.6.3
Error Protection .............................................................................................. 1467
Usage Notes .................................................................................................................... 1469
26.7.1
Switching between User MAT and User Boot MAT...................................... 1469
26.7.2
Interrupts during Programming/Erasing ......................................................... 1470
26.7.3
Other Notes..................................................................................................... 1472
Supplementary Information ............................................................................................ 1474
26.8.1 Specifications of the Standard Serial Communications Interface in Boot
Mode ............................................................................................................... 1474
26.8.2
Areas for Storage of the Procedural Program and Data for Programming...... 1505
Programmer Mode .......................................................................................................... 1512
Section 27 On-Chip RAM ............................................................................... 1513
27.1
27.2
Features........................................................................................................................... 1513
Usage Notes .................................................................................................................... 1515
27.2.1
Page Conflict .................................................................................................. 1515
27.2.2
RAME and RAMWE Bits .............................................................................. 1515
Section 28 Power-Down Modes...................................................................... 1517
28.1
28.2
Features........................................................................................................................... 1517
28.1.1
Power-Down Modes ....................................................................................... 1517
28.1.2
Reset ............................................................................................................... 1518
Input/Output Pins............................................................................................................ 1519
Page xxviii of xxx
28.3
28.4
28.5
Register Descriptions...................................................................................................... 1520
28.3.1
Standby Control Register (STBCR)................................................................ 1521
28.3.2
Standby Control Register 2 (STBCR2)........................................................... 1522
28.3.3
Standby Control Register 3 (STBCR3)........................................................... 1523
28.3.4
Standby Control Register 4 (STBCR4)........................................................... 1525
28.3.5
Standby Control Register 5 (STBCR5)........................................................... 1526
28.3.6
Standby Control Register 6 (STBCR6)........................................................... 1527
28.3.7
System Control Register 1 (SYSCR1) ............................................................ 1529
28.3.8
System Control Register 2 (SYSCR2) ............................................................ 1531
Operation ........................................................................................................................ 1533
28.4.1
Sleep Mode ..................................................................................................... 1533
28.4.2
Software Standby Mode.................................................................................. 1534
28.4.3
Module Standby Function............................................................................... 1536
Usage Notes .................................................................................................................... 1537
28.5.1
Current Consumption during Oscillation Settling Time ................................. 1537
28.5.2
Notes on Writing to Registers......................................................................... 1537
28.5.3 Notes on Canceling Software Standby Mode with an IRQx Interrupt
Request............................................................................................................ 1537
Section 29 User Debugging Interface (H-UDI) ...............................................1539
29.1
29.2
29.3
29.4
29.5
Features........................................................................................................................... 1539
Input/Output Pins............................................................................................................ 1540
Register Descriptions...................................................................................................... 1541
29.3.1
Bypass Register (SDBPR) .............................................................................. 1541
29.3.2
Instruction Register (SDIR) ............................................................................ 1541
Operation ........................................................................................................................ 1543
29.4.1
TAP Controller ............................................................................................... 1543
29.4.2
Reset Configuration ........................................................................................ 1544
29.4.3
TDO Output Timing ....................................................................................... 1544
29.4.4
H-UDI Reset ................................................................................................... 1545
29.4.5
H-UDI Interrupt .............................................................................................. 1545
Usage Notes .................................................................................................................... 1546
Section 30 List of Registers .............................................................................1547
30.1
30.2
30.3
Register Addresses
(by functional module, in order of the corresponding section numbers) ........................ 1548
Register Bits.................................................................................................................... 1572
Register States in Each Operating Mode ........................................................................ 1603
Page xxix of xxx
Section 31 Electrical Characteristics ............................................................... 1621
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.8
Absolute Maximum Ratings ........................................................................................... 1621
DC Characteristics .......................................................................................................... 1622
AC Characteristics .......................................................................................................... 1626
31.3.1
Clock Timing .................................................................................................. 1627
31.3.2
Control Signal Timing .................................................................................... 1630
31.3.3
Bus Timing ..................................................................................................... 1633
31.3.4
UBC Trigger Timing ...................................................................................... 1663
31.3.5
DMAC Module Timing .................................................................................. 1664
31.3.6
Multi Function Timer Pulse Unit 2 (MTU2) Timing...................................... 1665
31.3.7
Multi Function Timer Pulse Unit 2S (MTU2S) Timing ................................. 1666
31.3.8
POE2 Module Timing..................................................................................... 1667
31.3.9
Watchdog Timer Timing ................................................................................ 1668
31.3.10 SCI Module Timing ........................................................................................ 1669
31.3.11 SCIF Module Timing...................................................................................... 1671
31.3.12 Serial Communication Unit (SSU) Timing..................................................... 1673
31.3.13 Controller Area Network (RCAN-ET) Timing............................................... 1676
31.3.14 IIC3 Module Timing....................................................................................... 1677
31.3.15 A/D Trigger Input Timing .............................................................................. 1678
31.3.16 I/O Port Timing............................................................................................... 1679
31.3.17 H-UDI Related Pin Timing............................................................................. 1680
31.3.18 AC Characteristics Measurement Conditions ................................................. 1682
A/D Converter Characteristics........................................................................................ 1683
D/A Converter Characteristics........................................................................................ 1684
USB Characteristics........................................................................................................ 1685
Flash Memory Characteristics ........................................................................................ 1687
Usage Notes .................................................................................................................... 1688
31.8.1
Notes on Connecting Capacitors..................................................................... 1688
Appendix ........................................................................................................... 1689
A.
B.
C.
Pin States ........................................................................................................................ 1689
Product Code Lineup ...................................................................................................... 1709
Package Dimensions ....................................................................................................... 1710
Main Revisions and Additions in this Edition................................................... 1715
Index ................................................................................................................. 1769
Page xxx of xxx
SH7280 Group, SH7243 Group
Section 1 Overview
Section 1 Overview
1.1
SH7286, SH7285, and SH7243 Features
This LSI is a single-chip RISC microprocessor that integrates a Renesas original RISC CPU core
with peripheral functions required for system configuration.
The CPU in this LSI has a RISC-type (Reduced Instruction Set Computer) instruction set and uses
a superscalar architecture and a Harvard architecture, which greatly improves instruction
execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power.
With this CPU, it has become possible to assemble low-cost, high-performance, and highfunctioning systems, even for applications that were previously impossible with microprocessors,
such as realtime control, which demands high speeds.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as a large-capacity ROM, a ROM cache, a RAM, a direct memory access controller
(DMAC), a data transfer controller (DTC), multi-function timer pulse units 2 (MTU2 and
MTU2S), a serial communication interface with FIFO (SCIF), a serial communication interface
(SCI), a synchronous serial communication interface (SSU), an A/D converter, a D/A converter,
an interrupt controller (INTC), I/O ports, I2C bus interface 3 (IIC3), a universal serial bus (USB),
and a controller area network (RCAN-ET).
This LSI also provides an external memory access support function to enable direct connection to
various memory devices or peripheral LSIs.
These on-chip functions significantly reduce costs of designing and manufacturing application
systems.
The features of this LSI are listed in table 1.1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Table 1.1
SH7286, SH7285, and SH7243 Features
Items
Specification
CPU
•
Renesas original SuperH architecture
•
Compatible with SH-1 and SH-2 at object code level
•
32-bit internal data bus
•
Support of an abundant register-set
⎯ Sixteen 32-bit general registers
⎯ Four 32-bit control registers
⎯ Four 32-bit system registers
⎯ Register bank for high-speed response to interrupts
•
RISC-type instruction set (upward compatible with SH series)
⎯ Instruction length: 16-bit fixed-length basic instructions for
improved code efficiency and 32-bit instructions for high
performance and usability
⎯ Load/store architecture
⎯ Delayed branch instructions
⎯ Instruction set based on C language
Operating modes
•
Superscalar architecture to execute two instructions at one time
•
Instruction execution time: Up to two instructions/cycle
•
Address space: 4 Gbytes
•
Internal multiplier
•
Five-stage pipeline
•
Harvard architecture
•
Operating modes
Extended ROM enabled mode
Single-chip mode
•
Processing states
Program execution state
Exception handling state
Bus mastership release state
•
Power-down modes
Sleep mode
Software standby mode
Module standby mode
Page 2 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Items
Specification
ROM cache
•
Instruction/data separation system
•
Instruction prefetch cache: Full/set associative
•
Instruction prefetch miss cache: Full/set associative
•
Data cache: Full/set associative
•
Line size: 16 bytes
•
Hardware prefetch function (continuous/branch prefetch)
•
Nine external interrupt pins (NMI and IRQ7 to IRQ0)
•
On-chip peripheral interrupts: Priority level set for each module
•
16 priority levels available
•
Register bank enabling fast register saving and restoring in interrupt
processing
•
Address space divided into eight areas (0 to 7), each a maximum of 64
Mbytes
•
External bus: 8, 16, or 32 bits (32-bit bus available only in SH7286)
•
The following features settable for each area independently
Interrupt controller
(INTC)
Bus state controller
(BSC)
⎯ Supports both big endian and little endian for data access
⎯ Bus size (8, 16, or 32 bits): Available sizes depend on the area.
⎯ Number of access wait cycles (different wait cycles can be
specified for read and write access cycles in some areas)
⎯ Idle wait cycle insertion (between same area access cycles or
different area access cycles)
⎯ Direct connection to SRAM, SRAM interface with byte selection,
SDRAM burst ROM (clock synchronous or asynchronous) is
achieved by specifying the memory to be connected to each area.
Address/data multiplex I/O (MPX-I/O) interface is also supported.
•
SDRAM refresh
Auto refresh or self refresh mode selectable
•
Direct memory access •
controller (DMAC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SDRAM burst access
Eight channels; external request available for four (SH7286) and two
(SH7285 and SH7243) of them
•
Can be activated by on-chip peripheral modules
•
Burst mode and cycle steal mode
•
Intermittent mode available (16 and 64 cycles supported)
•
Transfer information can be automatically reloaded
Page 3 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Items
Specification
Data transfer
controller (DTC)
•
Data transfer activated by an on-chip peripheral module interrupt can
be done independently of the CPU transfer.
•
Transfer mode selectable for each interrupt source (transfer mode is
specified in memory)
•
Multiple data transfer enabled for one activation source
•
Various transfer modes
Normal mode, repeat mode, or block transfer mode can be selected.
•
Data transfer size can be specified as byte, word, or longword
•
The interrupt that activated the DTC can be issued to the CPU.
A CPU interrupt can be requested after one data transfer completion.
Clock pulse
generator (CPG)
•
A CPU interrupt can be requested after all specified data transfer
completion.
•
Clock mode: Input clock can be selected from external input (EXTAL)
or crystal resonator
•
Input clock can be multiplied by 8 (max.) by the internal PLL circuit
•
Five types of clocks generated:
⎯ CPU clock: Maximum 100 MHz
⎯ Bus clock: Maximum 50 MHz
⎯ Peripheral clock: Maximum 50 MHz
⎯ Timer clock: Maximum 100 MHz
⎯ AD clock: Maximum 50 MHz
Watchdog timer
(WDT)
•
On-chip one-channel watchdog timer
•
A counter overflow can reset the LSI
Power-down modes
•
Three power-down modes provided to reduce the current consumption
in this LSI
⎯ Sleep mode
⎯ Software standby mode
⎯ Module standby mode
Page 4 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Items
Specification
Multi-function timer
pulse unit 2 (MTU2)
•
Maximum 16 lines of pulse input/output and 3 lines of pulse input
based on six channels of 16-bit timers
•
21 output compare and input capture registers
•
Input capture function
•
Pulse output modes
Toggle, PWM, and complementary PWM
•
Synchronization of multiple counters
•
Complementary PWM output mode
⎯ Non-overlapping waveforms output for 3-phase inverter control
⎯ Automatic dead time setting
⎯ 0% to 100% PWM duty value specifiable
⎯ A/D conversion delaying function
⎯ Interrupt skipping at crest or trough
•
Reset-synchronized PWM mode
Three-phase PWM waveforms in positive and negative phases can be
output with a required duty value
•
Phase counting mode
Two-phase encoder pulse counting available
Multi-function timer
•
pulse unit 2S (MTU2S)
•
Port output enable 2
(POE2)
•
Compare match timer •
(CMT)
•
Serial communication
interface (SCI)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Subset of MTU2, included in channels 3 to 5
Operating at 100 MHz max.
High-impedance control of high-current pins at a falling edge or lowlevel input on the POE pin
Two-channel 16-bit counters
Four types of clock can be selected (Pφ/8, Pφ/32, Pφ/128, and Pφ/512)
•
DMA transfer request or interrupt request can be issued when a
compare match occurs
•
Four channels (SH7285 and SH7286)
Two channels (SH7243)
•
Clocked synchronous or asynchronous mode selectable
•
Simultaneous transmission and reception (full-duplex communication)
supported
•
Dedicated baud rate generator
Page 5 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Items
Specification
Serial communication
interface with FIFO
(SCIF)
•
One channel
•
Clocked synchronous or asynchronous mode selectable
•
Simultaneous transmission and reception (full-duplex communication)
supported
•
Dedicated baud rate generator
•
Separate 16-byte FIFO registers for transmission and reception
•
One channel
•
Master mode or slave mode selectable
•
Standard mode or bidirectional mode selectable
•
Transmit/receive data length can be selected from 8, 16, and 32 bits.
•
Simultaneous transmission and reception (full-duplex communication)
supported
Synchronous serial
communication unit
(SSU)
(only in SH7285 and
SH7286)
•
Consecutive serial communication
Universal serial bus
(USB)
•
USB 2.0 full-speed mode (12 Mbps) supported
•
Internal bus transceiver available
(only in SH7285 and
SH7286)
•
Standard commands automatically processed by hardware
•
Three transfer modes (control transfer, balk transfer, and interrupt
transfer)
•
16 types of interrupt sources available
•
DMA transfer interface
•
CAN version: Bosch 2.0B active is supported
•
Buffer size: 15 buffers for transmission/reception and one buffer for
reception only
•
One channel
•
One channel
•
Master mode and slave mode supported
•
Input or output can be selected for each bit
Controller area
network (RCAN-ET)
(only in SH7286)
2
I C bus interface 3
(IIC3)
(only in SH7285 and
SH7286)
I/O ports
Page 6 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Items
Specification
A/D converter
•
Three modules (SH7286)
Two modules (SH7285 and SH7243)
•
12-bit resolution
•
Eight input channels (SH7285 and SH7243) and twelve input channels
(SH7286)
•
Sampling can be carried out simultaneously on three channels.
•
A/D conversion request by the external trigger or timer trigger
D/A converter
•
8-bit resolution
(only in SH7286)
•
Two output channels
ASE break controller
(ABC)
•
Ten break channels
•
The cycle of the internal bus can be set as break conditions
User break controller
(UBC)
•
Four break channels
•
Addresses, data values, type of access, and data size can all be set as
break conditions
User debugging
interface (H-UDI)
•
E10A emulator support
•
JTAG-standard pin assignment
•
Realtime branch trace
•
Six input/output pins
•
Branch source address/destination address trace
•
Window data trace
•
Full trace
Advanced user
debugger (AUD)
All trace data can be output by interrupting CPU operation
•
Realtime trace
Trace data can be output within the range where CPU operation is not
interrupted
On-chip ROM
•
256 Kbytes, 512 Kbytes, 768 Kbytes, or 1 Mbyte
On-chip RAM
•
Four pages
•
32 Kbytes (SH7286, SH7285)
•
24 Kbytes (SH7286, SH7285)
•
12 Kbytes (SH7243)
•
8 Kbytes (SH7243)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 7 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Items
Specification
Power supply voltage
•
VCC: 3.0 to 5.5 V, AVCC: 4.5 to 5.5 V
DrVCC: 3.0 to 3.6 V (when USB is used)
3.0 to 5.5 V (when USB is not used)
Packages
•
LQFP2020-144 (0.5 pitch): R5F72856, R5F72855
•
LQFP2424-176 (0.5 pitch): R5F72867, R5F72866, R5F72865
•
LQFP2020-176 (0.4 pitch): R5F72867, R5F72866, R5F72865
•
LQFP1414-100 (0.5 pitch): R5F72434, R5F72433
Page 8 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
1.2
Section 1 Overview
Block Diagram
SH-2A
CPU core
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
On-chip ROM
Internal
bus controller
CPU bus
(C bus)
(I clock)
User break
controller (UBC)
On-chip RAM
Internal bus (B clock) (I bus)
Bus state
controller
(BSC)
Peripheral
bus controller
Data transfer
controller
(DTC)
Direct memory
access controller
(DMAC)
Peripheral bus (P clock) (P bus)
Pin function
controller
(PFC)
I/O
ports
Multi-function
timer pulse
unit 2S
(MTU2S)
Multi-function
timer pulse
unit 2
(MTU2)
Watchdog
timer
(WDT)
User debugging
interface
(H-UDI)
Interrupt
controller
(INTC)
Clock pulse
generator
(CPG)
Power-down
mode
control
Compare
match
timer
(CMT)
12-bit A/D
converter
(ADC)
Serial
communication
interface
(SCI)
Port output
enable 2
(POE2)
Serial
communication
interface
with FIFO
(SCIF)
Figure 1.1 Block Diagram (SH7243)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 9 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
SH-2A
CPU core
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
Internal
bus controller
On-chip ROM
CPU bus
(C bus)
(I clock)
User break
controller (UBC)
On-chip RAM
Internal bus (B clock) (I bus)
Bus state
controller
(BSC)
Data transfer
controller
(DTC)
Peripheral
bus controller
Direct memory
access controller
(DMAC)
Peripheral bus (P clock) (P bus)
Pin function
controller
(PFC)
D/A
converter
(DAC) *
I/O
ports
Multi-function
timer pulse
unit 2S
(MTU2S)
Controller
area network
(RCAN-ET) *
Multi-function
timer pulse
unit 2
(MTU2)
I2C bus
interface 3
(IIC3)
Watchdog
timer
(WDT)
Universal
serial bus
(USB)
12-bit A/D
converter
(ADC)
User debugging
interface
(H-UDI)
Port output
enable 2
(POE2)
Interrupt
controller
(INTC)
Compare
match
timer
(CMT)
Clock pulse
generator
(CPG)
Serial
communication
interface
(SCI)
Power-down
mode
control
Serial
communication
interface
with FIFO
(SCIF)
Synchronous
serial
communication
interface
(SSU)
Note: * Only in SH7286
Figure 1.2 Block Diagram (SH7285, SH7286)
Page 10 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
TDI
TDO
TCK
TMS
TRST
VCC
VSS
PB15/CKE/A21
PB16/CASL/A22/DACK3
PB17/CASU/A23/DREQ3
PB18/RASL/A24/DACK2
PB19/RASU/A25/DREQ2
VCC
VSS
USBXTAL
USBEXTAL
PB9/USPND
VBUS
DrVCC
USD+
USD-
DrVss
PB10
VSS
XTAL
VCC
EXTAL
NMI
VSS
PLLVSS
VCL
PE0/TIOC0A/TIOC4AS/DREQ0
PE1/TIOC0B/TIOC4BS/TEND0
PE2/TIOC0C/TIOC4CS/DREQ1
PE3/TIOC0D/TIOC4DS/TEND1
PE4/TIOC1A/RXD3
PE5/TIOC1B/TIOC3BS/TXD3
PE6/TIOC2A/TIOC3DS/SCK3
VCC
VSS
PB11/RXD2/CS6/CS0/IRQ0/CS2
PB12/TXD2/CS7/CS1/IRQ1/CS3
Pin Assignment
PB14/CRx0
PB13/CTx0
1.3
Section 1 Overview
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107106 105 104 103102 101 100 99 98 97 96 95 94 93 92 91 90 89
RES
133
88
VSS
FWE/ASEBRKAK/ASEBRK
134
135
87
86
VCC
ASEMD0
AVSS
136
85
PA7/CASL/TCLKB/SCK3
AVCC
137
84
PA8/TCLKC/TXD3/RDWR
PF0/AN0
138
83
PA9/CKE/TCLKD/RXD3
PF1/AN1
139
82
PA10/WRHL/DQMUL
PF2/AN2
140
81
PA11/WRHH/DQMUU/AH
PF3/AN3
141
80
PA12/WRH/DQMLU/POE8
PF4/AN4
142
79
PA13/WRL/DQMLL
PF5/AN5
143
144
78
77
PA14/RD
PF6/AN6
PF7/AN7
145
76
VSS
PA6/RASL/TCLKA
PA15/CK
AVREF
146
75
VCC
AVREFVSS
147
74
PD31/D31/TIOC3AS/ADTRG
AVCC
148
73
PD30/D30/TIOC3CS/IRQOUT
AVSS
149
72
PD29/D29/TIOC3BS
PF8/AN8
150
71
PD28/D28/TIOC3DS
PF9/AN9
151
70
PD27/D27/TIOC4AS/DACK0
PF10/AN10
152
69
PD26/D26/TIOC4BS/DACK1
PF11/AN11
153
68
PD25/D25/TIOC4CS/DREQ1
67
VSS
66
VCC
65
PD24/D24/DREQ0/TIOC4DS/AUDCK
AVREF
154
AVREFVSS
155
AVCC
156
AVSS
157
64
PD23/D23
DA0
158
63
PD22/D22/IRQ6/TIC5US/RXD4/AUDSYNC
DA1
159
62
PD21/D21/IRQ5/TIC5VS/TXD4
MD0
160
61
PD20/D20/IRQ4/TIC5WS/SCK4//POE8
LQFP-176
(Top view)
58
PD17/D17/IRQ1/POE5/SCK3/CS2/AUDATA1
PA1/TXD0/CS1
164
57
PD16/D16/IRQ0/CS3/AUDATA0
PA2/SCK0/SCS/CS2
165
56
VSS
PA3/RXD1/SSI/CS3
166
55
VCC
PA4/TXD1/SSO/CS4
167
54
VCL
168
53
PD15/D15/TIOC4DS
PE7/TIOC2B/RXD2/BS/UBCTRG
169
52
PD14/D14/TIOC4CS
VSS
170
51
PD13/D13/TIOC4BS
PE8/TIOC3A/SCK2
171
50
PD12/D12/TIOC4AS
PE10/TIOC3C/TXD2
172
49
PD11/D11/TIOC3DS
PE9/TIOC3B/FRAME
173
48
PD10/D10/TIOC3BS
PE11/TIOC3D
174
47
PD9/D9/TIOC3CS
PE12/TIOC4A
175
46
PD8/D8/TIOC3AS
PE13/TIOC4B/MRES
176
45
VSS
PD19/D19/IRQ3/POE7/RXD3/CS0/AUDATA3
VCC
PD7/D7/TIC5WS
PD6/D6/TIC5VS
PD5/D5/TIC5US
PD4/D4/TIC5W
PD3/D3/TIC5V
PD2/D2/TIC5U
PD1/D1
PD0/D0
VSS
VCC
PB8/A20/WAIT/POE8/IRQ7/SCK0
PB7/A19/BREQ/POE4/IRQ6/TXD0
PB6/A18/BACK/POE3/IRQ5/RXD0
PB3/SDA/POE2/IRQ1
PB2/SCL/POE1/IRQ0
PB1/A17/REFOUT/ADTRG/IRQ4
PB0/A16/IRQ3
PC15/A15/IRQ2
PC14/A14/IRQ1
PC13/A13/IRQ0
VSS
VCC
PC12/A12
PC11/A11
PC10/A10
PC9/A9
PC8/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
PC3/A3
8
PC2/A2
6 7
PC1/A1
4 5
PA22/CASU/CASL/TIC5V/POE4/IRQ2
2 3
VSS
1
VCC
PA5/SCK1/SSCK/CS5
PC0/A0/POE0
163
PA21/RASU/RASL/TIC5U/POE8/IRQ3
PD18/D18/IRQ2/POE6/TXD3/CS1/AUDATA2
PA0/RXD0/CS0
PA23/CKE/TIC5W/POE0/IRQ1/AH
59
VCL
60
162
PE14/DACK0/TIOC4C/AH
161
PE15/DACK1/TIOC4D/IRQOUT
MD1
WDTOVF
Figure 1.3 SH7286 Pin Assignment
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 11 of 1778
SH7280 Group, SH7243 Group
PD31/TIOC3AS/ADTRG
VCC
VSS
PA15/CK
PA14/RD
PA13/WRL/DQMLL
PA8/TCLKC/TXD3/RDWR
PA12/WRH/DQMLU/POE8
PA7/TCLKB/SCK3/CASL
PA9/TCLKD/RXD3/CKE
PA6/TCLKA/RASL
VSS
USBXTAL
USBEXTAL
PB9/USPND
VBUS
DrVCC
USD+
USD-
DrVSS
PB10
VSS
XTAL
VCC
EXTAL
NMI
VSS
PLLVSS
VCL
PE0/TIOC0A/TIOC4AS/DREQ0
PE1/TIOC0B/TIOC4BS/TEND0
PE2/TIOC0C/TIOC4CS/DREQ1
PE3/TIOC0D/TIOC4DS/TEND1
PE4/TIOC1A/RXD3
PE5/TIOC1B/TIOC3BS/TXD3
PE6/TIOC2A/TIOC3DS/SCK3
Section 1 Overview
108 107106 105 104 103102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VCC
109
72
PD30/TIOC3CS/IRQOUT
VSS
110
71
PD29/TIOC3BS
PB11/RXD2/CS6/CS2/CS0/IRQ0
111
70
PD28/TIOC3DS
PB12/TXD2/CS7/CS3/CS1/IRQ1
112
69
PD27/TIOC4AS/DACK0
RES
113
68
PD26/TIOC4BS/DACK1
FWE/ASEBRKAK/ASEBRK
114
67
PD25/TIOC4CS/DREQ1
ASEMD0
115
66
VSS
AVSS
116
65
VCC
AVCC
117
64
PD24/DREQ0/TIOC4DS/AUDCK
PF0/AN0
118
63
PD22/IRQ6/TIC5US/RXD4/AUDSYNC
PF1/AN1
119
62
PD21/IRQ5/TIC5VS/TXD4
PF2/AN2
120
61
PD20/IRQ4/TIC5WS/SCK4/POE8
PF3/AN3
121
60
PF4/AN4
122
59
PD18/IRQ2/POE6/TXD3/CS1/AUDATA2
PF5/AN5
123
58
PD17/IRQ1/POE5/SCK3/CS2/AUDATA1
PF6/AN6
124
57
PD16/IRQ0/CS3/AUDATA0
PF7/AN7
125
56
VSS
55
VCC
54
VCL
LQFP-144
PD19/IRQ3/POE7/RXD3/CS0/AUDATA3
AVREF
126
AVREFVSS
127
MD0
128
53
PD15/D15/TIOC4DS
MD1
129
52
PD14/D14/TIOC4CS
WDTOVF
130
51
PD13/D13/TIOC4BS
PA0/RXD0/CS0/TDI
131
50
PD12/D12/TIOC4AS
PA1/TXD0/CS1/TDO
132
49
PD11/D11/TIOC3DS
PA2/SCK0/SCS/CS2/TCK
133
48
PD10/D10/TIOC3BS
PA3/RXD1/SSI/CS3/TMS
134
47
PD9/D9/TIOC3CS
PA4/TXD1/SSO/CS4/TRST
135
46
PD8/D8/TIOC3AS
PA5/SCK1/SSCK/CS5
136
45
VSS
PE7/TIOC2B/RXD2/BS/UBCTRG
137
44
VCC
VSS
138
43
PD7/D7/TIC5WS
PE8/TIOC3A/SCK2
139
42
PD6/D6/TIC5VS
PE10/TIOC3C/TXD2
140
41
PD5/D5/TIC5US
PE9/TIOC3B
141
40
PD4/D4/TIC5W
PE11/TIOC3D
142
39
PD3/D3/TIC5V
PE12/TIOC4A
143
38
PD2/D2/TIC5U
PE13/TIOC4B/MRES
144
37
PD1/D1
PD0/D0
VSS
VCC
PB8/A20/WAIT/POE8/IRQ7/SCK0
PB7/A19/BREQ/POE4/IRQ6/TXD0
PB6/A18/BACK/POE3/IRQ5/RXD0
PB3/SDA/POE2/IRQ1
PB2/SCL/POE1/IRQ0
PB1/A17/REFOUT/ADTRG/IRQ4
PB0/A16/IRQ3
PC15/A15/IRQ2
PC14/A14/IRQ1
PC13/A13/IRQ0
VSS
VCC
PC12/A12
PC11/A11
PC10/A10
PC9/A9
PC8/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC0/A0/POE0
PC2/A2
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
PC1/A1
8
PA21/TIC5U/RASU/POE8/IRQ3/RASL
PA23/TIC5W/POE0/IRQ1/AH/CKE
PA22/TIC5V/CASU/POE4/IRQ2/CASL
6 7
VSS
PE14/DACK0/TIOC4C/AH
4 5
VCL
2 3
VCC
1
PE15/DACK1/TIOC4D/IRQOUT
(Top view)
Figure 1.4 SH7285 Pin Assignment
Page 12 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
PA14/RD
PA13/WRL/DQMLL
PA12/WRH/DQMLU/POE8
PA9/TCLKD/RXD3/CKE
PA8/TCLKC/TXD3/RDWR
PA7/TCLKB/SCK3/CASL
PA6/TCLKA/RASL
VSS
XTAL
VCC
EXTAL
NMI
PLLVSS
VCL
PE0/TIOC0A/TIOC4AS/DREQ0
PE1/TIOC0B/TIOC4BS/TEND0
PE2/TIOC0C/TIOC4CS/DREQ1
PE3/TIOC0D/TIOC4DS/TEND1
PE4/TIOC1A/RXD3
PB11/RXD2/CS6/CS0/IRQ0/CS2
PE5/TIOC1B/TIOC3BS/TXD3
PE6/TIOC2A/TIOC3DS/SCK3
PB12/TXD2/CS7/CS1/IRQ1/CS3
VCC
VSS
Section 1 Overview
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RES
76
50
PA15/CK
FWE/ASEBRKAK/ASEBRK
77
49
VSS
ASEMD0
78
48
PD15/D15/TIOC4DS
AVSS
79
47
PD14/D14/TIOC4CS
AVCC
80
46
PD13/D13/TIOC4BS
PF0/AN0
81
45
PD12/D12/TIOC4AS
PF1/AN1
82
44
PD11/D11/TIOC3DS
PF2/AN2
83
43
PD10/D10/TIOC3BS
PF3/AN3
84
42
PD9/D9/TIOC3CS
PF4/AN4
85
41
PD8/D8/TIOC3AS/AUDCK
PF5/AN5
86
40
VSS
PF6/AN6
87
39
VCC
PF7/AN7
88
38
PD7/D7/TIC5WS/AUDATA3
37
36
PD6/D6/TIC5VS/AUDATA2
LQFP-100
(Top view)
AVREF
89
AVREFVSS
90
MD0
91
35
PD4/D4/TIC5W/AUDATA0
MD1
PD5/D5/TIC5US/AUDATA1
92
34
PD3/D3/TIC5V/AUDSYNC
WDTOVF
93
33
PD2/D2/TIC5U
PE7/TIOC2B/RXD2/BS/UBCTRG
94
32
PD1/D1
PE8/TIOC3A/SCK2
PB7/A19/BREQ/POE4/IRQ6/TXD0
PE11/TIOC3D
98
99
28
27
PB6/A18/BACK/POE3/IRQ5/RXD0
PE12/TIOC4A
100
26
PB0/A16/IRQ3
PB1/A17/ADTRG/REFOUT/IRQ4
VSS
VCC
PC15/A15/IRQ2
PC14/A14/IRQ1
PC13/A13/IRQ0
PC12/A12
PC11/A11
PC10/A10
PC9/A9
VSS
PC8/A8
VCC
PC7/A7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PC6/A6
8
PC5/A5
6 7
PC4/A4/TRST
4 5
PC1/A1/TDO
2 3
VSS
1
VCC
PE13/TIOC4B/MRES
PC2/A2/TCK
29
PC3/A3/TMS
97
PC0/A0/POE0/TDI
PB8/A20/WAIT/POE8/IRQ7/SCK0
PE9/TIOC3B
VCL
PD0/D0
96
30
PE14/DACK0/TIOC4C
31
PE15/DACK1/TIOC4D/IRQOUT
95
PE10/TIOC3C/TXD2
Figure 1.5 SH7243 Pin Assignment
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 13 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
1.4
Pin Functions
Table 1.2 lists functions of each pin.
Table 1.2
Pin Functions
Classification
Symbol
I/O
Name
Function
Power supply
VCC
Input
Power supply
Power supply pins. All the VCC pins
must be connected to the system
power supply. This LSI does not
operate correctly if there is a pin left
open.
VSS
Input
Ground
Ground pins. All the VSS pins must be
connected to the system power supply
(0 V). This LSI does not operate
correctly if there is a pin left open.
VCL
Input
Internal stepdown power
supply
External capacitance pins for internal
step-down power supply. All the VCL
pins must be connected to VSS via a
0.47-μF capacitor (should be placed
close to the pins).
PLLVSS
Input
Ground for PLL Ground pin for the on-chip PLL
oscillator.
EXTAL
Input
External clock
XTAL
Output Crystal
Clock
USBEXTAL Input
Page 14 of 1778
Connected to a crystal resonator.
An external clock signal may also be
input to the EXTAL pin.
Connected to a crystal resonator.
Crystal for USB Connected to a resonator for the USB.
USBXTAL
Output Crystal for USB Connected to a resonator for the USB.
CK
Output System clock
Supplies the system clock to external
devices.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
Name
Function
Operating mode
control
MD1, MD0
Input
Mode set
Sets the operating mode. Do not
change the signal levels on these pins
during operation.
ASEMD0
Input
Debugging
mode
Enables the E10A-USB emulator
functions.
Input a high level to operate the LSI in
normal mode (not in debugging
mode). To operate it in debugging
mode, apply a low level to this pin on
the user system board.
System control
FWE
Input
Flash memory
write enable
Pin for flash memory. Flash memory
can be protected against writing or
erasure through this pin.
RES
Input
Power-on reset
This LSI enters the power-on reset
state when this signal goes low.
MRES
Input
Manual reset
This LSI enters the manual reset state
when this signal goes low.
WDTOVF
Output Watchdog timer
overflow
Outputs an overflow signal from the
WDT.
BREQ
Input
Bus-mastership
request
A low level is input to this pin when an
external device requests the release
of the bus mastership.
BACK
Output Bus-mastership
request
acknowledge
Indicates that the bus mastership has
been released to an external device.
Reception of the BACK signal informs
the device which has output the
BREQ signal that it has acquired the
bus.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 15 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
Name
Function
Interrupts
NMI
Input
Non-maskable
interrupt
Non-maskable interrupt request pin.
Fix it high when not in use.
IRQ7 to IRQ0
Input
Interrupt
requests 7 to 0
Maskable interrupt request pins.
Level-input or edge-input detection
can be selected. When the edge-input
detection is selected, the rising edge,
falling edge, or both edges can also
be selected.
IRQOUT
Output Interrupt request Indicates that an interrupt has
output
occurred, enabling external devices to
be informed of an interrupt occurrence
even while the bus mastership is
released.
Address bus
A25 to A0
Output Address bus
Outputs addresses. (A25 to A21 are
available only in the SH7286.)
Data bus
D31 to D0
I/O
Bidirectional data bus. (D31 to D16
are available only in the SH7286.)
Bus control
CS7 to CS0
Output Chip select 7
to 0
Chip-select signals for external
memory or devices.
RD
Output Read
Indicates that data is read from an
external device.
RD/WR
Output Read/write
Read/write signal.
BS
Output Bus start
Bus-cycle start signal.
AH
Output Address hold
Address hold timing signal for the
device that uses the address/datamultiplexed bus.
FRAME
Output Frame signal
In burst MPX-I/O interface mode,
negated before the last bus cycle to
indicate that the next bus cycle is the
last access (only in SH7286)
WAIT
Input
Input signal for inserting a wait cycle
into the bus cycles during access to
the external space.
WRHH
Output Write to HH byte Indicates a write access to bits 31 to
24 of data of external memory or
device (only in SH7286).
WRHL
Output Write to HL byte Indicates a write access to bits 23 to
16 of data of external memory or
device (only in SH7286).
Page 16 of 1778
Data bus
Wait
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
Name
Function
Bus control
WRH
Output
Write to upper
byte
Indicates a write access to bits 15 to 8
of data of external memory or device.
WRL
Output
Write to lower
byte
Indicates a write access to bits 7 to 0
of data of external memory or device.
DQMUU
Output
HH byte
selection
Selects bits D31 to D24 when SDRAM
is connected (only in SH7286).
DQMUL
Output
HL byte
selection
Selects bits D23 to D16 when SDRAM
is connected (only in SH7286).
DQMLU
Output
Upper byte
selection
Selects bits D15 to D8 when SDRAM
is connected.
DQMLL
Output
Lower byte
selection
Selects bits D7 to D0 when SDRAM is
connected.
RASU
Output
RAS
Connected to the RAS pin when
SDRAM is connected (only in
SH7286).
CASU
Output
CAS
Connected to the CAS pin when
SDRAM is connected (only in
SH7286).
RASL
Output
RAS
Connected to the RAS pin when
SDRAM is connected.
CASL
Output
CAS
Connected to the CAS pin when
SDRAM is connected.
CKE
Output
CK enable
Connected to the CKE pin when
SDRAM is connected.
REFOUT
Output
Refresh request Request signal output for refresh
output
execution while the bus mastership is
released.
Input
DMA-transfer
request
Input pins to receive external requests
for DMA transfer (DREQ2 and DREQ3
are only in SH7286).
DACK0 to
DACK3
Output
DMA-transfer
request accept
Output pins for signals indicating
acceptance of external requests from
external devices (DACK2 and DACK3
are only in SH7286).
TEND1,
TEND0
Output
DMA-transfer
end output
Output pins for DMA transfer end.
Direct memory
DREQ0 to
access controller DREQ3
(DMAC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 17 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
Multi-function
timer pulse unit
2 (MTU2)
TCLKA,
TCLKB,
TCLKC,
TCLKD
Input MTU2 timer clock External clock input pins for the
input
timer.
TIOC0A,
TIOC0B,
TIOC0C,
TIOC0D
I/O
MTU2 input
capture/output
compare
(channel 0)
The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins.
TIOC1A,
TIOC1B
I/O
MTU2 input
capture/output
compare
(channel 1)
The TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins.
TIOC2A,
TIOC2B
I/O
MTU2 input
capture/output
compare
(channel 2)
The TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins.
TIOC3A,
TIOC3B,
TIOC3C,
TIOC3D
I/O
MTU2 input
capture/output
compare
(channel 3)
The TGRA_3 to TGRD_3 input
capture input/output compare
output/PWM output pins.
TIOC4A,
TIOC4B,
TIOC4C,
TIOC4D
I/O
MTU2 input
capture/output
compare
(channel 4)
The TGRA_4 to TGRD_4 input
capture input/output compare
output/PWM output pins.
TIC5U,
TIC5V,
TIC5W
Input MTU2 input
capture
(channel 5)
The TGRU_5, TGRV_5, and
TGRW_5 input capture input/dead
time compensation input pins.
POE8 to POE0
Input Port output
control
Request signal input to place the
MTU2 and MTU2S waveform output
pin in the high impedance state
(SH7243 has only POE8, POE4,
POE3, and POE0).
Port output
enable (POE)
Page 18 of 1778
Name
Function
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
Name
Function
Multi-function
timer pulse unit
2S (MTU2S)
TIOC3AS,
TIOC3BS,
TIOC3CS,
TIOC3DS
I/O
MTU2S input
capture/output
compare
(channel 3)
The TGRA_3S to TGRD_3S input
capture input/output compare
output/PWM output pins.
TIOC4AS,
TIOC4BS,
TIOC4CS,
TIOC4DS
I/O
MTU2S input
capture/output
compare
(channel 4)
The TGRA_4S to TGRD_4S input
capture input/output compare
output/PWM output pins.
TIOC5US,
TIOC5VS,
TIOC5WS
Input
MTU2S input
capture
(channel 5)
The TGRU_5S, TGRV_5S, and
TGRW_5S input capture input/dead
time compensation input pins.
TXD4, TXD2 to
TXD0
Output Transmit data
Serial
communication
interface (SCI)
Serial
communication
interface with
FIFO (SCIF)
Synchronous
serial
communication
unit (SSU)
Data output pins. Only TXD2 and
TXD0 are available in the SH7243.
RXD4, RXD2 to Input
RXD0
Receive data
Data input pins. Only RXD2 and
RXD0 are available in the SH7243.
SCK4, SCK2 to I/O
SCK0
Serial clock
Clock input/output pins. Only SCK2
and SCK0 are available in the
SH7243.
TXD3
Output Transmit data
Data output pin.
RXD3
Input
Receive data
Data input pin.
SCK3
I/O
Serial clock
Clock input/output pin.
SSO
I/O
Data
Data input/output pin.
SSI
I/O
Data
Data input/output pin.
SSCK
I/O
Clock
Clock input/output pin.
I/O
Chip select
Chip select input/output pin.
(only in SH7285 SCS
and SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 19 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
Name
Function
Universal serial
bus (USB)
DrVCC
Input
USB power
supply
(only in SH7285
and SH7286)
DrVSS
Power supply pin for the internal
transceiver. Connect it to the 3.3-V
power supply.
Input
USB ground
Ground pin for the internal
transceiver.
USD+,
USD−
I/O
USB data
USB data input/output pins.
VBUS
Input
Cable connection USB cable connection monitor input
monitor
pin.
USPND
Output Suspend state
output
Outputs a high level when the
suspend state is entered.
CTx0
Output Transmit data
Transmit data pin for CAN bus.
CRx0
Input
Receive data
Receive data pin for CAN bus.
Controller area
network
(RCAN-ET)
(only in SH7286)
I2C bus
SCL
interface 3 (IIC3) SDA
(only in SH7285
and SH7286)
I/O
Serial clock pin
Serial clock input/output pin.
I/O
Serial data pin
Serial data input/output pin.
A/D converter
AN11 to AN0
Input
Analog input pins Analog input pins. Only AN7 to AN0
are available in the SH7285 and
SH7243.
ADTRG
Input
A/D conversion
trigger input
External trigger input pin for starting
A/D conversion.
AVCC
Input
Analog power
supply
Power supply pin for the A/D
converter. Connect this pin to the
system power supply (VCC) when
the A/D converter is not used.
AVREF
Input
Analog reference Reference voltage pin for the A/D
power supply
converter.
AVSS
Input
Analog ground
AVREFVSS
Input
Analog reference Reference ground pin for the A/D
ground
converter. Connect this pin to the
system power supply (VSS) when
the A/D converter is not used.
Page 20 of 1778
Ground pin for the A/D converter.
Connect this pin to the system
power supply (VSS) when the A/D
converter is not used.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
I/O
D/A converter
DA1, DA0
Output Analog output
pins
(only in SH7286)
I/O ports
PA23 to PA21, I/O
PA15 to PA0
Name
General port
Function
Analog output pins.
19-bit general input/output port pins.
Only PA23 to PA21, PA15 to PA12,
and PA9 to PA0 are available in the
SH7285.
Only PA15 to PA12 and PA9 to PA6
are available in the SH7243.
PB19 to PB6,
PB3 to PB0
I/O
General port
16-bit general input/output port pins.
Only PB12 to PB6 and PB3 to PB0
are available in the SH7285.
Only PB12, PB11, PB8 to PB6,
PB1, and PB0 are available in the
SH7243.
PC15 to PC0
I/O
General port
16-bit general input/output port pins.
PD31 to PD0
I/O
General port
32-bit general input/output port pins.
Only PD31 to PD24 and PD22 to
PD0 are available in the SH7285.
Only PD15 to PD0 are available in
the SH7243
PE15 to PE0
I/O
General port
16-bit general input/output port pins.
PF11 to PF0
Input
General port
12-bit general input port pins.
Only PF7 to PF0 are available in the
SH7285 and SH7243.
User debugging TCK
interface
TMS
(H-UDI)
TDI
Input
Test clock
Test-clock input pin.
Input
Test mode select Test-mode select signal input pin.
Input
Test data input
Serial input pin for instructions and
data.
TDO
Output Test data output
Serial output pin for instructions and
data.
TRST
Input
Initialization-signal input pin. Input a
low level when not using the H-UDI.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Test reset
Page 21 of 1778
SH7280 Group, SH7243 Group
Section 1 Overview
Classification
Symbol
Advanced user AUDATA3 to
debugger (AUD) AUDATA0
Emulator
interface
Name
Function
Output AUD data
Branch destination/source address
output pin
AUDCK
Output AUD clock
Sync clock output pin
AUDSYNC
Output AUD sync signal
Data start-position acknowledgesignal output pin
ASEBRKAK
Output Break mode
acknowledge
Indicates that the E10A-USB
emulator has entered its break
mode.
ASEBRK
Input
E10A-USB emulator break input pin.
User break
UBCTRG
controller (UBC)
Page 22 of 1778
I/O
Break request
Output User break trigger Trigger output pin for UBC condition
output
match.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
Section 2 CPU
2.1
Register Configuration
The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four
32-bit system registers.
2.1.1
General Registers
Figure 2.1 shows the general registers.
The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data
processing and address calculation. R0 is also used as an index register. Several instructions have
R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and
restoring the status register (SR) and program counter (PC) in exception handling is accomplished
by referencing the stack using R15.
31
0
R0*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15, SP (hardware stack pointer)*2
Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect
addressing mode. In some instructions, R0 functions as a fixed source register or destination register.
2. R15 functions as a hardware stack pointer (SP) during exception processing.
Figure 2.1 General Registers
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 23 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.1.2
Control Registers
The control registers consist of four 32-bit registers: the status register (SR), the global base
register (GBR), the vector base register (VBR), and the jump table base register (TBR).
The status register indicates instruction processing states.
The global base register functions as a base address for the GBR indirect addressing mode to
transfer data to the registers of on-chip peripheral modules.
The vector base register functions as the base address of the exception handling vector area
(including interrupts).
The jump table base register functions as the base address of the function table area.
31
14 13
9 8 7 6 5 4 3 2 1 0
BO CS
M Q
I[3:0]
S T
31
Status register (SR)
0
GBR
Global base register (GBR)
31
0
VBR
Vector base register (VBR)
0
31
TBR
Jump table base register (TBR)
Figure 2.2 Control Registers
(1)
Status Register (SR)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
BO
CS
-
-
-
M
Q
-
-
S
T
0
R
0
R/W
0
R/W
0
R
0
R
0
R
R/W
R/W
0
R
0
R
R/W
R/W
Initial value:
R/W:
Page 24 of 1778
I[3:0]
1
R/W
1
R/W
1
R/W
1
R/W
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
Bit Name
31 to 15 —
Section 2 CPU
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
14
BO
0
R/W
BO Bit
Indicates that a register bank has overflowed.
13
CS
0
R/W
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or fallen
below the saturation lower-limit value.
12 to 10 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
M
—
R/W
M Bit
8
Q
—
R/W
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
7 to 4
I[3:0]
1111
R/W
Interrupt Mask Level
3, 2
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
S
—
R/W
S Bit
Specifies a saturation operation for a MAC instruction.
0
T
—
R/W
T Bit
True/false condition or carry/borrow bit
(2)
Global Base Register (GBR)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3)
Vector Base Register (VBR)
VBR is referenced as the branch destination base address in the event of an exception or an
interrupt.
(4)
Jump Table Base Register (TBR)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 25 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.1.3
System Registers
The system registers consist of four 32-bit registers: the high and low multiply and accumulate
registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH
and MACL store the results of multiply or multiply and accumulate operations. PR stores the
return address from a subroutine procedure. PC indicates the program address being executed and
controls the flow of the processing.
31
0
Multiply and accumulate register high (MACH) and multiply
and accumulate register low (MACL):
Store the results of multiply or multiply and accumulate operations.
0
Procedure register (PR):
Stores the return address from a subroutine procedure.
0
Program counter (PC):
Indicates the four bytes ahead of the current instruction.
MACH
MACL
31
PR
31
PC
Figure 2.3 System Registers
(1)
Multiply and Accumulate Register High (MACH) and Multiply and Accumulate
Register Low (MACL)
MACH and MACL are used as the addition value in a MAC instruction, and store the result of a
MAC or MUL instruction.
(2)
Procedure Register (PR)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is
referenced by a subroutine return instruction (RTS).
(3)
Program Counter (PC)
PC indicates the address of the instruction being executed.
Page 26 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
2.1.4
Section 2 CPU
Register Banks
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and
system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried
out using a register bank. The register contents are automatically saved in the bank after the CPU
accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a
RESBANK instruction in an interrupt processing routine.
For details, refer to section 6.8, Register Banks, and the SH-2A, SH2A-FPU Software Manual.
2.1.5
Initial Values of Registers
Table 2.1 lists the values of the registers after a reset.
Table 2.1
Initial Values of Registers
Classification
Register
Initial Value
General registers
R0 to R14
Undefined
R15 (SP)
Value of the stack pointer in the vector
address table
SR
Bits I[3:0] are 1111 (H'F), BO and CS are
0, reserved bits are 0, and other bits are
undefined
GBR, TBR
Undefined
VBR
H'00000000
MACH, MACL, PR
Undefined
PC
Value of the program counter in the vector
address table
Control registers
System registers
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 27 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.2
Data Formats
2.2.1
Data Format in Registers
Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits)
or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a
register.
31
0
Longword
Figure 2.4 Data Format in Registers
2.2.2
Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in
8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored
in a register in sign-extended or zero-extended form.
A word operand should be accessed at a word boundary (an even address of multiple of two bytes:
address 2n), and a longword operand at a longword boundary (an even address of multiple of four
bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any
address.
Only big-endian byte order can be selected for the data format.
Data formats in memory are shown in figure 2.5.
Address m + 3
Address m + 1
Address m
31
Address m + 2
23
Byte
Address 2n
Address 4n
15
Byte
7
Byte
Word
0
Byte
Word
Longword
Figure 2.5 Data Formats in Memory
Page 28 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
2.2.3
Section 2 CPU
Immediate Data Format
Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the
MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword
data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction.
The MOVI20 instruction stores immediate data in the destination register in sign-extended form.
The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it
in the destination register in sign-extended form.
Word or longword immediate data is not located in the instruction code, but rather is stored in a
memory table. The memory table is accessed by an immediate data transfer instruction (MOV)
using the PC relative addressing mode with displacement.
See examples given in section 2.3.1 (10), Immediate Data.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 29 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.3
Instruction Features
2.3.1
RISC-Type Instruction Set
Instructions are RISC type. This section details their functions.
(1)
16-Bit Fixed-Length Instructions
Basic instructions have a fixed length of 16 bits, improving program code efficiency.
(2)
32-Bit Fixed-Length Instructions
The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease
of use.
(3)
One Instruction per State
Each basic instruction can be executed in one cycle using the pipeline system.
(4)
Data Length
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data in memory is sign-extended and handled as longword data.
Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It
is also handled as longword data.
Table 2.2
Sign Extension of Word Data
SH2-A CPU
MOV.W
ADD
.DATA.W
Description
@(disp,PC),R1 Data is sign-extended to 32 bits,
and R1 becomes H'00001234. It is
R1,R0
next operated upon by an ADD
.........
instruction.
H'1234
Example of Other CPU
ADD.W
#H'1234,R0
Note: @(disp, PC) accesses the immediate data.
(5)
Load-Store Architecture
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
Page 30 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(6)
Section 2 CPU
Delayed Branch Instructions
With the exception of some instructions, unconditional branch instructions, etc., are executed as
delayed branch instructions. With a delayed branch instruction, the branch is taken after execution
of the instruction immediately following the delayed branch instruction. This reduces disturbance
of the pipeline control when a branch is taken.
In a delayed branch, the actual branch operation occurs after execution of the slot instruction.
However, instruction execution such as register updating excluding the actual branch operation, is
performed in the order of delayed branch instruction → delay slot instruction. For example, even
though the contents of the register holding the branch destination address are changed in the delay
slot, the branch destination address remains as the register contents prior to the change.
Table 2.3
Delayed Branch Instructions
SH-2A CPU
Description
Example of Other CPU
BRA
TRGET
R1,R0
R1,R0
Executes the ADD before
branching to TRGET.
ADD.W
ADD
BRA
TRGET
(7)
Unconditional Branch Instructions with No Delay Slot
The SH-2A additionally features unconditional branch instructions in which a delay slot
instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code
size.
(8)
Multiply/Multiply-and-Accumulate Operations
16-bit × 16-bit → 32-bit multiply operations are executed in one to two cycles. 16-bit × 16-bit +
64-bit → 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit ×
32-bit → 64-bit multiply and 32-bit × 32-bit + 64-bit → 64-bit multiply-and-accumulate
operations are executed in two to four cycles.
(9)
T Bit
The T bit in the status register (SR) changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 31 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Table 2.4
T Bit
SH-2A CPU
Description
Example of Other CPU
CMP/GE
R1,R0
T bit is set when R0 ≥ R1.
CMP.W
R1,R0
BT
TRGET0
BGE
TRGET0
BF
TRGET1
The program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
BLT
TRGET1
ADD
#−1,R0
T bit is not changed by ADD.
SUB.W
#1,R0
CMP/EQ
#0,R0
T bit is set when R0 = 0.
BEQ
TRGET
BT
TRGET
The program branches if R0 = 0.
(10) Immediate Data
Byte immediate data is located in an instruction code. Word or longword immediate data is not
located in instruction codes but in a memory table. The memory table is accessed by an immediate
data transfer instruction (MOV) using the PC relative addressing mode with displacement.
With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for
21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a
register.
Table 2.5
Immediate Data Accessing
Classification
SH-2A CPU
8-bit immediate
MOV
#H'12,R0
MOV.B
#H'12,R0
16-bit immediate
MOVI20
#H'1234,R0
MOV.W
#H'1234,R0
20-bit immediate
MOVI20
#H'12345,R0
MOV.L
#H'12345,R0
28-bit immediate
MOVI20S
#H'12345,R0
MOV.L
#H'1234567,R0
OR
#H'67,R0
MOV.L
@(disp,PC),R0
MOV.L
#H'12345678,R0
32-bit immediate
Example of Other CPU
.................
.DATA.L
H'12345678
Note: @(disp, PC) accesses the immediate data.
Page 32 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
(11) Absolute Address
When data is accessed by an absolute address, the absolute address value should be placed in the
memory table in advance. That value is transferred to the register by loading the immediate data
during the execution of the instruction, and the data is accessed in register indirect addressing
mode.
With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also
possible to transfer immediate data located in the instruction code to a register and to reference the
data in register indirect addressing mode. However, when referencing data using an absolute
address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register.
Table 2.6
Absolute Address Accessing
Classification
SH-2A CPU
Up to 20 bits
MOVI20
#H'12345,R1
MOV.B
@R1,R0
MOVI20S
#H'12345,R1
OR
#H'67,R1
MOV.B
@R1,R0
MOV.L
@(disp,PC),R1
MOV.B
@R1,R0
21 to 28 bits
29 bits or more
Example of Other CPU
MOV.B
@H'12345,R0
MOV.B
@H'1234567,R0
MOV.B
@H'12345678,R0
..................
.DATA.L
H'12345678
(12) 16-Bit/32-Bit Displacement
When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed
in the memory table in advance. That value is transferred to the register by loading the immediate
data during the execution of the instruction, and the data is accessed in the indexed indirect
register addressing mode.
Table 2.7
Displacement Accessing
Classification
SH-2A CPU
Example of Other CPU
16-bit displacement
MOV.W
@(disp,PC),R0
MOV.W
@(R0,R1),R2
MOV.W
@(H'1234,R1),R2
..................
.DATA.W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
H'1234
Page 33 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.3.2
Addressing Modes
Addressing modes and effective address calculation are as follows:
Table 2.8
Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Register direct
Rn
Register indirect @Rn
The effective address is register Rn. (The operand
is the contents of register Rn.)
—
The effective address is the contents of register Rn. Rn
Rn
Register indirect @Rn+
with postincrement
Equation
Rn
The effective address is the contents of register Rn.
A constant is added to the contents of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
Rn
Rn
Rn + 1/2/4
+
Rn
(After
instruction
execution)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
1/2/4
Longword:
Rn + 4 → Rn
Register indirect @-Rn
with predecrement
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
Rn – 1/2/4
1/2/4
Page 34 of 1778
–
Rn – 1/2/4
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Addressing
Mode
Instruction
Format
Register indirect @(disp:4,
with
Rn)
displacement
Section 2 CPU
Effective Address Calculation
Equation
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Byte:
Rn + disp
Rn
disp
(zero-extended)
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Rn + disp × 1/2/4
+
×
1/2/4
Register indirect @(disp:12, The effective address is the sum of Rn and a 12with
Rn)
bit
displacement
displacement (disp). The value of disp is zeroextended.
Rn
+
Rn + disp
Byte:
Rn + disp
Word:
Rn + disp
Longword:
Rn + disp
disp
(zero-extended)
Indexed register @(R0,Rn)
indirect
The effective address is the sum of Rn and R0.
Rn + R0
Rn
+
Rn + R0
R0
GBR indirect
with
displacement
@(disp:8,
GBR)
The effective address is the sum of GBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and remains unchanged for
a byte operation, is doubled for a word operation,
and is quadrupled for a longword operation.
GBR
disp
(zero-extended)
+
GBR
+ disp × 1/2/4
Byte:
GBR + disp
Word:
GBR + disp ×
2
Longword:
GBR + disp ×
4
×
1/2/4
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 35 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Indexed GBR
indirect
@(R0, GBR) The effective address is the sum of GBR value
and R0.
GBR + R0
GBR
+
GBR + R0
R0
TBR duplicate
indirect with
displacement
@@
(disp:8,
TBR)
The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
Contents of
address (TBR
+ disp × 4)
TBR
disp
(zero-extended)
TBR
+
+ disp × 4
×
(TBR
4
PC indirect with @(disp:8,
displacement
PC)
+ disp × 4)
The effective address is the sum of PC value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC
+ disp × 4
PC
&
H'FFFFFFFC
(for longword)
+
disp
(zero-extended)
PC + disp × 2
or
PC & H'FFFFFFFC
+ disp × 4
×
2/4
Page 36 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
PC relative
disp:8
The effective address is the sum of PC value and
the value that is obtained by doubling the signextended 8-bit displacement (disp).
Equation
PC + disp × 2
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
disp:12
The effective address is the sum of PC value and
the value that is obtained by doubling the signextended 12-bit displacement (disp).
PC + disp × 2
PC
disp
(sign-extended)
+
PC + disp × 2
×
2
Rn
The effective address is the sum of PC value and
Rn.
PC + Rn
PC
+
PC + Rn
Rn
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 37 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
Immediate
#imm:20
Equation
The 20-bit immediate data (imm) for the MOVI20
instruction is sign-extended.
—
31
19
0
Signextended imm (20 bits)
The 20-bit immediate data (imm) for the MOVI20S
—
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits are
padded with zero.
31 27
8
0
imm (20 bits) 00000000
Sign-extended
Page 38 of 1778
#imm:8
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
—
#imm:8
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
—
#imm:8
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
—
#imm:3
The 3-bit immediate data (imm) for the BAND, BOR, —
BXOR, BST, BLD, BSET, and BCLR instructions
indicates the target bit location.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
2.3.3
Section 2 CPU
Instruction Format
The instruction formats and the meaning of source and destination operands are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
•
•
•
•
•
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Table 2.9
Instruction Formats
Instruction Formats
0 format
15
Source
Operand
Destination
Operand
Example
—
—
NOP
—
nnnn: Register
direct
MOVT
Rn
Control register or
system register
nnnn: Register
direct
STS
MACH,Rn
R0 (Register direct) nnnn: Register
direct
DIVU
R0,Rn
Control register or
system register
nnnn: Register
indirect with predecrement
STC.L
SR,@-Rn
mmmm: Register
direct
R15 (Register
indirect with predecrement)
MOVMU.L Rm,@-R15
R15 (Register
indirect with postincrement)
nnnn: Register
direct
MOVMU.L @R15+,Rn
0
xxxx xxxx xxxx xxxx
n format
15
xxxx
0
nnnn
xxxx
xxxx
R0 (Register direct) nnnn: (Register
indirect with postincrement)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
MOV.L
R0,@Rn+
Page 39 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Instruction Formats
m format
15
0
xxxx
mmmm
xxxx
xxxx
nm format
15
0
xxxx
nnnn
mmmm
xxxx
Source
Operand
Destination
Operand
mmmm: Register
direct
Control register or
system register
LDC
mmmm: Register
indirect with postincrement
Control register or
system register
LDC.L @Rm+,SR
mmmm: Register
indirect
—
JMP
mmmm: Register
indirect with predecrement
R0 (Register direct) MOV.L @-Rm,R0
Example
Rm,SR
@Rm
mmmm: PC relative —
using Rm
BRAF
Rm
mmmm: Register
direct
nnnn: Register
direct
ADD
Rm,Rn
mmmm: Register
direct
nnnn: Register
indirect
MOV.L Rm,@Rn
mmmm: Register
MACH, MACL
indirect with postincrement (multiplyand-accumulate)
MAC.W
@Rm+,@Rn+
nnnn*: Register
indirect with postincrement (multiplyand-accumulate)
md format
15
0
xxxx
xxxx
Page 40 of 1778
mmmm
dddd
mmmm: Register
indirect with postincrement
nnnn: Register
direct
MOV.L
@Rm+,Rn
mmmm: Register
direct
nnnn: Register
indirect with predecrement
MOV.L
Rm,@-Rn
mmmm: Register
direct
nnnn: Indexed
register indirect
MOV.L
Rm,@(R0,Rn)
mmmmdddd:
Register indirect
with displacement
R0 (Register direct) MOV.B
@(disp,Rm),R0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
Source
Operand
Instruction Formats
nd4 format
15
0
xxxx
xxxx
nnnn
dddd
nmd format
15
0
xxxx
nnnn
mmmm
32
xxxx
15
xxxx
16
nnnn
mmmm
dddd
dddd
d format
15
0
xxxx
xxxx
dddd
dddd
15
0
xxxx
dddd
dddd
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
mmmm: Register
direct
nnnndddd: Register MOV.L
indirect with
Rm,@(disp12,Rn)
displacement
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
dddddddd: GBR
indirect with
displacement
R0 (Register direct) MOV.L
@(disp,GBR),R0
15
0
xxxx
nnnn
dddd
dddd
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
MOV.L
@(disp,Rm),Rn
MOV.L
@(disp12,Rm),Rn
MOV.L
R0,@(disp,GBR)
dddddddd: PC
relative with
displacement
R0 (Register direct) MOVA
@(disp,PC),R0
dddddddd: TBR
duplicate indirect
with displacement
—
JSR/N
@@(disp8,TBR)
dddddddd: PC
relative
—
BF
label
dddddddddddd: PC —
relative
BRA
label
dddddddd: PC
relative with
displacement
MOV.L
@(disp,PC),Rn
dddd
nd8 format
MOV.B
R0,@(disp,Rn)
nnnndddd: Register MOV.L
indirect with
Rm,@(disp,Rn)
displacement
R0 (Register direct) dddddddd: GBR
indirect with
displacement
d12 format
Example
mmmm: Register
direct
xxxx
0
dddd
R0 (Register direct) nnnndddd:
Register indirect
with displacement
dddd
nmd12 format
Destination
Operand
nnnn: Register
direct
(label = disp +
PC)
Page 41 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Instruction Formats
Source
Operand
Destination
Operand
Example
i format
iiiiiiii: Immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
iiiiiiii: Immediate
R0 (Register direct)
AND
#imm,R0
iiiiiiii: Immediate
—
TRAPA
#imm
iiiiiiii: Immediate
nnnn: Register direct ADD
15
xxxx
xxxx
iiii
0
iiii
ni format
15
#imm,Rn
0
xxxx
nnnn
iiii iiii
ni3 format
nnnn: Register direct —
15
0
xxxx
xxxx
nnnn x iii
BLD
#imm3,Rn
nnnn: Register direct BST
#imm3,Rn
iii: Immediate
—
iii: Immediate
ni20 format
16
32
xxxx
nnnn
iiii
xxxx
15
iiii
iiii
iiii
iiii
15
xxxx
nnnn: Register direct MOVI20
#imm20, Rn
0
nid format
32
xxxx
iiiiiiiiiiiiiiiiiiii:
Immediate
16
nnnn
xiii
xxxx
0
dddd
dddd
dddd
nnnndddddddddddd: —
Register indirect with
displacement
BLD.B
#imm3,@(disp12,Rn
)
iii: Immediate
—
nnnndddddddddddd: BST.B
Register indirect with #imm3,@(disp12,Rn
displacement
)
iii: Immediate
Note:
*
In multiply-and-accumulate instructions, nnnn is the source register.
Page 42 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
2.4
Instruction Set
2.4.1
Instruction Set by Classification
Table 2.10 lists the instructions according to their classification.
Table 2.10 Classification of Instructions
Classification Types
Operation
Code
Function
No. of
Instructions
Data transfer
MOV
62
13
Data transfer
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Reverse stack transfer
MOVA
Effective address transfer
MOVI20
20-bit immediate data transfer
MOVI20S
20-bit immediate data transfer
8-bit left-shit
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
MOVML
R0–Rn register save/restore
MOVMU
Rn–R14 and PR register save/restore
MOVRT
T bit inversion and transfer to Rn
MOVT
T bit transfer
MOVU
Unsigned data transfer
NOTT
T bit inversion
PREF
Prefetch to operand cache
SWAP
Swap of upper and lower bytes
XTRCT
Extraction of the middle of registers connected
Page 43 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Classification Types
Arithmetic
operations
26
Operation
Code
Function
No. of
Instructions
ADD
Binary addition
40
ADDC
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond Comparison
Page 44 of 1778
CLIPS
Signed saturation value comparison
CLIPU
Unsigned saturation value comparison
DIVS
Signed division (32 ÷ 32)
DIVU
Unsigned division (32 ÷ 32)
DIV1
One-step division
DIV0S
Initialization of signed one-step division
DIV0U
Initialization of unsigned one-step division
DMULS
Signed double-precision multiplication
DMULU
Unsigned double-precision multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply-and-accumulate, double-precision
multiply-and-accumulate operation
MUL
Double-precision multiply operation
MULR
Signed multiplication with result storage in Rn
MULS
Signed multiplication
MULU
Unsigned multiplication
NEG
Negation
NEGC
Negation with borrow
SUB
Binary subtraction
SUBC
Binary subtraction with borrow
SUBV
Binary subtraction with underflow
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Classification Types
Logic
operations
Shift
Branch
6
12
10
Section 2 CPU
Operation
Code
Function
No. of
Instructions
AND
Logical AND
14
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit set
TST
Logical AND and T bit set
XOR
Exclusive OR
ROTL
One-bit left rotation
ROTR
One-bit right rotation
ROTCL
One-bit left rotation with T bit
ROTCR
One-bit right rotation with T bit
SHAD
Dynamic arithmetic shift
SHAL
One-bit arithmetic left shift
SHAR
One-bit arithmetic right shift
SHLD
Dynamic logical shift
SHLL
One-bit logical left shift
SHLLn
n-bit logical left shift
SHLR
One-bit logical right shift
SHLRn
n-bit logical right shift
BF
Conditional branch, conditional delayed
branch (branch when T = 0)
BT
Conditional branch, conditional delayed
branch (branch when T = 1)
BRA
Unconditional delayed branch
BRAF
Unconditional delayed branch
BSR
Delayed branch to subroutine procedure
BSRF
Delayed branch to subroutine procedure
JMP
Unconditional delayed branch
JSR
Branch to subroutine procedure
16
15
Delayed branch to subroutine procedure
RTS
Return from subroutine procedure
Delayed return from subroutine procedure
RTV/N
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Return from subroutine procedure with Rm →
R0 transfer
Page 45 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Classification Types
System
control
14
Operation
Code
Function
No. of
Instructions
CLRT
T bit clear
36
CLRMAC
MAC register clear
LDBANK
Register restoration from specified register
bank entry
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RESBANK Register restoration from register bank
Bit
manipulation
10
RTE
Return from exception handling
SETT
T bit set
SLEEP
Transition to power-down mode
STBANK
Register save to specified register bank entry
STC
Store control register data
STS
Store system register data
TRAPA
Trap exception handling
BAND
Bit AND
BCLR
Bit clear
BLD
Bit load
BOR
Bit OR
BSET
Bit set
BST
Bit store
BXOR
Bit exclusive OR
14
BANDNOT Bit NOT AND
Total:
Page 46 of 1778
91
BORNOT
Bit NOT OR
BLDNOT
Bit NOT load
197
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
Execution
States
T Bit
Value when no
wait states are
inserted.*1
Value of T bit after
instruction is
executed.
Instruction
Instruction Code
Operation
Indicated by mnemonic.
Indicated in MSB ↔
LSB order.
Indicates summary of
operation.
[Legend]
[Legend]
[Legend]
Explanation of
Symbols
Rm:
Source register
mmmm: Source register
→, ←:
Transfer direction
—: No change
Rn:
Destination register
nnnn: Destination register
0000: R0
0001: R1
.........
(xx):
Memory operand
imm: Immediate data
disp: Displacement*2
1111: R15
iiii:
Immediate data
dddd:
Displacement
M/Q/T: Flag bits in SR
&:
Logical AND of each bit
|:
Logical OR of each bit
^:
Exclusive logical OR of
each bit
~:
Logical NOT of each bit
n: n-bit right shift
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
practice, the number of instruction execution states will be increased in cases such as
the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is the same
as the register used by the next instruction.
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
refer to the SH-2A, SH2A-FPU Software Manual.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 47 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.4.2
Data Transfer Instructions
Table 2.11 Data Transfer Instructions
Compatibility
Execution
Operation
SH2,
Cycles T Bit SH2E SH4
Instruction
Instruction Code
SH-2A
MOV
#imm,Rn
1110nnnniiiiiiii imm → sign extension → Rn
1
⎯
Yes
Yes
Yes
MOV.W
@(disp,PC),Rn
1001nnnndddddddd (disp × 2 + PC) → sign
1
⎯
Yes
Yes
Yes
extension → Rn
MOV.L
@(disp,PC),Rn
1101nnnndddddddd (disp × 4 + PC) → Rn
1
⎯
Yes
Yes
Yes
MOV
Rm,Rn
0110nnnnmmmm0011 Rm → Rn
1
⎯
Yes
Yes
Yes
MOV.B
Rm,@Rn
0010nnnnmmmm0000 Rm → (Rn)
1
⎯
Yes
Yes
Yes
MOV.W
Rm,@Rn
0010nnnnmmmm0001 Rm → (Rn)
1
⎯
Yes
Yes
Yes
MOV.L
Rm,@Rn
0010nnnnmmmm0010 Rm → (Rn)
1
⎯
Yes
Yes
Yes
MOV.B
@Rm,Rn
0110nnnnmmmm0000 (Rm) → sign extension → Rn
1
⎯
Yes
Yes
Yes
MOV.W
@Rm,Rn
0110nnnnmmmm0001 (Rm) → sign extension → Rn
1
⎯
Yes
Yes
Yes
MOV.L
@Rm,Rn
0110nnnnmmmm0010 (Rm) → Rn
1
⎯
Yes
Yes
Yes
MOV.B
Rm,@-Rn
0010nnnnmmmm0100 Rn-1 → Rn, Rm → (Rn)
1
⎯
Yes
Yes
Yes
MOV.W
Rm,@-Rn
0010nnnnmmmm0101 Rn-2 → Rn, Rm → (Rn)
1
⎯
Yes
Yes
Yes
MOV.L
Rm,@-Rn
0010nnnnmmmm0110 Rn-4 → Rn, Rm → (Rn)
1
⎯
Yes
Yes
Yes
MOV.B
@Rm+,Rn
0110nnnnmmmm0100 (Rm) → sign extension → Rn, 1
⎯
Yes
Yes
Yes
⎯
Yes
Yes
Yes
Rm + 1 → Rm
MOV.W
@Rm+,Rn
0110nnnnmmmm0101 (Rm) → sign extension → Rn, 1
Rm + 2 → Rm
MOV.L
@Rm+,Rn
0110nnnnmmmm0110 (Rm) → Rn, Rm + 4 → Rm
1
⎯
Yes
Yes
Yes
MOV.B
R0,@(disp,Rn)
10000000nnnndddd R0 → (disp + Rn)
1
⎯
Yes
Yes
Yes
MOV.W
R0,@(disp,Rn)
10000001nnnndddd R0 → (disp × 2 + Rn)
1
⎯
Yes
Yes
Yes
MOV.L
Rm,@(disp,Rn)
0001nnnnmmmmdddd Rm → (disp × 4 + Rn)
1
⎯
Yes
Yes
Yes
MOV.B
@(disp,Rm),R0
10000100mmmmdddd (disp + Rm) → sign extension
1
⎯
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
→ R0
MOV.W
@(disp,Rm),R0
10000101mmmmdddd (disp × 2 + Rm) →
sign extension → R0
MOV.L
@(disp,Rm),Rn
0101nnnnmmmmdddd (disp × 4 + Rm) → Rn
1
⎯
Yes
Yes
Yes
MOV.B
Rm,@(R0,Rn)
0000nnnnmmmm0100 Rm → (R0 + Rn)
1
⎯
Yes
Yes
Yes
Page 48 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
Compatibility
Execution
Operation
SH2,
Cycles T Bit SH2E SH4
Instruction
Instruction Code
SH-2A
MOV.W
Rm,@(R0,Rn)
0000nnnnmmmm0101 Rm → (R0 + Rn)
1
⎯
Yes
Yes
Yes
MOV.L
Rm,@(R0,Rn)
0000nnnnmmmm0110 Rm → (R0 + Rn)
1
⎯
Yes
Yes
Yes
MOV.B
@(R0,Rm),Rn
0000nnnnmmmm1100 (R0 + Rm) →
1
⎯
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
sign extension → Rn
MOV.W
@(R0,Rm),Rn
0000nnnnmmmm1101 (R0 + Rm) →
sign extension → Rn
MOV.L
@(R0,Rm),Rn
0000nnnnmmmm1110 (R0 + Rm) → Rn
1
⎯
Yes
Yes
Yes
MOV.B
R0,@(disp,GBR)
11000000dddddddd R0 → (disp + GBR)
1
⎯
Yes
Yes
Yes
MOV.W
R0,@(disp,GBR)
11000001dddddddd R0 → (disp × 2 + GBR)
1
⎯
Yes
Yes
Yes
MOV.L
R0,@(disp,GBR)
11000010dddddddd R0 → (disp × 4 + GBR)
1
⎯
Yes
Yes
Yes
MOV.B
@(disp,GBR),R0
11000100dddddddd (disp + GBR) →
1
⎯
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
Yes
Yes
Yes
sign extension → R0
MOV.W
@(disp,GBR),R0
11000101dddddddd (disp × 2 + GBR) →
sign extension → R0
MOV.L
@(disp,GBR),R0
11000110dddddddd (disp × 4 + GBR) → R0
1
⎯
MOV.B
R0,@Rn+
0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn
1
⎯
Yes
MOV.W
R0,@Rn+
0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn
1
⎯
Yes
MOV.L
R0,@Rn+
0100nnnn10101011 R0 → Rn), Rn + 4 → Rn
1
⎯
Yes
MOV.B
@-Rm,R0
0100mmmm11001011 Rm-1 → Rm, (Rm) →
1
⎯
Yes
1
⎯
Yes
sign extension → R0
MOV.W
@-Rm,R0
0100mmmm11011011 Rm-2 → Rm, (Rm) →
sign extension → R0
0100mmmm11101011 Rm-4 → Rm, (Rm) → R0
MOV.L
@-Rm,R0
MOV.B
Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp + Rn)
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
0000dddddddddddd
MOV.W
Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp × 2 + Rn)
0001dddddddddddd
MOV.L
Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp × 4 + Rn)
0010dddddddddddd
MOV.B
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) →
0100dddddddddddd
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
sign extension → Rn
Page 49 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Compatibility
Execution
Instruction
MOV.W
Instruction Code
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp × 2 + Rm) →
0101dddddddddddd
MOV.L
Operation
SH2,
Cycles T Bit SH2E SH4
SH-2A
1
⎯
Yes
1
⎯
Yes
sign extension → Rn
@(disp12,Rm),Rn 0011nnnnmmmm0001 (disp × 4 + Rm) → Rn
0110dddddddddddd
MOVA
@(disp,PC),R0
11000111dddddddd disp × 4 + PC → R0
1
⎯
MOVI20
#imm20,Rn
0000nnnniiii0000 imm → sign extension → Rn
1
⎯
Yes
1
⎯
Yes
1 to 16
⎯
Yes
1 to 16
⎯
Yes
1 to 16
⎯
Yes
1 to 16
⎯
Yes
Yes
Yes
Yes
iiiiiiiiiiiiiiii
MOVI20S #imm20,Rn
0000nnnniiii0001 imm Rm (unsigned),
1
Com-
1→T
parison
Otherwise, 0 → T
result
When Rn > Rm (signed),
1
Com-
1→T
parison
Otherwise, 0 → T
result
When Rn > 0, 1 → T
1
Otherwise, 0 → T
Comparison
result
CMP/PZ
Rn
0100nnnn00010001
When Rn ≥ 0, 1 → T
1
Otherwise, 0 → T
Comparison
result
CMP/STR Rm,Rn
Page 52 of 1778
0010nnnnmmmm1100
When any bytes are equal,
1
Com-
1→T
parison
Otherwise, 0 → T
result
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
Compatibility
Execution
SH2,
Instruction
Instruction Code
Operation
Cycles T Bit
SH2E SH4
CLIPS.B
0100nnnn10010001
When Rn > (H'0000007F),
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
1
⎯
Yes
Rn
SH-2A
(H'0000007F) → Rn, 1 → CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80) → Rn, 1 → CS
CLIPS.W
Rn
0100nnnn10010101
When Rn > (H'00007FFF),
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
CLIPU.B
Rn
0100nnnn10000001
When Rn > (H'000000FF),
(H'000000FF) → Rn, 1 → CS
CLIPU.W Rn
0100nnnn10000101
When Rn > (H'0000FFFF),
(H'0000FFFF) → Rn, 1 → CS
DIV1
Rm,Rn
0011nnnnmmmm0100
1-step division (Rn ÷ Rm)
1
Calcu-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
lation
result
DIV0S
Rm,Rn
0010nnnnmmmm0111
MSB of Rn → Q,
1
MSB of Rm → M, M ^ Q → T
Calculation
result
DIV0U
DIVS
R0,Rn
0000000000011001
0 → M/Q/T
1
0
0100nnnn10010100
Signed operation of Rn ÷ R0
36
⎯
Yes
Unsigned operation of Rn ÷ R0 34
⎯
Yes
→ Rn 32 ÷ 32 → 32 bits
DIVU
R0,Rn
0100nnnn10000100
→ Rn 32 ÷ 32 → 32 bits
DMULS.L Rm,Rn
0011nnnnmmmm1101
Signed operation of Rn × Rm
2
⎯
Yes
Yes
Yes
2
⎯
Yes
Yes
Yes
1
Compa- Yes
Yes
Yes
→ MACH, MACL
32 × 32 → 64 bits
DMULU.L Rm,Rn
0011nnnnmmmm0101
Unsigned operation of Rn ×
Rm → MACH, MACL
32 × 32 → 64 bits
DT
EXTS.B
Rn
Rm,Rn
0100nnnn00010000
0110nnnnmmmm1110
Rn – 1 → Rn
When Rn is 0, 1 → T
rison
When Rn is not 0, 0 → T
result
Byte in Rm is
1
⎯
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
sign-extended → Rn
EXTS.W
Rm,Rn
0110nnnnmmmm1111
Word in Rm is
sign-extended → Rn
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 53 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
Compatibility
Execution
SH2,
Instruction
Instruction Code
Operation
Cycles T Bit
SH2E SH4 SH-2A
EXTU.B
0110nnnnmmmm1100
Byte in Rm is
1
⎯
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
4
⎯
Yes
Yes
Yes
3
⎯
Yes
Yes
Yes
2
⎯
Yes
Yes
Yes
Rm,Rn
zero-extended → Rn
EXTU.W
Rm,Rn
0110nnnnmmmm1101
Word in Rm is
zero-extended → Rn
MAC.L
@Rm+,@Rn+
0000nnnnmmmm1111
Signed operation of (Rn) ×
(Rm) + MAC → MAC
32 × 32 + 64 → 64 bits
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
Signed operation of (Rn) ×
(Rm) + MAC → MAC
16 × 16 + 64 → 64 bits
MUL.L
Rm,Rn
0000nnnnmmmm0111
Rn × Rm → MACL
32 × 32 → 32 bits
MULR
R0,Rn
0100nnnn10000000
R0 × Rn → Rn
2
Yes
32 × 32 → 32 bits
MULS.W
Rm,Rn
0010nnnnmmmm1111
Signed operation of Rn × Rm
1
⎯
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
→ MACL
16 × 16 → 32 bits
MULU.W
Rm,Rn
0010nnnnmmmm1110
Unsigned operation of Rn ×
Rm → MACL
16 × 16 → 32 bits
NEG
Rm,Rn
0110nnnnmmmm1011
0-Rm → Rn
1
⎯
Yes
Yes
Yes
NEGC
Rm,Rn
0110nnnnmmmm1010
0-Rm-T → Rn, borrow → T
1
Borrow Yes
Yes
Yes
SUB
Rm,Rn
0011nnnnmmmm1000
Rn-Rm → Rn
1
⎯
Yes
Yes
Yes
SUBC
Rm,Rn
0011nnnnmmmm1010
Rn-Rm-T → Rn, borrow → T
1
Borrow Yes
Yes
Yes
SUBV
Rm,Rn
0011nnnnmmmm1011
Rn-Rm → Rn, underflow → T
1
Under- Yes
Yes
Yes
flow
Page 54 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
2.4.4
Section 2 CPU
Logic Operation Instructions
Table 2.13 Logic Operation Instructions
Compatibility
Execution
SH2,
Instruction
Instruction Code
Operation
Cycles T Bit SH2E SH4
AND
Rm,Rn
0010nnnnmmmm1001
Rn & Rm → Rn
1
⎯
Yes
Yes
Yes
AND
#imm,R0
11001001iiiiiiii
R0 & imm → R0
1
⎯
Yes
Yes
Yes
AND.B
#imm,@(R0,GBR)
11001101iiiiiiii
(R0 + GBR) & imm →
3
⎯
Yes
Yes
Yes
SH-2A
(R0 + GBR)
NOT
Rm,Rn
0110nnnnmmmm0111
~Rm → Rn
1
⎯
Yes
Yes
Yes
OR
Rm,Rn
0010nnnnmmmm1011
Rn | Rm → Rn
1
⎯
Yes
Yes
Yes
OR
#imm,R0
11001011iiiiiiii
R0 | imm → R0
1
⎯
Yes
Yes
Yes
OR.B
#imm,@(R0,GBR)
11001111iiiiiiii
(R0 + GBR) | imm →
3
⎯
Yes
Yes
Yes
3
Test
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(R0 + GBR)
TAS.B
@Rn
0100nnnn00011011
When (Rn) is 0, 1 → T
Otherwise, 0 → T,
result
1 → MSB of(Rn)
TST
Rm,Rn
0010nnnnmmmm1000
Rn & Rm
1
When the result is 0, 1 → T
Test
result
Otherwise, 0 → T
TST
#imm,R0
11001000iiiiiiii
R0 & imm
1
When the result is 0, 1 → T
Test
result
Otherwise, 0 → T
TST.B
#imm,@(R0,GBR)
11001100iiiiiiii
(R0 + GBR) & imm
3
When the result is 0, 1 → T
Test
result
Otherwise, 0 → T
XOR
Rm,Rn
0010nnnnmmmm1010
Rn ^ Rm → Rn
1
⎯
Yes
Yes
Yes
XOR
#imm,R0
11001010iiiiiiii
R0 ^ imm → R0
1
⎯
Yes
Yes
Yes
XOR.B
#imm,@(R0,GBR)
11001110iiiiiiii
(R0 + GBR) ^ imm →
3
⎯
Yes
Yes
Yes
(R0 + GBR)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 55 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.4.5
Shift Instructions
Table 2.14 Shift Instructions
Compatibility
Execution
SH2,
Instruction
Instruction Code
Operation
Cycles T Bit SH2E SH4
SH-2A
ROTL
Rn
0100nnnn00000100
T ← Rn ← MSB
1
MSB
Yes
Yes
Yes
ROTR
Rn
0100nnnn00000101
LSB → Rn → T
1
LSB
Yes
Yes
Yes
ROTCL
Rn
0100nnnn00100100
T ← Rn ← T
1
MSB
Yes
Yes
Yes
ROTCR
Rn
0100nnnn00100101
T → Rn → T
1
LSB
Yes
Yes
Yes
SHAD
Rm,Rn
0100nnnnmmmm1100
When Rm ≥ 0, Rn > |Rm| →
[MSB → Rn]
SHAL
Rn
0100nnnn00100000
T ← Rn ← 0
1
MSB
Yes
Yes
Yes
SHAR
Rn
0100nnnn00100001
MSB → Rn → T
1
LSB
Yes
Yes
Yes
SHLD
Rm,Rn
0100nnnnmmmm1101
When Rm ≥ 0, Rn > |Rm| →
[0 → Rn]
SHLL
Rn
0100nnnn00000000
T ← Rn ← 0
1
MSB
Yes
Yes
Yes
SHLR
Rn
0100nnnn00000001
0 → Rn → T
1
LSB
Yes
Yes
Yes
SHLL2
Rn
0100nnnn00001000
Rn > 2 → Rn
1
⎯
Yes
Yes
Yes
SHLL8
Rn
0100nnnn00011000
Rn > 8 → Rn
1
⎯
Yes
Yes
Yes
SHLL16
Rn
0100nnnn00101000
Rn > 16 → Rn
1
⎯
Yes
Yes
Yes
Page 56 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
2.4.6
Section 2 CPU
Branch Instructions
Table 2.15 Branch Instructions
Compatibility
Execution
SH2,
Instruction
Instruction Code
Operation
Cycles T Bit SH2E SH4
BF
10001011dddddddd
When T = 0, disp × 2 + PC →
3/1*
⎯
Yes
Yes
Yes
2/1*
⎯
Yes
Yes
Yes
3/1*
⎯
Yes
Yes
Yes
2/1*
⎯
Yes
Yes
Yes
2
⎯
Yes
Yes
Yes
2
⎯
Yes
Yes
Yes
2
⎯
Yes
Yes
Yes
2
⎯
Yes
Yes
Yes
label
SH-2A
PC,
When T = 1, nop
BF/S
label
10001111dddddddd
Delayed branch
When T = 0, disp × 2 + PC →
PC,
When T = 1, nop
BT
label
10001001dddddddd
When T = 1, disp × 2 + PC →
PC,
When T = 0, nop
BT/S
label
10001101dddddddd
Delayed branch
When T = 1, disp × 2 + PC →
PC,
When T = 0, nop
BRA
label
1010dddddddddddd
Delayed branch,
disp × 2 + PC → PC
BRAF
Rm
0000mmmm00100011
Delayed branch,
Rm + PC → PC
BSR
label
1011dddddddddddd
Delayed branch, PC → PR,
disp × 2 + PC → PC
BSRF
Rm
0000mmmm00000011
Delayed branch, PC → PR,
Rm + PC → PC
JMP
@Rm
0100mmmm00101011
Delayed branch, Rm → PC
2
⎯
Yes
Yes
Yes
JSR
@Rm
0100mmmm00001011
Delayed branch, PC → PR,
2
⎯
Yes
Yes
Yes
PC-2 → PR, Rm → PC
3
⎯
Yes
PC-2 → PR,
5
⎯
Yes
2
⎯
Rm → PC
0100mmmm01001011
JSR/N
@Rm
JSR/N
@@(disp8,TBR) 10000011dddddddd
(disp × 4 + TBR) → PC
RTS
RTS/N
RTV/N
Note:
Rm
*
0000000000001011
Delayed branch, PR → PC
0000000001101011
PR → PC
3
⎯
Yes
0000mmmm01111011
Rm → R0, PR → PC
3
⎯
Yes
Yes
Yes
Yes
One cycle when the program does not branch.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 57 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.4.7
System Control Instructions
Table 2.16 System Control Instructions
Compatibility
Execution
SH2,
Cycles T Bit SH2E SH4
Instruction
Instruction Code
Operation
CLRT
0000000000001000
0→T
1
0
Yes
Yes
Yes
CLRMAC
0000000000101000
0 → MACH,MACL
1
⎯
Yes
Yes
Yes
0100mmmm11100101
(Specified register bank entry) 6
⎯
LDBANK
@Rm,R0
SH-2A
Yes
→ R0
LDC
Rm,SR
0100mmmm00001110
Rm → SR
3
LSB
LDC
Rm,TBR
0100mmmm01001010
Rm → TBR
1
⎯
LDC
Rm,GBR
0100mmmm00011110
Rm → GBR
1
⎯
LDC
Rm,VBR
0100mmmm00101110
Rm → VBR
1
LDC.L
@Rm+,SR
0100mmmm00000111
(Rm) → SR, Rm + 4 → Rm
5
LDC.L
@Rm+,GBR
0100mmmm00010111
(Rm) → GBR, Rm + 4 → Rm
LDC.L
@Rm+,VBR
0100mmmm00100111
LDS
Rm,MACH
LDS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
⎯
Yes
Yes
Yes
LSB
Yes
Yes
Yes
1
⎯
Yes
Yes
Yes
(Rm) → VBR, Rm + 4 → Rm
1
⎯
Yes
Yes
Yes
0100mmmm00001010
Rm → MACH
1
⎯
Yes
Yes
Yes
Rm,MACL
0100mmmm00011010
Rm → MACL
1
⎯
Yes
Yes
Yes
LDS
Rm,PR
0100mmmm00101010
Rm → PR
1
⎯
Yes
Yes
Yes
LDS.L
@Rm+,MACH
0100mmmm00000110
(Rm) → MACH, Rm + 4 → Rm 1
⎯
Yes
Yes
Yes
LDS.L
@Rm+,MACL
0100mmmm00010110
(Rm) → MACL, Rm + 4 → Rm 1
⎯
Yes
Yes
Yes
LDS.L
@Rm+,PR
0100mmmm00100110
(Rm) → PR, Rm + 4 → Rm
1
⎯
Yes
Yes
Yes
NOP
0000000000001001
No operation
1
⎯
Yes
Yes
Yes
RESBANK
0000000001011011
Bank → R0 to R14, GBR,
9*
⎯
6
⎯
Yes
Yes
Yes
Yes
MACH, MACL, PR
0000000000101011
RTE
Delayed branch,
stack area → PC/SR
SETT
0000000000011000
1→T
1
1
Yes
Yes
Yes
SLEEP
0000000000011011
Sleep
5
⎯
Yes
Yes
Yes
0100nnnn11100001
R0 →
7
⎯
STBANK
R0,@Rn
Yes
(specified register bank entry)
STC
SR,Rn
0000nnnn00000010
SR → Rn
2
⎯
STC
TBR,Rn
0000nnnn01001010
TBR → Rn
1
⎯
Page 58 of 1778
Yes
Yes
Yes
Yes
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 2 CPU
Compatibility
Execution
SH2,
Instruction
Instruction Code
Operation
Cycles T Bit SH2E SH4
STC
GBR,Rn
0000nnnn00010010
GBR → Rn
1
⎯
Yes
Yes
Yes
STC
VBR,Rn
0000nnnn00100010
VBR → Rn
1
⎯
Yes
Yes
Yes
STC.L
SR,@-Rn
0100nnnn00000011
Rn-4 → Rn, SR → (Rn)
2
⎯
Yes
Yes
Yes
STC.L
GBR,@-Rn
0100nnnn00010011
Rn-4 → Rn, GBR → (Rn)
1
⎯
Yes
Yes
Yes
STC.L
VBR,@-Rn
0100nnnn00100011
Rn-4 → Rn, VBR → (Rn)
1
⎯
Yes
Yes
Yes
STS
MACH,Rn
0000nnnn00001010
MACH → Rn
1
⎯
Yes
Yes
Yes
STS
MACL,Rn
0000nnnn00011010
MACL → Rn
1
⎯
Yes
Yes
Yes
STS
PR,Rn
0000nnnn00101010
PR → Rn
1
⎯
Yes
Yes
Yes
STS.L
MACH,@-Rn
0100nnnn00000010
Rn-4 → Rn, MACH → (Rn)
1
⎯
Yes
Yes
Yes
STS.L
MACL,@-Rn
0100nnnn00010010
Rn-4 → Rn, MACL → (Rn)
1
⎯
Yes
Yes
Yes
STS.L
PR,@-Rn
0100nnnn00100010
Rn-4 → Rn, PR → (Rn)
1
⎯
Yes
Yes
Yes
TRAPA
#imm
11000011iiiiiiii
PC/SR → stack area,
5
⎯
Yes
Yes
Yes
SH-2A
(imm × 4 + VBR) → PC
Notes:
*
Instruction execution cycles: The execution cycles shown in the table are minimums. In
practice, the number of instruction execution states in cases such as the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is the same
as the register used by the next instruction.
In the event of bank overflow, the number of cycles is 19.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 59 of 1778
SH7280 Group, SH7243 Group
Section 2 CPU
2.4.8
Bit Manipulation Instructions
Table 2.17 Bit Manipulation Instructions
Instruction
BAND.B
#imm3,@(disp12,Rn)
Instruction Code
Operation
Compatibility
Execution
SH2,
SHCycles T Bit SH2E SH4 2A
0011nnnn0iii1001
(imm of (disp + Rn)) & T →
3
Operation
result
Yes
0011nnnn0iii1001 ~(imm of (disp + Rn)) & T → T 3
Operation
result
Yes
3
⎯
Yes
0100dddddddddddd
BANDNOT.B #imm3,@(disp12,Rn)
1100dddddddddddd
BCLR.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 0 → (imm of (disp + Rn))
0000dddddddddddd
BCLR
#imm3,Rn
10000110nnnn0iii 0 → imm of Rn
1
⎯
Yes
BLD.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 (imm of (disp + Rn)) →
3
Operation
result
Yes
0011dddddddddddd
BLD
#imm3,Rn
10000111nnnn1iii imm of Rn → T
1
Operation
result
Yes
BLDNOT.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 ~(imm of (disp + Rn))
1011dddddddddddd → T
3
Operation
result
Yes
BOR.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 ( imm of (disp + Rn)) | T → T
3
Operation
result
Yes
0011nnnn0iii1001 ~( imm of (disp + Rn)) | T → T 3
Operation
result
Yes
3
⎯
Yes
0101dddddddddddd
BORNOT.B
#imm3,@(disp12,Rn)
1101dddddddddddd
BSET.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 1 → ( imm of (disp + Rn))
0001dddddddddddd
BSET
#imm3,Rn
10000110nnnn1iii 1 → imm of Rn
1
⎯
Yes
BST.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 T → (imm of (disp + Rn))
3
⎯
Yes
0010dddddddddddd
BST
#imm3,Rn
10000111nnnn0iii T → imm of Rn
1
⎯
Yes
BXOR.B
#imm3,@(disp12,Rn)
0011nnnn0iii1001 (imm of (disp + Rn)) ^ T → T
3
Operation
result
Yes
0110dddddddddddd
Page 60 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
2.5
Section 2 CPU
Processing States
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Manual reset from any processing state
except software standby mode
Power-on reset from any state
Manual reset state
Power-on reset state
Reset state
Reset canceled
Exception
handling state
Interrupt source or
DMA address error occurs
Bus request
cleared
Bus request
generated
Exception
handling
source
occurs
Bus-released state
Bus request
generated
Bus request
generated
Bus request
cleared
Sleep mode
Exception
handling
ends
Power-on reset
Bus request
cleared
Program execution state
STBY bit cleared
for SLEEP
instruction
STBY bit set
for SLEEP
instruction
Software standby mode
Power-down state
Figure 2.6 Transitions between Processing States
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 61 of 1778
Section 2 CPU
(1)
SH7280 Group, SH7243 Group
Reset State
In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset.
(2)
Exception Handling State
The exception handling state is a transient state that occurs when exception handling sources such
as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception handling vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception handling vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
(3)
Program Execution State
In the program execution state, the CPU sequentially executes the program.
(4)
Power-Down State
In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP
instruction places the CPU in the sleep mode or the software standby mode.
(5)
Bus-Released State
In the bus-released state, the CPU releases bus to a device that has requested it.
Page 62 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Selection of Operating Modes
This LSI has four MCU operating modes and three on-chip flash memory programming modes.
The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows
the allowable combinations of these pin settings; do not set these pins in the other way than the
shown combinations.
When power is applied to the system, be sure to conduct power-on reset.
The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip
mode. For the on-chip flash memory programming mode, boot mode, user boot mode, user
program mode, and USB boot mode (only in SH7285 and SH7286) which are on-chip
programming modes are available.
Table 3.1
Selection of Operating Modes
Pin Setting
Bus Width of CS0 Space
Mode No.
FWE
MD1
MD0 Mode Name
On-Chip ROM
SH7286 SH7285 SH7284
Mode 0
0
0
0
MCU extension mode 0
Not active
32
16
16
Mode 1
0
0
1
MCU extension mode 1
Not active
16
8
8
Mode 2
0
1
0
MCU extension mode 2
Active
Set by CS0BCR in BSC
0
1
1
Single chip mode
Active
⎯
Mode 4
*1
1
0
0
Boot mode
Active
Set by CS0BCR in BSC
Mode 5
*1
1
0
1
User boot mode
Active
Set by CS0BCR in BSC
Mode 6
*1
1
1
0
User program mode
Active
Set by CS0BCR in BSC
Mode 7
*1*2*3
1
1
1
USB boot mode
Active
—
Mode 7
*1*4
1
1
1
User program mode
Active
—
Mode 3
Notes: 1.
2.
3.
4.
Flash memory programming mode.
Setting mode is prohibited in the SH7243.
When always FWE = 1, after the power has been on.
If FWE = 0 starting from power-on and until power-on reset has been released, and if
FWE = 1 when the MCU operation has been set to single-chip mode, transition to the
user program mode is executed in a single chip state.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 63 of 1778
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
3.2
Input/Output Pins
Table 3.2 describes the configuration of operating mode related pin.
Table 3.2
Pin Configuration
Pin Name
Input/Output
Function
MD0
Input
Designates operating mode through the level applied to this pin
MD1
Input
Designates operating mode through the level applied to this pin
FWE
Input
Enables, by hardware, programming/erasing of the on-chip flash
memory
3.3
Operating Modes
3.3.1
Mode 0 (MCU Extension Mode 0)
In this mode, CS0 space becomes external memory spaces with 32-bit bus width (SH7286) or 16bit bus width (SH7285 and SH7243).
3.3.2
Mode 1 (MCU Extension Mode 1)
In this mode, CS0 space becomes external memory spaces with 16-bit bus width (SH7286) 8-bit
bus width (SH7285 and SH7243).
3.3.3
Mode 2 (MCU Extension Mode 2)
In this mode, the on-chip ROM (flash memory) is active and CS0 space can be used in this mode.
3.3.4
Mode 3 (Single Chip Mode)
All ports can be used in this mode, however the external address cannot be used.
Page 64 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
3.4
Section 3 MCU Operating Modes
Address Map
The address map for the operating modes is shown in figure 3.1 to 3.7.
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'000F FFFF
H'0010 0000
H'01FF FFFF
H'0200 0000
On-chip flash memory (1024 Kbytes)
Reserved area
Mode 3
Single chip mode
H'0000 0000
H'000F FFFF
H'0010 0000
On-chip flash memory (1024 Kbytes)
CS0 space
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'07FF FFFF
H'0800 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
CS7 space
H1FFF FFFF
H'2000 0000
H'1FFF FFFF
H'2000 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
H'FFFB FFFF
H'FFFC 0000
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
H'FFFF FFFF
Reserved area
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFF7 FFFF
H'FFF8 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
On-chip peripheral
I/O registers
Reserved area
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.1 SH7286F (1 MB) Address Map for Each Operating Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 65 of 1778
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'000B FFFF
H'000C 0000
H'01FF FFFF
H'0200 0000
On-chip flash memory (768 Kbytes)
Reserved area
Mode 3
Single chip mode
H'0000 0000
H'000B FFFF
H'000C 0000
On-chip flash memory (768 Kbytes)
CS0 space
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'07FF FFFF
H'0800 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
H'1FFF FFFF
H'2000 0000
CS7 space
H1FFF FFFF
H'2000 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
H'FFFF FFFF
Reserved area
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFF7 FFFF
H'FFF8 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (32 Kbytes)
On-chip peripheral
I/O registers
Reserved area
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.2 SH7286F (768 KB) Address Map for Each Operating Mode
Page 66 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'0007 FFFF
H'0008 0000
H'01FF FFFF
H'0200 0000
On-chip flash memory (512 Kbytes)
Reserved area
Mode 3
Single chip mode
H'0000 0000
H'0007 FFFF
H'0008 0000
On-chip flash memory (512 Kbytes)
CS0 space
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'07FF FFFF
H'0800 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
H'1FFF FFFF
H'2000 0000
CS7 space
H1FFF FFFF
H'2000 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (24 Kbytes)
H'FFF8 5FFF
H'FFF8 6000
H'FFFB FFFF
H'FFFC 0000
H'FFFF FFFF
Reserved area
On-chip RAM (24 Kbytes)
H'FFF8 5FFF
H'FFF8 6000
SDRAM mode setting space
Reserved area
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFF7 FFFF
H'FFF8 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (24 Kbytes)
On-chip peripheral
I/O registers
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.3 SH7286F (512 KB) Address Map for Each Operating Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 67 of 1778
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'000B FFFF
H'000C 0000
H'01FF FFFF
H'0200 0000
On-chip flash memory (768 Kbytes)
Reserved area
Mode 3
Single chip mode
H'0000 0000
H'000B FFFF
H'000C 0000
On-chip flash memory (768 Kbytes)
CS0 space
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'07FF FFFF
H'0800 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
H'1FFF FFFF
H'2000 0000
CS7 space
H1FFF FFFF
H'2000 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
H'FFFF FFFF
Reserved area
On-chip RAM (32 Kbytes)
H'FFF8 7FFF
H'FFF8 8000
SDRAM mode setting space
Reserved area
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFF7 FFFF
H'FFF8 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (32 Kbytes)
On-chip peripheral
I/O registers
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.4 SH7285F (768 KB) Address Map for Each Operating Mode
Page 68 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'0007 FFFF
H'0008 0000
H'01FF FFFF
H'0200 0000
On-chip flash memory (512 Kbytes)
Reserved area
Mode 3
Single chip mode
H'0000 0000
H'0007 FFFF
H'0008 0000
On-chip flash memory (512 Kbytes)
CS0 space
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'07FF FFFF
H'0800 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
H'1FFF FFFF
H'2000 0000
CS7 space
H1FFF FFFF
H'2000 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
H'FFF7 FFFF
H'FFF8 0000
H'FFF8 7FFF
H'FFF8 8000
H'FFFB FFFF
H'FFFC 0000
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
H'FFF8 5FFF
H'FFF8 6000
H'FFFB FFFF
H'FFFC 0000
H'FFFF FFFF
Reserved area
On-chip RAM (24 Kbytes)
H'FFF8 5FFF
H'FFF8 6000
SDRAM mode setting space
Reserved area
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (24 Kbytes)
On-chip RAM (24 Kbytes)
On-chip peripheral
I/O registers
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.5 SH7285F (512 KB) Address Map for Each Operating Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 69 of 1778
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'0003 FFFF
H'0004 0000
H'01FF FFFF
H'0200 0000
On-chip flash memory (256 Kbytes)
Reserved area
Mode 3
Single chip mode
H'0000 0000
H'0003 FFFF
H'0004 0000
On-chip flash memory (256 Kbytes)
CS0 space
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'07FF FFFF
H'0800 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
H'1FFF FFFF
H'2000 0000
CS7 space
H1FFF FFFF
H'2000 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
H'FFF8 2FFF
H'FFF8 3000
H'FFFB FFFF
H'FFFC 0000
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (12 Kbytes)
H'FFF8 2FFF
H'FFF8 3000
H'FFFB FFFF
H'FFFC 0000
H'FFFF FFFF
Reserved area
On-chip RAM (12 Kbytes)
H'FFF8 2FFF
H'FFF8 3000
SDRAM mode setting space
Reserved area
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFF7 FFFF
H'FFF8 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (12 Kbytes)
On-chip peripheral
I/O registers
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.6 SH7243F (256 KB) Address Map for Each Operating Mode
Page 70 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
Modes 0 and 1
On-chip ROM disabled mode
H'0000 0000
CS0 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'0001 FFFF
H'0002 0000
H'01FF FFFF
H'0200 0000
CS2 space
CS2 space
H'0BFF FFFF
H'0C00 0000
CS3 space
CS3 space
H'0FFF FFFF
H'1000 0000
H'0FFF FFFF
H'1000 0000
CS4 space
CS4 space
H'13FF FFFF
H'1400 0000
H'13FF FFFF
H'1400 0000
CS5 space
CS5 space
H'17FF FFFF
H'1800 0000
H'17FF FFFF
H'1800 0000
CS6 space
CS6 space
H'1BFF FFFF
H'1C00 0000
H'1BFF FFFF
H'1C00 0000
CS7 space
H'1FFF FFFF
H'2000 0000
CS7 space
H1FFF FFFF
H'2000 0000
Reserved area
H'FFF7 FFFF
H'FFF8 0000
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
H'FFF7 FFFF
H'FFF8 0000
On-chip RAM (8 Kbytes)
On-chip RAM (8 Kbytes)
Reserved area
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
H'FFF8 1FFF
H'FFF8 2000
H'FFFB FFFF
H'FFFC 0000
Reserved area
On-chip RAM (8 Kbytes)
H'FFF8 1FFF
H'FFF8 2000
SDRAM mode setting space
H'FFFC FFFF
H'FFFD 0000
Reserved area
H'FFFF FFFF
CS0 space
H'07FF FFFF
H'0800 0000
H'0BFF FFFF
H'0C00 0000
H'FFFD FFFF
H'FFFE 0000
On-chip flash memory (128 Kbytes)
CS1 space
CS1 space
H'07FF FFFF
H'0800 0000
H'FFFB FFFF
H'FFFC 0000
Reserved area
H'03FF FFFF
H'0400 0000
H'03FF FFFF
H'0400 0000
H'FFF8 2FFF
H'FFF8 3000
On-chip flash memory (128 Kbytes)
Mode 3
Single chip mode
H'0000 0000
H'0001 FFFF
H'0002 0000
On-chip peripheral
I/O registers
Reserved area
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.7 SH7243F (128 KB) Address Map for Each Operating Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 71 of 1778
SH7280 Group, SH7243 Group
Section 3 MCU Operating Modes
3.5
Initial State in This LSI
In the initial state of this LSI, some of on-chip modules are set in module standby state for saving
power. When operating these modules, clear module standby state according to the procedure in
section 28, Power-Down Modes.
3.6
Note on Changing Operating Mode
When changing operating mode while power is applied to this LSI, make sure to do it in the
power-on reset state (that is, the low level is applied to the RES pin).
CK
MD1, MD0
tMDS*
RES
Note: *
See section 31.3.2, Control Signal Timing.
Figure 3.8 Reset Input Timing when Changing Operating Mode
Page 72 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), a bus clock (Bφ), an MTU2S clock (Mφ), and an AD clock (Aφ). The CPG consists of a
crystal oscillator, a PLL circuit, and a divider circuit.
4.1
Features
• Five clocks generated independently
An internal clock (Iφ) for the CPU and cache, a peripheral clock (Pφ) for the peripheral
modules, a bus clock (Bφ = CK) for the external bus interface, an MTU2S clock (Mφ) for the
MTU2S module, and an AD clock (Aφ) for the ADC module can be generated independently.
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software
using frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped for sleep mode and software standby mode, and specific modules can
be stopped using the module standby function. For details on clock control in the power-down
modes, see section 28, Power-Down Modes.
Figure 4.1 shows a block diagram of the clock pulse generator.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 73 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
On-chip oscillator
USBXTAL*
Oscillator
USB clock*
(Uφ :48MHz)
Divider
USBEXTAL*
×1
×1/2
×1/4
×1/8
Internal clock
(Iφ, Max. 100 MHz)
Bus clock
(Bφ = CK, Max. 50 MHz)
Crystal
oscillator
XTAL
PLL circuit
Peripheral clock
(Pφ, Max. 50 MHz)
(×8)
EXTAL
Oscillation stop
detection
Oscillation
stop detection
circuit
MTU2S clock
(Mφ, Max. 100 MHz)
AD clock
(Aφ, Max. 50 MHz)
CK
CPG control unit
Clock frequency
control circuit
OSCCR
FRQCR
MCLKCR
Standby control circuit
ACLKCR
STBCR
STBCR2
STBCR3
STBCR4
STBCR5
STBCR6
Bus interface
HPB bus
[Legend]
FRQCR:
MCLKCR:
ACLKCR:
STBCR:
STBCR2:
Frequency control register
MTU2S clock frequency control register
AD clock frequency control register
Standby control register
Standby control register 2
STBCR3:
STBCR4:
STBCR5:
STBCR6:
OSCCR:
Standby control register 3
Standby control register 4
Standby control register 5
Standby control register 6
Oscillation stop detection control register
Note: * Not applied to the SH7243
Figure 4.1 Block Diagram of Clock Pulse Generator
Page 74 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
(1)
PLL Circuit
The PLL circuit multiplies the input clock frequency from the crystal oscillator or EXTAL pin by
8.
(2)
Crystal Oscillator
The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the
XTAL pin or EXTAL pin. This can be used according to the clock operating mode.
(3)
Divider
The divider generates a clock signal at the operating frequency used by the internal clock (Iφ), bus
clock (Bφ), peripheral clock (Pφ), MTU2S clock (Mφ), or AD clock (Aφ). The operating
frequency can be 1, 1/2, 1/4, or 1/8 times the output frequency of the PLL circuit. The division
ratio is set in the frequency control register (FRQCR). USB clock (Uφ) is set as fixed 1/2 and
when generating USB clock with a divider, set the crystal resonator to 12 MHz.
(4)
Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the frequency control
register (FRQCR).
(5)
Standby Control Circuit
The standby control circuit controls the states of the clock pulse generator and other modules
during clock switching, or sleep or software standby mode.
(6)
Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control bits assigned for the frequency division ratios
of the internal clock (Iφ), bus clock (Bφ), and peripheral clock (Pφ).
(7)
MTU2S Clock Frequency Control Register (MCLKCR)
The MTU2S clock frequency control register (MCLKCR) has control bits assigned for the
frequency division ratio of the MTU2S clock (Mφ).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 75 of 1778
Section 4 Clock Pulse Generator (CPG)
(8)
SH7280 Group, SH7243 Group
AD Clock Frequency Control Register (ACLKCR)
The AD clock frequency control register (ACLKCR) has control bits assigned for the frequency
division ratio of the AD clock (Aφ).
(9)
Standby Control Register
The standby control register has bits for controlling the power-down modes and for selecting the
USB clock. See section 28, Power-Down Modes, for more information.
(10) Oscillation Stop Detection Control Register (OSCCR)
The oscillation stop detection control register (OSCCR) has an oscillation stop detection flag and a
bit for selecting flag status output through an external pin.
(11) USB-only oscillator (SH7285, SH7286)
The oscillator for USB clock only that is connected to the resonator of 48 MHz.
Page 76 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
4.2
Section 4 Clock Pulse Generator (CPG)
Input/Output Pins
Table 4.1 lists the clock pulse generator pins and their functions.
Table 4.1
Pin Configuration and Functions of the Clock Pulse Generator
Pin Name
Symbol
I/O
Function
Crystal input/output XTAL
pins (clock input
pins)
EXTAL
Input
Clock output pin
Output Clock output pin. This pin can be placed in high-impedance state.
CK
Crystal input/output USBXTAL
pins for USB (clock
input pins)
USBEXTAL
Output Connected to the crystal resonator. (Leave this pin open when the
crystal resonator is not in use.)
Connected to the crystal resonator or used to input an external
clock.
Output Connected to the crystal resonator for USB (equivalent for
CSTCZ48M0X11R). Leave this pin open when the crystal
resonator is not in use.
Input
Connected to the crystal resonator for USB (equivalent for
CSTCZ48M0X11R). Connect this pin to Vss when the crystal
resonator is not in use.
To use the clock output (CK) pin, appropriate settings may be needed in the pin function controller
(PFC) in some cases. For details, refer to section 23, Pin Function Controller (PFC).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 77 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
4.3
Clock Operating Modes
Table 4.2 shows the clock operating modes of this LSI.
Table 4.2
Clock Operating Modes
Clock I/O
Mode
Source
Output
PLL Circuit
Input to Divider
1
EXTAL input or
crystal resonator
CK*
On (× 8)
×8
Note:
*
To output the clock through the CK pin, appropriate settings should be made in the
PFC. For details, refer to section 23, Pin Function Controller (PFC).
The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL
circuit before it is supplied to the on-chip modules in this LSI, which eliminates the need to
generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 10
MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 100
MHz.
Maximum operating frequencies:
Iφ = 100 MHz, Bφ = 50 MHz, Pφ = 50 MHz, Mφ = 100 MHz, Aφ = 50 MHz
Table 4.3 shows examples of the ranges of the frequency division ratios that can be specified with
FRQCR.
Page 78 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 4.3
Section 4 Clock Pulse Generator (CPG)
Clock Operating Modes and Settable Frequency Range Examples
PLL
FRQCR/MCLKCR/ACLKCR
MultipliDivision Ratio Setting
cation
Iφ
Bφ
Pφ
Mφ
Aφ
Ratio
×8
Clock Ratio
Clock Frequency (MHz)*
Iφ
Bφ
Pφ
Mφ
Aφ
Input Clock
Iφ
Bφ
Pφ
Mφ
Aφ
1/4
1/4
1/8
1/4
1/4
2
2
1
2
2
10
20
20
10
20
20
1/4
1/4
1/4
1/4
1/4
2
2
2
2
2
20
20
20
20
20
1/2
1/4
1/8
1/4
1/4
4
2
1
2
2
40
20
10
20
20
1/2
1/4
1/8
1/2
1/4
4
2
1
4
2
40
20
10
40
20
1/2
1/4
1/4
1/4
1/4
4
2
2
2
2
40
20
20
20
20
1/2
1/4
1/4
1/2
1/4
4
2
2
4
2
40
20
20
40
20
1/2
1/2
1/8
1/4
1/4
4
4
1
2
2
40
40
10
20
20
1/2
1/2
1/8
1/2
1/8
4
4
1
4
2
40
40
10
40
20
1/2
1/2
1/8
1/2
1/2
4
4
1
4
4
40
40
10
40
40
1/2
1/2
1/4
1/4
1/4
4
4
2
2
2
40
40
20
20
20
1/2
1/2
1/4
1/2
1/4
4
4
2
4
2
40
40
20
40
20
1/2
1/2
1/4
1/2
1/2
4
4
2
4
4
40
40
20
40
40
1/2
1/2
1/2
1/2
1/2
4
4
4
4
4
40
40
40
40
40
1/1
1/4
1/8
1/4
1/4
8
2
1
2
2
80
20
10
20
20
1/1
1/4
1/8
1/2
1/4
8
2
1
4
2
80
20
10
40
20
1/1
1/4
1/8
1/1
1/4
8
2
1
8
2
80
20
10
80
20
1/1
1/4
1/4
1/4
1/4
8
2
2
2
2
80
20
20
20
20
1/1
1/4
1/4
1/2
1/4
8
2
2
4
2
80
20
20
40
20
1/1
1/4
1/4
1/1
1/4
8
2
2
8
2
80
20
20
80
20
1/1
1/2
1/8
1/4
1/4
8
4
1
2
2
80
40
10
20
20
1/1
1/2
1/8
1/2
1/4
8
4
1
4
2
80
40
10
40
20
1/1
1/2
1/8
1/2
1/2
8
4
1
4
4
80
40
10
40
40
1/1
1/2
1/8
1/1
1/4
8
4
1
8
2
80
40
10
80
20
1/1
1/2
1/8
1/1
1/2
8
4
1
8
4
80
40
10
80
40
1/1
1/2
1/4
1/4
1/4
8
4
2
2
2
80
40
20
20
20
1/1
1/2
1/4
1/2
1/4
8
4
2
4
2
80
40
20
40
20
1/1
1/2
1/4
1/2
1/2
8
4
2
4
4
80
40
20
40
40
1/1
1/2
1/4
1/1
1/4
8
4
2
8
2
80
40
20
80
20
1/1
1/2
1/4
1/1
1/2
8
4
2
8
4
80
40
20
80
40
1/1
1/2
1/2
1/2
1/2
8
4
4
4
4
80
40
40
40
40
1/1
1/2
1/2
1/1
1/2
8
4
4
8
4
80
40
40
80
40
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 79 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
PLL
FRQCR/MCLKCR/ACLKCR
MultipliDivision Ratio Setting
cation
Iφ
Bφ
Pφ
Mφ
Aφ
Ratio
×8
Notes:
Clock Ratio
Clock Frequency (MHz)*
Iφ
Bφ
Pφ
Mφ
Aφ
Input Clock
Iφ
Bφ
Pφ
Mφ
Aφ
1/1
1/2
1/4
1/4
1/4
8
4
2
2
2
12.5
100
50
25
25
25
1/1
1/2
1/4
1/2
1/4
8
4
2
4
2
100
50
25
50
25
1/1
1/2
1/4
1/2
1/2
8
4
2
4
4
100
50
25
50
50
1/1
1/2
1/4
1/1
1/4
8
4
2
8
2
100
50
25
100
25
1/1
1/2
1/4
1/1
1/2
8
4
2
8
4
100
50
25
100
50
1/1
1/2
1/2
1/2
1/2
8
4
4
4
4
100
50
50
50
50
1/1
1/2
1/2
1/1
1/2
8
4
4
8
4
100
50
50
100
50
* Clock frequencies when the input clock frequency is assumed to be the shown value.
1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1, ×1/2, ×1/4,
and ×1/8 for each clock by the setting in the frequency control register.
2. The output frequency of the PLL circuit is obtained by multiplication of the frequency of the input
from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. This
output frequency must be 100 MHz or lower.
3. The input to the divider is always the output from the PLL circuit.
4. The internal clock (Iφ) frequency is obtained by multiplication of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio
of the divider. The resultant frequency of the internal clock (Iφ) must not exceed 100 MHz
(maximum operating frequency) or lower.
5. The bus clock (Bφ) frequency is obtained by multiplication of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio
of the divider. The resultant frequency of the bus clock (Bφ) must not exceed 50 MHz or the
internal clock (Iφ) frequency.
6. The peripheral clock (Pφ) frequency is obtained by multiplication of the frequency of the input from
the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division
ratio of the divider. The resultant frequency of the peripheral clock (Pφ) must not exceed 50 MHz or
the bus clock (Bφ) frequency.
7. When using the MTU2S, the MTU2S clock (Mφ) frequency must not exceed the internal clock (Iφ)
frequency and also be equal to or higher than Pφ and Bφ. The MTU2S clock (Mφ) frequency is
obtained by multiplication of the frequency of the input from the crystal resonator or EXTAL pin, the
multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider.
8. The frequency of the CK pin output is always equal to the bus clock (Bφ) frequency.
9.
When using the AD, the AD clock (Aφ) frequency must be equal to or higher than the peripheral
clock (Pφ) frequency.
10. When using the USB, the peripheral clock (Pφ) frequency must be 13 MHz or higher.
11. Uφ must be fixed to 48 MHz. When generating Uφ from the divider, input the clock 12 MHz or
connect the crystal resonator of 12MHz to the EXTAL or XTAL.
Page 80 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
4.4
Section 4 Clock Pulse Generator (CPG)
Register Descriptions
The clock pulse generator has the following registers.
Table 4.4
Register Configuration
Register Name
Abbreviation R/W
Initial Value Address
Frequency control register
FRQCR
R/W
H'0333
H'FFFE0010 16
MTU2S clock frequency
control register
MCLKCR
R/W
H'43
H'FFFE0410 8
AD clock frequency control
register
ACLKCR
R/W
H'43
H'FFFE0414 8
Oscillation stop detection
control register
OSCCR
R/W
H'00
H'FFFE001C 8
4.4.1
Access Size
Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify the frequency division ratios for the
internal clock (Iφ), bus clock (Bφ), and peripheral clock (Pφ). FRQCR can be accessed only in
word units. After setting FRQCR to a new value, read it to confirm that it actually holds the new
value, then execute NOP instructions for 32 cycles of Pφ. FRQCR should be modified by a
program in the on-chip ROM or on-chip RAM. Additionally, make settings for individual modules
after setting FRQCR*.
FRQCR is initialized to H'0333 only by a power-on reset. FRQCR retains its previous value by a
manual reset or in software standby mode. The previous value is also retained when an internal
reset is triggered by an overflow of the WDT.
When switching the division ratio of bus clock frequency, the CK pin is fixed at low level for a
cycle of an input clock so as to prevent a hazard of switching.
Note: * A register that is initialized in software standby mode is also initialized when the
FRQCR setting is changed.
Bit: 15
14
13
12
11
-
-
-
-
-
Initial value: 0
R/W: R
0
R
0
R
0
R
0
R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
10
9
8
STC[2:0]
0
R/W
1
R/W
7
6
-
1
R/W
0
R
5
4
IFC[2:0]
0
R/W
1
R/W
3
2
-
1
R/W
0
R
1
0
PFC[2:0]
0
R/W
1
R/W
1
R/W
Page 81 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
Bit
Bit Name
Initial
Value
R/W
Description
15 to 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8
STC[2:0]
011
R/W
Bus Clock (Bφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
bus clock.
000: × 1
001: × 1/2
010: Setting prohibited
011: × 1/4
100: Setting prohibited
101: × 1/8
Others: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
IFC[2:0]
011
R/W
Internal Clock (Iφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock.
000: × 1
001: × 1/2
010: Setting prohibited
011: × 1/4
100: Setting prohibited
101: × 1/8
Others: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 82 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PFC[2:0]
011
R/W
Peripheral Clock (Pφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock.
000: × 1
001: × 1/2
010: Setting prohibited
011: × 1/4
100: Setting prohibited
101: × 1/8
Others: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 83 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
4.4.2
MTU2S Clock Frequency Control Register (MCLKCR)
MCLKCR is an 8-bit readable/writable register. MCLKCR can be accessed only in byte units.
MCLKCR is initialized to H'43 only by a power-on reset. MCLKCR retains its previous value by
a manual reset or in software standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
-
-
-
-
-
-
0
R
1
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
1
0
MSDIVS[1:0]
1
R/W
1
R/W
This bit is always read as 0. The write value should
always be 0.
6
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
MSDIVS[1:0] 11
R/W
Division Ratio Select
These bits specify the frequency division ratio of the
source clock. Set these bits so that the output clock is
100 MHz or less, and also an integer multiple of the
peripheral clock frequency (Pφ).
00: × 1
01: × 1/2
10: Setting prohibited
11: × 1/4
Page 84 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
4.4.3
Section 4 Clock Pulse Generator (CPG)
AD Clock Frequency Control Register (ACLKCR)
ACLKCR is an 8-bit readable/writable register that can be accessed only in byte units. ACLKCR
is initialized to H'43 only by a power-on reset, but retains its previous value by a manual reset or
in software standby mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
-
-
-
-
-
-
0
R
1
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
7
⎯
0
R
1
0
ASDIVS[1:0]
1
R/W
1
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
6
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
ASDIVS[1:0] 11
R/W
Division Ratio Select
These bits specify the frequency division ratio of the
source clock. Set these bits so that the output clock is
50 MHz or less, and also an integer multiple of the
peripheral clock frequency (Pφ).
00: × 1
01: × 1/2
10: Setting prohibited
11: × 1/4
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 85 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
4.4.4
Oscillation Stop Detection Control Register (OSCCR)
OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects
flag status output to an external pin. OSCCR can be accessed only in byte units.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
OSC
STOP
-
OSC
ERS
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
OSCSTOP
0
R/W
Oscillation Stop Detection Flag
[Setting condition]
•
When a stop in the clock input is detected during
normal operation
[Clearing condition]
•
1
⎯
0
R
By a power-on reset input through the RES pin
Reserved
This bit is always read as 0. The write value should
always be 0.
0
OSCERS
0
R/W
Oscillation Stop Detection Flag Output Select
Selects whether to output the oscillation stop
detection flag signal through the WDTOVF pin.
0: Outputs only the WDT overflow signal through the
WDTOVF pin
1: Outputs the WDT overflow signal and oscillation
stop detection flag signal through the WDTOVF
pin
Page 86 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
4.5
Section 4 Clock Pulse Generator (CPG)
Changing the Frequency
Selecting division ratios for the frequency divider can change the frequencies of the internal clock,
bus clock, peripheral clock, MTU2S clock, and AD clock under the software control through the
frequency control register (FRQCR), MTU2S clock frequency control register (MCKCR), and AD
clock frequency control register (ACLKCR). The following describes how to specify the
frequencies.
1. In the initial state, IFC2 to IFC0 = B'011 (×1/4), STC2 to STC0 = B'011 (×1/4), PFC2 to PFC0
= B'011 (×1/4), MSDIVS1 and MSDIVS0 = 11 (×1/4), and ASDIVS1 and ASDIVS 0 = 11
(×1/4).
2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM.
3. Set the desired values in bits IFC2 to IFC0, STC2 to STC0, PFC2 to PFC0, MSDIVS1,
MSDIVS0, ASDIVS1, and ASDIVS 0. When specifying the frequencies, satisfy the following
condition: internal clock (Iφ) ≥ bus clock (Bφ) ≥ peripheral clock (Pφ). When using the
MTU2S clock, specify the frequencies to satisfy the following condition: internal clock (Iφ) ≥
MTU2S clock (MIφ) ≥ peripheral clock (Pφ).
4. The clock frequencies are immediately changed to the specified values after FRQCR setting is
completed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 87 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
4.6
Oscillator
The source of click supply can be selected from a connected crystal resonator or an external clock
input through a pin.
4.6.1
Connecting Crystal Resonator
A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd)
shown in table 4.5. Use a crystal resonator that has a resonance frequency of 10 to 12.5 MHz.
It is recommended to consult the crystal resonator manufacturer concerning the compatibility of
the crystal resonator and the LSI.
CL1
EXTAL
XTAL
Rd
CL2
CL1 = CL2 = 18 to 22 pF (reference value)
Figure 4.2 Example of Crystal Resonator Connection
Table 4.5
Damping Resistance Values (Reference Values)
Frequency (MHz)
10
12.5
Rd (Ω) (reference value)
0
0
Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the
characteristics shown in table 4.6.
CL
L
RS
XTAL
EXTAL
C0
Figure 4.3 Crystal Resonator Equivalent Circuit
Page 88 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 4.6
Section 4 Clock Pulse Generator (CPG)
Crystal Resonator Characteristics
Frequency (MHz)
10
12.5
Rs max. (Ω) (reference value)
60
50
C0 max. (pF) (reference value)
7
7
4.6.2
External Clock Input Method
Figure 4.4 shows an example of an external clock input connection. Drive the external clock high
when it is stopped in software standby mode. During operation, input an external clock with a
frequency of 10 to 12.5 MHz. Make sure the parasitic capacitance of the XTAL pin is 10 pF or
less.
Even when inputting an external clock, be sure to wait at least for the oscillation settling time in
power-on sequence or in canceling software standby mode, in order to ensure the PLL settling
time.
EXTAL
XTAL
External clock input
Open state
Figure 4.4 Example of External Clock Connection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 89 of 1778
Section 4 Clock Pulse Generator (CPG)
4.7
SH7280 Group, SH7243 Group
Oscillation Stop Detection
The CPG detects a stop in the clock input if any system abnormality halts the clock supply.
When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in
OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin. If
the OSCERS bit is 1 at this time, an oscillation stop detection flag signal is output through the
WDTOVF pin. In addition, the high-current ports (multiplexed pins to which the TIOC3B,
TIOC3D, and TIOC4A to TIOC4D signals in the MTU2, the TIOC3BS, TIOC3DS, and TIOC4AS
to TIOC4DS in the MTU2S are assigned) can be placed in high-impedance state regardless of the
OSCERS bit and PFC settings. For details, refer to appendix A, Pin States.
Even in software standby mode, these pins are placed in high-impedance state. For details, refer to
appendix A, Pin States. Under an abnormal condition where oscillation stops while the LSI is not
in software standby mode, LSI operations other than the oscillation stop detection function
become unpredictable. In this case, even after oscillation is restarted, LSI operations including the
above high-current pins become unpredictable.
Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues
oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and
operating voltage).
Page 90 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
4.8
Section 4 Clock Pulse Generator (CPG)
USB Operating Clock (48 MHz)
Connection of a ceramic resonator for USB, input of an external 48-MHz clock signal, and
selection of the internal CPG are available as methods for supplying the USB operating clock.
4.8.1
Connecting a Ceramic Resonator
Figure 4.5 shows an example of the connections for a ceramic resonator.
USBEXTAL
Ceramic
resonator
Rf
USBXTAL
Rd
Note:
Ceramic resonator: CSTCW48M0X11***-R0
(Murata Manufacturing Co., Ltd.)
Contact your Murata manufacturing sales agency for details
of Rf and Rd values.
Ta = 0 to +70°C
*** represents a three-digit alphanumeric which express "Individual Specification".
Since the frequency for USB requires high accuracy, the official product name will be
decided to match the frequency after evaluation of oscillation on the board that is
actually to be used.
Please contact your Renesas Electronics sales agency.
Figure 4.5 Example of Connecting a Ceramic Resonator
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 91 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
4.8.2
Input of an External 48-MHz Clock Signal
Figure 4.6 shows an example of the connections for input of an external 48-MHz clock signal. The
USBXTAL pin must be left open.
Input external clock
USBEXTAL
Open state
USBXTAL
Figure 4.6 Example of Connecting an External 48-MHz Clock
Table 4.7 shows the input conditions for the external 48-MHz clock.
Table 4.7
Input Conditions for the External 48-MHz Clock
Item
Symbol
Min.
Max.
Unit
Reference Figure
Frequency (48 MHz)
tFREQ
47.88
48.12
MHz
Figure 4.7
Clock rise time
tR48
—
3
ns
Clock fall time
tF48
—
3
ns
Duty (tHIGH/tFREQ)
tDUTY
40
60
%
tFREQ
tHIGH
tLOW
90%
VCC×5
USBEXTAL
10%
tR48
tF48
Figure 4.7 Input Timing of External 48-MHz Clock
Page 92 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
4.8.3
Section 4 Clock Pulse Generator (CPG)
Handling of pins when a Ceramic Resonator is not Connected (the Internal CPG is
Selected or the USB is Not in Use)
When a ceramic resonator is not connected, connect the USBEXTAL pin to ground (Vss) and
leave the USBEXTAL pin open-circuit as shown in Figure 4.8. Possible clock frequencies for
input to EXTAL are fixed to 12 MHz.
USBEXTAL
USBXTAL
Open state
Figure 4.8 Handling of Pins when a Ceramic Resonator is not Connected
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 93 of 1778
SH7280 Group, SH7243 Group
Section 4 Clock Pulse Generator (CPG)
4.9
Notes on Board Design
4.9.1
Note on Using an External Crystal Resonator
Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as
possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency,
the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring
wiring patterns close to these components.
Signal lines prohibited
CL2
CL1
EXTAL
XTAL
This LSI
Reference value
CL1 = 20 pF
CL2 = 20 pF
Note: The values for CL1 and CL2
should be determined after
consultation with the crystal
resonator manufacturer.
Figure 4.9 Note on Using a Crystal Resonator
A circuitry shown in figure 4.10 is recommended as an external circuitry around the PLL. PLLVss
must be separated from Vcc and Vss at the board power supply source. Be sure to insert bypass
capacitors CB and CPB close to the Vcc and Vss pins.
PLLVSS
VCL
CPB = 0.1 µF*
VCC
CB = 0.1 µF*
VSS
Note: * CB and CPB are laminated ceramic capacitors.
(Recommended values are shown.)
Figure 4.10 Recommended External Circuitry around PLL
Page 94 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 5 Exception Handling
Section 5 Exception Handling
5.1
Overview
5.1.1
Types of Exception Handling and Priority
Exception handling is started by sources, such as resets, address errors, register bank errors,
interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling
sources occur at once, they are processed according to the priority shown.
Table 5.1
Types of Exception Handling and Priority Order
Type
Exception Handling
Priority
Reset
Power-on reset
High
Manual reset
Address
error
DMAC address error
CPU address error
Instruction
Integer division exception (division by zero)
Integer division exception (overflow)
Register
bank error
Bank underflow
Bank overflow
Interrupt
NMI
User break
H-UDI
IRQ
On-chip peripheral modules
A/D converter (ADC)
Controller area network (RCAN-ET)
Direct memory access controller (DMAC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
USB function module (USB) DTC transfer
end
Multi-function timer pulse unit 2 (MTU2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Low
Page 95 of 1778
SH7280 Group, SH7243 Group
Section 5 Exception Handling
Type
Exception Handling
Interrupt
On-chip peripheral modules
Priority
Port output enable 2 (POE2): OEI1 and
OEI2 interrupts
High
Multi-function timer pulse unit 2S (MTU2S)
Port output enable 2 (POE2): OEI3
interrupt
USB function module (USB) USI0/USI1
I2C bus interface 3 (IIC3)
Synchronous serial communication unit
(SSU)
Serial communication interface (SCI)
Serial communication interface with FIFO
(SCIF)
Instruction
Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
1
2
branch instruction* , instructions that rewrite the PC* , 32-bit
3
instructions* , RESBANK instruction, DIVS instruction, and DIVU
instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Page 96 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.1.2
Section 5 Exception Handling
Exception Handling Operations
The exception handling sources are detected and begin processing according to the timing shown
in table 5.2.
Table 5.2
Timing of Exception Source Detection and Start of Exception Handling
Exception
Source
Timing of Source Detection and Start of Handling
Reset
Power-on reset
Starts when the RES pin changes from low to high, when the
H-UDI reset negate command is set after the H-UDI reset
assert command has been set, or when the WDT overflows.
Manual reset
Starts when the MRES pin changes from low to high or when
the WDT overflows.
Address error
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Interrupts
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Register bank Bank underflow
error
Starts upon attempted execution of a RESBANK instruction
when saving has not been performed to register banks.
Bank overflow
Instructions
In the state where saving has been performed to all register
bank areas, starts when acceptance of register bank overflow
exception has been set by the interrupt controller (the BOVE bit
in IBNR of the INTC is 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
Trap instruction
Starts from the execution of a TRAPA instruction.
General illegal
instructions
Starts from the decoding of undefined code anytime except
immediately after a delayed branch instruction (delay slot).
Slot illegal
instructions
Starts from the decoding of undefined code placed immediately
after a delayed branch instruction (delay slot), of instructions
that rewrite the PC, of 32-bit instructions, of the RESBANK
instruction, of the DIVS instruction, or of the DIVU instruction.
Integer division
instructions
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by −1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 97 of 1778
Section 5 Exception Handling
SH7280 Group, SH7243 Group
When exception handling starts, the CPU operates as follows:
(1)
Exception Handling Triggered by Reset
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004
addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets).
See section 5.1.3, Exception Handling Vector Table, for more information. The vector base
register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the
status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN
bit in IBNR of the interrupt controller (INTC) is also initialized to 0. The program begins running
from the PC address fetched from the exception handling vector table.
(2)
Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts,
and Instructions
SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling
other than NMI or UBC with usage of the register banks enabled, general registers R0 to R14,
control register GBR, system registers MACH, MACL, and PR, and the vector table address offset
of the interrupt exception handling to be executed are saved to the register banks. In the case of
exception handling due to an address error, register bank error, NMI interrupt, UBC interrupt, or
instruction, saving to a register bank is not performed. When saving is performed to all register
banks, automatic saving to the stack is performed instead of register bank saving. In this case, an
interrupt controller setting must have been made so that register bank overflow exceptions are not
accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow
exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow
exception will be generated. In the case of interrupt exception handling, the interrupt priority level
is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or
instruction, the I3 to I0 bits are not affected. The start address is then fetched from the exception
handling vector table and the program begins running from that address.
Page 98 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.1.3
Section 5 Exception Handling
Exception Handling Vector Table
Before exception handling begins running, the exception handling vector table must be set in
memory. The exception handling vector table stores the start addresses of exception service
routines. (The reset exception handling table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception handling, the start addresses of
the exception service routines are fetched from the exception handling vector table, which is
indicated by this vector table address.
Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector
table addresses are calculated.
Table 5.3
Exception Handling Vector Table
Vector
Numbers
Vector Table Address Offset
PC
0
H'00000000 to H'00000003
SP
1
H'00000004 to H'00000007
PC
2
H'00000008 to H'0000000B
SP
3
H'0000000C to H'0000000F
General illegal instruction
4
H'00000010 to H'00000013
(Reserved by system)
5
H'00000014 to H'00000017
Slot illegal instruction
6
H'00000018 to H'0000001B
(Reserved by system)
7
H'0000001C to H'0000001F
8
H'00000020 to H'00000023
9
H'00000024 to H'00000027
Exception Sources
Power-on reset
Manual reset
CPU address error
DMAC address error
10
H'00000028 to H'0000002B
NMI
11
H'0000002C to H'0000002F
User break
12
H'00000030 to H'00000033
(Reserved by system)
13
H'00000034 to H'00000037
H-UDI
14
H'00000038 to H'0000003B
Bank overflow
15
H'0000003C to H'0000003F
Bank underflow
16
H'00000040 to H'00000043
Interrupts
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 99 of 1778
SH7280 Group, SH7243 Group
Section 5 Exception Handling
Vector
Numbers
Vector Table Address Offset
Integer division exception
(division by zero)
17
H'00000044 to H'00000047
Integer division exception (overflow)
18
H'00000048 to H'0000004B
(Reserved by system)
19
H'0000004C to H'0000004F
Exception Sources
:
Trap instruction (user vector)
31
H'0000007C to H'0000007F
32
H'00000080 to H'00000083
:
External interrupts (IRQ),
on-chip peripheral module interrupts*
*
Table 5.4
:
63
H'000000FC to H'000000FF
64
H'00000100 to H'00000103
:
511
Note:
:
:
H'000007FC to H'000007FF
The vector numbers and vector table address offsets for each external interrupt and onchip peripheral module interrupt are given in table 6.4 in section 6, Interrupt Controller
(INTC).
Calculating Exception Handling Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, register bank
errors, interrupts, instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. Vector table address offset: See table 5.3.
2. Vector number: See table 5.3.
Page 100 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.2
Resets
5.2.1
Types of Reset
Section 5 Exception Handling
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 5.5, the CPU state is initialized in both a power-on reset and a
manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a
manual reset.
Table 5.5
Exception Source Detection and Exception Handling Start Timing
Conditions for Transition to Reset State
Type
Power-on
reset
Manual
reset
Note:
*
RES or
MRES
Internal States
On-Chip
Peripheral
Modules, I/O Port
WRCSR of WDT,
FRQCR of CPG
H-UDI Command
WDT
Overflow
CPU
Low
—
—
Initialized Initialized
Initialized
High
H-UDI reset assert —
command is set
Initialized Initialized
Initialized
High
Command other
than H-UDI reset
assert is set
Power-on
reset
Initialized Initialized
Not initialized
Low
—
—
Initialized Not initialized*
Not initialized
High
—
Manual
reset
Initialized Not initialized*
Not initialized
The BN bit in IBNR of the INTC is initialized.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 101 of 1778
Section 5 Exception Handling
5.2.2
(1)
SH7280 Group, SH7243 Group
Power-On Reset
Power-On Reset by Means of RES Pin
When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this
LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at
power-on or when in software standby mode (when the clock is halted), or at least 20 tcyc when the
clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip
peripheral module registers are initialized. See appendix A, Pin States, for the status of individual
pins during the power-on reset state.
In the power-on reset state, power-on reset exception handling starts when the RES pin is first
driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized. The BN bit in IBNR of the INTC is also initialized to 0.
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
(2)
Power-On Reset by Means of H-UDI Reset Assert Command
When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on
reset by means of an H-UDI reset assert command is equivalent to power-on reset by means of the
RES pin. Setting the H-UDI reset negate command cancels the power-on reset state. The time
required between an H-UDI reset assert command and H-UDI reset negate command is the same
as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state
generated by an H-UDI reset assert command, setting the H-UDI reset negate command starts
power-on reset exception handling. The CPU operates in the same way as when a power-on reset
was caused by the RES pin.
Page 102 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 5 Exception Handling
Power-On Reset Initiated by WDT
When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode,
and WTCNT of the WDT overflows, this LSI enters the power-on reset state.
In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal
generated by the WDT.
If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a
reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert
command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset
exception processing is started by the WDT, the CPU operates in the same way as when a poweron reset was caused by the RES pin.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 103 of 1778
Section 5 Exception Handling
5.2.3
(1)
SH7280 Group, SH7243 Group
Manual Reset
Manual Reset by Means of MRES Pin
When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without
fail, the MRES pin should be kept at the low level for at least 20 tcyc. In the manual reset state, the
CPU’s internal state is initialized, but all the on-chip peripheral module registers are not
initialized. In the manual reset state, manual reset exception handling starts when the MRES pin is
first driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized. The BN bit in IBNR of the INTC is also initialized to 0.
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.
(2)
Manual Reset Initiated by WDT
When a setting is made for a manual reset to be generated in the WDT’s watchdog timer mode,
and WTCNT of the WDT overflows, this LSI enters the manual reset state.
When manual reset exception processing is started by the WDT, the CPU operates in the same
way as when a manual reset was caused by the MRES pin.
When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the
bus is released or during DMAC burst transfer, manual reset exception handling will be deferred
until the CPU acquires the bus. However, if the interval from generation of the manual reset until
the end of the bus cycle is equal to or longer than the fixed internal manual reset interval cycles,
the internal manual reset source is ignored instead of being deferred, and manual reset exception
handling is not executed.
Page 104 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 5 Exception Handling
5.3
Address Errors
5.3.1
Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 5.6.
Table 5.6
Bus Cycles and Address Errors
Bus Cycle
Type
Instruction
fetch
Data
read/write
Bus
Master
Bus Cycle Description
Address Errors
CPU
Instruction fetched from even address
None (normal)
Instruction fetched from odd address
Address error occurs
Instruction fetched from other than on-chip
peripheral module space* or H'F0000000 to
H'F5FFFFFF in on-chip RAM space*
None (normal)
Instruction fetched from on-chip peripheral
module space* or H'F0000000 to
H'F5FFFFFF in on-chip RAM space*
Address error occurs
Instruction fetched from external memory
space in single-chip mode
Address error occurs
Word data accessed from even address
None (normal)
Word data accessed from odd address
Address error occurs
Longword data accessed from a longword
boundary
None (normal)
Longword data accessed from other than a
longword boundary
Address error occurs
Double longword data accessed from a
double longword boundary
None (normal)
Double longword data accessed from other
than a double longword boundary
Address error occurs
Byte or word data accessed in on-chip
peripheral module space*
None (normal)
Longword data accessed in 16-bit on-chip
peripheral module space*
None (normal)
Longword data accessed in 8-bit on-chip
peripheral module space*
None (normal)
External memory space accessed when in
single chip mode
Address error occurs
CPU,
DMAC, or
DTC
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 105 of 1778
Section 5 Exception Handling
Note:
5.3.2
*
SH7280 Group, SH7243 Group
See section 9, Bus State Controller (BSC), for details of the on-chip peripheral module
space and on-chip RAM space.
Address Error Exception Handling
When an address error occurs, the bus cycle in which the address error occurred ends*. When the
executing instruction then finishes, address error exception handling starts. The CPU operates as
follows:
1. The exception service routine start address which corresponds to the address error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
Note: * In the case of an address error caused by instruction fetching when data is read or
written, if the bus cycle on which the address error occurred is not completed by the
end of the operations described above operation 3, the CPU will recommence address
error exception processing until the end of that bus cycle.
Page 106 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.4
Register Bank Errors
5.4.1
Register Bank Error Sources
(1)
Section 5 Exception Handling
Bank Overflow
In the state where saving has already been performed to all register bank areas, bank overflow
occurs when acceptance of register bank overflow exception has been set by the interrupt
controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
(2)
Bank Underflow
Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving
has not been performed to register banks.
5.4.2
Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. The CPU operates
as follows:
1. The exception service routine start address which corresponds to the register bank error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction for a bank overflow, and the start
address of the executed RESBANK instruction for a bank underflow.
To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level
that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status
register (SR).
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 107 of 1778
SH7280 Group, SH7243 Group
Section 5 Exception Handling
5.5
Interrupts
5.5.1
Interrupt Sources
Table 5.7 shows the sources that start up interrupt exception handling. These are divided into
NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules.
Table 5.7
Interrupt Sources
Type
Request Source
Number of
Sources
NMI
NMI pin (external input)
1
User break
User break controller (UBC)
1
H-UDI
User debugging interface (H-UDI)
1
IRQ
IRQ0 to IRQ7 pins (external input)
8
On-chip peripheral module
A/D converter (ADC)
3
Controller area network (RCAN-ET)
4
Direct memory access controller (DMAC)
16
Compare match timer (CMT)
2
Bus state controller (BSC)
1
Watchdog timer (WDT)
1
USB function module (USB)
4
Multi-function timer pulse unit 2 (MTU2)
28
Multi-function timer pulse unit 2S (MTU2S)
13
Port output enable 2 (POE2)
3
2
I C bus interface 3 (IIC3)
5
Synchronous serial communication unit (SSU)
3
Serial communication interface (SCI)
16
Serial communication interface with FIFO (SCIF)
4
Each interrupt source is allocated a different vector number and vector table offset. See table 6.4
in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table
address offsets.
Page 108 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.5.2
Section 5 Exception Handling
Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller (INTC) determines their relative priorities and starts processing
according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels
of IRQ interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt
priority registers 01, 02, and 05 to 18 (IPR01, IPR02, and IPR05 to IPR18) of the INTC as shown
in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section
6.3.1, Interrupt Priority Registers 01, 02, 05 to 18 (IPR01, IPR02, IPR05 to IPR18), for details of
IPR01, IPR02, and IPR05 to IPR18.
Table 5.8
Interrupt Priority Order
Type
Priority Level
Comment
NMI
16
Fixed priority level. Cannot be masked.
User break
15
Fixed priority level.
H-UDI
15
Fixed priority level.
IRQ
0 to 15
Set with interrupt priority registers 01, 02, and 05
to 18 (IPR01, IPR02, and IPR05 to IPR18).
On-chip peripheral module
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 109 of 1778
Section 5 Exception Handling
5.5.3
SH7280 Group, SH7243 Group
Interrupt Exception Handling
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, interrupt exception handling begins. In interrupt exception
handling, the CPU fetches the exception service routine start address which corresponds to the
accepted interrupt from the exception handling vector table, and saves SR and the program counter
(PC) to the stack. In the case of interrupt exception handling other than NMI or UBC with usage
of the register banks enabled, general registers R0 to R14, control register GBR, system registers
MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to
be executed are saved in the register banks. In the case of exception handling due to an address
error, NMI interrupt, UBC interrupt, or instruction, saving is not performed to the register banks.
If saving has been performed to all register banks (0 to 14), automatic saving to the stack is
performed instead of register bank saving. In this case, an interrupt controller setting must have
been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of
the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE
bit in IBNR of the INTC is 1), register bank overflow exception occurs. Next, the priority level
value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority
level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start
address fetched from the exception handling vector table, program execution starts. The jump that
occurs is not a delayed branch. See section 6.6, Operation, for further details of interrupt exception
handling.
Page 110 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 5 Exception Handling
5.6
Exceptions Triggered by Instructions
5.6.1
Types of Exceptions Triggered by Instructions
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal
instructions, and integer division exceptions, as shown in table 5.9.
Table 5.9
Types of Exceptions Triggered by Instructions
Type
Source Instruction
Trap instruction
TRAPA
Slot illegal
instructions
Undefined code placed
immediately after a delayed
branch instruction (delay slot),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Comment
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
General illegal
instructions
Undefined code anywhere
besides in a delay slot
Integer division
exceptions
Division by zero
DIVU, DIVS
Negative maximum value ÷ (−1)
DIVS
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 111 of 1778
Section 5 Exception Handling
5.6.2
SH7280 Group, SH7243 Group
Trap Instructions
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
1. The exception service routine start address which corresponds to the vector number specified
in the TRAPA instruction is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
5.6.3
Slot Illegal Instructions
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites
the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction,
slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates
as follows:
1. The exception service routine start address is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
delayed branch instruction immediately before the undefined code, the instruction that rewrites
the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU
instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
Page 112 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.6.4
Section 5 Exception Handling
General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU
handles general illegal instructions in the same way as slot illegal instructions. Unlike processing
of slot illegal instructions, however, the program counter value stored is the start address of the
undefined code.
5.6.5
Integer Division Instructions
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by −1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division
instruction exception that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
integer division instruction at which the exception occurred.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 113 of 1778
SH7280 Group, SH7243 Group
Section 5 Exception Handling
5.7
When Exception Sources Are Not Accepted
When an address error, register bank error (overflow), or interrupt is generated immediately after a
delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown
in table 5.10. When this happens, it will be accepted when an instruction that can accept the
exception is decoded.
Table 5.10 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of Occurrence
Address Error
Register Bank Error
(Overflow)
Interrupt
Immediately after a delayed
branch instruction*
Not accepted
Not accepted
Not accepted
Note:
*
Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Page 114 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.8
Section 5 Exception Handling
Stack Status after Exception Handling Ends
The status of the stack after exception handling ends is as shown in table 5.11.
Table 5.11 Stack Status After Exception Handling Ends
Exception Type
Stack Status
Address error
SP
Address of instruction
after executed instruction
32 bits
SR
32 bits
Address of instruction
after executed instruction
32 bits
SR
32 bits
Address of instruction
after executed instruction
32 bits
SR
32 bits
Start address of relevant
RESBANK instruction
32 bits
SR
32 bits
Address of instruction
after TRAPA instruction
32 bits
SR
32 bits
Jump destination address
of delayed branch instruction
32 bits
SR
32 bits
Interrupt
SP
Register bank error (overflow)
SP
Register bank error (underflow)
SP
Trap instruction
SP
Slot illegal instruction
SP
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 115 of 1778
SH7280 Group, SH7243 Group
Section 5 Exception Handling
Exception Type
Stack Status
General illegal instruction
SP
Integer division instruction
(division by zero, overflow)
Page 116 of 1778
SP
Start address of general
illegal instruction
32 bits
SR
32 bits
Start address of relevant
integer division instruction
32 bits
SR
32 bits
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
5.9
Usage Notes
5.9.1
Value of Stack Pointer (SP)
Section 5 Exception Handling
The value of the stack pointer must always be a multiple of four. If it is not, an address error will
occur when the stack is accessed during exception handling.
5.9.2
Value of Vector Base Register (VBR)
The value of the vector base register must always be a multiple of four. If it is not, an address error
will occur when the stack is accessed during exception handling.
5.9.3
Address Errors Caused by Stacking of Address Error Exception Handling
When the stack pointer is not a multiple of four, an address error will occur during stacking of the
exception handling (interrupts, etc.) and address error exception handling will start up as soon as
the first exception handling is ended. Address errors will then also occur in the stacking for this
address error exception handling. To ensure that address error exception handling does not go into
an endless loop, no address errors are accepted at that point. This allows program control to be
shifted to the address error exception service routine and enables error processing.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. During stacking of the status register (SR) and program counter (PC), the SP is
decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking
either. The address value output during stacking is the SP value, so the address where the error
occurred is itself output. This means the write data stacked will be undefined.
5.9.4
Note When Changing Interrupt Mask Level (IMASK) of Status Register (SR) in
CPU
When enabling or disabling interrupts by modifying the interrupt mask level value of the CPU
status register (SR) using an LDC or LDC.L instruction, there must be at least five instructions
between the instruction to enable interrupts and the instruction to disable interrupts.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 117 of 1778
Section 5 Exception Handling
Page 118 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1
Features
• 16 levels of interrupt priority can be set
By setting the sixteen interrupt priority registers, the priority of IRQ interrupts and on-chip
peripheral module interrupts can be selected from 16 levels for request sources.
• NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as the noise
canceler function.
• Occurrence of interrupt can be reported externally (IRQOUT pin)
For example, when this LSI has released the bus mastership, this LSI can inform the external
bus master of occurrence of an on-chip peripheral module interrupt and request for the bus
mastership.
• Register banks
This LSI has register banks that enable register saving and restoration required in the interrupt
processing to be performed at high speed.
Figure 6.1 shows a block diagram of the INTC.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 119 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Comparator
Control input
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
CPU/DTC interrupt request
identifier
IRQOUT
DTC
(Interrupt request)
UBC
Interrupt
request
SR
I3 I2 I1 I0
(Interrupt request)
H-UDI
CPU
CPU/DTC/DMAC interrupt request identifier
CMT
BSC
WDT
MTU2
MTU2S
POE2
ADC
IIC3
SCI
SCIF
USB
Priority identifier
(Interrupt request)
DMAC
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
RCAN
(Interrupt request)
DTCERA to
DTCERE
ICR0
ICR1
IPR
IRQRR
DMAC
IBCR
IPR01, IPR02,
IPR05 to IPR18
IBNR
CHCR[11:8]
Module bus
Bus
interface
Internal bus
SSU
INTC
[Legend]
UBC:
H-UDI:
DMAC:
CMT:
BSC:
WDT:
MTU2:
MTU2S:
POE2:
ADC:
IIC3:
SCI:
SCIF:
SSU:
USB:
DTC:
RCAN:
User break controller
User debugging interface
Direct memory access controller
Compare match timer
Bus state controller
Watchdog timer
Multi-function timer pulse unit 2
Multi-function timer pulse unit 2S
Port output enable 2
A/D converter
I2C bus interface 3*1
Serial communication interface
Serial communication interface with FIFO
Synchronous serial communication unit*1
USB function module*1
Data transfer controller
Controller area network*2
ICR0:
ICR1:
IRQRR:
IBCR:
IBNR:
IPR01, IPR02, IPR05 to IPR18:
Interrupt control register 0
Interrupt control register 1
IRQ interrupt request register
Bank control register
Bank number register
Interrupt priority registers 01, 02, 05 to 18
Notes: 1. Only in SH7286 and SH7285
2. Only in SH7286
Figure 6.1 Block Diagram of INTC
Page 120 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.2
Section 6 Interrupt Controller (INTC)
Input/Output Pins
Table 6.1 shows the pin configuration of the INTC.
Table 6.1
Pin Configuration
Pin Name
Symbol
I/O
Function
Nonmaskable interrupt input
pin
NMI
Input
Input of nonmaskable interrupt
request signal
Interrupt request input pins
IRQ7 to IRQ0
Input
Input of maskable interrupt request
signals
Interrupt request output pin
IRQOUT
Output
Output of signal to report occurrence
of interrupt source
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 121 of 1778
Section 6 Interrupt Controller (INTC)
6.3
SH7280 Group, SH7243 Group
Register Descriptions
The INTC has the following registers. These registers are used to set the interrupt priorities and
control detection of the external interrupt input signal.
Table 6.2
Register Configuration
Initial
Access
Value
Size
Register Name
Abbreviation
R/W
Address
1
H'FFFE0800
16, 32
Interrupt control register 0
ICR0
R/W
*
Interrupt control register 1
ICR1
R/W
H'0000
H'FFFE0802
16
IRQ interrupt request register
IRQRR
R/(W)*2 H'0000
H'FFFE0806
16
Bank control register
IBCR
R/W
H'0000
H'FFFE080C
16, 32
Bank number register
IBNR
R/W
H'0000
H'FFFE080E
16
Interrupt priority register 01
IPR01
R/W
H'0000
H'FFFE0818
16, 32
Interrupt priority register 02
IPR02
R/W
H'0000
H'FFFE081A
16
Interrupt priority register 05
IPR05
R/W
H'0000
H'FFFE0820
16
Interrupt priority register 06
IPR06
R/W
H'0000
H'FFFE0C00
16, 32
Interrupt priority register 07
IPR07
R/W
H'0000
H'FFFE0C02
16
Interrupt priority register 08
IPR08
R/W
H'0000
H'FFFE0C04
16, 32
Interrupt priority register 09
IPR09
R/W
H'0000
H'FFFE0C06
16
Interrupt priority register 10
IPR10
R/W
H'0000
H'FFFE0C08
16, 32
Interrupt priority register 11
IPR11
R/W
H'0000
H'FFFE0C0A
16
Interrupt priority register 12
IPR12
R/W
H'0000
H'FFFE0C0C
16, 32
Interrupt priority register 13
IPR13
R/W
H'0000
H'FFFE0C0E
16
Interrupt priority register 14
IPR14
R/W
H'0000
H'FFFE0C10
16, 32
Interrupt priority register 15
IPR15
R/W
H'0000
H'FFFE0C12
16
Interrupt priority register 16
IPR16
R/W
H'0000
H'FFFE0C14
16, 32
Interrupt priority register 17
IPR17
R/W
H'0000
H'FFFE0C16
16
Interrupt priority register 18
IPR18
R/W
H'0000
H'FFFE0C18
16
USB-DTC transfer interrupt
USDTENDRR R/(W)*2 H'0000
H'FFFE0C50
16
request register
Notes: Two access cycles are needed for word access, and four access cycles for longword
access.
1. When the NMI pin is high, becomes H'8000; when low, becomes H'0000.
2. Only 0 can be written after reading 1, to clear the flag.
Page 122 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.3.1
Section 6 Interrupt Controller (INTC)
Interrupt Priority Registers 01, 02, 05 to 18 (IPR01, IPR02, IPR05 to IPR18)
IPR01, IPR02, and IPR05 to IPR18 are 16-bit readable/writable registers in which priority levels
from 0 to 15 are set for IRQ interrupts and on-chip peripheral module interrupts. Table 6.3 shows
the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR05
to IPR18.
Bit:
Initial value:
R/W:
Table 6.3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR18
Register Name
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
Interrupt priority
register 01
IRQ0
IRQ1
IRQ2
IRQ3
Interrupt priority
register 02
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt priority
register 05
Reserved
Reserved
ADI0
ADI1
Interrupt priority
register 06
DMAC0
DMAC1
DMAC2
DMAC3
Interrupt priority
register 07
DMAC4
DMAC5
DMAC6
DMAC7
Interrupt priority
register 08
CMT0
CMT1
BSC
WDT
Interrupt priority
register 09
MTU2_0
(TGIA_0 to TGID_0)
MTU2_0
(TCIV_0, TGIE_0,
TGIF_0)
MTU2_1
(TGIA_1, TGIB_1)
MTU2_1
(TCIV_1,
TCIU_1)
Interrupt priority
register 10
MTU2_2
(TGIA_2, TGIB_2)
MTU2_2
(TCIV_2, TCIU_2)
MTU2_3
(TGIA_3 to TGID_3)
MTU2_3
(TCIV_3)
Interrupt priority
register 11
MTU2_4
(TGIA_4 to TGID_4)
MTU2_4
(TCIV_4)
MTU2_5
(TGIU_5, TGIV_5,
TGIW_5)
POE2
(OEI1, OEI2)
Interrupt priority
register 12
MTU2S_3
(TGIA_3 to TGID_3)
MTU2S_3
(TCIV_3)
MTU2S_4
(TGIA_4 to TGID_4)
MTU2S_4
(TCIV_4)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 123 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Register Name
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
1
Bits 3 to 0
Interrupt priority
register 13
MTU5S
(TGIU_5, TGIV_5,
TGIW_5)
POE2
(OEI3)
IIC3*
Reserved
Interrupt priority
register 14
Reserved
Reserved
Reserved
SCIF3
Interrupt priority
register 15
Reserved
Reserved
Reserved
Reserved
Interrupt priority
register 16
SCI0
SCI1*
1
SCI2
Reserved
Interrupt priority
register 17
SSU*
1
ADI2*
Reserved
Interrupt priority
register 18
USB*
(USI0, USI1)
EP1-FIFO full DTC
1
transfer end*
(USBRXI)
EP2-FIFO empty
1
DTC transfer end*
(USBTXI)
1
SCI4*
2
1
RCAN_ET*
2
Notes: 1. The setting value is invalid in the SH7243. B'1111 should be written to.
2. The setting value is invalid in the SH7243 and SH7285. B'1111 should be written to.
Page 124 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.3.2
Section 6 Interrupt Controller (INTC)
Interrupt Control Register 0 (ICR0)
ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input
pin NMI, and indicates the input level at the NMI pin.
ICR0 is initialized by a power-on reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NMIL
-
-
-
-
-
-
NMIE
-
-
-
-
-
-
-
0
-
*
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Note: * 1 when the NMI pin is high, and 0 when the NMI pin is low.
Bit
Bit Name
Initial
Value
R/W
Description
15
NMIL
*
R
NMI Input Level
Sets the level of the signal input at the NMI pin. The
NMI pin level can be obtained by reading this bit. This
bit cannot be modified.
0: Low level is input to NMI pin
1: High level is input to NMI pin
14 to 9
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
NMIE
0
R/W
NMI Edge Select
Selects whether the falling or rising edge of the
interrupt request signal on the NMI pin is detected.
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
7 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 125 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
6.3.3
Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to
IRQ0 individually: low level, falling edge, rising edge, or both edges.
ICR1 is initialized by a power-on reset.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
IRQ71S
0
R/W
IRQ Sense Select
14
IRQ70S
0
R/W
13
IRQ61S
0
R/W
These bits select whether interrupt signals
corresponding to pins IRQ7 to IRQ0 are detected by a
low level, falling edge, rising edge, or both edges.
12
IRQ60S
0
R/W
11
IRQ51S
0
R/W
10
IRQ50S
0
R/W
9
IRQ41S
0
R/W
8
IRQ40S
0
R/W
7
IRQ31S
0
R/W
6
IRQ30S
0
R/W
5
IRQ21S
0
R/W
4
IRQ20S
0
R/W
3
IRQ11S
0
R/W
2
IRQ10S
0
R/W
1
IRQ01S
0
R/W
0
IRQ00S
0
R/W
00: Interrupt request is detected on low level of IRQn
input
01: Interrupt request is detected on falling edge of IRQn
input
10: Interrupt request is detected on rising edge of IRQn
input
11: Interrupt request is detected on both edges of IRQn
input
[Legend]
n = 7 to 0
Note: When the detecting condition of the IRQn input is changed, the IRQnF flag in IRQRR is
cleared to 0.
Page 126 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.3.4
Section 6 Interrupt Controller (INTC)
IRQ Interrupt Request Register (IRQRR)
IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.
If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after
reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
IRQRR is initialized by a power-on reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
7
6
5
4
3
2
1
0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 127 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Bit
Bit Name
Initial
Value
R/W
7
IRQ7F
0
R/(W)* IRQ Interrupt Request
6
IRQ6F
0
5
IRQ5F
0
4
IRQ4F
0
3
IRQ3F
0
2
IRQ2F
0
1
IRQ1F
0
0
IRQ0F
0
R/(W)* These bits indicate the status of the IRQ7 to IRQ0
interrupt requests.
R/(W)*
Level detection:
R/(W)*
0: IRQn interrupt request has not occurred
R/(W)*
[Clearing condition]
R/(W)*
• IRQn input is high
R/(W)*
1: IRQn interrupt has occurred
R/(W)*
[Setting condition]
Description
•
IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected
[Clearing conditions]
•
Cleared by reading IRQnF while IRQnF = 1, then
writing 0 to IRQnF
•
Cleared by executing IRQn interrupt exception
handling
•
Cleared when DTC is activated by the IRQn
interrupt, then the DISEL bit in MRB of DTC is set
to 0
•
Cleared when the setting of IRQn1S or IRQn0S of
ICR1 is changed
1: IRQn interrupt request is detected
[Setting condition]
•
Edge corresponding to IRQn1S or IRQn0S of
ICR1 has occurred at IRQn pin
[Legend]
n = 7 to 0
Page 128 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.3.5
Section 6 Interrupt Controller (INTC)
Bank Control Register (IBCR)
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority
level.
IBCR is initialized to H'0000 by a power-on reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
-
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
E15
0
R/W
Enable
14
E14
0
R/W
13
E13
0
R/W
These bits enable or disable use of register banks for
interrupt priority levels 15 to 1. However, use of register
banks is always disabled for the user break interrupts.
12
E12
0
R/W
11
E11
0
R/W
10
E10
0
R/W
9
E9
0
R/W
8
E8
0
R/W
7
E7
0
R/W
6
E6
0
R/W
5
E5
0
R/W
4
E4
0
R/W
3
E3
0
R/W
2
E2
0
R/W
1
E1
0
R/W
0
⎯
0
R
Bit:
0
0: Use of register banks is disabled
1: Use of register banks is enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 129 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
6.3.6
Bank Number Register (IBNR)
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow
exception. IBNR also indicates the bank number to which saving is performed next through the
bits BN3 to BN0.
IBNR is initialized to H'0000 by a power-on reset.
Bit:
15
14
BE[1:0]
0
R/W
13
12
11
10
9
8
7
6
5
4
BOVE
-
-
-
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Initial value:
R/W:
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
BE[1:0]
00
R/W
Register Bank Enable
3
2
1
0
BN[3:0]
0
R
0
R
0
R
0
R
These bits enable or disable use of register banks.
00: Use of register banks is disabled for all interrupts.
The setting of IBCR is ignored.
01: Use of register banks is enabled for all interrupts
except NMI and user break. The setting of IBCR is
ignored.
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the setting of
IBCR.
13
BOVE
0
R/W
Register Bank Overflow Enable
Enables of disables register bank overflow exception.
0: Generation of register bank overflow exception is
disabled
1: Generation of register bank overflow exception is
enabled
12 to 4
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 130 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Bit
Bit Name
Initial
Value
R/W
Description
3 to 0
BN[3:0]
0000
R
Bank Number
These bits indicate the bank number to which saving is
performed next. When an interrupt using register banks
is accepted, saving is performed to the register bank
indicated by these bits, and BN is incremented by 1.
After BN is decremented by 1 due to execution of a
RESBANK (restore from register bank) instruction,
restoration from the register bank is performed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 131 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
6.3.7
USB-DTC Transfer Interrupt Request Register (USDTENDRR)
USDTENDRR is a 16-bit register that indicates USB-DTC transfer end interrupt requests, which
are on-chip peripheral module interrupts. Writing 0 to the RXF or TXF bit after reading RXF = 1
or TXF = 1 cancels the retained interrupt.
USDTENDRR is initialized by a power-on reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RXF
TXF
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
0
0
0
R/(W)* R/(W)* R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
Initial
Value
R/W
Description
15
RXF
0
R/(W)*
EP1-FIFO Full DTC Transfer End Interrupt Request
0: EP1-FIFO full DTC transfer end interrupt request has
not occurred
[Clearing conditions]
•
Cleared by reading RFX = 1, then writing 0 to RFX
•
Cleared by executing EP1-FIFO full DTC transfer
end interrupt exception handling
1: EP1-FIFO full DTC transfer end interrupt request has
occurred
14
TXF
0
R/(W)*
EP2-FIFO Empty DTC Transfer End Interrupt Request
0: EP2-FIFO empty DTC transfer end interrupt request
has not occurred
[Clearing conditions]
•
Cleared by reading TFX = 1, then writing 0 to TFX
•
Cleared by executing EP2-FIFO empty DTC
transfer end interrupt exception handling
1: EP2-FIFO empty DTC transfer end interrupt request
has occurred
13 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 132 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.4
Section 6 Interrupt Controller (INTC)
Interrupt Sources
There are five types of interrupt sources: NMI, user break, H-UDI, IRQ, and on-chip peripheral
modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When
set to level 0, that interrupt is masked at all times.
6.4.1
NMI Interrupt
The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests
are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0)
selects whether the rising edge or falling edge is detected.
Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the
interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
Note that during a reset and after the reset has been canceled, the NMI pin should be fixed high for
3 tcyc.
6.4.2
User Break Interrupt
A user break interrupt which occurs when a break condition set in the user break controller (UBC)
matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits
in SR to level 15. For user break interrupts, see section 7, User Break Controller (UBC).
6.4.3
H-UDI Interrupt
The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial
input of an H-UDI interrupt instruction. H-UDI interrupt requests are edge-detected and retained
until they are accepted. The H-UDI interrupt exception handling sets the I3 to I0 bits in SR to level
15. For H-UDI interrupts, see section 29, User Debugging Interface (H-UDI).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 133 of 1778
Section 6 Interrupt Controller (INTC)
6.4.4
SH7280 Group, SH7243 Group
IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge,
rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense
select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The
priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority
registers 01 and 02 (IPR01 and IPR02).
When using low-level setting for IRQ interrupts, an interrupt request signal is sent to the INTC
while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the
INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be
checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request
register (IRQRR).
When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the
IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ
interrupt request detection is retained until that interrupt request is accepted. Whether IRQ
interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in
IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request
detection.
The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the
accepted IRQ interrupt.
The IRQnF bit will be set when the setting condition is satisfied regardless of the setting of the I3
to I0 bits in SR.
Page 134 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.4.5
Section 6 Interrupt Controller (INTC)
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A/D converter (ADC)
Controller area network (RCAN-ET)
Direct memory access controller (DMAC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
USB function module (USB)
Multi-function timer pulse unit 2 (MTU2)
Multi-function timer pulse unit 2S (MTU2S)
Port output enable 2 (POE2)
I2C bus interface 3 (IIC3)
Synchronous serial communication unit (SSU)
Serial communication interface (SCI)
Serial communication interface with FIFO (SCIF)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 18 can be set for each module
by interrupt priority registers 05 to 18 (IPR05 to IPR18). The on-chip peripheral module interrupt
exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip
peripheral module interrupt.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 135 of 1778
Section 6 Interrupt Controller (INTC)
6.5
SH7280 Group, SH7243 Group
Interrupt Exception Handling Vector Table and Priority
Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and
interrupt priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and vector table address offsets. In
interrupt exception handling, the interrupt exception service routine start address is fetched from
the vector table indicated by the vector table address. For details of calculation of the vector table
address, see table 5.4 in section 5, Exception Handling.
The priorities of IRQ interrupts and on-chip peripheral module interrupts can be set freely between
0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 18 (IPR01,
IPR02, and IPR05 to IPR18). However, if two or more interrupts specified by the same IPR
among IPR05 to IPR18 occur, the priorities are defined as shown in the IPR setting unit internal
priority of table 6.4, and the priorities cannot be changed. A power-on reset assigns priority level 0
to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to
two or more interrupt sources and interrupts from those sources occur simultaneously, they are
processed by the default priorities indicated in table 6.4.
Page 136 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 6.4
Section 6 Interrupt Controller (INTC)
Interrupt Exception Handling Vectors and Priorities
Interrupt Vector
Interrupt Source Number Vector
Interrupt
Priority
Corresponding
Vector Table
Address Offset (Initial Value) IPR (Bit)
IPR
Setting
Unit
Internal
Priority
Default
Priority
High
NMI
11
H'0000002C to
H'0000002F
16
⎯
⎯
UBC
12
H'00000030 to
H'00000033
15
⎯
⎯
H-UDI
14
H'00000038 to
H'0000003B
15
⎯
⎯
IRQ0
64
H'00000100 to
H'00000103
0 to 15 (0)
IPR01 (15 to 12) ⎯
IRQ1
65
H'00000104 to
H'00000107
0 to 15 (0)
IPR01 (11 to 8)
⎯
IRQ2
66
H'00000108 to
H'0000010B
0 to 15 (0)
IPR01 (7 to 4)
⎯
IRQ3
67
H'0000010C to
H'0000010F
0 to 15 (0)
IPR01 (3 to 0)
⎯
IRQ4
68
H'00000110 to
H'00000113
0 to 15 (0)
IPR02 (15 to 12) ⎯
IRQ5
69
H'00000114 to
H'00000117
0 to 15 (0)
IPR02 (11 to 8)
⎯
IRQ6
70
H'00000118 to
H'0000011B
0 to 15 (0)
IPR02 (7 to 4)
⎯
IRQ7
71
H'0000011C to
H'0000011F
0 to 15 (0)
IPR02 (3 to 0)
⎯
ADI0
92
H'00000170 to
H'00000173
0 to 15 (0)
IPR05 (7 to 4)
⎯
ADI1
96
H'00000180 to
H'00000183
0 to 15 (0)
IPR05 (3 to 0)
⎯
ADI2
100
H'00000190 to
H'00000193
0 to 15 (0)
IPR17 (7 to 4)
⎯
IRQ
ADC
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Low
Page 137 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source Number Vector
Interrupt
Priority
Corresponding
Vector Table
Address Offset (Initial Value) IPR (Bit)
RCAN
_ET
Default
Priority
1
High
ERS_0
104
H'000001A0 to
H'000001A3
0 to 15 (0)
OVR_0
105
H'000001A4 to
H'000001A7
0 to 15 (0)
2
RM0_0, RM1_0
106
H'000001A8 to
H'000001AB
0 to 15 (0)
3
SLE_0
107
H'000001AC to
H'000001AF
0 to 15 (0)
4
DMAC DMAC0 DEI0
108
H'000001B0 to
H'000001B3
0 to 15 (0)
IPR06 (15 to 12) 1
HEI0
109
H'000001B4 to
H'000001B7
DMAC1 DEI1
112
H'000001C0 to
H'000001C3
HEI1
113
H'000001C4 to
H'000001C7
DMAC2 DEI2
116
H'000001D0 to
H'000001D3
HEI2
117
H'000001D4 to
H'000001D7
DMAC3 DEI3
120
H'000001E0 to
H'000001E3
HEI3
121
H'000001E4 to
H'000001E7
DMAC4 DEI4
124
H'000001F0 to
H'000001F3
HEI4
125
H'000001F4 to
H'000001F7
DMAC5 DEI5
128
H'00000200 to
H'00000203
HEI5
129
H'00000204 to
H'00000207
Page 138 of 1778
IPR18 (11 to 8)
IPR
Setting
Unit
Internal
Priority
2
0 to 15 (0)
IPR06 (11 to 8)
1
2
0 to 15 (0)
IPR06 (7 to 4)
1
2
0 to 15 (0)
IPR06 (3 to 0)
1
2
0 to 15 (0)
IPR07 (15 to 12) 1
2
0 to 15 (0)
IPR07 (11 to 8)
1
2
Low
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source Number Vector
Interrupt
Priority
Corresponding
Vector Table
Address Offset (Initial Value) IPR (Bit)
1
High
132
H'00000210 to
H'00000213
HEI6
133
H'00000214 to
H'00000217
DMAC7 DEI7
136
H'00000220 to
H'00000223
HEI7
137
H'00000224 to
H'00000227
CMI0
140
H'00000230 to
H'00000233
0 to 15 (0)
IPR08 (15 to 12) ⎯
CMI1
144
H'00000240 to
H'00000243
0 to 15 (0)
IPR08 (11 to 8)
⎯
BSC
CMI
148
H'00000250 to
H'00000253
0 to 15 (0)
IPR08 (7 to 4)
⎯
WDT
ITI
152
H'00000260 to
H'00000263
0 to 15 (0)
IPR08 (3 to 0)
⎯
USB
154
EP1-FIFO full
DTC transfer end
(USBRXI)
H'00000268 to
H'0000026B
0 to 15 (0)
IPR18 (7 to 4)
⎯
EP2-FIFO empty 155
DTC transfer end
(USBTXI)
H'0000026C to
H'0000026F
0 to 15 (0)
IPR18 (3 to 0)
⎯
MTU2_0 TGIA_0
156
H'00000270 to
H'00000273
0 to 15 (0)
IPR09 (15 to 12) 1
TGIB_0
157
H'00000274 to
H'00000277
2
TGIC_0 158
H'00000278 to
H'0000027B
3
TGID_0 159
H'0000027C to
H'0000027F
4
TCIV_0
160
H'00000280 to
H'00000283
TGIE_0
161
H'00000284 to
H'00000287
2
TGIF_0
162
H'00000288 to
H'0000028B
3
MTU2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
IPR07 (7 to 4)
Default
Priority
DMAC DMAC6 DEI6
CMT
0 to 15 (0)
IPR
Setting
Unit
Internal
Priority
2
0 to 15 (0)
IPR07 (3 to 0)
1
2
0 to 15 (0)
IPR09 (11 to 8)
1
Low
Page 139 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source Number Vector
MTU2
Interrupt
Priority
Corresponding
Vector Table
Address Offset (Initial Value) IPR (Bit)
0 to 15 (0)
IPR09 (7 to 4)
IPR
Setting
Unit
Internal
Priority
Default
Priority
1
High
MTU2_1 TGIA_1
164
H'00000290 to
H'00000293
TGIB_1
165
H'00000294 to
H'00000297
TCIV_1
168
H'000002A0 to
H'000002A3
TCIU_1
169
H'000002A4 to
H'000002A7
MTU2_2 TGIA_2
172
H'000002B0 to
H'000002B3
TGIB_2
173
H'000002B4 to
H'000002B7
TCIV_2
176
H'000002C0 to
H'000002C3
TCIU_2
177
H'000002C4 to
H'000002C7
MTU2_3 TGIA_3
180
H'000002D0 to
H'000002D3
TGIB_3
181
H'000002D4 to
H'000002D7
2
TGIC_3
182
H'000002D8 to
H'000002DB
3
TGID_3
183
H'000002DC to
H'000002DF
4
TCIV_3
184
H'000002E0 to
H'000002E3
Page 140 of 1778
2
0 to 15 (0)
IPR09 (3 to 0)
1
2
0 to 15 (0)
IPR10 (15 to 12) 1
2
0 to 15 (0)
IPR10 (11 to 8)
1
2
0 to 15 (0)
0 to 15 (0)
IPR10 (7 to 4)
IPR10 (3 to 0)
1
⎯
Low
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
IPR
Setting
Unit
Internal
Priority
Interrupt Source Number
Interrupt
Priority
Corresponding
Vector Table
Vector Address Offset (Initial Value) IPR (Bit)
MTU2
MTU2_4 TGIA_4
188
H'000002F0 to
H'000002F3
TGIB_4
189
H'000002F4 to
H'000002F7
2
TGIC_4
190
H'000002F8 to
H'000002FB
3
TGID_4
191
H'000002FC to
H'000002FF
4
TCIV_4
192
H'00000300 to
H'00000303
0 to 15 (0)
IPR11 (11 to 8)
⎯
MTU2_5 TGIU_5
196
H'00000310 to
H'00000313
0 to 15 (0)
IPR11 (7 to 4)
1
TGIV_5
197
H'00000314 to
H'00000317
2
TGIW_5
198
H'00000318 to
H'0000031B
3
OEI1
200
H'00000320 to
H'00000323
OEI2
201
H'00000324 to
H'00000327
MTU2S MTU2S_3 TGIA_3S 204
H'00000330 to
H'00000333
TGIB_3S
205
H'00000334 to
H'00000337
2
TGIC_3S
206
H'00000338 to
H'0000033B
3
TGID_3S
207
H'0000033C to
H'0000033F
4
TCIV_3S
208
H'00000340 to
H'00000343
POE2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
0 to 15 (0)
0 to 15 (0)
IPR11 (15 to 12) 1
IPR11 (3 to 0)
Default
Priority
High
1
2
0 to 15 (0)
0 to 15 (0)
IPR12 (15 to 12) 1
IPR12 (11 to 8)
⎯
Low
Page 141 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source Number
Interrupt
Priority
Corresponding
Vector Table
Vector Address Offset (Initial Value) IPR (Bit)
IPR
Setting
Unit
Internal
Priority
Default
Priority
1
High
MTU2S MTU2S_4 TGIA_4S 212
H'00000350 to
H'00000353
TGIB_4S
213
H'00000354 to
H'00000357
2
TGIC_4S
214
H'00000358 to
H'0000035B
3
TGID_4S
215
H'0000035C to
H'0000035F
4
TCIV_4S
216
H'00000360 to
H'00000363
0 to 15 (0)
IPR12 (3 to 0)
MTU2S_5 TGIU_5S
220
H'00000370 to
H'00000373
0 to 15 (0)
IPR13 (15 to 12) 1
TGIV_5S
221
H'00000374 to
H'00000377
2
TGIW_5S 222
H'00000378 to
H'0000037B
3
0 to 15 (0)
IPR12 (7 to 4)
⎯
⎯
POE2
OEI3
224
H'00000380 to
H'00000383
0 to 15 (0)
IPR13 (11 to 8)
USB
USI0
226
H'00000388 to
H'0000038B
0 to 15 (0)
IPR18 (15 to 12) 1
USI1
227
H'0000038C to
H'0000038F
STPI
228
H'00000390 to
H'00000393
NAKI
229
H'00000394 to
H'00000397
2
RXI
230
H'00000398 to
H'0000039B
3
TXI
231
H'0000039C to
H'0000039F
4
TEI
232
H'000003A0 to
H'000003A3
5
IIC3
Page 142 of 1778
2
0 to 15 (0)
IPR13 (7 to 4)
1
Low
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source Number Vector
SSU
SCI
Interrupt
Priority
Corresponding
Vector Table
Address Offset (Initial Value) IPR (Bit)
SSERI
233
H'000003A4 to
H'000003A7
SSRXI
234
H'000003A8 to
H'000003AB
2
SSTXI
235
H'000003AC to
H'000003AF
3
ERI4
236
H'000003B0 to
H'000003B3
RXI4
237
H'000003B4 to
H'000003B7
2
TXI4
238
H'000003B8 to
H'000003BB
3
TEI4
239
H'000003BC to
H'000003BF
4
ERI0
240
H'000003C0 to
H'000003C3
RXI0
241
H'000003C4 to
H'000003C7
2
TXI0
242
H'000003C8 to
H'000003CB
3
TEI0
243
H'000003CC to
H'000003CF
4
ERI1
244
H'000003D0 to
H'000003D3
RXI1
245
H'000003D4 to
H'000003D7
2
TXI1
246
H'000003D8 to
H'000003DB
3
TEI1
247
H'000003DC to
H'000003DF
4
SCI4
SCI0
SCI1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
0 to 15 (0)
IPR
Setting
Unit
Internal
Priority
0 to 15 (0)
0 to 15 (0)
0 to 15 (0)
IPR17 (15 to 12) 1
IPR17 (11 to 8)
Default
Priority
High
1
IPR16 (15 to 12) 1
IPR16 (11 to 8)
1
Low
Page 143 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt Vector
Interrupt Source Number Vector
SCI
SCIF
SCI2
SCIF3
Page 144 of 1778
Interrupt
Priority
Corresponding
Vector Table
Address Offset (Initial Value) IPR (Bit)
0 to 15 (0)
Default
Priority
1
High
ERI2
248
H'000003E0 to
H'000003E3
RXI2
249
H'000003E4 to
H'000003E7
2
TXI2
250
H'000003E8 to
H'000003EB
3
TEI2
251
H'000003EC to
H'000003EF
4
BRI3
252
H'000003F0 to
H'000003F3
ERI3
253
H'000003F4 to
H'000003F7
2
RXI3
254
H'000003F8 to
H'000003FB
3
TXI3
255
H'000003FC to
H'000003FF
4
0 to 15 (0)
IPR16 (7 to 4)
IPR
Setting
Unit
Internal
Priority
IPR14 (3 to 0)
1
Low
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.6
Operation
6.6.1
Interrupt Operation Sequence
Section 6 Interrupt Controller (INTC)
The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
following the priority levels set in interrupt priority registers 01, 02, and 05 to 18 (IPR01,
IPR02, and IPR05 to IPR18). Lower priority interrupts are ignored*. If two of these interrupts
have the same priority level or if multiple interrupts occur within a single IPR, the interrupt
with the highest priority is selected, according to the default priority and IPR setting unit
internal priority shown in table 6.4.
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt
request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is
ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the
interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU.
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes
the instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling (figure 6.4).
6. The interrupt exception service routine start address is fetched from the exception handling
vector table corresponding to the accepted interrupt.
7. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt
is copied to bits I3 to I0 in SR.
8. The program counter (PC) is saved onto the stack.
9. The CPU jumps to the fetched interrupt exception service routine start address and starts
executing the program. The jump that occurs is not a delayed branch.
10. A high level is output from the IRQOUT pin. However, if the interrupt controller accepts an
interrupt with a higher priority than the interrupt just being accepted, the IRQOUT pin holds
low level.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 145 of 1778
Section 6 Interrupt Controller (INTC)
SH7280 Group, SH7243 Group
Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the
interrupt source flag, "time from occurrence of interrupt request until interrupt controller
identifies priority, compares it with mask bits in SR, and sends interrupt request signal to
CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually
cancelled. To ensure that an interrupt request that should have been cleared is not
inadvertently accepted again, read the interrupt source flag after it has been cleared, and
then execute an RTE instruction.
* Interrupt requests that are designated as edge-sensing are held pending until the
interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing
the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ
Interrupts.
Interrupts held pending due to edge-sensing are cleared by a power-on reset.
Page 146 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Program
execution state
No
Interrupt?
Yes
No
NMI?
Yes
No
User break?
Yes
No
H-UDI
interrupt?
Yes
Level 15
interrupt?
Yes
Yes
No
Level 14
interrupt?
I3 to I0 ≤
level 14?
No
No
Yes
Level 1
interrupt?
I3 to I0 ≤
level 13?
No
No
Yes
Yes
I3 to I0 =
level 0?
No
IRQOUT = low
Read exception
handling vector table
Save SR to stack
Copy accept-interrupt
level to I3 to I0
Save PC to stack
Branch to interrupt
exception service routine
IRQOUT = high
Figure 6.2 Interrupt Operation Flow
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 147 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
6.6.2
Stack after Interrupt Exception Handling
Figure 6.3 shows the stack after interrupt exception handling.
Address
4n – 8
PC*1
32 bits
4n – 4
SR
32 bits
SP*2
4n
Notes:
1.
2.
PC: Start address of the next instruction (return destination instruction)
after the executed instruction
Always make sure that SP is a multiple of 4.
Figure 6.3 Stack after Interrupt Exception Handling
Page 148 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.7
Section 6 Interrupt Controller (INTC)
Interrupt Response Time
Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt
request until the interrupt exception handling starts and fetching of the first instruction in the
exception service routine begins. The interrupt processing operations differ in the cases when
banking is disabled, when banking is enabled without register bank overflow, and when banking is
enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline operation
when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation when banking
is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of pipeline
operation when banking is enabled with register bank overflow.
Table 6.5
Interrupt Response Time
Number of States
Peripheral
Item
NMI
UBC
H-UDI
IRQ
Module
Remarks
Time from occurrence of interrupt
request until interrupt controller
identifies priority, compares it with
mask bits in SR, and sends interrupt
request signal to CPU
2 Icyc +
2 Bcyc +
1 Pcyc
3 Icyc
2 Icyc +
1 Pcyc
2 Icyc +
3 Bcyc +
1 Pcyc
2 Icyc +
1 Bcyc +
2 Pcyc
Interrupts with the DTC
activation sources
2 Icyc +
Interrupts without the DTC
1 Bcyc +
1 Bcyc
activation sources.
Time from
No register
Min.
3 Icyc + m1 + m2
input of
interrupt
request signal
to CPU until
sequence
currently being
executed is
completed,
interrupt
exception
handling starts,
and first
instruction in
exception
service routine
is fetched
banking
Max.
4 Icyc + 2(m1 + m2) + m3
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
Min. is when the interrupt
wait time is zero.
Max. is when a higherpriority interrupt request has
occurred during interrupt
exception handling.
Min.
—
—
3 Icyc + m1 + m2
Max.
—
—
12 Icyc + m1 + m2
Min.
—
—
3 Icyc + m1 + m2
Max.
—
—
3 Icyc + m1 + m2 + 19(m4)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred during
execution of the RESBANK
instruction.
Min. is when the interrupt
wait time is zero.
Max. is when an interrupt
request has occurred during
execution of the RESBANK
instruction.
Page 149 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Number of States
Item
Interrupt
No register
response
time
banking
Min.
Max.
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
Min.
Max.
Min.
Max.
NMI
UBC
H-UDI
IRQ
Peripheral
Module
Remarks
5 Icyc +
6 Icyc +
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*1*2:
2 Bcyc +
1 Pcyc +
m1 + m2
m1 + m2
1 Pcyc +
m1 + m2
3 Bcyc +
1 Pcyc +
m1 + m2
1 Bcyc +
1 Pcyc +
m1 + m2
0.080 to 0.150 μs
6 Icyc +
6 Icyc +
6 Icyc +
100-MHz operation*1*2:
1 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
0.120 to 0.190 μs
6 Icyc +
7 Icyc +
2 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
2(m1 + m2) + 1 Pcyc +
3 Bcyc +
m3
2(m1 + m2) + 1 Pcyc +
m3
2(m1 + m2) +
m3
—
—
—
—
—
—
—
—
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*1*2:
1 Pcyc +
m1 + m2
3 Bcyc +
1 Pcyc +
m1 + m2
1 Bcyc +
1 Pcyc +
m1 + m2
0.080 to 0.150 μs
14 Icyc +
14 Icyc +
14 Icyc +
100-MHz operation*1*2:
1 Pcyc +
m1 + m2
3 Bcyc +
1 Pcyc +
m1 + m2
1 Bcyc +
1 Pcyc +
m1 + m2
0.170 to 0.240 μs
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*1*2:
1 Pcyc +
3 Bcyc +
1 Bcyc +
0.080 to 0.150 μs
m1 + m2
1 Pcyc +
m1 + m2
1 Pcyc +
m1 + m2
5 Icyc +
5 Icyc +
5 Icyc +
100-MHz operation*1*2:
1 Pcyc +
m1 + m2 +
19(m4)
3 Bcyc +
1 Pcyc +
m1 + m2 +
19(m4)
1 Bcyc +
1 Pcyc +
m1 + m2 +
19(m4)
0.270 to 0.340 μs
Notes: m1 to m4 are the number of states needed for the following memory accesses.
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
stack.
1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case that (Iφ, Bφ, Pφ) = (100 MHz, 50 MHz, 50 MHz).
Page 150 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1
m2
m3
M
M
M
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt exception
service routine
F
D
E
E
F
D
E
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Instruction fetch. Instruction is fetched from memory in which program is stored.
F:
Instruction decoding. Fetched instruction is decoded.
D:
Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
E:
Memory access. Memory data access is performed.
M:
Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted
(No Register Banking)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 151 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
1 Icyc + m1 + 2(m2) + m3
3 Icyc + m1
IRQ
F
D
E
E
m1
m2
m3
M
M
M
First instruction in interrupt exception
service routine
First instruction in multiple interrupt
exception service routine
D
F
D
E
E
m1
m2
M
M
M
D
F
Multiple interrupt acceptance
Interrupt acceptance
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.5 Example of Pipeline Operation for Multiple Interrupts
(No Register Banking)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1
m2
m3
M
M
M
E
F
D
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt exception
service routine
F
D
E
E
E
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking without Register Bank Overflow)
Page 152 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
9 Icyc
3 Icyc + m1 + m2
IRQ
F
RESBANK instruction
D
E
E
E
E
E
E
E
E
Instruction (instruction replacing
interrupt exception handling)
E
D
E
E
m1
m2
m3
M
M
M
E
F
D
First instruction in interrupt
exception service routine
Interrupt acceptance
[Legend]
m1:
m2:
m3:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking without Register Bank Overflow)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1
m2
m3
M
M
M
...
M
F
...
...
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt exception
service routine
F
D
E
E
D
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking with Register Bank Overflow)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 153 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
2 Icyc + 17(m4)
1 Icyc + m1 + m2 + 2(m4)
IRQ
RESBANK instruction
F
D
Instruction (instruction replacing
interrupt exception handling)
E
M
M
M
...
M
m4
m4
M
M
W
D
E
E
First instruction in interrupt
exception service routine
m1
m2
m3
M
M
M
...
F
...
D
Interrupt acceptance
[Legend]
m1:
m2:
m3:
m4:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Restoration of banked registers
Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking with Register Bank Overflow)
Page 154 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.8
Section 6 Interrupt Controller (INTC)
Register Banks
This LSI has fifteen register banks used to perform register saving and restoration required in the
interrupt processing at high speed. Figure 6.10 shows the register bank configuration.
Registers
Register banks
General
registers
R0
R1
R0
R1
:
:
Interrupt generated
(save)
Bank 0
Bank 1
....
:
:
Bank 14
R14
R14
R15
GBR
Control
registers
System
registers
SR
GBR
VBR
TBR
MACH
MACL
PR
PC
RESBANK
instruction
(restore)
MACH
MACL
PR
VTO
Bank control registers (interrupt controller)
Bank control register
IBCR
Bank number register
IBNR
: Banked register
Note:
VTO:
Vector table address offset
Figure 6.10 Overview of Register Bank Configuration
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 155 of 1778
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
6.8.1
(1)
Banked Register and Input/Output of Banks
Banked Register
The contents of the general registers (R0 to R14), global base register (GBR), multiply and
accumulate registers (MACH and MACL), and procedure register (PR), and the vector table
address offset are banked.
(2)
Register Banks
This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in lastout (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes
place in the reverse order, beginning from the last bank saved to.
6.8.2
(1)
Bank Save and Restore Operations
Saving to Bank
Figure 6.11 shows register bank save operations. The following operations are performed when an
interrupt for which usage of register banks is allowed is accepted by the CPU:
a. Assume that the bank number bit value in the bank number register (IBNR), BN, is "i" before
the interrupt is generated.
b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector
table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN,
bank i.
c. The BN value is incremented by 1.
Register banks
+1
(c)
BN
(a)
Bank 0
Bank 1
:
:
Bank i
Bank i + 1
:
:
Registers
R0 to R14
(b)
GBR
MACH
MACL
PR
VTO
Bank 14
Figure 6.11 Bank Save Operations
Page 156 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
interrupt exception service routine.
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1
m2
m3
M
M
M
IRQ
Instruction (instruction replacing
interrupt exception handling)
F
D
E
E
E
(1) VTO, PR, GBR, MACL
(2) R12, R13, R14, MACH
(3) R8, R9, R10, R11
(4) R4, R5, R6, R7
Saved to bank
Overrun fetch
(5) R0, R1, R2, R3
F
First instruction in interrupt exception
service routine
F
D
E
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.12 Bank Save Timing
(2)
Restoration from Bank
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt service routine, execute the RTE instruction to return from the exception handling.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 157 of 1778
Section 6 Interrupt Controller (INTC)
6.8.3
SH7280 Group, SH7243 Group
Save and Restore Operations after Saving to All Banks
If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the
CPU in a state where saving has been performed to all register banks, automatic saving to the
stack is performed instead of register bank saving if the BOVE bit in the bank number register
(IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception
occurs and data is not saved to the stack.
Save and restore operations when using the stack are as follows:
(1)
Saving to Stack
1. The status register (SR) and program counter (PC) are saved to the stack during interrupt
exception handling.
2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to
the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14,
R13, …, R1, and R0.
3. The register bank overflow bit (BO) in SR is set to 1.
4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
maximum value of 15.
(2)
Restoration from Stack
When the RESBANK (restore from register bank) instruction is executed with the register bank
overflow bit (BO) in SR set to 1, the CPU operates as follows:
1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored
from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14,
PR, GBR, MACH, and MACL.
2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
maximum value of 15.
Page 158 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.8.4
Section 6 Interrupt Controller (INTC)
Register Bank Exception
There are two register bank exceptions (register bank errors): register bank overflow and register
bank underflow.
(1)
Register Bank Overflow
This exception occurs if, after data has been saved to all of the register banks, an interrupt for
which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number
register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number
register (IBNR) remains set to the bank count of 15 and saving is not performed to the register
bank.
(2)
Register Bank Underflow
This exception occurs if the RESBANK (restore from register bank) instruction is executed when
no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH,
MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number
register (IBNR) remains set to 0.
6.8.5
Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. When this
happens, the CPU operates as follows:
1. The exception service routine start address which corresponds to the register bank error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction for a register bank overflow, and
the start address of the executed RESBANK instruction for a register bank underflow. To
prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority
level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0)
of the status register (SR).
4. Program execution starts from the exception service routine start address.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 159 of 1778
Section 6 Interrupt Controller (INTC)
6.9
SH7280 Group, SH7243 Group
Data Transfer with Interrupt Request Signals
Interrupt request signals can be used to trigger the following data transfer.
• Only the DMAC is activated and no CPU interrupt occurs.
• Only the DTC is activated and a CPU interrupt may occur depending on the DTC setting.
Interrupt sources that are designated to activate the DMAC are masked without being input to the
INTC. The mask condition is as follows:
Mask condition = DME • (DE0 • interrupt source select 0 + DE1 • interrupt source select 1
+ DE2 • interrupt source select 2 + DE3 • interrupt source select 3 +
DE4 • interrupt source select 4 + DE5 • interrupt source select 5 + DE6
• interrupt source select 6 + DE7 • interrupt source select 7)
Here, DME is bit 0 in DMAOR of the DMAC, and DEn (n = 0 to 7) is bit 0 in CHCR0 to CHCR7
of the DMAC. For details, see section 10, Direct Memory Access Controller (DMAC).
The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The DTCE clearing
condition and interrupt source flag clearing condition are as follows:
DTCE clearing condition = DTC transfer end • DTCECLR
Interrupt source flag clearing condition = DTC transfer end • DTCECLR + DMAC transfer
end
However, DTCECLR = DISEL + counter value of 0
Page 160 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 6 Interrupt Controller (INTC)
Figures 6.13 and 6.14 show block diagrams of interrupt control.
Standby control
Standby
cancellation
identifier
IRQ edge detector
(in standby)
Interrupt controller
IRQ pin
CPU interrupt request
Interrupt priority
identifier
IRQ detection
DTC
DTC activation
request
DTCER
DTCE clearing
DTCECLR
Transfer end
IRQ flag clearing by DTC
Figure 6.13 Interrupt Control Block Diagram
Interrupt controller
Interrupt priority
identifier
CPU interrupt request
DMAC
Decoding
Bits RS[3:0]
in CHCR
DTC
Interrupt source
DMAC activation
request
DTC activation
request
DTCER
DTCE clearing
Interrupt source
flag clearing
DTCECLR
Transfer end
Interrupt source flag clearing by DTC
Interrupt source
flag clearing
by DMAC
Figure 6.14 Block Diagram of Controlling an On-Chip Peripheral Module Interrupt
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 161 of 1778
Section 6 Interrupt Controller (INTC)
6.9.1
SH7280 Group, SH7243 Group
Handling Interrupt Request Signals as DTC Activating Sources and CPU Interrupt
Sources but Not as DMAC Activating Sources
1. Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating
sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC.
2. Set both the corresponding DTCE bit and DISEL bit to 1 in the DTC.
3. Activating sources are applied to the DTC when interrupts occur.
4. The DTC clears the DTCE bit to 0 and sends interrupt requests to the CPU when starting data
transfer. The DTC does not clear the activating sources.
5. The CPU clears the interrupt sources in the interrupt exception handling routine, and then
confirms the transfer counter value. If the transfer counter value is not 0, the DTCE bit is set to
1 and the next data transfer enabled. If the transfer counter value is 0, the CPU performs the
necessary termination processing in the interrupt exception handling routine.
6.9.2
Handling Interrupt Request Signals as DMAC Activating Sources but Not as CPU
Interrupt Sources
1. Select DMAC activating sources and set both the DE and DME bits to 1. This masks CPU
interrupt sources regardless of the interrupt priority register and DTC register settings.
2. Activating sources are applied to the DMAC when interrupts occur.
3. The DMAC clears the activating sources when starting data transfer.
6.9.3
Handling Interrupt Request Signals as DTC Activating Sources but Not as CPU
Interrupt Sources or DMAC Activating Sources
1. Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating
sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC.
2. Set the corresponding DTCE bit to 1 and clear the DISEL bit to 0 in the DTC.
3. Activating sources are applied to the DTC when interrupts occur.
4. The DTC clears the activating sources when starting data transfer. Interrupt requests are not
sent to the CPU because the DTCE bit remains set to 1.
5. However, when the transfer counter value is 0, the DTCE bit is cleared to 0 and interrupt
requests are sent to the CPU. The activating source is not cleared here.
6. The CPU clears the interrupt source and performs the necessary termination processing in the
interrupt exception handling routine.
Page 162 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
6.9.4
Section 6 Interrupt Controller (INTC)
Handling Interrupt Request Signals as CPU Interrupt Sources but Not as DTC
Activating Sources or DMAC Activating Sources
1. Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating
sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC.
2. Clear the corresponding DTCE bit to 0 in the DTC.
3. Interrupt requests are sent to the CPU when interrupts occur.
4. The CPU clears the interrupt sources and performs the necessary termination processing in the
interrupt exception handling routine.
6.10
Usage Notes
6.10.1
Timing to Clear an Interrupt Source
The interrupt source flags should be cleared in the interrupt exception service routine. After
clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt
controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal
to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually
cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently
accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE
instruction.
6.10.2
In Case the NMI Pin is not in Use
When the NMI pin is not in use, fix the pin to the high level by connecting the pin to Vcc via a
resistor.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 163 of 1778
Section 6 Interrupt Controller (INTC)
6.10.3
SH7280 Group, SH7243 Group
Negate Timing of IRQOUT
When the interrupt controller accepts an interrupt request, a low-level signal is output from the
IRQOUT pin, and after jumping to the start address of the interrupt exception service routine, a
high-level signal is output from the IRQOUT pin.
However, in the case where an interrupt request is accepted by the interrupt controller and a lowlevel signal is output from the IRQOUT pin, but the interrupt request is canceled before a jump is
made to the start address of the interrupt exception service routine, a low-level signal will be
output from the IRQOUT pin until a jump is made to the start address of the interrupt exception
service routine called by the next interrupt request.
6.10.4
Notes on Canceling Software Standby Mode with an IRQx Interrupt Request
When canceling software standby mode using an IRQx interrupt request, change the IRQ sense
select setting of ICRx in a state in which no IRQx interrupt requests are generated and clear the
IRQxF flag in IRQRRx to 0 by the automatic clearing function of the IRQx interrupt processing.
If the IRQxF flag in the IRQ interrupt request register x (IRQRRx) is 1, changing the setting of the
IRQ sense select bits in the interrupt control register x (ICRx) or clearing the IRQxF flag in
IRQRRx to 0 will clear the relevant IRQx interrupt request but will not clear the software standby
cancellation request.
Page 164 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Section 7 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Instruction fetch or data read/write (bus master
(CPU, DMAC, or DTC) selection in the case of data read/write), data size, data contents, address
value, and stop timing in the case of instruction fetch are break conditions that can be set in the
UBC. Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is
performed by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus
is performed by issuing bus cycles on the memory access bus (M bus). The UBC monitors the C
bus and internal bus (I bus).
7.1
Features
1. The following break comparison conditions can be set.
Number of break channels: four channels (channels 0 to 3)
User break can be requested as the independent condition on channels 0, 1, 2, and 3.
• Address
Comparison of the 32-bit address is maskable in 1-bit units.
One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus
(IAB)) can be selected.
• Bus master when I bus is selected
Selection of CPU cycles, DMAC cycles, or DTC cycles
• Bus cycle
Instruction fetch (only when C bus is selected) or data access
• Read/write
• Operand size
Byte, word, and longword
2. Exception handling routine for user-specified break conditions can be executed.
3. In an instruction fetch cycle, it can be selected whether PC breaks are set before or after an
instruction is executed.
4. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 165 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
Access
control
I bus
C bus
IAB
MAB FAB
I bus
Access
comparator
BBR_0
BAR_0
Address
comparator
BAMR_0
Channel 0
Access
comparator
BBR_1
BAR_1
Address
comparator
BAMR_1
Channel 1
Access
comparator
BBR_2
BAR_2
Address
comparator
BAMR_2
Channel 2
Access
comparator
BBR_3
BAR_3
Address
comparator
BAMR_3
Channel 3
BRCR
Control
[Legend]
BBR: Break bus cycle register
BAR: Break address register
BAMR: Break address mask register
BRCR: Break control register
User break interrupt request
UBCTRG pin output
Figure 7.1 Block Diagram of UBC
Page 166 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.2
Section 7 User Break Controller (UBC)
Input/Output Pin
Table 7.1 shows the pin configuration of the UBC.
Table 7.1
Pin Configuration
Pin Name
Symbol
I/O
Function
UBC trigger
UBCTRG
Output
Indicates that a setting condition is
satisfied on either channel 0, 1, 2, or 3 of
the UBC.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 167 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
7.3
Register Descriptions
The UBC has the following registers.
Table 7.2
Register Configuration
Channel
Register Name
Abbreviation
R/W
Initial Value
Address
Access
Size
0
Break address register_0
BAR_0
R/W
H'00000000
H'FFFC0400
32
Break address mask register_0
BAMR_0
R/W
H'00000000
H'FFFC0404
32
1
2
3
Common
Break bus cycle register_0
BBR_0
R/W
H'0000
H'FFFC04A0
16
Break address register_1
BAR_1
R/W
H'00000000
H'FFFC0410
32
Break address mask register_1
BAMR_1
R/W
H'00000000
H'FFFC0414
32
Break bus cycle register_1
BBR_1
R/W
H'0000
H'FFFC04B0
16
Break address register_2
BAR_2
R/W
H'00000000
H'FFFC0420
32
Break address mask register_2
BAMR_2
R/W
H'00000000
H'FFFC0424
32
Break bus cycle register_2
BBR_2
R/W
H'0000
H'FFFC04A4
16
Break address register_3
BAR_3
R/W
H'00000000
H'FFFC0430
32
Break address mask register_3
BAMR_3
R/W
H'00000000
H'FFFC0434
32
Break bus cycle register_3
BBR_3
R/W
H'0000
H'FFFC04B4
16
Break control register
BRCR
R/W
H'00000000
H'FFFC04C0
32
Page 168 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.1
Section 7 User Break Controller (UBC)
Break Address Register_0 (BAR_0)
BAR_0 is a 32-bit readable/writable register. BAR_0 specifies the address used as a break
condition in channel 0. The control bits CD0_1 and CD0_0 in the break bus cycle register_0
(BBR_0) select one of the three address buses for a break condition of channel 0. BAR_0 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BA0_31BA0_30BA0_29BA0_28BA0_27BA0_26BA0_25BA0_24BA0_23BA0_22BA0_21BA0_20BA0_19BA0_18BA0_17BA0_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA0_15BA0_14BA0_13BA0_12BA0_11BA0_10 BA0_9 BA0_8 BA0_7 BA0_6 BA0_5 BA0_4 BA0_3 BA0_2 BA0_1 BA0_0
Initial value:
R/W:
0
R/W
0
R/W
Bit
Bit Name
31 to 0
BA0_31 to
BA0_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R/W
Break Address 0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 0.
When the C bus and instruction fetch cycle are
selected by BBR_0, specify an FAB address in bits
BA0_31 to BA0_0.
When the C bus and data access cycle are selected by
BBR_0, specify an MAB address in bits BA0_31 to
BA0_0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_0 to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 169 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
7.3.2
Break Address Mask Register_0 (BAMR_0)
BAMR_0 is a 32-bit readable/writable register. BAMR_0 specifies bits masked in the break
address bits specified by BAR_0. BAMR_0 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAM0_31 BAM0_30 BAM0_29 BAM0_28 BAM0_27 BAM0_26 BAM0_25 BAM0_24 BAM0_23 BAM0_22 BAM0_21 BAM0_20 BAM0_19 BAM0_18 BAM0_17 BAM0_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
BAM0_15 BAM0_14 BAM0_13 BAM0_12 BAM0_11 BAM0_10 BAM0_9
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
Bit
Bit Name
31 to 0
BAM0_31 to All 0
BAM0_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
8
7
6
5
4
3
2
1
0
BAM0_8
BAM0_7
BAM0_6
BAM0_5
BAM0_4
BAM0_3
BAM0_2
BAM0_1
BAM0_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
Description
R/W
Break Address Mask 0
Specify bits masked in the channel-0 break address
bits specified by BAR_0 (BA0_31 to BA0_0).
0: Break address bit BA0_n is included in the break
condition
1: Break address bit BA0_n is masked and not
included in the break condition
Note: n = 31 to 0
Page 170 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.3
Section 7 User Break Controller (UBC)
Break Bus Cycle Register_0 (BBR_0)
BBR_0 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user
break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C
bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size
as the break conditions of channel 0. BBR_0 is initialized to H'0000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
-
-
UBID0
-
-
0
R
0
R
0
R/W
0
R
0
R
10
9
8
7
CP0[2:0]
0
R/W
0
R/W
6
CD0[1:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
⎯
All 0
R
Reserved
0
R/W
5
4
ID0[1:0]
0
R/W
0
R/W
3
2
1
RW0[1:0]
0
R/W
0
SZ0[1:0]
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
13
UBID0
0
R/W
User Break Interrupt Disable 0
Disables or enables user break interrupt requests
when a channel-0 break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
12, 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8
CP0[2:0]
000
R/W
I-Bus Bus Master Select 0
Select the bus master when the bus cycle of the
channel-0 break condition is the I bus cycle. However,
when the C bus cycle is selected, this bit is invalidated
(only the CPU cycle).
xx1: CPU cycle is included in break conditions
x1x: DMAC cycle is included in break conditions
1xx: DTC cycle is included in break conditions
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 171 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
CD0[1:0]
00
R/W
C Bus Cycle/I Bus Cycle Select 0
Select the C bus cycle or I bus cycle as the bus cycle
of the channel-0 break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
5, 4
ID0[1:0]
00
R/W
Instruction Fetch/Data Access Select 0
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel-0 break condition. If
the instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
data access cycle
3, 2
RW0[1:0]
00
R/W
Read/Write Select 0
Select the read cycle or write cycle as the bus cycle of
the channel-0 break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
1, 0
SZ0[1:0]
00
R/W
Operand Size Select 0
Select the operand size of the bus cycle for the
channel-0 break condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
[Legend]
x:
Don't care
Page 172 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.4
Section 7 User Break Controller (UBC)
Break Address Register_1 (BAR_1)
BAR_1 is a 32-bit readable/writable register. BAR_1 specifies the address used as a break
condition in channel 1. The control bits CD1_1 and CD1_0 in the break bus cycle register_1
(BBR_1) select one of the three address buses for a break condition of channel 1. BAR_1 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BA1_31BA1_30BA1_29BA1_28BA1_27BA1_26BA1_25BA1_24BA1_23BA1_22BA1_21BA1_20BA1_19BA1_18BA1_17BA1_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA1_15BA1_14BA1_13BA1_12BA1_11BA1_10 BA1_9 BA1_8 BA1_7 BA1_6 BA1_5 BA1_4 BA1_3 BA1_2 BA1_1 BA1_0
Initial value:
R/W:
0
R/W
0
R/W
Bit
Bit Name
31 to 0
BA1_31 to
BA1_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R/W
Break Address 1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 1.
When the C bus and instruction fetch cycle are
selected by BBR_1, specify an FAB address in bits
BA1_31 to BA1_0.
When the C bus and data access cycle are selected by
BBR_1, specify an MAB address in bits BA1_31 to
BA1_0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_1 to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 173 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
7.3.5
Break Address Mask Register_1 (BAMR_1)
BAMR_1 is a 32-bit readable/writable register. BAMR_1 specifies bits masked in the break
address bits specified by BAR_1. BAMR_1 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAM1_31 BAM1_30 BAM1_29 BAM1_28 BAM1_27 BAM1_26 BAM1_25 BAM1_24 BAM1_23 BAM1_22 BAM1_21 BAM1_20 BAM1_19 BAM1_18 BAM1_17 BAM1_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
BAM1_15 BAM1_14 BAM1_13 BAM1_12 BAM1_11 BAM1_10 BAM1_9
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
Bit
Bit Name
31 to 0
BAM1_31 to All 0
BAM1_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
8
7
6
5
4
3
2
1
0
BAM1_8
BAM1_7
BAM1_6
BAM1_5
BAM1_4
BAM1_3
BAM1_2
BAM1_1
BAM1_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
Description
R/W
Break Address Mask 1
Specify bits masked in the channel-1 break address
bits specified by BAR_1 (BA1_31 to BA1_0).
0: Break address bit BA1_n is included in the break
condition
1: Break address bit BA1_n is masked and not
included in the break condition
Note: n = 31 to 0
Page 174 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.6
Section 7 User Break Controller (UBC)
Break Bus Cycle Register_1 (BBR_1)
BBR_1 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user
break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C
bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size
as the break conditions of channel 1. BBR_1 is initialized to H'0000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
-
-
UBID1
-
-
0
R
0
R
0
R/W
0
R
0
R
10
9
8
7
CP1[2:0]
0
R/W
0
R/W
6
CD1[1:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
⎯
All 0
R
Reserved
0
R/W
5
4
ID1[1:0]
0
R/W
0
R/W
3
2
1
RW1[1:0]
0
R/W
0
SZ1[1:0]
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
13
UBID1
0
R/W
User Break Interrupt Disable 1
Disables or enables user break interrupt requests
when a channel-1 break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
12, 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8
CP1[2:0]
000
R/W
I-Bus Bus Master Select 1
Select the bus master when the bus cycle of the
channel-1 break condition is the I bus cycle. However,
when the C bus cycle is selected, this bit is invalidated
(only the CPU cycle).
xx1: CPU cycle is included in break conditions
x1x: DMAC cycle is included in break conditions
1xx: DTC cycle is included in break conditions
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 175 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
CD1[1:0]
00
R/W
C Bus Cycle/I Bus Cycle Select 1
Select the C bus cycle or I bus cycle as the bus cycle
of the channel-1 break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
5, 4
ID1[1:0]
00
R/W
Instruction Fetch/Data Access Select 1
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel-1 break condition. If
the instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
data access cycle
3, 2
RW1[1:0]
00
R/W
Read/Write Select 1
Select the read cycle or write cycle as the bus cycle of
the channel-1 break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
1, 0
SZ1[1:0]
00
R/W
Operand Size Select 1
Select the operand size of the bus cycle for the
channel-1 break condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
[Legend]
x:
Don't care
Page 176 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.7
Section 7 User Break Controller (UBC)
Break Address Register_2 (BAR_2)
BAR_2 is a 32-bit readable/writable register. BAR_2 specifies the address used as a break
condition in channel 2. The control bits CD2_1 and CD2_0 in the break bus cycle register_2
(BBR_2) select one of the three address buses for a break condition of channel 2. BAR_2 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BA2_31BA2_30BA2_29BA2_28BA2_27BA2_26BA2_25BA2_24BA2_23BA2_22BA2_21BA2_20BA2_19BA2_18BA2_17BA2_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA2_15BA2_14BA2_13BA2_12BA2_11BA2_10 BA2_9 BA2_8 BA2_7 BA2_6 BA2_5 BA2_4 BA2_3 BA2_2 BA2_1 BA2_0
Initial value:
R/W:
0
R/W
0
R/W
Bit
Bit Name
31 to 0
BA2_31 to
BA2_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R/W
Break Address 2
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 2.
When the C bus and instruction fetch cycle are
selected by BBR_2, specify an FAB address in bits
BA2_31 to BA2_0.
When the C bus and data access cycle are selected by
BBR_2, specify an MAB address in bits BA2_31 to
BA0_2.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_2 to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 177 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
7.3.8
Break Address Mask Register_2 (BAMR_2)
BAMR_2 is a 32-bit readable/writable register. BAMR_2 specifies bits masked in the break
address bits specified by BAR_2. BAMR_2 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAM2_31 BAM2_30 BAM2_29 BAM2_28 BAM2_27 BAM2_26 BAM2_25 BAM2_24 BAM2_23 BAM2_22 BAM2_21 BAM2_20 BAM2_19 BAM2_18 BAM2_17 BAM2_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
BAM2_15 BAM2_14 BAM2_13 BAM2_12 BAM2_11 BAM2_10 BAM2_9
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
Bit
Bit Name
31 to 0
BAM2_31 to All 0
BAM2_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
8
7
6
5
4
3
2
1
0
BAM2_8
BAM2_7
BAM2_6
BAM2_5
BAM2_4
BAM2_3
BAM2_2
BAM2_1
BAM2_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
Description
R/W
Break Address Mask 2
Specify bits masked in the channel-2 break address
bits specified by BAR_2 (BA2_31 to BA2_0).
0: Break address bit BA2_n is included in the break
condition
1: Break address bit BA2_n is masked and not
included in the break condition
Note: n = 31 to 0
Page 178 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.9
Section 7 User Break Controller (UBC)
Break Bus Cycle Register_2 (BBR_2)
BBR_2 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user
break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C
bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size
as the break conditions of channel 2. BBR_2 is initialized to H'0000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
-
-
UBID2
-
-
0
R
0
R
0
R/W
0
R
0
R
10
9
8
7
CP2[2:0]
0
R/W
0
R/W
6
CD2[1:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
⎯
All 0
R
Reserved
0
R/W
5
4
ID2[1:0]
0
R/W
0
R/W
3
2
1
RW2[1:0]
0
R/W
0
SZ2[1:0]
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
13
UBID2
0
R/W
User Break Interrupt Disable 2
Disables or enables user break interrupt requests
when a channel-2 break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
12, 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8
CP2[2:0]
000
R/W
I-Bus Bus Master Select 2
Select the bus master when the bus cycle of the
channel-2 break condition is the I bus cycle. However,
when the C bus cycle is selected, this bit is invalidated
(only the CPU cycle).
xx1: CPU cycle is included in break conditions
x1x: DMAC cycle is included in break conditions
1xx: DTC cycle is included in break conditions
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 179 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
CD2[1:0]
00
R/W
C Bus Cycle/I Bus Cycle Select 2
Select the C bus cycle or I bus cycle as the bus cycle
of the channel-2 break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
5, 4
ID2[1:0]
00
R/W
Instruction Fetch/Data Access Select 2
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel-2 break condition. If
the instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
data access cycle
3, 2
RW2[1:0]
00
R/W
Read/Write Select 2
Select the read cycle or write cycle as the bus cycle of
the channel-2 break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
1, 0
SZ2[1:0]
00
R/W
Operand Size Select 2
Select the operand size of the bus cycle for the
channel-2 break condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
[Legend]
x:
Don't care
Page 180 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.10
Section 7 User Break Controller (UBC)
Break Address Register_3 (BAR_3)
BAR_3 is a 32-bit readable/writable register. BAR_3 specifies the address used as a break
condition in channel 3. The control bits CD3_1 and CD3_0 in the break bus cycle register_3
(BBR_3) select one of the three address buses for a break condition of channel 3. BAR_3 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BA3_31BA3_30BA3_29BA3_28BA3_27BA3_26BA3_25BA3_24BA3_23BA3_22BA3_21BA3_20BA3_19BA3_18BA3_17BA3_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA3_15BA3_14BA3_13BA3_12BA3_11BA3_10 BA3_9 BA3_8 BA3_7 BA3_6 BA3_5 BA3_4 BA3_3 BA3_2 BA3_1 BA3_0
Initial value:
R/W:
0
R/W
0
R/W
Bit
Bit Name
31 to 0
BA3_31 to
BA3_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R/W
Break Address 3
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 3.
When the C bus and instruction fetch cycle are
selected by BBR_3, specify an FAB address in bits
BA3_31 to BA3_0.
When the C bus and data access cycle are selected by
BBR_3, specify an MAB address in bits BA3_31 to
BA3_0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_3 to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 181 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
7.3.11
Break Address Mask Register_3 (BAMR_3)
BAMR_3 is a 32-bit readable/writable register. BAMR_3 specifies bits masked in the break
address bits specified by BAR_3. BAMR_3 is initialized to H'00000000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BAM3_31 BAM3_30 BAM3_29 BAM3_28 BAM3_27 BAM3_26 BAM3_25 BAM3_24 BAM3_23 BAM3_22 BAM3_21 BAM3_20 BAM3_19 BAM3_18 BAM3_17 BAM3_16
Initial value:
R/W:
Bit:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
BAM3_15 BAM3_14 BAM3_13 BAM3_12 BAM3_11 BAM3_10 BAM3_9
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
Bit
Bit Name
31 to 0
BAM3_31 to All 0
BAM3_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
8
7
6
5
4
3
2
1
0
BAM3_8
BAM3_7
BAM3_6
BAM3_5
BAM3_4
BAM3_3
BAM3_2
BAM3_1
BAM3_0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
Description
R/W
Break Address Mask 3
Specify bits masked in the channel-3 break address
bits specified by BAR_3 (BA3_31 to BA3_0).
0: Break address bit BA3_n is included in the break
condition
1: Break address bit BA3_n is masked and not
included in the break condition
Note: n = 31 to 0
Page 182 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.12
Section 7 User Break Controller (UBC)
Break Bus Cycle Register_3 (BBR_3)
BBR_3 is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user
break interrupts, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4) C
bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size
as the break conditions of channel 3. BBR_3 is initialized to H'0000 by a power-on reset, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
-
-
UBID3
-
-
0
R
0
R
0
R/W
0
R
0
R
10
9
8
7
CP3[2:0]
0
R/W
0
R/W
6
CD3[1:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
⎯
All 0
R
Reserved
0
R/W
5
4
ID3[1:0]
0
R/W
0
R/W
3
2
1
RW3[1:0]
0
R/W
0
SZ3[1:0]
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
13
UBID3
0
R/W
User Break Interrupt Disable 3
Disables or enables user break interrupt requests
when a channel-3 break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
12, 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8
CP3[2:0]
000
R/W
I-Bus Bus Master Select 3
Select the bus master when the bus cycle of the
channel-3 break condition is the I bus cycle. However,
when the C bus cycle is selected, this bit is invalidated
(only the CPU cycle).
xx1: CPU cycle is included in break conditions
x1x: DMAC cycle is included in break conditions
1xx: DTC cycle is included in break conditions
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 183 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
CD3[1:0]
00
R/W
C Bus Cycle/I Bus Cycle Select 3
Select the C bus cycle or I bus cycle as the bus cycle
of the channel-3 break condition.
00: Condition comparison is not performed
01: Break condition is the C bus (F bus or M bus) cycle
10: Break condition is the I bus cycle
11: Break condition is the C bus (F bus or M bus) cycle
5, 4
ID3[1:0]
00
R/W
Instruction Fetch/Data Access Select 3
Select the instruction fetch cycle or data access cycle
as the bus cycle of the channel-3 break condition. If
the instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed
01: Break condition is the instruction fetch cycle
10: Break condition is the data access cycle
11: Break condition is the instruction fetch cycle or
data access cycle
3, 2
RW3[1:0]
00
R/W
Read/Write Select 3
Select the read cycle or write cycle as the bus cycle of
the channel-3 break condition.
00: Condition comparison is not performed
01: Break condition is the read cycle
10: Break condition is the write cycle
11: Break condition is the read cycle or write cycle
1, 0
SZ3[1:0]
00
R/W
Operand Size Select 3
Select the operand size of the bus cycle for the
channel-3 break condition.
00: Break condition does not include operand size
01: Break condition is byte access
10: Break condition is word access
11: Break condition is longword access
[Legend]
x:
Don't care
Page 184 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.3.13
Section 7 User Break Controller (UBC)
Break Control Register (BRCR)
BRCR sets the following conditions:
1. Specifies whether user breaks are set before or after instruction execution.
2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied.
BRCR is a 32-bit readable/writable register that has break condition match flags and bits for
setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid
(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag
bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on
reset, but retains its previous value by a manual reset or in software standby mode or sleep mode.
Bit:
Initial value:
R/W:
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
0
R
0
R
0
R
0
R
SCMFC SCMFC SCMFC SCMFC SCMFD SCMFD SCMFD SCMFD
0
1
2
3
0
1
2
3
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
31 to 18
⎯
All 0
R
0
R/W
0
R/W
PCB3 PCB2 PCB1 PCB0
0
R/W
0
R/W
0
R/W
0
R/W
17
16
CKS[1:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
17, 16
CKS[1:0]
00
R/W
Clock Select
These bits specify the pulse width output to the
UBCTRG pin when a break condition is satisfied.
00: Pulse width of UBCTRG is one bus clock cycle
01: Pulse width of UBCTRG is two bus clock cycles
10: Pulse width of UBCTRG is four bus clock cycles
11: Pulse width of UBCTRG is eight bus clock cycles
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 185 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
15
SCMFC0
0
R/W
C Bus Cycle Condition Match Flag 0
When the C bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 0 does not
match
1: The C bus cycle condition for channel 0 matches
14
SCMFC1
0
R/W
C Bus Cycle Condition Match Flag 1
When the C bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 1 does not
match
1: The C bus cycle condition for channel 1 matches
13
SCMFC2
0
R/W
C Bus Cycle Condition Match Flag 2
When the C bus cycle condition in the break conditions
set for channel 2 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 2 does not
match
1: The C bus cycle condition for channel 2 matches
12
SCMFC3
0
R/W
C Bus Cycle Condition Match Flag 3
When the C bus cycle condition in the break conditions
set for channel 3 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 3 does not
match
1: The C bus cycle condition for channel 3 matches
11
SCMFD0
0
R/W
I Bus Cycle Condition Match Flag 0
When the I bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 0 does not
match
1: The I bus cycle condition for channel 0 matches
Page 186 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
10
SCMFD1
0
R/W
I Bus Cycle Condition Match Flag 1
When the I bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 1 does not
match
1: The I bus cycle condition for channel 1 matches
9
SCMFD2
0
R/W
I Bus Cycle Condition Match Flag 2
When the I bus cycle condition in the break conditions
set for channel 2 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 2 does not
match
1: The I bus cycle condition for channel 2 matches
8
SCMFD3
0
R/W
I Bus Cycle Condition Match Flag 3
When the I bus cycle condition in the break conditions
set for channel 3 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 3 does not
match
1: The I bus cycle condition for channel 3 matches
7
PCB3
0
R/W
PC Break Select 3
Selects the break timing of the instruction fetch cycle
for channel 3 as before or after instruction execution.
0: PC break of channel 3 is generated before
instruction execution
1: PC break of channel 3 is generated after instruction
execution
6
PCB2
0
R/W
PC Break Select 2
Selects the break timing of the instruction fetch cycle
for channel 2 as before or after instruction execution.
0: PC break of channel 2 is generated before
instruction execution
1: PC break of channel 2 is generated after instruction
execution
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 187 of 1778
SH7280 Group, SH7243 Group
Section 7 User Break Controller (UBC)
Bit
Bit Name
Initial
Value
R/W
Description
5
PCB1
0
R/W
PC Break Select 1
Selects the break timing of the instruction fetch cycle
for channel 1 as before or after instruction execution.
0: PC break of channel 1 is generated before
instruction execution
1: PC break of channel 1 is generated after instruction
execution
4
PCB0
0
R/W
PC Break Select 0
Selects the break timing of the instruction fetch cycle
for channel 0 as before or after instruction execution.
0: PC break of channel 0 is generated before
instruction execution
1: PC break of channel 0 is generated after instruction
execution
3 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 188 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.4
Operation
7.4.1
Flow of the User Break Operation
Section 7 User Break Controller (UBC)
The flow from setting of break conditions to user break interrupt exception handling is described
below:
1. The break address is set in a break address register (BAR). The masked address bits are set in a
break address mask register (BAMR). The bus break conditions are set in the break bus cycle
register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction
fetch/data access select, and read/write select) are each set. No user break will be generated if
even one of these groups is set to 00. The relevant break control conditions are set in the bits of
the break control register (BRCR). Make sure to set all registers related to breaks before setting
BBR, and branch after reading from the last written register. The newly written register values
become valid from the instruction at the branch destination.
2. In the case where the break conditions are satisfied, the UBC sends a user break interrupt
request to the CPU, sets the C bus condition match flag (SCMFC) or I bus condition match
flag (SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the
width set by the CKS1 and CKS0 bits. Setting the UBID bit in BBR to 1 enables external
monitoring of the trigger output without requesting user break interrupts.
3. On receiving a user break interrupt request signal, the INTC determines its priority. Since the
user break interrupt has a priority level of 15, it is accepted when the priority level set in the
interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits
are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are
checked, and condition match flags are set if the conditions match. For details on ascertaining
the priority, see section 6, Interrupt Controller (INTC).
4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been
satisfied. They are set when the conditions match, but are not reset. To use these flags again,
write 0 to the corresponding bit of the flags.
5. It is possible that the breaks set in channels 0 to 3 occur around the same time. In this case,
there will be only one user break request to the CPU, but these four break channel match flags
may be set at the same time.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 189 of 1778
Section 7 User Break Controller (UBC)
SH7280 Group, SH7243 Group
6. When selecting the I bus as the break condition, note as follows:
⎯ Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC
monitors bus cycles generated by the bus master specified by BBR, and determines the
condition match.
⎯ I bus cycles (including read fill cycles) resulting from instruction fetches on the C bus by
the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are
defined as data access cycles.
⎯ The DTC and DMAC only issue data access cycles for I bus cycles.
⎯ If a break condition is specified for the I bus, even when the condition matches in an I bus
cycle resulting from an instruction executed by the CPU, at which instruction the user
break is to be accepted cannot be clearly defined.
7.4.2
Break on Instruction Fetch Cycle
1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register
(BBR), the break condition is the FAB bus instruction fetch cycle. Whether PC breaks are set
before or after the execution of the instruction can then be selected with the PCB0 or PCB1 bit
of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is
set as a break condition, clear LSB in the break address register (BAR) to 0. A break cannot be
generated as long as this bit is set to 1.
2. A break for instruction fetch which is set as a break before instruction execution occurs when it
is confirmed that the instruction has been fetched and will be executed. This means a break
does not occur for instructions fetched by overrun (instructions fetched at a branch or during
an interrupt transition, but not to be executed). When this kind of break is set for the delay slot
of a delayed branch instruction, the break is not generated until the execution of the first
instruction at the branch destination.
Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is
not recognized as a delay slot.
3. When setting a break condition for break after instruction execution, the instruction set with
the break condition is executed and then the break is generated prior to execution of the next
instruction. As with pre-execution breaks, a break does not occur with overrun fetch
instructions. When this kind of break is set for a delayed branch instruction and its delay slot,
the break is not generated until the first instruction at the branch destination.
4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore,
break data cannot be set for the break of the instruction fetch cycle.
5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated.
Page 190 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.4.3
Section 7 User Break Controller (UBC)
Break on Data Access Cycle
1. If the C bus is specified as a break condition for data access break, condition comparison is
performed for the virtual address accessed by the executed instructions, and a break occurs if
the condition is satisfied. If the I bus is specified as a break condition, condition comparison is
performed for the physical address of the data access cycles that are issued by the bus master
specified by the bits to select the bus master of the I bus, and a break occurs if the condition is
satisfied. For details on the CPU bus cycles issued on the I bus, see 6 in section 7.4.1, Flow of
the User Break Operation.
2. The relationship between the data access cycle address and the comparison condition for each
operand size is listed in table 7.3.
Table 7.3
Data Access Cycle Addresses and Operand Size Comparison Conditions
Access Size
Address Compared
Longword
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Word
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Byte
Compares break address register bits 31 to 0 to address bus bits 31 to 0
This means that when address H'00001003 is set in the break address register (BAR), for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
3. If the data access cycle is selected, the instruction at which the break will occur cannot be
determined.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 191 of 1778
Section 7 User Break Controller (UBC)
7.4.4
SH7280 Group, SH7243 Group
Value of Saved Program Counter
When a break occurs, the address of the instruction from where execution is to be resumed is
saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch
cycle is specified as a break condition, the instruction at which the break should occur can be
uniquely determined. If the C bus/data access cycle or I bus/data access cycle is specified as a
break condition, the instruction at which the break should occur cannot be uniquely determined.
1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break
condition:
The address of the instruction that matched the break condition is saved to the stack. The
instruction that matched the condition is not executed, and the break occurs before it. However
when a delay slot instruction matches the condition, the instruction is executed, and the branch
destination address is saved to the stack.
2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break
condition:
The address of the instruction following the instruction that matched the break condition is
saved to the stack. The instruction that matches the condition is executed, and the break occurs
before the next instruction is executed. However when a delayed branch instruction or delay
slot matches the condition, the instruction is executed, and the branch destination address is
saved to the stack.
3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition:
The address after executing several instructions of the instruction that matched the break
condition is saved to the stack.
Page 192 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
7.4.5
(1)
Section 7 User Break Controller (UBC)
Usage Examples
Break Condition Specified for C Bus Instruction Fetch Cycle
(Example 1-1)
• Register specifications
BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010,
BAMR_1 = H'00000006, BBR_1 = H'0054, BRCR = H'00000020
Address: H'00000404, Address mask: H'00000000
Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
Address: H'00008010, Address mask: H'00000006
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
(Example 1-2)
• Register specifications
BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415,
BAMR_1 = H'00000000, BBR_1 = H'0054, BRCR = H'00000000
Address: H'00027128, Address mask: H'00000000
Bus cycle: C bus/instruction fetch (before instruction execution)/write/word
Address: H'00031415, Address mask: H'00000000
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
On channel 0, a user break does not occur since instruction fetch is not a write cycle. On
channel 1, a user break does not occur since instruction fetch is performed for an even address.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 193 of 1778
Section 7 User Break Controller (UBC)
SH7280 Group, SH7243 Group
(Example 1-3)
• Register specifications
BBR_0 = H'0054, BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_1 = H'0054,
BAR_1 = H'00008010, BAMR_1 = H'00000006, BRCR = H'00000020
Address: H'00008404, Address mask: H'00000FFF
Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
Address: H'00008010, Address mask: H'00000006
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed
or before an instruction with addresses H'00008010 to H'00008016 are executed.
(2)
Break Condition Specified for C Bus Data Access Cycle
(Example 2-1)
• Register specifications
BBR_0 = H'0064, BAR_0 = H'00123456, BAMR_0 = H'00000000,
BBR_1 = H'006A, BAR_1 = H'000ABCDE, BAMR_1 = H'000000FF, BRCR = H'00000000
Address: H'00123456, Address mask: H'00000000
Bus cycle: C bus/data access/read (operand size is not included in the condition)
Address: H'000ABCDE, Address mask: H'000000FF
Bus cycle: C bus/data access/write/word
On channel 0, a user break occurs with longword read from address H'00123456, word read
from address H'00123456, or byte read from address H'00123456. On channel 1, a user break
occurs when word is written in addresses H'000ABC00 to H'000ABCFE.
Page 194 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 7 User Break Controller (UBC)
Break Condition Specified for I Bus Data Access Cycle
(Example 3-1)
• Register specifications
BBR_0 = H'0094, BAR_0 = H'00314156, BAMR_0 = H'00000000,
BBR_1 = H'12A9, BAR_1 = H'00055555, BAMR_1 = H'00000000, BRCR = H'00000000
Address: H'00314156, Address mask: H'00000000
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
Address: H'00055555, Address mask: H'00000000
Bus cycle: I bus/data access/write/byte
On channel 0, the setting of I bus/instruction fetch is ignored.
On channel 1, a user break occurs when the DMAC writes byte data in address H'00055555 on
the I bus (write by the CPU does not generate a user break).
7.5
Interrupt Source
The UBC has the user break interrupt as an interrupt source.
Table 7.4 gives details on this interrupt source.
A user break interrupt is generated when one of the compare match flags (SCMFD3 to SCMFD0
and SCMFC3 to SCMFC0) in the break control register (BRCR) is set to 1. Clearing the interrupt
flag bit to 0 cancels the interrupt request.
Table 7.4
Interrupt Source
Abbreviation Interrupt Source
Interrupt
Enable Bit
User break
⎯
User break interrupt
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Interrupt Flag
Interrupt Level
SCMFD3, SCMFD2,
SCMFD1, SCMFD0,
SCMFC3, SCMFC2,
SCMFC1, SCMFC0
Fixed to 15
Page 195 of 1778
Section 7 User Break Controller (UBC)
7.6
SH7280 Group, SH7243 Group
Usage Notes
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the
period from executing an instruction to rewrite the UBC register till the new value is actually
rewritten, the desired break may not occur. In order to know the timing when the UBC register
is changed, read from the last written register. Instructions after then are valid for the newly
written register value.
2. The UBC cannot monitor access to the C bus and I bus cycles in the same channel.
3. When a user break and another exception occur at the same instruction, which has higher
priority is determined according to the priority levels defined in table 5.1 in section 5,
Exception Handling. If an exception with a higher priority occurs, the user break does not
occur.
4. Note the following when a break occurs in a delay slot.
If a pre-execution break is set at a delay slot instruction, the break is not generated until
immediately before execution of the branch destination.
5. User breaks are disabled during UBC module standby mode. Do not read from or write to the
UBC registers during UBC module standby mode; the values are not guaranteed.
6. Do not set an address within an interrupt exception handling routine whose interrupt priority
level is at least 15 (including user break interrupts) as a break address.
7. Do not set break after instruction execution for the SLEEP instruction or for the delayed
branch instruction where the SLEEP instruction is placed at its delay slot.
8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are
placed. If the address of the lower 16 bits is set and a break before instruction execution is set
as a break condition, the break is handled as a break after instruction execution.
Page 196 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by
an interrupt request.
8.1
Features
• Transfer possible over any number of channels
• Chain transfer
Multiple rounds of data transfer is executed in response to a single activation source
Chain transfer is only possible after data transfer has been done for the specified number of
times (i.e. when the transfer counter is 0)
• Three transfer modes
Normal/repeat/block transfer modes selectable
Transfer source and destination addresses can be selected from increment/decrement/fixed
• The transfer source and destination addresses can be specified by 32 bits to select a 4-Gbyte
address space directly
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC
A CPU interrupt can be requested after one data transfer completion
A CPU interrupt can be requested after the specified data transfer completion
• Read skip of the transfer information specifiable
• Write-back skip executed for the fixed transfer source and destination addresses
• Module stop mode specifiable
• Short address mode specifiable
• Bus release timing selectable: Three types
• DTC activation priority selectable: Two types
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 197 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in
SYSCR1 must be set to 1.
DTC
On-chip
memory
MRB
SAR
DAR
Activation
control
CRA
CRB
CPU/DTC
request
determination
DTC internal bus
INTC
Interrupt
request
Internal bus (32 bits)
On-chip
peripheral
module
Peripheral bus
MRA
Register
control
DTCERA to
DTCERE
CPU interrupt
request
DTCCR
Interrupt
control
Interrupt source
clear request
DTCVBR
External device
(memory mapped)
External bus
Bus interface
External
memory
Bus state
controller
[Legend]
MRA, MRB:
SAR:
DAR:
CRA, CRB:
DTCERA to DTCERE:
DTCCR:
DTCVBR:
DTC mode registers A, B
DTC source address register
DTC destination address register
DTC transfer count registers A, B
DTC enable registers A to E
DTC control register
DTC vector base register
Figure 8.1 Block Diagram of DTC
Page 198 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.2
Section 8 Data Transfer Controller (DTC)
Register Descriptions
DTC has the following registers. For details on the addresses of these registers and the states of
these registers in each processing state, see section 30, List of Registers.
These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the
CPU. The contents of these registers are stored in the data area as transfer information. When a
DTC activation request occurs, the DTC reads a start address of transfer information that is stored
in the data area according to the vector address, reads the transfer information, and transfers data.
After the data transfer is complete, it writes a set of updated transfer information back to the data
area.
On the other hand, DTCERA to DTCERE, DTCCR, and DTCVBR can be directly accessed by the
CPU.
Table 8.1
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
DTC enable register A
DTCERA
R/W
H'0000
H'FFFE6000
8, 16
DTC enable register B
DTCERB
R/W
H'0000
H'FFFE6002
8, 16
DTC enable register C
DTCERC
R/W
H'0000
H'FFFE6004
8, 16
DTC enable register D
DTCERD
R/W
H'0000
H'FFFE6006
8, 16
DTC enable register E
DTCERE
R/W
H'0000
H'FFFE6008
8, 16
DTC control register
DTCCR
R/W
H'00
H'FFFE6010
8
DTC vector base register
DTCVBR
R/W
H'00000000
H'FFFE6014
8, 16, 32
Bus function extending register BSCEHR
R/W
H'0000
H'FFFE3C1A
8, 16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 199 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
8.2.1
DTC Mode Register A (MRA)
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Bit:
7
6
5
MD[1:0]
Initial value:
R/W:
*
-
*
-
4
3
Sz[1:0]
*
-
*
-
2
1
0
-
-
*
-
*
-
SM[1:0]
*
-
*
-
* : Undefined
Bit
Bit Name
Initial
Value
7, 6
MD[1:0]
Undefined ⎯
R/W
Description
DTC Mode 1 and 0
Specify DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
5, 4
Sz[1:0]
Undefined ⎯
DTC Data Transfer Size 1 and 0
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: Longword-size transfer
11: Setting prohibited
3, 2
SM[1:0]
Undefined ⎯
Source Address Mode 1 and 0
Specify an SAR operation after a data transfer.
0x: SAR is fixed
(SAR write-back is skipped)
10: SAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
Page 200 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
1, 0
⎯
Undefined ⎯
R/W
Description
Reserved
The write value should always be 0.
[Legend]
x:
Don't care
8.2.2
DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit:
Initial value:
R/W:
7
6
5
4
CHNE
CHNS
DISEL
DTS
*
-
*
-
*
-
*
-
3
2
DM[1:0]
*
-
*
-
1
0
-
-
*
-
*
-
* : Undefined
Bit
Bit Name
Initial
Value
7
CHNE
Undefined ⎯
R/W
Description
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see section
8.5.6, Chain Transfer. The chain transfer condition is
selected by the CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
6
CHNS
Undefined ⎯
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
5
DISEL
Undefined ⎯
DTC Interrupt Select
When this bit is set to 1, an interrupt request is generated
to the CPU every time a data transfer or a block data
transfer ends. When this bit is set to 0, a CPU interrupt
request is only generated when the specified number of
data transfers ends.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 201 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
4
DTS
Undefined ⎯
R/W
Description
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
3, 2
DM[1:0]
Undefined ⎯
Destination Address Mode 1 and 0
Specify a DAR operation after a data transfer.
0x: DAR is fixed
(DAR write-back is skipped)
10: DAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
1, 0
⎯
Undefined ⎯
Reserved
The write value should always be 0.
[Legend]
x:
Don't care
Page 202 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.2.3
Section 8 Data Transfer Controller (DTC)
DTC Source Address Register (SAR)
SAR is a 32-bit register that designates the source address of data to be transferred by the DTC.
SAR cannot be accessed directly from the CPU.
Bit: 31
Initial value:
R/W:
*
-
Bit: 15
Initial value:
R/W:
*
-
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
* : Undefined
8.2.4
DTC Destination Address Register (DAR)
DAR is a 32-bit register that designates the destination address of data to be transferred by the
DTC.
DAR cannot be accessed directly from the CPU.
Bit: 31
Initial value:
R/W:
*
-
Bit: 15
Initial value:
R/W:
*
-
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
* : Undefined
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 203 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
8.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the
activation source is cleared and then an interrupt is requested to the CPU when the count reaches
H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536
when CRA = H'0000.
In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower
eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit
transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when
CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL =
H'00.
In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower
eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size
counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte
(word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the
count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01,
255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or
longwords) when CRAH = CRAL =H'00.
CRA cannot be accessed directly from the CPU.
Bit: 15
Initial value:
R/W:
*
-
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
* : Undefined
Page 204 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.2.6
Section 8 Data Transfer Controller (DTC)
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time a block of data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the
activation source is cleared and then an interrupt is requested to the CPU when the count reaches
H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536
when CRB = H'0000.
CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU.
Bit: 15
Initial value:
R/W:
*
-
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
*
-
* : Undefined
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 205 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
8.2.7
DTC Enable Registers A to E (DTCERA to DTCERE)
DTCER which is comprised of eight registers, DTCERA to DTCERE, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.2.
Bit: 15
14
13
12
11
10
DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
9
8
7
6
5
4
3
2
1
0
DTCE9
DTCE8
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
DTCE15
0
R/W
14
DTCE14
0
R/W
13
DTCE13
0
R/W
12
DTCE12
0
R/W
11
DTCE11
0
R/W
10
DTCE10
0
R/W
9
DTCE9
0
R/W
8
DTCE8
0
R/W
7
DTCE7
0
R/W
6
DTCE6
0
R/W
DTC Activation Enable 15 to 0
Setting this bit to 1 specifies a relevant interrupt source to
a DTC activation source.
[Clearing conditions]
• When writing 0 to the bit to be cleared after reading 1
• When the DISEL bit is 1 and the data transfer has
ended
• When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended
[Setting condition]
• Writing 1 to the bit after reading 0
5
DTCE5
0
R/W
4
DTCE4
0
R/W
3
DTCE3
0
R/W
2
DTCE2
0
R/W
1
DTCE1
0
R/W
0
DTCE0
0
R/W
Page 206 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.2.8
Section 8 Data Transfer Controller (DTC)
DTC Control Register (DTCCR)
DTCCR specifies transfer information read skip.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
RRS
RCHNE
-
-
ERR
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/(W)*
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
RRS
0
R/W
DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer information
read. A DTC vector number is always compared with the
vector number for the previous activation. If the vector
numbers match and this bit is set to 1, the DTC data
transfer is started without reading a vector address and
transfer information. If the previous DTC activation is a
chain transfer, the vector address read and transfer
information read are always performed.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
numbers match.
3
RCHNE
0
R/W
Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer counter
(CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the chain
transfer is enabled when CRAH is written to CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer
2, 1
⎯
All 0
R
Reserved
These are read-only bits and cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 207 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Bit
Bit Name
Initial
Value
R/W
0
ERR
0
R/(W)* Transfer Stop Flag
Description
Indicates that a DTC address error or NMI interrupt has
occurred.
If a DTC address error or NMI interrupt occurs while the
DTC is active, a DTC address error handling or NMI
interrupt handling processing is executed after the DTC
has released the bus mastership. The DTC halts after a
data transfer or a transfer information writing state
depending on the NMI input timing. Note that a writing
state is not exact, when the DTC halts after a data
transfer. When the data is to be transferred again, set the
transfer information again (except when a read skip is
performed).
0: No interrupt has occurred
1: An interrupt has occurred
[Clearing condition]
•
Note:
*
When writing 0 after reading 1
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Page 208 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.2.9
Section 8 Data Transfer Controller (DTC)
DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bit: 31
Initial value: 0
R/W: R/W
Bit: 15
Initial value: 0
R/W: R/W
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
Initial
Bit Name Value
31 to 12
R/W
Description
All 0
R/W
All 0
R
Bits 11 to 0 are always read as 0. The write value should
always be 0.
11 to 0
⎯
8.2.10
Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and other
functions. This register should be used to give priority to the DTC transfer or reduce the number
of cycles in which the DTC is active. For more details, see section 9.4.8, Bus Function Extending
Register (BSCEHR).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 209 of 1778
Section 8 Data Transfer Controller (DTC)
8.3
SH7280 Group, SH7243 Group
Activation Sources
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC
activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt
source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer
(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or
corresponding DTCER bit is cleared.
8.4
Location of Transfer Information and DTC Vector Table
Locate the transfer information in the data area. The start address of transfer information should be
located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored
during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2.
Short address mode can be selected by setting the DTSA bit in the bus function extending register
(BSCEHR) to 1 only when all DTC transfer sources and destinations are located in the on-chip
RAM and on-chip peripheral module areas (see section 9.4.8, Bus Function Extending Register
(BSCEHR)).
In normal transfer, four longwords should be read as the transfer information; in short address
mode, the transfer information is reduced to three longwords and the DTC active period becomes
shorter.
The DTC reads the start address of transfer information from the vector table according to the
activation source, and then reads the transfer information from the start address. Figure 8.3 shows
correspondences between the DTC vector address and transfer information.
Page 210 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Transfer information
in normal operation
Transfer information
in short address mode
Lower addresses
Lower addresses
Start
address
2
0
1
MRA
MRB
3
Transfer
information
for one transfer
(4 longwords)
SAR
DAR
Chain
transfer
CRA
MRA
Start
address
Reserved
(0 write)
Chain
transfer
CRB
Reserved
(0 write)
MRB
SAR
DAR
CRA
Transfer
information
for the 2nd
transfer
in chain transfer
(4 longwords)
CRB
0
1
3
2
MRA
SAR
MRB
DAR
CRA
CRB
MRA
SAR
MRB
DAR
CRA
CRB
Transfer
information
for one transfer
(3 longwords)
Transfer
information
for the 2nd
transfer
in chain transfer
(3 longwords)
4 bytes
Note: The short address mode can be used only for transfer between an on-chip
peripheral module and the on-chip RAM because the upper eight bits of
SAR and DAR are assumed as all 1s.
4 bytes
Figure 8.2 Transfer Information on Data Area
Upper: DTCVBR
Lower: H'400 + vector number × 4
DTC vector
address
+4
Vector table
Transfer information (1)
Transfer information (1)
start address
Transfer information (2)
start address
+4n
Transfer information (2)
:
:
:
Transfer information (n)
start address
:
:
:
4 bytes
Transfer information (n)
Figure 8.3 Correspondence between DTC Vector Address and Transfer Information
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 211 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Table 8.2 shows correspondence between the DTC activation source and vector address.
Table 8.2
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
Activation
Source
External pin
IRQ0
IRQ1
IRQ2
Vector
Number
64
65
66
DTC Vector
Address
1
Offset
DTCE*
Transfer
Source
Transfer
Destination
2
H'00000500 DTCERA15 Any location*
Priority
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
H'00000504 DTCERA14 Any location*
H'00000508 DTCERA13 Any location*
2
2
IRQ3
67
H'0000050C DTCERA12 Any location*
IRQ4
68
H'00000510 DTCERA11 Any location*
IRQ5
69
H'00000514 DTCERA10 Any location*
IRQ6
70
H'00000518 DTCERA9
Any location*
IRQ7
71
H'0000051C DTCERA8
Any location*
Any location*
ADI0
92
H'00000570 DTCERA7
ADDR0 to
ADDR3
Any location*
ADI1
96
H'00000580 DTCERA6
ADDR4 to
ADDR7
Any location*
ADI2
100
H'00000590 DTCERA5
ADDR8 to
ADDR11
Any location*
RCAN
RM0_0
106
H'000005A8 DTCERA4
CONTROL0H Any location*
to
3
CONTROL1L*
CMT
CMI0
140
H'00000630 DTCERA3
Any location*
CMI1
144
H'00000640 DTCERA2
EP1-FIFO full
transfer
request
(USBRXI)
154
EP2-FIFO
155
empty transfer
request
(USBTXI)
A/D
USB
Page 212 of 1778
High
2
2
2
2
2
2
2
2
2
2
Any location*
2
Any location*
2
Any location*
H'00000668 DTCERA1
USBEPDR1
Any location*
H'0000066C DTCERA0
Any location*
2
2
2
USBEPDR2
Low
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Origin of
Activation
Source
MTU2_CH0
Activation
Source
TGIA_0
TGIB_0
TGIC_0
MTU2_CH1
MTU2_CH2
MTU2_CH3
MTU2_CH4
MTU2_CH5
MTU2S_CH3
MTU2S_CH4
Section 8 Data Transfer Controller (DTC)
Vector
Number
156
157
158
DTC Vector
Address
1
Offset
DTCE*
Transfer
Source
Transfer
Destination
2
H'00000670 DTCERB15 Any location*
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
2
Any location*
H'00000674 DTCERB14 Any location*
H'00000678 DTCERB13 Any location*
TGID_0
159
H'0000067C DTCERB12 Any location*
TGIA_1
164
H'00000690 DTCERB11 Any location*
TGIB_1
165
H'00000694 DTCERB10 Any location*
TGIA_2
172
H'000006B0 DTCERB9
Any location*
TGIB_2
173
H'000006B4 DTCERB8
Any location*
TGIA_3
180
H'000006D0 DTCERB7
Any location*
TGIB_3
181
H'000006D4 DTCERB6
Any location*
TGIC_3
182
H'000006D8 DTCERB5
Any location*
TGID_3
183
H'000006DC DTCERB4
Any location*
TGIA_4
188
H'000006F0 DTCERB3
Any location*
TGIB_4
189
H'000006F4 DTCERB2
Any location*
TGIC_4
190
H'000006F8 DTCERB1
Any location*
TGID_4
191
H'000006FC DTCERB0
Any location*
TCIV_4
192
H'00000700 DTCERC15 Any location*
TGIU_5
196
H'00000710 DTCERC14 Any location*
TGIV_5
197
H'00000714 DTCERC13 Any location*
TGIW_5
198
H'00000718 DTCERC12 Any location*
TGIA_3S
204
H'00000730 DTCERC3
Any location*
TGIB_3S
205
H'00000734 DTCERC2
Any location*
TGIC_3S
206
H'00000738 DTCERC1
Any location*
TGID_3S
207
H'0000073C DTCERC0
Any location*
TGIA_4S
212
H'00000750 DTCERD15 Any location*
TGIB_4S
213
H'00000754 DTCERD14 Any location*
TGIC_4S
214
H'00000758 DTCERD13 Any location*
TGID_4S
215
H'0000075C DTCERD12 Any location*
TCIV_4S
216
H'00000760 DTCERD11 Any location*
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Priority
2
High
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Low
Page 213 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Origin of
Activation
Source
MTU2S_CH5
Activation
Source
TGIU_5S
TGIV_5S
IIC3
SSU
SCI4
SCI0
SCI1
SCI2
SCIF3
Vector
Number
220
221
DTC Vector
Address
1
Offset
DTCE*
Transfer
Source
Transfer
Destination
2
H'00000770 DTCERD10 Any location*
H'00000774 DTCERD9
Priority
2
Any location*
2
Any location*
2
Any location*
High
2
2
TGIW_5S
222
H'00000778 DTCERD8
Any location*
Any location*
RXI
230
H'00000798 DTCERD7
ICDRR
Any location*
TXI
231
H'0000079C DTCERD6
Any location*
ICDRT
SSRXI
234
H'000007A8 DTCERD5
SSRDR0 to
SSRDR3
Any location*
SSTXI
235
H'000007AC DTCERD4
Any location*
SSTDR0 to
SSTDR3
RXI4
237
H'000007B4 DTCERD3
SCRDR_4
Any location*
TXI4
238
H'000007B8 DTCERD2
Any location*
RXI0
241
H'000007C4 DTCERE15 SCRDR_0
TXI0
242
H'000007C8 DTCERE14 Any location*
SCTDR_0
RXI1
245
H'000007D4 DTCERE13 SCRDR_1
Any location*
TXI1
246
H'000007D8 DTCERE12 Any location*
SCTDR_1
RXI2
249
H'000007E4 DTCERE11 SCRDR_2
Any location*
TXI2
250
H'000007E8 DTCERE10 Any location*
SCTDR_2
RXI3
254
H'000007F8 DTCERE9
SCFRDR_3
Any location*
TXI3
255
H'000007FC DTCERE8
Any location*
2
2
2
2
2
2
SCTDR_4
2
Any location*
2
2
2
2
2
2
2
SCFTDR_3
Low
Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should
always be 0.
2. An external memory, a memory-mapped external device, an on-chip memory, or an onchip peripheral module (except for DTC, BSC, UBC, AUD, FLASH, and DMAC) can be
selected as the source or destination. Note that at least either the source or destination
must be an on-chip peripheral module; transfer cannot be done among an external
memory, a memory-mapped external device, and an on-chip memory.
3. Read to a message control field in mailbox 0 by using a block transfer mode or etc.
Page 214 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.5
Section 8 Data Transfer Controller (DTC)
Operation
There are three transfer modes: normal, repeat, and block. Since transfer information is in the data
area, it is possible to transfer data over any required number of channels. When activated, the DTC
reads the transfer information stored in the data area and transfers data according to the transfer
information. After the data transfer is complete, it writes updated transfer information back to the
data area.
The DTC specifies the source address and destination address in SAR and DAR, respectively.
After a transfer, SAR and DAR are incremented, decremented, or fixed independently.
Table 8.3 shows the DTC transfer modes.
Table 8.3
DTC Transfer Modes
Transfer
Mode
Size of Data Transferred at One Memory Address Increment or
Transfer Request
Decrement
Transfer
Count
Normal
1 byte/word/longword
Incremented/decremented by 1, 2, or
4, or fixed
1 to 65536
Repeat*1
1 byte/word/longword
Incremented/decremented by 1, 2, or
4, or fixed
1 to 256*3
Block*2
Block size specified by CRAH
Incremented/decremented by 1, 2, or
(1 to 256 bytes/words/longwords) 4, or fixed
1 to 65536*4
Notes: 1. Either source or destination is specified to repeat area.
2. Either source or destination is specified to block area.
3. After transfer of the specified transfer count, initial state is recovered to continue the
operation.
4. Number of transfers of the specified block size of data
Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a
single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have
chain transfer performed only when the transfer counter value is 0.
Figure 8.4 shows a flowchart of DTC operation, and table 8.4 summarizes the conditions for DTC
transfers including chain transfer (combinations for performing the second and third transfers are
omitted).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 215 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Start
Match &
RRS = 1
Vector number
comparison
Not match | RRS = 0
Read DTC vector
Next transfer
Read transfer
information
Transfer data
Update transfer
information
Update the start address
of transfer information
Write transfer information
CHNE = 1
Yes
No
Transfer counter = 0
or DISEL = 1
Yes
No
CHNS = 0
Yes
No
Transfer counter = 0
Yes
No
DISEL = 1
Yes
No
Clear activation
source flag
Clear DTCER/request an interrupt
to the CPU
End
Figure 8.4 Flowchart of DTC Operation
Page 216 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 8.4
Section 8 Data Transfer Controller (DTC)
DTC Transfer Conditions (Chain Transfer Conditions Included)
1st Transfer
Transfer
2nd Transfer
Transfer
Transfer
Mode
CHNE CHNS RCHNE DISEL Counter*1
Normal
0
⎯
⎯
0
Not 0
CHNE
CHNS
RCHNE DISEL Counter*1 DTC Transfer
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
0
⎯
⎯
0
0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
0
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
transfer
Interrupt request
to CPU
1
0
⎯
⎯
⎯
0
⎯
⎯
0
Not 0
Ends at 2nd
transfer
0
⎯
⎯
0
0
Ends at 2nd
0
⎯
⎯
1
⎯
transfer
Interrupt request
to CPU
1
1
⎯
0
Not 0
⎯
⎯
⎯
⎯
⎯
1
1
⎯
1
Not 0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Ends at 1st
transfer
Interrupt request
to CPU
1
1
⎯
⎯
0
0
⎯
⎯
0
Not 0
Ends at 2nd
transfer
0
⎯
⎯
0
0
Ends at 2nd
0
⎯
⎯
1
⎯
transfer
Interrupt request
to CPU
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 217 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
1st Transfer
Transfer
2nd Transfer
Transfer
Mode
CHNE CHNS RCHNE DISEL Counter*1
Repeat
0
⎯
⎯
0
⎯
Transfer
CHNE
CHNS
RCHNE DISEL Counter*1 DTC Transfer
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
0
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Interrupt request
to CPU
1
0
⎯
⎯
⎯
0
⎯
⎯
0
⎯
Ends at 2nd
0
⎯
⎯
1
⎯
Ends at 2nd
transfer
transfer
Interrupt request
to CPU
1
1
⎯
0
Not 0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
1
1
⎯
1
Not 0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Interrupt request
to CPU
1
1
0
0
2
0*
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
1
1
0
1
2
0*
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Interrupt request
to CPU
1
1
1
⎯
2
0*
0
⎯
⎯
0
⎯
Ends at 2nd
transfer
0
⎯
⎯
1
⎯
Ends at 2nd
transfer
Interrupt request
to CPU
Page 218 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
1st Transfer
Transfer
2nd Transfer
Transfer
Mode
CHNE CHNS RCHNE DISEL Counter*1
Block
0
⎯
⎯
0
Not 0
Transfer
CHNE
CHNS
RCHNE DISEL Counter*1 DTC Transfer
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
0
⎯
⎯
0
0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
0
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
transfer
Interrupt request
to CPU
1
0
⎯
⎯
⎯
0
⎯
⎯
0
Not 0
Ends at 2nd
transfer
0
⎯
⎯
0
0
Ends at 2nd
0
⎯
⎯
1
⎯
transfer
Interrupt request
to CPU
1
1
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
1
1
⎯
1
Not 0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Interrupt request
to CPU
1
1
⎯
1
0
0
⎯
⎯
0
Not 0
Ends at 2nd
transfer
0
⎯
⎯
0
0
Ends at 2nd
0
⎯
⎯
1
⎯
transfer
Interrupt request
to CPU
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
mode
2. When the contents of the CRAH is written to the CRAL
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 219 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
8.5.1
Transfer Information Read Skip Function
By setting the RRS bit of DTCCR, the vector address read and transfer information read can be
skipped. The current DTC vector number is always compared with the vector number of previous
activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without
reading the vector address and transfer information. If the previous activation is a chain transfer,
the vector address read and transfer information read are always performed. Figure 8.5 shows the
transfer information read skip timing.
To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the
vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is
cleared to 0, the stored vector number is deleted, and the updated vector table and transfer
information are read at the next activation.
Clock (Bφ)
DTC activation
request
DTC request
Skip transfer
information read
R
Internal address
Vector read
Transfer information
read
W
Data
transfer
R
Transfer information
write
Data
transfer
W
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.5 Transfer Information Read Skip Timing
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Page 220 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.5.2
Section 8 Data Transfer Controller (DTC)
Transfer Information Write-Back Skip Function
By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer
information will not be written back. Table 8.5 shows the transfer information write-back skip
condition and write-back skipped registers. Note that the CRA and CRB are always written back.
The write-back of the MRA and MRB are always skipped.
Table 8.5
Transfer Information Write-Back Skip Condition and Write-Back Skipped
Registers
SM1
DM1
SAR
DAR
0
0
Skipped
Skipped
0
1
Skipped
Written back
1
0
Written back
Skipped
1
1
Written back
Written back
8.5.3
Normal Transfer Mode
In normal transfer mode, data are transferred in one byte, one word, or one longword units in
response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer
source and destination addresses can be specified as incremented, decremented, or fixed. When the
specified number of transfers ends, an interrupt can be requested to the CPU.
Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in
normal transfer mode.
Table 8.6
Register Function in Normal Transfer Mode
Register
Function
Written Back Value
SAR
Source address
Incremented/decremented/fixed*
DAR
Destination address
Incremented/decremented/fixed*
CRA
Transfer count A
CRA − 1
Transfer count B
Not updated
CRB
Note:
*
Transfer information write-back is skipped.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 221 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Transfer source data area
Transfer destination data area
SAR
DAR
Transfer
Figure 8.6 Memory Map in Normal Transfer Mode
8.5.4
Repeat Transfer Mode
In repeat transfer mode, data are transferred in one byte, one word, or one longword units in
response to a single activation request. By the DTS bit in MRB, either the source or destination
can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified
number of transfers ends, the transfer counter and address register specified as the repeat area is
restored to the initial state, and transfer is repeated. The other address register is then incremented,
decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the
value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not
reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0.
Table 8.7 lists the register function in repeat transfer mode. Figure 8.7 shows the memory map in
repeat transfer mode.
Page 222 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 8.7
Section 8 Data Transfer Controller (DTC)
Register Function in Repeat Transfer Mode
Written Back Value
Register Function
SAR
CRAL is not 1
Source address
CRAL is 1
Incremented/decremented/fixed* DTS = 0: Incremented/
decremented/fixed*
DTS = 1: SAR initial value
DAR
Destination address Incremented/decremented/fixed* DTS = 0: DAR initial value
DTS = 1: Incremented/
decremented/fixed*
CRAH
Transfer count
storage
CRAH
CRAH
CRAL
Transfer count A
CRAL − 1
CRAH
CRB
Transfer count B
Not updated
Not updated
Note:
*
Transfer information write-back is skipped.
Transfer source data area
(specified as repeat area)
Transfer destination data area
SAR
DAR
Transfer
Figure 8.7 Memory Map in Repeat Transfer Mode
(When Transfer Source is Specified as Repeat Area)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 223 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
8.5.5
Block Transfer Mode
In block transfer mode, data are transferred in block units in response to a single activation
request. Either the transfer source or the transfer destination is designated as a block area by the
DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When transfer of one
block of data ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or
DAR when DTS = 0) for the area specified as the block area are initialized. The other address
register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. When the specified number of transfers ends, an interrupt is requested to the CPU.
Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in
block transfer mode.
Table 8.8
Register Function in Block Transfer Mode
Register Function
Written Back Value
SAR
DTS = 0: Incremented/decremented/fixed*
Source address
DTS = 1: SAR initial value
DAR
Destination address
DTS = 0: DAR initial value
DTS = 1: Incremented/decremented/fixed*
CRAH
Block size storage
CRAH
CRAL
Block size counter
CRAH
CRB
Block transfer counter
CRB − 1
Note:
*
Transfer information write-back is skipped.
Page 224 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Transfer source data area
SAR
1st block
:
:
:
Transfer destination data area
(specified as block area)
Transfer
Block area
DAR
Nth block
Figure 8.8 Memory Map in Block Transfer Mode
(When Transfer Destination is Specified as Block Area)
8.5.6
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed
consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB
set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB,
MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the
chain transfer operation.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source
flag for the activation source and DTCER are not affected.
In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB
to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 225 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Data area
Transfer source data (1)
Transfer information
stored in user area
Vector table
Transfer destination data (1)
DTC vector
address
Transfer information
start address
Transfer information
CHNE = 1
Transfer information
CHNE = 0
Transfer source data (2)
Transfer destination data (2)
Figure 8.9 Operation of Chain Transfer
Page 226 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.5.7
Section 8 Data Transfer Controller (DTC)
Operation Timing
Figures 8.10 to 8.15 show the DTC operation timings.
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
Vector read
Transfer information
read
W
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.10 Example of DTC Operation Timing:
Normal Transfer Mode or Repeat Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
Vector read
Transfer information
read
W
R
Data
transfer
W
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 227 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
Vector read
Transfer information
read
W
Data
transfer
R
Transfer information
write
Transfer information
read
W
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.12 Example of DTC Operation Timing: Chain Transfer
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
Vector read
Transfer information
read
W
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.13 Example of DTC Operation Timing:
Short Address Mode and Normal Transfer Mode or Repeat Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Page 228 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request
DTC request
R
Internal address
Vector read
Transfer information
read
W
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.14 Example of DTC Operation Timing: Normal Transfer, Repeat Transfer,
DTPR=1 (Activated by On-Chip Peripheral Module; Iφ: Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer
Information is Written in 3 Cycles)
Clock (Bφ)
DTC activation
request
by pins IRQ
DTC request
Internal address
R
Vector read
Transfer information
read
Data
transfer
W
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.15 Example of DTC Operation Timing: Normal Transfer, Repeat Transfer,
(Activated by IRQ; Iφ: Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer
Information is Written in 3 Cycles)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 229 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
8.5.8
Number of DTC Execution Cycles
Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the
number of cycles required for each execution.
Table 8.9
DTC Execution Status
Mode
Vector
Read
I
Normal
1
0*1
4
0*1
3
2*2
Repeat
1
0*1
4
0*1
3
Block
transfer
1
0*1
4
0*1
3
Transfer
Information
Read
J
Transfer
Information
Write
K
Data Read
L
Data
Write
M
Internal
Operation
N
1*3
1
1
1
0*1
2*2
1*3
1
1
1
0*1
2*2
1*3
1•P
1•P
1
0*1
[Legend]
P: Block size (CRAH and CRAL value)
Notes: 1. When transfer information read is skipped
2. When the SAR or DAR is in fixed mode
3. When the SAR and DAR are in fixed mode
Page 230 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Table 8.10 Number of Cycles Required for Each Execution State
On-Chip
On-Chip
Object to be Accessed
RAM*1
Flash Memory On-Chip I/O Registers
Bus width
32 bits
32 bits
8 bits*4
16 bits
8 bits
16 bits
32 bits
3Bφ to 4Iφ +
2Pφ
2Pφ
2Bφ
2Bφ
2Bφ
⎯
⎯
9Bφ
5Bφ
3Bφ
⎯
⎯
⎯
9Bφ
5Bφ
3Bφ
⎯
⎯
⎯
2Bφ*6
2Bφ*6
2Bφ*6
1Bφ to 3Bφ*1
⎯
1Bφ + 2Pφ*3
1Bφ + 2Pφ*3
3Bφ
3Bφ
3Bφ
Word data read SL
1Bφ to 3Bφ*
1
⎯
⎯
1Bφ + 2Pφ*
3
5Bφ
3Bφ
3Bφ
Longword data read SL
1Bφ to 3Bφ*1
⎯
⎯
1Bφ + 2Pφ*3
9Bφ
5Bφ
Byte data write SM
1Bφ to 3Bφ*
1
⎯
1Bφ + 2Pφ*
Word data write SM
1Bφ to 3Bφ*1
⎯
⎯
Longword data write SM
1Bφ to 3Bφ*1
⎯
⎯
Access cycles
1Bφ to 3Bφ*
1
External Device*5
3Bφ*2
Exe-
Vector read SI
1Bφ to 3Bφ*1
status
3Bφ to 4Iφ +
3Bφ*2
cution
Transfer information read 1Bφ to 3Bφ*1
SJ
Transfer information write 1Bφ to 3Bφ*1
Sk
Byte data read SL
3
1Bφ + 2Pφ*
6
3Bφ
2Bφ*
6
2Bφ*
2Bφ*6
1Bφ + 2Pφ*3
2Bφ*6
2Bφ*6
2Bφ*6
1Bφ + 2Pφ*3
2Bφ*6
2Bφ*6
2Bφ*6
Internal operation SN
3
1
Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of Iφ:Bφ.
Read
Write
Iφ:Bφ = 1:1
3Bφ
2Bφ
Iφ:Bφ = 1:1/2
2Bφ
2Bφ
Iφ:Bφ = 1:1/4
2Bφ
2Bφ
Iφ:Bφ = 1:1/8
1Bφ
1Bφ
2. Values for on-chip flash memory. Number of cycles varies depending on the ratio of
Iφ:Bφ.
Read
Write
Iφ:Bφ = 1:1
4Iφ + 3Bφ
4Iφ + 3Bφ
Iφ:Bφ = 1:1/2
4Iφ + 3Bφ
4Iφ + 3Bφ
Iφ:Bφ = 1:1/4
4Iφ + 3Bφ
4Iφ + 3Bφ
Iφ:Bφ = 1:1/8
3Bφ
3Bφ
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 231 of 1778
Section 8 Data Transfer Controller (DTC)
SH7280 Group, SH7243 Group
3. The values in the table are those for the fastest case. Depending on the state of the
internal bus, replace 1Bφ by 1Pφ in a slow case.
2
4. Value for I C2.
5. Values are different depending on the BSC register setting. The values in the table are
the sample for the case with no wait cycles and the WM bit in CSnWCR = 1.
6. Values are different depending on the bus state.
The number of cycles increases when many external wait cycles are inserted in the
case where writing is frequently executed, such as block transfer, and when the
external bus is in use because the write buffer cannot be used efficiently in such cases.
For details on the write buffer, see section 9.5.12 (2), Access from the Side of the LSI
Internal Bus Master.
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in
transfer information plus 1).
Number of execution cycles = I • SI + Σ (J • SJ + K • SK + L • SL + M • SM) + N • SN
8.5.9
DTC Bus Release Timing
The DTC requests the bus mastership of the internal bus (I bus) to the bus arbiter when an
activation request occurs. The DTC releases the bus after a vector read, transfer information read,
a single data transfer, or transfer information write-back. The DTC does not release the bus
mastership during transfer information read, a single data transfer, or write-back of transfer
information.
The bus release timing can be specified through the bus function extending register (BSCEHR).
For details see section 9.4.8, Bus Function Extending Register (BSCEHR). The difference in bus
release timing according to the register setting is summarized in table 8.11. Settings other than
shown in the table are prohibited. The value of BSCEHR must not be modified while the DTC is
active.
Figure 8.16 is a timing chart showing an example of bus release timing.
Page 232 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Table 8.11 DTC Bus Release Timing
Bus Release Timing
(O: Bus must be released;
x: Bus is not released)
Bus Function
Extending Register
(BSCEHR) Setting
Setting 1
DTLOCK
DTBST
After
Transfer
After a
After Vector Information Single data
Read
Transfer
Read
After Write-Back of
Transfer Information
Normal
Transfer
Continuous
Transfer
0
0
×
×
×
O
O
1
0
1
×
×
×
O
×
2
1
0
O
O
O
O
O
Setting 2*
Setting 3*
Notes: 1. The following restrictions apply to setting 2.
• The clock setting through the frequency control register (FROCR) must be Iφ : Bφ : Pφ :
Mφ : Aφ = 8 : 4 : 4 : 8 : 4 or 8 : 4 : 4 : 4 : 4
• The vector information must be stored in the on-chip flash memory or RAM.
• The transfer information must be stored in the on-chip RAM.
• Transfer must be between the on-chip RAM and an on-chip peripheral module or
between the external memory and an on-chip peripheral module.
2. The following restriction applies to setting 3.
• Use the DTPR bit in BSCEHR with this bit set to 0. Setting this bit to 1 is prohibited.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 233 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request 1
DTC activation
request 2
DTC request
Bus release timing
(setting 3)
Bus release timing
(setting 1)
Bus release timing
(setting 2)
R
Internal address
Vector
read
Transfer information
read
W
Data
transfer
R
Transfer
information
write
Vector
read
Transfer information
read
W
Data
transfer
Transfer
information
write
: Indicates bus mastership release timing.
: Bus mastership is only released for the external access request from the CPU.
Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined.
Figure 8.16 Example of DTC Operation Timing:
Conflict of Two Activation Requests in Normal Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ : Bφ : Pφ = 1 : 1/2 : 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Page 234 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.5.10
Section 8 Data Transfer Controller (DTC)
DTC Activation Priority Order
If multiple DTC activation requests are generated while the DTC is inactive, whether to start the
DTC transfer from the first activation request* or according to the DTC activation priority can be
selected through the DTPR bit setting in the bus function extending register (BSCEHR). If
multiple activation requests are generated while the DTC is active, transfer is performed according
to the DTC activation priority. Figure 8.17 shows an example of DTC activation according to the
priority.
Note: * When one DTC-activation request is generated before another, transfer starts with the
first request. When an activation request with a higher priority is generated before a
pending DTC request is accepted, transfer starts for the request with higher priority.
Timing of DTC request generation varies according to the operating state of internal
buses.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 235 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
(1) DTPR = 0
DTC is active
DTC is inactive
Transfer is started for the first activation request
Internal bus
Other than DTC
Transfer is performed according to the priority
DTC
(request 3)
DTC
(request 1)
DTC
(request 2)
Priority
determination
DTC request
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
(2) DTPR = 1
DTC is inactive
DTC is active
Transfer is started according to the priority
Internal bus
DTC request
DTC activation request 1
(High priority)
Other than DTC
DTC
(request 1)
Transfer is performed according to the priority
DTC
(request 2)
DTC
(request 3)
Priority
determination
Priority
determination
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
Figure 8.17 Example of DTC Activation According to Priority
Page 236 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.6
Section 8 Data Transfer Controller (DTC)
DTC Activation by Interrupt
The procedure for using the DTC with interrupt activation is shown in figure 8.18.
DTC activation by interrupt
Clear RRS bit in DTCCR to 0
[1]
Set transfer information
(MRA, MRB, SAR, DAR,
CRA, CRB)
[2]
Set starts address of transfer
information in DTC vector table
[3]
Set RRS bit in DTCCR to 1
[4]
[1] Clearing the RRS bit in DTCCR to 0 clears the read skip flag
of transfer information. Read skip is not performed when the
DTC is activated after clearing the RRS bit. When updating
transfer information, the RRS bit must be cleared.
[2] Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer
information in the data area. For details on setting transfer
information, see section 8.2, Register Descriptions. For details
on location of transfer information, see section 8.4, Location of
Transfer Information and DTC Vector Table.
[3] Set the start address of the transfer information in the DTC
vector table. For details on setting DTC vector table, see section
8.4, Location of Transfer Information and DTC Vector Table.
Set corresponding bit in
DTCER to 1
[5]
Set enable bit of interrupt
request for activation source
to 1
[6]
[4] Setting the RRS bit to 1 performs a read skip of second time or
later transfer information when the DTC is activated consecutively by the same interrupt source. Setting the RRS bit to 1 is
always allowed. However, the value set during transfer will be
valid from the next transfer.
[5] Set the bit in DTCER corresponding to the DTC activation
interrupt source to 1. For the correspondence of interrupts and
DTCER, refer to table 8.2. The bit in DTCER may be set to 1 on
the second or later transfer. In this case, setting the bit is not
needed.
Interrupt request generated
[6] Set the enable bits for the interrupt sources to be used as the
activation sources to 1. The DTC is activated when an interrupt
used as an activation source is generated. For details on the
settings of the interrupt enable bits, see the corresponding
descriptions of the corresponding module.
DTC activated
Determine
clearing method of
activation source
Clear corresponding
bit in DTCER
Clear
activation
source
[7]
[7] After the end of one data transfer, the DTC clears the activation
source flag or clears the corresponding bit in DTCER and
requests an interrupt to the CPU. The operation after transfer
depends on the transfer information. For details, see section
8.2, Register Descriptions and figure 8.4.
Corresponding bit in DTCER
cleared or CPU interrupt
requested
Transfer end
Figure 8.18 DTC Activation by Interrupt
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 237 of 1778
Section 8 Data Transfer Controller (DTC)
8.7
Examples of Use of the DTC
8.7.1
Normal Transfer Mode
SH7280 Group, SH7243 Group
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The
DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0,
DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where
the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive
end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation
will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination
processing should be performed in the interrupt handling routine.
Page 238 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.7.2
Section 8 Data Transfer Controller (DTC)
Chain Transfer when Transfer Counter = 0
By executing a second data transfer and performing re-setting of the first data transfer only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is
assumed to have been set to start at lower address H'0000. Figure 8.19 shows the chain transfer
when the counter value is 0.
1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source
address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first
data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at
addresses H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for resetting the transfer destination address for the first data transfer. Use the upper eight bits of
DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0.
If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits
of the transfer source address for the first data transfer to H'21. The lower 16 bits of the
transfer destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper eight bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
no interrupt request is sent to the CPU.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 239 of 1778
SH7280 Group, SH7243 Group
Section 8 Data Transfer Controller (DTC)
Input circuit
Transfer information
located on the on-chip memory
Input buffer
1st data transfer
information
Chain transfer
(counter = 0)
2nd data transfer
information
Upper 8 bits of DAR
Figure 8.19 Chain Transfer when Transfer Counter = 0
8.8
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or on completion of a single data transfer or a single block data transfer with the DISEL
bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is
generated. These interrupts to the CPU are subject to CPU mask level and priority level control in
the interrupt controller. For details, refer to section 6.9, Data Transfer with Interrupt Request
Signals.
Page 240 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.9
Usage Notes
8.9.1
Module Standby Mode Setting
Section 8 Data Transfer Controller (DTC)
Operation of the DTC can be disabled or enabled using the standby control register. The initial
setting is for operation of the DTC to be enabled. DTC operation is disabled in module standby
mode but register access is available. However, do not place the DTC in module standby mode
while it is active. Before entering software standby mode or module standby mode, all DTCER
registers must be cleared. For details, refer to section 28, Power-Down Modes.
8.9.2
On-Chip RAM
Transfer information can be located in on-chip RAM. In this case, the RAME bit in RAMCR must
not be cleared to 0.
8.9.3
DTCE Bit Setting
To set a DTCE bit, disable the corresponding interrupt, read 0 from the bit, and then write 1 to it.
While DTC transfer is in progress, do not modify the DTCE bits.
8.9.4
Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. SCI, SSU, RCAN-ET, SCIF, IIC3, USB, and A/D
converter interrupt/activation sources, on the other hand, are cleared when the DTC reads from or
writes to the relevant register when the last of the chain of data transfers is executed.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
8.9.5
Transfer Information Start Address, Source Address, and Destination Address
The transfer information start address to be specified in the vector table should be address 4n.
Transfer information should be placed in on-chip RAM or external memory space.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 241 of 1778
Section 8 Data Transfer Controller (DTC)
8.9.6
SH7280 Group, SH7243 Group
Access to DTC Registers through DTC
Do not access the DMAC or DTC registers by using DTC operation. Do not access the DTC
registers by using DMAC operation.
8.9.7
Note on IRQ Interrupt as DTC Activation Source
When a low level on the IRQ pin is to be detected, if the end of DTC transfer is used to request an
interrupt to the CPU (transfer counter = 0 or DISEL = 1), the IRQ signal must be held low until
the CPU accepts the interrupt.
8.9.8
Note on SCI or SCIF as DTC Activation Sources
When the TXI interrupt from the SCI is specified as a DTC activation source, the TEND flag in
the SCI must not be used as the transfer end flag.
When the TXIF interrupt from the SCIF is specified as a DTC activation source, the TEND flag in
the SCIF must not be used as the transfer end flag.
8.9.9
Clearing Interrupt Source Flag
The interrupt source flag set when the DTC transfer is completed should be cleared in the interrupt
handler in the same way as for general interrupt source flags. For details, refer to section 6.10,
Usage Notes.
8.9.10
Conflict between NMI Interrupt and DTC Activation
When a conflict occurs between the generation of the NMI interrupt and the DTC activation, the
NMI interrupt has priority. Thus the ERR bit is set to 1 and the DTC is not activated.
It takes 3Bφ + 2Pφ for checking DTC stop by the NMI, 3Bφ + 2Pφ for checking DTC activation
by the IRQ, and 1Bφ + 1Pφ to 4Bφ + 1Pφ for checking DTC activation by the peripheral module.
8.9.11
Note on USB as DTC Activation Sources
To generate a CPV interrupt when a DTC transfer activated by the USB is completed, refer to the
procedure described in section 25, USB Function Module.
Page 242 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
8.9.12
Section 8 Data Transfer Controller (DTC)
Operation when a DTC Activation Request has been Cancelled
Once DTC has accepted an activation request, the next activation request will not be accepted
until the sequence of the DTC transaction has finished up to the end of write-back.
8.9.13
Note on Writing to DTCER
When the same condition has been set as both a DTC activation source and a CPU interrupt
source, if the interrupt as both sources is generated while DTCER is also set for the DTC
activation source, the DTC and CPU may be activated at the same time. Determine the value of
DTCER before allowing the generation of DTC activation interrupts.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 243 of 1778
Section 8 Data Transfer Controller (DTC)
Page 244 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Section 9 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. BSC functions enable this LSI to
connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.
9.1
Features
The BSC has the following features.
1. External address space
⎯ A maximum of 64 Mbytes for each of areas CS0 to CS7.
⎯ Can specify the normal space interface, SRAM interface with byte selection, burst ROM
(clock synchronous or asynchronous), MPX-I/O, and SDRAM for each address space.
⎯ Can select the data bus width (8, 16, or 32 bits) for each address space.
⎯ Controls insertion of wait cycles for each address space.
⎯ Controls insertion of wait cycles for each read access and write access.
⎯ Can set independent idle cycles during the continuous access for five cases: read-write (in
same space/different spaces), read-read (in same space/different spaces), the first cycle is a
write access.
2. Normal space interface
⎯ Supports the interface that can directly connect to the SRAM.
3. Burst ROM interface (clock asynchronous)
⎯ High-speed access to the ROM that has the page mode function.
4. MPX-I/O interface
⎯ Can directly connect to a peripheral LSI that needs an address/data multiplexing.
5. SDRAM interface
⎯ Can set the SDRAM in up to two areas.
⎯ Multiplex output for row address/column address.
⎯ Efficient access by single read/single write.
⎯ High-speed access in bank-active mode.
⎯ Supports an auto-refresh and self-refresh.
⎯ Supports low-frequency and power-down modes.
⎯ Issues MRS and EMRS commands.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 245 of 1778
Section 9 Bus State Controller (BSC)
SH7280 Group, SH7243 Group
6. SRAM interface with byte selection
⎯ Can connect directly to a SRAM with byte selection.
7. Burst ROM interface (clock synchronous)
⎯ Can connect directly to a ROM of the clock-synchronous type.
8. Bus arbitration
⎯ Shares all of the resources with other CPU and outputs the bus enable after receiving the
bus request from external devices.
9. Refresh function
⎯ Supports the auto-refresh and self-refresh functions.
⎯ Specifies the refresh interval using the refresh counter and clock selection.
⎯ Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
10. Usage as interval timer for refresh counter
⎯ Generates an interrupt request at compare match.
Figure 9.1 shows a block diagram of the BSC.
Page 246 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
BACK
Bus
mastership
controller
Internal bus
BREQ
Section 9 Bus State Controller (BSC)
CMNCR
CS0WCR
...
Wait
controller
...
WAIT
CS7WCR
...
Module bus
CS7BCR
MD1, MD0
A25 to A0*,
D31 to D0*
BS, RD/WR,
RD, WRx,
RASL, RASU*,
CASL, CASU*,
CKE, DQMxx, AH,
CS0BCR
...
Area
controller
...
CS0 to CS7
Memory
controller
SDCR
RTCSR
REFOUT
Refresh
controller
RTCNT
Comparator
RTCOR
BSC
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0 to 7)
CSnBCR: CSn space bus control register (n = 0 to 7)
SDRAM control register
SDCR:
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Note * A20 to A0, D15 to D0, RASL, and CASL are available only in the SH7285 and the SH7243.
Figure 9.1 Block Diagram of BSC
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 247 of 1778
Section 9 Bus State Controller (BSC)
9.2
SH7280 Group, SH7243 Group
Input/Output Pins
Table 9.1 shows the pin configuration of the BSC.
Table 9.1
Pin Configuration
Name
I/O
Function
A25 to A0
Output Address bus (A20 to A0 in SH7285 and SH7243)
D31 to D0
I/O
BS
Output Bus cycle start
CS0 to CS7
Output Chip select
RD/WR
Output Read/write
Data bus (D15 to D0 in SH7285 and SH7243)
Connects to WE pins when SDRAM or SRAM with byte selection is
connected.
RD
Output Read pulse signal (read data output enable signal)
Functions as a strobe signal for indicating memory read cycles when
PCMCIA is used.
AH
Output A signal used to hold an address when MPX-I/O is in use
WRHH/DQMUU Output Indicates that D31 to D24 are being written to (only in SH7286).
Connected to the byte select signal when SRAM with byte selection is
connected.
Functions as the select signals for D31 to D24 when SDRAM is
connected.
WRHL/DQMUL
Output Indicates that D23 to D26 are being written to (only in SH7286).
Connected to the byte select signal when SRAM with byte selection is
connected.
Functions as the select signals for D23 to D26 when SDRAM is
connected.
WRH/DQMLU
Output Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a SRAM with byte selection
is connected.
Functions as the select signals for D15 to D8 when SDRAM is
connected.
Page 248 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Name
I/O
Function
WRL/DQMLL
Output Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a SRAM with byte selection
is connected.
Functions as the select signals for D7 to D0 when SDRAM is
connected.
RASL, RASU
Output Connected to RAS pin when SDRAM is connected (RASU is available
only in the SH7286).
CASL, CASU
Output Connected to CAS pin when SDRAM is connected (CASU is available
only in the SH7286).
CKE
Output Connected to CKE pin when SDRAM is connected.
WAIT
Input
External wait input
BREQ
Input
Bus request input
BACK
Output Bus enable output
REFOUT
Output Refresh request output in bus-released state
MD0
Input
Selects bus width of area 0.
8 or 16 bits: SH7285 and SH7243
16 or 32 bits: SH7286
It also selects the on-chip ROM enabled or disabled mode and external
bus access enabled or disabled mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 249 of 1778
Section 9 Bus State Controller (BSC)
9.3
Area Overview
9.3.1
Address Map
SH7280 Group, SH7243 Group
In the architecture, this LSI has a 32-bit address space, which is divided into external address
space and on-chip spaces (on-chip ROM, on-chip RAM, on-chip peripheral modules, and reserved
areas) according to the upper bits of the address.
The kind of memory to be connected and the data bus width are specified in each partial space.
The address map for the external address space is listed below.
Page 250 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 9.2
Section 9 Bus State Controller (BSC)
Address Map in On-Chip ROM-Enabled Mode
Address
Space
Memory to be Connected
Size
H'0000 0000 to H'000F FFFF
On-chip ROM
On-chip ROM
256 Kbytes
(SH7243)
768 Kbytes
(SH7285)
1 Mbytes
(SH7286)
H'0070 0000 to H'01FF FFFF
Other
Reserved area
⎯
H'0200 0000 to H'03FF FFFF
CS0
Normal space, SRAM with byte selection,
burst ROM (asynchronous or synchronous)
32 Mbytes
H'0400 0000 to H'07FF FFFF
CS1
Normal space, SRAM with byte selection
64 Mbytes
H'0800 0000 to H'0BFF FFFF
CS2
Normal space, SRAM with byte selection,
SDRAM
64 Mbytes
H'0C00 0000 to H'0FFF FFFF
CS3
Normal space, SRAM with byte selection,
SDRAM
64 Mbytes
H'1000 0000 to H'13FF FFFF
CS4
Normal space, SRAM with byte selection,
burst ROM (asynchronous)
64 Mbytes
H'1400 0000 to H'17FF FFFF
CS5
Normal space, SRAM with byte selection,
MPX-I/O
64 Mbytes
H'1800 0000 to H'1BFF FFFF
CS6
Normal space, SRAM with byte selection
64 Mbytes
H'1C00 0000 to H'1FFF FFFF
CS7
Normal space, SRAM with byte selection
64 Mbytes
H'2000 0000 to H'FFF7 FFFF
Other
Reserved area
⎯
H'FFF8 0000 to H'FFFB FFFF
Other
On-chip RAM, reserved area*
⎯
H'FFFC 0000 to H'FFFF FFFF
Other
On-chip peripheral modules, reserved area*
⎯
Note:
*
For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM.
For the on-chip peripheral module space, access the addresses shown in section 30,
List of Registers. Do not access addresses which are not described in these sections.
Otherwise, the correct operation cannot be guaranteed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 251 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.3
Address Map in On-Chip ROM-Disabled Mode
Address
Space
Memory to be Connected
Size
H'0000 0000 to H'03FF FFFF
CS0
Normal space, SRAM with byte selection,
burst ROM (asynchronous or synchronous)
64 Mbytes
H'0400 0000 to H'07FF FFFF
CS1
Normal space, SRAM with byte selection
64 Mbytes
H'0800 0000 to H'0BFF FFFF
CS2
Normal space, SRAM with byte selection,
SDRAM
64 Mbytes
H'0C00 0000 to H'0FFF FFFF
CS3
Normal space, SRAM with byte selection,
SDRAM
64 Mbytes
H'1000 0000 to H'13FF FFFF
CS4
Normal space, SRAM with byte selection,
burst ROM (asynchronous)
64 Mbytes
H'1400 0000 to H'17FF FFFF
CS5
Normal space, SRAM with byte selection,
MPX-I/O
64 Mbytes
H'1800 0000 to H'1BFF FFFF
CS6
Normal space, SRAM with byte selection
64 Mbytes
H'1C00 0000 to H'1FFF FFFF
CS7
Normal space, SRAM with byte selection
64 Mbytes
H'2000 0000 to H'FFF7 FFFF
Other
Reserved area
⎯
H'FFF8 0000 to H'FFFB FFFF
Other
On-chip RAM, reserved area*
⎯
H'FFFC 0000 to H'FFFF FFFF
Other
On-chip peripheral modules, reserved area*
⎯
Note:
*
For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM.
For the on-chip I/O register space, access the addresses shown in section 30, List of
Registers. Do not access addresses which are not described in these sections.
Otherwise, the correct operation cannot be guaranteed.
Page 252 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.3.2
Section 9 Bus State Controller (BSC)
Setting Operating Modes
This LSI can set the following modes of operation at the time of power-on reset using the external
pins.
• Single-Chip Mode/External Bus Accessible Mode
In single-chip mode, no access is made to the external bus, and the LSI is activated by the onchip ROM program upon a power-on reset. The BSC module enters the module standby state
to reduce power consumption.
The address, data, bus control pins used in external bus accessible mode can be used as the
port function pins in single-chip mode.
• On-Chip ROM-Enabled Mode/On-Chip ROM-Disabled Mode
In on-chip ROM-enabled mode, since the first half of area 0 is allocated to the on-chip ROM,
the LSI can be activated by the on-chip ROM program upon a power-on reset. The second half
of area 0 is the external memory space.
In on-chip ROM-disabled mode, the LSI is activated by the program stored in the external
memory allocated to area 0. The second half of area 0 is the external memory space. In this
case, a ROM is assumed for the external memory of area 0. Therefore, minimum functions are
provided for the pins including address bus, data bus, CS0, and RD. Although BS, RD/WR,
WRxx, and other pins are shown in the examples of access waveforms in this section, these are
examples when pin settings are performed by the pin function controller. For details, see
section 23, Pin Function Controller (PFC). Do not perform any operation except for area 0 read
access until the pin settings by the program is completed.
• Initial Settings of Data Bus Widths for Areas 0 to 7
The initial settings of data bus widths of areas 0 to 7 can be selected at a time as 16 bits or 32
bits in the SH7286 or 8 bits or 16 bits in the SH7285 and SH7243.
In on-chip ROM-disabled mode, the data bus width of area 0 cannot be changed from its initial
setting after a power-on reset, but the data bus widths of areas 1 to 7 can be changed by
register settings in the program. In on-chip ROM-enabled mode, all the data bus widths of
areas 0 to 7 can be changed by register settings in the program. Note that data bus widths will
be restricted depending on memory types.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 253 of 1778
Section 9 Bus State Controller (BSC)
SH7280 Group, SH7243 Group
• Initial Settings of Big Endian / Little Endian
The initial settings of byte-data alignment of areas 1 to 7 can be selected as big endian or little
endian. In on-chip ROM-disabled mode, the endianness of area 0 cannot be changed from its
initial setting after a power-on reset, but the endianness of areas 1 to 7 can be changed by
register settings in the program. In on-chip ROM-enabled mode, all the endianness of areas 1
to 7 can be changed by register settings in the program. Area 0 cannot be selected as little
endian. Since the instruction fetch is mixed with the 32- and 16-bit access and the allocation to
the little endian area is difficult, the instruction must be executed within the big endian area.
For details of mode settings, see section 3, MCU Operating Modes.
Page 254 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.4
Section 9 Bus State Controller (BSC)
Register Descriptions
The BSC has the following registers.
Do not access spaces other than area 0 until settings of the connected memory interface are
completed.
Table 9.4
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Common control register
CMNCR
R/W
H'00001010
H'FFFC0000
32
CSn space bus control register
CSnBCR
R/W
H'36DB0400*
H'FFFC 0004 to
H'FFFC 0020
32
CSn space wait control register
CSnWCR
R/W
H'00000500
H'FFFC0028 to
H'FFFC 0044
32
SDRAM control register
SDCR
R/W
H'00000000
H'FFFC004C
32
Refresh timer control/status register RTCSR
R/W
H'00000000
H'FFFC0050
32
Refresh timer counter
RTCNT
R/W
H'00000000
H'FFFC0054
32
Refresh time constant register
RTCOR
R/W
H'00000000
H'FFFC0058
32
Bus function extending register
BSCEHR
R/W
H'0000
H'FFFE3C1A
16
Note:
*
Value when selecting the16-bit bus width with the external pin (MD0). When selecting
the 32-bit bus width, the initial value will be H'36DB 0600 and when selecting the 8-bit
bus width, the initial value will be H'36DB 0200.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 255 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
9.4.1
Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. This register is
initialized to H'00001010 by a power-on reset and retains the value by a manual reset and in
software standby mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
6
-
-
-
-
BLOCK
0
R
0
R
0
R
1
R
0
R/W
Initial value:
R/W:
DPRTY[1:0]
0
R/W
0
R/W
DMAIW[2:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 13
⎯
All 0
R
Reserved
0
R/W
16
5
4
3
2
1
0
DMA
IWA
-
-
HIZ
CKIO
HIZ
MEM
HIZ
CNT
0
R/W
1
R
0
R
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
12
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
11
BLOCK
0
R/W
Bus Lock
Specifies whether or not the BREQ signal is received.
0: Receives BREQ.
1: Does not receive BREQ.
10, 9
DPRTY[1:0]
00
R/W
DMA Burst Transfer Priority
Specify the priority for a refresh request/bus
mastership request during DMA burst transfer.
00: Accepts a refresh request and bus mastership
request during DMA burst transfer.
01: Accepts a refresh request but does not accept a
bus mastership request during DMA burst transfer.
10: Accepts neither a refresh request nor a bus
mastership request during DMA burst transfer.
11: Reserved (setting prohibited)
Page 256 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
8 to 6
DMAIW[2:0]
000
R/W
Wait states between access cycles when DMA single
address transfer is performed.
Specify the number of idle cycles to be inserted after
an access to an external device with DACK when DMA
single address transfer is performed. The method of
inserting idle cycles depends on the contents of
DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
5
DMAIWA
0
R/W
Method of inserting wait states between access cycles
when DMA single address transfer is performed.
Specifies the method of inserting the idle cycles
specified by the DMAIW[2:0] bit. Clearing this bit will
make this LSI insert the idle cycles when another
device, which includes this LSI, drives the data bus
after an external device with DACK drove it. However,
when the external device with DACK drives the data
bus continuously, idle cycles are not inserted. Setting
this bit will make this LSI insert the idle cycles after an
access to an external device with DACK, even when
the continuous access cycles to an external device
with DACK are performed.
0: Idle cycles inserted when another device drives the
data bus after an external device with DACK drove
it.
1: Idle cycles always inserted after an access to an
external device with DACK
4
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 257 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
HIZCKIO
0
R/W
High-Z CK Control
Specifies the state in CK standby mode and when bus
mastership is released.
0: CK is in high impedance state in standby mode and
bus-released state.
1: CK is driven in standby mode and bus-released
state.
1
HIZMEM
0
R/W
High-Z Memory Control
Specifies the pin state in standby mode for A25 to A0,
BS, CSn, RD/WR, WRxx/DQMxx, AH, and RD. At busreleased state, these pins are in high-impedance state
regardless of the setting value of the HIZMEM bit.
0: High impedance in standby mode.
1: Driven in standby mode
0
HIZCNT
0
R/W
High-Z Control
Specifies the state in standby mode and bus-released
state for CKE, RASL, CASL, RASU, and CASU.
0: CKE, RASL, CASL, RASU, and CASU are in highimpedance state in standby mode and bus-released
state.
1: CKE, RASL, CASL, RASU, and CASU are driven in
standby mode and bus-released state.
Page 258 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.4.2
Section 9 Bus State Controller (BSC)
CSn Space Bus Control Register (CSnBCR) (n = 0 to 7)
CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to a
space, data bus width of an area, endian, and the number of waits between access cycles. This
register is initialized to H'36DB0x00 by a power-on reset and retains the value by a manual reset
and in software standby mode.
Do not access external memory other than area 0 until CSnBCR initial setting is completed.
Idle cycles may be inserted even when they are not specified. For details, see section 9.5.10, Wait
between Access Cycles.
Bit:
31
30
-
Initial value:
R/W:
0
R
0
R/W
Bit:
15
14
-
Initial value:
R/W:
0
R
29
28
27
IWW[2:0]
1
R/W
1
R/W
13
12
TYPE[2:0]
0
R/W
0
R/W
26
25
24
IWRWD[2:0]
22
21
20
19
18
IWRRD[2:0]
17
16
IWRRS[2:0]
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
11
10
9
8
7
6
5
4
3
2
1
0
BSZ[1:0]
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
ENDIAN
0
R/W
23
IWRWS[2:0]
0
R/W
0*
R/W
1*
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31
⎯
0
R
30 to 28
IWW[2:0]
011
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
Idle Cycles between Write-Read Cycles and WriteWrite Cycles
These bits specify the number of idle cycles to be
inserted after the access to a memory that is
connected to the space. The target access cycles are
the write-read cycle and write-write cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 259 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Initial
Value
Bit
Bit Name
27 to 25
IWRWD[2:0] 011
R/W
Description
R/W
Idle Cycles for Another Space Read-Write
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target access cycle is a read-write one in
which continuous access cycles switch between
different spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
24 to 22
IWRWS[2:0] 011
R/W
Idle Cycles for Read-Write in the Same Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-write cycle of which
continuous access cycles are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Page 260 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
21 to 19
IWRRD[2:0]
011
R/W
Description
Idle Cycles for Read-Read in Another Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-read cycle of which
continuous access cycles switch between different
spaces.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
18 to 16
IWRRS[2:0]
011
R/W
Idle Cycles for Read-Read in the Same Space
Specify the number of idle cycles to be inserted after
the access to a memory that is connected to the
space. The target cycle is a read-read cycle of which
continuous access cycles are for the same space.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 261 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
14 to 12
TYPE[2:0]
000
R/W
Description
Specify the type of memory connected to a space.
000: Normal space
001: Burst ROM (clock asynchronous)
010: MPX-I/O
011: SRAM with byte selection
100: SDRAM
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Burst ROM (clock synchronous)
For details of memory type in each area, see tables 9.2
and 9.3.
11
ENDIAN
0
R/W
Endian Select
Specifies data alignment in a space.
0: Big endian
1: Little endian
Page 262 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10, 9
BSZ[1:0]
01*
R/W
Data Bus Width Specification
Specify the data bus widths of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size (only in SH7286, Setting prohibited both
in the SH7285 and SH7243)
For MPX-I/O, selects bus width by address.
Notes:
1. If area 5 is specified as MPX-I/O, the bus
width can be specified as 8 bits or 16 bits
by the address according to the SZSEL bit
in CS5WCR by specifying the BSZ[1:0]
bits to 11. The fixed bus width can be
specified as 8 bits or 16 bits.
2. The initial data bus width for areas 0 to 7
is specified by external pins. In on-chip
ROM-disabled mode, writing to the BSZ1
and BSZ0 bits in CS0BCR is ignored, but
the bus width settings in CS1BCR to
CS7BCR can be modified. In on-chip
ROM-enabled mode, the bus width
settings in CS0BCR to CS7BCR can be
modified.
3. If area 2 or area 3 is specified as SDRAM
space, the bus width can be specified as
16 bits or 32 bits.
4. If area 0 or 4 is specified as clocksynchronous burst ROM space, the bus
width can be specified as 16 bits only.
8 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 263 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Note:
*
9.4.3
Details of Initial value of this bit are shown below according to the product and MCU
operating mode.
Mode
SH7243
SH7285
SH7286
Mode 0
10
10
11
Mode 1
01
01
10
Mode 2
01
01
01
Mode 3
01
01
01
CSn Space Wait Control Register (CSnWCR) (n = 0 to 7)
CSnWCR specifies various wait cycles for memory access. The bit configuration of this register
varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn
space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify
CSnBCR first, then specify CSnWCR.
CSnWCR is initialized to H'00000500 by a power-on reset and retains the value by a manual reset
and in software standby mode.
(1)
Normal Space, SRAM with Byte Selection, MPX-I/O
• CS0WCR
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
BAS
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
1
0
-
-
-
0
R/W
0
R/W
0
R/W
SW[1:0]
0
R/W
WR[3:0]
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 21
⎯*
All 0
R/W
Reserved
6
5
4
3
2
WM
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
16
HW[1:0]
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
Page 264 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
20
BAS*
0
R/W
Byte Access Selection when SRAM with Byte
Selection is Used
Specifies the WRxx and RD/WR signal timing when
the SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read/write timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WRxx signal during the read/write
access cycle and asserts the RD/WR signal at the
write timing.
19 to 13
⎯*
All 0
R/W
Reserved
Set these bits to 0 when the interface for normal space
or SRAM with byte selection is used.
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address, CS0 Assertion
to RD, WRxx Assertion
Specify the number of delay cycles from address and
CS0 assertion to RD and WRxx assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 265 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 7
WR[3:0]
1010
R/W
Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 266 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD, WRxx Negation to Address,
CS0 Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CS0 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Note
*
To connect the burst ROM to the CS0 space and switch to the burst ROM interface
after activation in ROM-disabled mode, set the TYPE[2:0] bits in CS0BCR after setting
the burst number by the bits 20 and 21 and the burst wait cycle number by the bits 16
and 17. Do not write 1 to the reserved bits other than above bits.
• CS1WCR, CS7WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
-
-
-
-
-
-
-
-
-
-
-
BAS
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
1
0
-
-
-
0
R
0
R
0
R
Initial value:
R/W:
SW[1:0]
0
R/W
WR[3:0]
0
R/W
1
R/W
Bit
Bit Name
Initial
Value
R/W
31 to 21
⎯
All 0
R
0
R/W
1
R/W
0
R/W
18
17
16
WW[2:0]
6
5
4
3
2
WM
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
HW[1:0]
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
20
BAS
0
R/W
SRAM with Byte Selection Byte Access Select
Specifies the WRxx and RD/WR signal timing when
the SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read/write timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WRxx signal during the read/write
access cycle and asserts the RD/WR signal at the
write timing.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 267 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
19
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16
WW[2:0]
000
R/W
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address, CSn Assertion
to RD, WRxx Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WRxx assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Page 268 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 7
WR[3:0]
1010
R/W
Number of Read Access Wait Cycles
Specify the number of cycles that are necessary for
read access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD, WRxx Negation to Address,
CSn Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 269 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
• CS2WCR, CS3WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
BAS
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
0
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Initial value:
R/W:
WR[3:0]
1
R/W
0
R/W
1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 21
⎯
All 0
R
Reserved
6
5
4
3
2
1
WM
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
These bits are always read as 0. The write value
should always be 0.
20
BAS
0
R/W
SRAM with Byte Selection Byte Access Select
Specifies the WRxx and RD/WR signal timing when
the SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WRxx signal during the read access
cycle and asserts the RD/WR signal at the write
timing.
19 to 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 270 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 7
WR[3:0]
1010
R/W
Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 271 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
• CS4WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
-
-
-
-
-
-
-
-
-
-
-
BAS
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R/W
0
R/W
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
1
0
-
-
-
0
R
0
R
0
R
Initial value:
R/W:
SW[1:0]
0
R/W
WR[3:0]
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 21
⎯
All 0
R
Reserved
18
17
16
WW[2:0]
6
5
4
3
2
WM
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
HW[1:0]
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
20
BAS
0
R/W
SRAM with Byte Selection Byte Access Select
Specifies the WRxx and RD/WR signal timing when
the SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WRxx signal during the read access
cycle and asserts the RD/WR signal at the write
timing.
19
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16
WW[2:0]
000
R/W
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Page 272 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address, CS4 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS4 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 to 7
WR[3:0]
1010
R/W
Number of Read Access Wait Cycles
Specify the number of cycles that are necessary for
read access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 273 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
6
WM
0
R/W
Description
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
⎯
5 to 2
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD, WRxx Negation to Address,
CS4 Negation
Specify the number of delay cycles from RD and WRxx
negation to address and CS4 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
-
-
-
-
-
-
-
-
-
-
SZSEL
MPXW/
BAS
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
0
-
-
-
0
R
0
R
0
R
Initial value:
R/W:
SW[1:0]
0
R/W
WR[3:0]
0
R/W
1
R/W
Bit
Bit Name
Initial
Value
R/W
31 to 22
⎯
All 0
R
0
R/W
1
R/W
0
R/W
18
17
16
WW[2:0]
6
5
4
3
2
1
WM
-
-
-
-
HW[1:0]
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 274 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
21
SZSEL
0
R/W
MPX-I/O Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BCR are specified as 11. This bit is
valid only when area 5 is specified as MPX-I/O. Always
set this bit to 0 in the SH7285 and SH7243.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus width
selected by A14 or A21 are summarized below.
20
MPXW
0
R/W
SZSEL
A14
A21
Bus Width
0
0
Not affected
8 bits
0
1
Not affected
16 bits
1
Not affected
0
8 bits
1
Not affected
1
16 bits
MPX-I/O Interface Address Wait
This bit setting is valid only when area 5 is specified as
MPX-I/O. Specifies the address cycle insertion wait for
MPX-I/O interface.
0: Inserts no wait cycle
1: Inserts 1 wait cycle
BAS
0
R/W
SRAM with Byte Selection Byte Access Select
This bit setting is valid only when area 5 is specified as
SRAM with byte selection.
Specifies the WRxx and RD/WR signal timing when
the SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WRxx signal during the read access
cycle and asserts the RD/WR signal at the write
timing.
19
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 275 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
18 to 16
WW[2:0]
000
R/W
Description
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address, CS5 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS5 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Page 276 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
10 to 7
WR[3:0]
1010
R/W
Description
Number of Read Access Wait Cycles
Specify the number of cycles that are necessary for
read access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 277 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD, WRxx Negation to Address,
CS5 Negation
Specify the number of delay cycles from RD and
WRxx negation to address and CS5 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS6WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
BAS
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
1
0
-
-
-
0
R
0
R
0
R
Initial value:
R/W:
SW[1:0]
0
R/W
WR[3:0]
0
R/W
1
R/W
Bit
Bit Name
Initial
Value
R/W
31 to 21
⎯
All 0
R
0
R/W
1
R/W
0
R/W
6
5
4
3
2
WM
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
16
HW[1:0]
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
20
BAS
0
R/W
SRAM with Byte Selection Byte Access Select
Specifies the WRxx and RD/WR signal timing when
the SRAM interface with byte selection is used.
0: Asserts the WRxx signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WRxx signal during the read/write
access cycle and asserts the RD/WR signal at the
write timing.
19 to 13
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 278 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address, CS6 Assertion
to RD, WRxx Assertion
Specify the number of delay cycles from address, CS6
assertion to RD and WRxx assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 to 7
WR[3:0]
1010
R/W
Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WN
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification of this bit is valid even when the
number of access wait cycles is 0.
0: The external wait input is valid
1: The external wait input is ignored
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 279 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
1, 0
HW[1:0]
00
R/W
Number of Delay Cycles from RD, WRxx Negation to
Address, CS6 Negation
Specify the number of delay cycles from RD, WRxx
negation to address, and CS6 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
(2)
Burst ROM (Clock Asynchronous)
• CS0WCR
Bit:
31
30
29
28
27
26
25
24
23
22
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Initial value:
R/W:
W[3:0]
1
R/W
0
R/W
1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 22
⎯
All 0
R
Reserved
21
20
19
18
-
-
0
R/W
0
R
0
R
0
R/W
0
R/W
0
BST[1:0]
17
16
BW[1:0]
6
5
4
3
2
1
WM
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
These bits are always read as 0. The write value
should always be 0.
Page 280 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
21, 20
BST[1:0]
00
R/W
Burst Count Specification
Specify the burst count for 16-byte access. These bits
must not be set to B'11.
Bus Width
BST[1:0]
Burst count
8 bits
00
16 burst × one time
01
4 burst × four times
00
8 burst × one time
01
2 burst × four times
10
4-4 or 2-4-2 burst
16 bits
19, 18
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
17, 16
BW[1:0]
00
R/W
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 281 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
10 to 7
W[3:0]
1010
R/W
Description
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the
first access cycle.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 282 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
• CS4WCR
Bit:
31
30
29
28
27
26
25
24
23
22
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
-
-
-
0
R
0
R
0
R
Initial value:
R/W:
SW[1:0]
0
R/W
W[3:0]
0
R/W
1
R/W
0
R/W
1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 22
⎯
All 0
R
Reserved
21
20
19
18
-
-
0
R/W
0
R
0
R
0
R/W
0
R/W
0
BST[1:0]
17
16
BW[1:0]
6
5
4
3
2
1
WM
-
-
-
-
HW[1:0]
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
21, 20
BST[1:0]
00
R/W
Burst Count Specification
Specify the burst count for 16-byte access. These bits
must not be set to B'11.
Bus Width
BST[1:0]
Burst count
8 bits
00
16 burst × one time
01
4 burst × four times
00
8 burst × one time
01
2 burst × four times
10
4-4 or 2-4-2 burst
16 bits
19, 18
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
17, 16
BW[1:0]
00
R/W
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 283 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address, CS4 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS4 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 to 7
W[3:0]
1010
R/W
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the
first access cycle.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Page 284 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
6
WM
0
R/W
Description
External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD, WRxx Negation to Address,
CS4 Negation
Specify the number of delay cycles from RD and
WRxx negation to address and CS4 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 285 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
(3)
SDRAM*
• CS2WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
A2CL[1:0]
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Initial value:
R/W:
Bit
Bit Name
Initial
Value
R/W
31 to 11
⎯
All 0
R
1
R/W
0
R/W
16
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
⎯
10
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
⎯
9
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8, 7
A2CL[1:0]
10
R/W
CAS Latency for Area 2
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
⎯
6 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note:
*
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or SRAM with byte selection.
Page 286 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
• CS3WCR
Bit: 31
Initial value:
R/W:
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
14
13
12
11
10
4
3
2
1
0
Bit: 15
-
Initial value:
R/W:
0
R
WTRP[1:0]*
0
R/W
0
R/W
9
8
7
6
5
-
WTRCD[1:0]*
-
A3CL[1:0]
-
-
0
R
0
R/W
0
R
0
R
0
R
1
R/W
1
R/W
0
R/W
TRWL[1:0]*
0
R/W
0
R/W
-
0
R
WTRC[1:0]*
0
R/W
0
R/W
Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0],
and WTRC[1:0] bit settings are used in both areas in common.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 15
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
14, 13
WTRP[1:0]*
00
R/W
Number of Auto-Precharge Completion Wait Cycles
Specify the number of minimum precharge completion
wait cycles as shown below.
•
From the start of auto-precharge and issuing of
ACTV command for the same bank
•
From issuing of the PRE/PALL command to issuing
of the ACTV command for the same bank
•
Till entering power-down mode or deep powerdown mode
•
From the issuing of PALL command to issuing REF
command in auto-refresh mode
•
From the issuing of PALL command to issuing
SELF command in self-refresh mode
The setting for areas 2 and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 287 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
12
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
11, 10
WTRCD[1:0]* 01
R/W
Number of Wait Cycles between ACTV Command and
READ(A)/WRIT(A) Command
Specify the minimum number of wait cycles from
issuing the ACTV command to issuing the
READ(A)/WRIT(A) command. The setting for areas 2
and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
9
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8, 7
A3CL[1:0]
10
R/W
CAS Latency for Area 3
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6, 5
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 288 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
4, 3
TRWL[1:0]*
00
R/W
Number of Auto-Precharge Startup Wait Cycles
Specify the number of minimum auto-precharge
startup wait cycles as shown below.
•
Cycle number from the issuance of the WRITA
command by this LSI until the completion of autoprecharge in the SDRAM.
Equivalent to the cycle number from the issuance
of the WRITA command until the issuance of the
ACTV command. Confirm that how many cycles
are required between the WRITE command receive
in the SDRAM and the auto-precharge activation,
referring to each SDRAM data sheet. And set the
cycle number so as not to exceed the cycle number
specified by this bit.
•
Cycle number from the issuance of the WRITA
command until the issuance of the PRE command.
This is the case when accessing another low
address in the same bank in bank active mode.
The setting for areas 2 and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
2
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 289 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Initial
Value
Bit
Bit Name
1, 0
WTRC[1:0]* 00
R/W
Description
R/W
Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command
Specify the number of minimum idle cycles in the
periods shown below.
•
From the issuance of the REF command until the
issuance of the ACTV/REF/MRS command
•
From releasing self-refresh until the issuance of the
ACTV/REF/MRS command.
The setting for areas 2 and 3 is common.
00: 2 cycles
01: 3 cycles
10: 5 cycles
11: 8 cycles
Note:
*
If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0],
and WTRC[1:0] bit settings are used in both areas in common.
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or SRAM with byte selection.
Page 290 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(4)
Section 9 Bus State Controller (BSC)
Burst ROM (Clock Synchronous)
• CS0WCR
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
0
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Initial value:
R/W:
W[3:0]
1
R/W
0
R/W
1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 18
⎯
All 0
R
Reserved
17
16
BW[1:0]
6
5
4
3
2
1
WM
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
These bits are always read as 0. The write value
should always be 0.
17, 16
BW[1:0]
00
R/W
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 291 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
10 to 7
W[3:0]
1010
R/W
Description
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the
first access cycle.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 292 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.4.4
Section 9 Bus State Controller (BSC)
SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
SDCR is initialized to H'00000000 by a power-on reset and retains the value by a manual reset and
in software standby mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
-
-
-
-
-
-
-
-
-
-
-
A2ROW[1:0]
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
Bit:
15
14
13
12
11
10
9
8
4
3
2
-
-
DEEP
SLOW
0
R
0
R
0
R/W
0
R/W
Initial value:
R/W:
7
6
5
RFSH RMODEPDOWN BACTV
-
-
-
0
R/W
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
31 to 21
⎯
All 0
R
Reserved
20
19
A3ROW[1:0]
0
R/W
0
R/W
18
17
16
A2COL[1:0]
-
0
R/W
0
R/W
1
0
A3COL[1:0]
0
R
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
20, 19
A2ROW[1:0] 00
R/W
Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
18
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 293 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
17, 16
A2COL[1:0]
00
R/W
Number of Bits of Column Address for Area 2
Specify the number of bits of column address for
area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
15, 14
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
13
DEEP
0
R/W
Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the deep
power-down entry command is issued and the lowpower SDRAM enters deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
12
SLOW
0
R/W
Low-Frequency Mode
Specifies the output timing of command, address, and
write data for SDRAM and the latch timing of read data
from SDRAM. Setting this bit makes the hold time for
command, address, write and read data extended for
half cycle (output or read at the falling edge of CK).
This mode is suitable for SDRAM with low-frequency
clock.
0: Command, address, and write data for SDRAM is
output at the rising edge of CK. Read data from
SDRAM is latched at the rising edge of CK.
1: Command, address, and write data for SDRAM is
output at the falling edge of CK. Read data from
SDRAM is latched at the falling edge of CK.
11
RFSH
0
R/W
Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
Page 294 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
RMODE
0
R/W
Refresh Control
Specifies whether to perform auto-refresh or selfrefresh when the RFSH bit is 1. When the RFSH bit is
1 and this bit is 1, self-refresh starts immediately.
When the RFSH bit is 1 and this bit is 0, auto-refresh
starts according to the contents that are set in registers
RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
9
PDOWN
0
R/W
Power-Down Mode
Specifies whether the SDRAM will enter power-down
mode after the access to the SDRAM. With this bit
being set to 1, after the SDRAM is accessed, the CKE
signal is driven low and the SDRAM enters powerdown mode.
0: The SDRAM does not enter power-down mode after
being accessed.
1: The SDRAM enters power-down mode after being
accessed.
8
BACTV
0
R/W
Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank
active mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT
commands)
Note: Bank active mode can be set only in area 3,
and only the 16-bit bus width can be set. When
both the CS2 and CS3 spaces are set to
SDRAM, specify auto-precharge mode.
7 to 5
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 295 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Initial
Value
Bit
Bit Name
4, 3
A3ROW[1:0] 00
R/W
Description
R/W
Number of Bits of Row Address for Area 3
Specify the number of bits of the row address for
area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
2
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
A3COL[1:0]
00
R/W
Number of Bits of Column Address for Area 3
Specify the number of bits of the column address for
area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
Page 296 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.4.5
Section 9 Bus State Controller (BSC)
Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM. RTCSR is initialized to H'00000000 by
a power-on reset and retains the value by a manual reset and in software standby mode.
When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection.
The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is
adjusted only by a power-on reset. Note that there is an error in the time until the compare match
flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value
other than B'000.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
CMF
CMIE
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Initial value:
R/W:
Bit
Bit Name
Initial
Value
R/W
Description
31 to 8
⎯
All 0
R
Reserved
CKS[2:0]
0
R/W
0
R/W
16
RRC[2:0]
0
R/W
0
R/W
0
R/W
0
R/W
These bits are always read as 0.
7
CMF
0
R/W
Compare Match Flag
Indicates that a compare match occurs between the
refresh timer counter (RTCNT) and refresh time
constant register (RTCOR). This bit is set or cleared in
the following conditions.
0: Clearing condition: When 0 is written in CMF after
reading out RTCSR during CMF = 1.
1: Setting condition: When the condition RTCNT =
RTCOR is satisfied.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 297 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
6
CMIE
0
R/W
Compare Match Interrupt Enable
Enables or disables CMF interrupt requests when the
CMF bit in RTCSR is set to 1.
0: Disables CMF interrupt requests.
1: Enables CMF interrupt requests.
5 to 3
CKS[2:0]
000
R/W
Clock Select
Select the clock input to count-up the refresh timer
counter (RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
2 to 0
RRC[2:0]
000
R/W
Refresh Count
Specify the number of continuous refresh cycles, when
the refresh request occurs after the coincidence of the
values of the refresh timer counter (RTCNT) and the
refresh time constant register (RTCOR). These bits
can make the period of occurrence of refresh long.
000: 1 time
001: 2 times
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
Page 298 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.4.6
Section 9 Bus State Controller (BSC)
Refresh Timer Counter (RTCNT)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value:
R/W:
RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR.
When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after
counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be
H'A55A to cancel write protection. This counter is initialized to H'00000000 by a power-on reset
and retains the value by a manual reset and in software standby mode.
Bit
Initial
Bit Name Value
R/W
Description
31 to 8
⎯
R
Reserved
All 0
These bits are always read as 0.
7 to 0
All 0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
R/W
8-Bit Counter
Page 299 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
9.4.7
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
The REFOUT signal can be asserted when a refresh request is generated while the bus is released.
For details, see the description of Relationship between Refresh Requests and Bus Cycles in
section 9.5.6 (9), Relationship between Refresh Requests and Bus Cycles, and section 9.5.11, Bus
Arbitration.
When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal.
The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit
only affects the interrupt request and does not clear the refresh request. Therefore, a combination
of refresh request and interval timer interrupt can be specified so that the number of refresh
requests are counted by using timer interrupts while refresh is performed periodically.
When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection. This register is initialized to H'00000000 by a power-on reset and retains the value by a
manual reset and in software standby mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value:
R/W:
Bit
Bit Name
Initial
Value
R/W Description
31 to 8
⎯
All 0
R
16
Reserved
These bits are always read as 0.
7 to 0
Page 300 of 1778
All 0
R/W 8-Bit Register
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.4.8
Section 9 Bus State Controller (BSC)
Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of DTC or DMAC bus release. It is used to
give priority to DTC or DMAC transfer or reduce the number of cycles in which the DTC is
active.
For the differences in DTC operation according to the combinations of the DTLOCK and DTBST
bit settings, refer to section 8.5.9, DTC Bus Release Timing.
Setting the DTSA bit enables DTC short address mode. For details of the short address mode, see
section 8.4, Location of Transfer Information and DTC Vector Table.
The DTPR bit selects the DTC activation priority used when multiple DTC activation requests are
generated before DTC activation.
Do not modify this register while the DMAC or DTC is active.
Bit:
15
DT
LOCK
Initial value: 0
R/W: R/W
14
13
12
-
-
-
0
R
0
R
0
R
11
10
DTBST DTSA
0
R/W
0
R/W
9
8
7
6
5
4
3
2
1
-
DTPR
-
-
-
-
-
-
-
-
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W Description
15
DTLOCK
0
R/W DTC Lock Enable
0
Specifies the timing of DTC bus release.
0: The DTC releases the bus when the NOP instruction
is issued after vector read, or after write-back of
transfer information is completed.
1: The DTC releases the bus after vector read, when
the NOP instruction is issued after vector read, after
transfer information read, after a single data transfer,
or after write-back of transfer information.
14 to 12
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 301 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W Description
11
DTBST
0
R/W DTC Burst Enable
Selects whether the DTC continues operation without
releasing the bus when multiple DTC activation
requests are generated.
0: The DTC releases the bus every time a DTC
activation request has been processed.
1: The DTC continues operation without releasing the
bus until all DTC activation requests have been
processed.
Notes: When this bit is set to 1, the following restrictions
apply.
1. Clock setting through the frequency control
register (FRQCR) must be Iφ : Bφ : Pφ : Mφ :
Aφ = 8 : 4 : 4 : 8 : 4 or 8 : 4 : 4 : 4 : 4.
2. The vector information must be stored in the
on-chip ROM or on-chip RAM.
3. The transfer information must be stored in
the on-chip RAM.
Page 302 of 1778
4.
Transfer must be between the on-chip RAM
and an on-chip peripheral module or
between the external memory and an onchip peripheral module.
5.
Do not set the DTBST bit to 1, when the
activation source is low-level setting for
IRQ7 to IRQ0 and the RRS bit is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W Description
10
DTSA
0
R/W DTC Short Address Mode
Selects the short address mode in which only three
longwords are required for DTC transfer information
read.
0: Four longwords are read as the transfer information.
The transfer information is arranged as shown in the
figure for normal mode in figure 8.2.
1: Three longwords are read as the transfer information.
The transfer information is arranged as shown in the
figure for short address mode in figure 8.2.
Note: The short address mode can be used only for
transfer between an on-chip peripheral module
and the on-chip RAM because the upper eight
bits of SAR and DAR are assumed as all 1s.
9
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8
DTPR
0
R/W DTC Activation Priority
Selects whether to start transfer from the first DTC
activation request or according to the DTC activation
priority when multiple DTC activation requests are
generated before the DTC is activated.
For details, see section 8.5.10, DTC Activation Priority
Order.
0: Starts transfer from the DTC activation request
generated first.
1: Starts transfer according to the DTC activation
priority.
Notes: When this bit is set to 1, the following restrictions
apply.
1. The vector information must be stored in the
on-chip ROM or on-chip RAM.
2. The transfer information must be stored in
the on-chip RAM.
3. The function for skipping the transfer
information read step is always disabled.
4. Set this bit to 1 while DTLOCK = 0. The
DTLOCK bit should not be set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 303 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W Description
7 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 304 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.5
Operation
9.5.1
Endian/Access Size and Data Alignment
Section 9 Bus State Controller (BSC)
This LSI supports big endian in which the 0 address is the most significant byte (MSB), and little
endian in which the 0 address is the least significant byte (LSB) in the byte data. In a space of
areas 1 to 7, endian can be set by the CSnBCR setting while the target space is not accessed. In a
space of area 0, the CSnBCR setting is invalid in on-chip ROM-disabled mode. In on-chip ROMenabled mode, endian can be set by the CSnBCR setting in a space of areas 0 to 7.
For normal memory and SRAM with byte selection, the data bus width can be selected from three
widths (8, 16, and 32 bits) in the SH7286 or two widths (8 and 16 bits) in the SH7285 and
SH7243. For SDRAM, the data bus width can be selected from two widths (16 and 32 bits) in the
SH7286 but only the 16-bit data bus width is available in the SH7285 and SH7243. For MPX-I/O,
the data bus width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access
address. Data alignment is performed in accordance with the data bus width of the device. This
also means that when longword data is read from a byte-width device, the read operation must be
done four times. In this LSI, data alignment and conversion of data length is performed
automatically between the respective interfaces.
Tables 9.5 to 9.10 show the relationship between device data width and access unit. Note that
addresses corresponding to the strobe signals for the 16-bit bus width differ between big endian
and little endian. WRH indicates the 0 address in big-endian mode, but WRL indicates the 0
address in little-endian mode.
Area 0 cannot be selected as little endian. Since the instruction fetch is mixed with the 32- and 16bit access and the allocation to the little endian area is difficult, the instruction must be executed
within the big endian aera.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 305 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.5
32-Bit External Device Access and Data Alignment in Big-Endian Mode (Only
in SH7286)
Data Bus
Strobe Signals
WRHH,
WRHL,
WRH,
D31 to D24
D23 to D16
D15 to D8
D7 to D0
DQMUU
DQMUL
DQMLU DQMLL
Byte access at 0
Data 7 to 0
⎯
⎯
⎯
Assert
⎯
⎯
⎯
Byte access at 1
⎯
Data 7 to 0
⎯
⎯
⎯
Assert
⎯
⎯
Byte access at 2
⎯
⎯
Data 7 to 0
⎯
⎯
⎯
Assert
⎯
Byte access at 3
⎯
⎯
⎯
Data 7 to 0
⎯
⎯
⎯
Assert
Word access at 0
Data 15 to 8
Data 7 to 0
⎯
⎯
Assert
Assert
⎯
⎯
Word access at 2
⎯
Data 15 to 8
Data 7 to 0
⎯
⎯
Assert
Assert
Longword access
Data 31 to 24 Data 23 to 16 Data 15 to 8
Data 7 to 0
Assert
Assert
Assert
Assert
Operation
WRL,
at 0
Table 9.6
16-Bit External Device Access and Data Alignment in Big-Endian Mode
Data Bus
Strobe Signals
D15 to D8
D7 to D0
WRH, DQMLU
WRL, DQMLL
Byte access at 0
Data 7 to 0
⎯
Assert
⎯
Byte access at 1
⎯
Data 7 to 0
⎯
Assert
Byte access at 2
Data 7 to 0
⎯
Assert
⎯
Byte access at 3
⎯
Data 7 to 0
⎯
Assert
Word access at 0
Data 15 to 8
Data 7 to 0
Assert
Assert
Word access at 2
Data 15 to 8
Data 7 to 0
Assert
Assert
1st time at 0
Data 23 to 16
Data 31 to 24
Assert
Assert
2nd time at 2
Data 7 to 0
Data 15 to 8
Assert
Assert
Operation
Longword
access at 0
Page 306 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 9.7
Section 9 Bus State Controller (BSC)
8-Bit External Device Access and Data Alignment in Big-Endian Mode
Data Bus
Strobe Signals
Operation
D15 to D8
D7 to D0
WRH, DQMLU
WRL, DQMLL
Byte access at 0
⎯
Data 7 to 0
⎯
Assert
Byte access at 1
⎯
Data 7 to 0
⎯
Assert
Byte access at 2
⎯
Data 7 to 0
⎯
Assert
Byte access at 3
⎯
Data 7 to 0
⎯
Assert
Word access at 0 1st time at 0
⎯
Data 15 to 8
⎯
Assert
⎯
Data 7 to 0
⎯
Assert
⎯
Data 15 to 8
⎯
Assert
2nd time at 3
⎯
Data 7 to 0
⎯
Assert
1st time at 0
⎯
Data 31 to 24
⎯
Assert
2nd time at 2
⎯
Data 23 to 16
⎯
Assert
3rd time at 2
⎯
Data 15 to 8
⎯
Assert
4th time at 3
⎯
Data 7 to 0
⎯
Assert
2nd time at 1
Word access at 2 1st time at 2
Longword
access at 0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 307 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.8
32-Bit External Device Access and Data Alignment in Little-Endian Mode (Only
in SH7286)
Data Bus
Strobe Signals
WRHH,
WRHL,
WRH,
Operation
D31 to D24
D23 to D16
D15 to D8
D7 to D0
DQMUU
DQMUL
DQMLU DQMLL
WRL,
Byte access at 0
⎯
⎯
⎯
Data 7 to 0
⎯
⎯
⎯
Assert
Byte access at 1
⎯
⎯
Data 7 to 0
⎯
⎯
⎯
Assert
⎯
Byte access at 2
⎯
Data 7 to 0
⎯
⎯
⎯
Assert
⎯
⎯
Byte access at 3
Data 7 to 0
⎯
⎯
⎯
Assert
⎯
⎯
⎯
Word access at 0
⎯
⎯
Data 15 to 8
Data 7 to 0
⎯
⎯
Assert
Assert
Word access at 2
Data 15 to 8
Data 7 to 0
⎯
⎯
Assert
Assert
⎯
⎯
Longword access at
Data 31 to 24 Data 23 to 16 Data 15 to 8
Data 7 to 0
Assert
Assert
Assert
Assert
0
Table 9.9
16-Bit External Device Access and Data Alignment in Little-Endian Mode
Data Bus
Strobe Signals
WRH, DQMLU
WRL, DQMLL
Data 7 to 0
⎯
Assert
⎯
Assert
⎯
⎯
Data 7 to 0
⎯
Assert
Byte access at 3
Data 7 to 0
⎯
Assert
⎯
Word access at 0
Data 15 to 8
Data 7 to 0
Assert
Assert
Word access at 2
Data 15 to 8
Data 7 to 0
Assert
Assert
1st time at 0
Data 15 to 8
Data 7 to 0
Assert
Assert
2nd time at 2
Data 31 to 24
Data 23 to 16
Assert
Assert
Operation
D15 to D8
D7 to D0
Byte access at 0
⎯
Byte access at 1
Data 7 to 0
Byte access at 2
Longword
access at 0
Page 308 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.10 8-Bit External Device Access and Data Alignment in Little-Endian Mode
Data Bus
Strobe Signals
Operation
D15 to D8
D7 to D0
WRH, DQMLU
WRL, DQMLL
Byte access at 0
⎯
Data 7 to 0
⎯
Assert
Byte access at 1
⎯
Data 7 to 0
⎯
Assert
Byte access at 2
⎯
Data 7 to 0
⎯
Assert
Byte access at 3
⎯
Data 7 to 0
⎯
Assert
Word access at 0 1st time at 0
⎯
Data 7 to 0
⎯
Assert
⎯
Data 15 to 8
⎯
Assert
⎯
Data 7 to 0
⎯
Assert
2nd time at 3
⎯
Data 15 to 8
⎯
Assert
1st time at 0
⎯
Data 7 to 0
⎯
Assert
2nd time at 2
⎯
Data 15 to 8
⎯
Assert
3rd time at 2
⎯
Data 23 to 16
⎯
Assert
4th time at 3
⎯
Data 31 to 24
⎯
Assert
2nd time at 1
Word access at 2 1st time at 2
Longword
access at 0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 309 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
9.5.2
(1)
Normal Space Interface
Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.8, SRAM Interface with Byte Selection. Figure 9.2 shows the basic timings of normal
space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle.
T1
T2
CK
A25 to A0
CSn
RD/WR
Read
RD
D15 to D0
RD/WR
Write
WRH, WRL
D15 to D0
BS
DACKn *
Note: * The waveform for DACKn is when active low is specified.
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)
Page 310 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 16 bits are always
read in case of a 16-bit device. When writing, only the WRxx signal for the byte to be written is
asserted.
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 9.3 and 9.4 show the basic timings of normal space access. If the WM bit in CSnWCR is
cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait
(figure 9.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is
inserted (figure 9.4).
T1
T2
Tnop
T1
T2
CK
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WRH, WRL
Write
D15 to D0
BS
DACKn *
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.3 Continuous Access for Normal Space 1
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0
(Access Wait = 0, Cycle Wait = 0)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 311 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
T1
T2
T1
T2
CK
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WRH, WRL
Write
D15 to D0
BS
DACKn *
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.4 Continuous Access for Normal Space 2
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1
(Access Wait = 0, Cycle Wait = 0)
Page 312 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
128K × 8-bit
SRAM
...
A2
CSn
RD
D31
A0
CS
OE
I/O7
I/O0
WE
...
D24
WRHH
D23
A16
...
...
A18
...
This LSI
...
D8
WRH
D7
D0
WRL
...
A16
A0
CS
OE
I/O7
...
...
D16
WRHL
D15
I/O0
WE
...
A16
...
A0
CS
OE
I/O7
I/O0
WE
...
A16
...
A0
CS
OE
I/O7
I/O0
WE
Figure 9.5 Example of 32-Bit Data-Width SRAM Connection (Only SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 313 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
128K × 8-bit
SRAM
••••
A0
CS
OE
I/O7
••••
I/O0
WE
••••
••••
••••
D0
WRL
A16
••••
••••
D8
WRH
D7
A0
CS
OE
I/O7
••••
••••
A1
CSn
RD
D15
A16
••••
••••
••••
A17
••••
This LSI
I/O0
WE
Figure 9.6 Example of 16-Bit Data-Width SRAM Connection
128K × 8-bit
SRAM
This LSI
A0
CS
RD
OE
D7
I/O7
...
A0
CSn
...
...
A16
...
A16
D0
I/O0
WRL
WE
Figure 9.7 Example of 8-Bit Data-Width SRAM Connection
Page 314 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.5.3
Section 9 Bus State Controller (BSC)
Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 1, 4, 5, and 7 to insert wait cycles independently in read
access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write
cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access
shown in figure 9.8.
T1
Tw
T2
CK
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WRH, WRL
Write
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 315 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CK at the transition from the T1 or Tw
cycle to the T2 cycle.
T1
Tw
Tw
Wait states inserted
by WAIT signal
Twx
T2
CK
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WRH, WRL
Write
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.9 Wait Cycle Timing for Normal Space Access
(Wait Cycle Insertion Using WAIT Signal)
Page 316 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.5.4
Section 9 Bus State Controller (BSC)
CSn Assert Period Expansion
The number of cycles from CSn assertion to RD, WRxx assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WRxx negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WRxx are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
Th
T1
T2
Tf
CK
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WRH, WRL
Write
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.10 CSn Assert Period Expansion
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 317 of 1778
Section 9 Bus State Controller (BSC)
9.5.5
SH7280 Group, SH7243 Group
MPX-I/O Interface
Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WRxx
signals control the accessing. The basic access for the MPX space consists of 2 cycles of address
output followed by an access to a normal space. The bus width for the address output cycle or the
data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits
depending on the address to be accessed.
Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3.
Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided
without inserting idle cycles, even in continuous access cycles. Address output is increased to 3
cycles by setting the MPXW bit in CS5WCR to 1.
The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and
low in the write cycle.
The data cycle is the same as that in a normal space access.
Timing charts are shown in figures 9.11 to 9.13.
Page 318 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Ta1
Ta2
Ta3
T1
T2
CK
A25 to A0
CS5
RD/WR
AH
RD
Read
D15/D7 to D0
Address
Data
WRH, WRL
Write
D15/D7 to D0
Address
Data
BS
DACKn*
Note * The waveform for DACKn is when active low is specified.
Figure 9.11 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 319 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Ta1
Tadw
Ta2
Ta3
T1
T2
CK
A25 to A0
CS5
RD/WR
AH
RD
Read
D15/D7 to D0
Address
Data
WRH, WRL
Write
D15/D7 to D0
Address
Data
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)
Page 320 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Ta1
Section 9 Bus State Controller (BSC)
Tadw
Ta2
Ta3
T1
Tw
Twx
T2
CK
A25 to A0
CS5
RD/WR
AH
RD
Read
D15/D7 to D0
Address
Data
WRH, WRL
Write
Address
D15/D7 to D0
Data
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.13 Access Timing for MPX Space
(Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 321 of 1778
Section 9 Bus State Controller (BSC)
9.5.6
(1)
SH7280 Group, SH7243 Group
SDRAM Interface
SDRAM Direct Connection
The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,
8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in
read and write command cycles.
The control signals for direct connection of SDRAM are RASU, RASL, CASL, CASU, RD/WR,
DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and
CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted.
SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to
SDRAM can be set to 32 bits or 16 bits in the SH7286 or 16 bits only in the SH7285 and SH7243.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
SDRAM operating mode.
Commands for SDRAM can be specified by RASL, CASL, RD/WR, and specific address signals.
These commands supports:
•
•
•
•
•
•
•
•
•
•
•
NOP
Auto-refresh (REF)
Self-refresh (SELF)
All banks pre-charge (PALL)
Specified bank pre-charge (PRE)
Bank active (ACTV)
Read (READ)
Read with pre-charge (READA)
Write (WRIT)
Write with pre-charge (WRITA)
Write mode register (MRS, EMRS)
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or
writing is performed for a byte whose corresponding DQMxx is low. For details on the
relationship between DQMxx and the byte to be accessed, see section 9.5.1, Endian/Access Size
and Data Alignment.
Figures 9.14 to 9.16 show examples of the connection of the SDRAM with the LSI.
Page 322 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
As shown in figure 9.16, two sets of SDRAMs of 32Mbytes or smaller can be connected to the
same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are
assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by
RASU and CASU. When accessing the address with A25 = 0, RASL and CASL are asserted.
When accessing the address with A25 = 1, RASU and CASU are asserted.
64M SDRAM
(1M × 16-bit × 4-bank)
This LSI
A13
...
D16
DQMUU
DQMUL
D15
D0
DQMLU
DQMLL
A0
CKE
CLK
CS
Unused
Unused
...
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
A13
...
...
A2
CKE
CK
CSn
RASU
CASU
RASL
CASL
RD/WR
D31
...
...
A15
A0
CKE
CLK
CS
...
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 9.14 Example of 32-Bit Data Width SDRAM Connection
(RASU and CASU are Not Used)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 323 of 1778
Section 9 Bus State Controller (BSC)
SH7280 Group, SH7243 Group
64M SDRAM
(1M × 16-bit × 4-bank)
...
A1
CKE
CK
CSn
RASU
CASU
RASL
CASL
RD/WR
D15
D0
DQMLU
DQMLL
A13
...
...
A14
A0
CKE
CLK
CS
RAS
CAS
WE
I/O15
...
This LSI
I/O0
DQMU
DQML
...
A13
A0
CKE
CLK
CS
...
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 9.15 Example of 16-Bit Data Width SDRAM Connection
(RASU and CASU are Used)
Page 324 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
64M SDRAM
(1M × 16-bit × 4-bank)
A1
CKE
CK
CSn
...
RASL
CASL
RD/WR
D15
D0
DQMLU
DQMLL
A13
...
...
A14
A0
CKE
CLK
CS
RAS
CAS
WE
I/O15
...
This LSI
I/O0
DQMU
DQML
Figure 9.16 Example of 16-Bit Data Width SDRAM Connection
(2)
Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0],
and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 9.11 to 9.16 show the
relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and
A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other
than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not
multiplexed and the original values of address are always output at these pins.
The A0 pin of SDRAM specifies a word address. Therefore, connect the A0 pin of SDRAM to the
A1 pin of the LSI; then connect the A1 pin of SDRAM to the A2 pin of the LSI, and so on.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 325 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (1)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 Bits)
00 (11 Bits)
00 (8 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A25
A17
A16
A24
A16
A15
A23
SDRAM Pin
Function
Unused
A15
A22*
2
A22*2
A12 (BA1)
A13
A21*
2
2
A11 (BA0)
A12
A20
L/H*1
A10/AP
Specifies
address/precharge
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
A0
A8
A0
A14
A21*
Specifies bank
Unused
Examples of connected memory
64-Mbit product (512 Kwords × 32 bits × 4 banks, column 8 bits product): 1
16-Mbit product (512 Kwords × 16 bits × 2 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Page 326 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (1)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 Bits)
01 (12 Bits)
00 (8 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A24
A17
A16
A23
SDRAM Pin
Function
Unused
A16
A23*
2
A23*2
A13 (BA1)
A14
A22*
2
2
A12 (BA0)
A13
A21
A13
A11
Address
A12
A20
L/H*1
A10/AP
Specifies
address/precharge
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
A0
A8
A0
A15
A22*
Specifies bank
Unused
Examples of connected memory
128-Mbit product (1 Mword × 32 bits × 4 banks, column 8 bits product): 1
64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 327 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 Bits)
01 (12 Bits)
01 (9 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A26
A17
A16
A25
SDRAM Pin
Function
Unused
A16
A24*
2
A24*2
A13 (BA1)
A14
A23*
2
2
A12 (BA0)
A13
A22
A13
A11
Address
A12
A21
L/H*1
A10/AP
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
A0
A9
A0
A15
A23*
Specifies bank
Unused
Examples of connected memory
256-Mbit product (2 Mwords × 32 bits × 4 banks, column 9 bits product): 1
128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Page 328 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 Bits)
01 (12 Bits)
10 (10 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A27
A17
A16
A26
A16
A15
A25*2*3
A25*2*3
2
A24*
SDRAM Pin
Function
Unused
2
A13 (BA1)
Specifies bank
A14
A24*
A12 (BA0)
A13
A23
A13
A11
Address
A12
A22
L/H*1
A10/AP
Specifies
address/precharge
A11
A21
A11
A9
Address
A10
A20
A10
A8
A9
A19
A9
A7
A8
A18
A8
A6
A7
A17
A7
A5
A6
A16
A6
A4
A5
A15
A5
A3
A4
A14
A4
A2
A3
A13
A3
A1
A2
A12
A2
A0
A1
A11
A1
A0
A10
A0
Unused
Examples of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 329 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (3)
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 Bits)
10 (13 Bits)
01 (9 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A26
A17
2
3
SDRAM Pin
Function
Unused
2
3
Specifies bank
A16
A25* *
A25* *
A14 (BA1)
A15
A24*2
A24*2
A13 (BA0)
A14
A23
A14
A12
A13
A22
A13
A11
A12
A21
L/H*1
A10/AP
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
A0
A9
A0
Address
Unused
Examples of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 9 bits product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
Page 330 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.14 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (4)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 Bits)
00 (11 Bits)
00 (8 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A25
A17
A16
A24
A16
A15
A23
A15
A14
A22
SDRAM Pin
Function
Unused
A14
A13
A21*
2
A21*2
A12 (BA1)
A12
A20*2
A20*2
A11 (BA0)
A11
A19
L/H*
A10/AP
Specifies
address/precharge
A10
A18
A10
A9
Address
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
1
Specifies bank
Unused
Example of connected memory
16-Mbit product (512 Kwords × 16 bits × 2 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 331 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.14 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (4)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 Bits)
01 (12 Bits)
00 (8 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A25
A17
A16
A24
A16
A15
A23
SDRAM Pin
Unused
A15
A22*
2
A22*2
A13 (BA1)
A13
A21*
2
2
A12 (BA0)
A12
A20
A14
Function
A21*
A12
1
Specifies bank
A11
Address
A11
A19
L/H*
A10/AP
Specifies
address/precharge
A10
A18
A10
A9
Address
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
Unused
Example of connected memory
64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to
access the mode.
2. Bank address specification
Page 332 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.15 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (5)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 Bits)
01 (12 Bits)
01 (9 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A26
A17
A16
A25
A16
A15
A24
SDRAM Pin
Unused
A15
A23*
2
A23*2
A13 (BA1)
A13
A22*
2
2
A12 (BA0)
A12
A21
A14
Function
A22*
A12
1
Specifies bank
A11
Address
A11
A20
L/H*
A10/AP
Specifies
address/precharge
A10
A19
A10
A9
Address
A9
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
Unused
Example of connected memory
128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 333 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.15 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (5)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
01 (12 bits)
10 (10 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A27
A17
A16
A26
A16
A15
A25
SDRAM Pin
Unused
A15
A24*
2
A24*2
A13 (BA1)
A13
A23*
2
2
A12 (BA0)
A12
A22
A14
Function
A23*
A12
1
Specifies bank
A11
Address
A11
A21
L/H*
A10/AP
Specifies
address/precharge
A10
A20
A10
A9
Address
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
A0
A10
A0
Unused
Example of connected memory
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Page 334 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.16 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (6)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
10 (13 bits)
01 (9 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A26
A17
A16
A25
SDRAM Pin
Function
Unused
A16
A24*
2
A24*2
A14 (BA1)
A14
A23*
2
2
A13 (BA0)
A13
A22
A13
A12
A12
A21
A12
A11
A11
A20
L/H*
A10/AP
Specifies
address/precharge
A10
A19
A10
A9
Address
A9
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
A15
A23*
1
Specifies bank
Address
Unused
Example of connected memory
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 335 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.16 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (6)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
10 (13 bits)
10 (10 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
A17
A27
A17
A16
A26
A15
SDRAM Pin
Function
Unused
A16
2
3
A25* *
2
A25*2*3
A24*
2
A14 (BA1)
Specifies bank
A14
A24*
A13
A23
A13
A12
A12
A22
A12
A11
A11
A21
L/H*
A10/AP
Specifies
address/precharge
A10
A20
A10
A9
Address
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
A0
A10
A0
1
A13 (BA0)
Address
Unused
Example of connected memory
512-Mbit product (8 Mwords × 16 bits × 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
3. Only the RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.
Page 336 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 9 Bus State Controller (BSC)
Burst Read
A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width.
• 16-byte transfer in DMAC
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that
is connected to a 16-bit data bus. This access is called the burst read with the burst number 8.
Table 9.17 shows the relationship between the access size and the number of bursts.
Table 9.17 Relationship between Access Size and Number of Bursts
Bus Width
Access Size
Number of Bursts
16 bits
8 bits
1
16 bits
1
32 bits
2
16 bytes
8
Figures 9.17 and 9.18 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CK) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an autoprecharge induced by the READA command in the SDRAM. In the Tap cycle, a new command
will not be issued to the same bank. However, access to another CS space or another bank in the
same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and
WTRP0 bits in CS3WCR.
In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM
in variable frequencies. Figure 9.18 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in
CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the
NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles
from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is
latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0
bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and WTRCD0 bit in CS3WCR. The
number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for
the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 337 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit
between this LSI and the SDRAM.
A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for
every burst read or every single read.
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
(Tap)
CK
A25 to A0
A12/A11*1
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.17 Burst Read Basic Timing (CAS Latency 1, Auto-Precharge)
Page 338 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Tr
Section 9 Bus State Controller (BSC)
Trw
Tc1
Tw
Tc2
Td1
Tc3
Td2
Tc4
Td3
Td4
Tde
(Tap)
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.18 Burst Read Wait Specification Timing (CAS Latency 2,
WTRCD[1:0] = 1 Cycle, Auto-Precharge)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 339 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
(4)
Single Read
A read access ends in one cycle when the data bus width is larger than or equal to the access size.
This, simply stated, is single read. As the SDRAM is set to the burst read with the burst length 1,
only the required data is output. A read access that ends in one cycle is called single read.
Figure 9.19 shows the single read basic timing.
Tr
Tc1
Td1
Tde
(Tap)
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.19 Basic Timing for Single Read (CAS Latency 1, Auto-Precharge)
Page 340 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(5)
Section 9 Bus State Controller (BSC)
Burst Write
A burst write occurs in the following cases in this LSI.
• Access size in writing is larger than data bus width.
• 16-byte transfer in DMAC
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 8 times to write 16-byte continuous data to the SDRAM that is
connected to a 16-bit data bus. This access is called burst write with the burst number 8.
The relationship between the access size and the number of bursts is shown in table 9.17.
Figure 9.20 shows a timing chart for burst writes. In burst write, an ACTV command is output in
the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA
command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data
is output simultaneously with the write command. After the write command with the autoprecharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the
Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the
SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same
bank. However, access to another CS space or another bank in the same SDRAM space is enabled.
The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The
number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 341 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tr
Tc1
Tc2
Tc3
Tc4
Trwl
Tap
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.20 Basic Timing for Burst Write (Auto-Precharge)
Page 342 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(6)
Section 9 Bus State Controller (BSC)
Single Write
A write access ends in one cycle when the data bus width is larger than or equal to access size. As
a single write or burst write with burst length 1 is set in SDRAM, only the required data is output.
The write access that ends in one cycle is called single write. Figure 9.21 shows the single write
basic timing.
Tr
Tc1
Trwl
Tap
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.21 Single Write Basic Timing (Auto-Precharge)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 343 of 1778
Section 9 Bus State Controller (BSC)
(7)
SH7280 Group, SH7243 Group
Bank Active
The SDRAM bank function can be used to support high-speed access to the same row address.
When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge
(READ or WRIT). This function is called bank-active function. This function is valid only for
either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2 should be
set to normal space or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM or
both the upper and lower bits of area 3 are connected to SDRAM, auto-precharge mode must be
set.
When the bank-active function is used, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. As SDRAM is internally divided
into several banks, it is possible to activate one row address in each bank. If the next access is to a
different row address, a PRE command is first issued to precharge the relevant bank, then when
precharging is completed, the access is performed by issuing an ACTV command followed by a
READ or WRIT command. If this is followed by an access to a different row address, the access
time will be longer because of the precharging performed after the access request is issued. The
number of cycles between issuance of the PRE command and the ACTV command is determined
by the WTRP1 and WTPR0 bits in CS3WCR.
In a write, when an auto-precharge is performed, a command cannot be issued to the same bank
for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode
is used, READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tap cycles for each write.
There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of tRAS.
A burst read cycle without auto-precharge is shown in figure 9.22, a burst read cycle for the same
row address in figure 9.23, and a burst read cycle for different row addresses in figure 9.24.
Similarly, a burst write cycle without auto-precharge is shown in figure 9.25, a burst write cycle
for the same row address in figure 9.26, and a burst write cycle for different row addresses in
figure 9.27.
In figure 9.23, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that
issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for
the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS
Page 344 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
When bank active mode is set, if only access cycles to the respective banks in the area 3 space are
considered, as long as access cycles to the same row address continue, the operation starts with the
cycle in figure 9.22 or 9.25, followed by repetition of the cycle in figure 9.23 or 9.26. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 9.23 or 9.26 is executed instead of
that in figure 9.24 or 9.27. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.22 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 345 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tnop
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.23 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank,
CAS Latency 1)
Page 346 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Tp
Section 9 Bus State Controller (BSC)
Tpw
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.24 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank,
CAS Latency 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 347 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tr
Tc1
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.25 Single Write Timing (Bank Active, Different Bank)
Page 348 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tnop
Tc1
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.26 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 349 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tp
Tpw
Tr
Tc1
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.27 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank)
Page 350 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(8)
Section 9 Bus State Controller (BSC)
Refreshing
This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by
clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can
be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long
period, self-refresh mode, in which the power consumption for data retention is low, can be
activated by setting both the RMODE bit and the RFSH bit to 1.
(a)
Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0
in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should
be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings
for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0
and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts
counting up from the value at that time. The RTCNT value is constantly compared with the
RTCOR value, and if the two values are the same, a refresh request is generated and an autorefresh is performed for the number of times specified by the RRC2 to RRC0. At the same time,
RTCNT is cleared to zero and the count-up is restarted.
Figure 9.28 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL
command is issued in the Tp cycle to make all the banks to pre-charged state from active state
when some bank is being pre-charged. Then REF command is issued in the Trr cycle after
inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A
new command is not issued for the duration of the number of cycles specified by the WTRC1 and
WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to
satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the
Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is
longer than or equal to 1 cycle.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 351 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tp
Tpw
Trr
Trc
Trc
Trc
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
Hi-z
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.28 Auto-Refresh Timing
Page 352 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 9 Bus State Controller (BSC)
Self-refreshing
Self-refresh mode is a standby mode in which the refresh timing and refresh addresses are
generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the
RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle
after the completion of the pre-charging bank. A SELF command is then issued after inserting idle
cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM
cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the
RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the
number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR.
Self-refresh timing is shown in figure 9.29. Settings must be made so that self-refresh clearing and
data retention are performed correctly, and auto-refreshing is performed at the correct intervals.
When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting
standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is
set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition
from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be
taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less
than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using the LSI standby function, and is maintained even after recovery from standby mode
due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby
state by setting the HIZCNT bit in CMNCR to 1.
The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state
controller's registers are initialized, and therefore the self-refresh state is cleared.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 353 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tp
Tpw
Trr
Trc
Trc
Trc
CK
CKE
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
Hi-z
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.29 Self-Refresh Timing
Page 354 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(9)
Section 9 Bus State Controller (BSC)
Relationship between Refresh Requests and Bus Cycles
If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle
to be completed. If a refresh request occurs while the bus is released by the bus arbitration
function, the refresh will not be executed until the bus mastership is acquired. This LSI has the
REFOUT pin to request the bus while waiting for refresh execution. For REFOUT pin function
selection, see section 23, Pin Function Controller (PFC). This LSI continues to assert REFOUT
(low level) until the bus is acquired.
On receiving the asserted REFOUT signal, the external device must negate the BREQ signal and
return the bus. If the external bus does not return the bus for a period longer than the specified
refresh interval, refresh cannot be executed and the SDRAM contents may be lost.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring.
If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is
completed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 355 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
(10) Low-Frequency Mode
When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and
fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency.
Figure 9.30 shows the access timing in low-frequency mode. In this mode, commands, addresses,
and write data are output in synchronization with the falling edge of CK, which is half a cycle
delayed than the normal timing. Read data is fetched at the rising edge of CK, which is half a
cycle faster than the normal timing. This timing allows the hold time of commands, addresses,
write data, and read data to be extended.
If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of
commands, addresses, write data, and read data are not guaranteed. Take the operating frequency
and timing design into consideration when making the SLOW bit setting.
Tr
Tc1
Td1
Tde
Tap
Tr
Tc1
Tnop
Trwl
Tap
CK
(High)
CKE
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.30 Low-Frequency Mode Access Timing
Page 356 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
(11) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing
the CKE signal to the low level in the non-access cycle. This power-down mode can effectively
lower the power consumption in the non-access cycle. However, please note that if an access
occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the
CKE in order to cancel power-down mode.
Figure 9.31 shows the access timing in power-down mode.
Power-down
Tnop
Tr
Tc1
Td1
Tde
Tap
Power-down
CK
CKE
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.31 Power-Down Mode Access Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 357 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
(12) Power-On Sequence
In order to use SDRAM, mode setting must first be made for SDRAM after waiting for 100 μs or
a longer period after powering on. This 100-μs or longer period should be obtained by a power-on
reset generating circuit or software.
To perform SDRAM initialization correctly, the bus state controller registers must first be set,
followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address
signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL,
and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be
written to the SDRAM mode register by performing a write to address H'FFFC4000 + X for area 2
SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is
ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS
latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is
written in a byte-size access to the addresses shown in table 9.18. In this time 0 is output at the
external address pins of A12 or later.
Table 9.18 Access Address in SDRAM Mode Register Write
• Setting for Area 2
Burst read/single write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'FFFC4440
H'0000440
3
H'FFFC4460
H'0000460
Burst read/burst write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'FFFC4040
H'0000040
3
H'FFFC4060
H'0000060
Page 358 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
• Setting for Area 3
Burst read/single write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'FFFC5440
H'0000440
3
H'FFFC5460
H'0000460
Burst read/burst write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'FFFC5040
H'0000040
3
H'FFFC5060
H'0000060
Mode register setting timing is shown in figure 9.32. A PALL command (all bank pre-charge
command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the
first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,
are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which
number is one or more, are inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse
width of the reset signal is longer than the idle time, mode register setting can be started
immediately after the reset, but care should be taken when the pulse width of the reset signal is
shorter than the idle time.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 359 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tp
PALL
Tpw
Trr
REF
Trc
Trc
Trr
REF
Trc
Trc
Tmw
MRS
Tnop
CK
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
Hi-Z
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.32 SDRAM Mode Write Timing (Based on JEDEC)
Page 360 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
(13) Low-Power SDRAM
The low-power SDRAM can be accessed using the same protocol as the normal SDRAM.
The differences between the low-power SDRAM and normal SDRAM are that partial refresh
takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh
function, and that power consumption is low during refresh under user conditions such as the
operating temperature. The partial refresh is effective in systems in which there is data in a work
area other than the specific area can be lost without severe repercussions.
The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode
registers as the normal SDRAM. This LSI supports issuing of the EMRS command.
The EMRS command is issued according to the conditions specified in table below. For example,
if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued
to the CS3 space in the following sequence: PALL -> REF × 8 -> MRS -> EMRS. In this case, the
MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data
H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the
CS3 space in the following sequence: PALL -> MRS -> EMRS.
However, since addresses written to this LSI are output without change, set data in accord with the
EMRS specifications for the given SDRAM area.
Table 9.19 Output Addresses when EMRS Command Is Issued
Access Data
Write
Access
Size
MRS
EMRS
Command
Command
Issue Address Issue Address
H'FFFC4XX0
H'********
16 bits
H'0000XX0
⎯
CS3 MRS
H'FFFC5XX0
H'********
16 bits
H'0000XX0
⎯
CS2 MRS + EMRS
H'FFFC4XX0
H'0YYYYYYY 32 bits
H'0000XX0
H'YYYYYYY
H'FFFC5XX0
H'0YYYYYYY 32 bits
H'0000XX0
H'YYYYYYY
H'FFFC4XX0
H'1YYYYYYY 32 bits
H'0000XX0
H'YYYYYYY
H'FFFC5XX0
H'1YYYYYYY 32 bits
H'0000XX0
H'YYYYYYY
Command to be
Issued
Access
Address
CS2 MRS
(with refresh)
CS3 MRS + EMRS
(with refresh)
CS2 MRS + EMRS
(without refresh)
CS3 MRS + EMRS
(without refresh)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 361 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Tp
Tpw
PALL
Trr
REF
Trc
Trc
Trr
REF
Trc
Trc
Tmw Tnop Temw Tnop
MRS
EMRS
CK
A25 to A0
BA1*1
BA0*2
A12/A11*3
CSn
RASL
CASL
RD/WR
DQMxx
D15 to D0
Hi-Z
BS
DACKn*4
Notes: 1. Address pin to be connected to pin BA1 of SDRAM.
2. Address pin to be connected to pin BA0 of SDRAM.
3. Address pin to be connected to pin A10 of SDRAM.
4. The waveform for DACKn is when active low is specified.
Figure 9.33 EMRS Command Issue Timing
Page 362 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
• Deep power-down mode
The low-power SDRAM supports deep power-down mode as a low-power consumption mode.
In the partial self-refresh function, self-refresh is performed on a specific area. In deep powerdown mode, self-refresh will not be performed on any memory area. This mode is effective in
systems where all of the system memory areas are used as work areas.
If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to
1, the low-power SDRAM enters deep power-down mode. If the RMODE bit is cleared to 0, the
CKE signal is pulled high to cancel deep power-down mode. Before executing an access after
returning from deep power-down mode, the power-up sequence must be re-executed.
Tp
Tpw
Tdpd
Trc
Trc
Trc
Trc
Trc
CK
CKE
A25 to A0
A12/A11*1
CSn
RASL
CASL
RD/WR
DQMxx
Hi-Z
D15 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.34 Deep Power-Down Mode Transition Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 363 of 1778
Section 9 Bus State Controller (BSC)
9.5.7
SH7280 Group, SH7243 Group
Burst ROM (Clock Asynchronous) Interface
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read
function using a method of address switching called burst mode or page mode. In a burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent access cycles are performed only by changing the address, without
negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles,
addresses are changed at the falling edge of the CK.
For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is
inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the W1
to W0 bits in CSnWCR is inserted.
In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle.
In the single access or write access that does not perform the burst operation in the burst ROM
(clock asynchronous) interface, access timing is same as a normal space.
Table 9.20 lists a relationship between bus width, access size, and the number of bursts. Figure
9.35 shows a timing chart.
Page 364 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.20 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width
Access Size
CSnWCR. BST[1:0] Bits Number of Bursts Access Count
8 bits
8 bits
Not affected
1
1
16 bits
Not affected
2
1
Not affected
4
1
x0
16
1
10
4
4
8 bits
Not affected
1
1
16 bits
Not affected
1
1
Not affected
2
1
00
8
1
01
2
4
4
2
2, 4, 2
3
32 bits
16 bytes*
16 bits
2
32 bits
16 bytes*
2
10*
1
Notes: 1. When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
2. Only the DMAC is capable of transfer with 16 bytes as the unit of access.
The maximum unit of access for the DTC and CPU is 32 bits.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 365 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
T1
Tw
Tw
TB2
Twb
TB2
Twb
TB2
Twb
T2
CK
A25 to A0
CSn
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.35 Burst ROM Access Timing (Clock Asynchronous)
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
Page 366 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.5.8
Section 9 Bus State Controller (BSC)
SRAM Interface with Byte Selection
The SRAM interface with byte selection is for access to an SRAM which has a byte-selection pin
(WRxx). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte
selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM
interface with byte selection is the same as that for the normal space interface. While in read
access of a byte-selection SRAM interface, the byte-selection signal is output from the WRxx pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 9.36. In write access, data is written to the memory according to the timing of the byteselection pin (WRxx). For details, please refer to the Data Sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WRxx pin and RD/WR pin timings change. Figure 9.37
shows the basic access timing. In write access, data is written to the memory according to the
timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write
must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 9.38 shows the access
timing when a software wait is specified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 367 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
T2
T1
CK
A25 to A0
CSn
WRH, WRL
RD/WR
Read
RD
D15 to D0
RD/WR
Write
RD
High
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.36 Basic Access Timing for SRAM with Byte Selection (BAS = 0)
Page 368 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
T1
T2
CK
A25 to A0
CSn
WRH, WRL
RD/WR
Read
RD
D15 to D0
RD/WR
High
Write
RD
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.37 Basic Access Timing for SRAM with Byte Selection (BAS = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 369 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Th
T1
Tw
T2
Tf
CK
A25 to A0
CSn
WRH, WRL
RD/WR
RD
Read
D15 to D0
RD/WR
High
RD
Write
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.38 Wait Timing for SRAM with Byte Selection (BAS = 1)
(SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
Page 370 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
64K × 16-bit
SRAM
This LSI
A16
..
.
A1
A15
..
.
A0
CSn
CS
RD
OE
RD/WR
D15
.
..
D0
WRH
WRL
WE
I/O 15
..
.
I/O 0
UB
LB
Figure 9.39 Example of Connection with 16-Bit Data-Width SRAM with Byte Selection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 371 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
9.5.9
Burst ROM (Clock Synchronous) Interface
The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous
burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as
a normal space. This interface is valid only for area 0.
In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be
inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the
number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR.
While the burst ROM (clock synchronous) is accessed, the BS signal is asserted only for the first
access cycle and an external wait input is also valid for the first access cycle.
If the bus width is 16 bits, the burst length must be specified as 8. The burst ROM interface does
not support the 8-bit bus width for the burst ROM.
The burst ROM interface performs burst operations for all read access. For example, in a
longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is
read six times. These invalid data read cycles increase the memory access time and degrade the
program execution speed and DMA transfer speed. To prevent this problem, using 16-byte read by
the DMA is recommended. The burst ROM interface performs write access in the same way as
normal space access.
T1
Tw
Tw
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2
CK
A25 to A0
CS0
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.40 Burst ROM Access Timing (Clock Synchronous)
(Burst Length = 8, Wait Cycles Inserted in First Access = 2,
Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
Page 372 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
9.5.10
Section 9 Bus State Controller (BSC)
Wait between Access Cycles
As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often
collides with the next data access when the read operation from devices with slow access speed is
completed. As a result of these collisions, the reliability of the device is low and malfunctions may
occur. A function that avoids data collisions by inserting idle (wait) cycles between continuous
access cycles has been newly added.
The number of wait cycles between access cycles can be set by the WM bit in CSnWCR, bits
IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and
IWRRS2 to IWRRS 0 in CSnBCR, and bits DMAIW2 to DMAIW0 and DMAIWA in CMNCR.
The conditions for setting the idle cycles between access cycles are shown below.
1.
2.
3.
4.
5.
6.
Continuous access cycles are write-read or write-write
Continuous access cycles are read-write for different spaces
Continuous access cycles are read-write for the same space
Continuous access cycles are read-read for different spaces
Continuous access cycles are read-read for the same space
Data output from an external device caused by DMA single address transfer is followed by
data output from another device that includes this LSI (DMAIWA = 0)
7. Data output from an external device caused by DMA single address transfer is followed by any
type of access (DMAIWA = 1)
For the specification of the number of idle cycles between access cycles described above, refer to
the description of each register.
Besides the idle cycles between access cycles specified by the registers, idle cycles must be
inserted to interface with the internal bus or to obtain the minimum pulse width for a multiplexed
pin (WRxx). The following gives detailed information about the idle cycles and describes how to
estimate the number of idle cycles.
The number of idle cycles on the external bus from CSn negation to CSn or CSm assertion is
described below.
There are eight conditions that determine the number of idle cycles on the external bus as shown
in table 9.21. The effects of these conditions are shown in figure 9.41.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 373 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.21 Conditions for Determining Number of Idle Cycles
No. Condition
Description
(1)
DMAIW[2:0] in
CMNCR
These bits specify the number of
0 to 12
idle cycles for DMA single address
transfer. This condition is effective
only for single address transfer and
generates idle cycles after the
access is completed.
When 0 is specified for the
number of idle cycles, the
DACK signal may be asserted
continuously. This causes a
discrepancy between the
number of cycles detected by
the device with DACK and the
DMAC transfer count,
resulting in a malfunction.
(2)
IW***[2:0] in
CSnBCR
These bits specify the number of
0 to 12
idle cycles for access other than
single address transfer. The
number of idle cycles can be
specified independently for each
combination of the previous and
next cycles. For example, in the
case where reading CS1 space
followed by reading other CS
space, the bits IWRRD[2:0] in
CS1BCR should be set to B'100 to
specify six or more idle cycles. This
condition is effective only for access
cycles other than single address
transfer and generates idle cycles
after the access is completed.
Do not set 0 for the number of
idle cycles between memory
types which are not allowed
to be accessed successively.
(3)
SDRAM-related These bits specify precharge
0 to 3
bits in
completion and startup wait cycles
CSnWCR
and idle cycles between commands
for SDRAM access. This condition
is effective only for SDRAM access
and generates idle cycles after the
access is completed
(4)
WM in
CSnWCR
Page 374 of 1778
Range
Note
Specify these bits in
accordance with the
specification of the target
SDRAM.
This bit enables or disables external 0 or 1
WAIT pin input for the memory
types other than SDRAM. When
this bit is cleared to 0 (external
WAIT enabled), one idle cycle is
inserted to check the external WAIT
pin input after the access is
completed. When this bit is set to 1
(disabled), no idle cycle is
generated.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
No. Condition
Description
Range
(5)
Read data
transfer cycle
One idle cycle is inserted after a
0 or 1
read access is completed. This idle
cycle is not generated for the first or
middle cycles in divided access
cycles. This is neither generated
when the WM[1:0] bits in CSnWCR
are not B'00.
(6)
Internal bus
External bus access requests from 0 or
idle cycles, etc. the CPU or DMAC and their results larger
are passed through the internal
bus. The external bus enters idle
state during internal bus idle cycles
or while a bus other than the
external bus is being accessed.
This condition is not effective for
divided access cycles, which are
generated by the BSC when the
access size is larger than the
external data bus width.
The number of internal bus
idle cycles may not become 0
depending on the Iφ:Bφ clock
ratio. Tables 9.22 and 9.23
show the relationship
between the clock ratio and
the minimum number of
internal bus idle cycles.
(7)
Write data wait During write access, a write cycle is 0 or 1
cycles
executed on the external bus only
after the write data becomes ready.
This write data wait period
generates idle cycles before the
write cycle. Note that when the
previous cycle is a write cycle and
the internal bus idle cycles are
shorter than the previous write
cycle, write data can be prepared in
parallel with the previous write cycle
and therefore, no idle cycle is
generated (write buffer effect).
For write → write or write →
read access cycles,
successive access cycles
without idle cycles are
frequently available due to
the write buffer effect
described in the left column. If
successive access cycles
without idle cycles are not
allowed, specify the minimum
number of idle cycles
between access cycles
through CSnBCR.
(8)
Idle cycles
between
different
memory types
The number of idle cycles
depends on the target
memory types. See table
9.24.
To ensure the minimum pulse width 0 to 2.5
on the signal-multiplexed pins, idle
cycles may be inserted before
access after memory types are
switched. For some memory types,
idle cycles are inserted even when
memory types are not switched.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Note
One idle cycle is always
generated after a read cycle
with SDRAM interface.
Page 375 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
In the above conditions, a total of four conditions, that is, condition (1) or (2) (either one is
effective), condition (3) or (4) (either one is effective), a set of conditions (5) to (7) (these are
generated successively, and therefore the sum of them should be taken as one set of idle cycles),
and condition (8) are generated at the same time. The maximum number of idle cycles among
these four conditions becomes the number of idle cycles on the external bus. To ensure the
minimum idle cycles, be sure to make register settings for condition (1) or (2).
CK
External bus idle cycles
Previous access
Next access
CSn
Idle cycle after access
Idle cycle before access
[1] DMAIW[2:0] setting in CMNCR
[2] IWW[2:0] setting in CSnBCR
IWRWD[2:0] setting in CSnBCR
IWRWS[2:0] setting in CSnBCR
IWRRD[2:0] setting in CSnBCR
IWRRS[2:0] setting in CSnBCR
[3] WTRP[1:0] setting in CSnWCR
TRWL[1:0] setting in CSnWCR
WTRC[1:0] setting in CSnWCR
Either one of them
is effective
Condition [1] or [2]
Either one of them
is effective
Condition [3] or [4]
[4] WM setting in CSnWCR
[5] Read
data
transfer
[6] Internal bus idle cycles, etc.
[7] Write
data
wait
Set of conditions
[5] to [7]
[8] Idle cycles
between
Condition [8]
different
memory types
Note: A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7],
and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of
cycles among these four conditions become the number of idle cycles.
Figure 9.41 Idle Cycle Conditions
Page 376 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.22 Minimum Number of Idle Cycles on Internal Bus (CPU Operation)
Clock Ratio (Iφ:Bφ)
CPU Operation
4:1
2:1
1:1
Write → write
2
2
3
Write → read
0
0
1
Read → write
2
2
3
Read → read
0
0
1
Table 9.23 Minimum Number of Idle Cycles on Internal Bus (DMAC Operation)
Transfer Mode
DMAC Operation
Dual Address
Single Address
Write → write
0
2
Write → read
0 or 2
0
Read → write
0
0
Read → read
0
2
Notes: 1. The write → write and read → read columns in dual address transfer indicate the cycles
in the divided access cycles.
2. For the write → read cycles in dual address transfer, 0 means different channels are
activated successively and 2 means when the same channel is activated successively.
3. The write → read and read → write columns in single address transfer indicate the case
when different channels are activated successively. The "write" means transfer from a
device with DACK to external memory and the "read" means transfer from external
memory to a device with DACK.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 377 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Table 9.24 Number of Idle Cycles Inserted between Access Cycles to Different Memory
Types
Next Cycle
SDRAM
Burst ROM
MPX- Byte SRAM Byte SRAM
(Low-Frequency Burst ROM
Previous Cycle SRAM
(Asynchronous) I/O
(BAS = 0)
(BAS = 1)
SDRAM
Mode)
(Synchronous)
SRAM
0
0
1
0
1
1
1.5
0
Burst ROM
0
0
1
0
1
1
1.5
0
MPX-I/O
1
1
0
1
1
1
1.5
1
Byte SRAM
0
0
1
0
1
1
1.5
0
1
1
2
1
0
0
1.5
1
SDRAM
1
1
2
1
0
0
⎯
1
SDRAM
1.5
1.5
2.5
1.5
0.5
⎯
1
1.5
0
0
1
0
1
1
1.5
0
(asynchronous)
(BAS = 0)
Byte SRAM
(BAS = 1)
(low-frequency
mode)
Burst ROM
(synchronous)
Figure 9.42 shows sample estimation of idle cycles between access cycles. In the actual operation,
the idle cycles may become shorter than the estimated value due to the write buffer effect or may
become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU
instruction execution or CPU register conflicts. Please consider these errors when estimating the
idle cycles.
Page 378 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Sample Estimation of Idle Cycles between Access Cycles
This example estimates the idle cycles for data transfer from the CS1 space to CS2 space by CPU access. Transfer is
repeated in the following order: CS1 read → CS1 read → CS2 write → CS2 write → CS1 read → ...
• Conditions
The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0.
In CS1WCR and CS2WCR, the WM bit is set to 1 (external WAIT pin disabled) and the HW[1:0] bits are set to 00
(CS negation is not extended).
Iφ:Bφ is set to 4:1, and no other processing is done during transfer.
For both the CS1 and CS2 spaces, normal SRAM devices are connected, the bus width is 32 bits, and access size is
also 32 bits.
The idle cycles generated under each condition are estimated for each pair of access cycles. In the following table,
R indicates a read cycle and W indicates a write cycle.
R→R
R→W
W→W
W→R
[1] or [2]
0
0
0
0
CSnBCR is set to 0.
[3] or [4]
0
0
0
0
The WM bit is set to 1.
[5]
1
1
0
0
Generated after a read cycle.
[6]
0
2
2
0
See the Iφ:Bφ = 4:1 column in table 9.19.
[7]
0
1
0
0
No idle cycle is generated for the second time due to the
write buffer effect.
[5] + [6] + [7]
0
4
2
0
[8]
0
0
0
0
Value for SRAM → SRAM access
Estimated idle
cycles
1
4
2
0
Maximum value among conditions [1] or [2], [3] or [4],
[5] + [6] + [7], and [8]
Actual idle
cycles
1
4
2
1
The estimated value does not match the actual value in
the W → R cycles because the internal idle cycles due to
condition [6] is estimated as 0 but actually an internal idle
cycle is generated due to execution of a loop condition
check instruction.
Condition
Note
Figure 9.42 Comparison between Estimated Idle Cycles and Actual Value
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 379 of 1778
Section 9 Bus State Controller (BSC)
9.5.11
SH7280 Group, SH7243 Group
Bus Arbitration
The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus
mastership after receiving a bus request from another device.
Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released
immediately after receiving a bus request when a bus cycle is not being performed. The release of
bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even
when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be
performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot
be immediately determined whether or not bus mastership has been released by looking at the CSn
signal or other bus control signals. The states that do not allow bus mastership release are shown
below.
1. Between the read and write cycles of a TAS instruction, or 64-bit transfer cycle of an FMOV
instruction
2. Multiple bus cycles generated when the data bus width is smaller than the access size (for
example, between bus cycles when longword access is made to a memory with a data bus
width of 8 bits)
3. 16-byte transfer by the DMAC
4. Setting the BLOCK bit in CMNCR to 1
Moreover, by using DPRTY bit in CMNCR, whether the bus mastership request is received or not
can be selected during DMAC burst transfer.
The LSI has the bus mastership until a bus request is received from another device. Upon
acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases
the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI
acknowledges the negation (high level) of the BREQ signal that indicates the external device has
released the bus, it negates the BACK signal and resumes the bus usage.
With the SDRAM interface, all bank pre-charge commands (PALLs) are issued when active banks
exist and the bus is released after completion of a PALL command.
The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state
synchronized with the rising edge of CK. The bus mastership enable signal is asserted 0.5 cycles
after the above timing, synchronized with the falling edge of CK. The bus control signals (BS,
CSn, RASL, CASL, CKE, DQMxx, WRxx, RD, and RD/WR) are placed in the high-impedance
state at subsequent rising edges of CK. Bus request signals are sampled at the falling edge of
CKIO. Note that CKE, RASL, and CASL can continue to be driven at the previous value even in
the bus-released state by setting the HIZCNT bit in CMNCR.
Page 380 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
The sequence for reclaiming the bus mastership from an external device is described below. 1.5
cycles after the negation of BREQ is detected at the falling edge of CK, the bus control signals are
driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The
fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the
rising edge of the CK where address and data signals are driven. Figure 9.43 shows the bus
arbitration timing.
When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership
should be returned using the REFOUT signal. For details on the selection of REFOUT, see section
23, Pin Function Controller (PFC). The REFOUT signal is kept asserting at low level until the bus
mastership is acquired. The BREQ signal is negated by asserting the REFOUT signal and the bus
mastership is returned from the external device. If the bus mastership is not returned for a
refreshing period or longer, the contents of SDRAM cannot be guaranteed because a refreshing
cannot be executed.
While releasing the bus mastership, the SLEEP instruction (to enter sleep mode or standby mode),
as well as a manual reset, cannot be executed until the LSI obtains the bus mastership.
The BREQ input signal is ignored in standby mode and the BACK output signal is placed in the
high impedance state. If the bus mastership request is required in this state, the bus mastership
must be released by pulling down the BACK pin to enter standby mode.
The bus mastership release (BREQ signal for high level negation) after the bus mastership request
(BREQ signal for low level assertion) must be performed after the bus usage permission (BACK
signal for low level assertion). If the BREQ signal is negated before the BACK signal is asserted,
only one cycle of the BACK signal is asserted depending on the timing of the BREQ signal to be
negated and this may cause a bus contention between the external device and the LSI.
CK
BREQ
BACK
A25 to A0
D15 to D0
CSn
Other bus
contorol sigals
Figure 9.43 Bus Arbitration Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 381 of 1778
Section 9 Bus State Controller (BSC)
9.5.12
(1)
SH7280 Group, SH7243 Group
Others
Reset
The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on
reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state
after the internal reset is synchronized with the internal clock. All control registers are initialized.
In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
At manual reset, only the current bus cycle being executed is completed. Since the RTCNT
continues counting up during manual reset signal assertion, a refresh request occurs to initiate the
refresh cycle.
(2)
Access from the Side of the LSI Internal Bus Master
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the internal bus before the previous external bus cycle is completed in a write cycle. If
the on-chip module is read or written after the external low-speed memory is written, the on-chip
module can be accessed before the completion of the external low-speed memory write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by a bus master other than
the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read
cycle is initiated before the previous write cycle is completed. Note, however, that if both the
DMA source and destination addresses exist in external memory space, the next write cycle will
not be initiated until the previous write cycle is completed.
Changing the registers in the BSC while the write buffer is operating may disrupt correct write
access. Therefore, do not change the registers in the BSC immediately after a write access. If this
change becomes necessary, do it after executing a dummy read of the write data.
Page 382 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 9 Bus State Controller (BSC)
On-Chip Peripheral Module Access
To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design.
When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding
instructions without waiting for the completion of writing to registers.
For example, a case is described here in which the system is transferring to software standby mode
for power savings. To make this transition, the SLEEP instruction must be performed after setting
the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is
required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes
the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not
software standby mode. A dummy read of the STBCR register is indispensable to complete
writing to the STBY bit.
To reflect the change by internal peripheral registers while performing the succeeding instructions,
execute a dummy read of registers to which write instruction is given and then perform the
succeeding instructions.
Table 9.25 shows the number of cycles required for access to the on-chip peripheral I/O registers
by the CPU.
Table 9.25 Number of Cycles for Access to On-Chip Peripheral module registers
Number of Access Cycles
Write
(2 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ
Read
(2 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ + (2 + I) × Iφ
Notes: The above indicates the number of access cycles of which executed when the instructions
are by on-chip ROM or by on-chip RAM.
When Iφ:Bφ = 1:1, n = 0 and I = 0.
When Iφ:Bφ = 2:1, n = 1 to 0 and I = 1.
When Iφ:Bφ = 4:1, n = 3 to 0 and I = 2.
When Iφ:Bφ = 8:1, n = 7 to 0 and I = 2.
When Bφ:Pφ = 1:1, m = 0.
When Bφ:Pφ = 2:1, m = 1 to 0.
When Bφ:Pφ = 4:1, m = 3 to 0.
n and m depend on the internal execution state.
Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus
are input and output in synchronization with rising edges of the corresponding clock signal. The C
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 383 of 1778
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
bus, the I bus, and the peripheral bus are synchronized with the Iφ, Bφ, and Pφ clock, respectively.
Figure 9.44 shows an example of the timing of write access to a peripheral bus when Iφ:Bφ:Pφ =
4:4:1. C bus whose are connected to CPU outputs data in synchronization with Iφ. A data transfer
from C bus to I bus requires a period of 2Iφ + Bφ when Iφ:Bφ = 1:1. The transfer from the I bus to
the peripheral bus, when Bφ:Pφ = 4:1, there are 4 clocks exist between Pφ × 1. Thus maximum the
period of 4 × Bφ is required corresponds to the rising edge of Pφ, which the timing of data output
to the peripheral bus from the I bus. When Iφ: Bφ = 4:2, transfer of data from the I bus to the
peripheral bus takes (3 + n) × Iφ (4 × Bφ is indicated in figure 9.44). The relation between the
timing of data output to the I bus and the rising edge of Pφ depends on the state of program
execution. In the case shown in the figure, where n = 0 and m = 3, the time required for access is 2
× Iφ + 4 × Bφ + 2 × Pφ.
Iφ
C bus
Bφ
I bus
Pφ
Peripheral bus
(2 + n) × Iφ
(1 + m) × Bφ
2 × Pφ
Figure 9.44 Timing of Write Access to On-Chip Peripheral I/O Registers
When Iφ;Bφ:Pφ = 4:4:1
Figure 9.45 shows an example of timing of read access to the peripheral bus when Iφ:Bφ:Pφ =
4:2:1. Transfer from the C bus to the peripheral bus is performed in the same way as for write
access. In the case of reading, however, values output onto the peripheral bus must be transferred
to the CPU. Although transfers from the peripheral bus to the I bus and from the I bus to the C bus
are performed in synchronization with the rising edge of the respective bus clocks, a period of (2 +
l) × Iφ is actually required because Iφ ≥ Bφ≥ Pφ. In the case shown in the figure 9.45, where n = 1,
m = 1, and l = 1, the time required for access is 3 × Iφ + 2 × Bφ + 2 × Pφ + 3 × Iφ.
Page 384 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 9 Bus State Controller (BSC)
Iφ
C bus
Bφ
I bus
Pφ
Peripheral bus
(2 + n) × Iφ
(1 + m) × Bφ
2 × Pφ
(2 + I) × Iφ
Figure 9.45 Timing of Read Access to On-Chip Peripheral I/O Registers
When Iφ:Bφ:Pφ = 4:2:1
9.6
Interrupt Source
The BSC has the compare match interrupt (CMI) as an interrupt source.
Table 9.26 gives details on this interrupt source. The compare match interrupt enable bit (CMIE)
in the refresh timer control/status register (RTCSR) can be used to enable or disable the interrupt
source.
The compare match interrupt (CMI) is generated when the compare match flag (CMF) and
compare match interrupt enable bit (CMIE) in RTCSR are set to 1.
Clearing the interrupt flag bit to 0 cancels the interrupt request.
Table 9.26 Interrupt Source
Abbreviation
Interrupt Source
Interrupt Enable Bit
Interrupt Flag
CMI
Compare match interrupt
CMIE
CMF
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 385 of 1778
Section 9 Bus State Controller (BSC)
Page 386 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Section 10 Direct Memory Access Controller (DMAC)
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1
Features
• Number of channels selectable: Eight channels (channels 0 to 7) max.
CH0 to CH2 channels (SH7285, SH7243) and CH0 to CH3 channels (SH7286) can receive
external requests.
• 4-Gbyte physical address space
• Transfer data length is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes
(longword × 4)
• Maximum transfer count: 16,777,216 transfers (24 bits)
• Address mode: Dual address mode and single address mode are supported.
• Transfer requests
⎯ External request
⎯ On-chip peripheral module request
⎯ Auto request
The following modules can issue on-chip peripheral module requests.
⎯ Two SCIF sources, two IIC3 sources, one A/D converter source, five MTU2 sources, two
CMT sources, two USB sources, two SSU sources, and one RCAN source
• Selectable bus modes
⎯ Cycle steal mode (normal mode and intermittent mode)
⎯ Burst mode
• Selectable channel priority levels: The channel priority levels are selectable between fixed
mode and round-robin mode.
• Interrupt request: An interrupt request can be sent to the CPU on completion of half- or fulldata transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to
the CPU when half of the initially specified DMA transfer is completed.
• External request detection: There are following four types of DREQ input detection.
⎯ Low level detection
⎯ High level detection
⎯ Rising edge detection
⎯ Falling edge detection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 387 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
can be set independently.
• Support of reload functions in DMA transfer information registers: DMA transfer using the
same information as the current transfer can be repeated automatically without specifying the
information again. Modifying the reload registers during DMA transfer enables next DMA
transfer to be done using different transfer information. The reload function can be enabled or
disabled independently in each channel.
Figure 10.1 shows the block diagram of the DMAC.
RDMATCR_n
On-chip
memory
Iteration
control
On-chip
peripheral module
Register
control
DMATCR_n
RSAR_n
Internal bus
Peripheral bus
SAR_n
Start-up
control
RDAR_n
DAR_n
DMA transfer request signal
CHCR_n
DMA transfer acknowledge signal
HEIn
DEIn
Interrupt controller
Request
priority
control
DMAOR
DMARS0
to DMARS3
External ROM
Bus
interface
External RAM
DMAC module
External device
(memory mapped)
External device
(with acknowledge)
Bus state
controller
DREQ0 to DREQ3*
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR: DMA reload transfer count register
DMATCR: DMA transfer count register
DMA reload source address register
RSAR:
DMA source address register
SAR:
DMA reload destination address register
RDAR:
DMA destination address register
DAR:
DMA channel control register
CHCR:
DMA operation register
DMAOR:
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3
DMA transfer half-end interrupt request to the CPU
HEIn:
DMA transfer end interrupt request to the CPU
DEIn:
n = 0 to 7
Notes: * DREQ0 and DREQ1 (SH7285 and SH7243)
DREQ0 to DREQ3 (SH7286)
Figure 10.1 Block Diagram of DMAC
Page 388 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.2
Section 10 Direct Memory Access Controller (DMAC)
Input/Output Pins
The external pins for DMAC are described below. Table 10.1 lists the configuration of the pins
that are connected to external bus. DMAC has pins for four channels (CH0 to CH3) for SH7286
and two channels (CH0 and CH1) for SH7243 and SH7285, as the external bus use.
Table 10.1 Pin Configuration
Channel Name
Abbreviation I/O
Function
DMA transfer request DREQ0
I
DMA transfer request input from an
external device to channel 0
DMA transfer request DACK0
acknowledge
O
DMA transfer request acknowledge
output from channel 0 to an external
device
DMA transfer request DREQ1
I
DMA transfer request input from an
external device to channel 1
DMA transfer request DACK1
acknowledge
O
DMA transfer request acknowledge
output from channel 1 to an external
device
DMA transfer request DREQ2
I
DMA transfer request input from an
external device to channel 2 (only in
SH7286)
DMA transfer request DACK2
acknowledge
O
DMA transfer request acknowledge
output from channel 2 to an external
device (only in SH7286)
DMA transfer request DREQ3
I
DMA transfer request input from an
external device to channel 3 (only in
SH7286)
DMA transfer request DACK3
acknowledge
O
DMA transfer request acknowledge
output from channel 3 to an external
device (only in SH7286)
0
DMA transfer end
TEND0
O
DMA transfer end output for channel 0
1
DMA transfer end
TEND1
O
DMA transfer end output for channel 1
0
1
2
3
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 389 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.3
Register Descriptions
The DMAC has the registers listed in table 10.2. There are four control registers and three reload
registers for each channel, and one common control register is used by all channels. In addition,
there is one extension resource selector per two channels. Each channel number is expressed in the
register names, as in SAR_0 for SAR in channel 0.
Table 10.2 Register Configuration
Channel
Register Name
Abbreviation R/W
Initial Value
Address
Access
Size
0
DMA source address
register_0
SAR_0
R/W
H'00000000
H'FFFE1000
16, 32
DMA destination
address register_0
DAR_0
R/W
H'00000000
H'FFFE1004
16, 32
DMA transfer count
register_0
DMATCR_0
R/W
H'00000000
H'FFFE1008
16, 32
DMA channel control
register_0
CHCR_0
R/W*1 H'00000000
H'FFFE100C 8, 16, 32
DMA reload source
address register_0
RSAR_0
R/W
H'00000000
H'FFFE1100
16, 32
DMA reload destination RDAR_0
address register_0
R/W
H'00000000
H'FFFE1104
16, 32
DMA reload transfer
count register_0
RDMATCR_0 R/W
H'00000000
H'FFFE1108
16, 32
DMA source address
register_1
SAR_1
R/W
H'00000000
H'FFFE1010
16, 32
DMA destination
address register_1
DAR_1
R/W
H'00000000
H'FFFE1014
16, 32
DMA transfer count
register_1
DMATCR_1
R/W
H'00000000
H'FFFE1018
16, 32
DMA channel control
register_1
CHCR_1
R/W*1 H'00000000
H'FFFE101C 8, 16, 32
DMA reload source
address register_1
RSAR_1
R/W
H'00000000
H'FFFE1110
16, 32
DMA reload destination RDAR_1
address register_1
R/W
H'00000000
H'FFFE1114
16, 32
RDMATCR_1 R/W
H'00000000
H'FFFE1118
16, 32
1
DMA reload transfer
count register_1
Page 390 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Channel
Register Name
Abbreviation R/W
Initial Value
Address
Access
Size
2
DMA source address
register_2
SAR_2
R/W
H'00000000
H'FFFE1020
16, 32
DMA destination
address register_2
DAR_2
R/W
H'00000000
H'FFFE1024
16, 32
DMA transfer count
register_2
DMATCR_2
R/W
H'00000000
H'FFFE1028
16, 32
DMA channel control
register_2
CHCR_2
R/W*1 H'00000000
H'FFFE102C 8, 16, 32
DMA reload source
address register_2
RSAR_2
R/W
H'00000000
H'FFFE1120
16, 32
DMA reload destination RDAR_2
address register_2
R/W
H'00000000
H'FFFE1124
16, 32
DMA reload transfer
count register_2
RDMATCR_2 R/W
H'00000000
H'FFFE1128
16, 32
DMA source address
register_3
SAR_3
R/W
H'00000000
H'FFFE1030
16, 32
DMA destination
address register_3
DAR_3
R/W
H'00000000
H'FFFE1034
16, 32
DMA transfer count
register_3
DMATCR_3
R/W
H'00000000
H'FFFE1038
16, 32
DMA channel control
register_3
CHCR_3
R/W*1 H'00000000
H'FFFE103C 8, 16, 32
DMA reload source
address register_3
RSAR_3
R/W
H'00000000
H'FFFE1130
16, 32
DMA reload destination RDAR_3
address register_3
R/W
H'00000000
H'FFFE1134
16, 32
RDMATCR_3 R/W
H'00000000
H'FFFE1138
16, 32
3
DMA reload transfer
count register_3
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 391 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Channel
Register Name
Abbreviation R/W
Initial Value
Address
Access
Size
4
DMA source address
register_4
SAR_4
R/W
H'00000000
H'FFFE1040
16, 32
DMA destination
address register_4
DAR_4
R/W
H'00000000
H'FFFE1044
16, 32
DMA transfer count
register_4
DMATCR_4
R/W
H'00000000
H'FFFE1048
16, 32
DMA channel control
register_4
CHCR_4
R/W*1 H'00000000
H'FFFE104C 8, 16, 32
DMA reload source
address register_4
RSAR_4
R/W
H'00000000
H'FFFE1140
16, 32
DMA reload destination RDAR_4
address register_4
R/W
H'00000000
H'FFFE1144
16, 32
DMA reload transfer
count register_4
RDMATCR_4 R/W
H'00000000
H'FFFE1148
16, 32
DMA source address
register_5
SAR_5
R/W
H'00000000
H'FFFE1050
16, 32
DMA destination
address register_5
DAR_5
R/W
H'00000000
H'FFFE1054
16, 32
DMA transfer count
register_5
DMATCR_5
R/W
H'00000000
H'FFFE1058
16, 32
DMA channel control
register_5
CHCR_5
R/W*1 H'00000000
H'FFFE105C 8, 16, 32
DMA reload source
address register_5
RSAR_5
R/W
H'00000000
H'FFFE1150
16, 32
DMA reload destination RDAR_5
address register_5
R/W
H'00000000
H'FFFE1154
16, 32
RDMATCR_5 R/W
H'00000000
H'FFFE1158
16, 32
5
DMA reload transfer
count register_5
Page 392 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Channel
Register Name
Abbreviation R/W
Initial Value
Address
Access
Size
6
DMA source address
register_6
SAR_6
R/W
H'00000000
H'FFFE1060
16, 32
DMA destination
address register_6
DAR_6
R/W
H'00000000
H'FFFE1064
16, 32
DMA transfer count
register_6
DMATCR_6
R/W
H'00000000
H'FFFE1068
16, 32
DMA channel control
register_6
CHCR_6
R/W*1 H'00000000
H'FFFE106C 8, 16, 32
DMA reload source
address register_6
RSAR_6
R/W
H'00000000
H'FFFE1160
16, 32
DMA reload destination RDAR_6
address register_6
R/W
H'00000000
H'FFFE1164
16, 32
DMA reload transfer
count register_6
RDMATCR_6 R/W
H'00000000
H'FFFE1168
16, 32
DMA source address
register_7
SAR_7
R/W
H'00000000
H'FFFE1070
16, 32
DMA destination
address register_7
DAR_7
R/W
H'00000000
H'FFFE1074
16, 32
DMA transfer count
register_7
DMATCR_7
R/W
H'00000000
H'FFFE1078
16, 32
DMA channel control
register_7
CHCR_7
R/W*1 H'00000000
H'FFFE107C 8, 16, 32
DMA reload source
address register_7
RSAR_7
R/W
H'00000000
H'FFFE1170
16, 32
DMA reload destination RDAR_7
address register_7
R/W
H'00000000
H'FFFE1174
16, 32
RDMATCR_7 R/W
H'00000000
H'FFFE1178
16, 32
7
DMA reload transfer
count register_7
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 393 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Address
Access
Size
R/W*2 H'0000
H'FFFE1200
8, 16
DMARS0
R/W
H'0000
H'FFFE1300
16
DMA extension
resource selector 1
DMARS1
R/W
H'0000
H'FFFE1304
16
4 and 5
DMA extension
resource selector 2
DMARS2
R/W
H'0000
H'FFFE1308
16
6 and 7
DMA extension
resource selector 3
DMARS3
R/W
H'0000
H'FFFE130C 16
Channel
Register Name
Abbreviation R/W
Common
DMA operation register DMAOR
0 and 1
DMA extension
resource selector 0
2 and 3
Initial Value
Notes: 1. For the HE and TE bits in CHCRn, only 0 can be written to clear the flags after 1 is
read.
2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is
read.
Page 394 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.3.1
Section 10 Direct Memory Access Controller (DMAC)
DMA Source Address Registers (SAR)
The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the
source address of a DMA transfer. During a DMA transfer, these registers indicate the next source
address. When the data of an external device with DACK is transferred in single address mode,
SAR is ignored.
To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address
boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary.
SAR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
16
Page 395 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.3.2
DMA Destination Address Registers (DAR)
The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address. When the data of an external device with DACK is transferred in single
address mode, DAR is ignored.
To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address
boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary.
DAR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Page 396 of 1778
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.3.3
Section 10 Direct Memory Access Controller (DMAC)
DMA Transfer Count Registers (DMATCR)
The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify
the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215
when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA
transfer, these registers indicate the remaining transfer count.
The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.
DMATCR is initialized to H'00000000 by a reset and retains the value in software standby mode
and module standby mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value:
R/W:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
16
Page 397 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.3.4
DMA Channel Control Registers (CHCR)
The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control
DMA transfer mode.
The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions
can be read and written to in channels 0 to 3, but they are reserved in channels 4 to 7. The TL bit
which specifies the TEND external pin function can be read and written to in channels 0 and 1, but
it is reserved in channels 2 to 7.
CHCR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit:
Initial value:
R/W:
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TC
-
-
RLD
-
-
-
-
DO
TL
-
-
HE
HIE
AM
AL
0
R/W
0
R
0
R
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
15
14
13
12
11
10
9
8
4
DM[1:0]
Initial value:
R/W:
0
R/W
0
R/W
SM[1:0]
0
R/W
0
R/W
RS[3:0]
0
R/W
0
R/W
0
R/W
0
R/W
7
6
5
DL
DS
TB
0
R/W
0
R/W
0
R/W
0
0
R/(W)* R/W
3
TS[1:0]
0
R/W
0
R/W
2
1
0
IE
TE
DE
0
0
0
R/W R/(W)* R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
Initial
Value
R/W
Descriptions
31
TC
0
R/W
Transfer Count Mode
Specifies whether to transmit data once or for the
count specified in DMATCR by one transfer request.
Note that when this bit is set to 0, the TB bit must not
be set to 1 (burst mode). When the USB, RCAN, SSU,
SCIF_3, or IIC3 is selected for the transfer request
source, this bit (TC) must not be set to 1.
0: Transmits data once by one transfer request
1: Transmits data for the count specified in DMATCR
by one transfer request
30, 29
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 398 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
28
RLD
0
R/W
Reload Function Enable or Disable
Enables or disables the reload function.
0: Disables the reload function
1: Enables the reload function
27 to 24
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
23
DO
0
R/W
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 to
CHCR_3. This bit is reserved in CHCR_4 and
CHCR_7; it is always read as 0 and the write value
should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22
TL
0
R/W
Transfer End Level
Specifies the TEND signal output is high active or low
active. This bit is valid only in CHCR_0 and CHCR_1.
This bit is reserved in CHCR_2 to CHCR_7; it is
always read as 0 and the write value should always be
0.
0: Low-active output from TEND
1: High-active output from TEND
21, 20
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 399 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
19
HE
0
R/(W)* Half-End Flag
Descriptions
This bit is set to 1 when the transfer count reaches half
of the DMATCR value that was specified before
transfer starts.
If DMA transfer ends because of an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR before the transfer count reaches
half of the initial DMATCR value, the HE bit is not set
to 1. If DMA transfer ends due to an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR after the HE bit is set to 1, the bit
remains set to 1.
To clear the HE bit, write 0 to it after HE = 1 is read.
0: DMATCR > (DMATCR set before transfer starts)/2
during DMA transfer or after DMA transfer is
terminated
[Clearing condition]
•
Writing 0 after reading HE = 1.
1: DMATCR ≤ (DMATCR set before transfer starts)/2
18
HIE
0
R/W
Half-End Interrupt Enable
Specifies whether to issue an interrupt request to the
CPU when the transfer count reaches half of the
DMATCR value that was specified before transfer
starts.
When the HIE bit is set to 1, the DMAC requests an
interrupt to the CPU when the HE bit becomes 1.
0: Disables an interrupt to be issued when DMATCR
= (DMATCR set before transfer starts)/2
1: Enables an interrupt to be issued when DMATCR
= (DMATCR set before transfer starts)/2
Page 400 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
17
AM
0
R/W
Acknowledge Mode
Specifies whether DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: DACK output in read cycle (dual address mode)
1: DACK output in write cycle (dual address mode)
16
AL
0
R/W
Acknowledge Level
Specifies the DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 to CHCR_3. This bit is
reserved in CHCR_4 to CHCR_7; it is always read as
0 and the write value should always be 0.
0: Low-active output from DACK
1: High-active output from DACK
Note: To use the DACK pins as high-active output, pull
them down and perform the following settings.
1. After the reset start, specify the high-active
output by this bit in CHCR for the DACK pins.
2. Then specify the DACK pins for the pin
function controller setting.
3. The DACK pin setting in CHCR should be
retained hereafter.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 401 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
15,14
DM[1:0]
00
R/W
Destination Address Mode
These bits select whether the DMA destination
address is incremented, decremented, or left fixed. (In
single address mode, DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (Setting prohibited in 16byte transfer)
01: Destination address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit transfer,
+16 in 16-byte transfer)
10: Destination address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer,
setting prohibited in 16-byte transfer)
11: Setting prohibited
13, 12
SM[1:0]
Page 402 of 1778
00
R/W
Source Address Mode
These bits select whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with
DACK.)
00: Fixed source address (Setting prohibited in 16byte-unit transfer)
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longwordunit transfer, setting prohibited in 16-byte-unit
transfer)
11: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
11 to 8
RS[3:0]
0000
R/W
Resource Select
These bits specify which transfer requests will be sent
to the DMAC. The changing of transfer request source
should be done in the state when DMA enable bit (DE)
is set to 0.
0000: External request, dual address mode
0001: Setting prohibited
0010: External request/single address mode
External address space → External device with
DACK
0011: External request/single address mode
External device with DACK → External address
space
0100: Auto request
0101: Setting prohibited
0110: Setting prohibited
0111: Setting prohibited
1000: DMA extension resource selector
1001: Setting prohibited
1010: Setting prohibited
1011: Setting prohibited
1100: Setting prohibited
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
Note: External request specification is valid only in
CHCR_0 to CHCR_3. If a request source is
selected in channels CHCR_4 to CHCR_7, no
operation will be performed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 403 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
7
DL
0
R/W
DREQ Level
6
DS
0
R/W
DREQ Edge Select
These bits specify the sampling method of the DREQ
pin input and the sampling level.
These bits are valid only in CHCR_0 to CHCR_3.
These bits are reserved in CHCR_4 to CHCR_7; they
are always read as 0 and the write value should
always be 0.
If the transfer request source is specified as an on-chip
peripheral module or if an auto-request is specified, the
specification by these bits is ignored.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5
TB
0
R/W
Transfer Bus Mode
Specifies bus mode when DMA transfers data. Note
that burst mode must not be selected when TC = 0.
0: Cycle steal mode
1: Burst mode
4, 3
TS[1:0]
00
R/W
Transfer Size
These bits specify the size of data to be transferred.
Select the size of data to be transferred when the
source or destination is an on-chip peripheral module
register of which transfer size is specified.
00: Byte unit
01: Word unit (two bytes)
10: Longword unit (four bytes)
11: 16-byte unit (four longwords)
2
IE
0
R/W
Interrupt Enable
Specifies whether or not an interrupt request is
generated to the CPU at the end of the DMA transfer.
Setting this bit to 1 generates an interrupt request
(DEI) to the CPU when TE bit is set to 1.
0: Disables an interrupt request
1: Enables an interrupt request
Page 404 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
1
TE
0
R/(W)* Transfer End Flag
Descriptions
This bit is set to 1 when DMATCR becomes 0 and
DMA transfer ends.
The TE bit is not set to 1 in the following cases.
•
DMA transfer ends due to an NMI interrupt or
DMA address error before DMATCR becomes 0.
•
DMA transfer is ended by clearing the DE bit and
DME bit in DMA operation register (DMAOR).
To clear the TE bit, write 0 after reading TE = 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
terminated
[Clearing condition]
•
Writing 0 after reading TE = 1
1: DMA transfer ends by the specified count
(DMATCR = 0)
0
DE
0
R/W
DMA Enable
Enables or disables the DMA transfer. In auto-request
mode, DMA transfer starts by setting the DE bit and
DME bit in DMAOR to 1. In this case, all of the bits
TE, NMIF in DMAOR, and AE must be 0. In an
external request or peripheral module request, DMA
transfer starts if DMA transfer request is generated by
the devices or peripheral modules after setting the
bits DE and DME to 1. In this case, however, all of the
bits TE, NMIF, and AE must be 0 as in the case of
auto-request mode. Clearing the DE bit to 0 can
terminate the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note:
*
Only 0 can be written to clear the flag after 1 is read.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 405 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.3.5
DMA Reload Source Address Registers (RSAR)
The DMA reload source address registers (RSAR) are 32-bit readable/writable registers.
When the reload function is enabled, the RSAR value is written to the source address register
(SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer
can be preset in RSAR during the current DMA transfer. When the reload function is disabled,
RSAR is ignored.
To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address
boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary.
RSAR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Page 406 of 1778
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.3.6
Section 10 Direct Memory Access Controller (DMAC)
DMA Reload Destination Address Registers (RDAR)
The DMA reload destination address registers (RDAR) are 32-bit readable/writable registers.
When the reload function is enabled, the RDAR value is written to the destination address register
(DAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer
can be preset in RDAR during the current DMA transfer. When the reload function is disabled,
RDAR is ignored.
To transfer data of 16-bit or 32-bit width, specify the address with 16-bit or 32-bit address
boundary respectively. To transfer data in units of 16 bytes, set a value at a 16-byte boundary.
RDAR is initialized to H'00000000 by a reset and retains the value in software standby mode and
module standby mode.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
16
Page 407 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.3.7
DMA Reload Transfer Count Registers (RDMATCR)
The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers.
When the reload function is enabled, the RDMATCR value is written to the transfer count register
(DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA
transfer can be preset in RDMATCR during the current DMA transfer. When the reload function
is disabled, RDMATCR is ignored.
The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0.
As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when
H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in
16 bytes, one 16-byte transfer (128 bits) counts one.
RDMATCR is initialized to H'00000000 by a reset and retains the value in software standby mode
and module standby mode.
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value:
R/W:
Page 408 of 1778
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.3.8
Section 10 Direct Memory Access Controller (DMAC)
DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
priority level of channels at the DMA transfer. This register also shows the DMA transfer status.
DMAOR is initialized to H'0000 by a reset and retains the value in software standby mode and
module standby mode.
Bit:
Initial value:
R/W:
15
14
-
-
0
R
0
R
13
12
CMS[1:0]
0
R/W
0
R/W
11
10
-
-
0
R
0
R
9
8
PR[1:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
⎯
All 0
R
Reserved
7
6
5
4
3
2
1
0
-
-
-
-
-
AE
NMIF
DME
0
R
0
R
0
R
0
R
0
R
0
0
0
R/(W)* R/(W)* R/W
These bits are always read as 0. The write value
should always be 0.
13, 12
CMS[1:0]
00
R/W
Cycle Steal Mode Select
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make intermittent mode
valid.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer for every 16 cycles of
Bφ clock.
11: Intermittent mode 64
Executes one DMA transfer for every 64 cycles of
Bφ clock.
11, 10
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 409 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
9, 8
PR[1:0]
00
R/W
Priority Mode
These bits select the priority level between channels
when there are transfer requests for multiple channels
simultaneously.
00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 >
CH5 > CH6 > CH7
01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 >
CH6 > CH3 > CH7
10: Setting prohibited
11: Round-robin mode (only supported in CH0 to CH3)
7 to 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
AE
0
R/(W)* Address Error Flag
Indicates whether an address error has occurred by
the DMAC. When this bit is set, even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1, DMA
transfer is not enabled. This bit can only be cleared by
writing 0 after reading 1.
0: No DMAC address error
1: DMAC address error occurred
[Clearing condition]
•
1
NMIF
0
Writing 0 after reading AE = 1
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. When this bit
is set, even if the DE bit in CHCR and the DME bit in
DMAOR are set to 1, DMA transfer is not enabled. This
bit can only be cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress
can be done in one transfer unit. Even if the NMI
interrupt is input while the DMAC is not in operation,
the NMIF bit is set to 1.
0: No NMI interrupt
1: NMI interrupt occurred
[Clearing condition]
•
Page 410 of 1778
Writing 0 after reading NMIF = 1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Description
0
DME
0
R/W
DMA Master Enable
Enables or disables DMA transfer on all channels. If
the DME bit and DE bit in CHCR are set to 1, DMA
transfer is enabled.
However, transfer is enabled only when the TE bit in
CHCR of the transfer corresponding channel, the NMIF
bit in DMAOR, and the AE bit are all cleared to 0.
Clearing the DME bit to 0 can terminate the DMA
transfer on all channels.
0: DMA transfer is disabled on all channels
1: DMA transfer is enabled on all channels
Note:
*
To clear the flags, read the register and write 0 only to the bits that were read as 1.
Write 1 to the bits that were read as 0.
If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If
fixed mode 2 is specified, the channel priority is specified as CH0 > CH4 > CH1 > CH5 > CH2 >
CH6 > CH3 > CH7. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 >
CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If round-robin mode is specified, the transfer end
channel is reset.
Table 10.3 show the priority change in each mode (modes 0 to 2) specified by the priority mode
bits. In each priority mode, the channel priority to accept the next transfer request may change in
up to three ways according to the transfer end channel.
For example, when the transfer end channel is channel 1, the priority of the channel to accept the
next transfer request is specified as CH2 > CH3 > CH0 >CH1 > CH4 > CH5 > CH6 > CH7. When
the transfer end channel is any one of the channels 4 to 7, round-robin will not be applied and the
priority level is not changed at the end of transfer in the channels 4 to 7.
The DMAC internal operation for an address error is as follows:
• No address error: Read (source to DMAC) → Write (DMAC to destination)
• Address error in source address: Nop → Nop
• Address error in destination address: Read → Nop
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 411 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Table 10.3 Combinations of Priority Mode Bits
Transfer
Priority Level at the End of Transfer
Priority Mode
End
Bits
High
Low
Mode
CH No.
PR[1]
PR[0]
0
1
2
3
4
5
6
7
Mode 0
Any
0
0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
(fixed mode 1)
channel
Mode 1
Any
0
1
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
(fixed mode 2)
channel
Mode 2
CH0
1
1
CH1
CH2
CH3
CH0
CH4
CH5
CH6
CH7
CH1
1
1
CH2
CH3
CH0
CH1
CH4
CH5
CH6
CH7
CH2
1
1
CH3
CH0
CH1
CH2
CH4
CH5
CH6
CH7
CH3
1
1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH4
1
1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH5
1
1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH6
1
1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH7
1
1
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
(round-robin mode)
Page 412 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.3.9
Section 10 Direct Memory Access Controller (DMAC)
DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3)
The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that
specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for
channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and
DMARS3 is for channels 6 and 7. Table 10.4 shows the specifiable combinations.
DMARS can specify transfer requests from two SCIF sources, two IIC3 sources, one A/D
converter source, five MTU2 sources, two CMT sources, two USB sources, one RCAN_ET
source, and two SSU sources.
DMARS is initialized to H'0000 by a reset and retains the value in software standby mode and
module standby mode.
• DMARS0
Bit:
15
14
13
12
11
10
CH1 MID[5:0]
Initial value:
R/W:
0
R/W
0
R/W
9
8
7
6
CH1 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
13
12
11
10
5
4
3
2
1
CH0 MID[5:0]
0
R/W
0
R/W
0
R/W
0
R/W
9
8
7
6
0
CH0 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
5
4
3
2
0
R/W
0
R/W
1
0
• DMARS1
Bit:
15
14
CH3 MID[5:0]
Initial value:
R/W:
0
R/W
0
R/W
CH3 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
13
12
11
10
CH2 MID[5:0]
0
R/W
0
R/W
0
R/W
0
R/W
9
8
7
6
CH2 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
5
4
3
2
0
R/W
0
R/W
1
0
• DMARS2
Bit:
15
14
CH5 MID[5:0]
Initial value:
R/W:
0
R/W
0
R/W
CH5 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
13
12
11
10
CH4 MID[5:0]
0
R/W
0
R/W
0
R/W
0
R/W
9
8
7
6
CH4 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
5
4
3
2
0
R/W
0
R/W
1
0
• DMARS3
Bit:
15
14
CH7 MID[5:0]
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
0
R/W
CH7 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
CH6 MID[5:0]
0
R/W
0
R/W
0
R/W
0
R/W
CH6 RID[1:0]
0
R/W
0
R/W
0
R/W
0
R/W
Page 413 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Transfer requests from the various modules specify MID and RID as shown in table 10.4.
Table 10.4 DMARS Settings
Setting Value for
One Channel
({MID, RID})
MID
RID
Function
USBRXI
H'81
B'100000
B'01
Receive
USBTXI
H'82
B'10
Transmit
Peripheral Module
USB
RCAN_ET
RM0_0
H'86
B'100001
B'10
Receive
SSU
SSTXI
H'89
B'100010
B'01
Transmit
SSRXI
H'8A
B'10
Receive
TXI3
H'8D
B'01
Transmit
RXI3
H'8E
B'10
Receive
TXI
H'A1
B'01
Transmit
RXI
H'A2
B'10
Receive
A/D converter_0
ADI0
H'B3
B'101100
B'11
⎯
MTU2_0
TGIA_0
H'E3
B'111000
B'11
⎯
MTU2_1
TGIA_1
H'E7
B'111001
B'11
⎯
MTU2_2
TGIA_2
H'EB
B'111010
B'11
⎯
MTU2_3
TGIA_3
H'EF
B'111011
B'11
⎯
MTU2_4
TGIA_4
H'F3
B'111100
B'11
⎯
CMT_0
CMI0
H'FB
B'111110
B'11
⎯
CMT_1
CMI0
H'FF
B'111111
B'11
⎯
SCIF_3
IIC3
B'100011
B'101000
When MID or RID other than the values listed in table 10.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits
(RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set,
the transfer request source is not accepted.
Page 414 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.4
Section 10 Direct Memory Access Controller (DMAC)
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. In bus mode, burst mode or cycle steal mode can be selected.
10.4.1
Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extension resource selector (DMARS) are set for the target transfer
conditions, the DMAC transfers data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of
data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus
mode.
3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the
initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1.
4. When transfer has been completed for the specified count (when DMATCR reaches 0), the
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is
terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in
DMAOR is cleared to 0.
Figure 10.2 is a flowchart of this procedure.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 415 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR,
DMAOR, DMARS)
DE, DME = 1 and
NMIF, AE, TE = 0?
No
Yes
Transfer request
occurs?*1
No
*2
Yes
*3
Bus mode,
transfer request mode,
DREQ detection system
Transfer (one transfer unit);
DMATCR – 1 → DMATCR,
SAR and DAR updated
No
DMATCR = 0?
Yes
No
DMATCR=1/2 ?
Yes
TE = 1
HE=1
DEI interrupt request
(when IE = 1)
HEI interrupt request
(when HE = 1)
When reload function is enabled,
RSAR → SAR, RDAR → DAR,
and RDMATCR → DMATCR
When the TC bit in CHCR is 0, or
for a request from an on-chip peripheral
module, the transfer acknowledge
signal is sent to the module.
For a request from an
on-chip peripheral module,
the transfer acknowledge signal
is sent to the module.
NMIF = 1
or AE = 1 or DE = 0
or DME = 0?
No
Yes
Transfer end
NMIF = 1
or AE = 1 or DE = 0
or DME = 0?
No
Yes
Normal end
Transfer terminated
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the
DE and DME bits are set to 1.
2. DREQ level detection in burst mode (external request) or cycle steal mode.
3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode.
Figure 10.2 DMA Transfer Flowchart
Page 416 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.4.2
Section 10 Direct Memory Access Controller (DMAC)
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated in external devices and on-chip peripheral modules that are neither the
transfer source nor destination.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_7 and
DMARS0 to DMARS3.
(1)
Auto-Request Mode
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal
internally. When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set to 1,
the transfer begins so long as the TE bits in CHCR_0 to CHCR_7, and the AE and NMIF bits in
DMAOR are 0.
(2)
External Request Mode
In this mode a transfer is performed at the request signals (DREQ0 to DREQ3) of an external
device. Choose one of the modes shown in table 10.5 according to the application system. When
the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), DMA transfer is
performed upon a request at the DREQ input.
Table 10.5 Selecting External Request Modes with the RS Bits
RS[3] RS[2] RS[1] RS[0] Address Mode
Transfer Source
0
0
0
0
Dual address mode
Any
0
0
1
0
Single address mode External memory,
memory-mapped
external device
1
External device with
DACK
Transfer
Destination
Any
External device with
DACK
External memory,
memory-mapped
external device
Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in
CHCR_0 to CHCR_3 as shown in table 10.6. The source of the transfer request does not have to
be the data transfer source or destination.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 417 of 1778
Section 10 Direct Memory Access Controller (DMAC)
SH7280 Group, SH7243 Group
Table 10.6 Selecting External Request Detection with DL and DS Bits
CHCR
DL bit
0
1
DS bit
Detection of External Request
0
Low level detection
1
Falling edge detection
0
High level detection
1
Rising edge detection
When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive
period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again
enters the request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is terminated after the same number of transfer has been performed as
requests.
Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 10.7 Selecting External Request Detection with DO Bit
CHCR
DO bit
External Request
0
Overrun 0
1
Overrun 1
Page 418 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 10 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request
In this mode, the transfer is performed in response to the DMA transfer request signal from an onchip peripheral module.
DMA transfer request signals from on-chip peripheral modules to the DMAC include transmit
data empty and receive data full requests from the SCIF, A/D conversion end transfer request from
the A/D converter, compare match transfer request from the CMT, and data transfer requests from
the IIC3, MTU2, RCAN_ET, SSU, and USB.
When a transfer request signal is sent in on-chip peripheral module request mode while DMA
transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, and NMIF = 0), DMA transfer is
performed.
When the transmit data empty from the SCIF is selected, specify the transfer destination as the
corresponding SCIF transmit data register. Likewise, when the receive data full from the SCIF is
selected, specify the transfer source as the corresponding SCIF receive data register. When a
transfer request is made by the A/D converter, the transfer source must be the A/D data register
(ADDR). When the IIC3 transmit is selected as the transfer request, the transfer destination must
be ICDRT; when the IIC3 reception is selected as the transfer request, the transfer source must be
ICDRR. When the USB is selected as the transfer request, the transfer destination must be the
USBEP2 data register (USBEPDR2). When the SSU is selected as the transfer request, the transfer
destination must be an SS transmit data register (SSTDR0 to SSTDR3). Any address can be
specified for data transfer source and destination when a transfer request is sent from the CMT or
MTU2.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 419 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Table 10.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR
DMARS
DMA Transfer
Request Signal
Transfer
Source
USB receive
EP1 FIFO full transfer request
(USBRXI)
USBEPDR1 Any
USB transmit
EP2 FIFO empty transfer request Any
(USBTXI)
USBEPDR2
100001 10
RCAN
RM0 (RCAN receive interrupt)
MB0 to
MB31
Any
100010 01
SSU transmit
SSTXI (transmit data empty)
Any
SSTDR0 to Cycle
SSTDR3
steal
SSU receive
SSRXI (receive data full)
SSRDR0 to Any
SSRDR3
RS[3:0] MID
1000
DMA Transfer
Request
RID Source
100000 01
10
10
100011 01
10
101000 01
10
Transfer
Bus
Destination Mode
SCIF_3 transmit TXI3 (transmit FIFO data empty) Any
SCFTDR3
SCIF_3 receive
RXI3 (receive FIFO data full)
SCFRDR3
Any
IIC3 transmit
TXI (transmit data empty)
Any
ICDRT
IIC3 receive
RXI (receive data full)
ICDRR
Any
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
101100 11
A/D converter_0 ADI0 (A/D conversion end)
ADDR0 to
ADDR3
Any
Cycle
steal
111000 11
MTU2_0
TGIA_0
Any
Any
111001 11
MTU2_1
TGIA_1
Any
Any
Cycle
steal or
burst
111010 11
MTU2_2
TGIA_2
Any
Any
111011 11
MTU2_3
TGIA_3
Any
Any
111100 11
MTU2_4
TGIA_4
Any
Any
111110 11
CMT_0
Compare match 0
Any
Any
111111 11
CMT_1
Compare match 1
Any
Any
Page 420 of 1778
Cycle
steal or
burst
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.4.3
Section 10 Direct Memory Access Controller (DMAC)
Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to a predetermined priority order. Three modes (fixed mode 1, fixed mode 2,
and round-robin mode) are selected using the PR1 and PR0 bits in DMAOR.
(1)
Fixed Mode
In fixed modes, the priority levels among the channels remain fixed. There are two kinds of fixed
modes as follows:
Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7
These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR).
(2)
Round-Robin Mode
Each time one unit of word, byte, longword, or 16 bytes is transferred on one channel, the priority
order is rotated. The channel on which the transfer was just finished is rotated to the lowest of the
priority order among the four round-robin channels (channels 0 to 4). The priority of the channels
other than the round-robin channels (channels 0 to 4) does not change even in round-robin mode.
The round-robin mode operation is shown in figure 10.3. The priority in round-robin mode is CH0
> CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 immediately after a reset.
When round-robin mode has been specified, do not concurrently specify cycle steal mode and
burst mode as the bus modes of any two or more channels.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 421 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order
after transfer
CH1 > CH2 > CH3 > CH0 > CH4 > CH5 > CH6 > CH7
Channel 0 is given the lowest priority
among the round-robin channels.
(2) When channel 1 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order
after transfer
CH2 > CH3 > CH0 > CH1 > CH4 > CH5 > CH6 > CH7
Channel 1 is given the lowest priority
among the round-robin channels. The
priority of channel 0, which was higher
than channel 1, is also shifted.
(3) When channel 2 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order
after transfer
CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7
Post-transfer priority order
when there is an
immediate transfer
request to channel 5 only
Channel 2 is given the lowest priority
among the round-robin channels. The
priority of channels 0 and 1, which were
higher than channel 2, is also shifted. If
there is a transfer request only to
channel 5 immediately after that, the
priority does not change because
channel 5 is not a round-robin channel.
CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7
(4) When channel 7 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order does not change.
Figure 10.3 Round-Robin Mode
Page 422 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.4 shows how the priority order changes when channel 0 and channel 3 transfers are
requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
transfer).
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
waiting)
4. When the channel 0 transfer ends, channel 0 is given the lowest priority among the round-robin
channels.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
(channel 3 waits for transfer).
6. When the channel 1 transfer ends, channel 1 is given the lowest priority among the round-robin
channels.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 are lowered in priority so that channel 3 is
given the lowest priority among the round-robin channels.
Transfer request
Waiting channel(s)
DMAC operation
Channel priority
(1) Channels 0 and 3
(2) Channel 0 transfer start
(3) Channel 1
0>1>2>3>4>5>6>7
3
1, 3 (4) Channel 0 transfer ends
Priority order
changes
1>2>3>0>4>5>6>7
(5) Channel 1 transfer starts
3
(6) Channel 1 transfer ends
Priority order
changes
2>3>0>1>4>5>6>7
(7) Channel 3 transfer starts
None
(8) Channel 3 transfer ends
Priority order
changes
0>1>2>3>4>5>6>7
Figure 10.4 Changes in Channel Priority in Round-Robin Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 423 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.4.4
DMA Transfer Types
DMA transfer has two types: single address mode transfer and dual address mode transfer. They
depend on the number of bus cycles of access to the transfer source and destination. A data
transfer timing depends on the bus mode, which is cycle steal mode or burst mode. The DMAC
supports the transfers shown in table 10.9.
Table 10.9 Supported DMA Transfers
Transfer Destination
External Device
with DACK
External
Memory
Memory-Mapped
External Device
On-Chip
On-Chip
Peripheral Module Memory
External device
with DACK
Not available
Dual, single
Dual, single
Not available
Not available
External memory
Dual, single
Dual
Dual
Dual
Dual
Memory-mapped
external device
Dual, single
Dual
Dual
Dual
Dual
On-chip
peripheral module
Not available
Dual
Dual
Dual
Dual
On-chip memory
Not available
Dual
Dual
Dual
Dual
Transfer Source
Notes: 1. Dual: Dual address mode
2. Single: Single address mode
3. 16-byte transfer is available only for on-chip peripheral modules that support longword
access.
Page 424 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
(1)
Address Modes
(a)
Dual Address Mode
In dual address mode, both the transfer source and destination are accessed (selected) by an
address. The transfer source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
10.5, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a data write cycle.
DMAC
SAR
Data bus
Address bus
DAR
Memory
Transfer source
module
Transfer destination
module
Data buffer
The SAR value is an address, data is read from the transfer source module,
and the data is tempolarily stored in the DMAC.
First bus cycle
DMAC
Memory
Data bus
DAR
Address bus
SAR
Transfer source
module
Transfer destination
module
Data buffer
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 10.5 Data Flow of Dual Address Mode
Auto request, external request, and on-chip peripheral module request are available for the transfer
request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the
channel control register (CHCR) can specify whether the DACK is output in read cycle or write
cycle.
Figure 10.6 shows an example of DMA transfer timing in dual address mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 425 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
CK
A25 to A0
Transfer source
address
Transfer destination
address
CSn
D31 to D0
RD
WRxx
DACKn
(Active-low)
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 10.6 Example of DMA Transfer Timing in Dual Mode
(Transfer Source: Normal Memory, Transfer Destination: Normal Memory)
Page 426 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 10 Direct Memory Access Controller (DMAC)
Single Address Mode
In single address mode, both the transfer source and destination are external devices, either of
them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In
this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external
devices by outputting the DACK transfer request acknowledge signal to it, and at the same time
outputting an address to the other device involved in the transfer. For example, in the case of
transfer between external memory and an external device with DACK shown in figure 10.7, when
the external device outputs data to the data bus, that data is written to the external memory in the
same bus cycle.
External address bus
External data bus
This LSI
External
memory
DMAC
External device
with DACK
DACK
DREQ
Data flow (from memory to device)
Data flow (from device to memory)
Figure 10.7 Data Flow in Single Address Mode
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. In both cases, only the external request signal (DREQ) is used
for transfer requests.
Figure 10.8 shows an example of DMA transfer timing in single address mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 427 of 1778
Section 10 Direct Memory Access Controller (DMAC)
SH7280 Group, SH7243 Group
CK
A25 to A0
Address output to external memory space
CSn
Select signal to external memory space
WRxx
Write strobe signal to external memory space
Data output from external device with DACK
D31 to D0
DACKn
DACK signal (active-low) to external device with DACK
(a) External device with DACK → External memory space (normal memory)
CK
A25 to A0
Address output to external memory space
CSn
Select signal to external memory space
RD
Read strobe signal to external memory space
Data output from external memory space
D31 to D0
DACKn
DACK signal (active-low) to external device with DACK
(b) External memory space (normal memory) → External device with DACK
Figure 10.8 Example of DMA Transfer Timing in Single Address Mode
(2)
Bus Modes
There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel
control registers (CHCR).
(a)
Cycle Steal Mode
• Normal mode
In normal mode of cycle steal, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from another bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to
another bus master. This is repeated until the transfer end conditions are satisfied.
The cycle-steal normal mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination.
Figure 10.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
⎯ Dual address mode
⎯ DREQ low level detection
Page 428 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU
CPU
DMAC DMAC
CPU
Read/Write
DMAC DMAC CPU
Read/Write
Figure 10.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
• Intermittent Mode 16 and Intermittent Mode 64
In intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next
transfer request occurs after that, DMAC obtains the bus mastership from other bus master
after waiting for 16 or 64 cycles of Bφ clock. DMAC then transfers data of one unit and returns
the bus mastership to other bus master. These operations are repeated until the transfer end
condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA
transfer than normal mode of cycle steal.
The cycle-steal intermittent mode can be used for any transfer section; transfer request source,
transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in
all channels.
Figure 10.10 shows an example of DMA transfer timing in cycle-steal intermittent mode.
Transfer conditions shown in the figure are:
⎯ Dual address mode
⎯ DREQ low level detection
DREQ
More than 16 or 64 Bφ clock cycles
(depends on the CPU's condition of using bus)
Bus cycle
CPU
CPU
CPU DMAC DMAC
Read/Write
CPU
CPU
DMAC DMAC
CPU
Read/Write
Figure 10.10 Example of DMA Transfer in Cycle-Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 429 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
(b)
Burst Mode
In burst mode, once the DMAC obtains the bus mastership, it does not release the bus mastership
and continues to perform transfer until the transfer end condition is satisfied. In external request
mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the
bus mastership is passed to another bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Figure 10.11 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC
Read
Write
Read
CPU
CPU
Write
Figure 10.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
(3)
Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 10.10 shows the relationship between request modes and bus modes by DMA transfer
category.
Page 430 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Table 10.10 Relationship of Request Modes and Bus Modes by DMA Transfer Category
Address
Mode
Transfer Category
Dual
Request
Mode
Bus
Mode
Transfer
Size (Bits)
Usable
Channels
External device with DACK and external memory
External
B/C
8/16/32/128
0 to 3
External device with DACK and memory-mapped
external device
External
B/C
8/16/32/128
0 to 3
External memory and external memory
All*
4
B/C
8/16/32/128
0 to 7*
External memory and memory-mapped external
device
All*
4
B/C
8/16/32/128
0 to 7*
Memory-mapped external device and memorymapped external device
All*
4
B/C
8/16/32/128
0 to 7*
External memory and on-chip peripheral module
All*
1
B/C*
Memory-mapped external device and
on-chip peripheral module
All*
1
B/C*
1
Single
3
3
5
8/16/32/128*
5
8/16/32/128*
B/C*
5
4
4
1
B/C*
8/16/32/128*
0 to 7*
On-chip peripheral module and on-chip peripheral All*
module
On-chip memory and on-chip memory
3
All*
2
0 to 7*
3
2
0 to 7*
8/16/32/128*
2
0 to 7*
B/C
8/16/32/128
0 to 7*
B/C
8/16/32/128
0 to 7*
3
3
3
3
On-chip memory and memory-mapped external
device
All*
On-chip memory and on-chip peripheral module
All*
On-chip memory and external memory
All*
4
B/C
8/16/32/128
0 to 7*
External device with DACK and external memory
External
B/C
8/16/32/128
0 to 3
External device with DACK and memory-mapped
external device
External
B/C
8/16/32/128
0 to 3
5
2
3
3
[Legend]
B: Burst
C: Cycle steal
Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all
available. However, along with the exception of CMT and MTU2 as the transfer request
source, the requesting module must be designated as the transfer source or the
transfer destination.
2. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
3. If the transfer request is an external request, channels 0 to 3 are only available.
4. External requests, auto requests, and on-chip peripheral module requests are all
available. In the case of on-chip peripheral module requests, however, the CMT and
MTU2 are only available.
5. Only cycle steal except for the MTU2 and CMT as the transfer request source.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 431 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
(4)
Bus Mode and Channel Priority
In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a
request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0
will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer
on channel 1 will only resume on completion of the transfer on channel 0.
When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the
higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing
the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1,
channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is
replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of
this is shown in figure 10.12.
When multiple channels are in burst mode, data transfer on the channel that has the highest
priority is given precedence. When DMA transfer is being performed on multiple channels, the
bus mastership is not released to another bus-master device until all of the competing burst-mode
transfers have been completed.
CPU
CPU
DMA
CH1
DMA
CH1
DMAC CH1
Burst mode
DMA
CH0
DMA
CH1
DMA
CH0
CH0
CH1
CH0
DMAC CH0 and CH1
Cycle steal mode
DMA
CH1
DMA
CH1
DMAC CH1
Burst mode
CPU
CPU
Priority: CH0 > CH1
CH0: Cycle steal mode
CH1: Burst mode
Figure 10.12 Bus State when Multiple Channels are Operating
In round-robin mode, the priority changes as shown in figure 10.3. Note that channels in cycle
steal and burst modes must not be mixed.
Page 432 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.4.5
(1)
Section 10 Direct Memory Access Controller (DMAC)
Number of Bus Cycles and DREQ Pin Sampling Timing
Number of Bus Cycles
When the DMAC is the bus master, the number of bus cycles is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
(2)
DREQ Pin Sampling Timing
Figures 10.13 to 10.16 show the DREQ input sampling timings in each bus mode.
CK
Bus cycle
DREQ
(Rising)
CPU
CPU
1st acceptance
DMAC
CPU
2nd acceptance
Non sensitive period
DACK
(Active-high)
Acceptance start
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CK
Bus cycle
DREQ
(Overrun 0 at
high level)
CPU
CPU
DMAC
CPU
2nd acceptance
1st acceptance
Non sensitive period
DACK
(Active-high)
Acceptance
start
CK
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
DMAC
CPU
2nd acceptance
Non sensitive period
Acceptance
start
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 433 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
CK
Bus cycle
DREQ
(Rising)
CPU
CPU
DMAC
DMAC
Burst acceptance
Non sensitive period
DACK
(Active-high)
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CK
Bus cycle
DREQ
(Overrun 0 at
high level)
CPU
CPU
DMAC
2nd
acceptance
1st acceptance
Non sensitive period
DACK
(Active-high)
Acceptance
start
CK
Bus cycle
DREQ
(Overrun 1 at
high level)
CPU
CPU
1st acceptance
DMAC
2nd acceptance
DMAC
3rd
acceptance
Non sensitive period
DACK
(Active-high)
Acceptance
start
Acceptance
start
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection
Page 434 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.17 shows the TEND output timing.
CK
End of DMA transfer
Bus cycle
DMAC
CPU
DMAC
CPU
CPU
DREQ
DACK
TEND
Figure 10.17 Example of DMA Transfer End Signal Timing
(Cycle Steal Mode Level Detection)
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit or 16-bit external device, when longword access is performed for an 8-bit
or 16-bit external device, or when word access is performed for an 8-bit external device. When a
setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal
is negated between bus cycles, note that DACK and TEND are divided like the CS signal for data
alignment. Also, if the DREQ detection is set to level-detection mode (DS bit in CHCR = 0), the
DREQ sampling may not be detected correctly with divided DACK, and one extra overrun may
occur at maximum.
Use a setting that does not divide DACK or specify a transfer size smaller than the external device
bus width if DACK is divided. Figure 10.18 shows this example.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 435 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
T1
T2
Taw
T1
T2
CK
Address
CS
RD
Data
WRxx
DACKn
(Active low)
TEND
(Active low)
WAIT
Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit
is divided into multiple bus cycles and the CS is negated between
the bus cycles, TEND is also divided.
Figure 10.18 BSC Normal Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Page 436 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
10.5
Interrupt Sources
10.5.1
Interrupt Sources and Priority Order
Section 10 Direct Memory Access Controller (DMAC)
The interrupt sources of the DMAC are the data transfer end interrupt (DEI) and data transfer halfend interrupt (HEI) for each channel.
Table 10.11 lists the interrupt sources and their priority. The IE and HIE bits in the DMA channel
control registers (CHCRs) enable or disable the respective interrupt sources. Furthermore, the
interrupt requests are independently conveyed to the interrupt controller.
A data-transfer end interrupt (DEI) is generated when, the transfer end flag and the transfer end
interrupt enable (IE) bit in the DMA channel control register (CHCR) are set to 1.
A data-transfer half end interrupt (HEI) is generated when the half-end flag and half-end interrupt
enable (HIE) bit in the DMA channel control register (CHCR) are set to 1.
Clearing the interrupt flag bit to 0 cancels the interrupt request.
Priority among the channels is adjustable by the interrupt controller. The order of priority for
interrupts of a given channel is fixed. For details, refer to section 6, Interrupt Controller (INTC).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 437 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
Table 10.11 Interrupt Sources
Channel
Interrupt Source
Interrupt
Enable Bit
Interrupt
Flag
Priority
0
Data transfer end interrupt (DEI0)
IE
TE
High
Data transfer half-end interrupt (HEI0)
HIE
HE
Data transfer end interrupt (DEI1)
IE
TE
Data transfer half-end interrupt (HEI1)
HIE
HE
Data transfer end interrupt (DEI2)
IE
TE
Data transfer half-end interrupt (HEI2)
HIE
HE
1
2
3
4
5
6
7
Data transfer end interrupt (DEI3)
IE
TE
Data transfer half-end interrupt (HEI3)
HIE
HE
Data transfer end interrupt (DEI4)
IE
TE
Data transfer half-end interrupt (HEI4)
HIE
HE
Data transfer end interrupt (DEI5)
IE
TE
Data transfer half-end interrupt (HEI5)
HIE
HE
Data transfer end interrupt (DEI6)
IE
TE
Data transfer half-end interrupt (HEI6)
HIE
HE
Data transfer end interrupt (DEI7)
IE
TE
Data transfer half-end interrupt (HEI7)
HIE
HE
Page 438 of 1778
Low
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.6
Usage Notes
10.6.1
Setting of the Half-End Flag and the Half-End Interrupt
Since the following points for caution apply in cases where reference to the state of the half-end
flag in the CHCR register or the half-end interrupt is used in conjunction with the reload function,
please take care on these points.
Ensure that the reloaded number of transfers (the value set in RDMATCR) is always the same as
the number of transfers that was initially set (the value set in DMATCR). If the initial setting in
DMATCR and the value for the second and later transfers in RDMATCR are different, the timing
with which the half-end flag is set may be faster than half the number of transfers, or the half-end
flag might not be set at all. The same considerations apply to the half-end interrupt.
10.6.2
Timing of DACK and TEND Outputs
When the external memory is MPX-I/O or burst MPX-I/O, assertion of the DACK output has the
same timing as the data cycle. For details, see the respective figures under section 9.5.5, MPX-I/O
Interface, in section 9, Bus State Controller (BSC).
When the memory is other than the MPX-I/O or burst MPX-I/O, the DACK output is asserted
with the same timing as the corresponding CS signal.
The TEND output does not depend on the type of memory and is always asserted with the same
timing as the corresponding CS signal.
10.6.3
CHCR Setting
When changing the CHCR setting, the DE bit of the relevant channel must be cleared before the
change.
10.6.4
Note on Activation of Multiple Channels
The same internal request must not be set to more than one channel.
10.6.5
Note on Transfer Request Input
A transfer request should be input after the DMAC settings have been made.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 439 of 1778
SH7280 Group, SH7243 Group
Section 10 Direct Memory Access Controller (DMAC)
10.6.6
Conflict between NMI Interrupt and DMAC Activation
When a conflict occurs between the generation of the NMI interrupt and the DMAC activation, the
NMI interrupt has priority. Thus the NMIF bit is set to 1 and the DMAC is not activated.
It takes 2 × Bcyc or 3 × Pcyc for checking DMAC stop by the NMI, 4 × Bcyc for checking DMAC
activation by the DREQ, and 1 × Bcyc + 1 × Pcyc for checking DMAC activation by a peripheral
module (Bcyc indicates the cycle of the external bus clock, Pcyc indicates the cycle of the
peripheral clock).
10.6.7
Number of On-Chip RAM Access Cycles from DMAC
The number of on-chip RAM access cycles from the DMAC becomes the number of cycles shown
in table 10.12, depending on whether the operation is read or write and the clock ratio between Iφ
(internal clock) and Bφ (external bus clock).
Table 10.12 Number of On-Chip RAM Access Cycles from DMAC
Setting of Iφ:Bφ
Read Operation
Write Operation
1:1
3 × Bcyc
2 × Bcyc
1:1/2
2 × Bcyc
2 × Bcyc
1:1/4
2 × Bcyc
2 × Bcyc
Smaller than 1:1/4
1 × Bcyc
1 × Bcyc
Note: Bcyc indicates the cycle of the external bus clock.
Page 440 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer
channels.
11.1
Features
• Maximum 16 pulse input/output lines and three pulse input lines
• Selection of eight counter input clocks for each channel (four clocks for channel 5)
• The following operations can be set for channels 0 to 4:
⎯ Waveform output at compare match
⎯ Input capture function
⎯ Counter clear operation
⎯ Multiple timer counters (TCNT) can be written to simultaneously
⎯ Simultaneous clearing by compare match and input capture is possible
⎯ Register simultaneous input/output is possible by synchronous counter operation
⎯ A maximum 12-phase PWM output is possible in combination with synchronous operation.
• Buffer operation settable for channels 0, 3, and 4
• Phase counting mode settable independently for each of channels 1 and 2
• Cascade connection operation
• Fast access via internal 16-bit bus
• 28 interrupt sources
• Automatic transfer of register data
• A/D converter start trigger can be generated
• Module standby mode can be settable
• A total of six-phase waveform output, which includes complementary PWM output, and
positive and negative phases of reset PWM output by interlocking operation of channels 3 and
4, is possible.
• AC synchronous motor (brushless DC motor) drive mode using complementary PWM output
and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the
selection of two types of waveform outputs (chopping and level) is possible.
• Dead time compensation counter available in channel 5
• External pulse width measurement available in channel 5
• In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D
converter start triggers can be skipped.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 441 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.1 MTU2 Functions
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Count clock
Pφ/1
Pφ/4
Pφ/16
Pφ/64
TCLKA
TCLKB
TCLKC
TCLKD
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
TCLKA
TCLKB
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/1024
TCLKA
TCLKB
TCLKC
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
TCLKA
TCLKB
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
TCLKA
TCLKB
Pφ/1
Pφ/4
Pφ/16
Pφ/64
General registers
TGRA_0
TGRB_0
TGRE_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRU_5
TGRV_5
TGRW_5
General registers/
buffer registers
TGRC_0
TGRD_0
TGRF_0
—
—
TGRC_3
TGRD_3
TGRC_4
TGRD_4
—
I/O pins
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC2B
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
TIOC4B
TIOC4C
TIOC4D
Input pins
TIC5U
TIC5V
TIC5W
Counter clear
function
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
Compare 0 output √
match
1 output √
output
Toggle √
output
√
√
√
√
—
√
√
√
√
—
√
√
√
√
—
Input capture
function
√
√
√
√
√
√
Synchronous
operation
√
√
√
√
√
—
PWM mode 1
√
√
√
√
√
—
PWM mode 2
√
√
√
—
—
—
Complementary
PWM mode
—
—
—
√
√
—
Page 442 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Item
Channel 0
Reset PWM mode —
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
—
—
√
√
—
AC synchronous
motor drive mode
√
—
—
√
√
—
Phase counting
mode
—
√
√
—
—
—
Buffer operation
√
—
—
√
√
—
Dead time
compensation
counter function
—
—
—
—
—
√
External pulse
width
measurement
—
—
—
—
—
√
DMAC activation
TGRA_0
compare
match or
input capture
TGRA_1
compare
match or
input
capture
TGRA_2
compare
match or
input capture
TGRA_3
compare
match or
input
capture
TGRA_4
compare
match or
input capture
and TCNT
overflow or
underflow
—
DTC activation
TGR
compare
match or
input capture
TGR
compare
match or
input
capture
TGR
compare
match or
input capture
TGR
compare
match or
input
capture
TGR
compare
match or
input capture
or TCNT
overflow or
underflow
TGR
compare
match or
input capture
A/D converter start TGRA_0
trigger
compare
match or
input capture
TGRA_1
compare
match or
input
capture
TGRA_2
compare
match or
input capture
TGRA_3
compare
match or
input
capture
TGRA_4
compare
match or
input capture
—
TGRE_0
compare
match
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
TCNT_4
underflow
(trough) in
complement
ary PWM
mode
Page 443 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Interrupt sources
7 sources
4 sources
4 sources
5 sources
5 sources
3 sources
•
•
•
Compare •
Compare
Compare •
Compare •
Compare •
Compare
match or
match or
match or
match or
match or
match or
input
input
input
input
input
input
capture
capture
capture
capture
capture
capture
0A
1A
2A
3A
4A
5U
Compare •
Compare
Compare •
Compare •
Compare •
Compare
match or
match or
match or
match or
match or
match or
input
input
input
input
input
input
capture
capture
capture
capture
capture
capture
0B
1B
2B
3B
4B
5V
Compare •
Compare •
Compare
match or
match or
match or
input
input
input
input
capture
capture
capture
capture
3C
4C
5W
Compare •
Compare
match or
match or
match or
input
input
input
capture
capture
capture
0D
3D
4D
•
•
Compare •
Overflow
match or
Underflow •
•
•
Overflow
•
Underflow
0C
•
•
•
Compare
Compare
•
•
Overflow
•
Overflow
match 0E
or
Compare
underflow
match 0F
•
Page 444 of 1778
Overflow
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Item
Channel 0
A/D converter start —
request delaying
function
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
—
—
—
•
—
A/D
converter
start
request at
a match
between
TADCOR
A_4 and
TCNT_4
•
A/D
converter
start
request at
a match
between
TADCOR
B_4 and
TCNT_4
Interrupt skipping
function
—
—
—
•
Skips
•
Skips
TGRA_3
TCIV_4
compare
interrupts
—
match
interrupts
[Legend]
√:
Possible
—:
Not possible
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 445 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel 5: TGIU_5
TGIV_5
TGIW_5
TGRW
TGRD
TGRD
TCNTW
TGRB
TGRC
TGRB
TGRC
TCBR
TDDR
TGRV
TCNTV
TCDR
TCNT
TGRA
TCNT
TGRA
TCNTS
TCNTU
BUS I/F
TGRF
TGRE
TGRD
TGRB
TGRB
TGRB
A/D converter conversion
start signal
Channels 0 to 4: TRGAN
Channel 0:
TRG0N
Channel 4:
TRG4AN
TRG4BN
TGRC
TCNT
TGRA
TCNT
TGRA
TCNT
TGRA
TSR
TIER
TSR
TIER
TSR
TIER
Interrupt request signals
Channel 3: TGIA_3
TGIB_3
TGIC_3
TGID_3
TCIV_3
Channel 4: TGIA_4
TGIB_4
TGIC_4
TGID_4
TCIV_4
Peripheral bus
TSTR
Module data bus
TSR
TIER
TSYR
TGRU
TSR
TIER
TIER
TGCR
TSR
TMDR
TIORL
TIORH
TIORL
TIORH
TIOR
TIOR
TIOR
TIORL
TIORH
Channel 5
Common
Control logic
TMDR
Channel 2
TCR
TMDR
Channel 1
TCR
Channel 0
Control logic for channels 0 to 2
Input/output pins
Channel 0: TIOC0A
TIOC0B
TIOC0C
TIOC0D
Channel 1: TIOC1A
TIOC1B
Channel 2: TIOC2A
TIOC2B
TMDR
Clock input
Internal clock:
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
External clock: TCLKA
TCLKB
TCLKC
TCLKD
TCR
Input pins
Channel 5: TIC5U
TIC5V
TIC5W
TCR
TOER
TOCR
Channel 3
TCR
TMDR
Channel 4
TCR
Input/output pins
Channel 3: TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4: TIOC4A
TIOC4B
TIOC4C
TIOC4D
Control logic for channels 3 and 4
Figure 11.1 shows a block diagram of the MTU2.
Interrupt request signals
Channel 0: TGIA_0
TGIB_0
TGIC_0
TGID_0
TGIE_0
TGIF_0
TCIV_0
Channel 1: TGIA_1
TGIB_1
TCIV_1
TCIU_1
Channel 2: TGIA_2
TGIB_2
TCIV_2
TCIU_2
[Legend]
TSTR: Timer start register
TSYR: Timer synchronous register
TCR: Timer control register
TMDR: Timer mode register
TIOR: Timer I/O control register
TIORH: Timer I/O control register H
TIORL: Timer I/O control register L
TIER: Timer interrupt enable register
TGCR: Timer gate control register
TOER: Timer output master enable register
TOCR: Timer output control register
TSR:
Timer status register
TCNT: Timer counter
TCNTS: Timer subcounter
TCDR:
TCBR:
TDDR:
TGRA:
TGRB:
TGRC:
TGRD:
TGRE:
TGRF:
TGRU:
TGRV:
TGRW:
Timer cycle data register
Timer cycle buffer register
Timer dead time data register
Timer general register A
Timer general register B
Timer general register C
Timer general register D
Timer general register E
Timer general register F
Timer general register U
Timer general register V
Timer general register W
Figure 11.1 Block Diagram of MTU2
Page 446 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.2
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Input/Output Pins
Table 11.2 Pin Configuration
Channel Pin Name I/O
Function
Common TCLKA
Input
External clock A input pin
(Channel 1 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channel 1 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channel 2 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channel 2 phase counting mode B phase input)
TIOC0A
I/O
TGRA_0 input capture input/output compare output/PWM output pin
TIOC0B
I/O
TGRB_0 input capture input/output compare output/PWM output pin
TIOC0C
I/O
TGRC_0 input capture input/output compare output/PWM output pin
TIOC0D
I/O
TGRD_0 input capture input/output compare output/PWM output pin
TIOC1A
I/O
TGRA_1 input capture input/output compare output/PWM output pin
TIOC1B
I/O
TGRB_1 input capture input/output compare output/PWM output pin
0
1
2
3
4
5
TIOC2A
I/O
TGRA_2 input capture input/output compare output/PWM output pin
TIOC2B
I/O
TGRB_2 input capture input/output compare output/PWM output pin
TIOC3A
I/O
TGRA_3 input capture input/output compare output/PWM output pin
TIOC3B
I/O
TGRB_3 input capture input/output compare output/PWM output pin
TIOC3C
I/O
TGRC_3 input capture input/output compare output/PWM output pin
TIOC3D
I/O
TGRD_3 input capture input/output compare output/PWM output pin
TIOC4A
I/O
TGRA_4 input capture input/output compare output/PWM output pin
TIOC4B
I/O
TGRB_4 input capture input/output compare output/PWM output pin
TIOC4C
I/O
TGRC_4 input capture input/output compare output/PWM output pin
TIOC4D
I/O
TGRD_4 input capture input/output compare output/PWM output pin
TIC5U
Input
TGRU_5 input capture input/external pulse input pin
TIC5V
Input
TGRV_5 input capture input/external pulse input pin
TIC5W
Input
TGRW_5 input capture input/external pulse input pin
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 447 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3
Register Descriptions
The MTU2 has the following registers. For details on register addresses and register states during
each process, refer to section 30, List of Registers. To distinguish registers in each channel, an
underscore and the channel number are added as a suffix to the register name; TCR for channel 0
is expressed as TCR_0.
Table 11.3 Register Descriptions
Register Name
Abbreviation
R/W
Initial
value
Address
Access
Size
Timer control register_3
TCR_3
R/W
H'00
H'FFFE4200
8, 16, 32
Timer control register_4
TCR_4
R/W
H'00
H'FFFE4201
8
Timer mode register_3
TMDR_3
R/W
H'00
H'FFFE4202
8, 16
Timer mode register_4
TMDR_4
R/W
H'00
H'FFFE4203
8
Timer I/O control register H_3
TIORH_3
R/W
H'00
H'FFFE4204
8, 16, 32
Timer I/O control register L_3
TIORL_3
R/W
H'00
H'FFFE4205
8
Timer I/O control register H_4
TIORH_4
R/W
H'00
H'FFFE4206
8, 16
Timer I/O control register L_4
TIORL_4
R/W
H'00
H'FFFE4207
8
Timer interrupt enable register_3
TIER_3
R/W
H'00
H'FFFE4208
8, 16
Timer interrupt enable register_4
TIER_4
R/W
H'00
H'FFFE4209
8
Timer output master enable register
TOER
R/W
H'C0
H'FFFE420A
8
Timer gate control register
TGCR
R/W
H'80
H'FFFE420D
8
Timer output control register 1
TOCR1
R/W
H'00
H'FFFE420E
8, 16
Timer output control register 2
TOCR2
R/W
H'00
H'FFFE420F
8
Timer counter_3
TCNT_3
R/W
H'0000
H'FFFE4210
16, 32
Timer counter_4
TCNT_4
R/W
H'0000
H'FFFE4212
16
Timer cycle control register
TCDR
R/W
H'FFFF
H'FFFE4214
16, 32
Timer dead time data register
TDDR
R/W
H'FFFF
H'FFFE4216
16
Timer general register A_3
TGRA_3
R/W
H'FFFF
H'FFFE4218
16, 32
Timer general register B_3
TGRB_3
R/W
H'FFFF
H'FFFE421A
16
Timer general register A_4
TGRA_4
R/W
H'FFFF
H'FFFE421C
16, 32
Page 448 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Register Name
Abbreviation
R/W
Initial
value
Address
Access
Size
Timer general register B_4
TGRB_4
R/W
H'FFFF
H'FFFE421E
16
Timer subcounter
TCNTS
R
H'0000
H'FFFE4220
16, 32
Timer cycle buffer register
TCBR
R/W
H'FFFF
H'FFFE4222
16
Timer general register C_3
TGRC_3
R/W
H'FFFF
H'FFFE4224
16, 32
Timer general register D_3
TGRD_3
R/W
H'FFFF
H'FFFE4226
16
Timer general register C_4
TGRC_4
R/W
H'FFFF
H'FFFE4228
16, 32
Timer general register D_4
TGRD_4
R/W
H'FFFF
H'FFFE422A
16
Timer status register_3
TSR_3
R/W
H'C0
H'FFFE422C
8, 16
Timer status register_4
TSR_4
R/W
H'C0
H'FFFE422D
8
Timer interrupt skipping set register TITCR
R/W
H'00
H'FFFE4230
8, 16
Timer interrupt skipping counter
TITCNT
R
H'00
H'FFFE4231
8
Timer buffer transfer set register
TBTER
R/W
H'00
H'FFFE4232
8
Timer dead time enable register
TDER
R/W
H'01
H'FFFE4234
8
Timer output level buffer register
TOLBR
R/W
H'00
H'FFFE4236
8
Timer buffer operation transfer
mode register_3
TBTM_3
R/W
H'00
H'FFFE4238
8, 16
Timer buffer operation transfer
mode register_4
TBTM_4
R/W
H'00
H'FFFE4239
8
Timer A/D converter start request
control register
TADCR
R/W
H'0000
H'FFFE4240
16
Timer A/D converter start request
cycle set register A_4
TADCORA_4 R/W
H'FFFF
H'FFFE4244
16, 32
Timer A/D converter start request
cycle set register B_4
TADCORB_4 R/W
H'FFFF
H'FFFE4246
16
Timer A/D converter start request
cycle set buffer register A_4
TADCOBRA_4 R/W
H'FFFF
H'FFFE4248
16, 32
Timer A/D converter start request
cycle set buffer register B_4
TADCOBRB_4 R/W
H'FFFF
H'FFFE424A
16
Timer waveform control register
TWCR
R/W
H'00
H'FFFE4260
8
Timer start register
TSTR
R/W
H'00
H'FFFE4280
8, 16
Timer synchronous register
TSYR
R/W
H'00
H'FFFE4281
8
Timer counter synchronous start
register
TCSYSTR
R/W
H'00
H'FFFE4282
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 449 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Register Name
Abbreviation
R/W
Initial
value
Address
Access
Size
Timer read/write enable register
TRWER
R/W
H'01
H'FFFE4284
8
Timer control register_0
TCR_0
R/W
H'00
H'FFFE4300
8, 16, 32
Timer mode register_0
TMDR_0
R/W
H'00
H'FFFE4301
8
Timer I/O control registerH_0
TIORH_0
R/W
H'00
H'FFFE4302
8, 16
Timer I/O control registerL_0
TIORL_0
R/W
H'00
H'FFFE4303
8
Timer interrupt enable register_0
TIER_0
R/W
H'00
H'FFFE4304
8, 16, 32
Timer status register_0
TSR_0
R/W
H'C0
H'FFFE4305
8
Timer counter_0
TCNT_0
R/W
H'0000
H'FFFE4306
16
Timer general register A_0
TGRA_0
R/W
H'FFFF
H'FFFE4308
16, 32
Timer general register B_0
TGRB_0
R/W
H'FFFF
H'FFFE430A
16
Timer general register C_0
TGRC_0
R/W
H'FFFF
H'FFFE430C
16, 32
Timer general register D_0
TGRD_0
R/W
H'FFFF
H'FFFE430E
16
Timer general register E_0
TGRE_0
R/W
H'FFFF
H'FFFE4320
16, 32
Timer general register F_0
TGRF_0
R/W
H'FFFF
H'FFFE4322
16
Timer interrupt enable register2_0
TIER2_0
R/W
H'00
H'FFFE4324
8, 16
Timer status register2_0
TSR2_0
R/W
H'C0
H'FFFE4325
8
Timer buffer operation transfer
mode register_0
TBTM_0
R/W
H'00
H'FFFE4326
8
Timer control register_1
TCR_1
R/W
H'00
H'FFFE4380
8, 16
Timer mode register_1
TMDR_1
R/W
H'00
H'FFFE4381
8
Timer I/O control register_1
TIOR_1
R/W
H'00
H'FFFE4382
8
Timer interrupt enable register_1
TIER_1
R/W
H'00
H'FFFE4384
8, 16, 32
Timer status register_1
TSR_1
R/W
H'C0
H'FFFE4385
8
Timer counter_1
TCNT_1
R/W
H'0000
H'FFFE4386
16
Timer general register A_1
TGRA_1
R/W
H'FFFF
H'FFFE4388
16, 32
Page 450 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Register Name
Abbreviation
R/W
Initial
value
Address
Access
Size
Timer general register B_1
TGRB_1
R/W
H'FFFF
H'FFFE438A
16
Timer input capture control register
TICCR
R/W
H'00
H'FFFE4390
8
Timer control register_2
TCR_2
R/W
H'00
H'FFFE4000
8, 16
Timer mode register_2
TMDR_2
R/W
H'00
H'FFFE4001
8
Timer I/O control register_2
TIOR_2
R/W
H'00
H'FFFE4002
8
Timer interrupt enable register_2
TIER_2
R/W
H'00
H'FFFE4004
8, 16, 32
Timer status register_2
TSR_2
R/W
H'C0
H'FFFE4005
8
Timer counter_2
TCNT_2
R/W
H'0000
H'FFFE4006
16
Timer general register A_2
TGRA_2
R/W
H'FFFF
H'FFFE4008
16, 32
Timer general register B_2
TGRB_2
R/W
H'FFFF
H'FFFE400A
16
Timer counter U_5
TCNTU_5
R/W
H'0000
H'FFFE4080
16, 32
Timer general register U_5
TGRU_5
R/W
H'FFFF
H'FFFE4082
16
Timer control register U_5
TCRU_5
R/W
H'00
H'FFFE4084
8
Timer I/O control register U_5
TIORU_5
R/W
H'00
H'FFFE4086
8
Timer counter V_5
TCNTV_5
R/W
H'0000
H'FFFE4090
16, 32
Timer general register V_5
TGRV_5
R/W
H'FFFF
H'FFFE4092
16
Timer control register V_5
TCRV_5
R/W
H'00
H'FFFE4094
8
Timer I/O control register V_5
TIORV_5
R/W
H'00
H'FFFE4096
8
Timer counter W_5
TCNTW_5
R/W
H'0000
H'FFFE40A0
16, 32
Timer general register W_5
TGRW_5
R/W
H'FFFF
H'FFFE40A2
16
Timer control register W_5
TCRW_5
R/W
H'00
H'FFFE40A4
8
Timer I/O control register W_5
TIORW_5
R/W
H'00
H'FFFE40A6
8
Timer status register_5
TSR_5
R/W
H'00
H'FFFE40B0
8
Timer interrupt enable register_5
TIER_5
R/W
H'00
H'FFFE40B2
8
Timer start register_5
TSTR_5
R/W
H'00
H'FFFE40B4
8
Timer compare match clear register
TCNTCMPCLR R/W
H'00
H'FFFE40B6
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 451 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.1
Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three
(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted
only when TCNT operation is stopped.
Bit:
7
6
5
CCLR[2:0]
Initial value: 0
R/W: R/W
0
R/W
4
3
2
CKEG[1:0]
0
R/W
0
R/W
0
R/W
1
0
TPSC[2:0]
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
CCLR[2:0]
000
R/W
Counter Clear 0 to 2
0
R/W
0
R/W
These bits select the TCNT counter clearing source.
See tables 11.4 and 11.5 for details.
4, 3
CKEG[1:0]
00
R/W
Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. MPφ/4 both edges = MPφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is MPφ/4 or slower. When
MPφ/1 or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
2 to 0
TPSC[2:0]
000
R/W
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 11.6 to 11.10 for details.
[Legend]
x:
Don't care
Page 452 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.4 CCLR0 to CCLR2 (Channels 0, 3, and 4)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3, 4
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture*
0
TCNT cleared by TGRD compare match/input
capture*2
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
1
1
0
1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 11.5 CCLR0 to CCLR2 (Channels 1 and 2)
Channel
Bit 7
Bit 6
Reserved*2 CCLR1
Bit 5
CCLR0
Description
1, 2
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*1
0
1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 453 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.6 TPSC0 to TPSC2 (Channel 0)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
1
1
0
1
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
Table 11.7 TPSC0 to TPSC2 (Channel 1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on Pφ/256
1
Counts on TCNT_2 overflow/underflow
1
1
0
1
Note: This setting is ignored when channel 1 is in phase counting mode.
Page 454 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.8 TPSC0 to TPSC2 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
1
1
0
1
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on Pφ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 11.9 TPSC0 to TPSC2 (Channels 3 and 4)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3, 4
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
0
Internal clock: counts on Pφ/256
1
Internal clock: counts on Pφ/1024
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
1
1
0
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 455 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.10 TPSC1 and TPSC0 (Channel 5)
Channel
Bit 1
TPSC1
Bit 0
TPSC0
Description
5
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
1
Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value
should always be 0.
11.3.2
Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Bit:
Initial value:
R/W:
7
6
5
4
-
BFE
BFB
BFA
0
R
0
R/W
0
R/W
0
R/W
3
2
1
0
MD[3:0]
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
R
Reserved
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
6
BFE
0
R/W
Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
operation
Page 456 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated in a mode other than complementary PWM.
TGRD compare match is generated in complementary
PWM mode. When compare match occurs during the
Tb period in complementary PWM mode, TGFD is set.
Therefore, set the TGIED bit in the timer interrupt
enable register 3/4 (TIER_3/4) to 0.
In channels 1 and 2, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated in a mode other than complementary PWM.
TGRC compare match is generated when in
complementary PWM mode. When compare match for
channel 4 occurs during the Tb period in
complementary PWM mode, TGFC is set. Therefore,
set the TGIEC bit in the timer interrupt enable register 4
(TIER_4) to 0.
In channels 1 and 2, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
3 to 0
MD[3:0]
0000
R/W
Modes 0 to 3
These bits are used to set the timer operating mode.
See table 11.11 for details.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 457 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
Table 11.11 Setting of Operation Mode by Bits MD0 to MD3
Bit 3
MD3
Bit 2
MD2
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Setting prohibited
0
PWM mode 1
1
PWM mode 2*1
0
Phase counting mode 1*2
1
Phase counting mode 2*2
0
Phase counting mode 3*2
1
Phase counting mode 4*2
0
Reset synchronous PWM mode*3
1
Setting prohibited
1
X
Setting prohibited
0
0
Setting prohibited
1
Complementary PWM mode 1 (transmit at crest)*3
0
Complementary PWM mode 2 (transmit at trough)*3
1
Complementary PWM mode 2 (transmit at crest and
trough)*3
1
1
0
1
1
0
1
0
1
[Legend]
X:
Don't care
Notes: 1. PWM mode 2 cannot be set for channels 3 and 4.
2. Phase counting mode cannot be set for channels 0, 3, and 4.
3. Reset synchronous PWM mode, complementary PWM mode can only be set for
channel 3. When channel 3 is set to reset synchronous PWM mode or complementary
PWM mode, the channel 4 settings become ineffective and automatically conform to the
channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or
complementary PWM mode. Reset synchronous PWM mode and complementary PWM
mode cannot be set for channels 0, 1, and 2.
Page 458 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.3.3
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2
has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and
2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5.
TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit:
7
6
5
4
3
IOB[3:0]
Initial value: 0
R/W: R/W
0
R/W
0
R/W
2
0
1
IOA[3:0]
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
IOB[3:0]
0000
R/W
I/O Control B0 to B3
0
R/W
0
R/W
Specify the function of TGRB.
See the following tables.
TIORH_0:
TIOR_1:
TIOR_2:
TIORH_3:
TIORH_4:
3 to 0
IOA[3:0]
0000
R/W
Table 11.12
Table 11.14
Table 11.15
Table 11.16
Table 11.18
I/O Control A0 to A3
Specify the function of TGRA.
See the following tables.
TIORH_0:
TIOR_1:
TIOR_2:
TIORH_3:
TIORH_4:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Table 11.20
Table 11.22
Table 11.23
Table 11.24
Table 11.26
Page 459 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIORL_0, TIORL_3, TIORL_4
Bit:
7
6
5
4
3
IOD[3:0]
Initial value: 0
R/W: R/W
0
R/W
0
R/W
2
0
1
IOC[3:0]
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
IOD[3:0]
0000
R/W
I/O Control D0 to D3
0
R/W
0
R/W
Specify the function of TGRD.
See the following tables.
TIORL_0: Table 11.13
TIORL_3: Table 11.17
TIORL_4: Table 11.19
3 to 0
IOC[3:0]
0000
R/W
I/O Control C0 to C3
Specify the function of TGRC.
See the following tables.
TIORL_0: Table 11.21
TIORL_3: Table 11.25
TIORL_4: Table 11.27
• TIORU_5, TIORV_5, TIORW_5
Bit:
Initial value:
R/W:
7
6
5
-
-
-
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
7 to 5
⎯
All 0
R
4
3
2
1
0
0
R/W
0
R/W
IOC[4:0]
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
4 to 0
IOC[4:0]
00000
R/W
I/O Control C0 to C4
Specify the function of TGRU_5, TGRV_5, and
TGRW_5.
For details, see table 11.28.
Page 460 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.12 TIORH_0 (Channel 0)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_0
Function
0
0
0
0
Output
compare
register
1
TIOC0B Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input capture Input capture at rising edge
register
Input capture at falling edge
1
X
Input capture at both edges
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 461 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.13 TIORL_0 (Channel 0)
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
0
0
0
0
Output
compare
register*2
1
TIOC0D Pin Function
Output retained*1
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
1
1
Input capture Input capture at rising edge
register*2
Input capture at falling edge
1
X
Input capture at both edges
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Page 462 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.14 TIOR_1 (Channel 1)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
0
0
0
0
Output
compare
register
1
TIOC1B Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
1
X
Input capture at both edges
X
X
Input capture at generation of TGRC_0 compare
match/input capture
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 463 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.15 TIOR_2 (Channel 2)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_2
Function
0
0
0
0
Output
compare
register
1
TIOC2B Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
Page 464 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.16 TIORH_3 (Channel 3)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_3
Function
0
0
0
0
Output
compare
register
1
TIOC3B Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 465 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.17 TIORL_3 (Channel 3)
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_3
Function
0
0
0
0
Output
compare
2
register*
1
TIOC3D Pin Function
Output retained*1
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register*2
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Page 466 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.18 TIORH_4 (Channel 4)
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_4
Function
0
0
0
0
Output
compare
register
1
TIOC4B Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 467 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.19 TIORL_4 (Channel 4)
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_4
Function
0
0
0
0
Output
compare
2
register*
1
TIOC4D Pin Function
Output retained*1
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register*2
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Page 468 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.20 TIORH_0 (Channel 0)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_0
Function
0
0
0
0
Output
compare
register
1
TIOC0A Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input capture Input capture at rising edge
register
Input capture at falling edge
1
X
Input capture at both edges
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 469 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.21 TIORL_0 (Channel 0)
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function
0
0
0
0
Output
compare
2
register*
1
TIOC0C Pin Function
Output retained*1
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
1
0
0
1
Input capture Input capture at rising edge
2
register*
Input capture at falling edge
1
X
Input capture at both edges
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Page 470 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.22 TIOR_1 (Channel 1)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
0
0
0
0
Output
compare
register
1
TIOC1A Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
1
X
Input capture at both edges
X
X
Input capture at generation of channel 0/TGRA_0
compare match/input capture
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 471 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.23 TIOR_2 (Channel 2)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_2
Function
0
0
0
0
Output
compare
register
1
TIOC2A Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
0
1
Input capture Input capture at rising edge
register
Input capture at falling edge
X
Input capture at both edges
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
Page 472 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.24 TIORH_3 (Channel 3)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_3
Function
0
0
0
0
Output
compare
register
1
TIOC3A Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 473 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.25 TIORL_3 (Channel 3)
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_3
Function
0
0
0
0
Output
compare
2
register*
1
TIOC3C Pin Function
Output retained*1
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register*2
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Page 474 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.26 TIORH_4 (Channel 4)
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_4
Function
0
0
0
0
Output
compare
register
1
TIOC4A Pin Function
Output retained*
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Note: * After power-on reset, 0 is output until TIOR is set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 475 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.27 TIORL_4 (Channel 4)
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_4
Function
0
0
0
0
Output
compare
2
register*
1
TIOC4C Pin Function
Output retained*1
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
X
0
1
1
Input capture Input capture at rising edge
register*2
Input capture at falling edge
X
Input capture at both edges
0
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Page 476 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5)
Description
Bit 4
IOC4
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
0
0
0
0
0
1
1
1
Compare
Compare match
match register Setting prohibited
1
X
Setting prohibited
X
X
Setting prohibited
1
X
X
X
0
0
0
0
1
1
1
TGRU_5,
TGRV_5, and
TGRW_5
TIC5U, TIC5V, and TIC5W Pin Function
Function
1
X
0
0
Setting prohibited
Input capture
register
Setting prohibited
Input capture at rising edge
0
Input capture at falling edge
1
Input capture at both edges
X
Setting prohibited
0
Setting prohibited
1
Measurement of low pulse width of external input signal
0
Measurement of low pulse width of external input signal
1
Measurement of low pulse width of external input signal
Capture at trough in complementary PWM mode
1
Capture at crest in complementary PWM mode
Capture at crest and trough in complementary PWM
mode
1
0
0
Setting prohibited
1
Measurement of high pulse width of external input
signal
Capture at trough in complementary PWM mode
1
0
Measurement of high pulse width of external input
signal
Capture at crest in complementary PWM mode
1
Measurement of high pulse width of external input
signal
Capture at crest and trough in complementary PWM
mode
[Legend]
X:
Don't care
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 477 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.4
Timer Compare Match Clear Register (TCNTCMPCLR)
TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5,
TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5.
Bit:
Initial value:
R/W:
7
6
5
4
3
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
—
All 0
R
Reserved
2
1
0
CMP
CMP
CMP
CLR5U CLR5V CLR5W
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
2
CMPCLR5U 0
R/W
TCNT Compare Clear 5U
Enables or disables requests to clear TCNTU_5 at
TGRU_5 compare match or input capture.
0: Disables TCNTU_5 to be cleared to H'0000 at
TCNTU_5 and TGRU_5 compare match or input
capture
1: Enables TCNTU_5 to be cleared to H'0000 at
TCNTU_5 and TGRU_5 compare match or input
capture
1
CMPCLR5V 0
R/W
TCNT Compare Clear 5V
Enables or disables requests to clear TCNTV_5 at
TGRV_5 compare match or input capture.
0: Disables TCNTV_5 to be cleared to H'0000 at
TCNTV_5 and TGRV_5 compare match or input
capture
1: Enables TCNTV_5 to be cleared to H'0000 at
TCNTV_5 and TGRV_5 compare match or input
capture
Page 478 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Value
Bit
Bit Name
0
CMPCLR5W 0
R/W
Description
R/W
TCNT Compare Clear 5W
Enables or disables requests to clear TCNTW_5 at
TGRW_5 compare match or input capture.
0: Disables TCNTW_5 to be cleared to H'0000 at
TCNTW_5 and TGRW_5 compare match or input
capture
1: Enables TCNTW_5 to be cleared to H'0000 at
TCNTW_5 and TGRW_5 compare match or input
capture
11.3.5
Timer Interrupt Enable Register (TIER)
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and
one each for channels 1 to 5.
• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4
Bit:
7
6
5
4
3
2
1
0
TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
TTGE
0
R/W
A/D Converter Start Request Enable
Enables or disables generation of A/D converter start
requests by TGRA input capture/compare match.
0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 479 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
6
TTGE2
0
R/W
A/D Converter Start Request Enable 2
Enables or disables generation of A/D converter start
requests by TCNT_4 underflow (trough) in
complementary PWM mode.
In channels 0 to 3, bit 6 is reserved. It is always read as
0 and the write value should always be 0.
0: A/D converter start request generation by TCNT_4
underflow (trough) disabled
1: A/D converter start request generation by TCNT_4
underflow (trough) enabled
5
TCIEU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 3 is reserved. It is always read
as 0 and the write value should always be 0.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Page 480 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0, 3, and 4.
In channels 1 and 2, bit 2 is reserved. It is always read
as 0 and the write value should always be 0.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 481 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIER2_0
Bit:
7
6
5
4
3
2
TTGE2
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Initial value: 0
R/W: R/W
1
0
TGIEF TGIEE
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
TTGE2
0
R/W
A/D Converter Start Request Enable 2
Enables or disables generation of A/D converter start
requests by compare match between TCNT_0 and
TGRE_0.
0: A/D converter start request generation by compare
match between TCNT_0 and TGRE_0 disabled
1: A/D converter start request generation by compare
match between TCNT_0 and TGRE_0 enabled
6 to 2
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
TGIEF
0
R/W
TGR Interrupt Enable F
Enables or disables interrupt requests by compare
match between TCNT_0 and TGRF_0.
0: Interrupt requests (TGIF) by TGFE bit disabled
1: Interrupt requests (TGIF) by TGFE bit enabled
0
TGIEE
0
R/W
TGR Interrupt Enable E
Enables or disables interrupt requests by compare
match between TCNT_0 and TGRE_0.
0: Interrupt requests (TGIE) by TGEE bit disabled
1: Interrupt requests (TGIE) by TGEE bit enabled
Page 482 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIER_5
Bit:
Initial value:
R/W:
7
6
5
4
3
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
—
All 0
R
Reserved
2
1
0
TGIE5U TGIE5V TGIE5W
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
2
TGIE5U
0
R/W
TGR Interrupt Enable 5U
Enables or disables interrupt requests (TGIU_5) by the
CMFU5 bit when the CMFU5 bit in TSR_5 is set to 1.
0: Interrupt requests (TGIU_5) disabled
1: Interrupt requests (TGIU_5) enabled
1
TGIE5V
0
R/W
TGR Interrupt Enable 5V
Enables or disables interrupt requests (TGIV_5) by the
CMFV5 bit when the CMFV5 bit in TSR_5 is set to 1.
0: Interrupt requests (TGIV_5) disabled
1: Interrupt requests (TGIV_5) enabled
0
TGIE5W
0
R/W
TGR Interrupt Enable 5W
Enables or disables interrupt requests (TGIW_5) by the
CMFW5 bit when the CMFW5 bit in TSR_5 is set to 1.
0: Interrupt requests (TGIW_5) disabled
1: Interrupt requests (TGIW_5) enabled
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 483 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.6
Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.
• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
TCFD
-
TCFU
TCFV
TGFD
TGFC
TGFB
TGFA
1
R
1
R
0
0
0
0
0
0
R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
Initial
Value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1 to 4.
In channel 0, bit 7 is reserved. It is always read as 1
and the write value should always be 1.
0: TCNT counts down
1: TCNT counts up
6
—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
5
TCFU
0
R/(W)*1 Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
[Clearing condition]
•
2
When 0 is written to TCFU after reading TCFU = 1*
[Setting condition]
•
Page 484 of 1778
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
4
Bit Name
TCFV
Initial
Value
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
Description
1
R/(W)* Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Clearing condition]
•
When 0 is written to TCFV after reading
2
TCFV = 1*
[Setting condition]
•
3
TGFD
0
When the TCNT value overflows (changes from
H'FFFF to H'0000)
In channel 4, when the TCNT_4 value underflows
(changes from H'0001 to H'0000) in complementary
PWM mode, this flag is also set.
R/(W)*1 Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0, 3, and 4.
Only 0 can be written, for flag clearing. In channels 1
and 2, bit 3 is reserved. It is always read as 0 and the
write value should always be 0.
[Clearing condition]
•
When 0 is written to TGFD after reading
2
TGFD = 1*
•
When DTC is activated by TGID interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
[Setting conditions]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
•
When TCNT = TGRD and TGRD is functioning as
output compare register
•
When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input
capture register
Page 485 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
2
Bit Name
TGFC
Initial
Value
0
R/W
Description
1
R/(W)* Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4.
Only 0 can be written, for flag clearing. In channels 1
and 2, bit 2 is reserved. It is always read as 0 and the
write value should always be 0.
[Clearing condition]
•
When DTC is activated by TGIC interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
•
When 0 is written to TGFC after reading
2
TGFC = 1*
[Setting conditions]
1
TGFB
0
•
When TCNT = TGRC and TGRC is functioning as
output compare register
•
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
R/(W)*1 Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for
flag clearing.
[Clearing condition]
•
When DTC is activated by TGIB interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
•
When 0 is written to TGFB after reading
2
TGFB = 1*
[Setting conditions]
Page 486 of 1778
•
When TCNT = TGRB and TGRB is functioning as
output compare register
•
When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
0
Bit Name
TGFA
Initial
Value
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
Description
1
R/(W)* Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
[Clearing conditions]
•
When DMAC is activated by TGIA interrupt.
•
When DTC is activated by TGIA interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
•
When 0 is written to TGFA after reading
2
TGFA = 1*
[Setting conditions]
•
When TCNT = TGRA and TGRA is functioning as
output compare register
•
When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. After reading 1, when the next flag set is generated before writing 0, the flag will not be
cleared by writing 0. Read 1 again and write 0 in this case.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 487 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR2_0
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
TGFF
TGFE
1
R
1
R
0
R
0
R
0
R
0
R
0
0
R/(W)*1 R/(W)*1
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
—
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
5 to 2
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
TGFF
0
R/(W)*1 Compare Match Flag F
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRF_0.
[Clearing condition]
•
When 0 is written to TGFF after reading
2
TGFF = 1*
[Setting condition]
•
0
TGFE
0
When TCNT_0 = TGRF_0 and TGRF_0 is
functioning as compare register
R/(W)*1 Compare Match Flag E
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRE_0.
[Clearing condition]
•
When 0 is written to TGFE after reading
2
TGFE = 1*
[Setting condition]
•
When TCNT_0 = TGRE_0 and TGRE_0 is
functioning as compare register
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. After reading 1 when the next flag set is generated before writing 0, the flag will not be
cleared by writing 0. Read 1 again and write 0 in this case.
Page 488 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR_5
Bit:
Initial value:
R/W:
2
1
0
7
6
5
4
3
-
-
-
-
-
CMFU5 CMFV5 CMFW5
0
R
0
R
0
R
0
R
0
R
0
0
0
R/(W)*1 R/(W)*1R/(W)*1
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
CMFU5
0
R/(W)*1 Compare Match/Input Capture Flag U5
Status flag that indicates the occurrence of TGRU_5
input capture or compare match.
[Clearing condition]
•
When DTC is activated by TGIU_5 interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
•
When 0 is written to CMFU5 after reading CMFU5 = 1
[Setting conditions]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
•
When TCNTU_5 = TGRU_5 and TGRU_5 is
functioning as output compare register
•
When TCNTU_5 value is transferred to TGRU_5 by
input capture signal and TGRU_5 is functioning as
input capture register
•
When TCNTU_5 value is transferred to TGRU_5 and
TGRU_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
registers U_5, V_5, and W_5 (TIORU_5, TIORV_5,
2
and TIORW_5).*
Page 489 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
1
Bit Name
CMFV5
Initial
Value
0
R/W
Description
1
R/(W)* Compare Match/Input Capture Flag V5
Status flag that indicates the occurrence of TGRV_5 input
capture or compare match.
[Clearing condition]
•
When DTC is activated by TGIV_5 interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
•
When 0 is written to CMFV5 after reading CMFV5 = 1
[Setting conditions]
Page 490 of 1778
•
When TCNTV_5 = TGRV_5 and TGRV_5 is
functioning as output compare register
•
When TCNTV_5 value is transferred to TGRV_5 by
input capture signal and TGRV_5 is functioning as
input capture register
•
When TCNTV_5 value is transferred to TGRV_5 and
TGRV_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
registers U_5, V_5, and W_5 (TIORU_5, TIORV_5,
2
and TIORW_5).*
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
0
Bit Name
CMFW5
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Value
R/W
Description
1
0
R/(W)* Compare Match/Input Capture Flag W5
Status flag that indicates the occurrence of TGRW_5
input capture or compare match. Only 0 can be written to
clear this flag.
[Clearing condition]
•
When DTC is activated by TGIW_5 interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
•
When 0 is written to CMFW5 after reading CMFW5 =
1
[Setting conditions]
•
When TCNTW_5 = TGRW_5 and TGRW_5 is
functioning as output compare register
•
When TCNTW_5 value is transferred to TGRW_5 by
input capture signal and TGRW_5 is functioning as
input capture register
•
When TCNTW_5 value is transferred to TGRW_5 and
TGRW_5 is functioning as a register for measuring
2
the pulse width of the external input signal. *
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Timing for transfer is set by the IOC bit in the timer I/O control register U_5/V_5/W_5
(TIORU_5/V_5/W_5).
11.3.7
Timer Buffer Operation Transfer Mode Register (TBTM)
The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring
data from the buffer register to the timer general register in PWM mode. The MTU2 has three
TBTM registers, one each for channels 0, 3, and 4.
Bit:
Initial value:
R/W:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
7
6
5
4
3
2
1
0
-
-
-
-
-
TTSE
TTSB
TTSA
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
Page 491 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
TTSE
0
R/W
Timing Select E
Specifies the timing for transferring data from TGRF_0
to TGRE_0 when they are used together for buffer
operation.
In channels 3 and 4, bit 2 is reserved. It is always read
as 0 and the write value should always be 0. When
channel 0 is used in a mode other than PWM mode, do
not set this bit to 1.
0: When compare match E occurs in channel 0
1: When TCNT_0 is cleared
1
TTSB
0
R/W
Timing Select B
Specifies the timing for transferring data from TGRD to
TGRB in each channel when they are used together for
buffer operation. When the channel is used in a mode
other than PWM mode, do not set this bit to 1.
0: When compare match B occurs in each channel
1: When TCNT is cleared in each channel
0
TTSA
0
R/W
Timing Select A
Specifies the timing for transferring data from TGRC to
TGRA in each channel when they are used together for
buffer operation. When the channel is used in a mode
other than PWM mode, do not set this bit to 1.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
Page 492 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.3.8
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer Input Capture Control Register (TICCR)
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
I2BE
I2AE
I1BE
I1AE
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
I2BE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
input capture conditions
1: Includes the TIOC2B pin in the TGRB_1 input
capture conditions
2
I2AE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC2A pin in the
TGRA_1 input capture conditions.
0: Does not include the TIOC2A pin in the TGRA_1
input capture conditions
1: Includes the TIOC2A pin in the TGRA_1 input
capture conditions
1
I1BE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC1B pin in the
TGRB_2 input capture conditions.
0: Does not include the TIOC1B pin in the TGRB_2
input capture conditions
1: Includes the TIOC1B pin in the TGRB_2 input
capture conditions
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 493 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
0
I1AE
0
R/W
Input Capture Enable
Specifies whether to include the TIOC1A pin in the
TGRA_2 input capture conditions.
0: Does not include the TIOC1A pin in the TGRA_2
input capture conditions
1: Includes the TIOC1A pin in the TGRA_2 input
capture conditions
11.3.9
Timer Synchronous Clear Register S (TSYCRS)
TSYCRS is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and
TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCRS in
channel 3 but the MTU2 has no TSYCRS.
Bit:
7
6
5
4
3
2
1
0
CE0A
CE0B
CE0C
CE0D
CE1A
CE1B
CE2A
CE2B
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
CE0A
0
R/W
Clear Enable 0A
Enables or disables counter clearing when the TGFA
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_0
1: Enables counter clearing by the TGFA flag in TSR_0
6
CE0B
0
R/W
Clear Enable 0B
Enables or disables counter clearing when the TGFB
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_0
1: Enables counter clearing by the TGFB flag in TSR_0
Page 494 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
5
CE0C
0
R/W
Clear Enable 0C
Enables or disables counter clearing when the TGFC
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFC flag in TSR_0
1: Enables counter clearing by the TGFC flag in TSR_0
4
CE0D
0
R/W
Clear Enable 0D
Enables or disables counter clearing when the TGFD
flag of TSR_0 in the MTU2 is set.
0: Disables counter clearing by the TGFD flag in TSR_0
1: Enables counter clearing by the TGFD flag in TSR_0
3
CE1A
0
R/W
Clear Enable 1A
Enables or disables counter clearing when the TGFA
flag of TSR_1 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_1
1: Enables counter clearing by the TGFA flag in TSR_1
2
CE1B
0
R/W
Clear Enable 1B
Enables or disables counter clearing when the TGFB
flag of TSR_1 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_1
1: Enables counter clearing by the TGFB flag in TSR_1
1
CE2A
0
R/W
Clear Enable 2A
Enables or disables counter clearing when the TGFA
flag of TSR_2 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_2
1: Enables counter clearing by the TGFA flag in TSR_2
0
CE2B
0
R/W
Clear Enable 2B
Enables or disables counter clearing when the TGFB
flag of TSR_2 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_2
1: Enables counter clearing by the TGFB flag in TSR_2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 495 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.10 Timer A/D Converter Start Request Control Register (TADCR)
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests
and specifies whether to link A/D converter start requests with interrupt skipping operation. The
MTU2 has one TADCR in channel 4.
Bit: 15
14
BF[1:0]
Initial value: 0
R/W: R/W
0
R/W
13
12
11
10
9
8
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
7
6
5
4
3
2
0
1
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
0
R/W
0*
R/W
0
R/W
0*
R/W
0*
R/W
0*
R/W
0*
R/W
0*
R/W
Note: * Do not set to 1 when complementary PWM mode is not selected.
Bit
Bit Name
Initial
Value
R/W
Description
15, 14
BF[1:0]
00
R/W
TADCOBRA_4/TADCOBRB_4 Transfer Timing Select
Select the timing for transferring data from
TADCOBRA_4 and TADCOBRB_4 to TADCORA_4
and TADCORB_4.
For details, see table 11.29.
13 to 8 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
UT4AE
0
R/W
Up-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 up-count operation.
0: A/D converter start requests (TRG4AN) disabled
during TCNT_4 up-count operation
1: A/D converter start requests (TRG4AN) enabled
during TCNT_4 up-count operation
6
DT4AE
0*
R/W
Down-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 down-count operation.
0: A/D converter start requests (TRG4AN) disabled
during TCNT_4 down-count operation
1: A/D converter start requests (TRG4AN) enabled
during TCNT_4 down-count operation
Page 496 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
5
UT4BE
0
R/W
Up-Count TRG4BN Enable
Enables or disables A/D converter start requests
(TRG4BN) during TCNT_4 up-count operation.
0: A/D converter start requests (TRG4BN) disabled
during TCNT_4 up-count operation
1: A/D converter start requests (TRG4BN) enabled
during TCNT_4 up-count operation
4
DT4BE
0*
R/W
Down-Count TRG4BN Enable
Enables or disables A/D converter start requests
(TRG4BN) during TCNT_4 down-count operation.
0: A/D converter start requests (TRG4BN) disabled
during TCNT_4 down-count operation
1: A/D converter start requests (TRG4BN) enabled
during TCNT_4 down-count operation
3
ITA3AE
0*
R/W
TGIA_3 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4AN) with TGIA_3 interrupt skipping operation.
0: Does not link with TGIA_3 interrupt skipping
1: Links with TGIA_3 interrupt skipping
2
ITA4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4AN) with TCIV_4 interrupt skipping operation.
0: Does not link with TCIV_4 interrupt skipping
1: Links with TCIV_4 interrupt skipping
1
ITB3AE
0*
R/W
TGIA_3 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4BN) with TGIA_3 interrupt skipping operation.
0: Does not link with TGIA_3 interrupt skipping
1: Links with TGIA_3 interrupt skipping
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 497 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
0
ITB4VE
0*
R/W
TCIV_4 Interrupt Skipping Link Enable
Select whether to link A/D converter start requests
(TRG4BN) with TCIV_4 interrupt skipping operation.
0: Does not link with TCIV_4 interrupt skipping
1: Links with TCIV_4 interrupt skipping
Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits.
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR
and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with
interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the
timer A/D converter start request control register (TADCR) to 0).
3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D
converter start requests will not be issued.
* Do not set to 1 when complementary PWM mode is not selected.
Table 11.29 Setting of Transfer Timing by Bits BF1 and BF0
Bit 7
Bit 6
BF1
BF0
Description
0
0
Does not transfer data from the cycle set buffer register to the cycle
set register.
0
1
Transfers data from the cycle set buffer register to the cycle set
register at the crest of the TCNT_4 count.*1
1
0
Transfers data from the cycle set buffer register to the cycle set
register at the trough of the TCNT_4 count.*2
1
1
Transfers data from the cycle set buffer register to the cycle set
register at the crest and trough of the TCNT_4 count.*2
Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the
crest of the TCNT_4 count is reached in complementary PWM mode, when compare
match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or
when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or
normal operation mode.
2. These settings are prohibited when complementary PWM mode is not selected.
Page 498 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and
TADCORB_4)
TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count
reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request
will be issued.
TADCORA_4 and TADCORB_4 are initialized to H'FFFF.
Bit: 15
Initial value: 1
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4
and TADCOBRB_4)
TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or
trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and
TADCORB_4, respectively.
TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF.
Bit: 15
Initial value: 1
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 499 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.13 Timer Counter (TCNT)
The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters,
one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5.
The TCNT counters are initialized to H'0000 by a reset.
Bit: 15
Initial value: 0
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
11.3.14 Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for
channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5.
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers.
TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers.
TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD.
TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the
TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for
operation as a buffer register. TGR buffer register combination is TGRE and TGRF.
TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse
width measurement registers.
Bit: 15
Initial value: 1
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits.
TGR registers are initialized to H'FFFF.
Page 500 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.15 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0
to 4.
TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5,
TCNTV_5, and TCNTW_5 for channel 5.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
• TSTR
Bit:
7
6
5
4
3
2
1
0
CST4
CST3
-
-
-
CST2
CST1
CST0
Initial value: 0
R/W: R/W
0
R/W
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
CST4
0
R/W
Counter Start 4 and 3
6
CST3
0
R/W
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_4 and TCNT_3 count operation is stopped
1: TCNT_4 and TCNT_3 performs count operation
5 to 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 501 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
2
CST2
0
R/W
Counter Start 2 to 0
1
CST1
0
R/W
These bits select operation or stoppage for TCNT.
0
CST0
0
R/W
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_2 to TCNT_0 count operation is stopped
1: TCNT_2 to TCNT_0 performs count operation
• TSTR_5
Bit :
Initial value:
R/W:
7
6
5
4
3
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
7 to 3
—
All 0
R
2
1
0
CSTU5 CSTV5 CSTW5
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
2
CSTU5
0
R/W
Counter Start U5
Selects operation or stoppage for TCNTU_5.
0: TCNTU_5 count operation is stopped
1: TCNTU_5 performs count operation
1
CSTV5
0
R/W
Counter Start V5
Selects operation or stoppage for TCNTV_5.
0: TCNTV_5 count operation is stopped
1: TCNTV_5 performs count operation
0
CSTW5
0
R/W
Counter Start W5
Selects operation or stoppage for TCNTW_5.
0: TCNTW_5 count operation is stopped
1: TCNTW_5 performs count operation
Page 502 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.16 Timer Synchronous Register (TSYR)
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Bit:
7
6
SYNC4 SYNC3
Initial value: 0
R/W: R/W
0
R/W
5
4
3
-
-
-
0
R
0
R
0
R
2
1
0
SYNC2 SYNC1 SYNC0
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
SYNC4
0
R/W
Timer Synchronous operation 4 and 3
6
SYNC3
0
R/W
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_4 and TCNT_3 operate independently (TCNT
presetting/clearing is unrelated to other channels)
1: TCNT_4 and TCNT_3 performs synchronous
operation
TCNT synchronous presetting/synchronous clearing
is possible
5 to 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 503 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
2
SYNC2
0
R/W
Timer Synchronous operation 2 to 0
1
SYNC1
0
R/W
0
SYNC0
0
R/W
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently (TCNT
presetting /clearing is unrelated to other channels)
1: TCNT_2 to TCNT_0 performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
Page 504 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.17 Timer Counter Synchronous Start Register (TCSYSTR)
TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and
MTU2S counters. Note that the MTU2S does not have TCSYSTR.
Bit:
6
5
4
3
2
SCH1
SCH2
SCH3
SCH4
-
SCH3S SCH4S
0
R
0
0
R/(W)* R/(W)*
Initial value: 0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
1
0
7
SCH0
Note: * Only 1 can be written to set the register.
Bit
Bit Name
Initial
Value
R/W
7
SCH0
0
R/(W)* Synchronous Start
Description
Controls synchronous start of TCNT_0 in the MTU2.
0: Does not specify synchronous start for TCNT_0 in
the MTU2
1: Specifies synchronous start for TCNT_0 in the MTU2
[Clearing condition]
•
6
SCH1
0
When 1 is set to the CST0 bit of TSTR in MTU2
while SCH0 = 1
R/(W)* Synchronous Start
Controls synchronous start of TCNT_1 in the MTU2.
0: Does not specify synchronous start for TCNT_1 in
the MTU2
1: Specifies synchronous start for TCNT_1 in the MTU2
[Clearing condition]
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
When 1 is set to the CST1 bit of TSTR in MTU2
while SCH1 = 1
Page 505 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
5
SCH2
0
R/(W)* Synchronous Start
Description
Controls synchronous start of TCNT_2 in the MTU2.
0: Does not specify synchronous start for TCNT_2 in
the MTU2
1: Specifies synchronous start for TCNT_2 in the MTU2
[Clearing condition]
•
4
SCH3
0
When 1 is set to the CST2 bit of TSTR in MTU2
while SCH2 = 1
R/(W)* Synchronous Start
Controls synchronous start of TCNT_3 in the MTU2.
0: Does not specify synchronous start for TCNT_3 in
the MTU2
1: Specifies synchronous start for TCNT_3 in the MTU2
[Clearing condition]
•
3
SCH4
0
When 1 is set to the CST3 bit of TSTR in MTU2
while SCH3 = 1
R/(W)* Synchronous Start
Controls synchronous start of TCNT_4 in the MTU2.
0: Does not specify synchronous start for TCNT_4 in
the MTU2
1: Specifies synchronous start for TCNT_4 in the MTU2
[Clearing condition]
•
2
—
0
R
When 1 is set to the CST4 bit of TSTR in MTU2
while SCH4 = 1
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 506 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
1
SCH3S
0
R/(W)* Synchronous Start
Description
Controls synchronous start of TCNT_3S in the MTU2S.
0: Does not specify synchronous start for TCNT_3S in
the MTU2S
1: Specifies synchronous start for TCNT_3S in the
MTU2S
[Clearing condition]
•
0
SCH4S
0
When 1 is set to the CST3 bit of TSTRS in MTU2S
while SCH3S = 1
R/(W)* Synchronous Start
Controls synchronous start of TCNT_4S in the MTU2S.
0: Does not specify synchronous start for TCNT_4S in
the MTU2S
1: Specifies synchronous start for TCNT_4S in the
MTU2S
[Clearing condition]
•
When 1 is set to the CST4 bit of TSTRS in MTU2S
while SCH4S = 1
Note: Only 1 can be written to set the register.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 507 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.18 Timer Read/Write Enable Register (TRWER)
TRWER is an 8-bit readable/writable register that enables or disables access to the registers and
counters which have write-protection capability against accidental modification in channels 3 and
4.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
RWE
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R/W
Bit
Bit Name
Initial
Value
R/W
7 to 1
—
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
0
RWE
1
R/W
Read/Write Enable
Enables or disables access to the registers which have
write-protection capability against accidental
modification.
0: Disables read/write access to the registers
1: Enables read/write access to the registers
[Clearing condition]
•
When 0 is written to the RWE bit after reading
RWE = 1
• Registers and counters having write-protection capability against accidental modification
22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3,
TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1,
TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4.
Page 508 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.19 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables/disables output settings for output pins
TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly
if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and
CH4.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
OE4D
OE4C
OE3D
OE4B
OE4A
OE3B
1
R
1
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
—
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
5
OE4D
0
R/W
Master Enable TIOC4D
This bit enables/disables the TIOC4D pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
4
OE4C
0
R/W
Master Enable TIOC4C
This bit enables/disables the TIOC4C pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
3
OE3D
0
R/W
Master Enable TIOC3D
This bit enables/disables the TIOC3D pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
2
OE4B
0
R/W
Master Enable TIOC4B
This bit enables/disables the TIOC4B pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
1
OE4A
0
R/W
Master Enable TIOC4A
This bit enables/disables the TIOC4A pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 509 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
0
OE3B
0
R/W
Master Enable TIOC3B
This bit enables/disables the TIOC3B pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
Note:
*
The inactive level is determined by the settings in timer output control registers 1 and 2
(TOCR1 and TOCR2). For details, refer to section 11.3.20, Timer Output Control
Register 1 (TOCR1), and section 11.3.21, Timer Output Control Register 2 (TOCR2).
Set these bits to 1 to enable MTU2 output in other than complementary PWM or resetsynchronized PWM mode. When these bits are set to 0, low level is output.
11.3.20 Timer Output Control Register 1 (TOCR1)
TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle
output in complementary PWM mode/reset synchronized PWM mode, and controls output level
inversion of PWM output.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
PSYE
-
-
TOCL
TOCS
OLSN
OLSP
0
R
0
R/W
0
R
0
R
0
0
R/(W)* R/W
0
R/W
0
R/W
Note: * This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit.
Bit
Bit Name
Initial
value
R/W
Description
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
PSYE
0
R/W
PWM Synchronous Output Enable
This bit selects the enable/disable of toggle output
synchronized with the PWM period.
0: Toggle output is disabled
1: Toggle output is enabled
5, 4
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 510 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
value
R/W
3
TOCL
0
R/(W)* TOC Register Write Protection*1
Description
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
enabled
1: Write access to the TOCS, OLSN, and OLSP bits is
disabled
2
TOCS
0
R/W
TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
1
OLSN
0
R/W
Output Level Select N*2
This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode.
See table 11.30.
0
OLSP
0
R/W
Output Level Select P*2
This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode.
See table 11.31.
Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
control.
2. Clearing the TOCS0 bit to 0 makes this bit setting valid.
Table 11.30 Output Level Select Function
Bit 1
Function
Compare Match Output
OLSN
Initial Output
Active Level
Up Count
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the
dead time after count start.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 511 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.31 Output Level Select Function
Bit 0
Function
Compare Match Output
OLSP
Initial Output
Active Level
Up Count
0
High level
Low level
Low level
High level
1
Low level
High level
High level
Low level
Down Count
Figure 11.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1,
OLSP = 1.
TCNT_3, and
TCNT_4 values
TGRA_3
TCNT_3
TCNT_4
TGRA_4
TDDR
H'0000
Time
Positive
phase output
Initial
output
Reverse
phase output
Initial
output
Active
level
Compare match
output (up count)
Active level
Compare match
output (down count)
Compare match
output (down count)
Compare match
output (up count)
Active level
Figure 11.2 Complementary PWM Mode Output Level Example
Page 512 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.21 Timer Output Control Register 2 (TOCR2)
TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output
in complementary PWM mode and reset-synchronized PWM mode.
Bit:
7
6
BF[1:0]
Initial value: 0
R/W: R/W
0
R/W
5
4
3
2
1
0
OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
value
R/W
Description
7, 6
BF[1:0]
00
R/W
TOLBR Buffer Transfer Timing Select
These bits select the timing for transferring data from
TOLBR to TOCR2.
For details, see table 11.32.
5
OLS3N
0
R/W
Output Level Select 3N*
This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode.
See table 11.33.
4
OLS3P
0
R/W
Output Level Select 3P*
This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode.
See table 11.34.
3
OLS2N
0
R/W
Output Level Select 2N*
This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode.
See table 11.35.
2
OLS2P
0
R/W
Output Level Select 2P*
This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode.
See table 11.36.
1
OLS1N
0
R/W
Output Level Select 1N*
This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode.
See table 11.37.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 513 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
value
R/W
Description
0
OLS1P
0
R/W
Output Level Select 1P*
This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode.
See table 11.38.
Note:
*
Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid.
Table 11.32 Setting of Bits BF1 and BF0
Bit 7
Bit 6
Description
BF1
BF0
Complementary PWM Mode
0
0
Does not transfer data from the
Does not transfer data from the
buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2.
0
1
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest of the TCNT_4 count.
Transfers data from the buffer
register (TOLBR) to TOCR2 when
TCNT_3/TCNT_4 is cleared
1
0
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
trough of the TCNT_4 count.
Setting prohibited
1
1
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest and trough of the TCNT_4
count.
Setting prohibited
Reset-Synchronized PWM Mode
Table 11.33 TIOC4D Output Level Select Function
Bit 5
Function
Compare Match Output
OLS3N
Initial Output
Active Level
Up Count
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of
the dead time after count start.
Page 514 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.34 TIOC4B Output Level Select Function
Bit 4
Function
Compare Match Output
OLS3P
Initial Output
Active Level
0
High level
Low level
Low level
High level
1
Low level
High level
High level
Low level
Up Count
Down Count
Table 11.35 TIOC4C Output Level Select Function
Bit 3
Function
Compare Match Output
OLS2N
Initial Output
Active Level
Up Count
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of
the dead time after count start.
Table 11.36 TIOC4A Output Level Select Function
Bit 2
Function
Compare Match Output
OLS2P
Initial Output
Active Level
Up Count
Down Count
0
High level
Low level
Low level
High level
1
Low level
High level
High level
Low level
Table 11.37 TIOC3D Output Level Select Function
Bit 1
Function
Compare Match Output
OLS1N
Initial Output
Active Level
Up Count
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of
the dead time after count start.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 515 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.38 TIOC3B Output Level Select Function
Bit 0
Function
Compare Match Output
OLS1P
Initial Output
Active Level
0
High level
Low level
Low level
High level
1
Low level
High level
High level
Low level
Up Count
Down Count
11.3.22 Timer Output Level Buffer Register (TOLBR)
TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies
the PWM output level in complementary PWM mode and reset-synchronized PWM mode.
Bit:
Initial value:
R/W:
7
6
-
-
0
R
0
R
5
4
3
2
1
0
OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
value
R/W
Description
7, 6
—
All 0
R
Reserved
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
5
OLS3N
0
R/W
Specifies the buffer value to be transferred to the
OLS3N bit in TOCR2.
4
OLS3P
0
R/W
Specifies the buffer value to be transferred to the
OLS3P bit in TOCR2.
3
OLS2N
0
R/W
Specifies the buffer value to be transferred to the
OLS2N bit in TOCR2.
2
OLS2P
0
R/W
Specifies the buffer value to be transferred to the
OLS2P bit in TOCR2.
1
OLS1N
0
R/W
Specifies the buffer value to be transferred to the
OLS1N bit in TOCR2.
0
OLS1P
0
R/W
Specifies the buffer value to be transferred to the
OLS1P bit in TOCR2.
Page 516 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 11.3 shows an example of the PWM output level setting procedure in buffer operation.
Set bit TOCS
[1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting.
[1]
[2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer
transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P
to specify the PWM output levels.
Set TOCR2
[2]
[3] The TOLBR initial setting must be the same value as specified in
bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
Set TOLBR
[3]
Figure 11.3 PWM Output Level Setting Procedure in Buffer Operation
11.3.23 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
BDC
N
P
FB
WF
VF
UF
1
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
value
R/W
Description
7
—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
6
BDC
0
R/W
Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 517 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
value
R/W
Description
5
N
0
R/W
Reverse Phase Output (N) Control
This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
4
P
0
R/W
Positive Phase Output (P) Control
This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are
output.
0: Level output
1: Reset synchronized PWM/complementary PWM
output
3
FB
0
R/W
External Feedback Signal Enable
This bit selects whether the switching of the output of
the positive/reverse phase is carried out automatically
with the MTU2/channel 0 TGRA, TGRB, TGRC input
capture signals or by writing 0 or 1 to bits 2 to 0 in
TGCR.
0: Output switching is external input (Input sources are
channel 0 TGRA, TGRB, TGRC input capture signal)
1: Output switching is carried out by software (setting
values of UF, VF, and WF in TGCR).
2
WF
0
R/W
Output Phase Switch 2 to 0
1
VF
0
R/W
0
UF
0
R/W
These bits set the positive phase/negative phase output
phase on or off state. The setting of these bits is valid
only when the FB bit in this register is set to 1. In this
case, the setting of bits 2 to 0 is a substitute for external
input. See table 11.39.
Note: When the BDC bit is set to 1 in the MTU2S, do not set the FB bit to 0.
Page 518 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.39 Output level Select Function
Function
Bit 2
Bit 1
Bit 0
TIOC3B
TIOC4A
TIOC4B
TIOC3D
TIOC4C
TIOC4D
WF
VF
UF
U Phase
V Phase
W Phase U Phase
V Phase
W Phase
0
0
1
1
0
1
0
OFF
OFF
OFF
OFF
OFF
OFF
1
ON
OFF
OFF
OFF
OFF
ON
0
OFF
ON
OFF
ON
OFF
OFF
1
OFF
ON
OFF
OFF
OFF
ON
0
OFF
OFF
ON
OFF
ON
OFF
1
ON
OFF
OFF
OFF
ON
OFF
0
OFF
OFF
ON
ON
OFF
OFF
1
OFF
OFF
OFF
OFF
OFF
OFF
11.3.24 Timer Subcounter (TCNTS)
TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode.
The initial value of TCNTS is H'0000.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
R/W: R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Note:
Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 519 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.25 Timer Dead Time Data Register (TDDR)
TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3
and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and
TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the
TCNT_3 counter and the count operation starts.
The initial value of TDDR is H'FFFF.
Bit: 15
Initial value: 1
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
11.3.26 Timer Cycle Data Register (TCDR)
TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync
value as the TCDR register value. This register is constantly compared with the TCNTS counter in
complementary PWM mode, and when a match occurs, the TCNTS counter switches direction
(decrement to increment).
The initial value of TCDR is H'FFFF.
Bit: 15
Initial value: 1
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.
Page 520 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.27 Timer Cycle Buffer Register (TCBR)
TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer
register for the TCDR register. The TCBR register values are transferred to the TCDR register
with the transfer timing set in the TMDR register.
Bit: 15
Initial value: 1
R/W: R/W
Note:
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
11.3.28 Timer Interrupt Skipping Set Register (TITCR)
TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and
specifies the interrupt skipping count. The MTU2 has one TITCR.
Bit:
7
6
T3AEN
Initial value: 0
R/W: R/W
5
4
3ACOR[2:0]
0
R/W
0
R/W
3
2
T4VEN
0
R/W
0
R/W
Bit
Bit Name
Initial
value
R/W
Description
7
T3AEN
0
R/W
T3AEN
0
1
4VCOR[2:0]
0
R/W
0
R/W
0
R/W
Enables or disables TGIA_3 interrupt skipping.
0: TGIA_3 interrupt skipping disabled
1: TGIA_3 interrupt skipping enabled
6 to 4
3ACOR[2:0] 000
R/W
These bits specify the TGIA_3 interrupt skipping count
within the range from 0 to 7.*
For details, see table 11.40.
3
T4VEN
0
R/W
T4VEN
Enables or disables TCIV_4 interrupt skipping.
0: TCIV_4 interrupt skipping disabled
1: TCIV_4 interrupt skipping enabled
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 521 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
value
Bit
Bit Name
2 to 0
4VCOR[2:0] 000
R/W
Description
R/W
These bits specify the TCIV_4 interrupt skipping count
within the range from 0 to 7.*
For details, see table 11.41.
Note:
*
When 0 is specified for the interrupt skipping count, no interrupt skipping will be
performed. Before changing the interrupt skipping count, be sure to clear the T3AEN
and T4VEN bits to 0 to clear the skipping counter (TICNT).
Table 11.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0
Bit 6
Bit 5
Bit 4
3ACOR2
3ACOR1
3ACOR0
Description
0
0
0
Does not skip TGIA_3 interrupts.
0
0
1
Sets the TGIA_3 interrupt skipping count to 1.
0
1
0
Sets the TGIA_3 interrupt skipping count to 2.
0
1
1
Sets the TGIA_3 interrupt skipping count to 3.
1
0
0
Sets the TGIA_3 interrupt skipping count to 4.
1
0
1
Sets the TGIA_3 interrupt skipping count to 5.
1
1
0
Sets the TGIA_3 interrupt skipping count to 6.
1
1
1
Sets the TGIA_3 interrupt skipping count to 7.
Table 11.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0
Bit 2
Bit 1
Bit 0
4VCOR2
4VCOR1
4VCOR0
Description
0
0
0
Does not skip TCIV_4 interrupts.
0
0
1
Sets the TCIV_4 interrupt skipping count to 1.
0
1
0
Sets the TCIV_4 interrupt skipping count to 2.
0
1
1
Sets the TCIV_4 interrupt skipping count to 3.
1
0
0
Sets the TCIV_4 interrupt skipping count to 4.
1
0
1
Sets the TCIV_4 interrupt skipping count to 5.
1
1
0
Sets the TCIV_4 interrupt skipping count to 6.
1
1
1
Sets the TCIV_4 interrupt skipping count to 7.
Page 522 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.29 Timer Interrupt Skipping Counter (TITCNT)
TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains its
value even after stopping the count operation of TCNT_3 and TCNT_4.
Bit:
7
6
-
Initial value:
R/W:
5
4
3ACNT[2:0]
0
R
0
R
0
R
3
2
-
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
R
Reserved
0
R
1
0
4VCNT[2:0]
0
R
0
R
0
R
This bit is always read as 0.
6 to 4
3ACNT[2:0]
000
R
TGIA_3 Interrupt Counter
While the T3AEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TGIA_3 interrupt
occurs.
[Clearing conditions]
3
—
0
R
•
When the 3ACNT2 to 3ACNT0 value in TITCNT
matches the 3ACOR2 to 3ACOR0 value in TITCR
•
When the T3AEN bit in TITCR is cleared to 0
•
When the 3ACOR2 to 3ACOR0 bits in TITCR are
cleared to 0
Reserved
This bit is always read as 0.
2 to 0
4VCNT[2:0]
000
R
TCIV_4 Interrupt Counter
While the T4VEN bit in TITCR is set to 1, the count in
these bits is incremented every time a TCIV_4 interrupt
occurs.
[Clearing conditions]
•
When the 4VCNT2 to 4VCNT0 value in TITCNT
matches the 4VCOR2 to 4VCOR2 value in TITCR
•
When the T4VEN bit in TITCR is cleared to 0
•
When the 4VCOR2 to 4VCOR2 bits in TITCR are
cleared to 0
Note: To clear the TITCNT, clear the bits T3AEN and T4VEN in TITCR to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 523 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.30 Timer Buffer Transfer Set Register (TBTER)
TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer
registers* used in complementary PWM mode to the temporary registers and specifies whether to
link the transfer with interrupt skipping operation. The MTU2 has one TBTER.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 2
—
All 0
R
Reserved
1
0
BTE[1:0]
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
1, 0
BTE[1:0]
00
R/W
These bits enable or disable transfer from the buffer
registers* used in complementary PWM mode to the
temporary registers and specify whether to link the
transfer with interrupt skipping operation.
For details, see table 11.42.
Note:
*
Applicable buffer registers:
TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR
Page 524 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.42 Setting of Bits BTE1 and BTE0
Bit 1
Bit 0
BTE1
BTE0
Description
0
0
Enables transfer from the buffer registers to the temporary registers*1
and does not link the transfer with interrupt skipping operation.
0
1
Disables transfer from the buffer registers to the temporary registers.
1
0
Links transfer from the buffer registers to the temporary registers with
interrupt skipping operation.*2
1
Setting prohibited
1
Note:
1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer
to section 11.4.8, Complementary PWM Mode.
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the
timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer
transfer will not be performed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 525 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.31 Timer Dead Time Enable Register (TDER)
TDER is an 8-bit readable/writable register that controls dead time generation in complementary
PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT
stops.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
TDER
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R/(W)
Bit
Bit Name
Initial
Value
R/W
7 to 1
—
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
0
TDER
1
R/(W)
Dead Time Enable
Specifies whether to generate dead time.
0: Does not generate dead time
1: Generates dead time*
[Clearing condition]
•
Note:
*
When 0 is written to TDER after reading TDER = 1
TDDR must be set to 1 or a larger value.
Page 526 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.32 Timer Waveform Control Register (TWCR)
TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter
clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to
clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be
modified only while TCNT stops.
Bit:
7
6
5
4
3
2
1
0
CCE
-
-
-
-
-
SCC
WRE
0
R
0
R
0
R
0
R
0
R
Initial value: 0*
R/W: R/(W)
0
0
R/(W) R/(W)
Note: * Do not set to 1 when complementary PWM mode is not selected.
Bit
Bit Name
Initial
Value
R/W
Description
7
CCE
0*
R/(W)
Compare Match Clear Enable
Specifies whether to clear counters at TGRA_3
compare match in complementary PWM mode.
0: Does not clear counters at TGRA_3 compare match
1: Clears counters at TGRA_3 compare match
[Setting condition]
•
6 to 2
—
All 0
R
When 1 is written to CCE after reading CCE = 0
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 527 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
1
SCC
0
R/(W)
Synchronous Clearing Control
Specifies whether to clear TCNT_3 and TCNT_4 in the
MTU2S when synchronous counter clearing between
the MTU2 and MTU2S occurs in complementary PWM
mode.
When using this control, place the MTU2S in
complementary PWM mode.
When modifying the SCC bit while the counters are
operating, do not modify the CCE or WRE bits.
Counter clearing synchronized with the MTU2 is
disabled by the SCC bit setting only when synchronous
clearing occurs outside the Tb interval at the trough.
When synchronous clearing occurs in the Tb interval at
the trough including the period immediately after
TCNT_3 and TCNT_4 start operation, TCNT_3 and
TCNT_4 in the MTU2S are cleared.
For the Tb interval at the trough in complementary
PWM mode, see figure 11.40.
In the MTU2, this bit is reserved. It is always read as 0
and the write value should always be 0.
0: Enables clearing of TCNT_3 and TCNT_4 in the
MTU2S by MTU2-MTU2S synchronous clearing
operation
1: Disables clearing of TCNT_3 and TCNT_4 in the
MTU2S by MTU2-MTU2S synchronous clearing
operation
[Setting condition]
•
Page 528 of 1778
When 1 is written to SCC after reading SCC = 0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
Bit Name
Initial
Value
R/W
Description
0
WRE
0
R/(W)
Initial Output Suppression Enable
Selects the waveform output when synchronous
counter clearing occurs in complementary PWM mode.
The initial output is suppressed only when synchronous
clearing occurs within the Tb interval at the trough in
complementary PWM mode. When synchronous
clearing occurs outside this interval, the initial value
specified in TOCR is output regardless of the WRE bit
setting. The initial value is also output when
synchronous clearing occurs in the Tb interval at the
trough immediately after TCNT_3 and TCNT_4 start
operation.
For the Tb interval at the trough in complementary
PWM mode, see figure 11.40.
0: Outputs the initial value specified in TOCR
1: Suppresses initial output
[Setting condition]
•
Note:
*
When 1 is written to WRE after reading WRE = 0
Do not set to 1 when complementary PWM mode is not selected.
11.3.33 Bus Master Interface
The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle
buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR),
timer A/D converter start request control register (TADCR), timer A/D converter start request
cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers
(TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units.
All registers other than the above registers are 8-bit registers. These are connected to the CPU by a
16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 529 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4
Operation
11.4.1
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, cycle counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Always select MTU2 external pins set function using the pin function controller (PFC).
(1)
Counter Operation
When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set
to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a
free-running counter, periodic counter, for example.
(a)
Example of Count Operation Setting Procedure
Figure 11.4 shows an example of the count operation setting procedure.
[1] Select the counter clock
with bits TPSC2 to TPSC0
in TCR. At the same time,
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Select counter clearing
source
[2]
Select output compare
register
[3]
Set period
[4]
Start count operation
[5]
[2] For periodic counter
operation, select the TGR
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
Free-running counter
Periodic counter
[3] Designate the TGR
selected in [2] as an output
compare register by means
of TIOR.
[4] Set the periodic counter
cycle in the TGR selected
in [2].
Start count operation
[5]
[5] Set the CST bit in TSTR to
1 to start the counter
operation.
Figure 11.4 Example of Counter Operation Setting Procedure
Page 530 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Free-Running Count Operation and Periodic Count Operation:
Immediately after a reset, the MTU2’s TCNT counters are all designated as free-running counters.
When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count
operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV
bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the
MTU2 requests an interrupt. After overflow, TCNT starts counting up again from H'0000.
Figure 11.5 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 11.5 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The TGR register for setting the period is designated
as an output compare register, and counter clearing by compare match is selected by means of bits
CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as
a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches
the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the MTU2 requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 531 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 11.6 illustrates periodic counter operation.
Counter cleared by TGR
compare match
TCNT value
TGR
H'0000
Time
CST bit
Flag cleared by software or
DMAC activation
TGF
Figure 11.6 Periodic Counter Operation
(2)
Waveform Output by Compare Match
The MTU2 can perform 0, 1, or toggle output from the corresponding output pin using compare
match.
(a)
Example of Setting Procedure for Waveform Output by Compare Match
Figure 11.7 shows an example of the setting procedure for waveform output by compare match.
Output selection
Select waveform output
mode
[1]
[1] Select initial value 0 output or 1 output,
and compare match output value 0
output, 1 output, or toggle output, by
means of TIOR. The set initial value is
output at the TIOC pin until the first
compare match occurs.
[2] Set the timing for compare match
generation in TGR.
Set output timing
[2]
Start count operation
[3]
[3] Set the CST bit in TSTR to 1 to start the
count operation.
Figure 11.7 Example of Setting Procedure for Waveform Output by Compare Match
Page 532 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Examples of Waveform Output Operation:
Figure 11.8 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been made
such that 1 is output by compare match A, and 0 is output by compare match B. When the set level
and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
No change
TIOCB
No change
0 output
Figure 11.8 Example of 0 Output/1 Output Operation
Figure 11.9 shows an example of toggle output.
In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both compare
match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 11.9 Example of Toggle Output Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 533 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1,
it is also possible to specify another channel's counter input clock or compare match signal as the
input capture source.
Note: When another channel's counter input clock is used as the input capture input for channels
0 and 1, Pφ/1 should not be selected as the counter input clock used for input capture
input. Input capture will not be generated if Pφ/1 is selected.
(a)
Example of Input Capture Operation Setting Procedure
Figure 11.10 shows an example of the input capture operation setting procedure.
Input selection
Select input capture input
[1]
[1] Designate TGR as an input capture
register by means of TIOR, and select
rising edge, falling edge, or both edges
as the input capture source and input
signal edge.
[2] Set the CST bit in TSTR to 1 to start
the count operation.
Start count
[2]
Figure 11.10 Example of Input Capture Operation Setting Procedure
Page 534 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Example of Input Capture Operation
Figure 11.11 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input capture
input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and
counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 11.11 Example of Input Capture Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 535 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.2
Synchronous Operation
In synchronous operation, the values in a number of TCNT counters can be rewritten
simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for
synchronous operation.
(1)
Example of Synchronous Operation Setting Procedure
Figure 11.12 shows an example of the synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to,
the same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 11.12 Example of Synchronous Operation Setting Procedure
Page 536 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Example of Synchronous Operation
Figure 11.13 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM
cycle.
For details of PWM modes, see section 11.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT0 to TCNT2
values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOC0A
TIOC1A
TIOC2A
Figure 11.13 Example of Synchronous Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 537 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.3
Buffer Operation
Buffer operation, provided for channels 0, 3, and 4 enables TGRC and TGRD to be used as buffer
registers. In channel 0, TGRF can also be used as a buffer register.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Note: TGRE_0 cannot be designated as an input capture register and can only operate as a
compare match register.
Table 11.43 shows the register combinations used in buffer operation.
Table 11.43 Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0
TGRA_0
TGRC_0
TGRB_0
TGRD_0
TGRE_0
TGRF_0
TGRA_3
TGRC_3
TGRB_3
TGRD_3
TGRA_4
TGRC_4
TGRB_4
TGRD_4
3
4
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 11.14.
Compare match signal
Buffer
register
Timer general
register
Comparator
TCNT
Figure 11.14 Compare Match Buffer Operation
Page 538 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 11.15.
Input capture
signal
Buffer
register
Timer general
register
TCNT
Figure 11.15 Input Capture Buffer Operation
(1)
Example of Buffer Operation Setting Procedure
Figure 11.16 shows an example of the buffer operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
Select TGR function
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 start the count
operation.
Set buffer operation
[2]
Start count
[3]
Figure 11.16 Example of Buffer Operation Setting Procedure
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 539 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Examples of Buffer Operation
(a)
When TGR is an output compare register
Figure 11.17 shows an operation example in which PWM mode 1 has been designated for channel
0, and buffer operation has been designated for TGRA and TGRC. The settings used in this
example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at
compare match B. In this example, the TTSA bit in TBTM is cleared to 0.
As buffer operation has been set, when compare match A occurs the output changes and the value
in buffer register TGRC is simultaneously transferred to timer general register TGRA. This
operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 11.4.5, PWM Modes.
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
TGRC_0 H'0200
H'0450
H'0520
Transfer
TGRA_0
H'0200
H'0450
TIOCA
Figure 11.17 Example of Buffer Operation (1)
(b)
When TGR is an input capture register
Figure 11.18 shows an operation example in which TGRA has been designated as an input capture
register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges
have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
Page 540 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
TGRA
H'0532
TGRC
H'0F07
H'09FB
H'0532
H'0F07
Figure 11.18 Example of Buffer Operation (2)
(3)
Selecting Timing for Transfer from Buffer Registers to Timer General Registers in
Buffer Operation
The timing for transfer from buffer registers to timer general registers can be selected in PWM
mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation
transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial
setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer
timing is one of the following cases.
• When TCNT overflows (H'FFFF to H'0000)
• When H'0000 is written to TCNT during counting
• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits
in TCR
Note: TBTM must be modified only while TCNT stops.
Figure 11.19 shows an operation example in which PWM mode 1 is designated for channel 0 and
buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are
TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare
match B. The TTSA bit in TBTM_0 is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 541 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_0 value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
H'0000
TGRC_0
Time
H'0200
H'0450
H'0520
Transfer
TGRA_0
H'0200
H'0450
H'0520
TIOCA
Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for
TGRC_0 to TGRA_0 Transfer Timing
11.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase counting mode.
Table 11.44 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
counters operates independently in phase counting mode.
Table 11.44 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 11.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Page 542 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.45 show the TICCR setting and input capture input pins.
Table 11.45 TICCR Setting and Input Capture Input Pins
Target Input Capture
TICCR Setting
Input Capture Input Pins
Input capture from TCNT_1 to
TGRA_1
I2AE bit = 0 (initial value)
TIOC1A
I2AE bit = 1
TIOC1A, TIOC2A
Input capture from TCNT_1 to
TGRB_1
I2BE bit = 0 (initial value)
TIOC1B
I2BE bit = 1
TIOC1B, TIOC2B
Input capture from TCNT_2 to
TGRA_2
I1AE bit = 0 (initial value)
TIOC2A
I1AE bit = 1
TIOC2A, TIOC1A
Input capture from TCNT_2 to
TGRB_2
I1BE bit = 0 (initial value)
TIOC2B
I1BE bit = 1
TIOC2B, TIOC1B
(1)
Example of Cascaded Operation Setting Procedure
Figure 11.20 shows an example of the setting procedure for cascaded operation.
[1] Set bits TPSC2 to TPSC0 in the channel 1
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
Cascaded operation
Set cascading
[1]
Start count
[2]
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
Figure 11.20 Cascaded Operation Setting Procedure
(2)
Cascaded Operation Example (a)
Figure 11.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 543 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCLKC
TCLKD
TCNT_2
TCNT_1
FFFD
FFFE
FFFF
0000
0000
0001
0002
0001
0001
0000
FFFF
0000
Figure 11.21 Cascaded Operation Example (a)
(3)
Cascaded Operation Example (b)
Figure 11.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture
conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising
edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the
TIOC2A rising edge for the input capture timing.
Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1
input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used.
TCNT_2 value
H'FFFF
H'C256
H'6128
H'0000
TCNT_1
Time
H'0512
H'0513
H'0514
TIOC1A
TIOC2A
TGRA_1
TGRA_2
H'0512
H'0513
H'C256
As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing.
Figure 11.22 Cascaded Operation Example (b)
Page 544 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(4)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Cascaded Operation Example (c)
Figure 11.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the
TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3
bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input
capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for
the TGRA_1 and TGRA_2 input capture conditions.
TCNT_2 value
H'FFFF
H'C256
H'9192
H'6128
H'2064
H'0000
TCNT_1
Time
H'0512
H'0513
H'0514
TIOC1A
TIOC2A
TGRA_1
H'0512
TGRA_2
H'6128
H'0513
H'2064
H'0514
H'C256
H'9192
Figure 11.23 Cascaded Operation Example (c)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 545 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(5)
Cascaded Operation Example (d)
Figure 11.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the
I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture
conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare
match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in
TIOR_2 have selected the TIOC2A rising edge for the input capture timing.
Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture
occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture
condition although the I2AE bit in TICCR has been set to 1.
TCNT_0 value
Compare match between TCNT_0 and TGRA_0
TGRA_0
Time
H'0000
TCNT_2 value
H'FFFF
H'D000
H'0000
TCNT_1
Time
H'0512
H'0513
TIOC1A
TIOC2A
TGRA_1
TGRA_2
H'0513
H'D000
Figure 11.24 Cascaded Operation Example (d)
Page 546 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.4.5
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is
output from the TIOCA and TIOCC pins at compare matches A and C, and the output
specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B
and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output specified in TIOR is performed by means of compare matches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 11.46.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 547 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.46 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
0
TGRA_0
TIOC0A
TGRB_0
TGRC_0
TGRA_1
TIOC0C
TGRA_2
TIOC1A
TGRA_3
TIOC2A
TIOC3A
TGRA_4
TIOC3C
TGRD_4
Cannot be set
Cannot be set
TIOC4A
TGRB_4
TGRC_4
Cannot be set
Cannot be set
TGRD_3
4
TIOC2A
TIOC2B
TGRB_3
TGRC_3
TIOC1A
TIOC1B
TGRB_2
3
TIOC0C
TIOC0D
TGRB_1
2
TIOC0A
TIOC0B
TGRD_0
1
PWM Mode 2
Cannot be set
Cannot be set
TIOC4C
Cannot be set
Cannot be set
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Page 548 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Example of PWM Mode Setting Procedure
Figure 11.25 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
Select counter clearing
source
[2]
Select waveform
output level
[3]
Set TGR
[4]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and
CKEG0 in TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select
the TGR to be used as the TCNT clearing
source.
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value
and output value.
[4] Set the cycle in the TGR selected in [2], and
set the duty in the other TGR.
[5] Select the PWM mode with bits MD3 to MD0
in TMDR.
[6] Set the CST bit in TSTR to 1 to start the
count operation.
Set PWM mode
[5]
Start count
[6]
Figure 11.25 Example of PWM Mode Setting Procedure
(2)
Examples of PWM Mode Operation
Figure 11.26 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty levels.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 549 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT value
Counter cleared by
TGRA compare match
TGRA
TGRB
H'0000
Time
TIOCA
Figure 11.26 Example of PWM Mode Operation (1)
Figure 11.27 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are
used as the duty levels.
TCNT value
Counter cleared by
TGRB_1 compare match
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
Figure 11.27 Example of PWM Mode Operation (2)
Page 550 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 11.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB rewritten
TGRB
rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 11.28 Example of PWM Mode Operation (3)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 551 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits
CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of
TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 11.47 shows the correspondence between external clock pins and channels.
Table 11.47 Phase Counting Mode Clock Input Pins
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 is set to phase counting mode
TCLKA
TCLKB
When channel 2 is set to phase counting mode
TCLKC
TCLKD
(1)
Example of Phase Counting Mode Setting Procedure
Figure 11.29 shows an example of the phase counting mode setting procedure.
[1] Select phase counting mode with bits
MD3 to MD0 in TMDR.
Phase counting mode
Select phase counting
mode
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start
the count operation.
Figure 11.29 Example of Phase Counting Mode Setting Procedure
Page 552 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two
external clocks. There are four modes according to the count conditions.
(a)
Phase counting mode 1
Figure 11.30 shows an example of phase counting mode 1 operation, and table 11.48 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Up-count
Down-count
Time
Figure 11.30 Example of Phase Counting Mode 1 Operation
Table 11.48 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
High level
Operation
Up-count
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
[Legend]
:
Rising edge
:
Falling edge
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 553 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Phase counting mode 2
Figure 11.31 shows an example of phase counting mode 2 operation, and table 11.49 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Up-count
Down-count
Time
Figure 11.31 Example of Phase Counting Mode 2 Operation
Table 11.49 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
High level
Don't care
Low level
Don't care
Low level
Don't care
High level
Up-count
High level
Don't care
Low level
Don't care
High level
Don't care
Low level
Down-count
[Legend]
:
Rising edge
:
Falling edge
Page 554 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(c)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Phase counting mode 3
Figure 11.32 shows an example of phase counting mode 3 operation, and table 11.50 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Up-count
Down-count
Time
Figure 11.32 Example of Phase Counting Mode 3 Operation
Table 11.50 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
Operation
Don't care
High level
Low level
Don't care
Low level
Don't care
High level
Up-count
High level
Down-count
Low level
Don't care
High level
Don't care
Low level
Don't care
[Legend]
:
Rising edge
:
Falling edge
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 555 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(d)
Phase counting mode 4
Figure 11.33 shows an example of phase counting mode 4 operation, and table 11.51 summarizes
the TCNT up/down-count conditions.
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
TCNT value
Up-count
Down-count
Time
Figure 11.33 Example of Phase Counting Mode 4 Operation
Table 11.51 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channel 1)
TCLKC (Channel 2)
TCLKB (Channel 1)
TCLKD (Channel 2)
High level
Operation
Up-count
Low level
Low level
Don't care
High level
High level
Down-count
Low level
High level
Don't care
Low level
[Legend]
:
Rising edge
:
Falling edge
Page 556 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Phase Counting Mode Application Example
Figure 11.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is
coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or
speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function and are set with the speed control period and
position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source and store the up/down-counter
values for the control periods.
This procedure enables the accurate detection of position and speed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 557 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT_1
TGRA_1
(speed period capture)
TGRB_1
(position period capture)
TCNT_0
TGRA_0
(speed control period)
+
-
TGRC_0
(position control period)
+
-
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 11.34 Phase Counting Mode Application Example
Page 558 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.4.7
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Reset-Synchronized PWM Mode
In reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms
that share a common wave transition point can be obtained by combining channels 3 and 4.
When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C,
TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter.
Table 11.52 shows the PWM output pins used. Table 11.53 shows the settings of the registers.
Table 11.52 Output Pins for Reset-Synchronized PWM Mode
Channel
Output Pin
Description
3
TIOC3B
PWM output pin 1
TIOC3D
PWM output pin 1' (negative-phase waveform of PWM output 1)
TIOC4A
PWM output pin 2
TIOC4C
PWM output pin 2' (negative-phase waveform of PWM output 2)
TIOC4B
PWM output pin 3
TIOC4D
PWM output pin 3' (negative-phase waveform of PWM output 3)
4
Table 11.53 Register Settings for Reset-Synchronized PWM Mode
Register
Description of Setting
TCNT_3
Initial setting of H'0000
TCNT_4
Initial setting of H'0000
TGRA_3
Set count cycle for TCNT_3
TGRB_3
Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins
TGRA_4
Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins
TGRB_4
Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 559 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
SH7280 Group, SH7243 Group
Procedure for Selecting the Reset-Synchronized PWM Mode
Figure 11.35 shows an example of procedure for selecting reset-synchronized PWM mode.
[1] Clear the CST3 and CST4 bits in the TSTR
to 0 to halt the counting of TCNT. The
reset-synchronized PWM mode must be set
up while TCNT_3 and TCNT_4 are halted.
Reset-synchronized
PWM mode
Stop counting
[1]
[2] Set bits TPSC2-TPSC0 and CKEG1 and
CKEG0 in the TCR_3 to select the counter
clock and clock edge for channel 3. Set bits
CCLR2-CCLR0 in the TCR_3 to select TGRA
compare-match as a counter clear source.
Select counter clock and
counter clear source
[2]
Brushless DC motor
control setting
[3]
Set TCNT
[4]
Set TGR
[5]
PWM cycle output enabling,
PWM output level setting
[6]
Set reset-synchronized
PWM mode
[7]
Enable waveform output
[8]
PFC setting
[9]
[7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select
the reset-synchronized PWM mode. Do not set to TMDR_4.
Start count operation
[10]
[8] Set the enabling/disabling of the PWM waveform output
pin in TOER.
[3] When performing brushless DC motor control,
set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source
and output chopping or gate signal direct output.
[4] Reset TCNT_3 and TCNT_4 to H'0000.
Reset-synchronized PWM mode
[5] TGRA_3 is the period register. Set the waveform
period value in TGRA_3. Set the transition timing
of the PWM output waveforms in TGRB_3,
TGRA_4, and TGRB_4. Set times within the
compare-match range of TCNT_3.
X ≤ TGRA_3 (X: set value).
[6] Select enabling/disabling of toggle output
synchronized with the PMW cycle using bit PSYE
in the timer output control register (TOCR), and set
the PWM output level with bits OLSP and OLSN.
When specifying the PWM output level by using TOLBR
as a buffer for TOCR_2, see figure 10.3.
[9] Set the port control register and the port I/O register.
[10] Set the CST3 bit in the TSTR to 1 to start the count
operation.
Note: The output waveform starts to toggle operation at the point of
TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty.
Figure 11.35 Procedure for Selecting Reset-Synchronized PWM Mode
Page 560 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Reset-Synchronized PWM Mode Operation
Figure 11.36 shows an example of operation in reset-synchronized PWM mode. TCNT_3 and
TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 comparematch occurs, and then begins incrementing from H'0000. The PWM output pin output toggles
with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears.
TCNT_3 and TCNT_4
values
TGRA_3
TGRB_3
TGRA_4
TGRB_4
H'0000
Time
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Figure 11.36 Reset-Synchronized PWM Mode Operation Example
(When TOCR’s OLSN = 1 and OLSP = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 561 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.8
SH7280 Group, SH7243 Group
Complementary PWM Mode
In complementary PWM mode, three-phase output of non-overlapping positive and negative
PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval are also available.
In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D
pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with
the PWM period. TCNT_3 and TCNT_4 function as up/down counters.
Table 11.54 shows the PWM output pins used. Table 11.55 shows the settings of the registers
used.
A function to directly cut off the PWM output by using an external signal is supported as a port
function.
Table 11.54 Output Pins for Complementary PWM Mode
Channel
Output Pin
Description
3
TIOC3A
Toggle output synchronized with PWM period (or I/O port)
TIOC3B
PWM output pin 1
4
Note:
*
TIOC3C
I/O port*
TIOC3D
PWM output pin 1'
(non-overlapping negative-phase waveform of PWM output 1;
PWM output without non-overlapping interval is also available)
TIOC4A
PWM output pin 2
TIOC4B
PWM output pin 3
TIOC4C
PWM output pin 2'
(non-overlapping negative-phase waveform of PWM output 2;
PWM output without non-overlapping interval is also available)
TIOC4D
PWM output pin 3'
(non-overlapping negative-phase waveform of PWM output 3;
PWM output without non-overlapping interval is also available)
Avoid setting the TIOC3C pin as a timer I/O pin in complementary PWM mode.
Page 562 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.55 Register Settings for Complementary PWM Mode
Channel
Counter/Register
Description
Read/Write from CPU
3
TCNT_3
Start of up-count from value set
in dead time register
Maskable by TRWER
setting*
TGRA_3
Set TCNT_3 upper limit value
(1/2 carrier cycle + dead time)
Maskable by TRWER
setting*
TGRB_3
PWM output 1 compare register
Maskable by TRWER
setting*
TGRC_3
TGRA_3 buffer register
Always readable/writable
TGRD_3
PWM output 1/TGRB_3 buffer
register
Always readable/writable
TCNT_4
Up-count start, initialized to
H'0000
Maskable by TRWER
setting*
TGRA_4
PWM output 2 compare register
Maskable by TRWER
setting*
TGRB_4
PWM output 3 compare register
Maskable by TRWER
setting*
TGRC_4
PWM output 2/TGRA_4 buffer
register
Always readable/writable
TGRD_4
PWM output 3/TGRB_4 buffer
register
Always readable/writable
Timer dead time data register
(TDDR)
Set TCNT_4 and TCNT_3 offset
value (dead time value)
Maskable by TRWER
setting*
Timer cycle data register
(TCDR)
Set TCNT_4 upper limit value
(1/2 carrier cycle)
Maskable by TRWER
setting*
Timer cycle buffer register
(TCBR)
TCDR buffer register
Always readable/writable
Subcounter (TCNTS)
Subcounter for dead time
generation
Read-only
Temporary register 1 (TEMP1)
PWM output 1/TGRB_3
temporary register
Not readable/writable
Temporary register 2 (TEMP2)
PWM output 2/TGRA_4
temporary register
Not readable/writable
Temporary register 3 (TEMP3)
PWM output 3/TGRB_4
temporary register
Not readable/writable
4
Note:
*
Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER
(timer read/write enable register).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 563 of 1778
SH7280 Group, SH7243 Group
TCBR
TGRA_3
TCDR
Comparator
TCNT_3
Match
signal
TCNTS
TCNT_4
TGRD_3
TGRC_4
TGRB_4
Temp 3
Match
signal
TGRA_4
Temp 2
TGRB_3
Temp 1
Comparator
PWM cycle
output
Output protection circuit
TDDR
TGRC_3
Output controller
TCNT_4 underflow
interrupt
TGRA_3 comparematch interrupt
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
External cutoff
input
POE0
POE1
POE2
POE3
TGRD_4
External cutoff
interrupt
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by TRWER)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Figure 11.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
Page 564 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Example of Complementary PWM Mode Setting Procedure
An example of the complementary PWM mode setting procedure is shown in figure 11.38.
[1] Clear bits CST3 and CST4 in the timer start register
(TSTR) to 0, and halt timer counter (TCNT) operation.
Perform complementary PWM mode setting when
TCNT_3 and TCNT_4 are stopped.
Complementary PWM mode
Stop count operation
[1]
Counter clock, counter clear
source selection
[2]
Brushless DC motor control
setting
[3]
TCNT setting
[4]
[2] Set the same counter clock and clock edge for channels
3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and
CKEG0 in the timer control register (TCR). Use bits
CCLR2-CCLR0 to set synchronous clearing only when
restarting by a synchronous clear from another channel
during complementary PWM mode operation.
[3] When performing brushless DC motor control, set bit BDC
in the timer gate control register (TGCR) and set the
feedback signal input source and output chopping or gate
signal direct output.
[4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000.
Inter-channel synchronization
setting
[5]
TGR setting
[6]
Enable/disable dead time
generation
[7]
Dead time, carrier cycle
setting
[8]
PWM cycle output enabling,
PWM output level setting
[9]
Complementary PWM mode
setting
[10]
Enable waveform output
[11]
setting
StartPFC
count
operation
[12]
[5] Set only when restarting by a synchronous clear from
another channel during complementary PWM mode
operation. In this case, synchronize the channel generating
the synchronous clear with channels 3 and 4 using the timer
synchro register (TSYR).
[6] Set the output PWM duty in the duty registers (TGRB_3,
TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4,
TGRD_4). Set the same initial value in each corresponding
TGR.
[7] This setting is necessary only when no dead time should be
generated. Make appropriate settings in the timer dead time
enable register (TDER) so that no dead time is generated.
[8] Set the dead time in the dead time register (TDDR), 1/2 the
carrier cycle in the carrier cycle data register (TCDR) and
carrier cycle buffer register (TCBR), and 1/2 the carrier cycle
plus the dead time in TGRA_3 and TGRC_3. When no dead
time generation is selected, set 1 in TDDR and 1/2 the carrier
cycle + 1 in TGRA_3 and TGRC_3.
[9] Select enabling/disabling of toggle output synchronized with
the PWM cycle using bit PSYE in the timer output control
register 1 (TOCR1), and set the PWM output level with bits OLSP
and OLSN. When specifying the PWM output level by using
TOLBR as a buffer for TOCR_2, see figure 10.3.
[10] Select complementary PWM mode in timer mode register 3
(TMDR_3). Do not set in TMDR_4.
Start count operation
[13]
[11] Set enabling/disabling of PWM waveform output pin output in
the timer output master enable register (TOER).
[12] Set the port control register and the port I/O register.
[13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start
the count operation.
Figure 11.38 Example of Complementary PWM Mode Setting Procedure
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 565 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
SH7280 Group, SH7243 Group
Outline of Complementary PWM Mode Operation
In complementary PWM mode, 6-phase PWM output is possible. Figure 11.39 illustrates counter
operation in complementary PWM mode, and figure 11.40 shows an example of complementary
PWM mode operation.
(a)
Counter Operation
In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform
up/down-count operations.
TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode
is selected and the CST bit in TSTR is 0.
When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to
down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter
switches to up-counting, and the operation is repeated in this way.
TCNT_4 is initialized to H'0000.
When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to
down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting,
and the operation is repeated in this way.
TCNTS is a read-only counter. It need not be initialized.
When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting
is started, and when TCNTS matches TCDR, the operation switches to up-counting. When
TCNTS matches TGRA_3, it is cleared to H'0000.
When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is
started, and when TCNTS matches TDDR, the operation switches to down-counting. When
TCNTS reaches H'0000, it is set with the value in TGRA_3.
TCNTS is compared with the compare register and temporary register in which the PWM duty is
set during the count operation only.
Page 566 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4
TCNTS
Counter value
TGRA_3
TCDR
TCNT_3
TCNT_4
TCNTS
TDDR
H'0000
Time
Figure 11.39 Complementary PWM Mode Counter Operation
(b)
Register Operation
In complementary PWM mode, nine registers are used, comprising compare registers, buffer
registers, and temporary registers. Figure 11.40 shows an example of complementary PWM mode
operation.
The registers which are constantly compared with the counters to perform PWM output are
TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits
OLSN and OLSP in the timer output control register (TOCR) is output.
The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4.
Between a buffer register and compare register there is a temporary register. The temporary
registers cannot be accessed by the CPU.
Data in a compare register is changed by writing the new data to the corresponding buffer register.
The buffer registers can be read or written at any time.
The data written to a buffer register is constantly transferred to the temporary register in the Ta
interval. Data is not transferred to the temporary register in the Tb interval. Data written to a
buffer register in this interval is transferred to the temporary register at the end of the Tb interval.
The value transferred to a temporary register is transferred to the compare register when TCNTS
for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting
down. The timing for transfer from the temporary register to the compare register can be selected
with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.40 shows an example in
which the mode is selected in which the change is made in the trough.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 567 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
In the Tb interval (tb1 in figure 11.40) in which data transfer to the temporary register is not
performed, the temporary register has the same function as the compare register, and is compared
with the counter. In this interval, therefore, there are two compare match registers for one-phase
output, with the compare register containing the pre-change data, and the temporary register
containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS—
and two registers—compare register and temporary register—are compared, and PWM output
controlled accordingly.
Page 568 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Transfer from temporary
register to compare register
Tb2
Transfer from temporary
register to compare register
Ta
Tb1
Ta
Tb2
Ta
TGRA_3
TCNTS
TCDR
TCNT_3
TGRA_4
TCNT_4
TGRC_4
TDDR
H'0000
Buffer register
TGRC_4
H'6400
H'0080
Temporary register
TEMP2
H'6400
H'0080
Compare register
TGRA_4
H'6400
H'0080
Output waveform
Output waveform
(Output waveform is active-low)
Figure 11.40 Example of Complementary PWM Mode Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 569 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(c)
Initialization
In complementary PWM mode, there are six registers that must be initialized. In addition, there is
a register that specifies whether to generate dead time (it should be used only when dead time
generation should be disabled).
Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register
(TMDR), the following initial register values must be set.
TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier
cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for
the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead
time Td in the timer dead time data register (TDDR).
When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should
be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR
should be set to 1.
Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4.
The values set in the five buffer registers excluding TDDR are transferred simultaneously to the
corresponding compare registers when complementary PWM mode is set.
Set TCNT_4 to H'0000 before setting complementary PWM mode.
Table 11.56 Registers and Counters Requiring Initialization
Register/Counter
Set Value
TGRC_3
1/2 PWM carrier cycle + dead time Td
(1/2 PWM carrier cycle + 1 when dead time generation
is disabled by TDER)
TDDR
Dead time Td (1 when dead time generation is
disabled by TDER)
TCBR
1/2 PWM carrier cycle
TGRD_3, TGRC_4, TGRD_4
Initial PWM duty value for each phase
TCNT_4
H'0000
Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and
dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3
must be set to 1/2 the PWM carrier cycle + 1.
Page 570 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(d)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
PWM Output Level Setting
In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in
timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer
output control register 2 (TOCR2).
The output level can be set for each of the three positive phases and three negative phases of 6phase output.
Complementary PWM mode should be cleared before setting or changing output levels.
(e)
Dead Time Setting
In complementary PWM mode, PWM pulses are output with a non-overlapping relationship
between the positive and negative phases. This non-overlap time is called the dead time.
The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is
used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4.
Complementary PWM mode should be cleared before changing the contents of TDDR.
(f)
Dead Time Suppressing
Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable
register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER =
1.
TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data
register (TDDR) should be set to 1.
By the above settings, PWM waveforms without dead time can be obtained. Figure 11.41 shows
an example of operation without dead time.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 571 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
Transfer from temporary register
to compare register
Transfer from temporary register
to compare register
Ta
Tb1
Ta
Tb2
Ta
TGRA_3=TCDR+1
TCNTS
TCDR
TCNT_3
TCNT_4
TGRA_4
TGRC_4
TDDR=1
H'0000
Buffer register TGRC_4
Data1
Data2
Temporary register TEMP2
Data1
Data2
Compare register TGRA_4
Data1
Output waveform
Initial output
Output waveform
Initial output
Data2
Output waveform is active-low.
Figure 11.41 Example of Operation without Dead Time
Page 572 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(g)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
PWM Cycle Setting
In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which
the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set.
The settings should be made so as to achieve the following relationship between these two
registers:
With dead time: TGRA_3 set value = TCDR set value + TDDR set value
Without dead time: TGRA_3 set value = TCDR set value + 1
The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and
TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and
TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode
register (TMDR).
The updated PWM cycle is reflected from the next cycle when the data update is performed at the
crest, and from the current cycle when performed in the trough. Figure 11.42 illustrates the
operation when the PWM cycle is updated at the crest.
See the following section, Register Data Updating, for the method of updating the data in each
buffer register.
Counter value TGRC_3
update
TGRA_3
update
TCNT_3
TGRA_3
TCNT_4
Time
Figure 11.42 Example of PWM Cycle Updating
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 573 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(h)
SH7280 Group, SH7243 Group
Register Data Updating
In complementary PWM mode, the buffer register is used to update the data in a compare register.
The update data can be written to the buffer register at any time. There are five PWM duty and
carrier cycle registers that have buffer registers and can be updated during operation.
There is a temporary register between each of these registers and its buffer register. When
subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value
is also rewritten. Transfer is not performed from buffer registers to temporary registers when
TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS
halts.
The temporary register value is transferred to the compare register at the data update timing set
with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.43 shows an example of
data updating in complementary PWM mode. This example shows the mode in which data
updating is performed at both the counter crest and trough.
When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the
update. Data transfer from the buffer registers to the temporary registers is performed
simultaneously for all five registers after the write to TGRD_4.
A write to TGRD_4 must be performed after writing data to the registers to be updated, even when
not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to
TGRD_4 should be the same as the data prior to the write operation.
Page 574 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
data1
Temp_R
GR
data1
BR
H'0000
TGRC_4
TGRA_4
TGRA_3
Counter value
data1
Transfer from
temporary register
to compare register
data2
data2
data2
Transfer from
temporary register
to compare register
Data update timing: counter crest and trough
data3
data3
Transfer from
temporary register
to compare register
data3
data4
data4
Transfer from
temporary register
to compare register
data4
data5
data5
Transfer from
temporary register
to compare register
data6
data6
data6
Transfer from
temporary register
to compare register
: Compare register
: Buffer register
Time
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 11.43 Example of Data Update in Complementary PWM Mode
Page 575 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(i)
Initial Output in Complementary PWM Mode
In complementary PWM mode, the initial output is determined by the setting of bits OLSN and
OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P
in timer output control register 2 (TOCR2).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in
the dead time register (TDDR). Figure 11.44 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty value is smaller than the TDDR value is
shown in figure 11.45.
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
TGRA_4
TDDR
Time
Initial output
Positive phase
output
Negative phase
output
Dead time
Active level
Active level
Complementary
PWM mode
(TMDR setting)
TCNT_3, 4 count start
(TSTR setting)
Figure 11.44 Example of Initial Output in Complementary PWM Mode (1)
Page 576 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
TDDR
TGRA_4
Time
Initial output
Positive phase
output
Negative phase
output
Active level
Complementary
PWM mode
(TMDR setting)
TCNT_3, 4 count start
(TSTR setting)
Figure 11.45 Example of Initial Output in Complementary PWM Mode (2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 577 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(j)
SH7280 Group, SH7243 Group
Complementary PWM Mode PWM Output Generation Method
In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead
time.
A PWM waveform is generated by output of the output level selected in the timer output control
register in the event of a compare-match between a counter and data register. While TCNTS is
counting, data register and temporary register values are simultaneously compared to create
consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match
occurrence may vary, but the compare-match that turns off each phase takes precedence to secure
the dead time and ensure that the positive phase and negative phase on times do not overlap.
Figures 11.46 to 11.48 show examples of waveform generation in complementary PWM mode.
The positive phase/negative phase off timing is generated by a compare-match with the solid-line
counter, and the on timing by a compare-match with the dotted-line counter operating with a delay
of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the
negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In
the T2 period, compare-match c that turns off the positive phase has the highest priority, and
compare-matches occurring prior to c are ignored.
In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as
shown in figure 11.46.
If compare-matches deviate from the a → b → c → d order, since the time for which the negative
phase is off is less than twice the dead time, the figure shows the positive phase is not being turned
on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the
positive phase is off is less than twice the dead time, the figure shows the negative phase is not
being turned on.
If compare-match c occurs first following compare-match a, as shown in figure 11.47, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because
turning off of the positive phase has priority due to the occurrence of compare-match c (positive
phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform
does not change since the positive phase goes from off to off).
Similarly, in the example in figure 11.48, compare-match a' with the new data in the temporary
register occurs before compare-match c, but other compare-matches occurring up to c, which turns
off the positive phase, are ignored. As a result, the negative phase is not turned on.
Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and
turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.
Page 578 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
T2 period
T1 period
T1 period
TGR3A_3
c
d
TCDR
a
b
a'
b'
TDDR
H'0000
Positive phase
Negative phase
Figure 11.46 Example of Complementary PWM Mode Waveform Output (1)
T2 period
T1 period
T1 period
TGRA_3
c
d
TCDR
a
b
a
b
TDDR
H'0000
Positive phase
Negative phase
Figure 11.47 Example of Complementary PWM Mode Waveform Output (2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 579 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
TDDR
c
a'
d
b'
H'0000
Positive phase
Negative phase
Figure 11.48 Example of Complementary PWM Mode Waveform Output (3)
(k)
Complementary PWM Mode 0% and 100% Duty Output
In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures
11.49 to 11.53 show output examples.
100% duty output is performed when the data register value is set to H'0000. The waveform in this
case has a positive phase with a 100% on-state. 0% duty output is performed when the data
register value is set to the same value as TGRA_3. The waveform in this case has a positive phase
with a 100% off-state.
On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off
compare-match for the same phase occur simultaneously, both compare-matches are ignored and
the waveform does not change.
Page 580 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period
T2 period
c
TGRA_3
T1 period
d
TCDR
a
b
a'
b'
TDDR
H'0000
Positive phase
Negative phase
Figure 11.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
a
b
TDDR
H'0000
c
d
Positive phase
Negative phase
Figure 11.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 581 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period
T2 period
c
TGRA_3
T1 period
d
TCDR
a
b
TDDR
H'0000
Positive phase
Negative phase
Figure 11.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3)
T1 period
T2 period
T1 period
TGRA_3
TCDR
a
b
TDDR
H'0000
Positive phase
c b'
d a'
Negative phase
Figure 11.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4)
Page 582 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
T1 period
TGRA_3
T2 period
c
ad
T1 period
b
TCDR
TDDR
H'0000
Positive phase
Negative phase
Figure 11.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 583 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(l)
SH7280 Group, SH7243 Group
Toggle Output Synchronized with PWM Cycle
In complementary PWM mode, toggle output can be performed in synchronization with the PWM
carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example
of a toggle output waveform is shown in figure 11.54.
This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match
between TCNT4 and H'0000.
The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
TGRA_3
TCNT_3
TCNT_4
H'0000
Toggle output
TIOC3A pin
Figure 11.54 Example of Toggle Output Waveform Synchronized with PWM Output
Page 584 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(m) Counter Clearing by Another Channel
In complementary PWM mode, by setting a mode for synchronization with another channel by
means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits
CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4,
and TCNTS cleared by another channel.
Figure 11.55 illustrates the operation.
Use of this function enables counter clearing and restarting to be performed by means of an
external signal.
TCNTS
TGRA_3
TCDR
TCNT_3
TCNT_4
TDDR
H'0000
Channel 1
Input capture A
TCNT_1
Synchronous counter clearing by channel 1 input capture A
Figure 11.55 Counter Clearing Synchronized with Another Channel
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 585 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(n)
Output Waveform Control at Synchronous Counter Clearing in Complementary PWM
Mode
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing
occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change
in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval
at the trough as indicated by (10) or (11) in figure 11.56. When synchronous clearing occurs
outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb
interval at the trough, if synchronous clearing occurs in the initial value output period (indicated
by (1) in figure 11.56) immediately after the counters start operation, initial value output is not
suppressed.
This function can be used in both the MTU2 and MTU2S. In the MTU2, synchronous clearing
generated in channels 0 to 2 in the MTU2 can cause counter clearing in complementary PWM
mode; in the MTU2S, compare match or input capture flag setting in channels 0 to 2 in the MTU2
can cause counter clearing.
Counter start
Tb interval
Tb interval
Tb interval
TGRA_3
TCNT_3
TCDR
TGRB_3
TCNT_4
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) (11)
Figure 11.56 Timing for Synchronous Counter Clearing
Page 586 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing
in Complementary PWM Mode
An example of the procedure for setting output waveform control at synchronous counter
clearing in complementary PWM mode is shown in figure 11.57.
Output waveform control at
synchronous counter clearing
Stop count operation
Set TWCR and
complementary PWM mode
[1]
[1] Clear bits CST3 and CST4 in the timer
start register (TSTR) to 0, and halt timer
counter (TCNT) operation. Perform
TWCR setting while TCNT_3 and
TCNT_4 are stopped.
[2] Read bit WRE in TWCR and then write 1
to it to suppress initial value output at
counter clearing.
[2]
[3] Set bits CST3 and CST4 in TSTR to 1 to
start count operation.
Start count operation
[3]
Output waveform control at
synchronous counter clearing
Figure 11.57 Example of Procedure for Setting Output Waveform Control at Synchronous
Counter Clearing in Complementary PWM Mode
• Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary
PWM Mode
Figures 11.58 to 11.61 show examples of output waveform control in which the MTU2
operates in complementary PWM mode and synchronous counter clearing is generated while
the WRE bit in TWCR is set to 1. In the examples shown in figures 11.58 to 11.61,
synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 11.56,
respectively.
In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in
complementary PWM mode and synchronous counter clearing is generated while the SCC bit
is cleared to 0 and the WRE bit is set to 1 in TWCR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 587 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Synchronous clearing
Bit WRE = 1
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2)
TCNT_4
(MTU2)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 11.58 Example of Synchronous Clearing in Dead Time during Up-Counting
(Timing (3) in Figure 11.56; Bit WRE of TWCR in MTU2 is 1)
Page 588 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Synchronous clearing
Bit WRE = 1
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2)
TCNT_4
(MTU2)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 11.59 Example of Synchronous Clearing in Interval Tb at Crest
(Timing (6) in Figure 11.56; Bit WRE of TWCR in MTU2 is 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 589 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Synchronous clearing
Bit WRE = 1
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2)
TCNT_4
(MTU2)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 11.60 Example of Synchronous Clearing in Dead Time during Down-Counting
(Timing (8) in Figure 11.56; Bit WRE of TWCR is 1)
Page 590 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit WRE = 1
Synchronous clearing
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2)
TCNT_4
(MTU2)
TDDR
H'0000
Positive phase
Initial value output is suppressed.
Negative phase
Output waveform is active-low.
Figure 11.61 Example of Synchronous Clearing in Interval Tb at Trough
(Timing (11) in Figure 11.56; Bit WRE of TWCR is 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 591 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(o)
Suppressing MTU2-MTU2S Synchronous Counter Clearing
In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused
by the MTU2.
Synchronous counter clearing is suppressed only within the interval shown in figure 11.62. When
using this function, the MTU2S should be set to complementary PWM mode.
For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S
counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter
clearing) in section 11.4.10, MTU2-MTU2S Synchronous Operation.
Tb interval
immediately
after counter
operation starts
Tb interval
at the crest
Tb interval
at the trough
Tb interval
at the crest
Tb interval
at the trough
TGRA_3
TCDR
TGRB_3
TDDR
H'0000
MTU2-MTU2S synchronous counter
clearing is suppressed.
MTU2-MTU2S synchronous counter
clearing is suppressed.
Figure 11.62 MTU2-MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC
Bit in TWCR
Page 592 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter Clearing
An example of the procedure for suppressing MTU2-MTU2S synchronous counter clearing is
shown in figure 11.63.
[1] Clear bits CST of the timer start register (TSTR) in the MTU2S
to 0, and halt count operation. Clear bits CST of TSTR in the
MTU2 to 0, and halt count operation.
MTU2-MTU2S synchronous counter
clearing suppress
Stop count operation (MTU2 and MTU2S) [1]
• Set the following.
• Complementary PWM mode (MTU2S)
• Compare match/input capture
operation (MTU2)
• Bit WRE in TWCR (MTU2S)
[2]
Start count operation (MTU2 and MTU2S) [3]
Set bit SCC in TWCR (MTU2S)
Output waveform control at
synchronous counter clearing and
synchronous counter clearing suppress
[4]
[2] Set the complementary PWM mode in the MTU2S and
compare match/input capture operation in the MTU2. When bit
WRE in TWCR should be set, make appropriate setting here.
[3] Set bits CST3 and CST4 of TSTR in the MTU2S to 1 to start
count operation. For MTU2-MTU2S synchronous counter
clearing, set bits CST of TSTR in the MTU2 to 1 to start count
operation in any one of TCNT_0 to TCNT_2.
[4] Read TWCR and then set bit SCC in TWCR to 1 to suppress
MTU2-MTU2S synchronous counter clearing*. Here, do not
modify the CCE and WRE bit values in TWCR of the MTU2S.
MTU2-MTU2S synchronous counter clearing is suppressed in
the intervals shown in figure 10.62.
Note: * The SCC bit value can be modified during counter
operation. However, if a synchronous clearing occurs
when bit SCC is modified from 0 to 1, the synchronous
clearing may not be suppressed. If a synchronous
clearing occurs when bit SCC is modified from 1 to 0, the
synchronous clearing may be suppressed.
Figure 11.63 Example of Procedure for Suppressing MTU2-MTU2S Synchronous Counter
Clearing
• Examples of Suppression of MTU2-MTU2S Synchronous Counter Clearing
Figures 11.64 to 11.67 show examples of operation in which the MTU2S operates in
complementary PWM mode and MTU2-MTU2S synchronous counter clearing is suppressed
by setting the SCC bit in TWCR in the MTU2S to 1. In the examples shown in figures 11.64 to
11.67, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure
11.56, respectively.
In these examples, the WRE bit in TWCR of the MTU2S is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 593 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2-MTU2S
synchronous clearing
Bit WRE = 1
Bit SCC = 1
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2S)
TCNT_4
(MTU2S)
Counters
are not cleared
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 11.64 Example of Synchronous Clearing in Dead Time during Up-Counting
(Timing (3) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)
Page 594 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2-MTU2S
synchronous clearing
Bit WRE = 1
Bit SCC = 1
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2S)
Counters
are not cleared
TCNT_4
(MTU2S)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 11.65 Example of Synchronous Clearing in Interval Tb at Crest
(Timing (6) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 595 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2-MTU2S
synchronous clearing
Bit WRE = 1
Bit SCC = 1
TGRA_3
TCDR
TGRB_3
Counters
are not cleared
TCNT_3
(MTU2S)
TCNT_4
(MTU2S)
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Figure 11.66 Example of Synchronous Clearing in Dead Time during Down-Counting
(Timing (8) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)
Page 596 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit WRE = 1
Bit SCC = 1
MTU2-MTU2S
synchronous clearing
TGRA_3
TCDR
TGRB_3
TCNT_3
(MTU2S)
TCNT_4
(MTU2S)
Counters
are cleared
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Initial value output
is suppressed.
Figure 11.67 Example of Synchronous Clearing in Interval Tb at Trough
(Timing (11) in Figure 11.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 597 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(p)
SH7280 Group, SH7243 Group
Counter Clearing by TGRA_3 Compare Match
In complementary PWM mode, by setting the CCE bit in the timer waveform control register
(TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare
match.
Figure 11.68 illustrates an operation example.
Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest)
2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to
SYNC4 bits in the timer synchronous register (TSYR) to 1 or the CE0A, CE0B, CE0C,
CE0D, CE1A, CE1B, CE1C, and CE1D bits in the timer synchronous clear register S
(TSYCRS) to 1).
3. Do not set the PWM duty value to H'0000.
4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1.
Counter cleared
by TGRA_3 compare match
TGRA_3
TCDR
TGRB_3
TDDR
H'0000
Output waveform
Output waveform
Output waveform is active-high.
Figure 11.68 Example of Counter Clearing Operation by TGRA_3 Compare Match
Page 598 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(q)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output
In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate
control register (TGCR). Figures 11.69 to 11.72 show examples of brushless DC motor drive
waveforms created using TGCR.
When output phase switching for a 3-phase brushless DC motor is performed by means of external
signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external
signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B,
and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the
output on/off state is switched automatically.
When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is
cleared to 0 or set to 1.
The drive waveforms are output from the complementary PWM mode 6-phase output pins. With
this 6-phase output, in the case of on output, it is possible to use complementary PWM mode
output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0,
level output is selected.
The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the
timer output control register (TOCR) regardless of the setting of the N and P bits.
External input
TIOC0A pin
TIOC0B pin
TIOC0C pin
6-phase output TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 0, P = 0, FB = 0, output active level = high
Figure 11.69 Example of Output Phase Switching by External Input (1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 599 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
External input
SH7280 Group, SH7243 Group
TIOC0A pin
TIOC0B pin
TIOC0C pin
6-phase output
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 1, P = 1, FB = 0, output active level = high
Figure 11.70 Example of Output Phase Switching by External Input (2)
TGCR
UF bit
VF bit
WF bit
6-phase output
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 0, P = 0, FB = 1, output active level = high
Figure 11.71 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1)
Page 600 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
TGCR
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
UF bit
VF bit
WF bit
6-phase output
TIOC3B pin
TIOC3D pin
TIOC4A pin
TIOC4C pin
TIOC4B pin
TIOC4D pin
When BDC = 1, N = 1, P = 1, FB = 1, output active level = high
Figure 11.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2)
(r)
A/D Converter Start Request Setting
In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3
compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels
3 and 4.
When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started
at the crest of the TCNT_3 count.
A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable
register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the
TTGE2 bit in TIER_4 to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 601 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
Interrupt Skipping in Complementary PWM Mode
Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up
to seven times by making settings in the timer interrupt skipping set register (TITCR).
Transfers from a buffer register to a temporary register or a compare register can be skipped in
coordination with interrupt skipping by making settings in the timer buffer transfer register
(TBTER). For the linkage with buffer registers, refer to description (c), Buffer Transfer Control
Linked with Interrupt Skipping, below.
A/D converter start requests generated by the A/D converter start request delaying function can
also be skipped in coordination with interrupt skipping by making settings in the timer A/D
converter request control register (TADCR). For the linkage with the A/D converter start request
delaying function, refer to section 11.4.9, A/D Converter Start Request Delaying Function.
The setting of the timer interrupt skipping setting register (TITCR) must be done while the
TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along
with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never
occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to
clear the skipping counter.
(a)
Example of Interrupt Skipping Operation Setting Procedure
Figure 11.73 shows an example of the interrupt skipping operation setting procedure. Figure 11.74
shows the periods during which interrupt skipping count can be changed.
[1] Set bits T3AEN and T4VEN in the timer interrupt
skipping set register (TITCR) to 0 to clear the
skipping counter.
Interrupt skipping
Clear interrupt skipping counter
[1]
Set skipping count and
enable interrupt skipping
[2]
[2] Specify the interrupt skipping count within the
range from 0 to 7 times in bits 3ACOR2 to
3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and
enable interrupt skipping through bits T3AEN and
T4VEN.
Note: The setting of TITCR must be done while the
TGIA_3 and TCIV_4 interrupt requests are
disabled by the settings of TIER_3
and TIER_4 along with under the conditions in
which TGFA_3 and TCFV_4 flag settings by
compare match never occur.
Before changing the skipping count, be sure to
clear the T3AEN and T4VEN bits to 0 to clear
the skipping counter.
Figure 11.73 Example of Interrupt Skipping Operation Setting Procedure
Page 602 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4
Period during which
changing skipping count
can be performed
Period during which
changing skipping count
can be performed
Period during which
changing skipping count
can be performed
Period during which
changing skipping count
can be performed
Figure 11.74 Periods during which Interrupt Skipping Count can be Changed
(b)
Example of Interrupt Skipping Operation
Figure 11.75 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping
count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping
set register (TITCR).
Interrupt skipping period
Interrupt skipping period
TGIA_3 interrupt
flag set signal
Skipping counter
00
01
02
03
00
01
02
03
TGFA_3 flag
Figure 11.75 Example of Interrupt Skipping Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 603 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(c)
SH7280 Group, SH7243 Group
Buffer Transfer Control Linked with Interrupt Skipping
In complementary PWM mode, whether to transfer data from a buffer register to a temporary
register and whether to link the transfer with interrupt skipping can be specified with the BTE1
and BTE0 bits in the timer buffer transfer set register (TBTER).
Figure 11.76 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and
BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the
temporary register.
Figure 11.77 shows an example of operation when buffer transfer is linked with interrupt skipping
(BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer
register outside the buffer transfer-enabled period. Depending on the timing of interrupt generation
and writing to the buffer register, the timing of transfer from the buffer register to the temporary
register and from the temporary register to the general register is one of two types.
Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the
timer interrupt skipping set register (TITCR). Figure 11.78 shows the relationship between the
T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period.
Note: This function must always be used in combination with interrupt skipping.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled,
buffer transfer is never performed.
Page 604 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_3
TCNT_4
data1
Bit BTE0 in TBTER
Bit BTE1 in TBTER
Buffer register
Data1
Data2
(1)
Temporary register
(3)
Data*
Data2
(2)
General register
Data*
Data2
Buffer transfer is suppressed
[Legend]
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period
(bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively).
(2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period.
(3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register.
Note: * When buffer transfer at the crest is selected.
Figure 11.76 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and
BTE0 = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 605 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt
TGIA_3 interrupt generation
TGIA_3 interrupt generation
TCNT_3
TCNT_4
Buffer register rewrite timing
Buffer register rewrite timing
Buffer
transfer-enabled
period
2
TITCR[6:4]
0
TITCNT[6:4]
1
2
0
1
Buffer register
Data
Data1
Data2
Temporary
register
Data
Data1
Data2
Data
Data1
Data2
General register
(2) When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt
TGIA_3 interrupt generation
TGIA_3 interrupt generation
TCNT_3
TCNT_4
Buffer register rewrite timing
Buffer
transfer-enabled
period
TITCR[6:4]
TITCNT[6:4]
2
0
1
2
0
1
Buffer register
Data
Data1
Temporary
register
Data
Data1
General register
Data
Data1
Note: * Buffer transfer at the crest is selected.
The skipping count is set to two.
T3AEN is set to 1.
Figure 11.77 Example of Operation when Buffer Transfer is Linked with Interrupt
Skipping (BTE1 = 1 and BTE0 = 0)
Page 606 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Skipping counter 3ACNT
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
0
Skipping counter 4VCNT
1
0
2
1
3
2
0
3
1
0
2
1
3
2
0
3
Buffer transfer-enabled period
(T3AEN is set to 1)
Buffer transfer-enabled period
(T4VEN is set to 1)
Buffer transfer-enabled period
(T3AEN and T4VEN are set to 1)
Note: * The skipping count is set to three.
Figure 11.78 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer
Transfer-Enabled Period
(4)
Complementary PWM Mode Output Protection Function
Complementary PWM mode output has the following protection functions.
(a)
Register and Counter Miswrite Prevention Function
With the exception of the buffer registers, which can be rewritten at any time, access by the CPU
can be enabled or disabled for the mode registers, control registers, compare registers, and
counters used in complementary PWM mode by means of the RWE bit in the timer read/write
enable register (TRWER). The applicable registers are some (21 in total) of the registers in
channels 3 and 4 shown in the following:
• TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and
TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3
and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR.
This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to
the mode registers, control registers, and counters. When the applicable registers are read in the
access-disabled state, undefined values are returned. Writing to these registers is ignored.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 607 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
SH7280 Group, SH7243 Group
Halting of PWM Output by External Signal
The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting
specified external signals. There are four external signal input pins.
See section 13, Port Output Enable 2 (POE2), for details.
(c)
Halting of PWM Output by Oscillation Stop
The 6-phase PWM output pins can detect the clock stop and set the output pin automatically to the
high-impedance state. However, the pin state is not guaranteed when the clock starts oscillation
again.
See section 4.7, Oscillation Stop Detection, for details.
11.4.9
A/D Converter Start Request Delaying Function
A/D converter start requests can be issued in channel 4 by making settings in the timer A/D
converter start request control register (TADCR), timer A/D converter start request cycle set
registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4).
The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or
TADCORB_4, and when their values match, the function issues a respective A/D converter start
request (TRG4AN or TRG4BN).
A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
TADCR.
• Example of Procedure for Specifying A/D Converter Start Request Delaying Function
Figure 11.79 shows an example of procedure for specifying the A/D converter start request
delaying function.
Page 608 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
[1] Set the cycle in the timer A/D converter start request cycle
buffer register (TADCOBRA_4 or TADCOBRB_4) and timer
A/D converter start request cycle register (TADCORA_4 or
TADCORB_4). (The same initial value must be specified in
the cycle buffer register and cycle register.)
A/D converter start request
delaying function
Set A/D converter start request cycle [1]
• Set the timing of transfer
from cycle set buffer register
• Set linkage with interrupt skipping
• Enable A/D converter start
request delaying function
A/D converter start request
delaying function
[2]
[2] Use bits BF1 and BF2 in the timer A/D converter start
request control register (TADCR) to specify the timing of
transfer from the timer A/D converter start request cycle
buffer register to A/D converter start request cycle register.
• Specify whether to link with interrupt skipping through bits
ITA3AE, ITA4VE, ITB3AE, and ITB4VE.
• Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable
A/D conversion start requests (TRG4AN or TRG4BN).
Notes: 1. Perform TADCR setting while TCNT_4 is stopped.
2. Do not set BF1 to 1 when complementary PWM mode
is not selected.
3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE,
DT4AE, or DT4BE to 1 when complementary PWM
mode is not selected.
Figure 11.79 Example of Procedure for Specifying A/D Converter
Start Request Delaying Function
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 609 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
• Basic Operation Example of A/D Converter Start Request Delaying Function
Figure 11.80 shows a basic example of A/D converter request signal (TRG4AN) operation
when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter
start request signal is output during TCNT_4 down-counting.
Transfer from cycle buffer
register to cycle register
Transfer from cycle buffer
register to cycle register
Transfer from cycle buffer
register to cycle register
TADCORA_4
TCNT_4
TADCOBRA_4
A/D converter start request
(TRG4AN)
(Complementary PWM mode)
Figure 11.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
• Buffer Transfer
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer
registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits
in the timer A/D converter start request control register (TADCR_4).
• A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR).
Figure 11.81 shows an example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D
converter start requests are linked with interrupt skipping.
Figure 11.82 shows another example of A/D converter start request signal (TRG4AN)
operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter
start requests are linked with interrupt skipping.
Page 610 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Note: This function must be used in combination with interrupt skipping.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt
skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not
linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR) to 0).
TCNT_4
TADCORA_4
TGIA_3 interrupt
skipping counter
00
TCIV_4 interrupt
skipping counter
01
00
02
01
00
02
01
00
01
TGIA_3 A/D request-enabled
period
TCIV_4 A/D request-enabled
period
A/D converter start request (TRG4AN)
When linked with TGIA_3 and TCIV_4
interrupt skipping
When linked with TGIA_3
interrupt skipping
When linked with TCIV_4
interrupt skipping
Note: *
(UT4AE/DT4AE = 1)
When the interrupt skipping count is set to two.
Figure 11.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
with Interrupt Skipping
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 611 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT_4
TADCORA_4
TGIA_3 interrupt
skipping counter
TCIV_4 interrupt
skipping counter
00
01
00
02
01
00
02
01
00
01
TGIA_3 A/D request-enabled
period
TCIV_4 A/D request-enabled
period
A/D converter start request (TRG4AN)
When linked with TGIA_3 and TCIV_4
interrupt skipping
When linked with TGIA_3
interrupt skipping
When linked with TCIV_4
interrupt skipping
Note: *
UT4AE = 1
DT4AE = 0
When the interrupt skipping count is set to two.
Figure 11.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked
with Interrupt Skipping
Page 612 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.10 MTU2-MTU2S Synchronous Operation
(1)
MTU2-MTU2S Synchronous Counter Start
The counters in the MTU2 and MTU2S which operate at different clock systems can be started
synchronously by making the TCSYSTR settings in the MTU2.
(a)
Example of MTU2-MTU2S Synchronous Counter Start Setting Procedure
Figure 11.83 shows an example of synchronous counter start setting procedure.
[1] Use TSTR registers in the MTU2 and MTU2S and halt the
counters used for synchronous start operation.
MTU2-MTU2S synchronous
counter start
[2] Specify necessary operation with appropriate registers such as
TCR and TMDR.
Stop count operation
[1]
Set the necessary operation
[2]
Set TCSYSTR
[3]
[3] In TCSYSTR in the MTU2, set the bits corresponding to the
counters to be started synchronously to 1. The TSTRs are
automatically set appropriately and the counters start
synchronously.
Notes: 1. Even if a bit in TCSYSTR corresponding to an operating
counter is cleared to 0, the counter will not stop. To stop
the counter, clear the corresponding bit in TSTR to 0
directly.
2. To start channels 3 and 4 in reset-synchronized PWM
mode or complementary PWM mode, make appropriate
settings in TCYSTR according to the TSTR setting for
the respective mode. For details, refer to section 11.4.7,
Reset-Synchronized PWM Mode, and section 11.4.8,
Complementary PWM Mode.
Figure 11.83 Example of Synchronous Counter Start Setting Procedure
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 613 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
Examples of Synchronous Counter Start Operation
Figures 11.84 (1) to (4) show examples of synchronous counter start operation when the clock
frequency ratios between the MTU2 and MTU2S are 1:1, 1:2, 1:3, and 1:4, respectively. In these
examples, the count clock is set to Pφ/1.
MTU2 clock
MTU2S clock
Automatically cleared after
TCSYSTR setting is made
TCSYSTR
H'00
H'51
H'00
MTU2/TSTR
H'00
H'42
MTU2S/TSTR
H'00
H'80
MTU2/TCNT_1
H'0000
H'0001
H'0002
MTU2S/TCNT_4
H'0000
H'0001
H'0002
Figure 11.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S
Clock Frequency Ratio = 1:1)
Page 614 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2 clock
MTU2S clock
Automatically cleared after
TCSYSTR setting is made
TCSYSTR
H'00
H'51
MTU2/TSTR
H'00
MTU2S/TSTR
H'00
MTU2/TCNT_1
H'0000
MTU2S/TCNT_4
H'0000
H'00
H'42
H'80
H'0001
H'0002
H'0002
H'0001
H'0004
H'0003
Figure 11.84 (2) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S
Clock Frequency Ratio = 1:2)
MTU2 clock
MTU2S clock
Automatically cleared after
TCSYSTR setting is made
TCSYSTR
H'00
H'51
H'00
MTU2/TSTR
H'00
H'42
MTU2S/TSTR
H'00
H'80
MTU2/TCNT_1
H'0001
H'0000
H'0002
MTU2S/TCNT_4
H'0002
H'0004
H'0000
H'0001
H'0003
Figure 11.84 (3) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S
Clock Frequency Ratio = 1:3)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 615 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2 clock
MTU2S clock
Automatically cleared after
TCSYSTR setting is made
TCSYSTR
H'00
H'51
H'00
MTU2/TSTR
H'00
H'42
MTU2S/TSTR
H'00
H'80
MTU2/TCNT_1
H'0000
H'0001
H'0002
H'0002 H'0004
MTU2S/TCNT_4
H'0000
H'0001 H'0003
Figure 11.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S
Clock Frequency Ratio = 1:4)
Page 616 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (MTU2-MTU2S
Synchronous Counter Clearing)
The MTU2S counters can be cleared by sources for setting the flags in TSR_0 to TSR_2 in the
MTU2 through the TSYCRS settings in the MTU2S.
(a)
Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting
Source
Figure 11.85 shows an example of procedure for specifying MTU2S counter clearing by MTU2
flag setting source.
[1] Use TSTR registers in the MTU2 and MTU2S and halt the
counters used for this function.
MTU2S counter clearing by
MTU2S flag setting source
Stop count operation
[1]
[2] Use TSYCRS in the MTU2S to specify the flag setting source
to be used for the TCNT_3 and TCNT_4 clearing source.
[3] Start TCNT_3 or TCNT_4 in the MTU2S.
Set TSYCRS
[2]
[4] Start TCNT_0, TCNT_1, or TCNT_2 in the MTU2.
Start channel 3 or 4 in MTU2S
[3]
Note: The TSYCRS setting is ignored while the counter is
stopped. The setting becomes valid after TCNT_3 or
TCNT4 is started.
Start one of channels 0 to 2 in MTU2
[4]
Figure 11.85 Example of Procedure for Specifying MTU2S Counter
Clearing by MTU2 Flag Setting Source
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 617 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
SH7280 Group, SH7243 Group
Examples of MTU2S Counter Clearing Caused by MTU2 Flag Setting Source
Figures 11.86 (1) and 11.86 (2) show examples of MTS2S counter clearing caused by MTU2 flag
setting source.
TSYCRS
H'00
H'80
Compare match between TCNT_0 and TGRA_0
TCNT_0 value in MTU2
TGRA_0
TCNT_0 in MTU2
H'0000
Time
TCNT_4 value in MTU2S
TCNT_4 in MTU2S
H'0000
Time
Figure 11.86 (1) Example of MTU2S Counter Clearing
Caused by MTU2 Flag Setting Source (1)
TSYCRS
H'00
H'F0
TCNT_0 value in MTU2
TGRD_0
TGRB_0
Compare match between TCNT_0 and TGR
TCNT_0 in MTU2
TGRC_0
TGRA_0
H'0000
Time
TCNT_4 value in MTU2S
TCNT_4 in MTU2S
H'0000
Time
Figure 11.86 (2) Example of MTU2S Counter Clearing
Caused by MTU2 Flag Setting Source (2)
Page 618 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.11 External Pulse Width Measurement
The pulse widths of up to three external input lines can be measured in channel 5.
(1)
Example of External Pulse Width Measurement Setting Procedure
[1] Use bits TPSC1 and TPSC0 in TCR to select the
counter clock.
External pulse width
measurement
Select counter clock
[1]
[2] In TIOR, select the high level or low level for the pulse
width measuring condition.
[3] Set bits CST in TSTR to 1 to start count operation.
Select pulse width measuring
conditions
[2]
Start count operation
[3]
Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or
CMPCLR5W in TCNTCMPCLR to 1.
2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in
TIER_5 to 1.
3. The value in TCNT is not captured in TGR.
Figure 11.87 Example of External Pulse Width Measurement Setting Procedure
(2)
Example of External Pulse Width Measurement
Pφ
TIC5U
TCNTU_5
0000
0001 0002 0003 0004 0005 0006 0007
0007 0008 0009 000A 000B
Figure 11.88 Example of External Pulse Width Measurement
(Measuring High Pulse Width)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 619 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
11.4.12 Dead Time Compensation
By measuring the delay of the output waveform and reflecting it to duty, the external pulse width
measurement function can be used as the dead time compensation function while the
complementary PWM is in operation.
Tdead
Upper arm signal
Lower arm signal
Inverter output detection signal
Tdelay
Dead time delay signal
Figure 11.89 Delay in Dead Time in Complementary PWM Operation
Page 620 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Example of Dead Time Compensation Setting Procedure
Figure 11.90 shows an example of dead time compensation setting procedure by using three
counters in channel 5.
[1] Place channels 3 and 4 in complementary PWM mode. For
details, refer to section 11.4.8, Complementary PWM Mode.
Complementary PWM mode
External pulse width
measurement
[1]
[2] Specify the external pulse width measurement function for
the target TIOR in channel 5. For details, refer to section
11.4.11, External Pulse Width Measurement.
[2]
[3] Set bits CST3 and CST4 in TSTR and bits CST5U, CST5V,
and CST5W in TSTR2 to 1 to start count operation.
Start count operation in
channels 3 to 5
TCNT_5 input capture occurs
Interrupt processing
[3]
[4] *
[5]
[4] When the capture condition specified in TIOR is satisfied,
the TCNT_5 value is captured in TGR_5.
[5] For U-phase dead time compensation, when an interrupt is
generated at the crest (TGIA_3) or trough (TCIV_4) in
complementary PWM mode, read the TGRU_5 value,
calculate the difference in time in TGRB_3, and write the
corrected value to TGRD_3 in the interrupt processing.
For the V phase and W phase, read the TGRV_5 and
TGRW_5 values and write the corrected values to TGRC_4
and TGRD_4, respectively, in the same way as for U-phase
compensation.
The TCNT_5 value should be cleared through the
TCNTCMPCLR setting or by software.
Notes: The PFC settings must be completed in advance.
* As an interrupt flag is set under the capture condition
specified in TIOR, do not enable interrupt requests in
TIER_5.
Figure 11.90 Example of Dead Time Compensation Setting Procedure
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 621 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
MTU
Complementary
PWM output
ch5
Dead time
delay input
≠
Level conversion
ch3/4
DC
+
W
Inverter output
monitor signals
V
U
W
Motor
V
U
W
U
V
Figure 11.91 Example of Motor Control Circuit Configuration
Page 622 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation
The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough
during complementary PWM operation. The timing for capturing in TGR can be selected by
TIOR.
Figure 11.92 shows an example in which TCNT is used as a free-running counter without being
cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or
both crest and trough).
TGRA_4
Tdead
Upper arm signal
Lower arm signal
Inverter output monitor signal
Tdelay
Dead time delay signal
Up-count/down-count signal (udflg)
TCNT[15:0]
TGR[15:0]
3DE7
3E5B
3DE7
3ED3
3E5B
3ED3
3F37
3FAF
3F37
3FAF
Figure 11.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 623 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.5
Interrupt Sources
11.5.1
Interrupt Sources and Priorities
SH7280 Group, SH7243 Group
There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 6, Interrupt Controller (INTC).
Table 11.57 lists the MTU2 interrupt sources.
Page 624 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.57 MTU2 Interrupts
Interrupt DMAC
Flag
Activation
Priority
TGIA_0 TGRA_0 input capture/compare match
TGFA_0
Possible
High
TGIB_0 TGRB_0 input capture/compare match
TGFB_0
Not possible
TGIC_0 TGRC_0 input capture/compare match
TGFC_0
Not possible
TGID_0 TGRD_0 input capture/compare match
TGFD_0
Not possible
TCIV_0
TCFV_0
Not possible
TGIE_0 TGRE_0 compare match
TGFE_0
Not possible
TGIF_0
Channel
Name
0
1
2
3
4
5
Interrupt Source
TCNT_0 overflow
TGFF_0
Not possible
TGIA_1 TGRA_1 input capture/compare match
TGRF_0 compare match
TGFA_1
Possible
TGIB_1 TGRB_1 input capture/compare match
TGFB_1
Not possible
TCIV_1
TCNT_1 overflow
TCFV_1
Not possible
TCIU_1
TCNT_1 underflow
TCFU_1
Not possible
TGIA_2 TGRA_2 input capture/compare match
TGFA_2
Possible
TGIB_2 TGRB_2 input capture/compare match
TGFB_2
Not possible
TCIV_2
TCNT_2 overflow
TCFV_2
Not possible
TCIU_2
TCNT_2 underflow
TCFU_2
Not possible
TGIA_3 TGRA_3 input capture/compare match
TGFA_3
Possible
TGIB_3 TGRB_3 input capture/compare match
TGFB_3
Not possible
TGIC_3 TGRC_3 input capture/compare match
TGFC_3
Not possible
TGID_3 TGRD_3 input capture/compare match
TGFD_3
Not possible
TCIV_3
TCFV_3
Not possible
TGIA_4 TGRA_4 input capture/compare match
TGFA_4
Possible
TGIB_4 TGRB_4 input capture/compare match
TGFB_4
Not possible
TGIC_4 TGRC_4 input capture/compare match
TGFC_4
Not possible
TGID_4 TGRD_4 input capture/compare match
TGFD_4
Not possible
TCIV_4
TCNT_4 overflow/underflow
TCFV_4
Not possible
TGIU_5 TGRU_5 input capture/compare match
TGFU_5
Not possible
TGIV_5 TGRV_5 input capture/compare match
TGFV_5
Not possible
TCNT_3 overflow
TGIW_5 TGRW_5 input capture/compare match TGFW_5 Not possible
Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 625 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
SH7280 Group, SH7243 Group
Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1
by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt
request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match
interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and
three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of
an input capture.
(2)
Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to
1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing
the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel.
(3)
Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to
1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing
the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.
11.5.2
(1)
DMAC and DTC Activation
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt in each channel and
the overflow interrupt of channel 4. For details, see section 8, Data Transfer Controller (DTC).
In the MTU2, a total of twenty input capture/compare match interrupts and overflow interrupts can
be used as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2,
five for channel 4 and three for channel 5.
(2)
DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel.
For details, see section 10, Direct Memory Access Controller (DMAC).
In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC
activation sources, one each for channels 0 to 4.
When the DMAC is activation by MTU2, the activation sources are cleared when the DMAC
requests the internal bus mastership. Accordingly, depending on the internal bus state, a wait state
Page 626 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
of the DMAC transfer may be generated even if the activation sources are cleared. Also, when
transferring DMAC burst by MTU2, the setting of bus function extension register (BSCEHR) is
required. See section 9.4.8, Bus Function Extending Register (BSCEHR), for details.
11.5.3
A/D Converter Activation
The A/D converter can be activated by one of the following three methods in the MTU2. Table
11.58 shows the relationship between interrupt sources and A/D converter start request signals.
(1)
A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4
Trough in Complementary PWM Mode
The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in
each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in
TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 =
H'0000).
A/D converter start request signal TRGAN is issued to the A/D converter under either one of the
following conditions.
• When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare
match on a particular channel while the TTGE bit in TIER is set to 1
• When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary
PWM operation while the TTGE2 bit in TIER_4 is set to 1
When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is
selected as the trigger in the A/D converter, A/D conversion will start.
(2)
A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0
The A/D converter can be activated by generating A/D converter start request signal TRG0N
when a compare match occurs between TCNT_0 and TGRE_0 in channel 0.
When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between
TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter
start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the
MTU2 is selected as the trigger in the A/D converter, A/D conversion will start.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 627 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
SH7280 Group, SH7243 Group
A/D Converter Activation by A/D Converter Start Request Delaying Function
The A/D converter can be activated by generating A/D converter start request signal TRG4AN or
TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE,
DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set
to 1. For details, refer to section 11.4.9, A/D Converter Start Request Delaying Function.
A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the
trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is
selected as the trigger in the A/D converter when TRG4BN is generated.
Table 11.58 Interrupt Sources and A/D Converter Start Request Signals
Target Registers
Interrupt Source
A/D Converter Start Request
Signal
TGRA_0 and TCNT_0
Input capture/compare match
TRGAN
TGRA_1 and TCNT_1
TGRA_2 and TCNT_2
TGRA_3 and TCNT_3
TGRA_4 and TCNT_4
TCNT_4
TCNT_4 Trough in
complementary PWM mode
TGRE_0 and TCNT_0
Compare match
TRG0N
TADCORA and TCNT_4
TRG4AN
TADCORB and TCNT_4
TRG4BN
Page 628 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.6
Operation Timing
11.6.1
Input/Output Timing
(1)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT Count Timing
Figures 11.93 and 94 show TCNT count timing in internal clock operation, and figure 11.95
shows TCNT count timing in external clock operation (normal mode), and figure 11.96 shows
TCNT count timing in external clock operation (phase counting mode).
Pφ
Falling edge
Internal clock
Rising edge
TCNT input
clock
TCNT
N-1
N
N+1
Figure 11.93 Count Timing in Internal Clock Operation (Channels 0 to 4)
Pφ
Rising edge
Internal clock
TCNT input
clock
TCNT
N-1
N
Figure 11.94 Count Timing in Internal Clock Operation (Channel 5)
Pφ
External clock
Falling edge
Rising edge
TCNT input
clock
TCNT
N-1
N
N+1
Figure 11.95 Count Timing in External Clock Operation (Channels 0 to 4)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 629 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
External
clock
Falling edge
Rising edge
TCNT input
clock
N-1
TCNT
N
N-1
Figure 11.96 Count Timing in External Clock Operation (Phase Counting Mode)
(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point
at which the count value matched by TCNT is updated). When a compare match signal is
generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
After a match between TCNT and TGR, the compare match signal is not generated until the
TCNT input clock is generated.
Figure 11.97 shows output compare output timing (normal mode and PWM mode) and figure
11.98 shows output compare output timing (complementary PWM mode and reset synchronous
PWM mode).
Pφ
TCNT input
clock
TCNT
TGR
N
N+1
N
Compare
match signal
TIOC pin
Figure 11.97 Output Compare Output Timing (Normal Mode/PWM Mode)
Page 630 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TIOC pin
Figure 11.98 Output Compare Output Timing
(Complementary PWM Mode/Reset Synchronous PWM Mode)
(3)
Input Capture Signal Timing
Figure 11.99 shows input capture signal timing.
Pφ
Input capture
input
Input capture
signal
N
TCNT
N+1
N+2
N
TGR
N+2
Figure 11.99 Input Capture Input Signal Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 631 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Timing for Counter Clearing by Compare Match/Input Capture
Figures 11.100 and 101 show the timing when counter clearing on compare match is specified,
and figure 11.102 shows the timing when counter clearing on input capture is specified.
Pφ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 11.100 Counter Clear Timing (Compare Match) (Channels 0 to 4)
Pφ
Compare
match signal
Counter
clear signal
TCNT
N-1
TGR
N
H'0000
Figure 11.101 Counter Clear Timing (Compare Match) (Channel 5)
Page 632 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
Input capture
signal
Counter clear
signal
TCNT
H'0000
N
N
TGR
Figure 11.102 Counter Clear Timing (Input Capture) (Channels 0 to 5)
(5)
Buffer Operation Timing
Figures 11.103 to 11.105 show the timing in buffer operation.
Pφ
TCNT
n
n+1
TGRA,
TGRB
n
N
TGRC,
TGRD
N
Compare
match buffer
signal
Figure 11.103 Buffer Operation Timing (Compare Match)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 633 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
Input capture
signal
TCNT
N
N+1
TGRA,
TGRB
n
N
N+1
n
N
TGRC,
TGRD
Figure 11.104 Buffer Operation Timing (Input Capture)
Pφ
n
H'0000
TGRA, TGRB,
TGRE
n
N
TGRC, TGRD,
TGRF
N
TCNT
TCNT clear
signal
Buffer transfer
signal
Figure 11.105 Buffer Transfer Timing (when TCNT Cleared)
Page 634 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(6)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Buffer Transfer Timing (Complementary PWM Mode)
Figures 11.106 to 11.108 show the buffer transfer timing in complementary PWM mode.
Pφ
H'0000
TCNTS
TGRD_4
write signal
Temporary register
transfer signal
Buffer
register
n
Temporary
register
n
N
N
Figure 11.106 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop)
Pφ
P-x
TCNTS
P
H'0000
TGRD_4
write signal
Buffer
register
Temporary
register
n
N
n
N
Figure 11.107 Transfer Timing from Buffer Register to Temporary Register
(TCNTS Operating)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 635 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNTS
P−1
P
H'0000
Buffer transfer
signal
Temporary
register
N
Compare
register
n
N
Figure 11.108 Transfer Timing from Temporary Register to Compare Register
11.6.2
(1)
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match
Figures 11.109 and 110 show the timing for setting of the TGF flag in TSR on compare match,
and TGI interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 11.109 TGI Interrupt Timing (Compare Match)
Page 636 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNT input
clock
TCNT
N
N-1
TGR
N
Compare
match signal
TGF flag
TGI interrupt
Figure 11.110 TGI Interrupt Timing (Compare Match) (Channel 5)
(2)
TGF Flag Setting Timing in Case of Input Capture
Figures 11.111 and 112 show the timing for setting of the TGF flag in TSR on input capture, and
TGI interrupt request signal timing.
Pφ
Input capture
signal
TCNT
TGR
N
N
TGF flag
TGI interrupt
Figure 11.111 TGI Interrupt Timing (Input Capture) (Channels 0 to 4)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 637 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 11.112 TGI Interrupt Timing (Input Capture) (Channel 5)
(3)
TCFV Flag/TCFU Flag Setting Timing
Figure 11.113 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV
interrupt request signal timing.
Figure 11.114 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU
interrupt request signal timing.
Pφ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 11.113 TCIV Interrupt Setting Timing
Page 638 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 11.114 TCIU Interrupt Setting Timing
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is
activated, the flag is cleared automatically. Figures 11.115 and 116 show the timing for status flag
clearing by the CPU, and figure 11.117 shows the timing for status flag clearing by the DMAC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 11.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 639 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TSR write cycle
T1
T2
Pφ
TSR address
Address
Write signal
Status flag
Interrupt
request signal
Figure 11.116 Timing for Status Flag Clearing by CPU (Channel 5)
DMAC read cycle
DMAC write cycle
Source address
Destination
address
Pφ, Bφ
Address
Status flag
Interrupt
request signal
Flag clear
signal
Figure 11.117 Timing for Status Flag Clearing by DTC Activation (Channels 0 to 4)
Page 640 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
DTC read cycle
DTC write cycle
Source address
Destination address
Pφ, Bφ
Address
Status flag
Interrupt
request signal
Flag clear
signal
Figure 11.118 Timing for Status Flag Clearing by DTC Activation (Channel 5)
DMAC
read cycle
DMAC
write cycle
Source
address
Destination
address
Pφ, Bφ
Address
Status flag
Interrupt
request signal
Flag clear
signal
Figure 11.119 Timing for Status Flag Clearing by DMAC Activation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 641 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7
Usage Notes
11.7.1
Module Standby Mode Setting
MTU2 operation can be disabled or enabled using the standby control register. The initial setting
is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode.
For details, refer to section 28, Power-Down Modes.
11.7.2
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.120 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
differdifference Overlap ence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 11.120 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Page 642 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.7.3
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
• Channel 0 to 4
Pφ
f=
(N + 1)
• Channel 5
Pφ
f=
N
Where
11.7.4
f:
Pφ:
N:
Counter frequency
Peripheral clock operating frequency
TGR set value
Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 11.121 shows the timing in this case.
TCNT write cycle
T2
T1
Pφ
Address
TCNT address
Write signal
Couter area
signal
TCNT
N
H'0000
Figure 11.121 Contention between TCNT Write and Clear Operations
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 643 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.5
Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 11.122 shows the timing in this case.
TCNT write cycle
T1
T2
Pφ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 11.122 Contention between TCNT Write and Increment Operations
Page 644 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.7.6
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the
compare match signal is also generated.
Figure 11.123 shows the timing in this case.
TGR write cycle
T2
T1
Pφ
TGR address
Address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 11.123 Contention between TGR Write and Compare Match
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 645 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.7
Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation is the data after write.
Figure 11.124 shows the timing in this case.
TGR write cycle
T1
T2
Pφ
Buffer register
address
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register write data
Buffer register
TGR
N
M
N
Figure 11.124 Contention between Buffer Register Write and Compare Match
Page 646 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.7.8
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 11.125 shows the timing in this case.
TGR write cycle
T1
T2
Pφ
Buffer register
address
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR
Buffer register write data
N
M
N
Figure 11.125 Contention between Buffer Register Write and TCNT Clear
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 647 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.9
Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 11.126 and 127 show the timing in this case.
TGR read cycle
T1
T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
M
N
Internal data
bus
N
Figure 11.126 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle
T1
T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
Internal data
bus
N
M
M
Figure 11.127 Contention between TGR Read and Input Capture (Channel 5)
Page 648 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel
5, write to TGR is performed and the input capture signal is generated.
Figures 11.128 and 129 show the timing in this case.
TGR write cycle
T1
T2
Pφ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
M
TGR
Figure 11.128 Contention between TGR Write and Input Capture (Channels 0 to 4)
TGR write cycle
T1
T2
Pφ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
TGR write data
TGR
N
Figure 11.129 Contention between TGR Write and Input Capture (Channel 5)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 649 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.11 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.130 shows the timing in this case.
Buffer register write cycle
T2
T1
Pφ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer register
N
M
N
M
Figure 11.130 Contention between Buffer Register Write and Input Capture
11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection
With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs
during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2
write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this
point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued.
Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0,
TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input
capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture
operation. The timing is shown in figure 11.131.
For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT
clearing.
Page 650 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
TCNT write cycle
T1
T2
Pφ
Address
TCNT_2 address
Write signal
TCNT_2
H'FFFE
H'FFFF
N
N+1
TCNT_2 write data
TGRA_2 to
TGRB_2
H'FFFF
Ch2 comparematch signal A/B
Disabled
TCNT_1 input
clock
TCNT_1
M
TGRA_1
M
Ch1 comparematch signal A
TGRB_1
N
M
Ch1 input capture
signal B
TCNT_0
P
TGRA_0 to
TGRD_0
Q
P
Ch0 input capture
signal A to D
Figure 11.131 TCNT_2 Write and Overflow/Underflow Contention with Cascade
Connection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 651 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.13 Counter Value during Complementary PWM Mode Stop
When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM
mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000.
When restarting complementary PWM mode, counting begins automatically from the initialized
state. This explanatory diagram is shown in figure 11.132.
When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to
the initial values.
TGRA_3
TCDR
TCNT_3
TCNT_4
TDDR
H'0000
Complementary PWM
mode operation
Complementary PWM
mode operation
Counter
operation stop
Complementary
PMW restart
Figure 11.132 Counter Value during Complementary PWM Mode Stop
11.7.14 Buffer Operation Setting in Complementary PWM Mode
In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting
register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3,
TGRA_4, and TGRB_4).
In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit
settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a
buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for
TGRA_4, and TCBR functions as the TCDR's buffer register.
Page 652 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4
to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is
set to 1.
In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA
and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3
functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer
register for TGRA_4.
The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are
operating as buffer registers.
Figure 11.133 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with
TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.
TGRA_3
TCNT3
Point a
TGRC_3
Buffer transfer with
compare match A3
TGRA_3,
TGRC_3
TGRB_3, TGRA_4,
TGRB_4
TGRD_3, TGRC_4,
TGRD_4
Point b
TGRB_3, TGRD_3,
TGRA_4, TGRC_4,
TGRB_4, TGRD_4
H'0000
TIOC3A
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TGFC
TGFD
Not set
Not set
Figure 11.133 Buffer Operation and Compare-Match Flags
in Reset Synchronous PWM Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 653 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.16 Overflow Flags in Reset Synchronous PWM Mode
When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3
bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the
TCR_3 setting.
In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when
specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up
to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both
cleared. At this point, TSR's overflow flag TCFV bit is not set.
Figure 11.134 shows a TCFV bit operation example in reset synchronous PWM mode with a set
value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified
without synchronous setting for the counter clear source.
Counter cleared by compare match 3A
TGRA_3
(H'FFFF)
TCNT_3 = TCNT_4
H'0000
TCFV_3
TCFV_4
Not set
Not set
Figure 11.134 Reset Synchronous PWM Mode Overflow Flag
Page 654 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.17 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.135 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter clear
signal
TGF
TCFV
Disabled
Figure 11.135 Contention between Overflow and Counter Clearing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 655 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.18 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.136 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
Pφ
TCNT address
Address
Write signal
TCNT write data
TCNT
TCFV flag
H'FFFF
M
Disabled
Figure 11.136 Contention between TCNT Write and Overflow
11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode
When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D,
TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct.
When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to
registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level
output, then set an initial register value of H'00 before making the mode transition.
When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to
normal operation, then initialize the output pins to low level output and set an initial register value
of H'00 before making the transition to reset-synchronized PWM mode.
Page 656 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode
When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the
PWM waveform output level is set with the OLSP and OLSN bits in the timer output control
register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode,
TIOR should be set to H'00.
11.7.21 Interrupts in Module Standby Mode
If module standby mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be
disabled before entering module standby mode.
11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection
When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade
connection, the cascade counter value cannot be captured successfully even if input-capture input
is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the
input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when
external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization
with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the
count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count
value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000
should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of
TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred.
The MTU2 has a new function that allows simultaneous capture of TCNT_1 and TCNT_2 with a
single input-capture as the trigger. This function allows reading of the 32-bit counter such that
TCNT_1 and TCNT_2 are captured at the same time. For details, see section 11.3.8, Timer Input
Capture Control Register (TICCR).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 657 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.23 Note on Output Waveform Control at Synchronous Counter Clearing in
Complementary PWM Mode
If either condition (1) or (2) is satisfied when output waveform control at synchronous counter
clearing is enabled (WRE bit in TWCR is 1) in complementary PWM mode, the following
phenomena occur.
• The dead time of the PWM output pins becomes shorter (or disappears).
• An active level is output from a PWM reverse phase output pin during a period other than the
active level output period.
Condition (1)
In the initial output suppression period (10), synchronous clearing is performed
while the PWM output is in the dead time (figure 11.137).
Condition (2)
In the initial output suppression periods (10) and (11), synchronous clearing is
performed while TGRB_3 ≤ TDDR, TGRA_4 ≤ TDDR, or TGRB_4 ≤ TDDR is
satisfied (figure 11.138).
Synchronous clearing
TGRA_3
(10)
(10)
(11)
(11)
TCNT3
Tb period
Tb period
TCNT4
TGR
TDDR
0
PWM output (positive phase)
PWM output (negative phase)
TDDR
Dead time becomes shorter
Initial output is suppressed
Dead time
Note: PWM output is active-low.
Figure 11.137 Example of Synchronous Clearing under Condition (1)
Page 658 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Synchronous clearing
TGRA_3
(10)
(11)
(10)
(11)
TCNT3
Tb period
Tb period
TCNT4
TDDR
TGR
0
PWM output (positive phase)
PWM output (negative phase)
Though there is no active-level output period,
an active-level is output at synchronous clearing
Dead time disappears
Initial output is suppressed
Dead time
Note: PWM output is active-low.
Figure 11.138 Example of Synchronous Clearing under Condition (2)
The above phenomena can be avoided by the following method.
Perform synchronous clearing after compare registers TGRB_3, TGRA_4, and TGRB_4 are all set
to be at least twice of the setting of the timer dead time data register (TDDR).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 659 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.8
MTU2 Output Pin Initialization
11.8.1
Operating Modes
SH7280 Group, SH7243 Group
The MTU2 has the following six operating modes. Waveform output is possible in all of these
modes.
•
•
•
•
•
•
Normal mode (channels 0 to 4)
PWM mode 1 (channels 0 to 4)
PWM mode 2 (channels 0 to 2)
Phase counting modes 1 to 4 (channels 1 and 2)
Complementary PWM mode (channels 3 and 4)
Reset-synchronized PWM mode (channels 3 and 4)
The MTU2 output pin initialization method for each of these modes is described in this section.
11.8.2
Reset Start Operation
The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2
pin function selection is performed by the pin function controller (PFC), when the PFC is set, the
MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC
immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When
the active level is low, the system will operate at this point, and therefore the PFC setting should
be made after initialization of the MTU2 output pins is completed.
Note: Channel number and port notation are substituted for *.
Page 660 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
11.8.3
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation in Case of Re-Setting Due to Error during Operation, etc.
If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is
performed by switching the pin output to port output with the PFC and outputting the inverse of
the active level. For large-current pins, output can also be cut by hardware, using port output
enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc.,
and the procedures for restarting in a different mode after re-setting, are shown below.
The MTU2 has six operating modes, as stated above. There are thus 36 mode transition
combinations, but some transitions are not available with certain channel and mode combinations.
Possible mode transition combinations are shown in table 11.59.
Table 11.59 Mode Transition Combinations
After
Before
Normal
PWM1
PWM2
PCM
CPWM
RPWM
Normal
(1)
(2)
(3)
(4)
(5)
(6)
PWM1
(7)
(8)
(9)
(10)
(11)
(12)
PWM2
(13)
(14)
(15)
(16)
None
None
PCM
(17)
(18)
(19)
(20)
None
None
CPWM
(21)
(22)
None
None
(23) (24)
(25)
RPWM
(26)
(27)
None
None
(28)
(29)
[Legend]
Normal: Normal mode
PWM1: PWM mode 1
PWM2: PWM mode 2
PCM: Phase counting modes 1 to 4
CPWM: Complementary PWM mode
RPWM: Reset-synchronized PWM mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 661 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.8.4
SH7280 Group, SH7243 Group
Overview of Initialization Procedures and Mode Transitions in Case of Error
during Operation, etc.
• When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output
level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of
a TIOR setting.
• In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR
will not initialize the pins. If initialization is required, carry it out in normal mode, then switch
to PWM mode 1.
• In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will
not initialize the pins. If initialization is required, carry it out in normal mode, then switch to
PWM mode 2.
• In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting
TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode,
carry out initialization, then set buffer mode again.
• In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not
initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization,
then set buffer mode again.
• When making a transition to a mode (CPWM, RPWM) in which the pin output level is
selected by the timer output control register (TOCR) setting, switch to normal mode and
perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable
channel 3 and 4 output with the timer output master enable register (TOER). Then operate the
unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER
setting).
Note: Channel number is substituted for * indicated in this article.
Pin initialization procedures are described below for the numbered combinations in table 11.59.
The active level is assumed to be low.
Page 662 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Normal Mode
Figure 11.139 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in normal mode after re-setting.
1
2
3
RESET TMDR TOER
(normal) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.139 Error Occurrence in Normal Mode, Recovery in Normal Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
After a reset, MTU2 output is low and ports are in the high-impedance state.
After a reset, the TMDR setting is for normal mode.
For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
Set MTU2 output with the PFC.
The count operation is started by TSTR.
Output goes low on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR.
Not necessary when restarting in normal mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 663 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(2)
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in PWM Mode 1
Figure 11.140 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in PWM mode 1 after re-setting.
1
2
3
RESET TMDR TOER
(normal) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM1) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC*A
Not initialized (TIOC*B)
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.140 Error Occurrence in Normal Mode, Recovery in PWM Mode 1
1 to 10 are the same as in figure 11.139.
11. Set PWM mode 1.
12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If
initialization is required, initialize in normal mode, then switch to PWM mode 1.)
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
Page 664 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in PWM Mode 2
Figure 11.141 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in PWM mode 2 after re-setting.
1
2
3
RESET TMDR TOER
(normal) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM2) (1 init (MTU2) (1)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.141 Error Occurrence in Normal Mode, Recovery in PWM Mode 2
1 to 10 are the same as in figure 11.139.
11. Set PWM mode 2.
12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If
initialization is required, initialize in normal mode, then switch to PWM mode 2.)
13. Set MTU2 output with the PFC.
14. Operation is restarted by TSTR.
Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not
necessary.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 665 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(4)
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Phase Counting Mode
Figure 11.142 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in phase counting mode after re-setting.
1
2
3
RESET TMDR TOER
(normal) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
Error
PFC TSTR TMDR
occurs (PORT) (0)
(PCM)
12
13
14
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.142 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode
1 to 10 are the same as in figure 11.139.
11.
12.
13.
14.
Set phase counting mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is
not necessary.
Page 666 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(5)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Complementary PWM Mode
Figure 11.143 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in complementary PWM mode after re-setting.
12
6
7
8
9
10
11
1
2
3
4
5
14
15
(16)
(17)
(18)
13
RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0)
(0 init (disabled) (0)
(normal) (1)
(1 init (MTU2) (1)
(CPWM) (1) (MTU2) (1)
0 out)
0 out)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.143 Error Occurrence in Normal Mode,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 11.139.
11.
12.
13.
14.
15.
16.
17.
18.
Initialize the normal mode waveform generation section with TIOR.
Disable operation of the normal mode waveform generation section with TIOR.
Disable channel 3 and 4 output with TOER.
Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
Set complementary PWM.
Enable channel 3 and 4 output with TOER.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 667 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(6)
Operation when Error Occurs during Normal Mode Operation, and Operation is
Restarted in Reset-Synchronized PWM Mode
Figure 11.144 shows an explanatory diagram of the case where an error occurs in normal mode
and operation is restarted in reset-synchronized PWM mode after re-setting.
1
2
3
4
5
6
RESET TMDR TOER TIOR
PFC TSTR
(normal) (1)
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
Error
PFC TSTR
occurs (PORT) (0)
11
12
14
15
16
17
18
13
TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
(0 init (disabled) (0)
(RPWM) (1) (MTU2) (1)
0 out)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.144 Error Occurrence in Normal Mode,
Recovery in Reset-Synchronized PWM Mode
1 to 13 are the same as in figure 11.139.
14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
15. Set reset-synchronized PWM.
16. Enable channel 3 and 4 output with TOER.
17. Set MTU2 output with the PFC.
18. Operation is restarted by TSTR.
Page 668 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(7)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Normal Mode
Figure 11.145 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in normal mode after re-setting.
1
2
3
RESET TMDR TOER
(PWM1) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC*A
Not initialized (TIOC*B)
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.145 Error Occurrence in PWM Mode 1, Recovery in Normal Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
After a reset, MTU2 output is low and ports are in the high-impedance state.
Set PWM mode 1.
For channels 3 and 4, enable output with TOER before initializing the pins with TIOR.
Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.)
Set MTU2 output with the PFC.
The count operation is started by TSTR.
Output goes low on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR.
Set normal mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 669 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(8)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in PWM Mode 1
Figure 11.146 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in PWM mode 1 after re-setting.
1
2
3
RESET TMDR TOER
(PWM1) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM1) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC*A
Not initialized (TIOC*B)
TIOC*B
Not initialized (TIOC*B)
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.146 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1
1 to 10 are the same as in figure 11.145.
11.
12.
13.
14.
Not necessary when restarting in PWM mode 1.
Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 670 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(9)
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in PWM Mode 2
Figure 11.147 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in PWM mode 2 after re-setting.
1
2
3
RESET TMDR TOER
(PWM1) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM2) (1 init (MTU2) (1)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
Not initialized (TIOC*B)
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.147 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2
1 to 10 are the same as in figure 11.145.
11.
12.
13.
14.
Set PWM mode 2.
Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not
necessary.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 671 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Phase Counting Mode
Figure 11.148 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in phase counting mode after re-setting.
1
2
3
RESET TMDR TOER
(PWM1) (1)
5
4
6
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
7
Match
8
9
10
11
Error
PFC TSTR TMDR
occurs (PORT) (0)
(PCM)
12
13
14
TIOR PFC TSTR
(1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC*A
Not initialized (TIOC*B)
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.148 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode
1 to 10 are the same as in figure 11.145.
11.
12.
13.
14.
Set phase counting mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is
not necessary.
Page 672 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Complementary PWM Mode
Figure 11.149 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in complementary PWM mode after re-setting.
1
2
3
4
5
14
15
16
17
18
19
6
7
8
9
10
11
12
13
RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
(PWM1) (1) (1 init (MTU2) (1)
(CPWM) (1) (MTU2) (1)
occurs (PORT) (0) (normal) (0 init (disabled) (0)
0 out)
0 out)
MTU2 module output
TIOC3A
TIOC3B
Not initialized (TIOC3B)
TIOC3D
Not initialized (TIOC3D)
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.149 Error Occurrence in PWM Mode 1,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 11.145.
11.
12.
13.
14.
15.
16.
17.
18.
19.
Set normal mode for initialization of the normal mode waveform generation section.
Initialize the PWM mode 1 waveform generation section with TIOR.
Disable operation of the PWM mode 1 waveform generation section with TIOR.
Disable channel 3 and 4 output with TOER.
Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
Set complementary PWM.
Enable channel 3 and 4 output with TOER.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 673 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
(12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is
Restarted in Reset-Synchronized PWM Mode
Figure 11.150 shows an explanatory diagram of the case where an error occurs in PWM mode 1
and operation is restarted in reset-synchronized PWM mode after re-setting.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR
(PWM1) (1) (1 init (MTU2) (1)
occurs (PORT) (0) (normal) (0 init (disabled) (0)
(RPWM) (1) (MTU2) (1)
0 out)
0 out)
MTU2 module output
TIOC3A
TIOC3B
Not initialized (TIOC3B)
TIOC3D
Not initialized (TIOC3D)
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.150 Error Occurrence in PWM Mode 1,
Recovery in Reset-Synchronized PWM Mode
1 to 14 are the same as in figure 11.149.
15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
16. Set reset-synchronized PWM.
17. Enable channel 3 and 4 output with TOER.
18. Set MTU2 output with the PFC.
19. Operation is restarted by TSTR.
Page 674 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Normal Mode
Figure 11.151 shows an explanatory diagram of the case where an error occurs in PWM mode 2
and operation is restarted in normal mode after re-setting.
1
2
3
5
4
6
7
8
9
10
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM2) (1 init (MTU2) (1)
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.151 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
After a reset, MTU2 output is low and ports are in the high-impedance state.
Set PWM mode 2.
Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the
example, TIOC *A is the cycle register.)
Set MTU2 output with the PFC.
The count operation is started by TSTR.
Output goes low on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR.
Set normal mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 675 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
(14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in PWM Mode 1
Figure 11.152 shows an explanatory diagram of the case where an error occurs in PWM mode 2
and operation is restarted in PWM mode 1 after re-setting.
1
2
3
5
4
6
7
8
9
10
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM2) (1 init (MTU2) (1)
occurs (PORT) (0) (PWM1) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
TIOC*B
Not initialized (TIOC*B)
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.152 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1
1 to 9 are the same as in figure 11.151.
10.
11.
12.
13.
Set PWM mode 1.
Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 676 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in PWM Mode 2
Figure 11.153 shows an explanatory diagram of the case where an error occurs in PWM mode 2
and operation is restarted in PWM mode 2 after re-setting.
1
2
3
5
4
6
7
8
9
10
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM2) (1 init (MTU2) (1)
occurs (PORT) (0) (PWM2) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
Not initialized (cycle register)
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.153 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2
1 to 9 are the same as in figure 11.151.
10.
11.
12.
13.
Not necessary when restarting in PWM mode 2.
Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 677 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
(16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Restarted in Phase Counting Mode
Figure 11.154 shows an explanatory diagram of the case where an error occurs in PWM mode 2
and operation is restarted in phase counting mode after re-setting.
1
2
3
5
4
6
7
8
9
10
11
12
13
RESET TMDR TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PWM2) (1 init (MTU2) (1)
occurs (PORT) (0)
(PCM) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.154 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode
1 to 9 are the same as in figure 11.151.
10.
11.
12.
13.
Set phase counting mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 678 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in Normal Mode
Figure 11.155 shows an explanatory diagram of the case where an error occurs in phase counting
mode and operation is restarted in normal mode after re-setting.
1
2
RESET TMDR
(PCM)
3
5
4
6
7
8
9
10
11
12
13
TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(1 init (MTU2) (1)
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.155 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
After a reset, MTU2 output is low and ports are in the high-impedance state.
Set phase counting mode.
Initialize the pins with TIOR. (The example shows initial high output, with low output on
compare-match occurrence.)
Set MTU2 output with the PFC.
The count operation is started by TSTR.
Output goes low on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR.
Set in normal mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 679 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
(18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in PWM Mode 1
Figure 11.156 shows an explanatory diagram of the case where an error occurs in phase counting
mode and operation is restarted in PWM mode 1 after re-setting.
1
2
3
5
4
6
7
8
9
10
11
12
13
RESET TMDR TIOR PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(PCM) (1 init (MTU2) (1)
occurs (PORT) (0) (PWM1) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
TIOC*A
TIOC*B
Not initialized (TIOC*B)
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.156 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1
1 to 9 are the same as in figure 11.155.
10.
11.
12.
13.
Set PWM mode 1.
Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 680 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in PWM Mode 2
Figure 11.157 shows an explanatory diagram of the case where an error occurs in phase counting
mode and operation is restarted in PWM mode 2 after re-setting.
1
2
RESET TMDR
(PCM)
3
4
5
6
7
8
9
10
11
12
13
TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(1 init (MTU2) (1)
occurs (PORT) (0) (PWM2) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
Not initialized (cycle register)
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.157 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2
1 to 9 are the same as in figure 11.155.
10.
11.
12.
13.
Set PWM mode 2.
Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 681 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
(20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation
is Restarted in Phase Counting Mode
Figure 11.158 shows an explanatory diagram of the case where an error occurs in phase counting
mode and operation is restarted in phase counting mode after re-setting.
1
2
RESET TMDR
(PCM)
3
5
4
6
7
8
9
10
11
12
13
TIOR
PFC TSTR Match Error
PFC TSTR TMDR TIOR PFC TSTR
(1 init (MTU2) (1)
occurs (PORT) (0)
(PCM) (1 init (MTU2) (1)
0 out)
0 out)
MTU2 module output
TIOC*A
TIOC*B
Port output
PEn
High-Z
PEn
High-Z
n = 0 to 15
Figure 11.158 Error Occurrence in Phase Counting Mode,
Recovery in Phase Counting Mode
1 to 9 are the same as in figure 11.155.
10.
11.
12.
13.
Not necessary when restarting in phase counting mode.
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 682 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(21) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Normal Mode
Figure 11.159 shows an explanatory diagram of the case where an error occurs in complementary
PWM mode and operation is restarted in normal mode after re-setting.
1
2
3
5
4
6
RESET TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.159 Error Occurrence in Complementary PWM Mode,
Recovery in Normal Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
After a reset, MTU2 output is low and ports are in the high-impedance state.
Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
Set complementary PWM.
Enable channel 3 and 4 output with TOER.
Set MTU2 output with the PFC.
The count operation is started by TSTR.
The complementary PWM waveform is output on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM
output initial value.)
Set normal mode. (MTU2 output goes low.)
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 683 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(22) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in PWM Mode 1
Figure 11.160 shows an explanatory diagram of the case where an error occurs in complementary
PWM mode and operation is restarted in PWM mode 1 after re-setting.
1
2
3
5
4
6
RESET TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM1) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC3A
TIOC3B
Not initialized (TIOC3B)
TIOC3D
Not initialized (TIOC3D)
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.160 Error Occurrence in Complementary PWM Mode,
Recovery in PWM Mode 1
1 to 10 are the same as in figure 11.159.
11.
12.
13.
14.
Set PWM mode 1. (MTU2 output goes low.)
Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 684 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(23) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode
Figure 11.161 shows an explanatory diagram of the case where an error occurs in complementary
PWM mode and operation is restarted in complementary PWM mode after re-setting (when
operation is restarted using the cycle and duty settings at the time the counter was stopped).
1
2
3
5
4
6
RESET TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
Error
PFC TSTR PFC TSTR Match
occurs (PORT) (0) (MTU2) (1)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.161 Error Occurrence in Complementary PWM Mode,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 11.159.
11. Set MTU2 output with the PFC.
12. Operation is restarted by TSTR.
13. The complementary PWM waveform is output on compare-match occurrence.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 685 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
SH7280 Group, SH7243 Group
(24) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode
Figure 11.162 shows an explanatory diagram of the case where an error occurs in complementary
PWM mode and operation is restarted in complementary PWM mode after re-setting (when
operation is restarted using completely new cycle and duty settings).
1
2
3
14
15
16
5
17
4
6
7
8
9
10
11
12
13
RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU2) (1)
(CPWM) (1) (MTU2) (1)
occurs (PORT) (0) (normal) (0)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.162 Error Occurrence in Complementary PWM Mode,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 11.159.
11. Set normal mode and make new settings. (MTU2 output goes low.)
12. Disable channel 3 and 4 output with TOER.
13. Select the complementary PWM mode output level and cyclic output enabling/disabling with
TOCR.
14. Set complementary PWM.
15. Enable channel 3 and 4 output with TOER.
16. Set MTU2 output with the PFC.
17. Operation is restarted by TSTR.
Page 686 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(25) Operation when Error Occurs during Complementary PWM Mode Operation, and
Operation is Restarted in Reset-Synchronized PWM Mode
Figure 11.163 shows an explanatory diagram of the case where an error occurs in complementary
PWM mode and operation is restarted in reset-synchronized PWM mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR
(CPWM) (1) (MTU2) (1)
occurs (PORT) (0) (normal) (0)
(RPWM) (1) (MTU2) (1)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.163 Error Occurrence in Complementary PWM Mode,
Recovery in Reset-Synchronized PWM Mode
1 to 10 are the same as in figure 11.159.
11. Set normal mode. (MTU2 output goes low.)
12. Disable channel 3 and 4 output with TOER.
13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling
with TOCR.
14. Set reset-synchronized PWM.
15. Enable channel 3 and 4 output with TOER.
16. Set MTU2 output with the PFC.
17. Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 687 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(26) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and
Operation is Restarted in Normal Mode
Figure 11.164 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in normal mode after re-setting.
1
2
3
5
4
6
RESET TOCR TMDR TOER PFC TSTR
(RPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (normal) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.164 Error Occurrence in Reset-Synchronized PWM Mode,
Recovery in Normal Mode
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
After a reset, MTU2 output is low and ports are in the high-impedance state.
Select the reset-synchronized PWM output level and cyclic output enabling/disabling with
TOCR.
Set reset-synchronized PWM.
Enable channel 3 and 4 output with TOER.
Set MTU2 output with the PFC.
The count operation is started by TSTR.
The reset-synchronized PWM waveform is output on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized
PWM output initial value.)
Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.)
Initialize the pins with TIOR.
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
Page 688 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(27) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and
Operation is Restarted in PWM Mode 1
Figure 11.165 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
1
2
3
5
4
6
RESET TOCR TMDR TOER PFC TSTR
(RPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
14
Error
PFC TSTR TMDR TIOR PFC TSTR
occurs (PORT) (0) (PWM1) (1 init (MTU2) (1)
0 out)
MTU2 module output
TIOC3A
TIOC3B
Not initialized (TIOC3B)
TIOC3D
Not initialized (TIOC3D)
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.165 Error Occurrence in Reset-Synchronized PWM Mode,
Recovery in PWM Mode 1
1 to 10 are the same as in figure 11.164.
11.
12.
13.
14.
Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.)
Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.)
Set MTU2 output with the PFC.
Operation is restarted by TSTR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 689 of 1778
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and
Operation is Restarted in Complementary PWM Mode
Figure 11.166 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in complementary PWM mode after resetting.
1
2
3
4
5
6
RESET TOCR TMDR TOER PFC TSTR
(RPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
14
15
16
Error
PFC TSTR TOER TOCR TMDR TOER PFC TSTR
occurs (PORT) (0)
(0)
(CPWM) (1) (MTU2) (1)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.166 Error Occurrence in Reset-Synchronized PWM Mode,
Recovery in Complementary PWM Mode
1 to 10 are the same as in figure 11.164.
11. Disable channel 3 and 4 output with TOER.
12. Select the complementary PWM output level and cyclic output enabling/disabling with
TOCR.
13. Set complementary PWM. (The MTU2 cyclic output pin goes low.)
14. Enable channel 3 and 4 output with TOER.
15. Set MTU2 output with the PFC.
16. Operation is restarted by TSTR.
Page 690 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(29) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and
Operation is Restarted in Reset-Synchronized PWM Mode
Figure 11.167 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in reset-synchronized PWM mode after resetting.
1
2
3
5
4
6
RESET TOCR TMDR TOER PFC TSTR
(RPWM) (1) (MTU2) (1)
7
Match
8
9
10
11
12
13
Error
PFC TSTR PFC TSTR Match
occurs (PORT) (0) (MTU2) (1)
MTU2 module output
TIOC3A
TIOC3B
TIOC3D
Port output
PE8
High-Z
PE9
High-Z
PE11
High-Z
Figure 11.167 Error Occurrence in Reset-Synchronized PWM Mode,
Recovery in Reset-Synchronized PWM Mode
1 to 10 are the same as in figure 11.164.
11. Set MTU2 output with the PFC.
12. Operation is restarted by TSTR.
13. The reset-synchronized PWM waveform is output on compare-match occurrence.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 691 of 1778
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Page 692 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
This LSI has an on-chip multi-function timer pulse unit 2S (MTU2S) that comprises three 16-bit
timer channels. The MTU2S includes channels 3 to 5 of the MTU2. For details, refer to section 11,
Multi-Function Timer Pulse Unit 2 (MTU2). To distinguish from the MTU2, "S" is added to the
end of the MTU2S input/output pin and register names. For example, TIOC3A is called TIOC3AS
and TGRA_3 is called TGRA_3S in this section.
The MTU2S can operate at 100 MHz max. for complementary PWM output functions or at 50
MHz max. for the other functions.
Table 12.1 MTU2S Functions
Item
Channel 3
Channel 4
Channel 5
Count clock
Mφ/1
Mφ/4
Mφ/16
Mφ/64
Mφ/256
Mφ/1024
Mφ/1
Mφ/4
Mφ/16
Mφ/64
Mφ/256
Mφ/1024
Mφ/1
Mφ/4
Mφ/16
Mφ/64
General registers
TGRA_3S
TGRB_3S
TGRA_4S
TGRB_4S
TGRU_5S
TGRV_5S
TGRW_5S
General registers/
buffer registers
TGRC_3S
TGRD_3S
TGRC_4S
TGRD_4S
—
I/O pins
TIOC3AS
TIOC3BS
TIOC3CS
TIOC3DS
TIOC4AS
TIOC4BS
TIOC4CS
TIOC4DS
Input pins
TIC5US
TIC5VS
TIC5WS
Counter clear
function
TGR compare match or
input capture
TGR compare match or
input capture
TGR compare match or
input capture
0 output √
√
—
1 output √
√
—
√
√
—
Input capture
function
√
√
√
Synchronous
operation
√
√
—
Compare
match
output
Toggle
output
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 693 of 1778
SH7280 Group, SH7243 Group
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Item
Channel 3
Channel 4
Channel 5
PWM mode 1
√
√
—
PWM mode 2
—
—
—
Complementary
PWM mode
√
√
—
Reset PWM mode
√
√
—
AC synchronous
motor drive mode
—
—
—
Phase counting
mode
—
—
—
Buffer operation
√
√
—
Counter function of
compensation for
dead time
—
—
√
DTC activation
TGR compare match or
input capture
TGR compare match or
input capture, or TCNT
overflow or underflow
TGR compare match or
input capture
A/D converter start
trigger
TGRA_3S compare
match or input capture
TGRA_4S compare
match or input capture
—
TCNT_4S underflow
(trough) in
complementary PWM
mode
Interrupt sources
Page 694 of 1778
5 sources
5 sources
3 sources
•
Compare match or
input capture 3AS
•
Compare match or
input capture 4AS
•
Compare match or
input capture 5US
•
Compare match or
input capture 3BS
•
Compare match or
input capture 4BS
•
Compare match or
input capture 5VS
•
Compare match or
input capture 3CS
•
Compare match or
input capture 4CS
•
Compare match or
input capture 5WS
•
Compare match or
input capture 3DS
•
Compare match or
input capture 4DS
•
Overflow
•
Overflow or
underflow
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Item
Channel 3
Channel 4
Channel 5
A/D converter start
request delaying
function
—
•
A/D converter start
request at a match
between
TADCORA_4S and
TCNT_4S
—
•
A/D converter start
request at a match
between
TADCORB_4S and
TCNT_4S
•
Skips TCIV_4S
interrupts
Interrupt skipping
function
•
Skips TGRA_3S
compare match
interrupts
—
[Legend]
√:
Possible
—:
Not possible
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 695 of 1778
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
12.1
SH7280 Group, SH7243 Group
Input/Output Pins
Table 12.2 Pin Configuration
Channel Symbol
3
4
5
I/O
Function
TIOC3AS I/O
TGRA_3S input capture input/output compare output/PWM output pin
TIOC3BS I/O
TGRB_3S input capture input/output compare output/PWM output pin
TIOC3CS I/O
TGRC_3S input capture input/output compare output/PWM output pin
TIOC3DS I/O
TGRD_3S input capture input/output compare output/PWM output pin
TIOC4AS I/O
TGRA_4S input capture input/output compare output/PWM output pin
TIOC4BS I/O
TGRB_4S input capture input/output compare output/PWM output pin
TIOC4CS I/O
TGRC_4S input capture input/output compare output/PWM output pin
TIOC4DS I/O
TGRD_4S input capture input/output compare output/PWM output pin
TIC5US
Input TGRU_5S input capture input/external pulse input pin
TIC5VS
Input TGRV_5S input capture input/external pulse input pin
TIC5WS
Input TGRW_5S input capture input/external pulse input pin
Page 696 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
12.2
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Register Descriptions
The MTU2S has the following registers. For details on register addresses and register states during
each process, refer to section 30, List of Registers. To distinguish registers in each channel, an
underscore and the channel number are added as a suffix to the register name; TCR for channel 3
is expressed as TCR_3S.
Table 12.3 Register Configuration
Register Name
Abbreviation
R/W
Initial
value
Access
Size
Address
Timer control register_3S
TCR_3S
R/W
H'00
H'FFFE4A00
8, 16, 32
Timer control register_4S
TCR_4S
R/W
H'00
H'FFFE4A01
8
Timer mode register_3S
TMDR_3S
R/W
H'00
H'FFFE4A02
8, 16
Timer mode register_4S
TMDR_4S
R/W
H'00
H'FFFE4A03
8
Timer I/O control register H_3S
TIORH_3S
R/W
H'00
H'FFFE4A04
8, 16, 32
Timer I/O control register L_3S
TIORL_3S
R/W
H'00
H'FFFE4A05
8
Timer I/O control register H_4S
TIORH_4S
R/W
H'00
H'FFFE4A06
8, 16
Timer I/O control register L_4S
TIORL_4S
R/W
H'00
H'FFFE4A07
8
Timer interrupt enable register_3S
TIER_3S
R/W
H'00
H'FFFE4A08
8, 16
Timer interrupt enable register_4S
TIER_4S
R/W
H'00
H'FFFE4A09
8
Timer output master enable register S
TOERS
R/W
H'C0
H'FFFE4A0A
8
Timer gate control register S
TGCRS
R/W
H'80
H'FFFE4A0D
8
Timer output control register 1S
TOCR1S
R/W
H'00
H'FFFE4A0E
8, 16
Timer output control register 2S
TOCR2S
R/W
H'00
H'FFFE4A0F
8
Timer counter_3S
TCNT_3S
R/W
H'0000
H'FFFE4A10
16, 32
Timer counter_4S
TCNT_4S
R/W
H'0000
H'FFFE4A12
16
Timer cycle data register S
TCDRS
R/W
H'FFFF
H'FFFE4A14
16, 32
Timer dead time data register S
TDDRS
R/W
H'FFFF
H'FFFE4A16
16
Timer general register A_3S
TGRA_3S
R/W
H'FFFF
H'FFFE4A18
16, 32
Timer general register B_3S
TGRB_3S
R/W
H'FFFF
H'FFFE4A1A
16
Timer general register A_4S
TGRA_4S
R/W
H'FFFF
H'FFFE4A1C
16, 32
Timer general register B_4S
TGRB_4S
R/W
H'FFFF
H'FFFE4A1E
16
Timer subcounter S
TCNTSS
R
H'0000
H'FFFE4A20
16, 32
Timer cycle buffer register S
TCBRS
R/W
H'FFFF
H'FFFE4A22
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 697 of 1778
SH7280 Group, SH7243 Group
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Register Name
Abbreviation
R/W
Initial
value
Address
Access
Size
Timer general register C_3S
TGRC_3S
R/W
H'FFFF
H'FFFE4A24
16, 32
Timer general register D_3S
TGRD_3S
R/W
H'FFFF
H'FFFE4A26
16
Timer general register C_4S
TGRC_4S
R/W
H'FFFF
H'FFFE4A28
16, 32
Timer general register D_4S
TGRD_4S
R/W
H'FFFF
H'FFFE4A2A
16
Timer status register_3S
TSR_3S
R/W
H'C0
H'FFFE4A2C
8, 16
Timer status register_4S
TSR_4S
R/W
H'C0
H'FFFE4A2D
8
Timer interrupt skipping set register S
TITCRS
R/W
H'00
H'FFFE4A30
8, 16
Timer interrupt skipping counter S
TITCNTS
R
H'00
H'FFFE4A31
8
Timer buffer transfer set register S
TBTERS
R/W
H'00
H'FFFE4A32
8
Timer dead time enable register S
TDERS
R/W
H'01
H'FFFE4A34
8
Timer output level buffer register S
TOLBRS
R/W
H'00
H'FFFE4A36
8
Timer buffer operation transfer mode
register_3S
TBTM_3S
R/W
H'00
H'FFFE4A38
8, 16
Timer buffer operation transfer mode
register_4S
TBTM_4S
R/W
H'00
H'FFFE4A39
8
Timer A/D converter start request
control register S
TADCRS
R/W
H'0000
H'FFFE4A40
16
Timer A/D converter start request cycle
set register A_4S
TADCORA_4S R/W
H'FFFF
H'FFFE4A44
16, 32
Timer A/D converter start request cycle
set register B_4S
TADCORB_4S R/W
H'FFFF
H'FFFE4A46
16
Timer A/D converter start request cycle
set buffer register A_4S
TADCOBRA_4S
R/W
H'FFFF
H'FFFE4A48
16, 32
Timer A/D converter start request cycle
set buffer register B_4S
TADCOBRB_4S
R/W
H'FFFF
H'FFFE4A4A
16
Timer synchronous clear register S*
TSYCRS
R/W
H'00
H'FFFE4A50
8
Timer waveform control register S
TWCRS
R/W
H'00
H'FFFE4A60
8
Timer start register S
TSTRS
R/W
H'00
H'FFFE4A80
8, 16
Timer synchronous register S
TSYRS
R/W
H'00
H'FFFE4A81
8
Timer read/write enable register S
TRWERS
R/W
H'01
H'FFFE4A84
8
Page 698 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Register Name
Abbreviation
R/W
Initial
value
Address
Access
Size
Timer counter U_5S
TCNTU_5S
R/W
H'0000
H'FFFE4880
16, 32
Timer general register U_5S
TGRU_5S
R/W
H'FFFF
H'FFFE4882
16
Timer control register U_5S
TCRU_5S
R/W
H'00
H'FFFE4884
8
Timer I/O control register U_5S
TIORU_5S
R/W
H'00
H'FFFE4886
8
Timer counter V_5S
TCNTV_5S
R/W
H'0000
H'FFFE4890
16, 32
Timer general register V_5S
TGRV_5S
R/W
H'FFFF
H'FFFE4892
16
Timer control register V_5S
TCRV_5S
R/W
H'00
H'FFFE4894
8
Timer I/O control register V_5S
TIORV_5S
R/W
H'00
H'FFFE4896
8
Timer counter W_5S
TCNTW_5S
R/W
H'0000
H'FFFE48A0
16, 32
Timer general register W_5S
TGRW_5S
R/W
H'FFFF
H'FFFE48A2
16
Timer control register W_5S
TCRW_5S
R/W
H'00
H'FFFE48A4
8
Timer I/O control register W_5S
TIORW_5S
R/W
H'00
H'FFFE48A6
8
Timer status register_5S
TSR_5S
R/W
H'00
H'FFFE48B0
8
Timer interrupt enable register_5S
TIER_5S
R/W
H'00
H'FFFE48B2
8
Timer start register_5S
TSTR_5S
R/W
H'00
H'FFFE48B4
8
Timer compare match clear register S
TCNTCMPCLRS
R/W
H'00
H'FFFE48B6
8
Note:
*
For detailed register descriptions, refer to section 11.3.9, Timer Synchronous Clear
Register S (TSYCRS), and figure 11.85 in section 11, Multi-Function Timer Pulse Unit 2
(MTU2).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 699 of 1778
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Page 700 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Section 13 Port Output Enable 2 (POE2)
The port output enable 2 (POE2) can be used to place the high-current pins (PE9/TIOC3B,
PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B, PE14/TIOC4C, PE15/TIOC4D, PE0/TIOC4AS,
PE1/TIOC4BS, PE2/TIOC4CS, PE3/TIOC4DS, PE5/TIOC3BS, PE6/TIOC3DS, PD15/TIOC4DS,
PD14/TIOC4CS, PD13/TIOC4BS, PD12/TIOC4AS, PD11/TIOC3DS, PD10/TIOC3BS,
PD24/TIOC4DS, PD25/TIOC4CS, PD26/TIOC4BS, PD27/TIOC4AS, PD28/TIOC3DS, and
PD29/TIOC3BS) and the pins for channel 0 of the MTU2 (PE0/TIOC0A, PE1/TIOC0B,
PE2/TIOC0C, and PE3/TIOC0D) in high-impedance state, depending on the change on the POE0
to POE8* input pins and the output status of the high-current pins, or by modifying register
settings. It can also simultaneously generate interrupt requests.
13.1
Features
• Each of the POE0 to POE8* input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or
Pφ/128 × 16 low-level sampling.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by POE0 to POE8* pin falling-edge or low-level sampling.
• High-current pins can be placed in high-impedance state when the high-current pin output
levels are compared and simultaneous active-level output continues for one cycle or more.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance
state by modifying the POE2 register settings.
• Interrupts can be generated by input-level sampling or output-level comparison results.
The POE2 has input level detection circuits, output level comparison circuits, and a highimpedance request/interrupt request generating circuit as shown in the block diagram of figure
13.1.
Note: * Only POE8, POE4, POE3, and POE0 are available in the SH7243.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 701 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Figure 13.1 shows a block diagram of the POE2.
Output level comparison
circuit
TIOC3BS
TIOC3DS
TIOC4AS
TIOC4CS
TIOC4BS
TIOC4DS
Output level comparison
circuit
Output level comparison
circuit
OCSR2
Output level comparison
circuit
Output level comparison
circuit
Output level comparison
circuit
Input level detection circuit
POE3
POE2
POE1
POE0
ICSR1
Falling edge
detection circuit
Low level
sampling circuit
Input level detection circuit
POE7
POE4
POE5
POE6
ICSR2
Falling edge
detection circuit
Low level
sampling circuit
High-impedance
request signal for
MTU2 high-current pins
High-impedance request/interrupt request generating circuit
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
OCSR1
POECR1,
POECR2
High-impedance
request signal for
MTU2 channel 0 pins
High-impedance
request signal for
MTU2S high-current pins
Interrupt
request signal
Input level detection circuit
POE8
ICSR3
Falling edge
detection circuit
Low level
sampling circuit
Pφ/8
Pφ/16
Pφ/128
SPOER
Frequency
divider
[Legend]
ICSR1:
ICSR2:
ICSR3:
OCSR1:
OCSR2:
Pφ
Input level control/status register 1
Input level control/status register 2
Input level control/status register 3
Output level control/status register 1
Output level control/status register 2
SPOER: Software port output enable register
POECR1: Port output enable control register 1
POECR2: Port output enable control register 2
Figure 13.1 Block Diagram of POE2
Page 702 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
13.2
Section 13 Port Output Enable 2 (POE2)
Input/Output Pins
Table 13.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Port output enable
input pins 0 to 3
POE0 to POE3
Input
Input request signals to place high-current pins
(PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A,
PE13/TIOC4B, PE14/TIOC4C, and
PE15/TIOC4D) for MTU2 in high-impedance
state
Port output enable
input pins 4 to 7
POE4 to POE7
Input
Input request signals to place high-current pins
(PE5/TIOC3BS, PE6/TIOC3DS, PE0/TIOC4AS,
PE1/TIOC4BS, PE2/TIOC4CS, PE3/TIOC4DS,
PD10/TIOC3BS, PD11/TIOC3DS,
PD12/TIOC4AS, PD13/TIOC4BS,
PD14/TIOC4CS, PD15/TIOC4DS,
PD29/TIOC3BS, PD28/TIOC3DS,
PD27/TIOC4AS, PD26/TIOC4BS,
PD25/TIOC4CS, and PD24/TIOC4DS) for
MTU2S in high-impedance state
Port output enable
input pin 8
POE8
Input
Inputs a request signal to place pins
(PE0/TIOC0A, PE1/TIOC0B, PE2/TIOC0C, and
PA3/TIOC0D) for channel 0 in MTU2 in highimpedance state
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 703 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Table 13.2 shows output-level comparisons with pin combinations.
Table 13.2 Pin Combinations
Pin Combination
I/O
PE9/TIOC3B and PE11/TIOC3D
Output The high-current pins for the MTU2 are placed in
high-impedance state when the pins
simultaneously output an active level for one or
more cycles of the peripheral clock (Pφ). (In the
case of TOCS = 0 in timer output control register 1
(TOCR1) in the MTU2, low level when the output
level select P (OLSP) bit is 0, or high level when
the OLSP bit is 1. In the case of TOCS = 1, low
level when the OLS3N, OLS3P, OLS2N, OLS2P,
OLS1N, and OLS1P bits are 0 in TOCR2, or high
level when these bits are 1.)
PE12/TIOC4A and PE14/TIOC4C
PE13/TIOC4B and PE15/TIOC4D
Description
This active level comparison is done when the
MTU2 output function or general output function is
selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and highimpedance control can be selected by POE2
registers.
PE5/PD10/PD29/TIOC3BS and
PE6/PD11/PD28/TIOC3DS
PE0/PD12/PD27/TIOC4AS and
PE2/PD14/PD25/TIOC4CS
PE1/PD13/PD26/TIOC4BS and
PE3/PD15/PD24/TIOC4DS
Output The high-current pins for the MTU2S are placed in
high-impedance state when the pins
simultaneously output an active level for one or
more cycles of the peripheral clock (Pφ). (In the
case of TOCS = 0 in timer output control register
1S (TOCR1S) in the MTU2S, low level when the
output level select P (OLSP) bit is 0, or high level
when the OLSP bit is 1. In the case of TOCS = 1,
low level when the OLS3N, OLS3P, OLS2N,
OLS2P, OLS1N, and OLS1P bits are 0 in
TOCR2S, or high level when these bits are 1.)
This active level comparison is done when the
MTU2S output function or general output function
is selected in the pin function controller. If another
function is selected, the output level is not
checked.
Pin combinations for output comparison and highimpedance control can be selected by POE2
registers.
Page 704 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
13.3
Section 13 Port Output Enable 2 (POE2)
Register Descriptions
The POE2 has the following registers.
All these registers are initialized by a power-on reset, but are not initialized by a manual reset or in
sleep mode, software standby mode, or module standby mode.
Table 13.3 Register Configuration
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
Input level control/status register 1
ICSR1
R/W
H'0000
H'FFFE5000
16
Output level control/status register 1
OCSR1
R/W
H'0000
H'FFFE5002
16
Input level control/status register 2
ICSR2
R/W
H'0000
H'FFFE5004
16
Output level control/status register 2
OCSR2
R/W
H'0000
H'FFFE5006
16
Input level control/status register 3
ICSR3
R/W
H'0000
H'FFFE5008
16
Software port output enable register
SPOER
R/W
H'00
H'FFFE500A
8
Port output enable control register 1
POECR1
R/W
H'00
H'FFFE500B
8
Port output enable control register 2
POECR2
R/W
H'7700
H'FFFE500C
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 705 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
13.3.1
Input Level Control/Status Register 1 (ICSR1)
ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1*3, POE2*3, and POE3 pin
input modes, controls the enable/disable of interrupts, and indicates status.
Bit:
15
14
13
12
POE3F POE2F POE1F POE0F
Initial value:
0
0
0
0
R/W: R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
11
10
9
8
-
-
-
PIE1
0
R
0
R
0
R
0
R/W
7
6
POE3M[1:0]
5
4
POE2M[1:0]
3
2
POE1M[1:0]
1
0
POE0M[1:0]
0
0
0
0
0
0
0
0
R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Bit
15
Bit Name
POE3F
Initial
Value
0
R/W
Description
1
R/(W)* POE3 Flag
Indicates that a high impedance request has been input
to the POE3 pin.
[Clearing conditions]
•
By writing 0 to POE3F after reading POE3F = 1
(when the falling edge is selected by bits 7 and 6 in
ICSR1)
•
By writing 0 to POE3F after reading POE3F = 1 after
a high level input to POE3 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 7 and 6 in ICSR1)
[Setting condition]
•
Page 706 of 1778
When the input set by bits 7 and 6 in ICSR1 occurs at
the POE3 pin
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
14
Bit Name
POE2F
Initial
Value
0
Section 13 Port Output Enable 2 (POE2)
R/W
Description
1
R/(W)* POE2 Flag
Indicates that a high impedance request has been input
to the POE2 pin.
[Clearing conditions]
•
By writing 0 to POE2F after reading POE2F = 1
(when the falling edge is selected by bits 5 and 4 in
ICSR1)
•
By writing 0 to POE2F after reading POE2F = 1 after
a high level input to POE2 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 5 and 4 in ICSR1)
[Setting condition]
•
13
POE1F
0
When the input set by bits 5 and 4 in ICSR1 occurs at
the POE2 pin
R/(W)*1 POE1 Flag
Indicates that a high impedance request has been input
to the POE1 pin.
[Clearing conditions]
•
By writing 0 to POE1F after reading POE1F = 1
(when the falling edge is selected by bits 3 and 2 in
ICSR1)
•
By writing 0 to POE1F after reading POE1F = 1 after
a high level input to POE1 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 3 and 2 in ICSR1)
[Setting condition]
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
When the input set by bits 3 and 2 in ICSR1 occurs at
the POE1 pin
Page 707 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
12
Bit Name
POE0F
Initial
Value
0
R/W
Description
1
R/(W)* POE0 Flag
Indicates that a high impedance request has been input
to the POE0 pin.
[Clear conditions]
•
By writing 0 to POE0F after reading POE0F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR1)
•
By writing 0 to POE0F after reading POE0F = 1 after
a high level input to POE0 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR1)
[Set condition]
•
11 to 9 ⎯
All 0
R
When the input set by bits 1 and 0 in ICSR1 occurs at
the POE0 pin
Reserved
These bits are always read as 0. The write value should
always be 0.
8
PIE1
0
R/W
Port Interrupt Enable 1
Enables or disables interrupt requests when any one of
the POE0F to POE3F bits of the ICSR1 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7, 6
POE3M[1:0] 00
2
R/W*
POE3 Mode
These bits select the input mode of the POE3 pin.
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE3 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE3 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Page 708 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
5, 4
Bit Name
Initial
Value
POE2M[1:0] 00
Section 13 Port Output Enable 2 (POE2)
R/W
Description
2
R/W*
POE2 Mode
These bits select the input mode of the POE2 pin.
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE2 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE2 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
3, 2
POE1M[1:0] 00
R/W*2
POE1 Mode
These bits select the input mode of the POE1 pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
1, 0
POE0M[1:0] 00
R/W*2
POE0 Mode
These bits select the input mode of the POE0 pin.
00: Accept request on falling edge of POE0 input
01: Accept request when POE0 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE0 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE0 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
3. POE1 and POE2 are not available in the SH7243.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 709 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
13.3.2
Output Level Control/Status Register 1 (OCSR1)
OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSF1
-
-
-
-
-
OCE1
OIE1
-
-
-
-
-
-
-
-
0
0
Initial value:
R/W: R/(W)*1 R
0
R
0
R
0
R
0
R
0
0
R/W*2 R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Bit
15
Initial
Bit Name Value
OSF1
0
R/W
Description
1
R/(W)* Output Short Flag 1
Indicates that any one of the three pairs of MTU2 2phase outputs to be compared has simultaneously
become an active level.
[Clearing condition]
•
By writing 0 to OSF1 after reading OSF1 = 1
[Setting condition]
•
14 to 10 ⎯
All 0
R
When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
Reserved
These bits are always read as 0. The write value should
always be 0.
9
OCE1
0
R/W*2
Output Short High-Impedance Enable 1
Specifies whether to place the pins in high-impedance
state when the OSF1 bit in OCSR1 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
8
OIE1
0
R/W
Output Short Interrupt Enable 1
Enables or disables interrupt requests when the OSF1 bit
in OCSR is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
Page 710 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
13.3.3
Input Level Control/Status Register 2 (ICSR2)
ICSR2 is a 16-bit readable/writable register that selects the POE4 to POE7*3 pin input modes,
controls the enable/disable of interrupts, and indicates status.
Bit:
15
14
13
12
POE7F POE6F POE5F POE4F
Initial value:
0
0
0
0
R/W: R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
11
10
9
8
-
-
-
PIE2
0
R
0
R
0
R
0
R/W
7
6
POE7M[1:0]
5
4
POE6M[1:0]
3
2
1
POE5M[1:0]
0
POE4M[1:0]
0
0
0
0
0
0
0
0
R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
3. Only POE4 is available in the SH7243.
Bit
15
Bit Name
POE7F
Initial
Value
0
R/W
Description
1
R/(W)* POE7 Flag
Indicates that a high impedance request has been input
to the POE7 pin.
[Clearing conditions]
•
By writing 0 to POE7F after reading POE7F = 1
(when the falling edge is selected by bits 7 and 6 in
ICSR2)
•
By writing 0 to POE7F after reading POE7F = 1 after
a high level input to POE7 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 7 and 6 in ICSR2)
[Setting condition]
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
When the input condition set by bits 7 and 6 in ICSR2
occurs at the POE7 pin
Page 711 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
14
Bit Name
POE6F
Initial
Value
0
R/W
Description
1
R/(W)* POE6 Flag
Indicates that a high impedance request has been input
to the POE6 pin.
[Clearing conditions]
•
By writing 0 to POE6F after reading POE6F = 1
(when the falling edge is selected by bits 5 and 4 in
ICSR2)
•
By writing 0 to POE6F after reading POE6F = 1 after
a high level input to POE6 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 5 and 4 in ICSR2)
[Setting condition]
•
13
POE5F
0
When the input condition set by bits 5 and 4 in ICSR2
occurs at the POE6 pin
R/(W)*1 POE5 Flag
Indicates that a high impedance request has been input
to the POE5 pin.
[Clearing conditions]
•
By writing 0 to POE5F after reading POE5F = 1
(when the falling edge is selected by bits 3 and 2 in
ICSR2)
•
By writing 0 to POE5F after reading POE5F = 1 after
a high level input to POE5 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 3 and 2 in ICSR2)
[Setting condition]
•
Page 712 of 1778
When the input condition set by bits 3 and 2 in ICSR2
occurs at the POE5 pin
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
12
Bit Name
POE4F
Initial
Value
0
Section 13 Port Output Enable 2 (POE2)
R/W
Description
1
R/(W)* POE4 Flag
Indicates that a high impedance request has been input
to the POE4 pin.
[Clearing conditions]
•
By writing 0 to POE4F after reading POE4F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR2)
•
By writing 0 to POE4F after reading POE4F = 1 after
a high level input to POE4 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR2)
[Setting condition]
•
11 to 9 —
All 0
R
When the input condition set by bits 1 and 0 in ICSR2
occurs at the POE4 pin
Reserved
These bits are always read as 0. The write value should
always be 0.
8
PIE2
0
R/W
Port Interrupt Enable 2
Enables or disables interrupt requests when any one of
the POE4F to POE7F bits of the ICSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7, 6
POE7M[1:0] 00
2
R/W*
POE7 Mode
These bits select the input mode of the POE7 pin.
00: Accept request on falling edge of POE7 input
01: Accept request when POE7 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE7 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE7 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 713 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
5, 4
Bit Name
Initial
Value
POE6M[1:0] 00
R/W
Description
2
R/W*
POE6 Mode
These bits select the input mode of the POE6 pin.
00: Accept request on falling edge of POE6 input
01: Accept request when POE6 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE6 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE6 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
3, 2
POE5M[1:0] 00
R/W*2
POE5 Mode
These bits select the input mode of the POE5 pin.
00: Accept request on falling edge of POE5 input
01: Accept request when POE5 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE5 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE5 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
1, 0
POE4M[1:0] 00
R/W*2
POE4 Mode
These bits select the input mode of the POE4 pin.
00: Accept request on falling edge of POE4 input
01: Accept request when POE4 input has been sampled
for 16 Pφ/8 clock pulses and all are at a low level.
10: Accept request when POE4 input has been sampled
for 16 Pφ/16 clock pulses and all are at a low level.
11: Accept request when POE4 input has been sampled
for 16 Pφ/128 clock pulses and all are at a low level.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Page 714 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
13.3.4
Section 13 Port Output Enable 2 (POE2)
Output Level Control/Status Register 2 (OCSR2)
OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSF2
-
-
-
-
-
OCE2
OIE2
-
-
-
-
-
-
-
-
0
0
Initial value:
R/W: R/(W)*1 R
0
R
0
R
0
R
0
R
0
0
R/W*2 R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit:
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Bit
15
Initial
Bit Name Value
OSF2
0
R/W
Description
1
R/(W)* Output Short Flag 2
Indicates that any one of the three pairs of MTU2S 2phase outputs to be compared has simultaneously
become an active level.
[Clearing condition]
•
By writing 0 to OSF2 after reading OSF2 = 1
[Setting condition]
•
14 to 10 ⎯
All 0
R
When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
Reserved
These bits are always read as 0. The write value should
always be 0.
9
OCE2
0
R/W*2
Output Short High-Impedance Enable 2
Specifies whether to place the pins in high-impedance
state when the OSF2 bit in OCSR2 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 715 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
Bit Name
Initial
Value
R/W
Description
8
OIE2
0
R/W
Output Short Interrupt Enable 2
Enables or disables interrupt requests when the OSF2 bit
in OCSR2 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
⎯
7 to 0
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
13.3.5
Input Level Control/Status Register 3 (ICSR3)
ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the
enable/disable of interrupts, and indicates status.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
POE8F
-
-
POE8E
PIE3
-
-
-
-
-
-
POE8M[1:0]
1
0
0
R
0
R
0
R
0
R/(W)*1
0
R
0
R
0
0
R/W*2 R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
0
R/W*2 R/W*2
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Bit
Bit Name
15 to 13 —
Initial
Value
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 716 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
12
Bit Name
POE8F
Initial
Value
0
Section 13 Port Output Enable 2 (POE2)
R/W
R/(W)*
Description
1
POE8 Flag
Indicates that a high impedance request has been input
to the POE8 pin.
[Clearing conditions]
•
By writing 0 to POE8F after reading POE8F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR3)
•
By writing 0 to POE8F after reading POE8F = 1 after
a high level input to POE8 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR3)
[Setting condition]
•
11, 10
⎯
All 0
R
When the input condition set by bits 1 and 0 in
ICSR3 occurs at the POE8 pin
Reserved
These bits are always read as 0. The write value should
always be 0.
9
POE8E
0
R/W*2
POE8 High-Impedance Enable
Specifies whether to place the pins in high-impedance
state when the POE8F bit in ICSR3 is set
to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
8
PIE3
0
R/W
Port Interrupt Enable 3
Enables or disables interrupt requests when the POE8
bit in ICSR3 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
7 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 717 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
1, 0
Bit Name
Initial
Value
R/W
Description
2
POE8M[1:0] 00
R/W*
POE8 Mode
These bits select the input mode of the POE8 pin.
00: Accept request on falling edge of POE8 input
01: Accept request when POE8 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE8 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE8 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
13.3.6
Software Port Output Enable Register (SPOER)
SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins.
Bit:
Initial value:
R/W:
Bit
Bit Name
7 to 3 —
7
6
5
4
3
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Initial
Value
R/W
Description
All 0
R
Reserved
2
1
0
MTU2S MTU2 MTU2
HIZ CH0HIZ CH34HIZ
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
Page 718 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
Bit Name
Initial
Value
R/W
Description
2
MTU2SHIZ
0
R/W
MTU2S Output High-Impedance
Specifies whether to place the high-current pins for
the MTU2S in high-impedance state.
0: Does not place the pins in high-impedance state
[Clearing conditions]
•
Power-on reset
•
By writing 0 to MTU2SHIZ after reading
MTU2SHIZ = 1
1: Places the pins in high-impedance state
[Setting condition]
•
1
MTU2CH0HIZ
0
R/W
By writing 1 to MTU2SHIZ
MTU2 Channel 0 Output High-Impedance
Specifies whether to place the pins for channel 0 in
the MTU2 in high-impedance state.
0: Does not place the pins in high-impedance state
[Clearing conditions]
•
Power-on reset
•
By writing 0 to MTU2CH0HIZ after reading
MTU2CH0HIZ = 1
1: Places the pins in high-impedance state
[Setting condition]
•
0
MTU2CH34HIZ 0
R/W
By writing 1 to MTU2CH0HIZ
MTU2 Channel 3 and 4 Output High-Impedance
Specifies whether to place the high-current pins for
the MTU2 in high-impedance state.
0: Does not place the pins in high-impedance state
[Clearing conditions]
•
Power-on reset
•
By writing 0 to MTU2CH34HIZ after reading
MTU2CH34HIZ = 1
1: Places the pins in high-impedance state
[Setting condition]
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
By writing 1 to MTU2CH34HIZ
Page 719 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
13.3.7
Port Output Enable Control Register 1 (POECR1)
POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins.
Bit:
Initial value:
R/W:
7
6
5
4
-
-
-
-
MTU2 MTU2 MTU2 MTU2
PE3ZE PE2ZE PE1ZE PE0ZE
3
2
1
0
0
R
0
R
0
R
0
R
0
0
0
0
R/W* R/W* R/W* R/W*
Note: * Can be modified only once after a power-on reset.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
MTU2PE3ZE
0
R/W*
MTU2PE3 High-Impedance Enable
Specifies whether to place the PE3/TIOC0D pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
2
MTU2PE2ZE
0
R/W*
MTU2PE2 High-Impedance Enable
Specifies whether to place the PE2/TIOC0C pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
1
MTU2PE1ZE
0
R/W*
MTU2PE1 High-Impedance Enable
Specifies whether to place the PE1/TIOC0B pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
Page 720 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
Bit Name
Initial
Value
R/W
Description
0
MTU2PE0ZE
0
R/W*
MTU2PE0 High-Impedance Enable
Specifies whether to place the PE0/TIOC0A pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
13.3.8
Port Output Enable Control Register 2 (POECR2)
POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
MTU2 MTU2 MTU2
P1CZE P2CZE P3CZE
-
MTU2S MTU2S MTU2S
P1CZE P2CZE P3CZE
-
MTU2S MTU2S MTU2S
P4CZE P5CZE P6CZE
-
MTU2S MTU2S MTU2S
P7CZE P8CZE P9CZE
Initial value: 0
R/W: R
1
1
1
R/W* R/W* R/W*
0
R
1
1
1
R/W* R/W* R/W*
0
R
0
0
0
R/W* R/W* R/W*
0
R
0
0
0
R/W* R/W* R/W*
Note: * Can be modified only once after a power-on reset.
Bit
Bit Name
Initial
Value
R/W
15
—
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14
MTU2P1CZE
1
R/W*
MTU2 Port 1 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PE9/TIOC3B and PE11/TIOC3D
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE2F,
POE3F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 721 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Bit
Bit Name
Initial
Value
R/W
Description
13
MTU2P2CZE
1
R/W*
MTU2 Port 2 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PE12/TIOC4A and PE14/TIOC4C
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE2F,
POE3F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
12
MTU2P3CZE
1
R/W*
MTU2 Port 3 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PE13/TIOC4B and PE15/TIOC4D
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE2F,
POE3F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
11
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 722 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Initial
Value
Bit
Bit Name
10
MTU2SP1CZE 1
R/W
Description
R/W*
MTU2S Port 1 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PE5/TIOC3BS and
PE6/TIOC3DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
9
MTU2SP2CZE 1
R/W*
MTU2S Port 2 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PE0/TIOC4AS and
PE2/TIOC4CS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 723 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Initial
Value
Bit
Bit Name
8
MTU2SP3CZE 1
R/W
Description
R/W*
MTU2S Port 3 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PE1/TIOC4BS and
PE3/TIOC4DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
MTU2SP4CZE 0
R/W*
MTU2S Port 4 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PD10/TIOC3BS and
PD11/TIOC3DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
Page 724 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Initial
Value
Bit
Bit Name
5
MTU2SP5CZE 0
R/W
Description
R/W*
MTU2S Port 5 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PD12/TIOC4AS and
PD14/TIOC4CS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
4
MTU2SP6CZE 0
R/W*
MTU2S Port 6 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PD13/TIOC4BS and
PD15/TIOC4DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
3
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 725 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
Initial
Value
Bit
Bit Name
2
MTU2SP7CZE 0
R/W
Description
R/W*
MTU2S Port 7 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PD29/TIOC3BS and
PD28/TIOC3DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
1
MTU2SP8CZE 0
R/W*
MTU2S Port 8 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PD27/TIOC4AS and
PD25/TIOC4CS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
0
MTU2SP9CZE 0
R/W*
MTU2S Port 9 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2S high-current PD26/TIOC4BS and
PD24/TIOC4DS pins and to place them in highimpedance state when the OSF2 bit is set to 1 while
the OCE2 bit is 1 or when any one of the POE4F,
POE5F, POE6F, POE7F, and MTU2SHIZ bits is set
to 1.
0: Does not compare output levels or place the pins in
high-impedance state.
1: Compares output levels and places the pins in
high-impedance state.
Note:
*
Can be modified only once after a power-on reset.
Page 726 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
13.4
Section 13 Port Output Enable 2 (POE2)
Operation
Table 13.4 shows the target pins for high-impedance control and conditions to place the pins in
high-impedance state.
Table 13.4 Target Pins and Conditions for High-Impedance Control
Pins
Conditions
Detailed Conditions
MTU2 high-current pins
(PE9/TIOC3B and
PE11/TIOC3D)
Input level detection,
output level comparison, or
SPOER setting
MTU2P1CZE
((POE3F+POE2F+POE1F+POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2 high-current pins
(PE12/TIOC4A and
PE14/TIOC4C)
Input level detection,
output level comparison, or
SPOER setting
MTU2P2CZE
((POE3F+POE2F+POE1F+POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2 high-current pins
(PE13/TIOC4B and
PE15/TIOC4D)
Input level detection,
output level comparison, or
SPOER setting
MTU2P3CZE
((POE3F+POE2F+POE1F+POE0F) +
(OSF1 • OCE1) + (MTU2CH34HIZ))
MTU2S high-current pins
(PE5/TIOC3BS and
PE6/TIOC3DS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP1CZE
((POE4F+POE5F+POE6F+POE7F) +
(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PE0/TIOC4A and
PE2/TIOC4CS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP2CZE
((POE4F+POE5F+POE6F+POE7F) +
(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PE1/TIOC4BS and
PE3/TIOC4DS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP3CZE
((POE4F+POE5F+POE6F+POE7F) +
(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PD10/TIOC3BS and
PD11/TIOC3DS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP4CZE
((POE4F+POE5F+POE6F+POE7F)
+(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PD12/TIOC4AS and
PD14/TIOC4CS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP5CZE
((POE4F+POE5F+POE6F+POE7F)
+(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PD13/TIOC4BS and
PD15/TIOC4DS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP6CZE
((POE4F+POE5F+POE6F+POE7F)
+(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PD29/TIOC3BS and
PD28/TIOC3DS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP7CZE
((POE4F+POE5F+POE6F+POE7F)
+(OSF2 • OCE2) + (MTU2SHIZ))
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 727 of 1778
Section 13 Port Output Enable 2 (POE2)
SH7280 Group, SH7243 Group
Pins
Conditions
Detailed Conditions
MTU2S high-current pins
(PD27/TIOC4AS and
PD25/TIOC4CS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP8CZE
((POE4F+POE5F+POE6F+POE7F)
+(OSF2 • OCE2) + (MTU2SHIZ))
MTU2S high-current pins
(PD26/TIOC4BS and
PD24/TIOC4DS)
Input level detection,
output level comparison, or
SPOER setting
MTU2SP9CZE
((POE4F+POE5F+POE6F+POE7F)
+(OSF2 • OCE2) + (MTU2SHIZ))
MTU2 CH0 pins
(PE0/TIOC0A,
PE1/TIOC0B,
PE2/TIOC0C, and
PE3/TIOC0D)
Input level detection or
SPOER setting
MTU2PE0ZE to MTU2PE3ZE
(POE8F • POE8E) +(MTU2CH0HIZ)
Page 728 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
13.4.1
Section 13 Port Output Enable 2 (POE2)
Input Level Detection Operation
If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current
pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however,
that these high-current and MTU2 pins enter high-impedance state only when general input/output
function, MTU2 function, or MTU2S function is selected for these pins.
(1)
Falling Edge Detection
When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins
and the pins for channel 0 of the MTU2 are placed in high-impedance state.
Figure 13.2 shows the sample timing after the level changes in input to the POE0 to POE8 pins
until the respective pins enter high-impedance state.
Pφ
Pφ rising edge
POE input
Falling edge detection
PE9/
TIOC3B
High-impedance state
Note: The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing.
Figure 13.2 Falling Edge Detection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 729 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
(2)
Low-Level Detection
Figure 13.3 shows the low-level detection operation. Sixteen continuous low levels are sampled
with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this
interval, the low level is not accepted.
The timing when the high-current pins enter the high-impedance state after the sampling clock is
input is the same in both falling-edge detection and in low-level detection.
8/16/128 clock
cycles
Pφ
Sampling
clock
POE input
PE9/TIOC3B
High-impedance state*
When low level is
sampled at all points
(1)
(2)
When high level is
sampled at least once
(1)
(2)
(3)
(16)
Flag set
(POE received)
(13)
Flag not set
Note: * The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing.
Figure 13.3 Low-Level Detection Operation
13.4.2
Output-Level Compare Operation
Figure 13.4 shows an example of the output-level compare operation for the combination of
TIOC3B and TIOC3D. The operation is the same for the other pin combinations.
Pφ
Low level overlapping detected
PE9/
TIOC3B
PE11/
TIOC3D
High impedance state
Figure 13.4 Output-Level Compare Operation
Page 730 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
13.4.3
Section 13 Port Output Enable 2 (POE2)
Release from High-Impedance State
High-current pins that have entered high-impedance state due to input-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing all of
the flags in bits 15 to 12 (POE8F to POE0F) of ICSR1 to ICSR3. However, note that when lowlevel sampling is selected by bits 7 to 0 in ICSR1 to ICSR3, just writing 0 to a flag is ignored (the
flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to one of
the POE0 to POE8 pins and is sampled.
High-current pins that have entered high-impedance state due to output-level detection can be
released either by returning them to their initial state with a power-on reset, or by clearing the flag
in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is
ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the
high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S
internal registers.
13.5
Interrupts
The POE2 issues a request to generate an interrupt when the specified condition is satisfied during
input level detection or output level comparison. Table 13.5 shows the interrupt sources and their
conditions.
Table 13.5 Interrupt Sources and Conditions
Name
Interrupt Source
Interrupt Flag
Condition
OEI1
Output enable interrupt 1
POE3F, POE2F, POE1F,
POE0F, and OSF1
PIE1 • (POE3F + POE2F +
POE1F + POE0F) + OIE1 •
OSF1
OEI2
Output enable interrupt 2
POE8F
PIE3 • POE8F
OEI3
Output enable interrupt 3
POE4F, POE5F, POE6F,
POE7F, and OSF2
PIE2 • (POE4F + POE5F +
POE6F + POE7F) + OIE2 •
OSF2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 731 of 1778
SH7280 Group, SH7243 Group
Section 13 Port Output Enable 2 (POE2)
13.6
Usage Notes
13.6.1
Pins States when the Watchdog Timer has Issued a Power-on Reset
A power-on reset issued from the watchdog timer (WDT) initializes the pin-function controller
(PFC) and all I/O port pins thus become general-purpose inputs in accord with the initial PFC
settings. However, when a power-on reset is issued while the port-output enable (POE) setting is
for high-impedance handling by the pins, the pins remain in the output state for an interval of one
cycle of the peripheral clock (Pφ) before switching to operation as general-purpose inputs.
The same condition applies when the WDT issues a power-on reset and short-circuit detection by
the MTU2 has led to high-impedance handling by a pin.
Figure 13.5 shows the situation where timer output has been selected and the WDT issues a
power-on reset while high-impedance handling is in progress due to the POE input.
Pφ
POE input
Pin state
Timer
General-purpose input
output
Timer output
High-impedance state
1 period of 1Pφ
PFC setting
Timer output
General-purpose input
Power-on reset
by the WDT
Figure 13.5 Pin States when the Watchdog Timer Issues a Power-on Reset
Page 732 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
Section 14 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.
The CMT has a16-bit counter, and can generate interrupts at set intervals.
14.1
Features
• Independent selection of four counter input clocks at two channels
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.
• Selection of DTC/DMA transfer request or interrupt request generation on compare match by
DTC/DMA setting
• When not in use, the CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 14.1 shows a block diagram of CMT.
CMI1
Pφ/512
Control circuit
Pφ/32
Pφ/128
Pφ/512
Clock selection
CMCNT_1
Clock selection
Pφ/8
Comparator
Pφ/128
CMCNT_0
Comparator
CMCOR_0
CMCSR_0
CMSTR
Control circuit
Pφ/32
CMCOR_1
Pφ/8
CMCSR_1
CMI0
Channel 0
Module bus
Channel 1
Bus
interface
CMT
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
Peripheral bus
Compare match timer start register
Compare match timer control/status register
Compare match constant register
Compare match counter
Compare match interrupt
Figure 14.1 Block Diagram of CMT
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 733 of 1778
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.2
Register Descriptions
The CMT has the following registers.
Table 14.1 Register Configuration
Channel
Register Name
Abbreviation
R/W
Initial
Value
Address
Common
Compare match timer start register
CMSTR
R/W
H'0000
H'FFFEC000 16
0
Compare match timer control/
status register_0
CMCSR_0
R/(W)* H'0000
H'FFFEC002 16
Compare match counter_0
CMCNT_0
R/W
H'0000
H'FFFEC004 16
Compare match constant register_0
CMCOR_0
R/W
H'FFFF
H'FFFEC006 16
Compare match timer control/
status register_1
CMCSR_1
R/(W)* H'0000
H'FFFEC008 16
Compare match counter_1
CMCNT_1
R/W
H'0000
H'FFFEC00A 16
Compare match constant register_1
CMCOR_1
R/W
H'FFFF
H'FFFEC00C 16
1
Page 734 of 1778
Access
Size
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
14.2.1
Section 14 Compare Match Timer (CMT)
Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is
stopped.
CMSTR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STR1
STR0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
STR1
0
R/W
Count Start 1
Specifies whether compare match counter_1 operates
or is stopped.
0: CMCNT_1 count is stopped
1: CMCNT_1 count is started
0
STR0
0
R/W
Count Start 0
Specifies whether compare match counter_0 operates
or is stopped.
0: CMCNT_0 count is stopped
1: CMCNT_0 count is started
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 735 of 1778
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.2.2
Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables or disables
interrupts, and selects the counter input clock.
CMCSR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
-
-
-
-
-
CMF
CMIE
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
R/(W)* R/W
0
R
0
R
0
R
0
R
1
0
CKS[1:0]
0
R/W
0
R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/(W)* Compare Match Flag
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match.
[Clearing condition]
•
When 0 is written to CMF after reading CMF = 1
•
When data is transferred after the DTC has been
activated by CMI (except when the DTC transfer
counter value has become H'000).
•
When data is transferred after the DMAC has been
activated by CMI
1: CMCNT and CMCOR values match
6
CMIE
0
R/W
Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Page 736 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
Bit
Bit Name
Initial
Value
R/W
Description
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1, 0
CKS[1:0]
00
R/W
Clock Select
These bits select the clock to be input to CMCNT from
four internal clocks obtained by dividing the peripheral
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS[1:0].
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note:
*
Only 0 can be written to clear the flag after 1 is read.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 737 of 1778
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.2.3
Compare Match Counter (CMCNT)
CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with
bits CKS[1:0] in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using
the selected clock. When the value in CMCNT and the value in compare match constant register
(CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
CMCNT is initialized to H'0000 by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Bit:
Initial value:
R/W:
14.2.4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Compare Match Constant Register (CMCOR)
CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT.
CMCOR is initialized to H'FFFF by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Page 738 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.3
Operation
14.3.1
Interval Count Operation
When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR
is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and
CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the
CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 14.2 shows the operation of the compare match counter.
CMCNT value
Counter cleared by compare
match with CMCOR
CMCOR
H'0000
Time
Figure 14.2 Counter Operation
14.3.2
CMCNT Count Timing
One of four clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the peripheral clock
(Pφ) can be selected with the CKS[1:0] bits in CMCSR. Figure 14.3 shows the timing.
Peripheral clock
(Pφ)
Count clock
Clock
N
CMCNT
Clock
N+1
N
N+1
Figure 14.3 Count Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 739 of 1778
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.4
Interrupts
14.4.1
Interrupt Sources and DTC/DMA Transfer Requests
The CMT has channels and each of them to which a different vector address is allocated has a
compare match interrupt. When both the interrupt request flag (CMF) and the interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 6, Interrupt Controller (INTC).
Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out,
another interrupt will be generated. The direct memory access controller (DMAC) can be set to be
activated when a compare match interrupt is requested. In this case, an interrupt is not issued to
the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the
CPU. The CMF bit is automatically cleared to 0 when data is transferred by the DMAC.
The data transfer controller (DTC) can be activated by an interrupt request. In this case, the
priority between channels is fixed. For details, refer to section 8, Data Transfer Controller (DTC).
Table 14.2 Interrupt Sources
Channel
Interrupt Source
Interrupt Enable
Bit
Interrupt
Flag
DMAC/DTC
Activation
Priority
0
CMI0
CMIE
CMF
Possible
High
1
CMI1
CMIE
CMF
Possible
Low
14.4.2
Timing of Compare Match Flag Setting
When CMCOR and CMCNT match, a compare match signal is generated at the last state in which
the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in
CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match
signal is not generated until the next CMCNT counter clock input. Figure 14.4 shows the timing of
CMF bit setting.
Page 740 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
Peripheral clock
(Pφ)
Counter clock
Clock
N+1
CMCNT
N
CMCOR
N
0
CMF
Figure 14.4 Timing of CMF Setting
14.4.3
Timing of Compare Match Flag Clearing
The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of
the DMAC being activated, the CMF bit is automatically cleared to 0 when data is transferred by
the DMAC.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 741 of 1778
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.5
Usage Notes
14.5.1
Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows
the timing to clear the CMCNT counter.
CMCSR write cycle
T1
T2
Peripheral clock
(Pφ)
Address signal
CMCNT
Internal write signal
Counter clear signal
CMCNT
N
H'0000
Figure 14.5 Conflict between Write and Compare Match Processes of CMCNT
Page 742 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
14.5.2
Section 14 Compare Match Timer (CMT)
Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the
timing to write to CMCNT in words.
CMCSR write cycle
T1
T2
Peripheral clock
(Pφ)
Address signal
CMCNT
Internal write signal
CMCNT count-up
enable signal
CMCNT
N
M
Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 743 of 1778
SH7280 Group, SH7243 Group
Section 14 Compare Match Timer (CMT)
14.5.3
Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has
priority over the count-up. In this case, the count-up is not performed. The byte data on the other
side, which is not written to, is also not counted and the previous contents are retained.
Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to
CMCNTH in bytes.
CMCSR write cycle
T1
T2
Peripheral clock
(Pφ)
Address signal
CMCNTH
Internal write signal
CMCNT count-up
enable signal
CMCNTH
N
M
CMCNTL
X
X
Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
14.5.4
Compare Match between CMCNT and CMCOR
Do not set a same value to CMCNT and CMCOR while the count operation of CMCNT is
stopped.
Page 744 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
Section 15 Watchdog Timer (WDT)
This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal
(WDTOVF) on overflow of the counter when the value of the counter has not been updated
because of a system malfunction. The WDT can simultaneously generate an internal reset signal
for the entire LSI.
The WDT is a single channel timer that counts up the clock oscillation settling period when the
system leaves the temporary standby periods that occur when the clock frequency is changed. It
can also be used as a general watchdog timer or interval timer.
15.1
Features
• Can be used to ensure the clock oscillation settling time
The WDT is used in leaving the temporary standby periods that occur when the clock
frequency is changed.
• Can switch between watchdog timer mode and interval timer mode.
• Outputs WDTOVF signal in watchdog timer mode
When the counter overflows in watchdog timer mode, the WDTOVF signal is output
externally. It is possible to select whether to reset the LSI internally when this happens. Either
the power-on reset or manual reset signal can be selected as the internal reset type.
• Interrupt generation in interval timer mode
An interval timer interrupt is generated when the counter overflows.
• Choice of eight counter input clocks
Eight clocks (Pφ × 1 to Pφ × 1/16384) that are obtained by dividing the peripheral clock can be
selected.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 745 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
Figure 15.1 shows a block diagram of the WDT.
WDT
Peripheral
clock
Divider
Interrupt
request
Interrupt
control
Clock selection
Clock selector
WDTOVF
Internal reset
request*
Reset
control
Overflow
WRCSR
WTCSR
Clock
WTCNT
Bus interface
Peripheral bus
[Legend]
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
WRCSR: Watchdog reset control/status register
Note: * The internal reset signal can be generated by making a register setting.
Figure 15.1 Block Diagram of WDT
Page 746 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
15.2
Section 15 Watchdog Timer (WDT)
Input/Output Pin
Table 15.1 shows the pin configuration of the WDT.
Table 15.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Watchdog timer overflow
WDTOVF
Output
Outputs the counter overflow signal in
watchdog timer mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 747 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
15.3
Register Descriptions
The WDT has the following registers.
Table 15.2 Register Configuration
Register Name
Abbreviation R/W
Initial
Value
Address
Access
Size
Watchdog timer counter
WTCNT
R/W
H'00
H'FFFE0002
16*
Watchdog timer control/status
register
WTCSR
R/W
H'18
H'FFFE0000
16*
Watchdog reset control/status
register
WRCSR
R/W
H'1F
H'FFFE0004
16*
Note:
15.3.1
*
For the access size, see section 15.3.4, Notes on Register Access.
Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock
signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in
watchdog timer mode and an interrupt in interval timer mode.
WTCNT is initialized to H'00 by a power-on reset caused by the RES pin or in software standby
mode.
Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read
from WTCNT.
Note: The method for writing to WTCNT differs from that for other registers to prevent
erroneous writes. See section 15.3.4, Notes on Register Access, for details.
Bit:
Initial value:
R/W:
Page 748 of 1778
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
15.3.2
Section 15 Watchdog Timer (WDT)
Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
WTCSR is initialized to H'18 by a power-on reset caused by the RES pin, an internal reset caused
by the WDT, or in software standby mode.
Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
erroneous writes. See section 15.3.4, Notes on Register Access, for details.
Bit:
7
6
5
4
3
IOVF
WT/IT
TME
-
-
0
R/W
0
R/W
1
R
1
R
0
Initial value:
R/W: R/(W)
2
1
0
CKS[2:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
IOVF
0
R/(W)
Interval Timer Overflow
0
R/W
Indicates that WTCNT has overflowed in interval timer
mode. This flag is not set in watchdog timer mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
When 0 is written to IOVF after reading IOVF
Page 749 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Use as interval timer
1: Use as watchdog timer
Note: When the WTCNT overflows in watchdog timer
mode, the WDTOVF signal is output externally.
If this bit is modified when the WDT is running,
the up-count may not be performed correctly.
5
TME
0
R/W
Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled
Count-up stops and WTCNT value is retained
1: Timer enabled
4, 3
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
Page 750 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
CKS[2:0]
000
R/W
Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown in the table is the value when the peripheral
clock (Pφ) is 40 MHz.
Bits 2 to 0
Clock Ratio
Overflow Cycle
000:
1 × Pφ
6.4 μs
001:
1/64 × Pφ
409.6 μs
010:
1/128 × Pφ
819.2 ms
011:
1/256 × Pφ
1.64 ms
100:
1/512 × Pφ
3.3 ms
101:
1/1024 × Pφ
6.6 ms
110:
1/4096 × Pφ
26.2 ms
111:
1/16384 × Pφ
104.9 ms
Note: If bits CKS[2:0] are modified when the WDT is
running, the up-count may not be performed
correctly. Ensure that these bits are modified
only when the WDT is not running.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 751 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
15.3.3
Watchdog Reset Control/Status Register (WRCSR)
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
WRCSR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by
the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in
software standby mode.
Note: The method for writing to WRCSR differs from that for other registers to prevent
erroneous writes. See section 15.3.4, Notes on Register Access, for details.
7
6
5
4
3
2
1
WOVF
RSTE
RSTS
-
-
-
-
-
0
Initial value:
R/W: R/(W)
0
R/W
0
R/W
1
R
1
R
1
R
1
R
1
R
Bit:
Bit
Bit Name
Initial
Value
R/W
Description
7
WOVF
0
R/(W)
Watchdog Timer Overflow
0
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
•
6
RSTE
0
R/W
When 0 is written to WOVF after reading WOVF
Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: *
Page 752 of 1778
LSI not reset internally, but WTCNT and
WTCSR reset within WDT.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
5
RSTS
0
R/W
Reset Select
Selects the type of reset when the WTCNT overflows
in watchdog timer mode. In interval timer mode, this
setting is ignored.
0: Power-on reset
1: Manual reset
4 to 0
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
15.3.4
Notes on Register Access
The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and
watchdog reset control/status register (WRCSR) are more difficult to write to than other registers.
The procedures for reading or writing to these registers are given below.
(1)
Writing to WTCNT and WTCSR
These registers must be written by a word transfer instruction. They cannot be written by a byte or
longword transfer instruction.
When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,
as shown in figure 15.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the
lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or
WTCSR.
WTCNT write
15
WTCSR write
8
15
Address: H'FFFE0000
0
7
H'5A
Address: H'FFFE0002
Write data
8
7
H'A5
0
Write data
Figure 15.2 Writing to WTCNT and WTCSR
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 753 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
(2)
Writing to WRCSR
WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte
transfer or longword transfer instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are
different, as shown in figure 15.3.
To write 0 to the WOVF bit, write H'A5 to the upper byte and write the write data to the lower
byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the
RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The
values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively.
The WOVF bit is not affected.
Writing 0 to the WOVF bit
15
Writing to the RSTE and RSTS bits
Address: H'FFFE0004
8
7
H'A5
Address: H'FFFE0004
15
0
Write data
8
7
H'5A
0
Write data
Figure 15.3 Writing to WRCSR
(3)
Reading from WTCNT, WTCSR, and WRCSR
WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is
allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address
H'FFFE0004. Byte transfer instructions must be used for reading from these registers.
Page 754 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
15.4
WDT Usage
15.4.1
Changing the Frequency
Section 15 Watchdog Timer (WDT)
To change the frequency used by the PLL, use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time.
3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The
WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes
operation. The WOVF flag in WRCSR is not set when this happens.
5. The counter stops at the value of H'00.
6. Before changing WTCNT after execution of the frequency change instruction, always confirm
that the value of WTCNT is H'00 by reading from WTCNT.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 755 of 1778
Section 15 Watchdog Timer (WDT)
15.4.2
SH7280 Group, SH7243 Group
Using Watchdog Timer Mode
1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR,
whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it
is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
the counter from overflowing.
4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the
WDTOVF signal is output externally (figure 15.4). The WDTOVF signal can be used to reset
the system. The WDTOVF signal is output for 64 × Pφ clock cycles.
5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated
simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be
selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for
128 × Pφ clock cycles.
6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin,
the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.
7. Since WTCSR is initialized by an internal reset caused by the WDT, the TME bit in WTCSR
is cleared to 0. This makes the counter stop (be initialized). To use the WDT in watchdog timer
mode again, after clearing the WOVF flag in WRCSR, set watchdog timer mode again.
Page 756 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
WTCNT
value
Overflow
H'FF
H'00
Time
H'00 written
in WTCNT
WT/IT = 1
TME = 1
WOVF = 1
WT/IT = 1
TME = 1
WDTOVF and internal reset generated
H'00 written
in WTCNT
WDTOVF
signal
64 × Pφ clock cycles
Internal
reset signal*
128 × Pφ clock cycles
[Legend]
WT/IT: Timer mode select bit
TME:
Timer enable bit
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 15.4 Operation in Watchdog Timer Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 757 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
15.4.3
Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in
WTCSR, and set the initial value of the counter in WTCNT.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF bit in WTCSR to 1 and an interval timer
interrupt request is sent to the INTC. The counter then resumes counting.
WTCNT value
Overflow
Overflow
Overflow
Overflow
H'FF
H'00
Time
WT/IT = 0
TME = 1
ITI
ITI
ITI
ITI
[Legend]
ITI: Interval timer interrupt request generation
Figure 15.5 Operation in Interval Timer Mode
Page 758 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
15.5
Section 15 Watchdog Timer (WDT)
Interrupt Source
The watchdog timer has the interval timer interrupt (ITI).
Table 15.3 gives details on this interrupt source.
The interval timer interrupt (ITI) is generated when the interval timer overflow flag (IOVF) in the
watchdog timer control/status register (WTCSR) is set to 1.
Clearing the interrupt flag bit to 0 cancels the interrupt request.
Table 15.3 Interrupt Source
Abbreviation
Interrupt Source
Interrupt Enable Bit
Interrupt Flag
ITI
Interval timer interrupt
⎯
Interval timer overflow flag
(IOVF)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 759 of 1778
SH7280 Group, SH7243 Group
Section 15 Watchdog Timer (WDT)
15.6
Usage Notes
Pay attention to the following points when using the WDT in either the interval timer or watchdog
timer mode.
15.6.1
Timer Variation
After timer operation has started, the period from the power-on reset point to the first count up
timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The
shortest such time period is thus one cycle of the peripheral clock, Pφ, while the longest is the
result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent
incrementation is in accord with the selected frequency division ratio. Accordingly, this time
difference is referred to as timer variation.
This also applies to the timing of the first incrementation after WTCNT has been written to during
timer operation.
15.6.2
Prohibition against Setting H'FF to WTCNT
When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred.
Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur
immediately, regardless of the current clock selection by the CKS[2:0] bits.
15.6.3
System Reset by WDTOVF Signal
If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.
Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To
reset the entire system with the WDTOVF signal, use the circuit shown in figure 15.6.
Reset input
Reset signal to
entire system
RES
WDTOVF
Figure 15.6 Example of System Reset Circuit Using WDTOVF Signal
Page 760 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
15.6.4
Section 15 Watchdog Timer (WDT)
Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the internal bus (I bus) cycle is continued. If
a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset
exception handling will be pended until the CPU acquires the bus mastership.
15.6.5
Connection of the WDTOVF Pin
When the WDTOVF pin is not in use, leave the pin open-circuit. The WDTOVF pin should not be
pulled down. If pulling down is required, connect a resistor whose value is at least 1 MΩ.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 761 of 1778
Section 15 Watchdog Timer (WDT)
Page 762 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Section 16 Serial Communication Interface (SCI)
This LSI has four channels (SH7286 and SH7285) or two channels (SH7243) of independent
serial communication interface (SCI). The SCI can handle both asynchronous and clock
synchronous serial communication. In asynchronous serial communication mode, serial data
communication can be carried out with standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function).
16.1
Features
• Choice of asynchronous or clock synchronous serial communication mode
• Asynchronous mode:
⎯ Serial data communication is performed by start-stop in character units. The SCIF can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are twelve selectable serial data
communication formats.
⎯ Data length: 7 or 8 bits
⎯ Stop bit length: 1 or 2 bits
⎯ Parity: Even, odd, or none
⎯ Multiprocessor communications
⎯ Receive error detection: Parity, overrun, and framing errors
⎯ Break detection: Break is detected by reading the RXD pin level directly when a framing
error occurs.
• Clock synchronous mode:
⎯ Serial data communication is synchronized with a clock signal. The SCIF can communicate
with other chips having a clock synchronous communication function.
⎯ Data length: 8 bits
⎯ Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so highspeed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal
clock) or SCK pin (external clock)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 763 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
• Choice of LSB-first or MSB-first data transfer (except for 7-bit data in asynchronous mode)
• Four types of interrupts: There are four interrupt sources, transmit-data-empty, transmit end,
receive-data-full, and receive error interrupts, and each interrupt can be requested
independently. The data transfer controller (DTC) can be activated by the transmit-data-empty
interrupt or receive-data-full interrupt to transfer data.
• Module standby mode can be set
Bus interface
Figure 16.1 shows a block diagram of the SCI.
Module data bus
SCRDR
SCTDR
SCSSR
Peripheral
bus
SCBRR
SCSCR
SCSMR
Baud rate
generator
SCSPTR
RXD
SCRSR
SCTSR
TXD
Parity generation
SCSDCR
Transmission/reception
control
Pφ
Pφ/4
Pφ/16
Pφ/64
Clock
Parity check
External clock
SCK
TEI
TXI
RXI
ERI
SCI
[Legend]
SCRSR:
SCRDR:
SCTSR:
SCTDR:
SCSMR:
SCSCR:
SCSSR:
SCBRR:
SCSPTR:
SCSDCR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Serial port register
Serial direction control register
Figure 16.1 Block Diagram of SCI
Page 764 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.2
Section 16 Serial Communication Interface (SCI)
Input/Output Pins
The SCI has the serial pins summarized in table 16.1.
Table 16.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
SCI0 clock input/output
RXD0
Input
SCI0 receive data input
TXD0
Output
SCI0 transmit data output
SCK1
I/O
SCI1 clock input/output (SH7286 and SH7285)
1
2
4
Note:
*
RXD1
Input
SCI1 receive data input (SH7286 and SH7285)
TXD1
Output
SCI1 transmit data output (SH7286 and SH7285)
SCK2
I/O
SCI2 clock input/output
RXD2
Input
SCI2 receive data input
TXD2
Output
SCI2 transmit data output
SCK4
I/O
SCI4 clock input/output (SH7286 and SH7285)
RXD4
Input
SCI4 receive data input (SH7286 and SH7285)
TXD4
Output
SCI4 transmit data output (SH7286 and SH7285)
Pin names SCK, RXD, and TXD are used in the description for all channels, omitting
the channel designation.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 765 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.3
Register Descriptions
The SCI has the following registers for each channel. For details on register addresses and register
states during each processing, refer to section 30, List of Registers.
Table 16.2 Register Configuration
Channel
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
0
Serial mode register_0
SCSMR_0
R/W
H'00
H'FFFF8000
8
Bit rate register_0
SCBRR_0
R/W
H'FF
H'FFFF8002
8
Serial control register_0
SCSCR_0
R/W
H'00
H'FFFF8004
8
Transmit data register_0
SCTDR_0
R/W
⎯
H'FFFF8006
8
1
(only for
SH7286
and
SH7285)
2
Serial status register_0
SCSSR_0
R/W
H'84
H'FFFF8008
8
Receive data register_0
SCRDR_0
R
⎯
H'FFFF800A
8
Serial direction control
register_0
SCSDCR_0
R/W
H'F2
H'FFFF800C
8
Serial port register_0
SCSPTR_0
R/W
H'0x
H'FFFF800E
8
Serial mode register_1
SCSMR_1
R/W
H'00
H'FFFF8800
8
Bit rate register_1
SCBRR_1
R/W
H'FF
H'FFFF8802
8
Serial control register_1
SCSCR_1
R/W
H'00
H'FFFF8804
8
Transmit data register_1
SCTDR_1
R/W
⎯
H'FFFF8806
8
Serial status register_1
SCSSR_1
R/W
H'84
H'FFFF8808
8
Receive data register_1
SCRDR_1
R
⎯
H'FFFF880A
8
Serial direction control
register_1
SCSDCR_1
R/W
H'F2
H'FFFF880C
8
Serial port register_1
SCSPTR_1
R/W
H'0x
H'FFFF880E
8
Serial mode register_2
SCSMR_2
R/W
H'00
H'FFFF9000
8
Bit rate register_2
SCBRR_2
R/W
H'FF
H'FFFF9002
8
Serial control register_2
SCSCR_2
R/W
H'00
H'FFFF9004
8
Transmit data register_2
SCTDR_2
R/W
⎯
H'FFFF9006
8
Serial status register_2
SCSSR_2
R/W
H'84
H'FFFF9008
8
Receive data register_2
SCRDR_2
R
⎯
H'FFFF900A
8
Serial direction control
register_2
SCSDCR_2
R/W
H'F2
H'FFFF900C
8
Serial port register_2
SCSPTR_2
R/W
H'0x
H'FFFF900E
8
Page 766 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Channel
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
4
(only for
SH7286
and
SH7285)
Serial mode register_4
SCSMR_4
R/W
H'00
H'FFFFA000
8
Bit rate register_4
SCBRR_4
R/W
H'FF
H'FFFFA002
8
Serial control register_4
SCSCR_4
R/W
H'00
H'FFFFA004
8
Transmit data register_4
SCTDR_4
R/W
⎯
H'FFFFA006
8
16.3.1
Serial status register_4
SCSSR_4
R/W
H'84
H'FFFFA008
8
Receive data register_4
SCRDR_4
R
⎯
H'FFFFA00A
8
Serial direction control
register_4
SCSDCR_4
R/W
H'F2
H'FFFFA00C
8
Serial port register_4
SCSPTR_4
R/W
H'0x
H'FFFFA00E
8
Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly.
16.3.2
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
-
-
-
-
-
-
-
-
Receive Data Register (SCRDR)
SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI
transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and
completes operation. After that, SCRSR is ready to receive data.
Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously.
SCRDR is a read-only register and cannot be written to by the CPU.
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 767 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.3.3
Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR)
into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After
transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into
SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set
to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to
SCTSR directly.
16.3.4
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
-
-
-
-
-
-
-
-
Transmit Data Register (SCTDR)
SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the
transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into
SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during
serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be
written or read to by the CPU.
Bit:
7
Initial value:
R/W: R/W
16.3.5
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial Mode Register (SCSMR)
SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read and write to SCSMR.
Bit:
7
6
5
4
3
2
C/A
CHR
PE
O/E
STOP
MP
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value: 0
R/W: R/W
Page 768 of 1778
1
0
CKS[1:0]
0
R/W
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
Description
7
C/A
0
R/W
Communication Mode
Selects whether the SCI operates in asynchronous or
clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode
6
CHR
0
R/W
Character Length
Selects 7-bit or 8-bit data in asynchronous mode. In the
clock synchronous mode, the data length is always
eight bits, regardless of the CHR setting. When 7-bit
data is selected, the MSB (bit 7) of the transmit data
register is not transmitted.
0: 8-bit data
1: 7-bit data
5
PE
0
R/W
Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In clock synchronous mode, a parity bit is neither
added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit
is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity
is checked according to the even/odd (O/E)
mode setting.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 769 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
Description
4
O/E
0
R/W
3
STOP
0
R/W
Parity mode
Selects even or odd parity when parity bits are added
and checked. The O/E setting is used only in
asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking.
The O/E setting is ignored in clock synchronous mode,
or in asynchronous mode when parity addition and
checking is disabled.
0: Even parity
1: Odd parity
If even parity is selected, the parity bit is added to
transmit data to make an even number of 1s in the
transmitted character and parity bit combined. Receive
data is checked to see if it has an even number of 1s in
the received character and parity bit combined.
If odd parity is selected, the parity bit is added to
transmit data to make an odd number of 1s in the
transmitted character and parity bit combined. Receive
data is checked to see if it has an odd number of 1s in
the received character and parity bit combined.
Stop Bit Length
Selects one or two bits as the stop bit length in
asynchronous mode. This setting is used only in
asynchronous mode. It is ignored in clock synchronous
mode because no stop bits are added.
1
0: One stop bit*
1: Two stop bits*2
When receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
Notes: 1. When transmitting, a single 1-bit is added at
the end of each transmitted character.
2. When transmitting, two 1 bits are added at the
end of each transmitted character.
2
MP
0
R/W
Multiprocessor Mode (only in asynchronous mode)
Enables or disables multiprocessor mode. The PE and
O/E bit settings are ignored in multiprocessor mode.
0: Multiprocessor mode disabled
1: Multiprocessor mode enabled
Page 770 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
Description
1, 0
CKS[1:0]
00
R/W
Clock Select 1 and 0
Select the internal clock source of the on-chip baud rate
generator. Four clock sources are available; Pφ, Pφ/4,
Pφ/16, and Pφ/64.
For further information on the clock source, bit rate
register settings, and baud rate, see section 16.3.10, Bit
Rate Register (SCBRR).
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 771 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.3.6
Serial Control Register (SCSCR)
SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt
requests and selects the transmit/receive clock source. The CPU can always read and write to
SCSCR.
Bit:
7
6
5
4
3
2
TIE
RIE
TE
RE
MPIE
TEIE
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial value: 0
R/W: R/W
1
0
CKE[1:0]
0
R/W
Bit
Bit Name
Initial
value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
0
R/W
Enables or disables a transmit-data-empty interrupt
(TXI) to be issued when the TDRE flag in the serial
status register (SCSSR) is set to 1 after serial transmit
data is sent from the transmit data register (SCTDR) to
the transmit shift register (SCTSR).
TXI can be canceled by clearing the TDRE flag to 0
after reading TDRE = 1 or by clearing the TIE bit to 0.
0: Transmit-data-empty interrupt request (TXI) is
disabled
1: Transmit-data-empty interrupt request (TXI) is
enabled
6
RIE
0
R/W
Receive Interrupt Enable
Enables or disables a receive-data-full interrupt (RXI)
and a receive error interrupt (ERI) to be issued when
the RDRF flag in SCSSR is set to 1 after the serial data
received is transferred from the receive shift register
(SCRSR) to the receive data register (SCRDR).
RXI can be canceled by clearing the RDRF flag after
reading RDRF =1. ERI can be canceled by clearing the
FER, PER, or ORER flag to 0 after reading 1 from the
flag. Both RXI and ERI can also be canceled by
clearing the RIE bit to 0.
0: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are disabled
1: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are enabled
Page 772 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
Description
5
TE
0
R/W
Transmit Enable
Enables or disables the SCI serial transmitter.
1
0: Transmitter disabled*
1: Transmitter enabled*
2
Notes: 1. The TDRE flag in SCSSR is fixed at 1.
2. Serial transmission starts after writing
transmit data into SCTDR and clearing the
TDRE flag in SCSSR to 0 while the
transmitter is enabled. Select the transmit
format in the serial mode register (SCSMR)
before setting TE to 1.
4
RE
0
R/W
Receive Enable
Enables or disables the SCI serial receiver.
0: Receiver disabled*
1
2
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
flags (RDRF, FER, PER, and ORER). These
flags retain their previous values.
2. Serial reception starts when a start bit is
detected in asynchronous mode, or
synchronous clock input is detected in clock
synchronous mode. Select the receive
format in SCSMR before setting RE to 1.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (only when MP = 1 in
SCSMR in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped and setting of the
RDRF, FER, and ORER status flags in SCSSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
to 0 and normal receiving operation is resumed. For
details, refer to section 16.4.4, Multiprocessor
Communication Function.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 773 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
Description
2
TEIE
0
R/W
Transmit End Interrupt Enable
Enables or disables a transmit end interrupt (TEI) to be
issued when no valid transmit data is found in SCTDR
during MSB data transmission.
TEI can be canceled by clearing the TEND flag to 0 (by
clearing the TDRE flag in SCSSR to 0 after reading
TDRE = 1) or by clearing the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled
1: Transmit end interrupt request (TEI) is enabled
1, 0
CKE[1:0]
00
R/W
Clock Enable 1 and 0
Select the SCI clock source and enable or disable clock
output from the SCK pin. Depending on the
combination of CKE1 and CKE0, the SCK pin can be
used for serial clock output or serial clock input.
When selecting the clock output in clock synchronous
mode, set the C/A bit in SCSMR to 1 and then set bits
CKE1 and CKE0. For details on clock source selection,
refer to table 16.14.
•
Asynchronous mode
00: Internal clock, SCK pin used for input pin (The input
signal is ignored.)
1
01: Internal clock, SCK pin used for clock output*
10: External clock, SCK pin used for clock input*
2
2
11: External clock, SCK pin used for clock input*
•
Clock synchronous mode
00: Internal clock, SCK pin used for synchronous clock
output
01: Internal clock, SCK pin used for synchronous clock
output
10: External clock, SCK pin used for synchronous clock
input
11: External clock, SCK pin used for synchronous clock
input
Notes: 1. The output clock frequency is 16 times the
bit rate.
2. The input clock frequency is 16 times the bit
rate.
Page 774 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.3.7
Section 16 Serial Communication Interface (SCI)
Serial Status Register (SCSSR)
SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF,
ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The
TEND flag is a read-only bit and cannot be modified.
Bit:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
1
R
0
R
0
R/W
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
Initial
value
R/W
7
TDRE
1
R/(W)* Transmit Data Register Empty
Description
Indicates whether data has been transferred from the
transmit data register (SCTDR) to the transmit shift
register (SCTSR) and SCTDR has become ready to
be written with next serial transmit data.
0: Indicates that SCTDR holds valid transmit data
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and
transmit data is transferred to SCTDR while the
DISEL bit of MRB in the DTC is 0 (except when
the DTC transfer counter value has become
H'0000).
1: Indicates that SCTDR does not hold valid transmit
data
[Setting conditions]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
•
By a power-on reset or in module standby mode
•
When the TE bit in SCSCR is 0
•
When data is transferred from SCTDR to SCTSR
and data can be written to SCTDR
Page 775 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
6
RDRF
0
R/(W)* Receive Data Register Full
Description
Indicates that the received data is stored in the
receive data register (SCRDR).
0: Indicates that valid received data is not stored in
SCRDR
[Clearing conditions]
•
By a power-on reset or in module standby mode
•
When 0 is written to RDRF after reading RDRF =
1
•
When the DTC is activated by an RXI interrupt
and data is transferred from SCRDR while the
DISEL bit of MRB in the DTC is 0 (except when
the DTC transfer counter value has become
H'0000).
1: Indicates that valid received data is stored in
SCRDR
[Setting condition]
•
When serial reception ends normally and receive
data is transferred from SCRSR to SCRDR
Note: SCRDR and the RDRF flag are not affected and
retain their previous states even if an error is
detected during data reception or if the RE bit in
the serial control register (SCSCR) is cleared to
0. If reception of the next data is completed
while the RDRF flag is still set to 1, an overrun
error will occur and the received data will be
lost.
Page 776 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
5
ORER
0
R/(W)* Overrun Error
Description
Indicates that an overrun error occurred during
reception, causing abnormal termination.
0: Indicates that reception is in progress or was
completed successfully*1
[Clearing conditions]
•
By a power-on reset or in module standby mode
•
When 0 is written to ORER after reading ORER =
1
1: Indicates that an overrun error occurred during
reception*2
[Setting condition]
•
When the next serial reception is completed while
RDRF = 1
Notes: 1. The ORER flag is not affected and retains
its previous value when the RE bit in
SCSCR is cleared to 0.
2. The receive data prior to the overrun error
is retained in SCRDR, and the data
received subsequently is lost. Subsequent
serial reception cannot be continued while
the ORER flag is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 777 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
4
FER
0
R/(W)* Framing Error
Description
Indicates that a framing error occurred during data
reception in asynchronous mode, causing abnormal
termination.
0: Indicates that reception is in progress or was
1
completed successfully*
[Clearing conditions]
•
By a power-on reset or in module standby mode
•
When 0 is written to FER after reading FER = 1
1: Indicates that a framing error occurred during
reception
[Setting condition]
•
When the SCI founds that the stop bit at the end
of the received data is 0 after completing
reception*2
Notes: 1. The FER flag is not affected and retains
its previous value when the RE bit in
SCSCR is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is
checked for a value to 1; the second stop
bit is not checked. If a framing error
occurs, the receive data is transferred to
SCRDR but the RDRF flag is not set.
Subsequent serial reception cannot be
continued while the FER flag is set to 1.
Page 778 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
3
PER
0
R/(W)* Parity Error
Description
Indicates that a parity error occurred during data
reception in asynchronous mode, causing abnormal
termination.
0: Indicates that reception is in progress or was
1
completed successfully*
[Clearing conditions]
•
By a power-on reset or in module standby mode
•
When 0 is written to PER after reading PER = 1
1: Indicates that a parity error occurred during
2
reception*
[Setting condition]
•
When the number of 1s in the received data and
parity does not match the even or odd parity
specified by the O/E bit in the serial mode register
(SCSMR).
Notes: 1. The PER flag is not affected and retains
its previous value when the RE bit in
SCSCR is cleared to 0.
2. If a parity error occurs, the receive data is
transferred to SCRDR but the RDRF flag
is not set. Subsequent serial reception
cannot be continued while the PER flag is
set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 779 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
R/W
Description
2
TEND
1
R
Transmit End
Indicates that no valid data was in SCTDR during
transmission of the last bit of the transmit character
and transmission has ended.
The TEND flag is read-only and cannot be modified.
0: Indicates that transmission is in progress
[Clearing condition]
•
When 0 is written to TDRE after reading TDRE = 1
1: Indicates that transmission has ended
[Setting conditions]
•
By a power-on reset or in module standby mode
•
When the TE bit in SCSCR is 0
•
When TDRE = 1 during transmission of the last bit
of a 1-byte serial transmit character
Note: The TEND flag value becomes undefined if
data is written to SCTDR by activating the DTC
by a TXI interrupt. In this case, do not use the
TEND flag as the transmit end flag.
1
MPB
0
R
Multiprocessor Bit
Stores the multiprocessor bit found in the receive
data. When the RE bit in SCSCR is cleared to 0, its
previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
Specifies the multiprocessor bit value to be added to
the transmit frame.
Note: *
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Page 780 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.3.8
Section 16 Serial Communication Interface (SCI)
Serial Port Register (SCSPTR)
SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the
SCI function pins. Data to be output through the TXD pin can be specified to control break of
serial transfer. Through bits 3 and 2, data reading and writing through the SCK pin can be
specified. Bit 7 enables or disables RXI interrupts. The CPU can always read and write to
SCSPTR. When reading the value on the SCI pins, use the respective port register. For details,
refer to section 24, I/O Ports.
Bit:
7
6
5
4
EIO
-
-
-
Initial value: 0
R/W: R/W
0
-
0
-
0
-
3
2
SPB1IO SPB1DT
0 Undefined
R/W
W
Bit
Bit Name
Initial
value
R/W
Description
7
EIO
0
R/W
Error Interrupt Only
1
0
-
SPB0DT
0
-
1
W
Enables or disables RXI interrupts. While the EIO bit is
set to 1, the SCI does not request an RXI interrupt to
the CPU even if the RIE bit is set to 1.
0: The RIE bit enables or disables RXI and ERI
interrupts. While the RIE bit is 1, RXI and ERI
interrupts are sent to the INTC.
1: While the RIE bit is 1, only the ERI interrupt is sent to
the INTC.
6 to 4
⎯
All 0
⎯
Reserved
These bits are always read as 0. The write value should
always be 0.
3
SPB1IO
0
R/W
Clock Port Input/Output in Serial Port
Specifies the input/output direction of the SCK pin in the
serial port. To output the data specified in the SPB1DT
bit through the SCK pin as a port output pin, set the C/A
bit in SCSMR and the CKE1 and CKE0 bits in SCSCR
to 0.
0: Does not output the SPB1DT bit value through the
SCK pin.
1: Outputs the SPB1DT bit value through the SCK pin.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 781 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Bit
Bit Name
Initial
value
2
SPB1DT
Undefined W
R/W
Description
Clock Port Data in Serial Port
Specifies the data output through the SCK pin in the
serial port. Output should be enabled by the SPB1IO bit
(for details, refer to the SPB1IO bit description). When
output is enabled, the SPB1DT bit value is output
through the SCK pin.
0: Low level is output
1: High level is output
1
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
0
SPB0DT
1
W
Serial Port Break Data
Controls the TXD pin by the TE bit in SCSCR.
However, TXD pin function should be selected by the
pin function controller (PFC). This is a read-only bit. The
read value is undefined.
TE bit setting SPB0DT bit
in SCSCR
setting
TXD pin state
0
0
Low output
0
1
High output (initial state)
1
*
Transmit data output in
accord with serial core
logic.
Note:
Page 782 of 1778
*
Don’t care
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.3.9
Section 16 Serial Communication Interface (SCI)
Serial Direction Control Register (SCSDCR)
The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first
transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode.
Bit:
Initial value:
R/W:
Bit
Bit Name
7 to 4 ⎯
0
7
6
5
4
3
2
1
-
-
-
-
DIR
-
-
-
1
R
1
R
1
R
1
R
0
R/W
0
R
1
R
0
R
Initial
Value
R/W
All 1
R
Description
Reserved
These bits are always read as 1. The write value should
always be 1.
3
DIR
0
R/W
Data Transfer Direction
Selects the serial/parallel conversion format. Valid for
an 8-bit transmit/receive format.
0: SCTDR contents are transmitted in LSB-first order
Receive data is stored in SCRDR in LSB-first
1: SCTDR contents are transmitted in MSB-first order
Receive data is stored in SCRDR in MSB-first
2
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
0
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 783 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.3.10
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive
bit rate.
The CPU can always read and write to SCBRR.
The SCBRR setting is calculated as follows:
Bit:
7
Initial value: 1
R/W: R/W
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Asynchronous mode:
• When the ABCS bit in serial extended mode register (SCSEMR) is 0
N=
Pφ
× 106 - 1
64 × 22n-1 × B
• When the ABCS bit in serial extended mode register (SCSEMR) is 1
N=
Pφ
× 106 - 1
32 × 22n-1 × B
Clock synchronous mode:
N=
Pφ
× 106 - 1
8 × 22n-1 × B
B:
N:
Bit rate (bits/s)
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting value should satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 16.3.)
Page 784 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.3 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: The bit rate error in asynchronous is given by the following formula:
• When the ABCS bit in serial extended mode register (SCSEMR) is 0
Error (%) =
Pφ × 106
-1
(N + 1) × B × 64 × 22n-1
× 100
• When the ABCS bit in serial extended mode register (SCSEMR) is 1
Error (%) =
Pφ × 106
-1
(N + 1) × B × 32 × 22n-1
× 100
Tables 16.4 to 16.6 show examples of SCBRR settings in asynchronous mode, and tables 16.7 to
16.9 show examples of SCBRR settings in clock synchronous mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 785 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1)
Pφ (MHz)
Bit
Rate
(bits/s) n N
10
12
Error
(%)
14
Error
n N
(%)
16
Error
n N
(%)
18
Error
20
Error
n N
(%)
n
N
0.03
3 79
Error
(%)
n
N
(%)
-0.12
3 88
-0.25
0.16
110
2 177 -0.25
2 212 0.03
2 248 -0.17
3 70
150
2 129 0.16
2 155 0.16
2 181 0.16
2 207 0.16
2 233 0.16
3 64
300
2 64
2 77
2 90
0.16
2 103 0.16
2 116 0.16
2 129 0.16
600
1 129 0.16
1 155 0.16
1 181 0.16
1 207 0.16
1 233 0.16
2 64
1200
1 64
1 77
1 90
0.16
1 103 0.16
1 116 0.16
1 129 0.16
2400
0 129 0.16
0 155 0.16
0 181 0.16
0 207 0.16
0 233 0.16
1 64
4800
0 64
0.16
0 77
0.16
0 90
0.16
0 103 0.16
0 116 0.16
0 129 0.16
9600
0 32
-1.36
0 38
0.16
0 45
-0.93
0 51
0.16
0 58
-0.69
0 64
0.16
14400
0 21
-1.36
0 25
0.16
0 29
1.27
0 34
-0.79
0 38
0.16
0 42
0.94
19200
0 15
1.73
0 19
-2.34
0 22
-0.93
0 25
0.16
0 28
1.02
0 32
-1.36
28800
0 10
-1.36
0 12
0.16
0 14
1.27
0 16
2.12
0 19
-2.34
0 21
-1.36
31250
0 9
0.00
0 11
0.00
0 13
0.00
0 15
0.00
0 17
0.00
0 19
0.00
38400
0 7
1.73
0 9
-2.34
0 10
3.57
0 12
0.16
0 14
-2.34
0 15
1.73
Page 786 of 1778
0.16
0.16
0.16
0.16
0.16
0.16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2)
Pφ (MHz)
Bit
Rate
(bits/s) n N
22
24
Error
26
Error
(%)
n N
(%)
28
Error
n N
(%)
30
Error
n N
(%)
32
Error
n
N
(%)
Error
n
N
(%)
110
3 97
-0.35
3 106 -0.44
3 114 0.36
3 123 0.23
3 132 0.13
3 141 0.03
150
3 71
-0.54
3 77
3 84
3 90
3 97
3 103 0.16
300
2 142 0.16
2 155 0.16
2 168 0.16
2 181 0.16
2 194 0.16
2 207 0.16
600
2 71
2 77
2 84
2 90
2 97
2 103 0.16
1200
1 142 0.16
1 155 0.16
1 168 0.16
1 181 0.16
1 194 0.16
1 207 0.16
2400
1 71
1 77
1 84
1 90
1 97
1 103 0.16
4800
0 142 0.16
0 155 0.16
0 168 0.16
0 181 0.16
0 194 0.16
0 207 0.16
9600
0 71
-0.54
0 77
0.16
0 84
-0.43
0 90
0.16
0 97
-0.35
0 103 0.16
14400
0 47
-0.54
0 51
0.16
0 55
0.76
0 60
-0.39
0 64
0.16
0 68
0.64
19200
0 35
-0.54
0 38
0.16
0 41
0.76
0 45
-0.93
0 48
-0.35
0 51
0.16
28800
0 23
-0.54
0 25
0.16
0 27
0.76
0 29
1.27
0 32
-1.36
0 34
-0.79
31250
0 21
0.00
0 23
0.00
0 25
0.00
0 27
0.00
0 29
0.00
0 31
0.00
38400
0 17
-0.54
0 19
-2.34
0 20
0.76
0 22
-0.93
0 23
1.73
0 25
0.16
-0.54
-0.54
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
0.16
0.16
0.16
-0.43
-0.43
-0.43
0.16
0.16
0.16
-0.35
-0.35
-0.35
Page 787 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3)
Pφ (MHz)
34
36
Bit
Rate
(bits/s) n
N
(%)
110
3
150
150
3
300
Error
38
Error
N
(%)
-0.05 3
159
110
-0.29 3
2
220
0.16
600
2
1200
Error
n
50
Error
N
(%)
n
N
(%)
-0.12 3
168
0.19
3
177
116
0.16
3
123
-0.24 3
2
233
0.16
2
246
0.16
110
-0.29 2
116
0.16
2
123
1
220
0.16
1
233
0.16
1
2400
1
110
-0.29 1
116
0.16
4800
0
220
0.16
0
233
9600
0
110
-0.29 0
116
14400
0
73
-0.29 0
19200
0
54
0.62
28800
0
31250
38400
Error
N
(%)
-0.25 3
221
-0.02
129
0.16
3
162
-0.15
64
0.16
3
80
0.47
-0.24 2
129
0.16
2
162
-0.15
246
0.16
64
0.16
2
80
0.47
1
123
-0.24 1
129
0.16
1
162
-0.15
0.16
0
246
0.16
64
0.16
1
80
0.47
0.16
0
123
-0.24 0
129
0.16
0
162
-0.15
77
0.16
0
81
0.57
0
86
-0.22 0
108
-0.45
0
58
-0.69 0
61
-0.24 0
64
0.16
0
80
0.47
36
-0.29 0
38
0.16
0
40
0.57
0
42
0.94
0
53
0.47
0
33
0.00
0
35
0.00
0
37
0.00
0
39
0.00
0
49
0
0
27
-1.18 0
28
1.02
0
30
-0.24 0
32
-1.36 0
40
-0.76
Page 788 of 1778
n
40
3
2
1
n
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1)
Pφ (MHz)
10
12
14
16
Bit Rate
(bits/s)
n
N
n
N
n
N
n
N
250
3
155
3
187
3
218
3
249
500
3
77
3
93
3
108
3
1000
2
155
2
187
2
218
2500
1
249
2
74
2
87
5000
1
124
1
149
1
10000
0
249
1
74
25000
0
99
0
50000
0
49
100000
0
250000
18
20
n
N
n
N
124
3
140
3
155
2
249
3
69
3
77
2
99
2
112
2
124
174
1
199
1
224
1
249
1
87
1
99
1
112
1
124
119
0
139
0
159
0
179
0
199
0
59
0
69
0
79
0
89
0
99
24
0
29
0
34
0
39
0
44
0
49
0
9
0
11
0
13
0
15
0
17
0
19
500000
0
4
0
5
0
6
0
7
0
8
0
9
1000000
⎯
⎯
0
2
⎯
⎯
0
3
⎯
⎯
0
4
2500000
0
0*
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0*
5000000
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 789 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2)
Pφ (MHz)
Bit Rate
(bits/s)
22
24
26
28
30
32
n
N
n
N
n
N
n
N
n
N
n
N
500
3
171
3
187
3
202
3
218
3
233
3
249
1000
3
85
3
93
3
101
3
108
3
116
3
124
2500
2
137
2
149
2
162
2
174
2
187
2
199
5000
2
68
2
74
2
80
2
87
2
93
2
99
10000
1
137
1
149
1
162
1
174
1
187
1
199
25000
0
219
0
239
1
64
1
69
1
74
1
79
50000
0
109
0
119
0
129
0
139
0
149
0
159
100000
0
54
0
59
0
64
0
69
0
74
0
79
250000
0
21
0
23
0
25
0
27
0
29
0
31
500000
0
10
0
11
0
12
0
13
0
14
0
15
1000000
⎯
⎯
0
5
⎯
⎯
0
6
⎯
⎯
0
7
2500000
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
2
⎯
⎯
5000000
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
250
Page 790 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3)
Pφ (MHz)
Bit Rate
(bits/s)
34
36
38
40
50
n
N
n
N
n
N
n
N
n
N
1000
3
132
3
140
3
147
3
155
3
194
2500
2
212
2
224
2
237
2
249
3
77
5000
2
105
2
112
2
118
2
124
2
155
10000
1
212
1
224
1
237
1
249
2
77
25000
1
84
1
89
1
94
1
99
1
124
50000
0
169
0
179
0
189
0
199
0
249
100000
0
84
0
89
0
94
0
99
0
124
250000
0
33
0
35
0
37
0
39
0
49
500000
0
16
0
17
0
18
0
19
0
24
1000000
⎯
⎯
0
8
⎯
⎯
0
9
⎯
⎯
2500000
⎯
⎯
⎯
⎯
⎯
⎯
0
3
0
4
5000000
⎯
⎯
⎯
⎯
⎯
⎯
0
1
250
500
[Legend]
Blank: No setting possible
⎯:
Setting possible, but error occurs
*:
Continuous transmission/reception is disabled.
Note: Settings with an error of 1% or less are recommended.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 791 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator
is used. Tables 16.11 and 16.12 list the maximum rates for external clock input.
Table 16.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)
Settings
Pφ (MHz)
Maximum Bit Rate (bits/s)
n
N
10
312500
0
0
12
375000
0
0
14
437500
0
0
16
500000
0
0
18
562500
0
0
20
625000
0
0
22
687500
0
0
24
750000
0
0
26
812500
0
0
28
875000
0
0
30
937500
0
0
32
1000000
0
0
34
1062500
0
0
36
1125000
0
0
38
1187500
0
0
40
1250000
0
0
50
1562500
0
0
Page 792 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
Pφ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
10
2.5000
156250
12
3.0000
187500
14
3.5000
218750
16
4.0000
250000
18
4.5000
281250
20
5.0000
312500
22
5.5000
343750
24
6.0000
375000
26
6.5000
406250
28
7.0000
437500
30
7.5000
468750
32
8.0000
500000
34
8.5000
531250
36
9.0000
562500
38
9.5000
593750
40
10.0000
625000
50
12.5000
781250
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 793 of 1778
Section 16 Serial Communication Interface (SCI)
SH7280 Group, SH7243 Group
Table 16.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode)
Pφ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
20
3.3333
3333333.3
22
3.6667
3666666.7
24
4.0000
4000000.0
26
4.3333
4333333.3
28
4.6667
4666666.7
30
5.0000
5000000.0
32
5.3333
5333333.3
34
5.6667
5666666.7
36
6.0000
6000000.0
38
6.3333
6333333.3
40
6.6667
6666666.7
50
8.3333
8333333.3
Page 794 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.4
Section 16 Serial Communication Interface (SCI)
Operation
16.4.1
Overview
For serial communication, the SCI has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses.
Asynchronous or clock synchronous mode is selected and the transmit format is specified in the
serial mode register (SCSMR) as shown in table 16.13. The SCI clock source is selected by the
combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in the serial control register
(SCSCR) as shown in table 16.14.
(1)
Asynchronous Mode
• Data length is selectable: 7 or 8 bits.
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding
selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and breaks.
• An internal or external clock can be selected as the SCI clock source.
⎯ When an internal clock is selected, the SCI operates using the clock supplied by the onchip baud rate generator and can output a clock with a frequency 16 times the bit rate.
⎯ When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
(2)
Clock Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and outputs a serial clock signal to external devices.
⎯ When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 795 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Table 16.13 SCSMR Settings and SCI Communication Formats
SCSMR Settings
SCI Communication Format
Bit 7 Bit 6 Bit 5 Bit 3
C/A CHR PE
STOP Mode
Data Length
Parity Bit
Stop Bit
Length
0
8-bit
Not set
1 bit
0
0
0
Asynchronous
1
1
2 bits
0
Set
1 bit
1
1
0
2 bits
0
7-bit
Not set
1 bit
1
1
2 bits
0
Set
1 bit
1
1
x
x
x
2 bits
Clock
synchronous
8-bit
Not set
None
[Legend]
x:
Don't care
Table 16.14 SCSMR and SCSCR Settings and SCI Clock Source Selection
SCSMR SCSCR Settings
Bit 7
C/A
Bit 1
CKE1
Bit 0
CKE0
Mode
Clock
Source
0
0
0
Asynchronous Internal
1
1
0
0
0
1
1
0
SCI does not use the SCK pin.
Clock with a frequency 16 times the bit rate
is output.
External Input a clock with frequency 16 times the
bit rate.
1
1
SCK Pin Function
Clock
synchronous
Internal
Serial clock is output.
External Input the serial clock.
1
Page 796 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.4.2
Section 16 Serial Communication Interface (SCI)
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. Both the transmitter and receiver have a double-buffered structure so that data can be
read or written during transmission or reception, enabling continuous data transfer.
Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
1
Serial
data
LSB
0
D0
Idle state
(mark state)
1
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
0/1
1
1
Parity
bit
Stop bit
1 bit or
none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 16.2 Example of Data Format in Asynchronous Communication
(8-Bit Data with Parity and Two Stop Bits)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 797 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
(1)
Transmit/Receive Formats
Table 16.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12
transfer formats can be selected according to the SCSMR settings.
Table 16.15 Serial Transfer Formats (Asynchronous Mode)
SCSMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
x
1
0
S
8-bit data
MPB STOP
0
x
1
1
S
8-bit data
MPB STOP STOP
1
x
1
0
S
7-bit data
MPB STOP
1
x
1
1
S
7-bit data
MPB STOP STOP
STOP
[Legend]
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
x:
Don't care
Page 798 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 16 Serial Communication Interface (SCI)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control
register (SCSCR) (table 16.14).
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to 16 times the desired bit rate.
(3)
Transmitting and Receiving Data
• SCI Initialization (Asynchronous Mode)
Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register
(SCSCR), then initialize the SCI as follows.
When changing the operation mode or the communication format, always clear the TE and RE bits
to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1
and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not
initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain
their previous contents.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 799 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
[1]
[2]
Start initialization
[3]
Clear RIE, TIE, TEIE, MPIE,
TE, and RE bits in SCSCR to 0*
[4]
Set CKE1 and CKE0 bits in SCSCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SCSMR and SCSDCR
[2]
Set value in SCBRR
[3]
[5]
Wait
No
1-bit interval elapsed?
Yes
Set the PFC for the external pins to be
used (SCK, TXD, RXD)
[4]
Set TE and RE bits of SCSCR to 1
Set the RIE, TIE, TEIE, and MPIE bits
in SCSCR
[5]
Set the clock selection in SCSCR.
Set the data transfer format in SCSMR
and SCSDCR.
Write a value corresponding to the bit
rate to SCBRR. Not necessary if an
external clock is used.
Set PFC of the external pin used. Set
RXD input during receiving and TXD
output during transmitting. Set SCK
input/output according to contents set by
CKE1 and CKE0. When CKE1 and
CKE0 are 0 in asynchronous mode,
setting the SCK pin is unnecessary.
Outputting clocks from the SCK pin
starts at synchronous clock output
setting.
Set the TE bit or RE bit in SCSCR to 1.*
Also make settings of the RIE, TIE,
TEIE, and MPIE bits. At this time, the
TXD, RXD, and SCK pins are ready to
be used. The TXD pin is in a mark state
during transmitting, and RXD pin is in an
idle state for waiting the start bit during
receiving.
< Initialization completed>
Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1
simultaneously.
Figure 16.3 Sample Flowchart for SCI Initialization
Page 800 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
• Transmitting Serial Data (Asynchronous Mode)
Figure 16.4 shows a sample flowchart for serial transmission. Use the following procedure for
serial data transmission after enabling the SCI for transmission.
Start of transmission
[1] SCI status check and transmit data
write:
Read TDRE flag in SCSSR
TDRE = 1?
No
[2] Serial transmission continuation
procedure:
Yes
Write transmit data in SCTDR
and clear TDRE bit in SCSSR to 0
All data transmitted?
No
Yes
Read TEND flag in SCSSR
TEND = 1?
No
Yes
Break output?
Yes
Clear SPB0DT bit to 0
Clear TE bit in SCSCR to 0
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR, and clear
the TDRE flag to 0.
No
To continue serial transmission, read
1 from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR, and then clear the TDRE
flag to 0.
When the DTC is activated by a
transmit data empty interrupt (TXI)
request to write data to SCTDR,
clearing of the TDRE flag is automatic
except when the transfer counter = 0
or DISEL = 1 as shown in the
flowchart of DTC operation in section
8, Data Transfer Controller (DTC).
When the transfer counter = 0 or
DISEL = 1, clear the TDRE flag in the
interrupt handling routine.
[3] Break output at the end of serial
transmission:
To output a break in serial
transmission, clear the SPB0DT bit to
0 and set the SPB0IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR to 0.
End of transmission
Figure 16.4 Sample Flowchart for Transmitting Serial Data
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 801 of 1778
Section 16 Serial Communication Interface (SCI)
SH7280 Group, SH7243 Group
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the
SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers
the data from SCTDR to the transmit shift register (SCTSR).
2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a
transmit-data-empty interrupt (TXI) request is generated.
The serial transmit data is sent from the TXD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
bit is output. (A format in which neither parity nor multiprocessor bit is output can also be
selected.)
D. Stop bit(s): One or two 1 bits (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the
"mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a
TEI interrupt request is generated.
Page 802 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Figure 16.5 shows an example of the operation for transmission.
Start
bit
1
Serial
data
0
Data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
TXI interrupt
request
request
Data written to SCTDR
and TDRE flag cleared to 0
by TXI interrupt handler
TEI interrupt
request
One frame
Figure 16.5 Example of Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 803 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
• Receiving Serial Data (Asynchronous Mode)
Figure 16.6 shows a sample flowchart for serial reception. Use the following procedure for serial
data reception after enabling the SCI for reception.
[1] Receive error handling and break
detection:
Start of reception
Read ORER, PER, and FER
flags in SCSSR
PER, FER, or ORER = 1?
No
Yes
Error handling
If a receive error occurs, read the ORER,
PER, and FER flags in SCSSR to identify
the error. After performing the
appropriate error processing, ensure that
the ORER, PER, and FER flags are all
cleared to 0. Reception cannot be
resumed if any of these flags are set to 1.
In the case of a framing error, a break
can also be detected by reading the
value of the RXD pin.
[2] SCI status check and receive data read:
Read RDRF flag in SCSSR
No
RDRF = 1?
Yes
Read receive data in
SCRDR, and clear RDRF
flag in SCSSR to 0
No
All data received?
Read SCSSR and check that RDRF = 1,
then read the receive data in SCRDR
clear the RDRF flag to 0.
[3] Serial reception continuation procedure:
To continue serial reception, clear the
RDRF flag to 0 before the stop bit for the
current frame is received. The RDRF flag
is cleared automatically when the data
transfer controller (DTC) is activated to
read the SCRDR value, and this step is
not needed.
Yes
Clear RE bit in SCSCR to 0
End of reception
Figure 16.6 Sample Flowchart for Receiving Serial Data (1)
Page 804 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Error processing
No
ORER = 1?
Yes
Overrun error processing
No
FER = 1?
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCSCR to 0
No
PER = 1?
Yes
Parity error processing
Clear ORER, PER, and
FER flags in SCSSR to 0
Figure 16.6 Sample Flowchart for Receiving Serial Data (2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 805 of 1778
Section 16 Serial Communication Interface (SCI)
SH7280 Group, SH7243 Group
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
A. Parity check: The SCI counts the number of 1s in the received data and checks whether the
count matches the even or odd parity specified by the O/E bit in the serial mode register
(SCSMR).
B. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the
first is checked.
C. Status check: The SCI checks whether the RDRF flag is 0 and the received data can be
transferred from the receive shift register (SCRSR) to SCRDR.
If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in
SCRDR. If a receive error is detected, the SCI operates as shown in table 16.16.
Note: When a receive error occurs, subsequent reception cannot be continued. In addition,
the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0.
4. If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1 when the RDRF
flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in
SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt
(ERI) request is generated.
Table 16.16 Receive Errors and Error Conditions
Receive Error
Abbreviation
Error Condition
Data Transfer
Overrun error
ORER
When the next data reception
is completed while the RDRF
flag in SCSSR is set to 1
The received data is not
transferred from SCRSR to
SCRDR.
Framing error
FER
When the stop bit is 0
The received data is
transferred from SCRSR to
SCRDR.
Parity error
PER
When the received data does
not match the even or odd
parity specified in SCSMR
The received data is
transferred from SCRSR to
SCRDR.
Page 806 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Figure 16.7 shows an example of the operation for reception.
1
Serial
data
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
0/1
RDRF
FER
RXI interrupt
request
One frame
Data read and RDRF flag
cleared to 0 by RXI
interrupt handler
ERI interrupt request
generated by framing
error
Figure 16.7 Example of SCI Receive Operation
(8-Bit Data, Parity, One Stop Bit)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 807 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.4.3
Clock Synchronous Mode
In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver are independent, so full-duplex communication is possible while
sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that
data can be read or written during transmission or reception, enabling continuous data transfer.
Figure 16.8 shows the general format in clock synchronous serial communication.
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
Serial data
MSB
Bit 1
Bit 2
Don't care
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High level except in continuous transfer
Figure 16.8 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first)
to the MSB (last). After output of the MSB, the communication line remains in the state of the
MSB.
Page 808 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
In clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising
edge of the serial clock.
(1)
Communication Format
The data length is fixed at eight bits. No parity bit can be added.
(2)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source,
see table 16.14.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin.
Eight clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains in the high state. However, in reception-only
operation, the synchronizing clock is output until an overrun error occurs or the RE bit is cleared
to 0. In operations for the reception of n characters, select the external clock as the clock source
for the SCI. If the internal clock is to be used instead, set both the RE and TE bits to 1, and then
transmit n characters of dummy data during reception of the n characters to be received.
(3)
Transmitting and Receiving Data
• SCI Initialization (Clock Synchronous Mode)
Before transmitting, receiving, or changing the mode or communication format, the software must
clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI.
Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR).
Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive
data register (SCRDR), which retain their previous contents.
Figure 16.9 shows a sample flowchart for initializing the SCI.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 809 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Start initialization
Clear RIE, TIE, TEIE, MPIE,
TE and RE bits in SCSCR to 0*
Set CKE1 and CKE0 bits in SCSCR
(TE and RE bits are 0)
[1]
Set data transfer format in
SCSMR
[2]
Set value in SCBRR
[3]
Wait
No
1-bit interval elapsed?
[1]
Set the clock selection in SCSCR.
[2]
Set the data transfer format in SCSMR.
[3]
Write a value corresponding to the bit rate to
SCBRR. Not necessary if an external clock is
used.
[4]
Set PFC of the external pin used. Set RXD
input during receiving and TXD output during
transmitting. Set SCK input/output according
to contents set by CKE1 and CKE0.
[5]
Set the TE bit or RE bit in SCR to 1.* Also
make settings of the RIE, TIE, TEIE, and
MPIE bits. At this time, the TXD, RXD, and
SCK pins are ready to be used. The TXD pin
is in a mark state during transmitting. When
synchronous clock output (clock master) is
set during receiving in clock synchronous
mode, outputting clocks from the SCK pin
starts.
Yes
Set the PFC for the external pins to be
used (SCK, TXD, RXD)
Set TE and RE bits of SCSCR to 1
Set the RIE, TIE, TEIE, and MPIE bits
in SCSCR
[4]
[5]
Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to
0 or set to 1 simultaneously.
Figure 16.9 Sample Flowchart for SCI Initialization
Page 810 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
• Transmitting Serial Data (Clock Synchronous Mode)
Figure 16.10 shows a sample flowchart for transmitting serial data. Use the following procedure
for serial data transmission after enabling the SCI for transmission.
Start of transmission
[1] SCI status check and transmit data
write:
Read TDRE flag in SCSSR
TDRE = 1?
No
[2] Serial transmission continuation
procedure:
Yes
Write transmit data to SCTDR
and clear TDRE flag
in SCSSR to 0
All data transmitted?
No
Yes
Read TEND flag in SCSSR
TEND = 1?
Yes
Clear TE bit in SCSCR to 0
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR, and clear
the TDRE flag to 0.
No
To continue serial transmission, read
1 from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR, and then clear the TDRE
flag to 0.
When the DTC is activated by a
transmit data empty interrupt (TXI)
request to write data to SCTDR,
clearing of the TDRE flag is automatic
except when the transfer counter = 0
or DISEL = 1 as shown in the
flowchart of DTC operation in section
8, Data Transfer Controller (DTC).
When the transfer counter = 0 or
DISEL = 1, clear the TDRE flag in the
interrupt handling routine.
End of transmission
Figure 16.10 Sample Flowchart for Transmitting Serial Data
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 811 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the
SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers
the data from SCTDR to the transmit shift register (SCTSR).
2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the transmit-data-empty interrupt enable bit (TIE) in the serial control register
(SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data is
output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is
0, the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is
started, If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the MSB (bit 7) is sent, and
then the TXD pin holds the states.
If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 16.11 shows an example of SCI transmit operation.
Transfer direction
Synchronization
clock
MSB
LSB
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt Data written to SCTDR
TXI interrupt
request
and TDRE flag cleared
request
to 0 by TXI interrupt handler
TEI interrupt
request
One frame
Figure 16.11 Example of SCI Transmit Operation
Page 812 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
• Receiving Serial Data (Clock Synchronous Mode)
Figure 16.12 shows a sample flowchart for receiving serial data. Use the following procedure for
serial data reception after enabling the SCIF for reception.
When switching from asynchronous mode to clock synchronous mode, make sure that the ORER,
PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not
be set and data reception cannot be started.
[1] Receive error handling:
Start of reception
Read ORER flag in SCSSR
ORER = 1?
No
Read RDRF flag in SCSMR
No
Error handling
[2] SCI status check and receive data read:
Read SCSSR and check that RDRF = 1,
then read the receive data in SCRDR,
and clear the RDRF flag to 0. The
transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
[3] Serial reception continuation procedure:
RDRF = 1?
Yes
Read the receive data in
SCRDR and clear RDRF flag
in SCSSR to 0
No
Yes
Read the ORER flag in SCSSR to
identify any error, perform the appropriate
error handling, then clear the ORER flag
to 0. Reception cannot be resumed while
the ORER flag is set to 1.
All data received?
To continue serial reception, read the
receive data register (SCRDR) and clear
the RDRF flag to 0 before the MSB (bit 7)
of the current frame is received. The
RDRF flag is cleared automatically when
the data transfer controller (DTC) is
activated by a receive-data-full interrupt
(RXI) request to read the SCRDR value,
and this step is not needed.
Yes
Clear RE bit in SCSCR to 0
End of reception
Figure 16.12 Sample Flowchart for Receiving Serial Data (1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 813 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCSSR to 0
End
Figure 16.12 Sample Flowchart for Receiving Serial Data (2)
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from
SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the
received data in SCRDR. If a receive error is detected, the SCI operates as shown in table
16.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will
not be set to 1 after reception; be sure to clear the RDRF flag to 0.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI).
Page 814 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Figure 16.13 shows an example of SCI receive operation.
Transfer direction
Synchronization
clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt Data read from SCRDR and
RXI interrupt
request
RDRF flag cleared to 0 by RXI request
interrupt handler
ERI interrupt request
by overrun error
One frame
Figure 16.13 Example of SCI Receive Operation
• Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode)
Figure 16.14 shows a sample flowchart for transmitting and receiving serial data simultaneously.
Use the following procedure for serial data transmission and reception after enabling the SCI for
transmission and reception.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 815 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Start of transmission and reception
[1]
SCI status check and transmit data write:
Read SCSSR and check that the TDRE flag is
set to 1, then write transmit data to SCTDR and
clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can also
be identified by a TXI interrupt.
[2]
Receive error processing:
If a receive error occurs, read the ORER flag in
SCSSR, and after performing the appropriate
error processing, clear the ORER flag to 0.
Reception cannot be resumed if the ORER flag
is set to 1.
[3]
SCI status check and receive data read:
Read SCSSR and check that the RDRF flag is
set to 1, then read the receive data in SCRDR
and clear the RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be identified by
an RXI interrupt.
[4]
Serial transmission/reception continuation
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame is
received, finish reading the RDRF flag, reading
SCRDR, and clearing the RDRF flag to 0. Also,
before the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag to
confirm that writing is possible. Then write data
to SCTDR and clear the TDRE flag to 0.
Checking and clearing of the TDRE flag is
automatic when the DTC is activated by a
transmit data empty interrupt (TXI) request and
data is written to SCTDR. Also, the RDRF flag
is cleared automatically when the DTC is
activated by a receive data full interrupt (RXI)
request and the SCRDR value is read.
[5]
Serial transmission/reception end procedure:
To finish serial transmission/reception, clear the
TE and RE bits in SCSCR to 0 simultaneously.
Read TDRE flag in SCSSR
No
TDRE = 1?
Yes
Write transmit data to SCTDR and
clear TDRE flag in SCSSR to 0
Read ORER flag in SCSSR
Yes
ORER = 1?
No
Error processing
Read RDRF flag in SCSSR
No
RDRF = 1?
Yes
Write transmit data to SCTDR, and
clear TDRE flag in SCSSR to 0
No
All data received?
Yes
Clear TE and RE bits in SCSCR to 0
End of transmission and reception
Note:
When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the
TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 16.14 Sample Flowchart for Transmitting/Receiving Serial Data
Page 816 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.4.4
Section 16 Serial Communication Interface (SCI)
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component cycles:
an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The
multiprocessor bit is used to differentiate between the ID transmission cycle and the data
transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the
multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 16.15 shows an example of
inter-processor communication using the multiprocessor format. The transmitting station first
sends the ID code of the receiving station with which it wants to perform serial communication as
data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor
bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data
with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID.
The station whose ID matches then receives the data sent next. Stations whose ID does not match
continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCSCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from SCRSR to SCRDR, error flag detection, and setting the SCSSR status
flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received.
On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SCSSR is set to 1
and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in
SCSCR is set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 817 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
ID transmission cycle =
receiving station
specification
(MPB = 0)
Data transmission cycle =
Data transmission to
receiving station specified
by ID
[Legend]
MPB: Multiprocessor bit
Figure 16.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Page 818 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.4.5
Section 16 Serial Communication Interface (SCI)
Multiprocessor Serial Data Transmission
Figure 16.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. Keep MPBT at 1 until
the ID is actually transmitted. For a data transmission cycle, clear the MPBT bit in SCSSR to 0
before transmission. All other SCI operations are the same as those in asynchronous mode.
[1]
Initialization
[1]
SCI initialization:
Set the TXD pin using the PFC.
After the TE bit is set to 1, 1 is output
for one frame, and transmission is
enabled. However, data is not
transmitted.
[2]
SCI status check and transmit data
write:
Read SCSSR and check that the
TDRE flag is set to 1, then write data
for transmission to SCTDR. Set the
MPBT bit in SCSSR to 0 or 1. Finally,
clear the TDRE flag to 0.
After initializing the SCI, when an ID
is written to SCTDR register so as to
transmit the ID, data is immediately
transferred, and then the TDRE flag is
set to 1. The MPBT bit must be held 1
because the ID is not transmitted from
the TXD pin at this time. When the
TDRE flag is set to 1 after data
following the ID is written to SCTDR,
clear the MPBT bit to 0.
[3]
Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to SCTDR, and then clear
the TDRE flag to 0. Checking and
clearing of the TDRE flag is automatic
when the DTC is activated by a
transmit data empty interrupt (TXI)
request, and data is written to
SCTDR.
[4]
Break output at the end of serial
transmission:
To output a break in serial
transmission, first clear the port data
register (DR) to 0, then clear the TE
bit to 0 in SCSCR and use the PFC to
select the TXD pin as an output port.
Start transmission
Read TDRE flag in SCSSR
[2]
No
TDRE = 1?
Yes
Write transmit data to SCTDR and
set MPBT bit in SCSSR
Clear TDRE flag to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SCSSR
No
TEND = 1?
Yes
No
Break output?
[4]
Yes
Clear DR to 0
Clear TE bit in SCSCR to 0;
select the TXD pin
as an output port with the PFC
Figure 16.16 Sample Multiprocessor Serial Transmission Flowchart
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 819 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.4.6
Multiprocessor Serial Data Reception
Figure 16.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
16.17 shows an example of SCI operation for multiprocessor format reception.
1
RXD
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
D0
D1
Stop
MPB bit
D7
0
1
1 Idle state
(mark state)
MPIE
RDRF
SCRDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
SCRDR data read If not this station’s ID,
and RDRF flag
MPIE bit is set to 1
cleared to 0 in
again
RXI interrupt
processing routine
RXI interrupt request is
not generated,
and SCRDR retains
its state
(a) Data does not match station’s ID
1
RXD
Start
bit
0
Data (ID2)
D0
D1
Stop
MPB bit
D7
1
1
Start
bit
0
Data (Data2)
D0
D1
D7
Stop
MPB bit
0
1
1 Idle state
(mark state)
MPIE
RDRF
SCRDR
value
ID1
MPIE = 0
Data2
ID2
RXI interrupt
request
(multiprocessor
interrupt)
generated
SCRDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
Matches this station’s ID,
MPIE bit is set to 1
so reception continues,
again
and data is received in RXI
interrupt processing routine
(b) Data matches station’s ID
Figure 16.17 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Page 820 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Initialization
[1]
Start reception
Set MPIE bit in SCSCR to 1
[2]
[1]
SCI initialization:
Set the RXD pin using the PFC.
[2]
ID reception cycle:
Set the MPIE bit in SCSCR to 1.
[3]
SCI status check, ID reception and
comparison:
Read SCSSR and check that the RDRF flag is
set to 1, then read the receive data in SCRDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again, and clear the RDRF flag to 0.
If the data is this station’s ID, clear the RDRF
flag to 0.
[4]
SCI status check and data reception:
Read SCSSR and check that the RDRF flag is
set to 1, then read the data in SCRDR.
[5]
Receive error processing and break detection:
If a receive error occurs, read the ORER and
FER flags in SCSSR to identify the error.
After performing the appropriate error
processing, ensure that the ORER and FER
flags are all cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RXD pin value.
Read ORER and FER flags
in SCSSR
Yes
FER = 1? or ORER = 1?
No
Read RDRF flag in SCSSR
[3]
No
RDRF = 1?
Yes
Read receive data in SCRDR
No
This station’s ID?
Yes
Read ORER and FER flags
in SCSSR
Yes
FER = 1? or ORER = 1?
No
Read RDRF flag in SCSSR
[4]
No
RDRF = 1?
Yes
Read receive data in SCRDR
No
All data received?
[5]
Error processing
Yes
Clear RE bit in SCSCR to 0
(Continued on
next page)
Figure 16.18 Sample Multiprocessor Serial Reception Flowchart (1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 821 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
[5]
Error processing
No
ORER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
Clear RE bit in SCSCR to 0
Clear ORER and FER
flags in SCSSR to 0
Figure 16.18 Sample Multiprocessor Serial Reception Flowchart (2)
Page 822 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.5
Section 16 Serial Communication Interface (SCI)
SCI Interrupt Sources and DTC
The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full
(RXI), and transmit-data-empty (TXI) interrupt requests.
Table 16.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of
the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is
sent to the interrupt controller for each of these interrupt sources.
When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt
request is generated. This request can be used to activate the data transfer controller (DTC) to
transfer data. The TDRE flag is automatically cleared to 0 when data is written to the transmit data
register (SCTDR) through the DTC.
When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. This request
can be used to activate the DTC to transfer data. The RDRF flag is automatically cleared to 0
when data is read from the receive data register (SCRDR) through the DTC.
When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated.
This request cannot be used to activate the DTC. In processing for data reception, generation of
ERI interrupt requests can only be enabled if generation of RXI interrupt requests is disabled. In
this case, set the RIE bit and the EIO bit in SCSPTR to 1. However, note that the DMAC or DTC
will not transfer received data since RXI interrupt requests are not generated while the EIO bit is
set to 1.
When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. This request
cannot be used to activate the DTC.
The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that
transmission has been completed.
Table 16.17 SCI Interrupt Sources
Interrupt Source
Description
DTC Activation
ERI
Interrupt caused by receive error (ORER, FER, or
PER)
Not possible
RXI
Interrupt caused by receive data full (RDRF)
Possible
TXI
Interrupt caused by transmit data empty (TDRE)
Possible
TEI
Interrupt caused by transmit end (TENT)
Not possible
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 823 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.6
Serial Port Register (SCSPTR) and SCI Pins
The relationship between SCSPTR and the SCI pins is shown in figures 16.19 and 16.20.
Reset
R
Q
D
SCKIO
C
Bit 3
SPTRW
Internal data bus
Reset
SCK
R
Bit 2
Q
D
SCKDT
C
SPTRW
Clock output enable signal*
Serial clock output signal*
Serial clock input signal*
Serial input enable signal*
[Legend]
SPTRW:
Note:
SCSPTR write
* These signals control the SCK pin according to the settings of the C/A bit in SCSMR
and bits CKE1 and CKE0 in SCSCR.
Figure 16.19 SCKIO Bit, SCKDT Bit, and SCK Pin
Page 824 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
Internal data bus
Reset
TXD
R
Bit 0
Q
D
SPBDT
C
SPTRW
Transmit enable signal
Serial transmit data
[Legend]
SPTRW:
SCSPTR write
Figure 16.20 SPBDT Bit and TXD Pin
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 825 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16.7
Usage Notes
16.7.1
SCTDR Writing and TDRE Flag
The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of
transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data
from SCTDR to SCTSR.
Data can be written to SCTDR regardless of the TDRE bit status.
If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be
lost because the data has not yet been transferred to SCTSR. Before writing transmit data to
SCTDR, be sure to check that the TDRE flag is set to 1.
16.7.2
Multiple Receive Error Occurrence
If multiple receive errors occur at the same time, the status flags in SCSSR are set as shown in
table 16.18. When an overrun error occurs, data is not transferred from the receive shift register
(SCRSR) to the receive data register (SCRDR) and the received data will be lost.
Table 16.18 SCSSR Status Flag Values and Transfer of Received Data
Receive Errors Generated
RDRF
ORER
FER
PER
Receive Data
Transfer from
SCRSR to
SCRDR
Overrun error
1
1
0
0
Not transferred
Framing error
0
0
1
0
Transferred
Parity error
0
0
0
1
Transferred
Overrun error + framing error
1
1
1
0
Not transferred
Overrun error + parity error
1
1
0
1
Not transferred
Framing error + parity error
0
0
1
1
Transferred
Overrun error + framing error + parity error
1
1
1
1
Not transferred
SCSSR Status Flags
Page 826 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.7.3
Section 16 Serial Communication Interface (SCI)
Break Detection and Processing
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set. Note that, although transfer of receive data to
SCRDR is halted in the break state, the SCI receiver continues to operate.
16.7.4
Sending a Break Signal
The I/O condition and level of the TXD pin are determined by SPB0DT bit in the serial port
register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During
the period, mark status is performed by SPB0DT bit. Therefore, the SPB0DT bit should be set to 1
(high level output).
To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear
the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized
regardless of the current transmission state, and 0 is output from the TXD pin.
16.7.5
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous
mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples
on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The
timing is shown in figure 16.21.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 827 of 1778
SH7280 Group, SH7243 Group
Section 16 Serial Communication Interface (SCI)
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
Base clock
–7.5 clocks
Receive data
(RXD)
+7.5 clocks
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 16.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5 -
D - 0.5
1
) - (L - 0.5) F (1+F) × 100 %
2N
N
Where: M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M
= (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Page 828 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
16.7.6
Section 16 Serial Communication Interface (SCI)
Note on Using DTC
When the external clock source is used for the clock for synchronization, input the external clock
after waiting for five or more cycles of the peripheral operating clock after SCTDR is modified
through the DTC. If a transmit clock is input within four cycles after SCTDR is modified, a
malfunction may occur (figure 16.22).
SCK
t
TDRE
TXD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When using the external clock, t must be set to larger than 4 cycles.
Figure 16.22 Example of Clock Synchronous Transfer Using DTC
When data is written to SCTDR by activating the DTC by a TXI interrupt, the TEND flag value
becomes undefined. In this case, do not use the TEND flag as the transmit end flag.
16.7.7
Note on Using External Clock in Clock Synchronous Mode
TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock
after the SCK external clock is changed from 0 to 1.
TE and RE must be set to 1 only while the SCK external clock is 1.
16.7.8
Module Standby Mode Setting
SCI operation can be disabled or enabled using the standby control register. The initial setting is
for SCI operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 28, Power-Down Modes.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 829 of 1778
Section 16 Serial Communication Interface (SCI)
Page 830 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Section 17 Serial Communication Interface with FIFO
(SCIF)
This LSI has one channel of serial communication interface with FIFO (SCIF) that supports both
asynchronous and clocked synchronous serial communication. It also has 16-stage FIFO registers
for both transmission and reception independently for each channel that enable this LSI to perform
efficient high-speed continuous communication.
17.1
Features
• Asynchronous serial communication:
⎯ Serial data communication is performed by start-stop in character units. The SCIF can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
⎯ Data length: 7 or 8 bits
⎯ Stop bit length: 1 or 2 bits
⎯ Parity: Even, odd, or none
⎯ Receive error detection: Parity, framing, and overrun errors
⎯ Break detection: Break is detected when a framing error is followed by at least one frame at
the space 0 level (low level). It is also detected by reading the RXD level directly from the
serial port register when a framing error occurs.
• Clocked synchronous serial communication:
⎯ Serial data communication is synchronized with a clock signal. The SCIF can communicate
with other chips having a clocked synchronous communication function. There is one serial
data communication format.
⎯ Data length: 8 bits
⎯ Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 831 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFOdata-full interrupt, and receive-error interrupts are requested independently.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• The quantity of data in the transmit and receive FIFO data registers and the number of receive
errors of the receive data in the receive FIFO data register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 17.1 shows a block diagram of the SCIF.
SCFRDR (16 stage)
SCFTDR (16 stage)
SCSMR
SCBRR
SCLSR
Bus interface
Module data bus
Peripheral
bus
SCFDR
SCFCR
RXD3
SCRSR
SCTSR
Baud rate
generator
SCFSR
SCSCR
Pφ/16
SCSPTR
Pφ/64
SCSEMR
Transmission/reception
control
TXD3
Pφ
Pφ/4
Clock
Parity generation
Parity check
External clock
SCK3
TXI
RXI
ERI
BRI
SCIF
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
SCFSR:
SCBRR:
SCSPTR:
SCFCR:
SCFDR:
SCLSR:
SCSEMR:
Serial status register
Bit rate register
Serial port register
FIFO control register
FIFO data count register
Line status register
Serial extended mode register
Figure 17.1 Block Diagram of SCIF
Page 832 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
17.2
Section 17 Serial Communication Interface with FIFO (SCIF)
Input/Output Pins
Table 17.1 shows the pin configuration of the SCIF.
Table 17.1 Pin Configuration
Channel
Pin Name
Symbol
I/O
Function
3
Serial clock pins
SCK3
I/O
Clock I/O
Receive data pins
RXD3
Input
Receive data input
Transmit data pins
TXD3
Output
Transmit data output
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 833 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3
Register Descriptions
The SCIF has the following registers.
Table 17.2 Register Configuration
Channel
Register Name
Abbreviation
R/W
Initial Value Address
Access
Size
3
Serial mode register_3
SCSMR_3
R/W
H'0000
H'FFFE9800
16
Bit rate register_3
SCBRR_3
R/W
H'FF
H'FFFE9804
8
Serial control register_3
SCSCR_3
R/W
H'0000
H'FFFE9808
16
Transmit FIFO data register_3
SCFTDR_3
W
Undefined
H'FFFE980C
8
Serial status register_3
SCFSR_3
R/(W)*
H'0060
H'FFFE9810
16
Receive FIFO data register_3
SCFRDR_3
R
Undefined
H'FFFE9814
8
FIFO control register_3
SCFCR_3
R/W
H'0000
H'FFFE9818
16
FIFO data count register_3
SCFDR_3
R
H'0000
H'FFFE981C
16
Serial port register_3
SCSPTR_3
R/W
H'00xx
H'FFFE9820
16
1
2
Line status register_3
SCLSR_3
R/(W)*
H'0000
H'FFFE9824
16
Serial extended mode
register_3
SCSEMR_3
R/W
H'00
H'FFFE9900
8
Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that
cannot be modified.
2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be
modified.
17.3.1
Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
Page 834 of 1778
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
-
-
-
-
-
-
-
-
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
17.3.2
Section 17 Serial Communication Interface with FIFO (SCIF)
Receive FIFO Data Register (SCFRDR)
SCFRDR is a register that stores serial receive data. The SCIF completes the reception of one byte
of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR
for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not
write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is
undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is initialized to an undefined value by a power-on reset.
17.3.3
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register
(SCFTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After
transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into
SCTSR and starts transmitting again.
The CPU cannot read or write to SCTSR directly.
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
-
-
-
-
-
-
-
-
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 835 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.4
Transmit FIFO Data Register (SCFTDR)
SCFTDR is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects
that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR
into SCTSR and starts serial transmission. Continuous serial transmission is performed until there
is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times.
When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new
data is attempted, the data is ignored.
SCFTDR is initialized to an undefined value by a power-on reset.
Page 836 of 1778
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
W
W
W
W
W
W
W
W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
17.3.5
Section 17 Serial Communication Interface with FIFO (SCIF)
Serial Mode Register (SCSMR)
SCSMR specifies the SCIF serial communication format and selects the clock source for the baud
rate generator.
The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on
reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
-
-
-
-
-
C/A
CHR
PE
O/E
STOP
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
1
0
CKS[1:0]
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
7
C/A
0
R/W
Communication Mode
Selects whether the SCIF operates in asynchronous or
clocked synchronous mode.
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length
Selects 7-bit or 8-bit data length in asynchronous mode.
In clocked synchronous mode, the data length is always
8 bits, regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: *
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
When 7-bit data is selected, the MSB (bit 7) of
the transmit FIFO data register is not
transmitted.
Page 837 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
5
PE
0
R/W
Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In clocked synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit is
added to transmit data, depending on the parity
mode (O/E) setting. Receive data parity is
checked according to the even/odd (O/E) mode
setting.
4
O/E
0
R/W
Parity mode
Selects even or odd parity when parity bits are added
and checked. The O/E setting is used only in
asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking.
The O/E setting is ignored in clocked synchronous
mode, or in asynchronous mode when parity addition
and checking is disabled.
0: Even parity*
1
1: Odd parity*2
Notes: 1. If even parity is selected, the parity bit is
added to transmit data to make an even
number of 1s in the transmitted character and
parity bit combined. Receive data is checked
to see if it has an even number of 1s in the
received character and parity bit combined.
2. If odd parity is selected, the parity bit is added
to transmit data to make an odd number of 1s
in the transmitted character and parity bit
combined. Receive data is checked to see if it
has an odd number of 1s in the received
character and parity bit combined.
Page 838 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
3
STOP
0
R/W
Stop Bit Length
Selects one or two bits as the stop bit length in
asynchronous mode. This setting is used only in
asynchronous mode. It is ignored in clocked
synchronous mode because no stop bits are added.
When receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
0: One stop bit
When transmitting, a single 1-bit is added at the end
of each transmitted character.
1: Two stop bits
When transmitting, two 1 bits are added at the end of
each transmitted character.
2
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
CKS[1:0]
00
R/W
Clock Select
Select the internal clock source of the on-chip baud rate
generator. For further information on the clock source,
bit rate register settings, and baud rate, see section
17.3.8, Bit Rate Register (SCBRR).
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ: Peripheral clock
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 839 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.6
Serial Control Register (SCSCR)
SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is
initialized to H'0000 by a power-on reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
-
-
-
-
-
-
-
-
TIE
RIE
TE
RE
REIE
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
1
0
CKE[1:0]
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
7
TIE
0
R/W
Transmit Interrupt Enable
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit data
is transferred from the transmit FIFO data register
(SCFTDR) to the transmit shift register (SCTSR), when
the quantity of data in the transmit FIFO register
becomes less than the specified number of
transmission triggers, and when the TDFE flag in the
serial status register (SCFSR) is set to 1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
disabled
1: Transmit-FIFO-data-empty interrupt request (TXI) is
enabled*
Note: * The TXI interrupt request can be cleared by
writing a greater quantity of transmit data than
the specified transmission trigger number to
SCFTDR and by clearing TDFE to 0 after
reading 1 from TDFE, or can be cleared by
clearing TIE to 0.
Page 840 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
6
RIE
0
R/W
Receive Interrupt Enable
Enables or disables the receive FIFO data full (RXI)
interrupts requested when the RDF flag or DR flag in
serial status register (SCFSR) is set to 1, receive-error
(ERI) interrupts requested when the ER flag in SCFSR
is set to 1, and break (BRI) interrupts requested when
the BRK flag in SCFSR or the ORER flag in line status
register (SCLSR) is set to 1.
0: Receive FIFO data full interrupt (RXI), receive-error
interrupt (ERI), and break interrupt (BRI) requests
are disabled
1: Receive FIFO data full interrupt (RXI), receive-error
interrupt (ERI), and break interrupt (BRI) requests
are enabled*
Note: * RXI interrupt requests can be cleared by
reading the DR or RDF flag after it has been
set to 1, then clearing the flag to 0, or by
clearing RIE to 0. ERI or BRI interrupt requests
can be cleared by reading the ER, BR or
ORER flag after it has been set to 1, then
clearing the flag to 0, or by clearing RIE and
REIE to 0.
5
TE
0
R/W
Transmit Enable
Enables or disables the serial transmitter.
0: Transmitter disabled
1: Transmitter enabled*
Note: * Serial transmission starts after writing of
transmit data into SCFTDR. Select the transmit
format in SCSMR and SCFCR and reset the
transmit FIFO before setting TE to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 841 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
4
RE
0
R/W
Receive Enable
Enables or disables the serial receiver of the SCIF.
0: Receiver disabled*
1
2
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
2. Serial reception starts when a start bit is
detected in asynchronous mode, or
synchronous clock input is detected in
clocked synchronous mode. Select the
receive format in SCSMR and SCFCR and
reset the receive FIFO before setting RE to 1.
3
REIE
0
R/W
Receive Error Interrupt Enable
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
(BRI) requests are disabled
1: Receive-error interrupt (ERI) and break interrupt
(BRI) requests are enabled*
Note: * ERI or BRI interrupt requests can be cleared by
reading the ER, BR or ORER flag after it has
been set to 1, then clearing the flag to 0, or by
clearing RIE and REIE to 0. Even if RIE is set
to 0, when REIE is set to 1, ERI or BRI
interrupt requests are enabled. Set so If SCIF
wants to inform INTC of ERI or BRI interrupt
requests during DMA transfer.
Page 842 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
2
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
CKE[1:0]
00
R/W
Clock Enable
Select the SCIF clock source and enable or disable
clock output from the SCK pin. Depending on CKE[1:0],
the SCK pin can be used for serial clock output or serial
clock input. If serial clock output is set in clocked
synchronous mode, set the C/A bit in SCSMR to 1, and
then set CKE[1:0].
•
Asynchronous mode
00: Internal clock, SCK pin used for input pin (input
signal is ignored)
01: Internal clock, SCK pin used for clock output
(The output clock frequency is 16 times the bit rate.)
10: External clock, SCK pin used for clock input
(The input clock frequency is 16 times the bit rate.)
11: Setting prohibited
•
Clocked synchronous mode
00: Internal clock, SCK pin used for serial clock output
01: Internal clock, SCK pin used for serial clock output
10: External clock, SCK pin used for serial clock input
11: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 843 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.7
Serial Status Register (SCFSR)
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive
FIFO data register, and the lower 8 bits indicate the status flag indicating SCIF operating state.
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written.
When receive data in the receive FIFO data register is transferred by using the DTC, the receive
data is cleared in the receive FIFO data register. At the same time, the PER and FER bits in
SCFSR are cleared. If DTC is used, an error is not judged by the FER or PER bit.
Bit:
15
14
13
12
11
10
PER[3:0]
Initial value:
R/W:
0
R
0
R
0
R
9
8
FER[3:0]
0
R
0
R
0
R
0
R
0
R
7
6
5
4
3
2
1
0
ER
TEND
TDFE
BRK
FER
PER
RDF
DR
0
R
0
R
0
1
1
0
R/(W)* R/(W)* R/(W)* R/(W)*
0
0
R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit
Bit Name
Initial
Value
R/W
Description
15 to 12
PER[3:0]
0000
R
Number of Parity Errors
Indicate the quantity of data including a parity error in
the receive data stored in the receive FIFO data
register (SCFRDR). The value indicated by bits 15 to
12 after the ER bit in SCFSR is set, represents the
number of parity errors in SCFRDR. When parity
errors have occurred in all 16-byte receive data in
SCFRDR, PER[3:0] shows 0000.
11 to 8
FER[3:0]
0000
R
Number of Framing Errors
Indicate the quantity of data including a framing error
in the receive data stored in SCFRDR. The value
indicated by bits 11 to 8 after the ER bit in SCFSR is
set, represents the number of framing errors in
SCFRDR. When framing errors have occurred in all
16-byte receive data in SCFRDR, FER[3:0] shows
0000.
Page 844 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
7
ER
0
R/(W)* Receive Error
Description
Indicates the occurrence of a framing error, or of a
1
parity error when receiving data that includes parity.*
0: Receiving is in progress or has ended normally
[Clearing conditions]
•
ER is cleared to 0 a power-on reset
•
ER is cleared to 0 when the chip is when 0 is
written after 1 is read from ER
1: A framing error or parity error has occurred.
[Setting conditions]
•
ER is set to 1 when the stop bit is 0 after checking
whether or not the last stop bit of the received
data is 1 at the end of one data receive
2
operation*
•
ER is set to 1 when the total number of 1s in the
receive data plus parity bit does not match the
even/odd parity specified by the O/E bit in SCSMR
Notes: 1. Clearing the RE bit to 0 in SCSCR does
not affect the ER bit, which retains its
previous value. Even if a receive error
occurs, the receive data is transferred to
SCFRDR and the receive operation is
continued. Whether or not the data read
from SCFRDR includes a receive error
can be detected by the FER and PER bits
in SCFSR.
2. In two stop bits mode, only the first stop
bit is checked; the second stop bit is not
checked.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 845 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
6
TEND
1
R/(W)* Transmit End
Description
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
•
TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR*
1: End of transmission
[Setting conditions]
•
TEND is set to 1 when the chip is a power-on
reset
•
TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
•
TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
Note: * Do not use this bit as a transmit end flag
when the DMAC writes data to SCFTDR
due to a TXI interrupt request.
Page 846 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
5
TDFE
1
R/W
Description
R/(W)* Transmit FIFO Data Empty
Indicates that data has been transferred from the
transmit FIFO data register (SCFTDR) to the transmit
shift register (SCTSR), the quantity of data in
SCFTDR has become less than the transmission
trigger number specified by the TTRG1 and TTRG0
bits in the FIFO control register (SCFCR), and writing
of transmit data to SCFTDR is enabled.
0: The quantity of transmit data written to SCFTDR is
greater than the specified transmission trigger
number
[Clearing conditions]
•
TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR after 1 is read from TDFE and then 0 is
written
•
TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR by the DMAC.
•
TDFE is cleared to 0 when data exceeding the
specified transmission trigger number is written to
SCFTDR by the DTC. (Except the transfer counter
value of DTC has become H'0000)
1: The quantity of transmit data in SCFTDR is less
than the specified transmission trigger number*
[Setting conditions]
•
TDFE is set to 1 by a power-on reset
•
TDFE is set to 1 when the quantity of transmit
data in SCFTDR becomes less than the specified
transmission trigger number as a result of
transmission.
Note: * Since SCFTDR is a 16-byte FIFO register,
the maximum quantity of data that can be
written when TDFE is 1 is "16 minus the
specified transmission trigger number". If an
attempt is made to write additional data, the
data is ignored. The quantity of data in
SCFTDR is indicated by the upper 8 bits of
SCFDR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 847 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
4
BRK
0
R/(W)* Break Detection
Description
Indicates that a break signal has been detected in
receive data.
0: No break signal received
[Clearing conditions]
•
BRK is cleared to 0 when the chip is a power-on
reset
•
BRK is cleared to 0 when software reads BRK
after it has been set to 1, then writes 0 to BRK
1: Break signal received*
[Setting condition]
•
BRK is set to 1 when data including a framing
error is received, and a framing error occurs with
space 0 in the subsequent receive data
Note: * When a break is detected, transfer of the
receive data (H'00) to SCFRDR stops after
detection. When the break ends and the
receive signal becomes mark 1, the transfer
of receive data resumes.
3
FER
0
R
Framing Error Indication
Indicates a framing error in the data read from the
next receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive framing error occurred in the next data
read from SCFRDR
[Clearing conditions]
•
FER is cleared to 0 when the chip undergoes a
power-on reset
•
FER is cleared to 0 when no framing error is
present in the next data read from SCFRDR
1: A receive framing error occurred in the next data
read from SCFRDR.
[Setting condition]
•
Page 848 of 1778
FER is set to 1 when a framing error is present in
the next data read from SCFRDR
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
2
PER
0
R
Parity Error Indication
Indicates a parity error in the data read from the next
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive parity error occurred in the next data
read from SCFRDR
[Clearing conditions]
•
PER is cleared to 0 when the chip undergoes a
power-on reset
•
PER is cleared to 0 when no parity error is present
in the next data read from SCFRDR
1: A receive parity error occurred in the next data read
from SCFRDR
[Setting condition]
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
PER is set to 1 when a parity error is present in
the next data read from SCFRDR
Page 849 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
1
RDF
0
R/(W)* Receive FIFO Data Full
Description
Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the
quantity of data in SCFRDR has become more than
the receive trigger number specified by the RTRG[1:0]
bits in the FIFO control register (SCFCR).
0: The quantity of transmit data written to SCFRDR is
less than the specified receive trigger number
[Clearing conditions]
•
•
•
•
RDF is cleared to 0 by a power-on reset, standby
mode
RDF is cleared to 0 when the SCFRDR is read
until the quantity of receive data in SCFRDR
becomes less than the specified receive trigger
number after 1 is read from RDF and then 0 is
written
RDF is cleared to 0 when SCFRDR is read by the
DMAC until the quantity of receive data in
SCFRDR becomes less than the specified receive
trigger number.
RDF is cleared to 0 when SCFRDR is read by the
DTC until the quantity of receive data in SCFRDR
becomes less than the specified receive trigger
number. (Except the transfer counter value of DTC
has become H'0000)
1: The quantity of receive data in SCFRDR is more
than the specified receive trigger number
[Setting condition]
•
RDF is set to 1 when a quantity of receive data
more than the specified receive trigger number is
stored in SCFRDR*
Note: * As SCFTDR is a 16-byte FIFO register, the
maximum quantity of data that can be read
when RDF is 1 becomes the specified
receive trigger number. If an attempt is made
to read after all the data in SCFRDR has
been read, the data is undefined. The
quantity of receive data in SCFRDR is
indicated by the lower 8 bits of SCFDR.
Page 850 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
0
DR
0
R/(W)* Receive Data Ready
Description
Indicates that the quantity of data in the receive FIFO
data register (SCFRDR) is less than the specified
receive trigger number, and that the next data has not
yet been received after the elapse of 15 ETU from the
last stop bit in asynchronous mode. In clocked
synchronous mode, this bit is not set to 1.
0: Receiving is in progress, or no receive data
remains in SCFRDR after receiving ended normally
[Clearing conditions]
•
DR is cleared to 0 when the chip undergoes a
power-on reset
•
DR is cleared to 0 when all receive data are read
after 1 is read from DR and then 0 is written.
•
DR is cleared to 0 when all receive data in
SCFRDR are read by the DMAC or DTC.
1: Next receive data has not been received
[Setting condition]
•
DR is set to 1 when SCFRDR contains less data
than the specified receive trigger number, and the
next data has not yet been received after the
elapse of 15 ETU from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the 8-bit,
1-stop-bit format. (ETU: elementary time unit)
Note:
*
Only 0 can be written to clear the flag after 1 is read.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 851 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.8
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS[1:0] bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
The SCBRR setting is calculated as follows:
Asynchronous mode:
• When the ABCS bit in serial extended mode register (SCSEMR) is 0
N=
Pφ
× 106 − 1
64 × 22n-1 × B
• When the ABCS bit in serial extended mode register (SCSEMR) is 1
N=
Pφ
× 106 − 1
32 × 22n-1 × B
Clocked synchronous mode:
N=
Pφ
× 106 − 1
8 × 22n-1 × B
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 17.3.)
Page 852 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.3 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
The bit rate error in asynchronous mode is given by the following formula:
• When the ABCS bit in serial extended mode register (SCSEMR) is 0
Error (%) =
Pφ × 106
-1
(N + 1) × B × 64 × 22n-1
× 100
• When the ABCS bit in serial extended mode register (SCSEMR) is 1
Error (%) =
Pφ × 106
-1
(N + 1) × B × 32 × 22n-1
× 100
Table 17.4 lists examples of SCBRR settings in asynchronous mode, and table 17.5 lists examples
of SCBRR settings in clocked synchronous mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 853 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.4 Bit Rates and SCBRR Settings (Asynchronous Mode)
Pφ (MHz)
12
10
Bit Rate
(bit/s)
n
N
Error (%)
n
N
Error (%)
110
2
177
–0.25
2
212
0.03
150
2
129
0.16
2
155
0.16
300
2
64
0.16
2
77
0.16
600
1
129
0.16
1
155
0.16
1200
1
64
0.16
1
77
0.16
2400
0
129
0.16
0
155
0.16
4800
0
64
0.16
0
77
0.16
9600
0
32
–1.36
0
38
0.16
19200
0
15
1.73
0
19
0.16
31250
0
9
0.00
0
11
0.00
38400
0
7
1.73
0
9
–2.34
Pφ (MHz)
12.288
14.7456
16
19.6608
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
217
0.08
3
64
0.70
3
70
0.03
3
86
0.31
150
2
159
0.00
2
191
0.00
2
207
0.16
2
255
0.00
300
2
79
0.00
2
95
0.00
2
103
0.16
2
127
0.00
600
1
159
0.00
1
191
0.00
1
207
0.16
1
255
0.00
1200
1
79
0.00
1
95
0.00
1
103
0.16
1
127
0.00
2400
0
159
0.00
0
191
0.00
0
207
0.16
0
255
0.00
4800
0
79
0.00
0
95
0.00
0
103
0.16
0
127
0.00
9600
0
39
0.00
0
47
0.00
0
51
0.16
0
63
0.00
19200
0
19
0.00
0
23
0.00
0
25
0.16
0
31
0.00
31250
0
11
2.40
0
14
–1.70
0
15
0.00
0
19
–1.70
38400
0
9
0.00
0
11
0.00
0
12
0.16
0
15
0.00
Page 854 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Pφ (MHz)
20
24
24.576
28.7
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
88
–0.25
3
106
–0.44
3
108
0.08
3
126
0.31
150
3
64
0.16
3
77
0.16
3
79
0.00
3
92
0.46
300
2
129
0.16
2
155
0.16
2
159
0.00
2
186
–0.08
600
2
64
0.16
2
77
0.16
2
79
0.00
2
92
0.46
1200
1
129
0.16
1
155
0.16
1
159
0.00
1
186
–0.08
2400
1
64
0.16
1
77
0.16
1
79
0.00
1
92
0.46
4800
0
129
0.16
0
155
0.16
0
159
0.00
0
186
–0.08
9600
0
64
0.16
0
77
0.16
0
79
0.00
0
92
0.46
19200
0
32
–1.36
0
38
0.16
0
39
0.00
0
46
–0.61
31250
0
19
0.00
0
23
0.00
0
24
–1.70
0
28
–1.03
38400
0
15
1.73
0
19
–2.34
0
19
0.00
0
22
1.55
Pφ (MHz)
30
33
40
50
Bit Rate (bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
132
0.13
3
145
0.33
3
117
–0.25
3
221
–0.02
150
3
97
–0.35
3
106
0.39
3
129
0.16
3
162
–0.15
300
2
194
0.16
2
214
–0.07
3
64
0.16
3
80
0.47
600
2
97
–0.35
2
106
0.39
2
129
0.16
2
162
–0.15
1200
1
194
0.16
1
214
–0.07
2
64
0.16
2
80
0.47
2400
1
97
–0.35
1
106
0.39
1
129
0.16
1
162
–0.15
4800
0
194
–1.36
0
214
–0.07
1
64
0.16
1
80
0.47
9600
0
97
–0.35
0
106
0.39
0
129
0.16
0
162
–0.15
19200
0
48
–0.35
0
53
–0.54
0
64
0.16
0
80
–0.47
31250
0
29
0.00
0
32
0.00
0
39
0.00
0
49
0
38400
0
23
1.73
0
26
–0.54
0
32
–1.36
0
40
–0.76
Note: Settings with an error of 1% or less are recommended.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 855 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.5 Bit Rates and SCBRR Settings (Clocked Synchronous Mode)
Pφ (MHz)
Bit Rate
(bit/s)
16
n
N
3
249
28.7
n
N
30
n
N
33
n
N
40
n
N
50
n
N
110
250
500
3
124
3
223
3
233
3
255
—
—
—
—
1k
2
249
3
111
3
116
3
125
3
152
3
194
2.5 k
2
99
2
178
2
187
2
200
2
243
3
77
5k
1
199
2
89
2
93
2
100
2
121
2
155
10 k
1
99
1
178
1
187
1
200
2
60
2
77
25 k
0
159
1
71
1
74
1
80
1
97
1
124
50 k
0
79
0
143
0
149
0
160
1
48
0
249
100 k
0
39
0
71
0
74
0
80
0
97
0
124
250 k
0
15
—
—
0
29
0
31
0
38
0
49
500 k
0
7
—
—
0
14
0
15
0
19
0
24
1M
0
3
0
7
0
9
—
—
2M
0
1
0
3
—
—
[Legend]
Blank: No setting possible
—:
Setting possible, but error occurs
Page 856 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is
used. Tables 17.7 and 17.8 list the maximum bit rates when the external clock input is used.
Table 17.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)
Settings
Pφ (MHz)
Maximum Bit Rate (bits/s)
n
N
12
375000
0
0
14.7456
460800
0
0
16
500000
0
0
19.6608
614400
0
0
20
625000
0
0
24
750000
0
0
24.576
768000
0
0
28.7
896875
0
0
30
937500
0
0
33
1031250
0
0
40
1250000
0
0
50
1562500
0
0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 857 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
Pφ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
12
3.0000
187500
14.7456
3.6864
230400
16
4.0000
250000
19.6608
4.9152
307200
20
5.0000
312500
24
6.0000
375000
24.576
6.1440
384000
28.7
7.1750
448436
30
7.5000
468750
33
8.2500
515625
40
10.0000
625000
50
12.5000
781250
Table 17.8 Maximum Bit Rates with External Clock Input
Pφ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
16
2.6667
2666666.7
24
4.0000
4000000.0
28.7
4.7833
4783333.3
30
5.0000
5000000.0
33
5.5000
5500000.0
40
6.6667
6666666.7
50
8.0000
8000000.0
Page 858 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
17.3.9
Section 17 Serial Communication Interface with FIFO (SCIF)
FIFO Control Register (SCFCR)
SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU. It is initialized to H'0000 by a power-on reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
-
-
-
-
-
-
-
-
RTRG[1:0]
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
—
All 0
R
Reserved
0
R/W
6
0
R/W
5
4
3
TTRG[1:0]
-
0
R/W
0
R/W
0
R
2
1
0
TFRST RFRST
LOOP
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value should
always be 0.
7, 6
RTRG[1:0]
00
R/W
Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register (SCFSR).
The RDF flag is set to 1 when the quantity of receive
data stored in the receive FIFO register (SCFRDR) is
increased more than the set trigger number shown
below.
•
Asynchronous mode •
Clocked synchronous mode
00: 1
00: 1
01: 4
01: 2
10: 8
10: 8
11: 14
11: 14
Note:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
In clock synchronous mode, to transfer the
receive data using DMAC, set the receive trigger
number to 1. If set to other than 1, CPU must
read the receive data left in SCFRDR.
Page 859 of 1778
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
5, 4
TTRG[1:0]
00
R/W
Transmit FIFO Data Trigger
SH7280 Group, SH7243 Group
Set the quantity of remaining transmit data which sets
the transmit FIFO data register empty (TDFE) flag in the
serial status register (SCFSR). The TDFE flag is set to 1
when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set
trigger number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
empty bytes in SCFTDR when the TDFE flag is
set to 1.
3
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
TFRST
0
R/W
Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1
RFRST
0
R/W
Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
0
LOOP
0
R/W
Loop-Back Test
Internally connects the transmit output pin (TXD) and
receive input pin (RXD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
Page 860 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data
register (SCFTDR) and the receive FIFO data register (SCFRDR).
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of
receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. SCFDR is
initialized to H'0000 by a power on reset.
Bit:
Initial value:
R/W:
15
14
13
-
-
-
0
R
0
R
0
R
12
11
10
9
8
T[4:0]
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
—
All 0
R
Reserved
7
6
5
-
-
-
0
R
0
R
0
R
4
3
2
1
0
0
R
0
R
R[4:0]
0
R
0
R
0
R
These bits are always read as 0. The write value should
always be 0.
12 to 8
T[4:0]
00000
R
7 to 5
—
All 0
R
T4 to T0 bits indicate the quantity of non-transmitted
data stored in SCFTDR. H'00 means no transmit data,
and H'10 means that SCFTDR is full of transmit data.
Reserved
These bits are always read as 0. The write value should
always be 0.
4 to 0
R[4:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
00000
R
R4 to R0 bits indicate the quantity of receive data
stored in SCFRDR. H'00 means no receive data, and
H'10 means that SCFRDR full of receive data.
Page 861 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.11 Serial Port Register (SCSPTR)
SCSPTR controls input/output and data of pins multiplexed to SCIF function. Bits 3 and 2 can
control input/output data of SCK pin. Bits 1 and 0 can input data from RXD pin and output data to
TXD pin, so they control break of serial transmitting/receiving.
The CPU can always read and write to SCSPTR. SCSPTR is initialized to H'00xx by a power-on
reset.
Bit:
Initial value:
R/W:
Bit
15
14
13
12
11
10
9
8
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0 Undefined 0 Undefined 0 Undefined 0 Undefined
R
R
R
R
R/W
W
R/W
W
Initial
Bit Name Value
15 to 7 —
All 0
3
2
1
0
SCKIO SCKDT SPB2IOSPB2DT
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
6
—
Undefined R
5
—
0
Reserved
Undefined value.
R
Reserved
This bit is always read as 0. The write value should always be
0.
4
—
Undefined R
Reserved
Undefined value.
3
SCKIO
0
R/W SCK Port Input/Output
Indicates input or output of the serial port SCK pin. When the
SCK pin is actually used as a port outputting the SCKDT bit
value, the CKE[1:0] bits in SCSCR should be cleared to 0.
0: SCKDT bit value not output to SCK pin
1: SCKDT bit value output to SCK pin
2
SCKDT
Undefined W
SCK Port Data
Indicates the input/output data of the serial port SCK pin.
Input/output is specified by the SCKIO bit. For output, the
SCKDT bit value is output to the SCK pin. The SCK pin
status is read from the SCKDT bit regardless of the SCKIO
bit setting. However, SCK input/output must be set in the
PFC.
0: Input/output data is low level
1: Input/output data is high level
Page 862 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
1
SPB2IO
0
R/W
Serial Port Break Input/Output
Indicates input or output of the serial port TXD pin.
When the TXD pin is actually used as a port
outputting the SPB2DT bit value, the TE bit in
SCSCR should be cleared to 0.
0: SPB2DT bit value not output to TXD pin
1: SPB2DT bit value output to TXD pin
0
SPB2DT
Undefined W
Serial Port Break Data
Indicates the input data of the RXD pin and the
output data of the TXD pin used as serial ports.
Input/output is specified by the SPB2IO bit. When the
TXD pin is set to output, the SPB2DT bit value is
output to the TXD pin. The RXD pin status is read
from the SPB2DT bit regardless of the SPB2IO bit
setting. However, RXD input and TXD output must be
set in the PFC.
0: Input/output data is low level
1: Input/output data is high level
17.3.12 Line Status Register (SCLSR)
The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can
be cleared to 0 only if it has first been read (after being set to 1).
SCLSR is initialized to H'0000 by a power-on reset.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ORER
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/(W)*
Note: * Only 0 can be written to clear the flag after 1 is read.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 863 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial
Value
R/W
Description
15 to 1
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ORER
0
R/(W)* Overrun Error
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*
1
[Clearing conditions]
•
ORER is cleared to 0 when the chip is a power-on
reset
•
ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
1: An overrun error has occurred*2
[Setting condition]
•
ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
Notes: 1. Clearing the RE bit to 0 in SCSCR does
not affect the ORER bit, which retains its
previous value.
2. The receive FIFO data register (SCFRDR)
retains the data before an overrun error
has occurred, and the next received data
is discarded. When the ORER bit is set to
1, the SCIF cannot continue the next
serial reception.
Page 864 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.13 Serial Extended Mode Register (SCSEMR)
SCSEMR is an 8-bit register that extends the SCIF functions. The transfer rate can be doubled by
setting the basic clock in asynchronous mode.
Be sure to set this register to H'00 in clocked synchronous mode. SCSEMR is initialized to H'00
by a power-on reset.
Bit:
Initial value:
R/W:
0
7
6
5
4
3
2
1
ABCS
-
-
-
-
-
-
-
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
ABCS
0
R/W
Asynchronous Basic Clock Select
Selects the basic clock for 1-bit period in
asynchronous mode.
Setting of ABCS is valid when the asynchronous
mode bit (C/A in SCSMR) = 0.
0: Basic clock with a frequency of 16 times the
transfer rate
1: Basic clock with a frequency of 8 times the transfer
rate
6 to 0
—
All 0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 865 of 1778
Section 17 Serial Communication Interface with FIFO (SCIF)
17.4
Operation
17.4.1
Overview
SH7280 Group, SH7243 Group
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually, and a clocked synchronous mode in which communication is
synchronized with clock pulses.
The SCIF has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead
of the CPU, and enabling continuous high-speed communication.
The transmission format is selected in the serial mode register (SCSMR), as shown in table 17.9.
The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial
control register (SCSCR), as shown in table 17.10.
(1)
Asynchronous Mode
• Data length is selectable: 7 or 8 bits
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding
selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full,
overrun errors, receive data ready, and breaks.
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source.
⎯ When an internal clock is selected, the SCIF operates using the clock of on-chip baud rate
generator.
⎯ When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
(2)
Clocked Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCIF clock source.
⎯ When an internal clock is selected, the SCIF operates using the clock of the on-chip baud
rate generator, and outputs this clock to external devices as the synchronous clock.
⎯ When an external clock is selected, the SCIF operates on the input synchronous clock not
using the on-chip baud rate generator.
Page 866 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Table 17.9 SCSMR Settings and SCIF Communication Formats
SCSMR
SCIF Communication Format
Bit 7 Bit 6 Bit 5 Bit 3
C/A CHR PE
STOP Mode
Data Length
Parity Bit
Stop Bit Length
0
8 bits
Not set
1 bit
0
0
0
Asynchronous
1
1
2 bits
0
Set
1
1
0
2 bits
0
7 bits
Not set
1
1
x
x
0
x
1 bit
2 bits
Set
1
1
1 bit
1 bit
2 bits
Clocked
synchronous
8 bits
Not set
None
[Legend]
x:
Don't care
Table 17.10 SCSMR and SCSCR Settings and SCIF Clock Source Selection
SCSMR
SCSCR
Bit 7
Bit 1
Bit 0
C/A
CKE1
CKE0
Mode
Clock
Source
0
0
0
Asynchronous
Internal
1
1
1
SCK Pin Function
SCIF does not use the SCK pin
Outputs a clock with a frequency 16
times the bit rate
0
External
1
Setting prohibited
0
x
1
0
1
Clocked
synchronous
Inputs a clock with frequency 16
times the bit rate
Internal
Outputs the serial clock
External
Inputs the serial clock
Setting prohibited
[Legend]
x:
Don't care
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 867 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.4.2
Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCIF are independent, so full duplex
communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be
written and read while transmitting and receiving are in progress, enabling continuous transmitting
and receiving.
Figure 17.2 shows the general format of asynchronous serial communication.
In asynchronous serial communication, the communication line is normally held in the mark
(high) state. The SCIF monitors the line and starts serial communication when the line goes to the
space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB
first), parity bit (high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit.
The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit
rate. Receive data is latched at the center of each bit.
Idle state (mark state)
1
(LSB)
Serial
data
0
Start
bit
1 bit
D0
(MSB)
D1
D2
D3
D4
D5
D6
D7
Transmit/receive data
7 or 8 bits
1
0/1
1
1
Parity
bit
Stop bit
1 bit
or
none
1 or 2 bits
One unit of transfer data (character or frame)
Figure 17.2 Example of Data Format in Asynchronous Communication
(8-Bit Data with Parity and Two Stop Bits)
Page 868 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 17 Serial Communication Interface with FIFO (SCIF)
Transmit/Receive Formats
Table 17.11 lists the eight communication formats that can be selected in asynchronous mode. The
format is selected by settings in the serial mode register (SCSMR).
Table 17.11 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits
CHR
PE STOP
Serial Transmit/Receive Format and Frame Length
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
START
8-bit data
STOP
0
0
1
START
8-bit data
STOP STOP
0
1
0
START
8-bit data
P
STOP
0
1
1
START
8-bit data
P
STOP STOP
1
0
0
START
7-bit data
STOP
1
0
1
START
7-bit data
STOP STOP
1
1
0
START
7-bit data
P
STOP
1
1
1
START
7-bit data
P
STOP STOP
[Legend]
START: Start bit
STOP: Stop bit
P:
Parity bit
(2)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE[1:0] in the serial control register
(SCSCR). For clock source selection, refer to table 17.10.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCIF operates on an internal clock, it can output a clock signal on the SCK pin. The
frequency of this output clock is 16 times the desired bit rate.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 869 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
(3)
Transmitting and Receiving Data
• SCIF Initialization (Asynchronous Mode)
Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register
(SCSCR), then initialize the SCIF as follows.
When changing the operating mode or the communication format, always clear the TE and RE bits
to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift
register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register
(SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which
retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the
TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the
transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1
and reset SCFTDR before TE is set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Figure 17.3 shows a sample flowchart for initializing the SCIF.
Start of initialization
[1] Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Clear TE and RE bits in SCSCR to 0
[2] Set the data transfer format in
SCSMR.
Set TFRST and RFRST bits in SCFCR to 1
After reading ER, DR, and BRK flags in SCFSR,
and each flag in SCLSR, write 0 to clear them
Set CKE1 and CKE0 in SCSCR
(leaving TIE, RIE, TE, and RE bits cleared to 0)
[1]
Set data transfer format in SCSMR
[2]
Set value in SCBRR
[3]
Set ABCS bit in SCSEMR
[3] Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
[4] Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Set RTRG[1:0] and TTRG[1:0], and MCE in
SCFCR, and clear TFRST and RFRST
Set TE and RE bits in SCSCR to 1,
and set TIE, RIE, and REIE bits
[4]
End of initialization
Figure 17.3 Sample Flowchart for SCIF Initialization
Page 870 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
• Transmitting Serial Data (Asynchronous Mode)
Figure 17.4 shows a sample flowchart for serial transmission. Use the following procedure for
serial data transmission after enabling the SCIF for transmission.
Start of transmission
Read TDFE flag in SCFSR
TDFE = 1?
No
Yes
Write transmit data in SCFTDR,
and read 1 from TDFE flag
and TEND flag in SCFSR,
then clear to 0
All data transmitted?
[1]
No
[2]
Yes
No
Yes
Break output?
No
Yes
Clear SPB2DT to 0 and
set SPB2IO to 1
[2] Serial transmission continuation
procedure:
To continue serial transmission, read
1 from the TDFE flag to confirm that
writing is possible, then write data to
SCFTDR, and then clear the TDFE
flag to 0.
[3] Break output during serial
transmission:
To output a break in serial
transmission, clear the SPB2DT bit to
0 and set the SPB2IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR to 0.
Read TEND flag in SCFSR
TEND = 1?
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and read 1
from the TDFE and TEND flags, then
clear to 0.
The quantity of transmit data that can
be written is 16 - (transmit trigger set
number).
[3]
In [1] and [2], it is possible to ascertain
the number of data bytes that can be
written from the number of transmit data
bytes in SCFTDR indicated by the upper
8 bits of SCFDR.
Clear TE bit in SCSCR to 0
End of transmission
Figure 17.4 Sample Flowchart for Transmitting Serial Data
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 871 of 1778
Section 17 Serial Communication Interface with FIFO (SCIF)
SH7280 Group, SH7243 Group
In serial transmission, the SCIF operates as described below.
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is
generated.
The serial transmit data is sent from the TXD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is
not output can also be selected.)
D. Stop bit(s): One or two 1 bits (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
sent.
3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
Page 872 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Figure 17.5 shows an example of the operation for transmission.
1
Serial
data
Start
bit
0
Parity
bit
Data
D0
D1
D7
0/1
Stop
bit
1
Start
bit
0
Parity
bit
Data
D0
D1
D7
0/1
Stop
bit
1
1
Idle state
(mark state)
TDFE
TEND
TXI interrupt
request
Data written to SCFTDR and TDFE
flag read as 1 then cleared to 0 by
TXI interrupt handler
TXI interrupt
request
One frame
Figure 17.5 Example of Transmit Operation
(8-Bit Data, Parity, 1 Stop Bit)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 873 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Asynchronous Mode)
Figures 17.6 and 17.7 show sample flowcharts for serial reception. Use the following procedure
for serial data reception after enabling the SCIF for reception.
[1] Receive error handling and
break detection:
Start of reception
Read ER, DR, BRK flags in
SCFSR and ORER
flag in SCLSR
ER, DR, BRK or ORER = 1?
No
Read RDF flag in SCFSR
No
[1]
Yes
Error handling
[2]
[2] SCIF status check and receive
data read:
Read SCFSR and check that
RDF flag = 1, then read the
receive data in SCFRDR, read
1 from the RDF flag, and then
clear the RDF flag to 0. The
transition of the RDF flag from
0 to 1 can be identified by an
RXI interrupt.
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
Read the DR, ER, and BRK
flags in SCFSR, and the
ORER flag in SCLSR, to
identify any error, perform the
appropriate error handling,
then clear the DR, ER, BRK,
and ORER flags to 0. In the
case of a framing error, a
break can also be detected by
reading the value of the RxD
pin.
[3] Serial reception continuation
procedure:
All data received?
Yes
Clear RE bit in SCSCR to 0
End of reception
[3]
To continue serial reception,
read at least the receive
trigger set number of receive
data bytes from SCFRDR,
read 1 from the RDF flag, then
clear the RDF flag to 0. The
number of receive data bytes
in SCFRDR can be
ascertained by reading from
SCRFDR.
Figure 17.6 Sample Flowchart for Receiving Serial Data
Page 874 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
ER = 1?
Yes
Receive error handling
• Whether a framing error or parity error
has occurred in the receive data that
is to be read from the receive FIFO
data register (SCFRDR) can be
ascertained from the FER and PER
bits in the serial status register
(SCFSR).
• When a break signal is received,
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.
No
BRK = 1?
Yes
Break handling
No
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, BRK flags
in SCFSR,
and ORER flag in SCLSR to 0
End
Figure 17.7 Sample Flowchart for Receiving Serial Data (cont)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 875 of 1778
Section 17 Serial Communication Interface with FIFO (SCIF)
SH7280 Group, SH7243 Group
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
the first is checked.
B. The SCIF checks whether receive data can be transferred from the receive shift register
(SCRSR) to SCFRDR.
C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error
has not occurred.
D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
set.
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: When a parity error or a framing error occurs, reception is not suspended.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to
1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the
RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Page 876 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Figure 17.8 shows an example of the operation for reception.
1
Serial
data
Start
bit
0
Data
D0
D1
D7
Parity
bit
Stop
bit
Start
bit
0/1
1
0
Parity
bit
Data
D0
D1
D7
0/1
Stop
bit
1
1
Idle state
(mark state)
RDF
RXI interrupt
request
FER
One frame
Data read and RDF flag
read as 1 then cleared to 0
by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 17.8 Example of SCIF Receive Operation
(8-Bit Data, Parity, 1 Stop Bit)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 877 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.4.3
Operation in Clocked Synchronous Mode
In clocked synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCIF transmitter and receiver are independent, so full-duplex communication is possible
while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 17.9 shows the general format in clocked synchronous serial communication.
One unit of transfer data (character or frame)
*
*
Serial clock
LSB
Serial data
Don't care
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't care
Note: * High except in continuous transfer
Figure 17.9 Data Format in Clocked Synchronous Communication
In clocked synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock.
In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB
(last). After output of the MSB, the communication line remains in the state of the MSB.
In clocked synchronous mode, the SCIF receives data by synchronizing with the rising edge of the
serial clock.
Page 878 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 17 Serial Communication Interface with FIFO (SCIF)
Transmit/Receive Formats
The data length is fixed at eight bits. No parity bit can be added.
(2)
Clock
An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in
SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as
the SCIF transmit/receive clock.
When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCIF is not transmitting or
receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs
while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive
FIFO data trigger number.
(3)
Transmitting and Receiving Data
• SCIF Initialization (Clocked Synchronous Mode)
Before transmitting, receiving, or changing the mode or communication format, the software must
clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF.
Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does
not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which
retain their previous contents.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 879 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Figure 17.10 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits
in SCSCR to 0
[1]
[2] Set the data transfer format in
SCSMR.
Set TFRST and RFRST bits
in SCFCR to 1 to clear
the FIFO buffer
[3] Set CKE[1:0].
After reading ER, DR,
and BRK flags in SCFSR,
write 0 to clear them
Set data transfer format
in SCSMR
[2]
Set CKE[1:0] in SCSCR
(leaving TIE, RIE, TE,
and RE bits cleared to 0)
[3]
Set value in SCBRR
[4]
Set RTRG[1:0] and TTRG[1:0] in SCFCR,
and clear TFRST and RFRST
Set TE and RE bits in SCSCR
to 1, and set TIE, RIE,
and REIE bits
[1] Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
[4] Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used.
[5] Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the TXD,
RXD, and SCK pins to be used.
When transmitting, the TXD pin
will go to the mark state.
When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCK pin at this
point.
[5]
End of initialization
Figure 17.10 Sample Flowchart for SCIF Initialization
Page 880 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
• Transmitting Serial Data (Clocked Synchronous Mode)
Figure 17.11 shows a sample flowchart for transmitting serial data. Use the following procedure
for serial data transmission after enabling the SCIF for transmission.
Start of transmission
[1] SCIF status check and transmit data
write:
Read TDFE flag in SCFSR
TDFE = 1?
Read SCFSR and check that the
TDFE and TEND flags are set to 1,
then write transmit data to the
transmit FIFO data register
(SCFTDR). Read 1 from the TDFE
and TEND flags, then clear these
flags to 0.
No
Yes
Write transmit data to SCFTDR,
read 1 from TDFE and FEND
flags in SCFSR, and
clear them to 0
All data transmitted?
[1]
No
[2] Serial transmission continuation
procedure:
To continue serial transmission, read
1 from the TDFE flag to confirm that
[2]
Yes
Read TEND flag in SCFSR
TEND = 1?
No
Yes
Clear TE bit in SCSCR to 0
End of transmission
Figure 17.11 Sample Flowchart for Transmitting Serial Data
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 881 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below.
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is
generated.
If clock output mode is selected, the SCIF outputs eight synchronous clock pulses. If an
external clock source is selected, the SCIF outputs data in synchronization with the input
clock. Data is output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCIF checks the SCFTDR transmit data at the timing for sending the MSB (bit 7). If data
is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the
next frame is started. If there is no data, the TXD pin holds the state after the TEND flag in
SCFSR is set to 1 and the MSB (bit 7) is sent.
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 17.12 shows an example of SCIF transmit operation.
Serial clock
LSB
Bit 0
Serial data
Bit 1
MSB
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDFE
TEND
TXI
interrupt
request
Data written to SCFTDR
TXI
and TDFE flag cleared interrupt
to 0 by TXI interrupt
request
handler
One frame
Figure 17.12 Example of SCIF Transmit Operation
Page 882 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Clocked Synchronous Mode)
Figures 17.13 and 17.14 show sample flowcharts for receiving serial data. When switching from
asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that
ORER, PER, and FER are cleared to 0.
Start of reception
[1] Receive error handling:
Read the ORER flag in SCLSR to identify
any error, perform the appropriate error
handling, then clear the ORER flag to 0.
Reception cannot be resumed while the
ORER flag is set to 1.
Read ORER flag in SCLSR
ORER = 1?
Yes
[1]
No
Read RDF flag in SCFSR
No
Error handling
[2]
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
[3]
[2] SCIF status check and receive data read:
Read SCFSR and check that RDF = 1,
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
of the RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
[3] Serial reception continuation procedure:
To continue serial reception, read at least
the receive trigger set number of receive
data bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
SCFRDR. However, the RDF bit is
cleared to 0 automatically when an RXI
interrupt activates the DMAC to read the
data in SCFRDR.
End of reception
Figure 17.13 Sample Flowchart for Receiving Serial Data (1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 883 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 17.14 Sample Flowchart for Receiving Serial Data (2)
In serial reception, the SCIF operates as described below.
1. The SCIF synchronizes with serial clock input or output and starts the reception.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the RDF flag is set to 1 and the SCIF stores the received data in SCFRDR. If
the check is not passed (overrun error is detected), further reception is prevented.
3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in
SCSCR, the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and
the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE)
in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Page 884 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
Figure 17.15 shows an example of SCIF receive operation.
Serial clock
LSB
Serial data
Bit 7
MSB
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDF
ORER
RXI
interrupt
request
Data read from SCFRDR and
RDF flag cleared to 0 by RXI
interrupt handler
RXI
interrupt
request
BRI interrupt request
by overrun error
One frame
Figure 17.15 Example of SCIF Receive Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 885 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
• Transmitting and Receiving Serial Data Simultaneously (Clocked Synchronous Mode)
Figure 17.16 shows a sample flowchart for transmitting and receiving serial data simultaneously.
Use the following procedure for the simultaneous transmission/reception of serial data, after
enabling the SCIF for transmission/reception.
[1] SCIF status check and transmit data
write:
Initialization
Read SCFSR and check that the
TDFE and TEND flags are set to 1,
then write transmit data to SCFTDR
and clear the TDFE and TEND flags
to 0. The transition of the TDFE flag
from 0 to 1 can also be identified by a
TXI interrupt.
Start of transmission and reception
Read TDFE flag in SCFSR
No
[2] Receive error handling:
TDFE = 1?
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
Yes
Write transmit data to SCFTDR,
read 1 from TDFE and FEND
flags in SCFSR, and
clear them to 0
[1]
[3] SCIF status check and receive data
read:
Read SCFSR and check that RDF
flag = 1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by an RXI
interrupt.
Read ORER flag in SCLSR
Yes
ORER = 1?
[2]
No
Error handling
Read RDF flag in SCFSR
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
[3]
[4] Serial transmission and reception
continuation procedure:
To continue serial transmission and
reception, read 1 from the RDF flag
and the receive data in SCFRDR, and
clear the RDF flag to 0 before
receiving the MSB in the current
frame. Similarly, read 1 from the
TDFE flag to confirm that writing is
possible before transmitting the MSB
in the current frame. Then write data
to SCFTDR and clear the TDFE flag
to 0.
All data received?
Yes
Clear TE and RE bits
in SCSCR to 0
[4]
Note: When switching from a transmit operation
or receive operation to simultaneous
transmission and reception operations,
clear the TE and RE bits to 0, and then
set them simultaneously to 1.
End of transmission and reception
Figure 17.16 Sample Flowchart for Transmitting/Receiving Serial Data
Page 886 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
17.5
Section 17 Serial Communication Interface with FIFO (SCIF)
SCIF Interrupts
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive FIFO data full (RXI), and break (BRI).
Table 17.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC or DTC can be activated and
data transfer performed by this TXI interrupt request. At DMAC activation, an interrupt request is
not sent to the CPU.
When an RXI request is enabled by the RIE bit and the RDFE flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. The DMAC or DTC can be activated and data transfer
performed by this RXI interrupt request. At DMAC activation, an interrupt request is not sent to
the CPU. The RXI interrupt request caused by the DR flag is generated only in asynchronous
mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt
without requesting an RXI interrupt.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
Table 17.12 SCIF Interrupt Sources
Interrupt
Source
Description
DMAC or DTC Priority on
Activation
Reset Release
BRI
Interrupt initiated by break (BRK) or overrun error
(ORER)
Not possible
ERI
Interrupt initiated by receive error (ER)
Not possible
RXI
Interrupt initiated by receive FIFO data full (RDF) or Possible
data ready (DR)
TXI
Interrupt initiated by transmit FIFO data empty
(TDFE)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
High
Possible
Low
Page 887 of 1778
Section 17 Serial Communication Interface with FIFO (SCIF)
17.6
SH7280 Group, SH7243 Group
Usage Notes
Note the following when using the SCIF.
17.6.1
SCFTDR Writing and TDFE Flag
The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes
written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number
set by bits TTRG[1:0] in the FIFO control register (SCFCR). After the TDFE flag is set, transmit
data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous
transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE
flag clearing should therefore be carried out when SCFTDR contains more than the transmit
trigger number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO
data count register (SCFDR).
17.6.2
SCFRDR Reading and RDF Flag
The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in
the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger
number set by bits RTRG[1:0] in the FIFO control register (SCFCR). After RDF flag is set,
receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient
continuous reception.
However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will
be set to 1 again if it is cleared to 0. The RDF flag should therefore be cleared to 0 after being read
as 1 after reading the number of the received data in the receive FIFO data register (SCFRDR)
which is less than the trigger number.
The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data
count register (SCFDR).
Page 888 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
17.6.3
Section 17 Serial Communication Interface with FIFO (SCIF)
Restriction on DMAC and DTC Usage
When the DMAC or DTC writes data to SCFTDR due to a TXI interrupt request, the state of the
TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end
flag in such a case.
17.6.4
Break Detection and Processing
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set
and the parity error flag (PER) may also be set.
Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF
receiver continues to operate.
17.6.5
Sending a Break Signal
The I/O condition and level of the TXD pin are determined by the SPB2IO and SPB2DT bits in
the serial port register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, the TXD pin does not work.
During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and
SPB2DT bits should be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD
pin.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 889 of 1778
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
17.6.6
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
The SCIF operates on a base clock with a frequency of 16 times the transfer rate.* In reception,
the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in
figure 17.17.
Note: * This is an example when ABCS = 0 in SCSEMR. When ABCS = 1, a frequency of 8 times
the bit rate becomes the basic clock, and receive data is sampled at the fourth rising edge
of the basic clock.
16 clocks
8 clocks
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
Base clock
–7.5 clocks
Receive data
(RxD)
Start bit
+7.5 clocks
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 17.17 Receive Data Sampling Timing in Asynchronous Mode
Page 890 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 17 Serial Communication Interface with FIFO (SCIF)
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5 −
Where: M:
N:
D:
L:
F:
D − 0.5
1
) − (L − 0.5) F −
(1 + F) × 100 %
2N
N
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M = (0.5 − 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
17.6.7
FER Flag and PER Flag of Serial Status Register (SCFSR)
The FER flag and PER flag in the serial status register (SCFSR) are status flag that apply to next
entry to be read from the receive FIFO data register (SCFRDR). After the CPU or DMAC reads
the receive FIFO data register, the flags of framing errors and parity errors will disappear.
To check the received data for the states of framing errors and parity errors, only read the receive
FIFO register after reading the serial status register.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 891 of 1778
Section 17 Serial Communication Interface with FIFO (SCIF)
Page 892 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Section 18 Synchronous Serial Communication Unit (SSU)
This LSI (SH7286 or SH7285) has an independent synchronous serial communication unit (SSU)
channel. The SSU has master mode in which this LSI outputs clocks as a master device for
synchronous serial communication and slave mode in which clocks are input from an external
device for synchronous serial communication. Synchronous serial communication can be
performed with devices having different clock polarity and clock phase.
18.1
•
•
•
•
•
•
•
•
•
•
•
Features
Choice of SSU mode and clock synchronous mode
Choice of master mode and slave mode
Choice of standard mode and bidirectional mode
Synchronous serial communication with devices with different clock polarity and clock phase
Choice of 8/16/32-bit width of transmit/receive data
Full-duplex communication capability
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
Consecutive serial communication
Choice of LSB-first or MSB-first transfer
Choice of a clock source
Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
Five interrupt sources
Transmit end, transmit data register empty, receive data full, overrun error, and conflict error.
The data transfer controller (DTC) can be activated by a transmit data register empty request or
a receive data full request to transfer data.
Module standby mode can be set
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 893 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Module data bus
SSCRH
Bus interface
Figure 18.1 shows a block diagram of the SSU.
Peripheral bus
SSTDR 0
SSRDR 0
SSCRL
SSTDR 1
SSRDR 1
SSCR2
SSOEI
SSTDR 2
SSRDR 2
SSMR
SSCEI
SSTDR 3
SSRDR 3
SSER
SSRXI
SSSR
SSTXI
Control circuit
SSTEI
Clock
Clock
selector
Shiftin
Shiftout
SSTRSR
Pφ/4
Pφ/8
Pφ/16
Pφ/32
Pφ/64
Pφ/128
Pφ/256
Selector
SSI
[Legend]
SSCRH:
SSCRL:
SSCR2:
SSMR:
SSER:
SSSR:
SSTDR0 to SSTDR3:
SSRDR0 to SSRDR3:
SSTRSR:
SSO
SCS
SSCK (External clock)
SS control register H
SS control register L
SS control register 2
SS mode register
SS enable register
SS status register
SS transmit data registers 0 to 3
SS receive data registers 0 to 3
SS shift register
Figure 18.1 Block Diagram of SSU
Page 894 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.2
Section 18 Synchronous Serial Communication Unit (SSU)
Input/Output Pins
Table 18.1 shows the SSU pin configuration.
Table 18.1 Pin Configuration
Symbol
I/O
Function
SSCK
I/O
SSU clock input/output
SSI
I/O
SSU data input/output
SSO
I/O
SSU data input/output
SCS
I/O
SSU chip select input/output
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 895 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
18.3
Register Descriptions
The SSU has the following registers. For details on the addresses of these registers and the states
of these registers in each processing state, see section 30, List of Registers.
Table 18.2 Register Configuration
Register Name
Abbreviation
R/W
Initial value
Address
Access Size
SS control register H
SSCRH
R/W
H'0D
H'FFFFB000
8, 16
SS control register L
SSCRL
R/W
H'00
H'FFFFB001
8
SS mode register
SSMR
R/W
H'00
H'FFFFB002
8, 16
SS enable register
SSER
R/W
H'00
H'FFFFB003
8
SS status register
SSSR
R/W
H'04
H'FFFFB004
8, 16
SS control register 2
SSCR2
R/W
H'00
H'FFFFB005
8
SS transmit data register 0
SSTDR0
R/W
H'00
H'FFFFB006
8, 16
SS transmit data register 1
SSTDR1
R/W
H'00
H'FFFFB007
8
SS transmit data register 2
SSTDR2
R/W
H'00
H'FFFFB008
8, 16
SS transmit data register 3
SSTDR3
R/W
H'00
H'FFFFB009
8
SS receive data register 0
SSRDR0
R
H'00
H'FFFFB00A
8, 16
SS receive data register 1
SSRDR1
R
H'00
H'FFFFB00B
8
SS receive data register 2
SSRDR2
R
H'00
H'FFFFB00C
8, 16
SS receive data register 3
SSRDR3
R
H'00
H'FFFFB00D
8
Page 896 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.3.1
Section 18 Synchronous Serial Communication Unit (SSU)
SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit:
0
7
6
5
4
3
2
1
MSS
BIDE
-
SOL
SOLP
-
CSS[1:0]
Initial value: 0
R/W: R/W
0
R/W
0
R
0
R/W
1
R/W
1
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
MSS
0
R/W
Master/Slave Device Select
1
R/W
Selects that this module is used in master mode or
slave mode. When master mode is selected, transfer
clocks are output from the SSCK pin. When the CE bit
in SSSR is set, this bit is automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
6
BIDE
0
R/W
Bidirectional Mode Enable
Selects that both serial data input pin and output pin are
used or one of them is used. However, transmission
and reception are not performed simultaneously when
bidirectional mode is selected. For details, section
18.4.3, Relationship between Data Input/Output Pins
and Shift Register.
0: Standard mode (two pins are used for data input and
output)
1: Bidirectional mode (one pin is used for data input and
output)
5
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 897 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
4
SOL
0
R/W
Serial Data Output Value Select
The serial data output retains its level of the last bit
after completion of transmission. The output level
before or after transmission can be specified by setting
this bit. When specifying the output level, use the MOV
instruction after clearing the SOLP bit to 0. Since writing
to this bit during data transmission causes malfunctions,
this bit should not be changed.
0: Serial data output is changed to low.
1: Serial data output is changed to high.
3
SOLP
1
R/W
SOL Bit Write Protect
When changing the output level of serial data, set the
SOL bit to 1 or clear the SOL bit to 0 after clearing the
SOLP bit to 0 using the MOV instruction.
0: Output level can be changed by the SOL bit
1: Output level cannot be changed by the SOL bit. This
bit is always read as 1.
2
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
1, 0
CSS[1:0]
01
R/W
SCS Pin Select
Select that the SCS pin functions as SCS input or
output.
00: Setting prohibited
01: Setting prohibited
10: Function as SCS automatic input/output (function as
SCS input before and after transfer and output a
low level during transfer)
11: Function as SCS automatic output (outputs a high
level before and after transfer and outputs a low
level during transfer)
Page 898 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.3.2
Section 18 Synchronous Serial Communication Unit (SSU)
SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit:
7
-
Initial value:
R/W:
0
R
6
5
SSUMS SRES
0
R/W
0
R/W
0
4
3
2
1
-
-
-
DATS[1:0]
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
R
Reserved
0
R/W
0
R/W
The bit is always read as 0. The write value should
always be 0.
6
SSUMS
0
R/W
Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
5
SRES
0
R/W
Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
4 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 899 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Initial
Value
Bit
Bit Name
1, 0
DATS[1:0] 00
R/W
Description
R/W
Transmit/Receive Data Length Select
Select serial data length.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
18.3.3
SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous
serial communication.
Bit:
7
6
5
4
3
MLS
CPOS
CPHS
-
-
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
7
MLS
0
R/W
2
1
0
CKS[2:0]
0
R/W
0
R/W
0
R/W
Description
MSB First/LSB First Select
Selects that the serial data is transmitted in MSB first or
LSB first.
0: LSB first
1: MSB first
6
CPOS
0
R/W
Clock Polarity Select
Selects the SSCK clock polarity.
0: High output in idle mode, and low output in active
mode
1: Low output in idle mode, and high output in active
mode
5
CPHS
0
R/W
Clock Phase Select (Only for SSU Mode)
Selects the SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
Page 900 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
4, 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2 to 0
CKS[2:0]
000
R/W
Transfer Clock Rate Select
Select the transfer clock rate (prescaler division rate)
when an internal clock is selected.
000: Reserved
001: Pφ/4
010: Pφ/8
011: Pφ/16
100: Pφ/32
101: Pφ/64
110: Pφ/128
111: Pφ/256
18.3.4
SS Enable Register (SSER)
SSER performs transfer/receive control of synchronous serial communication and setting of
interrupt enable.
Bit:
7
6
5
4
3
2
1
0
TE
RE
-
-
TEIE
TIE
RIE
CEIE
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Initial value: 0
R/W: R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
TE
0
R/W
Transmit Enable
6
RE
0
R/W
Receive Enable
When this bit is set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
5, 4
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 901 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
TEIE
0
R/W
Transmit End Interrupt Enable
SH7280 Group, SH7243 Group
When this bit is set to 1, an SSTEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, an SSTXI interrupt request is
enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an SSRXI interrupt request
and an SSOEI interrupt request are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, an SSCEI interrupt request is
enabled.
Page 902 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.3.5
Section 18 Synchronous Serial Communication Unit (SSU)
SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
ORER
-
-
TEND
TDRE
RDRF
CE
0
R
0
R/W
0
R
0
R
0
R/W
1
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
ORER
0
R/W
Overrun Error
If the next data is received while RDRF = 1 in data
transfer mode (TE=RE=1), an overrun error occurs,
indicating abnormal termination. SSRDR stores 1-frame
receive data before an overrun error occurs and loses
data to be received later. While ORER = 1, consecutive
serial reception cannot be continued. Serial
transmission cannot be continued, either.
[Setting condition]
•
When one byte of the next serial reception is
completed with RDRF = 1 in data transfer mode
(TE=RE=1).
[Clearing condition]
•
5, 4
⎯
All 0
R
When writing 0 after reading ORER = 1
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 903 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
TEND
0
R/W
Transmit End
[Setting conditions]
•
When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
•
After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
2
TDRE
1
R/W
•
When writing 0 after reading TEND = 1
•
When writing data to SSTDR
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
•
When the TE bit in SSER is 0
•
When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
Page 904 of 1778
•
When writing 0 after reading TDRE = 1
•
When writing data to SSTDR with TE = 1
•
When transmit data is written to SSTDR while the
DMAC is activated by an SSTXI.
•
When transmit data is written to SSTDR while the
DISEL bit in MRB of the DTC is 0 if the DMAC/DTC
is activated by an SSTXI interrupt and then DMAC
is activated.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
1
RDRF
0
R/W
0
CE
0
R/W
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
• When transmit data is read into SSRDR while the
DISEL bit in MRB of the DTC is 0 if the DMAC/DTC
is activated by an SSRXI interrupt and then DTC is
activated
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave device), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. In addition, an incomplete
error occurs when the next serial reception starts as
RDRF=1 in the state of SSUMS=0 (SSU mode) or
MSS=0 (slave device), then the SCS pin is changed to
1 after the RDRF is cleared to 0 while the SSRDR was
read before data reception is completed. Data reception
does not continue while the CE bit is set to 1. Serial
transmission also does not continue. Reset the SSU
internal sequencer by setting the SRES bit in SSCRL to
1 before resuming transfer after incomplete error.
[Setting conditions]
•
When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
•
When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
When the SCS pin is changed to 1, the next
reception starts as RDRF=1, then after having read
the SSRDR before data reception is completed
during transfer in slave mode (the MSS bit in
SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1
•
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 905 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
18.3.6
SS Control Register 2 (SSCR2)
SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS
pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of
the TEND bit.
Bit:
7
SDOS
Initial value: 0
R/W: R/W
6
5
4
3
2
SSCKOS SCSOS TENDSTS SCSATS SSODTS
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
0
-
-
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
SDOS
0
R/W
Serial Data Pin Open Drain Select
Selects whether the serial data output pin is used as a
TTL or an NMOS open drain output. Pins to output
serial data differ according to the register setting. For
details, see section 18.4.3, Relationship between Data
Input/Output Pins and Shift Register.
0: TTL output
1: NMOS open drain output
6
SSCKOS
0
R/W
SSCK Pin Open Drain Select
Selects whether the SSCK pin is used as a TTL or an
NMOS open drain output.
0: TTL output
1: NMOS open drain output
5
SCSOS
0
R/W
SCS Pin Open Drain Select
Selects whether the SCS pin is used as a TTL or an
NMOS open drain output.
0: TTL output
1: NMOS open drain output
4
TENDSTS 0
R/W
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
transmitted
1: Sets the TEND bit after the last bit is transmitted
Page 906 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
Initial
Value
R/W
Description
3
SCSATS
0
R/W
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc
1: Min. values of tLEAD and tLAG are 3/2 × tSUcyc
2
SSODTS
0
R/W
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
1, 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 907 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
18.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Do not
access SSTDR that is not valid.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DTC/DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Bit:
7
Initial value: 0
R/W: R/W
Bit
Bit Name
7 to 0
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R/W
Serial transmit data
Table 18.3 Setting of DATS Bits in SSCRL and Corresponding SSTDR
DATS[1:0] Setting
00
01
10
11 (Invalid Setting)
SSTDR0
Valid
Valid
Valid
Invalid
SSTDR1
Invalid
Valid
Valid
Invalid
SSTDR2
Invalid
Invalid
Valid
Invalid
SSTDR3
Invalid
Invalid
Valid
Invalid
Page 908 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.3.8
Section 18 Synchronous Serial Communication Unit (SSU)
SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Do
not access SSRDR that is not valid.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR
function as a double buffer in this way, consecutive receive operations can be performed.
Read SSRDR after confirming that the RDRF bit in SSSR is set to 1.
SSRDR is a read-only register, therefore, cannot be written to by the CPU.
Bit
Bit Name
7 to 0
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Initial
Value
R/W
Description
All 0
R
Serial receive data
Table 18.4 Setting of DATS Bit in SSCRL and Corresponding SSRDR
DATS[1:0] Setting
00
01
10
11 (Invalid Setting)
SSRDR0
Valid
Valid
Valid
Invalid
SSRDR1
Invalid
Valid
Valid
Invalid
SSRDR2
Invalid
Invalid
Valid
Invalid
SSRDR3
Invalid
Invalid
Valid
Invalid
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 909 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
18.3.9
SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data.
When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR
contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB
first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to
perform serial data transmission.
In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB
(bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to
SSRDR. SSTRSR cannot be directly accessed by the CPU.
Page 910 of 1778
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
-
-
-
-
-
-
-
-
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.4
Operation
18.4.1
Transfer Clock
Section 18 Synchronous Serial Communication Unit (SSU)
A transfer clock can be selected from seven internal clocks and an external clock. Before using
this module, enable the SSCK pin function in the PFC. When the MSS bit in SSCRH is 1, an
internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the
clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin.
When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.
18.4.2
Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of the
CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0. Figure 18.2
shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting
is valid.
Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data
is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the
LSB.
(1) When CPHS = 0
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(2) When CPHS = 1
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 18.2 Relationship of Clock Phase, Polarity, and Data
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 911 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
18.4.3
SH7280 Group, SH7243 Group
Relationship between Data Input/Output Pins and Shift Register
The connection between data input/output pins and the SS shift register (SSTRSR) depends on the
combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 18.3
shows the relationship.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 18.3 (1)). The SSU
transmits serial data from the SSI pin and receives serial data from the SSO pin when operating
with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 18.3 (2)).
The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode
when operating with BIDE = 1 (bidirectional mode) (see figures 18.3 (3) and (4)).
However, even if both the TE and RE bits are set to 1, transmission and reception are not
performed simultaneously. Either the TE or RE bit must be selected.
The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when
operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function
as an input pin when MSS = 0 (see figures 18.3 (5) and (6)).
Page 912 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
(1) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 1, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSO
(2) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 0, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSI
SSI
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 1, and either TE or RE = 1
SSCK
Shift register
(SSTRSR)
SSO
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 0, and either TE or RE = 1
SSCK
Shift register
(SSTRSR)
(6) When SSUMS = 1 and MSS = 0
SSCK
SSCK
Shift register
(SSTRSR)
SSO
SSI
SSI
(5) When SSUMS = 1 and MSS = 1
SSO
SSO
SSI
Shift register
(SSTRSR)
SSO
SSI
Figure 18.3 Relationship between Data Input/Output Pins and the Shift Register
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 913 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
18.4.4
Communication Modes and Pin Functions
The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the
communication modes and register settings. The input/output directions of the pins should be
selected in the port I/O registers. The relationship of communication modes and input/output pin
functions are shown in tables 18.5 to 18.7.
Table 18.5 Communication Modes and Pin States of SSI and SSO Pins
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
BIDE
MSS
TE
RE
SSI
SSO
0
0
0
0
1
⎯
Input
1
0
Output
⎯
1
SSU (bidirectional)
0
communication mode
1
0
1
Clock synchronous
1
communication mode
0
0
1
1
Output
Input
0
1
Input
⎯
1
0
⎯
Output
1
Input
Output
0
1
⎯
Input
1
0
⎯
Output
0
1
⎯
Input
1
0
⎯
Output
0
1
Input
⎯
1
0
⎯
Output
1
Input
Output
0
1
Input
⎯
1
0
⎯
Output
1
Input
Output
[Legend]
⎯: Not used as SSU pin
Page 914 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Table 18.6 Communication Modes and Pin States of SSCK Pin
Register Setting
Pin State
Communication Mode
SSUMS
MSS
SSCK
SSU communication mode
0
0
Input
1
Output
0
Input
1
Output
Clock synchronous communication mode
1
Table 18.7 Communication Modes and Pin States of SCS Pin
Communication
Mode
SSU communication
mode
Register Setting
Pin State
SSUMS
MSS
CSS1
CSS0
SCS
0
0
x
x
Input
1
0
0
⎯
0
1
⎯
1
0
Automatic
input/output
1
1
Output
x
x
⎯
Clock synchronous
1
communication mode
x
[Legend]
x:
Don't care
⎯:
Not used as SSU pin
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 915 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
18.4.5
SH7280 Group, SH7243 Group
SSU Mode
In SSU mode, data communications are performed via four lines: clock line (SSCK), data input
line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS).
In addition, the SSU supports bidirectional mode in which a single pin functions as data input and
data output lines.
(1)
Initial Settings in SSU Mode
Figure 18.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both
the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Page 916 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Start setting initial values
Clear TE and RE bits in SSER to 0
[1] Make appropriate settings in the PFC for the external pins to be used.
[2] Specify master/slave mode selection, bidirectional mode enable,
SSO pin output value selection, SSCK pin selection, and SCS pin
selection.
[1]
Set PFC for external pins to be used
(SSCK, SSI, SSO, and SCS)
[2]
Specify MSS, BIDE, SOL, CSS1,
and CSS0 bits in SSCRH
[3]
Clear SSUMS in SSCRH to 0 and
specify bits DATS1 and DATS0
[5] Specify open-drain output for the SSO, SSI, SSCK, and SCS pins.
Specify timing of TEND bit setting, SCS pin assertion, and data
output on the SSO pin.
Specify MLS, CPOS, CPHS, CKS2,
CKS1, and CKS0 bits in SSMR
[6] Enables/disables interrupt requests to the CPU.
[4]
[3] Selects SSU mode and specify transmit/receive data length.
[5]
[6]
[4] Specify MSB first/LSB first selection, clock polarity selection,
clock phase selection, and transfer clock rate selection.
Specify bits SDOS, SSCKOS, SCSOS,
TENDSTS, STSATS, and SSODTS
in SSCR2
Specify bits TE, RE, TEIE, TIE, RIE,
and CEIE in SSER simultaneously
End
Figure 18.4 Example of Initial Settings in SSU Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 917 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
(2)
SH7280 Group, SH7243 Group
Data Transmission
Figure 18.5 shows an example of transmission operation, and figure 18.6 shows a flowchart
example of data transmission.
When transmitting data, the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal
is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in
synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the
SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0 before transmission.
Page 918 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
1 frame
SSCK
SSO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
7
SSTDR0
(LSB first transmission)
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
SSTDR0
(MSB first transmission)
TDRE
TEND
TXI interrupt
TEI interrupt
generated
LSI operation
generated
User operation Data written to SSTDR0
TXI interrupt
generated
Data written to SSTDR0
TEI interrupt
generated
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
Bit
1
Bit
2
SSO
(MSB first)
Bit
7
Bit
6
Bit
5
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
0
Bit
1
Bit
2
Bit
2
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
SSTDR1
Bit
4
Bit
3
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
2
Bit
1
Bit
0
SSTDR0
SSTDR0
Bit
4
Bit
3
SSTDR1
TDRE
TEND
LSI operation
TXI interrupt generated
User operation Data written to SSTDR0 and SSTDR1
TEI interrupt generated
(3) When 32-bit data length is selected (SSTDR0 to SSTDR3 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSO
(LSB first)
Bit
0
to
Bit
7
SSTDR 3
SSO
(MSB first)
Bit
7
to
Bit
0
SSTDR0
Bit
0
to
Bit
7
SSTDR2
Bit
7
to
Bit
0
SSTDR1
Bit
0
to
Bit
7
SSTDR1
Bit
7
to
Bit
0
SSTDR2
Bit
0
to
Bit
7
SSTDR0
Bit
7
to
Bit
0
SSTDR3
TDRE
TEND
LSI operation
TXI interrupt generated
User operation Data written to SSTDR0 to SSTDR3
TEI interrupt generated
Figure 18.5 Example of Transmission Operation (SSU Mode)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 919 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
TDRE = 1?
[1] Initial setting:
Specify the transmit data format.
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
No
Yes
Write transmit data to SSTDR
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
TDRE automatically cleared
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Consecutive data transmission?
Yes
No
Read TEND in SSSR
TEND = 1?
No
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
[4]
One bit time
quantum elapsed?
Yes
No
Clear TE in SSER to 0
End transmission
Note: Hatching boxes represent SSU internal operations.
Figure 18.6 Flowchart Example of Data Transmission (SSU Mode)
Page 920 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 18 Synchronous Serial Communication Unit (SSU)
Data Reception
Figure 18.7 shows an example of reception operation, and figure 18.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
In continuous reception as the slave device in SSU mode, be sure to read SSRDR before reception
of the next frame starts. If reception of a next frame starts before clearing RDRF to 0, then read
SSRDR before completing the reception of the next frame, CE in SSSR will be set to 1 at the end
of the next frame.
If reception of the next frame starts before RDRF is cleared to 0 then SSRDR will not be read until
the end of completion, neither CE nor ORER in SSSR will be set but the received data will be
discarded.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 921 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
1 frame
SSCK
Bit Bit Bit Bit Bit Bit Bit Bit
0
1
2
3
4
5
6
7
SSI
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
SSRDR0 (LSB first transmission)
SSRDR0 (MSB first transmission)
RDRF
RXI interrupt
generated
LSI operation
RXI interrupt
generated
Read SSRDR0
User operation Dummy-read SSRDR0
(2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSI
(LSB first)
Bit Bit Bit Bit Bit Bit Bit Bit
0
1
2
3
4
5
6
7
SSI
(MSB first)
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
Bit Bit Bit Bit Bit Bit Bit Bit
0
1
2
3
4
5
6
7
SSRDR1
SSRDR0
Bit Bit Bit Bit Bit Bit Bit Bit
7
6
5
4
3
2
1
0
SSRDR0
SSRDR1
RDRF
LSI operation
RXI interrupt generated
User operation Dummy-readSSRDR0
(3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0
1 frame
SCS
SSCK
SSI
(LSB first)
Bit
0
SSI
(MSB first)
Bit
7
to
Bit Bit
7
0
SSRDR3
to
Bit Bit
7
0
SSRDR2
Bit Bit
0
7
SSRDR0
to
to
Bit
0
SSRDR1
to
Bit
7
SSRDR1
Bit
7
to
Bit
0
Bit
7
SSRDR0
Bit Bit
0
7
SSRDR2
to
to
Bit
0
SSRDR3
RDRF
LSI operation
User operation Dummy-readSSRDR0
RXI interrupt generated
Figure 18.7 Example of Reception Operation (SSU Mode)
Page 922 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Dummy-read SSRDR
RDRF = 1?
Yes
ORER = 1?
Initial setting:
Specify the receive data format.
[2]
Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
[3], [6] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
Read SSSR
No
[1]
Yes
[3]
[4]
To continue single reception:
When continuing single reception, wait for time of tSUcyc
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
[5]
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
No
[4]
Consecutive data reception?
No
Yes
Read received data in SSRDR
RDRF automatically cleared
[5]
RE = 0
Read receive data in SSRDR
End reception
[6]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 18.8 Flowchart Example of Data Reception (SSU Mode)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 923 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
(4)
SH7280 Group, SH7243 Group
Data Transmission/Reception
Figure 18.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
Page 924 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR.
[1] Initial setting:
Specify the transmit/receive data format.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
TDRE set to 1 to start transmission
Read SSSR
[3]
No
RDRF = 1?
Yes
ORER = 1?
Yes [4]
No
Read receive data in SSRDR
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Yes [5]
Read the TEND bit in SSSR
TEND = 1?
No
Yes
Clear TEND in SSSR to 0
One-bit interval elapsed?
Yes
No
Error processing
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 18.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 925 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
18.4.6
SH7280 Group, SH7243 Group
SCS Pin Control and Conflict Error
When bits CSS1 and CSS0 in SSCRH are set to B'10 and the SSUMS bit in SSCRL is cleared to
0, the SCS pin becomes an input pin (Hi-Z) before the serial transfer is started and after the serial
transfer is complete. Because of this, the SSU performs conflict error detection during these
periods. If a low level signal is input to the SCS pin during these periods, it is detected as a
conflict error. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception cannot be restarted. Clear the CE bit
to 0 before restarting the transmission or reception.
External input to SCS
Internally-clocked SCS
MSS
Internal signal for
transfer enable
Data written
to SSTDR
CE
SCS output
(Hi-Z)
Conflict error
detection period
Worst time for
internal clocking of SCS
Figure 18.10 Conflict Error Detection Timing (Before Transfer)
Page 926 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Pφ
SCS
(Hi-Z)
MSS
Internal signal for
transfer enable
CE
Transfer
end
Conflict error detection period
Figure 18.11 Conflict Error Detection Timing (After Transfer End)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 927 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
18.4.7
SH7280 Group, SH7243 Group
Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Initial Settings in Clock Synchronous Communication Mode
Figure 18.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1]
Set PFC for external pins to be used
(SSCK, SSI, SSO, and SCS)
[2]
Specify MSS in SSCRH
[1] Make appropriate settings in the PFC for the external
pins to be used.
[2] Specify master/slave mode selection and SSCK pin
selection.
[3] Selects clock synchronous communication mode and
specify transmit/receive data length.
[4] Specify clock polarity selection and transfer clock rate
selection.
[3]
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
[4]
Specify CPOS, CKS2, CKS1, and
CKS0 bits in SSMR
[5]
Specify bits SDOS, SSCKOS, SCSOS,
TENDSTS, STSATS, and SSODTS
in SSCR2
[6]
Specify bits TE, RE, TEIE, TIE, RIE,
and CEIE in SSER simultaneously
[5] Specify open-drain output for the SSO, SSI, SSCK, and SCS pins.
Specify timing of TEND bit setting, SCS pin assertion, and data
output on the SSO pin.
[6] Enables/disables interrupt requests to the CPU.
End
Figure 18.12 Example of Initial Settings in Clock Synchronous Communication Mode
Page 928 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 18 Synchronous Serial Communication Unit (SSU)
Data Transmission
Figure 18.13 shows an example of transmission operation, and figure 18.14 shows a flowchart
example of data transmission. When transmitting data in clock synchronous communication mode,
the SSU operates as shown below.
In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is
input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock.
Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and
the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and
starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated.
When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to
SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been
transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time,
if the TEIE bit is set to 1, a TEI interrupt is generated.
While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit
is cleared to 0 before transmission.
SSCK
SSO
Bit 0
Bit 1
Bit 7
Bit 0
1 frame
Bit 1
Bit 7
1 frame
TDRE
TEND
LSI operation
User operation
TXI interrupt
generated
Data written
to SSTDR
TXI interrupt
generated
TEI interrupt
generated
Data written
to SSTDR
Figure 18.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 929 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
[1] Initial setting:
Specify the transmit data format.
Start
[1]
Initial setting
[2]
Read TDRE in SSSR
TDRE = 1?
[2] Check that the SSU state and write transmit data:
Write transmit data to SSTDR after reading and confirming
that the TDRE bit is 1. The TDRE bit is automatically cleared
to 0 and transmission is started by writing data to SSTDR.
No
[3] Procedure for consecutive data transmission:
To continue data transmission, confirm that the TDRE bit is 1
meaning that SSTDR is ready to be written to. After that, data
can be written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.
Yes
Write transmit data to SSTDR
TDRE automatically cleared
[4] Procedure for data transmission end:
To end data transmission, confirm that the TEND bit is cleared
to 0. After completion of transmitting the last bit, clear the TE
bit to 0.
Data transferred from SSTDR to SSTRSR
Set TDRE to 1 to start transmission
[3]
Consecutive data transmission?
SH7280 Group, SH7243 Group
Yes
No
Read TEND in SSSR
TEND = 1?
No
Yes
Clear TEND to 0
Confirm that TEND is cleared to 0
One-bit intreval
elapsed?
Yes
[4]
No
Clear TE in SSER to 0
End transmission
Note: Hatched boxes represent SSU internal operations.
Figure 18.14 Flowchart Example of Transmission Operation
(Clock Synchronous Communication Mode)
Page 930 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 18 Synchronous Serial Communication Unit (SSU)
Data Reception
Figure 18.15 shows an example of reception operation, and figure 18.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When SSU is set in slave mode and receive data continuously, read SSRDR before starting
reception of a next frame. When the next reception starts before RDRF is cleared to 0, all
subsequent data is not guaranteed.
SSCK
SSO
Bit 0
Bit 7
1 frame
Bit 0
Bit 7
Bit 0
Bit 7
1 frame
RDRF
RXI interrupt
generated
LSI operation
User operation
Read data
from SSRDR
RXI interrupt
generated
Read data
from SSRDR
RXI interrupt
generated
Dummy-read SSRDR
Figure 18.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 931 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
RE = 1 (reception started)
RDRF = 1?
Initial setting:
Specify the receive data format.
[2]
Start reception:
When the RE bit is set to 1, reception is started.
[4]
Yes
ORER = 1?
[1]
[3], [5] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
Read SSSR
No
Yes [3]
No
Consecutive data reception?
SH7280 Group, SH7243 Group
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
No
Yes
Read received data in SSRDR
RDRF automatically cleared
[4]
RE = 0
Read receive data in SSRDR
End reception
[5]
Overrun error processing
Clear ORER in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 18.16 Flowchart Example of Data Reception
(Clock Synchronous Communication Mode)
Page 932 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(4)
Section 18 Synchronous Serial Communication Unit (SSU)
Data Transmission/Reception
Figure 18.17 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bits to 1.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 933 of 1778
SH7280 Group, SH7243 Group
Section 18 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read TDRE in SSSR.
[1] Initial setting:
Specify the transmit/receive data format.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE bit
is automatically cleared to 0 and transmission is started
by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
TDRE automatically cleared
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Read SSSR
[3]
No
RDRF = 1?
Yes
ORER = 1?
Yes [4]
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
No
Read receive data in SSRDR
RDRF automatically cleared
Consecutive data
transmission/reception?
No
Yes [5]
Read the TEND bit in SSSR
TEND = 1?
No
Yes
Clear TEND in SSSR to 0
One-bit interval elapsed?
Yes
No
Error processing
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 18.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode)
Page 934 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.5
Section 18 Synchronous Serial Communication Unit (SSU)
SSU Interrupt Sources and DTC or DMAC
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, and a transmit data register empty can activate the DTC or DMAC for data
transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 18.8 lists the
interrupt sources.
When an interrupt condition shown in table 18.8 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU, DTC, or DMAC data transfer.
Table 18.8 SSU Interrupt Sources
DTC or DMAC
Activation
Abbreviation
Interrupt Source
Symbol Interrupt Condition
SSERI
Overrun error
SSOEI
(RIE = 1) • (ORER = 1) ⎯
Conflict error
SSCEI
(CEIE = 1) • (CE = 1)
SSRXI
Receive data register full
SSRXI
(RIE = 1) • (RDRF = 1) Yes
SSTXI
Transmit data register empty SSTXI
(TIE = 1) • (TDRE = 1)
Transmit end
(TEIE = 1) • (TEND = 1) ⎯
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SSTEI
⎯
Yes
Page 935 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
18.6
Usage Notes
18.6.1
Module Standby Mode Setting
SH7280 Group, SH7243 Group
The SSU operation can be disabled or enabled using the standby control register. The initial
setting is for SSU operation to be halted. Access to registers is enabled by clearing module
standby mode. For details, refer to section 28, Power-Down Modes.
18.6.2
Access to SSTDR and SSRDR Registers
Do not access SSTDR and SSRDR registers not validated by the setting of the DATS bits of the
SSCRL register. If accessed, transmission or reception thereafter may not be performed normally.
18.6.3
Continuous Transmission/Reception in SSU Slave Mode
During continuous transmission/reception in SSU slave mode, negate the SCS pin (high level) for
every frame. If the SCS pin is kept asserted (low level) for more than one frame, transmission or
reception cannot be performed correctly.
18.6.4
Note for Reception Operations in SSU Slave Mode
In continuous reception when slave reception in SSU mode has been selected, read the SS receivedata register (SSRDR) before each next round of reception starts (i.e. before an externally
connected master device starts a next round of transmission).
If the next round of reception starts after the SS status register receive-data full (RDRF) bit has
been set to 1 but before the SSRDR has been read, and the SSRDR is read before the reception of
one frame is complete, the conflict /incomplete error bit in SSSR will be set to 1 on completion of
reception.
Furthermore, when the next round of reception starts after the receive-data full (RDRF) bit has
been set to 1 and before the SSRDR has been read, and the SSRDR has not been read by the end
of the reception of the frame, the CE and overflow-error (ORER) bits will not have been set, but
the received data will be discarded.
Further note that this point for caution does not apply to simultaneous transmission and reception
in SSU slave mode or to clock-synchronous mode.
Page 936 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
18.6.5
Section 18 Synchronous Serial Communication Unit (SSU)
Note on Master Transmission and Master Reception Operations in SSU Mode
To perform master transmission or reception in SSU mode, perform one of the following
operations:
• After the TDRE flag in SSSR is set to 1, store the next byte of transmit data in SSTDR before
transmission of the second to last bit starts.
• Store the next byte of transmit data in SSTDR after confirming that the TEND flag in SSSR
has been set to 1.
• Use the SSU with the TENDSTS bit in SSCR2 cleared to 0, or with both the TENDSTS and
SCSATS bits in SSCR2 set to 1.
18.6.6
Note on DTC Transfers
When a DTC transfer occurs with SSTXI as the activation source, TDRE is not cleared when the
transfer counter reaches H'0000 but communication operation starts anyway.
When using the SSTXI interrupt to clear the flag, perform interrupt handling first.
However, do not clear the flag within the SSTXI interrupt handler when the initial value of the
DTC’s transfer counter is set to H'0001 and the DISEL bit is set to 1. In this case, clearing the flag
by the interrupt handler may cause the SSU to start communication operation a second time.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 937 of 1778
Section 18 Synchronous Serial Communication Unit (SSU)
Page 938 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 19 I2C Bus Interface 3 (IIC3)
Section 19 I2C Bus Interface 3 (IIC3)
The I2C bus interface 3 conforms to and provides a subset of the Philips I2C (Inter-IC) bus
interface functions. However, the configuration of the registers that control the I2C bus differs
partly from the Philips register configuration.
19.1
Features
• Selection of I2C format or clocked synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
I2C bus format:
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• The direct memory access controller (DMAC) or data transfer controller (DTC) can be
activated by a transmit-data-empty request or receive-data-full request to transfer data.
• Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clocked synchronous serial format:
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
• The direct memory access controller (DMAC)) or data transfer controller (DTC) can be
activated by a transmit-data-empty request or receive-data-full request to transfer data.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 939 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Figure 19.1 shows a block diagram of the I2C bus interface 3.
Transfer clock
generation
circuit
Transmission/
reception
control circuit
Output
control
SCL
ICCR1
ICCR2
ICMR
Noise filter
Output
control
SDA
ICDRS
Peripheral bus
ICDRT
SAR
Address
comparator
Noise canceler
ICDRR
NF2CYC
Bus state
decision circuit
Arbitration
decision circuit
[Legend]
ICCR1:
ICCR2:
ICMR:
ICSR:
ICIER:
ICDRT:
ICDRR:
ICDRS:
SAR:
NF2CYC:
ICSR
ICIER
I2C bus control register 1
I2C bus control register 2
I2C bus mode register
I2C bus status register
I2C bus interrupt enable register
I2C bus transmit data register
I2C bus receive data register
I2C bus shift register
Slave address register
NF2CYC register
Interrupt
generator
Interrupt
request
Figure 19.1 Block Diagram of I2C Bus Interface 3
Page 940 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
19.2
Input/Output Pins
Table 19.1 shows the pin configuration of the I2C bus interface 3.
Table 19.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Serial clock
SCL
I/O
I2C serial clock input/output
Serial data
SDA
I/O
I2C serial data input/output
Figure 19.2 shows an example of I/O pin connections to external circuits.
Vcc*
SCL in
Vcc*
SCL
SCL
SDA
SDA
SCL out
SDA in
SCL in
SCL
SDA
(Master)
SCL
SDA
SDA out
SCL in
SCL out
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
(Slave 2)
Note: * Turn on/off Vcc for the I2C bus power supply and for this LSI simultaneously.
Figure 19.2 External Circuit Connections of I/O Pins
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 941 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.3
SH7280 Group, SH7243 Group
Register Descriptions
The I2C bus interface 3 has the following registers.
Table 19.2 Register Configuration
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
I2C bus control register 1
ICCR1
R/W
H'00
H'FFFEE000
8
ICCR2
R/W
H'7D
H'FFFEE001
8
2
I C bus control register 2
2
I C bus mode register
ICMR
R/W
H'38
H'FFFEE002
8
I2C bus interrupt enable register
ICIER
R/W
H'00
H'FFFEE003
8
I2C bus status register
ICSR
R/W
H'00
H'FFFEE004
8
Slave address register
SAR
R/W
H'00
H'FFFEE005
8
2
ICDRT
R/W
H'FF
H'FFFEE006
8
2
I C bus receive data register
ICDRR
R/W
H'FF
H'FFFEE007
8
NF2CYC register
NF2CYC
R/W
H'00
H'FFFEE008
8
I C bus transmit data register
Page 942 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
19.3.1
I2C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I2C bus interface 3,
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
ICCR1 is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
ICE
RCVD
MST
TRS
0
R/W
0
R/W
0
R/W
0
R/W
3
2
1
0
CKS[3:0]
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
ICE
0
R/W
I C Bus Interface 3 Enable
0
R/W
2
0: Output from SCL and SDA is disabled. (Input to SCL
and SDA enabled.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W
Reception Disable
Enables or disables the next operation when TRS is 0
and ICDRR is read. In master receive mode, when
ICDRR cannot be read before the rising edge of the
8th clock of SCL, set the RCVD bit to 1 so that data is
received in byte units. Clear this bit to 0 in other
modes.
When receiving data in byte units with the RCVD bit
set to 1, read from ICDRR after the fall of the ninth
clock.
0: Enables next reception
1: Disables next reception
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 943 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
5
MST
0
R/W
Master/Slave Select
4
TRS
0
R/W
Transmit/Receive Select
2
In master mode with the I C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the 8th bit is set to 1, TRS is automatically
set to 1. If an overrun error occurs in master receive
mode with the clocked synchronous serial format, MST
is cleared and the mode changes to slave receive
mode.
Operating modes are described below according to
MST and TRS combination. When clocked
synchronous serial format is selected and MST = 1,
clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3 to 0
CKS[3:0]
0000
R/W
Transfer Clock Select
These bits should be set according to the necessary
transfer rate (table 19.3) in master mode.
Page 944 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Table 19.3 Transfer Rate
Bit 3
Bit 2
Bit 1
Bit 0
Transfer Rate
CKS3
CKS2
CKS1
CKS0
Clock
Pφ = 40 MHz
(160/8)
Pφ = 48 MHz
(160/6)
Pφ = 50 MHz
(160/4)
0
0
0
0
Pφ/64
625
750
781
0
0
0
1
Pφ/72
556
667
694
0
0
1
0
Pφ/84
476
571
595
0
0
1
1
Pφ/92
435
521
543
0
1
0
0
Pφ/100
400
480
500
0
1
0
1
Pφ/108
370
444
463
0
1
1
0
Pφ/120
333
400
417
0
1
1
1
Pφ/124
322
387
403
1
0
0
0
Pφ/256
156
188
195
1
0
0
1
Pφ/288
139
167
174
1
0
1
0
Pφ/336
119
143
149
1
0
1
1
Pφ/368
109
130
136
1
1
0
0
Pφ/400
100
120
125
1
1
0
1
Pφ/432
92.6
111
116
1
1
1
0
Pφ/480
83.3
100
104
1
1
1
1
Pφ/496
80.6
96.7
101
Note: The settings should satisfy external specifications.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 945 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.3.2
SH7280 Group, SH7243 Group
I2C Bus Control Register 2 (ICCR2)
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I2C bus.
ICCR2 is initialized to H'7D by a power-on reset.
Bit:
Initial value:
R/W:
7
6
2
1
0
BBSY
SCP
SDAO SDAOP SCLO
5
4
-
IICRST
-
0
R/W
1
R/W
1
R/W
1
R
0
R/W
1
R
1
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
BBSY
0
R/W
Bus Busy
3
1
R
2
Enables to confirm whether the I C bus is occupied or
released and to issue start/stop conditions in master
mode. With the clocked synchronous serial format, this
2
bit is always read as 0. With the I C bus format, this bit
is set to 1 when the SDA level changes from high to low
under the condition of SCL = high, assuming that the
start condition has been issued. This bit is cleared to 0
when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop
condition has been issued. Write 1 to BBSY and 0 to
SCP to issue a start condition. Follow this procedure
when also re-transmitting a start condition. Write 0 in
BBSY and 0 in SCP to issue a stop condition.
6
SCP
1
R/W
Start/Stop Issue Condition Disable
Controls the issue of start/stop conditions in master
mode. To issue a start condition, write 1 in BBSY and 0
in SCP. A retransmit start condition is issued in the
same way. To issue a stop condition, write 0 in BBSY
and 0 in SCP. This bit is always read as 1. Even if 1 is
written to this bit, the data will not be stored.
Page 946 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
5
SDAO
1
R/W
SDA Output Value Control
This bit is used with SDAOP when modifying output
level of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
4
SDAOP
1
R/W
SDAO Write Protect
Controls change of output level of the SDA pin by
modifying the SDAO bit. To change the output level,
clear SDAO and SDAOP to 0 or set SDAO to 1 and
clear SDAOP to 0. This bit is always read as 1.
3
SCLO
1
R
SCL Output Level
Monitors SCL output level. When SCLO is 1, SCL pin
outputs high. When SCLO is 0, SCL pin outputs low.
2
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
1
IICRST
0
R/W
IIC Control Part Reset
2
Resets the control part except for I C registers. If this bit
is set to 1 when hang-up occurs because of
communication failure during I2C bus operation, some
IIC3 registers and the control part can be reset.
0
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 947 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.3.3
SH7280 Group, SH7243 Group
I2C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, and selects the transfer bit count.
ICMR is initialized to H'38 by a power-on reset. Bits BC[2:0] are initialized to H'0 by the IICRST
bit in ICCR2.
Bit:
Initial value:
R/W:
7
6
5
4
3
MLS
-
-
-
BCWP
0
R/W
0
R/W
1
R
1
R
1
R/W
2
1
0
BC[2:0]
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
MSB-First/LSB-First Select
0
R/W
0: MSB-first
1: LSB-first
2
Set this bit to 0 when the I C bus format is used.
6
⎯
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
5, 4
⎯
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
3
BCWP
1
R/W
BC Write Protect
Controls the BC[2:0] modifications. When modifying the
BC[2:0] bits, this bit should be cleared to 0. In clocked
synchronous serial mode, the BC[2:0] bits should not
be modified.
0: When writing, values of the BC[2:0] bits are set.
1: When reading, 1 is always read.
When writing, settings of the BC[2:0] bits are invalid.
Page 948 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
BC[2:0]
000
R/W
Bit Counter
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
2
is indicated. With the I C bus format, the data is
transferred with one addition acknowledge bit. Should
be made between transfer frames. If these bits are set
to a value other than B'000, the setting should be made
while the SCL pin is low. After the stop condition is
detected, the value of these bits returns automatically to
B'111. The value returns to B'000 at the end of a data
transfer, including the acknowledge bit. These bits are
cleared by a power-on reset and in software standby
mode and module standby mode. These bits are also
cleared by setting the IICRST bit of ICCR2 to 1. With
the clocked synchronous serial format, these bits
should not be modified.
2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
I C Bus Format
Clocked Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bit
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
Page 949 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.3.4
SH7280 Group, SH7243 Group
I2C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received.
ICIER is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
TIE
TEIE
RIE
NAKIE
STIE
ACKE ACKBR ACKBT
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
0
0
R/W
When the TDRE bit in ICSR is set to 1 or 0, this bit
enables or disables the transmit data empty interrupt
(TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6
TEIE
0
R/W
Transmit End Interrupt Enable
Enables or disables the transmit end interrupt (TEI) at
the rise of the ninth clock while the TDRE bit in ICSR is
1. TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5
RIE
0
R/W
Receive Interrupt Enable
Enables or disables the receive data full interrupt
request (RXI) when receive data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
RXI can be canceled by clearing the RDRF or RIE bit to
0.
0: Receive data full interrupt request (RXI) are disabled.
1: Receive data full interrupt request (RXI) are enabled.
Page 950 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
4
NAKIE
0
R/W
NACK Receive Interrupt Enable
Enables or disables the NACK detection and arbitration
lost/overrun error interrupt request (NAKI) when the
NACKF or AL/OVE bit in ICSR is set. NAKI can be
canceled by clearing the NACKF, AL/OVE, or NAKIE bit
to 0.
0: Disables the NACK detection and arbitration
lost/overrun error interrupt request (NAKI).
1: Enables the NACK detection and arbitration
lost/overrun error interrupt request (NAKI).
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable
Enables or disables the stop condition detection
interrupt request (STPI) when the STOP bit in ICSR is
set.
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous
transfer is halted.
1
ACKBR
0
R
Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot
be modified. This bit can be canceled by setting the
BBSY bit in ICCR2 to 1.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at
the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 951 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.3.5
SH7280 Group, SH7243 Group
I2C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
ICSR is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
1
0
TDRE
TEND
RDRF NACKF STOP AL/OVE
5
4
AAS
ADZ
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
3
0
R/W
2
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
TDRE
0
R/W
Transmit Data Register Empty
[Clearing conditions]
•
When 0 is written in TDRE after reading TDRE = 1
•
When data is written to ICDRT
[Setting conditions]
6
TEND
0
R/W
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
•
When TRS is set
•
When the start condition (including retransmission)
is issued
•
When slave mode is changed from receive mode to
transmit mode
Transmit End
[Clearing conditions]
•
When 0 is written in TEND after reading TEND = 1
•
When data is written to ICDRT
[Setting conditions]
Page 952 of 1778
•
When the ninth clock of SCL rises with the I C bus
format while the TDRE flag is 1
•
When the final bit of transmit frame is sent with the
clocked synchronous serial format
2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
5
RDRF
0
R/W
Receive Data Full
[Clearing conditions]
•
When 0 is written in RDRF after reading RDRF = 1
•
When ICDRR is read
[Setting condition]
•
4
NACKF
0
R/W
When a receive data is transferred from ICDRS to
ICDRR
No Acknowledge Detection Flag
[Clearing condition]
•
When 0 is written in NACKF after reading NACKF
=1
[Setting condition]
•
3
STOP
0
R/W
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
Stop Condition Detection Flag
[Clearing condition]
•
When 0 is written in STOP after reading STOP = 1
[Setting conditions]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
•
In master mode, when a stop condition is detected
after frame transfer
•
In slave mode, when the slave address in the first
byte after the general call and detecting start
condition matches the address set in SAR, and then
the stop condition is detected
Page 953 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Bit
Bit Name
Initial
Value
R/W
Description
2
AL/OVE
0
R/W
Arbitration Lost Flag/Overrun Error Flag
Indicates that arbitration was lost in master mode with
2
the I C bus format and that the final bit has been
received while RDRF = 1 with the clocked synchronous
format.
When two or more master devices attempt to seize the
2
bus at nearly the same time, if the I C bus interface 3
detects data differing from the data it sent, it sets AL to
1 to indicate that the bus has been occupied by another
master.
[Clearing condition]
•
When 0 is written in AL/OVE after reading AL/OVE
=1
[Setting conditions]
1
AAS
0
R/W
•
If the internal SDA and SDA pin disagree at the rise
of SCL in master transmit mode
•
When the SDA pin outputs high in master mode
while a start condition is detected
•
When the final bit is received with the clocked
synchronous format while RDRF = 1
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA[6:0]
in SAR.
[Clearing condition]
•
When 0 is written in AAS after reading AAS = 1
[Setting conditions]
0
ADZ
0
R/W
•
When the slave address is detected in slave receive
mode
•
When the general call address is detected in slave
receive mode.
General Call Address Recognition Flag
2
This bit is valid in slave receive mode with the I C bus
format.
[Clearing condition]
•
When 0 is written in ADZ after reading ADZ = 1
[Setting condition]
•
Page 954 of 1778
When the general call address is detected in slave
receive mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
19.3.6
Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I2C bus format, if the upper seven bits of SAR match the
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
SAR is initialized to H'00 by a power-on reset.
7
Bit:
6
5
4
3
2
1
SVA[6:0]
Initial value:
R/W:
0
R/W
0
R/W
0
R/W
0
R/W
0
FS
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1
SVA[6:0]
0000000
R/W
Slave Address
0
R/W
0
R/W
0
R/W
These bits set a unique address in these bits,
differing form the addresses of other slave devices
2
connected to the I C bus.
0
FS
0
R/W
Format Select
2
0: I C bus format is selected
1: Clocked synchronous serial format is selected
19.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. ICDRT is initialized to H'FF.
Bit:
Initial value:
R/W:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Page 955 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.3.8
SH7280 Group, SH7243 Group
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register.
ICDRR is initialized to H'FF by a power-on reset.
Bit:
Initial value:
R/W:
19.3.9
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
Page 956 of 1778
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
-
-
-
-
-
-
-
-
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
19.3.10 NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects the range of the noise filtering for the
SCL and SDA pins. For details of the noise filter, see section 19.4.7, Noise Filter.
NF2CYC is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
NF2
CYC
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
NF2CYC
0
R/W
Noise Filtering Range Select
0: The noise less than one cycle of the peripheral clock
can be filtered out
1: The noise less than two cycles of the peripheral clock
can be filtered out
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 957 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.4
SH7280 Group, SH7243 Group
Operation
The I2C bus interface 3 can communicate either in I2C bus mode or clocked synchronous serial
mode by setting FS in SAR.
I2C Bus Format
19.4.1
Figure 19.3 shows the I2C bus formats. Figure 19.4 shows the I2C bus timing. The first frame
following a start condition always consists of eight bits.
(a) I2C bus format (FS = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
m
(b) I2C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
1
7
1
1
n1
1
1
7
1
1
n2
1
m1
1
A/A
P
1
1
m2
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 19.3 I2C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
DATA
8
9
A
1-7
8
DATA
9
A
P
Figure 19.4 I2C Bus Timing
[Legend]
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.
Page 958 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
19.4.2
Section 19 I2C Bus Interface 3 (IIC3)
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 19.5 and 19.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Also, set ICMR and bits CKS[3:0] in ICCR1. (Initial setting)
2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition
issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or
the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to slave receive mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 959 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SCL
(Master output)
1
SDA
(Master output)
SH7280 Group, SH7243 Group
2
Bit 7
Bit 6
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
2
Bit 7
Bit 6
R/W
Slave address
SDA
(Slave output)
A
TDRE
TEND
ICDRT
Address + R/W
ICDRS
Data 1
Address + R/W
User [2] Instruction of start
processing condition issuance
Data 2
Data 1
[4] Write data to ICDRT (second byte)
[5] Write data to ICDRT (third byte)
[3] Write data to ICDRT (first byte)
Figure 19.5 Master Transmit Mode Operation Timing (1)
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
1
Bit 7
2
Bit 6
3
4
5
6
7
8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A
9
A/A
TDRE
TEND
Data n
ICDRT
ICDRS
Data n
User
[5] Write data to ICDRT
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 19.6 Master Transmit Mode Operation Timing (2)
Page 960 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
19.4.3
Section 19 I2C Bus Interface 3 (IIC3)
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 19.7 and 19.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at the rise of the 9th receive clock pulse, issue the stage
condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to slave receive mode.
Note: If only one byte is received, read ICDRR (dummy-read) after the RCVD bit in ICCR1 is
set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 961 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Master transmit mode
SCL
(Master output)
Master receive mode
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
1
A
SDA
(Slave output)
Bit 7
A
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
Data 1
ICDRS
Data 1
ICDRR
[3] Read ICDRR
User
processing
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
Figure 19.7 Master Receive Mode Operation Timing (1)
SCL
(Master output)
9
SDA
(Master output)
A
SDA
(Slave output)
1
2
3
4
5
6
7
8
9
A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS
Data n
Data n-1
ICDRR
User
processing
Data n-1
[5] Read ICDRR after setting RCVD
Data n
[6] Issue stop
condition
[7] Read ICDRR,
and clear RCVD
[8] Set slave
receive mode
Figure 19.8 Master Receive Mode Operation Timing (2)
Page 962 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
19.4.4
Section 19 I2C Bus Interface 3 (IIC3)
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 19.9 and 19.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and
TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit
in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The
continuous transmission is performed by writing transmit data to ICDRT every time TDRE is
set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened.
5. Clear TDRE.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 963 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Slave transmit
mode
Slave receive
mode
SCL
(Master output)
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
1
A
SCL
(Slave output)
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
ICDRT
Data 1
ICDRS
Data 2
Data 1
Data 3
Data 2
ICDRR
User
processing
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 19.9 Slave Transmit Mode Operation Timing (1)
Page 964 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Slave transmit mode
SCL
(Master output)
9
SDA
(Master output)
A
1
2
3
4
5
6
7
8
Slave receive
mode
9
A
SCL
(Slave output)
SDA
(Slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User
processing
[3] Clear TEND
[4] Read ICDRR (dummy read)
after clearing TRS
[5] Clear TDRE
Figure 19.10 Slave Transmit Mode Operation Timing (2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 965 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.4.5
SH7280 Group, SH7243 Group
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 19.11 and 19.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and
TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
Bit 7
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[2] Read ICDRR
[2] Read ICDRR (dummy read)
Figure 19.11 Slave Receive Mode Operation Timing (1)
Page 966 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 2
Data 1
ICDRR
Data 1
User
processing
[3] Set ACKBT
[3] Read ICDRR
[4] Read ICDRR
Figure 19.12 Slave Receive Mode Operation Timing (2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 967 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.4.6
SH7280 Group, SH7243 Group
Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
(1)
Data Transfer Format
Figure 19.13 shows the clocked synchronous serial transfer format.
The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6
Bit 7
Figure 19.13 Clocked Synchronous Serial Transfer Format
(2)
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 19.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting)
2. Set the TRS bit in ICCR1 to select transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
Page 968 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
SCL
1
2
7
8
1
7
8
1
SDA
(Output)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
TRS
TDRE
Data 1
ICDRT
Data 2
Data 1
ICDRS
User
processing
[3] Write data [3] Write data
to ICDRT
to ICDRT
[2] Set TRS
Data 3
Data 2
[3] Write data
to ICDRT
[3] Write data
to ICDRT
Figure 19.14 Transmit Mode Operation Timing
(3)
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 19.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock rises while RDRF is 1, the overrun is detected and AL/OVE
in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
fixed high after receiving the next byte data.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 969 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Notes: Follow the steps below to receive only one byte with MST = 1 specified. See figure 19.16
for the operation timing.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting)
2. Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be
output.
3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1.
This causes the SCL to be fixed to the high level after outputting one byte of the
receive clock.
SCL
1
2
7
8
1
7
8
1
2
SDA
(Input)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
Bit 1
MST
TRS
RDRF
Data 1
ICDRS
Data 1
ICDRR
User
processing
Data 2
[2] Set MST
(when outputting the clock)
[3] Read ICDRR
Data 3
Data 2
[3] Read ICDRR
Figure 19.15 Receive Mode Operation Timing
Page 970 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
SCL
1
2
3
4
5
6
7
8
SDA
(Input)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
001
000
MST
RCVD
BC2 to BC0
000
[2] Set MST
111
110
101
100
011
010
[3] Set the RCVD bit after checking if BC2 = 1
Figure 19.16 Operation Timing For Receiving One Byte (MST = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 971 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.4.7
SH7280 Group, SH7243 Group
Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 19.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
Sampling clock
SCL or SDA
input signal
C
C
Q
D
D
Latch
Latch
C
Q
D
Q
Latch
Match
detector
1
Match
detector
0
Internal
SCL or SDA
signal
NF2CYC
Peripheral clock
cycle
Sampling
clock
Figure 19.17 Block Diagram of Noise Filter
Page 972 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Using the IICRST Bit to Reset I2C Bus Interface 3
19.4.8
Some registers and the control part for I2C of the I2C bus interface 3 can be reset by writing 1 to
the IICRST bit in ICCR2. Figure 19.18 shows an example of the sequence for resetting the I2C bus
interface 3 by using the IICRST bit.
Reset start
No
(1) Write 0 to the ICE bit in ICCR1 to halt functioning
of the I2C bus interface 3.
Halt the I2C function (ICE in ICCR1 = 0)
(1)
(2) Write 1 to the IICRST bit in ICCR2 to reset some
registers and the contol part of the I2C bus interface
3 module. The BBSY flag in ICCR2 becomes undefined.
Reset the I2C module (IICRST in ICCR2 = 1)
(2)
(3) Write 0 to the MST and TRS bits in ICCR1 to switch
the operating mode to slave receiver mode.
Slave receiver mode
(MST and TRS in ICCR1 = 0)
(3)
(4) Wait until the bus is released. Determine whether
the bus is released by reading the I/O port bits
(the PB2PR and PB3PR bits in PBPRL) corresponding
to SCL and SDA.
Are SCL and SDA at the high level?
(PB2PR = 1 and PB3PR = 1?)
(5) Write 1 to the FS bit in SAR and clear the BBSY flag
in ICCR2 to 0. After the BBSY flag has been cleared
to 0, write 0 to the FS bit.
(4)
(7) Write 0 to the IICRST bit to release the I2C module
from the reset state.
Yes
Clear the BBSY flag in ICCR2 to 0
(FS in SAR = 1)
(6) Clear the flags (TEND, RDRF, NACKF, STOP, AL/OVE,
AAS, and ADS) in ICSR to 0.
(5)
(8) Initialize I2C registers (ICCR1, ICCR2, ICMR, ICIER,
SAR, and NF2CYC).
(9) Write 1 to the ICE bit in ICCR1 to enable transfer
operations.
FS in SAR = 0
Clear the flags in ICCR
(6)
Cancel the I2C reset
(IICRST in ICCR2 = 0)
(7)
Initial settings
(8)
Enable I2C operation (ICE in ICCR1 = 1)
(9)
Reset end
Figure 19.18 Sequence for Using the IICRST Bit to Reset I2C Bus Interface 3
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 973 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.4.9
SH7280 Group, SH7243 Group
Example of Use
Flowcharts in respective modes that use the I2C bus interface 3 are shown in figures 19.19 to
19.22.
Start
Initialize
Read BBSY in ICCR2
[1]
No
BBSY=0 ?
Yes
Set MST and TRS
in ICCR1 to 1
[1]
Test the status of the SCL and SDA lines.
[2]
Set master transmit mode.
[3]
Issue the start condition.
[4]
Set the first byte (slave address + R/W) of transmit data.
[5]
Wait for 1 byte to be transmitted.
[6]
Test the acknowledge transferred from the specified slave device.
[7]
Set the second and subsequent bytes (except for the final byte) of transmit data.
[8]
Wait for ICDRT empty.
[9]
Set the last byte of transmit data.
[2]
Write 1 to BBSY
and 0 to SCP
[3]
Write transmit data
in ICDRT
[4]
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Read ACKBR in ICIER
ACKBR=0 ?
No
[6]
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
Yes
Transmit
mode?
Yes
No
Write transmit data in ICDRT
Master receive mode
[7]
[13] Issue the stop condition.
Read TDRE in ICSR
No
[8]
[14] Wait for the creation of stop condition.
TDRE=1 ?
Yes
No
[12] Clear the STOP flag.
[15] Set slave receive mode. Clear TDRE.
Last byte?
Yes
Write transmit data in ICDRT
[9]
Read TEND in ICSR
No
[10]
TEND=1 ?
Yes
Clear TEND in ICSR
[11]
Clear STOP in ICSR
[12]
Write 0 to BBSY
and SCP
[13]
Read STOP in ICSR
No
STOP=1 ?
Yes
Set MST and TRS
in ICCR1 to 0
[14]
[15]
Clear TDRE in ICSR
End
Figure 19.19 Sample Flowchart for Master Transmit Mode
Page 974 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Master receive mode
[1]
Clear TEND, select master receive mode, and then clear TDRE.*1
[2]
Set acknowledge to the transmit device.*1
[3]
Dummy-read ICDDR.*1*2
[4]
Wait for 1 byte to be received
[5]
Check whether it is the (last receive - 1).
[6]
Read the receive data.
[7]
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[8]
Read the (final byte - 1) of received data.
[9]
Wait for the last byte to be receive.
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
[1]
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
Read RDRF in ICSR
No
[4]
RDRF=1 ?
Yes
Last receive
- 1?
No
Read ICDRR
Yes
[5]
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
Set ACKBT in ICIER to 1
[7]
Set RCVD in ICCR1 to 1
Read ICDRR
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
[9]
Notes: 1. Make sure that no interrupt will be generated during steps [1] to [3].
2. If the RCVD bit is to be set to 1 for enabling data reception in byte units,
set it before performing the dummy read from ICDRR.
Read RDRF in ICSR
No
RDRF=1 ?
[13] Read the last byte of receive data.
Yes
Clear STOP in ICSR
[10]
Write 0 to BBSY
and SCP
[11]
When the size of receive data is only one byte in reception,
steps [2] to [6] are skipped after step [1], before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Read STOP in ICSR
No
[12]
STOP=1 ?
Yes
Read ICDRR
[13]
Clear RCVD in ICCR1 to 0
[14]
Clear MST in ICCR1 to 0
[15]
End
Figure 19.20 Sample Flowchart for Master Receive Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 975 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
[1] Clear the AAS flag.
Slave transmit mode
Clear AAS in ICSR
[1]
Write transmit data
in ICDRT
[2]
[3] Wait for ICDRT empty.
[4] Set the last byte of transmit data.
Read TDRE in ICSR
[5] Wait for the last byte to be transmitted.
[3]
No
TDRE=1 ?
Yes
Yes
[6] Clear the TEND flag.
[7] Set slave receive mode.
Last
byte?
No
[2] Set transmit data for ICDRT (except for the last byte).
[8] Dummy-read ICDRR to release the SCL.
[4]
[9] Clear the TDRE flag.
Write transmit data
in ICDRT
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Clear TEND in ICSR
[6]
Clear TRS in ICCR1 to 0
[7]
Dummy-read ICDRR
[8]
Clear TDRE in ICSR
[9]
End
Figure 19.21 Sample Flowchart for Slave Transmit Mode
Page 976 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR
[1]
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
[2] Set acknowledge to the transmit device.
[3] Dummy-read ICDRR.
[5] Check whether it is the (last receive - 1).
Read RDRF in ICSR
No
[4]
RDRF=1 ?
[6] Read the receive data.
[7] Set acknowledge of the last byte.
Yes
Last receive
- 1?
[4] Wait for 1 byte to be received.
Yes
No
Read ICDRR
[5]
[8] Read the (last byte - 1) of receive data.
[9] Wait the last byte to be received.
[6]
[10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR
[8]
Note: When the size of receive data is only one byte in
reception, steps [2] to [6] are skipped after
step [1], before jumping to step [7]. The step [8]
is dummy-read in ICDRR.
Read RDRF in ICSR
No
[9]
RDRF=1 ?
Yes
Read ICDRR
[10]
End
Figure 19.22 Sample Flowchart for Slave Receive Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 977 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.5
SH7280 Group, SH7243 Group
Interrupt Requests
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost/overrun error. Table 19.4 shows the
contents of each interrupt request.
Table 19.4 Interrupt Requests
2
Interrupt Request
Abbreviation
Interrupt Condition
I C Bus
Format
Clocked Synchronous
Serial Format
Transmit data Empty
TXI
(TDRE = 1) • (TIE = 1)
√
√
Transmit end
TEI
(TEND = 1) • (TEIE = 1)
√
√
Receive data full
RXI
(RDRF = 1) • (RIE = 1)
√
√
STOP recognition
STPI
(STOP = 1) • (STIE = 1)
√
⎯
NACK detection
NAKI
{(NACKF = 1) + (AL = 1)} •
(NAKIE = 1)
√
⎯
√
√
Arbitration lost/
overrun error
When the interrupt condition described in table 19.4 is 1, the CPU executes an interrupt exception
handling. Note that a TXI or RXI interrupt can activate the DMAC or DTC if the setting for
DMAC or DTC activation has been made. In such a case, an interrupt request is not sent to the
CPU. In cases other than data transfer by the DMAC or DTC, interrupt sources should be cleared
in the exception handling. The TDRE and TEND bits are automatically cleared to 0 by writing the
transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by reading ICDRR. The
TDRE bit is set to 1 again at the same time when the transmit data is written to ICDRT. Therefore,
when the TDRE bit is cleared to 0, then an excessive data of one byte may be transmitted.
Page 978 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
19.6
Data Transfer Using DTC
In the I2C bus format, the slave device and transfer direction are selected through the slave address
and R/W bit, and data reception is confirmed and the last frame is indicated through the
acknowledge bit. Therefore, when the DTC is used to transfer data continuously, the DTC
processing should be done in combination with the CPU processing activated by interrupts.
Table 19.5 shows an example of I2C data transfer using the DTC. This example assumes that the
transfer data count is determined in advance in slave mode.
Table 19.5 Example of Data Transfer Using DTC
Item
Master Transmit
Mode
Master Receive
Mode
Slave Transmit
Mode
Slave address + R/W Transmitted by DTC Transmitted by CPU Received by CPU
bit transmit/receive
(ICDR writing)
(ICDR writing)
(ICDR reading)
Dummy data read
⎯
Processed by CPU
⎯
Slave Receive
Mode
Received by CPU
(ICDR reading)
⎯
(ICDR writing)
Main data
transmit/receive
Transmitted by DTC Received by DTC
Transmitted by DTC Received by DTC
(ICDR writing)
(ICDR reading)
(ICDR writing)
(ICDR reading)
Last frame
processing
Not necessary
Received by CPU
Not necessary
Received by CPU
DTC transfer data
frame count setting
Transmission: Actual Reception; Actual
data count
data count + 1
(+1 is required for
the slave address +
R/W bit transfer)
(ICDR reading)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
(ICDR reading)
Transmission; Actual Reception; Actual
data count
data count
Page 979 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.7
SH7280 Group, SH7243 Group
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 19.23 shows the timing of the bit synchronous circuit and table 19.6 shows the time when
the SCL output changes from low to Hi-Z then SCL is monitored.
Page 980 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
(a) SCL is normally driven
1
Synchronous clock *
VIH
SCL pin
*2
Internal
delay
Internal SCL
The monitor value is
high level.
Time for
monitoring SCL
(b) When SCL is driven to low by the slave device
Synchronous clock *1
SCL is driven to low by
the slave device.
VIH
VIH
SCL pin
SCL is not driven to low.
Internal SCL
2
Internal *
delay
The monitor value
is low level.
Time for
monitoring SCL
The monitor value
is high level.
Time for
monitoring SCL
Internal
delay
*2
The monitor value
is high level.
Time for
monitoring SCL
(c) When the rising speed of SCL is lowered
1
Synchronous clock *
The frequency is not
the setting frequency.
VIH
SCL pin
SCL is not driven to low.
2
Internal *
delay
Internal SCL
The monitor value is low level.
SCL
Notes: 1. The clock is the transfer rate clock set by the CKS[3:0] bit in I2C Bus Control Register 1 (ICCR1).
2. When the NF2CYC bit in NF2CYC Register (NF2CYC) is set to 0, the internal delay time is 3 to 4 tpcyc.
When this bit is set to 1, the internal delay time is 4 to 5 tpcyc.
Figure 19.23 Bit Synchronous Circuit Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 981 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
SH7280 Group, SH7243 Group
Table 19.6 Time for Monitoring SCL
CKS[3]
CKS[2]
Time for Monitoring SCL
0
0
9 tpcyc*
1
21 tpcyc*
0
39 tpcyc*
1
87 tpcyc*
1
Note:
*
tpcyc indicates peripheral clock (Pφ) cycle.
Page 982 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
19.8
Usage Notes
19.8.1
Setting for Multi-Master Operation
Section 19 I2C Bus Interface 3 (IIC3)
In multi-master operation, when the setting for IIC transfer rate (ICCR1.CKS[3:0]) makes this LSI
slower than the other masters, pulse cycles with an unexpected length will infrequently be output
on SCL.
Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other
masters.
19.8.2
Note on Master Receive Mode
Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data.
In addition, when the RCVD bit is set to 1 around the falling edge of the 8th clock and the receive
buffer is full, a stop condition may not be issued.
Use the following measure against the situations above.
• In master receive mode, read ICDRR before the rising edge of the 8th clock.
19.8.3
Note on Setting ACKBT in Master Receive Mode
In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the
last data being continuously transferred. Not doing so can lead to an overrun for the slave
transmission device.
19.8.4
Note on the States of Bits MST and TRN when Arbitration Is Lost
When sequential bit-manipulation instructions are used to set the MST and TRS bits to select
master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but
the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing
of the loss of arbitration when the bit manipulation instruction for TRS is executed.
This can be avoided in either of the following ways.
• In multi-master operation, use the MOV instruction to set the MST and TRS bits.
• When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits
have been set to a value other than 0, clear the bits to 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 983 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
19.8.5
SH7280 Group, SH7243 Group
Access to ICE and IICRST Bits during I2C Bus Operations
Writing 0 to the ICE bit in ICCR1 or 1 to the IICRST bit in ICCR2 while this LSI is in any of the
following states (1 to 4) causes the BBSY flag in ICCR2 and the STOP flag in ICSR to become
undefined.
1.
2.
3.
4.
This module is the I2C bus master in master transmit mode (MST = 1 and TRS = 1 in ICCR1).
This module is the I2C bus master in master receive mode (MST = 1 and TRS = 0 in ICCR1).
This module is transmitting data in slave transmit mode (MST = 0 and TRS = 1 in ICCR1).
This module is transmitting acknowledge signals in slave receive mode (MST = 0 and TRS = 0
in ICCR1).
Executing any of the following procedures releases the BBSY flag in ICCR2 from the undefined
state.
• Input a start condition (falling edge of SDA while SCL is at the high level) to set the BBSY
flag to 1.
• Input a stop condition (rising edge of SDA while SCL is at the high level) to clear the BBSY
flag to 0.
• If the module is in master transmit mode, issue a start condition by writing 1 and 0 to the
BBSY flag and the SCP bit in ICCR2, respectively, while SCL and SDA are at the high level.
The BBSY flag is set to 1 on output of the start condition (falling edge of SDA while SCL is at
the high level).
• With the module in master transmit or master receive mode, SDA at the low level, and no
other device holding SCL at the low level, issue a stop condition by writing 0 to the BBSY flag
and the SCP bit in ICCR2. The BBSY flag is cleared to 0 on output of the stop condition
(rising edge of SDA while SCL is at the high level).
• Writing 1 to the FS bit in SAR clears the BBSY flag to 0.
Page 984 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
19.8.6
Section 19 I2C Bus Interface 3 (IIC3)
Using the IICRST Bit to Initialize the Registers
• Writing 1 to the IICRST bit sets the SDAO and SCLO bits in ICCR2 to 1.
• Writing 1 to the IICRST bit in master transmit mode or slave transmit mode sets the TDRE
flag in ICSR to 1.
• During a reset due to the IICRST bit being set to 1, writing to the BBSY flag and the SCP and
SDAO bits is disabled.
• Even during a reset due to the IICRST bit being set to 1, the input of a start (falling edge of
SDA while SCL is at the high level) or stop (rising edge of SDA while SCL is at the high
level) condition on SCL and SDA causes the BBSY flag to be set to 1 or cleared to 0,
respectively.
19.8.7
Operation of I2C Bus Interface 3 while ICE = 0
Writing 0 to the ICE bit in ICCR1 disables output to SCL and SDA. However, input on SCL and
SDA remains valid. This module operates in accord with the signals input on SCL and SDA.
19.8.8
Note on Master Transmit Mode
When the ACKE bit is set to 1 in master transmit mode, issue a stop condition after confirming the
falling edge of the 9th clock of SCL.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 985 of 1778
Section 19 I2C Bus Interface 3 (IIC3)
Page 986 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Section 20 A/D Converter (ADC)
This LSI includes a successive approximation type 12-bit A/D converter.
20.1
Features
• 12-bit resolution
• Input channels: Twelve channels (SH7286) or eight channels (SH7285 and SH7243)
• High-speed conversion
When Aφ = 50 MHz: Minimum 1.0 μs per channel
AD clock = 50 MHz, 50 conversion states
• Two operating modes
⎯ Single-cycle scan mode: Continuous A/D conversion on one to four channels
⎯ Continuous scan mode: Repetitive A/D conversion on one to four channels
• Twelve A/D data registers (SH7286) or eight A/D data registers (SH7285 and SH7243)
A/D conversion results are stored in 16-bit A/D data registers (ADDR) that correspond to the
input channels.
• Sample-and-hold function
Sample-and-hold circuits are built into the A/D converter of this LSI, simplifying the
configuration of the external analog input circuitry. Multiple channels can be sampled
simultaneously because sample-and-hold circuits can be dedicated to channels 0 to 2.
⎯ Group A (GrA): Analog input pins selected from channels 0, 1, and 2 can be
simultaneously sampled.
• Offset canceling (OFC) function
The offset canceling processing for the A/D converter is automatically performed.
• Three methods for starting A/D conversion
Software: Setting of the ADST bit in ADCR
Timer: TRGAN, TRG0N, TRG4AN, and TRG4BN from the MTU2
TRGAN, TRG4AN, and TRG4BN from the MTU2S
External trigger: ADTRG (LSI pin)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 987 of 1778
Section 20 A/D Converter (ADC)
SH7280 Group, SH7243 Group
• Selectable analog input channel
A/D conversion of a selected channel is accomplished by setting the A/D analog input channel
select registers (ADANSR).
• A/D conversion end interrupt, DMAC transfer function, and DTC transfer function are
supported
On completion of A/D conversion, A/D conversion end interrupts (ADI) can be generated and
the DMAC or DTC can be activated by an ADI.
Figure 20.1 shows a block diagram of the A/D converter.
Page 988 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D_0
Internal data bus
GrA
ADSR_0
ADSTRGR_0
ADBYPSCR_0
ADCR_0
ADDR3
Sample-andhold circuit
AN1
Sample-andhold circuit
AN2
Sample-andhold circuit
Aφ
Analog multiplexer
AN0
ADDR2
12-bit D/A
ADDR1
AVss
AVREF
AVREFVSS
ADDR0
Successive
approximation
register
AVcc
ADANSR_0
Bus interface
−
+
Sample-andhold circuit
Comparator
A/D 0 conversion
control circuit
Offset cancel circuit
A/D conversion
end interrupt
signal (ADI_3)
AN3
AVcc
AVss
AVREF
AVREFVSS
A/D trigger signal
from MTU2S
(TRGAN,
TRG4AN,
TRG4BN)
A/D_1
Internal data bus
ADSTRGR_1
ADBYPSCR_1
ADSR_1
ADCR_1
ADDR7
ADDR6
12-bit D/A
ADDR5
AVss
AVREF
ADDR4
Successive
approximation
register
AVcc
ADANSR_1
Bus interface
AVREFVSS
A/D trigger signal
from MTU2
(TRGAN,
TRG0N,
TRG4AN,
TRG4BN)
Analog multiplexer
AN4
AN5
AN6
−
+
Sample-andhold circuit
Comparator
A/D 1 conversion
control circuit
Offset cancel circuit
AN7
A/D conversion
end interrupt
signal (ADI_4)
A/D_2
Internal data bus
ADSTRGR_2
ADBYPSCR_2
ADSR_2
ADCR_2
ADDR11
ADDR10
12-bit D/A
ADDR9
AVss
AVREF
AVREFVSS
ADDR8
Successive
approximation
register
AVcc
ADANSR_2
Bus interface
External trigger signal
(ADTRG)
AN9
AN10
Analog multiplexer
AN8
Sample-andhold circuit
−
+
Comparator
A/D 2 conversion
control circuit
Offset cancel circuit
AN11
A/D conversion
end interrupt
signal (ADI_4)
[Legend]
A/D data register
ADDR:
A/D control register
ADCR:
ADANSR: A/D analog input channel select register
A/D status register
ADSR:
ADSTRGR: A/D start trigger select register
ADBYPSCR: A/D bypass control register
Group A
GrA:
Note: A/D_2 is only in the SH7286.
Figure 20.1 Block Diagram of A/D Converter
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 989 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
20.2
Input/Output Pins
Table 20.1 shows the configuration of the pins used by the A/D converter. For the pin usage, refer
to the usage notes in section 20.7, Usage Notes.
Table 20.1 Pin Configuration
Module
Pin Name
I/O
Function
Common
AVCC
Input
Analog block power supply pin
AVSS
Input
Analog block ground pin
AVREF
Input
Analog block reference power supply pin (high)
AVREFVSS
Input
Analog block reference power supply pin (low)
ADTRG
Input
A/D external trigger input pin
AN0
Input
Analog input pin 0 (Group A)
AN1
Input
Analog input pin 1 (Group A)
AN2
Input
Analog input pin 2 (Group A)
AN3
Input
Analog input pin 3
AN4
Input
Analog input pin 4
AN5
Input
Analog input pin 5
AN6
Input
Analog input pin 6
AN7
Input
Analog input pin 7
AN8
Input
Analog input pin 8 (only for SH7286)
AN9
Input
Analog input pin 9 (only for SH7286)
AN10
Input
Analog input pin 10 (only for SH7286)
AN11
Input
Analog input pin 11 (only for SH7286)
A/D module 0
(A/D_0)
A/D module 1
(A/D_1)
A/D module 2
(A/D_2)
Page 990 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.3
Section 20 A/D Converter (ADC)
Register Descriptions
The A/D converter has the following registers. (ADCR_2 to ADANSR_2, and ADDR8 to
ADDR11 are only in the SH7286.)
Table 20.2 Register Configuration
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
A/D control register_0
ADCR_0
R/W
H'00
H'FFFFE800
8
A/D status register_0
ADSR_0
R/W
H'00
H'FFFFE802
8
A/D start trigger select register_0
ADSTRGR_0
R/W
H'00
H'FFFFE81C
8
A/D analog input channel select
register_0
ADANSR_0
R/W
H'00
H'FFFFE820
8
A/D bypass control register_0
ADBYPSCR_0
R/W
H'00
H'FFFFE830
8
A/D data register 0
ADDR0
R
H'0000
H'FFFFE840
16
A/D data register 1
ADDR1
R
H'0000
H'FFFFE842
16
A/D data register 2
ADDR2
R
H'0000
H'FFFFE844
16
A/D data register 3
ADDR3
R
H'0000
H'FFFFE846
16
A/D control register_1
ADCR_1
R/W
H'00
H'FFFFEC00
8
A/D status register_1
ADSR_1
R/W
H'00
H'FFFFEC02
8
A/D start trigger select register_1
ADSTRGR_1
R/W
H'00
H'FFFFEC1C 8
A/D analog input channel select
register_1
ADANSR_1
R/W
H'00
H'FFFFEC20
8
A/D bypass control register_1
ADBYPSCR_1
R/W
H'00
H'FFFFEC30
8
A/D data register 4
ADDR4
R
H'0000
H'FFFFEC40
16
A/D data register 5
ADDR5
R
H'0000
H'FFFFEC42
16
A/D data register 6
ADDR6
R
H'0000
H'FFFFEC44
16
A/D data register 7
ADDR7
R
H'0000
H'FFFFEC46
16
A/D control register_2
ADCR_2
R/W
H'00
H'FFFFEE00
8
A/D status register_2
ADSR_2
R/W
H'00
H'FFFFEE02
8
A/D start trigger select register_2
ADSTRGR_2
R/W
H'00
H'FFFFEE1C
8
A/D analog input channel select
register_2
ADANSR_2
R/W
H'00
H'FFFFEE20
8
A/D bypass control register_2
ADBYPSCR_2
R/W
H'00
H'FFFFEE30
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 991 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
A/D data register 8
ADDR8
R
H'0000
H'FFFFEE40
16
A/D data register 9
ADDR9
R
H'0000
H'FFFFEE42
16
A/D data register 10
ADDR10
R
H'0000
H'FFFFEE44
16
A/D data register 11
ADDR11
R
H'0000
H'FFFFEE46
16
Page 992 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.3.1
Section 20 A/D Converter (ADC)
A/D Control Registers 0 to 2 (ADCR_0 to ADCR_2)
ADCR is an 8-bit readable/writable register that selects A/D conversion mode and others.
Bit:
6
5
4
3
2
ADCS
ACE
ADIE
-
-
TRGE EXTRG
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
ADST
0
R/W
A/D Start
1
0
7
ADST
0
R/W
When this bit is cleared to 0, A/D conversion is stopped
and the A/D converter enters the idle state. When this bit
is set to 1, A/D conversion is started. In single-cycle scan
mode, this bit is automatically cleared to 0 when A/D
conversion ends on the selected single channel. In
continuous scan mode, A/D conversion is continuously
performed for the selected channels in sequence until this
bit is cleared by software, a reset, or in software standby
mode.
6
ADCS
0
R/W
A/D Continuous Scan
Selects either a single-cycle or a continuous scan in scan
mode. This bit is valid only when scan mode is selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the ADST
bit to 0.
5
ACE
0
R/W
Automatic Clear Enable
Enables or disables the automatic clearing of ADDR after
ADDR is read by the CPU or DMAC. When this bit is set
to 1, ADDR is automatically cleared to H'0000 after the
CPU or DMAC reads ADDR. This function allows the
detection of any renewal failures of ADDR.
0: Automatic clearing of ADDR after being read is
disabled.
1: Automatic clearing of ADDR after being read is enabled.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 993 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Bit
Bit Name
Initial
Value
R/W
Description
4
ADIE
0
R/W
A/D Interrupt Enable
Enables or disables the generation of A/D conversion end
interrupts (ADI) to the CPU. Operating modes must be
changed when the ADST bit is 0 to prevent incorrect
operations.
When A/D conversion ends and the ADF bit in ADSR is
set to 1 and this bit is set to 1, ADI is sent to the CPU. By
clearing the ADF bit or the ADIE bit to 0, ADI can be
cleared.
In addition, ADIE activates the DMAC when an ADI is
generated. At this time, no interrupt to the CPU is
generated.
0: Generation of A/D conversion end interrupt is disabled
1: Generation of A/D conversion end interrupt is enabled
3, 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
TRGE
0
R/W
Trigger Enable
Enables or disables A/D conversion start by the external
trigger input (ADTRG) or A/D conversion start triggers
from the MTU2 and MTU2S (TRGAN, TRG0N, TRG4AN,
and TRG4BN from the MTU2 and TRGAN, TRG4AN, and
TRG4BN from the MTU2S). For selection of the external
trigger and A/D conversion start trigger from the MTU2 or
MTU2S, see the description of the EXTRG bit.
0: A/D conversion start by the external trigger or an A/D
conversion start trigger from the MTU or MTU2S is
disabled
1: A/D conversion start by the external trigger or an A/D
conversion start trigger from the MTU2 or MTU2S is
enabled
Page 994 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Bit
Bit Name
Initial
Value
R/W
Description
0
EXTRG
0
R/W
Trigger Select
Selects the external trigger (ADTRG) or an A/D conversion
start trigger from the MTU2 or MTU2S as an A/D
conversion start trigger.
When the external trigger is selected (EXTRG = 1), upon
input of a low-level pulse to the ADTRG pin after the
TRGE bit is set to 1, the A/D converter detects the falling
edge of the pulse, and sets the ADST bit in ADCR to 1.
The operation which is performed when 1 is written to the
ADST bit by software is subsequently performed. A/D
conversion start by the external trigger input is enabled
only when the ADST bit is cleared to 0.
When the external trigger is used as an A/D conversion
start trigger, the low-level pulse input to the ADTRG pin
must be at least 1.5 Pφ clock cycles in width.
0: A/D converter is started by the A/D conversion start
trigger from the MTU2 or MTU2S
1: A/D converter is started by the external pin (ADTRG)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 995 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
20.3.2
A/D Status Registers 0 to 2 (ADSR_0 to ADSR_2)
ADSR is an 8-bit readable/writable register that indicates the status of the A/D converter.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
ADF
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/(W)*
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Do not overwrite 0 while this flag is 0.
Bit
Bit Name
7 to 1 ⎯
Initial
Value
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
0
ADF
0
R/(W)*
A/D End Flag
A status flag that indicates the completion of A/D
conversion.
[Setting condition]
•
When A/D conversion on all specified channels is
completed in scan mode
[Clearing conditions]
Page 996 of 1778
•
When 0 is written after reading ADF = 1
•
When the DMAC is activated by an ADI interrupt and
ADDR is read
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.3.3
Section 20 A/D Converter (ADC)
A/D Start Trigger Select Registers 0 to 2 (ADSTRGR_0 to ADSTRGR_2)
ADSTRGR selects an A/D conversion start trigger from the MTU2 or MTU2S. The A/D
conversion start trigger is used as an A/D conversion start source when the TRGE bit in ADCR is
set to 1 and the EXTRG bit in ADCR is set to 0.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
STR6
STR5
STR4
STR3
STR2
STR1
STR0
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
7
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
6
STR6
0
R/W
Start Trigger 6
Enables or disables the A/D conversion start request
input from the MTU2S.
0: Disables the A/D conversion start by TRGAN trigger
(MTU2S).
1: Enables the A/D conversion start by TRGAN trigger
(MTU2S).
5
STR5
0
R/W
Start Trigger 5
Enables or disables the A/D conversion start request
input from the MTU2S.
0: Disables the A/D conversion start by TRG4AN trigger
(MTU2S).
1: Enables the A/D conversion start by TRG4AN trigger
(MTU2S).
4
STR4
0
R/W
Start Trigger 4
Enables or disables the A/D conversion start request
input from the MTU2S.
0: Disables the A/D conversion start by TRG4BN trigger
(MTU2S).
1: Enables the A/D conversion start by TRG4BN trigger
(MTU2S).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 997 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Bit
Bit Name
Initial
Value
R/W
Description
3
STR3
0
R/W
Start Trigger 3
Enables or disables the A/D conversion start request
input from the MTU2.
0: Disables the A/D conversion start by TRG0N trigger
(MTU2).
1: Enables the A/D conversion start by TRG0N trigger
(MTU2).
2
STR2
0
R/W
Start Trigger 2
Enables or disables the A/D conversion start request
input from the MTU2.
0: Disables the A/D conversion start by TRGAN trigger
(MTU2).
1: Enables the A/D conversion start by TRGAN trigger
(MTU2).
1
STR1
0
R/W
Start Trigger 1
Enables or disables the A/D conversion start request
input from the MTU2.
0: Disables the A/D conversion start by TRG4AN trigger
(MTU2).
1: Enables the A/D conversion start by TRG4AN trigger
(MTU2).
0
STR0
0
R/W
Start Trigger 0
Enables or disables the A/D conversion start request
input from the MTU2.
0: Disables the A/D conversion start by TRG4BN trigger
(MTU2).
1: Enables the A/D conversion start by TRG4BN trigger
(MTU2).
Page 998 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.3.4
Section 20 A/D Converter (ADC)
A/D Analog Input Channel Select Registers 0 to 2 (ADANSR_0 to ADANSR_2)
ADANSR is an 8-bit readable/writable register that selects an analog input channel.
Bit:
Initial value:
R/W:
Bit
Bit Name
7 to 4 ⎯
7
6
5
4
3
2
1
0
-
-
-
-
ANS3
ANS2
ANS1
ANS0
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
ANS3
0
R/W
2
ANS2
0
R/W
1
ANS1
0
R/W
0
ANS0
0
R/W
Setting bits in the A/D analog input channel select
register to 1 selects a channel that corresponds to a
specified bit. For the correspondence between analog
input pins and bits, see table 20.3.
When changing the analog input channel, the ADST bit in
ADCR must be cleared to 0 to prevent incorrect
operations.
Table 20.3 Channel Select List
Analog Input Channels
Bit Name
A/D_0
A/D_1
A/D_2
ANS0
AN0
AN4
AN8 (only for SH7286)
ANS1
AN1
AN5
AN9 (only for SH7286)
ANS2
AN2
AN6
AN10 (only for SH7286)
ANS3
AN3
AN7
AN11 (only for SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 999 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
20.3.5
A/D Bypass Control Registers 0 to 2 (ADBYPSCR_0 to ADBYPSCR_2)
For A/D conversion of group A (GrA), it can be selected whether or not to use the sample-andhold circuits dedicated to the group A channels.
Setting the SH bit in ADBYPSCR_0 to 1 selects the sample-and-hold circuits dedicated to the
channels. When the sample-and-hold circuits are not to be used, the A/D conversion time does not
include the time for sampling in the dedicated sample-and-hold circuits. For details, refer to
section 20.4, Operation.
Setting the OFC bit to 0 enables the offset canceling processing (OFC) for the comparator in the
A/D converter; setting the OFC bit to 1 disables automatic correction during A/D conversion. To
obtain a higher accuracy, clear the OFC bit to 0.
The function of the SH bit in this register is available only for A/D converter_0. A/D converter_1,
2 are always in the same state as when the SH bit is set to 0.
Bit:
Initial value:
R/W:
Bit
Bit Name
7 to 2 ⎯
7
6
5
4
3
2
1
0
-
-
-
-
-
-
OFC
SH
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
OFC
0
R/W
Offset Canceling Bypass
0: A/D conversion in high-accuracy automatic correction
mode
1: A/D conversion without no correction
0
SH
0
R/W
Dedicated Sample-and-Hold Circuit Select
(ADBYPSCR_0 only)
0: Does not select the sample-and-hold circuits
1: Selects the sample-and-hold circuits
This bit is a reserved bit in ADBYPSCR_1 and
ADBYPSCR_2. The writing value should always be 0.
Page 1000 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.3.6
Section 20 A/D Converter (ADC)
A/D Data Registers 0 to 11 (ADDR0 to ADDR11)
ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is
stored in ADDR with the corresponding number. (See table 20.4.)
The converted 12-bit data is stored in bits 11 to 0.
The initial value of ADDR is H'0000.
After ADDR is read, ADDR can be automatically cleared to H'0000 by setting the ACE bit in
ADCR to 1.
Bit: 15
14
13
12
-
-
-
-
Initial value: 0
R/W: R
0
R
0
R
0
R
Bit
10
9
8
7
6
5
4
3
2
1
0
0
R
0
R
0
R
0
R
0
R
ADD[11:0]
0
R
0
R
0
R
0
R
Initial
Value
R/W
Description
All 0
R
Reserved
ADD[11:0] All 0
R
12-bit data
Bit Name
15 to 12 ⎯
11 to 0
11
0
R
0
R
0
R
Table 20.4 Correspondence between Analog Channels and Registers (ADDR0 to ADDR11)
Analog Input Channels
A/D Data Registers
AN0
ADDR0
AN1
ADDR1
AN2
ADDR2
AN3
ADDR3
AN4
ADDR4
AN5
ADDR5
AN6
ADDR6
AN7
ADDR7
AN8
ADDR8 (only for SH7286)
AN9
ADDR9 (only for SH7286)
AN10
ADDR10 (only for SH7286)
AN11
ADDR11 (only for SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1001 of 1778
Section 20 A/D Converter (ADC)
20.4
SH7280 Group, SH7243 Group
Operation
The A/D converter has two operating modes: single-cycle scan mode and continuous scan mode.
In single-cycle scan mode, A/D conversion is performed once on one or more specified channels
and then it ends. In continuous scan mode, the A/D conversion is performed sequentially on one or
more specified channels until the ADST bit is cleared to 0.
The ADCS bit in the A/D control register (ADCR) is used to select the operating mode. Setting
the ADCS bit to 0 selects single-cycle scan mode and setting the ADCS bit to 1 selects continuous
scan mode. In both modes, A/D conversion starts on the channel with the lowest number in the
analog input channels selected by the A/D analog input channel select register (ADANSR) from
AN0 to AN3.
In single-cycle scan mode, when one cycle of A/D conversion on all specified channels is
completed, the ADF bit in ADSR is set to 1 and the ADST bit is automatically cleared to 0. In
continuous scan mode, when conversion on all specified channels is completed, the ADF bit in
ADSR is set to 1. To stop A/D conversion, write 0 to the ADST bit. When the ADF bit is set to 1,
if the ADIE bit in ADCR is set to 1, an A/D conversion end interrupt (ADI) is generated. When
clearing the ADF bit to 0, read the ADF bit while set to 1 and then write 0. However, when the
DMAC or DTC is activated by an ADI interrupt, the ADF bit is automatically cleared to 0.
Page 1002 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.4.1
Section 20 A/D Converter (ADC)
Single-Cycle Scan Mode
The following example shows the operation when analog input channels 0 to 3 (AN0 to AN3) are
selected and the A/D conversion is performed in single-cycle scan mode using four channels.
1.
2.
3.
4.
5.
Set the ADCS bit in the A/D control register (ADCR) to 0.
Set all bits ANS0 to ANS3 in the A/D analog input channel select register (ADANSR) to 1.
Set the OFC and SH bits in the A/D bypass control register_0 (ADBYPSCR_0).
Set the ADST bit in the A/D control register (ADCR) to 1 to start A/D conversion.
After channels 0 to 2 (GrA) are sampled simultaneously, offset canceling processing (OFC) is
performed*. Then, A/D conversion is performed on channel 0. Upon completion of the A/D
conversion, the A/D conversion result is transferred to ADDR1. In the same way, channel 2 is
converted and the A/D conversion result is transferred to ADDR2.
6. A/D conversion of channel 3 is then started. Upon completion of the A/D conversion, the A/D
conversion result is transferred to ADDR3.
7. When A/D conversion ends on all specified channels (AN0 to AN3), the ADF bit is set to 1,
the ADST bit is automatically cleared to 0, and the A/D conversion ends. At this time, if the
ADIE bit is set to 1, an ADI interrupt is generated after the A/D conversion.
Note: * The operation depends on the OFC and SH bit settings in ADBYPSCR_0. For details,
see figures 20.2 through 20.5.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1003 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST automatically cleared
ADF cleared*
ADF
Simultaneous sampling
AN0
Waiting for
conversion
S
OFC
H
A/D
conversion
Waiting for conversion
Simultaneous sampling
AN1
Waiting for
conversion
S
OFC
H
A/D
conversion
H
Waiting for conversion
Simultaneous sampling
AN2
Waiting for
conversion
AN3
Waiting for
conversion
S
OFC
H
OFC
H
A/D
conversion
Waiting for conversion
ADDR0
ADDR1
ADDR2
Waiting for conversion
A/D
conversion
A/D conversion result (AN0)
A/D conversion result (AN1)
A/D conversion result (AN2)
ADDR3
[Legend]
OFC: Offset canceling processing
S:
Sampling
H:
Holding
Note: * Instruction execution by software
Waiting for conversion
A/D conversion result (AN3)
[ADBYPSCR_0 settings]
OFC bit = 0
SH bit = 1
Figure 20.2 Example 1 of A/D_0 Converter Operation (Single-Cycle Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Enabled)
Page 1004 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST automatically cleared
ADF cleared*
ADF
AN0
Waiting for
conversion OFC
A/D
conversion
AN1
Waiting for
conversion OFC
Waiting for
conversion
AN2
Waiting for
conversion OFC
Waiting for
conversion
AN3
Waiting for
conversion OFC
Waiting for conversion
Waiting for conversion
A/D
conversion
ADDR0
ADDR1
ADDR2
ADDR3
[Legend]
OFC: Offset canceling processing
S:
Sampling
H:
Holding
Waiting for conversion
A/D
conversion
Waiting for conversion
A/D
conversion
Waiting for conversion
A/D conversion result (AN0)
A/D conversion result (AN1)
A/D conversion result (AN2)
A/D conversion result (AN3)
[ADBYPSCR_0 settings]
OFC bit = 0
SH bit = 0
Note: * Instruction execution by software
Figure 20.3 Example 2 of A/D_0 Converter Operation (Single-Cycle Scan Mode,
Sample-and-Hold Circuit Disabled, and Offset Canceling Circuit Enabled)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1005 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST automatically cleared
ADF cleared*
ADF
Simultaneous sampling
AN0
Waiting for
conversion
AN1
Waiting for
conversion
S
A/D
conversion
Waiting for conversion
Simultaneous sampling
S
A/D
conversion
H
Waiting for conversion
Simultaneous sampling
AN2
Waiting for
conversion
AN3
S
H
Waiting for conversion
ADDR0
ADDR1
ADDR2
ADDR3
[Legend]
OFC: Offset canceling processing
S:
Sampling
H:
Holding
A/D
conversion
Waiting for conversion
A/D
conversion
Waiting for conversion
A/D conversion result (AN0)
A/D conversion result (AN1)
A/D conversion result (AN2)
A/D conversion result (AN3)
[ADBYPSCR_0 settings]
OFC bit = 1
SH bit = 1
Note: * Instruction execution by software
Figure 20.4 Example 3 of A/D_0 Converter Operation (Single-Cycle Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Disabled)
Page 1006 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST automatically cleared
ADF cleared*
ADF
AN0
Waiting for
conversion
A/D
conversion
Waiting for conversion
AN1
Waiting for
conversion
AN2
Waiting for conversion
AN3
A/D
conversion
Waiting for conversion
ADDR0
ADDR1
ADDR2
ADDR3
[Legend]
OFC: Offset canceling processing
S:
Sampling
H:
Holding
Waiting for conversion
A/D
conversion
Waiting for conversion
A/D
conversion
Waiting for conversion
A/D conversion result (AN0)
A/D conversion result (AN1)
A/D conversion result (AN2)
A/D conversion result (AN3)
[ADBYPSCR_0 settings]
OFC bit = 1
SH bit = 0
Note: * Instruction execution by software
Figure 20.5 Example 4 of A/D_0 Converter Operation (Single-Cycle Scan Mode,
Sample-and-Hold Circuit Disabled, and Offset Canceling Circuit Disabled)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1007 of 1778
Section 20 A/D Converter (ADC)
20.4.2
SH7280 Group, SH7243 Group
Continuous Scan Mode
The following example shows the operation when analog input 0, 2, and 3 (AN0, AN2, AN3) are
selected and the A/D conversion is performed in continuous scan mode using the three channels.
This operation also applies to the A/D_1 conversion.
1. Set the ADCS bit in the A/D control register (ADCR) to 0.
2. Set all bits of ANS0, ANS2, and ANS3 in the A/D analog input channel select register
(ADANSR) to 1.
3. Set the OFC and SH bits in the A/D bypass control register_0 (ADBYPSCR_0).
4. Set the ADST bit in the A/D control register (ADCR) to 1 to start A/D conversion.
5. Channels 0 and 2 (GrA) are sampled simultaneously*. As the ANS1 bit in ADANSR is set to
0, channel 1 is not sampled. After this, offset canceling processing (OFC) is performed*. Then
the A/D conversion on channel 0 is started. Upon completion of the A/D conversion, the A/D
conversion result is transferred to ADDR0. In the same way, channel 2 is converted and the
A/D conversion result is transferred to ADDR2. The A/D conversion is not performed on
channel 1.
6. The A/D conversion of channel 3 starts. Upon completion of the A/D conversion, the A/D
conversion result is transferred to ADDR3.
7. When the A/D conversion ends on all the specified channels (AN0, AN2, and AN3), the ADF
bit is set to 1. At this time, if the ADIE bit is set to 1, an ADI interrupt is generated after the
A/D conversion.
8. Steps 5 to 7 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, the A/D conversion stops. After this, if the ADST bit is set to 1, the A/D
conversion starts again and repeats steps 5 to 7.
Note: * The operation depends on the OFC and SH bit settings in ADBYPSCR_0. For details,
see figures 20.6 through 20.9.
Page 1008 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST cleared*
ADF cleared*
ADF
Simultaneous sampling
Waiting for
conversion
AN0
S
OFC
H
Waiting for
conversion
A/D
conversion
S
OFC
H
Waiting for
conversion
Waiting for
conversion
S
OFC
H
Stop
Simultaneous sampling
A/D
conversion
H
Waiting for conversion
OFC
Simultaneous sampling
AN2
Waiting for
conversion
S
OFC
H
A/D
conversion
H
(1)
Waiting for
conversion
AN3
OFC
Waiting for
conversion
Waiting for
conversion
Waiting for
conversion
S
(2)
A/D
conversion
Waiting for
conversion OFC
Waiting for
conversion
Waiting for
conversion
A/D
conversion
(1)
(2)
A/D conversion result (AN0)
ADDR0
Waiting for
conversion
S
(2)
Waiting for conversion
OFC
Waiting for
conversion
A/D
conversion
(1)
AN1
Stop
Simultaneous sampling
A/D conversion result (AN0)
(1)
(2)
ADDR1
ADDR2
A/D conversion result (AN2)
A/D conversion result (AN2)
(1)
(2)
A/D conversion result (AN3)
ADDR3
A/D conversion result (AN3)
(1)
[Legend]
OFC:
S:
H:
Note:
(2)
[ADBYPSCR_0 settings]
Offset canceling processing
Sampling
Holding
OFC bit = 0
SH bit = 1
* Instruction execution by software
Figure 20.6 Example 1 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Enabled)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1009 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST cleared*
ADF cleared*
ADF
Stop
Waiting for
conversion
AN0
OFC
A/D
conversion
Waiting for
conversion
OFC
A/D
conversion
(1)
AN1
Waiting for
conversion
OFC
AN2
Waiting for
conversion
OFC
Waiting for
conversion
Waiting for
conversion
OFC
(2)
Waiting for conversion
Waiting for conversion
OFC
Stop
Waiting for
conversion
A/D
conversion
Waiting for
conversion
OFC
Waiting for
conversion
A/D
conversion
(1)
Waiting for
conversion OFC
AN3
Waiting for
conversion
Waiting for
conversion OFC
A/D
conversion
A/D
conversion
Waiting for
conversion
OFC
(1)
Waiting for
conversion
(2)
A/D conversion result (AN0)
ADDR0
Waiting for
conversion
(2)
A/D conversion result (AN0)
(1)
(2)
ADDR1
ADDR2
A/D conversion result (AN2)
A/D conversion result (AN2)
(1)
ADDR3
(2)
A/D conversion result (AN3)
A/D conversion result (AN3)
(2)
(1)
[Legend]
OFC:
S:
H:
Offset canceling processing
Sampling
Holding
[ADBYPSCR_0 settings]
OFC bit = 0
SH bit = 0
Note: * Instruction execution by software
Figure 20.7 Example 2 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Disabled, and Offset Canceling Circuit Enabled)
Page 1010 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST cleared*
ADF cleared*
ADF
Stop
AN0
Waiting for
conversion
S
A/D
conversion
Waiting for conversion
S
A/D
conversion
Waiting for conversion
Waiting for
conversion
S
(2)
(1)
Waiting for conversion
AN1
Stop
AN2
Waiting for
conversion
S
H
A/D
conversion
Waiting for
conversion
S
A/D
conversion
H
(1)
AN3
Waiting for conversion
Waiting for
conversion
(2)
A/D
conversion
A/D
conversion
Waiting for conversion
(1)
ADDR0
Waiting for
conversion
S
Waiting for
conversion
(2)
A/D conversion result (AN0)
A/D conversion result (AN0)
(1)
(2)
ADDR1
ADDR2
A/D conversion result (AN2)
A/D conversion result (AN2)
(1)
ADDR3
(2)
A/D conversion result (AN3)
A/D conversion result (AN3)
(2)
(1)
[Legend]
OFC:
Offset canceling processing
S:
Sampling
H:
Holding
Note:
[ADBYPSCR_0 settings]
OFC bit = 1
SH bit = 1
* Instruction execution by software
Figure 20.8 Example 3 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Disabled)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1011 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D conversion execution
ADST set*
ADST
ADST cleared*
ADF cleared*
ADF
Stop
Waiting for
conversion
AN0
A/D
conversion
Waiting for
conversion
A/D
conversion
(1)
Waiting for
conversion
A/D
conversion
Waiting for conversion
(2)
Waiting for conversion
AN1
Waiting for
conversion
AN2
AN3
A/D
conversion
(1)
Waiting for conversion
Waiting for
conversion
A/D
conversion
Waiting for conversion
(2)
A/D
conversion
(1)
Waiting for
conversion
A/D
conversion
A/D conversion result (AN0)
ADDR0
Waiting for conversion
A/D conversion result (AN0)
(1)
(2)
ADDR1
ADDR2
A/D conversion result (AN2)
A/D conversion result (AN2)
(2)
(1)
ADDR3
A/D conversion result (AN3)
(1)
Note:
(2)
[ADBYPSCR_0 settings]
[Legend]
OFC:
S:
H:
A/D conversion result (AN3)
Offset canceling processing
Sampling
Holding
OFC bit = 1
SH bit = 0
* Instruction execution by software
Figure 20.9 Example 4 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Disabled, and Offset Canceling Circuit Disabled)
Page 1012 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.4.3
Section 20 A/D Converter (ADC)
Input Sampling and A/D Conversion Time
The A/D converter has built-in sample-and-hold circuits. Channels 0 to 2 can be simultaneously
sampled as one group when the SH bit in ADBYPSCR_0 is set to 1. This group is referred to as
Group A (GrA) (in table 20.5). When the SH bit is cleared to 0, these channels are sampled
individually in the same way as other channels.
Setting the ADST bit to 1 starts A/D conversion. The A/D conversion time (tCONV) from the
beginning to the end of conversion is determined by the following five time factors (figure 20.10):
the A/D conversion start delay time (tD), sampling time (tSPLSH), offset canceling processing time
(tOFC), sampling time (tSPL), and A/D conversion processing time; the A/D conversion time (tCONV) is
the sum of these times. tSPLSH and tOFC can be reduced according to the following procedures.
To reduce tSPLSH, clear the SH bit in ADBYPSCR_0 to 0 (initial value). Note that when GrA
channels should be sampled simultaneously, the SH bit should be set to 1 to provide appropriate
tSPLSH. tSPLSH indicates the time required for the operation of the sample-and-hold circuits dedicated
to channels 0 to 2 and it does not depend on the number of channels sampled simultaneously.
To reduce tOFC, set the OFC bit in ADBYPSCR_0 to 1. Note that when highly accurate A/D
conversion is required, the OFC bit should be cleared to 0 (initial value) to provide appropriate
tOFC. In most cases, it is recommended to clear the OFC bit to 0 (initial value).
In continuous scan mode, the A/D conversion time (tCONV) given in table 20.6 applies to the
conversion time of the first cycle. The conversion time of the second and subsequent cycles is
expressed as (tCONV − tD + 6).
Table 20.6 shows the state for the Aφ1 clock. The value is calculated by multiplying the cycle time
of Aφ and the number of the state. The Aφ should always be set to Pφ or greater (Pφ ≤ Aφ) value.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1013 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Table 20.5 Correspondence between Analog Input Channels and Groups being Allowed
Simultaneous Sampling
A/D Converter Module
Analog Input Channels
Group
A/D converter module 0
AN0
GrA
AN1
AN2
A/D converter module 1
A/D converter module 2
(available only in SH7286)
Page 1014 of 1778
AN3
⎯
AN4
⎯
AN5
⎯
AN6
⎯
AN7
⎯
AN8
⎯
AN9
⎯
AN10
⎯
AN11
⎯
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Table 20.6 A/D Conversion Time
Item
Symbol
Min.
1
Typ.
Max.
A/D conversion start delay time
tD
11*
—
15*2
Analog input sampling time of sampleand-hold circuits dedicated to GrA
tSPLSH
—
30
—
Offset canceling processing time
tOFC
—
50
—
Analog input sampling time of sampleand-hold circuit common to all channels
tSPL
—
20
—
Completion of conversion
tend
—
4
—
A/D
conversion
time
tCONV
50n + 65*3
—
50n + 69*3
ADBYPSCR.SH = 0,
ADBYPSCR.OFC = 1
50n + 15*3
—
50n + 19*3
ADBYPSCR.SH = 1,
ADBYPSCR.OFC = 0
50n + 95*3
—
50n + 99*3
ADBYPSCR.SH = 1,
ADBYPSCR.OFC = 1
50n + 45*3
—
50n + 49*3
ADBYPSCR.SH = 0,
ADBYPSCR.OFC = 0
Notes: 1. A/D activation by MTU2, MTU2S trigger signal
2. A/D activation by the external trigger signal
3. n is a number of channel (n = 1 to 4)
TRGAN
(MTU2, MTU2S trigger signal)
ADST
A/D conversion time (tCONV)
tD
A/D
converter
Waiting
Sampling and
hold time (tSPLSH)*1
Sampleand-hold
tOFC*2
OFC
Sampling and
hold time (tSPL)
Sampleand-hold
Conversion complete
processing (tend)
A/D
conversion
Waiting
ADDR
End of A/D
conversion
ADF
Notes: *1 tSPLSH can be reduced by clearing the SH bit in ADBYPSCR to 0.
*2 tOFC can be reduced by setting the OFC bit in ADBYPSCR to 1.
Conversion time
per channel
50 states
(Aφ = 50 MHz: 1.00 μs)
Figure 20.10 A/D Conversion Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1015 of 1778
Section 20 A/D Converter (ADC)
20.4.4
SH7280 Group, SH7243 Group
A/D Converter Activation by MTU2 and MTU2S
A/D conversion is activated by the A/D conversion start triggers (TRGAN, TRG0N, TRG4N, and
TRG4BN) from the MTU2 and A/D conversion start triggers (TRGAN, TRG4AN, and TRG4BN)
from the MTU2S. To enable this function, set the TRGE bit in ADCR to 1 and clear the EXTRG
bit to 0. After this setting is made, if an A/D conversion start trigger from the MTU2 or MTU2S is
generated, the ADST bit is set to 1. The time between the setting of the ADST bit to 1 and the start
of the A/D conversion is the same as when A/D conversion is activated by writing 1 to the ADST
bit by software.
Page 1016 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.4.5
Section 20 A/D Converter (ADC)
External Trigger Input Timing
The A/D conversion can also be externally triggered. To input an external trigger, set the pin
function controller (PFC) to select the ADTRG pin function, drive the ADTRG pin high, set the
TRGE bit to 1 in ADCR, clear the ADST bit to 0, and set the EXTRG bit to 1. In this state, input a
trigger through the ADTRG pin. A falling edge of the ADTRG signal sets the ADST bit to 1 in
ADCR, starting the A/D conversion. Other operations are conducted in the same way as when A/D
conversion is activated by writing 1 to the ADST bit by software. Figure 20.11 shows the timing.
The ADST bit is set to 1 after ((5 – n*)Pφ) states have elapsed from the point at which the A/D
converter detects a falling edge on the ADTRG pin.
Notes: *
n=0
n=1
n=2
when Pφ : Aφ = 1:1
when Pφ : Aφ = 1:2
when Pφ : Aφ = 1:4
Pφ
ADTRG
External trigger
signal
ADST
A/D conversion
Figure 20.11 External Trigger Input Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1017 of 1778
Section 20 A/D Converter (ADC)
20.4.6
SH7280 Group, SH7243 Group
Example of ADDR Auto-Clear Function
When the A/D data register (ADDR) is read by the CPU or DMAC, ADDR can be automatically
cleared to H'0000 by setting the ACE bit in ADCR to 1. This function allows the detection of nonupdated ADDR states.
Figure 20.12 shows an example of when the auto-clear function of ADDR is disabled (normal
state) and enabled.
When the ACE bit is 0 (initial value) and the A/D conversion result (H'0222) is not written to
ADDR for some reason, the old data (H'0111) becomes the ADDR value. In addition, when the
ADDR value is read into a general register using an A/D conversion end interrupt, the old data
(H'0111) is stored in the general register. To detect a renewal failure, every time the old data needs
to be stored in the RAM, a general register, etc.
When the ACE bit is 1, reading ADDR = H'0111 by the CPU, DMAC, or DTC automatically
clears ADDR to H'0000. After this, if the A/D conversion result (H'0222) cannot be transferred to
ADDR for some reason, the cleared data (H'0000) remains as the ADDR value. When this ADDR
value is read into a general register, H'0000 is stored in the general register. Just by checking
whether the read data value is H'0000 or not allows the detection of non-updated ADDR states.
Page 1018 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
• ACE bit = 0 (Normal condition: Auto-clear function is disabled.)
A/D conversion result
H'0111
H'0222
H'0333
H'0444
ADDR not renewed
A/D data register (ADDR)
H'0333
H'0111
A/D conversion end interrupt
Read
Read
RAM, general register etc.
Read
H'0111
H'0333
Because ADDR is not renewed, old data is used.
However, it is impossible to know that the data is old or not.
• ACE bit = 1 (Auto-clear function is enabled.)
A/D conversion result
H'0111
H'0222
H'0333
H'0444
ADDR not renewed
A/D data register (ADDR)
H'0111
A/D conversion end interrupt
H'0000
Automatic clearing
after read
Read
RAM, general register etc.
H'0333
Automatic clearing
after read
Read
H'0111
H'0000
Automatic clearing
after read
Read
H'0000
H'0333
When H'0000 is read, a failure is detected by software.
Figure 20.12 Example of When ADDR Auto-clear Function is
Disabled (Normal Condition)/Enabled
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1019 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
20.5
Interrupt Sources and DMAC or DTC Transfer Requests
The A/D converter generates A/D conversion end interrupts (ADI). An ADI interrupt generation is
enabled when the ADIE bit in ADCR is set to 1. The DMAC or DTC can be activated by the
DMAC or DTC setting when an ADI interrupt is generated. At this time, no interrupt to the CPU
is generated. When the DMAC or DTC is activated by an ADI interrupt, the ADF bit in ADSR is
automatically cleared at the data transfer by the DMAC or DTC.
Table 20.7 AD Interrupt Sources
A/D Converter Module
Name
DMAC Activation
Request
DTC Activation
Request
A/D converter module 0
ADI0
Available
Available
A/D converter module 1
ADI1
Not available
Available
A/D converter module 2
ADI2
Not available
Available
Page 1020 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.6
Section 20 A/D Converter (ADC)
Definitions of A/D Conversion Accuracy
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital conversion output codes
• Offset error
The deviation of the actual A/D conversion characteristic from the ideal A/D conversion
characteristic when the digital output value changes from the minimum voltage value (zero
voltage) B'000000000000 to B'000000000001. Does not include a quantization error (see
figure 20.13).
• Full-scale error
The deviation of the actual A/D conversion characteristic from the ideal A/D conversion
characteristic when the digital output value changes from B'111111111110 to the maximum
voltage value (full-scale voltage) B'111111111111. Does not include a quantization error (see
figure 20.13).
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 20.13).
• Nonlinearity error
The deviation of the actual A/D conversion characteristic from the ideal A/D conversion
characteristic between zero voltage and full-scale voltage. Does not include offset error, fullscale error, or quantization error (see figure 20.13).
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1021 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Digital output
Full-scale error
Digital output
Ideal A/D conversion
characteristic
111
Ideal A/D conversion
characteristic
110
101
100
Nonlinearity
error
011
Quantization error
010
Actual A/D conversion
characteristic
001
000
0
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
Analog
Offset error
input voltage
FS
Analog
input voltage
[Legend]
FS: Full-scale
Figure 20.13 Definitions of A/D Conversion Accuracy
Page 1022 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.7
Usage Notes
20.7.1
Analog Input Voltage Range
Section 20 A/D Converter (ADC)
The voltage applied to analog input pin (ANn) during A/D conversion should be in the range
AVss ≤ ANn (n = 0 to 11) ≤ AVref.
20.7.2
Relationship between AVcc, AVss and Vcc, Vss
When using the A/D converter, set AVcc = 5.0 V ± 0.5 V and AVss = Vss. When the A/D
converter is not used, set Vcc ≤ AVcc ≤ 5.0V ± 0.5 V, AVss = Vss, and do not leave the AVcc pin
open.
20.7.3
Range of AVREF Pin Settings
Set AVREF = 4.5 V to AVcc when using the A/D converter, or set AVREF = AVcc when not
using the A/D converter. Set AVREFVSS = AVSS, and do not leave the AVREFVSS pin open. If
these conditions are not met, the reliability of the LSI may be adversely affected.
20.7.4
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and the layout in which the digital circuit signal lines and analog circuit signal lines cross or are in
close proximity to each other should be avoided as much as possible. Failure to do so may result in
the incorrect operation of the analog circuitry due to inductance, adversely affecting the A/D
conversion values.
In addition, digital circuitry must be isolated from the analog input signals (AN0 to AN11), analog
reference power supply (AVREF), the analog power supply (AVcc), and the analog ground
(AVss). AVss should be connected at one point to a stable digital ground (Vss) on the board.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1023 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
20.7.5
Notes on Noise Countermeasures
To prevent damage due to an abnormal voltage, such as an excessive surge at the analog input pins
(AN0 to AN11) and analog reference power supply (AVREF), a protection circuit should be
connected between the AVcc and AVss, as shown in figure 20.14. The bypass capacitors
connected to AVREF and the filter capacitor connected to ANn should be connected to the
AVREFVSS. The 0.1-μF capacitor in figure 20.14 should be placed close to the pin.
If a filter capacitor is connected as shown in figure 20.14, the input currents at the analog input pin
(ANn) are averaged, and an error may occur. Careful consideration is therefore required when
deciding the circuit constants.
AVcc
4.5 V to 5.5 V
10 μF
0.1 μF
AVss
GND
This LSI
AVREF
0.1 μF
Analog input pins
(channels 0 to 11)
Filter resistor: 100 Ω or less (reference value)
AVREFVSS
AN0 to AN11
Sensor output
impedance: 3 kΩ or less
Filter capacitor: 0.1 μF or less (reference value)
Figure 20.14 Example of Analog Input Pin Protection Circuit
20.7.6
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion precision is guaranteed for an input signal
for which the signal source impedance is 3 kΩ or less. This specification is provided to enable the
A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 3 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with
a large capacitance provided externally for A/D conversion in single mode, the input load will
essentially comprise only the internal input resistance of 10 kΩ, and the signal source impedance
is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to
follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater). When
converting a high-speed analog signal or in scan mode, a low-impedance buffer should be
inserted.
Page 1024 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
20.7.7
Section 20 A/D Converter (ADC)
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board (i.e., acting as antennas).
20.7.8
Notes when Two A/D Modules Run Simultaneously
The SH7243 and SH7285 have two A/D modules, and the SH7286 has three A/D modules. When
two or more modules run simultaneously, or if the conversion of the next A/D module is started
during the conversion of the first A/D module, as shown in figures 20.15 and 20.16, the
guaranteed absolute precision of the A/D conversion module which has been activated first will be
the values as listed in tables 20.8 and 20.9. The absolute precision depends on the cycle difference
(TAD0-AD1 in figures 20.15 and 20.16) between the start of the first activated A/D conversion and the
one of the next activated A/D conversion. Therefore, evaluate the specifications fully when two or
more A/D modules are run simultaneously.
A/D_0
ADST
AN1
ADST set
Waiting for
conversion
A/D conversion
Waiting for conversion
A/D_1
ADST
AN6
ADST set
Waiting for
conversion
A/D conversion
Waiting for
conversion
TAD0-AD1
Figure 20.15 A/D Conversion Start Timing between A/D_0 Converter and A/D_1 Converter
(Sample-and-Hold Circuits Disabled and Offset Canceling Circuits Disabled in
A/D_0 and A/D_1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1025 of 1778
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
A/D_0
ADST
AN1
ADST set
Waiting for
conversion
S
A/D conversion
OFC
Waiting for
conversion
A/D_1
ADST
AN6
ADST set
Waiting for
conversion
A/D conversion
Waiting for
conversion
TAD0-AD1
Figure 20.16 A/D Conversion Start Timing between A/D_0 Converter and A/D_1 Converter
(Sample-and-Hold Circuit Enabled and Offset Canceling Circuit Enabled in A/D_0,
Offset Canceling Circuit Disabled in A/D_1)
Table 20.8 Absolute Precision and A/D Conversion Start Cycle Difference, TAD0-AD1 (Aφ)
between A/D_0 and A/D_1 in Figure 20.15
Absolute precision
TAD0-AD1
Unit
0 to 15, 21 to 30, 45 or more
Aφ (clock)
±8
LSB
Notes: 1. This table lists the A/D_0 absolute precision when the converter of A/D_0 is started first.
2. The precision of A/D_1 is ±8LSB regardless of TAD0-AD1 when the converter of A/D_0 is
started first.
3. When the conversion of A/D_0 and A/D_1 is started simultaneously, the absolute
precision values of A/D_0 and A/D_1 are ±8LSB because TAD0-AD1 = 0.
4. When two A/D modules run simultaneously, the absolute precision of the first activated
A/D is not guaranteed except for TAD0-AD1.
5. When A/D_0 and A/D_1 are activated separately, each of TAD0-AD1 values is 45 or more.
Thus, the absolute precision values of A/D_0 and A/D_1 are ±8LSB.
Page 1026 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 20 A/D Converter (ADC)
Table 20.9 Absolute Precision and A/D Conversion Start Cycle Difference, TAD0-AD1 (Aφ)
between A/D_0 and A/D_1 in Figure 20.16
Absolute precision
TAD0-AD1
Unit
0 to 15, 33 to 45, 55 to 65, 83 to 95, 107 or more
Aφ (clock)
±8
LSB
Notes: 1. This table lists the A/D_0 absolute precision when the converter of A/D_0 is started first.
2. The precision of A/D_1 is ±8LSB regardless of TAD0-AD1 when the converter of A/D_0 is
started first.
3. When the conversion of A/D_0 and A/D_1 is started simultaneously, the absolute
precision values of A/D_0 and A/D_1 are ±8LSB because TAD0-AD1 = 0.
4. When two A/D modules run simultaneously, the absolute precision of the first activated
A/D is not guaranteed except for TAD0-AD1.
5. When A/D_0 and A/D_1 are activated separately, each of TAD0-AD1 values is 107 or more.
Thus, the absolute precision values of A/D_0 and A/D_1 are ±8LSB.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1027 of 1778
Section 20 A/D Converter (ADC)
Page 1028 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 21 D/A Converter (DAC) (SH7286 Only)
Section 21 D/A Converter (DAC) (SH7286 Only)
21.1
8-bit resolution
Two output channels
Maximum conversion time of 10 μs (with 20 pF load)
Output voltage of 0 V to AVREF (AVCC)
D/A output hold function in software standby mode
Module standby mode can be set
Internal data bus
DACR
8-bit
D/A
DADR1
AVcc
AVREF
DA0
DA1
AVss
DADR0
Module data bus
Bus interface
•
•
•
•
•
•
Features
Control circuit
[Legend]
DADR0: D/A data register 0
DADR1: D/A data register 1
DACR: D/A control register
Figure 21.1 Block Diagram of D/A Converter
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1029 of 1778
SH7280 Group, SH7243 Group
Section 21 D/A Converter (DAC) (SH7286 Only)
21.2
Input/Output Pins
Table 21.1 shows the pin configuration of the D/A converter.
Table 21.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVcc
Input
Analog block power supply (pin 156)
Analog ground pin
AVss
Input
Analog block ground (pin 157)
Analog output pin 0
DA0
Output
Channel 0 analog output
Analog output pin 1
DA1
Output
Channel 1 analog output
Page 1030 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
21.3
Section 21 D/A Converter (DAC) (SH7286 Only)
Register Descriptions
The D/A converter has the following registers.
Table 21.2 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
D/A data register 0
DADR0
R/W
H'00
H'FFFE6800
8, 16
D/A data register 1
DADR1
R/W
H'00
H'FFFE6801
8, 16
D/A control register
DACR
R/W
H'1F
H'FFFE6802
8, 16
21.3.1
D/A Data Registers 0 and 1 (DADR0 and DADR1)
DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be
performed. Whenever analog output is enabled, the values in DADR are converted and output to
the analog output pins.
DADR is initialized to H'00 by a power-on reset or in module standby mode.
Bit:
Initial value:
R/W:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Page 1031 of 1778
SH7280 Group, SH7243 Group
Section 21 D/A Converter (DAC) (SH7286 Only)
21.3.2
D/A Control Register (DACR)
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter.
DACR is initialized to H'1F by a power-on reset or in module standby mode.
Bit:
7
6
DAOE1 DAOE0
Initial value:
R/W:
0
R/W
0
R/W
5
4
3
2
1
DAE
-
-
-
-
-
0
R/W
1
-
1
-
1
-
1
-
1
-
Bit
Bit Name
Initial
Value
R/W
Description
7
DAOE1
0
R/W
D/A Output Enable 1
0
Controls D/A conversion and analog output for channel 1.
0: Analog output of channel 1 (DA1) is disabled
1: D/A conversion of channel 1 is enabled. Analog output
of channel 1 (DA1) is enabled.
6
DAOE0
0
R/W
D/A Output Enable 0
Controls D/A conversion and analog output for channel 0.
0: Analog output of channel 0 (DA0) is disabled
1: D/A conversion of channel 0 is enabled. Analog output
of channel 0 (DA0) is enabled.
5
DAE
0
R/W
D/A Enable
Used together with the DAOE0 and DAOE1 bits to control
D/A conversion. Output of conversion results is always
controlled by the DAOE0 and DAOE1 bits. For details,
see table 21.3.
0: D/A conversion for channels 0 and 1 is controlled
independently
1: D/A conversion for channels 0 and 1 is controlled
together
4 to 0
⎯
All 1
⎯
Reserved
These bits are always read as 1 and cannot be modified.
Page 1032 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 21 D/A Converter (DAC) (SH7286 Only)
Table 21.3 Control of D/A Conversion
Bit 5
Bit 7
Bit 6
DAE
DAOE1
DAOE0
0
0
1
1
0
1
Description
0
D/A conversion is disabled.
1
D/A conversion of channel 0 is enabled and D/A conversion
of channel 1 is disabled.
0
D/A conversion of channel 1 is enabled and D/A conversion
of channel 0 is disabled.
1
D/A conversion of channels 0 and 1 is enabled.
0
D/A conversion is disabled.
1
D/A conversion of channels 0 and 1 is enabled.
0
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1033 of 1778
SH7280 Group, SH7243 Group
Section 21 D/A Converter (DAC) (SH7286 Only)
21.4
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate
independently. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the
conversion result is output.
An operation example of D/A conversion on channel 0 is shown below. Figure 21.2 shows the
timing of this operation.
1. Write the conversion data to DADR0.
2. Set the DAOE0 bit in DACR to 1 to start D/A conversion. The conversion result is output from
the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result
continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The
output value is expressed by the following formula:
Contents of DADR
256
× AVcc
3. If DADR0 is written to again, the conversion is immediately started. The conversion result is
output after the conversion time tDCONV has elapsed.
4. If the DAOE0 bit is cleared to 0, analog output is disabled.
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
DADR0
Conversion data 1
Conversion data 2
DAOE0
Conversion
result 2
Conversion
result 1
DA0
High-impedance state
tDCONV
tDCONV
[Legend]
tDCONV: D/A conversion time
Figure 21.2 Example of D/A Converter Operation
Page 1034 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
21.5
Usage Notes
21.5.1
Module Standby Mode Setting
Section 21 D/A Converter (DAC) (SH7286 Only)
Operation of the D/A converter can be disabled or enabled using the standby control register. The
initial setting is for operation of the D/A converter to be halted. Register access is enabled by
canceling module standby mode. For details, see section 28, Power-Down Modes.
21.5.2
D/A Output Hold Function in Software Standby Mode
When this LSI enters software standby mode with D/A conversion enabled, the D/A outputs are
retained, and the analog power supply current is equal to as during D/A conversion. If the analog
power supply current needs to be reduced in software standby mode, clear the DAOE0, DAOE1,
and DAE bits to 0 to disable the D/A outputs.
21.5.3
Setting Analog Input Voltage
The reliability of this LSI may be adversely affected if the following voltage range is exceeded.
• AVcc and AVss input voltages
Input voltages AVcc and AVss should be Vcc − 0.3 V ≤ AVcc and AVss = Vss. Do not leave
the AVcc and AVss pins open when the A/D converter or D/A converter is not in use and in
software standby mode. When not in use, connect AVcc to the power supply (Vcc) and AVss
to the ground (Vss).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1035 of 1778
Section 21 D/A Converter (DAC) (SH7286 Only)
Page 1036 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Section 22 Controller Area Network (RCAN-ET)
(SH7286 Only)
22.1
Summary
22.1.1
Overview
This document primarily describes the programming interface for the RCAN-ET module. It serves
to facilitate the hardware/software interface so that engineers involved in the RCAN-ET
implementation can ensure the design is successful.
22.1.2
Scope
The CAN Data Link Controller function is not described in this document. It is the responsibility
of the reader to investigate the CAN Specification Document (see references). The interfaces from
the CAN Controller are described, in so far as they pertain to the connection with the User
Interface.
The programming model is described in some detail. It is not the intention of this document to
describe the implementation of the programming interface, but to simply present the interface to
the underlying CAN functionality.
The document places no constraints upon the implementation of the RCAN-ET module in terms of
process, packaging or power supply criteria. These issues are resolved where appropriate in
implementation specifications.
22.1.3
Audience
In particular this document provides the design reference for software authors who are responsible
for creating a CAN application using this module.
In the creation of the RCAN-ET user interface LSI engineers must use this document to
understand the hardware requirements.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1037 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.1.4
SH7280 Group, SH7243 Group
References
1.
2.
3.
4.
CAN Licence Specification, Robert Bosch GmbH, 1992
CAN Specification Version 2.0 part A, Robert Bosch GmbH, 1991
CAN Specification Version 2.0 part B, Robert Bosch GmbH, 1991
Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In
Automation, Erlangen, Germany, 1997
5. Road vehicles - Controller area network (CAN): Part 1: Data link layer and physical signalling
(ISO-11898-1, 2003)
22.1.5
•
•
•
•
•
•
•
•
•
•
•
•
Features
supports CAN specification 2.0B
Bit timing compliant with ISO-11898-1
16 Mailbox version
Clock 20 to 50 MHz
15 programmable Mailboxes for transmit / receive + 1 receive-only mailbox
sleep mode for low power consumption and automatic recovery from sleep mode by detecting
CAN bus activity
programmable receive filter mask (standard and extended identifier) supported by all
Mailboxes
programmable CAN data rate up to 1MBit/s
transmit message queuing with internal priority sorting mechanism against the problem of
priority inversion for real-time applications
data buffer access without SW handshake requirement in reception
flexible micro-controller interface
flexible interrupt structure
Page 1038 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.2
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Architecture
The RCAN-ET device offers a flexible and sophisticated way to organise and control CAN
frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed
from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox,
Mailbox Control and CAN Interface. The figure below shows the block diagram of the RCAN-ET
Module. The bus interface timing is designed according to the peripheral bus I/F required for each
product.
CRx0
CTx0
CAN Interface
REC
Transmit Buffer
BCR
TEC
Can Core
Receive Buffer
Control
Signals
Status
Signals
clkp
preset_n
Micro Processor
Interface
pms_can_n
p_read_n
TXPR
TXACK
TXCR
ABACK
RXPR
RFPR
MBIMR
UMSR
p_write_n
psize_n
pwait_can_n
MCR
IRR
GSR
IMR
pd
IrQs
scan_mode
16-bit
peripheral
bus
32-bit internal Bus System
pa
Mailbox Control
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
control0
LAFM
DATA
Mailbox 0 - 15 (RAM)
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
control1
Mailbox 0 - 15 (register)
Figure 22.1 RCAN-ET Architecture
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1039 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
Important: Although core of RCAN-ET is designed based on a 32-bit bus system, the whole
RCAN-ET including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord
(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,
LongWord access means the two consecutive accesses.
• Micro Processor Interface (MPI)
The MPI allows communication between the Renesas CPU and RCAN-ET’s
registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic
that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-ET so
that the RCAN-ET can automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
• Mailbox
The Mailboxes consists of RAM configured as message buffers and registers. There are 16
Mailboxes, and each mailbox has the following information.
⎯ CAN message control (identifier, rtr, ide,etc)
⎯ CAN message data (for CAN Data frames)
⎯ Local Acceptance Filter Mask for reception
⎯ CAN message control (dlc)
⎯ 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, AutoTransmission for Remote Request bit, New Message Control bit
• Mailbox Control
The Mailbox Control handles the following functions:
⎯ For received messages, compare the IDs and generate appropriate RAM addresses/data to
store messages from the CAN Interface into the Mailbox and set/clear appropriate registers
accordingly.
⎯ To transmit messages, RCAN-ET will run the internal arbitration to pick the correct
priority message, and load the message from the Mailbox into the Tx-buffer of the CAN
Interface and set/clear appropriate registers accordingly.
⎯ Arbitrates Mailbox accesses between the CPU and the Mailbox Control.
⎯ Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and
MBIMR.
Page 1040 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• CAN Interface
This block conforms to the requirements for a CAN Bus Data Link Controller which is
specified in Ref. [2, 4]. It fulfils all the functions of a standard DLC as specified by the OSI 7
Layer Reference model. This functional entity also provides the registers and the logic which
are specific to a given CAN bus, which includes the Receive Error Counter, Transmit Error
Counter, the Bit Configuration Registers and various useful Test Modes. This block also
contains functional entities to hold the data received and the data to be transmitted for the
CAN Data Link Controller.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1041 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.3
Programming Model - Overview
The purpose of this programming interface is to allow convenient, effective access to the CAN bus
for efficient message transfer. Please bear in mind that the user manual reports all settings allowed
by the RCAN-ET IP. Different use of RCAN-ET is not allowed.
22.3.1
Memory Map
The diagram of the memory map is shown below.
Bit 15
H'000
Bit 0
Master Control Register (MCR)
H'002
General Status Register(GSR)
H'004
Bit Configuration Register 1 (BCR1)
H'006
Bit Configuration Register 0 (BCR0)
H'008
H'0A4
Interrupt Mask Register (IMR)
Transmit Error Counter
(TEC)
H'020
Receive Error Counter
(REC)
H'100
Transmit Pending Register (TXPR1)
H'022
Transmit Pending Register (TXPR0)
H'02A
H'032
Bit 0
Interrupt Request Register (IRR)
H'00A
H'00C
Bit 15
H'0A0
Transmit Cancel Register (TXCR0)
Transmit Acknowledge Register (TXACK0)
Mailbox-0 Control 0
(STDID, EXTID, RTR, IDE)
H'104
LAFM
H'108
0
H'10A
2
H'10C
4
5
6
7
H'10E
1
3
Mailbox 0 Data (8 bytes)
H'110
Mailbox-0 Control 1 (NMC, MBC, DLC)
H'03A
Abort Acknowledge Register (ABACK0)
H'120
H'042
H'140
H'04A
H'052
H'05A
Mailbox-1 Control/LAFM/Data etc.
Receive Pending Register (RXPR0)
Remote Frame Pending Register (RFPR0)
H'160
Mailbox-2 Control/LAFM/Data etc.
Mailbox-3 Control/LAFM/Data etc.
Mailbox Interrupt Mask Register (MBIMR0)
Unread Message Status Register (UMSR0)
H'2E0
Mailbox-15 Control/LAFM/Data etc.
Figure 22.2 RCAN-ET Memory Map
The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed.
Page 1042 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.3.2
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Mailbox Structure
Mailboxes play a role as message buffers to transmit / receive CAN frames. Each Mailbox is
comprised of 3 identical storage fields that are 1): Message Control, 2): Local Acceptance Filter
Mask, 3): Message Data. The following table shows the address map for the control, LAFM, data
and addresses for each mailbox.
Address
Control0
LAFM
Data
Control1
Mailbox
4 bytes
4 bytes
8 bytes
2 bytes
0 (Receive Only)
100 – 103
104– 107
108 – 10F
110 – 111
1
120 – 123
124 – 127
128 – 12F
130 – 131
2
140 – 143
144 – 147
148 – 14F
150 – 151
3
160 – 163
164 - 167
168 – 16F
170 – 171
4
180 – 183
184 – 187
188 – 18F
190 – 191
5
1A0 – 1A3
1A4 – 1A7
1A8 – 1AF
1B0 – 1B1
6
1C0 – 1C3
1C4 – 1C7
1C8 – 1CF
1D0 – 1D1
7
1E0 – 1E3
1E4 – 1E7
1E8 – 1EF
1F0 – 1F1
8
200 – 203
204 – 207
208 – 20F
210 – 211
9
220 – 223
224 – 227
228 – 22F
230 – 231
10
240 – 243
244 – 247
248 – 24F
250 – 251
11
260 – 263
264 – 267
268 – 26F
270 – 271
12
280 – 283
284 – 287
288 – 28F
290 – 291
13
2A0 – 2A3
2A4 – 2A7
2A8 – 2AF
2B0 – 2B1
14
2C0 – 2C3
2C4 – 2C7
2C8 – 2CF
2D0 – 2D1
15
2E0 – 2E3
2E4 – 2E7
2E8 – 2EF
2F0 – 2F1
Mailbox-0 is a receive-only box, and all the other Mailboxes can operate as both receive and
transmit boxes, dependant upon the MBC (Mailbox Configuration) bits in the Message Control.
The following diagram shows the structure of a Mailbox in detail.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1043 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Table 22.1 Roles of Mailboxes
Tx
Rx
MB15-1
OK
OK
MB0
⎯
OK
MB0 (reception MB)
Byte: 8-bit access, Word: 16-bit access, LW (LongWord): 32-bit access
Address
H'100 + N*32
Data Bus
15
14
13
IDE
RTR
0
12
11
10
9
7
Access Size
6
5
4
3
2
1
EXTID[17:16]
STDID[10:0]
IDE_
LAFM
0
0
EXTID_LAFM[15:0]
H'106 + N*32
Word/LW
Word
EXTID_
LAFM[17:16]
STDID_LAFM[10:0]
Word
MSG_DATA_0 (first Rx Byte)
MSG_DATA_1
H'10A + N*32
MSG_DATA_2
MSG_DATA_3
Byte/Word
H'10C + N*32
MSG_DATA_4
MSG_DATA_5
Byte/Word/LW
H'110 + N*32
0
NMC
0
0
MBC[2:0]
0
0
0
0
6
5
4
LAFM
Byte/Word/LW
MSG_DATA_7
MSG_DATA_6
0
Control 0
Word/LW
H'108 + N*32
H'10E + N*32
Field Name
0
EXTID[15:0]
H'102 + N*32
H'104 + N*32
8
Data
Byte/Word
DLC[3:0]
Byte/Word
Control 1
Access Size
Field Name
MBC[1] is fixed to "1"
MB15-1 (MB for transmission/reception)
Address
H'100 + N*32
Data Bus
15
14
13
IDE
RTR
0
12
11
10
9
8
7
3
STDID[10:0]
2
1
0
EXTID[17:16]
Word/LW
Control 0
EXTID[15:0]
H'102 + N*32
H'104 + N*32
IDE_
LAFM
0
Word
EXTID_
LAFM[17:16]
STDID_LAFM[10:0]
0
EXTID_LAFM[15:0]
H'106 + N*32
Word/LW
LAFM
Word
H'108 + N*32
MSG_DATA_0 (first Rx/Tx Byte)
MSG_DATA_1
Byte/Word/LW
H'10A + N*32
MSG_DATA_2
MSG_DATA_3
Byte/Word
H'10C + N*32
MSG_DATA_4
MSG_DATA_5
Byte/Word/LW
H'10E + N*32
MSG_DATA_6
MSG_DATA_7
H'110 + N*32
0
0
NMC ATX DART
MBC[2:0]
0
0
0
0
Data
Byte/Word
DLC[3:0]
Byte/Word
Control 1
Figure 22.3 Mailbox-N Structure
Notes: 1. All bits shadowed in grey are reserved and must be written LOW. The value returned
by a read may not always be ‘0’ and should not be relied upon.
2. ATX and DART are not supported by Mailbox-0, and the MBC setting of Mailbox-0 is
limited.
3. ID Reorder (MCR15) can change the order of STDID, RTR, IDE and EXTID of both
message control and LAFM.
Page 1044 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Message Control Field
STDID[10:0]: These bits set the identifier (standard identifier) of data frames and remote frames.
EXTID[17:0]: These bits set the identifier (extended identifier) of data frames and remote frames.
RTR (Remote Transmission Request bit) : Used to distinguish between data frames and remote
frames. This bit is overwritten by received CAN Frames depending on Data Frames or Remote
Frames.
Important: Please note that, when ATX bit is set with the setting MBC=001(bin), the RTR bit
will never be set. When a Remote Frame is received, the CPU can be notified by the
corresponding RFPR set or IRR[2] (Remote Frame Request Interrupt), however, as RCAN-ET
needs to transmit the current message as a Data Frame, the RTR bit remains unchanged.
Important: In order to support automatic answer to remote frame when MBC=001(bin) is used
and ATX=1 the RTR flag must be programmed to zero to allow data frame to be transmitted.
Note: when a Mailbox is configured to send a remote frame request the DLC used for
transmission is the one stored into the Mailbox.
RTR
Description
0
Data frame
1
Remote frame
IDE (Identifier Extension bit) : Used to distinguish between the standard format and extended
format of CAN data frames and remote frames.
IDE
Description
0
Standard format
1
Extended format
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1045 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• Mailbox-0
Bit: 15
14
13
12
11
0
0
NMC
0
0
Initial value: 0
R/W: R
0
R
0
R/W
0
R
0
R
10
9
8
MBC[2:0]
1
R/W
7
6
5
4
0
0
0
0
3
2
1
0
DLC[3:0]
1
R/W
1
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
0
R
0
R
0
R
Note: MBC[1] of MB0 is always "1".
• Mailbox-15 to 1
Bit: 15
14
13
12
11
0
0
NMC
ATX
DART
Initial value: 0
R/W: R
0
R
0
R/W
0
R/W
0
R/W
10
MBC[2:0]
1
R/W
1
R/W
1
R/W
DLC[3:0]
0
R/W
0
R/W
0
R/W
0
R/W
NMC (New Message Control): When this bit is set to ‘0’, the Mailbox of which the RXPR or
RFPR bit is already set does not store the new message but maintains the old one and sets the
UMSR correspondent bit. When this bit is set to ‘1’, the Mailbox of which the RXPR or RFPR bit
is already set overwrites with the new message and sets the UMSR correspondent bit.
Important: Please note that if a remote frame is overwritten with a data frame or vice versa could
be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this
case the RTR bit within the Mailbox Control Field should be relied upon.
NMC
Description
0
Overrun mode (Initial value)
1
Overwrite mode
ATX (Automatic Transmission of Data Frame): When this bit is set to ‘1’ and a Remote Frame
is received into the Mailbox DLC is stored. Then, a Data Frame is transmitted from the same
Mailbox using the current contents of the message data and updated DLC by setting the
corresponding TXPR automatically. The scheduling of transmission is still governed by ID
priority or Mailbox priority as configured with the Message Transmission Priority control bit
(MCR.2). In order to use this function, MBC[2:0] needs to be programmed to be ‘001’ (Bin).
When a transmission is performed by this function, the DLC (Data Length Code) to be used is the
one that has been received. Application needs to guarantee that the DLC of the remote frame
correspond to the DLC of the data frame requested.
Important: When ATX is used and MBC=001 (Bin) the filter for the IDE bit cannot be used since
ID of remote frame has to be exactly the same as that of data frame as the reply message.
Page 1046 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Important: Please note that, when this function is used, the RTR bit will never be set despite
receiving a Remote Frame. When a Remote Frame is received, the CPU will be notified by the
corresponding RFPR set, however, as RCAN-ET needs to transmit the current message as a Data
Frame, the RTR bit remains unchanged.
Important: Please note that in case of overrun condition (UMSR flag set when the Mailbox has
its NMC = 0) the message received is discarded. In case a remote frame is causing overrun into a
Mailbox configured with ATX = 1, the transmission of the corresponding data frame may be
triggered only if the related RFPR flag is cleared by the CPU when the UMSR flag is set. In such
case RFPR flag would get set again.
ATX
Description
0
Automatic Transmission of Data Frame disabled (Initial value)
1
Automatic Transmission of Data Frame enabled
DART (Disable Automatic Re-Transmission): When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the
CAN bus. In effect, when this function is used, the corresponding TXCR bit is automatically set at
the start of transmission. When this bit is set to ‘0’, RCAN-ET tries to transmit the message as
many times as required until it is successfully transmitted or it is cancelled by the TXCR.
DART
Description
0
Re-transmission enabled (Initial value)
1
Re-Transmission disabled
MBC[2:0] (Mailbox Configuration): These bits configure the nature of each Mailbox as follows.
When MBC=111 (Bin), the Mailbox is inactive, i.e., it does not receive or transmit a message
regardless of TXPR or other settings. The MBC=’110’, ‘101’ and ‘100’ settings are prohibited.
When the MBC is set to any other value, the LAFM field becomes available. Please don't set
TXPR when MBC is set as reception. There is no hardware protection, and TXPR remains set.
MBC[1] of Mailbox-0 is fixed to "1" by hardware. This is to ensure that MB0 cannot be
configured to transmit Messages.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1047 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Data
Frame
MBC[2] MBC[1] MBC[0] Transmit
Remote
Frame
Transmit
Data
Frame
Receive
Remote
Frame
Receive
Remarks
0
0
0
Yes
Yes
No
No
•
Not allowed for Mailbox-0
0
0
1
Yes
Yes
No
Yes
•
Can be used with ATX*
•
Not allowed for Mailbox-0
•
LAFM can be used
•
Allowed for Mailbox-0
•
LAFM can be used
•
Allowed for Mailbox-0
•
LAFM can be used
0
1
0
No
No
Yes
0
1
1
No
1
0
0
Setting prohibited
1
0
1
Setting prohibited
1
1
0
Setting prohibited
1
1
1
Mailbox inactive (Initial value)
Notes: *
No
Yes
Yes
No
In order to support automatic retransmission, RTR shall be "0" when MBC=001(bin) and
ATX=1.
When ATX=1 is used the filter for IDE must not be used
DLC[3:0] (Data Length Code): These bits encode the number of data bytes from 0,1, 2, … 8 that
will be transmitted in a data frame. Please note that when a remote frame request is transmitted the
DLC value to be used must be the same as the DLC of the data frame that is requested.
DLC[3]
DLC[2]
DLC[1]
DLC[0]
Description
0
0
0
0
Data Length = 0 bytes (Initial value)
0
0
0
1
Data Length = 1 byte
0
0
1
0
Data Length = 2 bytes
0
0
1
1
Data Length = 3 bytes
0
1
0
0
Data Length = 4 bytes
0
1
0
1
Data Length = 5 bytes
0
1
1
0
Data Length = 6 bytes
0
1
1
1
Data Length = 7 bytes
1
x
x
x
Data Length = 8 bytes
Page 1048 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Local Acceptance Filter Mask (LAFM)
This area is used as Local Acceptance Filter Mask (LAFM) for receive boxes.
LAFM: When MBC is set to 001, 010, 011 (Bin), this field is used as LAFM Field. It allows a
Mailbox to accept more than one identifier. The LAFM is comprised of two 16-bit read/write
areas as follows.
15
IDE_
H'104 + N*32 LAFM
14
13
0
0
12
11
10
9
8
7
6
5
4
3
2
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
H'106 + N*32
1
0
EXTID_
LAFM[17:16]
Word/LW
LAFM Field
Word
Figure 22.4 Acceptance Filter
If a bit is set in the LAFM, then the corresponding bit of a received CAN identifier is ignored
when the RCAN-ET searches a Mailbox with the matching CAN identifier. If the bit is cleared,
then the corresponding bit of a received CAN identifier must match to the STDID/IDE/EXTID set
in the mailbox to be stored. The structure of the LAFM is same as the message control in a
Mailbox. If this function is not required, it must be filled with ‘0’.
Important: RCAN-ET starts to find a matching identifier from Mailbox-15 down to Mailbox-0.
As soon as RCAN-ET finds one matching, it stops the search. The message will be stored or not
depending on the NMC and RXPR/RFPR flags. This means that, even using LAFM, a received
message can only be stored into 1 Mailbox.
Important: When a message is received and a matching Mailbox is found, the whole message is
stored into the Mailbox. This means that, if the LAFM is used, the STDID, RTR, IDE and EXTID
may differ to the ones originally set as they are updated with the STDID, RTR, IDE and EXTID of
the received message.
STD_LAFM[10:0] — Filter mask bits for the CAN base identifier [10:0] bits.
STD_LAFM[10:0]
Description
0
Corresponding STD_ID bit is cared
1
Corresponding STD_ID bit is "don't cared"
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1049 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
EXT_LAFM[17:0] — Filter mask bits for the CAN Extended identifier [17:0] bits.
EXT_LAFM[17:0]
Description
0
Corresponding EXT_ID bit is cared
1
Corresponding EXT_ID bit is "don't cared"
IDE_LAFM — Filter mask bit for the CAN IDE bit.
IDE_LAFM
Description
0
Corresponding IDE_ID bit is cared
1
Corresponding IDE_ID bit is "don't cared"
(3)
Message Data Fields
Storage for the CAN message data that is transmitted or received. MSG_DATA[0] corresponds to
the first data byte that is transmitted or received. The bit order on the CAN bus is bit 7 through to
bit 0.
Page 1050 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.3.3
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
RCAN-ET Control Registers
The following sections describe RCAN-ET control registers. The address is mapped as follow.
Important: These registers can only be accessed in Word size (16-bit).
Description
Address
Name
Access Size (bits)
Master Control Register
000
MCR
Word
General Status Register
002
GSR
Word
Bit Configuration Register 1
004
BCR1
Word
Bit Configuration Register 0
006
BCR0
Word
Interrupt Request Register
008
IRR
Word
Interrupt Mask Register
00A
IMR
Word
Error Counter Register
00C
TEC/REC
Word
Figure 22.5 RCAN-ET Control Registers
(1)
Master Control Register (MCR)
The Master Control Register (MCR) is a 16-bit read/write register that controls RCAN-ET.
• MCR (Address = H'000)
Bit: 15
14
MCR15 MCR14
Initial value: 1
R/W: R/W
0
R/W
13
12
11
-
-
-
0
R
0
R
0
R
10
9
0
R/W
0
R/W
7
6
5
4
3
2
1
0
MCR7
MCR6
MCR5
-
-
MCR2
MCR1
MCR0
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
1
R/W
8
TST[2:0]
0
R/W
Bit 15 — ID Reorder (MCR15): This bit changes the order of STDID, RTR, IDE and EXTID of
both message control and LAFM.
Bit15 : MCR15
Description
0
RCAN-ET is the same as HCAN2
1
RCAN-ET is not the same as HCAN2 (Initial value)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1051 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
MCR15 (ID Reorder) = 0
15
H'100 + N*32
14
13
12
11
10
0
9
7
6
5
4
3
2
RTR
IDE
EXTID[17:16]
1
0
0
IDE_
LAFM
EXTID_LAFM
[17:16]
Word/LW
Control 0
H'102 + N*32
H'104 + N*32
8
STDID[10:0]
Word
EXTID[15:0]
STDID_LAFM[10:0]
0
Word/LW
LAFM Field
Word
EXTID_LAFM[15:0]
H'106 + N*32
MCR15 (ID Reorder) = 1
H'100 + N*32
15
14
13
IDE
RTR
0
12
11
10
8
7
6
5
4
3
STDID[10:0]
2
1
0
EXTID[17:16]
Word/LW
Control 0
H'102 + N*32
H'104 + N*32
9
Word
EXTID[15:0]
IDE_
LAFM
0
0
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
H'106 + N*32
EXTID_LAFM
[17:16]
Word/LW
LAFM Field
Word
Figure 22.6 ID Reorder
This bit can be modified only in reset mode.
Bit 14 — Auto Halt Bus Off (MCR14): If both this bit and MCR6 are set, MCR1 is
automatically set as soon as RCAN-ET enters BusOff.
Bit14 : MCR14
Description
0
RCAN-ET remains in BusOff for normal recovery sequence (128 x 11
Recessive Bits) (Initial value)
1
RCAN-ET moves directly into Halt Mode after it enters BusOff if MCR6 is
set.
This bit can be modified only in reset mode.
Bit 13 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 12 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 11 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 10 - 8 — Test Mode (TST[2:0]): This bit enables/disables the test modes. Please note that
before activating the Test Mode it is requested to move RCAN-ET into Halt mode or Reset mode.
This is to avoid that the transition to Test Mode could affect a transmission/reception in progress.
For details, please refer to section 22.4.1, Test Mode Settings.
Please note that the test modes are allowed only for diagnosis and tests and not when RCAN-ET is
used in normal operation.
Page 1052 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit10:
TST2
Bit9:
TST1
Bit8:
TST0
Description
0
0
0
Normal Mode (initial value)
0
0
1
Listen-Only Mode (Receive-Only Mode)
0
1
0
Self Test Mode 1 (External)
0
1
1
Self Test Mode 2 (Internal)
1
0
0
Write Error Counter
1
0
1
Error Passive Mode
1
1
0
setting prohibited
1
1
1
setting prohibited
Bit 7 — Auto-wake Mode (MCR7): MCR7 enables or disables the Auto-wake mode. If this bit is
set, the RCAN-ET automatically cancels the sleep mode (MCR5) by detecting CAN bus activity
(dominant bit). If MCR7 is cleared the RCAN-ET does not automatically cancel the sleep mode.
RCAN-ET cannot store the message that wakes it up.
Note: MCR7 cannot be modified while in sleep mode.
Bit7 : MCR7
Description
0
Auto-wake by CAN bus activity disabled (Initial value)
1
Auto-wake by CAN bus activity enabled
Bit 6 — Halt during Bus Off (MCR6): MCR6 enables or disables entering Halt mode
immediately when MCR1 is set during Bus Off. This bit can be modified only in Reset or Halt
mode. Please note that when Halt is entered in Bus Off the CAN engine is also recovering
immediately to Error Active mode.
Bit6 : MCR6
Description
0
If MCR[1] is set, RCAN-ET will not enter Halt mode during Bus Off but wait
up to end of recovery sequence (Initial value)
1
Enter Halt mode immediately during Bus Off if MCR[1] or MCR[14] are
asserted.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1053 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
Bit 5 — Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while
RCAN-ET is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after
entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep
mode. This mode will be exited in two ways:
1. by writing a '0' to this bit position,
2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus.
If Auto wake up mode is disabled, RCAN-ET will ignore all CAN bus activities until the sleep
mode is terminated. When leaving this mode the RCAN-ET will synchronise to the CAN bus (by
checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2
method is used, RCAN-ET will miss the first message to receive. CAN transceivers stand-by
mode will also be unable to cope with the first message when exiting stand by mode, and the S/W
needs to be designed in this manner.
In sleep mode only the following registers can be accessed: MCR, GSR, IRR and IMR.
Important: RCAN-ET is required to be in Halt mode before requesting to enter in Sleep mode.
That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts
are cleared RCAN-ET must leave the Halt mode and enter Sleep mode simultaneously (by writing
MCR[5]=1 and MCR[1]=0 at the same time).
Bit 5 : MCR5
Description
0
RCAN-ET sleep mode released (Initial value)
1
Transition to RCAN-ET sleep mode enabled
Bit 4 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 3 — Reserved. The written value should always be '0' and the returned value is '0'.
Bit 2 — Message Transmission Priority (MCR2): MCR2 selects the order of transmission for
pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in
the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-15 as
the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for
transmission).
Page 1054 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by
running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE
bit + EXTID (if IDE=1) + RTR bit) with the lowest digital value and is transmitted first. The
internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same
way as the arbitration on the CAN Bus between two CAN nodes starting transmission at the same
time).
This bit can be modified only in Reset or Halt mode.
Bit 2 : MCR2
Description
0
Transmission order determined by message identifier priority (Initial value)
1
Transmission order determined by mailbox number priority (Mailbox-15 →
Mailbox-1)
Bit 1—Halt Request (MCR1): Setting the MCR1 bit causes the CAN controller to complete its
current operation and then enter Halt mode (where it is cut off from the CAN bus). The RCAN-ET
remains in Halt Mode until the MCR1 is cleared. During the Halt mode, the CAN Interface does
not join the CAN bus activity and does not store messages or transmit messages. All the user
registers (including Mailbox contents and TEC/REC) remain unchanged with the exception of
IRR0 and GSR4 which are used to notify the halt status itself. If the CAN bus is in idle or
intermission state regardless of MCR6, RCAN-ET will enter Halt Mode within one Bit Time. If
MCR6 is set, a halt request during Bus Off will be also processed within one Bit Time. Otherwise
the full Bus Off recovery sequence will be performed beforehand. Entering the Halt Mode can be
notified by IRR0 and GSR4.
If both MCR14 and MCR6 are set, MCR1 is automatically set as soon as RCAN-ET enters
BusOff.
In the Halt mode, the RCAN-ET configuration can be modified with the exception of the Bit
Timing setting, as it does not join the bus activity. MCR[1] has to be cleared by writing a ‘0’ in
order to re-join the CAN bus. After this bit has been cleared, RCAN-ET waits until it detects 11
recessive bits, and then joins the CAN bus.
Note: After issuing a Halt request the CPU is not allowed to set TXPR or TXCR or clear MCR1
until the transition to Halt mode is completed (notified by IRR0 and GSR4). After MCR1
is set this can be cleared only after entering Halt mode or through a reset operation (SW or
HW).
Note: Transition into or recovery from HALT mode, is only possible if the BCR1 and BCR0
registers are configured to a proper Baud Rate.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1055 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit 1 : MCR1
Description
0
Clear Halt request (Initial value)
1
Halt mode transition request
SH7280 Group, SH7243 Group
Bit 0 — Reset Request (MCR0): Controls resetting of the RCAN-ET module. When this bit is
changed from ‘0’ to ‘1’ the RCAN-ET controller enters its reset routine, re-initialising the internal
logic, which then sets GSR3 and IRR0 to notify the reset mode. During a re-initialisation, all user
registers are initialised.
RCAN-ET can be re-configured while this bit is set. This bit has to be cleared by writing a ‘0’ to
join the CAN bus. After this bit is cleared, the RCAN-ET module waits until it detects 11
recessive bits, and then joins the CAN bus. The Baud Rate needs to be set up to a proper value in
order to sample the value on the CAN Bus.
After Power On Reset, this bit and GSR3 are always set. This means that a reset request has been
made and RCAN-ET needs to be configured.
The Reset Request is equivalent to a Power On Reset but controlled by Software.
Bit 0 : MCR0
Description
0
Clear Reset Request
1
CAN Interface reset mode transition request (Initial value)
Page 1056 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
General Status Register (GSR)
The General Status Register (GSR) is a 16-bit read-only register that indicates the status of
RCAN-ET.
• GSR (Address = H'002)
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
GSR5
GSR4
GSR3
GSR2
GSR1
GSR0
Initial value: 0
R/W: R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
Bits 15 to 6: Reserved. The written value should always be '0' and the returned value is '0'.
Bit 5 — Error Passive Status Bit (GSR5): Indicates whether the CAN Interface is in Error
Passive or not. This bit will be set high as soon as the RCAN-ET enters the Error Passive state and
is cleared when the module enters again the Error Active state (this means the GSR5 will stay high
during Error Passive and during Bus Off). Consequently to find out the correct state both GSR5
and GSR0 must be considered.
Bit 5 : GSR5
0
Description
RCAN-ET is not in Error Passive or in Bus Off status (Initial value)
[Reset condition] RCAN-ET is in Error Active state
1
RCAN-ET is in Error Passive (if GSR0=0) or Bus Off (if GSR0=1)
[Setting condition] When TEC ≥ 128 or REC ≥ 128 or if Error Passive Test
Mode is selected
Bit 4 — Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep
state or not. Please note that the clearing time of this flag is not the same as the setting time of
IRR12.
Please note that this flag reflects the status of the CAN engine and not of the full RCAN-ET IP.
RCAN-ET exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits
sleep mode only after two additional transmission clocks on the CAN Bus.
Bit 4 : GSR4
Description
0
RCAN-ET is not in the Halt state or Sleep state (Initial value)
1
Halt mode (if MCR1=1) or Sleep mode (if MCR5=1)
[Setting condition] If MCR1 is set and the CAN bus is either in intermission or
idle or MCR5 is set and RCAN-ET is in the halt mode or RCAN-ET is moving
to Bus Off when MCR14 and MCR6 are both set
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1057 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
Bit 3 — Reset Status Bit (GSR3): Indicates whether the RCAN-ET is in the reset state or not.
Bit 3 : GSR3
Description
0
RCAN-ET is not in the reset state
1
Reset state (Initial value)
[Setting condition] After an RCAN-ET internal reset (due to SW or HW reset)
Bit 2 — Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if the
RCAN-ET is in Bus Off or transmitting a message or an error/overload flag due to error detected
during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK
is set at the 7th bit of End Of Frame. GSR2 is set at the 3rd bit of intermission if there are no more
messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset or halt
transition.
Bit 2 : GSR2
Description
0
RCAN-ET is in Bus Off or a transmission is in progress
1
[Setting condition] Not in Bus Off and no transmission in progress (Initial
value)
Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning.
Bit 1 : GSR1
Description
0
[Reset condition] When (TEC < 96 and REC < 96) or Bus Off (Initial value)
1
[Setting condition] When 96 ≤ TEC < 256 or 96 ≤ REC < 256
Note: REC is incremented during Bus Off to count the recurrences of 11 recessive bits as
requested by the Bus Off recovery sequence. However the flag GSR1 is not set in Bus Off.
Bit 0—Bus Off Flag (GSR0): Flag that indicates that RCAN-ET is in the bus off state.
Bit 0 : GSR0
Description
0
[Reset condition] Recovery from bus off state or after a HW or SW reset
(Initial value)
1
[Setting condition] When TEC ≥ 256 (bus off state)
Note: Only the lower 8 bits of TEC are accessible from the user interface. The 9th bit is
equivalent to GSR0.
Page 1058 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit Configuration Register (BCR0, BCR1)
The bit configuration registers (BCR0 and BCR1) are 2 X 16-bit read/write register that are used
to set CAN bit timing parameters and the baud rate pre-scaler for the CAN Interface.
The Time quanta is defined as:
Timequanta =
2 * BRP
fclk
Where: BRP (Baud Rate Pre-scaler) is the value stored in BCR0 incremented by 1 and fclk is the
used peripheral bus frequency.
• BCR1 (Address = H'004)
Bit: 15
14
13
12
11
TSG1[3:0]
Initial value: 0
R/W: R/W
0
R/W
0
R/W
10
-
0
R/W
0
R
9
8
TSG2[2:0]
0
R/W
0
R/W
0
R/W
7
6
5
4
3
2
1
0
-
-
SJW[1:0]
-
-
-
BSP
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
Bits 15 to 12 — Time Segment 1 (TSG1[3:0] = BCR1[15:12]): These bits are used to set the
segment TSEG1 (= PRSEG + PHSEG1) to compensate for edges on the CAN Bus with a positive
phase error. A value from 4 to 16 time quanta can be set.
Bit 15: Bit 14: Bit 13: Bit 12:
TSG1[3] TSG1[2] TSG1[1] TSG1[0] Description
0
0
0
0
Setting prohibited (Initial value)
0
0
0
1
Setting prohibited
0
0
1
0
Setting prohibited
0
0
1
1
PRSEG + PHSEG1 = 4 time quanta
0
1
0
0
PRSEG + PHSEG1 = 5 time quanta
:
:
:
:
:
:
:
:
:
:
1
1
1
1
PRSEG + PHSEG1 = 16 time quanta
Bit 11 : Reserved. The written value should always be '0' and the returned value is '0'.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1059 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
Bits 10 to 8 — Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the
segment TSEG2 (=PHSEG2) to compensate for edges on the CAN Bus with a negative phase
error. A value from 2 to 8 time quanta can be set as shown below.
Bit 10: Bit 9:
Bit 8:
TSG2[2] TSG2[1] TSG2[0] Description
0
0
0
Setting prohibited (Initial value)
0
0
1
PHSEG2 = 2 time quanta (conditionally prohibited)
0
1
0
PHSEG2 = 3 time quanta
0
1
1
PHSEG2 = 4 time quanta
1
0
0
PHSEG2 = 5 time quanta
1
0
1
PHSEG2 = 6 time quanta
1
1
0
PHSEG2 = 7 time quanta
1
1
1
PHSEG2 = 8 time quanta
Bits 7 and 6 : Reserved. The written value should always be '0' and the returned value is '0'.
Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the
synchronisation jump width.
Bit 5:
SJW[1]
Bit 4:
SJW[0]
Description
0
0
Synchronisation Jump width = 1 time quantum (Initial value)
0
1
Synchronisation Jump width = 2 time quanta
1
0
Synchronisation Jump width = 3 time quanta
1
1
Synchronisation Jump width = 4 time quanta
Bits 3 to 1 : Reserved. The written value should always be '0' and the returned value is '0'.
Bit 0 — Bit Sample Point (BSP = BCR1[0]): Sets the point at which data is sampled.
Bit 0 : BSP
Description
0
Bit sampling at one point (end of time segment 1) (Initial value)
1
Bit sampling at three points (rising edge of the last three clock cycles of
PHSEG1)
Page 1060 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• BCR0 (Address = H'006)
Bit: 15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
-
Initial value: 0
R/W: R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
7
6
5
4
3
2
1
0
0
R/W
0
R/W
0
R/W
BRP[7:0]
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bits 8 to 15 : Reserved. The written value should always be '0' and the returned value is '0'.
Bits 7 to 0—Baud Rate Pre-scale (BRP[7:0] = BCR0 [7:0]): These bits are used to define the
peripheral bus clock periods contained in a Time Quantum.
Bit 7:
BRP[7]
Bit 6:
BRP[6]
Bit 5:
BRP[5]
Bit 4:
BRP[4]
Bit 3:
BRP[3]
Bit 2:
BRP[2]
Bit 1:
BRP[1]
Bit 0:
BRP[0]
0
0
0
0
0
0
0
0
2 × peripheral bus clock
(Initial value)
0
0
0
0
0
0
0
1
4 × peripheral bus clock
0
0
0
0
0
0
1
0
6 × peripheral bus clock
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
2 × (register value+1) ×
peripheral bus clock
0
1
1
1
1
1
1
1
512 × peripheral bus clock
Description
• Requirements of Bit Configuration Register
1-bit time (8-25 quanta)
SYNC_SEG
1
PRSEG
PHSEG1
PHSEG2
TSEG1
TSEG2
4-16
2-8
Quantum
SYNC_SEG: Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit
edge transitions occur in this segment.)
PRSEG:
Segment for compensating for physical delay between networks.
PHSEG1:
Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronisation (resynchronisation) is established.)
PHSEG2:
Buffer segment for correcting phase drift (negative). (This segment is shortened
when synchronisation (resynchronisation) is established)
TSEG1:
TSG1 + 1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1061 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
TSEG2:
SH7280 Group, SH7243 Group
TSG2 + 1
The RCAN-ET Bit Rate Calculation is:
Bit Rate =
fclk
2 * (BRP + 1) * (TSEG1 + TSEG2 + 1)
where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1
and TSG2 register values. The ‘+ 1’ in the above formula is for the Sync-Seg which duration is 1
time quanta.
fCLK = Peripheral Clock
BCR Setting Constraints
TSEG1min > TSEG2 ≥ SJWmax
(SJW = 1 to 4)
8 ≤ TSEG1 + TSEG2 + 1 ≤ 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)
TSEG2 ≥ 2
These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the
Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows
that there is no allowed combination of TSEG1 and TSEG2.
Page 1062 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
001
010
011
100
101
110
111
TSG2
2
3
4
5
6
7
8
TSEG2
TSG1
TSEG1
0011
4
No
1-3
No
No
No
No
No
0100
5
1-2
1-3
1-4
No
No
No
No
0101
6
1-2
1-3
1-4
1-4
No
No
No
0110
7
1-2
1-3
1-4
1-4
1-4
No
No
0111
8
1-2
1-3
1-4
1-4
1-4
1-4
No
1000
9
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1001
10
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1010
11
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1011
12
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1100
13
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1101
14
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1110
15
1-2
1-3
1-4
1-4
1-4
1-4
1-4
1111
16
1-2
1-3
1-4
1-4
1-4
1-4
1-4
Example 1: To have a Bit rate of 500 Kbps with a frequency of fclk = 40 MHz it is possible to set:
BRP = 43, TSEG1 = 6, TSEG2 = 3.
Then the configuration to write is BCR1 = 5200 and BCR0 = 0003.
Example 2: To have a Bit rate of 250 Kps with a frequency of 35 MHz it is possible to set:
BPR = 4, TSEG1 = 8, TSEG2 = 5.
Then the configuration to write is BCR1 = 7400 and BCR0 = 0004.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1063 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
(4)
Interrupt Request Register (IRR)
The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the
various interrupt sources.
• IRR (Address = H'008)
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
IRR13
IRR12
-
-
IRR9
IRR8
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0
Initial value: 0
R/W: R
0
R
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
1
R/W
Bits 15 to 14: Reserved.
Bit 13 - Message Error Interrupt (IRR13): this interrupt indicates that:
• A message error has occurred when in test mode.
• Note: If a Message Overload condition occurs when in Test Mode, then this bit will not be set.
When not in test mode this interrupt is inactive.
Bit 13: IRR13
Description
0
message error has not occurred in test mode (Initial value)
[Clearing condition] Writing 1
1
[Setting condition] message error has occurred in test mode
Bit 12 – Bus activity while in sleep mode (IRR12): IRR12 indicates that a CAN bus activity is
present. While the RCAN-ET is in sleep mode and a dominant bit is detected on the CAN bus, this
bit is set. This interrupt is cleared by writing a '1' to this bit position. Writing a '0' has no effect. If
auto wakeup is not used and this interrupt is not requested it needs to be disabled by the related
interrupt mask register. If auto wake up is not used and this interrupt is requested it should be
cleared only after recovering from sleep mode. This is to avoid that a new falling edge of the
reception line causes the interrupt to get set again.
Please note that the setting time of this interrupt is different from the clearing time of GSR4.
Bit 12: IRR12
Description
0
bus idle state (Initial value)
[Clearing condition] Writing 1
1
Page 1064 of 1778
[Setting condition] dominant bit level detection on the Rx line while in sleep
mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bits 11 to 10: Reserved
Bit 9 – Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has
been received but the existing message in the matching Mailbox has not been read as the
corresponding RXPR or RFPR is already set to ‘1’ and not yet cleared by the CPU. The received
message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message
Control) bit. This bit is cleared when all bit in UMSR (Unread Message Status Register) are cleared
(by writing ‘1’) or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set . It is also
cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position
has no effect.
Bit 9: IRR9
0
Description
No pending notification of message overrun/overwrite
[Clearing condition] Clearing of all bit in UMSR/setting MBIMR for all UMSR
set (initial value)
1
A receive message has been discarded due to overrun condition or a
message has been overwritten
[Setting condition] Message is received while the corresponding RXPR
and/or RFPR =1 and MBIMR =0
Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for
transmission has been successfully sent (corresponding TXACK flag is set) or has been
successfully aborted (corresponding ABACK flag is set). The related TXPR is also cleared and
this mailbox is now ready to accept a new message data for the next transmission. In effect, this
bit is set by an OR’ed signal of the TXACK and ABACK bits not masked by the corresponding
MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and ABACK bits
are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR.
Writing to this bit position has no effect.
Bit 8: IRR8
Description
0
Messages set for transmission or transmission cancellation request NOT
progressed. (Initial value)
[Clearing Condition] All the TXACK and ABACK bits are cleared/setting
MBIMR for all TXACK and ABACK set
1
Message has been transmitted or aborted, and new message can be stored
[Setting condition]
When one of the TXPR bits is cleared by completion of transmission or
completion of transmission abort, i.e., when a TXACK or ABACK bit is set (if
MBIMR=0).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1065 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
Bit 7 - Overload Frame (IRR7): Flag indicating that the RCAN-ET has detected a condition that
should initiate the transmission of an overload frame. Note that on the condition of transmission
being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7
will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0'
has no effect.
Bit 7: IRR7
Description
0
[Clearing condition] Writing 1 (Initial value)
1
[Setting conditions] Overload condition detected
Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when RCAN-ET enters the Bus-off state or
when RCAN-ET leaves Bus-off and returns to Error-Active. The cause therefore is the existing
condition TEC ≥ 256 at the node or the end of the Bus-off recovery sequence (128X11
consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit
remains set even if the RCAN-ET node leaves the bus-off condition, and needs to be explicitly
cleared by S/W. The S/W is expected to read the GSR0 to judge whether RCAN-ET is in the busoff or error active status. It is cleared by writing a '1' to this bit position even if the node is still
bus-off. Writing a '0' has no effect.
Bit 6: IRR6
Description
0
[Clearing condition] Writing 1 (Initial value)
1
Enter Bus off state caused by transmit error or Error Active state returning
from Bus-off
[Setting condition] When TEC becomes ≥ 256 or End of Bus-off after 128X11
consecutive recessive bits or transition from Bus Off to Halt
Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state
caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is
reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node
may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge
whether RCAN-ET is in Error Passive or Bus Off status.
Bit 5: IRR5
Description
0
[Clearing condition] Writing 1 (Initial value)
1
Error passive state caused by transmit/receive error
[Setting condition] When TEC ≥ 128 or REC ≥ 128 or Error Passive test
mode is used
Page 1066 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit 4 - Receive Error Counter Warning Interrupt Flag (IRR4): This bit becomes set if the
receive error counter (REC) reaches a value greater than 95 when RCAN-ET is not in the Bus Off
status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
Bit 4: IRR4
Description
0
[Clearing condition] Writing 1 (Initial value)
1
Error warning state caused by receive error
[Setting condition] When REC ≥ 96 and RCAN-ET is not in Bus Off
Bit 3 - Transmit Error Counter Warning Interrupt Flag (IRR3): This bit becomes set if the
transmit error counter (TEC) reaches a value greater than 95. The interrupt is reset by writing a '1'
to this bit position, writing '0' has no effect.
Bit 3: IRR3
Description
0
[Clearing condition] Writing 1 (Initial value)
1
Error warning state caused by transmit error
[Setting condition] When TEC ≥ 96
Bit 2 - Remote Frame Request Interrupt Flag (IRR2): flag indicating that a remote frame has
been received in a mailbox. This bit is set if at least one receive mailbox, with related MBIMR not
set, contains a remote frame transmission request. This bit is automatically cleared when all bits in
the Remote Frame Receive Pending Register (RFPR), are cleared. It is also cleared by writing a '1'
to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
Bit 2: IRR2
Description
0
[Clearing condition] Clearing of all bits in RFPR (Initial value)
1
at least one remote request is pending
[Setting condition] When remote frame is received and the corresponding
MBIMR = 0
Bit 1 – Data Frame Received Interrupt Flag (IRR1): IRR1 indicates that there are pending Data
Frames received. If this bit is set at least one receive mailbox contains a pending message. This bit
is cleared when all bits in the Data Frame Receive Pending Register (RXPR) are cleared, i.e. there
is no pending message in any receiving mailbox. It is in effect a logical OR of the RXPR flags
from each configured receive mailbox with related MBIMR not set. It is also cleared by writing a
'1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1067 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
SH7280 Group, SH7243 Group
Bit 1: IRR1
Description
0
[Clearing condition] Clearing of all bits in RXPR (Initial value)
1
Data frame received and stored in Mailbox
[Setting condition] When data is received and the corresponding MBIMR = 0
Bit 0 – Reset/Halt/Sleep Interrupt Flag (IRR0): This flag can get set for three different reasons.
It can indicate that:
1. Reset mode has been entered after a SW (MCR0) or HW reset
2. Halt mode has been entered after a Halt request (MCR1)
3. Sleep mode has been entered after a sleep request (MCR5) has been made while in Halt mode.
The GSR may be read after this bit is set to determine which state RCAN-ET is in.
Important : When a Sleep mode request needs to be made, the Halt mode must be used
beforehand. Please refer to the MCR5 description and figure 22.9.
IRR0 is set by the transition from "0" to "1" of GSR3 or GSR4 or by transition from Halt mode to
Sleep mode. So, IRR0 is not set if RCAN-ET enters Halt mode again right after exiting from Halt
mode, without GSR4 being cleared. Similarly, IRR0 is not set by direct transition from Sleep
mode to Halt Request. At the transition from Halt/Sleep mode to Transition/Reception, clearing
GSR4 needs (one-bit time - TSEG2) to (one-bit time * 2 - TSEG2).
In the case of Reset mode, IRR0 is set, however, the interrupt to the CPU is not asserted since
IMR0 is automatically set by initialisation.
Bit 0: IRR0
Description
0
[Clearing condition] Writing 1
1
Transition to S/W reset mode or transition to halt mode or transition to sleep
mode (Initial value)
[Setting condition] When reset/halt/sleep transition is completed after a reset
(MCR0 or HW) or Halt mode (MCR1) or Sleep mode (MCR5) is requested
Page 1068 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(5)
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Interrupt Mask Register (IMR)
The interrupt mask register is a 16 bit register that protects all corresponding interrupts in the
Interrupt Request Register (IRR) from generating an output signal on the IRQ. An interrupt
request is masked if the corresponding bit position is set to '1'. This register can be read or written
at any time. The IMR directly controls the generation of IRQ, but does not prevent the setting of
the corresponding bit in the IRR.
• IMR (Address = H'00A)
Bit: 15
14
13
12
11
10
IMR15 IMR14 IMR13 IMR12 IMR11 IMR10
Initial value: 1
R/W: R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
9
8
7
6
5
4
3
2
1
0
IMR9
IMR8
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1
IMR0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Bit 15 to 0: Maskable interrupt sources corresponding to IRR[15:0] respectively. When a bit is
set, the interrupt signal is not generated, although setting the corresponding IRR bit is still
performed.
Bit[15:0]: IMRn
Description
0
Corresponding IRR is not masked (IRQ is generated for interrupt conditions)
1
Corresponding interrupt of IRR is masked (Initial value)
(6)
Transmit Error Counter (TEC) and Receive Error Counter (REC)
The Transmit Error Counter (TEC) and Receive Error Counter (REC) is a 16-bit read/(write)
register that functions as a counter indicating the number of transmit/receive message errors on the
CAN Interface. The count value is stipulated in the CAN protocol specification Refs. [1], [2], [3]
and [4]. When not in (Write Error Counter) test mode this register is read only, and can only be
modified by the CAN Interface. This register can be cleared by a Reset request (MCR0) or
entering to bus off.
In Write Error Counter test mode (i.e. TST[2:0] = 3'b100), it is possible to write to this register.
The same value can only be written to TEC/REC, and the value written into TEC is set to TEC
and REC. When writing to this register, RCAN-ET needs to be put into Halt Mode. This feature is
only intended for test purposes.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1069 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• TEC/REC (Address = H'00C)
Bit: 15
TEC7
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * It is only possible to write the value in test mode when TST[2:0] in MCR is 3'b100.
REC is incremented during Bus Off to count the recurrences of 11 recessive bits as
requested by the Bus Off recovery sequence.
22.3.4
RCAN-ET Mailbox Registers
The following sections describe RCAN-ET Mailbox registers that control / flag individual
Mailboxes. The address is mapped as follows.
Important : LongWord access is carried out as two consecutive Word accesses.
Page 1070 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Description
Address
Name
Access Size (bits)
Transmit Pending 1
H'020
TXPR1
LW
Transmit Pending 0
H'022
TXPR0
⎯
H'024
H'026
H'028
Transmit Cancel 0
H'02A
TXCR0
H'02C
H'02E
H'030
Transmit Acknowledge 0
H'032
TXACK0
Word
ABACK0
Word
RXPR0
Word
RFPR0
Word
MBIMR0
Word
UMSR0
Word
H'034
H'036
H'038
Abort Acknowledge 0
H'03A
H'03C
H'03E
H'040
Data Frame Receive Pending 0
H'042
H'044
H'046
H'048
Remote Frame Receive Pending 0 H'04A
H'04C
H'04E
H'050
Mailbox Interrupt Mask Register 0
H'052
H'054
H'056
H'058
Unread message Status Register 0 H'05A
H'05C
H'05E
Figure 22.7 RCAN-ET Mailbox Registers
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1071 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
(1)
Transmit Pending Register (TXPR1, TXPR0)
The concatenation of TXPR1 and TXPR0 is a 32-bit register that contains any transmit pending
flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as
two consecutive word accesses.
16-bit Peripheral bus
16-bit Peripheral bus
consecutive access
Temp
Temp
TXPR1
H'020
TXPR0
H'022
Data is stored into Temp instead of TXPR1.
TXPR1
H'020
TXPR0
H'022
Lower word data are stored into TXPR0.
TXPR1 is always H'0000.
16-bit Peripheral bus
16-bit Peripheral bus
consecutive access
always
H'0000
Temp
TXPR1
H'020
TXPR0
H'022
TXPR0 is stored into Temp,
when TXPR1 (= H'0000) is read.
Temp
TXPR1
H'020
TXPR0
H'022
Temp is read instead of TXPR0.
The TXPR1 register cannot be modified and it is always fixed to ‘0’. The TXPR0 controls
Mailbox-15 to Mailbox-1. The CPU may set the TXPR bits to affect any message being
considered for transmission by writing a '1' to the corresponding bit location. Writing a '0' has no
effect, and TXPR cannot be cleared by writing a ‘0’ and must be cleared by setting the
corresponding TXCR bits. TXPR may be read by the CPU to determine which, if any,
transmissions are pending or in progress. In effect there is a transmit pending bit for all Mailboxes
except for the Mailbox-0. Writing a '1' to a bit location when the mailbox is not configured to
transmit is not allowed.
Page 1072 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
The RCAN-ET will clear a transmit pending flag after successful transmission of its
corresponding message or when a transmission abort is requested successfully from the TXCR.
The TXPR flag is not cleared if the message is not transmitted due to the CAN node losing the
arbitration process or due to errors on the CAN bus, and RCAN-ET automatically tries to transmit
it again unless its DART bit (Disable Automatic Re-Transmission) is set in the Message-Control
of the corresponding Mailbox. In such case (DART set), the transmission is cleared and notified
through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit within the Abort
Acknowledgement Register (ABACK).
If the status of the TXPR changes, the RCAN-ET shall ensure that in the identifier priority scheme
(MCR2=0), the highest priority message is always presented for transmission in an intelligent way
even under circumstances such as bus arbitration losses or errors on the CAN bus. Please refer to
section 22.4, Application Note.
When the RCAN-ET changes the state of any TXPR bit position to a '0', an empty slot interrupt
(IRR8) may be generated. This indicates that either a successful or an aborted mailbox
transmission has just been made. If a message transmission is successful it is signalled in the
TXACK register, and if a message transmission abortion is successful it is signalled in the
ABACK register. By checking these registers, the contents of the Message of the corresponding
Mailbox may be modified to prepare for the next transmission.
• TXPR1
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXPR1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Any write operation is ignored.
Read value is always H'0000. Long word access is mandatory when reading or writing
TXPR1/TXPR0. Writing any value to TXPR1 is allowed, however, write operation to TXPR1 has
no effect.
• TXPR0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
TXPR0[15:1]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0
-
Note : * it is possible only to write a ‘1’ for a Mailbox configured as transmitter.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1073 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit 15 to 1 — indicates that the corresponding Mailbox is requested to transmit a CAN Frame.
The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively. When multiple bits are set, the order
of the transmissions is governed by the MCR2 – CAN-ID or Mailbox number.
Bit[15:1]:TXPR0
0
Description
Transmit message idle state in corresponding mailbox (Initial value)
[Clearing Condition] Completion of message transmission or message
transmission abortion (automatically cleared)
1
Transmission request made for corresponding mailbox
Bit 0— Reserved: This bit is always ‘0’ as this is a receive-only Mailbox. Writing a '1' to this bit
position has no effect. The returned value is '0'.
(2)
Transmit Cancel Register (TXCR0)
TXCR0 is a 16-bit read / conditionally-write registers. The TXCR0 controls Mailbox-15 to
Mailbox-1.This register is used by the CPU to request the pending transmission requests in the
TXPR to be cancelled. To clear the corresponding bit in the TXPR the CPU must write a '1' to the
bit position in the TXCR. Writing a '0' has no effect.
When an abort has succeeded the CAN controller clears the corresponding TXPR + TXCR bits,
and sets the corresponding ABACK bit. However, once a Mailbox has started a transmission, it
cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding TXACK bit,
however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN
controller clears the corresponding TXPR + TXCR bit, and sets the corresponding ABACK bit. If
an attempt is made by the CPU to clear a mailbox transmission that is not transmit-pending it has
no effect. In this case the CPU will be not able at all to set the TXCR flag.
• TXCR0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
TXCR0[15:1]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0
-
Note : * Only writing a ‘1’ to a Mailbox that is requested for transmission and is configured as
transmit.
Page 1074 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit 15 to 1 — requests the corresponding Mailbox, that is in the queue for transmission, to cancel
its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1]) respectively.
Bit[15:1]:TXCR0
Description
0
Transmit message cancellation idle state in corresponding mailbox (Initial
value)
[Clearing Condition] Completion of transmit message cancellation
(automatically cleared)
1
Transmission cancellation request made for corresponding mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a '1' to this bit position
has no effect and always read back as a ‘0’.
(3)
Transmit Acknowledge Register (TXACK0)
The TXACK0 is a 16-bit read / conditionally-write registers. This register is used to signal to the
CPU that a mailbox transmission has been successfully made. When a transmission has succeeded
the RCAN-ET sets the corresponding bit in the TXACK register. The CPU may clear a TXACK
bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect.
• TXACK0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
TXACK0[15:1]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0
-
Note : * Only when writing a ‘1’ to clear.
Bit 15 to 1 — notifies that the requested transmission of the corresponding Mailbox has been
finished successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit[15:1]:TXACK0
Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox has successfully transmitted message (Data or
Remote Frame)
[Setting Condition] Completion of message transmission for corresponding
mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a '1' to this bit position
has no effect and always read back as a ‘0’.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1075 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
(4)
Abort Acknowledge Register (ABACK0)
The ABACK0 is a 16-bit read / conditionally-write registers. This register is used to signal to the
CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded
the RCAN-ET sets the corresponding bit in the ABACK register. The CPU may clear the Abort
Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. An
ABACK bit position is set by the RCAN-ET to acknowledge that a TXPR bit has been cleared by
the corresponding TXCR bit.
• ABACK0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ABACK0[15:1]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0
-
Note : * Only when writing a ‘1’ to clear.
Bit 15 to 1 — notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Bit[15:1]:ABACK0 Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition] Completion of transmission cancellation for corresponding
mailbox
Bit 0 — This bit is always ‘0’ as this is a receive-only mailbox. Writing a '1' to this bit position
has no effect and always read back as a ‘0’.
(5)
Data Frame Receive Pending Register (RXPR0)
The RXPR0 is a 16-bit read / conditionally-write registers. The RXPR is a register that contains
the received Data Frames pending flags associated with the configured Receive Mailboxes. When
a CAN Data Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RXPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox
Configuration) to receive Data Frames. When a RXPR bit is set, it also sets IRR1 (Data Frame
Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the
interrupt signal is generated if IMR1 is not set. Please note that these bits are only set by receiving
Data Frames and not by receiving Remote frames.
Page 1076 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• RXPR0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXPR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a ‘1’ to clear.
Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position
from 15 to 0 respectively.
Bit[15:0]: RXPR0
Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox received a CAN Data Frame
[Setting Condition] Completion of Data Frame receive on corresponding
mailbox
(6)
Remote Frame Receive Pending Register (RFPR0)
The RFPR0 is a 16-bit read / conditionally-write registers. The RFPR is a register that contains the
received Remote Frame pending flags associated with the configured Receive Mailboxes. When a
CAN Remote Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RFPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. In effect there is a bit position for all mailboxes. However, the bit may only be set if the
mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a
RFPR bit is set, it also sets IRR2 (Remote Frame Request Interrupt Flag) if its MBIMR (Mailbox
Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Please
note that these bits are only set by receiving Remote Frames and not by receiving Data frames.
• RFPR0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RFPR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a ‘1’ to clear.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1077 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Bit 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively.
Bit[15:0]: RFPR0
Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox received Remote Frame
[Setting Condition] Completion of remote frame receive in corresponding
mailbox
(7)
Mailbox Interrupt Mask Register (MBIMR)
The MBIMR1 and MBIMR0 are 16-bit read / write registers. The MBIMR only prevents the
setting of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt,
IRR[2] – Remote Frame Request Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] –
Message OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the
corresponding bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and
IRR[9]) but does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR.
Similarly when a mailbox has been configured for transmission, a mask prevents the generation of
an Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or
abortion of transmission (IRR[8]), however, it does not prevent the RCAN-ET from clearing the
corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does
not prevent the RCAN-ET from clearing the corresponding TXPR/TXCR bit + setting the
ABACK bit for abortion of the transmission.
A mask is set by writing a '1' to the corresponding bit position for the mailbox activity to be
masked. At reset all mailbox interrupts are masked.
• MBIMR0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
MBIMR0[15:0]
Initial value: 1
R/W: R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0
respectively.
Bit[15:0]: MBIMR0 Description
0
Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled
1
Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)
Page 1078 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(8)
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Unread Message Status Register (UMSR)
This register is a 16-bit read/conditionally write register and it records the mailboxes whose
contents have not been accessed by the CPU prior to a new message being received. If the CPU
has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox
is received, the corresponding UMSR bit is set to ‘1’. This bit may be cleared by writing a ‘1’ to
the corresponding bit location in the UMSR. Writing a ‘0’ has no effect.
If a mailbox is configured as transmit box, the corresponding UMSR will not be set.
• UMSR0
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UMSR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition
has occurred for Mailboxes 15 to 0.
Bit[15:0]: UMSR0
Description
0
[Clearing Condition] Writing ‘1’ (initial value)
1
Unread received message is overwritten by a new message or overrun
condition
[Setting Condition] When a new message is received before RXPR or RFPR
is cleared
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1079 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.4
Application Note
22.4.1
Test Mode Settings
SH7280 Group, SH7243 Group
The RCAN-ET has various test modes. The register TST[2:0] (MCR[10:8]) is used to select the
RCAN-ET test mode. The default (initialised) settings allow RCAN-ET to operate in Normal
mode. The following table is examples for test modes.
Test Mode can be selected only while in configuration mode. The user must then exit the
configuration mode (ensuring BCR0/BCR1 is set) in order to run the selected test mode.
Bit10:
TST2
Bit9:
TST1
Bit8:
TST0
Description
0
0
0
Normal Mode (initial value)
0
0
1
Listen-Only Mode (Receive-Only Mode)
0
1
0
Self Test Mode 1 (External)
0
1
1
Self Test Mode 2 (Internal)
1
0
0
Write Error Counter
1
0
1
Error Passive Mode
1
1
0
Setting prohibited
1
1
1
Setting prohibited
Normal Mode:
RCAN-ET operates in the normal mode.
Listen-Only Mode:
ISO-11898 requires this mode for baud rate detection. The Error
Counters are cleared and disabled so that the TEC/REC does not increase
the values, and the Tx Output is disabled so that RCAN-ET does not
generate error frames or acknowledgment bits. IRR13 is set when a
message error occurs.
Self Test Mode 1:
RCAN-ET generates its own Acknowledge bit, and can store its own
messages into a reception mailbox (if required). The Rx/Tx pins must be
connected to the CAN bus.
Self Test Mode 2:
RCAN-ET generates its own Acknowledge bit, and can store its own
messages into a reception mailbox (if required). The Rx/Tx pins do not
need to be connected to the CAN bus or any external devices, as the
internal Tx is looped back to the internal Rx. Tx pin outputs only
recessive bits and Rx pin is disabled.
Page 1080 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Write Error Counter:
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
TEC/REC can be written in this mode. RCAN-ET can be forced to
become an Error Passive mode by writing a value greater than 127 into
the Error Counters. The value written into TEC is used to write into REC,
so only the same value can be set to these registers. Similarly, RCAN-ET
can be forced to become an Error Warning by writing a value greater than
95 into them.
RCAN-ET needs to be in Halt Mode when writing into TEC/REC
(MCR1 must be "1" when writing to the Error Counter). Furthermore this
test mode needs to be exited prior to leaving Halt mode.Error Passive
Mode: RCAN-ET can be forced to enter Error Passive mode.
Note: the REC will not be modified by implementing this Mode.
However, once running in Error Passive Mode, the REC will increase
normally should errors be received. In this Mode, RCAN-ET will enter
BusOff if TEC reaches 256 (Dec). However when this mode is used
RCAN-ET will not be able to become Error Active. Consequently, at the
end of the Bus Off recovery sequence, RCAN-ET will move to Error
Passive and not to Error Active
When message error occurs, IRR13 is set in all test modes.
22.4.2
Configuration of RCAN-ET
RCAN-ET is considered in configuration mode or after a H/W (Power On Reset)/ S/W (MCR[0])
reset or when in Halt mode. In both conditions RCAN-ET cannot join the CAN Bus activity and
configuration changes have no impact on the traffic on the CAN Bus.
• After a Reset request
The following sequence must be implemented to configure the RCAN-ET after (S/W or H/W)
reset. After reset, all the registers are initialised, therefore, RCAN-ET needs to be configured
before joining the CAN bus activity. Please read the notes carefully.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1081 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Reset Sequence
Configuration Mode
Power On/SW Reset*1
No
GSR[3] = 0?
MCR[0] = 1
(automatically in hardware reset only)
Yes
IRR[0] = 1, GSR[3] = 1 (automatically)
RCAN-ET is in Tx_Rx Mode
clear IRR[0] Bit
Set TXPR to start transmission
or stay idle to receive
Configure MCR[15]
Transmission_Reception
(Tx_Rx) Mode
Clear Required IMR Bits
Mailbox Setting
(STD-ID, EXT-ID, LAFM, DLC,
RTR, IDE, MBC, MBIMR, DART,
ATX, NMC, Message-Data)*2
Set Bit Timing (BCR)
Detect 11 recessive bits and
Join the CAN bus activity
Receive*3
Transmit*3
Clear MCR[0]
Notes:
1.
2.
3.
SW reset could be performed at any time by setting MCR[0] = 1.
Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC.
If there is no TXPR set, RCAN-ET will receive the next incoming message.
If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
Figure 22.8 Reset Sequence
Page 1082 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• Halt mode
When RCAN-ET is in Halt mode, it cannot take part to the CAN bus activity. Consequently
the user can modify all the requested registers without influencing existing traffic on the CAN
Bus. It is important for this that the user waits for the RCAN-ET to be in halt mode before to
modify the requested registers - note that the transition to Halt Mode is not always immediate
(transition will occurs when the CAN Bus is idle or in intermission). After RCAN-ET transit to
Halt Mode, GSR4 is set.
Once the configuration is completed the Halt request needs to be released. RCAN-ET will join
CAN Bus activity after the detection of 11 recessive bits on the CAN Bus.
• Sleep mode
When RCAN-ET is in sleep mode the clock for the main blocks of the IP is stopped in order to
reduce power consumption. Only the following user registers are clocked and can be accessed:
MCR, GSR, IRR and IMR. Interrupt related to transmission (TXACK and ABACK) and
reception (RXPR and RFPR) cannot be cleared when in sleep mode (as TXACK, ABACK,
RXPR and RFPR are not accessible) and must to be cleared beforehand.
The following diagram shows the flow to follow to move RCAN-ET into sleep mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1083 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Sleep Mode
Sequence flow
Halt Request
Write MCR[1] = 1
: Hardware operation
GSR[4] = 1?
No
: Manual operation
User monitor
Yes
IRR[0] = 1
Write IRR[0] = 1
IRR[0] = 0
Sleep Request
Write MCR[1] = 0 & MCR[5] = 1
IRR[0] = 1
Write IRR[0] = 1
IRR0 = 0
Sleep Mode
CAN Bus Activity
No
CLK is
STOP
Yes
Only MCR, GSR,
IRR, IMR can be
accessed.
IRR[12] = 1
MCR[7] = 1?
No
Yes
Write IRR[12] = 1
IRR[12] = 0
MCR[5] = 0
Write MCR[5] = 0
Write IRR[12] = 1
IRR[12] = 0
GSR4 = 0?
No
User monitor
Yes
Transmission/Reception Mode
Page 1084 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Figure 22.9 - Halt Mode / Sleep Mode shows allowed state transition.
⎯ Please don't set MCR5 (Sleep Mode) without entering Halt Mode.
⎯ After MCR1 is set, please don't clear it before GSR4 is set and RCAN-ET enters Halt
Mode.
Power On/SW Reset
Reset
clear MCR0
and GSR3 = 0
clear MCR1
and MCR5
Transmission
Reception
set MCR1*3
clear MCR5*1
clear MCR5
set MCR1*4
Halt Request
except Transmitter/Receiver/BusOff, if MCR6 = 0
BusOff or except Transmitter/Receiver, if MCR6 = 1
Halt Mode
Sleep Mode
set MCR5
clear MCR1*2
Figure 22.9 Halt Mode / Sleep Mode
Notes: 1. MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if
MCR7 is set or by writing "0"
2. MCR1 is cleared in SW. Clearing MCR1 and setting MCR5 have to be carried out by
the same instruction.
3. MCR1 must not be cleared in SW, before GSR4 is set. MCR1 can be set automatically
in HW when RCAN-ET moves to Bus Off and MCR14 and MCR6 are both set.
4. When MCR5 is cleared and MCR1 is set at the same time, RCAN-ET moves to Halt
Request. Right after that, it moves to Halt Mode with no reception/transmission.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1085 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
The following table shows conditions to access registers.
RCAN-ET Registers
MCR
Status Mode GSR
IRR
IMR
BCR
MBIMR
mailbox
mailbox mailbox
Flag_register (ctrl0, LAFM) (data)
(ctrl1)
Reset
yes
yes
yes
yes
yes
yes
yes
1
yes
yes
no*
1
Transmission yes
Reception
Halt Request
yes
no*
Halt
yes
yes
no*
yes
yes
Sleep
yes
yes
no
no
no
1
2
yes*
yes
2
1
yes*
no*
yes
yes
yes
no
no
no
2
yes*
Notes: 1. No hardware protection
2. When TXPR is not set.
Page 1086 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.4.3
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Message Transmission Sequence
• Message Transmission Request
The following sequence is an example to transmit a CAN frame onto the bus. As described in
the previous register section, please note that IRR8 is set when one of the TXACK or ABACK
bits is set, meaning one of the Mailboxes has completed its transmission or transmission
abortion and is now ready to be updated for the next transmission, whereas, the GSR2 means
that there is currently no transmission request made (No TXPR flags set).
Mailbox[x] is ready
to be updated for
next transmission
RCAN-ET is in Tx_Rx Mode
(MBC[x] = 0)
Update Message Data of
Mailbox[x]
Clear TXACK[x]
Yes
Write '1' to the TXPR[x] bit
at any desired time
Internal Arbitration
'x' Highest Priority?
TXACK[x] = 1?
No
No
Waiting for interrupt
Yes
No
Waiting for interrupt
IRR8 = 1?
Yes
Transmission Start
CAN Bus
Arbitration
Acknowledge Bit
CAN Bus
Figure 22.10 Transmission Request
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1087 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
• Internal Arbitration for transmission
The following diagram explains how RCAN-ET manages to schedule transmission-requested
messages in the correct order based on the CAN identifier. ‘Internal arbitration’ picks up the
highest priority message amongst transmit-requested messages.
Transmission
Frame-1
CAN bus
state
RCAN-ET
scheduler state
Bus Idle
SOF
EOF Interm SOF
Message
Tx Arb for Tx/Rx Arb for
Frame-1
Frame-1
Reception
Frame-2
Tx Arb for
Frame-3
Transmission
Frame-3
EOF Interm SOF
Message
Tx/Rx Arb for
Frame-3/2
Tx Arb for
Frame-3
Tx/Rx Arb for
Frame-3
Scheduler
start point
TXPR/TXCR/
Error/Arb-Lost
Set Point
1-1
Interm:
SOF:
EOF:
Message:
1-2
2-1
2-2
3-1
3-2
Intermission Field
Start Of Frame
End Of Frame
Arbitration + Control + Data + CRC + Ack Field
Figure 22.11 Internal Arbitration for Transmission
The RCAN-ET has two state machines. One is for transmission, and the other is for reception.
1-1: When a TXPR bit(s) is set while the CAN bus is idle, the internal arbitration starts running
immediately and the transmission is started.
1-2: Operations for both transmission and reception starts at SOF. Since there is no reception
frame, RCAN-ET becomes transmitter.
2-1: At crc delimiter, internal arbitration to search next message transmitted starts.
2-2: Operations for both transmission and reception starts at SOF. Because of a reception frame
with higher priority, RCAN-ET becomes receiver. Therefore, Reception is carried out instead
of transmitting Frame-3.
3-1: At crc delimiter, internal arbitration to search next message transmitted starts.
3-2: Operations for both transmission and reception starts at SOF. Since a transmission frame has
higher priority than reception one, RCAN-ET becomes transmitter.
Internal arbitration for the next transmission is also performed at the beginning of each error
delimiter in case of an error is detected on the CAN Bus. It is also performed at the beginning of
error delimiters following overload frame.
Page 1088 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
As the arbitration for transmission is performed at CRC delimiter, in case a remote frame request
is received into a Mailbox with ATX=1 the answer can join the arbitration for transmission only at
the following Bus Idle, CRC delimiter or Error Delimiter.
Depending on the status of the CAN bus, following the assertion of the TXCR, the corresponding
Message abortion can be handled with a delay of maximum 1 CAN Frame.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1089 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.4.4
Message Receive Sequence
The diagram below shows the message receive sequence.
CAN Bus
End Of Arbitration Field
End Of Frame
RCAN-ET
IDLE
Valid CAN Frame Received
Valid CAN-ID Received
N=N-1
Loop (N = 15; N ≥ 0; N = N - 1)
Exit Interrupt Service
Routine
Compare ID with
Mailbox[N] + LAFM[N]
(if MBC is config to receive)
Yes
ID Matched?
No
No
Yes
N = 0?
RXPR[N]
(RFPR[N])
Already Set?
Yes
Store Mailbox-Number[N]
and go back to idle state
Interrupt signal
Check and clear
UMSR[N] **
Write 1 to RXPR[N]
Write 1 to RFPR[N]
Read Mailbox[N]
Read Mailbox[N]
Read RXPR[N] = 1
Read RFPR[N] = 1
Yes
MSG
OverWrite or
OverRun?
(NMC)
OverWrite
•Store Message by Overwriting
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
No
Check and clear
UMSR[N] **
OverRun
•Reject Message
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N]) *
Interrupt signal
Yes
•Store Message
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
IRR[1]
set?
No
Read IRR
Interrupt signal
CPU received interrupt due to CAN Message Reception
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the
message has not been updated.
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared
and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/
UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
Figure 22.12 Message Receive Sequence
Page 1090 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
When RCAN-ET recognises the end of the Arbitration field while receiving a message, it starts
comparing the received identifier to the identifiers set in the Mailboxes, starting from Mailbox-15
down to Mailbox-0. It first checks the MBC if it is configured as a receive box, and reads LAFM,
and reads the CAN-ID of Mailbox-15 (if configured as receive) to finally compare them to the
received ID. If it does not match, the same check takes place at Mailbox-14 (if configured as
receive). Once RCAN-ET finds a matching identifier, it stores the number of Mailbox-[N] into an
internal buffer, stops the search, and goes back to idle state, waiting for the EndOfFrame (EOF) to
come. When the 6th bit of EOF is notified by the CAN Interface logic, the received message is
written or abandoned, depending on the NMC bit. No modification of configuration during
communication is allowed. Entering Halt Mode is one of ways to modify configuration. If it is
written into the corresponding Mailbox, including the CAN-ID, i.e., there is a possibility that the
CAN-ID is overwritten by a different CAN-ID of the received message due to the LAFM used.
This also implies that, if the identifier of a received message matches to ID + LAFM of 2 or more
Mailboxes, the higher numbered Mailbox will always store the relevant messages and the lower
numbered Mailbox will never receive messages. Therefore, the settings of the identifiers and
LAFMs need to be carefully selected.
With regards to the reception of data and remote frames described in the above flow diagram the
clearing of the UMSR flag after the reading of IRR is to detect situations where a message is
overwritten by a new incoming message stored in the same mailbox while the interrupt service
routine is running. If during the final check of UMSR a overwrite condition is detected the
message needs to be discarded and read again.
In case UMSR is set and the Mailbox is configured for overrun (NMC = 0) the message is still
valid, however it is obsolete as it is not reflecting the latest message monitored on the CAN Bus.
Please access the full Mailbox content before clearing the related RXPR/RFPR flag.
Please note that in the case a received remote frame is overwritten by a data frame, both the
remote frame request interrupt (IRR2) and data frame received interrupt (IRR1) and also the
Receive Flags (RXPR and RFPR) are set. In an analogous way, the overwriting of a data frame by
a remote frame, leads to setting both IRR2 and IRR1.
In the Overrun Mode (NMC = ’0’), only the first Mailbox will cause the flags to be asserted. So, if
a Data Frame is initially received, then RXPR and IRR1 are both asserted. If a Remote Frame is
then received before the Data Frame has been read, then RFPR and IRR2 are NOT set. In this case
UMSR of the corresponding Mailbox will still be set.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1091 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.4.5
SH7280 Group, SH7243 Group
Reconfiguration of Mailbox
When re-configuration of Mailboxes is required, the following procedures should be taken.
• Change configuration of transmit box
Two cases are possible.
⎯ Change of ID, RTR, IDE, LAFM, Data, DLC, NMC, ATX, DART
This change is possible only when MBC=3'b000. Confirm that the corresponding TXPR is
not set. The configuration (except MBC bit) can be changed at any time.
⎯ Change from transmit to receive configuration (MBC)
Confirm that the corresponding TXPR is not set. The configuration can be changed only in
Halt or reset state. Please note that it might take longer for RCAN-ET to transit to halt state
if it is receiving or transmitting a message (as the transition to the halt state is delayed until
the end of the reception/transmission), and also RCAN-ET will not be able to
receive/transmit messages during the Halt state.
In case RCAN-ET is in the Bus Off state the transition to halt state depends on the
configuration of the bit 6 of MCR and also bit and 14 of MCR.
• Change configuration (ID, RTR, IDE, LAFM, Data, DLC, NMC, ATX, DART, MBC) of
receiver box or Change receiver box to transmitter box
The configuration can be changed only in Halt Mode.
RCAN-ET will not lose a message if the message is currently on the CAN bus and RCAN-ET
is a receiver. RCAN-ET will be moving into Halt Mode after completing the current reception.
Please note that it might take longer if RCAN-ET is receiving or transmitting a message (as the
transition to the halt state is delayed until the end of the reception/transmission), and also
RCAN-ET will not be able to receive/transmit messages during the Halt Mode.
In case RCAN-ET is in the Bus Off state the transition to halt mode depends on the
configuration of the bit 6 and 14 of MCR.
Page 1092 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Method by Halt Mode
RCAN-ET is in Tx_Rx Mode
Set MCR[1] (Halt Mode)
Is RCAN-ET
Transmitter, Receiver
or Bus Off?
Finish
current
session
Yes
No
Generate interrupt (IRR0)
Read IRR0 & GSR4 as '1'
RCAN-ET is in Halt Mode
Change ID or MBC of Mailbox
Clear MCR1
RCAN-ET is in Tx_Rx Mode
The shadowed boxes need to be
done by S/W (host processor)
Figure 22.13 Change ID of Receive Box or Change Receive Box to Transmit Box
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1093 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.5
SH7280 Group, SH7243 Group
Interrupt Sources
Table 22.2 lists the RCAN-ET interrupt sources. With the exception of the reset processing
interrupt (IRR0) by a power-on reset, these sources can be masked. Masking is implemented using
the mailbox interrupt mask register 0 (MBIMR0) and interrupt mask register (IMR). For details on
the interrupt vector of each interrupt source, see section 6, Interrupt Controller (INTC).
Table 22.2 RCAN-ET Interrupt Sources
Interrupt
Flag
DTC
Activation
Error Passive Mode (TEC ≥ 128 or REC ≥
128)
IRR5
Not possible
Bus Off (TEC ≥ 256)/Bus Off recovery
IRR6
Error warning (TEC ≥ 96)
IRR3
Error warning (REC ≥ 96)
IRR4
Message error detection
IRR13*1
Reset/halt/CAN sleep transition
IRR0
Module
Interrupt Description
RCAN-ET
ERS_0
OVR_0
Overload frame transmission
IRR7
Unread message overwrite (overrun)
IRR9
Detection of CAN bus operation in CAN
sleep mode
IRR12
Data frame reception
IRR1*3
RM1_0*
Remote frame reception
IRR2*
SLE_0
Message transmission/transmission
disabled (slot empty)
IRR8
RM0_0*2
2
Possible*4
3
Not possible
Notes: 1. Available only in Test Mode.
2. RM0_0 is an interrupt generated by the remote request pending flag for mailbox 0
(RFPR0[0]) or the data frame receive flag for mailbox 0 (RXPR0[0]). RM1_0 is an
interrupt generated by the remote request pending flag for mailbox n (RFPR0[n]) or the
data frame receive flag for mailbox n (RXPR0[n]) (n = 1 to 15).
3. IRR1 is a data frame received interrupt flag for mailboxes 0 to 15, and IRR2 is a remote
frame request interrupt flag for mailboxes 0 to 15.
4. The DTC can be activated only by the RM0_0 interrupt.
Page 1094 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.6
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
DTC Interface
The DTC can be activated by the reception of a message in RCAN-ET mailbox 0. When DTC
transfer ends after DTC activation has been set, flags of RXPR0 and RFPR0 are cleared
automatically. An interrupt request due to a receive interrupt from the RCAN-ET cannot be sent to
the CPU in this case. Figure 22.14 shows a DTC transfer flowchart.
: Settings by user
DTC initialization
DTC enable register setting
DTC register information setting
: Processing by hardware
Message reception in RCAN-ET
mailbox 0
DTC activation
End of DTC transfer?
No
Yes
RXPR and RFPR flags clearing
Transfer counter = 0
or DISEL = 1?
No
Yes
Interrupt to CPU
END
Figure 22.14 DTC Transfer Flowchart
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1095 of 1778
SH7280 Group, SH7243 Group
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.7
DMAC Interface
The DMAC can be activated by the reception of a message in RCAN-ET mailbox 0. When
DMAC transfer ends after DMAC activation has been set, flags of RXPR0 and RFPR0 are cleared
automatically. An interrupt request due to a receive interrupt from the RCAN-ET cannot be sent to
the CPU in this case. Figure 22.15 shows a DMAC transfer flowchart.
: Settings by user
DMAC initialization
DMAC enable register setting
DMAC register information setting
: Processing by hardware
Message reception in RCAN-ET
mailbox 0
DMAC activation
End of DMAC transfer?
No
Yes
RXPR and RFPR flags clearing
DMAC interrupt
enabled?
No
Yes
Interrupt to CPU
END
22.15 DMAC Transfer Flowchart
Page 1096 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.8
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
CAN Bus Interface
A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Renesas HA13721
transceiver IC and its compatible products are recommended. Figure 22.16 shows a sample
connection diagram.
120 Ω
This LSI
Vcc
HA13721
CTx0
Txd MODE
CAN bus
GND CANH
CRx0
Vcc
CANL
Rxd
NC
120 Ω
[Legend]
NC: No Connection
Figure 22.16 High-Speed CAN Interface Using HA13721
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1097 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.9
Usage Notes
22.9.1
Module Standby Mode
SH7280 Group, SH7243 Group
The clock supply to RCAN-ET can be stopped or started by using the standby control register 6
(STBCR6). With the initial value, the clock supply is stopped. Access to the RCAN-ET registers
should be made only after releasing RCAN-ET from module standby mode.
22.9.2
Reset
RCAN-ET can be reset by hardware reset or software reset.
• Hardware reset
RCAN-ET is reset to the initial state by power-on reset or on entering hardware standby or
module standby mode.
• Software reset
By setting the MCR0 bit in Master Control Register (MCR), RCAN-ET registers, excluding
the MCR0 bit, and the CAN communication circuitry are initialized.
Since the IRR0 bit in Interrupt Request Register (IRR) is set by the initialization upon reset, it
should be cleared while RCAN-ET is in configuration mode during the reset sequence.
The areas except for message control field 1 (CONTROL1) of mailboxes are not initialized by
reset because they are in RAM. After power-on reset, all mailboxes should be initialized while
RCAN-ET is in configuration mode during the reset sequence.
22.9.3
CAN Sleep Mode
In CAN sleep mode, the clock supply to the major parts in the module is stopped. Therefore, do
not make access in CAN sleep mode except for access to the MCR, GSR, IRR, and IMR registers.
22.9.4
Register Access
If the mailbox area is accessed while the CAN communication circuitry in RCAN-ET is storing a
received CAN bus frame in a mailbox, a 0 to five peripheral clock cycles of wait state is
generated.
Page 1098 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
22.9.5
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Interrupts
As shown in table 22.2, a Mailbox 0 receive interrupt can activate the DTC. If configured such
that the DTC is activated by a Mailbox 0 receive interrupt and clearing of the interrupt source flag
upon DTC transfer is enabled, use block transfer mode and read the whole Mailbox 0 message up
to the message control field 1 (CONTROL1).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1099 of 1778
Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
Page 1100 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Section 23 Pin Function Controller (PFC)
The pin function controller (PFC) is composed of registers that are used to select the functions of
multiplexed pins and assign pins to be inputs or outputs. Tables 23.1 to 23.16 list the multiplexed
pins of this LSI.
Table 23.1 Multiplexed Pins (SH7243 Port A)
Function 1 Function 2
Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
A
PA15 I/O
CK output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(port)
(BSC)
PA14 I/O
RD output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(port)
(BSC)
PA13 I/O
WRL output, ⎯
⎯
⎯
⎯
⎯
⎯
⎯
(port)
DQMLL
⎯
POE8 input ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
output (BSC)
PA12 I/O
WRH output, ⎯
(port)
DQMLU
(POE2)
output (BSC)
PA9 I/O
CKE output
(port)
(BSC)
⎯
⎯
⎯
RXD3 input TCLKD
(SCIF)
input
(MTU2)
PA8 I/O
RDWR
(port)
output (BSC)
⎯
PA7 I/O
CASL output ⎯
(port)
(BSC)
⎯
⎯
⎯
⎯
TXD3
TCLKC
output
input
(SCIF)
(MTU2)
SCK3 I/O
TCLKB
(SCIF)
input
(MTU2)
PA6 I/O
RASL output ⎯
(port)
(BSC)
⎯
⎯
⎯
TCLKA
input
(MTU2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1101 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.2 Multiplexed Pins (SH7285 Port A)
Function 1 Function 2
Function 3
Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
A
PA23 I/O
CKE output
AH output
IRQ1 input
POE0 input ⎯
TIC5W
⎯
⎯
(port)
(BSC)
(BSC)
(INTC)
(POE2)
input
PA22 I/O
CASL output CASU
IRQ2 input
POE4 input ⎯
TIC5V input ⎯
⎯
(port)
(BSC)
(INTC)
(POE2)
(MTU2)
(MTU2)
output
(BSC)
PA21 I/O
RASL output RASU
IRQ3 input
POE8 input ⎯
TIC5U input ⎯
(port)
(BSC)
(INTC)
(POE2)
(MTU2)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
output
⎯
(BSC)
PA15 I/O
CK output
(port)
(BSC)
PA14 I/O
RD output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(port)
(BSC)
PA13 I/O
WRL output, ⎯
⎯
⎯
⎯
⎯
⎯
⎯
(port)
DQMLL
⎯
POE8 input ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SSCL I/O
⎯
output (BSC)
PA12 I/O
WRH output, ⎯
(port)
DQMLU
(POE2)
output (BSC)
PA9 I/O
CKE output
(port)
(BSC)
⎯
⎯
⎯
RXD3 input TCLKD
(SCIF)
input
(MTU2)
PA8 I/O
RDWR
(port)
output (BSC)
⎯
PA7 I/O
CASL output ⎯
(port)
(BSC)
⎯
⎯
⎯
⎯
TXD3
TCLKC
output
input
(SCIF)
(MTU2)
SCK3 I/O
TCLKB
(SCIF)
input
(MTU2)
PA6 I/O
RASL output ⎯
(port)
(BSC)
⎯
⎯
⎯
TCLKA
input
(MTU2)
PA5 I/O
CS5 output
(port)
(BSC)
Page 1102 of 1778
⎯
⎯
⎯
SCK1 I/O
(SCI)
⎯
(SSU)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2
Function 3
Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
A
PA4 I/O
CS4 output
⎯
⎯
⎯
TXD1
⎯
SSO I/O
TRST input
(port)
(BSC)
(SSU)
(H-UDI)
RXD1 input ⎯
SSI I/O
TMS input
(SCI)
(SSU)
(H-UDI)
SCS I/O
TCK input
(SSU)
(H-UDI)
⎯
TDO input
output
(SCI)
PA3 I/O
CS3 output
(port)
(BSC)
PA2 I/O
CS2 output
(port)
(BSC)
PA1 I/O
CS1 output
(port)
(BSC)
⎯
⎯
⎯
⎯
⎯
⎯
SCK0 I/O
⎯
(SCI)
⎯
⎯
⎯
TXD0
⎯
output
(H-UDI)
(SCI)
PA0 I/O
CS0 output
(port)
(BSC)
⎯
⎯
⎯
RXD0 input ⎯
⎯
TDI input
(SCI)
(H-UDI)
Table 23.3 Multiplexed Pins (SH7286 Port A)
Function 1 Function 2
Function 3
Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
A
PA23 I/O
CKE output
AH output
IRQ1 input
POE0 input ⎯
TIC5W
⎯
⎯
(port)
(BSC)
(BSC)
(INTC)
(POE2)
input
PA22 I/O
CASL output
CASU
IRQ2 input
POE4 input ⎯
TIC5V input ⎯
⎯
(port)
(BSC)
output
(INTC)
(POE2)
(MTU2)
(MTU2)
(BSC)
PA21 I/O
RASL output
RASU
IRQ3 input
POE8 input ⎯
TIC5U
(port)
(BSC)
output
(INTC)
(POE2)
input
(BSC)
PA15 I/O
CK output
(port)
(BSC)
PA14 I/O
RD output
(port)
(BSC)
PA13 I/O
WRL output,
(port)
DQMLL output
⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(BSC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1103 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2
Function 3
Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
A
PA12 I/O
WRH output,
⎯
⎯
POE8 input ⎯
⎯
⎯
⎯
(port)
DQMLU
(POE2)
output (BSC)
PA11 I/O
WRHH output, ⎯
(port)
DQMLUU
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RXD3 input TCLKD
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SSCK I/O
⎯
output, AH
output
(BSC)
PA10 I/O
WRHL output, ⎯
(port)
DQMUL
PA9 I/O
CKE output
(port)
(BSC)
output (BSC)
⎯
(SCIF)
input
(MTU2)
PA8 I/O
RDWR output ⎯
(port)
(BSC)
PA7 I/O
CASL output
(port)
(BSC)
⎯
⎯
⎯
⎯
⎯
TXD3
TCLKC
output
input
(SCIF)
(MTU2)
SCK3 I/O
TCLKB
(SCIF)
input
(MTU2)
PA6 I/O
RASL output
(port)
(BSC)
⎯
⎯
⎯
⎯
TCLKA
input
(MTU2)
PA5 I/O
CS5 output
(port)
(BSC)
PA4 I/O
CS4 output
(port)
(BSC)
⎯
⎯
⎯
SCK1 I/O
⎯
(SCI)
⎯
⎯
⎯
TXD1
(SSU)
⎯
output
SSO I/O
⎯
(SSU)
(SCI)
PA3 I/O
CS3 output
(port)
(BSC)
PA2 I/O
CS2 output
(port)
(BSC)
Page 1104 of 1778
⎯
⎯
⎯
⎯
⎯
⎯
RXD1 input ⎯
SSI I/O
(SCI)
(SSU)
SCK0 I/O
(SCI)
⎯
SCS I/O
⎯
⎯
(SSU)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2
Function 3
Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
A
PA1 I/O
CS1 output
⎯
⎯
⎯
TXD0
⎯
⎯
⎯
(port)
(BSC)
RXD0 input ⎯
⎯
⎯
output
(SCI)
PA0 I/O
CS0 output
(port)
(BSC)
⎯
⎯
⎯
(SCI)
Table 23.4 Multiplexed Pins (SH7243 Port B)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
B
PB12 I/O
CS1 output CS7 output IRQ1 input
⎯
TXD2
⎯
CS3 output ⎯
(port)
(BSC)
(BSC)
(INTC)
output
(BSC)
(SCI)
PB11 I/O
CS0 input
CS6 output IRQ0 input
(port)
(BSC)
(BSC)
(INTC)
PB8 I/O
A20 output
WAIT input
IRQ7 input
POE8 input SCK0 I/O
(port)
(BSC)
(BSC)
(INTC)
(POE2)
PB7 I/O
A19output
BREQ input IRQ6 input
POE4 input TXD0
(port)
(BSC)
(BSC)
(INTC)
(POE2)
PB6 I/O
A18 output
BACK
(port)
(BSC)
output
⎯
RXD2 input ⎯
CS2 output ⎯
(SCI)
(BSC)
⎯
⎯
⎯
⎯
⎯
⎯
IRQ5 input
POE3 input RXD0 input ⎯
⎯
⎯
(INTC)
(POE2)
(SCI)
⎯
⎯
ADTRG
⎯
(SCI)
output
(SCI)
(BSC)
PB1 I/O
A17output
REFOUT
IRQ4 input
(port)
(BSC)
output
(INTC)
⎯
input
(BSC)
PB0 I/O
A16 output
(port)
(BSC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
⎯
(ADC)
IRQ3 input
⎯
⎯
⎯
⎯
⎯
(INTC)
Page 1105 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.5 Multiplexed Pins (SH7285 Port B)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
B
PB12 I/O
CS1 output CS7 output IRQ1 input
⎯
TXD2
⎯
CS3 output ⎯
(port)
(BSC)
(BSC)
(INTC)
output
(BSC)
(SCI)
PB11 I/O
CS0 output CS6 output IRQ0 input
(port)
(BSC)
(BSC)
(INTC)
PB10 I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
USPND
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ADTRG
⎯
⎯
RXD2 input ⎯
CS2 output ⎯
(SCI)
(BSC)
(port)
PB9 I/O
(port)
output
(USB)
PB8 I/O
A20 output
WAIT input
IRQ7 input
POE8 input SCK0 I/O
(port)
(BSC)
(BSC)
(INTC)
(POE2)
PB7 I/O
A19 output
BREQ input IRQ6 input
POE4 input TXD0
(port)
(BSC)
(BSC)
(POE2)
(INTC)
(SCI)
output
(SCI)
PB6 I/O
A18 output
BACK input IRQ5 input
POE3 input RXD0 input ⎯
(port)
(BSC)
(BSC)
(INTC)
(POE2)
PB3 I/O
⎯
⎯
IRQ1 input
POE2 input SDA I/O
(INTC)
(POE2)
IRQ0 input
POE1 input SCL I/O
(INTC)
(POE2)
(IIC3)
⎯
⎯
(port)
PB2 I/O
⎯
⎯
(port)
PB1 I/O
A17output
REFOUT
IRQ4 input
(port)
(BSC)
output
(INTC)
(SCI)
(IIC3)
input
(BSC)
PB0 I/O
A16 output
(port)
(BSC)
Page 1106 of 1778
⎯
(ADC)
IRQ3 input
⎯
⎯
⎯
⎯
⎯
(INTC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.6 Multiplexed Pins (SH7286 Port B)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
B
PB19 I/O
A25 output
RASU
⎯
⎯
⎯
⎯
DREQ2
⎯
(Port)
(BSC)
output
PB18 I/O
A24 output
RASL
(Port)
(BSC)
output
output
(BSC)
(DMAC)
input
(BSC)
(DMAC)
⎯
⎯
⎯
⎯
DACK2
PB17 I/O
A23 output
CASU
(Port)
(BSC)
output
input
(BSC)
(DMAC)
⎯
⎯
⎯
⎯
DREQ3
PB16 I/O
A22 output
CASL
(Port)
(BSC)
output
output
(BSC)
(DMAC)
⎯
PB15 I/O
A21 output
CKE output ⎯
(Port)
(BSC)
(BSC)
PB14 I/O
⎯
⎯
⎯
⎯
⎯
⎯
(Port)
PB13 I/O
⎯
⎯
⎯
DACK3
⎯
⎯
⎯
⎯
⎯
⎯
CRx0 input ⎯
⎯
⎯
⎯
⎯
⎯
⎯
CS3 output ⎯
(RCAN)
⎯
⎯
⎯
⎯
(Port)
CTx0
output
(RCAN)
PB12 I/O
CS1 output CS7 output IRQ1 input
(Port)
(BSC)
(BSC)
⎯
(INTC)
TXD2
output
(BSC)
(SCI)
PB11 I/O
CS0 output CS6 output IRQ0 input
(Port)
(BSC)
(BSC)
(INTC)
PB10 I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RXD2 input ⎯
CS2 output ⎯
(SCI)
(BSC)
⎯
⎯
⎯
⎯
USPND
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(Port)
PB9 I/O
(Port)
output
(USB)
PB8 I/O
A20 output
WAIT input IRQ7 input
POE8 input SCK0 I/O
(Port)
(BSC)
(BSC)
(POE2)
PB7 I/O
A19 output
BREQ input IRQ6 input
POE4 input TXD0
(Port)
(BSC)
(BSC)
(POE2)
(INTC)
(INTC)
(SCI)
output
(SCI)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1107 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
B
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PB6 I/O
A18 output
BACK
IRQ5 input
POE3 input RXD0 input ⎯
⎯
⎯
(Port)
(BSC)
output
(INTC)
(POE2)
IRQ1 input
POE2 input SDA I/O
⎯
⎯
⎯
(INTC)
(POE2)
IRQ0 input
POE1 input SCL I/O
⎯
⎯
⎯
(INTC)
(POE2)
(IIC3)
⎯
⎯
⎯
ADTRG
⎯
(SCI)
(BSC)
PB3 input
⎯
⎯
(Port)
PB2 input
⎯
⎯
(Port)
PB1 I/O
A17 output
REFOUT
IRQ4 input
(Port)
(BSC)
output
(INTC)
(IIC3)
input (ADC)
(BSC)
PB0 I/O
A16 output
(Port)
(BSC)
Page 1108 of 1778
⎯
IRQ3 input
⎯
⎯
⎯
⎯
⎯
(INTC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.7 Multiplexed Pins (SH7243 Port C)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
C
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
⎯
IRQ2 input
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PC15 I/O
A15 output
(Port)
(BSC)
PC14 I/O
A14 output
(Port)
(BSC)
PC13 I/O
A13 output
(Port)
(BSC)
PC12 I/O
A12 output
(Port)
(BSC)
PC11 I/O
A11 output
(Port)
(BSC)
PC10 I/O
A10 output
(Port)
(BSC)
PC9 I/O
A9 output
(Port)
(BSC)
PC8 I/O
A8 output
(Port)
(BSC)
PC7 I/O
A7 output
(Port)
(BSC)
PC6 I/O
A6 output
(Port)
(BSC)
PC5 I/O
A5 output
(Port)
(BSC)
PC4 I/O
A4 output
(Port)
(BSC)
PC3 I/O
A3 output
(Port)
(BSC)
PC2 I/O
A2 output
(Port)
(BSC)
PC1 I/O
A1 output
(Port)
(BSC)
PC0 I/O
A0 output
(Port)
(BSC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
(INTC)
⎯
IRQ1 input
(INTC)
⎯
IRQ0 input
(INTC)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TRST input
(H-UDI)
⎯
⎯
⎯
⎯
⎯
⎯
TMS input
(H-UDI)
⎯
⎯
⎯
⎯
⎯
⎯
TCK input
(H-UDI)
⎯
⎯
⎯
⎯
⎯
⎯
TDO output
(H-UDI)
⎯
⎯
POE0 input ⎯
(POE2)
⎯
⎯
TDI input
(H-UDI)
Page 1109 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.8 Multiplexed Pins (SH7285 and SH7286 Port C)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
C
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
⎯
IRQ2 input
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PC15 I/O
A15 output
(Port)
(BSC)
PC14 I/O
A14 output
(Port)
(BSC)
PC13 I/O
A13 output
(Port)
(BSC)
PC12 I/O
A12 output
(Port)
(BSC)
PC11 I/O
A11 output
(Port)
(BSC)
PC10 I/O
A10 output
(Port)
(BSC)
PC9 I/O
A9 output
(Port)
(BSC)
PC8 I/O
A8 output
(Port)
(BSC)
PC7 I/O
A7 output
(Port)
(BSC)
PC6 I/O
A6 output
(Port)
(BSC)
PC5 I/O
A5 output
(Port)
(BSC)
PC4 I/O
A4 output
(Port)
(BSC)
PC3 I/O
A3 output
(Port)
(BSC)
PC2 I/O
A2 output
(Port)
(BSC)
PC1 I/O
A1 output
(Port)
(BSC)
PC0 I/O
A0 output
(Port)
(BSC)
Page 1110 of 1778
(INTC)
⎯
IRQ1 input
(INTC)
⎯
IRQ0 input
(INTC)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
POE0 input ⎯
⎯
⎯
⎯
(POE2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.9 Multiplexed Pins (SH7243 Port D)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
D
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
⎯
⎯
TIOC4DS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
AUDCK
⎯
PD15 I/O
D15 I/O
(Port)
(BSC)
PD14 I/O
D14 I/O
(Port)
(BSC)
I/O
(MTU2S)
⎯
⎯
TIOC4CS
I/O
(MTU2S)
PD13 I/O
D13 I/O
(Port)
(BSC)
⎯
⎯
TIOC4BS
I/O
(MTU2S)
PD12 I/O
D12 I/O
(Port)
(BSC)
⎯
⎯
TIOC4AS
I/O
(MTU2S)
PD11 I/O
D11 I/O
(Port)
(BSC)
⎯
⎯
TIOC3DS
I/O
(MTU2S)
PD10 I/O
D10 I/O
(Port)
(BSC)
⎯
⎯
TIOC3BS
I/O
(MTU2S)
PD9 I/O
D9 I/O
(Port)
(BSC)
⎯
⎯
TIOC3CS
I/O
(MTU2S)
PD8 I/O
D8 I/O
(Port)
(BSC)
PD7 I/O
D7 I/O
(Port)
(BSC)
PD6 I/O
D6 I/O
(Port)
(BSC)
⎯
⎯
⎯
⎯
TIOC3AS
I/O
output
(MTU2S)
(AUD)
TIC5WS
⎯
⎯
input
PD5 I/O
D5 I/O
(Port)
(BSC)
PD4 I/O
D4 I/O
(Port)
(BSC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
⎯
⎯
⎯
⎯
⎯
TIC5VS
(AUD)
⎯
⎯
AUDATA2
input
output
(MTU2S)
(AUD)
TIC5US
⎯
⎯
AUDATA1
input
output
(MTU2S)
(AUD)
⎯
⎯
output
(MTU2S)
⎯
AUDATA3
⎯
TIC5W
AUDATA0
input
output
(MTU2)
(AUD)
⎯
⎯
⎯
Page 1111 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
D
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PD3 I/O
D3 I/O
⎯
⎯
⎯
⎯
TIC5V input AUDSYNC
(Port)
(BSC)
(MTU2)
⎯
output
(AUD)
PD2 I/O
D2 I/O
(Port)
(BSC)
PD1 I/O
D1 I/O
(Port)
(BSC)
PD0 I/O
D0 I/O
(Port)
(BSC)
Page 1112 of 1778
⎯
⎯
⎯
⎯
TIC5U input ⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.10 Multiplexed Pins (SH7285 Port D)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
D
PD31 I/O
(Port)
⎯
⎯
⎯
TIOC3AS
I/O
(MTU2S)
⎯
⎯
ADTRG
⎯
input (ADC)
PD30 I/O
(Port)
⎯
⎯
IRQOUT
output
(INTC)/
REFOUT
output
(BSC)
TIOC3CS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD29 I/O
(Port)
⎯
⎯
⎯
TIOC3BS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD28 I/O
(Port)
⎯
⎯
⎯
TIOC3DS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD27 I/O
(Port)
⎯
DACK0
output
(DMAC)
⎯
TIOC4AS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD26 I/O
(Port)
⎯
DACK1
output
(DMAC)
⎯
TIOC4BS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD25 I/O
(Port)
⎯
DREQ1
input
(DMAC)
⎯
TIOC4CS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD24 I/O
(Port)
⎯
DREQ0
input
(DMAC)
⎯
TIOC4DS
I/O
(MTU2S)
⎯
⎯
AUDCK
output
(AUD)
⎯
PD22 I/O
(Port)
⎯
⎯
IRQ6 input
(INTC)
TIC5US
input
(MTU2S)
RXD4 input ⎯
(SCI)
AUDSYNC
output
(AUD)
⎯
PD21 I/O
(Port)
⎯
⎯
IRQ5 input
(INTC)
TIC5VS
input
(MTU2S)
TXD4
⎯
output (SCI)
⎯
⎯
PD20 I/O
(Port)
⎯
⎯
IRQ4 input
(INTC)
TIC5WS
input
(MTU2S)
SCK4 I/O
(SCI)
POE8 input ⎯
(PDE2)
⎯
PD19 I/O
(Port)
⎯
CS0 output IRQ3 input
(BSC)
(INTC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
POE7 input RXD3 input ⎯
(POE2)
(SCIF)
AUDATA3
output
(AUD)
⎯
Page 1113 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
D
⎯
⎯
AUDATA2
⎯
PD18 I/O
(Port)
PD17 I/O
⎯
(Port)
CS1 output IRQ2 input
POE6 input TXD3
(BSC)
(POE2)
(INTC)
output
output
(SCIF)
(AUD)
CS2 output IRQ1 input
POE5 input SCK3 I/O
(BSC)
(POE2)
(INTC)
⎯
(SCIF)
AUDATA1
⎯
output
(AUD)
PD16 I/O
⎯
(Port)
CS3 output IRQ0 input
(BSC)
⎯
⎯
⎯
(INTC)
AUDATA0
⎯
output
(AUD)
PD15 I/O
D15 I/O
(Port)
(BSC)
⎯
⎯
TIOC4DS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I/O
(MTU2S)
PD14 I/O
D14 I/O
(Port)
(BSC)
⎯
⎯
TIOC4CS
I/O
(MTU2S)
PD13 I/O
D13 I/O
(Port)
(BSC)
⎯
⎯
TIOC4BS
I/O
(MTU2S)
PD12 I/O
D12 I/O
(Port)
(BSC)
PD11 I/O
D11 I/O
(Port)
(BSC)
⎯
⎯
TIOC4AS
I/O
(MTU2S)
⎯
⎯
TIOC3DS
I/O
(MTU2S)
PD10 I/O
D10 I/O
(Port)
(BSC)
⎯
⎯
TIOC3BS
I/O
(MTU2S)
PD9 I/O
D9 I/O
(Port)
(BSC)
⎯
⎯
TIOC3CS
I/O
(MTU2S)
PD8 I/O
D8 I/O
(Port)
(BSC)
⎯
⎯
TIOC3AS
I/O
(MTU2S)
PD7 I/O
D7 I/O
(Port)
(BSC)
⎯
⎯
TIC5WS
input
(MTU2S)
Page 1114 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
D
PD6 I/O
D6 I/O
⎯
⎯
TIC5VS
⎯
⎯
⎯
⎯
(Port)
(BSC)
⎯
⎯
⎯
⎯
TIC5W
⎯
⎯
⎯
TIC5V input ⎯
⎯
⎯
⎯
⎯
input
(MTU2S)
PD5 I/O
D5 I/O
(Port)
(BSC)
⎯
⎯
TIC5US
input
(MTU2S)
PD4 I/O
D4 I/O
(Port)
(BSC)
⎯
⎯
⎯
input
(MTU2)
PD3 I/O
D3 I/O
(Port)
(BSC)
PD2 I/O
D2 I/O
(Port)
(BSC)
PD1 I/O
D1 I/O
(Port)
(BSC)
PD0 I/O
D0 I/O
(Port)
(BSC)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
⎯
⎯
⎯
(MTU2)
⎯
⎯
⎯
TIC5U input ⎯
(MTU2)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Page 1115 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.11 Multiplexed Pins (SH7286 Port D)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
D
PD31 I/O
(Port)
D31 I/O
(BSC)
⎯
⎯
TIOC3AS
I/O
(MTU2S)
⎯
⎯
ADTRG
⎯
input (ADC)
PD30 I/O
(Port)
D30 I/O
(BSC)
⎯
IRQOUT
output
(INTC)/
REFOUT
output
(BSC)
TIOC3CS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD29 I/O
(Port)
D29 I/O
(BSC)
⎯
⎯
TIOC3BS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD28 I/O
(Port)
D28 I/O
(BSC)
⎯
⎯
TIOC3DS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD27 I/O
(Port)
D27 I/O
(BSC)
DACK0
output
(DMAC)
⎯
TIOC4AS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD26 I/O
(Port)
D26 I/O
(BSC)
DACK1
output
(DMAC)
⎯
TIOC4BS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD25 I/O
(Port)
D25 I/O
(BSC)
DREQ1
input
(DMAC)
⎯
TIOC4CS
I/O
(MTU2S)
⎯
⎯
⎯
⎯
PD24 I/O
(Port)
D24 I/O
(BSC)
DREQ0
input
(DMAC)
⎯
TIOC4DS
I/O
(MTU2S)
⎯
⎯
AUDCK
output
(AUD)
⎯
PD23 I/O
(Port)
D23 I/O
(BSC)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PD22 I/O
(Port)
D22 I/O
(BSC)
⎯
IRQ6 input
(INTC)
TIC5US
input
(MTU2S)
RXD4 input ⎯
(SCI)
AUDSYNC
output
(AUD)
⎯
PD21 I/O
(Port)
D21 I/O
(BSC)
⎯
IRQ5 input
(INTC)
TIC5VS
input
(MTU2S)
TXD4
output
(SCI)
⎯
⎯
⎯
PD20 I/O
(Port)
D20 I/O
(BSC)
⎯
IRQ4 input
(INTC)
TIC5WS
input
(MTU2S)
SCK4 I/O
(SCI)
POE8 input ⎯
(POE2)
⎯
Page 1116 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
D
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PD19 I/O
D19 I/O
CS0 output IRQ3 input
POE7 input RXD3 input ⎯
AUDATA3
⎯
(Port)
(BSC)
(BSC)
(POE2)
output
(INTC)
(SCIF)
(AUD)
PD18 I/O
D18 I/O
CS1 output IRQ2 input
POE6 input TXD3
(Port)
(BSC)
(BSC)
(POE2)
(INTC)
AUDATA2
output
(SCIF)
(AUD)
PD17 I/O
D17 I/O
CS2 output IRQ1 input
POE5 input SCK3 I/O
(Port)
(BSC)
(BSC)
(POE2)
(INTC)
⎯
output
⎯
(SCIF)
AUDATA1
⎯
⎯
output
(AUD)
PD16 I/O
D16 I/O
CS3 output IRQ0 input
(Port)
(BSC)
(BSC)
⎯
⎯
⎯
(INTC)
AUDATA0
⎯
output
(AUD)
PD15 I/O
D15 I/O
(Port)
(BSC)
⎯
⎯
TIOC4DS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I/O
(MTU2S)
PD14 I/O
D14 I/O
(Port)
(BSC)
⎯
⎯
TIOC4CS
I/O
(MTU2S)
PD13 I/O
D13 I/O
(Port)
(BSC)
PD12 I/O
D12 I/O
(Port)
(BSC)
⎯
⎯
TIOC4BS
I/O
(MTU2S)
⎯
⎯
TIOC4AS
I/O
(MTU2S)
PD11 I/O
D11 I/O
(Port)
(BSC)
⎯
⎯
TIOC3DS
I/O
(MTU2S)
PD10 I/O
D10 I/O
(Port)
(BSC)
⎯
⎯
TIOC3BS
I/O
(MTU2S)
PD9 I/O
D9 I/O
(Port)
(BSC)
⎯
⎯
TIOC3CS
I/O
(MTU2S)
PD8 I/O
D8 I/O
(Port)
(BSC)
⎯
⎯
TIOC3AS
I/O
(MTU2S)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1117 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
D
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PD7 I/O
D7 I/O
⎯
⎯
TIC5WS
⎯
⎯
⎯
⎯
(Port)
(BSC)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TIC5W
⎯
⎯
TIC5V input ⎯
⎯
input
(MTU2S)
PD6 I/O
D6 I/O
(Port)
(BSC)
⎯
⎯
TIC5VS
input
(MTU2S)
PD5 I/O
D5 I/O
(Port)
(BSC)
⎯
⎯
TIC5US
input
(MTU2S)
PD4 I/O
D4 I/O
(Port)
(BSC)
⎯
⎯
⎯
input
(MTU2)
PD3 I/O
D3 I/O
(Port)
(BSC)
PD2 I/O
D2 I/O
(Port)
(BSC)
PD1 I/O
D1 I/O
(Port)
(BSC)
PD0 I/O
D0 I/O
(Port)
(BSC)
Page 1118 of 1778
⎯
⎯
⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
TIC5U input ⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.12 Multiplexed Pins (SH7243 Port E)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
E
PE15 I/O
⎯
DACK1
IRQOUT
⎯
⎯
TIOC4D I/O ⎯
output
output
(DMAC)
(INTC)/
(Port)
⎯
(MTU2)
REFOUT
output
(BSC)
PE14 I/O
⎯
(Port)
DACK0
⎯
⎯
⎯
output
TIOC4C I/O ⎯
⎯
(MTU2)
(DMAC)
PE13 I/O
⎯
⎯
(Port)
MRES input ⎯
⎯
(system
TIOC4B I/O ⎯
⎯
(MTU2)
control)
PE12 I/O
⎯
⎯
⎯
⎯
⎯
(Port)
PE11 I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TXD2
TIOC3C I/O ⎯
⎯
output (SCI) (MTU2)
⎯
⎯
⎯
⎯
⎯
(Port)
PE8 I/O
TIOC3D I/O ⎯
(MTU2)
(Port)
PE9 I/O
⎯
(MTU2)
(Port)
PE10 I/O
TIOC4A I/O ⎯
TIOC3B I/O ⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
(Port)
PE7 I/O
BS output
(Port)
(BSC)
⎯
UBCTRG
⎯
output
SCK2 I/O
TIOC3A I/O ⎯
(SCI)
(MTU2)
RXD2 input TIOC2B I/O ⎯
(SCI)
(MTU2)
TIOC3DS
SCK3 I/O
TIOC2A I/O ⎯
I/O
(SCIF)
(MTU2)
TIOC3BS
TXD3
TIOC1B I/O ⎯
I/O
output
(MTU2)
(MTU2S)
(SCIF)
⎯
⎯
(UBC)
PE6 I/O
⎯
⎯
⎯
(Port)
⎯
(MTU2S)
PE5 I/O
⎯
⎯
⎯
(Port)
PE4 I/O
⎯
⎯
⎯
⎯
(Port)
PE3 I/O
⎯
(Port)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
TEND1
⎯
TIOC4DS
output
I/O
(DMAC)
(MTU2S)
RXD3 input TIOC1A I/O ⎯
(SCIF)
(MTU2)
⎯
TIOC0D I/O ⎯
⎯
⎯
⎯
(MTU2)
Page 1119 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
E
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PE2 I/O
⎯
DREQ1
⎯
TIOC4CS
⎯
TIOC0C I/O ⎯
(Port)
PE1 I/O
⎯
(Port)
PE0 I/O
(Port)
Page 1120 of 1778
⎯
input
I/O
(DMAC)
(MTU2S)
TEND0
⎯
TIOC4BS
output
I/O
(DMAC)
(MTU2S)
DREQ0
⎯
TIOC4AS
input
I/O
(DMAC)
(MTU2S)
⎯
(MTU2)
⎯
TIOC0B I/O ⎯
⎯
(MTU2)
⎯
TIOC0A I/O ⎯
⎯
(MTU2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.13 Multiplexed Pins (SH7285 Port E)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
E
PE15 I/O
(Port)
⎯
DACK1
output
(DMAC)
IRQOUT
output
(INTC)/
REFOUT
output
(BSC)
⎯
⎯
TIOC4D I/O ⎯
(MTU2)
⎯
PE14 I/O
(Port)
AH output
(BSC)
DACK0
output
(DMAC)
⎯
⎯
⎯
TIOC4C I/O ⎯
(MTU2)
⎯
PE13 I/O
(Port)
⎯
⎯
MRES
input
(system
control)
⎯
⎯
TIOC4B I/O ⎯
(MTU2)
⎯
PE12 I/O
(Port)
⎯
⎯
⎯
⎯
⎯
TIOC4A I/O ⎯
(MTU2)
⎯
PE11 I/O
(Port)
⎯
⎯
⎯
⎯
⎯
TIOC3D I/O ⎯
(MTU2)
⎯
PE10 I/O
(Port)
⎯
⎯
⎯
⎯
TXD2
output
(SCI)
TIOC3C I/O ⎯
(MTU2)
⎯
PE9 I/O
(Port)
⎯
⎯
⎯
⎯
⎯
TIOC3B I/O ⎯
(MTU2)
⎯
PE8 I/O
(Port)
⎯
⎯
⎯
⎯
SCK2 I/O
(SCI)
TIOC3A I/O ⎯
(MTU2)
⎯
PE7 I/O
(Port)
BS output
(BSC)
⎯
UBCTRG
output
(UBC)
⎯
RXD2 input TIOC2B I/O ⎯
(SCI)
(MTU2)
⎯
PE6 I/O
(Port)
⎯
⎯
⎯
TIOC3DS
I/O
(MTU2S)
SCK3 I/O
(SCIF)
TIOC2A I/O ⎯
(MTU2)
⎯
PE5 I/O
(Port)
⎯
⎯
⎯
TIOC3BS
I/O
(MTU2S)
TXD3
output
(SCIF)
TIOC1B I/O ⎯
(MTU2)
⎯
PE4 I/O
(Port)
⎯
⎯
⎯
⎯
RXD3 input TIOC1A I/O ⎯
(SCIF)
(MTU2)
⎯
PE3 I/O
(Port)
⎯
TEND1
output
(DMAC)
⎯
TIOC4DS
I/O
(MTU2S)
⎯
⎯
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
TIOC0D I/O ⎯
(MTU2)
Page 1121 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
E
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PE2 I/O
⎯
DREQ1
⎯
TIOC4CS
⎯
TIOC0C I/O ⎯
(Port)
PE1 I/O
⎯
(Port)
PE0 I/O
(Port)
Page 1122 of 1778
⎯
input
I/O
(DMAC)
(MTU2S)
TEND0
⎯
TIOC4BS
output
I/O
(DMAC)
(MTU2S)
DREQ0
⎯
TIOC4AS
input
I/O
(DMAC)
(MTU2S)
⎯
(MTU2)
⎯
TIOC0B I/O ⎯
⎯
(MTU2)
⎯
TIOC0A I/O ⎯
⎯
(MTU2)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.14 Multiplexed Pins (SH7286 Port E)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Port
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
E
PE15 I/O
⎯
DACK1
IRQOUT
⎯
⎯
TIOC4D I/O ⎯
output
output
(Port)
(DMAC)
(INTC)
PE14 I/O
AH output
DACK0
⎯
(Port)
(BSC)
output
⎯
(MTU2)
⎯
⎯
TIOC4C I/O ⎯
⎯
(MTU2)
(DMAC)
PE13 I/O
⎯
⎯
(Port)
MRES
⎯
⎯
input
TIOC4B I/O ⎯
⎯
(MTU2)
(system
control)
PE12 I/O
⎯
⎯
⎯
⎯
⎯
(Port)
PE11 I/O
⎯
(MTU2)
⎯
⎯
⎯
⎯
⎯
(Port)
PE10 I/O
TIOC4A I/O ⎯
TIOC3D I/O ⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
(Port)
TXD2
TIOC3C I/O ⎯
output
(MTU2)
⎯
(SCI)
PE9 I/O
⎯
⎯
⎯
⎯
⎯
(Port)
PE8 I/O
TIOC3B I/O ⎯
⎯
(MTU2)
⎯
⎯
⎯
⎯
(Port)
PE7 I/O
BS output
(Port)
(BSC)
⎯
UBCTRG
⎯
output
SCK2 I/O
TIOC3A I/O ⎯
(SCI)
(MTU2)
RXD2 input TIOC2B I/O ⎯
(SCI)
(MTU2)
TIOC3DS
SCK3 I/O
TIOC2A I/O ⎯
I/O
(SCIF)
(MTU2)
TIOC3BS
TXD3
TIOC1B I/O ⎯
I/O
output
(MTU2)
(MTU2S)
(SCIF)
⎯
RXD3 input TIOC1A I/O ⎯
⎯
⎯
(UBC)
PE6 I/O
⎯
⎯
⎯
(Port)
⎯
(MTU2S)
PE5 I/O
⎯
⎯
⎯
(Port)
PE4 I/O
⎯
⎯
⎯
(Port)
PE3 I/O
⎯
(Port)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
TEND1
⎯
TIOC4DS
output
I/O
(DMAC)
(MTU2S)
(SCIF)
(MTU2)
⎯
TIOC0D I/O ⎯
⎯
⎯
⎯
(MTU2)
Page 1123 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
E
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
PE2 I/O
⎯
DREQ1
⎯
TIOC4CS
⎯
TIOC0C I/O ⎯
(Port)
PE1 I/O
⎯
(Port)
PE0 I/O
⎯
(Port)
input
I/O
(DMAC)
(MTU2S)
TEND0
⎯
TIOC4BS
output
I/O
(DMAC)
(MTU2S)
DREQ0
⎯
TIOC4AS
input
I/O
(DMAC)
(MTU2S)
⎯
(MTU2)
⎯
TIOC0B I/O ⎯
⎯
(MTU2)
⎯
TIOC0A I/O ⎯
⎯
(MTU2)
Table 23.15 Multiplexed Pins (SH7285 and SH7243 Port F)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
F
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PF7 input
AN7 input
(Port)
(ADC)
PF6 input
AN6 input
(Port)
(ADC)
PF5 input
AN5 input
(Port)
(ADC)
PF4 input
AN4 input
(Port)
(ADC)
PF3 input
AN3 input
(Port)
(ADC)
PF2 input
AN2 input
(Port)
(ADC)
PF1 input
AN1 input
(Port)
(ADC)
PF0 input
AN0 input
(Port)
(ADC)
Note: AN input function is valid during A/D conversion.
Page 1124 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Table 23.16 Multiplexed Pins (SH7286 Port F)
Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 Function 9
Port
F
Note:
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
(Related
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
Module)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PF11 input
AN11 input ⎯
(Port)
(ADC)
PF10 input
AN10 input ⎯
(Port)
(ADC)
PF9 input
AN9 input
(Port)
(ADC)
PF8 input
AN8 input
(Port)
(ADC)
PF7 input
AN7 input
(Port)
(ADC)
PF6 input
AN6 input
(Port)
(ADC)
PF5 input
AN5 input
(Port)
(ADC)
PF4 input
AN4 input
(Port)
(ADC)
PF3 input
AN3 input
(Port)
(ADC)
PF2 input
AN2 input
(Port)
(ADC)
PF1 input
AN1 input
(Port)
(ADC)
PF0 input
AN0 input
(Port)
(ADC)
AN input function is valid during A/D conversion.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1125 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1
Register Descriptions
The PFC has the following registers. See section 30, List of Registers for register addresses and
register states in each operating mode.
Table 23.17 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port A I/O register H
PAIORH
R/W
H'0000
H'FFFE3804
8, 16, 32
Port A I/O register L
PAIORL
R/W
H'0000
H'FFFE3806
8, 16
Port A control register H2
PACRH2
R/W
H'0000
H'FFFE380C
8, 16, 32
Port A control register L4
PACRL4
R/W
H'0000*
H'FFFE3810
8, 16, 32
Port A control register L3
PACRL3
R/W
H'0000*
H'FFFE3812
8, 16
Port A control register L2
PACRL2
R/W
H'0000
H'FFFE3814
8, 16, 32
Port A control register L1
PACRL1
R/W
H'0000
H'FFFE3816
8, 16
Port A pull-up MOS control PAPCRH
register H
R/W
H'0000
H'FFFE3828
8, 16, 32
Port A pull-up MOS control PAPCRL
register L
R/W
H'0000
H'FFFE382A
8, 16
Port B I/O register H
PBIORH
R/W
H'0000
H'FFFE3884
8, 16, 32
Port B I/O register L
PBIORL
R/W
H'0000
H'FFFE3886
8, 16
Port B control register H1
PBCRH1
R/W
H'0000*
H'FFFE388E
8, 16
Port B control register L4
PBCRL4
R/W
H'0000*
H'FFFE3890
8, 16, 32
Port B control register L3
PBCRL3
R/W
H'0000*
H'FFFE3892
8, 16
Port B control register L2
PBCRL2
R/W
H'0000*
H'FFFE3894
8, 16, 32
Port B control register L1
PBCRL1
R/W
H'0000*
H'FFFE3896
8, 16
Port B pull-up MOS control PBPCRH
register H
R/W
H'0000
H'FFFE38A8
8, 16, 32
Port B pull-up MOS control PBPCRL
register L
R/W
H'0000
H'FFFE38AA
8, 16
Port C I/O register L
PCIORL
R/W
H'0000
H'FFFE3906
8, 16
Port C control register L4
PCCRL4
R/W
H'0000*
H'FFFE3910
8, 16, 32
Port C control register L3
PCCRL3
R/W
H'0000*
H'FFFE3912
8, 16
Port C control register L2
PCCRL2
R/W
H'0000*
H'FFFE3914
8, 16, 32
Port C control register L1
PCCRL1
R/W
H'0000*
H'FFFE3916
8, 16
Page 1126 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port C pull-up MOS
control register L
PCPCRL
R/W
H'0000
H'FFFE392A
8, 16
Port D I/O register H
PDIORH
R/W
H'0000
H'FFFE3984
8, 16, 32
Port D I/O register L
PDIORL
R/W
H'0000
H'FFFE3986
8, 16
Port D control register H4
PDCRH4
R/W
H'0000*
H'FFFE3988
8, 16, 32
Port D control register H3
PDCRH3
R/W
H'0000*
H'FFFE398A
8, 16
Port D control register H2
PDCRH2
R/W
H'0000*
H'FFFE398C
8, 16, 32
Port D control register H1
PDCRH1
R/W
H'0000*
H'FFFE398E
8, 16
Port D control register L4
PDCRL4
R/W
H'0000*
H'FFFE3990
8, 16, 32
Port D control register L3
PDCRL3
R/W
H'0000*
H'FFFE3992
8, 16
Port D control register L2
PDCRL2
R/W
H'0000*
H'FFFE3994
8, 16, 32
Port D control register L1
PDCRL1
R/W
H'0000*
H'FFFE3996
8, 16
Port D pull-up MOS
control register H
PDPCRH
R/W
H'0000
H'FFFE39A8
8, 16, 32
Port D pull-up MOS
control register L
PDPCRL
R/W
H'0000
H'FFFE39AA
8, 16
Port E I/O register L
PEIORL
R/W
H'0000
H'FFFE3A06
8, 16
Port E control registerL4
PECRL4
R/W
H'0000
H'FFFE3A10
8, 16, 32
Port E control register L3
PECRL3
R/W
H'0000
H'FFFE3A12
8, 16
Port E control register L2
PECRL2
R/W
H'0000
H'FFFE3A14
8, 16, 32
Port E control register L1
PECRL1
R/W
H'0000
H'FFFE3A16
8, 16
Large current Port control
register
HCPCR
R/W
H'000F
H'FFFE3A20
8, 16, 32
IRQOUT function control
register
IFCR
R/W
H'0000
H'FFFE3A22
8, 16
R/W
H'0000
H'FFFE3A2A
8, 16
Port E pull-up MOS control PEPCRL
register L
Note:
*
The initial values of registers in each product vary according to the setting of the
operating mode. See the description of each register in this section for details.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1127 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.1
Port A I/O Registers H and L (PAIORH and PAIORL)
PAIORH and PAIORL are 16-bit readable/writable registers that are used to set the pins on port A
as inputs or outputs. Bits PA23IOR to PA21IOR, PA15IOR to PA0IOR correspond to pins PA23
to PA21, PA15 to PA0 (multiplexed port pin names except for the port names are abbreviated
here). PAIORH and PAIORL are enabled when the port A pins are functioning as general-purpose
inputs/outputs (PA23 to PA21 for PAIORH and PA15 to PA0 for PAIORL). In other states, they
are disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORH or
PAIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 7 to 5 of PAIORH and
bits 11, 10 and 5 to 0 of PAIORL are disabled in SH7243, and bits 11 and 10 of PAIORL are
disabled in SH7285.
Bits 15 to 8, 4 to 0 of PAIORH are reserved. These bits are always read as 0. The write value
should always be 0.
The initial values of PAIORL and PAIORH are H'0000.
• Port A I/O Register H (PAIORH)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
PA23
IOR
PA22
IOR
PA21
IOR
-
-
-
-
0
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
• Port A I/O Register L (PAIORL)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
IOR
PA14
IOR
PA13
IOR
PA12
IOR
PA11
IOR
PA10
IOR
PA9
IOR
PA8
IOR
PA7
IOR
PA6
IOR
PA5
IOR
PA4
IOR
PA3
IOR
PA2
IOR
PA1
IOR
PA0
IOR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit:
Page 1128 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
23.1.2
Section 23 Pin Function Controller (PFC)
Port A Control Registers H2, L1 to L4 (PACRH2, PACRL1 to PACRL4)
PACRH2 and PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select
the functions of the multiplexed pins on port A.
(1)
SH7243
• Port A Control Register H2 (PACRH2)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
0
These bits are always read as 0. The write value
should always be 0.
• Port A Control Register L4 (PACRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PA15MD[2:0]
0
R/W
0*2
R/W
0
R/W
11
10
-
9
8
PA14MD[2:0]
0
R
0
R/W
0
R/W
0*1
R/W
7
-
0
R
6
5
4
PA13MD[2:0]
0
R/W
0
R/W
0*1
R/W
3
-
0
R
2
1
0
PA12MD[2:0]
0
R/W
0
R/W
0*1
R/W
Notes: 1. The initial value is 1 during the on-chip ROM disabled external extension mode.
2. The initial value is 1 during the on-chip ROM enabled/disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1129 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
R/W
Description
14 to 12 PA15MD[2:0] 000*²
R/W
PA15 Mode
Bit
Bit Name
Select the function of the PA15/CK output pin.
000: PA15 I/O (port)
001: CK output (BSC)
010: Setting prohibited
011: Setting prohibited)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA14MD[2:0] 000*¹
R/W
PA14 Mode
Select the function of the PA14/RD pin.
000: PA14 I/O (port)
001: RD output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1130 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PA13MD[2:0] 000*¹
R/W
PA13 Mode
Select the function of the PA13/WRL/DQMLL pin.
000: PA13 I/O (port)
001: WRL output, DQMLL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA12MD[2:0] 000*¹
R/W
PA12 Mode
Select the function of the PA12/WRH/DQMLU/POE8
pin.
000: PA12 I/O (port)
001: WRH output, DQMLU output (BSC)
010: Setting prohibited
011: Setting prohibited
100: POE8 input (POE2)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Notes: 1. The initial value is 1 during the on-chip ROM disabled external extension mode.
2. The initial value is 1 during the on-chip ROM enabled/disabled external extension
mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1131 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L3 (PACRL3)
Bit:
15
14
13
12
11
10
9
8
7
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 7
⎯
All 0
R
Reserved
6
5
4
PA9MD[2:0]
0
R/W
0
R/W
3
2
0
R/W
0
R
1
0
PA8MD[2:0]
-
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
6 to 4
PA9MD[2:0]
000
R/W
PA9 Mode
Select the function of the PA9/CKE/RXD3/TCLKD pin.
000: PA9 I/O (port)
001: CKE output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 input (SCIF)
110: TCLKD input (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA8MD[2:0]
000
R/W
PA8 Mode
Select the function of the PA8/RDWR/TXD3/TCLKC
pin.
000: PA8 I/O (port)
001: RDWR output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD3 output (SCIF)
110: TCLKC input (MTU2)
111: Setting prohibited
Page 1132 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L2 (PACRL2)
Bit:
15
14
-
13
12
0
R/W
0
R/W
11
10
-
PA7MD[2:0]
0
R/W
9
8
PA6MD[2:0]
0
R
0
R/W
0
R/W
0
R/W
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PA7MD[2:0]
000
R/W
PA7 Mode
Select the function of the PA7/CASL/SCK3/TCLKB
pin.
000: PA7 I/O (port)
001: CASL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK3 I/O (SCIF)
110: TCLKB input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA6MD[2:0]
000
R/W
PA6 Mode
Select the function of the PA6/RASL/TCLKA pin.
000: PA6 I/O (port)
001: RASL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TCLKA input (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1133 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port A Control Register L1 (PACRL1)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
(2)
SH7285
• Port A Control Register H2 (PACRH2)
Bit:
15
-
14
13
12
PA23MD[2:0]
0
R/W
0
R/W
0
R/W
11
10
-
9
8
PA22MD[2:0]
0
R
0
R/W
0
R/W
0
R/W
7
-
Initial value:
R/W:
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
6
5
4
PA21MD[2:0]
0
R/W
0
R/W
0
R/W
3
2
1
-
-
-
0
-
0
R
0
R
0
R
0
R
This bit is always read as 0. The write value should
always be 0.
Page 1134 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
14 to 12
PA23MD[2:0] 000
R/W
Description
R/W
PA23 Mode
Select the function of the
PA23/CKE/AH/IRQ1/POE0/TIC5W pin.
000: PA23 I/O (port)
001: CKE output (BSC)
010: AH output (BSC)
011: IRQ1 input (INTC)
100: POE0 input (POE2)
101: Setting prohibited
110: TIC5W input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA22MD[2:0] 000
R/W
PA22 Mode
Select the function of the
PA22/CASL/CASU/IRQ2/POE4/TIC5V pin.
000: PA22 I/O (port)
001: CASL output (BSC)
010: CASU output (BSC)
011: IRQ2 input (INTC)
100: POE4 input (POE2)
101: Setting prohibited
110: TIC5V input (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1135 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
6 to 4
PA21MD[2:0] 000
R/W
Description
R/W
PA21 Mode
Select the function of the
PA21/RASL/RASU/IRQ3/POE8/TIC5U pin.
000: PA21 I/O (port)
001: RASL output (BSC)
010: RASU output (BSC)
011: IRQ3 input (INTC)
100: POE8 input (POE2)
101: Setting prohibited
110: TIC5U input (MTU2)
111: Setting prohibited
⎯
3 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port A Control Register L4 (PACRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PA15MD[2:0]
0
R/W
0*2
R/W
0
R/W
11
10
-
9
8
PA14MD[2:0]
0
R
0
R/W
0
R/W
0*1
R/W
7
-
0
R
6
5
4
PA13MD[2:0]
0
R/W
0
R/W
0*1
R/W
3
-
0
R
2
1
0
PA12MD[2:0]
0
R/W
0
R/W
0*1
R/W
Notes: 1. The initial value is 1 during the on-chip ROM disabled external extension mode.
2. The initial value is 1 during the on-chip ROM enabled/disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1136 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
Bit Name
14 to 12
PA15MD
[2:0]
Section 23 Pin Function Controller (PFC)
Initial
Value
R/W
Description
000*²
R/W
PA15 Mode
Select the function of the PA15/CK pin.
000: PA15 I/O (port)
001: CK output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA14MD
[2:0]
000*¹
R/W
PA14 Mode
Select the function of the PA14/RD pin.
000: PA14 I/O (port)
001: RD output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1137 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
6 to 4
PA13MD
[2:0]
Initial
Value
R/W
Description
000*¹
R/W
PA13 Mode
Select the function of the PA13/WRL/DQMLL pin.
000: PA13 I/O (port)
001: WRL output, DQMLL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA12MD
[2:0]
000*¹
R/W
PA12 Mode
Select the function of the PA12/WRH/DQMLU/POE8
pin.
000: PA12 I/O (port)
001: WRH output DQMLU output (BSC)
010: Setting prohibited
011: Setting prohibited
100: POE8 input (POE2)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Notes: 1. The initial value is 1 during the on-chip ROM disabled external extension mode.
2. The initial value is 1 during the on-chip ROM enabled/disabled external extension
mode.
Page 1138 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L3 (PACRL3)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
15 to 7
⎯
All 0
R
6
5
4
PA9MD[2:0]
0
R/W
0
R/W
3
2
0*
R/W
0
R
1
0
PA8MD[2:0]
-
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
6 to 4
PA9MD[2:0]
000*
R/W
PA9 Mode
Select the function of the PA9/CKE/RXD3/TCLKD pin.
000: PA9 I/O (port)
001: CKE output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 input (SCIF)
110: TCLKD input (MTU2)
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA8MD[2:0]
000
R/W
PA8 Mode
Select the function of the PA8/RDWR/TXD3/TCLKC
pin.
000: PA8 I/O (port)
001: RDWR output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 output (SCIF)
110: TCLKC input (MTU2)
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1139 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L2 (PACRL2)
Bit:
15
14
-
13
12
0
R/W
0
R/W
11
10
-
PA7MD[2:0]
0
R/W
9
8
0
R
0
R/W
0
R/W
7
6
-
PA6MD[2:0]
Initial value:
R/W:
0
R
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
5
4
0
R/W
0
R/W
3
2
-
PA5MD[2:0]
0
R/W
0
R
1
0
PA4MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PA7MD[2:0] 000
R/W
PA7 Mode
Select the function of the PA7/CASL/SCK3/TCLKB
pin.
000: PA7 I/O (port)
001: CASL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK3 output (SCIF)
110: TCLKB input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA6MD[2:0] 000
R/W
PA6 Mode
Select the function of the PA6/RASL/TCLKA pin.
000: PA6 I/O (port)
001: RASL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TCLKA input (MTU2)
111: Setting prohibited
Page 1140 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PA5MD[2:0] 000
R/W
PA5 Mode
Select the function of the PA5/CS5/SCK1/SSCK pin.
000: PA5 I/O (port)
001: CS5 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK1 I/O (SCI)
110: Setting prohibited
111: SSCK I/O (SSU)
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA4MD[2:0] 000
R/W
PA4 Mode
Select the function of the PA4/CS4/TXD1/SSO/TRST
pin. When using E10A (ASEMD0 = L), these bits are
fixed to TRST input.
000: PA4 I/O (port)
001: CS4 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD1 output (SCI)
110: Setting prohibited
111: SSO I/O (SSU)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1141 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L1 (PACRL1)
Bit:
15
14
-
13
12
0
R/W
0
R/W
11
10
-
PA3MD[2:0]
0
R/W
9
8
0
R
0
R/W
0
R/W
7
6
-
PA2MD[2:0]
Initial value:
R/W:
0
R
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
5
4
0
R/W
0
R/W
3
2
-
PA1MD[2:0]
0
R/W
0
R
1
0
PA0MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PA3MD[2:0] 000
R/W
PA3 Mode
Select the function of the PA3/CS3/RXD1/SSI/TMS
pin. When using E10A (ASEMD0 = L), these bits are
fixed to TMS input.
000: PA3 I/O (port)
001: CS3 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD1 input (SCI)
110: Setting prohibited
111: SSI I/O (SSU)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1142 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
10 to 8
PA2MD[2:0] 000
R/W
Description
R/W
PA2 Mode
Select the function of the PA2/CS2/SCK0/SCS/TCK
pin. When using E10A (ASEMD0 = L), these bits are
fixed to TCK input.
000: PA2 I/O (port)
001: CS2 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK0 I/O (SCI)
110: Setting prohibited
111: SCS I/O (SSU)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PA1MD[2:0] 000
R/W
PA1 Mode
Select the function of the PA1/CS1/TXD0/TDO pin.
When using E10A (ASEMD0 = L), these bits are fixed
to TDO input.
000: PA1 I/O (port)
001: CS1 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD0 output (SCI)
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1143 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
2 to 0
PA0MD[2:0] 000
R/W
Description
R/W
PA0 Mode
Select the function of the PA0/CS0/RXD0/TDI pin.
When using E10A (ASEMD0 = L), these bits are fixed
to TDI input
000: PA0 I/O (port)
001: CS0 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD0 input (SCI)
110: Setting prohibited
111: Setting prohibited
(3)
SH7286
• Port A Control Register H2 (PACRH2)
Bit:
15
-
14
13
12
PA23MD[2:0]
11
10
-
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
0
R/W
0
R/W
0
R/W
9
8
PA22MD[2:0]
0
R
0
R/W
0
R/W
0
R/W
7
-
0
R
6
5
4
PA21MD[2:0]
0
R/W
0
R/W
0
R/W
3
2
1
-
-
-
0
-
0
R
0
R
0
R
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1144 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
Bit Name
14 to 12
PA23MD
[2:0]
Section 23 Pin Function Controller (PFC)
Initial
Value
R/W
Description
000
R/W
PA23 Mode
Select the function of the
PA23/CKE/AH/IRQ1/POE0/TIC5W pin.
000: PA23 I/O (port)
001: CKE output (BSC)
010: AH output (BSC)
011: IRQ1 input (INTC)
100: POE0 input (POE2)
101: Setting prohibited
110: TIC5W input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA22MD
[2:0]
000
R/W
PA22 Mode
Select the function of the
PA22/CASL/CASU/IRQ2/POE4/TIC5V pin.
000: PA22 I/O (port)
001: CASL output (BSC)
010: CASU output (BSC)
011: IRQ2 input (INTC)
100: POE4 input (POE2)
101: Setting prohibited
110: TIC5V input (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1145 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
6 to 4
PA21MD
[2:0]
Initial
Value
R/W
Description
000
R/W
PA21 Mode
Select the function of the
PA21/RASL/RASU/IRQ3/POE8/TIC5U pin.
000: PA21 I/O (port)
001: RASL output (BSC)
010: RASU output (BSC)
011: IRQ3 input (INTC)
100: POE8 input (POE2)
101: Setting prohibited
110: TIC5U input (MTU2)
111: Setting prohibited
⎯
3 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port A Control Register L4 (PACRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PA15MD[2:0]
0
R/W
0*2
R/W
0
R/W
11
10
-
9
8
PA14MD[2:0]
0
R
0
R/W
0
R/W
0*1
R/W
7
-
0
R
6
5
4
PA13MD[2:0]
0
R/W
0
R/W
0*1
R/W
3
-
0
R
2
1
0
PA12MD[2:0]
0
R/W
0
R/W
0*1
R/W
Notes: 1. The initial value is 1 during the on-chip ROM disabled external extension mode.
2. The initial value is 1 during the on-chip ROM enabled/disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1146 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
Bit Name
14 to 12
PA15MD
[2:0]
Section 23 Pin Function Controller (PFC)
Initial
Value
R/W
Description
000*²
R/W
PA15 Mode
Select the function of the PA15/CK pin.
000: PA15 I/O (port)
001: CK output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA14MD
[2:0]
000*¹
R/W
PA14 Mode
Select the function of the PA14/RD pin.
000: PA14 I/O (port)
001: RD output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1147 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
6 to 4
PA13MD
[2:0]
Initial
Value
R/W
Description
000*¹
R/W
PA13 Mode
Select the function of the PA13/WRL/DQMLL pin.
000: PA13 I/O (port)
001: WRL output, DQMLL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA12MD
[2:0]
000*¹
R/W
PA12 Mode
Select the function of the PA12/WRH/DQMLU/POE8
pin.
000: PA12 I/O (port)
001: WRH output, DQMLU output (BSC)
010: Setting prohibited
011: Setting prohibited
100: POE8 input (POE2)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Notes: 1. The initial value is 1 during the on-chip ROM disabled external extension mode.
2. The initial value is 1 during the on-chip ROM enabled/disabled external extension
mode.
Page 1148 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L3 (PACRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PA11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
9
8
7
PA10MD[2:0]
-
0
R
0
R/W
0
R/W
0*
R/W
6
-
0
R
5
4
3
PA9MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PA8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PA11MD
[2:0]
000*
R/W
PA11 Mode
Select the function of the PA11/WRHH /DQMUU/AH
pin.
000: PA11 I/O (port)
001: WRHH output, DQMUU output and AH output
(BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1149 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
10 to 8
PA10MD
[2:0]
Initial
Value
R/W
Description
000*
R/W
PA10 Mode
Select the function of the PA10/WRHL/DQMUL pin.
000: PA10 I/O (port)
001: WRHL output, DQMUL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PA9MD[2:0] 000
R/W
PA9 Mode
Select the function of the PA9/CKE/RXD3/TCLKD pin.
000: PA9 I/O (port)
001: CKE output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 input (SCIF)
110: TCLKD input (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1150 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
2 to 0
PA8MD[2:0] 000*
R/W
Description
R/W
PA8 Mode
Select the function of the PA8/RDWR/TXD3/TCLKC
pin.
000: PA8 I/O (port)
001: RDWR output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD3 output (SCIF)
110: TCLKC input (MTU2)
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
• Port A Control Register L2 (PACRL2)
Bit:
15
14
-
13
12
0
R/W
0
R/W
11
10
-
PA7MD[2:0]
0
R/W
9
8
0
R
0
R/W
0
R/W
7
6
-
PA6MD[2:0]
Initial value:
R/W:
0
R
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
5
4
0
R/W
0
R/W
3
2
-
PA5MD[2:0]
0
R/W
0
R
1
0
PA4MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1151 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
14 to 12
PA7MD[2:0] 000
R/W
Description
R/W
PA7 Mode
Select the function of the PA7/CASL/SCK3/TCLKB
pin.
000: PA7 I/O (port)
001: CASL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK3 I/O (SCIF)
110: TCLKB input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PA6MD[2:0] 000
R/W
PA6 Mode
Select the function of the PA6/RASL/TCLKA pin.
000: PA6 I/O (port)
001: RASL output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TCLKA input (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1152 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
6 to 4
PA5MD[2:0] 000
R/W
Description
R/W
PA5 Mode
Select the function of the PA5/CS5/SCK1/SSCK pin.
000: PA5 I/O (port)
001: CS5 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK1 I/O (SCI)
110: Setting prohibited
111: SSCK I/O (SSU)
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PA4MD[2:0] 000
R/W
PA4 Mode
Select the function of the PA4/CS4/TXD1/SSO pin.
000: PA4 I/O (port)
001: CS4 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD1 output (SCI)
110: Setting prohibited
111: SSO I/O (SSU)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1153 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Control Register L1 (PACRL1)
Bit:
15
14
-
13
12
0
R/W
0
R/W
11
10
-
PA3MD[2:0]
0
R/W
9
8
0
R
0
R/W
0
R/W
7
6
-
PA2MD[2:0]
Initial value:
R/W:
0
R
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
5
4
0
R/W
0
R/W
3
2
-
PA1MD[2:0]
0
R/W
0
R
1
0
PA0MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PA3MD[2:0] 000
R/W
PA3 Mode
Select the function of the PA3/CS3/RXD1/SSI pin.
000: PA3 I/O (port)
001: CS3 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD1 output (SCI)
110: Setting prohibited
111: SSI I/O (SSU)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1154 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
10 to 8
PA2MD[2:0] 000
R/W
Description
R/W
PA2 Mode
Select the function of the PA2/CS2/SCK0/SCSpin.
000: PA2 I/O (port)
001: CS2 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK0 I/O (SCI)
110: Setting prohibited
111: SCS I/O (SSU)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PA1MD[2:0] 000
R/W
PA1 Mode
Select the function of the PA1/CS1/TXD0 pin.
000: PA1 I/O (port)
001: CS1 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD0 output (SCI)
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1155 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
2 to 0
PA0MD[2:0] 000
R/W
Description
R/W
PA0 Mode
Select the function of the PA0/CS0/RXD0 pin.
000: PA0 I/O (port)
001: CS0 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD0 input (SCI)
110: Setting prohibited
111: Setting prohibited
23.1.3
Port A Pull-Up MOS Control Registers H and L (PAPCRH and PAPCRL)
PAPCRH and PAPCRL control on and off of the input pull-up MOS of port A in bits.
(1)
SH7243
• Port A Pull-Up MOS Control Register H (PAPCRH)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
0
These bits are always read as 0. The write value
should always be 0.
Page 1156 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Pull-Up MOS Control Register L (PAPCRL)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PA15
PCR
PA14
PCR
PA13
PCR
PA12
PCR
-
-
PA9
PCR
PA8
PCR
PA7
PCR
PA6
PCR
-
-
-
-
-
0
-
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
PA15PCR
0
R/W
14
PA14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PA13PCR
0
R/W
12
PA12PCR
0
R/W
11, 10
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
PA9PCR
0
R/W
8
PA8PCR
0
R/W
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
5 to 0
⎯
All 0
R
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
(2)
SH7285
• Port A Pull-Up MOS Control Register H (PAPCRH)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
PA23
PCR
PA22
PCR
PA21
PCR
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
0
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1157 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
PA23PCR
0
R/W
6
PA22PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
5
PA21PCR
0
R/W
4 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port A Pull-Up MOS Control Register L (PAPCRL)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
PCR
PA14
PCR
PA13
PCR
PA12
PCR
-
-
PA9
PCR
PA8
PCR
PA7
PCR
PA6
PCR
PA5
PCR
PA4
PCR
PA3
PCR
PA2
PCR
PA1
PCR
PA0
PCR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PA15PCR
0
R/W
14
PA14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PA13PCR
0
R/W
12
PA12PCR
0
R/W
11, 10
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 1158 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
9
PA9PCR
0
R/W
8
PA8PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
5
PA5PCR
0
R/W
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
(3)
SH7286
• Port A Pull-Up MOS Control Register H (PAPCRH)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
PA23
PCR
PA22
PCR
PA21
PCR
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
0
These bits are always read as 0. The write value
should always be 0.
7
PA23PCR
0
R/W
6
PA22PCR
0
R/W
5
PA21PCR
0
R/W
4 to 0
⎯
All 0
R
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1159 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port A Pull-Up MOS Control Register (PAPCRL)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
PCR
PA14
PCR
PA13
PCR
PA12
PCR
PA11
PCR
PA10
PCR
PA9
PCR
PA8
PCR
PA7
PCR
PA6
PCR
PA5
PCR
PA4
PCR
PA3
PCR
PA2
PCR
PA1
PCR
PA0
PCR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PA15PCR
0
R/W
14
PA14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PA13PCR
0
R/W
12
PA12PCR
0
R/W
11
PA11PCR
0
R/W
10
PA10PCR
0
R/W
9
PA9PCR
0
R/W
8
PA8PCR
0
R/W
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
5
PA5PCR
0
R/W
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
Page 1160 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
23.1.4
Section 23 Pin Function Controller (PFC)
Port B I/O Registers H and L (PBIORH and PBIORL)
PBIORH and PBIORL are 16-bit readable/writable registers that are used to set the pins on port B
as inputs or outputs. Bits PB19IOR to PB6IOR, and PB3IOR to PB0IOR correspond to pins PB19
to PB6, and PB3 to PB0 respectively (multiplexed port pin names except for the port names are
abbreviated here). PAIORH and PAIORL are enabled when the port A pins are functioning as
general-purpose inputs/outputs (PB19 to PB16 for PAIORH and PB15 to PB0 for PAIORL). In
other states, they are disabled. A given pin on port B will be an output pin if the corresponding bit
in PAIORH or PAIORL is set to 1, and an input pin if the bit is cleared to 0. However, bits 3 to 0
of PBIORH and bits 15 to 13, 10, 9, 3 and 2 of PBIORL are disabled in SH7243, and bits 3 and 0
of PBIORH are disabled in SH7285.
Bits 15 to 4 of PBIORH and bits 5 and 4 of PBIORL are reserved. These bits are always read as 0.
The write value should always be 0. The initial values of PBIORH and PBIORL are H'0000.
• Port B I/O Register H (PBIORH)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
PB19
IOR
PB18
IOR
PB17
IOR
PB16
IOR
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
• Port B I/O Register L (PBIORL)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PB15
IOR
PB14
IOR
PB13
IOR
PB12
IOR
PB11
IOR
PB10
IOR
PB9
IOR
PB8
IOR
PB7
IOR
PB6
IOR
-
-
PB3
IOR
PB2
IOR
PB1
IOR
PB0
IOR
0
Initial value:
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1161 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.5
Port B Control Registers H1 and L1 to L4 (PBCRH1 and PBCRL1 to PBCRL4)
PBCRH1 and PBCRL1 to PBCRL4 are 16-bit readable/writable registers that are used to select
the function of the multiplexed pins on port B.
(1)
SH7243
• Port B Control Register H1 (PBCRH1)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
15 to 0
⎯
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port B Control Register L4 (PBCRL4)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
2
1
0
PB12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15 to 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 1162 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PB12MD[2:0]
000*
R/W
PB12 Mode
Select the function of the
PB12/CS1/CS7/IRQ1/TXD2/CS3 pin.
000: PB12 I/O (port)
001: CS1 output (BSC)
010: CS7 output (BSC)
011: IRQ1 input (INTC)
100: Setting prohibited
101: TXD3 output (SCI)
110: Setting prohibited
111: CS3 output (BSC)
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
• Port B Control Register L3 (PBCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PB11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
9
8
7
6
5
4
3
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
2
1
0
PB8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1163 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PB11MD[2:0]
000*
R/W
PB11 Mode
Select the function of the
PB11/CS0/CS6/IRQ0/RXD2/CS2 pin.
000: PB11 I/O (port)
001: CS0 output (BSC)
010: CS6 output (BSC)
011: IRQ0 input (INTC)
100: Setting prohibited
101: RXD2 input (SCI)
110: Setting prohibited
111: CS2 output (BSC)
⎯
11 to 3
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0
PB8MD[2:0]
000*
R
PB8 Mode
Select the function of the
PB8/A20/WAIT/IRQ7/POE8/SCK0 pin.
000: PB8 I/O (port)
001: A20 output (BSC)
010: WAIT input (BSC)
011: IRQ7 input (INTC)
100: POE8 input (POE2)
101: SCK0 I/O (SCI)
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1164 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port B Control Register L2 (PBCRL2)
Bit:
15
14
-
Initial value:
R/W:
0
R
13
12
PB7MD[2:0]
0
R/W
0
R/W
11
10
-
0*
R/W
0
R
0
R/W
7
6
5
4
3
2
1
PB6MD[2:0]
9
8
-
-
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0*
R/W
0
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PB7MD[2:0]
000*
R/W
PB7 Mode
Select the function of the
PB7/A19/BREQ/IRQ6/POE4/TXD0 pin.
000: PB7 I/O (port)
001: A19 output (BSC)
010: BREQ output (BSC)
011: IRQ6 input (INTC)
100: POE4 I/O (POE2)
101: TXD0 output (SCI)
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1165 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PB6MD[2:0]
000*
R/W
PB6 Mode
Select the function of the
PB6/A18/BACK/IRQ5/POE3/RXD0 pin.
000: PB6 I/O (port)
001: A18 output (BSC)
010: BACK output (BSC)
011: IRQ5 input (INTC)
100: POE3 input (POE2)
101: RXD0 output (SCI)
110: Setting prohibited
111: Setting prohibited
⎯
7 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
• Port B Control Register L1 (PBCRL1)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
6
5
4
0
R/W
0
R/W
3
2
-
PB1MD[2:0]
0*
R/W
0
R
1
0
PB0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15 to 7
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 1166 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PB1MD[2:0]
000*
R/W
PB1 Mode
Select the function of the
PB1/A17/REFOUT/IRQ4/ADTRG pin.
000: PB1 I/O (port)
001: A17 output (BSC)
010: REFOUT output (BSC)
011: IRQ4 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: ADTRG input (ADC)
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PB0MD[2:0]
000*
R/W
PB0 Mode
Select the function of the PB0/A16/IRQ3 pin.
000: PB0 I/O (port)
001: A16 input (BSC)
010: Setting prohibited
011: IRQ3 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
(2)
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
SH7285
• Port B Control Register H1 (PBCRH1)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1167 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port B Control Register L4 (PBCRL4)
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
2
1
0
PB12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15 to 3
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2 to 0
PB12MD[2:0] 000*
R/W
PB12 Mode
Select the function of the
PB12/CS1/CS7/IRQ1/TXD2/CS3 pin.
000: PB12 I/O (port)
001: CKE output (BSC)
010: CKE output (BSC)
011: IRQ1 input (INTC)
100: Setting prohibited
101: TXD2 output (SCI)
110: Setting prohibited
111: CS3 output (BSC)
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1168 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port B Control Register L3 (PBCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PB11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PB10MD[2:0]
0
R/W
0
R/W
0
R/W
7
6
-
0
R
5
4
0
R/W
0
R/W
3
2
-
PB9MD[2:0]
0
R/W
0
R
1
0
PB8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PB11MD[2:0]
000*
R/W
PB11 Mode
Select the function of the
PB11/CS0/CS6/IRQ0/RXD2/CS2 pin.
000: PB11 I/O (port)
001: CS0 output (BSC)
010: CS6 output (BSC)
011: IRQ0 input (INTC)
100: Setting prohibited
101: RXD2 input (SCI)
110: Setting prohibited
111: CS2 output (BSC
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PB10MD[2:0]
000
R/W
PB10 Mode
Select the function of the PB10 pin.
000: PB10 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1169 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PB9MD[2:0]
000
R/W
PB9 Mode
Select the function of the PB9/USPND pin.
000: PB9 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: USPND output (USB)
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PB8MD[2:0]
000*
R/W
PB8 Mode
Select the function of the
PB8/A20/WAIT/IRQ7/POE8/SCK0 pin.
000: PB8 I/O (port)
001: A20 output (BSC)
010: WAIT input (BSC)
011: IRQ7 input (INTC)
100: POE8 input (POE2)
101: SCK0 I/O (SCI)
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1170 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port B Control Register L2 (PBCRL2)
Bit:
15
14
-
Initial value:
R/W:
0
R
13
12
PB7MD[2:0]
0
R/W
0
R/W
11
10
-
0*
R/W
0
R
0
R/W
7
6
5
4
3
2
1
PB6MD[2:0]
9
8
-
-
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0*
R/W
0
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PB7MD[2:0]
000*
R/W
PB7 Mode
Select the function of the
PB7/A19/BREQ/IRQ6/POE4/TXD0 pin.
000: PB7 I/O (port)
001: A19 output (BSC)
010: BREQ input (BSC)
011: IRQ6 input (INTC)
100: POE4 input (POE2)
101: TXD0 I/O (SCI)
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1171 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PB6MD[2:0]
000*
R/W
PB6 Mode
Select the function of the
PB6/A18/BACK/IRQ5/POE3/RXD0 pin.
000: PB6 I/O (port)
001: A18 output (BSC)
010: BACK input (BSC)
011: IRQ5 input (INTC)
100: POE3 I/O (POE2)
101: RXD0 input (SCI)
110: Setting prohibited
111: Setting prohibited
⎯
7 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
• Port B Control Register L1 (PBCRL1)
Bit:
15
14
-
Initial value:
R/W:
0
R
13
12
11
PB3MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
10
9
8
0
R/W
0
R/W
7
6
-
PB2MD[2:0]
0
R/W
0
R
5
4
3
0
R/W
0
R/W
2
-
PB1MD[2:0]
0*
R/W
0
R
1
0
PB0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1172 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PB3MD[2:0]
000
R/W
PB3 Mode
Select the function of the PB3/IRQ1/POE2/SDA pin.
000: PB3 input (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ1 input (INTC)
100: POE2 input (POE2)
101: SDA I/O (IIC3)
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PB2MD[2:0]
000
R/W
PB2 Mode
Select the function of the PB2/IRQ0/POE1/SCL pin.
000: PB2 input (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ0 input (INTC)
100: POE1 input (POE2)
101: SCL I/O (IIC3)
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1173 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PB1MD[2:0]
000*
R/W
PB1 Mode
Select the function of the
PB1/A17/REFOUT/IRQ4/ADTRG pin.
000: PB1 I/O (port)
001: A17 output (BSC)
010: REFOUT output (BSC)
011: IRQ4 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: ADTRG input (ADC)
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PB0MD[2:0]
000*
R/W
PB0 Mode
Select the function of the PB0/A16/IRQ3 pin.
000: PB0 I/O (port)
001: A16 output (BSC)
010: Setting prohibited
011: IRQ3 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1174 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 23 Pin Function Controller (PFC)
SH7286
• Port B Control Register H1 (PBCRH1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PB19MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PB18MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PB17MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PB16MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PB19MD[2:0]
000*
R/W
PB19 Mode
Select the function of the PB19/A25/RASU/DREQ2
pin.
000: PB19 I/O (port)
001: A25 output (BSC)
010: RASU output (BSC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: DREQ2 input (DMAC)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1175 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PB18MD[2:0]
000*
R/W
PB18 Mode
Select the function of the PB18/A24/RASL/DACK2
pin.
000: PB18 I/O (port)
001: A24 output (BSC)
010: RASL output (BSC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: DACK2 input (DMAC)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PB17MD[2:0]
000*
R/W
PB17 Mode
Select the function of the PB17/A23/CASU/DREQ3
pin.
000: PB17 I/O (port)
001: A23 output (BSC)
010: CASU output (BSC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: DREQ3 input (DMAC)
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1176 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PB16MD[2:0]
000*
R/W
PB16 Mode
Select the function of the PB16/A22/CASL/DACK3
pin.
000: PB16 I/O (port)
001: A22 output (BSC)
010: CASL output (BSC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: DACK3 input (DMAC)
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
• Port B Control Register L4 (PBCRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PB15MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PB14MD[2:0]
0
R/W
0
R/W
0
R/W
7
-
0
R
6
5
4
PB13MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PB12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1177 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PB15MD[2:0]
000*
R/W
PB15 Mode
Select the function of the PB15/A21/CKE pin.
000: PB15 I/O (port)
001: A21 output (BSC)
010: CKE output (BSC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PB14MD[2:0]
000
R/W
PB14 Mode
Select the function of the PB14/CRx0 pin.
000: PB14 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: CRx0 input (RCAN)
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1178 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PB13MD[2:0]
000
R/W
PB13 Mode
Select the function of the PB13/CTx0 pin.
000: PB13 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: CTx0 output (RCAN)
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PB12MD[2:0]
000*
R/W
PB12 Mode
Select the function of the
PB12/CS1/CS7/IRQ1/TXD2/CS3 pin.
000: PB12 I/O (port)
001: CS1 output (BSC)
010: CS7 output (BSC)
011: IRQ1 input (INTC)
100: Setting prohibited
101: TXD2 output (SCI)
110: Setting prohibited
111: CS3 output (BSC)
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1179 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port B Control Register L3 (PBCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PB11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PB10MD[2:0]
0
R/W
0
R/W
0
R/W
7
6
-
0
R
5
4
0
R/W
0
R/W
3
2
-
PB9MD[2:0]
0
R/W
0
R
1
0
PB8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PB11MD[2:0]
000*
R/W
PB11 Mode
Select the function of the
PB11/CS0/CS6/IRQ0/RXD2/CS2 pin.
000: PB11 I/O (port)
001: CS0 output (BSC)
010: CS6 output (BSC)
011: IRQ0 input (INTC)
100: Setting prohibited
101: RXD2 input (SCI)
110: Setting prohibited
111: CS2 output (BSC)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1180 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PB10MD[2:0]
000
R/W
PB10 Mode
Select the function of the PB10 pin.
000: PB10 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PB9MD[2:0]
000
R/W
PB9 Mode
Select the function of the PB9/USPND pin.
000: PB9 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: USPND output (USB)
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1181 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PB8MD[2:0]
000*
R/W
PB8 Mode
Select the function of the
PB8/A20/WAIT/IRQ7/POE8/SCK0 pin.
000: PB8 I/O (port)
001: A20 output (BSC)
010: WAIT input (BSC)
011: IRQ7 input (INTC)
100: POE8 input (POE2)
101: SCK0 I/O (SCI)
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
• Port B Control Register L2 (PBCRL2)
Bit:
15
14
-
Initial value:
R/W:
0
R
13
12
PB7MD[2:0]
0
R/W
0
R/W
11
10
-
0*
R/W
0
R
7
6
5
4
3
2
1
PB6MD[2:0]
9
-
-
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
8
0*
R/W
0
Note: The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1182 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PB7MD[2:0]
000*
R/W
PB7 Mode
Select the function of the
PB7/A19/BREQ/IRQ6/POE4/TXD0 pin.
000: PB7 I/O (port)
001: A19 output (BSC)
010: BREQ input (BSC)
011: IRQ6 input (INTC)
100: POE4 input (POE2)
101: TXD0 output (SCI)
110: Setting prohibited
111: Setting prohibited
⎯
11
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PB6MD[2:0]
000*
R/W
PB6 Mode
Select the function of the
PB6/A18/BACK/IRQ5/POE3/RXD0 pin.
000: PB6 I/O (port)
001: A18 output (BSC)
010: BACK output (BSC)
011: IRQ5 input (INTC)
100: POE3 input (POE2)
101: RXD0 input (SCI)
110: Setting prohibited
111: Setting prohibited
⎯
7 to 0
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1183 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port B Control Register L1 (PBCRL1)
Bit:
15
14
-
Initial value:
R/W:
0
R
13
12
PB3MD[2:0]
0
R/W
0
R/W
11
10
-
0
R/W
0
R
0
R/W
9
8
7
PB2MD[2:0]
-
0
R/W
0
R
0
R/W
6
5
4
3
0
R/W
0
R/W
2
-
PB1MD[2:0]
0*
R/W
0
R
1
0
PB0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PB3MD[2:0]
000
R/W
PB3 Mode
Select the function of the PB3/IRQ1/POE2/SDA pin.
000: PB3 input (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ1 input (INTC)
100: POE2 input (POE2)
101: SDA I/O (IIC3)
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PB2MD[2:0]
000
R/W
PB2 Mode
Select the function of the PB2/IRQ0/POE1/SCL pin.
000: PB2 input (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ0 input (INTC)
100: POE1 input (POE2)
101: SCL I/O (IIC3)
110: Setting prohibited
111: Setting prohibited
Page 1184 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PB1MD[2:0]
000*
R/W
PB1 Mode
Select the function of the
PB1/A17/REFOUT/IRQ4/ADTRG pin.
000: PB1 I/O (port)
001: A17 output (BSC)
010: REFOUT output (BSC)
011: IRQ4 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: ADTRG input (ADC)
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PB0MD[2:0]
000*
R/W
PB0 Mode
Select the function of the PB0/A16/IRQ3 pin.
000: PB0 I/O (port)
001: A16 output (BSC)
010: Setting prohibited
011: IRQ3 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1185 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.6
Port B Pull-Up MOS Control Register H and L (PBPCRH and PBPCRL)
PBPCRH and PBPCRL control on/off of the input pull-up MOS of port B in bits.
(1)
SH7243
• Port B Pull-Up MOS Control Register H (PBPCRH)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port B Pull-Up MOS Control Register L (PBPCRL)
Bit:
Initial value:
R/W:
Bit
15
14
13
-
-
-
0
R
0
R
0
R
Bit Name
15 to 13 ⎯
12
11
PB12 PB11
PCR PCR
0
0
R/W R/W
10
9
-
-
0
R
0
R
8
PB8
PCR
0
R/W
7
PB7
PCR
0
R/W
Initial
Value
R/W
Description
All 0
R
Reserved
6
PB6
PCR
0
R/W
5
4
3
2
-
-
-
-
0
R
0
R
0
R
0
R
1
PB1
PCR
0
R/W
0
PB0
PCR
0
R/W
These bits are always read as 0. The write value
should always be 0.
12
PB12PCR
0
R/W
11
PB11PCR
0
R/W
10, 9
⎯
All 0
R
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
8
PB8PCR
0
R/W
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
Page 1186 of 1778
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
(2)
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
SH7285
• Port B Pull-Up MOS Control Register H (PBPCRH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
15 to 0
⎯
All 0
R
Bit:
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port B Pull-UP MOS Control Register L (PBPCRL)
Bit:
Initial value:
R/W:
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
PB12
PCR
PB11
PCR
PB10
PCR
PB9
PCR
PB8
PCR
PB7
PCR
PB6
PCR
-
-
-
-
PB1
PCR
PB0
PCR
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Bit Name
15 to 13 ⎯
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1187 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
12
PB12PCR
0
R/W
11
PB11PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
10
PB10PCR
0
R/W
9
PB9PCR
0
R/W
8
PB8PCR
0
R/W
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
(3)
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
SH7286
• Port B Pull-Up MOS Control Register H (PBPCRH)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
15 to 4
⎯
All 0
R
3
2
1
0
PB19 PB18 PB17 PB16
PCR PCR PCR PCR
0
0
0
0
R/W R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
3
PB19PCR
0
R/W
2
PB18PCR
0
R/W
1
PB17PCR
0
R/W
0
PB16PCR
0
R/W
Page 1188 of 1778
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port B Pull-Up MOS Control Register L (PBPCRL)
Bit:
15
14
13
12
11
10
PB15 PB14 PB13 PB12 PB11 PB10
PCR PCR PCR PCR PCR PCR
0
0
0
0
0
Initial value: 0
R/W: R/W R/W R/W R/W R/W R/W
9
PB9
PCR
0
R/W
8
PB8
PCR
0
R/W
7
PB7
PCR
0
R/W
6
PB6
PCR
0
R/W
5
4
3
2
-
-
-
-
0
R
0
R
0
R
0
R
1
PB1
PCR
0
R/W
0
PB0
PCR
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PB15PCR
0
R/W
14
PB14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PB13PCR
0
R/W
12
PB12PCR
0
R/W
11
PB11PCR
0
R/W
10
PB10PCR
0
R/W
9
PB9PCR
0
R/W
8
PB8PCR
0
R/W
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
Page 1189 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.7
Port C I/O Register L (PCIORL)
PCIORL is a 16-bit readable/writable register that is used to set the pins on port C as inputs or
outputs. Bits PC15IOR to PC0IOR correspond to pins PC15 to PC0 respectively (multiplexed port
pin names except for the port names are abbreviated here). PCIORL is enabled when the port C
pins are functioning as general-purpose inputs/outputs (PC15 to PC0). In other states, PCIORL is
disabled. A given pin on port C will be an output pin if the corresponding bit in PCIORL is set to
1, and an input pin if the bit is cleared to 0.
The initial value of PCIORL is H'0000.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC15
IOR
PC14
IOR
PC13
IOR
PC12
IOR
PC11
IOR
PC10
IOR
PC9
IOR
PC8
IOR
PC7
IOR
PC6
IOR
PC5
IOR
PC4
IOR
PC3
IOR
PC2
IOR
PC1
IOR
PC0
IOR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit:
23.1.8
Port C Control Register L1 to L4 (PCCRL1 to PCCRL4)
PCCRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port C.
(1)
SH7243
• Port C Control Register L4 (PCCRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC15MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PC14MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PC13MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PC12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1190 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PC15MD[2:0]
000*
R/W
PC15 Mode
Select the function of the PC15/A15/IRQ2 pin.
000: PC15 I/O (port)
001: A15 output (BSC)
010: Setting prohibited
011: IRQ2 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC14MD[2:0]
000*
R/W
PC14 Mode
Select the function of the PC14/A14/IRQ1 pin.
000: PC14 I/O (port)
001: A14 output (BSC)
010: Setting prohibited
011: IRQ1 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1191 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PC13MD[2:0]
000*
R/W
PC13 Mode
Select the function of the PC13/A13/IRQ0 pin.
000: PC13 I/O (port)
001: A13 output (BSC)
010: Setting prohibited
011: IRQ0 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC12MD[2:0]
000*
R/W
PC12 Mode
Select the function of the PC12/A12 pin.
000: PC12 I/O (port)
001: A12 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1192 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port C Control Register L3 (PCCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PC10MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PC9MD[2:0]
0
R/W
0
R/W
0*
R/W
3
2
-
0
R
1
0
PC8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PC11MD[2:0]
000*
R/W
PC11 Mode
Select the function of the PC11/A11 pin.
000: PC11 I/O (port)
001: A11 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC10MD[2:0]
000*
R/W
PC10 Mode
Select the function of the PC10/A10 pin.
000: PC10 I/O (port)
001: A10 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1193 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PC9MD[2:0]
000*
R/W
PC9 Mode
Select the function of the PC9/A9 pin.
000: PC9 I/O (port)
001: A9 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC8MD[2:0]
000*
R/W
PC8 Mode
Select the function of the PC8/A8 pin.
000: PC8 I/O (port)
001: A8 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1194 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port C Control Register L2 (PCCRL2)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC7MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
0
R/W
9
8
7
PC6MD[2:0]
-
0
R/W
0
R
0*
R/W
6
5
4
3
PC5MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PC4MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PC7MD[2:0]
000*
R/W
PC7 Mode
Select the function of the PC7/A7 pin.
000: PC7 I/O (port)
001: A7 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC6MD[2:0]
000*
R/W
PC6 Mode
Select the function of the PB2/A6 pin.
000: PC6 I/O (port)
001: A6 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1195 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PC5MD[2:0]
000*
R/W
PC5 Mode
Select the function of the PC5/A5 pin.
000: PC5 I/O (port)
001: A5 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC4MD[2:0]
000*
R/W
PC4 Mode
Select the function of the PC4/A4/TRST pin. When
using E10A (ASEMD0 = L), these pins are fixed to
TRST input.
000: PC4 I/O (port)
001: A4 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1196 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port C Control Register L1 (PCCRL1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC3MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
0
R/W
9
8
7
PC2MD[2:0]
-
0
R/W
0
R
0*
R/W
6
5
4
PC1MD[2:0]
0
R/W
0
R/W
0*
R/W
3
2
-
0
R
1
0
PC0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PC3MD[2:0]
000*
R/W
PC3 Mode
Select the function of the PC3/A3/TMS pin. When
using E10A (ASEMD0 = L), these pins are fixed to
TMS input.
000: PC3 I/O (port)
001: A3 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1197 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PC2MD[2:0]
000*
R/W
PC2 Mode
Select the function of the PC2/A2/TCK pin. When
using E10A (ASEMD0 = L), these pins are fixed to
TCK input.
000: PC2 I/O (port)
001: A2 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PC1MD[2:0]
000*
R/W
PC1 Mode
Select the function of the PC1/A1/TDO pin. When
using E10A (ASEMD0 = L), these pins are fixed to
TDO output.
000: PC1 I/O (port)
001: A1 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1198 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PC0MD[2:0]
000*
R/W
PC0 Mode
Select the function of the PC0/A0/POE0/TDI pin.
When using E10A (ASEMD0 = L), these pins are
fixed to TDI input.
000: PC0 I/O (port)
001: A0 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: POE0 input (POE2)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
(2)
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
SH7285/SH7286
• Port C Control Register L4 (PCCRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC15MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PC14MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PC13MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PC12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1199 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PC15MD[2:0]
000*
R/W
PC15 Mode
Select the function of the PC15/A15/IRQ2 pin.
000: PC15 I/O (port)
001: A15 output (BSC)
010: Setting prohibited
011: IRQ2 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC14MD[2:0]
000*
R/W
PC14 Mode
Select the function of the PC14/A14/IRQ1 pin.
000: PC14 I/O (port)
001: A14 output (BSC)
010: Setting prohibited
011: IRQ1 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1200 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PC13MD[2:0]
000*
R/W
PC13 Mode
Select the function of the PC13/A13/IRQ0 pin.
000: PC13 I/O (port)
001: A13 output (BSC)
010: Setting prohibited
011: IRQ0 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC12MD[2:0]
000*
R/W
PC12 Mode
Select the function of the PC12/A12 pin.
000: PC12 I/O (port)
001: A12 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1201 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port C Control Register L3 (PCCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PC10MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
3
0
R/W
0
R/W
2
-
PC9MD[2:0]
0*
R/W
0
R
1
0
PC8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PC11MD[2:0]
000*
R/W
PC11 Mode
Select the function of the PC11/A11pin.
000: PC11 I/O (port)
001: A11 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC10MD[2:0]
000*
R/W
PC10 Mode
Select the function of the PC10/A10 pin.
000: PC10 I/O (port)
001: A10 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Page 1202 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PC9MD[2:0]
000*
R/W
PC9 Mode
Select the function of the PC9/A9 pin.
000: PC9 I/O (port)
001: A9 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC8MD[2:0]
000*
R/W
PC8 Mode
Select the function of the PC8/A8 pin.
000: PC8 I/O (port)
001: A8 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1203 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port C Control Register L2 (PCCRL2)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC7MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
0
R/W
9
8
7
PC6MD[2:0]
-
0
R/W
0
R
0*
R/W
6
5
4
3
PC5MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PC4MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PC7MD[2:0]
000*
R/W
PC7 Mode
Select the function of the PC7/A7 pin.
000: PC7 I/O (port)
001: A7 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC6MD[2:0]
000*
R/W
PC6 Mode
Select the function of the PC6/A6 pin.
000: PC6 I/O (port)
001: A6 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Page 1204 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PC5MD[2:0]
000*
R/W
PC5 Mode
Select the function of the PC5/A5 pin.
000: PC5 I/O (port)
001: A5 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC4MD[2:0]
000*
R/W
PC4 Mode
Select the function of the PC4/A4 pin.
000: PC4 I/O (port)
001: A4 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1205 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port C Control Register L1 (PCCRL1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PC3MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
0
R/W
9
8
7
PC2MD[2:0]
-
0
R/W
0
R
0*
R/W
6
5
4
PC1MD[2:0]
0
R/W
0
R/W
0*
R/W
3
2
-
0
R
1
0
PC0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PC3MD[2:0]
000*
R/W
PC3 Mode
Select the function of the PC3/A3 pin.
000: PC3 I/O (port)
001: A3 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PC2MD[2:0]
000*
R/W
PC2 Mode
Select the function of the PC2/A2 pin.
000: PC2 I/O (port)
001: A2 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Page 1206 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PC1MD[2:0]
000*
R/W
PC1 Mode
Select the function of the PC1/A1 pin.
000: PC1 I/O (port)
001: A1 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PC0MD[2:0]
000*
R/W
PC0 Mode
Select the function of the PC0/A0/POE0 pin.
000: PC0 I/O (port)
001: A0 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: POE0 input (POE2)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1207 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.9
Port C Pull-Up MOS Control Register L (PCPCRL)
PCPCRL controls on/off of the input pull-up MOS of port C in bits.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC15
PCR
PC14
PCR
PC13
PCR
PC12
PCR
PC11
PCR
PC10
PCR
PC9
PCR
PC8
PCR
PC7
PCR
PC6
PCR
PC5
PCR
PC4
PCR
PC3
PCR
PC2
PCR
PC1
PCR
PC0
PCR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PC15PCR
0
R/W
14
PC14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PC13PCR
0
R/W
12
PC12PCR
0
R/W
11
PC11PCR
0
R/W
10
PC10PCR
0
R/W
9
PC9PCR
0
R/W
8
PC8PCR
0
R/W
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
5
PC5PCR
0
R/W
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
Page 1208 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.10 Port D I/O Registers H and L (PDIORH and PDIORL)
PDIORH and PDIORL are 16-bit readable/writable registers that are used to set the pins on port D
as inputs or outputs. Bits PD31IOR to PD0IOR correspond to pins PD31 to PD0 respectively
(multiplexed port pin names except for the port names are abbreviated here). PDIORH and
PDIORL are enabled when the port D pins are functioning as general-purpose inputs/outputs
(PD15 to PD0 for PDIORL and PD31 to PD16 for PDIORH) and TIOC input/output in MTU2S.
In other states, they are disabled. A given pin on port D will be an output pin if the corresponding
bit in PDIORL and PDIORH is set to 1, and an input pin if the bit is cleared to 0. However, bits 16
to 0 of PDIORH in SH7243 and bits 7 of PDIORLH in SH7285 are disabled. The initial values of
PDIORL and PDIORH are H'0000.
• Port D I/O Register H (PDIORH)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD31
IOR
PD30
IOR
PD29
IOR
PD28
IOR
PD27
IOR
PD26
IOR
PD25
IOR
PD24
IOR
PD23
IOR
PD22
IOR
PD21
IOR
PD20
IOR
PD19
IOR
PD18
IOR
PD17
IOR
PD16
IOR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
• Port D I/O Register L (PDIORL)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
IOR
PD14
IOR
PD13
IOR
PD12
IOR
PD11
IOR
PD10
IOR
PD9
IOR
PD8
IOR
PD7
IOR
PD6
IOR
PD5
IOR
PD4
IOR
PD3
IOR
PD2
IOR
PD1
IOR
PD0
IOR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
23.1.11 Port D Control Registers H1 to H4 and L1 to L4 (PDCRH1 to PDCRH4 and
PDCRL1 to PDCRL4)
PDCRH1 to PDCRH4 and PDCRL1 to PDCRL4 are 16-bit readable/writable registers that are
used to select the functions of the multiplexed pins on port D.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1209 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
(1)
SH7243
• Port D Control Register H4 (PDCRH4)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port D Control Register H3 (PDCRH3)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port D Control Register H2 (PDCRH2)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Page 1210 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register H1 (PDCRH1)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port D Control Register L4 (PDCRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD15MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD14MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PD13MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PD12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 16-bit external extention mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD15MD[2:0]
000*
R/W
PD15 Mode
Select the function of the PD15/D15/TIOC4DS pin.
000: PD15 I/O (port)
001: D15 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1211 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD14MD[2:0]
000*
R/W
PD14 Mode
Select the function of the PD14/D14/TIOC4CS pin.
000: PD14 I/O (port)
001: D14 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD13MD[2:0]
000*
R/W
PD13 Mode
Select the function of the PD13/D13/TIOC4BS pin.
000: PD13 I/O (port)
001: D13 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1212 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PD12MD[2:0]
000*
R/W
PD12 Mode
Select the function of the PD12/D12/TIOC4AS pin.
000: PD12 I/O (port)
001: D12 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
• Port D Control Register L3 (PDCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD10MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD9MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD11MD[2:0]
000*
R/W
PD11 Mode
Select the function of the PD11/D11/TIOC3DS pin.
000: PD11 I/O (port)
001: D11 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1213 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD10MD[2:0]
000*
R/W
PD10 Mode
Select the function of the PD10/D10/TIOC3BS pin.
000: PD10 I/O (port)
001: D10 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD9MD[2:0]
000*
R/W
PD9 Mode
Select the function of the PD9/D9/TIOC3CS pin.
000: PD9 I/O (port)
001: D9 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1214 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PD8MD[2:0]
000*
R/W
PD8 Mode
Select the function of the PD8/D8/TIOC3AS/AUDCK
pin.
000: PD8 I/O (port)
001: D8 output (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: AUDCK output (AUD)
Note:
*
The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
• Port D Control Register L2 (PDCRL2)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
0
R/W
0
R/W
11
10
-
PD7MD[2:0]
0*
R/W
0
R
9
8
PD6MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
0
R/W
5
4
3
PD5MD[2:0]
-
0
R/W
0
R
0*
R/W
2
1
0
PD4MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1215 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PD7MD[2:0]
000*
R/W
PD7 Mode
Select the function of the
PD7/D7/TIC5WS/AUDATA3 pin.
000: PD7 I/O (port)
001: D7 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5WS input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: AUDATA3 output (AUD)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD6MD[2:0]
000*
R/W
PD6 Mode
Select the function of the
PD6/D6/TIC5VS/AUDATA2 pin.
000: PD6 I/O (port)
001: D6 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5VS input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: AUDATA2 output (AUD)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1216 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PD5MD[2:0]
000*
R/W
PD5 Mode
Select the function of the
PD5/D5/TIC5US/AUDATA1 pin.
000: PD5 I/O (port)
001: D5 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5US input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: AUDATA1 output (AUD)
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD4MD[2:0]
000*
R/W
PD4 Mode
Select the function of the PD4/D4/TIC5W/AUDATA0
pin.
000: PD4 I/O (port)
001: D4 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5W input (MTU2)
111: AUDATA0 output (AUD)
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1217 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L1 (PDCRL1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
0
R/W
0
R/W
11
10
-
PD3MD[2:0]
0*
R/W
0
R
9
8
PD2MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD1MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD3MD[2:0]
000*
R/W
PD3 Mode
Select the function of the PD3/D3/TIC5V/AUDSYNC
pin.
000: PD3 I/O (port)
001: D3 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5V input (MTU2)
111: AUDSYNC output (AUD)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1218 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PD2MD[2:0]
000*
R/W
PD2 Mode
Select the function of the PD2/D2/TIC5U pin.
000: PD2 I/O (port)
001: D2 I/O (CPG)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5U input (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD1MD[2:0]
000*
R/W
PD1 Mode
Select the function of the PD1/D1 pin.
000: PD1 I/O (port)
001: D1 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1219 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PD0MD[2:0]
000*
R/W
PD0 Mode
Select the function of the PD0/D0 pin.
000: PD0 I/O (port)
001: D0 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
(2)
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
SH7285
• Port D Control Register H4 (PDCRH4)
Bit:
15
-
14
13
12
PD31MD[2:0]
11
10
-
9
8
PD30MD[2:0]
7
-
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
6
5
4
PD29MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PD28MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
Page 1220 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PD31MD[2:0]
000
R/W
PD31 Mode
Select the function of the PD31/TIOC3AS/ADTRG
pin.
000: PD31 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: ADTRG input (ADC)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD30MD[2:0]
000
R/W
PD30 Mode
Select the function of the
PD30/IRQOUT/REFOUT/TIOC3CS pin.
000: PD30 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: IRQOUT output (INTC)/REFOUT output (BSC)*
100: TIOC3CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1221 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PD29MD[2:0]
000
R/W
PD29 Mode
Select the function of the PD29/TIOC3BS pin.
000: PD29 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD28MD[2:0]
000
R/W
PD28 Mode
Select the function of the PD28/TIOC3DS pin.
000: PD28 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
IRQOUT (INTC) or REFOUT (BSC) is selected by the IRQOUT function control register
(IFCR).
Page 1222 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register H3 (PDCRH3)
Bit:
15
-
14
13
12
PD27MD[2:0]
0
R/W
0
R/W
0
R/W
11
10
-
0
R
9
8
PD26MD[2:0]
0
R/W
0
R/W
0
R/W
7
-
Initial value:
R/W:
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
6
5
4
PD25MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PD24MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD27MD[2:0]
000
R/W
PD27 Mode
Select the function of the PD27/DACK0/TIOC4AS
pin.
000: PD27 I/O (port)
001: Setting prohibited
010: DACK0 output (DMAC)
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD26MD[2:0]
000
R/W
PD26 Mode
Select the function of the PD26/DACK1/TIOC4BS
pin.
000: PD26 I/O (port)
001: Setting prohibited
010: DACK1 output (DMAC)
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1223 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD25MD[2:0]
000
R/W
PD25 Mode
Select the function of the PD25/DREQ1/TIOC4CS
pin.
000: PD25 I/O (port)
001: Setting prohibited
010: DREQ1 input (DMAC)
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD24MD[2:0]
000
R/W
PD24 Mode
Select the function of the
PD24/DREQ0/TIOC4DS/AUDCK pin.
000: PD24 I/O (port)
001: Setting prohibited
010: DREQ0 input (DMAC)
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: AUDCK output (AUD)
Page 1224 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register H2 (PDCRH2)
Bit:
15
14
13
12
11
-
-
-
-
-
10
9
8
Initial value:
R/W:
0
R
0
R/W
0
R/W
0
R/W
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 11
⎯
All 0
R
Reserved
PD22MD[2:0]
0
R/W
0
R/W
0
R/W
7
-
0
R
6
5
4
PD21MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PD20MD[2:0]
0
R/W
0
R/W
0
R/W
These bits are always read as 0. The write value
should always be 0.
10 to 8
PD22MD[2:0]
000
R/W
PD22 Mode
Select the function of the
PD22/IRQ6/TIC5US/RXD4/AUDSYNC pin.
000: PD22 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ6 input (INTC)
100: TIC5US input (MTU2S)
101: RXD4 input (SCI)
110: Setting prohibited
111: AUDSYNC output (AUD)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD21MD[2:0]
000
R/W
PD21 Mode
Select the function of the PD21/IRQ5/TIC5VS/TXD4
pin.
000: PD21 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ5 input (INTC)
100: TIC5VS input (MTU2S)
101: TXD4 output (SCI)
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1225 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD20MD[2:0]
000
R/W
PD20 Mode
Select the function of the
PD20/IRQ4/TIC5WS/SCK4/POE8 pin.
000: PD20 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: IRQ4 input (INTC)
100: TIC5WS input (MTU2S)
101: SCK4 I/O (SCI)
110: POE8 input (POE2)
111: Setting prohibited
• Port D Control Register H1 (PDCRH1)
Bit:
15
-
14
13
12
PD19MD[2:0]
0
R/W
0
R/W
0
R/W
11
10
-
0
R
9
8
PD18MD[2:0]
0
R/W
0
R/W
0
R/W
7
-
Initial value:
R/W:
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
6
5
4
PD17MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PD16MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
Page 1226 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
14 to 12
PD19MD[2:0] 000
R/W
Description
R/W
PD19 Mode
Select the function of the
PD19/CS0/IRQ3/POE7/RXD3/AUDATA3 pin.
000: PD19 I/O (port)
001: Setting prohibited
010: CS0 output (BSC)
011: IRQ3 input (INTC)
100: POE7 input (POE2)
101: RXD3 input (SCIF)
110: Setting prohibited
111: AUDATA3 output (AUD)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD18MD[2:0] 000
R/W
PD18 Mode
Select the function of the
PD18/CS1/IRQ2/POE6/TXD3/AUDATA2 pin.
000: PD18 I/O (port)
001: Setting prohibited
010: CS1 output (BSC)
011: IRQ2 input (INTC)
100: POE6 input (POE2)
101: TXD3 output (SCIF)
110: Setting prohibited
111: AUDATA2 output (AUD)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1227 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Initial
Value
Bit
Bit Name
6 to 4
PD17MD[2:0] 000
R/W
Description
R/W
PD17 Mode
Select the function of the
PD17/CS2/IRQ1/POE5/SCK3/AUDATA1 pin.
000: PD17 I/O (port)
001: Setting prohibited
010: CS2 output (BSC)
011: IRQ1 input (INTC)
100: POE5 input (POE2)
101: SCK3 I/O (SCIF)
110: Setting prohibited
111: AUDATA1 output (AUD)
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD16MD[2:0] 000
R/W
PD16 Mode
Select the function of the
PD16/CS3/IRQ0/AUDATA0 pin.
000: PD16 I/O (port)
001: Setting prohibited
010: CS3 output (BSC)
011: IRQ0 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: AUDATA0 output (AUD)
Page 1228 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L4 (PDCRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD15MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD14MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PD13MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PD12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD15MD[2:0]
000*
R/W
PD15 Mode
Select the function of the PD15/D15/TIOC4DS pin.
000: PD15 I/O (port)
001: D15 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD14MD[2:0]
000*
R/W
PD14 Mode
Select the function of the PD14/D14/TIOC4CS pin.
000: PD14 I/O (port)
001: D14 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1229 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD13MD[2:0]
000*
R/W
PD13 Mode
Select the function of the PD13/D13/TIOC4BS pin.
000: PD13 I/O (port)
001: D13 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD12MD[2:0]
000*
R/W
PD12 Mode
Select the function of the PD12/D12/TIOC4AS pin.
000: PD12 I/O (port)
001: D12 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
Page 1230 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L3 (PDCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD10MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD9MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD11MD[2:0]
000*
R/W
PD11 Mode
Select the function of the PD11/D11/TIOC3DS pin.
000: PD11 I/O (port)
001: D11 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD10MD[2:0]
000*
R/W
PD10 Mode
Select the function of the PD10/D10/TIOC3BS pin.
000: PD10 I/O (port)
001: D10 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1231 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD9MD[2:0]
000*
R/W
PD9 Mode
Select the function of the PD9/D9/TIOC3CS pin.
000: PD9 I/O (port)
001: D9 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD8MD[2:0]
000*
R/W
PD8 Mode
Select the function of the PD8/D8/TIOC3AS pin.
000: PD8 I/O (port)
001: D8 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled 16-bit external extension mode.
Page 1232 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L2 (PDCRL2)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
0
R/W
0
R/W
11
10
-
PD7MD[2:0]
0*
R/W
0
R
9
8
7
0
R/W
0
R/W
0*
R/W
6
-
PD6MD[2:0]
0
R
5
4
3
PD5MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD4MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD7MD[2:0]
000*
R/W
PD7 Mode
Select the function of the PD7/D7/TIC5WS pin.
000: PD7 I/O (port)
001: D7 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5WS input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD6MD[2:0]
000*
R/W
PD6 Mode
Select the function of the PD6/D6/TIC5VS pin.
000: PD6 I/O (port)
001: D6 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5VS input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1233 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD5MD[2:0]
000*
R/W
PD5 Mode
Select the function of the PD5/D5/TIC5US pin.
000: PD5 I/O (port)
001: D5 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5US input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD4MD[2:0]
000*
R/W
PD4 Mode
Select the function of the PD4/D4/TIC5W pin.
000: PD4 I/O (port)
001: D4 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5W input (MTU2)
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1234 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L1 (PDCRL1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
0
R/W
0
R/W
11
10
-
PD3MD[2:0]
0*
R/W
0
R
9
8
PD2MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD1MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD3MD[2:0]
000*
R/W
PD3 Mode
Select the function of the PD3/D3/TIC5V pin.
000: PD3 I/O (port)
001: D3 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5V input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD2MD[2:0]
000*
R/W
PD2 Mode
Select the function of the PD2/D2/TIC5U pin.
000: PD2 I/O (port)
001: D2 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5U input (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1235 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD1MD[2:0]
000*
R/W
PD1 Mode
Select the function of the PD1/D1 pin.
000: PD1 I/O (port)
001: D1 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD0MD[2:0]
000*
R/W
PD0 Mode
Select the function of the PD0/D0 pin.
000: PD0 I/O (port)
001: D0 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1236 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 23 Pin Function Controller (PFC)
SH7286
• Port D Control Register H4 (PDCRH4)
Bit:
15
-
14
13
12
PD31MD[2:0]
0*2
R/W
11
10
-
9
8
PD30MD[2:0]
0*2
R/W
7
-
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R
6
5
4
PD29MD[2:0]
0
R/W
0
R/W
0*2
R/W
3
-
0
R
2
1
0
PD28MD[2:0]
0
R/W
0
R/W
0*2
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD31MD[2:0]
000*2
R/W
PD31 Mode
Select the function of the
PD31/D31/TIOC3AS/ADTRG pin.
000: PD31 I/O (port)
001: D31 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: ADTRG input (ADC)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1237 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
10 to 8
Bit Name
PD30MD[2:0]
Initial
Value
2
000*
R/W
Description
R/W
PD30 Mode
Select the function of the
PD30/D30/IRQOUT/REFOUT/TIOC3CS pin.
000: PD30 I/O (port)
001: D30 I/O (BSC)
010: Setting prohibited
011: IRQOUT output (INTC)/REFOUT output (BSC)*
1
100: TIOC3AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD29MD[2:0]
000*2
R/W
PD29 Mode
Select the function of the PD29/D29/TIOC3BS pin.
000: PD29 I/O (port)
001: D29 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1238 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
Initial
Value
Bit Name
2 to 0
Section 23 Pin Function Controller (PFC)
PD28MD[2:0]
2
000*
R/W
Description
R/W
PD28 Mode
Select the function of the PD28/D28/TIOC3DS pin.
000: PD28 I/O (port)
001: D28 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Notes: 1. IRQOUT (INTC) or REFOUT (BSC) is selected by the IRQOUT function control register
(IFCR).
2. The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
• Port D Control Register H3 (PDCRH3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD27MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD26MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PD25MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PD24MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1239 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PD27MD[2:0]
000*
R/W
PD27 Mode
Select the function of the
PD27/D27/DACK0/TIOC4AS pin.
000: PD27 I/O (port)
001: D27 I/O (BSC)
010: DACK0 output (DMAC)
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD26MD[2:0]
000*
R/W
PD26 Mode
Select the function of the
PD26/D26/DACK1/TIOC4BS pin.
000: PD26 I/O (port)
001: D26 I/O (BSC)
010: DACK1 output (DMAC)
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1240 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PD25MD[2:0]
000*
R/W
PD25 Mode
Select the function of the
PD25/D25/DREQ1/TIOC4CS pin.
000: PD25 I/O (port)
001: D25 I/O (BSC)
010: DREQ1 input (DMAC)
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD24MD[2:0]
000*
R/W
PD24 Mode
Select the function of the
PD24/D24/DREQ0/TIOC4DS/AUDCK pin.
000: PD24 I/O (port)
001: D24 I/O (BSC)
010: DREQ0 input (DMAC)
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: AUDCK output (AUD)
Note:
*
The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1241 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register H2 (PDCRH2)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD23MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD22MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
3
-
PD21MD[2:0]
0
R/W
0
R/W
0*
R/W
0
R
2
1
0
PD20MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD23MD[2:0]
000*
R/W
PD23 Mode
Select the function of the PD23/D23 pin.
000: PD23 I/O (port)
001: D23 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD22MD[2:0]
000*
R/W
PD22 Mode
Select the function of the
PD22/D22/IRQ6/TIC5US/RXD4/AUDSYNC pin.
000: PD22 I/O (port)
001: D22 I/O (BSC)
010: Setting prohibited
011: IRQ6 input (INTC)
100: TIC5US I/O (MTU2S)
101: RXD4 input (SCI)
110: Setting prohibited
111: AUDSYNC output (AUD)
Page 1242 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD21MD[2:0]
000*
R/W
PD21 Mode
Select the function of the
PD21/D21/IRQ5/TIC5VS/TXD4 pin.
000: PD21 I/O (port)
001: D21 I/O (BSC)
010: Setting prohibited
011: IRQ5 input (INTC)
100: TIC5VS input (MTU2S)
101: TXD4 output (SCI)
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD20MD[2:0]
000*
R/W
PD20 Mode
Select the function of the
PD20/D20/IRQ4/TIC5WS/SCK4/POE8 pin.
000: PD20 I/O (port)
001: D20 I/O (BSC)
010: Setting prohibited
011: IRQ4 input (INTC)
100: TIC5WS input (MTU2S)
101: SCK4 I/O (SCI)
110: POE8 input (POE2)
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1243 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register H1 (PDCRH1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD19MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD18MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
PD17MD[2:0]
0
R/W
0
R/W
0*
R/W
3
-
0
R
2
1
0
PD16MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD19MD[2:0]
000*
R/W
PD19 Mode
Select the function of the
PD19/D19/CS0/IRQ3/POE7/RXD3/AUDATA3 pin.
000: PD19 I/O (port)
001: D19 I/O (BSC)
010: CS0 output (BSC)
011: IRQ3 input (INTC)
100: POE7 input (POE2)
101: RXD3 input (SCIF)
110: Setting prohibited
111: AUDATA3 output (AUD)
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1244 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PD18MD[2:0]
000*
R/W
PD18 Mode
Select the function of the
PD18/D18/CS1/IRQ2/POE6/TXD3/AUDATA2pin.
000: PD18 I/O (port)
001: D18 I/O (BSC)
010: CS1 output (BSC)
011: IRQ2 input (INTC)
100: POE6 input (POE2)
101: TXD3 output (SCIF)
110: Setting prohibited
111: AUDATA2 output (AUD)
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD17MD[2:0]
000*
R/W
PD17 Mode
Select the function of the
PD17/D17/CS2/IRQ1/POE5/SCK3/AUDATA1 pin.
000: PD17 I/O (port)
001: D17 I/O (BSC)
010: CS2 output (BSC)
011: IRQ1 input (INTC)
100: POE5 input (POE2)
101: SCK3 I/O (SCIF)
110: Setting prohibited
111: AUDATA1 output (AUD)
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1245 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PD16MD[2:0]
000*
R/W
PD16 Mode
Select the function of the
PD16/D16/CS3/IRQ0/AUDATA0 pin.
000: PD16 I/O (port)
001: D16 I/O (BSC)
010: CS3 output (BSC)
011: IRQ0 input (INTC)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: AUDATA0 output (AUD)
Note:
*
The initial value is 1 during the on-chip ROM disabled 32-bit external extension mode.
• Port D Control Register L4 (PDCRL4)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD15MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD14MD[2:0]
0
R/W
0
R/W
0*
R/W
7
-
0
R
6
5
4
3
-
PD13MD[2:0]
0
R/W
0
R/W
0*
R/W
0
R
2
1
0
PD12MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1246 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PD15MD[2:0]
000*
R/W
PD15 Mode
Select the function of the PD15/D15/TIOC4DS pin.
000: PD15 I/O (port)
001: D15 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD14MD[2:0]
000*
R/W
PD14 Mode
Select the function of the PD14/D14/TIOC4CS pin.
000: PD14 I/O (port)
001: D14 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1247 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PD13MD[2:0]
000*
R/W
PD13 Mode
Select the function of the PD13/D13/TIOC4BS pin.
000: PD13 I/O (port)
001: D13 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD12MD[2:0]
000*
R/W
PD12 Mode
Select the function of the PD12/D12/TIOC4AS pin.
000: PD12 I/O (port)
001: D12 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1248 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L3 (PDCRL3)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
PD11MD[2:0]
0
R/W
0
R/W
0*
R/W
11
10
-
0
R
9
8
PD10MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD9MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD8MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD11MD[2:0]
000*
R/W
PD11 Mode
Select the function of the PD11/D11/TIOC3DS pin.
000: PD11 I/O (port)
001: D11 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD10MD[2:0]
000*
R/W
PD10 Mode
Select the function of the PD10/D10/TIOC3BS pin.
000: PD10 I/O (port)
001: D10 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1249 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD9MD[2:0]
000*
R/W
PD9 Mode
Select the function of the PD9/D9/TIOC3CS pin.
000: PD9 I/O (port)
001: D9 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3CS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD8MD[2:0]
000*
R/W
PD8 Mode
Select the function of the PD8/D8/TIOC3AS pin.
000: PD8 I/O (port)
001: D8 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIOC3AS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1250 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L2 (PDCRL2)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
0
R/W
0
R/W
11
10
-
PD7MD[2:0]
0*
R/W
0
R
9
8
PD6MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD5MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD4MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD7MD[2:0]
000*
R/W
PD7 Mode
Select the function of the PD7/D7/TIC5WS pin.
000: PD7 I/O (port)
001: D7 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5WS I/O (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD6MD[2:0]
000*
R/W
PD6 Mode
Select the function of the PD6/D6/TIC5VS pin.
000: PD6 I/O (port)
001: D6 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5VS input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1251 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD5MD[2:0]
000*
R/W
PD5 Mode
Select the function of the PD5/D5/TIC5US pin.
000: PD5 I/O (port)
001: D5 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: TIC5US input (MTU2S)
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD4MD[2:0]
000*
R/W
PD4 Mode
Select the function of the PD4/D4/TIC5W pin.
000: PD4 I/O (port)
001: D4 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5W input (MTU2S)
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1252 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Control Register L1 (PDCRL1)
Bit:
15
-
Initial value:
R/W:
0
R
14
13
12
0
R/W
0
R/W
11
10
-
PD3MD[2:0]
0*
R/W
0
R
9
8
PD2MD[2:0]
0
R/W
0
R/W
0*
R/W
7
6
-
0
R
5
4
3
PD1MD[2:0]
-
0
R/W
0
R
0
R/W
0*
R/W
2
1
0
PD0MD[2:0]
0
R/W
0
R/W
0*
R/W
Note: * The initial value is 1 during the on-chip ROM disabled external extension mode.
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PD3MD[2:0]
000*
R/W
PD3 Mode
Select the function of the PD3/D3/TIC5V pin.
000: PD3 I/O (port)
001: D3 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5V input (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PD2MD[2:0]
000*
R/W
PD2 Mode
Select the function of the PD2/D2/TIC5U pin.
000: PD2 I/O (port)
001: D2 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIC5U input (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1253 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PD1MD[2:0]
000*
R/W
PD1 Mode
Select the function of the PD1/D1 pin.
000: PD1 I/O (port)
001: D1 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PD0MD[2:0]
000*
R/W
PD0 Mode
Select the function of the PD0/D0 pin.
000: PD0 I/O (port)
001: D0 I/O (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
*
The initial value is 1 during the on-chip ROM disabled external extension mode.
Page 1254 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.12 Port D Pull-Up MOS Control Register H and L (PDPCRH and PDPCRL)
PDPCRH and PDPCRL control on/off of the input pull-up MOS of port D in bits.
(1)
SH7243
• Port D Pull-Up MOS Control Register H (PDPCRH)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
• Port D Pull-UP MOS Control Register L (PDPCRL)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PCR
PD14
PCR
PD13
PCR
PD12
PCR
PD11
PCR
PD10
PCR
PD9
PCR
PD8
PCR
PD7
PCR
PD6
PCR
PD5
PCR
PD4
PCR
PD3
PCR
PD2
PCR
PD1
PCR
PD0
PCR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD15PCR
0
R/W
14
PD14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PD13PCR
0
R/W
12
PD12PCR
0
R/W
11
PD11PCR
0
R/W
10
PD10PCR
0
R/W
9
PD9PCR
0
R/W
8
PD8PCR
0
R/W
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1255 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
(2)
SH7285
• Port D Pull-Up MOS Control Register H (PDPCRH)
Bit:
15
14
13
12
11
10
9
8
PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24
PCR PCR PCR PCR PCR PCR PCR PCR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
7
0
R
6
5
4
3
2
1
0
PD22 PD21 PD20 PD19 PD18 PD17 PD16
PCR PCR PCR PCR PCR PCR PCR
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD31PCR
0
R/W
14
PD30PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PD29PCR
0
R/W
12
PD28PCR
0
R/W
11
PD27PCR
0
R/W
10
PD26PCR
0
R/W
9
PD25PCR
0
R/W
8
PD24PCR
0
R/W
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
PD22PCR
0
R/W
5
PD21PCR
0
R/W
4
PD20PCR
0
R/W
3
PD19PCR
0
R/W
2
PD18PCR
0
R/W
1
PD17PCR
0
R/W
0
PD16PCR
0
R/W
Page 1256 of 1778
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Pull-Up MOS Control Register L (PDPCRL)
Bit:
15
14
13
12
11
10
PD15 PD14 PD13 PD12 PD11 PD10
PCR PCR PCR PCR PCR PCR
0
0
0
0
0
0
Initial value:
R/W: R/W R/W R/W R/W R/W R/W
9
PD9
PCR
0
R/W
8
PD8
PCR
0
R/W
7
PD7
PCR
0
R/W
6
5
PD6 PD5
PCR PCR
0
0
R/W R/W
4
PD4
PCR
0
R/W
3
PD3
PCR
0
R/W
2
PD2
PCR
0
R/W
1
PD1
PCR
0
R/W
0
PD0
PCR
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD15PCR
0
R/W
14
PD14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PD13PCR
0
R/W
12
PD12PCR
0
R/W
11
PD11PCR
0
R/W
10
PD10PCR
0
R/W
9
PD9PCR
0
R/W
8
PD8PCR
0
R/W
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1257 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
(3)
SH7286
• Port D Pull-Up MOS Control Register H (PDPCRH)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD31 PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16
PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR PCR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial
Value
R/W
Description
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
15
PD31PCR
0
R/W
14
PD30PCR
0
R/W
13
PD29PCR
0
R/W
12
PD28PCR
0
R/W
11
PD27PCR
0
R/W
10
PD26PCR
0
R/W
9
PD25PCR
0
R/W
8
PD24PCR
0
R/W
7
PD23PCR
0
R/W
6
PD22PCR
0
R/W
5
PD21PCR
0
R/W
4
PD20PCR
0
R/W
3
PD19PCR
0
R/W
2
PD18PCR
0
R/W
1
PD17PCR
0
R/W
0
PD16PCR
0
R/W
Page 1258 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port D Pull-Up MOS Control Register L (PDPCRL)
Bit:
15
14
13
12
11
10
PD15 PD14 PD13 PD12 PD11 PD10
PCR PCR PCR PCR PCR PCR
0
0
0
0
0
Initial value: 0
R/W: R/W R/W R/W R/W R/W R/W
9
PD9
PCR
0
R/W
8
PD8
PCR
0
R/W
7
PD7
PCR
0
R/W
6
PD6
PCR
0
R/W
5
PD5
PCR
0
R/W
4
PD4
PCR
0
R/W
3
PD3
PCR
0
R/W
2
PD2
PCR
0
R/W
1
PD1
PCR
0
R/W
0
PD0
PCR
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD15PCR
0
R/W
14
PD14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PD13PCR
0
R/W
12
PD12PCR
0
R/W
11
PD11PCR
0
R/W
10
PD10PCR
0
R/W
9
PD9PCR
0
R/W
8
PD8PCR
0
R/W
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
23.1.13 Port E I/O Register L (PEIORL)
PEIORL is a 16-bit readable/writable register that is used to set the pins on port C as inputs or
outputs. Bits PE15IOR to PE0IOR correspond to pins PE15 to PE0 respectively (multiplexed port
pin names except for the port names are abbreviated here). PEIORL is enabled when the port C
pins are functioning as general-purpose inputs/outputs (PC15 to PC0) and TIOC input/output in
MTU2. In other states, PEIORL is disabled. A given pin on port E will be an output pin if the
corresponding bit in PEIORL is set to 1, and an input pin if the bit is cleared to 0. The initial value
of PEIORL is H'0000.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1259 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.14 Port E Control Register L1 to L4 (PECRL1 to PECRL4)
PECRL1 to PECRL4 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port E.
(1)
SH7243
• Port E Control Register L4 (PECRL4)
Bit:
15
-
14
13
12
PE15MD[2:0]
11
10
-
9
8
PE14MD[2:0]
7
-
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
6
5
4
PE13MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PE12MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE15MD[2:0]
000
R/W
PE15 Mode
Select the function of the
PE15/DACK1/IRQOUT/REFOUT/TIOC4D pin.
000: PE15 I/O (port)
001: Setting prohibited
010: DACK1 output (DMAC)
011: IRQOUT output (INTC)/REFOUT output (BSC)*
100: Setting prohibited
101: Setting prohibited
110: TIOC4D I/O (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1260 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PE14MD[2:0]
000
R/W
PE14 Mode
Select the function of the PE14/DACK0/TIOC4C pin.
000: PE14 I/O (port)
001: Setting prohibited
010: DACK0 output (DMAC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC4C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE13MD[2:0]
000
R/W
PE13 Mode
Select the function of the PE13/MRES/TIOC4B pin.
000: PE13 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: MRES input (system control)
100: Setting prohibited
101: Setting prohibited
110: TIOC4B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1261 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE12MD[2:0]
000
R/W
PE12 Mode
Select the function of the PE12/TIOC4A pin.
000: PE12 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC4A I/O (MTU2)
111: Setting prohibited
Note:
*
IRQOUT (INTC) or REFOUT (BSC) is selected by the IRQOUT function control register
(IFCR).
• Port E Control Register L3 (PECRL3)
Bit:
15
-
14
13
12
PE11MD[2:0]
11
10
-
9
8
PE10MD[2:0]
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
6
-
0
R
0
R/W
5
4
3
PE9MD[2:0]
-
0
R/W
0
R
0
R/W
2
1
0
PE8MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE11MD[2:0]
000
R/W
PE11 Mode
Select the function of the PE11/TIOC3D pin.
000: PE11 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC3D I/O (MTU2)
111: Setting prohibited
Page 1262 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE10MD[2:0]
000
R/W
PE10 Mode
Select the function of the PE10/TXD2/TIOC3C pin.
000: PE10 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD2 output (SCI)
110: TIOC3C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE9MD[2:0]
000
R/W
PE9 Mode
Select the function of the PE9/TIOC3B pin.
000: PE9 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC3B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1263 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE8MD[2:0]
000
R/W
PE8 Mode
Select the function of the PE8/SCK2/TIOC3A pin.
000: PE8 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK2 I/O (SCI)
110: TIOC3A I/O (MTU2)
111: Setting prohibited
• Port E Control Register L2 (PECRL2)
Bit:
15
-
14
13
12
11
10
-
PE7MD[2:0]
9
8
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
6
-
PE6MD[2:0]
0
R/W
0
R
5
4
3
PE5MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PE4MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE7MD[2:0]
000
R/W
PE7 Mode
Select the function of the
PE7/BS/UBCTRG/RXD2/TIOC2B pin.
000: PE7 I/O (port)
001: BS output (BSC)
010: Setting prohibited
011: UBCTRG output (UBC)
100: Setting prohibited
101: RXD2 input (SCI)
110: TIOC2B I/O (MTU2)
111: Setting prohibited
Page 1264 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE6MD[2:0]
000
R/W
PE6 Mode
Select the function of the
PE6/TIOC3DS/SCK3/TIOC2A pin.
000: PE6 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: SCK3 I/O (SCI)
110: TIOC2A I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE5MD[2:0]
000
R/W
PE5 Mode
Select the function of the
PE5/TIOC3BS/TXD3/TIOC1B pin.
000: PE5 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: TXD3 output (SCIF)
110: TIOC1B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1265 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE4MD[2:0]
000
R/W
PE4 Mode
Select the function of the PE4/RXD3/TIOC1A pin.
000: PE4 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 input (SCIF)
110: TIOC1A I/O (MTU2)
111: Setting prohibited
• Port E Control Register L1 (PECRL1)
Bit:
15
-
14
13
12
11
10
-
PE3MD[2:0]
9
8
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
6
-
PE2MD[2:0]
0
R/W
0
R
5
4
3
PE1MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PE0MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE3MD[2:0]
000
R/W
PE3 Mode
Select the function of the
PE3/TEND1/TIOC4DS/TIOC0D pin.
000: PE3 I/O (port)
001: Setting prohibited
010: TEND1 output (DMAC)
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: TIOC0D I/O (MTU2)
111: Setting prohibited
Page 1266 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE2MD[2:0]
000
R/W
PE2 Mode
Select the function of the
PE2/DREQ1/TIOC4CS/TIOC0C pin.
000: PE2 I/O (port)
001: Setting prohibited
010: DREQ1 input (DMAC)
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: TIOC0C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE1MD[2:0]
000
R/W
PE1 Mode
Select the function of the
PE1/TEND0/TIOC4BS/TIOC0B pin.
000: PE1 I/O (port)
001: Setting prohibited
010: TEND0 output (DMAC)
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: TIOC0B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1267 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE0MD[2:0]
000
R/W
PE0 Mode
Select the function of the
PE0/DREQ0/TIOC4AS/TIOC0A pin.
000: PE0 I/O (port)
001: Setting prohibited
010: DREQ0 input (DMAC)
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: TIOC0A I/O (MTU2)
111: Setting prohibited
(2)
SH7285
• Port E Control Register L4 (PECRL4)
Bit:
15
-
14
13
12
PE15MD[2:0]
11
10
-
9
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
0
R/W
0
R/W
0
R/W
0
R
8
PE14MD[2:0]
0
R/W
0
R/W
0
R/W
7
-
0
R
6
5
4
PE13MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PE12MD[2:0]
0
R/W
0
R/W
0
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1268 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PE15MD[2:0]
000
R/W
PE15 Mode
Select the function of the
PE15/DACK1/IRQOUT/REFOUT/TIOC4D pin.
000: PE15 I/O (port)
001: Setting prohibited
010: DACK1 output (DMAC)
011: IRQOUT output (INTC)/REFOUT output (BSC)*
100: Setting prohibited
101: Setting prohibited
110: TIOC4D I/O (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE14MD[2:0]
000
R/W
PE14 Mode
Select the function of the PE14/AH/DACK0/TIOC4C
pin.
000: PE14 I/O (port)
001: AH output (BSC)
010: DACK0 output (DMAC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC4C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1269 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
6 to 4
PE13MD[2:0]
000
R/W
PE13 Mode
Select the function of the PE13/MRES/TIOC4B pin.
000: PE13 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: MRES (system control)
100: Setting prohibited
101: Setting prohibited
110: TIOC4B I/O (MTU2)
111: Setting prohibited
⎯
3
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PE12MD[2:0]
000
R/W
PE12 Mode
Select the function of the PE12/TIOC4A pin.
000: PE12 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC4A I/O (MTU2)
111: Setting prohibited
Note:
*
IRQOUT (INTC) or REFOUT (BSC) is selected by the IRQOUT function control register
(IFCR).
Page 1270 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port E Control Register L3 (PECRL3)
Bit:
15
-
14
13
12
PE11MD[2:0]
11
10
-
9
8
PE10MD[2:0]
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
6
-
0
R
0
R/W
5
4
3
PE9MD[2:0]
-
0
R/W
0
R
0
R/W
2
1
0
PE8MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE11MD[2:0]
000
R/W
PE11 Mode
Select the function of the PE11/TIOC3D pin.
000: PE11 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC3D I/O (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE10MD[2:0]
000
R/W
PE10 Mode
Select the function of the PE10/TXD2/TIOC3C pin.
000: PE10 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD2 output (SCI)
110: TIOC3C I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1271 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE9MD[2:0]
000
R/W
PE9 Mode
Select the function of the PE9/TIOC3B pin.
000: PE9 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC3B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PE8MD[2:0]
000
R/W
PE8 Mode
Select the function of the PE8/SCK2/TIOC3A pin.
000: PE8 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK2 I/O (SCI)
110: TIOC3A I/O (MTU2)
111: Setting prohibited
Page 1272 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port E Control Register L2 (PECRL2)
Bit:
15
-
14
13
12
11
10
-
PE7MD[2:0]
9
8
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
6
-
PE6MD[2:0]
0
R/W
0
R
5
4
3
PE5MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PE4MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE7MD[2:0]
000
R/W
PE7 Mode
Select the function of the
PE7/BS/UBCTRG/RXD2/TIOC2B pin.
000: PE7 I/O (port)
001: BS output (BSC)
010: Setting prohibited
011: UBCTRG output (UBC)
100: Setting prohibited
101: RXD2 input (SCI)
110: TIOC2B I/O (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE6MD[2:0]
000
R/W
PE6 Mode
Select the function of the
PE6/TIOC3DS/SCK3/TIOC2A pin.
000: PE6 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: SCK3 I/O (SCI)
110: TIOC2A I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1273 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE5MD[2:0]
000
R/W
PE5 Mode
Select the function of the
PE5/TIOC3BS/TXD3/TIOC1B pin.
000: PE5 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: TXD3 output (SCIF)
110: TIOC1B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PE4MD[2:0]
000
R/W
PE4 Mode
Select the function of the PE4/RXD3/TIOC1A pin.
000: PE4 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 input (SCIF)
110: TIOC1A I/O (MTU2)
111: Setting prohibited
Page 1274 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
• Port E Control Register L1 (PECRL1)
Bit:
15
-
14
13
12
11
10
-
PE3MD[2:0]
9
8
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
6
-
PE2MD[2:0]
0
R/W
0
R
5
4
3
PE1MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PE0MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE3MD[2:0]
000
R/W
PE3 Mode
Select the function of the
PE3/TEND1/TIOC4DS/TIOC0D pin.
000: PE3 I/O (port)
001: Setting prohibited
010: TEND1 output (DMAC)
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: TIOC0D I/O (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE2MD[2:0]
000
R/W
PE2 Mode
Select the function of the
PE2/DREQ1/TIOC4CS/TIOC0C pin.
000: PE2 I/O (port)
001: Setting prohibited
010: DREQ1 input (DMAC)
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: TIOC0C I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1275 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE1MD[2:0]
000
R/W
PE1 Mode
Select the function of the
PE1/TEND0/TIOC4BS/TIOC0B pin.
000: PE1 I/O (port)
001: Setting prohibited
010: TEND0 output (DMAC)
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: TIOC0B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0
PE0MD[2:0]
000
R/W
PE0 Mode
Select the function of the
PE0/DREQ0/TIOC4AS/TIOC0A pin.
000: PE0 I/O (port)
001: Setting prohibited
010: DREQ0 input (DMAC)
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: TIOC0A I/O (MTU2)
111: Setting prohibited
Page 1276 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 23 Pin Function Controller (PFC)
SH7286
• Port E Control Register L4 (PECRL4)
Bit:
15
-
14
13
12
PE15MD[2:0]
11
10
-
9
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
15
⎯
0
R
0
R/W
0
R/W
0
R/W
0
R
8
7
-
PE14MD[2:0]
0
R/W
0
R/W
0
R/W
0
R
6
5
4
PE13MD[2:0]
0
R/W
0
R/W
0
R/W
3
-
0
R
2
1
0
PE12MD[2:0]
0
R/W
0
R/W
0
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE15MD[2:0]
000
R/W
PE15 Mode
Select the function of the
PE15/DACK1/IRQOUT/REFOUT/TIOC4D pin.
000: PE15 I/O (port)
001: Setting prohibited
010: DACK1 output (DMAC)
011: IRQOUT output (INTC)/REFOUT output (BSC)*
100: Setting prohibited
101: Setting prohibited
110: TIOC4D I/O (MTU2)
111: Setting prohibited
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1277 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
10 to 8
PE14MD[2:0]
000
R/W
PE14 Mode
Select the function of the PE14/AH/DACK0/TIOC4C
pin.
000: PE14 I/O (port)
001: AH output (BSC)
010: DACK0 output (DMAC)
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC4C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE13MD[2:0]
000
R/W
PE13 Mode
Select the function of the PE13/MRES/TIOC4B pin.
000: PE13 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: MRES input (system control)
100: Setting prohibited
101: Setting prohibited
110: TIOC4B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1278 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE12MD[2:0]
000
R/W
PE12 Mode
Select the function of the PE12/TIOC4A pin.
000: PE12 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC4A I/O (MTU2)
111: Setting prohibited
Note:
*
IRQOUT (INTC) or REFOUT (BSC) is selected by the IRQOUT function control register
(IFCR).
• Port E Control Register L3 (PECRL3)
Bit:
15
-
14
13
12
PE11MD[2:0]
11
10
-
9
8
PE10MD[2:0]
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
6
-
0
R
0
R/W
5
4
3
PE9MD[2:0]
-
0
R/W
0
R
0
R/W
2
1
0
PE8MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE11MD[2:0]
000
R/W
PE11 Mode
Select the function of the PE11/TIOC3D pin.
000: PE11 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC3D I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1279 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE10MD[2:0]
000
R/W
PE10 Mode
Select the function of the PE10/TXD2/TIOC3C pin.
000: PE10 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: TXD2 output (SCI)
110: TIOC3C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE9MD[2:0]
000
R/W
PE9 Mode
Select the function of the PE9/FRAME/TIOC3B pin.
000: PE9 I/O (port)
001: FRAME output (BSC)
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: TIOC3B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1280 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE8MD[2:0]
000
R/W
PE8 Mode
Select the function of the PE8/SCK2/TIOC3A pin.
000: PE8 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: SCK2 I/O (SCI)
110: TIOC3A I/O (MTU2)
111: Setting prohibited
• Port E Control Register L2 (PECRL2)
Bit:
15
-
14
13
12
11
10
-
PE7MD[2:0]
9
8
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
6
-
PE6MD[2:0]
0
R/W
0
R
5
4
3
PE5MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PE4MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE7MD[2:0]
000
R/W
PE7 Mode
Select the function of the
PE7/BS/UBCTRG/RXD2/TIOC2B pin.
000: PE7 I/O (port)
001: BS output (BSC)
010: Setting prohibited
011: UBCTRG output (UBC)
100: Setting prohibited
101: RXD2 input (SCI)
110: TIOC2B I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1281 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE6MD[2:0]
000
R/W
PE6 Mode
Select the function of the
PE6/TIOC3DS/SCK3/TIOC2A pin.
000: PE6 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3DS I/O (MTU2S)
101: SCK3 I/O (SCI)
110: TIOC2A I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE5MD[2:0]
000
R/W
PE5 Mode
Select the function of the
PE5/TIOC3BS/TXD3/TIOC1B pin.
000: PE5 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: TIOC3BS I/O (MTU2S)
101: TXD3 output (SCIF)
110: TIOC1B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1282 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE4MD[2:0]
000
R/W
PE4 Mode
Select the function of the PE4/RXD3/TIOC1A pin.
000: PE4 I/O (port)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: RXD3 input (SCIF)
110: TIOC1A I/O (MTU2)
111: Setting prohibited
• Port E Control Register L1 (PECRL1)
Bit:
15
-
14
13
12
11
10
-
PE3MD[2:0]
9
8
7
Initial value:
R/W:
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
⎯
0
R
Reserved
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
6
-
PE2MD[2:0]
0
R/W
0
R
5
4
3
PE1MD[2:0]
-
0
R/W
0
R
0
R/W
0
R/W
2
1
0
PE0MD[2:0]
0
R/W
0
R/W
0
R/W
This bit is always read as 0. The write value should
always be 0.
14 to 12
PE3MD[2:0]
000
R/W
PE3 Mode
Select the function of the
PE3/TEND1/TIOC4DS/TIOC0D pin.
000: PE3 I/O (port)
001: Setting prohibited
010: TEND1 output (DMAC)
011: Setting prohibited
100: TIOC4DS I/O (MTU2S)
101: Setting prohibited
110: TIOC0D I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1283 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8
PE2MD[2:0]
000
R/W
PE2 Mode
Select the function of the
PE2/DREQ1/TIOC4CS/TIOC0C pin.
000: PE2 I/O (port)
001: Setting prohibited
010: DREQ1 input (DMAC)
011: Setting prohibited
100: TIOC4CS I/O (MTU2S)
101: Setting prohibited
110: TIOC0C I/O (MTU2)
111: Setting prohibited
7
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4
PE1MD[2:0]
000
R/W
PE1 Mode
Select the function of the
PE1/TEND0/TIOC4BS/TIOC0B pin.
000: PE1 I/O (port)
001: Setting prohibited
010: TEND0 output (DMAC)
011: Setting prohibited
100: TIOC4BS I/O (MTU2S)
101: Setting prohibited
110: TIOC0B I/O (MTU2)
111: Setting prohibited
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1284 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
2 to 0
PE0MD[2:0]
000
R/W
PE0 Mode
Select the function of the
PE0/DREQ0/TIOC4AS/TIOC0A pin.
000: PE0 I/O (port)
001: Setting prohibited
010: DREQ0 input (DMAC)
011: Setting prohibited
100: TIOC4AS I/O (MTU2S)
101: Setting prohibited
110: TIOC0A I/O (MTU2)
111: Setting prohibited
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1285 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.15 Port E Pull-Up MOS Control Register L (PEPCRL)
PFCRL controls the on/off of the input pull-up MOS of the port E in bits.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PE15
PCR
PE14
PCR
PE13
PCR
PE12
PCR
PE11
PCR
PE10
PCR
PE9
PCR
PE8
PCR
PE7
PCR
PE6
PCR
PE5
PCR
PE4
PCR
PE3
PCR
PE2
PCR
PE1
PCR
PE0
PCR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PE15PCR
0
R/W
14
PE14PCR
0
R/W
The corresponding input pull-up MOS turns on when
one of these bits is set to 1.
13
PE13PCR
0
R/W
12
PE12PCR
0
R/W
11
PE11PCR
0
R/W
10
PE10PCR
0
R/W
9
PE9PCR
0
R/W
8
PE8PCR
0
R/W
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
4
PE4PCR
0
R/W
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
Page 1286 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.16 Large Current Port Control Register (HCPCR)
HCPCR is a 16-bit readable/writable register that is used to control the large current port. It
controls bits PD10 to PD15, PE0 to PE3, PE5, PE6, PE9, PE11 to PE15 in SH7243, PD10 to
PD15, PD24 to PD29, PE0 to PE3, PE5, PE6, PE9, PE11 to PE15 in SH7285, and PD10 to PD15,
PD24 to PD29, PE0 to PE3, PE5, PE6, and PE9 in SH7286.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
MZI
ZDH
MZI
ZDL
MZI
ZEH
MZI
ZEL
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R/W
1
R/W
1
R/W
1
R/W
Bit
Bit Name
Initial
Value
R/W
15 to 4
⎯
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
3
MZIZDH
1
R/W
Port D Large Current Port High Impedance H
Selects whether to set the large current port of PD24
to PD29 to the high-impedance state regardless of the
setting of the PFC during the oscillation stop detection
and software standby mode.
0: Set to the high-impedance state
1: Do not set to the high-impedance state
The pin state is retained during the oscillation stop
detection when this bit is set to 1. See appendix A,
Pin States, for details on the software standby mode.
2
MZIZEL
1
R/W
Port D Large Current Port High Impedance L
Selects whether to set the large current port of PD10
to PD15 to the high-impedance state regardless of the
setting of the PFC during the oscillation stop detection
and software standby mode.
0: Set to the high-impedance state
1: Do not set to the high-impedance state
The pin state is retained during the oscillation stop
detection when this bit is set to 1. See appendix A,
Pin States, for details on the software standby mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1287 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
Bit
Bit Name
Initial
Value
R/W
Description
1
MZIZEH
1
R/W
Port E Large Current Port High Impedance H
Selects whether to set the large current port of PE9,
PE11 to PE15 to the high-impedance state regardless
of the setting of the PFC during the oscillation stop
detection and software standby mode.
0: Set to the high-impedance state
1: Do not set to the high-impedance state
The pin state is retained during the oscillation stop
detection when this bit is set to 1. See appendix A,
Pin States, for details on the software standby mode
0
MZIZEL
1
R/W
Port E Large Current Port High Impedance L
Selects whether to set the large current port of PE0 to
PE3, PE5 and PE6 to the high-impedance state
regardless of the setting of the PFC during the
oscillation stop detection and software standby mode.
0: Set to the high-impedance state
1: Do not set to the high-impedance state
The pin state is retained during the oscillation stop
detection when this bit is set to 1. See appendix A,
Pin States, for details on the software standby mode.
Page 1288 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.1.17 IRQOUT Function Control Register (IFCR)
IFCR is a 16-bit readable/writable register that is used to control the IRQOUT pin output when it
is selected as the multiplexed pin function by port D control register H4 (PDCRH4) and port E
control register L4 (PECRL4). When PDCRH4 or PECRL4 selects another function, the IFCR
setting does not affect the pin function.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
IRQ
MD3
IRQ
MD2
IRQ
MD1
IRQ
MD0
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
15 to 4
⎯
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
3
IRQMD3
0
R/W
Port D IRQOUT Pin Function Select
2
IRQMD2
0
R/W
Select the IRQOUT pin function when bits 10, 9 and 8
(PD30MD2, PD30MD1 and PD30MD0) in PDCRH4
are set to 0, 1, and 1.
00: Interrupt request accept output
01: Refresh signal output
10: Interrupt request accept output or refresh signal
output (depends on the operating state)
11: Always high-level output
1
IRQMD1
0
R/W
Port E IRQOUT Pin Function Select
0
IRQMD0
0
R/W
Select the IRQOUT pin function when bits 14, 13 and
12 (PE15MD2, PE15MD1 and PE15MD0) in PECRL4
are set to 0, 1, and 1.
00: Interrupt request accept output
01: Refresh signal output
10: Interrupt request accept output or refresh signal
output (depends on the operating state)
11: Always high-level output
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1289 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
23.2
Pull-Up MOS Control by Pin Function
Table 23.18 shows the pull-up MOS control by pin function and the pull-up MOS control in each
operating mode.
Table 23.18 Pull-Up MOS Control
When
Power-On Manual
Software
Pin Function
Reset
Reset
Reset
I/O port input (port)
Off
On/off
On/off
Oscillation
When POE
Stop is
Function is Normal
Sleep
Detected
Used
Operation
On/off
On/off
On/off
On/off
BREQ input, WAIT input (BSC)
DREQ0 to DREQ3 input (DMAC)
IRQ0 to IRQ7 input (INTC)
MRES input (system control)
POE0 to POE8 input (POE2)
RXD0 to RXD4 input, SCK0 to
SCK4 input (SCI, SCIF)
CRx0 input (RCAN)
ADTRG input (ADC)
SCS input, SSI input, SSO input,
SSCK input (SSU)
TDI input, TMS input, TCK input,
TRST input (H-UDI)
Page 1290 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
When
Power-On
Manual
Software
Pin Function
Reset
Reset
Reset
I/O port output, address output,
Off
On/off*
On/off*
Oscillation
When POE
Stop is
Function is Normal
Sleep
Detected
Used
Operation
On/off*
On/off*
On/off*
On/off*
CK output, RD output (BSC),
WRHH, WRHL, WRH, WRL output
(BSC),
DQMUU, DQMUL, DQMLU,
DQMLL output (BSC),
RD/WR output, CS0 to CS7
output, BS output, FRAME output
(BSC),
AH output, BACK output, REFOUT
output (BSC),
CKE output, CASU output, CASL
output, RASU output, RASL output
(BSC),
DACK0 to DACK3 output, TEND0,
TEND1 (DMAC),
IRQOUT output (INTC),
UBCTRG output (UBC),
SCK0 to SCK4 output, TXD0 to
TXD4 output (SCI, SCIF),
USPND output (USB),
CTx0 output (RCAN), SCS output,
SSI output, SSO output, SSCK
output (SSU)
AUDSYNC output, AUDCK output,
AUDATA0 to AUDATA3 output
(AUD), TDO output (H-UDI)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1291 of 1778
SH7280 Group, SH7243 Group
Section 23 Pin Function Controller (PFC)
When
Power-On
Manual
Software
Pin Function
Reset
Reset
Reset
PB2, PB3 input (port)
Off
Off
Off
Oscillation
When POE
Stop is
Function is Normal
Sleep
Detected
Used
Operation
Off
Off
Off
Off
Data bus input/output
TIC5US, TIC5VS, TIC5WS input
(MTU2S)
TIOC3AS, TIOC3BS, TIOC3CS,
TIOC3DS input/output (MTU2S)
TIOC4AS, TIOC4BS, TIOC4CS,
TIOC4DS input/output (MTU2S)
TCLKA, TCLKB, TCLKC, TCLKD
input (MTU2)
TIC5U, TIC5V, TIC5W input
(MTU2)
TIOC0A, TIOC0B, TIOC0C,
TIOC0D input/output (MTU2)
TIOC1A, TIOC1B, TIOC1C,
TIOC1D input/output (MTU2)
TIOC3A, TIOC3B, TIOC3C,
TIOC3D input/output (MTU2)
TIOC4A, TIOC4B, TIOC4C,
TIOC4D input/output (MTU2)
SCL input/output, SDA input/output
(IIC3)
[Legend]
Off:
Input pull-up MOS is always off.
On/off: Input pull-up MOS is on when the value of pull-up MOS control register is 1 and the pin is
in input state or high impedance and off in other states.
On/off*: Input pull-up MOS is on when the value of pull-up MOS control register is 1 and the pin is
in input state or high impedance and off in other states.
Note: For SCK (SCI, SCIF), SCS, SSI, SSO, and SSCK (SSU) functions, when the pull-up MOS
control register value is 1, if the input/output is switched, the on/off of the pull-up MOS also
switched.
Page 1292 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
23.3
Section 23 Pin Function Controller (PFC)
Usage Notes
1. In this LSI, the same function is available as a multiplexed function on multiple pins. This
approach is intended to increase the number of selectable pin functions and to allow the easier
design of boards. Note the following points when two or more pins are specified for one
function.
• When the pin function is input
Signals input to several pins are formed as one signal through OR or AND logic and the signal
is transmitted into the LSI. Therefore, a signal that differs from the input signals may be
transmitted to the LSI depending on the input signals in other pins that have the same
functions. Table 23.19 shows the transmit forms of input functions allocated to several pins.
When using one of the functions shown below in multiple pins, use it with care of signal
polarity considering the transmit forms.
Table 23.19 Transmission Format of Input Function Allocated on Multiple Pins
OR Type
AND Type
SCK0, SCK3, RXD0, RXD2, RXD3, POE0
POE4 POE8, TIOC3AS to TIOC4DS, TIC5U,
TIC5V, TIC5W, TIC5VS, TIC5WS
IRQ0 to IRQ6, DREQ0, DREQ1, ADTRG
OR Type:
AND Type:
Signals input to several pins are formed as one signal through OR logic and the
signal is transmitted into the LSI.
Signals input to several pins are formed as one signal through AND logic and
the signal is transmitted into the LSI.
• When the pin function is output
Each selected pin can output the same function.
2. When the port input is switched from the low level to the DREQ edge or the IRQ edge for the
pins that are multiplexed with I/O and DREQ or IRQ, the corresponding edge is detected.
3. Do not set functions other than those specified in tables 23.1 to 23.16. Otherwise, correct
operation cannot be guaranteed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1293 of 1778
Section 23 Pin Function Controller (PFC)
Page 1294 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Section 24 I/O Ports
SH7243 has six ports: A, B, C, D, E, and F. Port A is an 8-bit, port B is a 7-bit, ports C to E are
16-bit I/O ports, and port F is an 8-bit input-only port.
SH7285 has six ports: A, B, C, D, E, and F. Port A is a 17-bit, port B is an 11-bit, port C is a 16bit, port D is a 32-bit and port E is a 16-bit I/O port, and port F is an 8-bit input-only port.
SH7286 has six ports: A, B, C, D, E, and F. Port A is a 19-bit, port B is an 18-bit, port C is a 16bit, port D is a 32-bit and port E is a 16-bit I/O port, and port F is a 12-bit input-only port.
All port pins are multiplexed with other pin functions. The functions of the multiplex pins are
selected by means of the pin function controller (PFC). Each port is provided with data registers
for storing the pin data.
24.1
Port A
Port A of SH7243 is an I/O port with 8 pins shown in figure 24.1.
PA15 (I/O) / CK (output)
PA14 (I/O) / RD (output)
PA13 (I/O) / WRL (output) / DQMLL (output)
Port A
PA12 (I/O) / WRH (output) / DQMLU (output) / POE8 (input)
PA9 (I/O) / CKE (output) / TCLKD (input) / RXD3 (input)
PA8 (I/O) / TCLKC (input) / TXD3 (output) / RDWR (output)
PA7 (I/O) / CASL (output) / TCLKB (input) / SCK3 (I/O)
PA6 (I/O) / RASL (output) / TCLKA (input)
Figure 24.1 Port A (SH7243)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1295 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Port A of SH7285 is an I/O port with 17 pins shown in figure 24.2.
PA23 (I/O) / CKE (output) / TIC5W (input) / POE0 (input) / IRQ1 (input) / AH (output)
PA22 (I/O) / CASL (output) / TIC5V (input) / POE4 (input) / IRQ2 (input) / CASU (output)
PA21 (I/O) / RASL (output) / TIC5U (input) / POE8 (input) / IRQ3 (input) / RASU (output)
PA15 (I/O) / CK (output)
PA14 (I/O) / RD (output)
PA13 (I/O) / WRL (output) / DQMLL (output)
PA12 (I/O) / WRH (output) / DQMLU (output) / POE8 (input)
PA9 (I/O) / CKE (output) / TCLKD (input) / RXD3 (input)
Port A
PA8 (I/O) / TCLKC (input) / TXD3 (output) / RDWR (output)
PA7 (I/O) / CASL (output) / TCLKB (input) / SCK3 (I/O)
PA6 (I/O) / RASL (output) / TCLKA (input)
PA5 (I/O) / SCK1 (I/O) / SSCK (I/O) / CS5 (output)
PA4 (I/O) / TXD1 (output) / SSO (I/O) / CS4 (output) / TRST (input)
PA3 (I/O) / RXD1 (input) / SSI (I/O) / CS3 (output) / TMS (input)
PA2 (I/O) / SCK0 (I/O) / SCS (I/O) / CS2 (output) / TCK (input)
PA1 (I/O) / TXD0 (output) / CS1 (output) / TDO (output)
PA0 (I/O) / RXD0 (input) / CS0 (output) / TDI (input)
Figure 24.2 Port A (SH7285)
Page 1296 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Port A of SH7286 is an I/O port with 19 pins shown in figure 24.3.
PA23 (I/O) / CKE (output) / TIC5W (input) / POE0 (input) / IRQ1 (input) / AH (output)
PA22 (I/O) / CASL (output) / TIC5V (input) / POE4 (input) / IRQ2 (input) / CASU (output)
PA21 (I/O) / RASL (output) / TIC5U (input) / POE8 (input) / IRQ3 (input) / RASU (output)
PA15 (I/O) / CK (output)
PA14 (I/O) / RD (output)
PA13 (I/O) / WRL (output) / DQMLL (output)
PA12 (I/O) / WRH (output) / DQMLU (output) / POE8 (input)
PA11 (I/O) / WRHH (output) / DQMUU (output) / AH (output)
PA10 (I/O) / WRHL (output) / DQMUL (output)
Port A
PA9 (I/O) / CKE (output) / TCLKD (input) / RXD3 (input)
PA8 (I/O) / TCLKC (input) / TXD3 (output) / RDWR (output)
PA7 (I/O) / CASL (output) / TCLKB (input) / SCK3 (I/O)
PA6 (I/O) / RASL (output) / TCLKA (input)
PA5 (I/O) / SCK1 (I/O) / SSCK (I/O) / CS5 (output)
PA4 (I/O) / TXD1 (output) / SSO (I/O) / CS4 (output)
PA3 (I/O) / RXD1 (input) / SSI (I/O) / CS3 (output)
PA2 (I/O) / SCK0 (I/O) / SCS (I/O) / CS2 (output)
PA1 (I/O) / TXD0 (output) / CS1 (output)
PA0 (I/O) / RXD0 (input) / CS0 (output)
Figure 24.3 Port A (SH7286)
24.1.1
Register Descriptions
Port A is an 8-bit I/O port in SH7243, 17-bit I/O port in SH7285 and 19-bit I/O port in SH7286.
Port A has the following registers. See section 30, List of Registers for details on the register
address and states in each operating mode.
Table 24.1 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port A data register H
PADRH
R/W
H'0000
H'FFFE3800
8, 16, 32
Port A data register L
PADRL
R/W
H'0000
H'FFFE3802
8, 16
Port A port register H
PAPRH
R
H'xxxx
H'FFFE381C
8, 16, 32
Port A port register L
PAPRL
R
H'xxxx
H'FFFE381E
8, 16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1297 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.1.2
Port A Data Registers H and L (PADRH and PADRL)
PADRH and PADRL are 16-bit readable/writable registers that store port A data. In SH7243, bits
PA15DR to PA12DR and PA9DR to PA6DR correspond to pins PA15 to PA12 and PA9 to PA6
respectively (description of multiplexed functions are abbreviated here). In SH7285, bits PA23DR
to PA21DR, PA15DR to PA12DR and PA9DR to PA0DR correspond to pins PA23 to PA21,
PA15 to PA12 and PA9 to PA0 respectively (description of multiplexed functions are abbreviated
here). In SH7286, bits PA23DR to PA21DR and PA15DR to PA0DR correspond to pins PA23 to
PA21 and PA15 to PA0 respectively (description of multiplexed functions are abbreviated here).
When a pin function is general output, if a value is written to PADRH or PADRL, the value is
output directly from the pin, and if PADRH or PADRL is read, the register value is returned
directly regardless of the pin state.
When a pin function is general input, if PADRH or PADRL is read, the pin state, not the register
value, is returned directly. If a value is written to PADRH or PADRL, although that value is
written into PADRH or PADRL, it does not affect the pin state. Table 24.2 summarizes read/write
operations of port A data register.
• PADRH (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 1298 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PADRH (SH7285 and SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PA23
DR
PA22
DR
PA21
DR
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
PA23DR
0
R/W
6
PA22DR
0
R/W
5
PA21DR
0
R/W
4 to 0
⎯
All 0
R
See table 24.2.
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1299 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PADRL (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PA15
DR
PA14
DR
PA13
DR
PA12
DR
-
-
PA9
DR
PA8
DR
PA7
DR
PA6
DR
-
-
-
-
-
-
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15
PA15DR
0
R/W
See table 24.2.
14
PA14DR
0
R/W
13
PA13DR
0
R/W
12
PA12DR
0
R/W
11, 10
⎯
All 0
R
0
Reserved
These bits are always read as 0. The write value should
always be 0.
9
PA9DR
0
R/W
8
PA8DR
0
R/W
7
PA7DR
0
R/W
6
PA6DR
0
R/W
5 to 0
⎯
All 0
R
See table 24.2.
Reserved
These bits are always read as 0. The write value should
always be 0.
Page 1300 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PADRL (SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
DR
PA14
DR
PA13
DR
PA12
DR
-
-
PA9
DR
PA8
DR
PA7
DR
PA6
DR
PA5
DR
PA4
DR
PA3
DR
PA2
DR
PA1
DR
PA0
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PA15DR
0
R/W
See table 24.2.
14
PA14DR
0
R/W
13
PA13DR
0
R/W
12
PA12DR
0
R/W
11, 10
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
PA9DR
0
R/W
8
PA8DR
0
R/W
7
PA7DR
0
R/W
6
PA6DR
0
R/W
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
See table 24.2.
Page 1301 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PADRL (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
DR
PA14
DR
PA13
DR
PA12
DR
PA11
DR
PA10
DR
PA9
DR
PA8
DR
PA7
DR
PA6
DR
PA5
DR
PA4
DR
PA3
DR
PA2
DR
PA1
DR
PA0
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PA15DR
0
R/W
See table 24.2.
14
PA14DR
0
R/W
13
PA13DR
0
R/W
12
PA12DR
0
R/W
11
PA11DR
0
R/W
10
PA10DR
0
R/W
9
PA9DR
0
R/W
8
PA8DR
0
R/W
7
PA7DR
0
R/W
6
PA6DR
0
R/W
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
Page 1302 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Table 24.2 Port A Data Registers H and L (PADRH and PADRL) Read/Write Operations
• PADRH bits 7 to 5 and PADRL bits 15 to 0
PAIORH,
PAIORL
Pin Function
Read
Write
0
General input
Pin state
Can write to PADRH and PADRL, but it has no
effect on pin state.
Other than
general input
Pin state
Can write to PADRH and PADRL, but it has no
effect on pin state.
General output
PADRH or
PADRL value
The value written is output from the pin.
Other than
general output
PADRH or
PADRL value
Can write to PADRH and PADRL, but it has no
effect on pin state.
1
24.1.3
Port A Port Registers H and L (PAPRH and PAPRL)
PAPRH and PAPRL are 16-bit read-only registers, which return the states of the pins. However,
when the SCIF function is selected for PA8, the TE bit in SCSCR is 0, and the SPB2IO bit in
SCSPTR is 0, the states of the corresponding pins cannot be read out. In SH7243, bits PA15PR to
PA12PR and PA9PR to PA6PR correspond to pins PA15 to PA12 and PA9 to PA6 respectively
(description of multiplexed functions are abbreviated here). In SH7285, bits PA23PR to PA21PR,
PA15PR to PA12PR and PA9PR to PA0PR correspond to pins PA23 to PA21, PA15 to PA12 and
PA9 to PA0 respectively (description of multiplexed functions are abbreviated here). In SH7286,
bits PA23PR to PA21PR and PA15PR to PA0PR correspond to pins PA23 to PA21 and PA15 to
PA0 respectively (description of multiplexed functions are abbreviated here).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1303 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PAPRH (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
⎯
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
• PAPRH (SH7285 and SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
PA23
PR
PA22
PR
PA21
PR
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
*
R
*
R
*
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
7
PA23PR
Pin state R
6
PA22PR
Pin state R
5
PA21PR
Pin state R
4 to 0
⎯
All 0
R
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
Page 1304 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PAPRL (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
PR
PA14
PR
PA13
PR
PA12
PR
-
-
PA9
PR
PA8
PR
PA7
PR
PA6
PR
-
-
-
-
-
-
Initial value:
R/W:
*
R
*
R
*
R
*
R
0
R
0
R
*
R
*
R
*
R
*
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
15
PA15PR
Pin state R
14
PA14PR
Pin state R
13
PA13PR
Pin state R
12
PA12PR
Pin state R
11, 10
⎯
All 0
R/W
R
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
9
PA9PR
Pin state R
8
PA8PR
Pin state R
7
PA7PR
Pin state R
6
PA6PR
Pin state R
5 to 0
⎯
All 0
R
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1305 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PAPRL (SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
PR
PA14
PR
PA13
PR
PA12
PR
-
-
PA9
PR
PA8
PR
PA7
PR
PA6
PR
PA5
PR
PA4
PR
PA3
PR
PA2
PR
PA1
PR
PA0
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
0
R
0
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PA15PR
Pin state R
14
PA14PR
Pin state R
13
PA13PR
Pin state R
12
PA12PR
Pin state R
11, 10
⎯
All 0
R/W
R
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
9
PA9PR
Pin state R
8
PA8PR
Pin state R
7
PA7PR
Pin state R
6
PA6PR
Pin state R
5
PA5PR
Pin state R
4
PA4PR
Pin state R
3
PA3PR
Pin state R
2
PA2PR
Pin state R
1
PA1PR
Pin state R
0
PA0PR
Pin state R
Page 1306 of 1778
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PAPRL (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PA15
PR
PA14
PR
PA13
PR
PA12
PR
PA11
PR
PA10
PR
PA9
PR
PA8
PR
PA7
PR
PA6
PR
PA5
PR
PA4
PR
PA3
PR
PA2
PR
PA1
PR
PA0
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PA15PR
Pin state R
14
PA14PR
Pin state R
13
PA13PR
Pin state R
12
PA12PR
Pin state R
11
PA11PR
Pin state R
10
PA10PR
Pin state R
9
PA9PR
Pin state R
8
PA8PR
Pin state R
7
PA7PR
Pin state R
6
PA6PR
Pin state R
5
PA5PR
Pin state R
4
PA4PR
Pin state R
3
PA3PR
Pin state R
2
PA2PR
Pin state R
1
PA1PR
Pin state R
0
PA0PR
Pin state R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
R/W
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Page 1307 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.2
Port B
Port B of SH7243 is an I/O port with 7 pins shown in figure 24.4.
PB12 (I/O) / TXD2 (output) / CS7 (output) / CS1 (output) / IRQ1 (input) / CS3 (output)
PB11 (I/O) / RXD2 (input) / CS6 (output) / CS0 (output) / IRQ0 (input) / CS2 (output)
PB8 (I/O) / A20 (output) / WAIT (input) / POE8 (input) / IRQ7 (input) / SCK0 (I/O)
Port B
PB7 (I/O) / A19 (output) / BREQ (input) / POE4 (input) / IRQ6 (input) / TXD0 (output)
PB6 (I/O) / A18 (output) / BACK (output) / POE3 (input) / IRQ5 (input) / RXD0 (input)
PB1 (I/O) / A17 (output) / ADTRG (input) / IRQ4 (input) / REFOUT (output)
PB0 (I/O) / A16 (output) / IRQ3 (input)
Figure 24.4 Port B (SH7243)
Port B of SH7285 is an I/O port with 11 pins shown in figure 24.5.
PB12 (I/O) / TXD2 (output) / CS7 (output) / CS1 (output) / IRQ1 (input) / CS3 (output)
PB11 (I/O) / RXD2 (input) / CS6 (output) / CS0 (output) / IRQ0 (input) / CS2 (output)
PB10 (I/O)
PB9 (I/O) / USPND (output)
PB8 (I/O) / A20 (output) / WAIT (input) / POE8 (input) / IRQ7 (input) / SCK0 (I/O)
Port B
PB7 (I/O) / A19 (output) / BREQ (input) / POE4 (input) / IRQ6 (input) / TXD0 (output)
PB6 (I/O) / A18 (output) / BACK (output) / POE3 (input) / IRQ5 (input)/ RXD0 (input)
PB3 (input) / SDA (I/O) / POE2 (input) / IRQ1 (input)
PB2 (input) / SCL (I/O) / POE1 (input) / IRQ0 (input)
PB1 (I/O) / A17 (output) / ADTRG (input) / IRQ4 (input) / REFOUT (output)
PB0 (I/O) / A16 (output) / IRQ3 (input)
Figure 24.5 Port B (SH7285)
Page 1308 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Port B of SH7286 is an I/O port with 18 pins shown in figure 24.6.
PB19 (I/O) / RASU (output) / A25 (output) / DREQ2 (input)
PB18 (I/O) / RASL (output) / A24 (output) / DACK2 (output)
PB17 (I/O) / CASU (output) / A23 (output) / DREQ3 (input)
PB16 (I/O) / CASL (output) / A22 (output) / DACK3 (output)
PB15 (I/O) / CKE (output) / A21 (output)
PB14 (I/O) / CRx0 (input)
PB13 (I/O) / CTx0 (output)
PB12 (I/O) / TXD2 (output) / CS7 (output) / CS1 (output) / IRQ1 (input) / CS3 (output)
Port B
PB11 (I/O) / RXD2 (input) / CS6 (output) / CS0 (output) / IRQ0 (input) / CS2 (output)
PB10 (I/O)
PB9 (I/O) / USPND (output)
PB8 (I/O) / A20 (output) / WAIT (input) / POE8 (input) /IRQ7 (input) / SCK0 (I/O)
PB7 (I/O) / A19 (output) / BREQ (input) / POE4 (input) / IRQ6 (input) / TXD0 (output)
PB6 (I/O) / A18 (output) / BACK (output) / POE3 (input) / IRQ5 (input) / RXD0 (input)
PB3 (input) / SDA (I/O) / POE2 (input) / IRQ1 (input)
PB2 (input) / SCL (I/O) / POE1 (input) / IRQ0 (input)
PB1 (I/O) / A17 (output) / ADTRG (input) / IRQ4 (input) / REFOUT (output)
PB0 (I/O) / A16 (output) / IRQ3 (input)
Figure 24.6 Port B (SH7286)
24.2.1
Register Descriptions
Port B is a 7-bit I/O port in SH7243, 11-bit I/O port in SH7285 and 18-bit I/O port in SH7286.
Port B has the following registers. See section 30, List of Registers for details on the register
address and states in each operating mode.
Table 24.3 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port B data register H
PBDRH
R/W
H'0000
H'FFFE3880
8, 16, 32
Port B data register L
PBDRL
R/W
H'0000
H'FFFE3882
8, 16
Port B port register H
PBPRH
R
⎯
H'FFFE389C
8, 16, 32
Port B port register L
PBPRL
R
⎯
H'FFFE389E
8, 16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1309 of 1778
Section 24 I/O Ports
24.2.2
SH7280 Group, SH7243 Group
Port B Data Registers H and L (PBDRH and PBDRL)
PBDRH and PBDRL are 16-bit readable/writable registers that store port B data. In SH7243, bits
PB12DR, PB11DR, PB8DR to PB6DR, PB1DR and PB0DR correspond to pins PB12, PB11, PB8
to PB6, PB1 and PB0 respectively (description of multiplexed functions are abbreviated here). In
SH7285, bits PB12DR to PB6DR and PB3DR to PB0DR correspond to pins PB12 to PB6, and
PB3 to PB0 respectively (description of multiplexed functions are abbreviated here). In SH7286,
bits PB19DR to PB6DR and PB3DR to PB0DR correspond to pins PB19 to PB6 and PB3 to PB0
respectively (description of multiplexed functions are abbreviated here).
When a pin function is general output, if a value is written to PBDRH or PBDRL, the value is
output directly from the pin, and if PBDRH or PBDRL is read, the register value is returned
directly regardless of the pin state.
When a pin function is general input, if PBDRH or PBDRL is read, the pin state, not the register
value, is returned directly. If a value is written to PBDRH or PBDRL, although that value is
written into PBDRH or PBDRL, it does not affect the pin state. Table 24.4 summarizes read/write
operations of port B data register.
Page 1310 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBDRH (SH7243 and SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
• PBDRH (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
PB19
DR
PB18
DR
PB17
DR
PB16
DR
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15 to 4
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
PB19DR
0
R/W
2
PB18DR
0
R/W
1
PB17DR
0
R/W
0
PB16DR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
See table 24.4.
Page 1311 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBDRL (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
PB12
DR
PB11
DR
-
-
PB8
DR
PB7
DR
PB6
DR
-
-
-
-
PB1
DR
PB0
DR
Initial value:
R/W:
0
R
0
R
0
R
0
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12
PB12DR
0
R/W
11
PB11DR
0
R/W
10, 9
—
All 0
R
See table 24.4.
Reserved
These bits are always read as 0. The write value should
always be 0.
8
PB8DR
0
R/W
7
PB7DR
0
R/W
6
PB6DR
0
R/W
5 to 2
—
All 0
R
See table 24.4.
Reserved
These bits are always read as 0. The write value should
always be 0.
1
PB1DR
0
R/W
0
PB0DR
0
R/W
Page 1312 of 1778
See table 24.4.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBDRL (SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
PB12
DR
PB11
DR
PB10
DR
PB9
DR
PB8
DR
PB7
DR
PB6
DR
-
-
PB3
DR
PB2
DR
PB1
DR
PB0
DR
Initial value:
R/W:
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12
PB12DR
0
R/W
11
PB11DR
0
R/W
10
PB10DR
0
R/W
9
PB9DR
0
R/W
8
PB8DR
0
R/W
7
PB7DR
0
R/W
6
PB6DR
0
R/W
5, 4
—
All 0
R
See table 24.4.
Reserved
These bits are always read as 0. The write value should
always be 0.
3
PB3DR
0
R
2
PB2DR
0
R
These bits are always read as 0. The write value should
always be 0.
1
PB1DR
0
R/W
See table 24.4.
0
PB0DR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1313 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBDRL (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PB15
DR
PB14
DR
PB13
DR
PB12
DR
PB11
DR
PB10
DR
PB9
DR
PB8
DR
PB7
DR
PB6
DR
-
-
PB3
DR
PB2
DR
PB1
DR
PB0
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PB15DR
0
R/W
See table 24.4.
14
PB14DR
0
R/W
13
PB13DR
0
R/W
12
PB12DR
0
R/W
11
PB11DR
0
R/W
10
PB10DR
0
R/W
9
PB9DR
0
R/W
8
PB8DR
0
R/W
7
PB7DR
0
R/W
6
PB6DR
0
R/W
5, 4
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
PB3DR
0
R
2
PB2DR
0
R
1
PB1DR
0
R/W
0
PB0DR
0
R/W
Page 1314 of 1778
These bits are always read as 0. The write value should
always be 0.
See table 24.4.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Table 24.4 Port B Data Registers H and L (PBDRH and PBDRL) Read/Write Operations
• PBDRH bits 3 to 0 and PBDRL bits 15 to 6 and 3 to 0
PBDRH,
PBDRL
Pin Function
Read
Write
0
General input
Pin state
Can write to PBDRH or PBDRL, but it has no
effect on pin state.
Other than
general input
Pin state
Can write to PBDRH or PBDRL, but it has no
effect on pin state.
General output
PBDRH/PBDRL The value written is output from the pin.
value
Other than
general output
PBDRH/PBDRL Can write to PBDRH or PBDRL, but it has no
value
effect on pin state.
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1315 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.2.3
Port B Port Registers H and L (PBPRH and PBPRL)
PBPRH and PBPRL are 16-bit read-only registers, which always return the states of the pins
regardless of the PFC setting. In SH7243, bits PB12PR to PB11PR, PB8PR to PB6PR, PB1PR and
PB0PR correspond to pins PB12 to PB11, PB8 to PB6, PB1PR and PB0PR respectively
(description of multiplexed functions are abbreviated here). In SH7285, bits PB12PR to PB6PR,
PB3PR to PB0PR correspond to pins PB12 to PB6, PB3 to PB0 respectively (description of
multiplexed functions are abbreviated here). In SH7286, bits PB19PR to PB6PR and PB3PR to
PB0PR correspond to pins PB19 to PB6 and PB3 to PB0 respectively (description of multiplexed
functions are abbreviated here).
• PBPRH (SH7243 and SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
• PBPRH (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
PB19
PR
PB18
PR
PB17
PR
PB16
PR
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 4
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
3
PB19PR
Pin state R
2
PB18PR
Pin state R
1
PB17PR
Pin state R
0
PB16PR
Pin state R
Page 1316 of 1778
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBPRL (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
PB12
PR
PB11
PR
-
-
PB8
PR
PB7
PR
PB6
PR
-
-
-
-
PB1
PR
PB0
PR
Initial value:
R/W:
0
R
0
R
0
R
*
R
*
R
0
R
0
R
*
R
*
R
*
R
0
R
0
R
0
R
0
R
*
R
*
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
12
PB12PR
Pin state R
11
PB11PR
Pin state R
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
10, 9
—
All 0
Reserved
R
These bits are always read as 0 and cannot be
modified.
8
PB8PR
Pin state R
7
PB7PR
Pin state R
6
PB6PR
Pin state R
5 to 2
—
All 0
R
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
1
PB1PR
Pin state R
0
PB0PR
Pin state R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Page 1317 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBPRL (SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
PB12
PR
PB11
PR
PB10
PR
PB9
PR
PB8
PR
PB7
PR
PB6
PR
-
-
PB3
PR
PB2
PR
PB1
PR
PB0
PR
Initial value:
R/W:
0
R
0
R
0
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
0
R
0
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 13
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
12
PB12PR
Pin state R
11
PB11PR
Pin state R
10
PB10PR
Pin state R
9
PB9PR
Pin state R
8
PB8PR
Pin state R
7
PB7PR
Pin state R
6
PB6PR
Pin state R
5, 4
—
All 0
R
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
3
PB3PR
Pin state R
2
PB2PR
Pin state R
1
PB1PR
Pin state R
0
PB0PR
Pin state R
Page 1318 of 1778
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PBPRL (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PB15
PR
PB14
PR
PB13
PR
PB12
PR
PB11
PR
PB10
PR
PB9
PR
PB8
PR
PB7
PR
PB6
PR
-
-
PB3
PR
PB2
PR
PB1
PR
PB0
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
0
R
0
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PB15PR
Pin state R
14
PB14PR
Pin state R
13
PB13PR
Pin state R
12
PB12PR
Pin state R
11
PB11PR
Pin state R
10
PB10PR
Pin state R
9
PB9PR
Pin state R
8
PB8PR
Pin state R
7
PB7PR
Pin state R
6
PB6PR
Pin state R
5, 4
—
All 0
R/W
R
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
These bits are always read as 0 and cannot be
modified.
3
PB3PR
Pin state R
2
PB2PR
Pin state R
1
PB1PR
Pin state R
0
PB0PR
Pin state R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Page 1319 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.3
Port C
Port C of SH7243 is an I/O port with 16 pins shown in figure 24.7.
PC15 (I/O) / A15 (output) / IRQ2 (input)
PC14 (I/O) / A14 (output) / IRQ1 (input)
PC13 (I/O) / A13 (output) / IRQ0 (input)
PC12 (I/O) / A12 (output)
PC11 (I/O) / A11 (output)
PC10 (I/O) / A10 (output)
PC9 (I/O) / A9 (output)
Port C
PC8 (I/O) / A8 (output)
PC7 (I/O) / A7 (output)
PC6 (I/O) / A6 (output)
PC5 (I/O) / A5 (output)
PC4 (I/O) / A4 (output) / TRST (input)
PC3 (I/O) / A3 (output) / TMS (input)
PC2 (I/O) / A2 (output) / TCK (input)
PC1 (I/O) / A1 (output) / TDO (output)
PC0 (I/O) / A0 (output) / POE0 (input) / TDI (input)
Figure 24.7 Port C (SH7243)
Page 1320 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Port C of SH7285 and SH7286 are I/O ports with 16 pins shown in figure 24.8.
PC15 (I/O) / A15 (output) / IRQ2 (input)
PC14 (I/O) / A14 (output) / IRQ1 (input)
PC13 (I/O) / A13 (output) / IRQ0 (input)
PC12 (I/O) / A12 (output)
PC11 (I/O) / A11 (output)
PC10 (I/O) / A10 (output)
PC9 (I/O) / A9 (output)
PC8 (I/O) / A8 (output)
Port C
PC7 (I/O) / A7 (output)
PC6 (I/O) / A6 (output)
PC5 (I/O) / A5 (output)
PC4 (I/O) / A4 (output)
PC3 (I/O) / A3 (output)
PC2 (I/O) / A2 (output)
PC1 (I/O) / A1 (output)
PC0 (I/O) / A0 (output) / POE0 (input)
Figure 24.8 Port C (SH7285 and SH7286)
24.3.1
Register Descriptions
Port C is a 16-bit I/O port in SH7243, SH7285 and SH7286. Port C has the following registers.
See section 30, List of Registers for details on the register address and states in each operating
mode.
Table 24.5 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port C data register L
PCDRL
R/W
H'0000
H'FFFE3902
8, 16
Port C port register L
PCPRL
R
—
H'FFFE391E
8, 16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1321 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.3.2
Port C Data Register L (PCDRL)
PCDRL is a 16-bit readable/writable register that store port C data. In SH7243, SH7285 and
SH7286, bits PC15DR to PC0DR, correspond to pins PC15 to PC0 (description of multiplexed
functions are abbreviated) respectively.
When a pin function is general output, if a value is written to PBDRL, the value is output directly
from the pin, and if PCDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PCDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PCDRL, although that value is written into PCDRL, it
does not affect the pin state. Table 24.6 summarizes read/write operations of port C data register.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC15
DR
PC14
DR
PC13
DR
PC12
DR
PC11
DR
PC10
DR
PC9
DR
PC8
DR
PC7
DR
PC6
DR
PC5
DR
PC4
DR
PC3
DR
PC2
DR
PC1
DR
PC0
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PC15DR
0
R/W
See table 24.6.
14
PC14DR
0
R/W
13
PC13DR
0
R/W
12
PC12DR
0
R/W
11
PC11DR
0
R/W
10
PC10DR
0
R/W
9
PC9DR
0
R/W
8
PC8DR
0
R/W
7
PC7DR
0
R/W
6
PC6DR
0
R/W
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
Page 1322 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Table 24.6 Port C Data Register L (PCDRL) Read/Write Operations
• PCDRL bits 15 to 0
PCIORL
Pin Function
Read
Write
0
General input
Pin state
Can write to PCDRL, but it has no effect on pin
state.
Other than
general input
Pin state
Can write to PCDRL, but it has no effect on pin
state.
General output
PCDRL value
The value written is output from the pin.
Other than
general output
PCDRL value
Can write to PCDRL, but it has no effect on pin
state.
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1323 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.3.3
Port C Port Register L (PCPRL)
PCPRL is a 16-bit read-only register, which always return the states of the pins regardless of the
PFC setting. In SH7243, SH7285 and SH7286, bits PC15PR to PC0PR correspond to pins PC15 to
PC0 respectively (description of multiplexed functions are abbreviated here).
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC15
PR
PC14
PR
PC13
PR
PC12
PR
PC11
PR
PC10
PR
PC9
PR
PC8
PR
PC7
PR
PC6
PR
PC5
PR
PC4
PR
PC3
PR
PC2
PR
PC1
PR
PC0
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PC15PR
Pin state R
14
PC14PR
Pin state R
13
PC13PR
Pin state R
12
PC12PR
Pin state R
11
PC11PR
Pin state R
10
PC10PR
Pin state R
9
PC9PR
Pin state R
8
PC8PR
Pin state R
7
PC7PR
Pin state R
6
PC6PR
Pin state R
5
PC5PR
Pin state R
4
PC4PR
Pin state R
3
PC3PR
Pin state R
2
PC2PR
Pin state R
1
PC1PR
Pin state R
0
PC0PR
Pin state R
Page 1324 of 1778
R/W
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
24.4
Section 24 I/O Ports
Port D
Port D of SH7243 is an I/O port with 16 pins shown in figure 24.9.
PD15 (I/O) / D15 (I/O) / TIOC4DS (I/O)
PD14 (I/O) / D14 (I/O) / TIOC4CS (I/O)
PD13 (I/O) / D13 (I/O) / TIOC4BS (I/O)
PD12 (I/O) / D12 (I/O) / TIOC4AS (I/O)
PD11 (I/O) / D11 (I/O) / TIOC3DS (I/O)
PD10 (I/O) / D10 (I/O) / TIOC3BS (I/O)
PD9 (I/O) / D9 (I/O) / TIOC3CS (I/O)
Port D
PD8 (I/O) / D8 (I/O) / TIOC3AS (I/O) / AUDCK (output)
PD7 (I/O) / D7 (I/O) / TIC5WS (input) / AUDATA3 (output)
PD6 (I/O) / D6 (I/O) / TIC5VS (input) / AUDATA2 (output)
PD5 (I/O) / D5 (I/O) / TIC5US (input) / AUDATA1 (output)
PD4 (I/O) / D4 (I/O) / TIC5W (input) / AUDATA0 (output)
PD3 (I/O) / D3 (I/O) / TIC5V (input) / AUDSYNC (output)
PD2 (I/O) / D2 (I/O) / TIC5U (input)
PD1 (I/O) / D1 (I/O)
PD0 (I/O) / D0 (I/O)
Figure 24.9 Port D (SH7243)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1325 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Port D of SH7285 is an I/O port with 31 pins shown in figure 24.10.
PD31 (I/O) / TIOC3AS (I/O) / ADTRG (input)
PD30 (I/O) / TIOC3CS (I/O) / IRQOUT (output) / REFOUT (output)
PD29 (I/O) / TIOC3BS (I/O)
PD28 (I/O) / TIOC3DS (I/O)
PD27 (I/O) / TIOC4AS (I/O) / DACK0 (output)
PD26 (I/O) / TIOC4BS (I/O) / DACK1 (output)
PD25 (I/O) / TIOC4CS (I/O) / DREQ1 (input)
PD24 (I/O) / DREQ0 (input) / TIOC4DS (I/O) / AUDCK (output)
PD22 (I/O) / IRQ6 (input) / TIC5US (input) / RXD4 (input) / AUDSYNC (output)
PD21 (I/O) / IRQ5 (input) / TIC5VS (input) / TXD4 (output)
PD20 (I/O) / IRQ4 (input) / TIC5WS (input) / SCK4 (I/O) / POE8 (input)
PD19 (I/O) / IRQ3 (input) / POE7 (input) / RXD3 (input) / CS0 (output) / AUDATA3 (output)
PD18 (I/O) / IRQ2 (input) / POE6 (input) / TXD3 (output) / CS1 (output) / AUDATA2 (output)
PD17 (I/O) / IRQ1 (input) / POE5 (input) / SCK3 (I/O) / CS2 (output) / AUDATA1 (output)
PD16 (I/O) / IRQ0 (input) / CS3 (output) / AUDATA0 (output)
Port D
PD15 (I/O) / D15 (I/O) / TIOC4DS (I/O)
PD14 (I/O) / D14 (I/O) / TIOC4CS (I/O)
PD13 (I/O) / D13 (I/O) / TIOC4BS (I/O)
PD12 (I/O) / D12 (I/O) / TIOC4AS (I/O)
PD11 (I/O) / D11 (I/O) / TIOC3DS (I/O)
PD10 (I/O) / D10 (I/O) / TIOC3BS (I/O)
PD9 (I/O) / D9 (I/O) / TIOC3CS (I/O)
PD8 (I/O) / D8 (I/O) / TIOC3AS (I/O)
PD7 (I/O) / D7 (I/O) / TIC5WS (input)
PD6 (I/O) / D6 (I/O) / TIC5VS (input)
PD5 (I/O) / D5 (I/O) / TIC5US (input)
PD4 (I/O) / D4 (I/O) / TIC5W (input)
PD3 (I/O) / D3 (I/O) / TIC5V (input)
PD2 (I/O) / D2 (I/O) / TIC5U (input)
PD1 (I/O) / D1 (I/O)
PD0 (I/O) / D0 (I/O)
Figure 24.10 Port D (SH7285)
Page 1326 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Port D of SH7286 is an I/O port with 32 pins shown in figure 24.11.
PD31 (I/O) / D31 (I/O) / TIOC3AS (I/O) / ADTRG (input)
PD30 (I/O) / D30 (I/O) / TIOC3CS (I/O) / IRQOUT (output) / REFOUT (output)
PD29 (I/O) / D29 (I/O) / TIOC3BS (I/O)
PD28 (I/O) / D28 (I/O) / TIOC3DS (I/O)
PD27 (I/O) / D27 (I/O) / TIOC4AS (I/O) / DACK0 (output)
PD26 (I/O) / D26 (I/O) / TIOC4BS (I/O) / DACK1 (output)
PD25 (I/O) / D25 (I/O) / TIOC4CS (I/O) / DREQ1 (input)
PD24 (I/O) / D24 (I/O) / DREQ0 (input) / TIOC4DS (I/O) / AUDCK (output)
PD23 (I/O) / D23 (I/O)
PD22 (I/O) / D22 (I/O) / IRQ6 (input) / TIC5US (input) / RXD4 (input) / AUDSYNC (output)
PD21 (I/O) / D21 (I/O) / IRQ5 (input) / TIC5VS (input) / TXD4 (output)
PD20 (I/O) / D20 (I/O) / IRQ4 (input) / TIC5WS (input) / SCK4 (I/O) / POE8 (input)
PD19 (I/O) / D19 (I/O) / IRQ3 (input) / POE7 (input) / RXD3 (input) / CS0 (output) / AUDATA3 (output)
PD18 (I/O) /D18 (I/O) / IRQ2 (input) / POE6 (input) / TXD3 (output) / CS1 (output) / AUDATA2 (output)
PD17 (I/O) /D17 (I/O) / IRQ1 (input) / POE5 (input) / SCK3 (I/O) / CS2 (output) / AUDATA1 (output)
PD16 (I/O) /D16 (I/O) / IRQ0 (input) / CS3 (output) / AUDATA0 (output)
Port D
PD15 (I/O) / D15 (I/O) / TIOC4DS (I/O)
PD14 (I/O) / D14 (I/O) / TIOC4CS (I/O)
PD13 (I/O) / D13 (I/O) / TIOC4BS (I/O)
PD12 (I/O) / D12 (I/O) / TIOC4AS (I/O)
PD11 (I/O) / D11 (I/O) / TIOC3DS (I/O)
PD10 (I/O) / D10 (I/O) / TIOC3BS (I/O)
PD9 (I/O) / D9 (I/O) / TIOC3CS (I/O)
PD8 (I/O) / D8 (I/O) / TIOC3AS (I/O)
PD7 (I/O) / D7 (I/O) / TIC5WS (input)
PD6 (I/O) / D6 (I/O) / TIC5VS (input)
PD5 (I/O) / D5 (I/O) / TIC5US (input)
PD4 (I/O) / D4 (I/O) / TIC5W (input)
PD3 (I/O) / D3 (I/O) / TIC5V (input)
PD2 (I/O) / D2 (I/O) / TIC5U (input)
PD1 (I/O) / D1 (I/O)
PD0 (I/O) / D0 (I/O)
Figure 24.11 Port D (SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1327 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.4.1
Register Descriptions
Port D is a 16-bit I/O port in SH7243, 31-bit I/O port in SH7285 and 32-bit I/O port in SH7286.
Port D has the following registers. See section 30, List of Registers for details on the register
address and states in each operating mode.
Table 24.7 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port D data register H
PDDRH
R/W
H'0000
H'FFFE3980
8, 16, 32
Port D data register L
PDDRL
R/W
H'0000
H'FFFE3982
8, 16
Port D port register H
PDPRH
R
H'xxxx
H'FFFE399C
8, 16, 32
Port D port register L
PDPRL
R
H'xxxx
H'FFFE399E
8, 16
24.4.2
Port D Data Registers H and L (PDDRH and PDDRL)
PDDRH and PDDRL are 16-bit readable/writable registers that store port D data. In SH7243, bits
PD15DR, to PD0DR correspond to pins PD15 to PD0 respectively (description of multiplexed
functions are abbreviated here). In SH7285, bits PD31DR to PD24DR and PD22DR to PD0DR
correspond to pins PD31 to PD24, and PD22 to PD0 respectively (description of multiplexed
functions are abbreviated here). In SH7286, bits PD31DR to PD0DR correspond to pins PD31 to
PD0 respectively (description of multiplexed functions are abbreviated here).
When a pin function is general output, if a value is written to PDDRH or PDDRL, the value is
output directly from the pin, and if PDDRH or PDDRL is read, the register value is returned
directly regardless of the pin state.
When a pin function is general input, if PDDRH or PDDRL is read, the pin state, not the register
value, is returned directly. If a value is written to PDDRH or PDDRL, although that value is
written into PDDRH or PDDRL, it does not affect the pin state. Table 24.8 summarizes read/write
operations of port D data register.
Page 1328 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PDDRH (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
• PDDRH (SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD31
DR
PD30
DR
PD29
DR
PD28
DR
PD27
DR
PD26
DR
PD25
DR
PD24
DR
-
PD22
DR
PD21
DR
PD20
DR
PD19
DR
PD18
DR
PD17
DR
PD16
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD31DR
0
R/W
See table 24.8.
14
PD30DR
0
R/W
13
PD29DR
0
R/W
12
PD28DR
0
R/W
11
PD27DR
0
R/W
10
PD26DR
0
R/W
9
PD25DR
0
R/W
8
PD24DR
0
R/W
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1329 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
6
PD22DR
0
R/W
See table 24.8.
5
PD21DR
0
R/W
4
PD20DR
0
R/W
3
PD19DR
0
R/W
2
PD18DR
0
R/W
1
PD17DR
0
R/W
0
PD16DR
0
R/W
• PDDRH (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD31
DR
PD30
DR
PD29
DR
PD28
DR
PD27
DR
PD26
DR
PD25
DR
PD24
DR
PD23
DR
PD22
DR
PD21
DR
PD20
DR
PD19
DR
PD18
DR
PD17
DR
PD16
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD31DR
0
R/W
See table 24.8.
14
PD30DR
0
R/W
13
PD29DR
0
R/W
12
PD28DR
0
R/W
11
PD27DR
0
R/W
10
PD26DR
0
R/W
9
PD25DR
0
R/W
8
PD24DR
0
R/W
7
PD23DR
0
R/W
6
PD22DR
0
R/W
5
PD21DR
0
R/W
4
PD20DR
0
R/W
3
PD19DR
0
R/W
2
PD18DR
0
R/W
1
PD17DR
0
R/W
0
PD16DR
0
R/W
Page 1330 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PDDRL (SH7243, SH7285 and SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
DR
PD14
DR
PD13
DR
PD12
DR
PD11
DR
PD10
DR
PD9
DR
PD8
DR
PD7
DR
PD6
DR
PD5
DR
PD4
DR
PD3
DR
PD2
DR
PD1
DR
PD0
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PD15DR
0
R/W
See table 24.8.
14
PD14DR
0
R/W
13
PD13DR
0
R/W
12
PD12DR
0
R/W
11
PD11DR
0
R/W
10
PD10DR
0
R/W
9
PD9DR
0
R/W
8
PD8DR
0
R/W
7
PD7DR
0
R/W
6
PD6DR
0
R/W
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1331 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Table 24.8 Port D Data Register L (PBDRL) Read/Write Operations
• PDDRL bits 15 to 0
PDDRL
Pin Function
Read
Write
0
General input
Pin state
Can write to PDDRL, but it has no effect on pin
state.
Other than
general input
Pin state
Can write to PDDRL, but it has no effect on pin
state.
General output
PDDRL value
The value written is output from the pin.
Other than
general output
PDDRL value
Can write to PDDRL, but it has no effect on pin
state.
1
24.4.3
Port D Port Registers H and L (PDPRH and PDPRL)
PDPRH and PDPRL are 16-bit read-only registers, which return the states of the pins. However,
when the SCIF function is selected for PD18, the TE bit in SCSCR is 0, and the SPB2IO bit in
SCSPTR is 0, the states of the corresponding pins cannot be read out. In SH7243, bits PD15PR to
PD0PR correspond to pins PD15 to PD0 respectively (description of multiplexed functions are
abbreviated here). In SH7285, bits PD31PR to PD24PR, and PD22PR to PD0PR correspond to
pins PD31 to PD24 and PD22 to PD0 respectively (description of multiplexed functions are
abbreviated here). In SH7286, bits PD31PR to PD0PR correspond to pins PD31 to PD0
respectively (description of multiplexed functions are abbreviated here).
• PDPRH (SH7243)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 0
—
All 0
R
Reserved
These bits are always read as 0 and cannot be
modified.
Page 1332 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PDPRH (SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD31
PR
PD30
PR
PD29
PR
PD28
PR
PD27
PR
PD26
PR
PD25
PR
PD24
PR
-
PD22
PR
PD21
PR
PD20
PR
PD19
PR
PD18
PR
PD17
PR
PD16
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
0
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PD31PR
Pin state R
14
PD30PR
Pin state R
13
PD29PR
Pin state R
12
PD28PR
Pin state R
11
PD27PR
Pin state R
10
PD26PR
Pin state R
9
PD25PR
Pin state R
8
PD24PR
Pin state R
7
—
0
R/W
R
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Reserved
This bit is always read as 0. The write value should
always be 0.
6
PD22PR
Pin state R
5
PD21PR
Pin state R
4
PD20PR
Pin state R
3
PD19PR
Pin state R
2
PD18PR
Pin state R
1
PD17PR
Pin state R
0
PD16PR
Pin state R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Page 1333 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PDPRH (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD31
PR
PD30
PR
PD29
PR
PD28
PR
PD27
PR
PD26
PR
PD25
PR
PD24
PR
PD23
PR
PD22
PR
PD21
PR
PD20
PR
PD19
PR
PD18
PR
PD17
PR
PD16
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PD31PR
Pin state R
14
PD30PR
Pin state R
13
PD29PR
Pin state R
12
PD28PR
Pin state R
11
PD27PR
Pin state R
10
PD26PR
Pin state R
9
PD25PR
Pin state R
8
PD24PR
Pin state R
7
PD23PR
Pin state R
6
PD22PR
Pin state R
5
PD21PR
Pin state R
4
PD20PR
Pin state R
3
PD19PR
Pin state R
2
PD18PR
Pin state R
1
PD17PR
Pin state R
0
PD16PR
Pin state R
Page 1334 of 1778
R/W
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PDPRL (SH7243, SH7285 and SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD15
PR
PD14
PR
PD13
PR
PD12
PR
PD11
PR
PD10
PR
PD9
PR
PD8
PR
PD7
PR
PD6
PR
PD5
PR
PD4
PR
PD3
PR
PD2
PR
PD1
PR
PD0
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PD15PR
Pin state R
14
PD14PR
Pin state R
13
PD13PR
Pin state R
12
PD12PR
Pin state R
11
PD11PR
Pin state R
10
PD10PR
Pin state R
9
PD9PR
Pin state R
8
PD8PR
Pin state R
7
PD7PR
Pin state R
6
PD6PR
Pin state R
5
PD5PR
Pin state R
4
PD4PR
Pin state R
3
PD3PR
Pin state R
2
PD2PR
Pin state R
1
PD1PR
Pin state R
0
PD0PR
Pin state R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
R/W
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
Page 1335 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.5
Port E
Port D of SH7243, SH7285 and SH7286 is an I/O port with 16 pins shown in figures 24.12, 24.13
and 24.14.
PE15 (I/O) / DACK1 (output) / TIOC4D (I/O) / IRQOUT (output) / REFOUT (output)
PE14 (I/O) / DACK0 (output) / TIOC4C (I/O)
PE13 (I/O) / TIOC4B (I/O) / MRES (input)
PE12 (I/O) / TIOC4A (I/O)
PE11 (I/O) / TIOC3D (I/O)
PE10 (I/O) / TIOC3C (I/O) / TXD2 (output)
PE9 (I/O) / TIOC3B (I/O)
Port E
PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O)
PE7 (I/O) / TIOC2B (I/O) / RXD2 (input) / BS (output) / UBCTRG (output)
PE6 (I/O) / TIOC2A (I/O) / TIOC3DS (I/O) / SCK3 (I/O)
PE5 (I/O) / TIOC1B (I/O) / TIOC3BS (I/O) / TXD3 (output)
PE4 (I/O) / TIOC1A (I/O) / RXD3 (input)
PE3 (I/O) / TIOC0D (I/O) / TIOC4DS (I/O) / TEND1 (output)
PE2 (I/O) / TIOC0C (I/O) / TIOC4CS (I/O) / DREQ1 (input)
PE1 (I/O) / TIOC0B (I/O) / TIOC4BS (I/O) / TEND0 (output)
PE0 (I/O) / TIOC0A (I/O) / TIOC4AS (I/O) / DREQ0 (input)
Figure 24.12 Port E (SH7243)
Page 1336 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
PE15 (I/O) / DACK1 (output) / TIOC4D (I/O) / IRQOUT (output) / REFOUT (output)
PE14 (I/O) / DACK0 (output) / TIOC4C (I/O) / AH (output)
PE13 (I/O) / TIOC4B (I/O) / MRES (input)
PE12 (I/O) / TIOC4A (I/O)
PE11 (I/O) / TIOC3D (I/O)
PE10 (I/O) / TIOC3C (I/O) / TXD2 (output)
PE9 (I/O) / TIOC3B (I/O)
Port E
PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O)
PE7 (I/O) / TIOC2B (I/O) / RXD2 (input) / BS (output) / UBCTRG (output)
PE6 (I/O) / TIOC2A (I/O) / TIOC3DS (I/O) / SCK3 (I/O)
PE5 (I/O) / TIOC1B (I/O) / TIOC3BS (I/O) / TXD3 (output)
PE4 (I/O) / TIOC1A (I/O) / RXD3 (input)
PE3 (I/O) / TIOC0D (I/O) / TIOC4DS (I/O) / TEND1 (output)
PE2 (I/O) / TIOC0C (I/O) / TIOC4CS (I/O) / DREQ1 (input)
PE1 (I/O) / TIOC0B (I/O) / TIOC4BS (I/O) / TEND0 (output)
PE0 (I/O) / TIOC0A (I/O) / TIOC4AS (I/O) / DREQ0 (input)
Figure 24.13 Port E (SH7285)
PE15 (I/O) / DACK1 (output) / TIOC4D (I/O) / IRQOUT (output) / REFOUT (output)
PE14 (I/O) / DACK0 (output) / TIOC4C (I/O) / AH (output)
PE13 (I/O) / TIOC4B (I/O) / MRES (input)
PE12 (I/O) / TIOC4A (I/O)
PE11 (I/O) / TIOC3D (I/O)
PE10 (I/O) / TIOC3C (I/O) / TXD2 (output)
PE9 (I/O) / TIOC3B (I/O) / FRAME (output)
PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O)
Port E
PE7 (I/O) / TIOC2B (I/O) / RXD2 (input) / BS (output) / UBCTRG (output)
PE6 (I/O) / TIOC2A (I/O) / TIOC3DS (I/O) / SCK3 (I/O)
PE5 (I/O) / TIOC1B (I/O) / TIOC3BS (I/O) / TXD3 (output)
PE4 (I/O) / TIOC1A (I/O) / RXD3 (input)
PE3 (I/O) / TIOC0D (I/O) / TIOC4DS (I/O) / TEND1 (output)
PE2 (I/O) / TIOC0C (I/O) / TIOC4CS (I/O) / DREQ1 (input)
PE1 (I/O) / TIOC0B (I/O) / TIOC4BS (I/O) / TEND0 (output)
PE0 (I/O) / TIOC0A (I/O) / TIOC4AS (I/O) / DREQ0 (input)
Figure 24.14 Port E (SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1337 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.5.1
Register Descriptions
Port E is a 16-bit I/O port in SH7243, SH7285 and SH7286. Port E has the following registers. See
section 30, List of Registers for details on the register address and states in each operating mode.
Table 24.9 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port E data register L
PEDRL
R/W
H'0000
H'FFFE3A02
8, 16
Port E port register L
PEPRL
R
—
H'FFFE3A1E
8, 16
24.5.2
Port E Data Register L (PEDRL)
PEDRL is a 16-bit readable/writable register that stores port E data. In SH7243, SH7285 and
SH7286, bits PE15DR to PE0DR, correspond to pins PE15 to PE0 respectively (description of
multiplexed functions are abbreviated here).
When a pin function is general output, if a value is written to PEDRL, the value is output directly
from the pin, and if PEDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PEDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PEDRL, although that value is written into PEDRL, it
does not affect the pin state. Table 24.10 summarizes read/write operations of port E data register.
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PE15
DR
PE14
DR
PE13
DR
PE12
DR
PE11
DR
PE10
DR
PE9
DR
PE8
DR
PE7
DR
PE6
DR
PE5
DR
PE4
DR
PE3
DR
PE2
DR
PE1
DR
PE0
DR
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
PE15DR
0
R/W
See table 24.10.
14
PE14DR
0
R/W
13
PE13DR
0
R/W
12
PE12DR
0
R/W
Page 1338 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
11
PE11DR
0
R/W
See table 24.10.
10
PE10DR
0
R/W
9
PE9DR
0
R/W
8
PE8DR
0
R/W
7
PE7DR
0
R/W
6
PE6DR
0
R/W
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
Table 24.10 Port E Data Register L (PEDRL) Read/Write Operations
• PEDRL bits 15 to 0
PEIORL
Pin Function
Read
Write
0
General input
Pin state
Can write to PEDRL, but it has no effect on pin
state.
Other than
general input
Pin state
Can write to PEDRL, but it has no effect on pin
state.
General output
PEDRL value
The value written is output from the pin.
Other than
general output
PEDRL value
Can write to PEDRL, but it has no effect on pin
state.
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1339 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.5.3
Port E Port Register L (PEPRL)
PEPRL is a 16-bit read-only register, which always return the states of the pins regardless of the
PFC setting. In SH7243, SH7285 and SH7286, bits PE15PR to PE0PR correspond to pins PE15 to
PE0 respectively (description of multiplexed functions are abbreviated here).
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PE15
PR
PE14
PR
PE13
PR
PE12
PR
PE11
PR
PE10
PR
PE9
PR
PE8
PR
PE7
PR
PE6
PR
PE5
PR
PE4
PR
PE3
PR
PE2
PR
PE1
PR
PE0
PR
Initial value:
R/W:
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
15
PE15PR
Pin state R
14
PE14PR
Pin state R
13
PE13PR
Pin state R
12
PE12PR
Pin state R
11
PE11PR
Pin state R
10
PE10PR
Pin state R
9
PE9PR
Pin state R
8
PE8PR
Pin state R
7
PE7PR
Pin state R
6
PE6PR
Pin state R
5
PE5PR
Pin state R
4
PE4PR
Pin state R
3
PE3PR
Pin state R
2
PE2PR
Pin state R
1
PE1PR
Pin state R
0
PE0PR
Pin state R
Page 1340 of 1778
R/W
Description
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
24.6
Section 24 I/O Ports
Port F
Port F in SH7243 and SH7285 is an I/O port with 8 pins shown in figure 24.15.
PF7 (input) / AN7 (input)
PF6 (input) / AN6 (input)
PF5 (input) / AN5 (input)
PF4 (input) / AN4 (input)
Port F
PF3 (input) / AN3 (input)
PF2 (input) / AN2 (input)
PF1 (input) / AN1 (input)
PF0 (input) / AN0 (input)
Figure 24.15 Port F (SH7243 and SH7285)
Port F in SH7286 is an I/O port with 12 pins shown in figure 24.16.
PF11 (input) / AN11 (input)
PF10 (input) / AN10 (input)
PF9 (input) / AN9 (input)
PF8 (input) / AN8 (input)
PF7 (input) / AN7 (input)
PF6 (input) / AN6 (input)
Port F
PF5 (input) / AN5 (input)
PF4 (input) / AN4 (input)
PF3 (input) / AN3 (input)
PF2 (input) / AN2 (input)
PF1 (input) / AN1 (input)
PF0 (input) / AN0 (input)
Figure 24.16 Port F (SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1341 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
24.6.1
Register Descriptions
Port F is an 8-bit I/O port in SH7243 and SH7285, and 12-bit I/O port in SH7286. Port F has the
following registers. See section 30, List of Registers for details on the register address and states
in each operating mode.
Table 24.11 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Port F data register L
PFDRL
R
H'xxxx
H'FFFE3A82
8, 16
24.6.2
Port F Data Register L (PFDRL)
PFDRL is a 16-bit read-only register that stores port F data. In SH7243 and SH7285, bits PF7DR
to PF0DR, correspond to pins PF7 to PF0 (description of multiplexed functions are abbreviated
here) and in SH7286, bits PF11DR to PF0DR correspond to pins PF11 to PF0 respectively
(description of multiplexed functions are abbreviated here).
Even if a value is written to PFDR, the value is not written into PFDR, and it does not affect the
pin state. If PFDR is read, the pin state, not the register value, is returned directly. However, when
sampling the analog input of A/D converter, 1 is read. Table 24.12 and 24.13 summarize
read/write operations of port F data registers.
Page 1342 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PFDRL (SH7243 and SH7285)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PF7
DR
PF6
DR
PF5
DR
PF4
DR
PF3
DR
PF2
DR
PF1
DR
PF0
DR
Initial value:
R/W:
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
PF7DR
Pin state R
6
PF6DR
Pin state R
5
PF5DR
Pin state R
4
PF4DR
Pin state R
3
PF3DR
Pin state R
2
PF2DR
Pin state R
1
PF1DR
Pin state R
0
PF0DR
Pin state R
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
See table 24.12.
Page 1343 of 1778
SH7280 Group, SH7243 Group
Section 24 I/O Ports
• PFDRL (SH7286)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
PF11
DR
PF10
DR
PF9
DR
PF8
DR
PF7
DR
PF6
DR
PF5
DR
PF4
DR
PF3
DR
PF2
DR
PF1
DR
PF0
DR
Initial value:
R/W:
0
R
0
R
0
R
0
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
*
R
Bit
Bit Name
Initial
Value
R/W
Description
15 to 12
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
11
PF11DR
Pin state R
10
PF10DR
Pin state R
9
PF9DR
Pin state R
8
PF8DR
Pin state R
7
PF7DR
Pin state R
6
PF6DR
Pin state R
5
PF5DR
Pin state R
4
PF4DR
Pin state R
3
PF3DR
Pin state R
2
PF2DR
Pin state R
1
PF1DR
Pin state R
0
PF0DR
Pin state R
See table 24.13.
Table 24.12 Port F Data Register L (PFDRL) Read/Write Operations
• PFDRL bits 11 and 0
Pin Function
Read
Write
General input
Pin state
Ignored (no effect on pin state)
ANn input
1
Ignored (no effect on pin state)
Page 1344 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
24.7
Usage Notes
24.7.1
Handling of Unused Pins
Section 24 I/O Ports
Unused pins should be connected to Vcc or GND via resistors to fix high or low levels on the pins.
PF0 to PF11 should be connected to AVcc or AVss via resistors.
For handling of the NMI, USD+, USD−, EXTAL, XTAL, USBEXTAL, USBXTAL, WDTOVF,
TRST, TMS, TCK, TDO, and TDI pins, follow the instructions in the sections on the relevant
modules.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1345 of 1778
Section 24 I/O Ports
Page 1346 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Section 25 USB Function Module
25.1
Features
• Incorporates UDC (USB device controller) conforming to the USB standard
Automatic processing of USB protocol
Automatic processing of USB standard commands for endpoint 0 (some commands and
class/vendor commands require decoding and processing by firmware)
• Transfer speed: Full-speed
• Endpoint configuration
Transfer Type
Maximum
Packet Size
FIFO Buffer
Capacity
(Byte)
DMA/DTC
Transfer
EP0s
Setup
8
8
⎯
EP0i
Control IN
8
8
⎯
EP0o
Control OUT
8
8
⎯
Endpoint 1
EP1
Bulk OUT
64
128
Possible
Endpoint 2
EP2
Bulk IN
64
128
Possible
Endpoint 3
EP3
Interrupt
8
8
⎯
Endpoint
Name
Abbreviation
Endpoint 0
Configuration 1
Interface 0
Alternate setting 0
Endpoint 1
Endpoint 2
Endpoint 3
• Interrupt requests: generates various interrupt signals necessary for USB
transmission/reception
• Clock: External input (48 MHz)
Internal input (only when 12-MHz EXTAL is used)
• Power-down mode
Power consumption can be reduced by stopping UDC internal clock when USB cable is
disconnected
• Power mode: Self-powered
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1347 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.1.1
Block Diagram
Internal
peripheral bus
USB function module
Status
and control
registers
Interrupt request signals
USI0, USI1
DMA/DTC transfer request signals
USBRXI, USBTXI
USD+
UDC
To transceiver
USD–
FIFO
(288 bytes)
Clock (48 MHz)
[Legend]
UDC: USB device controller
Figure 25.1 Block Diagram of USB
Page 1348 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.2
Section 25 USB Function Module
Pin Configuration
Table 25.1 Pin Configuration and Functions
Pin Name
I/O
Function
DrVcc
Input
USB power supply (3.0 V to 3.6 V)*
DrVss
Input
USB ground (Connect to Vss)
VBUS
Input
USB cable connection monitor pin
USPND
Output
Transceiver suspend state output pin
USBEXTAL
Input
Connected to a 48-MHz resonator for USB
USBXTAL
Output
Connected to a 48-MHz resonator for USB
USD+
I/O
On-chip transceiver USD+ signal
USD–
I/O
On-chip transceiver USD– signal
PUPD (PB10)
Output
Pull-up control
Note:
*
For 3.0 V ≤ Vcc ≤ 3.6 V, DrVcc = Vcc or 3.0 V ≤ DrVcc ≤ 3.6 V.
For 3.6 V ≤ Vcc ≤ 5.5 V, DrVcc ≤ 3.6 V < Vcc.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1349 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3
Register Descriptions
The USB has the following registers.
Table 25.2 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access
Size
USB interrupt flag register 0
USBIFR0
R/W
H'10
H'FFFE7000
8
USB interrupt flag register 1
USBIFR1
R/W
H'00
H'FFFE7001
8
USBEP0i data register
USBEPDR0i
R/W
Undetermined
H'FFFE7002
8
USBEP0o data register
USBEPDR0o
R/W
Undetermined
H'FFFE7003
8
USB trigger register
USBTRG
W
H'00
H'FFFE7004
8
USB FIFO clear register
USBFCLR
W
H'00
H'FFFE7005
8
USBEP0o receive data size register USBEPSZ0o
R
H'00
H'FFFE7006
8
USBEP0s data register
USBEPDR0s
R
Undetermined
H'FFFE7007
8
USB data status register
USBDASTS
R
H'00
H'FFFE7008
8
USB interrupt select register 0
USBISR0
R/W
H'00
H'FFFE700A
8
USB endpoint stall register
USBEPSTL
R/W
H'00
H'FFFE700B
8
USB interrupt enable register 0
USBIER0
R/W
H'00
H'FFFE700C
8
USB interrupt enable register 1
USBIER1
R/W
H'00
H'FFFE700D
8
USBEP1 receive data size register
USBEPSZ1
R
H'00
H'FFFE700F
8
USB interrupt select register 1
USBISR1
R/W
H'07
H'FFFE7010
8
USB DMA transfer setting register
USBDMAR
R/W
H'00
H'FFFE7011
8
USBEP3 data register
USBEPDR3
W
Undetermined
H'FFFE7012
8
USBEP1 data register
USBEPDR1
R
Undetermined
H'FFFE7014
8, 16, 32
USBEP2 data register
USBEPDR2
W
Undetermined
H'FFFE7018
8, 16, 32
Page 1350 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.3.1
Section 25 USB Function Module
USB Interrupt Flag Register 0 (USBIFR0)
Together with USB interrupt flag register 1 (USBIFR1), USBIFR0 indicates interrupt status
information required by the application. When an interrupt occurs, the corresponding bit is set to 1
and an interrupt request is sent to the CPU according to the combination with USB interrupt
enable register 0 (USBIER0). Clearing is performed by writing 0 to the bit to be cleared, and 1 to
the other bits. However, EP1 FULL and EP2 EMPTY are status bits, and cannot be cleared.
USBIFR0 is initialized to H'10 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
BRST
EP1
FULL
EP2TR
0
R/W
0
R
0
R/W
4
3
2
1
0
EP2 SETUP
EP0oTS EP0iTR EP0iTS
EMPTY TS
1
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
BRST
0
R/W
Bus Reset
0
R/W
0
R/W
0
R/W
Set to 1 when the bus reset signal is detected on the
USB bus.
6
EP1FULL
0
R
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data normally from the host, and holds a value of 1 as
long as there is valid data in the FIFO buffer. EP1
FULL is a status bit, and cannot be cleared.
5
EP2TR
0
R/W
EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
4
EP2EMPTY 1
R
EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written. EP2 EMPTY is a status bit, and cannot be
cleared.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1351 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Bit
Bit Name
Initial
Value
R/W
Description
3
SETUPTS
0
R/W
Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives normally
a setup command requiring decoding on the
application side, and returns an ACK handshake to
the host.
2
EP0oTS
0
R/W
EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host normally, stores the data in the FIFO buffer,
and returns an ACK handshake to the host.
1
EP0iTR
0
R/W
EP0i Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
0
EP0iTS
0
R/W
EP0i Transmit Complete
This bit is set when data is transmitted to the host
from endpoint 0 and an ACK handshake is returned.
Page 1352 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.3.2
Section 25 USB Function Module
USB Interrupt Flag Register 1 (USBIFR1)
Together with USB interrupt flag register 0 (USBIFR0), USBIFR1 indicates interrupt status
information required by the application. When an interrupt occurs, the corresponding bit is set to 1
and an interrupt request is sent to the CPU according to the combination with USB interrupt
enable register 1 (USBIER1). Clearing is performed by writing 0 to the bit to be cleared, and 1 to
the other bits. However, VBUSMN is a status bit, and cannot be cleared.
USBIFR1 is initialized to H'20 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
-
-
-
-
VBU
SMN
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
⎯
All 0
R
Reserved
2
1
0
EP3TR EP3TS VBUSF
0
R/W
0
R/W
0
R/W
The write value should always be 0.
3
VBUSMN
0
R
Status bit for monitoring the status of the VBUS pin.
The status of the VBUS pin is reflected.
0: Disconnected
1: Connected
2
EP3TR
0
R/W
EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NACK handshake is
returned to the host until data is written to the FIFO
buffer and packet transmission is enabled.
1
EP3TS
0
R/W
EP3 Transmit Complete
This bit is set when data is transmitted to the host
from endpoint 3 and an ACK handshake is returned.
0
VBUSF
0
R/W
UBS Disconnection Detection
This bit is set to 1 when a function is connected to or
disconnected from the USB bus. Use the VBUSCNT
pin of this module to detect connection/disconnection.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1353 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.3
USB Interrupt Select Register 0 (USBISR0)
USBISR0 selects the vector numbers of the interrupt requests indicated in USB interrupt flag
register 0 (USBIFR0). If the USB issues an interrupt request to the INTC when the corresponding
bit in USBISR0 is cleared to 0, the interrupt will be USI0 (USB interrupt 0). If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR0 is set to 1, the interrupt will
be USI1 (USB interrupt 1). If interrupts occur simultaneously, USI0 has priority by default.
USBISR0 is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
BRST
EP1
FULL
EP2TR
0
R/W
0
R/W
0
R/W
4
3
2
1
0
EP2 SETUP
EP0oTS EP0iTR EP0iTS
EMPTY TS
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
BRST
0
R/W
Bus reset
6
EP1FULL
0
R/W
EP1FIFO full
5
EP2TR
0
R/W
EP2 transfer request
4
EP2EMPTY 0
R/W
EP2 FIFO empty
3
SETUPTS
0
R/W
Setup command receive completion
2
EP0oTS
0
R/W
EPOo receive completion
1
EP0iTR
0
R/W
EPOi transfer request
0
EP0iTS
0
R/W
EPOi transmit completion
Page 1354 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.3.4
Section 25 USB Function Module
USB Interrupt Select Register 1 (USBISR1)
USBISR1 selects the vector numbers of the interrupt requests indicated in USB interrupt flag
register 1 (USBIFR1). If the USB issues an interrupt request to the INTC when the corresponding
bit in USBISR1 is cleared to 0, the interrupt will be USI0 (USB interrupt 0). If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will
be USI1 (USB interrupt 1). If interrupts occur simultaneously, USI0 has priority by default.
USBISR1 is initialized to H'07 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
⎯
All 0
R
Reserved
2
1
0
EP3TR EP3TS VBUSF
1
R/W
1
R/W
1
R/W
The write value should always be 0.
2
EP3TR
1
R/W
EP3 transfer request
1
EP3TS
1
R/W
EP3 transmission completion
0
VBUSF
1
R/W
USB bus connection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1355 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.5
USB Interrupt Enable Register 0 (USBIER0)
USBIER0 enables the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0).
When an interrupt flag is set while the corresponding bit in USBIER0 is set to 1, an interrupt
request is sent to the CPU. The interrupt vector number is decided by the contents of USB
interrupt select register 0 (USBISR0).
USBIER0 is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
BRST
EP1
FULL
EP2TR
0
R/W
0
R/W
0
R/W
4
3
2
1
0
EP2 SETUP EP0oTS EP0iTR EP0iTS
EMPTY TS
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
BRST
0
R/W
Bus reset
6
EP1FULL
0
R/W
EP1FIFO full
5
EP2TR
0
R/W
EP2 transfer request
4
EP2EMPTY 0
R/W
EP2 FIFO empty
3
SETUPTS
0
R/W
Setup command receive completion
2
EP0oTS
0
R/W
EPOo receive completion
1
EP0iTR
0
R/W
EPOi transfer request
0
EP0iTS
0
R/W
EPOi transmit completion
Page 1356 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.3.6
Section 25 USB Function Module
USB Interrupt Enable Register 1 (USBIER1)
USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1).
When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt
request is sent to the CPU. The interrupt vector number is decided by the contents of USB
interrupt select register 1 (USBISR1).
USBEPDR0I is initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
7 to 3
⎯
All 0
R
2
1
0
EP3TR EP3TS VBUSF
0
R/W
0
R/W
0
R/W
Description
Reserved
The write value should always be 0.
2
EP3TR
0
R/W
EP3 transfer request
1
EP3TS
0
R/W
EP3 transmit completion
0
VBUSF
0
R/W
USB bus connection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1357 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.7
USBEP0i Data Register (USBEPDR0i)
USBEPDR0i is an 8-byte transmit FIFO buffer for endpoint 0, holding one packet of transmit data
for control IN. Transmit data is fixed by writing one packet of data and setting the EP0iPKTE bit
in the trigger register. When an ACK handshake is returned from the host after the data has been
transmitted, bit 0 (EP0iTS) in USB interrupt flag register 0 is set.
USBEPDR0i can be initialized by means of the EP0iCLR bit in USBFCLR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
⎯
W
Data register for control IN transfer
25.3.8
USBEP0o Data Register (USBEPDR0o)
USBEPDR0o is an 8-byte receive FIFO buffer for endpoint 0. USBEPDR0o holds endpoint 0
receive data other than setup commands. When data is received normally, the EP0oTS bit in USB
interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive
data size register. After the data has been read, setting the EP0oRDFN bit in the trigger register
enables the next packet to be received.
USBEPDR0o can be initialized by means of the EP0oCLR bit in USBFCLR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
⎯
R
Data register for control OUT transfer
Page 1358 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.3.9
Section 25 USB Function Module
USBEP0s Data Register (USBEPDR0s)
USBEPDR0s is an 8-byte FIFO buffer specifically for endpoint 0 setup command reception and
stores an 8-byte command data that is sent in the setup stage. USBEPDR0s receives only
commands requiring processing on the microcomputer (firmware) side. Commands that this
module automatically processes are not stored. When command data is received normally, the
SETUPTS bit in USB interrupt flag register 0 is set.
As a setup command must be received without fail, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority and the read data is invalid.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
⎯
R
Register for storing the setup command on control
OUT transfer
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1359 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.10 USBEP1 Data Register (USBEPDR1)
USBEPDR1 is a 128-byte receive FIFO buffer for endpoint 1. USBEPDR1 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When one packet of data is
received normally from the host, the EP1FULL bit in USB interrupt flag register 0 is set. The
number of receive bytes is indicated in the EP1 receive data size register. After the data has been
read, the buffer that was read is enabled to receive again by writing 1 to the EP1RDFN bit in the
USB trigger register. The receive data in this FIFO buffer can be transferred by DMA or DTC
(dual address transfer byte by byte).
USBEPDR1 can be initialized by means of the EP1CLR bit in USBFCLR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
⎯
R
Data register for endpoint 1 transfer
Page 1360 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.11 USBEP2 Data Register (USBEPDR2)
USBEPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. USBEPDR2 has a dual-buffer
configuration, and has a capacity of twice the maximum packet size. When transmit data is written
to this FIFO buffer and the EP2PKTE bit in the USB trigger register is set, one packet of transmit
data is fixed, and the dual buffer is switched over. Transmit data for this FIFO buffer can be
transferred by DMA or DTC (dual address transfer byte by byte).
USBEPDR2 can be initialized by means of the EP2CLR bit in USBFCLR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
⎯
W
Data register for endpoint 2 transfer
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1361 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.12 USBEP3 Data Register (USBEPDR3)
USBEPDR3 is an 8-byte transmit FIFO buffer for endpoint 3, holding one packet of transmit data
in endpoint 3 interrupt transfer. Transmit data is fixed by writing one packet of data and setting the
EP3PKTE bit in the USB trigger register. When an ACK handshake is received from the host after
one packet of data has been transmitted normally, the EP3TS bit in the USB interrupt flag register
0 is set.
USBEPDR3 can be initialized by means of the EP3CLR bit in USBFCLR.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
⎯
W
Data register for endpoint 3 transfer
25.3.13 USBEP0o Receive Data Size Register (USBEPSZ0o)
USBEPSZ0o indicates, in bytes, the amount of data received from the host by endpoint 0o.
USBEPSZ0o can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
⎯
All 0
R
Number of bytes received by endpoint 0
Page 1362 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.14 USBEP1 Receive Data Size Register (USBEPSZ1)
USBEPSZ1 indicates, in bytes, the amount of data received from the host by endpoint 1. The
endpoint 1 FIFO buffer has a dual-FIFO configuration. The receive data size indicated by this
register refers to the currently selected FIFO (that can be read by CPU).
USBEPSZ1 can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
-
-
-
-
-
-
-
0
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
⎯
All 0
R
Number of bytes received by endpoint 1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1363 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.15 USB Trigger Register (USBTRG)
USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint.
USBTRG can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
EP3
PKTE
EP1
RDFN
EP2
PKTE
-
EP0s
RDFN
EP0o
RDFN
EP0i
PKTE
0
-
0
W
0
W
0
W
0
-
0
W
0
W
0
W
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
6
EP3PKTE
0
W
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
5
EP1RDFN
0
W
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-FIFO configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
4
EP2PKTE
0
W
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 FIFO buffer, the transmit data is fixed by
writing 1 to this bit.
3
⎯
0
⎯
Reserved
The write value should always be 0.
Page 1364 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Bit
Bit Name
Initial
Value
R/W
Description
2
EP0sRDFN
0
W
EP0s Read Complete
Write 1 to this bit after EP0s command FIFO data has
been read. Writing 1 to this bit enables
transmission/reception of data in the following data
stage. A NACK handshake is returned in response to
transmit/receive requests from the host in the data
stage until 1 is written to this bit.
1
EP0oRDFN
0
W
EP0o Read Complete
Writing 1 to this bit after one packet of data has been
read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet to
be received.
0
EP0iPKTE
0
W
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1365 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.16 USB Data Status Register (USBDASTS)
USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set to 1 when
data is written to the corresponding FIFO buffer and the packet enable state is set. This bit is
cleared when all data has been transmitted to the host.
In the case of dual-FIFO buffer for endpoint 2, this bit is cleared when all data on two FIFOs has
been transmitted to the host.
USBDASTS can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
-
-
0
R
0
R
5
4
3
2
1
0
-
-
-
EP0iDE
0
R
0
R
0
R
0
R
EP3DE EP2DE
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
⎯
All 0
R
Reserved
The write value should always be 0.
5
EP3DE
0
R
EP3 Data Present
This bit is set when the endpoint 3 FIFO buffer
contains valid data.
4
EP2DE
0
R
EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data
3 to 1
⎯
All 0
R
0
EP0iDE
0
R
Reserved
The write value should always be 0.
EP0i Data Present
This bit is set when the endpoint 0 FIFO buffer
contains valid data.
Page 1366 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.17 USBFIFO Clear Register (USBFCLR)
USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
USBFCLR can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
EP3
CLR
EP1
CLR
EP2
CLR
-
-
EP0o
CLR
EP0i
CLR
0
W
0
W
0
W
0
0
-
-
0
W
0
W
0
-
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
⎯
Reserved
The write value should always be 0.
6
EP3CLR
0
W
EP3 Clear
When 1 is written to this bit, the endpoint 3 transmit
FIFO buffer is initialized.
5
EP1CLR
0
W
EP1 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 1 receive FIFO buffer are initialized.
4
EP2CLR
0
W
EP2 Clear
When 1 is written to this bit, both FIFOs in the
endpoint 2 transmit FIFO buffer are initialized.
3, 2
⎯
All 0
⎯
Reserved
The write value should always be 0.
1
EP0oCLR
0
W
EP0o Clear
When 1 is written to this bit, the endpoint 0 receive
FIFO buffer is initialized.
0
EP0iCLR
0
W
EP0i Clear
When 1 is written to this bit, the endpoint 0 transmit
FIFO buffer is initialized.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1367 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.18 USBDMA Transfer Setting Register (USBDMAR)
USBDMAR enables DMA or DTC transfer between the endpoint 1 and endpoint 2 data registers
and memory by means of the on-chip DMA controller (DMAC) or on-chip data transfer controller
(DTC). Dual address transfer is performed with the transfer size of only on a per-byte basis. In
order to start DMA transfer, DMAC settings must be made in addition to the settings in this
register. For details of DMA transfer, see section 25.8, DMA Transfer. For DTC transfer, DTC
settings must be made in addition to the settings in this register. For details of DTC transfer, see
section 25.9, DTC Transfer.
USBDMAR can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
-
-
-
-
-
-
EP2
EP1
DMAE DMAE
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
7 to 2
⎯
All 0
R
1
0
0
R/W
Description
Reserved
The write value should always be 0.
1
EP2DMAE*1 0
R/W
Endpoint 2 DMA/DTC Transfer Enable
When this bit is set, DMA/DTC transfer is enabled
from memory to the endpoint 2 transmit FIFO buffer. If
there is at least one byte of space in the FIFO buffer,
a transfer request is asserted for the DMAC or DTC.
In DMA/DTC transfer, when 64 bytes are written to
the FIFO buffer, the EP2 packet enable bit is set
automatically, allowing 64 bytes of data to be
transferred. If there is still space in the other of the
two FIFOs, a transfer request is asserted for the
DMAC or DTC again. However, if the size of the data
packet to be transmitted is less than 64 bytes, the
EP2 packet enable bit is not set automatically, and so
should be set by the CPU with a DMA/DTC transfer
end interrupt.
Also, as EP2-related interrupt requests to the CPU
are not automatically masked, interrupt requests
should be masked as necessary in the interrupt
enable register.
Page 1368 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
0
Bit Name
2
EP1DMAE*
Section 25 USB Function Module
Initial
Value
R/W
Description
0
R/W
Endpoint 1 DMA/DTC Transfer Enable
When this bit is set, DMA/DTC transfer is enabled
from the endpoint 1 receive FIFO buffer to memory. If
there is at least one byte of receive data in the FIFO
buffer, a transfer request is asserted for the DMAC or
DTC. In DMA/DTC transfer, when all the received
data is read, EP1 is read automatically and the
completion trigger operates.
Also, as EP1-related interrupt requests to the CPU
are not automatically masked, interrupt requests
should be masked as necessary in the interrupt
enable register.
Notes: 1. Before setting this bit, set the DME bit in DMAOR to start DMA transfer or set the
DTCE0 bit in DTCERA to start DTC transfer.
If the DME bit in DMAOR and the DTCE0 bit in DTCERA are not set, an EP2-FIFO
empty DTC transfer end interrupt (TXF bit in USDTENDRR) is generated.
2. Before setting this bit, set the DME bit in DMAOR to start DMA transfer or set the
DTCE1 bit in DTCERA to start DTC transfer.
If the DME bit in DMAOR and the DTCE1 bit in DTCERA are not set, an EP1-FIFO full
DTC transfer end interrupt (RXF bit in USDTENDRR) is generated.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1369 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.3.19 USB Endpoint Stall Register (USBEPSTL)
The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit
is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for
endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data for which
decoding is performed in this function module. When the SETUPTS flag in USBIFR0 is set,
writing 1 to the EP0STL bit is ignored. For details, see section 25.7, Stall Operations. When
ASCE = 1 is specified, the EPxSTL bit is automatically cleared.
USBEPSTL can be initialized to H'00 by a power-on reset.
Bit:
Initial value:
R/W:
7
6
5
-
-
-
ASCE EP3STL EP2STL EP1STL EP0STL
4
3
0
R
0
R
0
R
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
⎯
All 0
R
Reserved
2
0
R/W
1
0
R/W
0
0
R/W
The write value should always be 0.
4
ASCE
0
R/W
Auto-Stall Clear Enable
When this bit is set to 1, the stall setting bit
(USBEPSTLR/ESxSTL) of the USB endpoint is
automatically cleared after a stall handshake is
returned to the host. This bit cannot be set for each
endpoint.
3
EP3STL
0
R/W
EP3 Stall
When this bit is set to 1, endpoint 3 is placed in the
stall state.
2
EP2STL
0
R/W
EP2 Stall
When this bit is set to 1, endpoint 2 is placed in the
stall state.
1
EP1STL
0
R/W
EP1 Stall
When this bit is set to 1, endpoint 1 is placed in the
stall state.
0
EP0STL
0
R/W
EP0 Stall
When this bit is set to 1, endpoint 0 is placed in the
stall state.
Page 1370 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.4
Section 25 USB Function Module
Interrupt Sources
This module has two interrupt signals. Table 25.3 shows the interrupt sources and their
corresponding interrupt request signals.
Table 25.3 Interrupt Sources
Description
Interrupt
Request
Signal
DMAC/DTC
Activation by
USB Request
Register
Bit
Interrupt
Transfer Type Source
USBIFR0
7
(Status)
BRST
Bus reset
USI0 or USI1
×
6
Bulk-OUT
(EP1)
EP1FULL
EP1 FIFO full
USI0 or USI1
USBRXI*
5
Bulk-IN
(EP2)
EP2TR
EP2 transfer request
USI0 or USI1
×
EP2EMPTY
EP2 FIFO empty
USI0 or USI1
USBTXI*
3
Setup
(EP0s)
SETUPTS
Set command receive
completion
USI0 or USI1
×
2
Control-OUT
(EP0o)
EP0oTS
EP0o receive completion USI0 or USI1
×
1
Control-IN
(EP0i)
EP0iTR
EP0i transfer request
USI0 or USI1
×
EP0iTS
EP0i transmit completion USI0 or USI1
×
7
⎯
Reserved
⎯
⎯
⎯
6
⎯
Reserved
⎯
⎯
⎯
5
⎯
Reserved
⎯
⎯
⎯
4
⎯
Reserved
⎯
⎯
⎯
4
0
USBIFR1
1
2
3
(Status)
VBUSMN
VBUS monitor
USI0 or USI1
×
2
Interrupt
(EP3)
EP3TR
EP3 transfer request
USI0 or USI1
×
EP3TS
EP3 transmit completion USI0 or USI1
×
(Status)
VBUSF
USB disconnection
detect
×
1
0
USI0 or USI1
Notes: 1. For bulk-OUT transfer, set the EP1DMAE bit in USBDMAR to enable DMA/DTC
transfer requests.
2. For bulk-IN transfer, set the EP2DMAE bit in USBDMAR to enable DMA/DTC transfer
requests.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1371 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
• USI0 signal
The USI0 signal requests interrupts from the sources for which the corresponding bits in
interrupt select register 0 or 1 (UISR0 or UISR1) are cleared to 0. This signal is asserted if any
interrupt flag register bit that corresponds to the interrupt source assigned to this signal is set to
1.
• USI1 signal
The USI0 signal requests interrupts from the sources for which the corresponding bits in
interrupt select register 0 or 1 (UISR0 or UISR1) are set to 1. This signal is asserted if any
interrupt flag register bit that corresponds to the interrupt source assigned to this signal is set to
1.
25.5
Operation
25.5.1
Initial Settings
USB function
Cancel power-on reset
Start supplying
USB 48-MHz clock
Application
Select USB 48-MHz clock
(Clear USBSEL bit in STBCR6 to 0)
(Set USBCLK bit in STBCR6 to 1)*1
Wait for stable USB 48-MHz
clock oscillation (8 ms)*2
Cancel USB module stop state
(Clear MSTP66 bit in STBCR6 to 0)
Wait for USB cable
connection
Notes: 1. This setting is not required when the ceramic resonator for the USB is
connected or the external 48-MHz clock is input.
2. The initial values of the USBSEL and USBCLK bits in STBCR6 immediately
after a power-on reset are 0 and 1, respectively. Wait for the power-on oscillation
settling time indicated in section 31.3.1, Clock Timing, before canceling the
power-on reset state. This secures the oscillation settling time for the USB
48-MHz clock. After halting the clock to change the values of the USBSEL and
USBCLK bits, secure the oscillation settling time when restarting the clock.
Figure 25.2 Initial Setting Operation
Page 1372 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.5.2
Section 25 USB Function Module
Cable Connection
USB function
Application
Cable disconnected
VBUS pin = 0 V
UDC core reset
USB module interrupt
setting
Initial
settings
As soon as preparations are
completed, enable D+ pull-up
in general output port
USB cable connection
No
General output port
D+ pull-up enabled?
Yes
USBIFR1/VBUS = 1
USB bus connection interrupt
Interrupt request
Firmware preparations for
start of USB communication
UDC core reset release
Bus reset reception
USBIFR0/BRST = 1
Bus reset interrupt
Wait for setup command
reception complete interrupt
Clear VBUS flag
(USBIFR1/VBUS)
Interrupt request
Clear bus reset flag
(USBIFR0/BRST)
Clear FIFOs
(EP0, EP1, EP2, EP3)
Wait for setup command
reception complete interrupt
Figure 25.3 Cable Connection Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1373 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
The flowchart in figure 25.3 shows the operation in the case for section 25.10, Example of USB
External Circuitry.
In applications that do not require USB cable connection to be detected, processing by the USB
bus connection interrupt is not necessary. Preparations should be made with the bus reset interrupt.
Also, in applications that require connection detection regardless of USD+ pull-up control,
detection should be carried out using IRQx or a general input port. For details, see section 25.10,
Example of USB External Circuitry.
25.5.3
Cable Disconnection
USB function
Application
Cable connected
VBUS pin = 1
USB cable disconnection
VBUS pin = 0
UDC core reset
End
Figure 25.4 Cable Disconnection Operation
The flowchart in figure 25.4 shows the operation in the case for section 25.10, Example of USB
External Circuitry.
Page 1374 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.5.4
Section 25 USB Function Module
Control Transfer
Control transfer consists of three stages: setup, data (not always included), and status (figure 25.5).
The data stage comprises a number of bus transactions. Operation flowcharts for each stage are
shown below.
Setup stage
Control IN
Control OUT
No data
Data stage
SETUP(0)
IN(1)
IN(0)
DATA0
DATA1
DATA0
SETUP(0)
OUT(1)
OUT(0)
DATA0
DATA1
DATA0
Status stage
...
...
IN(0/1)
OUT(1)
DATA0/1
DATA1
OUT(0/1)
IN(1)
DATA0/1
DATA1
SETUP(0)
IN(1)
DATA0
DATA1
Figure 25.5 Transfer Stages in Control Transfer
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1375 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Setup Stage:
USB function
Application
SETUP token reception
Receive 8-byte command
data in EP0s
Command
to be processed by
application?
No
Automatic
processing by
this module
Yes
Set setup command
reception complete flag
(USBIFR0/SETUP TS = 1)
To data stage
Interrupt request
Clear SETUP TS flag
(USBIFR0/SETUP TS = 0)
Clear EP0i FIFO (UFCLR/EP0iCLR = 1)
Clear EP0o FIFO (UFCLR/EP0oCLR = 1)
Read 8-byte data from EP0s
Decode command data
Determine data stage direction*1
Write 1 to EP0s read complete bit
(USBTRG/EP0s RDFN = 1)
*2
To control-in
data stage
To control-out
data stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by
the application, and determines the subsequent processing (for example, data stage direction, etc.).
2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status
stage should be enabled here. When the transfer direction is control-in, this interrupt is not required
and should be disabled.
Figure 25.6 Setup Stage Operation
Page 1376 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Data Stage (Control-IN): The application first analyzes command data from the host in the setup
stage, and determines the subsequent data stage direction. If the result of command data analysis is
that the data stage is in-transfer, one packet of data to be sent to the host is written to the FIFO. If
there is more data to be sent, this data is written to the FIFO after the data written first has been
sent to the host (USBIFR0/EP0iTS = 1).
The end of the data stage is identified when the host transmits an OUT token and the status stage
is entered.
USB function
Application
IN token reception
From setup stage
1 written
to USBTRG/EP0s
RDFN?
Write data to USBEP0i
data register (USBEPDR0i)
No
NACK
Yes
Valid data
in EP0i FIFO?
Write 1 to EP0i packet
enable bit
(USBTRG/EP0i PKTE = 1)
No
NACK
Yes
Data transmission to host
ACK
Set EP0i transmission
complete flag
(USBIFR0/EP0i TS = 1)
Interrupt request
Clear EP0i transmission
complete flag
(USBIFR0/EP0i TS = 0)
Write data to USBEP0i
data register (USBEPDR0i)
Write 1 to EP0i packet
enable bit
(USBTRG/EP0i PKTE = 1)
Figure 25.7 Data Stage (Control-IN) Operation
Note: If the size of the data transmitted by the function is smaller than the data size requested by
the host, the function indicates the end of the data stage by returning to the host a packet
shorter than the maximum packet size. If the size of the data transmitted by the function is
an integral multiple of the maximum packet size, the function indicates the end of the data
stage by transmitting a zero-length packet.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1377 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Data Stage (Control-OUT): The application first analyzes command data from the host in the
setup stage, and determines the subsequent data stage direction. If the result of command data
analysis is that the data stage is OUT-transfer, the application waits for data from the host, and
after data is received (USBIFR0/EP0oTS = 1), reads data from the FIFO. Next, the application
writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the
next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
USB function
Application
OUT token reception
1 written
to USBTRG/EP0s
RDFN?
No
NACK
Yes
Data reception from host
ACK
Set EP0o reception
complete flag
(USBIFR0/EP0o TS = 1)
Interrupt request
Read data from USBEP0o
receive data size register
(USBEPSZ0o)
OUT token reception
1 written
to USBTRG/EP0o
RDFN?
Clear EP0o reception
complete flag
(USBIFR0/EP0o TS = 0)
No
NACK
Read data from USBEP0o
data register (USBEPDR0o)
Yes
Write 1 to EP0o read
complete bit
(USBTRG/EP0o RDFN = 1)
Figure 25.8 Data Stage (Control-OUT) Operation
Page 1378 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Status Stage (Control-IN): The control-IN status stage starts with an OUT token from the host.
The application receives 0-byte data from the host, and ends control transfer.
USB function
Application
OUT token reception
0-byte reception from host
ACK
Set EP0o reception
complete flag
(USBIFR0/EP0o TS = 1)
End of control transfer
Interrupt request
Clear EP0o reception
complete flag
(USBIFR0/EP0o TS = 0)
Write 1 to EP0o read
complete bit
(USBTRG/EP0o RDFN = 1)
End of control transfer
Figure 25.9 Status Stage (Control-IN) Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1379 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Status Stage (Control-OUT): The control-OUT status stage starts with an IN token from the
host. When an IN token is received at the start of the status stage, there is not yet any data in the
EP0iFIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from
this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is
written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next
IN token causes 0-byte data to be transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
USB function
Application
IN token reception
Valid data
in EP0i FIFO?
Interrupt request
No
NACK
Clear EP0i transfer
request flag
(USBIFR0/EP0i TR = 0)
Yes
Write 1 to EP0i packet
enable bit
(USBTRG/EP0i PKTE = 1)
0-byte transmission to host
ACK
Set EP0i transmission
complete flag
(USBIFR0/EP0i TS = 1)
End of control transfer
Interrupt request
Clear EP0i transmission
complete flag
(USBIFR0/EP0i TS = 0)
End of control transfer
Figure 25.10 Status Stage (Control-OUT) Operation
Page 1380 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.5.5
Section 25 USB Function Module
EP1 Bulk-OUT Transfer (Dual FIFOs)
EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads
without being aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the
first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty,
and so the next packet can be received immediately. When both FIFOs are full, NACK is returned
to the host automatically. When reading of the receive data is completed following data reception,
1 is written to the USBTRG/EP1 RDFN bit. This operation empties the FIFO that has just been
read, and makes it ready to receive the next packet.
USB function
Application
OUT token reception
Space
in EP1 FIFO?
No
NACK
Yes
Data reception from host
ACK
Interrupt request
Set EP1 FIFO full status
(USBIFR0/EP1 FULL = 1)
Read USBEP1 receive data
size register (USBEPSZ1)
Read data from USBEP1
data register (USBEPDR1)
Write 1 to EP1 read
complete bit
(USBTRG/EP1 RDFN = 1)
Both
EP1 FIFOs empty?
No
Interrupt request
Yes
Clear EP1 FIFO full status
(USBIFR0/EP1 FULL = 0)
Figure 25.11 EP1 Bulk-OUT Transfer Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1381 of 1778
Section 25 USB Function Module
25.5.6
SH7280 Group, SH7243 Group
EP2 Bulk-IN Transfer (Dual FIFOs)
EP2 has two 64-byte FIFOs, but the user can perform data transmission and transmit data writes
without being aware of this dual-FIFO configuration. However, one data write is performed for
one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2/PKTE at
one time after consecutively writing 128 bytes of data. EP2/PKTE must be performed for each 64byte write.
When performing bulk-IN transfer, as there is no valid data in the FIFOs on reception of the first
IN token, a USBIFR0/EP2 TR interrupt is requested. With this interrupt, 1 is written to the
USBIER0/EP2EMPTY bit, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs
are empty, and so an EP2 FIFO empty interrupt is generated immediately.
The data to be transmitted is written to the data register using this interrupt. After the first transmit
data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to
the other FIFO immediately. When both FIFOs are full, EP2EMPTY is cleared to 0. If at least one
FIFO is empty, USBIFR0/EP2EMPTY is set to 1. When ACK is returned from the host after data
transmission is completed, the FIFO used in the data transmission becomes empty. If the other
FIFO contains valid transmit data at this time, transmission can be continued.
When transmission of all data has been completed, write 0 to USBIER0/EP2EMPTY and disable
interrupt requests.
Page 1382 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
USB function
Application
IN token reception
NO
Valid data
in EP2 FIFO?
NACK
Is there data
for transmission
to host?
YES
YES
NO
Data transmission to host
Enable EP2 FIFO
empty interrupt
(USBIER0/EP2 EMPTY = 1)
ACK
Space
in EP2 FIFO?
YES
Set EP2
empty status
(USBIFR0/EP2
EMPTY = 1)
Interrupt
request
USBIER0/EP2 EMPTY
interrupt
NO
Write one packet of data
to USBEP2 data register
(USBEPDR2)
Clear EP2 empty status
(USBIFR0/EP2 EMPTY = 0)
Write 1 to EP2 packet
enable bit
(USBTRG/EP2 PKTE = 1)
NO
Is there data
for transmission
to host?
YES
Disable EP2 FIFO
empty interrupt
(USBIER0/EP2 EMPTY = 0)
Figure 25.12 EP2 Bulk-IN Transfer Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1383 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.5.7
EP3 Interrupt-IN Transfer
USB function
Application
Is there data
for transmission
to host?
No
Yes
IN token reception
Write data to USBEP3 data
register (USBEPDR3)
Valid data
in EP3 FIFO?
No
NACK
Yes
Write 1 to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
Data transmission to host
ACK
Set EP3 transmission
complete flag
(USBIFR1/EP3 TS = 1)
Interrupt request
Clear EP3 transmission
complete flag
(USBIFR1/EP3 TS = 0)
Is there data
for transmission
to host?
No
Yes
Write data to USBEP3 data
register (USBEPDR3)
Write 1 to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register
is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 25.13 EP3 Interrupt-IN Transfer Operation
Page 1384 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.6
Processing of USB Standard Commands and Class/Vendor
Commands
25.6.1
Processing of Commands Transmitted by Control Transfer
A command transmitted from the host by control transfer may require decoding and execution of
command processing on the application side. Whether command decoding is required on the
application side is indicated in table 25.4 below.
Table 25.4 Command Decoding on Application Side
Decoding not Necessary on Application Side
Decoding Necessary on Application Side
Clear feature
Get Descriptor
Get configuration
Synch Frame
Get interface
Set Descriptor
Get status
Class/Vendor command
Set address
Set configuration
Set feature
Set interface
If decoding is not necessary on the application side, command decoding and data stage and status
stage processing are performed automatically. No processing is necessary by the user. An interrupt
is not generated in this case.
If decoding is necessary on the application side, the USB function module stores the command in
the EP0s FIFO. After normal reception is completed, the USBIER0/SETUP TS flag is set and an
interrupt request is generated. In the interrupt routine, 8 bytes of data must be read from the EP0s
data register (USBEPDR0S) and decoded by firmware. The necessary data stage and status stage
processing should then be carried out according to the result of the decoding operation.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1385 of 1778
Section 25 USB Function Module
25.7
SH7280 Group, SH7243 Group
Stall Operations
This section describes stall operations in the USB function module. There are two cases in which
the USB function module stall function is used:
• When the application forcibly stalls an endpoint for some reason
• When a stall is performed automatically within the USB function module due to a USB
specification violation
The USB function module has internal status bits that hold the status (stall or non-stall) of each
endpoint. When a transaction is sent from the host, the module references these internal status bits
and determines whether to return a stall to the host. These bits cannot be cleared by the
application; they must be cleared with a Clear Feature command from the host. The internal status
bit for EP0 is automatically cleared only when the setup command is received.
25.7.1
Forcible Stall by Application
The application uses USBEPSTL register to issue a stall request for the USB function module.
When the application wishes to stall a specific endpoint, it sets the corresponding bit in
USBEPSTL (1-1 in figure 25.14). The internal status bits are not changed. When a transaction is
sent from the host for the endpoint for which the USBEPSTL bit was set, the USB function
module references the internal status bit, and if this is not set, references the corresponding bit in
USBEPSTL (1-2 in figure 25.14). If the corresponding bit in USBEPSTL is set, the USB function
module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 25.14). If
the corresponding bit in USBEPSTL is not set, the internal status bit is not changed and the
transaction is accepted.
Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the
host, without regard to USBEPSTL register. Even after a bit is cleared by the Clear Feature
command (3-1 in figure 25.14), the USB function module continues to return a stall handshake
while the bit in USBEPSTL is set, since the internal status bit is set each time a transaction is
executed for the corresponding endpoint (1-2 in figure 25.14). To clear a stall, therefore, it is
necessary for the corresponding bit in USBEPSTL to be cleared by the application, and also for
the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure
25.14).
Page 1386 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
(1) Transition from normal operation to stall
(1-1)
USB
Internal status bit
0
USBEPSTL
0→1
1. 1 written to
USBEPSTL by
application
USBEPSTL
1
1. IN/OUT token
received from host
2. USBEPSTL
referenced
USBEPSTL
1
1. 1 set in USBEPSTL
2. Internal status bit
set to 1
3. Transmission of
STALL handshake
(1-2)
Reference
Transaction request
Internal status bit
0
(1-3)
Stall
STALL handshake
Internal status bit
0→1
To (2-1) or (3-1)
(2) When Clear Feature is sent after USBEPSTL is cleared
(2-1)
Transaction request
Internal status bit
1
USBEPSTL
1→0
Internal status bit
1
USBEPSTL
0
1. Transmission of
STALL handshake
Internal status bit
1→0
USBEPSTL
0
1. Internal status bit
cleared to 0
(2-2)
STALL handshake
1. USBEPSTL cleared
to 0 by application
2. IN/OUT token
received from host
3. Internal status bit
already set to 1
4. USBEPSTL not
referenced
5. Internal status bit
not changed
(2-3)
Clear Feature command
Normal status restored
(3) When Clear Feature is sent before USBEPSTL is cleared to 0
(3-1)
Clear Feature command
USBEPSTL
1
Internal status bit
1→0
1. Internal status bit
cleared to 0
2. USBEPSTL not
changed
To (1-2)
Figure 25.14 Forcible Stall by Application
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1387 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.7.2
Automatic Stall by USB Function Module
When a stall setting is made with the Set Feature command, or in the event of a USB specification
violation, the USB function module automatically sets the internal status bit for the relevant
endpoint without regard to USBEPSTL register, and returns a stall handshake (1-1 in
figure 25.15).
Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the
host, without regard to USBEPSTL register. After a bit is cleared by the Clear Feature command,
USBEPSTL is referenced (3-1 in figure 25.15). The USB function module continues to return a
stall handshake while the internal status bit is set, since the internal status bit is set even if a
transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 25.15). To clear a
stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure
25.15). If set by the application, USBEPSTL should also be cleared (2-1 in figure 25.15).
(1) Transition from normal operation to stall
(1-1)
STALL handshake
Internal status bit
0→1
USBEPSTL
0
To (2-1) or (3-1)
1. In case of USB
specification
violation, etc., USB
function module
stalls endpoint
automatically
(2) When transaction is performed when internal status bit is set, and Clear Feature is sent
(2-1)
Transaction request
Internal status bit
1
USBEPSTL
0
Internal status bit
1
USBEPSTL
0
1. USBEPSTL cleared
to 0 by application
2. IN/OUT token
received from host
3. Internal status bit
already set to 1
4. USBEPSTL not
referenced
5. Internal status bit
not changed
(2-2)
STALL handshake
1. Transmission of
STALL handshake
Stall status maintained
(3) When Clear Feature is sent before transaction is performed
(3-1)
Clear Feature command
Internal status bit
1→0
USBEPSTL
0
1. Internal status bit
cleared to 0
2. USBEPSTL not
changed
Normal status restored
Figure 25.15 Automatic Stall by USB Function Module
Page 1388 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.8
Section 25 USB Function Module
DMA Transfer
This module allows DMAC transfer for endpoints 1 and 2, excluding transfer of word and
longword.
If endpoint 1 contains at least one byte of valid receive data, a DMA transfer request is issued to
endpoint 1. If there is no valid data in endpoint 2, a DMA transfer request is issued to endpoint 2.
When EP1DMAE in the USBDMA setting register is set to 1 to allow DMA transfer, 0-length
data received for endpoint 1 is ignored. When DMA transfer is set, it is unnecessary to write 1 to
the EP1 USBTRG/RDFN and EP2 USBTRG/PKTE bits. (1 must be written to the
USBTRG/PKTE bit for data that consists of the maximum number of bytes or less.) For EP1, the
FIFO buffer automatically becomes empty when all the received data is read. For EP2, the FIFO
automatically becomes full when the maximum number of bytes (64 bytes) is written to the FIFO
and then the data in the FIFO is transmitted. (See figures 25.16 and 25.19.)
25.8.1
DMA Transfer for Endpoint 1
If the received data for EP1 is transferred by DMA, when the data on the currently selected FIFO
becomes empty, an equivalent processing of writing 1 to the USBTRG/RDFN bit is automatically
performed in the module. Therefore, do not write 1 to the EP1RDFN bit in USBTRG after reading
the data on one side of the FIFO. Correct operation cannot be guaranteed.
For example, if 150 bytes of data are received from the host, the equivalent processing of writing 1
to the USBTRG/RDFN bit is automatically performed internally in the three places in figure
25.16. This processing is done when the data on the currently selected FIFO becomes empty
meaning that the processing is to be automatically performed even if 64 bytes of data or less than
that are transferred.
64 bytes
64 bytes
RDFN
(automatically written)
22 bytes
RDFN
RDFN
(automatically written) (automatically written)
Figure 25.16 EP1 RDFN Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1389 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
DMA function
Application
Set I[3:0] bits in SR
Set bits 15 to 12 in IPR06
(enable interrupts)
Set transfer information
(SAR_0, DAR_0, DMATCR_0,
CHCR_0, DMAOR, DMARS0)
DMA transfer
request
Activate DMA
DMA transfer end
Set TE bit in CHCR
Data transfer end interrupt
Set EP1DMAE bit in USBDMAR
to 1
Interrupt request
to CPU
Clear EP1DMAE bit in USBDMAR
to 0 and clear TE bit in CHCR
Figure 25.17 Example of DMA Transfer (Channel 0) for Bulk-OUT Transfer (EP1)
(When Receive Data Size is Determined Before Receiving Out Token)
Page 1390 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
USB function
DMA function
Application
Set I[3:0] bits in SR
OUT token reception
Set bits 15 to 12 in IPR06
(enable interrupts)
Space
in EP1 FIFO?
NO
NACK
Set transfer information
(SAR_0, DAR_0, CHCR_0,
DMAOR, DMARS0)
YES
Data reception from host
ACK
Set EP1 FIFO full status
(USBIFR0/EP1 FULL = 1)
Interrupt request to CPU*
Disable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 0)
Read USBEP1 receive data
size register (USBEPSZ1)
Set transfer information
(DMATCR_0)
[1]
DMA transfer
request
Set EP1DMAE bit in USBDMAR
to 1
Interrupt request
to CPU Clear EP1DMAE bit in USBDMAR
DMA transfer end
Set TE bit in CHCR
to 0 and clear TE bit in CHCR
Data transfer end
interrupt
Enable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 1)
Activate DMA
Interrupt request to CPU*
Both
EP1 FIFOs empty?
NO
YES
Clear EP1 FIFO full status
(USBIFR0/EP1 FULL = 0)
[1] Set DMATCR_0 to the same value as the USBEP1 receive data size register (USBEPSZ1).
Note: * To generate an interrupt request to the CPU, enable the EP1 FULL interrupt (USBIER0/EP1 FULL = 1).
Figure 25.18 Example of DMA Transfer (Channel 0) for Bulk-OUT Transfer (EP1)
(When Receive Data Size Cannot be Determined Before Receiving Out Token)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1391 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.8.2
DMA Transfer for Endpoint 2
If the transmitted data for EP2 is transferred by DMA, when the data on one side of FIFO (64
bytes) becomes full, an equivalent processing of writing 1 to the USBTRG/PKTE bit is
automatically performed in the module. Therefore, when data to be transferred is a multiple of 64
bytes, writing 1 to the USBTRG/PKTE bit is not necessary.
For the data less than 64 bytes, a 1 should be written to the USBTRG/PKTE bit by a DMA
transfer end interrupt of the DMAC. If a 1 is written to the USBTRG/PKTE bit for transferring the
maximum number of bytes (64 bytes), the correct operation cannot be guaranteed.
For example, if 150 bytes of data are transmitted to the host, the equivalent processing if writing 1
to the USBTRG/PKTE bit is automatically performed internally in the two places in figure 25.19.
This processing is done when the data on the currently selected FIFO becomes full meaning that
the processing is to be automatically performed only when 64 bytes of data are transferred.
When the last 22 bytes are transferred, write 1 to the USBTRG/PKTE bit because this is not
automatically written to. There is no data to be transferred in the application side, but this module
outputs the DMA transfer request for EP2 as long as the FIFO has a space. When all the data is
transferred by DMA, write 0 to the USBDMA/EP2DMAE bit to cancel the DMA transfer request
for EP2.
64 bytes
64 bytes
PKTE
(automatically written)
22 bytes
PKTE
PKTE
(automatically written) not written
Generate DMA transfer end interrupt
Figure 25.19 EP2 PKTE Operation
Page 1392 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
DMA function
Application
Set I[3:0] bits in SR
Set bits 15 to 12 in IPR06
(enable interrupts)
Set transfer information
(SAR_0, DAR_0, DMATCR_0,
CHCR_0, DMAOR, DMARS0)
DMA transfer
request
Activate DMA
DMA transfer end
Set TE bit in CHCR
Data transfer end interrupt
Set EP2DMAE bit in USBDMAR
to 1
Interrupt request
to CPU
Clear EP2DMAE bit in USBDMAR
to 0 and clear TE bit in CHCR
Write 1 to EP2 packet
enable bit
(USBTRG/EP2 PKTE = 1)
[1]
[1] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Figure 25.20 Example of DMA Transfer (Channel 0) for Bulk-IN Transfer (EP2)
(When Transmit Data Size is Determined Before Receiving IN Token)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1393 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
USB function
DMA function
Application
Set I[3:0] bits in SR
IN token reception
Valid data
in EP2 FIFO?
NO
Set bits 15 to 12 in IPR06
(enable interrupts)
NACK
YES
Set transfer information
(SAR_0, DAR_0, DMATCR_0,
CHCR_0, DMAOR, DMARS0)
Data transmission to host
ACK
Is there data
for transmission
to host?
NO
YES
Enable EP2 FIFO empty interrupt
(USBIER0/EP2 EMPTY = 1)
Space
in EP2 FIFO?
YES
NO
Set EP2 empty status
(USBIFR0/EP2
EMPTY = 1)
Interrupt request to CPU
Activate DMA
Clear EP2 empty status
(USBIFR0/EP2
EMPTY = 0)
DMA transfer end
Set TE bit in CHCR
Data transfer end
interrupt
DMA transfer
request
Disable EP2 FIFO
empty interrupt
(USBIER0/EP2 EMPTY = 0)
Set EP2DMAE bit in USBDMAR
to 1
Interrupt request
to CPU
Clear EP2DMAE bit in USBDMAR
to 0 and clear TE bit in CHCR
Write 1 to EP2 packet
enable bit
(USBTRG/EP2 PKTE = 1)
[1]
[1] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Figure 25.21 Example of DMA Transfer (Channel 0) for Bulk-IN Transfer (EP2)
(When Transmit Data Size Cannot be Determined Before Receiving IN Token)
Page 1394 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.9
Section 25 USB Function Module
DTC Transfer
This module allows DTC transfer for endpoints 1 and 2, excluding transfer of word and longword.
If endpoint 1 contains at least one byte of valid receive data, a DTC transfer request is issued to
endpoint 1. If there is no valid data in endpoint 2, a DTC transfer request is issued to endpoint 2.
When EP1DMAE in the USBDMA setting register is set to 1 to allow DTC transfer, 0-length data
received for endpoint 1 is ignored. When DTC transfer is set, it is unnecessary to write 1 to the
EP1 USBTRG/RDFN and EP2 USBTRG/PKTE bits. (1 must be written to the USBTRG/PKTE
bit for data that consists of the maximum number of bytes or less.) For EP1, the FIFO buffer
automatically becomes empty when all the received data is read. For EP2, the FIFO automatically
becomes full when the maximum number of bytes (64 bytes) is written to the FIFO and then the
data in the FIFO is transmitted. (See figures 25.22 and 25.25.)
25.9.1
DTC Transfer for Endpoint 1
If the received data for EP1 is transferred by DTC when the data on the currently selected FIFO
becomes empty, an equivalent processing of writing 1 to the USBTRG/RDFN bit is automatically
performed in the module. Therefore, do not write 1 to the EP1RDFN bit in USBTRG after reading
the data on one side of the FIFO. Correct operation cannot be guaranteed.
For example, if 150 bytes of data are received from the host, the equivalent processing of writing 1
to the USBTRG/RDFN bit is automatically performed internally in the three places in figure
25.22. This processing is done when the data on the currently selected FIFO becomes empty
meaning that the processing is to be automatically performed even if 64 bytes of data or less than
that are transferred.
64 bytes
64 bytes
RDFN
(automatically written)
22 bytes
RDFN
RDFN
(automatically written) (automatically written)
Figure 25.22 EP1 RDFN Operation
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1395 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
Application
DTC function
Set I[3:0] bits in SR
Clear RRS bit in DTCCR to 0
Set transfer information
(MRA, MRB, SAR, DAR,
CRA, CRB)
[1]
Set RRS bit in DTCCR to 1
Set the start address of transfer
information in DTC vector table
Set DTCE1 bit in DTCERA to 1
Clear RXF bit in USDTENDRR
and set bits 7 to 4 in IPR18
(enable interrupts)
DTC transfer
request
Set EP1DMAE bit in USBDMAR
to 1
Activate DTC
DTC transfer end
Clear DTCE1 bit in DTCERA
Receive data transfer end interrupt
Interrupt request
to CPU
Clear EP1DMAE bit in USBDMAR
to 0 and set bits 7 to 4 in IPR18
(disable interrupts)
[1] In block transfer mode, the block size set in CRA should be 64 bytes or less.
Figure 25.23 Example of DTC Transfer for Bulk-OUT Transfer (EP1)
(When Receive Data Size is Determined Before Receiving Out Token)
Page 1396 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
USB function
DTC function
Application
Set I[3:0] bits in SR
Clear RRS bit in DTCCR to 0
OUT token reception
Set transfer information
(MRA, MRB, SAR, DAR)
NO
Space
in EP1 FIFO?
NACK
Set the start address of transfer
information in DTC vector table
YES
Data reception from host
Set DTCE1 bit in DTCERA to 1
ACK
Set EP1 FIFO full status
(USBIFR0/EP1 FULL = 1)
Disable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 0)
Interrupt request to CPU*
Read USBEP1 receive data
size register (USBEPSZ1)
Clear RRS bit in DTCCR to 0
[1] Set CRA and CRB to the same value
as the USBEP1 receive data size register
(USBEPSZ1).
Set transfer information
(CRA, CRB)
Note: * To generate an interrupt request to the CPU,
enable the EP1 FULL interrupt
(USBIER0/EP1 FULL = 1).
[1]
Set RRS bit in DTCCR to 1
DTC transfer
request
Clear RXF bit in USDTENDRR
and set bits 7 to 4 in IPR18
(enable interrupts)
Set EP1DMAE bit in USBDMAR
to 1
Activate DTC
Interrupt request
to CPU
Clear EP1DMAE bit in USBDMAR
to 0 and set bits 7 to 4 in IPR18
(disable interrupts)
DTC transfer end
Clear DTCE1 bit in DTCERA
Receive data transfer end interrupt
Enable EP1 FIFO full interrupt
(USBIER0/EP1 FULL = 1)
Both
EP1 FIFOs empty?
NO Interrupt request to CPU*
YES
Clear EP1 FIFO full status
(USBIFR0/EP1 FULL = 0)
Figure 25.24 Example of DTC Transfer for Bulk-OUT Transfer (EP1)
(When Receive Data Size Cannot be Determined Before Receiving Out Token)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1397 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.9.2
DTC Transfer for Endpoint 2
If the transmitted data for EP2 is transferred by DTC, when the data on one side of FIFO (64
bytes) becomes full, an equivalent processing of writing 1 to the USBTRG/PKTE bit is
automatically performed in the module. Therefore, when data to be transferred is a multiple of 64
bytes, writing 1 to the USBTRG/PKTE bit is not necessary.
For the data less than 64 bytes, a 1 should be written to the USBTRG/PKTE bit by a transmit data
transfer end interrupt of the DTC. If a 1 is written to the USBTRG/PKTE bit for transferring the
maximum number of bytes (64 bytes), the correct operation cannot be guaranteed.
For example, if 150 bytes of data are transmitted to the host, the equivalent processing if writing 1
to the USBTRG/PKTE bit is automatically performed internally in the two places in figure 25.25.
This processing is done when the data on the currently selected FIFO becomes full meaning that
the processing is to be automatically performed only when 64 bytes of data are transferred.
When the last 22 bytes are transferred, write 1 to the USBTRG/PKTE bit because this is not
automatically written to. There is no data to be transferred in the application side, but this module
outputs the DTC transfer request for EP2 as long as the FIFO has a space. When all the data is
transferred by DTC, write 0 to the USBDMA/EP2DMAE bit to cancel the DTC transfer request
for EP2.
64 bytes
64 bytes
PKTE
(automatically written)
22 bytes
PKTE
PKTE
(automatically written) not written
Generate DTC transfer end interrupt
Figure 25.25 EP2 PKTE Operation
Page 1398 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
DTC function
Application
Set I[3:0] bits in SR
Clear RRS bit in DTCCR to 0
Set transfer information
(MRA, MRB, SAR, DAR,
CRA, CRB)
[1]
Set RRS bit in DTCCR to 1
Set the start address of transfer
information in DTC vector table
Set DTCE0 bit in DTCERA to 1
Clear TXF bit in USDTENDRR
and set bits 3 to 0 in IPR18
(enable interrupts)
Activate DTC
DTC transfer end
Clear DTCE1 bit in DTCERA
Transmit data transfer end interrupt
DTC transfer
request
Interrupt request
to CPU
Set EP2DMAE bit in USBDMAR
to 1
Clear EP2DMAE bit in USBDMAR
to 0 and set bits 3 to 0 in IPR18
(disable interrupts)
Write 1 to EP2 packet
enable bit
(USBTRG/EP2 PKTE = 1)
[2]
[1] In block transfer mode, the block size set in CRA should be 64 bytes or less.
[2] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Figure 25.26 Example of DTC Transfer for Bulk-IN Transfer (EP2)
(When Transmit Data Size is Determined Before Receiving IN Token)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1399 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
USB function
DTC function
Application
Set I[3:0] bits in SR
IN token reception
Clear RRS bit in DTCCR to 0
Valid data
in EP2 FIFO?
NO
Set transfer information
(MRA, MRB, SAR, DAR)
NACK
YES
Set the start address of transfer
information in DTC vector table
Data transmission to host
ACK
Set DTCE0 bit in DTCERA to 1
Is there data
for transmission
to host?
NO
YES
Enable EP2 FIFO empty interrupt
(USBIER0/EP2 EMPTY = 1)
Space
in EP2 FIFO?
YES
NO
Set EP2 empty status
(USBIFR0/EP2
EMPTY = 1)
Disable EP2 FIFO
empty interrupt
(USBIER0/EP2 EMPTY = 0)
Interrupt request to CPU
Clear RRS bit in DTCCR to 0
Set transfer information
(CRA, CRB)
Clear EP2 empty status
(USBIFR0/EP2
EMPTY = 0)
[1]
Set RRS bit in DTCCR to 1
Clear TXF bit in USDTENDRR
and set bits 3 to 0 in IPR18
(enable interrupts)
DTC transfer
request
Activate DTC
DTC transfer end
Clear DTCE1 bit in DTCERA
Transmit data transfer end
interrupt
[1] In block transfer mode, the block size set in CRA should be 64 bytes or less.
[2] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Set EP2DMAE bit in USBDMAR
to 1
Interrupt request
to CPU
Clear EP2DMAE bit in USBDMAR
to 0 and set bits 3 to 0 in IPR18
(disable interrupts)
Write 1 to EP2 packet
enable bit
(USBTRG/EP2 PKTE = 1)
[2]
Figure 25.27 Example of DTC Transfer for Bulk-IN Transfer (EP2)
(When Transmit Data Size Cannot be Determined Before Receiving IN Token)
Page 1400 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
25.10
Section 25 USB Function Module
Example of USB External Circuitry
USD+ Pull-Up Control: In a system where it is wished to delay USB host/hub connection
notification (USD+ pull-up) (during high-priority processing or initialization processing, for
example), USD+ pull-up is controlled using a general output port. When the USB cable has been
connected to the host or hub and USD+ pull-up is inhibited, USD+ and USD– are placed in the
low level state (USD+ and USD– are pull down on the host or hub side) and the USB module
recognizes as if the USB bus reset has been received from the host. In that case, the USD+ pull-up
control signal and VBUS pin input signal should be controlled using a general output port and the
USB cable VBUS (AND circuit) as shown in figure 25.28. (The UDC core of this LSI holds the
powered state independent of USD+ and USD– state when the VBUS pin is low level.)
Detection of USB Cable Connection/Disconnection: As USB states are managed by hardware in
this module, a VBUS signal that recognizes connection/disconnection is necessary. The power
supply signal (VBUS) in the USB cable is used for this purpose. However, if the cable is
connected to the USB host/hub when the on-chip function LSI power is off, a voltage (5 V) will be
applied from the USB host/hub. Therefore, an IC (HD74LV1G08A, 2G08A, etc.) that allows
voltage application when the system power is off should be connected externally.
This LSI
IC that allows
voltage application
when the system (LSI)
power is off.
PB10
(PUPD)
USB module
3.3 V
VBUS
IC that allows
voltage application
when the system (LSI)
power is off.
USD+
USD-
USB
connector
VBUS
5V
USD+
USDGND
Note: Operation cannot be guaranteed by this example.
When the system requires countermeasures against external surge
or ESD noise, use the protection diode or noise canceler.
USB
cable
Figure 25.28 Example of USB Function Module External Circuitry
(For On-Chip Transceiver)
Note: The same voltage as the CPU voltage (Vcc) should be applied to VBUS.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1401 of 1778
Section 25 USB Function Module
25.11
SH7280 Group, SH7243 Group
Notes on Usage
25.11.1 Receiving Setup Data
Note that the following when 8-byte setup data is received by USBEPDR0s.
1.
2.
The USB must always receive the setup command. Therefore, writing from the USB bus has
priority over reading from the CPU. When the USB starts receiving the next setup command
while the CPU is reading data after data reception, the USB forcibly invalidates reading from
the CPU to start writing. The value that is read after starting reception is undefined.
USBEPDR0s must be read in 8-byte unit. When reading is stopped in the middle, the data that
is received by the next setup command cannot be read correctly.
25.11.2 Clearing FIFO
If the connected USB cable is disconnected during communication, the data being received or
transmitted may remain in the FIFO. Therefore, clear the FIFO immediately after connecting the
USB cable.
Do not clear the FIFO that is receiving or transmitting data from or to the host.
25.11.3 Overreading or Overwriting Data Register
Note that the following when reading or writing the data register of this module:
Receive Data Register: Do not read the number of data which exceeds that of valid receive data
from the receive data register, i.e., data that exceeds the number of bytes indicated by the receive
data size register must not be read. For USBEPDR1 that has two FIFOs, the maximum number of
bytes that can be read at once is 64 bytes. After reading the data on the currently selected side,
write 1 to USBTRG/EP1RDFN to change the current side to another side. This allows the number
of bytes for the new side to be used as the receive data size, enabling the next data to be read.
Transmit Data Register: Do not write the number of data that exceeds the maximum packet size
to the transmit data register. For USBEPDR2 that has two FIFOs, the data to be written at one
time must be the maximum packet size or less. After writing the data, write 1 to TRG/PKTE to
change the currently selected side to another in the module to allow the next data to be written to
the new side. Therefore, do not write data to one side of FIFO right after the other side.
Page 1402 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 25 USB Function Module
25.11.4 Assigning Interrupt Source for EP0
Interrupt sources (bits 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be
assigned to the same interrupt pin using USBISR0.
25.11.5 Clearing FIFO when Setting DMA/DTC Transfer
Clearing the endpoint 1 data register (USBEPDR1) is impossible when DMA/DTC transfer is
enabled (USBDMAR/EP1DMAE = 1) for endpoint 1. To clear this register, cancel DMA/DTC
transfer.
25.11.6 Manual Reset for DMA/DTC Transfer
Do not input a manual reset during DMA/DTC transfer for endpoints 1 and 2. Correct operation
cannot be guaranteed.
25.11.7 USB Clock
Wait for the USB clock settling time and then cancel the module stop setting for the USB function
module.
25.11.8 Using TR Interrupt
Note that the following when using the transfer request interrupt (TR interrupt) for interrupt-IN
transfer of EP0i/EP2/EP3.
The TR interrupt flag is set when the IN token is sent from the USB host and there is no data in
the FIFO of the EP. However, TR interrupts occur continuously at the timing shown in figure
25.29. Make sure that no malfunction occurs in these cases.
Note: This module checks NAK acknowledgement if there is no data in the FIFO of the EP
when receiving the IN token. However the TR interrupt flag is set after transmitting the
NAK handshake. Therefore, when writing the USBTRG/PKTE bit is later than the next IN
token, the TR interrupt flag is set again.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1403 of 1778
SH7280 Group, SH7243 Group
Section 25 USB Function Module
TR interrupt routine
Clear TR flag, Write transmit
data, and TRG/PKTE
CPU
Host
USB
TR interrupt routine
IN token
IN token
IN token
Check NAK
Check NAK
NAK
NAK
Set TR flag
Data
transmission
ACK
Set TR flag
(flag is set again)
Figure 25.29 Timing for Setting the TR Interrupt Flag
25.11.9 Handling of Unused USB Pins
• Handle the unused pins as listed below.
If this process is not performed, correct operation of the LSI cannot be guaranteed.
DrVcc = 3.0 V to 5.5 V
DrVss = 0 V
USD+ = Open
USD- = Open
VBUS = 0 V
USEBEXTAL = 0 V
USBXTAL = Open
Page 1404 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Section 26 Flash Memory (ROM)
This LSI has on-chip flash memory. The flash memory has the following features.
26.1
Features
• Two flash-memory MATs, with one selected by the mode in which the LSI starts up
The on-chip flash memory has two memory spaces in the same address space (hereafter
referred to as memory MATs). The mode setting when the LSI starts up determines the
memory MAT that is currently mapped. The MAT can be switched by bank-switching after the
LSI has started up.
⎯ Size of the user MAT, from which booting-up proceeds after a power-on reset in user
mode: 1 Mbyte (SH7286), 256 Kbytes (SH7243), 768 Kbytes (SH7285)
⎯ Size of the user boot MAT, from which booting-up proceeds after a power-on reset in user
boot mode: 12 Kbytes (SH7286, SH7285)
• Four (three in SH7243) on-board programming modes and one off-board programming mode
On-board programming modes:
⎯ Boot mode: The on-chip SCIF interface is used for programming in this mode. Either the
user MAT or user-boot MAT can be programmed, and the bit rate for data transfer between
the host and this LSI are automatically adjusted.
⎯ User program mode: This mode allows programming of the user MAT via any desired
interface.
⎯ User boot mode (SH7286, SH7285): This mode allows writing of a user boot program via
any desired interface and programming of the user MAT.
Off-board programming mode:
⎯ Programmer mode: This mode allows programming of the user MAT and user boot MAT
with the aid of a PROM programmer.
• High-speed reading through ROM cache
Both the user MAT and user boot MAT can be read at high speed through the ROM cache.
They can be read only in on-chip ROM enabled mode.
• Downloading of an on-chip program to provide an interface for programming/erasure
This LSI has a dedicated programming/erasing program. After this program has been
downloaded to the on-chip RAM, programming or erasing can be performed by setting
parameters as arguments. “User branching” is also supported.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1405 of 1778
Section 26 Flash Memory (ROM)
•
•
•
•
SH7280 Group, SH7243 Group
User branching:
Programming is performed in 256-byte units. Each round of programming consists of
application of the programming pulse, reading for verification, and several other steps. Erasing
is performed in block units and each round of erasing consists of several steps. A userprocessing routine can be executed between each round of erasing, and making the setting for
this is called the addition of a user branch.
Protection modes
There are two modes of protection: software protection is applied by register settings and
hardware protection is applied by the level on the FWE pin. Protection of the flash memory
from programming or erasure can be selected.
When an abnormal state is detected, such as runaway execution of programming/erasing, the
protection modes initiate the transition to the error protection state and suspend
programming/erasing processing.
Programming/erasing time
The time taken to program 256 bytes of flash memory in a single round is tP ms (typ.), which is
equivalent to tP/256 ms per byte. The erasing time is tEs (typ.) per block. Refer to section 31.7,
Flash Memory Characteristics.
Number of programming operations
The flash memory can be programmed up to NWEC times.
Operating frequency for programming/erasing
The operating frequency for programming/erasing is 50 MHz (Pφ).
Page 1406 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.2
Overview
26.2.1
Block Diagram
ROM cache address bus
ROM cache data bus (128 bits)
FCCS
Module bus
FPCS
Memory MAT unit
FECS
FKEY
FMATS
FTDAR
Control unit
User MAT: 256 Kbytes,
512 Kbytes,
768 Kbytes,
1 Mbyte
User boot MAT: 12 Kbytes*
Flash memory
FWE pin
Mode pins
Operating
mode
[Legend]
FCCS:
FPCS:
FECS:
FKEY:
FMATS:
FTDAR:
Flash code control and status register
Flash program code select register
Flash erase code select register
Flash key code register
Flash MAT select register
Flash transfer destination address register
Note: *
User boot MAT cannot be used in the SH7243.
Figure 26.1 Block Diagram of Flash Memory
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1407 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.2.2
Operating Mode
When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the
microcontroller enters each operating mode as shown in figure 26.2. For the setting of each mode
pin and the FWE pin, see table 26.1.
• Flash memory cannot be read, programmed, or erased in ROM invalid mode. The
programming/erasing interface registers cannot be written to. When these registers are read,
H'00 is always read.
• Flash memory can be read in user mode, but cannot be programmed or erased.
• Flash memory can be read, programmed, or erased on the board only in user program mode,
user boot mode, and boot mode.
• Flash memory can be read, programmed, or erased by means of the PROM programmer in
programmer mode.
=0
U
=0
Programmer
mode
RE
S=
Bo
S
m
od
S
g
ttin
e
es
Us
mo er p
de rog
se ram
ttin
g
0
=
Reset state
RE
r
se
RES = 0
Programmer
mode setting
ot g
bo tin
er set
Us de
mo
S
RE
RES = 0
ROM invalid
mode setting
RE
ROM invalid
mode
ot
mo
de
0
se
ttin
g
FWE = 0
User mode
FWE = 1
User program
mode
User boot
mode
Boot mode
On-board programming mode
Figure 26.2 Mode Transition of Flash Memory
Page 1408 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 26.1
Section 26 Flash Memory (ROM)
Relationship between FWE and MD Pins and Operating Modes
Pin
Reset
State
ROM
Invalid
Mode
ROM
Valid
Mode
User
User
Program Boot
3
Mode
Mode*
Boot
Mode
USB
Boot
Programmer
Mode*3*4 Mode
RES
0
1
1
1
1
1
1
FWE
0/1
0
1
1
1
1
0/1*
0
1
0
1
1
1
0
0
1
MD0
0/1
0/1*
MD1
0/1
0
0
1
2
Setting value
depends on
the condition
of the
specialized
PROM
programmer.
Notes: 1. MD0 = 0: 16-bit external bus, MD0 = 1: 8-bit external bus
2. MD0 = 0: External bus can be used, MD0 = 1: Single-chip mode (external bus cannot
be used)
3. Setting is prohibited in the SH7243.
4. Becomes USB boot mode if always FWE = 1 after the power has been turned on. If
FWE = 0 until the reset is released and then changed to FWE = 1 after the MCU
operating mode is determined as single-chip mode, the operating mode transits to user
program mode.
26.2.3
Mode Comparison
The comparison table of programming and erasing related items about boot mode, user program
mode, user boot mode, and programmer mode is shown in table 26.2.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1409 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.2 Comparison of Programming Modes
Boot Mode
User
Program
Mode
User Boot
Mode*3
USB Boot
Mode*3
Programmer
Mode
Programming/
erasing
environment
On-board
programming
On-board
programming
On-board
programming
On-board
programming
Off-board
programming
Programming/
erasing enable
MAT
User MAT
User MAT
User boot MAT
User MAT
User MAT
User MAT
User boot
MAT
Programming/
erasing control
Command
method
Programming/ Programming/ Command
erasing
erasing
method
interface
interface
—
All erasure
Possible
(Automatic)
Possible
Possible
Possible
(Automatic)
Possible
(Automatic)
Block division
erasure
Possible*1
Possible
Possible
Possible*1
Not possible
Program data
transfer
From host via
SCI
From optional From optional
device via
device via
RAM
RAM
From host via
USB
Via
programmer
User branch
function
Not possible
Possible
Possible
Not possible
Not possible
Reset initiation
MAT
Embedded
program
storage MAT
User MAT
User boot
2
MAT*
Embedded
program
storage MAT
Embedded
program
storage MAT
Transition to user Mode setting
mode
change and
reset
FWE setting
change
Mode setting
change and
reset
Mode setting
change and
reset
—
Pin state
Dependent on CK: output
user settings (initial setting)
CK: output
Programmer
dedicated pins
CK: output
Other pins:
input
(same as the
states in MCU
extension
mode 2)
Other pins:
input (initial
setting)
Other pins:
input
(same as the
states in MCU
extension
mode 2)
RXD0 and
TXD0: valid
Notes: 1. All-erasure is performed. After that, the specified block can be erased.
2. Initiation starts from the embedded program storage MAT. After checking the flashmemory related registers, initiation starts from the reset vector of the user MAT.
3. Not available in the SH7243.
Page 1410 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
• The user boot MAT can be programmed or erased only in boot mode and programmer mode.
• The user MAT and user boot MAT are all erased in boot mode. Then, the user MAT and user
boot MAT can be programmed by means of the command method. However, the contents of
the MAT cannot be read until this state.
Only user boot MAT is programmed and the user MAT is programmed in user boot mode or
only user MAT is programmed because user boot mode is not used.
• In user boot mode, the boot operation of the optional interface can be performed by a mode pin
setting different from user program mode.
26.2.4
Flash Memory Configuration
This LSI's flash memory is configured by the 128-Kbyte, 256-Kbyte (SH7243), 512-Kbyte, 768Kbyte (SH7286, SH7285), or 1-Mbyte (SH7286) user MAT and 12-Kbyte user boot MAT
(SH7286, SH7285).
The start address is allocated to the same address in the user MAT and user boot MAT. Therefore,
when the program execution or data access is performed between the two MATs, the MAT must
be switched by using FMATS.
The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However,
the user boot MAT can be programmed only in boot mode and programmer mode.
Address H'00000000
*
Address H'00000000
12 Kbytes
Address H'00002FFF
Address
H'0003FFFF (for 256-Kbyte MAT)
H'0007FFFF (for 512-Kbyte MAT)
H'000BFFFF (for 768-Kbyte MAT)
H'000FFFFF (for 1-Mbyte MAT)
Note: * Only available in the SH7285 and SH7286
Figure 26.3 Flash Memory Configuration
The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT
that is 12 Kbytes or more. When a user boot MAT exceeding 12 Kbytes is read from, an undefined
value is read.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1411 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.2.5
Block Division
The user MAT is divided into 128 Kbytes (one block in the 256-Kbyte MAT, three blocks in the
512-Kbyte MAT, five blocks in the 768-Kbyte MAT, or seven blocks in the 1-Mbyte MAT), 64
Kbytes (one block), and 8 Kbytes (eight blocks) as shown in figure 26.4. The user MAT can be
erased in this divided-block units and the erase-block number of EB0 to EB11 is specified when
erasing.
< User MAT >
Address H'00000000
Erase block
EB0
8 Kbytes x 8
:
256 Kbytes
EB7
512 Kbytes
Last address of 256-Kbyte MAT
H'0003FFFF
(SH7243)
768 Kbytes
Last address of 512-Kbyte MAT
H'0007FFFF
(SH7285)
64 Kbytes
EB8
128 Kbytes
EB9
128 Kbytes
EB10
128 Kbytes
EB11
128 Kbytes
EB12
128 Kbytes
EB13
128 Kbytes
EB14
128 Kbytes
EB15
1 Mbyte
Last address of 768-Kbyte MAT
(SH7285, SH7286) H'000BFFFF
Last address of 1-Mbyte MAT
H'000FFFFF
(SH7286)
Figure 26.4 Block Division of User MAT
Page 1412 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
26.2.6
Section 26 Flash Memory (ROM)
Programming/Erasing Interface
Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and
specifying the program address/data and erase block by using the interface registers/parameters.
The procedure program is made by the user in user program mode and user boot mode. The
overview of the procedure is as follows. For details, see section 26.5.3, User Program Mode.
Start user procedure
program for
programming/erasing.
Select on-chip program
to be downloaded and
set download destination
Download on-chip
program by setting VBR,
FKEY, and SCO bits.
Initialization execution
(on-chip program execution)
Programming (in 256-byte
units) or erasing (in
one-block units)
(on-chip program execution)
No
Programming/
erasing
completed?
Yes
End user procedure
program
Figure 26.5 Overview of User Procedure Program
(1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination
This LSI has programming/erasing programs and they can be downloaded to the on-chip
RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in
the programming/erasing interface registers. The download destination can be specified by
FTDAR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1413 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
(2) Download of On-Chip Program
The on-chip program is automatically downloaded by clearing VBR of the CPU to
H'80000000 and then setting the SCO bit in the flash code control and status register (FCCS)
and the flash key code register (FKEY), which are programming/erasing interface registers.
The user MAT is replaced to the embedded program storage area when downloading. Since the
flash memory cannot be read when programming/erasing, the procedure program, which is
working from download to completion of programming/erasing, must be executed in a space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameters,
whether the normal download is executed or not can be confirmed.
Note that VBR can be changed after download is completed.
(3) Initialization of Programming/Erasing
The operating frequency and user branch are set before execution of programming/erasing.
The user branch destination must be in an area other than the user MAT area which is in the
middle of programming and the area where the on-chip program is downloaded. These settings
are performed by using the programming/erasing interface parameters.
(4) Programming/Erasing Execution
To program or erase, the FWE pin must be brought high and user program mode must be
entered.
The program data/programming destination address is specified in 256-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameters and the onchip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction to perform the subroutine call of the specified address in the on-chip RAM. The
execution result is returned to the programming/erasing interface parameters.
The area to be programmed must be erased in advance when programming flash memory.
Do not generate NMI, IRQ, and all other interrupts during programming/erasing.
(5) When Programming/Erasing is Executed Consecutively
When the processing is not ended by the 128-byte programming or one-block erasure, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program is left in the on-chip RAM after the processing,
download and initialization are not required when the same processing is executed
consecutively.
Page 1414 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
26.3
Section 26 Flash Memory (ROM)
Input/Output Pins
Flash memory is controlled by the pins as shown in table 26.3.
Table 26.3 Pin Configuration
Pin Name
Symbol
Input/Output
Function
Power-on reset
RES
Input
Reset
Flash programming
enable
FWE
Input
Hardware protection when
programming flash memory
Mode 1
MD1
Input
Sets operating mode of this LSI
Mode 0
MD0
Input
Sets operating mode of this LSI
SCI transmit data
TXD0 (PA1)
Output
Serial transmit data output (used in
boot mode)
(SH7285 and SH7286)
TXD0 (PB7)
Output
Serial transmit data output (used in
boot mode)
(SH7243)
RXD0 (PA0)
Input
Serial receive data input (used in boot
mode)
(SH7285 and SH7286)
RXD0 (PB6)
Input
Serial receive data input (used in boot
mode)
(SH7243)
Pull-up control
PUPD (PB10)
Output
Pull-up control (used in USB boot
mode)
(SH7285 and SH7286)
USB data
USB+
USB−
I/O
USD signal from the USB that has a
transceiver (used in USB boot mode)
(SH7285 and SH7286)
USB cable connection
monitor
VBUS
Input
Detects connection and disconnection
of the USB cable (used in USB boot
mode)
(SH7285 and SH7286)
USB clock select
PC0
Input
Selects the clock supplied by the USB
(used in USB boot mode)
(SH7285 and SH7286)
SCI receive data
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1415 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.4
Register Descriptions
26.4.1
Registers
The registers/parameters which control flash memory when the on-chip flash memory is valid are
shown in table 26.4.
There are several operating modes for accessing flash memory, for example, read mode/program
mode.
There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters
are allocated for each operating mode and MAT selection. The correspondence of operating modes
and registers/parameters for use is shown in table 26.5.
Table 26.4 (1)
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access
Size
Flash code control and status FCCS
register
R, W*1 H'00*2
H'80*2
H'FFFFA800
8
Flash program code select
register
FPCS
R/W
H'00
H'FFFFA801
8
Flash erase code select
register
FECS
R/W
H'00
H'FFFFA802
8
Flash key code register
FKEY
R/W
H'00
H'FFFFA804
8
3
Flash MAT select register
FMATS
R/W
H'00*
H'AA*3
H'FFFFA805
8
Flash transfer destination
address register
FTDAR
R/W
H'00
H'FFFFA806
8
ROM cache control register
RCCR
R/W
H'00000001
H'FFFC1400
32
Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit.
(The value which can be read is always 0.)
2. The initial value of the FWE bit is 0 when the FWE pin goes low.
The initial value of the FWE bit is 1 when the FWE pin goes high.
3. The initial value at initiation in user mode or user program mode is H'00.
The initial value at initiation in user boot mode is H'AA.
Page 1416 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table 26.4 (2)
Section 26 Flash Memory (ROM)
Parameter Configuration
Name
Abbreviation
R/W
Initial
Value
Address
Download pass/fail result
DPFR
R/W
Undefined
On-chip RAM* 8, 16, 32
Flash pass/fail result
FPFR
R/W
Undefined
R0 of CPU
8, 16, 32
Flash multipurpose address
area
FMPAR
R/W
Undefined
R5 of CPU
8, 16, 32
Flash multipurpose data
destination area
FMPDR
R/W
Undefined
R4 of CPU
8, 16, 32
Flash erase block select
FEBS
R/W
Undefined
R4 of CPU
8, 16, 32
Flash program and erase
frequency control
FPEFEQ
R/W
Undefined
R4 of CPU
8, 16, 32
Flash user branch address
set parameter
FUBRA
R/W
Undefined
R5 of CPU
8, 16, 32
Note:
*
Access
Size
One byte of the start address in the on-chip RAM area specified by FTDAR is valid.
Table 26.5 Register/Parameter and Target Mode
InitialiDownload zation
Programming
Erasure
Read
RAM
Emulation
Programming/
FCCS
erasing interface FPCS
registers
PECS
√
—
—
—
—
—
√
—
—
—
—
—
√
—
—
—
—
—
FKEY
√
—
√
√
—
—
FMATS
—
—
√*
√*
√*
—
FTDAR
√
—
—
—
—
—
√
—
—
—
—
—
—
√
√
√
—
—
—
√
—
—
—
—
—
√
—
—
—
—
Programming/
DPFR
erasing interface
FPFR
parameters
FPEFEQ
FUBRA
1
1
2
FMPAR
—
—
√
—
—
—
FMPDR
—
—
√
—
—
—
FEBS
—
—
—
√
—
—
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1417 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.4.2
Programming/Erasing Interface Registers
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in bytes.
(1)
Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence
during programming or erasing flash memory and the download of the on-chip program.
Bit:
7
6
5
4
3
2
1
0
FWE
MAT
-
FLER
-
-
-
SCO
1/0
R
0
R
0
R
0
R
0
R
0
R
0
(R)/W
Initial value: 1/0
R/W: R
Bit
Bit Name
Initial
Value
R/W
Description
7
FWE
1/0
R
Flash Programming Enable
Monitors the level which is input to the FWE pin that
performs hardware protection of the flash memory
programming or erasing. The initial value is 0 or 1
according to the FWE pin state.
0: When the FWE pin goes low (in hardware protection
state)
1: When the FWE pin goes high
6
MAT
1/0
R
MAT Bit
Indicates whether the user MAT or user boot MAT is
selected.
0: User MAT is selected
1: User boot MAT is selected
5
⎯
0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
Page 1418 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
R/W
Description
4
FLER
0
R
Flash Memory Error
Indicates an error occurs during programming and erasing
flash memory.
When FLER is set to 1, flash memory enters the error
protection state.
When FLER is set to 1, high voltage is applied to the
internal flash memory. To reduce the damage to flash
memory, the reset signal must be released after the reset
period of 100 μs which is longer than normal.
0: Flash memory operates normally
Programming/erasing protection for flash memory (error
protection) is invalid.
[Clearing condition]
At a power-on reset
1: Indicates an error occurs during programming/erasing
flash memory.
Programming/erasing protection for flash memory (error
protection) is valid.
[Setting condition]
See section 26.6.3, Error Protection.
3 to 1
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1419 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
R/W
Description
0
SCO
0
(R)/W
Source Program Copy Operation
Requests the on-chip programming/erasing program to be
downloaded to the on-chip RAM.
When this bit is set to 1, the on-chip program which is
selected by FPCS/FECS is automatically downloaded in
the on-chip RAM area specified by FTDAR.
In order to set this bit to 1, H'A5 must be written to FKEY
and this operation must be in the on-chip RAM.
Eight NOP instructions must be executed immediately
after setting this bit to 1.
For interrupts during download, see section 26.7.2,
Interrupts during Programming/Erasing. For the download
time, see section 26.7.3, Other Notes.
Since this bit is cleared to 0 when download is completed,
this bit cannot be read as 1.
Download by setting the SCO bit to 1 requires a special
interrupt processing that performs bank switching to the
on-chip program storage area. Therefore, before issuing a
download request (SCO = 1), set VBR to H'80000000.
Otherwise, the CPU gets out of control. Once download
end is confirmed, VBR can be changed to any other value.
The mode in which the FWE pin is high must be used
when using the SCO function.
0: Download of the on-chip programming/erasing program
to the on-chip RAM is not executed.
[Clearing condition]
When download is completed
1: Request that the on-chip programming/erasing program
is downloaded to the on-chip RAM is generated
[Setting conditions]
When all of the following conditions are satisfied and 1 is
written to this bit
Page 1420 of 1778
•
FKEY is written to H'A5
•
During execution in the on-chip RAM
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 26 Flash Memory (ROM)
Flash Program Code Select Register (FPCS)
FPCS selects the on-chip programming program to be downloaded.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
PPVS
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
PPVS
0
R/W
Program Pulse Single
Selects the programming program.
0: On-chip programming program is not selected
[Clearing condition]
When transfer is completed
1: On-chip programming program is selected
(3)
Flash Erase Code Select Register (FECS)
FECS selects download of the on-chip erasing program.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
EPVB
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1421 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
R/W
Description
0
EPVB
0
R/W
Erase Pulse Verify Block
Selects the erasing program.
0: On-chip erasing program is not selected
[Clearing condition]
When transfer is completed
1: On-chip erasing program is selected
(4)
Flash Key Code Register (FKEY)
FKEY is a register for software protection that enables download of the on-chip program and
programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the
on-chip program or executing the downloaded programming/erasing program, these processings
cannot be executed if the key code is not written.
Bit:
7
6
5
3
2
1
0
0
R/W
0
R/W
0
R/W
0
R/W
4
K[7:0]
Initial value: 0
R/W: R/W
0
R/W
0
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
K[7:0]
All 0
R/W
Key Code
Only when H'A5 is written, writing to the SCO bit is valid.
When a value other than H'A5 is written to FKEY, 1
cannot be written to the SCO bit. Therefore downloading
to the on-chip RAM cannot be executed.
Only when H'5A is written, programming/erasing of flash
memory can be executed. Even if the on-chip
programming/erasing program is executed, flash memory
cannot be programmed or erased when a value other than
H'5A is written to FKEY.
H'A5: Writing to the SCO bit is enabled (The SCO bit
cannot be set by a value other than H'A5.)
H'5A: Programming/erasing is enabled (A value other than
H'5A enables software protection state.)
H'00: Initial value
Page 1422 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(5)
Section 26 Flash Memory (ROM)
Flash MAT Select Register (FMATS)
FMATS specifies whether user MAT or user boot MAT is selected.
Bit:
7
6
5
4
3
2
1
0
MS7
MS6
MS5
MS4
MS3
MS2
MS1
MS0
Initial value: 0/1
R/W: R/W
0
R/W
0/1
R/W
0
R/W
0/1
R/W
0
R/W
0/1
R/W
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
MS7
0/1
R/W
MAT Select
6
MS6
0
R/W
5
MS5
0/1
R/W
4
MS4
0
R/W
These bits are in user-MAT selection state when a value
other than H'AA is written and in user-boot-MAT selection
state when H'AA is written.
3
MS3
0/1
R/W
2
MS2
0
R/W
1
MS1
0/1
R/W
0
MS0
0
R/W
The MAT is switched by writing a value in FMATS with the
on-chip RAM instruction.
When the MAT is switched, follow section 26.7.1,
Switching between User MAT and User Boot MAT. (The
user boot MAT cannot be programmed in user program
mode if user boot MAT is selected by FMATS. The user
boot MAT must be programmed in boot mode or in
programmer mode.)
H'AA: The user boot MAT is selected (in user-MAT
selection state when the value of these bits are
other than H'AA)
Initial value when these bits are initiated in user
boot mode.
H'00: Initial value when these bits are initiated in a mode
except for user boot mode (in user-MAT selection
state)
[Programmable condition]
These bits are in the execution state in the on-chip RAM.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1423 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(6)
Flash Transfer Destination Address Register (FTDAR)
FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make
settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which
points to the start address (H'FFF81000) in on-chip RAM.
Bit:
7
6
5
4
TDER
Initial value: 0
R/W: R/W
3
2
1
0
0
R/W
0
R/W
0
R/W
TDA[6:0]
0
R/W
0
R/W
0
R/W
0
R/W
Bit
Bit
Name
Initial
Value R/W
Description
7
TDER
0
Transfer Destination Address Setting Error
R/W
This bit is set to 1 when there is an error in the download start
address set by bits 6 to 0 (TDA6 to TDA0). Whether the address
setting is erroneous or not is tested by checking whether the
setting of TDA6 to TDA0 is in the range of H'00 to H'05 after
setting the SCO bit in FCCS to 1 and performing download.
Before setting the SCO bit to 1 be sure to set the FTDAR value
between H'00 to H'05 as well as clearing this bit to 0.
0: Setting of TDA6 to TDA0 is normal
1: Setting of TDER and TDA6 to TDA0 is H'06 to H'FF and
download has been aborted
6 to 0 TDA[6:0] All 0
R/W
Transfer Destination Address
These bits specify the download start address. A value from
H'00 to H'05 can be set to specify the download start address in
on-chip RAM in 2-Kbyte units.
A value from H'06 to H'7F cannot be set. If such a value is set,
the TDER bit (bit 7) in this register is set to 1 to prevent
download from being executed.
H'00: Download start address is set to H'FFF81000
H'01: Download start address is set to H'FFF81800
H'02: Download start address is set to H'FFF82000
H'03: Download start address is set to H'FFF82800
H'04: Download start address is set to H'FFF83000
H'05: Download start address is set to H'FFF83800
H'06 to H'7F: Setting prohibited. If this value is set, the TDER bit
(bit 7) is set to 1 to abort the download processing.
Page 1424 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(7)
Section 26 Flash Memory (ROM)
ROM Cache Control Register (RCCR)
RCCR contains the RCF bit that controls the disabling of all lines in the ROM cache.
This register can be accessed only in longwords.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit: 15
0
Initial value:
R/W:
Initial value:
R/W:
Bit
16
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-
-
-
-
-
-
-
-
-
-
-
-
RCF
-
-
-
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R
0
R
1
R
Bit Name
31 to 4 ⎯
Initial
Value
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
3
RCF
0
R/W
ROM Cache Flush
Writing 1 to this bit disables (flushes) the instructions or
data in the ROM cache. This bit is read as 0.
0: Does not disable the instructions or data in the ROM
cache
1: Disables the instructions or data in the ROM cache
[Clearing condition]
•
By a power-on reset or in standby mode
[Setting condition]
•
2, 1
⎯
All 0
R
Writing 1 to this bit
Reserved
The write value should always be 0; otherwise normal
operation cannot be guaranteed.
0
⎯
1
R
Reserved
The write value should always be 1; otherwise normal
operation cannot be guaranteed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1425 of 1778
Section 26 Flash Memory (ROM)
26.4.3
SH7280 Group, SH7243 Group
Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, user branch
destination address, storage place for program data, programming destination address, and erase
block and exchanges the processing result for the downloaded on-chip program. This parameter
uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value
is undefined.
At download all CPU registers are stored, and at initialization or when the on-chip program is
executed, CPU registers except for R0 are stored. The return value of the processing result is
written in R0. Since the stack area is used for storing the registers or as a work area, the stack area
must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.)
The programming/erasing interface parameters are used in the following four items.
1.
2.
3.
4.
Download control
Initialization before programming or erasing
Programming
Erasing
These items use different parameters. The correspondence table is shown in table 26.6.
The processing results of initialization, programming, and erasing are returned, but the bit contents
have different meanings according to the processing program. See the description of FPFR for
each processing.
Page 1426 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.6 Usable Parameters and Target Modes
ProAbbrevia- Down- Initiali- gramtion
load
zation ming Erasure R/W
Name of
Parameter
Initial
Value
Allocation
Download pass/fail DPFR
result
√
—
—
—
R/W
Undefined On-chip
RAM*
Flash pass/fail
result
FPFR
—
√
√
√
R/W
Undefined R0 of CPU
Flash
programming/
erasing frequency
control
FPEFEQ
—
√
—
—
R/W
Undefined R4 of CPU
Flash user branch
address set
FUBRA
—
√
—
—
R/W
Undefined R5 of CPU
Flash multipurpose FMPAR
address area
—
—
√
—
R/W
Undefined R5 of CPU
Flash multipurpose FMPDR
data destination
area
—
—
√
—
R/W
Undefined R4 of CPU
Flash erase block
select
—
—
—
√
R/W
Undefined R4 of CPU
Note:
*
FEBS
One byte of start address of download destination specified by FTDAR
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1427 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(1)
Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by
FTDAR. For the address map of the on-chip RAM, see figure 26.10.
The download control is set by using the programming/erasing interface registers. The return
value is given by the DPFR parameter.
(a)
Download Pass/Fail Result Parameter (DPFR: One Byte of Start Address of On-Chip
RAM Specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the
start address of the on-chip RAM area specified by FTDAR to a value other than the return value
of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For
the checking method of download results, see section 26.5.3 (2), Programming Procedure in User
Program Mode.
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
SS
FK
SF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
R/W: R/W
Page 1428 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
7 to 3
⎯
Undefined R/W
R/W
Description
Unused
Return 0.
2
SS
Undefined R/W
Source Select Error Detect
The on-chip program which can be downloaded can be
specified as only one type. When more than two types
of the program are selected, the program is not
selected, or the program is selected without mapping,
an error occurs.
0: Download program can be selected normally
1: Download error occurs (Multi-selection or program
which is not mapped is selected)
1
FK
Undefined R/W
Flash Key Register Error Detect
Returns the check result whether the value of FKEY is
set to H'A5.
0: FKEY setting is normal (FKEY = H'A5)
1: FKEY setting is abnormal (FKEY = value other than
H'A5)
0
SF
Undefined R/W
Success/Fail
Returns the result whether download has ended
normally or not.
0: Downloading on-chip program has ended normally
(no error)
1: Downloading on-chip program has ended abnormally
(error occurs)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1429 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2)
Programming/Erasing Initialization
The on-chip programming/erasing program to be downloaded includes the initialization program.
The specified period pulse must be applied when programming or erasing. The specified pulse
width is made by the method in which wait loop is configured by the CPU instruction. The
operating frequency of the CPU must be set. Since the user branch function is supported, the user
branch destination address must be set.
The initial program is set as a parameter of the programming/erasing program which has
downloaded these settings.
(2.1) Flash Programming/Erasing Frequency Parameter (FPEFEQ: General Register R4 of
CPU)
This parameter sets the operating frequency of the CPU.
For the operating frequency of this LSI, see section 31.3.1, Clock Timing.
Bit: 31
-
Initial value: R/W: R/W
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
Initial value: R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 1430 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
31 to
16
⎯
Undefined R/W
R/W
Description
Unused
Return 0.
15 to 0 F15 to F0
Undefined R/W
Frequency Set
Set the operating frequency Iφ of the CPU following the
calculation below.
4
Iφ = F[15:0] × 10 Hz
1. Round it off to the digit of 1 kHz, and round down the
lower digits.
2. For example, when Iφ = 33.333 MHz, set as follows:
(1)
Iφ = 3333 × 104 Hz
(2)
F[15:0] = 3333 (H'0D05)
(3)
Set R4 (FPEFEQ) to H'00000D05.
(2.2) Flash User Branch Address Setting Parameter (FUBRA: General Register R5 of CPU)
This parameter sets the user branch destination address. The user program which has been set can
be executed in specified processing units when programming and erasing.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
UA31
UA30
UA29
UA28
UA27
UA26
UA25
UA24
UA23
UA22
UA21
UA20
UA19
UA18
UA17
UA16
Initial value: R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA15
UA14
UA13
UA12
UA11
UA10
UA9
UA8
UA7
UA6
UA5
UA4
UA3
UA2
UA1
UA0
Initial value: R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1431 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
31 to 0 UA31 to
UA0
Initial
Value
R/W
Undefined R/W
Description
User Branch Destination Address
When the user branch is not required, address 0
(H'00000000) must be set.
The user branch destination must be an area other than
the flash memory, an area other than the RAM area in
which on-chip program has been transferred, or the
external bus space.
Note that the CPU must not branch to an area without
the execution code and get out of control. The on-chip
program download area and stack area must not be
overwritten. If CPU runaway occurs or the download
area or stack area is overwritten, the value of flash
memory cannot be guaranteed.
The download of the on-chip program, initialization,
initiation of the programming/erasing program must not
be executed in the processing of the user branch
destination. Programming or erasing cannot be
guaranteed when returning from the user branch
destination. The program data which has already been
prepared must not be programmed.
Store general registers R8 to R15. General registers R0
to R7 are available without storing them.
Moreover, the programming/erasing interface registers
must not be written to in the processing of the user
branch destination.
After the processing of the user branch has ended, the
programming/erasing program must be returned to by
using the RTS instruction.
For the execution intervals of the user branch
processing, see note 2 (User branch processing
intervals) in section 26.7.3, Other Notes.
Page 1432 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2.3) Flash Pass/Fail Result Parameter (FPFR: General Register R0 of CPU)
This parameter indicates the return value of the initialization result.
Bit: 31
-
Initial value: R/W: R/W
Bit: 15
-
Initial value: R/W: R/W
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
BR
FQ
SF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial
Value
R/W
31 to 3 ⎯
Undefined R/W
2
Undefined R/W
Description
Unused
Return 0.
BR
User Branch Error Detect
Returns the check result whether the specified user
branch destination address is in the area other than the
storage area of the programming/erasing program
which has been downloaded.
0: User branch address setting is normal
1: User branch address setting is abnormal
1
FQ
Undefined R/W
Frequency Error Detect
Returns the check result whether the specified
operating frequency of the CPU is in the range of the
supported operating frequency.
0: Setting of operating frequency is normal
1: Setting of operating frequency is abnormal
0
SF
Undefined R/W
Success/Fail
Indicates whether initialization is completed normally.
0: Initialization has ended normally (no error)
1: Initialization has ended abnormally (error occurs)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1433 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(3)
Programming Execution
When flash memory is programmed, the programming destination address and programming data
on the user MAT must be passed to the programming program in which the program data is
downloaded.
1. The start address of the programming destination on the user MAT is set in general register R5
of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter).
Since the program data is always in 256-byte units, the lower eight bits (MOA7 to MOA0)
must be H'00 as the boundary of the programming start address on the user MAT.
2. The program data for the user MAT must be prepared in the consecutive area. The program
data must be in the consecutive space which can be accessed by using the MOV.L instruction
of the CPU and is not the flash memory space.
When data to be programmed does not satisfy 256 bytes, the 256-byte program data must be
prepared by embedding the dummy code (H'FF).
The start address of the area in which the prepared program data is stored must be set in
general register R4. This parameter is called FMPDR (flash multipurpose data destination area
parameter).
For details on the programming procedure, see section 26.5.3, User Program Mode.
(3.1) Flash Multipurpose Address Area Parameter (FMPAR: General Register R5 of CPU)
This parameter indicates the start address of the programming destination on the user MAT.
When an address in an area other than the flash memory space is set, an error occurs.
The start address of the programming destination must be at the 256-byte boundary. If this
boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA
bit (bit 1) in FPFR.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MOA31 MOA30 MOA29 MOA28 MOA27 MOA26 MOA25 MOA24 MOA23 MOA22 MOA21 MOA20 MOA19 MOA18 MOA17 MOA16
Initial value: R/W: R/W
Bit: 15
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
MOA15 MOA14 MOA13 MOA12 MOA11 MOA10 MOA9
Initial value: R/W: R/W
Page 1434 of 1778
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
7
6
5
4
3
2
1
0
MOA8
MOA7
MOA6
MOA5
MOA4
MOA3
MOA2
MOA1
MOA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Bit
Bit Name
31 to 0 MOA31 to
MOA0
Section 26 Flash Memory (ROM)
Initial
Value
R/W
Description
Undefined R/W
MOA31 to MOA0
Store the start address of the programming destination
on the user MAT. The consecutive 256-byte
programming is executed starting from the specified
start address of the user MAT. The MOA7 to MOA0 bits
are always 0 because the start address of the
programming destination is at the 256-byte boundary.
(3.2) Flash Multipurpose Data Destination Area Parameter (FMPDR: General Register R4
of CPU)
This parameter indicates the start address in the area which stores the data to be programmed in
the user MAT. When the storage destination of the program data is in flash memory, an error
occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MOD31 MOD30 MOD29 MOD28 MOD27 MOD26 MOD25 MOD24 MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16
Initial value: R/W: R/W
Bit: 15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MOD15 MOD14 MOD13 MOD12 MOD11 MOD10 MOD9 MOD8 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0
Initial value: R/W: R/W
Bit
R/W
Bit Name
R/W
R/W
Initial
Value
R/W
R/W
R/W
31 to 0 MOD31 to Undefined R/W
MOD0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
MOD31 to MOD0
Store the start address of the area which stores the
program data for the user MAT. The consecutive 256byte data is programmed to the user MAT starting from
the specified start address.
Page 1435 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(3.3) Flash Pass/Fail Result Parameter (FPFR: General Register R0 of CPU)
This parameter indicates the return value of the program processing result.
Bit: 31
-
Initial value: R/W: R/W
Bit: 15
-
Initial value: R/W: R/W
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
MD
EE
FK
-
WD
WA
SF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial
Value
R/W
31 to 7 ⎯
Undefined R/W
6
Undefined R/W
Description
Unused
Return 0.
MD
Programming Mode Related Setting Error Detect
Returns the check result of whether the signal input to
the FWE pin is high and whether the error protection
state is not entered.
When a low-level signal is input to the FWE pin or the
error protection state is entered, 1 is written to this bit.
The input level to the FWE pin and the error protection
state can be confirmed with the FWE bit (bit 7) and the
FLER bit (bit 4) in FCCS, respectively. For conditions to
enter the error protection state, see section 26.6.3,
Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
= 0)
1: FWE = 0 or FLER = 1, and programming cannot be
performed
Page 1436 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
5
EE
Undefined R/W
R/W
Description
Programming Execution Error Detect
1 is returned to this bit when the specified data could
not be written because the user MAT was not erased or
when flash-memory related register settings are
partially changed on returning from the user branch
processing.
If this bit is set to 1, there is a high possibility that the
user MAT is partially rewritten. In this case, after
removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is
selected, an error occurs when programming is
performed. In this case, both the user MAT and user
boot MAT are not rewritten.
Programming of the user boot MAT must be executed
in boot mode or programmer mode.
0: Programming has ended normally
1: Programming has ended abnormally (programming
result is not guaranteed)
4
FK
Undefined R/W
Flash Key Register Error Detect
Returns the check result of the value of FKEY before
the start of the programming processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than H'5A)
3
⎯
Undefined R/W
Unused
Return 0.
2
WD
Undefined R/W
Write Data Address Error Detect
When an address in the flash memory area is specified
as the start address of the storage destination of the
program data, an error occurs.
0: Setting of write data address is normal
1: Setting of write data address is abnormal
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1437 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
1
WA
Undefined R/W
R/W
Description
Write Address Error Detect
When the following items are specified as the start
address of the programming destination, an error
occurs.
•
The programming destination address is an area
other than flash memory
•
The specified address is not at the 256-byte
boundary (A7 to A0 are not 0)
0: Setting of programming destination address is normal
1: Setting of programming destination address is
abnormal
0
SF
Undefined R/W
Success/Fail
Indicates whether the program processing has ended
normally or not.
0: Programming has ended normally (no error)
1: Programming has ended abnormally (error occurs)
Page 1438 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(4)
Section 26 Flash Memory (ROM)
Erasure Execution
When flash memory is erased, the erase-block number on the user MAT must be passed to the
erasing program which is downloaded. This is set to the FEBS parameter (general register R4).
One block is specified from the block number 0 to 15.
For details on the erasing procedure, see section 26.5.3, User Program Mode.
(4.1) Flash Erase Block Select Parameter (FEBS: General Register R4 of CPU)
This parameter specifies the erase-block number. Several block numbers cannot be specified.
Bit: 31
-
Initial value: R/W: R/W
Bit: 15
-
Initial value: R/W: R/W
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
31 to 8 ⎯
Initial
Value
R/W
Undefined R/W
16
EBS[7:0]
R/W
R/W
R/W
R/W
R/W
Description
Unused
Return 0.
7 to 0
EBS[7:0]
Undefined R/W
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Set the erase-block number in the range from 0 to 11. 0
corresponds to the EB0 block and 11 corresponds to
the EB11 block. An error occurs when a number other
than 0 to 15 (H'00 to H'0F) is set.
Page 1439 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(4.2) Flash Pass/Fail Result Parameter (FPFR: General Register R0 of CPU)
This parameter returns the value of the erasing processing result.
Bit: 31
-
Initial value: R/W: R/W
Bit: 15
-
Initial value: R/W: R/W
Bit
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
MD
EE
FK
EB
-
-
SF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Initial
Value
R/W
31 to 7 ⎯
Undefined R/W
6
Undefined R/W
Description
Unused
Return 0.
MD
Erasure Mode Related Setting Error Detect
Returns the check result of whether the signal input to
the FWE pin is high and whether the error protection
state is not entered.
When a low-level signal is input to the FWE pin or the
error protection state is entered, 1 is written to this bit.
The input level to the FWE pin and the error protection
state can be confirmed with the FWE bit (bit 7) and the
FLER bit (bit 4) in FCCS, respectively. For conditions to
enter the error protection state, see section 26.6.3,
Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
= 0)
1: FWE = 0 or FLER = 1, and erasure cannot be
performed
Page 1440 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Bit
Bit Name
Initial
Value
5
EE
Undefined R/W
R/W
Description
Erasure Execution Error Detect
1 is returned to this bit when the user MAT could not be
erased or when flash-memory related register settings
are partially changed on returning from the user branch
processing.
If this bit is set to 1, there is a high possibility that the
user MAT is partially erased. In this case, after
removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is
selected, an error occurs when erasure is performed. In
this case, both the user MAT and user boot MAT are
not erased.
Erasure of the user boot MAT must be executed in boot
mode or programmer mode.
0: Erasure has ended normally
1: Erasure has ended abnormally (erasure result is not
guaranteed)
4
FK
Undefined R/W
Flash Key Register Error Detect
Returns the check result of FKEY value before start of
the erasing processing.
0: FKEY setting is normal (FKEY = H'5A)
1: FKEY setting is error (FKEY = value other than H'5A)
3
EB
Undefined R/W
Erase Block Select Error Detect
Returns the check result whether the specified eraseblock number is in the block range of the user MAT.
0: Setting of erase-block number is normal
1: Setting of erase-block number is abnormal
2, 1
⎯
Undefined R/W
Unused
Return 0.
0
SF
Undefined R/W
Success/Fail
Indicates whether the erasing processing has ended
normally or not.
0: Erasure has ended normally (no error)
1: Erasure has ended abnormally (error occurs)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1441 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.5
On-Board Programming Mode
When the pin is set in on-board programming mode and the reset start is executed, the on-board
programming state that can program/erase the on-chip flash memory is entered. On-board
programming mode has three operating modes: user program mode, user boot mode, and boot
mode.
For details on the pin setting for entering each mode, see table 26.1. For details on the state
transition of each mode for flash memory, see figure 26.2.
26.5.1
Boot Mode
Boot mode executes programming/erasing user MAT and user boot MAT by means of the control
command and program data transmitted from the host using the on-chip SCI. The tool for
transmitting the control command and program data must be prepared in the host. The SCI
communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin
is set in boot mode, the boot program in the microcontroller is initiated. After the SCI bit rate is
automatically adjusted, the communication with the host is executed by means of the control
command method.
The system configuration diagram in boot mode is shown in figure 26.6. For details on the pin
setting in boot mode, see table 26.1. Interrupts are ignored in boot mode, so do not generate them.
Note that the AUD cannot be used during boot mode operation.
This LSI
Control command,
analysis execution
software (on-chip)
Flash
memory
Host
Control command, program data
Boot
programming
tool and program
data
RXD0 (PA0)
(SH7285, SH7286)
RXD0 (PB6)
(SH7243)
On-chip SCI
Reply response
On-chip RAM
TXD0 (PA1)
(SH7285, SH7286)
TXD0 (PB7)
(SH7243)
Figure 26.6 System Configuration in Boot Mode
Page 1442 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(1)
Section 26 Flash Memory (ROM)
SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCIcommunication data (H'00), which is transmitted consecutively by the host. The SCI
transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate
of transmission by the host by means of the measured low period and transmits the bit adjustment
end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign
(H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not
executed normally, boot mode is initiated again (reset) and the operation described above must be
executed. The bit rate between the host and this LSI is not matched because of the bit rate of
transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the
transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and the
bit rate of this LSI is shown in table 26.7. Boot mode must be initiated in the range of this system
clock.
Start
bit
D0
D1
D2
D3
D4
D5
Measure low period (9 bits) (data is H'00)
D6
D7
Stop bit
High period of
at least 1 bit
Figure 26.7 Automatic Adjustment Operation of SCI Bit Rate
Table 26.7 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate of
This LSI
Host Bit Rate
Peripheral Clock (Pφ) Frequency That Can Automatically
Adjust LSI's Bit Rate
9,600 bps
10 to 50 MHz
19,200 bps
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1443 of 1778
Section 26 Flash Memory (ROM)
(2)
SH7280 Group, SH7243 Group
State Transition Diagram
Figure 26.8 gives an overview of the state transitions after the chip has been started up in boot
mode. For details on boot mode, see section 26.8.1, Specifications of the Standard Serial
Communications Interface in Boot Mode.
1. Bit-rate matching
After the chip has been started up in boot mode, bit-rate matching between the SCI and the
host proceeds.
2. Waiting for inquiry and selection commands
The chip sends the requested information to the host in response to inquiries regarding the size
and configuration of the user MAT, start addresses of the MATs, information on supported
devices, etc.
3. Automatic erasure of the entire user MAT and user boot MAT
After all necessary inquiries and selections have been made and the command for transition to
the programming/erasure state is sent by the host, the entire user MAT and user boot MAT are
automatically erased.
4. Waiting for programming/erasure command
⎯ On receiving the programming selection command, the chip waits for data to be
programmed. To program data, the host transmits the programming command code
followed by the address where programming should start and the data to be programmed.
This is repeated as required while the chip is in the programming-selected state. To
terminate programming, H'FFFFFFFF should be transmitted as the first address of the area
for programming. This makes the chip return to the programming/erasure command
waiting state from the programming data waiting state.
⎯ On receiving the erasure select command, the chip waits for the block number of a block to
be erased. To erase a block, the host transmits the erasure command code followed by the
number of the block to be erased. This is repeated as required while the chip is in the
erasure-selected state. To terminate erasure, H'FF should be transmitted as the block
number. This makes the chip return to the programming/erasure command waiting state
from the erasure block number waiting state. Erasure should only be executed when a
specific block is to be reprogrammed without executing a reset-start of the chip after the
flash memory has been programmed in boot mode. If all desired programming is done in a
single operation, such erasure processing is not necessary because all blocks are erased
before the chip enters the programming/erasure/other command waiting state.
⎯ In addition to the programming and erasure commands, commands for sum checking and
blank checking (checking for erasure) of the user MAT and user boot MAT, reading data
from the user MAT/user boot MAT, and acquiring current state information are provided.
Page 1444 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Note that the command for reading from the user MAT/user boot MAT can only read data that has
been programmed after automatic erasure of the entire user MAT and user boot MAT.
Start in boot mode
(reset in boot mode)
(Bit rate matching)
Reception of H'00, …, H'00
Bit rate matching
1.
5
f H'5
tion o
p
Rece
Reception of
inquiry/selection command
2.
Wait for inquiry/selection
command
3.
4.
Response to
inquiry/selection command
Erasure of entire
user MAT and
user boot MAT
Wait for
programming/erasure
command
Reception of
read/check command
Response to command
Erasure complete
Programming
complete
Execute processing
in response to inquiry/
selection command
Execute processing
in response to read/
check command
Reception of erasure
select command
Reception of programming
select command
Erasure block specification
Wait for erasure
block number
Transmission of programming
data by the host
Wait for
programming data
Figure 26.8 State Transitions in Boot Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1445 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.5.2
USB Boot Mode (SH7286 and SH7285)
The USB boot mode is for conducting programming and erasure of the user mat by sending
control commands and data for programming from an externally connected host via the USB.
For USB boot mode, a tool for transmitting the control commands and data to be programmed, as
well as the data itself, must be prepared on the host side. Figure 26.9 shows a system configuration
for USB boot mode. Interrupt requests generated in USB boot mode are ignored. On the system
side, ensure that interrupt requests are not generated.
This LSI
FWE*
1
11
MD1*, MD0*
Flash memory
PB10 (PUPD)
Host or
self-powered HUB
EXTAL
XTAL
USBEXTAL
USBXTAL
System clock
12 MHz
USB resonator
1.5 kΩ
Rs
D+
D-
USD+
Data
transmission
USB
Rs
VBUS
On-chip
RAM
USD-
PLLVSS
PC0
PLL external
circuit settings
Clock selection
VBUS
Note * FWE pin and mode pin input must satisfy the mode programming setup time (tMDS = 200 ns) when a reset is released.
Figure 26.9 System Configuration Diagram when Using USB Boot Mode
(1)
Features
• Bus power mode and self power mode are selectable.
• D+ pull-up control connection supported for the PBIO pin only.
• See table 26.8 for enumeration information.
Table 26.8 Enumeration Information
USB standard
Ver.2.0 (Full-speed)
Transfer modes
Control (in, out), Bulk (in, out)
Endpoint configuration
EP0 Control (in, out) 64 Bytes
Configuration 1
InterfaceNumber 0
AlternateSetting 0
EP1 Bulk (out) 64 Bytes
EP2 Bulk (in) 64 Bytes
Page 1446 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 26 Flash Memory (ROM)
State Transitions
State transitions that can follow booting-up in USB boot mode are shown in figure 26.10.
Initiation in boot mode
(reset in boot mode)
1.
Enumeration
5
f H'5
no
tio
cep
Re
2.
Waiting for inquiry-setting
commands
Reception of inquiry command
Execution of inquiry-setting
command processing
Response to inquiry command
Erasure of
whole user mat
3.
Reception of READ, CHECK, etc. commands
4.
Waiting for programming
and erasure commands
Response to command
Execution of READ, CHECK
command processing
(Reception of
erasure-selection command)
(Erasure complete)
(Programming
complete)
(Reception of programming-selection command)
Erase-block contains data.
(Reception of data to be programmed)
Waiting for data
to be programmed
Figure 26.10 USB Boot Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1447 of 1778
Section 26 Flash Memory (ROM)
(3)
SH7280 Group, SH7243 Group
1.
The boot program embedded in this LSI is initiated on transition to USB boot mode. On
initiation of the USB boot program in this LSI, enumeration with the host proceeds.
When enumeration has been completed, transmit one byte with the value H'55 from the
host. If normal reception of this byte is not possible, re-boot into boot mode.
2.
Inquiry information on the size, configuration, first address, state of support etc. for the
user mat is transmitted to the host.
3.
Once the inquiry process is complete, the whole user mat is automatically erased.
4.
A transition to waiting for programming or erasure follows automatic erasure of the user
mat. A transition to waiting for the data to be programmed follows reception of a
programming command. Erasure proceeds in the same way. Commands other than those
for programming and erasure are for sum checking and blank checking (checking of
erasure), reading from memory, and acquiring the current state information.
Points to Note Regarding Execution in USB Boot Mode
• A 48-MHz clock signal must be supplied to the USB module. Set the frequency of the external
clock or clock oscillator so that the dedicated USB clock (Uφ) runs at 48-MHz. For details,
refer to section 4, Clock Pulse Generator (CPG).
• Make the PC0 setting to select supply of the USB clock.
PC0 = 0: USBEXTAL and USBXTAL are used.
PC0 = 1: The system clock is used.
• When PC0 = 0, connect a 48-MHz oscillator across the USBEXTAL and USBXTAL pins.
• When PC0 = 1, connect USBEXTAL to the 0 level and leave USBXTAL open, and connect a
12-MHz oscillator across the EXTAL and XTAL pins.
• Use the PBIO pin for the D+ pull-up-control connection.
• To provide stabilization of the power supply during the programming and erasure of flash
memory, do not connect a cable via the password hub.
• If the USB cable is disconnected during the programming and erasure of flash memory, there
is a worst-case possibility of permanent destruction of the LSI circuit, so be particularly careful
on this point.
• In bus-power mode, transitions to software-standby mode as a low-power-consumption mode
do not proceed even if the USB enters suspension mode.
Page 1448 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
26.5.3
Section 26 Flash Memory (ROM)
User Program Mode
The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be
programmed/erased.)
Programming/erasing is executed by downloading the program in the microcontroller.
The overview flow is shown in figure 26.11.
High voltage is applied to internal flash memory during the programming/erasing processing.
Therefore, transition to reset must not be executed. Doing so may cause damage or destroy flash
memory. If reset is executed accidentally, the reset signal must be released after the reset input
period, which is longer than the normal 100 μs.
For details on the programming procedure, see the description in section 26.5.3 (2), Programming
Procedure in User Program Mode. For details on the erasing procedure, see the description in
section 26.5.3 (3), Erasing Procedure in User Program Mode.
For the overview of a processing that repeats erasing and programming by downloading the
programming program and the erasing program in separate on-chip ROM areas using FTDAR, see
the description in section 26.5.3 (4), Erasing and Programming Procedure in User Program Mode.
Programming/erasing
start
1. Inputting high level to the FWE pin sets the
FWE bit to 1.
2. Programming/erasing is executed only in
the on-chip RAM. However, if the program data
is in a consecutive area and can be accessed
by the MOV.L instruction of the CPU like
SRAM/ROM, the program data can be in an
external space.
When programming,
program data is prepared
FWE=1 ?
No
Yes
Programming/erasing
procedure program is
transferred to the on-chip
RAM and executed
Programming/erasing
end
Figure 26.11 Programming/Erasing Overview Flow
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1449 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(1)
On-Chip RAM Address Map when Programming/Erasing is Executed
Parts of the procedure program that are made by the user, like download request,
programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM.
All of the on-chip program that is to be downloaded is in on-chip RAM. Note that on-chip RAM
must be controlled so that these parts do not overlap.
Figure 26.12 shows the program area to be downloaded.
Area that can be
used by user
Area to be
downloaded
(Size: 3 Kbytes)
Unusable area in
programming/erasing
processing period
Address
RAMTOP (H'FFFF8000)
DPFR
FTDAR setting
(Return value: 1 byte)
System use area
(15 bytes)
FTDAR setting + 16
Programming/
erasing entry
Initialization
process entry
FTDAR setting + 32
Initialization +
programming program
or Initialization +
erasing program
FTDAR setting + 3072
Area that can be
used by user
Figure 26.12 RAM Map after Download
Page 1450 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(2)
Section 26 Flash Memory (ROM)
Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 26.13.
1
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(2.1)
Set FKEY to H'5A
(2.9)
Set FKEY to H'A5
(2.2)
Set parameter to R4 and
R5 (FMPAR and FMPDR)
(2.10)
After clearing VBR,
set SCO to 1 and
execute download
Programming
JSR FTDAR setting+16
(2.11)
(2.3)
Clear FKEY to 0
(2.4)
Initialization
Download error processing
(2.6)
Initialization
JSR FTDAR setting+32
(2.7)
Yes
Yes
No
No
Set the FPEFEQ and
FUBRA parameters
FPFR = 0?
(2.12)
FPFR = 0?
(2.5)
DPFR = 0?
Yes
Programming
Download
Start programming
procedure program
Required data
programming is
completed?
No
Clear FKEY and
programming
error processing
(2.13)
Yes
Clear FKEY to 0
(2.14)
End programming
procedure program
(2.8)
No
Initialization error processing
1
Figure 26.13 Programming Procedure
The details of the programming procedure are described below. The procedure program must be
executed in an area other than the flash memory to be programmed. Especially the part where the
SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify
Iφ = Bφ = Pφ as the frequency division ratio of an internal clock (Iφ), a bus clock (Bφ), and a
peripheral clock (Pφ) through the frequency control register (FRQCR).
After downloading has been completed and the SCO bit has been cleared to 0, FRQCR can be
changed to a desired value.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1451 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 26.8.2, Areas for Storage of the Procedural Program
and Data for Programming.
The following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing has not been executed, carry out
erasing before writing.
256-byte programming is performed in one program processing. When more than 256-byte
programming is performed, programming destination address/program data parameter is updated
in 256-byte units and programming is repeated.
When less than 256-byte programming is performed, data must total 256 bytes by adding the
invalid data. If the invalid data to be added is H'FF, the program processing period can be
shortened.
(2.1) Select the on-chip program to be downloaded
When the PPVS bit of FPCS is set to 1, the programming program is selected.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
(2.2) Write H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a
download request.
(2.3) VBR is set to 0 and 1 is written to the SCO bit of FCCS, and then download is executed.
VBR must always be set to H'80000000 before setting the SCO bit to 1.
To write 1 to the SCO bit, the following conditions must be satisfied.
1. H'A5 is written to FKEY.
2. The SCO bit writing is executed in the on-chip RAM.
Page 1452 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
When the SCO bit is set to 1, download is started automatically. When execution returns to the
user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of the DPFR parameter. Before
the SCO bit is set to 1, incorrect decision must be prevented by setting the DPFR parameter,
that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value
other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcontroller processing, so VBR
need to be set to H'80000000. Thirty-two NOP instructions are executed immediately after the
instructions that set the SCO bit to 1.
1. The user MAT space is switched to the on-chip program storage area.
2. After the selection condition of the download program and the address set in FTDAR are
checked, the transfer processing is executed starting to the on-chip RAM address specified
by FTDAR.
3. The SCO bits in FCCS, FPCS, and FECS are cleared to 0.
4. The return value is set to the DPFR parameter.
5. After the on-chip program storage area is returned to the user MAT space, execution
returns to the user procedure program.
After download is completed and the user procedure program is running, the VBR setting can
be changed.
The notes on download are as follows.
In the download processing, the values of the general registers of the CPU are retained.
During the download processing, interrupts must not be generated. For details on the
relationship between download and interrupts, see section 26.7.2, Interrupts during
Programming/Erasing.
Since a stack area of maximum 256 bytes is used, an area of at least 128 bytes must be saved
before setting the SCO bit to 1.
If flash memory is accessed by the DMAC during downloading, operation cannot be
guaranteed. Therefore, access by the DMAC must not be executed.
(2.4) FKEY is cleared to H'00 for protection.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1453 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
(2.5) The value of the DPFR parameter must be checked to confirm the download result.
A recommended procedure for confirming the download result is shown below.
1. Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
2. If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
3. If the value of the DPFR parameter is different from before downloading, check the SS bit
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY register setting were normal, respectively.
(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is
set to the FUBRA parameter for initialization.
1. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
R4). The settable FPEFEQ parameter is Iφ ≤ 50 MHz.
When the frequency is set out of this range, an error is returned to the FPFR parameter of
the initialization program and initialization is not performed. For details on the frequency
setting, see the description in section 26.4.3 (2.1), Flash Programming/Erasing Frequency
Parameter (FPEFEQ: General Register R4 of CPU).
2. The start address in the user branch destination is set to the (FUBRA: CPU general register
R5) parameter.
When the user branch processing is not required, 0 must be set to FUBRA.
When the user branch is executed, the branch destination is executed in flash memory other
than the one that is to be programmed. The area of the on-chip program that is downloaded
cannot be set.
The program processing must be returned from the user branch processing by the RTS
instruction.
See the description in section 26.4.3 (2.2), Flash User Branch Address Setting Parameter
(FUBRA: General Register R5 of CPU).
Page 1454 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2.7) Initialization
When a programming program is downloaded, the initialization program is also downloaded to
on-chip RAM. There is an entry point of the initialization program in the area from (download
start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed
by using the following steps.
MOV.L
#DLTOP+32,R1
; Set entry address to R1
JSR
@R1
; Call initialization routine
NOP
1. The general registers other than R0 are saved in the initialization program.
2. R0 is a return value of the FPFR parameter.
3. Since the stack area is used in the initialization program, a stack area of 256 bytes or more
must be reserved in RAM.
4. Interrupts can be accepted during the execution of the initialization program. However, the
program storage area and stack area in on-chip RAM and register values must not be
destroyed.
(2.8) The return value of the initialization program, FPFR (general register R0) is checked.
(2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming.
(2.10) The parameter which is required for programming is set.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register R5. The start address of the program data storage area (FMPDR) is set to general
register R4.
1. FMPAR setting
FMPAR specifies the programming destination start address. When an address other than
one in the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 256 bytes, the lower eight bits (MOA7 to MOA0) must be in the 256-byte
boundary of H'00.
2. FMPDR setting
If the storage destination of the program data is flash memory, even when the program
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to on-chip RAM and
then programming must be executed.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1455 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2.11) Programming
There is an entry point of the programming program in the area from (download start address
set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is
executed by using the following steps.
MOV.L
#DLTOP+16,R1
; Set entry address to R1
JSR
@R1
; Call programming routine
NOP
1. The general registers other than R0 are saved in the programming program.
2. R0 is a return value of the FPFR parameter.
3. Since the stack area is used in the programming program, a stack area of maximum 128
bytes must be reserved in RAM.
(2.12) The return value in the programming program, FPFR (general register R0) is checked.
(2.13) Determine whether programming of the necessary data has finished.
If more than 256 bytes of data are to be programmed, specify FMPAR and FMPDR in 256byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by
256 bytes and update the programming data pointer correctly. If an address which has already
been programmed is written to again, not only will a programming error occur, but also flash
memory will be damaged.
(2.14) After programming finishes, clear FKEY and specify software protection.
If this LSI is restarted by a power-on reset immediately after user MAT programming has
finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 μs.
Page 1456 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(3)
Section 26 Flash Memory (ROM)
Erasing Procedure in User Program Mode
The procedures for download, initialization, and erasing are shown in figure 26.14.
Start erasing procedure
program
Set FRQCR to satisfy
Iφ = Bφ = Pφ
Select on-chip program
to be downloaded and
set download destination
by FTDAR
1
(3.1)
Set FKEY to H'5A
After clearing VBR,
set SCO to 1 and
execute download
Erasing
Download
Set FKEY to H'A5
Clear FKEY to 0
Set FEBS parameter
(3.2)
Erasing
JSR FTDAR setting + 16
(3.3)
Yes
DPFR = 0?
Yes
No
Download error processing
No
Initialization
No
Clear FKEY and erasing
error processing
Required block
erasing is
completed?
Set the FPEFEQ and
FUBRA parameters
(3.5)
Yes
Clear FKEY to 0
Initialization
JSR FTDAR setting + 32
FPFR = 0 ?
(3.4)
FPFR = 0 ?
(3.6)
End erasing
procedure program
No
Yes Initialization error processing
1
Figure 26.14 Erasing Procedure
The details of the erasing procedure are described below. The procedure program must be
executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in onchip RAM.
The frequency division ratio of an internal clock (Iφ), a bus clock (Bφ), and a peripheral clock (Pφ)
is specified as Iφ = Bφ = Pφ ≤ 50 MHz by the frequency control register (FRQCR).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1457 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
After downloading has been completed and the SCO bit has been cleared to 0, FRQCR can be
changed to a desired value.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 26.8.2, Areas for Storage of the Procedural Program
and Data for Programming.
For the downloaded on-chip program area, see the RAM map for programming/erasing in figure
26.11.
A single divided block is erased by one erasing processing. For block divisions, see figure 26.4.
To erase two or more blocks, update the erase block number and perform the erasing processing
for each block.
(3.1) Select the on-chip program to be downloaded and the download destination address
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, see the description in section 26.5.3
(2), Programming Procedure in User Program Mode.
(3.2) Set the FEBS parameter necessary for erasure
Set the erase block number of the user MAT in the flash erase block select parameter (FEBS:
general register R4). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
Page 1458 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(3.3) Erasure
Similar to as in programming, there is an entry point of the erasing program in the area from
(download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called
and erasing is executed by using the following steps.
MOV.L
#DLTOP+16,R1
; Set entry address to R1
JSR
@R1
; Call erasing routine
NOP
1. The general registers other than R0 are saved in the erasing program.
2. R0 is a return value of the FPFR parameter.
3. Since the stack area is used in the erasing program, a stack area of maximum 128 bytes
must be reserved in RAM.
(3.4) The return value in the erasing program, FPFR (general register R0) is checked.
(3.5) Determine whether erasure of the necessary blocks has finished.
If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to
(3.5). Blocks that have already been erased can be erased again.
(3.6) After erasure finishes, clear FKEY and specify software protection.
If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished,
secure a reset period (period of RES = 0) that is at least as long as the normal 100 μs.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1459 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(4)
Erasing and Programming Procedure in User Program Mode
By changing the on-chip RAM address of the download destination in FTDAR, the erasing
program and programming program can be downloaded to separate on-chip RAM areas.
Figure 26.15 shows an example of repetitively executing RAM emulation, erasing, and
programming.
1
Set FTDAR to H'00
(Specify H'FFF81000 as
download destination)
Download erasing program
Programming program
download
Initialize erasing program
Set FTDAR to H'01
(Specify H'FFF82000 as
download destination)
Download programming
program
Initialize programming
program
Emulation/Erasing/Programming
Erasing program
download
Start procedure program
Erase relevant block
(execute erasing program)
Set FMPDR to H'FFF86000 to
program relevant block
(execute programming program)
Confirm operation
End?
No
Yes
End procedure program
1
Figure 26.15 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming
(Overview)
Page 1460 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Download and initialization are performed only once at the beginning.
In this kind of operation, note the following:
1. Be careful not to destroy on-chip RAM with overlapped settings.
In addition to the erasing program area and programming program area, areas for the user
procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make
settings that will overwrite data in these areas.
2. Be sure to initialize both the erasing program and programming program.
Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both
the erasing program and the programming program. Initialization must be executed for
both entry addresses: (download start address for erasing program) + 32 bytes
(H'FFF81020 in this example) and (download start address for programming program) + 32
bytes (H'FFF82000 in this example).
26.5.4
User Boot Mode (SH7286 and SH7285)
This LSI has user boot mode which is initiated with different mode pin settings than those in user
program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that
uses the on-chip SCI.
Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the
user boot MAT is only enabled in boot mode or programmer mode.
In addition, the user boot mode is not available in the SH7243.
(1)
User Boot Mode Initiation
For the mode pin settings to start up user boot mode, see table 26.1.
When the reset start is executed in user boot mode, the check routine for flash-memory related
registers runs on the on-chip RAM. NMI and all other interrupts cannot be accepted. Neither can
the AUD be used in this period. This period is 100 μs while operating at an internal frequency of
40 MHz.
Next, processing starts from the execution start address of the reset vector in the user boot MAT.
At this point, H'AA is set to the flash MAT select register (FMATS) because the execution MAT
is the user boot MAT.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1461 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2)
User MAT Programming in User Boot Mode
For programming the user MAT in user boot mode, additional processings made by setting
FMATS are required: switching from user-boot-MAT selection state to user-MAT selection
state, and switching back to user-boot-MAT selection state after programming completes.
Figure 26.16 shows the procedure for programming the user MAT in user boot mode.
Start programming
procedure program
1
Select on-chip program
to be downloaded and
set download destination
by FTDAR
Set FMATS to value other than
H'AA to select user MAT
Set FKEY to H'5A
Yes
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
Initialization
JSR FTDAR setting+32
FPFR=0 ?
Set parameter to R4 and
R5 (FMPAR and FMPDR)
Programming
JSR FTDAR setting+16
Programming
Clear FKEY to 0
User-MAT selection state
Download
After clearing VBR,
set SCO to 1 and
execute download
DPFR=0 ?
Initialization
User-boot-MAT selection state
Set FKEY to H'A5
MAT
switchover
FPFR=0 ?
No
Yes Clear FKEY and programming
error processing*
No
Required data
programming is
completed?
Yes
No
Clear FKEY to 0
Yes Initialization error processing
Set FMATS to H'AA to
select user boot MAT
1
User-boot-MAT
selection state
MAT
switchover
End programming
procedure program
Note: * The MAT must be switched by FMATS
to perform the programming error
processing in the user boot MAT.
Figure 26.16 Procedure for Programming User MAT in User Boot Mode
Page 1462 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
The difference between the programming procedures in user program mode and user boot
mode is whether the MAT is switched or not as shown in figure 26.16.
In user boot mode, the user boot MAT can be seen in the flash memory space with the user
MAT hidden in the background. The user MAT and user boot MAT are switched only while
the user MAT is being programmed. Because the user boot MAT is hidden while the user
MAT is being programmed, the procedure program must be located in an area other than flash
memory. After programming finishes, switch the MATs again to return to the first state.
MAT switchover is enabled by writing a specific value to FMATS. However note that while
the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not
allowed until MAT switching is completely finished, and if an interrupt occurs, from which
MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance
with the description in section 26.7.1, Switching between User MAT and User Boot MAT.
Except for MAT switching, the programming procedure is the same as that in user program
mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 26.8.2, Areas for Storage of the Procedural
Program and Data for Programming.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1463 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(3)
User MAT Erasing in User Boot Mode
For erasing the user MAT in user boot mode, additional processings made by setting FMATS
are required: switching from user-boot-MAT selection state to user-MAT selection state, and
switching back to user-boot-MAT selection state after erasing completes.
Figure 26.17 shows the procedure for erasing the user MAT in user boot mode.
Start erasing
procedure program
1
Select on-chip program
to be downloaded and
set download destination
by FTDAR
Set FMATS to value other
than H'AA to select user MAT
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
Initialization
JSR FTDAR setting+32
FPFR=0 ?
Set FEBS parameter
Programming
JSR FTDAR setting+16
Erasing
Clear FKEY to 0
Yes
MAT
switchover
Set FKEY to H'5A
User-MAT selection state
Download
After clearing VBR,
set SCO to 1 and
execute download
DPFR=0 ?
Initialization
User-boot-MAT selection state
Set FKEY to H'A5
FPFR=0 ?
No
No
Yes Clear FKEY and erasing
error processing*
Required
block erasing is
completed?
Yes
No
Clear FKEY to 0
Yes Initialization error processing
1
Set FMATS to H'AA to
select user boot MAT
User-boot-MAT
selection state
MAT
switchover
End erasing
procedure program
Note: * The MAT must be switched by FMATS to perform the
erasing error processing in the user boot MAT.
Figure 26.17 Procedure for Erasing User MAT in User Boot Mode
Page 1464 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
The difference between the erasing procedures in user program mode and user boot mode depends
on whether the MAT is switched or not as shown in figure 26.17.
MAT switching is enabled by writing a specific value to FMATS. However note that while the
MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until
MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt
vector is read from is undetermined. Perform MAT switching in accordance with the description
in section 26.7.1, Switching between User MAT and User Boot MAT.
Except for MAT switching, the erasing procedure is the same as that in user program mode.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 26.8.2, Areas for Storage of the Procedural Program
and Data for Programming.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1465 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
26.6
Protection
There are three kinds of flash memory program/erase protection: hardware, software, and error
protection.
26.6.1
Hardware Protection
Programming and erasing of flash memory is forcibly disabled or suspended by hardware
protection. In this state, the downloading of an on-chip program and initialization of the flash
memory are possible. However, an activated program for programming or erasure cannot program
or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR
parameter.
Table 26.9 Hardware Protection
Function to be Protected
Item
Description
FWE-pin protection The input of a low-level signal on the FWE
pin clears the FWE bit of FCCS and the LSI
enters a programming/erasing-protected
state.
Reset/standby
protection
Page 1466 of 1778
Download
Programming/
Erasure
—
√
•
√
A power-on reset (including a power-on
reset by the WDT) and entry to standby
mode initializes the programming/erasing
interface registers and the LSI enters a
programming/erasing-protected state.
•
Resetting by means of the RES pin after
power is initially supplied will not make
the LSI enter the reset state unless the
RES pin is held low until oscillation has
stabilized. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width that is specified in the
section on AC characteristics. If the LSI is
reset during programming or erasure,
data in the flash memory is not
guaranteed. In this case, execute erasure
and then execute programming again.
√
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
26.6.2
Section 26 Flash Memory (ROM)
Software Protection
Software protection is set up in any of two ways: by disabling the downloading of on-chip
programs for programming and erasing, and by means of a key code.
Table 26.10 Software Protection
Function to be Protected
Item
Description
Download
Programming/
Erasure
Protection by the
SCO bit
Clearing the SCO bit in FCCS disables
downloading of the programming/erasing
program, thus making the LSI enter a
programming/erasing-protected state.
√
√
Protection by FKEY
Downloading and programming/erasing
√
are disabled unless the required key code
is written in FKEY. Different key codes are
used for downloading and for
programming/erasing.
√
26.6.3
Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcontroller getting out of control during programming/erasing of the flash
memory or operations that are not in accordance with the established procedures for
programming/erasing. Aborting programming or erasure in such cases prevents damage to the
flash memory due to excessive programming or erasing.
If the microcontroller malfunctions during programming/erasing of the flash memory, the FLER
bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or
erasure.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1467 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
The FLER bit is set to 1 in the following conditions:
• When the relevant bank area of flash memory is read during programming/erasing (including a
vector read or an instruction fetch)
• When a SLEEP instruction (including software standby mode) is executed during
programming/erasing
Error protection is cancelled (FLER bit is cleared) only by a power-on reset.
Note that the reset signal should only be released after providing a reset input over a period longer
than the normal 100 μs. Since high voltages are applied during programming/erasing of the flash
memory, some voltage may still remain even after the error protection state has been entered. For
this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset
period so that the charge is released.
The state-transition diagram in figure 26.18 shows transitions to and from the error protection
state.
Program mode
Erase mode
Read disabled
Programming/erasing
enabled
FLER=0
Reset
(Hardware protection)
RES = 0
Er
Error occurred
ror
0
S=
RE
oc
cu
oft rred
wa
re
sta
(S
Read enabled
Programming/erasing disabled
FLER=0
RES=0
Programming/erasing interface
register is in its initial state.
nd
by
)
Error protection mode
Read enabled
Programming/erasing disabled
FLER=1
Software standby mode
Error protection mode
(Software standby)
Read disabled
Cancel
Programming/erasing disabled
software standby mode
FLER=1
Programming/erasing interface
register is in its initial state.
Figure 26.18 Transitions to and from Error Protection State
Page 1468 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
26.7
Usage Notes
26.7.1
Switching between User MAT and User Boot MAT
Section 26 Flash Memory (ROM)
It is possible to switch between the user MAT and user boot MAT. However, the following
procedure is required because these MATs are allocated to address 0.
(Switching to the user boot MAT disables programming and erasing. Programming of the user
boot MAT must take place in boot mode or programmer mode.)
1. MAT switching by FMATS should always be executed from the on-chip RAM. The SH
microcontroller prefetches execution instructions. Therefore, a switchover during program
execution in the user MAT causes an instruction code in the user MAT to be prefetched or an
instruction in the newly selected user boot MAT to be prefetched, thus resulting in unstable
operation.
2. To ensure that the MAT that has been switched to is accessible, execute thirty-two NOP
instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this
prevents access to the flash memory during MAT switching).
3. If an interrupt occurs during switching, there is no guarantee of which memory MAT is being
accessed.
Always mask the maskable interrupts before switching MATs. In addition, configuring the
system so that NMI interrupts do not occur during MAT switching is recommended.
4. After the MATs have been switched, take care because the interrupt vector table will also have
been switched.
If the same interrupt processings are to be executed before and after MAT switching or
interrupt requests cannot be disabled, transfer the interrupt processing routine to on-chip RAM,
and use the VBR setting to place the interrupt vector table in on chip RAM. In this case, make
sure the VBR setting change does not conflict with the interrupt occurrence.
5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user
boot MAT, do not access addresses exceeding the 12-Kbyte memory space. If access goes
beyond the 12-Kbyte space, the values read are undefined.
6. ROM cache must be flushed after the MATs have been switched.
Disable (flush) the instructions or data cached in the ROM cache by writing 1 to the RCF bit in
RCCR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1469 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Procedure for
switching to the
user boot MAT
Procedure for
switching to
the user MAT
Procedure for switching to the user boot MAT
(1) Mask interrupts.
(2) Write H'AA to FMATS.
(3) Write H'00000009 to RCCR.
(4) Execute thirty-two NOP instructions before
accessing the user boot MAT.
Procedure for switching to the user MAT
(1) Mask interrupts.
(2) Write a value other than H'AA to FMATS.
(3) Write H'00000009 to RCCR.
(4) Execute thirty-two NOP instructions before accessing
the user MAT.
Figure 26.19 Switching between User MAT and User Boot MAT
26.7.2
Interrupts during Programming/Erasing
(1)
Download of On-Chip Program
(a)
VBR Setting Change
Before downloading the on-chip program, VBR must be set to H'80000000. If VBR is set to a
value other than H'80000000, the interrupt vector table is placed in the user MAT (FMATS is not
H'AA) or the user boot MAT (FMATS is H'AA) on setting H'80000000 to VBR.
When VBR setting change conflicts with interrupt occurrence, whether the vector table before or
after VBR is changed is referenced may cause an error.
Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a
vector table to be referenced when VBR is H'00000000 (initial value) at the start of the user MAT
or user boot MAT.
Page 1470 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 26 Flash Memory (ROM)
SCO Download Request and Interrupt Request
Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in
FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover.
Operation when the SCO download request and interrupt request conflicts is described below.
1. Contention between SCO download request and interrupt request
Figure 26.18 shows the timing of contention between execution of the instruction that sets the
SCO bit in FCCS to 1 and interrupt acceptance.
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
Interrupt acceptance
n
n+1
n+2
n+3
n+4
Fetch
Decoding
Execution
Execution
Execution
(a)
(b)
(a) When the interrupt is accepted at the (n + 1) cycle or before
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle or later
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Figure 26.20 Timing of Contention between SCO Download Request and Interrupt Request
2. Generation of interrupt requests during downloading
Ensure that interrupts are not generated during downloading that is initiated by the SCO bit.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1471 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2)
Interrupts during Programming/Erasing
Do not generate NMI, IRQ, and all other interrupts during programming/erasing of the
downloaded on-chip program.
26.7.3
(1)
Other Notes
Download Time of On-Chip Program
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock
frequency is 40 MHz, the download for each program takes approximately 10 ms at maximum.
(2)
User Branch Processing Intervals
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 26.11 lists the maximum and minimum intervals for initiating
the user branch processing when the CPU clock frequency is 40 MHz.
Table 26.11 Initiation Intervals of User Branch Processing
Processing Name
Maximum Interval
Programming
1.6 ms
Erasing
12 ms
However, when operation is done with CPU clock of 40 MHz, maximum and minimum values of
the time until first user branch processing are as shown in table 26.12.
Table 26.12 Initial User Branch Processing Time
Processing Name
Maximum
Programming
1.6 ms
Erasing
12 ms
(3)
Write to Flash-Memory Related Registers by DMAC
While an instruction in on-chip RAM is being executed, the DMAC can write to the SCO bit in
FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure
that these registers are not accidentally written to, otherwise an on-chip program may be
downloaded and destroy RAM or a MAT switchover may occur and the CPU get out of control.
Page 1472 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(4)
Section 26 Flash Memory (ROM)
State in which Interrupts are Ignored
In the following modes or period, interrupt requests are ignored; they are not executed and the
interrupt sources are not retained.
• Boot mode
• Programmer mode
(5)
Compatibility with Programming/Erasing Program of Conventional F-ZTAT SH
Microcontroller
A programming/erasing program for flash memory used in the conventional F-ZTAT SH
microcontroller which does not support download of the on-chip program by a SCO transfer
request cannot run in this LSI.
Be sure to download the on-chip program to execute programming/erasing of flash memory in this
LSI.
(6)
Monitoring Runaway by WDT
Unlike the conventional F-ZTAT SH microcontroller, no countermeasures are available for a
runaway by WDT during programming/erasing by the downloaded on-chip program.
Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for
WDT while taking the programming/erasing time into consideration as required.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1473 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
26.8
Supplementary Information
26.8.1
Specifications of the Standard Serial Communications Interface in Boot Mode
The boot program activated in boot mode communicates with the host via the on-chip SCI of the
LSI. The specifications of the serial communications interface between the host and the boot
program are described below.
(1)
States of Boot Program
The boot program has three states.
1. Bit-rate matching state
In this state, the boot program adjusts the bit rate to match that of the host. When the chip
starts up in boot mode, the boot program is activated and enters the bit-rate matching state, in
which it receives commands from the host and adjusts the bit rate accordingly. After bit-rate
matching is complete, the boot program proceeds to the inquiry-and-selection state.
2. Inquiry-and-selection state
In this state, the boot program responds to inquiry commands from the host. The device, clock
mode, and bit rate are selected in this state. After making these selections, the boot program
enters the programming/erasure state in response to the transition-to-programming/erasure
state command. The boot program transfers the erasure program to RAM and executes erasure
of the user MAT and user boot MAT before it enters the programming/erasure state.
3. Programming/erasure state
In this state, programming/erasure are executed. The boot program transfers the program for
programming/erasure to RAM in line with the command received from the host and executes
programming/erasure. It also performs sum checking and blank checking as directed by the
respective commands.
Page 1474 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Figure 26.21 shows the flow of processing by the boot program.
Reset
Bit rate matching state
Bit rate matching
Inquiry-and-selection state
Wait for inquiry and
selection
Inquiry
Inquiry
processing
Selection
Selection
processing
Enter
programming/erasure state
Programming/erasure state
Erase
user MAT/use boot MAT
Wait for programming/erasure
selection
Programming
Programming
processing
Erasure
Erasure
processing
Checking
Checking
processing
Figure 26.21 Flow of Processing by the Boot Program
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1475 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(2)
Bit-Rate Matching State
In bit-rate matching, the boot program measures the low-level intervals in a signal carrying H'00
data that is transmitted by the host, and calculates the bit rate from this. The bit rate can be
changed by the new-bit-rate selection command. On completion of bit-rate matching, the boot
program goes to the inquiry and selection state. The sequence of processing in bit-rate matching is
shown in figure 26.22.
Host
Boot program
H'00 (max. 30 times)
Measures the
length of one bit
H'00 (bit rate matching complete)
H'55
H'E6 (response)
H'FF (error)
Figure 26.22 Sequence of Bit-Rate Matching
(3)
Communications Protocol
Formats in the communications protocol between the host and boot program after completion of
the bit-rate matching are as follows.
1. One-character command or one-character response
A command or response consisting of a single character used for an inquiry or the ACK code
indicating normal completion.
2. n-character command or n-character response
A command or response that requires n bytes of data, which is used as a selection command or
response to an inquiry. The length of programming data is treated separately below.
3. Error response
Response to a command in case of an error: two bytes, consisting of the error response and
error code.
Page 1476 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
4. 256-byte programming command
The command itself does not include data-size information. The data length is known from the
response to the command for inquiring about the programming size.
5. Response to a memory reading command
This response includes four bytes of size information.
One-character command
or one-character response
n-character command
or n-character response
Command or response
Data
Size
Checksum
Command or response
Error response
Error code
Error response
256-byte
programming command
Address
Data (n bytes)
Command
Response to
memory read command
Data size
Checksum
Data
Response
Checksum
Figure 26.23 Formats in the Communications Protocol
• Command (1 byte): Inquiry, selection, programming, erasure, checking, etc.
• Response (1 byte): Response to an inquiry
• Size (one or two bytes): The length of data for transfer, excluding the command/response, size,
and checksum.
• Data (n bytes): Particular data for the command or response
• Checksum (1 byte): Set so that the total sum of byte values from the command code to the
checksum is H'00.
• Error response (1 byte): Error response to a command
• Error code (1 byte): Indicates the type of error.
• Address (4 bytes): Address for programming
• Data (n bytes): Data to be programmed. "n" is known from the response to the command used
to inquire about the programming size.
• Data size (4 bytes): Four-byte field included in the response to a memory reading command.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1477 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(4)
Inquiry-and-Selection State
In this state, the boot program returns information on the flash ROM in response to inquiry
commands sent from the host, and selects the device, clock mode, and bit rate in response to the
respective selection commands.
The inquiry and selection commands are listed in table 26.13.
Table 26.13 Inquiry and Selection Commands
Command
Command Name
Function
H'20
Inquiry on supported
devices
Requests the device codes and their respective boot
program names.
H'10
Device selection
Selects a device code.
H'21
Inquiry on clock modes Requests the number of available clock modes and their
respective values.
H'11
Clock-mode selection
Selects a clock mode.
H'22
Inquiry on frequency
multipliers
Requests the number of clock signals for which frequency
multipliers and divisors are selectable, the number of
multiplier and divisor settings for the respective clocks, and
the values of the multipliers and divisors.
H'23
Inquiry on operating
frequency
Requests the minimum and maximum values for operating
frequency of the main clock and peripheral clock.
H'24
Inquiry on user boot
MATs
Requests the number of user boot MAT areas along with
their start and end addresses.
H'25
Inquiry on user MATs
Requests the number of user MAT areas along with their
start and end addresses.
H'26
Inquiry on erasure
blocks
Requests the number of erasure blocks along with their
start and end addresses.
H'27
Inquiry on
programming size
Requests the unit of data for programming.
H'3F
New bit rate selection
Selects a new bit rate.
H'40
Transition to
programming/erasure
state
On receiving this command, the boot program erases the
user MAT and user boot MAT and enters the
programming/erasure state.
H'4F
Inquiry on boot
program state
Requests information on the current state of boot
processing.
Page 1478 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
The selection commands should be sent by the host in this order: device selection (H'10), clockmode selection (H'11), new bit rate selection (H'3F). These commands are mandatory. If the same
selection command is sent two or more times, the command that is sent last is effective.
All commands in the above table, except for the boot program state inquiry command (H'4F), are
valid until the boot program accepts the transition-to-programming/erasure state command (H'40).
That is, until the transition command is accepted, the host can continue to send commands listed in
the above table until it has made the necessary inquiries and selections. The host can send the boot
program state inquiry command (H'4F) even after acceptance of the transition-toprogramming/erasure state command (H'40) by the boot program.
(a)
Inquiry on Supported Devices
In response to the inquiry on supported devices, the boot program returns the device codes of the
devices it supports and the product names of their respective boot programs.
Command
H'20
• Command H'20 (1 byte): Inquiry on supported devices
Response
H'30
Size
Number of
Device code
No. of devices
Product name
characters
…
SUM
• Response H'30 (1 byte): Response to the inquiry on supported devices
• Size (1 byte): The length of data for transfer excluding the command code, this field (size), and
the checksum. Here, it is the total number of bytes taken up by the number of devices, number
of characters, device code, and product name fields.
• Number of devices (1 byte): The number of device models supported by the boot program
embedded in the microcontroller.
• Number of characters (1 byte): The number of characters in the device code and product name
fields.
• Device code (4 bytes): Device code of a supported device (ASCII encoded)
• Product name (n bytes): Product code of the boot program (ASCII encoded)
• SUM (1 byte): Checksum
This is set so that the total sum of all bytes from the command code to the checksum is H'00.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1479 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(b)
Device Selection
In response to the device selection command, the boot program sets the specified device as the
selected device. The boot program will return the information on the selected device in response to
subsequent inquiries.
Command
H'10
Size
Device code
SUM
• Command H'10 (1 byte): Device selection
• Size (1 byte): Number of characters in the device code (fixed at 2)
• Device code (4 bytes): A device code that was returned in response to an inquiry on supported
devices (ASCII encoded)
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to device selection
This is the ACK code and is returned when the specified device code matches one of the
supported devices.
Error
response
H'90
ERROR
• Error response H'90 (1 byte): Error response to device selection
• ERROR (1 byte): Error code
H'11: Sum-check error
H'21: Non-matching device code
Page 1480 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(c)
Section 26 Flash Memory (ROM)
Inquiry on Clock Modes
In response to the inquiry on clock modes, the boot program returns the number of available clock
modes.
Command
H'21
• Command H'21 (1 byte): Inquiry on clock modes
Response
•
•
•
•
(d)
H'31
Size
Mode
…
SUM
Response H'31 (1 byte): Response to the inquiry on clock modes
Size (1 byte): The total length of the number of modes and mode data fields
Mode (1 byte): Selectable clock mode (example: H'01 = clock mode 1)
SUM (1 byte): Checksum
Clock-Mode Selection
In response to the clock-mode selection command, the boot program sets the specified clock
mode. The boot program will return the information on the selected clock mode in response to
subsequent inquiries.
Command
•
•
•
•
H'11
Size
Mode
SUM
Command H'11 (1 byte): Clock mode selection
Size (1 byte): Number of characters in the clock-mode field (fixed at 1)
Mode (1 byte): A clock mode returned in response to the inquiry on clock modes
SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to clock mode selection
This is the ACK code and is returned when the specified clock-mode matches one of the
available clock modes.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1481 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Error
response
H'91
ERROR
• Error response H'91 (1 byte): Error response to clock mode selection
• ERROR (1 byte): Error code
H'11: Sum-check error
H'21: Non-matching clock mode
(e)
Inquiry on Frequency Multipliers
In response to the inquiry on frequency multipliers, the boot program returns information on the
settable frequency multipliers or divisors.
Command
H'22
• Command H'22 (1 byte): Inquiry on frequency multipliers
Response
H'32
Size
Number of
operating clocks
No. of multipliers Multiplier
…
…
SUM
• Response H'32 (1 byte): Response to the inquiry on frequency multipliers
• Size (1 byte): The total length of the number of operating clocks, number of multipliers, and
multiplier fields.
• Number of operating clocks (1 byte): The number of operating clocks for which multipliers
can be selected
(for example, if frequency multiplier settings can be made for the frequencies of the main and
peripheral operating clocks, the value should be H'02).
• Number of multipliers (1 byte): The number of multipliers selectable for the operating
frequency of the main or peripheral modules
• Multiplier (1 byte):
Multiplier: Numerical value in the case of frequency multiplication (e.g. H'04 for ×4)
Divisor: Two’s complement negative numerical value in the case of frequency division (e.g.
H'FE [-2] for ×1/2)
As many multiplier fields are included as there are multipliers or divisors, and combinations of
the number of multipliers and multiplier fields are repeated as many times as there are
operating clocks.
Page 1482 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
• SUM (1 byte): Checksum
(f)
Inquiry on Operating Frequency
In response to the inquiry on operating frequency, the boot program returns the number of
operating frequencies and the maximum and minimum values.
Command
H'23
• Command H'23 (1 byte): Inquiry on operating frequency
Response
H'33
Size
Operating freq. (min)
Number of operating clocks
Operating freq. (max)
…
SUM
• Response H'33 (1 byte): Response to the inquiry on operating frequency
• Size (1 byte): The total length of the number of operating clocks, and maximum and minimum
values of operating frequency fields.
• Number of operating clocks (1 byte): The number of operating clock frequencies required
within the device.
For example, the value two indicates main and peripheral operating clock frequencies.
• Minimum value of operating frequency (2 bytes): The minimum frequency of a frequencymultiplied or -divided clock signal.
The value in this field and in the maximum value field is the frequency in MHz to two decimal
places, multiplied by 100 (for example, if the frequency is 20.00 MHz, the value multiplied by
100 is 2000, so H'07D0 is returned here).
• Maximum value of operating frequency (2 bytes): The maximum frequency of a frequencymultiplied or -divided clock signal.
As many pairs of minimum/maximum values are included as there are operating clocks.
• SUM (1 byte): Checksum
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1483 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(g)
Inquiry on User Boot MATs
In response to the inquiry on user boot MATs, the boot program returns the number of user boot
MAT areas and their addresses.
Command
H'24
• Command H'24 (1 byte): Inquiry on user boot MAT information
Response
H'34
Size
First address of the area
No. of areas
Last address of the area
…
SUM
• Response H'34 (1 byte): Response to the inquiry on user boot MATs
• Size (1 byte): The total length of the number of areas and first and last address fields.
• Number of areas (1 byte): The number of user boot MAT areas.
H'01 is returned if the entire user boot MAT area is continuous.
• First address of the area (4 bytes)
• Last address of the area (4 bytes)
As many pairs of first and last address field are included as there are areas.
• SUM (1 byte): Checksum
(h)
Inquiry on User MATs
In response to the inquiry on user MATs, the boot program returns the number of user MAT areas
and their addresses.
Command
H'25
• Command H'25 (1 byte): Inquiry on user MAT information
Page 1484 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Response
H'35
Section 26 Flash Memory (ROM)
Size
No. of areas
First address of the area
Last address of the area
…
SUM
• Response H'35 (1 byte): Response to the inquiry on user MATs
• Size (1 byte): The total length of the number of areas and first and last address fields.
• Number of areas (1 byte): The number of user MAT areas.
H'01 is returned if the entire user MAT area is continuous.
• First address of the area (4 bytes)
• Last address of the area (4 bytes)
As many pairs of first and last address field are included as there are areas.
• SUM (1 byte): Checksum
(i)
Inquiry on Erasure Blocks
In response to the inquiry on erasure blocks, the boot program returns the number of erasure
blocks in the user MAT and the addresses where each block starts and ends.
Command
H'26
• Command H'26 (1 byte): Inquiry on erasure blocks
Response
H'36
Size
First address of the block
No. of blocks
Last address of the block
…
SUM
•
•
•
•
•
Response H'36 (1 byte): Response to the inquiry on erasure blocks
Size (2 bytes): The total length of the number of blocks and first and last address fields.
Number of blocks (1 byte): The number of erasure blocks in flash memory
First address of the block (4 bytes)
Last address of the block (4 bytes)
As many pairs of first and last address data are included as there are blocks.
• SUM (1 byte): Checksum
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1485 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(j)
Inquiry on Programming Size
In response to the inquiry on programming size, the boot program returns the size, in bytes, of the
unit for programming.
Command
H'27
• Command H'27 (1 byte): Inquiry on programming size
Response
H'37
Size
Programming size
SUM
• Response H'37 (1 byte): Response to the inquiry on programming size
• Size (1 byte): The number of characters in the programming size field (fixed at 2)
• Programming size (2 bytes): The size of the unit for programming
This is the unit for the reception of data to be programmed.
• SUM (1 byte): Checksum
(k)
New Bit Rate Selection
In response to the new-bit-rate selection command, the boot program changes the bit rate setting to
the new bit rate and, if the setting was successful, responds to the ACK sent by the host by
returning another ACK at the new bit rate.
The new-bit-rate selection command should be sent after clock-mode selection.
Command
H'3F
Size
Multiplier type Multiplier 1
Bit rate
Input frequency
Multiplier 2
count
SUM
• Command H'3F (1 byte): New bit rate selection
• Size (1 byte): The total length of the bit rate, input frequency, number of multiplier types, and
multiplier fields
• Bit rate (2 bytes): New bit rate
The bit rate value divided by 100 should be set here (for example, to select 19200 bps, the set
H'00C0, which is 192 in decimal notation).
• Input frequency (2 bytes): The frequency of the clock signal fed to the boot program
This should be the frequency in MHz to the second decimal place, multiplied by 100 (for
example, if the frequency is 28.882 MHz, the values is truncated to the second decimal place
and multiplied by 100, making 2888; so H'0B48 should be set in this field).
Page 1486 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
• Multiplier type count (1 byte): The number of selectable frequency multiplier types for the
device.
This is normally 2, which indicates the main operating frequency and the operating frequency
of the peripheral modules.
• Multiplier 1 (1 byte): Multiplier or divisor for the main operating frequency
Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for ×4)
Divisor: Two’s complement negative numerical value in the case of frequency division (e.g.
H'FE [-2] for ×1/2)
• Multiplier 2 (1 byte): Multiplier or divisor for the peripheral operating frequency
Multiplier: Numerical value of the frequency multiplier (e.g. H'04 for ×4)
Divisor: Two’s complement negative numerical value in the case of frequency division (e.g.
H'FE [-2] for ×1/2)
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the new-bit-rate selection command
This is the ACK code and is returned if the specified bit rate is selected.
Error
response
H'BF
ERROR
• Error response H'BF (1 byte): Error response to the new-bit-rate selection command
• ERROR (1 byte): Error code
H'11: Sum-check error
H'24: Bit rate selection error (the specified bit rate is not selectable).
H'25: Input frequency error (the specified input frequency is not within the range from the
minimum to the maximum value).
H'26: Frequency multiplier error (the specified multiplier does not match an available one).
H'27: Operating frequency error (the specified operating frequency is not within the range
from the minimum to the maximum value).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1487 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
The received data are checked in the following ways.
1. Input frequency
The value of the received input frequency is checked to see if it is within the range of the
minimum and maximum values of input frequency for the selected clock mode of the selected
device. A value outside the range generates an input frequency error.
2. Multiplier
The value of the received multiplier is checked to see if it matches a multiplier or divisor that
is available for the selected clock mode of the selected device. A value that does not match an
available ratio generates a frequency multiplier error.
3. Operating frequency
The operating frequency is calculated from the received input frequency and the frequency
multiplier or divisor. The input frequency is the frequency of the clock signal supplied to the
LSI, while the operating frequency is the frequency at which the LSI is actually driven. The
following formulae are used for this calculation.
Operating frequency = input frequency × multiplier, or
Operating frequency = input frequency / divisor
The calculated operating frequency is checked to see if it is within the range of the minimum
and maximum values of the operating frequency for the selected clock mode of the selected
device. A value outside the range generates an operating frequency error.
Page 1488 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
4. Bit rate
From the peripheral operating frequency (Pφ) and the bit rate (B), the value (= n) of the clock
select bits (CKS) in the serial mode register (SCSMR) and the value (= N) of the bit rate
register (SCBRR) are calculated, after which the error in the bit rate is calculated. This error is
checked to see if it is smaller than 4%. A result greater than or equal to 4% generates a bit rate
selection error. The following formula is use to calculate the error.
Error (%) = [
Pφ × 106
]-1
(N + 1) × B × 64 × 22n-1
× 100
When the new bit rate is selectable, the boot program returns an ACK code to the host and then
makes the register setting to select the new bit rate. The host then sends an ACK code at the
new bit rate, and the boot program responds to this with another ACK code, this time at the
new bit rate.
Acknowledge
H'06
• Acknowledge H'06 (1 byte): The ACK code sent by the host to acknowledge the new bit rate.
Response
H'06
• Response H'06 (1 byte): The ACK code transferred in response to acknowledgement of the
new bit rate
The sequence of new bit rate selection is shown in figure 26.24.
Host
Boot program
New bit rate setting
H'06 (ACK)
Wait for one-bit
period at the current
bit rate setting
New bit rate setting
Setting the new
bit rate
H'06 (ACK) at the new bit rate
H'06 (ACK) at the new bit rate
Figure 26.24 Sequence of New Bit Rate Selection
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1489 of 1778
Section 26 Flash Memory (ROM)
(l)
SH7280 Group, SH7243 Group
Transition to the Programming/Erasure State
In response to the transition to the programming/erasure state command, the boot program
transfers the erasing program and runs it to erase any data in the user MAT and then the user boot
MAT. On completion of this erasure, the boot program returns the ACK code and enters the
programming/erasure state.
Before sending the programming selection command and data for programming, the host must
select the device, clock mode, and new bit rate for the LSI by issuing the device selection
command, clock-mode selection command, new-bit-rate selection command, and then initiate the
transition to the programming/erasure state by sending the corresponding command to the boot
program.
Command
H'40
• Command H'40 (1 byte): Transition to programming/erasure state
Response
H'06
• Response H'06 (1 byte): Response to the transition-to-programming/erasure state command
This is returned as ACK when erasure of the user boot MAT and user MAT has succeeded
after transfer of the erasure program.
Error
response
H'C0
H'51
• Error response H'C0 (1 byte): Error response to the transition-to-programming/erasure state
command
• ERROR (1 byte): Error code
H'51: Erasure error (Erasure did not succeed because of an error.)
Page 1490 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(m) Command Error
Command errors are generated by undefined commands, commands sent in an incorrect order, and
the inability to accept a command. For example, sending the clock-mode selection command
before device selection or an inquiry command after the transition-to-programming/erasure state
command generates a command error.
Error
response
H'80
H'xx
• Error response H'80 (1 byte): Command error
• Command H'xx (1 byte): Received command
(n)
Order of Commands
In the inquiry-and-selection state, commands should be sent in the following order.
1. Send the inquiry on supported devices command (H'20) to get the list of supported devices.
2. Select a device from the returned device information, and send the device selection command
(H'10) to select that device.
3. Send the inquiry on clock mode command (H'21) to get the available clock modes.
4. Select a clock mode from among the returned clock modes, and send the clock-mode selection
command (H'11).
5. After selection of the device and clock mode, send the commands to inquire about frequency
multipliers (H'22) and operating frequencies (H'23) to get the information required to select a
new bit rate.
6. Taking into account the returned information on the frequency multipliers and operating
frequencies, send a new-bit-rate selection command (H'3F).
7. After the device and clock mode have been selected, get the information required for
programming and erasure of the user boot MAT and user MAT by sending the commands to
inquire about the user boot MAT (H'24), user MAT (H'25), erasure block (H'26), and
programming size (H'27).
8. After making all necessary inquiries and the new bit rate selection, send the transition-toprogramming/erasure state command (H'40) to place the boot program in the
programming/erasure state.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1491 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
(5)
Programming/Erasure State
In this state, the boot program must select the form of programming corresponding to the
programming-selection command and then write data in response to 256-byte programming
commands, or perform erasure in block units in response to the erasure-selection and blockerasure commands.
The programming and erasure commands are listed in table 26.14.
Table 26.14 Programming and Erasure Commands
Command
Command Name
Function
H'42
Selection of user boot
MAT programming
Selects transfer of the program for user boot MAT
programming.
H'43
Selection of user MAT
programming
Selects transfer of the program for user MAT programming.
H'50
256-byte programming Executes 256-byte programming.
H'48
Erasure selection
Selects transfer of the erasure program.
H'58
Block erasure
Executes erasure of the specified block.
H'52
Memory read
Reads from memory.
H'4A
Sum checking of user
boot MAT
Executes sum checking of the user boot MAT.
H'4B
Sum checking of user
MAT
Executes sum checking of the user MAT.
H'4C
Blank checking of user Executes blank checking of the user boot MAT.
boot MAT
H'4D
Blank checking of user Executes blank checking of the user MAT.
MAT
H'4F
Inquiry on boot
program state
Page 1492 of 1778
Requests information on the state of boot processing.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(a)
Section 26 Flash Memory (ROM)
Programming
Programming is performed by issuing a programming-selection command and the 256-byte
programming command.
Firstly, the host issues the programming-selection command to select the MAT to be programmed.
Two programming-selection commands are provided for the selection of either of the two target
areas.
1. Selection of user boot MAT programming
2. Selection of user MAT programming
Next, the host issues a 128-byte programming command. 256 bytes of data for programming by
the method selected by the preceding programming selection command are expected to follow the
command. To program more than 256 bytes, repeatedly issue 256-byte programming commands.
To terminate programming, the host should send another 256-byte programming command with
the address H'FFFFFFFF. On completion of programming, the boot program waits for the next
programming/erasure selection command.
To then program the other MAT, start by sending the programming select command.
The sequence of programming by programming-selection and 128-byte programming commands
is shown in figure 26.25.
Host
Boot program
Programming selection (H'42, H'43)
Transfer the program
that performs
programming
ACK
256-byte programming (address and data)
Programming
Repeat
ACK
256-byte programming (H'FFFFFFFF)
ACK
Figure 26.25 Sequence of Programming
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1493 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
1. Selection of User Boot MAT Programming
In response to the command for selecting programming of the user boot MAT, the boot program
transfers the corresponding flash-writing program, i.e. the program for writing to the user boot
MAT.
Command
H'42
• Command H'42 (1 byte): Selects programming of the user boot MAT.
Response
H'06
• Response H'06 (1 byte): Response to selection of user boot MAT programming
This ACK code is returned after transfer of the program that performs writing to the user boot
MAT.
Error
response
H'C2
ERROR
• Error response H'C2 (1 byte): Error response to selection of user boot MAT programming
• ERROR (1 byte): Error code
H'54: Error in selection processing (processing was not completed because of a transfer error)
2. Selection of User MAT Programming
In response to the command for selecting programming of the user MAT, the boot program
transfers the corresponding flash-writing program, i.e. the program for writing to the user MAT.
Command
H'43
• Command H'43 (1 byte): Selects programming of the user MAT.
Response
H'06
• Response H'06 (1 byte): Response to selection of user MAT programming
This ACK code is returned after transfer of the program that performs writing to the user
MAT.
Page 1494 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Error
response
H'C3
ERROR
• Error response H'C3 (1 byte): Error response to selection of user MAT programming
• ERROR (1 byte): Error code
H'54: Error in selection processing (processing was not completed because of a transfer error)
3. 256-Byte Programming
In response to the 256-byte programming command, the boot program executes the flash-writing
program transferred in response to the command to select programming of the user boot MAT or
user MAT.
Command
H'50
Address for programming
Data
…
…
SUM
• Command H'50 (1 byte): 256-byte programming
• Address for programming (4 bytes): Address where programming starts
Specify the address of a 256-byte boundary.
[Example] H'00, H01, H'00, H'00: H'00100000
• Programming data (n bytes): Data for programming
The length of the programming data is the size returned in response to the programming size
inquiry command.
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to 256-byte programming
The ACK code is returned on completion of the requested programming.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1495 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Error
response
H'D0
ERROR
• Error response H'D0 (1 byte): Error response to 256-byte programming
• ERROR (1 byte): Error code
H'11: Sum-check error
H'2A: Address error (the address is not within the range for the selected MAT)
H'53: Programming error (programming failed because of an error in programming)
Specify the address on a boundary corresponding to the unit of programming (programming size).
For example, when the programming size is 128 bytes, specify H'00 or H'80 for the lower byte of
the address. When less than 256 bytes of data are to be programmed, the host should transmit the
data after padding the vacant bytes with H'FF.
To terminate programming of a given MAT, send a 256-byte programming command with the
address field H'FFFFFFFF. This informs the boot program that all data for the selected MAT have
been sent; the boot program then waits for the next programming/erasure selection command.
Command
H'50
Address for programming
SUM
• Command H'50 (1 byte): 256-byte programming
• Address for programming (4 bytes): Terminating code (H'FF, H'FF, H'FF, H'FF)
• SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to 256-byte programming
This ACK code is returned on completion of the requested programming.
Error
response
H'D0
ERROR
• Error response H'D0 (1 byte): Error response to 256-byte programming
• ERROR (1 byte): Error code
H'11: Sum-check error
H'53: Programming error
Page 1496 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(b)
Section 26 Flash Memory (ROM)
Erasure
Erasure is performed by issuing the erasure selection command and then one or more block
erasure commands.
Firstly, the host sends the erasure selection command to select erasure; after that, it sends a block
erasure command to actually erase a specific block. To erase multiple blocks, send further block
erasure commands. To terminate erasure, the host should send a block erasure command with the
block number H'FF. After this, the boot program waits for the next programming/erasure selection
command.
The sequence of erasure by the erasure selection command and block erasure command is shown
in figure 26.26.
Boot program
Host
Erasure selection (H'48)
Transfer the
program that
performs erasure
ACK
Erasure (block number)
Repeat
Erasure
ACK
Erasure (H'FF)
ACK
Figure 26.26 Sequence of Erasure
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1497 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
1. Select Erasure
In response to the erasure selection command, the boot program transfers the program that
performs erasure, i.e. erases data in the user MAT.
Command
H'48
• Command H'48 (1 byte): Selects erasure.
Response
H'06
• Response H'06 (1 byte): Response to selection of erasure
This ACK code is returned after transfer of the program that performs erasure.
Error
response
H'C8
ERROR
• Error response H'C8 (1 byte): Error response to selection of erasure
• ERROR (1 byte): Error code
H'54: Error in selection processing (processing was not completed because of a transfer error.)
2. Block Erasure
In response to the block erasure command, the boot program erases the data in a specified block of
the user MAT.
Command
•
•
•
•
H'58
Size
Block number
SUM
Command H'58 (1 byte): Erasure of a block
Size (1 byte): The number of characters in the block number field (fixed at 1)
Block number (1 byte): Block number of the block to be erased
SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): Response to the block erasure command
This ACK code is returned when the block has been erased.
Page 1498 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Error
response
H'D8
ERROR
• Error response H'D8 (1 byte): Error response to the block erasure command
• ERROR (1 byte): Error code
H'11: Sum-check error
H'29: Block number error (the specified block number is incorrect.)
H'51: Erasure error (an error occurred during erasure.)
On receiving the command with H'FF as the block number, the boot program stops erasure
processing and waits for the next programming/erasure selection command.
Command
•
•
•
•
H'58
Size
Block number
SUM
Command H'58 (1 byte): Erasure of a block
Size (1 byte): The number of characters in the block number field (fixed at 1)
Block number (1 byte): H'FF (erasure terminating code)
SUM (1 byte): Checksum
Response
H'06
• Response H'06 (1 byte): ACK code to indicate response to the request for termination of
erasure
To perform erasure again after having issued the command with the block number specified as
H'FF, execute the process from the selection of erasure.
(c)
Memory Read
In response to the memory read command, the boot program returns the data from the specified
address.
Command
H'52
Amount to read
Size
Area
First address for reading
SUM
• Command H'52 (1 byte): Memory read
• Size (1 byte): The total length of the area, address for reading, and amount to read fields (fixed
value of 9)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1499 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
• Area (1 byte):
H'00: User boot MAT
H'01: User MAT
An incorrect area specification will produce an address error.
• Address where reading starts (4 bytes)
• Amount to read (4 bytes): The amount of data to be read
• SUM (1 byte): Checksum
Response
H'52
Amount to read
Data
…
SUM
•
•
•
•
Response H'52 (1 byte): Response to the memory read command
Amount to read (4 bytes): The amount to read as specified in the memory read command
Data (n bytes): The specified amount of data read out from the specified address
SUM (1 byte): Checksum
Error
response
H'D2
ERROR
• Error response H'D2 (1 byte): Error response to memory read command
• ERROR (1 byte): Error code
H'11: Sum-check error
H'2A: Address error (the address specified for reading is beyond the range of the MAT)
H'2B: Size error (the specified amount is greater than the size of the MAT,
the last address for reading as calculated from the specified address for the start of reading and
the amount to read is beyond the MAT area, or "0" was specified as the amount to read)
Page 1500 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(d)
Section 26 Flash Memory (ROM)
Sum Checking of the User Boot MAT
In response to the command for sum checking of the user boot MAT, the boot program adds all
bytes of data in the user boot MAT and returns the result.
Command
H'4A
• Command H'4A (1 byte): Sum checking of the user boot MAT
Response
H'5A
Size
Checksum for the MAT
SUM
• Response H'5A (1 byte): Response to sum checking of the user boot MAT
• Size (1 byte): The number of characters in the checksum for the MAT (fixed at 4)
• Checksum for the MAT (4 bytes): Result of checksum calculation for the user boot MAT:
the total of all data in the MAT, in byte units.
• SUM (1 byte): Checksum (for the transmitted data)
(e)
Sum Checking of the User MAT
In response to the command for sum checking of the user MAT, the boot program adds all bytes of
data in the user MAT and returns the result.
Command
H'4B
• Command H'4B (1 byte): Sum checking of the user MAT
Response
H'5B
Size
Checksum for the MAT
SUM
• Response H'5B (1 byte): Response to sum checking of the user MAT
• Size (1 byte): The number of characters in the checksum for the MAT (fixed at 4)
• Checksum for the MAT (4 bytes): Result of checksum calculation for the user MAT:
the total of all data in the MAT, in byte units.
• SUM (1 byte): Checksum (for the transmitted data)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1501 of 1778
Section 26 Flash Memory (ROM)
(f)
SH7280 Group, SH7243 Group
Blank Checking of the User Boot MAT
In response to the command for blank checking of the user boot MAT, the boot program checks to
see if the whole of the user boot MAT is blank; the value returned indicates the result.
Command
H'4C
• Command H'4C (1 byte): Blank checking of the user boot MAT
Response
H'06
• Response H'06 (1 byte): Response to blank checking of the user boot MAT
This ACK code is returned when the whole area is blank (all bytes are H'FF).
Error
response
H'CC
H'52
• Error response H'CC (1 byte): Error response to blank checking of the user boot MAT
• Error code H'52 (1 byte): Non-erased error
(g)
Blank Checking of the User MAT
In response to the command for blank checking of the user MAT, the boot program checks to see
if the whole of the user MAT is blank; the value returned indicates the result.
Command
H'4D
• Command H'4D (1 byte): Blank checking of the user boot MAT
Response
H'06
• Response H'06 (1 byte): Response to blank checking of the user MAT
The ACK code is returned when the whole area is blank (all bytes are H'FF).
Error
response
H'CD
H'52
• Error response H'CD (1 byte): Error response to blank checking of the user MAT
• Error code H'52 (1 byte): Non-erased error
Page 1502 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
(h)
Section 26 Flash Memory (ROM)
Inquiry on Boot Program State
In response to the command for inquiry on the state of the boot program, the boot program returns
an indicator of its current state and error information. This inquiry can be made in the inquiry-andselection state or the programming/erasure state.
Command
H'4F
• Command H'4F (1 byte): Inquiry on boot program state
Response
H'5F
Size
STATUS
ERROR
SUM
• Response H'5F (1 byte): Response to the inquiry regarding boot-program state
• Size (1 byte): The number of characters in STATUS and ERROR (fixed at 2)
• STATUS (1 byte): State of the standard boot program
See table 26.15, Status Codes.
• ERROR (1 byte): Error state (indicates whether the program is in normal operation or an error
has occurred)
ERROR = 0: Normal
ERROR ≠ 0: Error
See table 26.16, Error Codes.
• SUM (1 byte): Checksum
Table 26.15 Status Codes
Code
Description
H'11
Waiting for device selection
H'12
Waiting for clock-mode selection
H'13
Waiting for bit-rate selection
H'1F
Waiting for transition to programming/erasure status (bit-rate selection complete)
H'31
Erasing the user MAT or user boot MAT
H'3F
Waiting for programming/erasure selection (erasure complete)
H'4F
Waiting to receive data for programming (programming complete)
H'5F
Waiting for erasure block specification (erasure complete)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1503 of 1778
Section 26 Flash Memory (ROM)
SH7280 Group, SH7243 Group
Table 26.16 Error Codes
Code
Description
H'00
No error
H'11
Sum check error
H'21
Non-matching device code error
H'22
Non-matching clock mode error
H'24
Bit-rate selection failure
H'25
Input frequency error
H'26
Frequency multiplier error
H'27
Operating frequency error
H'29
Block number error
H'2A
Address error
H'2B
Data length error (size error)
H'51
Erasure error
H'52
Non-erased error
H'53
Programming error
H'54
Selection processing error
H'80
Command error
H'FF
Bit-rate matching acknowledge error
Page 1504 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
26.8.2
Section 26 Flash Memory (ROM)
Areas for Storage of the Procedural Program and Data for Programming
In the descriptions in the previous section, storable areas for the programming/erasing procedure
programs and program data are assumed to be in on-chip RAM. However, the procedure programs
and data can be stored in and executed from other areas (e.g. external address space) as long as the
following conditions are satisfied.
1. The on-chip programming/erasing program is downloaded from the address set by FTDAR in
on-chip RAM, therefore, this area is not available for use.
2. The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure
this area is reserved.
3. Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
executed in on-chip RAM.
4. The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been decided. When in a mode in which the external address space
is not accessible, such as single-chip mode, the required procedure programs, interrupt vector
table, interrupt processing routine, and user branch program should be transferred to on-chip
RAM before programming/erasing of the flash memory starts.
5. The flash memory is not accessible during programming/erasing operations. Therefore, the
programming/erasing program must be downloaded to on-chip RAM in advance. Areas for
executing each procedure program for initiating programming/erasing and the user program at
the user branch destination for programming/erasing must be located in on-chip RAM other
than flash memory or the external address space.
6. After programming/erasing, access to flash memory is inhibited until FKEY is cleared.
A reset state (RES = 0) for more than at least 100 μs must be taken when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Transitions to the reset state during programming/erasing are inhibited. When the reset signal
is accidentally input to the LSI, a longer period in the reset state than usual (100 μs) is needed
before the reset signal is released.
7. Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in
user boot mode. The program which switches the MATs should be executed from the on-chip
RAM. For details, see section 26.7.1, Switching between User MAT and User Boot MAT.
Please make sure you know which MAT is selected when switching the MATs.
8. When the program data storage area indicated by the FMPDR parameter in the programming
processing is within the flash memory area, an error will occur. Therefore, temporarily transfer
the program data to on-chip RAM to change the address set in FMPDR to an address other
than flash memory.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1505 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Based on these conditions, tables show the areas in which the program data can be stored and
executed according to the operation type and mode.
Table 26.17 Executable MAT
Initiated Mode
Operation
User Program Mode
User Boot Mode*
Programming
Table 26.18 (1)
Table 26.18 (3)
Erasing
Table 26.18 (2)
Table 26.18 (4)
Note:
*
Programming/Erasing is possible to user MATs.
Page 1506 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.18 (1) Usable Area for Programming in User Program Mode
Storable/Executable Area
Programming
procedure
Note:
*
Selected MAT
Item
OnChip
RAM
User
MAT
External
Space
User
MAT
Embedded
Program
Storage
MAT
Program data storage area
√
X*
√
—
—
Selecting on-chip program to be
downloaded
√
√
√
√
Writing H'A5 to key register
√
√
√
√
Writing 1 to SCO in FCCS
(download)
√
X
X
Key register clearing
√
√
√
√
Judging download result
√
√
√
√
Download error processing
√
√
√
√
Setting initialization parameters
√
√
√
√
Initialization
√
X
X
√
Judging initialization result
√
√
√
√
Initialization error processing
√
√
√
√
Writing H'5A to key register
√
√
√
√
Setting programming parameters √
X
√
√
Programming
√
X
X
√
Judging programming result
√
X
√
√
Programming error processing
√
X
√
√
Key register clearing
√
X
√
√
√
If the data has been transferred to on-chip RAM in advance, this area can be used.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1507 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.18 (2) Usable Area for Erasure in User Program Mode
Storable/Executable Area
Selected MAT
OnChip
RAM
User
MAT
External
Space
User
MAT
Selecting on-chip program to be
downloaded
√
√
√
√
Writing H'A5 to key register
√
√
√
√
Writing 1 to SCO in FCCS
(download)
√
X
X
Key register clearing
√
√
√
√
Judging download result
√
√
√
√
Download error processing
√
√
√
√
Setting initialization parameters
√
√
√
√
Initialization
√
X
X
√
√
√
√
√
√
√
√
√
√
√
√
√
Setting erasure parameters
√
X
√
√
Erasure
√
X
X
√
Judging erasure result
√
X
√
√
Erasing error processing
√
X
√
√
Key register clearing
√
X
√
√
Item
Erasing Judging initialization result
proceInitialization error processing
dure
Writing H'5A to key register
Page 1508 of 1778
Embedded
Program
Storage
MAT
√
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.18 (3) Usable Area for Programming in User Boot Mode
Storable/Executable Area
User
MAT
User
Boot
MAT
Embedded
Program
Storage
Area
—
—
—
OnChip
RAM
User
Boot
MAT
External
Space
Program data storage
area
√
X*1
√
Selecting on-chip
program to be
downloaded
√
√
√
√
Writing H'A5 to key
register
√
√
√
√
Writing 1 to SCO in
FCCS (download)
√
X
X
Key register clearing
√
√
√
√
Judging download
result
√
√
√
√
Download error
processing
√
√
√
√
Setting initialization
parameters
√
√
√
√
Initialization
√
X
X
√
Judging initialization
result
√
√
√
√
Initialization error
processing
√
√
√
√
Switching MATs by
FMATS
√
X
X
√
Writing H'5A to Key
Register
√
X
√
√
Item
Programming
procedure
Selected MAT
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
√
Page 1509 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.18 (3) Usable Area for Programming in User Boot Mode (cont)
Storable/Executable Area
OnChip
RAM
User
Boot
MAT
External
Space
User
MAT
Setting programming
parameters
√
X
√
√
Programming
√
X
X
√
Judging programming
result
√
X
√
√
Programming error
processing
√
X*2
√
√
Key register clearing
√
X
√
√
Switching MATs by
FMATS
√
X
X
Item
Programming
procedure
Selected MAT
User
Boot
MAT
Embedded
Program
Storage
Area
√
Notes: 1. If the data has been transferred to on-chip RAM in advance, this area can be used.
2. If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used.
Page 1510 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.18 (4) Usable Area for Erasure in User Boot Mode
Storable/Executable Area
Selected MAT
OnChip
RAM
User
Boot
MAT
External
Space
Selecting on-chip
program to be
downloaded
√
√
√
√
Writing H'A5 to key
register
√
√
√
√
Writing 1 to SCO in
FCCS (download)
√
X
X
Key register clearing
√
√
√
√
Judging download
result
√
√
√
√
Download error
processing
√
√
√
√
√
√
√
√
√
X
X
√
Judging initialization
result
√
√
√
√
Initialization error
processing
√
√
√
√
Switching MATs by
FMATS
√
X
X
√
Writing H'5A to key
register
√
X
√
√
Setting erasure
parameters
√
X
√
√
Item
Erasing Setting initialization
proce- parameters
dure
Initialization
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
User
MAT
User
Boot
MAT
Embedded
Program
Storage
Area
√
Page 1511 of 1778
SH7280 Group, SH7243 Group
Section 26 Flash Memory (ROM)
Table 26.18 (4) Usable Area for Erasure in User Boot Mode (cont)
Storable/Executable Area
Item
OnChip
RAM
User
Boot
MAT
External
Space
User
MAT
Erasure
√
X
X
√
Judging erasure result
√
X
√
√
√
X*
√
√
√
X
√
√
√
X
X
Erasing Erasing error
proce- processing
dure
Key register clearing
Switching MATs by
FMATS
Note:
26.9
*
Selected MAT
User
Boot
MAT
Embedded
Program
Storage
Area
√
If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used.
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the
Renesas 512-Kbyte flash memory on-chip MCU device type
(FZTAT512DV5A/FZTAT1024DV5A).
Page 1512 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 27 On-Chip RAM
Section 27 On-Chip RAM
This LSI has an on-chip RAM module which can be used to store instructions or data.
On-chip RAM operation and write access to the RAM can be enabled or disabled through the
RAM enable bits and RAM write enable bits.
27.1
Features
• Pages
SH7243: SH72433 One page (pages 0), SH72434 Two pages (pages 0 and 1)
SH7285: SH72855 Three pages (pages 0 to 2), SH72856 Four pages (pages 0 to 3)
SH7286: Four pages (pages 0 to 3)
• Memory map
The on-chip RAM is located in the address spaces shown in tables 27.1 and 27.2.
Table 27.1 On-Chip RAM Address Spaces (SH7286 and SH7285)
Page
Address
Page 0
H'FFF80000 to H'FFF81FFF
Page 1
H'FFF82000 to H'FFF83FFF
Page 2
H'FFF84000 to H'FFF85FFF
Page 3
H'FFF86000 to H'FFF87FFF
Table 27.2 On-Chip RAM Address Spaces (SH7243)
Page
Address
Page 0
H'FFF80000 to H'FFF81FFF
Page 1
H'FFF82000 to H'FFF82FFF
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1513 of 1778
Section 27 On-Chip RAM
SH7280 Group, SH7243 Group
• Ports
Each page has two independent read and write ports and is connected to the internal bus (I
bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F
bus is connected only to the read ports.)
The F bus and M bus are used for access by the CPU, and the I bus is used for access by the
DMAC or DTC.
• Priority
When the same page is accessed from different buses simultaneously, the access is processed
according to the priority. The priority is I bus > M bus > F bus.
Page 1514 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
27.2
Usage Notes
27.2.1
Page Conflict
Section 27 On-Chip RAM
When the same page is accessed from different buses simultaneously, a conflict on the page
occurs. Although each access is completed correctly, this kind of conflict degrades the memory
access speed. Therefore, it is advisable to provide software measures to prevent such conflicts as
far as possible. For example, no conflict will arise if different memory or pages are accessed by
each bus.
27.2.2
RAME and RAMWE Bits
Before disabling memory operation or write access through the RAME or RAMWE bit, be sure to
read from any address and then write to the same address in each page; otherwise, the last written
data in each page may not be actually written to the RAM.
// For page 0
MOV.L
#H'FFF80000,R0
MOV.L
@R0,R1
MOV.L
R1,@R0
// For page 1
MOV.L
#H'FFF88000,R0
MOV.L
@R0,R1
MOV.L
R1,@R0
// For page 2
MOV.L
#H'FFF90000,R0
MOV.L
@R0,R1
MOV.L
R1,@R0
// For page 3
MOV.L
#H'FFF98000,R0
MOV.L
@R0,R1
MOV.L
R1,@R0
Figure 27.1 Examples of Read/Write before Disabling RAM
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1515 of 1778
Section 27 On-Chip RAM
Page 1516 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Section 28 Power-Down Modes
In power-down modes, operation of some of the internal peripheral modules and of the CPU stops.
This leads to reduced power consumption. These modes are canceled by a reset or interrupt.
28.1
Features
28.1.1
Power-Down Modes
This LSI has the following power-down modes and function:
1. Sleep mode
2. Software standby mode
3. Module standby function
Table 28.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral module states in each mode and the procedures for
canceling each mode.
Table 28.1 States of Power-Down Modes
State*
Power-Down
Mode
Sleep mode
Software
standby mode
CPG
CPU
CPU
On-Chip
Register Memory
Runs
Execute SLEEP
instruction with STBY bit
cleared to 0 in STBCR
Halts
Held
Transition Conditions
*
Runs
External
Memory
Canceling
Procedure
Autorefreshing
•
Interrupt
•
Manual reset
•
Power-on reset
•
DMA address
error
Halts
Execute SLEEP
instruction with STBY bit
set to 1 in STBCR
Halts
Held
Halts
(contents are
held)
Halts
Selfrefreshing
•
Power-on reset
Runs
Runs
Held
Specified
module halts
(contents are
held)
Specified
module halts
Autorefreshing
•
Clear MSTP bit
to 0
•
Power-on reset
(only for H-UDI,
UBC, DMAC,
and DTC)
Module standby Set the MSTP bits in
function
STBCR2, STBCR3,
STBCR4, STBCR5, and
STBCR6 to 1
Note:
Runs
(RAM)
Halts
(Flash memory)
On-Chip
Peripheral
Modules
The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1517 of 1778
Section 28 Power-Down Modes
28.1.2
SH7280 Group, SH7243 Group
Reset
A reset is used when the power is turned on or to run the LSI again from the initialized state.
There are two types of reset: power-on reset and manual reset. In a power-on reset, all the ongoing
processing is halted and any unprocessed events are canceled, and the reset processing starts
immediately. On the other hand, a manual reset does not interrupt processing to retain external
memory data. Conditions for generating a power-on reset or manual reset are as follows:
(1)
Power-On Reset
1.
2.
A low level is input to the RES pin.
The watchdog timer (WDT) starts counting with the WT/IT bit in WTCSR set to 1 and with
the RSTS bit in WRCSR set to 0 while the RSRE bit in WRCSR is 1, and the counter
overflows.
The H-UDI reset is generated (for details on the H-UDI reset, see section 29, User
Debugging Interface (H-UDI)).
3.
(2)
Manual Reset
1.
2.
A low level is input to the MRES pin.
The WDT starts counting with the WT/IT bit in WTCSR set to 1 and with the RSTS bit in
WRCSR set to 1 while the RSRE bit in WRCSR is 1, and the counter overflows.
Page 1518 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.2
Section 28 Power-Down Modes
Input/Output Pins
Table 28.2 lists the pins used for power-down modes.
Table 28.2 Pin Configuration
Name
Pin Name
I/O
Function
Power-on reset
RES
Input
Power-on reset processing starts when a low
level is input to this pin.
Manual reset
MRES
Input
Manual reset processing starts when a low
level is input to this pin.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1519 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
28.3
Register Descriptions
The following registers are used in power-down modes.
Table 28.3 Register Configuration
Register Name
Abbreviation
R/W
Initial
Value
Address
Access
Size
Standby control register
STBCR
R/W
H'00
H'FFFE0014
8
Standby control register 2
STBCR2
R/W
H'00
H'FFFE0018
8
Standby control register 3
STBCR3
R/W
H'7E
H'FFFE0408
8
Standby control register 4
STBCR4
R/W
H'F6
H'FFFE040C
8
Standby control register 5
STBCR5
R/W
H'FF
H'FFFE0418
8
Standby control register 6
STBCR6
R/W
H'DF
H'FFFE041C
8
System control register 1
SYSCR1
R/W
H'FF
H'FFFE0402
8
System control register 2
SYSCR2
R/W
H'FF
H'FFFE0404
8
Page 1520 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.3.1
Section 28 Power-Down Modes
Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This
register is initialized to H'00 by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is possible.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
STBY
-
-
-
-
-
-
-
0
R/W
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Bit
Bit Name
Initial
Value
R/W
Description
7
STBY
0
R/W
Software Standby
0
Specifies transition to software standby mode.
0: Executing SLEEP instruction puts chip into sleep
mode.
1: Executing SLEEP instruction puts chip into
software standby mode.
6 to 0
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1521 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
28.3.2
Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR2 is initialized to H'00 by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit:
Initial value:
R/W:
4
3
2
1
MSTP
10
7
MSTP MSTP
9
8
6
5
-
-
-
MSTP
4
-
0
R/W
0
R/W
0
R
0
R
0
R
0
R/W
0
R
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTP10
0
R/W
Module Stop 10
0
When the MSTP10 bit is set to 1, the supply of the
clock to the H-UDI is halted.
0: H-UDI runs.
1: Clock supply to H-UDI halted.
6
MSTP9
0
R/W
Module Stop 9
When the MSTP9 bit is set to 1, the supply of the
clock to the UBC is halted.
0: UBC runs.
1: Clock supply to UBC halted.
5
MSTP8
0
R/W
Module Stop 8
When the MSTP8 bit is set to 1, the supply of the
clock to the DMAC is halted.
0: DMAC runs.
1: Clock supply to DMAC halted.
4 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
MSTP4
0
R/W
Module Stop 4
When the MSTP4 bit is set to 1, the supply of the
clock to the DTC is halted.
0: DTC runs.
1: Clock supply to DTC halted.
0
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1522 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.3.3
Section 28 Power-Down Modes
Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR3 is initialized to H'7E by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit:
7
6
HIZ
Initial value:
R/W:
0
R/W
2
1
0
MSTP MSTP
36
35
5
MSTP MSTP
34
33
MSTP
32
MSTP
31
-
1
R/W
1
R/W
1
R/W
1
R/W
0
R
1
R/W
4
3
1
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
HIZ
0
R/W
Port High Impedance
Selects whether the state of a specified pin is
retained or the pin is placed in the high-impedance
state in software standby mode. See appendix A, Pin
States, to determine the pin to which this control is
applied.
Do not set this bit when the TME bit of WTSCR of the
WDT is 1. When setting the output pin to the highimpedance state, set the HIZ bit with the TME bit
being 0.
0: The pin state is held in software standby mode.
1: The pin state is set to the high-impedance state in
software standby mode.
6
MSTP36
1
R/W
Module Stop 36
When the MSTP36 bit is set to 1, the supply of the
clock to the MTU2S is halted.
0: MTU2S runs.
1: Clock supply to MTU2S halted.
5
MSTP35
1
R/W
Module Stop 35
When the MSTP35 bit is set to 1, the supply of the
clock to the MTU2 is halted.
0: MTU2 runs.
1: Clock supply to MTU2 halted.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1523 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
4
MSTP34
1
R/W
Module Stop 34
When the MSTP34 bit is set to 1, the supply of the
clock to the POE2 is halted.
0: POE2 runs.
1: Clock supply to POE2 halted.
3
MSTP33
1
R/W
Module Stop 33
When the MSTP33 bit is set to 1, the supply of the
clock to the IIC3 is halted.
0: IIC3 runs.
1: Clock supply to IIC3 halted.
Note: Write 1 to this bit in the SH7243.
2
MSTP32
1
R/W
Module Stop 32
When the MSTP32 bit is set to 1, the supply of the
clock to the ADC0 is halted.
0: ADC0 runs.
1: Clock supply to ADC0 halted.
1
MSTP31
1
R/W
Module Stop 31
When the MSTP31 bit is set to 1, the supply of the
clock to the DAC is halted.
0: DAC runs.
1: Clock supply to DAC halted.
Note: Write 1 to this bit in the SH7285 and SH7243.
0
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Page 1524 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.3.4
Section 28 Power-Down Modes
Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR4 is initialized to H'F6 by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
⎯
⎯
⎯
MSTP
44
⎯
MSTP
42
⎯
⎯
1
R
1
R
1
R
1
R/W
0
R
1
R/W
1
R
0
R
Bit
Bit Name
Initial
Value
R/W
7 to 5
⎯
All 1
R
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
4
MSTP44
1
R/W
Module Stop 44
When the MSTP44 bit is set to 1, the supply of the
clock to the SCIF3 is halted.
0: SCIF3 runs.
1: Clock supply to SCIF3 halted.
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
MSTP42
1
R/W
Module Stop 42
When the MSTP42 bit is set to 1, the supply of the
clock to the CMT is halted.
0: CMT runs.
1: Clock supply to CMT halted.
1
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
0
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1525 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
28.3.5
Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR5 is initialized to H'FF by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit:
Initial value:
R/W:
4
3
2
MSTP
57
7
MSTP MSTP
56
55
6
5
⎯
MSTP
53
MSTP
52
MSTP MSTP
51
50
1
R/W
1
R/W
1
R
1
R/W
1
R/W
1
R/W
1
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTP57
1
R/W
Module Stop 57
1
0
1
R/W
When the MSTP57 bit is set to 1, the supply of the
clock to the SCI0 is halted.
0: SCI0 runs.
1: Clock supply to SCI0 halted.
6
MSTP56
1
R/W
Module Stop 56
When the MSTP56 bit is set to 1, the supply of the
clock to the SCI1 is halted.
0: SCI1 runs.
1: Clock supply to SCI1 halted.
Note: Write 1 to this bit in the SH7243.
5
MSTP55
1
R/W
Module Stop 55
When the MSTP55 bit is set to 1, the supply of the
clock to the SCI2 is halted.
0: SCI2 runs.
1: Clock supply to SCI2 halted.
4
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
Page 1526 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
3
MSTP53
1
R/W
Module Stop 53
When the MSTP53 bit is set to 1, the supply of the
clock to the SCI4 is halted.
0: SCI4 runs.
1: Clock supply to SCI4 halted.
Note: Write 1 to this bit in the SH7243.
2
MSTP52
1
R/W
Module Stop 52
When the MSTP52 bit is set to 1, the supply of the
clock to the ADC1 is halted.
0: ADC1 runs.
1: Clock supply to ADC1 halted.
1
MSTP51
1
R/W
Module Stop 51
When the MSTP51 bit is set to 1, the supply of the
clock to the ADC2 is halted.
0: ADC2 runs.
1: Clock supply to ADC2 halted.
Note: Write 1 to this bit in the SH7285, SH7243.
0
MSTP50
1
R/W
Module Stop 50
When the MSTP50 bit is set to 1, the supply of the
clock to the SSU is halted.
0: SSU runs.
1: Clock supply to SSU halted.
Note: Write 1 to this bit in the SH7243.
28.3.6
Standby Control Register 6 (STBCR6)
STBCR6 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR6 is initialized to H'DF by a power-on reset but retains its previous value by
a manual reset or in software standby mode. Only byte access is possible.
Bit:
Initial value:
R/W:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
7
6
5
4
3
2
1
0
USB
SEL*1
MSTP
66*2
USB
CLK
MSTP
64
⎯
⎯
⎯
⎯
1
R/W
1
R/W
0
R/W
1
R/W
1
R
1
R
1
R
1
R
Page 1527 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Bit
7
Bit Name
1
USBSEL*
Initial
Value
R/W
Description
1
R/W
USB Clock Select
Selects the on-chip CPG or the USB oscillator as the
source of the USB clock.
0: On-chip CPG
1: USB oscillator
Note: Write 1 to this bit in the SH7243.
6
MSTP66*
2
1
R/W
Module Stop 66
When the MSTP66 bit is set to 1, the supply of the
clock to the USB is halted.
0: USB runs.
1: Clock supply to USB halted.
Note: Write 1 to this bit in the SH7243.
5
USBCLK
0
R/W
USB Oscillator Stop
When the USBCLK bit is set to 1, the oscillator
dedicated for the USB stops.
0: USB oscillator operates.
1: USB oscillator stops.
Note: Write 1 to this bit in the SH7243.
4
MSTP64
1
R/W
Module Stop 64
When the MSTP64 bit is set to 1, the supply of the
clock to the RCAN-ET is halted.
0: RCAN-ET runs.
1: Clock supply to RCAN-ET halted.
Note: Write 1 to this bit in the SH7285 and SH7243.
3 to 0
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
Notes: When using the USB, Follow the notes shown below. Otherwise the clock will not be
generated correctly so that USB can be operated improperly.
1. When selecting the on-chip CPG, set the frequency of the input clock to 12MHz.
2. When using the USB, set the frequency of the peripheral clock (Pφ) to 13 MHz or more.
Page 1528 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.3.7
Section 28 Power-Down Modes
System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM.
SYSCR1 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is possible.
When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME
bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an
undefined value is returned when reading data or fetching an instruction from the on-chip RAM,
and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAME bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
located immediately after the instruction to write to SYSCR1. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
To enable the on-chip RAM by setting the RAME bit to 1, place an instruction to read data from
SYSCR1 immediately after an instruction to write to SYSCR1. If an instruction to access the onchip RAM is placed immediately after the instruction to write to SYSCR1, normal access is not
guaranteed.
Bit:
Initial value:
R/W:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
7
6
5
4
-
-
-
-
1
R
1
R
1
R
1
R
3
2
1
0
RAME3 RAME2 RAME1 RAME0
1
R/W
1
R/W
1
R/W
1
R/W
Page 1529 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
3
RAME3
1
R/W
RAM Enable 3 (corresponding RAM addresses:
H'FFF86000 to H'FFF87FFF)
0: On-chip RAM disabled
1: On-chip RAM enabled
Note: Write 1 to this bit in the SH7243.
2
RAME2
1
R/W
RAM Enable 2 (corresponding RAM addresses:
H'FFF84000 to H'FFF85FFF)
0: On-chip RAM disabled
1: On-chip RAM enabled
Note: Write 1 to this bit in the SH7243.
1
RAME1
1
R/W
RAM Enable 1 (SH7286/SH7285: H'FFF82000 to
H'FFF83FFF, SH7243: H’FFF82000 to H’FFF82FFF)
0: On-chip RAM disabled
1: On-chip RAM enabled
0
RAME0
1
R/W
RAM Enable 0 (corresponding RAM addresses:
H'FFF80000 to H'FFF81FFF)
0: On-chip RAM disabled
1: On-chip RAM enabled
Page 1530 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.3.8
Section 28 Power-Down Modes
System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM.
SYSCR2 is initialized to H'FF by a power-on reset but retains its previous value by a manual reset
or in software standby mode. Only byte access is valid.
When an RAMWE bit is set to 1, the corresponding on-chip RAM area is enabled. When an
RAMWE bit is cleared to 0, the corresponding on-chip RAM area cannot be written to. In this
case, writing to the on-chip RAM is ignored. The initial value of an RAMWE bit is 1.
Note that when clearing the RAMWE bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAMWE bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
located immediately after the instruction to write to SYSCR2. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
To enable the on-chip RAM by setting the RAMWE bit to 1, locate an instruction to read data
from SYSCR2 immediately after an instruction to write to SYSCR2. If an instruction to access the
on-chip RAM is located immediately after the instruction to write to SYSCR2, normal access is
not guaranteed.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
-
-
-
RAM
WE3
RAM
WE2
RAM
WE1
RAM
WE0
1
R
1
R
1
R
1
R
1
R/W
1
R/W
1
R/W
1
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
⎯
All 1
R
Reserved
These bits are always read as 1. The write value
should always be 1.
3
RAMWE3
1
R/W
RAM Write Enable 3 (corresponding RAM addresses:
H'FFF86000 to H'FFF87FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
Note: Write 1 to this bit in the SH7243.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1531 of 1778
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
2
RAMWE2
1
R/W
RAM Write Enable 2 (corresponding RAM addresses:
H'FFF84000 to H'FFF85FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
Note: Write 1 to this bit in the SH7243.
1
RAMWE1
1
R/W
RAM Write Enable 1 (SH7286/SH7285: H'FFF82000
to H'FFF83FFF, SH7243: H’FFF82000 to
H’FFF82FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
0
RAMWE0
1
R/W
RAM Write Enable 0 (corresponding RAM addresses:
H'FFF80000 to H'FFF81FFF)
0: On-chip RAM write disabled
1: On-chip RAM write enabled
Page 1532 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.4
Operation
28.4.1
Sleep Mode
(1)
Section 28 Power-Down Modes
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules
continue to run in sleep mode. Clock pulses are output continuously on the CK pin.
(2)
Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address
error, or reset (manual reset or power-on reset).
• Canceling with an interrupt
When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and
interrupt exception handling is executed. When the priority level of the generated interrupt is
equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU,
or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt
request is not accepted and sleep mode is not canceled.
• Canceling with a DMA or DTC address error
When a DMA or DTC address error occurs, sleep mode is canceled and DMA or DTC address
error exception handling is executed.
• Canceling with a reset
Sleep mode is canceled by a power-on reset or a manual reset.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1533 of 1778
Section 28 Power-Down Modes
28.4.2
(1)
SH7280 Group, SH7243 Group
Software Standby Mode
Transition to Software Standby Mode
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the
CPU but also the clock and on-chip peripheral modules halt. The clock output from the CK pin
also halts.
The contents of the CPU registers and cache remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. Table 28.4 shows the states of peripheral module
registers in software standby mode.
The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely
reflected in the SLEEP instruction.
Page 1534 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 28 Power-Down Modes
Table 28.4 Register States in Software Standby Mode
Module Name
Initialized Registers
Registers Whose
Content is Retained
Interrupt controller (INTC)
⎯
All registers
Clock pulse generator (CPG)
⎯
All registers
User break controller (UBC)
⎯
All registers
Bus state controller (BSC)
⎯
All registers
A/D converter (ADC)
All registers
⎯
I/O port
⎯
All registers
User debugging interface (H-UDI)
⎯
All registers
Serial communication interface with FIFO
(SCIF)
⎯
All registers
Direct memory access controller (DMAC)
⎯
All registers
Multi-function timer pulse unit 2 (MTU2)
⎯
All registers
Multi-function timer pulse unit 2S (MTU2S)
⎯
All registers
Port output enable 2 (POE2)
⎯
All registers
Compare match timer (CMT)
All registers
⎯
I2C bus interface 3 (IIC3)
BC2 and BC0 bits in
ICMR register
Other than BC[2:0] bits in
ICMR
D/A converter (DAC)
⎯
All registers
Serial communication interface (SCI)
⎯
All registers
USB function module (USB)
⎯
All registers
Synchronous serial communication interface
(SSU)
⎯
All registers
Controller area network (RCAN-IF)
⎯
All registers
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
values to secure the specified oscillation settling time.
3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1535 of 1778
Section 28 Power-Down Modes
(2)
SH7280 Group, SH7243 Group
Exit from Software Standby Mode
Software standby mode should be exited by a power-on reset. Software standby mode cannot be
exited by a manual reset. When transferring the state of this LSI to a manual reset during software
standby mode, operations of this LSI cannot be guaranteed. Also, when generating an interrupt
during software standby mode, operations of this LSI cannot be guaranteed after the interrupt
occurred.
(a)
Exit from Software Standby by a Reset
When the RES pin is driven low, this LSI enters the power-on reset and software standby mode is
exited.
Keep the RES pin low until the clock oscillation settles.
Internal clock pulses are output continuously on the CK pin.
28.4.3
(1)
Module Standby Function
Transition to Module Standby Function
Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding
on-chip peripheral modules. This function can be used to reduce the power consumption in normal
mode and sleep mode. Disable a module before placing it in the module standby state. In addition,
do not access the module's registers while it is in the module standby state.
For details of register states, refer to section 30.3, Register States in Each Operating Mode.
(2)
Canceling Module Standby Function
The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on
reset (only possible for H-UDI, UBC, DMAC, and DTC). When taking a module out of the
module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to confirm
that it has been cleared to 0.
Page 1536 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
28.5
Usage Notes
28.5.1
Current Consumption during Oscillation Settling Time
Section 28 Power-Down Modes
While waiting for clock oscillation to settle, the current consumption is increased.
28.5.2
Notes on Writing to Registers
When writing to a register related to power-down modes by the CPU, after the CPU executes the
write instruction, it then executes the subsequent instruction without waiting for the actual writing
process to the register to finish.
To update the change made by writing to a register while executing the subsequent instruction,
perform a dummy read to the same register between the instruction to write to the register and the
subsequent instruction.
28.5.3
Notes on Canceling Software Standby Mode with an IRQx Interrupt Request
When canceling software standby mode using an IRQx interrupt request, change the IRQ sense
select setting of ICRx in a state in which no IRQx interrupt requests are generated and clear the
IRQxF flag in IRQRRx to 0 by the automatic clearing function of the IRQx interrupt processing.
If the IRQxF flag in the IRQ interrupt request register x (IRQRRx) is 1, changing the setting of the
IRQ sense select bits in the interrupt control register x (ICRx) or clearing the IRQxF flag in
IRQRRx to 0 will clear the relevant IRQx interrupt request but will not clear the software standby
cancellation request.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1537 of 1778
Section 28 Power-Down Modes
Page 1538 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 29 User Debugging Interface (H-UDI)
Section 29 User Debugging Interface (H-UDI)
This LSI incorporates a user debugging interface (H-UDI) for emulator support.
29.1
Features
The user debugging interface (H-UDI) has reset and interrupt request functions.
The H-UDI in this LSI is used for emulator connection. Refer to the emulator manual for the
method of connecting the emulator.
Figure 29.1 shows a block diagram of the H-UDI.
SDBPR
TDO
Shift register
TDI
SDIR
MUX
TCK
TMS
TAP control circuit
Decoder
Local
bus
TRST
[Legend]
SDBPR:
SDIR:
Bypass register
Instruction register
Figure 29.1 Block Diagram of H-UDI
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1539 of 1778
SH7280 Group, SH7243 Group
Section 29 User Debugging Interface (H-UDI)
29.2
Input/Output Pins
Table 29.1 Pin Configuration
Pin Name
I/O
Function
H-UDI serial data input/output TCK
clock pin
Input
Data is serially supplied to the H-UDI from
the data input pin (TDI), and output from
the data output pin (TDO), in
synchronization with this clock.
Mode select input pin
TMS
Input
The state of the TAP control circuit is
determined by changing this signal in
synchronization with TCK. For the protocol,
see figure 29.2.
H-UDI reset input pin
TRST
Input
Input is accepted asynchronously with
respect to TCK, and when low, the H-UDI is
reset. TRST must be low for a constant
period when power is turned on regardless
of using the H-UDI function. See section
29.4.2, Reset Configuration, for more
information.
H-UDI serial data input pin
TDI
Input
Data transfer to the H-UDI is executed by
changing this signal in synchronization with
TCK.
H-UDI serial data output pin
TDO
Output
Data read from the H-UDI is executed by
reading this pin in synchronization with
TCK. The initial value of the data output
timing is the TCK falling edge. This can be
changed to the TCK rising edge by
inputting the TDO change timing switch
command to SDIR. See section 29.4.3,
TDO Output Timing, for more information.
ASE mode select pin
ASEMD0* Input
Note:
*
Symbol
If a low level is input at the ASEMD0 pin
while the RES pin is asserted, ASE mode is
entered; if a high level is input, normal
mode is entered. In ASE mode, dedicated
emulator function can be used. The input
level at the ASEMD0 pin should be held for
at least one cycle after RES negation.
When the emulator is not in use, fix this pin to the high level.
Page 1540 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
29.3
Section 29 User Debugging Interface (H-UDI)
Register Descriptions
The H-UDI has the following registers.
Table 29.2 Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Access Size
Bypass register
SDBPR
⎯
⎯
⎯
⎯
Instruction register
SDIR
R
H'EFFD
H'FFFE2000
16
29.3.1
Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
29.3.2
Instruction Register (SDIR)
SDIR is a 16-bit read-only register. It is initialized by TRST assertion or in the TAP test-logicreset state, and can be written to by the H-UDI irrespective of CPU mode. Operation is not
guaranteed if a reserved command is set in this register. The initial value is H'EFFD.
Bit:
15
14
13
12
11
10
9
8
TI[7:0]
Initial value:
R/W:
1*
R
1*
R
1*
R
0*
R
1*
R
1*
R
1*
R
1*
R
7
6
5
4
3
2
1
-
-
-
-
-
-
-
0
-
1
R
1
R
1
R
1
R
1
R
1
R
0
R
1
R
Note: * The initial value of the TI[7:0] bits is a reserved value. When setting a command, the TI[7:0] bits must be set to another value.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1541 of 1778
SH7280 Group, SH7243 Group
Section 29 User Debugging Interface (H-UDI)
Bit
Bit Name
Initial Value
R/W
Description
15 to 8
TI[7:0]
11101111*
R
Test Instruction
The H-UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 29.3.
⎯
7 to 2
All 1
R
Reserved
These bits are always read as 1.
⎯
1
0
R
Reserved
This bit is always read as 0.
⎯
0
1
R
Reserved
This bit is always read as 1.
Table 29.3 H-UDI Commands
Bits 15 to 8
TI7
TI6
TI5
TI4
TI3
TI2
TI1
TI0
Description
0
1
1
0
—
—
—
—
H-UDI reset negate
0
1
1
1
—
—
—
—
H-UDI reset assert
1
0
0
1
1
1
0
0
TDO change timing switch
1
0
1
1
—
—
—
—
H-UDI interrupt
1
1
1
1
—
—
—
—
BYPASS mode
Other than above
Page 1542 of 1778
Reserved
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 29 User Debugging Interface (H-UDI)
29.4
Operation
29.4.1
TAP Controller
Figure 29.2 shows the internal states of the TAP controller.
1
Test -logic-reset
0
1
0
1
Run-test/idle
1
Select-DR
Select-IR
0
0
1
1
Capture-DR
Capture-IR
0
0
Shift-DR
0
Shift-IR
1
0
1
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
1
0
0
Pause-IR
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
1
1
0
0
Figure 29.2 TAP Controller State Transitions
Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is
sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details
on change timing of the TDO value, see section 29.4.3, TDO Output Timing. The TDO is
at high impedance, except with shift-DR and shift-IR states. During the change to TRST =
0, there is a transition to test-logic-reset asynchronously with TCK.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1543 of 1778
SH7280 Group, SH7243 Group
Section 29 User Debugging Interface (H-UDI)
29.4.2
Reset Configuration
Table 29.4 Reset Configuration
ASEMD0*1
RES
TRST
Chip State
H
L
L
Power-on reset and H-UDI reset
H
Power-on reset
H
L
L
H
L
H-UDI reset only (normal operation)
H
Normal operation
L
Reset hold*2
H
Power-on reset
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs normal mode and ASE mode settings
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is
negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI
operation is enabled, but the CPU does not start up. The reset hold state is cancelled
by a power-on reset.
29.4.3
TDO Output Timing
The initial value of the TDO change timing is to perform data output from the TDO pin on the
TCK falling edge. However, setting a TDO change timing switch command in SDIR via the HUDI pin and passing the Update-IR state synchronizes the TDO change timing to the TCK rising
edge. Thereafter the TDO change timing cannot be changed unless a power-on reset that asserts
the TRST pin simultaneously is performed.
TCK
TDO
(after execution of TDO change
timing switch command)
tTDOD
tTDOD
TDO
(initial value)
Figure 29.3 H-UDI Data Transfer Timing
Page 1544 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
29.4.4
Section 29 User Debugging Interface (H-UDI)
H-UDI Reset
An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by setting an H-UDI reset
negate command. The required time between the H-UDI reset assert command and H-UDI reset
negate command is the same as time for keeping the RES pin low to apply a power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
Fetch the initial values of PC and SR from
the exception handling vector table
CPU state
Figure 29.4 H-UDI Reset
29.4.5
H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in fetching the
exception service routine start address from the exception handling vector table, jumping to that
address, and starting program execution from that address. This interrupt request has a fixed
priority level of 15.
H-UDI interrupts are accepted in sleep mode, but not in software standby mode.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1545 of 1778
Section 29 User Debugging Interface (H-UDI)
29.5
SH7280 Group, SH7243 Group
Usage Notes
1. An H-UDI command, once set, will not be modified as long as another command is not set
again from the H-UDI. If the same command is to be set continuously, the command must be
set after a command (BYPASS mode, etc.) that does not affect chip operations is once set.
2. In software standby mode, this LSI stops operation and does not accept any H-UDI command.
To retain the TAP status before and after software standby mode, keep TCK high before
entering software standby mode.
Page 1546 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Section 30 List of Registers
This section gives information on the on-chip I/O registers of this LSI in the following structures.
1.
•
•
•
Register Addresses (by functional module, in order of the corresponding section numbers)
Registers are described by functional module, in order of the corresponding section numbers.
Access to reserved addresses which are not described in this register address list is prohibited.
When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big-endian
mode is selected.
2. Register Bits
• Bit configurations of the registers are described in the same order as the Register Addresses
(by functional module, in order of the corresponding section numbers).
• Reserved bits are indicated by — in the bit name.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
3. Register States in Each Operating Mode
• Register states are described in the same order as the Register Addresses (by functional
module, in order of the corresponding section numbers).
• For the initial state of each bit, refer to the description of the register in the corresponding
section.
• The register states described are for the basic operating modes. If there is a specific reset for an
on-chip peripheral module, refer to the section on that on-chip peripheral module.
4. Notes when Writing to the On-Chip Peripheral Modules
• To access an on-chip module register, two or more peripheral module clock (Pf) cycles are
required. Care must be taken in system design. When the CPU writes data to the internal
peripheral registers, the CPU performs the succeeding instructions without waiting for the
completion of writing to registers. For example, a case is described here in which the system is
transferring to the software standby mode for power savings. To make this transition, the
SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1.
However a dummy read of the STBCR register is required before executing the SLEEP
instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the
STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy
read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the
change by internal peripheral registers while performing the succeeding instructions, execute a
dummy read of registers to which write instruction is given and then perform the succeeding
instructions.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1547 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
30.1
Register Addresses (by functional module, in order of the
corresponding section numbers)
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
CPG
Frequency control register
FRQCR
16
H'FFFE0010
16
MTU2S clock frequency control register
MCLKCR
8
H'FFFE0410
8
AD clock frequency control register
ACLKCR
INTC
UBC
8
H'FFFE0414
8
Oscillation stop detection control register OSCCR
8
H'FFFE001C
8
Interrupt control register 0
ICR0
16
H'FFFE0800
16, 32
Interrupt control register 1
ICR1
16
H'FFFE0802
16
IRQ interrupt request register
IRQRR
16
H'FFFE0806
16
Bank control register
IBCR
16
H'FFFE080C
16, 32
Bank number register
IBNR
16
H'FFFE080E
16
Interrupt priority register 01
IPR01
16
H'FFFE0818
16, 32
Interrupt priority register 02
IPR02
16
H'FFFE081A
16
Interrupt priority register 05
IPR05
16
H'FFFE0820
16
Interrupt priority register 06
IPR06
16
H'FFFE0C00
16, 32
Interrupt priority register 07
IPR07
16
H'FFFE0C02
16
Interrupt priority register 08
IPR08
16
H'FFFE0C04
16, 32
Interrupt priority register 09
IPR09
16
H'FFFE0C06
16
Interrupt priority register 10
IPR10
16
H'FFFE0C08
16, 32
Interrupt priority register 11
IPR11
16
H'FFFE0C0A
16
Interrupt priority register 12
IPR12
16
H'FFFE0C0C
16, 32
Interrupt priority register 13
IPR13
16
H'FFFE0C0E
16
Interrupt priority register 14
IPR14
16
H'FFFE0C10
16, 32
Interrupt priority register 15
IPR15
16
H'FFFE0C12
16
Interrupt priority register 16
IPR16
16
H'FFFE0C14
16, 32
Interrupt priority register 17
IPR17
16
H'FFFE0C16
16
Interrupt priority register 18
IPR18
16
H'FFFE0C18
16
USB-DTC transfer interrupt request
register
USDTENDRR
16
H'FFFE0C50
16
Break address register_0
BAR_0
32
H'FFFC0400
32
Break address mask register_0
BAMR_0
32
H'FFFC0404
32
Break bus cycle register_0
BBR_0
16
H'FFFC04A0
16
Break address register_1
BAR_1
32
H'FFFC0410
32
Break address mask register_1
BAMR_1
32
H'FFFC0414
32
Page 1548 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
UBC
Break bus cycle register_1
BBR_1
16
H'FFFC04B0
16
Break address register_0
BAR_2
32
H'FFFC0420
32
Break address mask register_2
BAMR_2
32
H'FFFC0424
32
Break bus cycle register_2
BBR_2
16
H'FFFC04A4
16
DTC
BSC
Break address register_3
BAR_3
32
H'FFFC0430
32
Break address mask register_3
BAMR_3
32
H'FFFC0434
32
Break bus cycle register_3
BBR_3
16
H'FFFC04B4
16
Break control register
BRCR
32
H'FFFC04C0
32
DTC enable register A
DTCERA
16
H'FFFE6000
8, 16
DTC enable register B
DTCERB
16
H'FFFE6002
8, 16
DTC enable register C
DTCERC
16
H'FFFE6004
8, 16
DTC enable register D
DTCERD
16
H'FFFE6006
8, 16
DTC enable register E
DTCERE
16
H'FFFE6008
8, 16
DTC control register
DTCCR
8
H'FFFE6010
8
DTC vector base register
DTCVBR
32
H'FFFE6014
8, 16, 32
Common control register
CMNCR
32
H'FFFC0000
32
CS0 space bus control register
CS0BCR
32
H'FFFC0004
32
CS1 space bus control register
CS1BCR
32
H'FFFC0008
32
CS2 space bus control register
CS2BCR
32
H'FFFC000C
32
CS3 space bus control register
CS3BCR
32
H'FFFC0010
32
CS4 space bus control register
CS4BCR
32
H'FFFC0014
32
CS5 space bus control register
CS5BCR
32
H'FFFC0018
32
CS6 space bus control register
CS6BCR
32
H'FFFC001C
32
CS7 space bus control register
CS7BCR
32
H'FFFC0020
32
CS0 space wait control register
CS0WCR
32
H'FFFC0028
32
CS1 space wait control register
CS1WCR
32
H'FFFC002C
32
CS2 space wait control register
CS2WCR
32
H'FFFC0030
32
CS3 space wait control register
CS3WCR
32
H'FFFC0034
32
CS4 space wait control register
CS4WCR
32
H'FFFC0038
32
CS5 space wait control register
CS5WCR
32
H'FFFC003C
32
CS6 space wait control register
CS6WCR
32
H'FFFC0040
32
CS7 space wait control register
CS7WCR
32
H'FFFC0044
32
SDRAM control register
SDCR
32
H'FFFC004C
32
Refresh timer control/status register
RTCSR
32
H'FFFC0050
32
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1549 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
BSC
Refresh timer counter
RTCNT
32
H'FFFC0054
32
Refresh time constant register
RTCOR
32
H'FFFC0058
32
DMAC
Bus function extending register
BSCEHR
16
H'FFFE3C1A
8, 16
DMA source address register_0
SAR_0
32
H'FFFE1000
16, 32
DMA destination address register_0
DAR_0
32
H'FFFE1004
16, 32
DMA transfer count register_0
DMATCR_0
32
H'FFFE1008
16, 32
DMA channel control register_0
CHCR_0
32
H'FFFE100C
8, 16, 32
DMA reload source address register_0
RSAR_0
32
H'FFFE1100
16, 32
DMA reload destination address
register_0
RDAR_0
32
H'FFFE1104
16, 32
DMA reload transfer count register_0
RDMATCR_0
32
H'FFFE1108
16, 32
DMA source address register_1
SAR_1
32
H'FFFE1010
16, 32
DMA destination address register_1
DAR_1
32
H'FFFE1014
16, 32
DMA transfer count register_1
DMATCR_1
32
H'FFFE1018
16, 32
DMA channel control register_1
CHCR_1
32
H'FFFE101C
8, 16, 32
DMA reload source address register_1
RSAR_1
32
H'FFFE1110
16, 32
DMA reload destination address
register_1
RDAR_1
32
H'FFFE1114
16, 32
DMA reload transfer count register_1
RDMATCR_1
32
H'FFFE1118
16, 32
DMA source address register_2
SAR_2
32
H'FFFE1020
16, 32
DMA destination address register_2
DAR_2
32
H'FFFE1024
16, 32
DMA transfer count register_2
DMATCR_2
32
H'FFFE1028
16, 32
DMA channel control register_2
CHCR_2
32
H'FFFE102C
8, 16, 32
DMA reload source address register_2
RSAR_2
32
H'FFFE1120
16, 32
DMA reload destination address
register_2
RDAR_2
32
H'FFFE1124
16, 32
DMA reload transfer count register_2
RDMATCR_2
32
H'FFFE1128
16, 32
DMA source address register_3
SAR_3
32
H'FFFE1030
16, 32
DMA destination address register_3
DAR_3
32
H'FFFE1034
16, 32
DMA transfer count register_3
DMATCR_3
32
H'FFFE1038
16, 32
DMA channel control register_3
CHCR_3
32
H'FFFE103C
8, 16, 32
DMA reload source address register_3
RSAR_3
32
H'FFFE1130
16, 32
DMA reload destination address
register_3
RDAR_3
32
H'FFFE1134
16, 32
DMA reload transfer count register_3
RDMATCR_3
32
H'FFFE1138
16, 32
Page 1550 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
DMAC
DMA source address register_4
SAR_4
32
H'FFFE1040
16, 32
DMA destination address register_4
DAR_4
32
H'FFFE1044
16, 32
DMA transfer count register_4
DMATCR_4
32
H'FFFE1048
16, 32
DMA channel control register_4
CHCR_4
32
H'FFFE104C
8, 16, 32
DMA reload source address register_4
RSAR_4
32
H'FFFE1140
16, 32
DMA reload destination address
register_4
RDAR_4
32
H'FFFE1144
16, 32
DMA reload transfer count register_4
RDMATCR_4
32
H'FFFE1148
16, 32
DMA source address register_5
SAR_5
32
H'FFFE1050
16, 32
DMA destination address register_5
DAR_5
32
H'FFFE1054
16, 32
DMA transfer count register_5
DMATCR_5
32
H'FFFE1058
16, 32
DMA channel control register_5
CHCR_5
32
H'FFFE105C
8, 16, 32
DMA reload source address register_5
RSAR_5
32
H'FFFE1150
16, 32
DMA reload destination address
register_5
RDAR_5
32
H'FFFE1154
16, 32
DMA reload transfer count register_5
RDMATCR_5
32
H'FFFE1158
16, 32
DMA source address register_6
SAR_6
32
H'FFFE1060
16, 32
DMA destination address register_6
DAR_6
32
H'FFFE1064
16, 32
DMA transfer count register_6
DMATCR_6
32
H'FFFE1068
16, 32
DMA channel control register_6
CHCR_6
32
H'FFFE106C
8, 16, 32
DMA reload source address register_6
RSAR_6
32
H'FFFE1160
16, 32
DMA reload destination address
register_6
RDAR_6
32
H'FFFE1164
16, 32
DMA reload transfer count register_6
RDMATCR_6
32
H'FFFE1168
16, 32
DMA source address register_7
SAR_7
32
H'FFFE1070
16, 32
DMA destination address register_7
DAR_7
32
H'FFFE1074
16, 32
DMA transfer count register_7
DMATCR_7
32
H'FFFE1078
16, 32
DMA channel control register_7
CHCR_7
32
H'FFFE107C
8, 16, 32
DMA reload source address register_7
RSAR_7
32
H'FFFE1170
16, 32
DMA reload destination address
register_7
RDAR_7
32
H'FFFE1174
16, 32
DMA reload transfer count register_7
RDMATCR_7
32
H'FFFE1178
16, 32
DMA operation register
DMAOR
16
H'FFFE1200
8, 16
DMA extension resource selector 0
DMARS0
16
H'FFFE1300
16
DMA extension resource selector 1
DMARS1
16
H'FFFE1304
16
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1551 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
DMAC
DMA extension resource selector 2
DMARS2
16
H'FFFE1308
16
DMA extension resource selector 3
DMARS3
16
H'FFFE130C
16
MTU2
Timer control register_0
TCR_0
8
H'FFFE4300
8, 16, 32
Timer mode register_0
TMDR_0
8
H'FFFE4301
8
Timer I/O control register H_0
TIORH_0
8
H'FFFE4302
8, 16
Timer I/O control register L_0
TIORL_0
8
H'FFFE4303
8
Timer interrupt enable register_0
TIER_0
8
H'FFFE4304
8, 16, 32
Timer status register_0
TSR_0
8
H'FFFE4305
8
Timer counter_0
TCNT_0
16
H'FFFE4306
16
Timer general register A_0
TGRA_0
16
H'FFFE4308
16, 32
Timer general register B_0
TGRB_0
16
H'FFFE430A
16
Timer general register C_0
TGRC_0
16
H'FFFE430C
16, 32
Timer general register D_0
TGRD_0
16
H'FFFE430E
16
Timer general register E_0
TGRE_0
16
H'FFFE4320
16, 32
Timer general register F_0
TGRF_0
16
H'FFFE4322
16
Timer interrupt enable register 2_0
TIER2_0
8
H'FFFE4324
8, 16
Timer status register 2_0
TSR2_0
8
H'FFFE4325
8
Timer buffer operation transfer mode
register 2_0
TBTM_0
8
H'FFFE4326
8
Timer control register_1
TCR_1
8
H'FFFE4380
8, 16
Timer mode register_1
TMDR_1
8
H'FFFE4381
8
Timer I/O control register_1
TIOR_1
8
H'FFFE4382
8
Timer interrupt enable register_1
TIER_1
8
H'FFFE4384
8, 16, 32
Timer status register_1
TSR_1
8
H'FFFE4385
8
Timer counter_1
TCNT_1
16
H'FFFE4386
16
Timer general register A_1
TGRA_1
16
H'FFFE4388
16, 32
Timer general register B_1
TGRB_1
16
H'FFFE438A
16
Timer input capture control register
TICCR
8
H'FFFE4390
8
Timer control register_2
TCR_2
8
H'FFFE4000
8, 16
Timer mode register_2
TMDR_2
8
H'FFFE4001
8
Timer I/O control register_2
TIOR_2
8
H'FFFE4002
8
Timer interrupt enable register_2
TIER_2
8
H'FFFE4004
8, 16, 32
Timer status register_2
TSR_2
8
H'FFFE4005
8
Timer counter_2
TCNT_2
16
H'FFFE4006
16
Page 1552 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
MTU2
Timer general register A_2
TGRA_2
16
H'FFFE4008
16, 32
Timer general register B_2
TGRB_2
16
H'FFFE400A
16
Timer control register_3
TCR_3
8
H'FFFE4200
8, 16, 32
Timer mode register_3
TMDR_3
8
H'FFFE4202
8, 16
Timer I/O control register H_3
TIORH_3
8
H'FFFE4204
8, 16, 32
Timer I/O control register L_3
TIORL_3
8
H'FFFE4205
8
Timer interrupt enable register_3
TIER_3
8
H'FFFE4208
8, 16
Timer status register_3
TSR_3
8
H'FFFE422C
8, 16
Timer counter_3
TCNT_3
16
H'FFFE4210
16, 32
Timer general register A_3
TGRA_3
16
H'FFFE4218
16, 32
Timer general register B_3
TGRB_3
16
H'FFFE421A
16
Timer general register C_3
TGRC_3
16
H'FFFE4224
16, 32
Timer general register D_3
TGRD_3
16
H'FFFE4226
16
Timer buffer operation transfer mode
register_3
TBTM_3
8
H'FFFE4238
8, 16
Timer control register_4
TCR_4
8
H'FFFE4201
8
Timer mode register_4
TMDR_4
8
H'FFFE4203
8
Timer I/O control register H_4
TIORH_4
8
H'FFFE4206
8, 16
Timer I/O control register L_4
TIORL_4
8
H'FFFE4207
8
Timer interrupt enable register_4
TIER_4
8
H'FFFE4209
8
Timer status register_4
TSR_4
8
H'FFFE422D
8
Timer counter_4
TCNT_4
16
H'FFFE4212
16
Timer general register A_4
TGRA_4
16
H'FFFE421C
16, 32
Timer general register B_4
TGRB_4
16
H'FFFE421E
16
Timer general register C_4
TGRC_4
16
H'FFFE4228
16, 32
Timer general register D_4
TGRD_4
16
H'FFFE422A
16
Timer buffer operation transfer mode
register_4
TBTM_4
8
H'FFFE4239
8
Timer A/D converter start request control TADCR
register
16
H'FFFE4240
16
Timer A/D converter start request cycle
set register A_4
TADCORA_4
16
H'FFFE4244
16, 32
Timer A/D converter start request cycle
set register B_4
TADCORB_4
16
H'FFFE4246
16
Timer A/D converter start request cycle
set buffer register A_4
TADCOBRA_4
16
H'FFFE4248
16, 32
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1553 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
MTU2
Register Name
Abbreviation
Number
of Bits Address
Access
Size
Timer A/D converter start request cycle
set buffer register B_4
TADCOBRB_4
16
H'FFFE424A
16
Timer control register U_5
TCRU_5
8
H'FFFE4084
8
Timer control register V_5
TCRV_5
8
H'FFFE4094
8
Timer control register W_5
TCRW_5
8
H'FFFE40A4
8
Timer I/O control register U_5
TIORU_5
8
H'FFFE4086
8
Timer I/O control register V_5
TIORV_5
8
H'FFFE4096
8
Timer I/O control register W_5
TIORW_5
8
H'FFFE40A6
8
Timer interrupt enable register_5
TIER_5
8
H'FFFE40B2
8
Timer status register_5
TSR_5
8
H'FFFE40B0
8
Timer start register_5
TSTR_5
8
H'FFFE40B4
8
Timer counter U_5
TCNTU_5
16
H'FFFE4080
16
Timer counter V_5
TCNTV_5
16
H'FFFE4090
16
Timer counter W_5
TCNTW_5
16
H'FFFE40A0
16
Timer general register U_5
TGRU_5
16
H'FFFE4082
16
Timer general register V_5
TGRV_5
16
H'FFFE4092
16
Timer general register W_5
TGRW_5
16
H'FFFE40A2
16
Timer compare match clear register
TCNTCMPCLR
8
H'FFFE40B6
8
Timer start register
TSTR
8
H'FFFE4280
8
Timer synchronous register
TSYR
8
H'FFFE4281
8
Timer counter synchronous start register TCSYSTR
8
H'FFFE4282
8
Timer read/write enable register
TRWER
8
H'FFFE4284
8
Timer output master enable register
TOER
8
H'FFFE420A
8
Timer output control register 1
TOCR1
8
H'FFFE420E
8, 16
Timer output control register 2
TOCR2
8
H'FFFE420F
8
Timer gate control register
TGCR
8
H'FFFE420D
8
Timer cycle control register
TCDR
16
H'FFFE4214
16, 32
Timer dead time data register
TDDR
16
H'FFFE4216
16
Timer subcounter
TCNTS
16
H'FFFE4220
16, 32
Timer cycle buffer register
TCBR
16
H'FFFE4222
16
Timer cycle buffer register
TITCR
8
H'FFFE4230
8, 16
Timer interrupt skipping counter
TITCNT
8
H'FFFE4231
8
Timer buffer transfer set register
TBTER
8
H'FFFE4232
8
Timer dead time enable register
TDER
8
H'FFFE4234
8
Page 1554 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
MTU2
Timer waveform control register
TWCR
8
H'FFFE4260
8
Timer output level buffer register
TOLBR
8
H'FFFE4236
8
MTU2S
Timer control register_3S
TCR_3S
8
H'FFFE4A00
8, 16, 32
Timer mode register_3S
TMDR_3S
8
H'FFFE4A02
8, 16
Timer I/O control register H_3S
TIORH_3S
8
H'FFFE4A04
8, 16, 32
Timer I/O control register L_3S
TIORL_3S
8
H'FFFE4A05
8
Timer interrupt enable register_3S
TIER_3S
8
H'FFFE4A08
8, 16
Timer status register_3S
TSR_3S
8
H'FFFE4A2C
8, 16
Timer counter_3S
TCNT_3S
16
H'FFFE4A10
16, 32
Timer general register A_3S
TGRA_3S
16
H'FFFE4A18
16, 32
Timer general register B_3S
TGRB_3S
16
H'FFFE4A1A
16
Timer general register C_3S
TGRC_3S
16
H'FFFE4A24
16, 32
Timer general register D_3S
TGRD_3S
16
H'FFFE4A26
16
Timer buffer operation transfer mode
register_3S
TBTM_3S
8
H'FFFE4A38
8, 16
Timer control register_4S
TCR_4S
8
H'FFFE4A01
8
Timer mode register_4S
TMDR_4S
8
H'FFFE4A03
8
Timer I/O control register H_4S
TIORH_4S
8
H'FFFE4A06
8, 16
Timer I/O control register L_4S
TIORL_4S
8
H'FFFE4A07
8
Timer interrupt enable register_4S
TIER_4S
8
H'FFFE4A09
8
Timer status register_4S
TSR_4S
8
H'FFFE4A2D
8
Timer counter_4S
TCNT_4S
16
H'FFFE4A12
16
Timer general register A_4S
TGRA_4S
16
H'FFFE4A1C
16, 32
Timer general register B_4S
TGRB_4S
16
H'FFFE4A1E
16
Timer general register C_4S
TGRC_4S
16
H'FFFE4A28
16, 32
Timer general register D_4S
TGRD_4S
16
H'FFFE4A2A
16
Timer buffer operation transfer mode
register_4S
TBTM_4S
8
H'FFFE4A39
8
Timer A/D converter start request control TADCRS
register S
16
H'FFFE4A40
16
Timer A/D converter start request cycle
set register A_4S
TADCORA_4S
16
H'FFFE4A44
16, 32
Timer A/D converter start request cycle
set register B_4S
TADCORB_4S
16
H'FFFE4A46
16
Timer A/D converter start request cycle
set buffer register A_4S
TADCOBRA_4S
16
H'FFFE4A48
16, 32
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1555 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
MTU2S
Register Name
Abbreviation
Number
of Bits Address
Access
Size
Timer A/D converter start request cycle
set buffer register B_4S
TADCOBRB_4S
16
H'FFFE4A4A
16
Timer control register U_5S
TCRU_5S
8
H'FFFE4884
8
Timer control register V_5S
TCRV_5S
8
H'FFFE4894
8
Timer control register W_5S
TCRW_5S
8
H'FFFE48A4
8
Timer I/O control register U_5S
TIORU_5S
8
H'FFFE4886
8
Timer I/O control register V_5S
TIORV_5S
8
H'FFFE4896
8
Timer I/O control register W_5S
TIORW_5S
8
H'FFFE48A6
8
Timer interrupt enable register_5S
TIER_5S
8
H'FFFE48B2
8
Timer status register_5S
TSR_5S
8
H'FFFE48B0
8
Timer start register_5S
TSTR_5S
8
H'FFFE48B4
8
Timer counter U_5S
TCNTU_5S
16
H'FFFE4880
16, 32
Timer counter V_5S
TCNTV_5S
16
H'FFFE4890
16, 32
Timer counter W_5S
TCNTW_5S
16
H'FFFE48A0
16, 32
Timer general register U_5S
TGRU_5S
16
H'FFFE4882
16
Timer general register V_5S
TGRV_5S
16
H'FFFE4892
16
Timer general register W_5S
TGRW_5S
16
H'FFFE48A2
16
Timer compare match clear register S
TCNTCMPCLRS
8
H'FFFE48B6
8
Timer start register S
TSTRS
8
H'FFFE4A80
8, 16
Timer synchronous register S
TSYRS
8
H'FFFE4A81
8
Timer read/write enable register S
TRWERS
8
H'FFFE4A84
8
Timer output master enable register S
TOERS
8
H'FFFE4A0A
8
Timer output control register 1S
TOCR1S
8
H'FFFE4A0E
8, 16
Timer output control register 2S
TOCR2S
8
H'FFFE4A0F
8
Timer gate control register S
TGCRS
8
H'FFFE4A0D
8
Timer cycle control register S
TCDRS
16
H'FFFE4A14
16, 32
Timer dead time data register S
TDDRS
16
H'FFFE4A16
16
Timer subcounter S
TCNTSS
16
H'FFFE4A20
16, 32
Timer cycle buffer register S
TCBRS
16
H'FFFE4A22
16
Timer interrupt skipping set register S
TITCRS
8
H'FFFE4A30
8, 16
Timer interrupt skipping counter S
TITCNTS
8
H'FFFE4A31
8
Timer buffer transfer set register S
TBTERS
8
H'FFFE4A32
8
Timer dead time enable register S
TDERS
8
H'FFFE4A34
8
Timer synchronous clear register S
TSYCRS
8
H'FFFE4A50
8
Page 1556 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
MTU2S
Timer waveform control register S
TWCRS
8
H'FFFE4A60
8
Timer output level buffer register S
TOLBRS
8
H'FFFE4A36
8
Input level control/status register 1
ICSR1
16
H'FFFE5000
16
Output level control/status register 1
OCSR1
16
H'FFFE5002
16
Input level control/status register 2
ICSR2
16
H'FFFE5004
16
Output level control/status register 2
OCSR2
16
H'FFFE5006
16
Input level control/status register 3
ICSR3
16
H'FFFE5008
16
Software port output enable register
SPOER
8
H'FFFE500A
8
Port output enable control register 1
POECR1
8
H'FFFE500B
8
Port output enable control register 2
POECR2
16
H'FFFE500C
16
POE2
CMT
WDT
Compare match timer start register
CMSTR
16
H'FFFEC000
16
Compare match timer control/status
register_0
CMCSR_0
16
H'FFFEC002
16
Compare match counter_0
CMCNT_0
16
H'FFFEC004
16
Compare match constant register_0
CMCOR_0
16
H'FFFEC006
16
Compare match timer control/status
register_1
CMCSR_1
16
H'FFFEC008
16
Compare match counter_1
CMCNT_1
16
H'FFFEC00A
16
Compare match constant register_1
CMCOR_1
16
H'FFFEC00C
16
Watchdog timer control/status register
WTCSR
16
H'FFFE0000
*
Watchdog timer counter
WTCNT
16
H'FFFE0002
*
Watchdog reset control/status register
WRCSR
16
H'FFFE0004
*
SCI
Serial mode register_0
(channel 0)
Bit rate register_0
SCSMR_0
8
H'FFFF8000
8
SCBRR_0
8
H'FFFF8002
8
Serial control register_0
SCSCR_0
8
H'FFFF8004
8
Transmit data register_0
SCTDR_0
8
H'FFFF8006
8
Serial status register_0
SCSSR_0
8
H'FFFF8008
8
Receive data register_0
SCRDR_0
8
H'FFFF800A
8
Serial direction control register_0
SCSDCR_0
8
H'FFFF800C
8
Serial port register_0
SCSPTR_0
8
H'FFFF800E
8
SCI
Serial mode register_1
(channel 1)
Bit rate register_1
Serial control register_1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SCSMR_1
8
H'FFFF8800
8
SCBRR_1
8
H'FFFF8802
8
SCSCR_1
8
H'FFFF8804
8
Page 1557 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Abbreviation
Number
of Bits Address
Access
Size
Transmit data register_1
SCI
(channel 1)
Serial status register_1
SCTDR_1
8
H'FFFF8806
8
SCSSR_1
8
H'FFFF8808
8
Receive data register_1
SCRDR_1
8
H'FFFF880A
8
Serial direction control register_1
SCSDCR_1
8
H'FFFF880C
8
Register Name
Serial port register_1
SCSPTR_1
8
H'FFFF880E
8
SCSMR_2
8
H'FFFF9000
8
SCBRR_2
8
H'FFFF9002
8
Serial control register_2
SCSCR_2
8
H'FFFF9004
8
Transmit data register_2
SCTDR_2
8
H'FFFF9006
8
Serial status register_2
SCSSR_2
8
H'FFFF9008
8
Receive data register_2
SCRDR_2
8
H'FFFF900A
8
Serial direction control register_2
SCSDCR_2
8
H'FFFF900C
8
Serial port register_2
SCSPTR_2
8
H'FFFF900E
8
SCSMR_4
8
H'FFFFA000
8
SCBRR_4
8
H'FFFFA002
8
Serial control register_4
SCSCR_4
8
H'FFFFA004
8
Transmit data register_4
SCTDR_4
8
H'FFFFA006
8
Serial status register_4
SCSSR_4
8
H'FFFFA008
8
SCI
Serial mode register_2
(channel 2)
Bit rate register_2
SCI
Serial mode register_4
(channel 4)
Bit rate register_4
SCIF
SSU
Receive data register_4
SCRDR_4
8
H'FFFFA00A
8
Serial direction control register_4
SCSDCR_4
8
H'FFFFA00C
8
Serial port register_4
SCSPTR_4
8
H'FFFFA00E
8
Serial mode register_3
SCSMR_3
16
H'FFFE9800
16
Bit rate register_3
SCBRR_3
8
H'FFFE9804
8
Serial control register_3
SCSCR_3
16
H'FFFE9808
16
Transmit FIFO data register_3
SCFTDR_3
8
H'FFFE980C
8
Serial status register_3
SCFSR_3
16
H'FFFE9810
16
Receive FIFO data register_3
SCFRDR_3
8
H'FFFE9814
8
FIFO control register_3
SCFCR_3
16
H'FFFE9818
16
FIFO data count register_3
SCFDR_3
16
H'FFFE981C
16
Serial port register_3
SCSPTR_3
16
H'FFFE9820
16
Line status register_3
SCLSR_3
16
H'FFFE9824
16
Serial expanded mode register
SCSEMR_3
8
H'FFFE9900
8
SS control register H
SSCRH
8
H'FFFFB000
8, 16
SS control register L
SSCRL
8
H'FFFFB001
8
Page 1558 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
SSU
SS mode register
SSMR
8
H'FFFFB002
8, 16
SS enable register
SSER
8
H'FFFFB003
8
SS status register
SSSR
8
H'FFFFB004
8, 16
SS control register 2
SSCR2
8
H'FFFFB005
8
SS transmit data register 0
SSTDR0
8
H'FFFFB006
8, 16
SS transmit data register 1
SSTDR1
8
H'FFFFB007
8
SS transmit data register 2
SSTDR2
8
H'FFFFB008
8, 16
SS transmit data register 3
SSTDR3
8
H'FFFFB009
8
SS receive data register 0
SSRDR0
8
H'FFFFB00A
8, 16
SS receive data register 1
SSRDR1
8
H'FFFFB00B
8
SS receive data register 2
SSRDR2
8
H'FFFFB00C
8, 16
SS receive data register 3
SSRDR3
8
H'FFFFB00D
8
2
ICCR1
8
H'FFFEE000
8
2
ICCR2
8
H'FFFEE001
8
2
ICMR
8
H'FFFEE002
8
2
ICIER
8
H'FFFEE003
8
I C bus status register
2
ICSR
8
H'FFFEE004
8
Slave address register
8
IIC3
I C bus control register 1
I C bus control register 2
I C bus mode register
I C bus interrupt enable register
SAR
8
H'FFFEE005
2
ICDRT
8
H'FFFEE006
8
I C bus receive data register
2
ICDRR
8
H'FFFEE007
8
I C bus transmit data register
ADC
NF2CYC register
NF2CYC
8
H'FFFEE008
8
A/D control register_0
ADCR_0
8
H'FFFFE800
8
A/D status register_0
ADSR_0
8
H'FFFFE802
8
A/D start trigger select register_0
ADSTRGR_0
8
H'FFFFE81C
8
A/D analog input channel select
register_0
ADANSR_0
8
H'FFFFE820
8
A/D bypass control register_0
ADBYPSCR_0
8
H'FFFFE830
8
A/D data register 0
ADDR0
16
H'FFFFE840
16
A/D data register 1
ADDR1
16
H'FFFFE842
16
A/D data register 2
ADDR2
16
H'FFFFE844
16
A/D data register 3
ADDR3
16
H'FFFFE846
16
A/D control register_1
ADCR_1
8
H'FFFFEC00
8
A/D control register_1
ADSR_1
8
H'FFFFEC02
8
A/D start trigger select register_1
ADSTRGR_1
8
H'FFFFEC1C
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1559 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
ADC
DAC
RCAN-ET
Register Name
Abbreviation
Number
of Bits Address
Access
Size
A/D analog input channel select
register_1
ADANSR_1
8
H'FFFFEC20
8
A/D bypass control register_1
ADBYPSCR_1
8
H'FFFFEC30
8
A/D data register 4
ADDR4
16
H'FFFFEC40
16
A/D data register 5
ADDR5
16
H'FFFFEC42
16
A/D data register 6
ADDR6
16
H'FFFFEC44
16
A/D data register 7
ADDR7
16
H'FFFFEC46
16
A/D control register_2
ADCR_2
8
H'FFFFEE00
8
A/D status register_2
ADSR_2
8
H'FFFFEE02
8
A/D start trigger select register_2
ADSTRGR_2
8
H'FFFFEE1C
8
A/D analog input channel select
register_2
ADANSR_2
8
H'FFFFEE20
8
A/D bypass control register_2
ADBYPSCR_2
8
H'FFFFEE30
8
A/D data register 8
ADDR8
16
H'FFFFEE40
16
A/D data register 9
ADDR9
16
H'FFFFEE42
16
A/D data register 10
ADDR10
16
H'FFFFEE44
16
A/D data register 11
ADDR11
16
H'FFFFEE46
16
D/A data register 0
DADR0
8
H'FFFE6800
8, 16
D/A data register 1
DADR1
8
H'FFFE6801
8, 16
D/A control register
DACR
8
H'FFFE6802
8, 16
Master control register
MCR
16
H'FFFFD000
16
General control register
GSR
16
H'FFFFD002
16
Bit configuration register 1
BCR1
16
H'FFFFD004
16
Bit configuration register 0
BCR0
16
H'FFFFD006
16
Interrupt request register
IRR
16
H'FFFFD008
16
Interrupt mask register
IMR
16
H'FFFFD00A
16
Transmit error counter/Receive error
counter
TEC/REC
16
H'FFFFD00C
16
Transmit wait register 1, 0
TXPR1, 0
32
H'FFFFD020
32
Transmit cancel register 0
TXCR0
16
H'FFFFD02A
16
Transmit acknowledge register 0
TXACK0
16
H'FFFFD032
16
Abort acknowledge register 0
ABACK0
16
H'FFFFD03A
16
Data frame receive completion register
RXPR0
16
H'FFFFD042
16
Remote frame receive completion
register
RFPR0
16
H'FFFFD04A
16
Page 1560 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
RCAN-ET
Mailbox interrupt mask register 0
MBIMR0
16
H'FFFFD052
16
Unread message status register 0
UMSR0
16
H'FFFFD05A
16
MB[0].
MB[1].
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
CONTROL0H
—
16
H'FFFFD100
16, 32
CONTROL0L
—
16
H'FFFFD102
16
LAFMH
—
16
H'FFFFD104
16, 32
LAFML
—
16
H'FFFFD106
16
MSG_DATA[0]
—
8
H'FFFFD108
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD109
8
MSG_DATA[2]
—
8
H'FFFFD10A
8, 16
MSG_DATA[3]
—
8
H'FFFFD10B
8
MSG_DATA[4]
—
8
H'FFFFD10C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD10D
8
MSG_DATA[6]
—
8
H'FFFFD10E
8, 16
MSG_DATA[7]
—
8
H'FFFFD10F
8
CONTROL1H
—
8
H'FFFFD110
8, 16
CONTROL1L
—
8
H'FFFFD111
8
CONTROL0H
—
16
H'FFFFD120
16, 32
CONTROL0L
—
16
H'FFFFD122
16
LAFMH
—
16
H'FFFFD124
16, 32
LAFML
—
16
H'FFFFD126
16
MSG_DATA[0]
—
8
H'FFFFD128
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD129
8
MSG_DATA[2]
—
8
H'FFFFD12A
8, 16
MSG_DATA[3]
—
8
H'FFFFD12B
8
MSG_DATA[4]
—
8
H'FFFFD12C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD12D
8
MSG_DATA[6]
—
8
H'FFFFD12E
8, 16
MSG_DATA[7]
—
8
H'FFFFD12F
8
CONTROL1H
—
8
H'FFFFD130
8, 16
CONTROL1L
—
8
H'FFFFD131
8
Page 1561 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
RCAN-ET
MB[2].
MB[3].
Page 1562 of 1778
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD140
16, 32
CONTROL0L
—
16
H'FFFFD142
16
LAFMH
—
16
H'FFFFD144
16, 32
LAFML
—
16
H'FFFFD146
16
MSG_DATA[0]
—
8
H'FFFFD148
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD149
8
MSG_DATA[2]
—
8
H'FFFFD14A
8, 16
MSG_DATA[3]
—
8
H'FFFFD14B
8
MSG_DATA[4]
—
8
H'FFFFD14C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD14D
8
MSG_DATA[6]
—
8
H'FFFFD14E
8, 16
MSG_DATA[7]
—
8
H'FFFFD14F
8
CONTROL1H
—
8
H'FFFFD150
8, 16
CONTROL1L
—
8
H'FFFFD151
8
CONTROL0H
—
16
H'FFFFD160
16, 32
CONTROL0L
—
16
H'FFFFD162
16
LAFMH
—
16
H'FFFFD164
16, 32
LAFML
—
16
H'FFFFD166
16
MSG_DATA[0]
—
8
H'FFFFD168
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD169
8
MSG_DATA[2]
—
8
H'FFFFD16A
8, 16
MSG_DATA[3]
—
8
H'FFFFD16B
8
MSG_DATA[4]
—
8
H'FFFFD16C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD16D
8
MSG_DATA[6]
—
8
H'FFFFD16E
8, 16
MSG_DATA[7]
—
8
H'FFFFD16F
8
CONTROL1H
—
8
H'FFFFD170
8, 16
CONTROL1L
—
8
H'FFFFD171
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
Register Name
RCAN-ET
MB[4].
MB[5].
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 30 List of Registers
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD180
16, 32
CONTROL0L
—
16
H'FFFFD182
16
LAFMH
—
16
H'FFFFD184
16, 32
LAFML
—
16
H'FFFFD186
16
MSG_DATA[0]
—
8
H'FFFFD188
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD189
8
MSG_DATA[2]
—
8
H'FFFFD18A
8, 16
MSG_DATA[3]
—
8
H'FFFFD18B
8
MSG_DATA[4]
—
8
H'FFFFD18C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD18D
8
MSG_DATA[6]
—
8
H'FFFFD18E
8, 16
MSG_DATA[7]
—
8
H'FFFFD18F
8
CONTROL1H
—
8
H'FFFFD190
8, 16
CONTROL1L
—
8
H'FFFFD191
8
CONTROL0H
—
16
H'FFFFD1A0
16, 32
CONTROL0L
—
16
H'FFFFD1A2
16
LAFMH
—
16
H'FFFFD1A4
16, 32
LAFML
—
16
H'FFFFD1A6
16
MSG_DATA[0]
—
8
H'FFFFD1A8
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD1A9
8
MSG_DATA[2]
—
8
H'FFFFD1AA
8, 16
MSG_DATA[3]
—
8
H'FFFFD1AB
8
MSG_DATA[4]
—
8
H'FFFFD1AC
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD1AD
8
MSG_DATA[6]
—
8
H'FFFFD1AE
8, 16
MSG_DATA[7]
—
8
H'FFFFD1AF
8
CONTROL1H
—
8
H'FFFFD1B0
8, 16
CONTROL1L
—
8
H'FFFFD1B1
8
Page 1563 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
RCAN-ET
MB[6].
MB[7].
Page 1564 of 1778
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD1C0
16, 32
CONTROL0L
—
16
H'FFFFD1C2
16
LAFMH
—
16
H'FFFFD1C4
16, 32
LAFML
—
16
H'FFFFD1C6
16
MSG_DATA[0]
—
8
H'FFFFD1C8
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD1C9
8
MSG_DATA[2]
—
8
H'FFFFD1CA
8, 16
MSG_DATA[3]
—
8
H'FFFFD1CB
8
MSG_DATA[4]
—
8
H'FFFFD1CC
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD1CD
8
MSG_DATA[6]
—
8
H'FFFFD1CE
8, 16
MSG_DATA[7]
—
8
H'FFFFD1CF
8
CONTROL1H
—
8
H'FFFFD1D0
8, 16
CONTROL1L
—
8
H'FFFFD1D1
8
CONTROL0H
—
16
H'FFFFD1E0
16, 32
CONTROL0L
—
16
H'FFFFD1E2
16
LAFMH
—
16
H'FFFFD1E4
16, 32
LAFML
—
16
H'FFFFD1E6
16
MSG_DATA[0]
—
8
H'FFFFD1E8
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD1E9
8
MSG_DATA[2]
—
8
H'FFFFD1EA
8, 16
MSG_DATA[3]
—
8
H'FFFFD1EB
8
MSG_DATA[4]
—
8
H'FFFFD1EC
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD1ED
8
MSG_DATA[6]
—
8
H'FFFFD1EE
8, 16
MSG_DATA[7]
—
8
H'FFFFD1EF
8
CONTROL1H
—
8
H'FFFFD1F0
8, 16
CONTROL1L
—
8
H'FFFFD1F1
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
Register Name
RCAN-ET
MB[8].
MB[9].
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 30 List of Registers
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD200
16, 32
CONTROL0L
—
16
H'FFFFD202
16
LAFMH
—
16
H'FFFFD204
16, 32
LAFML
—
16
H'FFFFD206
16
MSG_DATA[0]
—
8
H'FFFFD208
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD209
8
MSG_DATA[2]
—
8
H'FFFFD20A
8, 16
MSG_DATA[3]
—
8
H'FFFFD20B
8
MSG_DATA[4]
—
8
H'FFFFD20C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD20D
8
MSG_DATA[6]
—
8
H'FFFFD20E
8, 16
MSG_DATA[7]
—
8
H'FFFFD20F
8
CONTROL1H
—
8
H'FFFFD210
8, 16
CONTROL1L
—
8
H'FFFFD211
8
CONTROL0H
—
16
H'FFFFD220
16, 32
CONTROL0L
—
16
H'FFFFD222
16
LAFMH
—
16
H'FFFFD224
16, 32
LAFML
—
16
H'FFFFD226
16
MSG_DATA[0]
—
8
H'FFFFD228
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD229
8
MSG_DATA[2]
—
8
H'FFFFD22A
8, 16
MSG_DATA[3]
—
8
H'FFFFD22B
8
MSG_DATA[4]
—
8
H'FFFFD22C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD22D
8
MSG_DATA[6]
—
8
H'FFFFD22E
8, 16
MSG_DATA[7]
—
8
H'FFFFD22F
8
CONTROL1H
—
8
H'FFFFD230
8, 16
CONTROL1L
—
8
H'FFFFD231
8
Page 1565 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
RCAN-ET
MB[10].
MB[11].
Page 1566 of 1778
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD240
16, 32
CONTROL0L
—
16
H'FFFFD242
16
LAFMH
—
16
H'FFFFD244
16, 32
LAFML
—
16
H'FFFFD246
16
MSG_DATA[0]
—
8
H'FFFFD248
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD249
8
MSG_DATA[2]
—
8
H'FFFFD24A
8, 16
MSG_DATA[3]
—
8
H'FFFFD24B
8
MSG_DATA[4]
—
8
H'FFFFD24C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD24D
8
MSG_DATA[6]
—
8
H'FFFFD24E
8, 16
MSG_DATA[7]
—
8
H'FFFFD24F
8
CONTROL1H
—
8
H'FFFFD250
8, 16
CONTROL1L
—
8
H'FFFFD251
8
CONTROL0H
—
16
H'FFFFD260
16, 32
CONTROL0L
—
16
H'FFFFD262
16
LAFMH
—
16
H'FFFFD264
16, 32
LAFML
—
16
H'FFFFD266
16
MSG_DATA[0]
—
8
H'FFFFD268
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD269
8
MSG_DATA[2]
—
8
H'FFFFD26A
8, 16
MSG_DATA[3]
—
8
H'FFFFD26B
8
MSG_DATA[4]
—
8
H'FFFFD26C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD26D
8
MSG_DATA[6]
—
8
H'FFFFD26E
8, 16
MSG_DATA[7]
—
8
H'FFFFD26F
8
CONTROL1H
—
8
H'FFFFD270
8, 16
CONTROL1L
—
8
H'FFFFD271
8
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
Register Name
RCAN-ET
MB[12].
MB[13].
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Section 30 List of Registers
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD280
16, 32
CONTROL0L
—
16
H'FFFFD282
16
LAFMH
—
16
H'FFFFD284
16, 32
LAFML
—
16
H'FFFFD286
16
MSG_DATA[0]
—
8
H'FFFFD288
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD289
8
MSG_DATA[2]
—
8
H'FFFFD28A
8, 16
MSG_DATA[3]
—
8
H'FFFFD28B
8
MSG_DATA[4]
—
8
H'FFFFD28C
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD28D
8
MSG_DATA[6]
—
8
H'FFFFD28E
8, 16
MSG_DATA[7]
—
8
H'FFFFD28F
8
CONTROL1H
—
8
H'FFFFD290
8, 16
CONTROL1L
—
8
H'FFFFD291
8
CONTROL0H
—
16
H'FFFFD2A0
16, 32
CONTROL0L
—
16
H'FFFFD2A2
16
LAFMH
—
16
H'FFFFD2A4
16, 32
LAFML
—
16
H'FFFFD2A6
16
MSG_DATA[0]
—
8
H'FFFFD2A8
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD2A9
8
MSG_DATA[2]
—
8
H'FFFFD2AA
8, 16
MSG_DATA[3]
—
8
H'FFFFD2AB
8
MSG_DATA[4]
—
8
H'FFFFD2AC
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD2AD
8
MSG_DATA[6]
—
8
H'FFFFD2AE
8, 16
MSG_DATA[7]
—
8
H'FFFFD2AF
8
CONTROL1H
—
8
H'FFFFD2B0
8, 16
CONTROL1L
—
8
H'FFFFD2B1
8
Page 1567 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
RCAN-ET
MB[14].
MB[15].
PFC
Abbreviation
Number
of Bits Address
Access
Size
CONTROL0H
—
16
H'FFFFD2C0
16, 32
CONTROL0L
—
16
H'FFFFD2C2
16
LAFMH
—
16
H'FFFFD2C4
16, 32
LAFML
—
16
H'FFFFD2C6
16
MSG_DATA[0]
—
8
H'FFFFD2C8
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD2C9
8
MSG_DATA[2]
—
8
H'FFFFD2CA
8, 16
MSG_DATA[3]
—
8
H'FFFFD2CB
8
MSG_DATA[4]
—
8
H'FFFFD2CC
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD2CD
8
MSG_DATA[6]
—
8
H'FFFFD2CE
8, 16
MSG_DATA[7]
—
8
H'FFFFD2CF
8
CONTROL1H
—
8
H'FFFFD2D0
8, 16
CONTROL1L
—
8
H'FFFFD2D1
8
CONTROL0H
—
16
H'FFFFD2E0
16, 32
CONTROL0L
—
16
H'FFFFD2E2
16
LAFMH
—
16
H'FFFFD2E4
16, 32
LAFML
—
16
H'FFFFD2E6
16
MSG_DATA[0]
—
8
H'FFFFD2E8
8, 16, 32
MSG_DATA[1]
—
8
H'FFFFD2E9
8
MSG_DATA[2]
—
8
H'FFFFD2EA
8, 16
MSG_DATA[3]
—
8
H'FFFFD2EB
8
MSG_DATA[4]
—
8
H'FFFFD2EC
8, 16, 32
MSG_DATA[5]
—
8
H'FFFFD2ED
8
MSG_DATA[6]
—
8
H'FFFFD2EE
8, 16
MSG_DATA[7]
—
8
H'FFFFD2EF
8
CONTROL1H
—
8
H'FFFFD2F0
8, 16
CONTROL1L
—
8
H'FFFFD2F1
8
Port A I/O register H
PAIORH
16
H'FFFE3804
8, 16, 32
Port A I/O register L
PAIORL
16
H'FFFE3806
8, 16
Port A control register H2
PACRH2
16
H'FFFE380C
8, 16, 32
Port A control register L4
PACRL4
16
H'FFFE3810
8, 16, 32
Port A control register L3
PACRL3
16
H'FFFE3812
8, 16
Port A control register L2
PACRL2
16
H'FFFE3814
8, 16, 32
Page 1568 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
PFC
Port A control register L1
PACRL1
16
H'FFFE3816
8, 16
Port A pull-up MOS control register H
PAPCRH
16
H'FFFE3828
8, 16, 32
Port A pull-up MOS control register L
PAPCRL
16
H'FFFE382A
8, 16
Port B I/O register H
PBIORH
16
H'FFFE3884
8, 16, 32
Port B I/O register L
PBIORL
16
H'FFFE3886
8, 16
Port B control register H1
PBCRH1
16
H'FFFE388E
8, 16
Port B control register L4
PBCRL4
16
H'FFFE3890
8, 16, 32
Port B control register L3
PBCRL3
16
H'FFFE3892
8, 16
Port B control register L2
PBCRL2
16
H'FFFE3894
8, 16, 32
Port B control register L1
PBCRL1
16
H'FFFE3896
8, 16
Port B pull-up MOS control register H
PBPCRH
16
H'FFFE38A8
8, 16, 32
Port B pull-up MOS control register L
PBPCRL
16
H'FFFE38AA
8, 16
Port C I/O register L
PCIORL
16
H'FFFE3906
8, 16
Port C control register L4
PCCRL4
16
H'FFFE3910
8, 16, 32
Port C control register L3
PCCRL3
16
H'FFFE3912
8, 16
Port C control register L2
PCCRL2
16
H'FFFE3914
8, 16, 32
Port C control register L1
PCCRL1
16
H'FFFE3916
8, 16
Port C pull-up MOS control register L
PCPCRL
16
H'FFFE392A
8, 16
Port D I/O register H
PDIORH
16
H'FFFE3984
8, 16, 32
Port D I/O register L
PDIORL
16
H'FFFE3986
8, 16
Port D control register H4
PDCRH4
16
H'FFFE3988
8, 16, 32
Port D control register H3
PDCRH3
16
H'FFFE398A
8, 16
Port D control register H2
PDCRH2
16
H'FFFE398C
8, 16, 32
Port D control register H1
PDCRH1
16
H'FFFE398E
8, 16
Port D control register L4
PDCRL4
16
H'FFFE3990
8, 16, 32
Port D control register L3
PDCRL3
16
H'FFFE3992
8, 16
Port D control register L2
PDCRL2
16
H'FFFE3994
8, 16, 32
Port D control register L1
PDCRL1
16
H'FFFE3996
8, 16
Port D pull-up MOS control register H
PDPCRH
16
H'FFFE39A8
8, 16, 32
Port D pull-up MOS control register L
PDPCRL
16
H'FFFE39AA
8, 16
Port E I/O register L
PEIORL
16
H'FFFE3A06
8, 16
Port E control register L4
PECRL4
16
H'FFFE3A10
8, 16, 32
Port E control register L3
PECRL3
16
H'FFFE3A12
8, 16
Port E control register L2
PECRL2
16
H'FFFE3A14
8, 16, 32
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1569 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
PFC
Port E control register L1
PECRL1
16
H'FFFE3A16
8, 16
Large current Port control register
HCPCR
16
H'FFFE3A20
8, 16, 32
IRQOUT function control register
IFCR
16
H'FFFE3A22
8, 16
Port E pull-up MOS control register L
PEPCRL
16
H'FFFE3A2A
8, 16
I/O port
USB
Port A data register H
PADRH
16
H'FFFE3800
8, 16, 32
Port A data register L
PADRL
16
H'FFFE3802
8, 16
Port A port register H
PAPRH
16
H'FFFE381C
8, 16, 32
Port A port register L
PAPRL
16
H'FFFE381E
8, 16
Port B data register H
PBDRH
16
H'FFFE3880
8, 16, 32
Port B data register L
PBDRL
16
H'FFFE3882
8, 16
Port B port register H
PBPRH
16
H'FFFE389C
8, 16, 32
Port B port register L
PBPRL
16
H'FFFE389E
8, 16
Port C data register L
PCDRL
16
H'FFFE3902
8, 16
Port C port register L
PCPRL
16
H'FFFE391E
8, 16
Port D data register H
PDDRH
16
H'FFFE3980
8, 16, 32
Port D data register L
PDDRL
16
H'FFFE3982
8, 16
Port D port register H
PDPRH
16
H'FFFE399C
8, 16, 32
Port D port register L
PDPRL
16
H'FFFE399E
8, 16
Port E data register L
PEDRL
16
H'FFFE3A02
8, 16
Port E port register L
PEPRL
16
H'FFFE3A1E
8, 16
Port F data register L
PFDRL
16
H'FFFE3A82
8, 16
USB interrupt flag register 0
USBIFR0
8
H'FFFE7000
8
USB interrupt flag register 1
USBIFR1
8
H'FFFE7001
8
USBP0i data register
USBEPDR0i
8
H'FFFE7002
8
USBP0o data register
USBEPDR0o
8
H'FFFE7003
8
USB trigger register
USBTRG
8
H'FFFE7004
8
USBFIFO clear register
USBFCLR
8
H'FFFE7005
8
USBEP0o receive data size register
USBEPSZ0o
8
H'FFFE7006
8
USBEP0s data register
USBEPDR0s
8
H'FFFE7007
8
USB data status register
USBDASTS
8
H'FFFE7008
8
USB interrupt select register 0
USBISR0
8
H'FFFE700A
8
USB end point install register
USBEPSTL
8
H'FFFE700B
8
USB interrupt enable register 0
USBIER0
8
H'FFFE700C
8
USB interrupt enable register 1
USBIER1
8
H'FFFE700D
8
Page 1570 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register Name
Abbreviation
Number
of Bits Address
Access
Size
USB
USBEP1 receive data size register
USBEPSZ1
8
H'FFFE700F
8
USB interrupt select register 1
USBISR1
8
H'FFFE7010
8
FLC
Powerdown
mode
H-UDI
Note:
*
USBDMA transfer setting register
USBDMAR
8
H'FFFE7011
8
USBEP3 data register
USBEPDR3
8
H'FFFE7012
8
USBEP1 data register
USBEPDR1
8
H'FFFE7014
8, 16, 32
USBEP2 data register
USBEPDR2
8
H'FFFE7018
8, 16, 32
Flash code control and status register
FCCS
8
H'FFFFA800
8
Flash program code select register
FPCS
8
H'FFFFA801
8
Flash erase code select register
FECS
8
H'FFFFA802
8
Flash key code register
FKEY
8
H'FFFFA804
8
Flash MAT select register
FMATS
8
H'FFFFA805
8
Flash transfer destination address
register
FTDAR
8
H'FFFFA806
8
ROM cache control register
RCCR
32
H'FFFC1400
32
Standby control register
STBCR
8
H'FFFE0014
8
Standby control register 2
STBCR2
8
H'FFFE0018
8
System control register 1
SYSCR1
8
H'FFFE0402
8
System control register 2
SYSCR2
8
H'FFFE0404
8
Standby control register 3
STBCR3
8
H'FFFE0408
8
Standby control register 4
STBCR4
8
H'FFFE040C
8
Standby control register 5
STBCR5
8
H'FFFE0418
8
Standby control register 6
STBCR6
8
H'FFFE041C
8
Instruction register
SDIR
16
H'FFFE2000
16
The access sizes of the WDT registers are different between the read and write to
prevent incorrect writing.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1571 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
30.2
Module
Name
CPG
Register Bits
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
FRQCR
—
—
—
—
MCLKCR
INTC
—
IFC[2:0]
—
—
—
—
—
STC[2:0]
—
PFC[2:0]
—
—
MSDIVS[1:0]
ASDIVS[1:0]
ACLKCR
—
—
—
—
—
—
OSCCR
—
—
—
—
—
OSCSTOP
ICR0
ICR1
IRQRR
IBCR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IRQ71S
IRQ70S
IRQ61S
IRQ60S
IRQ51S
IRQ50S
IRQ41S
IRQ40S
IRQ31S
IRQ30S
IRQ21S
IRQ20S
IRQ11S
IRQ10S
IRQ01S
IRQ00S
—
—
—
—
—
—
—
—
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
—
BOVE
—
—
—
—
—
—
—
—
—
BE[1:0]
—
—
IPR01
IPR02
IPR06
IPR07
OSCERS
NMIL
IBNR
IPR05
—
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
—
—
—
—
—
ADI0
ADI1
DMAC0
DMAC1
DMAC2
DMAC3
DMAC4
DMAC5
DMAC6
DMAC7
CMT0
CMT1
BSC
WDT
IPR09
MTU0
MTU0
MTU1
MTU1
IPR11
Page 1572 of 1778
NMIE
BN[3:0]
IPR08
IPR10
Bit
24/16/8/0
MTU2
MTU2
MTU3
MTU3
MTU4
MTU4
MTU5
POE2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
INTC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
IPR12
IPR13
MTU3S
MTU3S
MTU4S
MTU4S
MTU5S
POE2
IIC3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IPR14
—
—
—
—
—
—
—
—
IPR15
—
—
—
—
—
—
—
—
—
—
—
—
IPR16
SCIF3
SCI0
SCI1
SCI2
IPR17
—
—
—
—
SSU
SCI4
ADI2
IPR18
USB
RCAN
USB
USDTENDRR
UBC
BAR_0
BAMR_0
BBR_0
RXF
TXF
BAMR_1
BBR_1
—
—
—
—
—
—
—
—
—
—
—
BA0_30
BA0_29
BA0_28
BA0_27
BA0_26
BA0_25
BA0_24
BA0_23
BA0_22
BA0_21
BA0_20
BA0_19
BA0_18
BA0_17
BA0_16
BA0_15
BA0_14
BA0_13
BA0_12
BA0_11
BA0_10
BA0_9
BA0_8
BA0_7
BA0_6
BA0_5
BA0_4
BA0_3
BA0_2
BA0_1
BA0_0
BAM0_31
BAM0_30
BAM0_29
BAM0_28
BAM0_27
BAM0_26
BAM0_25
BAM0_24
BAM0_23
BAM0_22
BAM0_21
BAM0_20
BAM0_19
BAM0_18
BAM0_17
BAM0_16
BAM0_15
BAM0_14
BAM0_13
BAM0_12
BAM0_11
BAM0_10
BAM0_9
BAM0_8
BAM0_7
BAM0_6
BAM0_5
BAM0_4
BAM0_3
BAM0_2
BAM0_1
BAM0_0
—
—
UBID0
—
—
ID0[1:0]
CP0[2:0]
RW0[1:0]
SZ0[1:0]
BA1_31
BA1_30
BA1_29
BA1_28
BA1_27
BA1_26
BA1_25
BA1_24
BA1_23
BA1_22
BA1_21
BA1_20
BA1_19
BA1_18
BA1_17
BA1_16
BA1_15
BA1_14
BA1_13
BA1_12
BA1_11
BA1_10
BA1_9
BA1_8
BA1_7
BA1_6
BA1_5
BA1_4
BA1_3
BA1_2
BA1_1
BA1_0
BAM1_31
BAM1_30
BAM1_29
BAM1_28
BAM1_27
BAM1_26
BAM1_25
BAM1_24
BAM1_23
BAM1_22
BAM1_21
BAM1_20
BAM1_19
BAM1_18
BAM1_17
BAM1_16
BAM1_15
BAM1_14
BAM1_13
BAM1_12
BAM1_11
BAM1_10
BAM1_9
BAM1_8
BAM1_7
BAM1_6
BAM1_5
BAM1_4
BAM1_3
BAM1_2
BAM1_1
BAM1_0
—
—
UBID1
—
—
CD1[1:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
USB
—
BA0_31
CD0[1:0]
BAR_1
Bit
24/16/8/0
ID1[1:0]
CP1[2:0]
RW1[1:0]
SZ1[1:0]
Page 1573 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
UBC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
BAR_2
BAMR_2
BBR_2
BA2_31
BA2_30
BA2_29
BA2_28
BA2_27
BA2_26
BA2_25
BA2_24
BA2_23
BA2_22
BA2_21
BA2_20
BA2_19
BA2_18
BA2_17
BA2_16
BA2_15
BA2_14
BA2_13
BA2_12
BA2_11
BA2_10
BA2_9
BA2_8
BA2_7
BA2_6
BA2_5
BA2_4
BA2_3
BA2_2
BA2_1
BA2_0
BAM2_31
BAM2_30
BAM2_29
BAM2_28
BAM2_27
BAM2_26
BAM2_25
BAM2_24
BAM2_23
BAM2_22
BAM2_21
BAM2_20
BAM2_19
BAM2_18
BAM2_17
BAM2_16
BAM2_15
BAM2_14
BAM2_13
BAM2_12
BAM2_11
BAM2_10
BAM2_9
BAM2_8
BAM2_7
BAM2_6
BAM2_5
BAM2_4
BAM2_3
BAM2_2
BAM2_1
BAM2_0
—
—
UBID2
—
—
CD2[1:0]
BAR_3
BAMR_3
BBR_3
ID2[1:0]
DTC
DTCERA
CP2[2:0]
RW2[1:0]
SZ2[1:0]
BA3_31
BA3_30
BA3_29
BA3_28
BA3_27
BA3_26
BA3_25
BA3_24
BA3_23
BA3_22
BA3_21
BA3_20
BA3_19
BA3_18
BA3_17
BA3_16
BA3_15
BA3_14
BA3_13
BA3_12
BA3_11
BA3_10
BA3_9
BA3_8
BA3_7
BA3_6
BA3_5
BA3_4
BA3_3
BA3_2
BA3_1
BA3_0
BAM3_31
BAM3_30
BAM3_29
BAM3_28
BAM3_27
BAM3_26
BAM3_25
BAM3_24
BAM3_23
BAM3_22
BAM3_21
BAM3_20
BAM3_19
BAM3_18
BAM3_17
BAM3_16
BAM3_15
BAM3_14
BAM3_13
BAM3_12
BAM3_11
BAM3_10
BAM3_9
BAM3_8
BAM3_7
BAM3_6
BAM3_5
BAM3_4
BAM3_3
BAM3_2
BAM3_1
BAM3_0
—
—
UBID3
—
—
CD3[1:0]
BRCR
Bit
24/16/8/0
—
ID3[1:0]
—
—
CP3[2:0]
RW3[1:0]
—
—
SZ3[1:0]
—
—
—
—
—
—
—
SCMFC0
SCMFC1
SCMFC2
SCMFC3
SCMFD0
SCMFD1
PCB3
PCB2
PCB1
PCB0
—
—
DTCERA15
DTCERA14
DTCERA13
DTCERA12
DTCERA11
DTCERA10
—
—
CKS[1:0]
SCMFD2
SCMFD3
—
—
DTCERA9 DTCERA8
DTCERA7 DTCERA6 DTCERA5 DTCERA4 DTCERA3 DTCERA2 DTCERA1 DTCERA0
DTCERB
DTCERB15
DTCERB14
DTCERB13
DTCERB12
DTCERB11
DTCERB10
DTCERB9 DTCERB8
DTCERB7 DTCERB6 DTCERB5 DTCERB4 DTCERB3 DTCERB2 DTCERB1 DTCERB0
DTCERC
DTCERC15
—
—
—
—
DTCERD
DTCERD15
DTCERD14
DTCERD13
DTCERD12
DTCERC14
DTCERC13
DTCERC12
—
—
DTCCR
Page 1574 of 1778
—
DTCERC3 DTCERC2 DTCERC1 DTCERC0
DTCERD11
DTCERD10 DTCERD9 DTCERD8
DTCERD7 DTCERD6 DTCERD5 DTCERD4 DTCERD3 DTCERD2
DTCERE
—
—
—
DTCERE9 DTCERE8
DTCERE15
DTCERE14
DTCERE13
DTCERE12
DTCERE11
DTCERE10
—
—
—
—
—
—
—
—
—
—
—
RRS
RCHNE
—
—
ERR
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
DTC
BSC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
DTCVBR
CMNCR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BLOCK
DMAIWA
—
—
DMAIW[1:0]
CS0BCR
—
IWW[2:0]
IWRWS[1:0]
—
—
CS1BCR
—
IWRRD[2:0]
—
IWRWS[1:0]
—
CS2BCR
—
—
—
IWRWS[1:0]
—
—
—
—
TYPE[2:0]
—
IWW[2:0]
TYPE[2:0]
—
IWW[2:0]
IWRWS[1:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
IWRRS[2:0]
—
—
—
—
IWRWD[2:0]
BSZ[1:0]
—
IWRWD[2:0]
IWRWS[2]
IWRRS[2:0]
ENDIAN
BSZ[1:0]
—
IWRWD[2:0]
IWRWS[2]
IWRRS[2:0]
ENDIAN
—
—
IWRWS[2]
IWRRS[2:0]
ENDIAN
TYPE[2:0]
—
IWRWS[2]
BSZ[1:0]
IWRRD[2:0]
—
—
—
IWRRD[2:0]
—
—
BSZ[1:0]
—
IWRRD[2:0]
—
—
—
ENDIAN
—
—
IWRWS[2]
IWRRS[2:0]
IWW[2:0]
—
—
IWRRD[2:0]
IWRWS[1:0]
CS6BCR
—
—
IWRWD[2:0]
TYPE[2:0]
IWRWS[1:0]
CS5BCR
—
IWW[2:0]
—
CS4BCR
IWRRS[2:0]
ENDIAN
—
—
IWRWS[2]
BSZ[1:0]
IWRRD[2:0]
—
—
—
IWRWD[2:0]
TYPE[2:0]
—
BSZ[1:0]
—
ENDIAN
—
HIZCNT
IWRWS[2]
IWRWD[2:0]
IWW[2:0]
—
CS3BCR
—
IWRRD[2:0]
IWRWS[1:0]
—
ENDIAN
—
TYPE[2:0]
—
HIZMEM
—
DMAIW[2]
IWRRS[2:0]
IWW[2:0]
—
HIZCKIO
IWRWD[2:0]
TYPE[2:0]
—
DPRTY[1:0]
—
—
BSZ[1:0]
—
—
—
—
Page 1575 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
BSC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
CS7BCR
IWRWS[2]
—
IWW[2:0]
IWRWS[1:0]
—
CS0WCR*1
CS0WCR*2
CS0WCR*4
CS1WCR*1
IWRWD[2:0]
IWRRD[2:0]
TYPE[2:0]
IWRRS[2:0]
ENDIAN
BSZ[1:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BAS
—
—
—
—
—
—
—
WR[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SW[1:0]
BST[1:0]
WR[3:1]
CS2WCR*3
CS3WCR*1
CS3WCR*3
—
BW[1:0]
—
—
—
—
—
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W[3:1]
—
—
—
—
—
—
—
—
—
—
—
W[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BAS
—
BW[1:0]
W[3:1]
WW[2:0]
WR[3:1]
WR[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
BAS
—
—
—
—
—
—
—
WR[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HW[1:0]
A2CL[1]
—
—
—
—
WR[3:1]
—
—
—
—
—
—
—
A2CL[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BAS
—
—
—
—
—
—
—
—
—
WR[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A3CL[1]
—
A3CL[0]
Page 1576 of 1778
HW[1:0]
—
W[0]
SW[1:0]
CS2WCR*1
—
—
WTRP[1:0]
—
—
—
TRWL[1:0]
WR[3:1]
WTRCD[1:0]
—
WTRC[1:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
BSC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
CS4WCR*1
CS4WCR*2
CS5WCR*1
1
CS6WCR*
CS7WCR*1
SDCR
RTCSR
RTCNT
RTCOR
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
—
—
—
—
—
—
—
—
BAS
—
—
—
—
—
—
—
—
SW[1:0]
—
—
—
—
—
—
—
—
—
—
BST[1:0]
—
—
—
W[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
SZSEL
MPXW/
BAS
—
—
—
—
WR[0]
WM
—
SW[1:0]
SW[1:0]
—
—
—
—
—
—
—
—
BAS
—
—
—
—
WR[0]
WM
—
—
—
—
—
—
—
—
—
—
—
—
—
BAS
—
—
—
WR[0]
WM
—
—
—
—
—
—
—
—
—
—
—
DEEP
HW[1:0]
—
—
HW[1:0]
—
—
—
SW[1:0]
WR[3:1]
—
HW[1:0]
—
—
WW[2:0]
SW[1:0]
WR[3:1]
A2ROW[1:0]
SLOW
BW[1:0]
WR[3:1]
—
—
—
—
WW[2:0]
—
—
HW[1:0]
—
W[3:1]
—
—
—
WR[3:1]
—
—
—
WW[2:0]
—
—
Bit
24/16/8/0
RFSH
A3ROW[1:0]
—
RMODE
—
HW[1:0]
—
—
A2COL[1:0]
PDOWN
BACTV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CMF
CMIE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CKS[2:0]
A3COL[1:0]
RRC[2:0]
Page 1577 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
BSC
DMAC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
BSCEHR
Bit
24/16/8/0
DTLOCK
—
—
—
DTBST
DTSA
—
DTPR
—
—
—
—
—
—
—
—
TC
—
—
RLD
—
—
—
—
TL
—
—
HE
HIE
AM
AL
TE
DE
SAR_0
DAR_0
DMATCR_0
CHCR_0
DO
DM[1:0]
DL
SM[1:0]
DS
TB
RS[3:0]
TS[1:0]
IE
RSAR_0
RDAR_0
RDMATCR_0
SAR_1
Page 1578 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
DMAC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
DAR1
DMATCR_1
CHCR_1
TC
—
—
RLD
—
—
—
—
DO
TL
—
—
HE
HIE
AM
AL
DS
TB
TE
DE
DM[1:0]
DL
SM[1:0]
RS[3:0]
TS[1:0]
IE
RSAR_1
RDAR_1
RDMATCR_1
SAR_2
DAR_2
DMATCR_2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1579 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
DMAC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
CHCR_2
Bit
24/16/8/0
TC
—
—
RLD
—
—
—
—
DO
—
—
—
HE
HIE
AM
AL
DL
DS
TB
IE
TE
DE
TC
—
—
—
—
—
—
AM
AL
TE
DE
DM[1:0]
SM[1:0]
RS[3:0]
TS[1:0]
RSAR_2
RDAR_2
RDMATCR_2
SAR_3
DAR_3
DMATCR_3
CHCR_3
DO
DM[1:0]
DL
RLD
—
—
—
HE
HIE
SM[1:0]
DS
TB
RS[3:0]
TS[1:0]
IE
RSAR_3
Page 1580 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
DMAC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
RDAR_3
RDMATCR_3
SAR_4
DAR_4
DMATCR_4
CHCR_4
TC
—
—
—
—
—
DM[1:0]
—
RLD
—
—
—
HE
HIE
SM[1:0]
—
TB
—
—
—
—
TE
DE
RS[3:0]
TS[1:0]
IE
RSAR_4
RDAR_4
RDMATCR_4
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1581 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
DMAC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
SAR_5
DAR_5
DMATCR_5
CHCR_5
TC
—
—
—
—
—
DM[1:0]
—
RLD
—
—
—
HE
HIE
SM[1:0]
—
TB
—
—
—
—
TE
DE
RS[3:0]
TS[1:0]
IE
RSAR_5
RDAR_5
RDMATCR_5
SAR_6
DAR_6
Page 1582 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
DMAC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
DMATCR_6
CHCR_6
TC
—
—
—
—
—
DM[1:0]
—
RLD
—
—
—
HE
HIE
SM[1:0]
—
—
—
—
—
TE
DE
RS[3:0]
TB
TS[1:0]
IE
RSAR_6
RDAR_6
RDMATCR_6
SAR_7
DAR_7
DMATCR_7
CHCR_7
TC
—
—
RLD
—
—
—
—
—
—
—
—
HE
HIE
—
—
—
TB
TE
DE
DM[1:0]
—
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SM[1:0]
RS[3:0]
TS[1:0]
IE
Page 1583 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
DMAC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
RSAR_7
RDAR_7
RDMATCR_7
DMAOR
—
—
—
—
CMS[1:0]
—
—
—
—
—
AE
PR[1:0]
NMIF
CH1MID[5:0]
CH0MID[5:0]
CH0RID[1:0]
DMARS1
CH3MID[5:0]
CH3RID[1:0]
CH2MID[5:0]
CH2RID[1:0]
CH5MID[5:0]
CH5RID[1:0]
DMARS2
DMARS3
CH1RID[1:0]
CH4MID[5:0]
CH4RID[1:0]
CH7MID[5:0]
CH7RID[1:0]
CH6MID[5:0]
MTU2
DME
DMARS0
TCR_0
TMDR_0
CCLR[2:0]
—
BFE
CH6RID[1:0]
CKEG[1:0]
BFB
BFA
TPSC[2:0]
MD[3:0]
TIORH_0
IOB[3:0]
IOA[3:0]
TIORL_0
IOD[3:0]
IOC[3:0]
TIER_0
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_0
—
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_0
TGRA_0
TGRB_0
TGRC_0
Page 1584 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
MTU2
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
TGRD_0
TGRE_0
TGRF_0
TIER2_0
TTGE2
—
—
—
—
TSR2_0
—
—
—
—
TBTM_0
—
—
—
—
TCR_1
—
TMDR_1
—
CCLR[1:0]
—
TIOR_1
—
—
TGIEF
TGIEE
—
—
TGFF
TGFE
—
TTSE
TTSB
TTSA
CKEG[1:0]
TPSC[2:0]
—
MD[3:0]
IOB[3:0]
IOA[3:0]
TIER_1
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
TSR_1
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
TICCR
—
—
—
—
I2BE
I2AE
I1BE
I1AE
TCR_2
—
TMDR_2
—
—
TIER_2
TTGE
TSR_2
TCFD
TCNT_1
TGRA_1
TGRB_1
CCLR[1:0]
CKEG[1:0]
TPSC[2:0]
—
—
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
—
TCFU
TCFV
—
—
TGFB
TGFA
BFB
BFA
TIOR_2
MD[3:0]
IOB[3:0]
IOA[3:0]
TCNT_2
TGRA_2
TGRB_2
TCR_3
TMDR_3
CCLR[2:0]
—
—
CKEG[1:0]
TPSC[2:0]
MD[3:0]
TIORH_3
IOB[3:0]
IOA[3:0]
TIORL_3
IOD[3:0]
IOC[3:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1585 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
MTU2
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
TIER_3
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_3
TCFD
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
—
—
—
—
—
—
TTSB
TTSA
BFB
BFA
TCNT_3
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TBTM_3
TCR_4
TMDR_4
CCLR[2:0]
—
—
CKEG[1:0]
TPSC[2:0]
MD[3:0]
TIORH_4
IOB[3:0]
IOA[3:0]
TIORL_4
IOD[3:0]
IOC[3:0]
TIER_4
TTGE
TTGE2
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_4
TCFD
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
—
—
TCNT_4
TGRA_4
TGRB_4
TGRC_4
TGRD_4
TBTM_4
TADCR
BF[1:0]
UT4AE
DT4AE
—
—
—
—
TTSB
TTSA
—
—
—
—
—
—
UT4BE
DT4BE
ITA3AE
ITA4VE
ITB3AE
ITB4VE
TADCORA_4
TADCORB_4
Page 1586 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
MTU2
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
TADCOBRA_4
TADCOBRB_4
TCRU_5
—
—
—
—
—
—
TPSC[1:0]
TCRV_5
—
—
—
—
—
—
TPSC[1:0]
TCRW_5
—
—
—
—
—
—
TPSC[1:0]
TIORU_5
—
—
—
IOC[4:0]
TIORV_5
—
—
—
IOC[4:0]
TIORW_5
—
—
—
IOC[4:0]
TIER_5
—
—
—
—
—
TGIE5U
TGIE5V
TGIE5W
TSR_5
—
—
—
—
—
CMFU5
CMFV5
CMFW5
TSTR_5
—
—
—
—
—
CSTU5
CSTV5
CSTW5
—
—
—
—
—
TCNTU_5
TCNTV_5
TCNTW_5
TGRU_5
TGRV_5
TGRW_5
TCNTCMPCLR
CMPCLR5U CMPCLR5V
CMPCLR5W
TSTR
CST4
CST3
—
—
—
CST2
CST1
CST0
TSYR
SYNC4
SYNC3
—
—
—
SYNC2
SYNC1
SYNC0
SCH0
SCH1
SCH2
SCH3
SCH4
—
SCH3S
SCH4S
TCSYSTR
TRWER
—
—
—
—
—
—
—
RWE
TOER
—
—
OE4D
OE4C
OE3D
OE4B
OE4A
OE3B
TOCR1
—
TOCR2
TGCR
PSYE
BF[1:0]
—
BDC
—
—
TOCL
TOCS
OLSN
OLSP
OLS3N
OLS3P
OLS2N
OLS2P
OLS1N
OLS1P
N
P
FB
WF
VF
UF
TCDR
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1587 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
MTU2
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
TDDR
TCNTS
TCBR
TITCR
MTU2S
T3AEN
3ACOR[2:0]
T4VEN
TITCNT
—
TBTER
—
—
—
—
—
—
TDER
—
—
—
—
—
—
TWCR
CCE
—
—
—
—
—
SCC
WRE
TOLBR
—
—
OLS3N
OLS3P
OLS2N
OLS2P
OLS1N
OLS1P
TCR_3S
TMDR_3S
3ACNT[2:0]
4VCOR[2:0]
CCLR[2:0]
—
—
TIORH_3S
—
4VCNT[2:0]
CKEG[1:0]
BFB
TDER
TPSC[2:0]
BFA
MD[3:0]
IOB[3:0]
TIORL_3S
BTE[1:0]
—
IOA[3:0]
IOD[3:0]
IOC[3:0]
TIER_3S
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_3S
TCFD
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
—
—
—
—
—
—
TTSB
TTSA
BFB
BFA
TCNT_3S
TGRA_3S
TGRB_3S
TGRC_3S
TGRD_3S
TBTM_3S
TCR_4S
TMDR_4S
CCLR[2:0]
—
—
CKEG[1:0]
TPSC[2:0]
MD[3:0]
TIORH_4S
IOB[3:0]
IOA[3:0]
TIORL_4S
IOD[3:0]
IOC[3:0]
TIER_4S
TTGE
TTGE2
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_4S
TCFD
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_4S
Page 1588 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
MTU2S
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
TGRA_4S
TGRB_4S
TGRC_4S
TGRD_4S
TBTM_4S
—
TADCRS
—
BF[1:0]
UT4AE
DT4AE
—
—
—
—
TTSB
TTSA
—
—
—
—
—
—
UT4BE
DT4BE
ITA3AE
ITA4VE
ITB3AE
ITB4VE
TADCORA_4S
TADCORB_4S
TADCOBRA_4S
TADCOBRB_4S
TCRU_5S
—
—
—
—
—
—
TPSC[1:0]
TCRV_5S
—
—
—
—
—
—
TPSC[1:0]
—
—
—
TPSC[1:0]
TCRW_5S
—
—
—
TIORU_5S
—
—
—
IOC[4:0]
TIORV_5S
—
—
—
IOC[4:0]
TIORW_5S
—
—
—
TIER_5S
—
—
—
—
—
TGIE5U
TGIE5V
TGIE5W
TSR_5S
—
—
—
—
—
CMFU5
CMFV5
CMFW5
TSTR_5S
—
—
—
—
—
CSTU5
CSTV5
CSTW5
IOC[4:0]
TCNTU_5S
TCNTV_5S
TCNTW_5S
TGRU_5S
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1589 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
MTU2S
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
TGRV_5S
TGRW_5S
—
—
—
—
—
TSTRS
CST4
CST3
—
—
—
CST2
CST1
CST0
TSYRS
SYNC4
SYNC3
—
—
—
SYNC2
SYNC1
SYNC0
TCNTCMPCLRS
CMPCLR5U CMPCLR5V
CMPCLR5W
TRWERS
—
—
—
—
—
—
—
RWE
TOERS
—
—
OE4D
OE4C
OE3D
OE4B
OE4A
OE3B
TOCR1S
—
PSYE
—
—
TOCL
TOCS
OLSN
OLSP
OLS3N
OLS3P
OLS2N
OLS2P
OLS1N
OLS1P
N
P
FB
WF
VF
UF
TOCR2S
TGCRS
BF[1:0]
—
BDC
TCDRS
TDDRS
TCNTSS
TCBRS
TITCRS
TITCNTS
—
TBTERS
—
TDERS
3ACOR[2:0]
T4VEN
3ACNT[2:0]
—
—
4VCOR[2:0]
—
—
—
4VCNT[2:0]
—
BTE[1:0]
—
—
—
—
—
—
—
TDER
TSYCRS
CE0A
CE0B
CE0C
CE0D
CE1A
CE1B
CE2A
CE2B
TWCRS
CCE
—
—
—
—
—
SCC
WRE
TOLBRS
POE2
T3AEN
ICSR1
—
—
OLS3N
OLS3P
OLS2N
OLS2P
OLS1N
OLS1P
POE3F
POE2F
POE1F
POE0F
—
—
—
PIE1
POE3M[1:0]
OCSR1
ICSR2
POE2M[1:0]
POE0M[1:0]
OSF1
—
—
—
—
—
OCE1
OIE1
—
—
—
—
—
—
—
—
POE7F
POE6F
POE5F
POE4F
—
—
—
PIE2
POE7M[1:0]
—
POE6M[1:0]
OCSR2
OSF2
—
—
ICSR3
—
—
—
—
—
Page 1590 of 1778
POE1M[1:0]
—
POE5M[1:0]
POE4M[1:0]
—
—
—
OCE2
OIE2
—
—
—
—
—
—
—
POE8F
—
—
POE8E
PIE3
—
—
—
POE8M[1:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
POE2
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
SPOER
—
—
—
—
MTU2SHIZ
MTU2
MTU2
CH0HIZ
CH34HIZ
MTU2PE0ZE
POECR1
—
—
—
—
MTU2PE3ZE
MTU2PE2ZE
MTU2PE1ZE
POECR2
—
MTU2
MTU2
MTU2
—
MTU2S
MTU2S
MTU2S
P1CZE
P2CZE
P3CZE
SP1CZE
SP2CZE
SP3CZE
—
CMT
—
Bit
24/16/8/0
MTU2S
MTU2S
MTU2S
SP4CZE
SP5CZE
SP6CZE
—
MTU2S
MTU2S
MTU2S
SP7CZE
SP8CZE
SP9CZE
CMSTR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STR1
STR0
CMCSR_0
—
—
—
—
—
—
—
—
CMF
CMIE
—
—
—
—
CKS[1:0]
CMF
CMIE
—
—
—
—
CKS[1:0]
IOVF
WT/IT
TME
—
—
WOVF
RSTE
RSTS
—
—
—
SCI
SCSMR_0
(channel 0)
SCBRR_0
C/A
CHR
PE
O/E
STOP
MP
CKS[1:0]
SCSCR_0
TIE
RIE
TE
RE
MPIE
TEIE
CKE[1:0]
TDRE
RDRF
ORER
FER
PER
TEND
CMCNT_0
CMCOR_0
CMCSR_1
CMCNT_1
CMCOR_1
WDT
WTCSR
CKS[2:0]
WTCNT
WRCSR
—
—
SCTDR_0
SCSSR_0
MPB
MPBT
SCRDR_0
SCSDCR_0
—
—
—
—
DIR
—
—
—
SCSPTR_0
EIO
—
—
—
SPB1IO
SPB1DT
—
SPB0DT
SCI
SCSMR_1
(channel 1)
SCBRR_1
C/A
CHR
PE
O/E
STOP
MP
CKS[1:0]
SCSCR_1
TIE
RIE
TE
RE
MPIE
TEIE
CKE[1:0]
TDRE
RDRF
ORER
FER
PER
TEND
SCTDR_1
SCSSR_1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
MPB
MPBT
Page 1591 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
SCI
SCRDR_1
(channel 1)
SCSDCR_1
SCSPTR_1
—
—
—
—
DIR
—
—
—
Bit
24/16/8/0
—
EIO
—
—
—
SPB1IO
SPB1DT
SCI
SCSMR_2
(channel 2)
SCBRR_2
C/A
CHR
PE
O/E
STOP
MP
CKS[1:0]
SPB0DT
SCSCR_2
TIE
RIE
TE
RE
MPIE
TEIE
CKE[1:0]
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SCSDCR_2
—
—
—
—
DIR
—
—
—
SCSPTR_2
—
SCTDR_2
SCSSR_2
SCRDR_2
EIO
—
—
—
SPB1IO
SPB1DT
SCI
SCSMR_4
(channel 4)
SCBRR_4
C/A
CHR
PE
O/E
STOP
MP
CKS[1:0]
SPB0DT
SCSCR_4
TIE
RIE
TE
RE
MPIE
TEIE
CKE[1:0]
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
SCSDCR_4
—
—
—
—
DIR
—
—
—
SCSPTR_4
EIO
—
—
—
SPB1IO
SPB1DT
—
SPB0DT
SCSMR_3
—
—
—
—
—
—
—
—
C/A
CHR
PE
O/E
STOP
—
—
—
—
—
—
—
TIE
RIE
TE
RE
REIE
—
SCTDR_4
SCSSR_4
SCRDR_4
SCIF
CKS[1:0]
SCBRR_3
SCSCR_3
—
—
CKE[1:0]
SCFTDR_3
SCFSR_3
PER[3:0]
FER[3:0]
ER
TEND
TDFE
BRK
FER
PER
RDF
DR
—
—
—
—
—
—
—
—
—
TFRST
RFRST
LOOP
SCFRDR_3
SCFCR_3
RTRG[1:0]
SCFDR_3
—
—
—
—
SCSPTR_3
—
—
—
—
—
—
—
—
—
—
—
—
SCKIO
SCKDT
SPB2IO
SPB2DT
SCLSR_3
SCSEMR_3
Page 1592 of 1778
—
TTRG[1:0]
—
T[4:0]
R[4:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ORER
ABCS
—
—
—
—
—
—
—
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
SSU
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
Bit
24/16/8/0
SSCRH
MSS
BIDE
—
SOL
SOLP
—
CSS[1:0]
SSCRL
—
SSUMS
SRES
—
—
—
DATS[1:0]
SSMR
MLS
CPOS
CPHS
—
—
SSER
TE
RE
—
—
TEIE
TIE
RIE
CEIE
SSSR
—
ORER
—
—
TEND
TDRE
RDRF
CE
SDOS
SSCKOS
SCSOS
TENDSTS
SCSATS
SSODTS
—
—
ICCR1
ICE
RCVD
MST
TRS
ICCR2
BBSY
SCP
SDAO
SDAOP
SCLO
IICRST
—
ICMR
MLS
—
—
—
BCWP
ICIER
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR
TDRE
TEND
RDRF
NACKF
STOP
AL/OVE
AAS
ADZ
SSCR2
CKS[2:0]
SSTDR0
SSTDR1
SSTDR2
SSTDR3
SSRDR0
SSRDR1
SSRDR2
SSRDR3
IIC3
SAR
CKS[3:0]
—
BC[2:0]
SVA[6:0]
FS
ICDRT
ICDRR
ADC
NF2CYC
—
—
—
—
ADCR_0
ADST
ADCS
ACE
ADIE
ADSR_0
—
—
—
—
ADSTRGR_0
—
STR6
STR5
STR4
—
—
—
NF2CYC
—
—
TRGE
EXTRG
—
—
—
ADF
STR3
STR2
STR1
STR0
ANS0
ADANSR_0
—
—
—
—
ANS3
ANS2
ANS1
ADBYPSCR_0
—
—
—
—
—
—
OFC
SH
ADDR0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
ADDR1
ADDR2
ADDR3
ADCR_1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
ADST
ADCS
ACE
ADIE
—
—
TRGE
EXTRG
Page 1593 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
ADC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
ADSR_1
—
—
—
—
—
—
—
ADF
ADSTRGR_1
—
STR6
STR5
STR4
STR3
STR2
STR1
STR0
ANS0
ADANSR_1
—
—
—
—
ANS3
ANS2
ANS1
ADBYPSCR_1
—
—
—
—
—
—
OFC
—
ADDR4
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
ADDR5
ADDR6
ADDR7
ADCR_2
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
ADST
ADCS
ACE
ADIE
—
—
TRGE
EXTRG
ADSR_2
—
—
—
—
—
—
—
ADF
ADSTRGR_2
—
STR6
STR5
STR4
STR3
STR2
STR1
STR0
ANS0
ADANSR_2
—
—
—
—
ANS3
ANS2
ANS1
ADBYPSCR_2
—
—
—
—
—
—
OFC
—
ADDR8
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
ADDR9
ADDR10
ADDR11
DAC
Bit
24/16/8/0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
—
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
—
—
—
DADR0
DADR1
RCAN-ET
DACR
DAOE1
DAOE0
DAE
—
—
MCR
MCR15
MCR14
—
—
—
MCR7
MCR6
MCR5
—
—
MCR2
MCR1
MCR0
—
—
—
—
—
—
—
—
—
—
GSR5
GSR4
GSR3
GSR2
GSR1
GSR0
GSR
BCR1
BCR0
TSG1[3:0]
—
—
—
—
—
SJW[1:0]
—
TST[2:0]
—
TSG2[2:0]
—
—
—
BSP
—
—
—
—
BRP[7:0]
Page 1594 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
RCAN-ET
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
IRR
IMR
TEC/REC
Bit
24/16/8/0
—
—
IRR13
IRR12
—
—
IRR9
IRR8
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0
IMR15
IMR14
IMR13
IMR12
IMR11
IMR10
IMR9
IMR8
IMR7
IMR6
IMR5
IMR4
IMR3
IMR2
IMR1
IMR0
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
TXPR1, 0
TXPR1[15:8]
TXPR1[7:0]
TXPR0[15:8]
TXPR0[7:1]
TXCR0
—
TXCR0[15:8]
TXCR0[7:1]
TXACK0
—
TXACK0[15:8]
TXACK0[7:1]
ABACK0
—
ABACK0[15:8]
ABACK0[7:1]
RXPR0
—
RXPR0[15:8]
RXPR0[7:0]
RFPR0
RFPR0[15:8]
RFPR0[7:0]
MBIMR0
MBIMR0[15:8]
UMSR0
UMSR0[15:8]
MBIMR0[7:0]
UMSR0[7:0]
RCAN-ET
(MCR15 = 1)
MB[0].
CONTROL0H
IDE
RCAN-ET
(MCR15 = 0)
MB[0].
CONTROL0H
—
RCAN-ET
MB[0].
CONTROL0L
RCAN-ET
(MCR15 = 1)
MB[0].
LAFMH
IDE_LAFM
RCAN1-ET
(MCR15 = 0)
MB[0].
LAFMH
—
RCAN-ET
MB[0].
LAFML
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
RTR
—
STDID[10:6]
STDID[5:0]
EXTID[17:16]
STDID[10:4]
STDID[3:0]
RTR
IDE
EXTID[17:16]
EXTID[15:8]
EXTID[7:0]
—
—
STDID_LAFM[10:6]
STDID_LAFM[5:0]
EXTID_LAFM[17:16]
STDID_LAFM[10:4]
STDID_LAFM[3:0]
—
IDE_LAFM
EXTID_LAFM[17:16]
EXTID_LAFM[15:8]
EXTID_LAFM[7:0]
Page 1595 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
RCAN-ET
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
MB[0].
MSG_DATA
[0]
MSG_DATA_0
MB[0].
MSG_DATA
[1]
MSG_DATA_1
MB[0].
MSG_DATA
[2]
MSG_DATA_2
MB[0].
MSG_DATA
[3]
MSG_DATA_3
MB[0].
MSG_DATA
[4]
MSG_DATA_4
MB[0].
MSG_DATA
[5]
MSG_DATA_5
MB[0].
MSG_DATA
[6]
MSG_DATA_6
MB[0].
MSG_DATA
[7]
MSG_DATA_7
MB[0].
CONTROL1H
—
—
NMC
—
MB[0].
CONTROL1L
—
—
—
—
RCAN-ET
(MCR15 = 1)
MB[1].
CONTROL0H
IDE
RTR
—
RCAN-ET
(MCR15 = 0)
MB[1].
CONTROL0H
—
RCAN-ET
MB[1].
CONTROL0L
MB[1].
RCAN-ET
(MCR15 = 1) LAFMH
RCAN1-ET
(MCR15 = 0)
MB[1].
LAFMH
RCAN-ET
MB[1].
LAFML
MB[1].
MSG_DATA
[0]
Page 1596 of 1778
—
Bit
24/16/8/0
MBC[2:0]
DLC[3:0]
STDID[10:6]
STDID[5:0]
EXTID[17:16]
STDID[10:4]
STDID[3:0]
RTR
IDE
EXTID[17:16]
EXTID[15:8]
EXTID[7:0]
IDE_LAFM
—
—
STDID_LAFM[10:6]
STDID_LAFM[5:0]
—
EXTID_LAFM[17:16]
STDID_LAFM[10:4]
STDID_LAFM[3:0]
—
IDE_LAFM
EXTID_LAFM[17:16]
EXTID_LAFM[15:8]
EXTID_LAFM[7:0]
MSG_DATA_0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
RCAN-ET
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
MB[1].
MSG_DATA
[1]
MSG_DATA_1
MB[1].
MSG_DATA
[2]
MSG_DATA_2
MB[1].
MSG_DATA
[3]
MSG_DATA_3
MB[1].
MSG_DATA
[4]
MSG_DATA_4
MB[1].
MSG_DATA
[5]
MSG_DATA_5
MB[1].
MSG_DATA
[6]
MSG_DATA_6
MB[1].
MSG_DATA
[7]
MSG_DATA_7
MB[1].
CONTROL1H
—
—
NMC
ATX
MB[1].
CONTROL1L
—
—
—
—
DART
Bit
24/16/8/0
MBC[2:0]
DLC[3:0]
MB[2].
Same bit configuration as MB[1]
MB[3].↓
Same bit configuration as MB[1]
MB[13].
Same bit configuration as MB[1]
(Ditto)
PFC
MB[14].
Same bit configuration as MB[1]
MB[15].
Same bit configuration as MB[1]
PAIORH
PAIORL
PACRH2
PACRL4
PACRL3
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
—
—
—
—
—
—
—
PA23IOR
PA22IOR
PA21IOR
—
—
—
—
—
PA15IOR
PA14IOR
PA13IOR
PA12IOR
PA11IOR
PA10IOR
PA9IOR
PA8IOR
PA7IOR
PA6IOR
PA5IOR
PA4IOR
PA3IOR
PA2IOR
PA1IOR
PA0IOR
—
PA23MD[2:0]
—
—
PA21MD[2:0]
—
—
PA15MD[2:0]
—
PA14MD[2:0]
—
PA13MD[2:0]
—
PA12MD[2:0]
—
PA11MD[2:0]
—
PA10MD[2:0]
—
PA9MD[2:0]
—
PA8MD[2:0]
—
PA22MD[2:0]
—
—
—
Page 1597 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
PFC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
PACRL2
PACRL1
PAPCRH
—
PA7MD[2:0]
—
PA6MD[2:0]
—
PA5MD[2:0]
—
PA4MD[2:0]
—
PA3MD[2:0]
—
PA2MD[2:0]
—
PA1MD[2:0]
—
—
—
—
PA23PCR PA22PCR PA21PCR
PAPCRL
PBIORH
PBIORL
PA0MD[2:0]
—
—
—
—
—
—
—
—
—
PA9PCR
PA8PCR
PA7PCR
PA6PCR
PA5PCR
PA4PCR
PA3PCR
PA2PCR
PA1PCR
PA0PCR
—
—
—
—
—
—
—
—
—
—
—
—
PB19IOR
PB18IOR
PB17IOR
PB16IOR
PB15IOR
PB14IOR
PB13IOR
PB12IOR
PB11IOR
PB10IOR
PB9IOR
PB8IOR
PB7IOR
PB6IOR
—
—
PB3IOR
PB2IOR
PB1IOR
PB0IOR
—
—
PB17MD[2:0]
—
PB16MD[2:0]
PBCRL4
—
PB15MD[2:0]
—
PB14MD[2:0]
—
PB13MD[2:0]
—
PB12MD[2:0]
PBCRL3
—
PB11MD[2:0]
—
PB10MD[2:0]
—
PB9MD[2:0]
—
PB8MD[2:0]
PB19MD[2:0]
—
—
—
PB7MD[2:0]
—
—
—
PB3MD[2:0]
PBPCRH
—
—
—
—
—
—
—
—
—
PCIORL
PB18MD[2:0]
—
—
PBCRL1
PBPCRL
—
PB6MD[2:0]
—
—
PB1MD[2:0]
—
—
—
PB0MD[2:0]
—
—
—
PB19PCR PB18PCR PB17PCR PB16PCR
PB15PCR PB14PCR PB13PCR PB12PCR PB11PCR PB10PCR
PB9PCR
PB8PCR
PB7PCR
PB6PCR
—
—
—
—
PB1PCR
PB0PCR
PC15IOR
PC14IOR
PC13IOR
PC12IOR
PC11IOR
PC10IOR
PC9IOR
PC8IOR
PC7IOR
PC6IOR
PC5IOR
PC4IOR
PC3IOR
PC2IOR
PC1IOR
PC0IOR
—
—
PC13MD[2:0]
—
PC12MD[2:0]
PCCRL3
—
PC11MD[2:0]
—
PC10MD[2:0]
—
PC9MD[2:0]
—
PC8MD[2:0]
PCCRL2
—
PC7MD[2:0]
—
PC6MD[2:0]
—
PC5MD[2:0]
—
PC4MD[2:0]
—
PC3MD[2:0]
—
PC2MD[2:0]
—
PC1MD[2:0]
—
PC0MD[2:0]
Page 1598 of 1778
—
PB2MD[2:0]
PCCRL4
PCCRL1
—
PA15PCR PA14PCR PA13PCR PA12PCR PA11PCR PA10PCR
PBCRH1
PBCRL2
Bit
24/16/8/0
PC15MD[2:0]
—
PC14MD[2:0]
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
PFC
Section 30 List of Registers
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
PCPCRL
Bit
24/16/8/0
PC15PCR PC14PCR PC13PCR PC12PCR PC11PCR PC10PCR PC19PCR
PC8PCR
PC7PCR
PC6PCR
PC5PCR
PC4PCR
PC3PCR
PC2PCR
PC1PCR
PC0PCR
PD31IOR
PD30IOR
PD29IOR
PD28IOR
PD27IOR
PD26IOR
PD25IOR
PD24IOR
PD23IOR
PD22IOR
PD21IOR
PD20IOR
PD19IOR
PD18IOR
PD17IOR
PD16IOR
PD15IOR
PD14IOR
PD13IOR
PD12IOR
PD11IOR
PD10IOR
PD9IOR
PD8IOR
PD7IOR
PD6IOR
PD5IOR
PD4IOR
PD3IOR
PD2IOR
PD1IOR
PD0IOR
PDIORH
PDIORL
PDCRH4
—
—
PD29MD[2:0]
—
PD28MD[2:0]
PDCRH3
—
PD27MD[2:0]
—
PD26MD[2:0]
—
PD25MD[2:0]
—
PD24MD[2:0]
—
PD23MD[2:0]
—
PD22MD[2:0]
—
PD21MD[2:0]
—
PD20MD[2:0]
PDCRH1
—
PD19MD[2:0]
—
PD18MD[2:0]
—
PD17MD[2:0]
—
PD16MD[2:0]
PDCRL4
—
PD15MD[2:0]
—
PD14MD[2:0]
—
PD13MD[2:0]
—
PD12MD[2:0]
PDCRL3
—
PD11MD[2:0]
—
PD10MD[2:0]
—
PD9MD[2:0]
—
PD8MD[2:0]
—
PD7MD[2:0]
—
PD6MD[2:0]
—
PD5MD[2:0]
—
PD4MD[2:0]
—
PD3MD[2:0]
—
PD2MD[2:0]
—
PD1MD[2:0]
—
PD0MD[2:0]
PDCRH2
PDCRL2
PDCRL1
PD31MD[2:0]
—
PD30MD[2:0]
PDPCRH
PD31PCR PD30PCR PD29PCR PD28PCR PD27PCR PD26PCR PD25PCR PD24PCR
PDPCRL
PD15PCR PD14PCR PD13PCR PD12PCR PD11PCR PD10PCR
PD9PCR
PD8PCR
PD7PCR
PD6PCR
PD5PCR
PD4PCR
PD3PCR
PD2PCR
PD1PCR
PD0PCR
PE15IOR
PE14IOR
PE13IOR
PE12IOR
PE11IOR
PE10IOR
PE9IOR
PE8IOR
PE7IOR
PE6IOR
PE5IOR
PE4IOR
PE3IOR
PE2IOR
PE1IOR
PE0IOR
PD23PCR PD22PCR PD21PCR PD20PCR PD19PCR PD18PCR PD17PCR PD16PCR
PEIORL
PECRL4
—
—
PE13MD[2:0]
—
PE12MD[2:0]
PECRL3
—
PE11MD[2:0]
—
PE10MD[2:0]
—
PE9MD[2:0]
—
PE8MD[2:0]
PECRL2
—
PE7MD[2:0]
—
PE6MD[2:0]
—
PE5MD[2:0]
—
PE4MD[2:0]
—
PE3MD[2:0]
—
PE2MD[2:0]
—
PE1MD[2:0]
—
PE0MD[2:0]
PECRL1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
PE15MD[2:0]
—
PE14MD[2:0]
Page 1599 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
PFC
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
HCPCR
IFCR
PEPCRL
I/O port
Bit
24/16/8/0
—
—
—
—
—
—
—
—
—
—
—
—
MZIZDH
MZIZDL
MZIZEH
MZIZEL
—
—
—
—
—
—
—
—
—
—
—
—
IRQMD3
IRQMD2
IRQMD1
IRQMD0
PE15PCR PE14PCR PE13PCR PE12PCR PE11PCR PE10PCR
PE9PCR
PE8PCR
PE7PCR
PE6PCR
PE5PCR
PE4PCR
PE3PCR
PE2PCR
PE1PCR
PE0PCR
PADRH
—
—
—
—
—
—
—
—
PA23DR
PA22DR
PA21DR
—
—
—
—
—
PADRL
PA15DR
PA14DR
PA13DR
PA12DR
PA11DR
PA10DR
PA9DR
PA8DR
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
PAPRH
PAPRL
—
—
—
—
—
—
—
—
PA23PR
PA22PR
PA21PR
—
—
—
—
—
PA15PR
PA14PR
PA13PR
PA12PR
PA11PR
PA10PR
PA9PR
PA8PR
PA7PR
PA6PR
PA5PR
PA4PR
PA3PR
PA2PR
PA1PR
PA0PR
PBDRH
—
—
—
—
—
—
—
—
—
—
—
—
PB19DR
PB18DR
PB17DR
PB16DR
PBDRL
PB15DR
PB14DR
PB13DR
PB12DR
PB11DR
PB10DR
PB9DR
PB8DR
PB7DR
PB6DR
—
—
PB3DR
PB2DR
PB1DR
PB0DR
PBPRH
—
—
—
—
—
—
—
—
—
—
—
—
PB19PR
PB18PR
PB17PR
PB16PR
PBPRL
PB15PR
PB14PR
PB13PR
PB12PR
PB11PR
PB10PR
PB9PR
PB8PR
PB7PR
PB6PR
—
—
PB3PR
PB2PR
PB1PR
PB0PR
PCDRL
PC15DR
PC14DR
PC13DR
PC12DR
PC11DR
PC10DR
PC9DR
PC8DR
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
PCPRL
PC15PR
PC14PR
PC13PR
PC12PR
PC11PR
PC10PR
PC9PR
PC8PR
PC7PR
PC6PR
PC5PR
PC4PR
PC3PR
PC2PR
PC1PR
PC0PR
PDDRH
PD31DR
PD30DR
PD29DR
PD28DR
PD27DR
PD26DR
PD25DR
PD24DR
PD23DR
PD22DR
PD21DR
PD20DR
PD19DR
PD18DR
PD17DR
PD16DR
PDDRL
PD15DR
PD14DR
PD13DR
PD12DR
PD11DR
PD10DR
PD9DR
PD8DR
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
PDPRH
PD31PR
PD30PR
PD29PR
PD28PR
PD27PR
PD26PR
PD25PR
PD24PR
PD23PR
PD22PR
PD21PR
PD20PR
PD19PR
PD18PR
PD17PR
PD16PR
PDPRL
PD15PR
PD14PR
PD13PR
PD12PR
PD11PR
PD10PR
PD9PR
PD8PR
PD7PR
PD6PR
PD5PR
PD4PR
PD3PR
PD2PR
PD1PR
PD0PR
PE15DR
PE14DR
PE13DR
PE12DR
PE11DR
PE10DR
PE9DR
PE8DR
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
PEDRL
Page 1600 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
I/O port
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
PEPRL
PFDRL
USB
USBIFR0
Bit
24/16/8/0
PE15PR
PE14PR
PE13PR
PE12PR
PE11PR
PE10PR
PE9PR
PE8PR
PE7PR
PE6PR
PE5PR
PE4PR
PE3PR
PE2PR
PE1PR
PE0PR
—
—
—
—
PF11DR
PF10DR
PF9DR
PF8DR
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
BRST
EP1FULL
EP2TR
EP2EMPTY
SETUPTS
EP0oTS
EP0iTR
EP0iTS
USBIFR1
—
—
—
—
VBUSMN
EP3TR
EP3TS
VBUSF
USBEPDR0i
D7
D6
D5
D4
D3
D2
D1
D0
USBEPDR0o
D7
D6
D5
D4
D3
D2
D1
D0
USBTRG
—
—
EP0sRDFN
USBFCLR
—
—
—
EP3PKTE EP1RDFN EP2PKTE
EP3CLR
EP1CLR
EP2CLR
EP0oRDFN EP0iPKTE
EP0oCLR
EP0iCLR
USBEPSZ0o
—
—
—
—
—
—
—
—
USBEPDR0s
D7
D6
D5
D4
D3
D2
D1
D0
USBDASTS
—
—
EP3DE
EP2DE
—
—
—
EO0iDE
BRST
EP1FULL
EP2TR
EP2EMPTY
SETUPTS
EP0oTS
EP0iTR
Ep0iTS
—
—
—
ASCE
EP3STL
EP2STL
EP1STL
EP0STL
USBIER0
BRST
EP1FULL
EP2TR
EP2EMPTY
SETUPTS
EP0oTS
EP0iTR
Ep0iTS
USBIER1
—
—
—
—
—
EP3TR
EP3TS
VBUSF
USBEPSZ1
—
—
—
—
—
—
—
—
USBISR1
—
—
—
—
—
EP3TR
EP3TS
VBUSF
USBDMAR
—
—
—
—
—
—
USBEPDR3
D7
D6
D5
D4
D3
D2
USBISR0
USBEPSTL
FLASH
Section 30 List of Registers
EP2DMAE EP1DMAE
D1
D0
USBEPDR1
D7
D6
D5
D4
D3
D2
D1
D0
USBEPDR2
D7
D6
D5
D4
D3
D2
D1
D0
FCCS
FWE
MAT
—
FLER
—
—
—
SCO
FPCS
—
—
—
—
—
—
—
PPVS
FECS
—
—
—
—
—
—
—
EPVB
FKEY
K7
K6
K5
K4
K3
K2
K1
K0
FMATS
MS7
MS6
MS5
MS4
MS3
MS2
MS1
MS0
FTDAR
TDER
TDA6
TDA5
TDA4
TDA3
TDA2
TDA1
TDA0
RCCR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
—
—
—
—
—
—
—
—
—
—
—
—
RCF
—
—
—
Page 1601 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
PowerSTBCR
down mode
STBCR2
H-UDI
STBY
—
—
—
—
—
—
—
MSTP10
MSTP9
MSTP8
—
—
—
MSTP4
—
SYSCR1
—
—
—
—
RAME3
RAME2
RAME1
RAME0
SYSCR2
—
—
—
—
RAMWE3
RAMWE2
RAMWE1
RAMWE0
STBCR3
HIZ
MSTP36
MSTP35
MSTP34
MSTP33
MSTP32
MSTP31
—
STBCR4
—
—
—
MSTP44
—
MSTP42
—
—
STBCR5
MSTP57
MSTP56
MSTP55
—
MSTP53
MSTP52
MSTP51
MSTP50
STBCR6
USBSEL
MSTP66
USBCLK
MSTP64
—
—
—
—
—
—
—
—
SDIR
TI[7:0]
—
Notes: 1.
2.
3.
4.
Bit
24/16/8/0
—
—
—
When normal memory, SRAM with byte selection, or MPX-I/O is the memory type
When burst ROM (clocked asynchronous) is the memory type
When SDRAM is the memory type
When burst ROM (clocked synchronous) is the memory type
Page 1602 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
30.3
Module
Name
CPG
INTC
UBC
Section 30 List of Registers
Register States in Each Operating Mode
Register
Power-on
Reset
Manual
Reset
1
Software
Standby
Module
Standby
Sleep
FRQCR
Initialized* Retained
Retained
—
Retained
MCLKCR
Initialized
Retained
Retained
—
Retained
ACLKCR
Initialized
Retained
Retained
—
Retained
OSCCR
Initialized
Retained
Retained
—
Retained
ICR0
Initialized
Retained
Retained
—
Retained
ICR1
Initialized
Retained
Retained
—
Retained
IRQRR
Initialized
Retained
Retained
—
Retained
IBCR
Initialized
Retained
Retained
—
Retained
IBNR
Initialized
Retained*2
Retained
—
Retained
IPR01
Initialized
Retained
Retained
—
Retained
IPR02
Initialized
Retained
Retained
—
Retained
IPR05
Initialized
Retained
Retained
—
Retained
IPR06
Initialized
Retained
Retained
—
Retained
IPR07
Initialized
Retained
Retained
—
Retained
IPR08
Initialized
Retained
Retained
—
Retained
IPR09
Initialized
Retained
Retained
—
Retained
IPR10
Initialized
Retained
Retained
—
Retained
IPR11
Initialized
Retained
Retained
—
Retained
IPR12
Initialized
Retained
Retained
—
Retained
IPR13
Initialized
Retained
Retained
—
Retained
IPR14
Initialized
Retained
Retained
—
Retained
IPR15
Initialized
Retained
Retained
—
Retained
IPR16
Initialized
Retained
Retained
—
Retained
IPR17
Initialized
Retained
Retained
—
Retained
IPR18
Initialized
Retained
Retained
—
Retained
USDTENDRR
Initialized
Retained
Retained
—
Retained
BAR_0
Initialized
Retained
Retained
Retained
Retained
BAMR_0
Initialized
Retained
Retained
Retained
Retained
BBR_0
Initialized
Retained
Retained
Retained
Retained
BAR_1
Initialized
Retained
Retained
Retained
Retained
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1603 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
UBC
BAMR_1
Initialized
Retained
Retained
Retained
Retained
BBR_1
Initialized
Retained
Retained
Retained
Retained
BAR_2
Initialized
Retained
Retained
Retained
Retained
BAMR_2
Initialized
Retained
Retained
Retained
Retained
BBR_2
Initialized
Retained
Retained
Retained
Retained
BAR_3
Initialized
Retained
Retained
Retained
Retained
BAMR_3
Initialized
Retained
Retained
Retained
Retained
BBR_3
Initialized
Retained
Retained
Retained
Retained
BRCR
Initialized
Retained
Retained
Retained
Retained
DTCERA
Initialized
Retained
Retained
Retained
Retained
DTCERB
Initialized
Retained
Retained
Retained
Retained
DTCERC
Initialized
Retained
Retained
Retained
Retained
DTC
BSC
DTCERD
Initialized
Retained
Retained
Retained
Retained
DTCERE
Initialized
Retained
Retained
Retained
Retained
DTCCR
Initialized
Retained
Retained
Retained
Retained
DTCVBR
Initialized
Retained
Retained
Retained
Retained
CMNCR
Initialized
Retained
Retained
—
Retained
CS0BCR
Initialized
Retained
Retained
—
Retained
CS1BCR
Initialized
Retained
Retained
—
Retained
CS2BCR
Initialized
Retained
Retained
—
Retained
CS3BCR
Initialized
Retained
Retained
—
Retained
CS4BCR
Initialized
Retained
Retained
—
Retained
CS5BCR
Initialized
Retained
Retained
—
Retained
CS6BCR
Initialized
Retained
Retained
—
Retained
CS7BCR
Initialized
Retained
Retained
—
Retained
CS0WCR
Initialized
Retained
Retained
—
Retained
CS1WCR
Initialized
Retained
Retained
—
Retained
CS2WCR
Initialized
Retained
Retained
—
Retained
CS3WCR
Initialized
Retained
Retained
—
Retained
CS4WCR
Initialized
Retained
Retained
—
Retained
CS5WCR
Initialized
Retained
Retained
—
Retained
CS6WCR
Initialized
Retained
Retained
—
Retained
Page 1604 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
BSC
CS7WCR
Initialized
Retained
Retained
—
Retained
SDCR
Initialized
Retained
Retained
—
Retained
RTCSR
Initialized
Retained
(Flag
processing
continued)
Retained
—
Retained
(Flag
processing
continued)
RTCNT
Initialized
Retained
(Count-up
continued)
Retained
—
Retained
(Count-up
continued)
RTCOR
Initialized
Retained
Retained
—
Retained
BSCEHR
Initialized
Retained
Retained
—
Retained
SAR_0
Initialized
Retained
Retained
Retained
Retained
DAR_0
Initialized
Retained
Retained
Retained
Retained
DMATCR_0
Initialized
Retained
Retained
Retained
Retained
CHCR_0
Initialized
Retained
Retained
Retained
Retained
RSAR_0
Initialized
Retained
Retained
Retained
Retained
RDAR_0
Initialized
Retained
Retained
Retained
Retained
RDMATCR_0
Initialized
Retained
Retained
Retained
Retained
SAR_1
Initialized
Retained
Retained
Retained
Retained
DAR_1
Initialized
Retained
Retained
Retained
Retained
DMATCR_1
Initialized
Retained
Retained
Retained
Retained
CHCR_1
Initialized
Retained
Retained
Retained
Retained
RSAR_1
Initialized
Retained
Retained
Retained
Retained
DMAC
RDAR_1
Initialized
Retained
Retained
Retained
Retained
RDMATCR_1
Initialized
Retained
Retained
Retained
Retained
SAR_2
Initialized
Retained
Retained
Retained
Retained
DAR_2
Initialized
Retained
Retained
Retained
Retained
DMATCR_2
Initialized
Retained
Retained
Retained
Retained
CHCR_2
Initialized
Retained
Retained
Retained
Retained
RSAR_2
Initialized
Retained
Retained
Retained
Retained
RDAR_2
Initialized
Retained
Retained
Retained
Retained
RDMATCR_2
Initialized
Retained
Retained
Retained
Retained
SAR_3
Initialized
Retained
Retained
Retained
Retained
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1605 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
DMAC
DAR_3
Initialized
Retained
Retained
Retained
Retained
DMATCR_3
Initialized
Retained
Retained
Retained
Retained
CHCR_3
Initialized
Retained
Retained
Retained
Retained
RSAR_3
Initialized
Retained
Retained
Retained
Retained
RDAR_3
Initialized
Retained
Retained
Retained
Retained
RDMATCR_3
Initialized
Retained
Retained
Retained
Retained
SAR_4
Initialized
Retained
Retained
Retained
Retained
DAR_4
Initialized
Retained
Retained
Retained
Retained
DMATCR_4
Initialized
Retained
Retained
Retained
Retained
CHCR_4
Initialized
Retained
Retained
Retained
Retained
RSAR_4
Initialized
Retained
Retained
Retained
Retained
RDAR_4
Initialized
Retained
Retained
Retained
Retained
RDMATCR_4
Initialized
Retained
Retained
Retained
Retained
SAR_5
Initialized
Retained
Retained
Retained
Retained
DAR_5
Initialized
Retained
Retained
Retained
Retained
DMATCR_5
Initialized
Retained
Retained
Retained
Retained
CHCR_5
Initialized
Retained
Retained
Retained
Retained
RSAR_5
Initialized
Retained
Retained
Retained
Retained
RDAR_5
Initialized
Retained
Retained
Retained
Retained
RDMATCR_5
Initialized
Retained
Retained
Retained
Retained
SAR_6
Initialized
Retained
Retained
Retained
Retained
DAR_6
Initialized
Retained
Retained
Retained
Retained
DMATCR_6
Initialized
Retained
Retained
Retained
Retained
CHCR_6
Initialized
Retained
Retained
Retained
Retained
RSAR_6
Initialized
Retained
Retained
Retained
Retained
RDAR_6
Initialized
Retained
Retained
Retained
Retained
RDMATCR_6
Initialized
Retained
Retained
Retained
Retained
SAR_7
Initialized
Retained
Retained
Retained
Retained
DAR_7
Initialized
Retained
Retained
Retained
Retained
DMATCR_7
Initialized
Retained
Retained
Retained
Retained
CHCR_7
Initialized
Retained
Retained
Retained
Retained
RSAR_7
Initialized
Retained
Retained
Retained
Retained
Page 1606 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
DMAC
RDAR_7
Initialized
Retained
Retained
Retained
Retained
RDMATCR_7
Initialized
Retained
Retained
Retained
Retained
DMAOR
Initialized
Retained
Retained
Retained
Retained
DMARS0
Initialized
Retained
Retained
Retained
Retained
DMARS1
Initialized
Retained
Retained
Retained
Retained
DMARS2
Initialized
Retained
Retained
Retained
Retained
DMARS3
Initialized
Retained
Retained
Retained
Retained
TCR_0
Initialized
Retained
Retained
Initialized
Retained
TMDR_0
Initialized
Retained
Retained
Initialized
Retained
TIORH_0
Initialized
Retained
Retained
Initialized
Retained
TIORL_0
Initialized
Retained
Retained
Initialized
Retained
TIER_0
Initialized
Retained
Retained
Initialized
Retained
MTU2
TSR_0
Initialized
Retained
Retained
Initialized
Retained
TCNT_0
Initialized
Retained
Retained
Initialized
Retained
TGRA_0
Initialized
Retained
Retained
Initialized
Retained
TGRB_0
Initialized
Retained
Retained
Initialized
Retained
TGRC_0
Initialized
Retained
Retained
Initialized
Retained
TGRD_0
Initialized
Retained
Retained
Initialized
Retained
TGRE_0
Initialized
Retained
Retained
Initialized
Retained
TGRF_0
Initialized
Retained
Retained
Initialized
Retained
TIER2_0
Initialized
Retained
Retained
Initialized
Retained
TSR2_0
Initialized
Retained
Retained
Initialized
Retained
TBTM_0
Initialized
Retained
Retained
Initialized
Retained
TCR_1
Initialized
Retained
Retained
Initialized
Retained
TMDR_1
Initialized
Retained
Retained
Initialized
Retained
TIOR_1
Initialized
Retained
Retained
Initialized
Retained
TIER_1
Initialized
Retained
Retained
Initialized
Retained
TSR_1
Initialized
Retained
Retained
Initialized
Retained
TCNT_1
Initialized
Retained
Retained
Initialized
Retained
TGRA_1
Initialized
Retained
Retained
Initialized
Retained
TGRB_1
Initialized
Retained
Retained
Initialized
Retained
TICCR
Initialized
Retained
Retained
Initialized
Retained
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1607 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
MTU2
TCR_2
Initialized
Retained
Retained
Initialized
Retained
TMDR_2
Initialized
Retained
Retained
Initialized
Retained
TIOR_2
Initialized
Retained
Retained
Initialized
Retained
TIER_2
Initialized
Retained
Retained
Initialized
Retained
TSR_2
Initialized
Retained
Retained
Initialized
Retained
TCNT_2
Initialized
Retained
Retained
Initialized
Retained
TGRA_2
Initialized
Retained
Retained
Initialized
Retained
TGRB_2
Initialized
Retained
Retained
Initialized
Retained
TCR_3
Initialized
Retained
Retained
Initialized
Retained
TMDR_3
Initialized
Retained
Retained
Initialized
Retained
TIORH_3
Initialized
Retained
Retained
Initialized
Retained
TIORL_3
Initialized
Retained
Retained
Initialized
Retained
TIER_3
Initialized
Retained
Retained
Initialized
Retained
TSR_3
Initialized
Retained
Retained
Initialized
Retained
TCNT_3
Initialized
Retained
Retained
Initialized
Retained
TGRA_3
Initialized
Retained
Retained
Initialized
Retained
TGRB_3
Initialized
Retained
Retained
Initialized
Retained
TGRC_3
Initialized
Retained
Retained
Initialized
Retained
TGRD_3
Initialized
Retained
Retained
Initialized
Retained
TBTM_3
Initialized
Retained
Retained
Initialized
Retained
TCR_4
Initialized
Retained
Retained
Initialized
Retained
TMDR_4
Initialized
Retained
Retained
Initialized
Retained
TIORH_4
Initialized
Retained
Retained
Initialized
Retained
TIORL_4
Initialized
Retained
Retained
Initialized
Retained
TIER_4
Initialized
Retained
Retained
Initialized
Retained
TSR_4
Initialized
Retained
Retained
Initialized
Retained
TCNT_4
Initialized
Retained
Retained
Initialized
Retained
TGRA_4
Initialized
Retained
Retained
Initialized
Retained
TGRB_4
Initialized
Retained
Retained
Initialized
Retained
TGRC_4
Initialized
Retained
Retained
Initialized
Retained
TGRD_4
Initialized
Retained
Retained
Initialized
Retained
TBTM_4
Initialized
Retained
Retained
Initialized
Retained
Page 1608 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
MTU2
TADCR
Initialized
Retained
Retained
Initialized
Retained
TADCORA_4
Initialized
Retained
Retained
Initialized
Retained
TADCORB_4
Initialized
Retained
Retained
Initialized
Retained
TADCOBRA_4
Initialized
Retained
Retained
Initialized
Retained
TADCOBRB_4
Initialized
Retained
Retained
Initialized
Retained
TCRU_5
Initialized
Retained
Retained
Initialized
Retained
TCRV_5
Initialized
Retained
Retained
Initialized
Retained
TCRW_5
Initialized
Retained
Retained
Initialized
Retained
TIORU_5
Initialized
Retained
Retained
Initialized
Retained
TIORV_5
Initialized
Retained
Retained
Initialized
Retained
TIORW_5
Initialized
Retained
Retained
Initialized
Retained
TIER_5
Initialized
Retained
Retained
Initialized
Retained
TSR_5
Initialized
Retained
Retained
Initialized
Retained
TSTR_5
Initialized
Retained
Retained
Initialized
Retained
TCNTU_5
Initialized
Retained
Retained
Initialized
Retained
TCNTV_5
Initialized
Retained
Retained
Initialized
Retained
TCNTW_5
Initialized
Retained
Retained
Initialized
Retained
TGRU_5
Initialized
Retained
Retained
Initialized
Retained
TGRV_5
Initialized
Retained
Retained
Initialized
Retained
TGRW_5
Initialized
Retained
Retained
Initialized
Retained
TCNTCMPCLR
Initialized
Retained
Retained
Initialized
Retained
TSTR
Initialized
Retained
Retained
Initialized
Retained
TSYR
Initialized
Retained
Retained
Initialized
Retained
TCSYSTR
Initialized
Retained
Retained
Initialized
Retained
TRWER
Initialized
Retained
Retained
Initialized
Retained
TOER
Initialized
Retained
Retained
Initialized
Retained
TOCR1
Initialized
Retained
Retained
Initialized
Retained
TOCR2
Initialized
Retained
Retained
Initialized
Retained
TGCR
Initialized
Retained
Retained
Initialized
Retained
TCDR
Initialized
Retained
Retained
Initialized
Retained
TDDR
Initialized
Retained
Retained
Initialized
Retained
TCNTS
Initialized
Retained
Retained
Initialized
Retained
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1609 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
MTU2
TCBR
Initialized
Retained
Retained
Initialized
Retained
TITCR
Initialized
Retained
Retained
Initialized
Retained
TITCNT
Initialized
Retained
Retained
Initialized
Retained
TBTER
Initialized
Retained
Retained
Initialized
Retained
MTU2S
TDER
Initialized
Retained
Retained
Initialized
Retained
TWCR
Initialized
Retained
Retained
Initialized
Retained
TOLBR
Initialized
Retained
Retained
Initialized
Retained
TCR_3S
Initialized
Retained
Retained
Initialized
Retained
TMDR_3S
Initialized
Retained
Retained
Initialized
Retained
TIORH_3S
Initialized
Retained
Retained
Initialized
Retained
TIORL_3S
Initialized
Retained
Retained
Initialized
Retained
TIER_3S
Initialized
Retained
Retained
Initialized
Retained
TSR_3S
Initialized
Retained
Retained
Initialized
Retained
TCNT_3S
Initialized
Retained
Retained
Initialized
Retained
TGRA_3S
Initialized
Retained
Retained
Initialized
Retained
TGRB_3S
Initialized
Retained
Retained
Initialized
Retained
TGRC_3S
Initialized
Retained
Retained
Initialized
Retained
TGRD_3S
Initialized
Retained
Retained
Initialized
Retained
TBTM_3S
Initialized
Retained
Retained
Initialized
Retained
TCR_4S
Initialized
Retained
Retained
Initialized
Retained
TMDR_4S
Initialized
Retained
Retained
Initialized
Retained
TIORH_4S
Initialized
Retained
Retained
Initialized
Retained
TIORL_4S
Initialized
Retained
Retained
Initialized
Retained
TIER_4S
Initialized
Retained
Retained
Initialized
Retained
TSR_4S
Initialized
Retained
Retained
Initialized
Retained
TCNT_4S
Initialized
Retained
Retained
Initialized
Retained
TGRA_4S
Initialized
Retained
Retained
Initialized
Retained
TGRB_4S
Initialized
Retained
Retained
Initialized
Retained
TGRC_4S
Initialized
Retained
Retained
Initialized
Retained
TGRD_4S
Initialized
Retained
Retained
Initialized
Retained
TBTM_4S
Initialized
Retained
Retained
Initialized
Retained
TADCRS
Initialized
Retained
Retained
Initialized
Retained
Page 1610 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
MTU2S
TADCORA_4S
Initialized
Retained
Retained
Initialized
Retained
TADCORB_4S
Initialized
Retained
Retained
Initialized
Retained
TADCOBRA_4S
Initialized
Retained
Retained
Initialized
Retained
TADCOBRB_4S
Initialized
Retained
Retained
Initialized
Retained
TCRU_5S
Initialized
Retained
Retained
Initialized
Retained
TCRV_5S
Initialized
Retained
Retained
Initialized
Retained
TCRW_5S
Initialized
Retained
Retained
Initialized
Retained
TIORU_5S
Initialized
Retained
Retained
Initialized
Retained
TIORV_5S
Initialized
Retained
Retained
Initialized
Retained
TIORW_5S
Initialized
Retained
Retained
Initialized
Retained
TIER_5S
Initialized
Retained
Retained
Initialized
Retained
TSR_5S
Initialized
Retained
Retained
Initialized
Retained
TSTR_5S
Initialized
Retained
Retained
Initialized
Retained
TCNTU_5S
Initialized
Retained
Retained
Initialized
Retained
TCNTV_5S
Initialized
Retained
Retained
Initialized
Retained
TCNTW_5S
Initialized
Retained
Retained
Initialized
Retained
TGRU_5S
Initialized
Retained
Retained
Initialized
Retained
TGRV_5S
Initialized
Retained
Retained
Initialized
Retained
TGRW_5S
Initialized
Retained
Retained
Initialized
Retained
TCNTCMPCLRS
Initialized
Retained
Retained
Initialized
Retained
TSTRS
Initialized
Retained
Retained
Initialized
Retained
TSYRS
Initialized
Retained
Retained
Initialized
Retained
TRWERS
Initialized
Retained
Retained
Initialized
Retained
TOERS
Initialized
Retained
Retained
Initialized
Retained
TOCR1S
Initialized
Retained
Retained
Initialized
Retained
TOCR2S
Initialized
Retained
Retained
Initialized
Retained
TGCRS
Initialized
Retained
Retained
Initialized
Retained
TCDRS
Initialized
Retained
Retained
Initialized
Retained
TDDRS
Initialized
Retained
Retained
Initialized
Retained
TCNTSS
Initialized
Retained
Retained
Initialized
Retained
TCBRS
Initialized
Retained
Retained
Initialized
Retained
TITCRS
Initialized
Retained
Retained
Initialized
Retained
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1611 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
MTU2S
TITCNTS
Initialized
Retained
Retained
Initialized
Retained
TBTERS
Initialized
Retained
Retained
Initialized
Retained
TDERS
Initialized
Retained
Retained
Initialized
Retained
TSYCRS
Initialized
Retained
Retained
Initialized
Retained
POE2
CMT
WDT
TWCRS
Initialized
Retained
Retained
Initialized
Retained
TOLBRS
Initialized
Retained
Retained
Initialized
Retained
ICSR1
Initialized
Retained
Retained
Retained
Retained
OCSR1
Initialized
Retained
Retained
Retained
Retained
ICSR2
Initialized
Retained
Retained
Retained
Retained
OCSR2
Initialized
Retained
Retained
Retained
Retained
ICSR3
Initialized
Retained
Retained
Retained
Retained
SPOER
Initialized
Retained
Retained
Retained
Retained
POECR1
Initialized
Retained
Retained
Retained
Retained
POECR2
Initialized
Retained
Retained
Retained
Retained
CMSTR
Initialized
Retained
Initialized
Retained
Retained
CMCSR_0
Initialized
Retained
Initialized
Retained
Retained
CMCNT_0
Initialized
Retained
Initialized
Retained
Retained
CMCOR_0
Initialized
Retained
Initialized
Retained
Retained
CMCSR_1
Initialized
Retained
Initialized
Retained
Retained
CMCNT_1
Initialized
Retained
Initialized
Retained
Retained
CMCOR_1
Initialized
Retained
Initialized
Retained
Retained
WTCSR
Initialized
Retained*4
Initialized
—
Retained
Initialized
4
Initialized
—
Retained
WTCNT
Retained*
1
WRCSR
Initialized* Retained
Initialized
—
Retained
SCI
SCSMR_0
Initialized
Retained
Retained
Initialized
Retained
(Channel 0)
SCBRR_0
Initialized
Retained
Retained
Initialized
Retained
SCSCR_0
Initialized
Retained
Retained
Initialized
Retained
SCTDR_0
—
Retained
Retained
Initialized
Retained
SCSSR_0
Initialized
Retained
Retained
Initialized
Retained
SCRDR_0
—
Retained
Retained
Initialized
Retained
SCSDCR_0
Initialized
Retained
Retained
Initialized
Retained
Initialized* Retained
Retained
Initialized
Retained
SCSPTR_0
Page 1612 of 1778
5
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
SCI
SCSMR_1
Initialized
Retained
Retained
Initialized
Retained
(Channel 1)
SCBRR_1
Initialized
Retained
Retained
Initialized
Retained
SCSCR_1
Initialized
Retained
Retained
Initialized
Retained
SCTDR_1
—
Retained
Retained
Initialized
Retained
SCSSR_1
Initialized
Retained
Retained
Initialized
Retained
SCRDR_1
—
Retained
Retained
Initialized
Retained
SCSDCR_1
Initialized
Retained
Retained
Initialized
Retained
SCSPTR_1
Initialized* Retained
Retained
Initialized
Retained
SCI
SCSMR_2
Initialized
Retained
Retained
Initialized
Retained
(Channel 2)
SCBRR_2
Initialized
Retained
Retained
Initialized
Retained
SCSCR_2
Initialized
Retained
Retained
Initialized
Retained
SCTDR_2
—
Retained
Retained
Initialized
Retained
SCSSR_2
Initialized
Retained
Retained
Initialized
Retained
SCRDR_2
—
Retained
Retained
Initialized
Retained
SCSDCR_2
Initialized
Retained
Retained
Initialized
Retained
SCSPTR_2
Initialized* Retained
Retained
Initialized
Retained
SCI
SCSMR_4
Initialized
Retained
Retained
Initialized
Retained
(Channel 4)
SCBRR_4
Initialized
Retained
Retained
Initialized
Retained
SCSCR_4
Initialized
Retained
Retained
Initialized
Retained
SCTDR_4
—
Retained
Retained
Initialized
Retained
SCSSR_4
Initialized
Retained
Retained
Initialized
Retained
SCRDR_4
—
Retained
Retained
Initialized
Retained
SCSDCR_4
Initialized
Retained
Retained
Initialized
Retained
SCSPTR_4
Initialized* Retained
Retained
Initialized
Retained
SCSMR_3
Initialized
Retained
Retained
Retained
Retained
SCBRR_3
Initialized
Retained
Retained
Retained
Retained
SCSCR_3
Initialized
Retained
Retained
Retained
Retained
SCFTDR_3
—
Retained
Retained
Retained
Retained
SCFSR_3
Initialized
Retained
Retained
Retained
Retained
SCFRDR_3
—
Retained
Retained
Retained
Retained
SCFCR_3
Initialized
Retained
Retained
Retained
Retained
SCFDR_3
Initialized
Retained
Retained
Retained
Retained
SCIF
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
5
5
5
Page 1613 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
SCIF
SCSPTR_3
Initialized
Retained
Retained
Retained
Retained
SCLSR_3
Initialized
Retained
Retained
Retained
Retained
SCSEMR_3
Initialized
Retained
Retained
Retained
Retained
SSCRH
Initialized
Retained
Retained
Initialized
Retained
SSU
IIC3
SSCRL
Initialized
Retained
Retained
Initialized
Retained
SSMR
Initialized
Retained
Retained
Initialized
Retained
SSER
Initialized
Retained
Retained
Initialized
Retained
SSSR
Initialized
Retained
Retained
Initialized
Retained
SSCR2
Initialized
Retained
Retained
Initialized
Retained
SSTDR0
Initialized
Retained
Retained
Initialized
Retained
SSTDR1
Initialized
Retained
Retained
Initialized
Retained
SSTDR2
Initialized
Retained
Retained
Initialized
Retained
SSTDR3
Initialized
Retained
Retained
Initialized
Retained
SSRDR0
Initialized
Retained
Retained
Initialized
Retained
SSRDR1
Initialized
Retained
Retained
Initialized
Retained
SSRDR2
Initialized
Retained
Retained
Initialized
Retained
SSRDR3
Initialized
Retained
Retained
Initialized
Retained
ICCR1
Initialized
Retained
Retained
Retained
Retained
ICCR2
Initialized
Retained
Retained
Retained
Retained
ICMR
Initialized
Retained
Retained/
Initialized
(bc2-0)
Retained/
Initialized
(bc2-0)
Retained
ICIER
Initialized
Retained
Retained
Retained
Retained
ICSR
Initialized
Retained
Retained
Retained
Retained
SAR
Initialized
Retained
Retained
Retained
Retained
ICDRT
Initialized
Retained
Retained
Retained
Retained
ICDRR
Initialized
Retained
Retained
Retained
Retained
NF2CYC
Initialized
Retained
Retained
Retained
Retained
Page 1614 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
ADC
ADCR_0
Initialized
Retained
Initialized
Retained
Retained
ADSR_0
Initialized
Retained
Initialized
Retained
Retained
ADSTRGR_0
Initialized
Retained
Initialized
Retained
Retained
ADANSR_0
Initialized
Retained
Initialized
Retained
Retained
ADBYPSCR_0
Initialized
Retained
Initialized
Retained
Retained
ADDR0
Initialized
Retained
Initialized
Retained
Retained
ADDR1
Initialized
Retained
Initialized
Retained
Retained
ADDR2
Initialized
Retained
Initialized
Retained
Retained
ADDR3
Initialized
Retained
Initialized
Retained
Retained
ADCR_1
Initialized
Retained
Initialized
Retained
Retained
ADSR_1
Initialized
Retained
Initialized
Retained
Retained
ADSTRGR_1
Initialized
Retained
Initialized
Retained
Retained
ADANSR_1
Initialized
Retained
Initialized
Retained
Retained
ADBYPSCR_1
Initialized
Retained
Initialized
Retained
Retained
ADDR4
Initialized
Retained
Initialized
Retained
Retained
ADDR5
Initialized
Retained
Initialized
Retained
Retained
ADDR6
Initialized
Retained
Initialized
Retained
Retained
ADDR7
Initialized
Retained
Initialized
Retained
Retained
ADCR_2
Initialized
Retained
Initialized
Retained
Retained
ADSR_2
Initialized
Retained
Initialized
Retained
Retained
ADSTRGR_2
Initialized
Retained
Initialized
Retained
Retained
ADANSR_2
Initialized
Retained
Initialized
Retained
Retained
ADBYPSCR_2
Initialized
Retained
Initialized
Retained
Retained
ADDR8
Initialized
Retained
Initialized
Retained
Retained
ADDR9
Initialized
Retained
Initialized
Retained
Retained
ADDR10
Initialized
Retained
Initialized
Retained
Retained
ADDR11
Initialized
Retained
Initialized
Retained
Retained
DADR0
Initialized
Retained
Retained
Initialized
Retained
DAC
DADR1
Initialized
Retained
Retained
Initialized
Retained
DACR
Initialized
Retained
Retained
Initialized
Retained
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1615 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
RCAN-ET
MCR
Initialized
Retained
Initialized
Initialized
Retained
GSR
Initialized
Retained
Initialized
Initialized
Retained
BCR1
Initialized
Retained
Initialized
Initialized
Retained
BCR0
Initialized
Retained
Initialized
Initialized
Retained
IRR
Initialized
Retained
Initialized
Initialized
Retained
IMR
Initialized
Retained
Initialized
Initialized
Retained
TEC/REC
Initialized
Retained
Initialized
Initialized
Retained
TXPR1, 0
Initialized
Retained
Initialized
Initialized
Retained
TXCR0
Initialized
Retained
Initialized
Initialized
Retained
TXACK0
Initialized
Retained
Initialized
Initialized
Retained
ABACK0
Initialized
Retained
Initialized
Initialized
Retained
RXPR0
Initialized
Retained
Initialized
Initialized
Retained
RFPR0
Initialized
Retained
Initialized
Initialized
Retained
MBIMR0
Initialized
Retained
Initialized
Initialized
Retained
UMSR0
Initialized
Retained
Initialized
Initialized
Retained
MB[0].
CONTROL0H
—
Retained
—
—
Retained
MB[0].
CONTROL0L
—
Retained
—
—
Retained
MB[0].
LAFMH
—
Retained
—
—
Retained
MB[0].
LAFML
—
Retained
—
—
Retained
MB[0].
MSG_DATA[0]
—
Retained
—
—
Retained
MB[0].
MSG_DATA[1]
—
Retained
—
—
Retained
MB[0].
MSG_DATA[2]
—
Retained
—
—
Retained
MB[0].
MSG_DATA[3]
—
Retained
—
—
Retained
MB[0].
MSG_DATA[4]
—
Retained
—
—
Retained
MB[0].
MSG_DATA[5]
—
Retained
—
—
Retained
Page 1616 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Module
Name
RCAN-ET
PFC
Section 30 List of Registers
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
MB[0].
MSG_DATA[6]
—
Retained
—
—
Retained
MB[0].
MSG_DATA[7]
—
Retained
—
—
Retained
MB[0].
CONTROL1H
Initialized
Retained
Initialized
Initialized
Retained
MB[0].
CONTROL1L
Initialized
Retained
Initialized
Initialized
Retained
MB[1].
Same as MB[0]
MB[2].
Same as MB[0]
MB[3].
Same as MB[0]
↓
(Ditto)
MB[13].
Same as MB[0]
MB[14].
Same as MB[0]
MB[15].
Same as MB[0]
PAIORH
Initialized
Retained
Retained
—
Retained
PAIORL
Initialized
Retained
Retained
—
Retained
PACRH2
Initialized
Retained
Retained
—
Retained
PACRL4
Initialized
Retained
Retained
—
Retained
PACRL3
Initialized
Retained
Retained
—
Retained
PACRL2
Initialized
Retained
Retained
—
Retained
PACRL1
Initialized
Retained
Retained
—
Retained
PAPCRH
Initialized
Retained
Retained
—
Retained
PAPCRL
Initialized
Retained
Retained
—
Retained
PBIORH
Initialized
Retained
Retained
—
Retained
PBIORL
Initialized
Retained
Retained
—
Retained
PBCRH1
Initialized
Retained
Retained
—
Retained
PBCRL4
Initialized
Retained
Retained
—
Retained
PBCRL3
Initialized
Retained
Retained
—
Retained
PBCRL2
Initialized
Retained
Retained
—
Retained
PBCRL1
Initialized
Retained
Retained
—
Retained
PBPCRH
Initialized
Retained
Retained
—
Retained
PBPCRL
Initialized
Retained
Retained
—
Retained
Register
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1617 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
PFC
PCIORL
Initialized
Retained
Retained
—
Retained
PCCRL4
Initialized
Retained
Retained
—
Retained
PCCRL3
Initialized
Retained
Retained
—
Retained
PCCRL2
Initialized
Retained
Retained
—
Retained
I/O port
PCCRL1
Initialized
Retained
Retained
—
Retained
PCPCRL
Initialized
Retained
Retained
—
Retained
PDIORH
Initialized
Retained
Retained
—
Retained
PDIORL
Initialized
Retained
Retained
—
Retained
PDCRH4
Initialized
Retained
Retained
—
Retained
PDCRH3
Initialized
Retained
Retained
—
Retained
PDCRH2
Initialized
Retained
Retained
—
Retained
PDCRH1
Initialized
Retained
Retained
—
Retained
PDCRL4
Initialized
Retained
Retained
—
Retained
PDCRL3
Initialized
Retained
Retained
—
Retained
PDCRL2
Initialized
Retained
Retained
—
Retained
PDCRL1
Initialized
Retained
Retained
—
Retained
PDPCRH
Initialized
Retained
Retained
—
Retained
PDPCRL
Initialized
Retained
Retained
—
Retained
PEIORL
Initialized
Retained
Retained
—
Retained
PECRL4
Initialized
Retained
Retained
—
Retained
PECRL3
Initialized
Retained
Retained
—
Retained
PECRL2
Initialized
Retained
Retained
—
Retained
PECRL1
Initialized
Retained
Retained
—
Retained
HCPCR
Initialized
Retained
Retained
—
Retained
IFCR
Initialized
Retained
Retained
—
Retained
PEPCRL
Initialized
Retained
Retained
—
Retained
PADRH
Initialized
Retained
Retained
—
Retained
PADRL
Initialized
Retained
Retained
—
Retained
PAPRH
—
Retained
Retained
—
Retained
PAPRL
—
Retained
Retained
—
Retained
PBDRH
Initialized
Retained
Retained
—
Retained
PBDRL
Initialized
Retained
Retained
—
Retained
Page 1618 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
I/O port
PBPRH
—
Retained
Retained
—
Retained
PBPRL
—
Retained
Retained
—
Retained
PCDRL
Initialized
Retained
Retained
—
Retained
PCPRL
—
Retained
Retained
—
Retained
PDDRH
Initialized
Retained
Retained
—
Retained
PDDRL
Initialized
Retained
Retained
—
Retained
PDPRH
—
Retained
Retained
—
Retained
PDPRL
—
Retained
Retained
—
Retained
PEDRL
Initialized
Retained
Retained
—
Retained
PEPRL
—
Retained
Retained
—
Retained
PFDRL
—
Retained
Retained
—
Retained
USBIFR0
Initialized
Retained
Retained
Retained
Retained
USBIFR1
Initialized
Retained
Retained
Retained
Retained
USBEPDR0i
—
Retained
Retained
Retained
Retained
USBEPDR0o
—
Retained
Retained
Retained
Retained
USBTRG
Initialized
Retained
Retained
Retained
Retained
USBFCLR
Initialized
Retained
Retained
Retained
Retained
USBEPSZ0o
Initialized
Retained
Retained
Retained
Retained
USBEPDR0s
—
Retained
Retained
Retained
Retained
USBDASTS
Initialized
Retained
Retained
Retained
Retained
USBISR0
Initialized
Retained
Retained
Retained
Retained
USBEPSTL
Initialized
Retained
Retained
Retained
Retained
USBIER0
Initialized
Retained
Retained
Retained
Retained
USBIER1
Initialized
Retained
Retained
Retained
Retained
USBEPSZ1
Initialized
Retained
Retained
Retained
Retained
USBISR1
Initialized
Retained
Retained
Retained
Retained
USBDMAR
Initialized
Retained
Retained
Retained
Retained
USBEPDR3
—
Retained
Retained
Retained
Retained
USBEPDR1
—
Retained
Retained
Retained
Retained
USBEPDR2
—
Retained
Retained
Retained
Retained
USB
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1619 of 1778
SH7280 Group, SH7243 Group
Section 30 List of Registers
Module
Name
Register
Power-on
Reset
Manual
Reset
Software
Standby
Module
Standby
Sleep
FLASH
FCCS
Initialized
Retained
Initialized
—
Retained
FPCS
Initialized
Retained
Initialized
—
Retained
FECS
Initialized
Retained
Initialized
—
Retained
FKEY
Initialized
Retained
Initialized
—
Retained
FMATS
Initialized
Retained
Initialized
—
Retained
FTDAR
Initialized
Retained
Initialized
—
Retained
RCCR
Initialized
Retained
Retained
Retained
Retained
STBCR
Initialized
Retained
Retained
—
Retained
STBCR2
Initialized
Retained
Retained
—
Retained
SYSCR1
Initialized
Retained
Retained
—
Retained
SYSCR2
Initialized
Retained
Retained
—
Retained
STBCR3
Initialized
Retained
Retained
—
Retained
STBCR4
Initialized
Retained
Retained
—
Retained
STBCR5
Initialized
Retained
Retained
—
Retained
STBCR6
Initialized
Retained
Retained
—
Retained
SDIR
Retained
Retained
Retained
Retained
Retained
Powerdown
mode
H-UDI*
3
Notes: 1.
2.
3.
4.
5.
Retains the previous value after an internal power-on reset by means of the WDT.
Bits BN[3:0] are initialized.
Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller.
Initialized after an internal manual reset by means of the WDT.
Some bits are not initialized.
Page 1620 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Section 31 Electrical Characteristics
Note: The current specifications of this section are provisional. Note that they are subject to
change without notice.
31.1
Absolute Maximum Ratings
Table 31.1 lists the absolute maximum ratings.
Table 31.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage (Internal)
VCC
−0.3 to +7.0
V
DrVCC
−0.3 to +7.0
V
Input voltage (except analog input pins)
Vin
−0.3 to VCC +0.3
V
Analog power supply voltage
AVCC
−0.3 to +7.0
V
Analog reference voltage
AVREF
−0.3 to AVCC +0.3
V
Analog input voltage
VAN
−0.3 to AVCC +0.3
V
Topr
−20 to +85
°C
−40 to +85
°C
−55 to +125
°C
Operating
temperature
Consumer
specifications
Industrial
specifications
Storage temperature
Caution:
Tstg
Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1621 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.2
DC Characteristics
Tables 31.2 and 31.3 list DC characteristics.
Table 31.2 DC Characteristics (1) [Common Items]
Conditions: Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
VCC
3.0
5.0
5.5
V
Analog power supply voltage
AVCC
4.5
5.0
5.5
V
USB power supply*
DrVCC
3.0
3.3
3.6
V
Supply
1
current*
ICC
—
155
180
mA
Iφ = 100 MHz
Bφ = 50 MHz
Pφ = 50 MHz
(SH7286, SH7285)
ICC
—
125
140
mA
Iφ = 100 MHz
Bφ = 50 MHz
Pφ = 50 MHz
(SH7243)
Software standby
mode
Istby
—
10
20
mA
VCC = 5.0 V
Sleep mode
Isleep
—
80
120
mA
SH7286
SH7285
70
100
3
Normal operation
Test Conditions
SH7243
Input leakage
current
All input pins
|Iin |
—
—
1
μA
Vin =
0.5 to VCC – 0.5 V
Three-state
leakage
current
Input/output pins, all
output pins
(off state)
|ISTI |
—
—
1
μA
Vin =
0.5 to VCC – 0.5 V
Input
capacitance
All pins
Cin
—
—
20
pF
AICC
—
3.0
5.0
mA
Per 1 module
—
30
50
μA
Per 1 module
Analog power During A/D or D/A
supply current conversion
Waiting for A/D or D/A
conversion
Page 1622 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Item
Reference
power supply
current
During A/D or D/A
conversion
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
AIref
—
2.0
3.0
mA
Per 1 module
—
1.5
2.0
mA
Per 1 module
Waiting for A/D or D/A
conversion
Caution:
When the A/D converter or D/A converter is not in use, the AVCC and AVSS pins should
not be open.
Notes: 1. Supply current values are when all output pins are unloaded.
2. ICC, Isleep, and Istby represent the total currents consumed in the VCC and PLLVCC systems.
3. 3.0 V ≤ DrVCC ≤ VCC when the USB is not used.
Table 31.2 DC Characteristics (2) [Except for I2C-Related Pins]
Conditions: VCC = PLLVCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V*,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
VIH
VCC – 0.7
—
VCC + 0.3
V
VCC = 3.6 to 5.5 V
VCC – 0.5
—
VCC + 0.3
V
VCC = 3.0 to 3.6 V
Analog ports
2.2
—
AVCC + 0.3
V
AVCC = 3.0 to 5.5 V*
Input pins other than
2.2
—
VCC + 0.3
V
−0.3
—
0.5
V
−0.3
—
0.8
V
Input high
RES, MRES, NMI,
voltage
MD1, MD0, FWE,
ASEMD0, TRST,
EXTAL, USBEXTAL
above (excluding
Schmitt pins)
Input low
RES, MRES, NMI,
voltage
MD1, MD0, FWE,
VIL
ASEMD0, TRST,
EXTAL, USBXTAL
Input pins other than
above (excluding
Schmitt pins)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1623 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Item
Symbol
Schmitt trigger TIOC0A to TIOC0D,
TIOC1A, TIOC1B,
input
characteristics TIOC2A, TIOC2B,
Min.
Typ.
Max.
Unit
VT
+
VCC – 0.5
—
—
V
VT
−
—
—
1.0
V
—
—
0.5
0.2
—
—
V
VCC = 3.6 to 5.5 V
VCC × 0.05 —
—
V
VCC = 3.0 to 3.6 V
VCC – 0.5
—
—
V
IOH = –200 μA
VCC – 1.0
—
—
V
IOH = –5 mA
—
—
1.4
V
TIOC3A to TIOC3D,
TIOC4A to TIOC4D,
+
VT − VT
TIC5U to TIC5W,
TCLKA to TCLKD,
−
Test Conditions
VCC = 3.6 to 5.5 V
VCC = 3.0 to 3.6 V
TIOC3AS to TIOC3DS,
TIOC4AS to TIOC4DS,
TIC5US, TIC5VS,
TIC5WS,
POE8 to POE0,
SCK4 to SCK0,
RxD4 to RxD0,
IRQ7 to IRQ0, SCCK,
SCS, SSI, SSO, SCL,
SDA
Output high
All output pins
voltage
TIOC3B, TIOC3D,
VOH
TIOC4A to TIOC4D,
TIOC3BS, TIOC3DS,
TIOC4AS to TIOC4DS
Output low
TIOC3B, TIOC3D,
voltage
TIOC4A to TIOC4D,
VOL
IOL = 15 mA,
VCC = 3.6 to 5.5 V
TIOC3BS, TIOC3DS,
—
TIOC4AS to TIOC4DS
—
0.9
IOL = 10 mA,
VCC = 3.0 to 3.6 V
SCL, SDA
All output pins
—
—
0.4
IOL = 3 mA
—
—
0.5
IOL = 8 mA
—
—
0.4
IOL = 1.6 mA
–10
—
–800
μA
Vin = 0 V
2.0
—
—
V
VCC
except for above
pins
Input pull-up
Ports A, B, C, and D, –IP
MOS current
ASEMD0
RAM standby
VRAM
voltage
Note:
*
When the A/D pins are used as input ports, connect AVCC to VCC. In such a case, AVCC =
3.0 to 5.5 V. When the A/D converter is used, AVCC = 4.5 to 5.5 V.
Page 1624 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Table 31.3 Permissible Output Currents
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Typ.
Max.
1
Unit
2
Permissible output low
current (per pin)
IOL
—
—
2.0* *
mA
Permissible output low current (total)
ΣIOL
—
—
80
mA
Permissible output high current (per pin)
−IOH
—
—
2
mA
Permissible output high current (total)
Σ−IOH
—
—
25
mA
Notes: 1. TIOC3B, TIOC3D, TIOC4A to TIOC4D, TIOC3BS, TIOC3DS, and TIOC4AS to
TIOC4DS: IOL = 15 mA (Max)/-IOH = 5 mA. SCL and SDA: IOL = 8 mA (Max).
Of these pins, the number of pins from which current more than 2.0 mA runs evenly
should be 3 or less.
2. Pins except USD+, USDCaution:
To protect the LSI's reliability, do not exceed the output current values in table 31.3.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1625 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3
AC Characteristics
Signals input to this LSI are basically handled as signals in synchronization with a clock. The
setup and hold times for input pins must be followed.
Table 31.4 Maximum Operating Frequency
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Operating
frequency
Symbol Min.
Typ.
Max.
Unit
f
10
—
100
MHz
Internal bus, external bus
(Bφ)
10
—
50
Peripheral module (Pφ)
10
—
50
MTU2S (Mφ)
10
—
100
AD (Aφ)
10
—
50
CPU (Iφ)
Page 1626 of 1778
Remarks
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.3.1
Section 31 Electrical Characteristics
Clock Timing
Table 31.5 Clock Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol Min.
Max.
Unit
Figure
EXTAL clock input frequency
fEX
10
12.5
MHz
Figure 31.1
EXTAL clock input cycle time
tEXcyc
80
100
ns
EXTAL clock input pulse low width
tEXL
20
—
ns
EXTAL clock input pulse high width
tEXH
20
—
ns
EXTAL clock input rise time
tEXr
—
5
ns
EXTAL clock input fall time
tEXf
—
5
ns
CK clock output frequency
fOP
10
50
MHz
CK clock output cycle time
tcyc
20
100
ns
CK clock output pulse low width
tCKOL
4
—
ns
CK clock output pulse high width
tCKOH
4
—
ns
CK clock output rise time
tCKOr
—
3
ns
CK clock output fall time
tCKOf
—
3
ns
Power-on oscillation setting time
tOSC1
10
—
ms
Figure 31.3
Oscillation settling time on return from
standby 1
tOSC2
10
—
ms
Figure 31.4
Oscillation settling time on return from
standby 2
tOSC3
10
—
ms
Figure 31.5
USB clock power-on oscillation setting time
tOSC4
8
—
ms
Figure 31.3
USB clock input frequency
fUSB
48
MHz
—
USB clock input cycle time
fUSBcyc
20.8
ns
—
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Figure 31.2
Page 1627 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
tEXcyc
tEXH
EXTAL*
(input)
1/2 PVcc
VIH
tEXL
VIH
1/2 PVcc
VIH
VIL
VIL
tEXf
tEXr
Note: * When the clock is input on the EXTAL pin.
Figure 31.1 EXTAL Clock Input Timing
tcyc
tCKOH
CK
(output)
1/2 PVcc
tCKOL
VOH
VOH
VOL
VOH
VOL
1/2 PVcc
tCKOf
tCKOr
Figure 31.2 CK Clock Output Timing
Oscillation settling time
CK,
Internal clock,
USB clock
Vcc
Vcc Min.
tRESW/tMRESW tRESS/tMRESS
tOSC1, tOSC4
RES,
MRES
Note: Oscillation settling time when the internal oscillator is used.
Figure 31.3 Power-On Oscillation Settling Time
Page 1628 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Oscillation settling time
Standby period
CK,
Internal clock
tOSC2
tRESW/tMRESW
RES,
MRES
Note: Oscillation settling time when the internal oscillator is used.
Figure 31.4 Oscillation Settling Time on Return from Standby (Return by Reset)
Oscillation settling time
Standby period
CK,
Internal clock
tOSC3
NMI, IRQ
Note: Oscillation settling time when the internal oscillator is used.
Figure 31.5 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1629 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.2
Control Signal Timing
Table 31.6 Control Signal Timing
Conditions: VCC = PLLVCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Bφ = 50 MHz
Item
Symbol Min.
Max.
Unit
Figure
RES pulse width
tRESW
20*2
⎯
tcyc
tRESS
65
⎯
ns
tRESH
15
⎯
ns
Figures 31.3,
31.4, 31.6,
31.7
RES setup time*
1
RES hold time
MRES pulse width
tMRESW
20*
⎯
tcyc
MRES setup time
tMRESS
100
⎯
ns
MRES hold time
tMRESH
15
⎯
ns
MD1, MD0, FWE setup time
tMDS
20
—
tcyc
Figure 31.6
BREQ setup time
tBREQS
1/2tcyc + 15 ⎯
ns
Figure 31.8
BREQ hold time
tBREQH
1/2tcyc + 10 ⎯
ns
NMI setup time*1
tNMIS
60
⎯
ns
tNMIH
10
⎯
ns
NMI hold time
2
tIRQS
35
⎯
ns
IRQ7 to IRQ0 hold time
tIRQH
10
⎯
ns
IRQ pulse width
tIRQW
4*3
⎯
tcyc
tNMIW
3
⎯
tcyc
IRQ7 to IRQ0 setup time*
1
NMI pulse width
4*
Figure 31.7
IRQOUT/REFOUT output delay time
tIRQOD
⎯
100
ns
Figure 31.9
BACK delay time
tBACKD
⎯
1/2tcyc + 20 ns
Figure 31.8
Bus tri-state delay time 1
tBOFF1
0
100
ns
Bus tri-state delay time 2
tBOFF2
0
100
ns
Bus buffer on time 1
tBON1
0
30
ns
Bus buffer on time 2
tBON2
0
30
ns
Notes: 1. RES, NMI, and IRQ7 to IRQ0 are asynchronous signals. When these setup times are
observed, a change of these signals is detected at the clock rising edge. If the setup
times are not observed, detection of a signal change may be delayed until the next
rising edge of the clock.
2. In standby mode or when the clock multiplication ratio is changed, tRESW = tOSC1 (10 ms).
Since the CK width is initialized by the RES pin, tcyc becomes the initial value.
3. The clock ratio of Bφ:Pφ = 4:1.
Page 1630 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
CK
tRESS
tRESS
tRESW
RES
tMDS
MD1, MD0,
FWE
tMRESS
tMRESS
MRES
tMRESW
Figure 31.6 Reset Input Timing
CK
tRESH/tMRESH tRESS/tMRESS
VIH
RES
MRES
VIL
tNMIH
tNMIS
VIH
NMI
VIL
tIRQH
tIRQS
tNMIW
VIH
IRQ7 to IRQ0
VIL
tIRQW
Figure 31.7 Interrupt Signal Input Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1631 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
tBOFF2
tBON2
CK
(HIZCNT = 0)
CK
(HIZCNT = 1)
tBREQH tBREQS
tBREQH tBREQS
BREQ
tBACKD
tBACKD
BACK
tBOFF1
A25 to A0,
D31 to D0
tBON1
tBOFF2
tBON2
RD, RD/WR,
RASU/L,
CASU/L,
CSn, WEn,
BS, CKE
When
HZCNT = 1
When
HZCNT = 0
Figure 31.8 Bus Release Timing
CK
tIRQOD
tIRQOD
IRQOUT/
REFOUT
Figure 31.9 Interrupt Signal Output Timing
Page 1632 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.3.3
Section 31 Electrical Characteristics
Bus Timing
Table 31.7 Bus Timing
Conditions: VCC = PLLVCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 V to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Bφ = 50 MHz*1
Item
Symbol
Min.
Max.
Unit
Figure
Address delay time 1
tAD1
1
18
ns
Figures 31.10 to
31.34
Address delay time 2
tAD2
1/2tcyc + 1
1/2tcyc + 18
ns
Figure 31.17
Address delay time 3
tAD3
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.35, 31.36
Address setup time
tAS
0
⎯
ns
Figures 31.10 to
31.13, 31.17
Address hold time
tAH
0
⎯
ns
Figures 31.10 to
31.13
BS delay time
tBSD
⎯
18
ns
Figures 31.10 to
31.31, 31.35
CS delay time 1
tCSD1
1
18
ns
Figures 31.10 to
31.34
CS delay time 2
tCSD2
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.35, 31.36
CS setup time
tCSS
0
⎯
ns
Figures 31.10 to
31.13
CS hold time
tCSH
0
⎯
ns
Figures 31.10 to
31.13
Read write delay time 1
tRWD1
1
18
ns
Figures 31.10 to
31.34
Read write delay time 2
tRWD2
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.35, 31.36
Read strobe delay time
tRSD
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.10 to
31.17
Read data setup time 1
tRDS1
1/2tcyc + 14
⎯
ns
Figures 31.10 to
31.16
Read data setup time 2
tRDS2
14
⎯
ns
Figures 31.18 to
31.21, 31.26 to
31.28
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1633 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Bφ = 50 MHz*1
Item
Symbol
Min.
Max.
Unit
Figure
Read data setup time 3
tRDS3
1/2tcyc + 14
⎯
ns
Figure 31.17
Read data setup time 4
tRDS4
1/2tcyc + 14
⎯
ns
Figure 31.35
Read data hold time 1
tRDH1
0
⎯
ns
Figures 31.10 to
31.14, 31.16
Read data hold time 2
tRDH2
2
⎯
ns
Figures 31.15, 31.18
to 31.21, 31.26 to
31.28
Read data hold time 3
tRDH3
0
⎯
ns
Figure 31.17
Read data hold time 4
tRDH4
1/2tcyc + 5
⎯
ns
Figure 31.35
Write enable delay time 1 tWED1
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.10 to
31.14
Write enable delay time 2 tWED2
⎯
18
ns
Figure 31.16
Write data delay time 1
tWDD1
⎯
18
ns
Figures 31.10 to
31.16
Write data delay time 2
tWDD2
⎯
18
ns
Figures 31.22 to
31.25, 31.29 to
31.31
Write data delay time 3
tWDD3
⎯
1/2tcyc + 18
ns
Figure 31.35
Write data hold time 1
tWDH1
1
15
ns
Figures 31.10 to
31.16
Write data hold time 2
tWDH2
1
⎯
ns
Figures 31.22 to
31.25, 31.29 to
31.31
Write data hold time 3
tWDH3
1/2tcyc + 1
⎯
ns
Figure 31.35
Write data hold time 4
tWDH4
0
⎯
ns
Figures 31.10 to
31.13
Read data access time
tACC*3
tcyc (n + 1.5)
− 32*2
⎯
ns
Figures 31.10 to
31.13
Access time from read
strobe
tOE*3
tcyc (n + 1)
− 32*2
⎯
ns
Figures 31.10 to
31.13
WAIT setup time
tWTS
1/2tcyc + 18
⎯
ns
Figures 31.11 to
31.17
WAIT hold time
tWTH
1/2tcyc + 2
⎯
ns
Figures 31.11 to
31.17
Page 1634 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Bφ = 50 MHz*1
Item
Symbol
Min.
Max.
Unit
Figure
RAS delay time 1
tRASD1
1
18
ns
Figures 31.18 to
31.34
RAS delay time 2
tRASD2
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.35, 31.36
CAS delay time 1
tCASD1
1
18
ns
Figures 31.18 to
31.34
CAS delay time 2
tCASD2
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.35, 31.36
DQM delay time 1
tDQMD1
1
18
ns
Figures 31.18 to
31.31
DQM delay time 2
tDQMD2
1/2tcyc + 1
1/2tcyc + 18
ns
Figures 31.35, 31.36
CKE delay time 1
tCKED1
1
18
ns
Figure 31.33
CKE delay time 2
tCKED2
1/2tcyc + 1
1/2tcyc + 18
ns
Figure 31.36
AH delay time
tAHD
1/2tcyc + 1
1/2tcyc + 18
ns
Figure 31.14
Multiplexed address delay tMAD
time
–
18
ns
Figure 31.14
Multiplexed address hold tMAH
time
1
⎯
ns
Figure 31.14
DACK, TEND delay time
tDACD
⎯
Refer to
peripheral
modules
ns
Figures 31.10 to
31.31, 31.35, 31.38
FRAME delay time
tFMD
1
18
ns
Notes: 1. The maximum value (fmax) of Bφ (external bus clock) depends on the number of wait
cycles and the system configuration of your board.
2. n represents the number of wait cycles.
3. When access-time requirement is satisfied, tRDS1 need not be satisfied.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1635 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
T1
T2
CK
tAD1
tAD1
A25 to A0
tAS
tCSD1
tCSD1
CSn
tCSS
tRWD1
tRWD1
RD/WR
tRSD
tRSD
tAH
tCSH
tRDH1
RD
Read
tACC
D31 to D0
tRDS1
tOE
tWED1
tWED1
tCSH
WRxx
Write
tAH
tWDH4
tWDD1
tWDH1
D31 to D0
tBSD
tBSD
BS
tDACD
tDACD
DACKn
TENDn*
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.10 Basic Bus Timing for Normal Space (No Wait)
Page 1636 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
T1
Tw
T2
CK
tAD1
tAD1
A25 to A0
tAS
tCSD1
tCSD1
CSn
tCSS
tRWD1
tRWD1
RD/WR
tRSD
tRSD
tAH
tCSH
tRDH1
RD
tACC
Read
D31 to D0
tOE
tWED1
tWED1
tAH
tCSH
WRxx
Write
tRDS1
tWDH4
tWDD1
tWDH1
D31 to D0
tBSD
tBSD
BS
tDACD
DACKn
TENDn*
tDACD
tWTH
tWTS
WAIT
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.11 Basic Bus Timing for Normal Space (One Software Wait Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1637 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
T1
TwX
T2
CK
tAD1
tAD1
A25 to A0
tAS
tCSD1
tCSD1
CSn
tCSS
tRWD1
tRWD1
RD/WR
tRSD
tRSD
tAH
RD
tCSH
Read
tACC
D31 to D0
tRDH1
tOE
tWED1
tWED1
WRxx
Write
tRDS1
tAH
tCSH
tWDH4
tWDD1
tWDH1
D31 to D0
tBSD
tBSD
BS
tDACD
DACKn
TENDn*
tDACD
tWTH
tWTS
tWTH
tWTS
WAIT
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.12 Basic Bus Timing for Normal Space (One External Wait Cycle)
Page 1638 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
T1
Tw
T2
Taw
T1
Tw
T2
Taw
CK
tAD1
tAD1
tAD1
tAD1
A25 to A0
tAS
tCSD1
tCSD1
tAS
tCSD1
tRWD1
tCSS
tRWD1
tCSD1
CSn
tRWD1
tCSS
tRWD1
RD/WR
tRSD
tRSD
RD
tAH
tRSD
tRSD
tCSH
Read
tACC
tAH
tCSH
tRDH1
tRDS1
tACC
tRDS1
tRDH1
D15 to D0
tOE
tWED1
tOE
tWED1
tAH
tWED1
tWED1
tCSH
WRxx
tCSH
Write
tAH
tWDD1
tWDH1
tWDD1
tWDH1
tWDH4
D15 to D0
tBSD
tBSD
tBSD
tBSD
BS
tDACD
DACKn
TENDn*
tDACD
tWTH
tWTS
tDACD
tDACD
tWTH
tWTS
WAIT
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.13 Basic Bus Timing for Normal Space
(One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1639 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Ta1
Ta2
Ta3
T1
Tw
Tw
T2
CK
tAD1
tAD1
tCSD1
tCSD1
A25 to A0
CS5
tRWD1
tRWD1
RD/WR
tAHD
tAHD
tAHD
AH
tRSD
tRSD
RD
tRDH1
Read
tMAD
D15 to D0
tMAH
tRDS1
Data
Address
tWED1
WRH, WRL
tWED1
tWDHC
tWDD1
Write
tMAD
D15 to D0
tWDH1
tMAH
Address
tBSD
Data
tBSD
BS
tWTH
tWTS
tWTH
tWTS
WAIT
tDACD
tDACD
DACKn*
tDACD
tDACD
TENDn*
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.14 MPX-I/O Interface Bus Cycle
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)
Page 1640 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Th
T1
Twx
T2
Tf
CK
tAD1
tAD1
tCSD1
tCSD1
A25 to A0
CSn
tWED1
tWED1
WRx
tRWD1
tRWD1
RD/WR
tRSD
Read
tRSD
RD
tRDH1
tRDS1
D31 to D0
tRWD1
tRWD1
tWDD1
tWDH1
RD/WR
Write
D31 to D0
tBSD
tBSD
BS
tDACD
tDACD
DACKn
TENDn*
tWTH
tWTH
WAIT
tWTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.15 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1641 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Th
T1
Twx
T2
Tf
CK
tAD1
tAD1
tCSD1
tCSD1
tWED2
tWED2
A25 to A0
CSn
WRx
tRWD1
RD/WR
tRSD
tRSD
RD
Read
tRDH1
tRDS1
D31 to D0
tRWD1
tRWD1
tRWD1
RD/WR
tWDD1
Write
tWDH1
D31 to D0
tBSD
tBSD
BS
tDACD
tDACD
DACKn
TENDn*
tWTH
tWTH
WAIT
tWTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.16 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control))
Page 1642 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
T1
Tw
Twx
T2B
Twb
T2B
CK
tAD1
tAD2
tAD2
tAD1
A25 to A0
tCSD1
tAS
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRSD
tRSD
RD
tRDH3
tRDS3
tRDH3
tRDS3
D31 to D0
WRx
tBSD
tBSD
BS
tDACD
tDACD
DACKn
TENDn*
tWTH
tWTH
WAIT
tWTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.17 Burst ROM Read Cycle
(One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two-Cycle Burst)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1643 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc1
Tcw
Td1
Tde
CK
tAD1
A25 to A0
tAD1
Row address
tAD1
A12/A11
*1
tAD1
Column address
tAD1
tAD1
READA command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.18 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Page 1644 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Trw
Tc1
Tcw
Td1
Tde
Tap
CK
tAD1
A25 to A0
tAD1
Row address
tAD1
Column address
tAD1
1
A12/A11*
tAD1
tAD1
READA command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.19 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1645 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc1
Tc2
Td1
Td2
Tc3
Tc4
Td3
Td4
Tde
CK
tAD1
A25 to A0
tAD1
tAD1
Row
address
tAD1
tAD1
Column
address
A12/A11
tAD1
(1 to 4)
tAD1
*1
tAD1
tAD1
tAD1
READA
command
READ command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.20 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)
Page 1646 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Tr
Section 31 Electrical Characteristics
Trw
Tc1
Tc2
Td1
Td2
Tc3
Tc4
Td3
Td4
Tde
CK
tAD1
tAD1
tAD1
Row
address
A25 to A0
tAD1
tAD1
Column
address
tAD1
(1 to 4)
tAD1
*1
A12/A11
tAD1
tAD1
READ command
tAD1
READA
command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.21 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1647 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc1
Trwl
CK
tAD1
tAD1
tAD1
Row
address
A25 to A0
tAD1
Column
address
tAD1
*1
tAD1
WRITA
command
A12/A11
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tBSD
tBSD
D31 to D0
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.22 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 1 Cycle)
Page 1648 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Trw
Trw
Tc1
Trwl
CK
tAD1
A25 to A0
tAD1
tAD1
Column
address
Row address
tAD1
tAD1
*1
tAD1
WRITA
command
A12/A11
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tBSD
tBSD
D31 to D0
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.23 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1649 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc1
Tc2
Tc3
Tc4
Trwl
CK
tAD1
tAD1
tAD1
Row
address
A25 to A0
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
tAD1
*1
WRIT command
A12/A11
WRITA
command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tWDD2
tWDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.24 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle)
Page 1650 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Trwl
CK
tAD1
tAD1
tAD1
Row
address
A25 to A0
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
tAD1
*1
A12/A11
WRIT command
WRITA
command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
tCASD1
tCASD1
RD/WR
tRASD1
tRASD1
RASU/L
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tWDD2
tWDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.25 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1651 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc1
Tc2
Td1
Td2
Tc3
Tc4
Td3
Td4
Tde
CK
tAD1
A25 to A0
tAD1
Row
address
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
tAD1
*1
A12/A11
tAD1
READ command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle)
Page 1652 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tc1
Tc2
Td1
Td2
Tc3
Tc4
Td3
Td4
Tde
CK
tAD1
A25 to A0
tAD1
tAD1
Column
address
tAD1
*1
A12/A11
tAD1
READ command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
RD/WR
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.27 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1653 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tp
Trw
Tr
Tc1
Tc2
Td1
Td2
Tc3
Tc4
Td3
Td4
Tde
CK
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
Row
address
A25 to A0
tAD1
tAD1
tAD1
*1
A12/A11
tAD1
READ command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRASD1
tRASD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tRDS2
tRDH2
tRDS2
tRDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.28 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CAS Latency 2, WTRCD = 0 Cycle)
Page 1654 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc1
Tc2
Tc3
Tc4
CK
tAD1
tAD1
tAD1
Row
address
A25 to A0
tAD1
tAD1
tAD1
tAD1
Column
address
tAD1
tAD1
*1
A12/A11
WRIT command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tWDD2
tWDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1655 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tnop
Tc1
Tc2
Tc3
Tc4
CK
tAD1
tAD1
tAD1
tAD1
tAD1
Column
address
A25 to A0
tAD1
tAD1
tAD1
*1
A12/A11
WRIT command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
RD/WR
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tWDD2
tWDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
TRWL = 0 Cycle)
Page 1656 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
CK
tAD1
A25 to A0
tAD1
tAD1
Row address
tAD1
tAD1
tAD1
tAD1
Column address
tAD1
tAD1
tAD1
*1
A12/A11
WRIT command
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRASD1
tRASD1
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
tDQMD1
tDQMD1
DQMxx
tWDD2
tWDH2
tWDD2
tWDH2
D31 to D0
tBSD
tBSD
BS
(High)
CKE
tDACD
tDACD
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.31 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1657 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tp
Tpw
Trr
Trc
Trc
Trc
CK
tAD1
tAD1
A25 to A0
tAD1
tAD1
*1
A12/A11
tCSD1
tCSD1
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRWD1
RD/WR
tRASD1
tRASD1
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
DQMxx
(Hi-Z)
D31 to D0
BS
(High)
CKE
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.32 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)
Page 1658 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tp
Tpw
Trr
Trc
Trc
Trc
CK
tAD1
tAD1
A25 to A0
tAD1
A12/A11
tAD1
*1
tCSD1
tCSD1
tCSD1
tCSD1
CSn
tRWD1
tRWD1
tRASD1
tRASD1
tRWD1
RD/WR
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
CASU/L
DQMxx
(Hi-Z)
D31 to D0
BS
tCKED1
tCKED1
CKE
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.33 Synchronous DRAM Self-Refreshing Timing
(WTRP = 1 Cycle)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1659 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tp
Tpw
Trr
Trc
Trc
Trr
Trc
Trc
Tmw
Tde
CK
PALL
REF
REF
MRS
tAD1
tAD1
tAD1
A25 to A0
tAD1
tAD1
*1
A12/A11
tCSD1
tCSD1
tRWD1
tRWD1
tRASD1
tRASD1
tCSD1
tCSD1
tCSD1
tCSD1
tCSD1
tCSD1
tRWD1
tRWD1
tRASD1
tRASD1
CSn
tRWD1
RD/WR
tRASD1
tRASD1
tRASD1
tRASD1
RASU/L
tCASD1
tCASD1
tCASD1
tCASD1
tCASD1
tCASD1
CASU/L
DQMxx
(Hi-Z)
D31 to D0
BS
CKE
DACKn
TENDn*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.34 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)
Page 1660 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tr
Tc
Td1
Tde
Tap
Tr
Tc
Tnop
Trw1
Tap
CK
tAD3
tAD3
Row
address
A25 to A0
tAD3
tAD3
tAD3
*1
tAD3
Column
address
tAD3
tAD3
tAD3
tAD3
READA
Command
A12/A11
tCSD2
tAD3
Row
address
Column
address
tAD3
tAD3
WRITA
Command
tCSD2
tCSD2
tCSD2
CSn
tRWD2
tRWD2
tRWD2
RD/WR
tRASD2
tRASD2
tCASD2
tCASD2
tRASD2
tRASD2
RASU/L
tCASD2
tCASD2
tCASD2
CASU/L
tDQMD2
tDQMD2
tDQMD2
tDQMD2
DQMxx
tRDS4
tRDH4
tWDD3
tWDH3
tBSD
tBSD
D31 to D0
tBSD
tBSD
BS
(High)
(High)
CKE
tDACD
tDACD
tDACD
tDACD
DACKn
TENDn *2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.35 Synchronous DRAM Access Timing in Low-Frequency Mode
(Auto-Precharge, TRWL = 2 Cycles)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1661 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
Tp
Tpw
Trr
Trc
Trc
Trc
CK
tAD3
tAD3
tAD3
tAD3
A25 to A0
A12/A11
*1
tCSD2
tCSD2
tRWD2
tRWD2
tRASD2
tRASD2
tCSD2
tCSD2
tRASD2
tRASD2
tCASD2
tCASD2
CSn
RD/WR
RASU/L
tCASD2
CASU/L
tDQMD2
DQMxx
(Hi-Z)
D31 to D0
BS
tCKED2
tCKED2
CKE
DACKn
TENDn *2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.36 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
(WTRP = 2 Cycles)
Page 1662 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.3.4
Section 31 Electrical Characteristics
UBC Trigger Timing
Table 31.8 UBC Trigger Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
UBCTRG delay time
tUBCTGD
—
20
ns
Figure 31.37
CK
tUBCTGD
UBCTRG
Figure 31.37 UBC Trigger Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1663 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.5
DMAC Module Timing
Table 31.9 DMAC Module Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
DREQ setup time
tDRQS
20
—
ns
Figure 31.38
DREQ hold time
tDRQH
20
—
DACK, TEND delay time
tDACD
—
20
Figure 31.39
CK
tDRQS tDRQH
DREQn
Note: n = 0 to 2
Figure 31.38 DREQ Input Timing
CK
t
DACD
t
DACD
TENDn
DACKm
Note: n = 0, 1
m = 0 to 2
Figure 31.39 DACK, TEND Output Timing
Page 1664 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.3.6
Section 31 Electrical Characteristics
Multi Function Timer Pulse Unit 2 (MTU2) Timing
Table 31.10 Multi Function Timer Pulse Unit 2 (MTU2) Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
Output compare output delay time
tTOCD
⎯
50
ns
Figure 31.40
Input capture input setup time
tTICS
20
⎯
ns
Input capture input pulse width
(single edge)
tTICW
1.5
⎯
tPcyc
Input capture input pulse width
(both edges)
tTICW
2.5
⎯
tPcyc
Timer input setup time
tTCKS
20
⎯
ns
Timer clock pulse width (single edge) tTCKWH/L
1.5
⎯
tPcyc
Timer clock pulse width (both edges)
tTCKWH/L
2.5
⎯
tPcyc
Timer clock pulse width
(phase counting mode)
tTCKWH/L
2.5
⎯
tPcyc
Figure 31.41
Note: tPcyc indicates peripheral clock (Pφ) cycle.
CK
tTOCD
Output compare
output
tTICS
Input capture
input
tTICW
Figure 31.40 MTU2 Input/Output Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1665 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
CK
tTCKS
tTCKS
TCLKA to
TCLKD
tTCKWL
tTCKWH
Figure 31.41 MTU2 Clock Input Timing
31.3.7
Multi Function Timer Pulse Unit 2S (MTU2S) Timing
Table 31.11 Multi Function Timer Pulse Unit 2S (MTU2S) Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
Output compare output delay time
tTOCD
⎯
50
ns
Figure 31.42
Input capture input setup time
tTICS
20
⎯
ns
Input capture input pulse width
(single edge)
tTICW
1.5
⎯
tMcyc
Input capture input pulse width
(both edges)
tTICW
2.5
⎯
tMcyc
Note: tMcyc indicates MTU2S clock (Mφ) cycle.
CK*
tTOCD
Output compare
output
tTICS
Input capture
input
tTICW
Note: * When the Mφ frequency is higher than the Bφ frequency, Mφ is used instead of CK.
Figure 31.42 MTU2S Input/Output Timing
Page 1666 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.3.8
Section 31 Electrical Characteristics
POE2 Module Timing
Table 31.12 POE2 Module Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
POE input setup time
tPOES
50
—
ns
Figure 31.43
POE input pulse width
tPOEW
1.5
—
tpcyc
Note: tpcyc indicates peripheral clock (Pφ) cycle.
CK
tPOES
POEn input
tPOEW
Figure 31.43 POE2 Input/Output Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1667 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.9
Watchdog Timer Timing
Table 31.13 Watchdog Timer Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
WDTOVF delay time
tWOVD
—
50
ns
Figure 31.44
CK
tWOVD
tWOVD
WDTOVF
Figure 31.44 Watchdog Timer Timing
Page 1668 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.10 SCI Module Timing
Table 31.14 SCI Module Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol Min.
Max.
Unit
Figure
Input clock cycle (asynchronous)
tScyc
4
⎯
tpcyc
Figure 31.45
Input clock cycle (clocked synchronous)
tScyc
6
⎯
tpcyc
Input clock pulse width
tSCKW
0.4
0.6
tscyc
Input clock rise time
tSCKr
⎯
1.5
tpcyc
Input clock fall time
tSCKf
⎯
1.5
tpcyc
Transmit data delay time (asynchronous) tTXD
⎯
4tpcyc + 20
ns
Receive data setup time
tRXS
4tpcyc
⎯
ns
Receive data hold time
tRXH
4tpcyc
⎯
ns
Transmit data delay time (clocked
synchronous)
Receive data setup time
tTXD
⎯
3tpcyc + 20
ns
tRXS
3tpcyc + 20
–
ns
Receive data hold time
tRXH
3tpcyc + 20
–
ns
Figure 31.46
Note: tpcyc indicates peripheral clock (Pφ) cycle.
tSCKr
tSCKW
VIH
SCK0 to SCK2,
SCK4
VIH
VIH
VIL
VIL
tSCKf
VIH
VIL
tScyc
Figure 31.45 Input Clock Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1669 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
SCI I/O timing (clocked synchronous mode)
tscyc
SCK0 to SCK2, SCK4
(input/output)
tTXD
TXD0 to TXD2, TXD4
(transmit data)
tRXS
tRXH
RXD0 to RXD2, RXD4
(receive data)
SCI I/O timing (asynchronous mode)
T1
VOH
Tn
VOH
CK
tTXD
TXD0 to TXD2, TXD4
(transmit data)
tRXS
tRXH
RXD0 to RXD2, RXD4
(receive data)
Figure 31.46 SCI Input/Output Timing
Page 1670 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.11 SCIF Module Timing
Table 31.15 SCIF Module Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol Min.
Input clock cycle (clocked synchronous) tScyc
(asynchronous)
Max.
Unit
Figure
6
—
tpcyc
Figure 31.47
4
—
tpcyc
Figure 31.47
Input clock rise time
tSCKr
—
1.5
tpcyc
Figure 31.47
Input clock fall time
tSCKf
—
1.5
tpcyc
Figure 31.47
Input clock width
tSCKW
0.4
0.6
tScyc
Figure 31.47
Transmit data delay time
(clocked synchronous)
tTXD
—
3tpcyc + 20
tpcyc
Figure 31.48
Receive data setup time
(clocked synchronous)
tRXS
3tpcyc + 20
—
ns
Figure 31.48
Receive data hold time
(clocked synchronous)
tRXH
2tpcyc + 5
—
ns
Figure 31.48
Transmit data delay time
(asynchronous)
tTXD
—
3tpcyc + 20
tpcyc
Figure 31.48
Receive data setup time
(asynchronous)
tRXS
3tpcyc + 20
—
ns
Figure 31.48
Receive data hold time
(asynchronous)
tRXH
2tpcyc + 5
—
ns
Figure 31.48
Note: tpcyc indicates peripheral clock (Pφ) cycle.
tSCKW
tSCKr
tSCKf
SCK
tScyc
Figure 31.47 SCK Input Clock Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1671 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
tscyc
SCK3
(input/output)
tTXD
TXD3
(transmit data)
tRXS
tRXH
RXD3
(receive data)
SCIF input/output timing (clocked synchronous mode)
T1
VOH
Tn
VOH
CK
tTXD
TXD3
(transmit data)
tRXS
tRXH
RXD3
(receive data)
SCIF input/output timing (asynchronous mode)
Figure 31.48 SCIF Input/Output Timing in Clocked Synchronous Mode
Page 1672 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.12 Serial Communication Unit (SSU) Timing
Table 31.16 Serial Communication Unit (SSU) Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Clock cycle
Master
Symbol Min.
Max.
Unit
Figure
tSUcyc
4
—
tpcyc
4
—
Figures
31.49, 31.50,
31.51, 31.52
35
—
35
—
35
—
35
—
Slave
Clock high pulse width
Master
tHI
Slave
Clock low pulse width
Master
tLO
Slave
ns
ns
Clock rise time
tRISE
—
15
ns
Clock fall time
tFALL
—
15
ns
tSU
15
—
ns
30
—
10
—
10
—
1.5
—
1.5
—
1.5
—
1.5
—
—
20
—
35
1.5
—
1.5
—
Data input setup time
Master
Slave
Data input hold time
Master
tH
Slave
SCS setup time
Master
tLEAD
Slave
SCS hold time
Master
tLAG
Slave
Data output delay time
Master
tOD
Slave
Continuous transmission
delay time
Master
tTD
Slave
ns
tpcyc
tpcyc
ns
tpcyc
Slave access time
tSA
—
1
tpcyc
Figure 31.51
Slave out release time
tREL
—
1
tpcyc
Figure 31.52
Note: tpcyc indicates peripheral clock (Pφ) cycle.
The above values are for a TTL output. The above values are not guaranteed for an opendrain output.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1673 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
SCS (output)
tTD
tLEAD
tFALL
tHI
SSCK (output)
CPOS = 1
tRISE
tLAG
t LO
t HI
SSCK (output)
CPOS = 0
tSUcyc
tLO
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 31.49 SSU Timing (Master, CPHS = 1)
SCS (output)
tTD
tLEAD
tFALL
tHI
SSCK (output)
CPOS = 1
tRISE
tLAG
tLO
tHI
SSCK (output)
CPOS = 0
tLO
tSUcyc
SSO (output)
tOD
SSI (input)
tSU
tH
Figure 31.50 SSU Timing (Master, CPHS = 0)
Page 1674 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
SCS (input)
tLEAD
tFALL
t HI
SSCK (input)
CPOS = 1
tRISE
tLAG
tTD
tLO
tHI
SSCK (input)
CPOS = 0
tLO
tSUcyc
SSO (input)
tSU
tH
tREL
SSI (output)
tOD
tSA
Figure 31.51 SSU Timing (Slave, CPHS = 1)
SCS (input)
tTD
tLEAD
tFALL
tHI
SSCK (input)
CPOS = 1
tRISE
tLAG
tLO
tHI
SSCK (input)
CPOS = 0
t SUcyc
tLO
SSO (input)
tSU
tH
tREL
SSI (output)
t SA
t OD
Figure 31.52 SSU Timing (Slave, CPHS = 0)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1675 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.13 Controller Area Network (RCAN-ET) Timing
Table 31.17 shows RCAN-ET timing.
Table 31.17 Controller Area Network (RCAN-ET) Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = 4.5 to 5.5 V,
AVREF = 4.5 V to AVCC , Vss = PLLVss = AVss = AVREFVss = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
Figure 31.53
Transmit data delay time
tCTxD
—
100
ns
Receive data setup time
tCRxS
100
—
ns
Receive data hold time
tCRxH
100
—
ns
VOH
VOH
CK
tCTxD
CTx
(Transmit data)
tCRxS
tCRxH
CRx
(Receive data)
Figure 31.53 RCAN-ET Input/Output Timing
Page 1676 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.14 IIC3 Module Timing
Table 31.18 I2C Bus Interface 3 Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Specifications
Item
Symbol
Test Conditions
Min.
1
Typ.
Max.
Unit
Figure
Figure 31.54
SCL input cycle time
tSCL
12 tpcyc* + 600
—
—
ns
SCL input high pulse width
tSCLH
3 tpcyc*1 + 300
—
—
ns
SCL input low pulse width
tSCLL
5 tpcyc*1 + 300
—
—
ns
SCL, SDA input rise time
tSr
—
—
300
ns
SCL, SDA input fall time
tSf
—
—
300
ns
SCL, SDA input spike pulse
tSP
—
—
1 tpcyc*1
ns
SDA input bus free time
tBUF
5
—
—
tpcyc*1
Start condition input hold time
tSTAH
3
—
—
tpcyc*1
Retransmit start condition input
tSTAS
3
—
—
tpcyc*1
Stop condition input setup time
tSTOS
3
—
—
tpcyc*1
Data input setup time
tSDAS
1 tpcyc*1 + 20
—
—
ns
Data input hold time
tSDAH
0
—
—
ns
SCL, SDA capacitive load
Cb
0
—
400
pF
SCL, SDA output fall time*3
tSf
20 + 0.1 cb
—
250
ns
2
removal time*
setup time
Notes: 1. tpcyc indicates peripheral clock (Pφ) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1677 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSP
tSTAS
tSTOS
SCL
P*
S*
tSf
Sr*
tSCLL
P*
tSDAS
tSr
tSCL
tSDAH
[Legend]
S: Start condition
P: Stop condition
Sr: Start condition for retransmission
Figure 31.54 I2C Bus Interface 3 Input/Output Timing
31.3.15 A/D Trigger Input Timing
Table 31.19 A/D Trigger Input Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Module
Item
A/D
converter
Trigger input
setup time
Symbol
Min.
Max.
Unit
Figure
tTRGS
20
—
ns
Figure 31.55
B:P clock ratio = 2:1
tcyc + 20
—
B:P clock ratio = 4:1
3 × tcyc + 20
—
B:P clock ratio = 1:1
CK
tTRGS
ADTRG
Figure 31.55 A/D Converter External Trigger Input Timing
Page 1678 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.16 I/O Port Timing
Table 31.20 I/O Port Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
Output data delay time
tPORTD
—
50
ns
Figure 31.56
Input data setup time
tPORTS
20
—
Input data hold time
tPORTH
20
—
CK
tPORTS tPORTH
Port
(read)
tPORTD
Port
(write)
Figure 31.56 I/O Port Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1679 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.17 H-UDI Related Pin Timing
Table 31.21 H-UDI Related Pin Timing
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Max.
Unit
Figure
TCK cycle time
tTCKcyc
50*
—
ns
Figure 31.57
TCK high pulse width
tTCKH
0.4
0.6
tTCKcyc
TCK low pulse width
tTCKL
0.4
0.6
tTCKcyc
TDI setup time
tTDIS
15
—
ns
TDI hold time
tTDIH
15
—
ns
TMS setup time
tTMSS
15
—
ns
TMS hold time
tTMSH
15
—
ns
TDO delay time
tTDOD
—
30
ns
Note:
*
Figure 31.58
Should be greater than the peripheral clock (Pφ) cycle time.
tTCKcyc
tTCKH
tTCKL
VIH
VIH
VIH
1/2 PVcc
1/2 PVcc
VIL
VIL
Figure 31.57 TCK Input Timing
Page 1680 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
tTCKcyc
TCK
tTDIS
tTDIH
tTMSS
tTMSH
TDI
TMS
tTDOD
TDO change timing
after switch command setting
TDO
tTDOD
Initial value
Figure 31.58 H-UDI Data Transfer Timing
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1681 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.3.18 AC Characteristics Measurement Conditions
• I/O signal level: VIL (Max.)/VIH (Min.)
• Output signal reference level: High level = 2.0 V, low level = 0.8 V
• Input rise and fall times: 1 ns
IOL
DUT output
LSI output pin
VREF
CL
IOH
Notes: 1. CL is the total value that includes the capacitance of measurement
tools. Each pin is set as follows:
30 pF: CK
30 pF: All pins
2. Test conditions include IOL = 1.6 mA and IOH = −200 µA.
Figure 31.59 Output Load Circuit
Page 1682 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.4
Section 31 Electrical Characteristics
A/D Converter Characteristics
Table 31.22 lists the A/D converter characteristics.
Table 31.22 A/D Converter Characteristics
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Min.
Typ.
Resolution
—
12.0
—
bits
Conversion time
1.0
—
—
μs
Sample & hold circuits or
offset cancel circuit is not in
use
2.6
—
—
μs
Sample & hold circuits or
offset cancel circuit is in use
Analog input capacitance
—
—
5.0
pF
Permissible signal-source impedance
—
—
3.0
kΩ
Nonlinearity error (integral error)
—
—
±4.0
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
0.5
LSB
—
—
±8.0
LSB
VAN = AVREFVSS + 0.25 V to
AVREF – 0.25 V
Sample & hold
—
circuits are not in
use
—
±8.0
LSB
VAN = AVREFVSS to AVREF
Absolute accuracy
Sample & hold
circuits are in
use
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Max. Unit
Test Condition
Page 1683 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.5
D/A Converter Characteristics
Table 31.23 lists the D/A converter characteristics.
Table 31.23 D/A Converter Characteristics
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5 V,
VSS = PLLVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Min.
Typ.
Max.
Unit
Resolution
—
8
—
bits
Conversion time
10
—
—
μs
Load capacitance 20 pF
Absolute accuracy
—
±2.0
±3.0
LSB
Load resistance 2 MΩ
—
—
±2.5
LSB
Load resistance 4 MΩ
Page 1684 of 1778
Test Conditions
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.6
Section 31 Electrical Characteristics
USB Characteristics
Table 31.24 USB Characteristics (USD+ and USD- Pins) when Using On-Chip Transceiver
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Specifications
Item
Symbol Min.
Max.
Unit
Test Condition
Figure
Input
Input high level
characteri voltage
stics
Input low level
VIH
2.0
—
V
VIL
—
0.8
V
Differential input
sense
VDI
0.2
—
V
Differential
common mode
range
VCM
0.8
2.5
V
VOH
2.8
—
V
RL of 15 kΩ to VSS
VOL
—
0.3
V
RL of 1.5 kΩ to 3.6 V
Crossover voltage
VCRS
1.3
2.0
V
Rise time
tR
4
20
ns
Fall time
tF
4
20
ns
Rise time/fall time
matching
tRFM
90
111.11 %
Output resistance
ZDRV
28
44
Figures
31.60,
31.61
voltage
Output
Output high level
characteri voltage
stics
Output low level
I(D+) – (D – )I
DrVCC = 3.3 to 3.6 V
voltage
Ω
(tR/tF)
Including
Rs = 20 Ω
Note: When the USB is not used, connect DrVss to GND and DrVcc to Vcc.
USD− and USD+ should be left open. In this case, DrVcc = 3.0 V to 5.5 V.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1685 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
USD+, USD-
Rise time
90%
VCRS
Fall time
90%
10%
Differential
data lines
10%
tR
tF
Figure 31.60 Data Signal Timing
USD+
Rs = 20 Ω
USD-
Rs = 20 Ω
Test point
C L = 50 pF
Test point
C L = 50 pF
Figure 31.61 Test Load Circuit
Page 1686 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
31.7
Section 31 Electrical Characteristics
Flash Memory Characteristics
Table 31.25 Flash Memory Characteristics
Conditions: VCC = 3.0 to 5.5 V, AVCC = AVREF = 4.5 to 5.5V,
VSS = PLLVSS = AVREFVSS = AVSS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol
Min.
Typ.
Max.
Unit
tP
—
2
20
ms/256 bytes
Erase time* * *
tE
—
0.6
1.5
s/byte
Number of rewrite times
NWEC
—
—
100
times
1
2
Programming time* *
1
Notes: 1.
2.
3.
4.
3
4
Use the on-chip writing/erasing routine for writing or erasing.
When all 0 is written
When a 64-Kbyte block is erased
tE is distributed centering around the typical value (Typ.).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1687 of 1778
SH7280 Group, SH7243 Group
Section 31 Electrical Characteristics
31.8
Usage Notes
31.8.1
Notes on Connecting Capacitors
This LSI includes an internal step-down circuit to automatically reduce the internal power supply
voltage to an appropriate level. Between this internal stepped-down power supply (VCL pin) and
the VSS pin, a capacitor for stabilizing the internal voltage needs to be connected. Connection of
the external capacitor is shown in figure 31.62. The external capacitor should be located near the
pin. Do not apply any power supply voltage to the VCL pin.
A multilayer ceramic capacitor should be inserted for each pair of power supply pins as a bypass
capacitor. The bypass capacitor must be inserted as close to the power supply pins of the LSI as
possible. Connect the bypass capacitor and the capacitor for stabilizing the internal voltage with
the capacitance from 0.02 to 0.33 μF, after being evaluated in the system. For details on capacitors
related to crystal oscillation, see section 4.9, Notes on Board Design.
0.1 µF
External power-supply
stabilizing capacitor
Bypass capacitor
0.1 µF
VCL
0.1 µF
0.1 µF
VCCQ
VSS
VCL
VCL
VCCQ
VCCQ
VSS
VSS
0.1 µF
0.1 µF
Note: Do not apply any power supply voltage to the VCL pin.
Use multilayer ceramic capacitors (one capacitor
for each VCL pin and VCCQ pin), which should be located near the pin.
The above capacitance is a recommended value.
Figure 31.62 Connection of Capacitors
Page 1688 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Appendix
A.
Pin States
Pin initial states differ according to MCU operating modes. Refer to section 23, Pin Function
Controller (PFC), for details.
Table A.1
Pin States (SH7243)
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Clock
Pin Name
8 bits
CK
O
XTAL
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Z
Manual Software Standby
4
Stop
Sleep Release Detected
4
Function
Used
O
Z*
O
Z*
O
O
O
O
L
O
O
O
O
EXTAL
I
I
I
I
I
I
I
System
RES
I
I
I
I
I
I
I
control
MRES
Z
I
I*
I
I
I*7
I
7
WDTOVF
O*
O
O
O
O
O
O
BREQ
Z
I
Z
I
I
I
I
BACK
Z
O
Z
O
L
O
O
Operating
MD0, MD1
I
I
I
I
I
mode control
ASEMD0
I*
I*
I*
I*
FWE
I
I
I
NMI
I
I
I
IRQ0 to IRQ7
Z
I
I
Interrupt
IRQOUT
9
10
10
Z
O
(PE15)
10
Z
10
I
10
I
10
I*
I*
I*10
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O*
O
Z
O
7
O
(MZIZEH in HCPCR = 0)
1
H*
(MZIZEH in HCPCR = 1)
Address bus A0 to A20
O
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Z
O
Z*3
O
Page 1689 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
Data bus
D0 to D8, D10
Z
Bus control
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Used
I/O
I/O
I/O
Z
I/O
Z
WAIT
I
Z
CS0, CS1,
Function
Sleep Release Detected
D9, D11 to D15 Z
Z
Stop
Manual Software Standby
Z
I/O
6
I/O
Z
I/O*
I/O
I
Z
I
I
O
Z*
3
O
Z
O
O
Z
O
Z*3
O
Z
O
O
Z
O
Z*3
O
Z
O
2
H
Z
CS2, CS3
CS2, CS3,
CS6, CS7
BS
RASL
CASL
DQMLU,
Z
Z
O
Z*
O
O
O
2
O
O
2
Z*
2
O
Z*
O
O
3
Z*
Z
O
Z*
O
Z
O
O
RDWR
Z
O
Z*3
O
Z
O
O
RD
H
O
Z*3
O
Z
O
O
O
3
O
Z
O
O
DQMLL
WRH, WRL
CKE
DMAC
DREQ0 (PE0),
H
Z
Z
Z
O
Z*
2
Z*
O
2
Z*
O
O
8
Z
I
Z
I
I
I*
I
Z
O
Z
O
O
O*7
O
O
O
O*8
O
I
I
I
I
DREQ1 (PE2)
DACK0,
DACK1
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
TEND0,
Z
O
TEND1
Z
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
MTU2
TCLKA to
Z
I
Z
TCLKD
Page 1690 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
MTU2
TIOC0A to
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
Used
I/O
I/O
I/O
I/O
Z
TIOC0D
Z
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC1A
Z
I/O
K*1
I/O
I/O
I/O
I/O
TIOC1B
Z
I/O
Z
I/O
I/O
I/O*8
I/O
I/O
I/O
I/O*8
I/O
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2A
Z
I/O
Z
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2B
TIOC3A,
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
K*
1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*7
Z
I/O
I/O
I/O*7
Z
Z
TIOC3C
TIOC3B,
TIOC3D
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
TIOC4A to
Z
I/O
TIOC4D
Z
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
TIC5U, TIC5V,
Z
I
Z
I
I
I
I
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*6
Z
TIC5W
MTU2S
TIOC3AS,
TIOC3CS
TIOC3BS
(PD10),
(MZIZDL in HCPCR = 0)
TIOC3DS
K*
(PD11)
(MZIZDL in HCPCR = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
1
Page 1691 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
MTU2S
Pin Name
8 bits
TIOC3BS
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Function
Sleep Release Detected
I/O
I/O
I/O
I/O*8
Z
I/O
I/O
I/O*6
Z
I/O
I/O
I/O*8
Z
Z
(PE5),
(MZIZEL in HCPCR = 0)
TIOC3DS
K*
(PE6)
TIOC4AS
Stop
Manual Software Standby
Used
1
(MZIZEL in HCPCR = 1)
Z
I/O
Z
(PD12),
(MZIZDL in HCPCR = 0)
TIOC4BS
K*
(PD13),
(MZIZDL in HCPCR = 1)
1
TIOC4CS
(PD14),
TIOC4DS
(PD15)
TIOC4AS
Z
I/O
Z
(PE0),
(MZIZEL in HCPCR = 0)
TIOC4BS
K*
(PE1),
(MZIZEL in HCPCR = 1)
1
TIOC4CS
(PE2),
TIOC4DS
(PE3)
TIC5US,
Z
I
Z
I
I
I
I
Z
I
Z
I
I
I
I
SCK0, SCK2
Z
I/O
K*1
I/O
I/O
I/O
I/O
RXD0, RXD2
Z
I
Z
I
I
I
I
O
O
O
O
TIC5VS,
TIC5WS
POE
POE0,
POE3, POE4,
POE8
SCI
TXD0, TXD2
Page 1692 of 1778
Z
O
O*
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
SCIF
SCK3
Z
SCK3 (PE6)
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Manual Software Standby
I/O
I/O
K*1
Z
Stop
Function
Sleep Release Detected
Used
I/O
I/O
I/O
I/O
I/O
I
I/O
8
I/O
I/O*
I
I
I
O
O
O
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
RXD3
TXD3
TXD3 (PE5)
Z
Z
Z
I
O
O
Z
1
O*
Z
O
O
O
O*
8
O
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
UBC
UBCTRG
Z
O
O*1
O
O
O
O
A/D
AN0 to AN7
Z
I
Z
I
I
I
I
Converter
ADTRG
Z
I
Z
I/O Port
PA6 to PA9,
I
I
I
I
1
Z
I/O
K*
I/O
I/O
I/O
I/O
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
K*
1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*6
Z
PA10 to PA15
PB0, PB1,
PB6 to PB8,
PB11, PB12
PC0 to PC15
PD0 to PD8,
PD10
PD9,
PD11 to PD15
(MZIZDL in HCPCR = 0)
K*
1
(MZIZDL in HCPCR = 1)
PE4, PE7,
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*8
Z
PE8, PE10
PE0 to PE3,
PE5, PE6
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1693 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
I/O Port
Pin Name
8 bits
PE9, PE11 to
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
I/O
I/O
I/O
I/O*7
Z
I
I
I
I
PE15
Z
Used
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
PF0 to PF7
Z
I
Z
[Legend]
I:
Input
O:
Output
H:
High-level output
L:
Low-level output
Z:
High-impedance
K:
Input pins become high-impedance, and output pins retain their state.
Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 3
(STBCR3) is set to 1.
2. Becomes output when the HIZCNT bit in the common control register (CMNCR) is set
to 1.
3. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set
to 1.
4. Becomes output when the HIZCKIO bit in the common control register (CMNCR) is set
to 1.
5. Becomes high-impedance when the MZIZDH bit in the high-current port control register
(HCPCR) is cleared to 0.
6. Becomes high-impedance when the MZIZDL bit in the high-current port control register
(HCPCR) is cleared to 0.
7. Becomes high-impedance when the MZIZEH bit in the high-current port control register
(HCPCR) is cleared to 0.
8. Becomes high-impedance when the MZIZEL bit in the high-current port control register
(HCPCR) is cleared to 0.
9. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pulldown with a resistance of at least 1 MΩ as required.
10. Pulled-up inside the LSI when there is no input.
Page 1694 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Table A.2
Appendix
Pin States (SH7285)
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
Clock
CK
O
XTAL
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
Stop
Manual Software Standby
Z
O
Z*4
O
Z*4
O
O
O
O
L
O
O
O
O
EXTAL
I
I
I
I
I
I
I
System
RES
I
I
I
I
I
I
control
MRES
Z
7
Sleep Release Detected
Function
chip
I
I*
I
I
I*
Used
I
7
I
WDTOVF
O*
O
O
O
O
O
O
BREQ
Z
I
Z
I
I
I
I
BACK
Z
O
Z
O
L
O
O
9
Operating
MD0, MD1
I
I
I
I
I
I
I
mode control
ASEMD0
I*
I*10
I*10
I*10
I*10
I*10
I*10
FWE
I
I
I
I
I
I
I
NMI
I
I
I
I
I
I
I
IRQ0 to IRQ7
Z
I
I
I
I
I
Interrupt
IRQOUT
10
Z
O
(PE15)
Z
I
O
O
O*
7
O
(MZIZEH in HCPCR = 0)
1
H*
(MZIZEH in HCPCR = 1)
IRQOUT
Z
O
H*
1
O
O
O
O
O
Z*3
O
Z
O
O
(PE30)
Address bus A0 to A20
O
Data bus
Bus control
D0 to D8, D10
Z
Z
I/O
Z
I/O
Z
I/O
I/O
D9, D11 to D15 Z
I/O
Z
I/O
Z
I/O*6
I/O
WAIT
I
Z
CS0, CS1
CS2, CS3,
Z
H
Z
O
I
Z
I
I
3
O
Z
O
O
3
O
O
O
O
O
O
Z*
Z
O
Z*
O
Z
Z
O
Z*3
O
Z
O
2
CS4 to CS7
BS
RASL
Z
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Z*
O
Z*
2
Page 1695 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
Bus control
CASL
Z
DQMLU,
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Manual Software Standby
Stop
Sleep Release Detected
Function
Used
O
Z*2
O
Z*2
O
O
Z
O
Z*
3
O
Z
O
O
Z
O
Z*3
O
Z
O
DQMLL
AH (PA23)
AH (PE14)
Z
O
Z
O
7
O
Z
O*
O
(MZIZEH in HCPCR = 0)
3
Z*
(MZIZEH in HCPCR = 1)
RDWR
RD
DMAC
Z
H
Z
O
Z*3
O
Z
O
O
O
3
O
Z
O
O
3
Z*
WRH, WRL
H
O
Z*
O
Z
O
O
CKE
Z
O
Z*2
O
Z*2
O
O
DREQ0 (PD24),
Z
I
Z
I
I
I*5
I
Z
I
Z
I
I
I*8
I
Z
O
Z
O
O
O*5
O
O
O
O*7
O
Z
DREQ1 (PD25)
DREQ0 (PE0),
DREQ1 (PE2)
DACK0 (PD26),
DACK1 (PD27)
(MZIZDH in HCPCR = 0)
O*
1
(MZIZDH in HCPCR = 1)
DACK0 (PE14), Z
O
DACK1 (PE15)
Z
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
TEND0,
Z
O
O*1
O
O
O
O
Z
I
Z
I
I
I
I
TEND1
MTU2
TCLKA to
TCLKD
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
Page 1696 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
MTU2
Pin Name
8 bits
TIOC0A to
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
I/O
I/O
I/O
I/O*8
Z
TIOC0D
Z
Used
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC1A
Z
I/O
K*1
I/O
I/O
I/O
I/O
TIOC1B
Z
I/O
Z
I/O
I/O
I/O*8
I/O
I/O
I/O
I/O*8
I/O
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2A
Z
I/O
Z
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2B
Z
I/O
K*1
I/O
I/O
I/O
I/O
TIOC3A,
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*7
Z
I/O
I/O
I/O*7
Z
TIOC3C
TIOC3B,
TIOC3D
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
TIOC4A to
Z
I/O
TIOC4D
Z
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
TIC5U, TIC5V,
Z
I
Z
I
I
I
I
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*6
Z
TIC5W
TIOC3AS,
TIOC3CS
TIOC3BS
(PD10),
(MZIZDL in HCPCR = 0)
TIOC3DS
K*
(PD11)
(MZIZDL in HCPCR = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
1
Page 1697 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
MTU2S
Pin Name
8 bits
TIOC3BS
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
I/O
I/O
I/O
I/O*5
Z
I/O
I/O
I/O*8
Z
I/O
I/O
I/O*6
Z
I/O
I/O
I/O*5
Z
I/O
I/O
I/O*8
Z
Z
(MZIZDH in HCPCR = 0)
TIOC3DS
K*
(PD28)
Used
1
(MZIZDH in HCPCR = 1)
Z
I/O
Z
(PE5),
(MZIZEL in HCPCR = 0)
TIOC3DS
K*
(PE6)
(MZIZEL in HCPCR = 1)
TIOC4AS
Function
Sleep Release Detected
(PD29),
TIOC3BS
Stop
Manual Software Standby
Z
I/O
1
Z
(PD12),
(MZIZDL in HCPCR = 0)
TIOC4BS
K*
(PD13),
(MZIZDL in HCPCR = 1)
1
TIOC4CS
(PD14),
TIOC4DS
(PD15)
TIOC4AS
Z
I/O
Z
(PD27),
(MZIZDH in HCPCR = 0)
TIOC4BS
K*
(PD26),
(MZIZDH in HCPCR = 1)
1
TIOC4CS
(PD25),
TIOC4DS
(PD24)
TIOC4AS
Z
I/O
(PE0),
Z
(MZIZEL in HCPCR = 0)
1
TIOC4BS
K*
(PE1),
(MZIZEL in HCPCR = 1)
TIOC4CS
(PE2),
TIOC4DS
(PE3)
TIC5US,
Z
I
Z
I
I
I
I
POE0 to POE8 Z
I
Z
I
I
I
I
TIC5VS,
TIC5WS
POE
Page 1698 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
SCI
Pin Name
8 bits
SCK0 to SCK2, Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Manual Software Standby
Stop
Function
Sleep Release Detected
Used
I/O
K*1
I/O
I/O
I/O
I/O
I
Z
I
I
I
I
O
O*1
O
O
O
O
I/O
K*1
I/O
I/O
I/O
I/O
I/O
I/O
I
SCK4
RXD0 to RXD2, Z
RXD4
TXD0 to TXD2, Z
TXD4
SCIF
SCK3
SCK3 (PE6)
Z
Z
I/O
Z
8
I/O
I/O*
I
I
I
O
O
O
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
RXD3
TXD3
TXD3 (PE5)
Z
Z
Z
I
O
O
Z
1
O*
Z
O
O
O
O*
8
O
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
SSU
SSCK
I/O
K*
1
I/O
I/O
I/O
I/O
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SCS
Z
I/O
K*
SSI
Z
I/O
Z
SSO
IIC3
Z
Z
I/O
K*
1
SCL
Z
I/O
Z
I/O
I/O
I/O
I/O
SDA
Z
I/O
Z
I/O
I/O
I/O
I/O
UBC
UBCTRG
Z
O
O*1
O
O
O
O
A/D
AN0 to AN7
Z
I
Z
I
I
I
I
Converter
ADTRG
Z
I
Z
I
I
I
I
USB
USBXTAL
O
O
L
O
O
O
O
USBEXTAL
I
I
I
I
I
I
I
1
USPND
Z
O
O*
O
O
O
O
VBUS
I
I
I
I
I
I
I
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1699 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
USB
USD+
USD-
I/O Port
PA0 to PA9,
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
Used
Z
I/O
I
I/O
I/O
I/O
I/O
Z
I/O
I
I/O
I/O
I/O
I/O
1
Z
I/O
K*
I/O
I/O
I/O
I/O
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I
Z
PA12 to PA15,
PA21 to PA23
PB0, PB1,
PB6 to PB12
PB2, PB3
PC0 to PC15
PD0 to PD9,
Z
I/O
I
I
I
I
1
I/O
I/O
I/O
I/O
1
K*
Z
I/O
K*
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*6
Z
I/O
I/O
I/O*5
Z
PD16 to PD22,
PD30, PD31
PD10 to PD15
(MZIZDL in HCPCR = 0)
K*
1
(MZIZDL in HCPCR = 1)
PD24 to PD29
Z
I/O
Z
(MZIZDH in HCPCR = 0)
K*1
(MZIZDH in HCPCR = 1)
PE4, PE7,
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*8
Z
I/O
I/O
I/O*7
Z
I
I
I
I
PE8, PE10
PE0 to PE3,
PE5, PE6
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
PE9, PE11 to
Z
I/O
PE15
Z
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
PF0 to PF7
Z
I
Z
[Legend]
I:
Input
Page 1700 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
O:
H:
L:
Z:
K:
Notes:
Appendix
Output
High-level output
Low-level output
High-impedance
Input pins become high-impedance, and output pins retain their state.
1. Output pins become high-impedance when the HIZ bit in standby control register 3
(STBCR3) is set to 1.
2. Becomes output when the HIZCNT bit in the common control register (CMNCR) is set
to 1.
3. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set
to 1.
4. Becomes output when the HIZCKIO bit in the common control register (CMNCR) is set
to 1.
5. Becomes high-impedance when the MZIZDH bit in the high-current port control register
(HCPCR) is cleared to 0.
6. Becomes high-impedance when the MZIZDL bit in the high-current port control register
(HCPCR) is cleared to 0.
7. Becomes high-impedance when the MZIZEH bit in the high-current port control register
(HCPCR) is cleared to 0.
8. Becomes high-impedance when the MZIZEL bit in the high-current port control register
(HCPCR) is cleared to 0.
9. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pulldown with a resistance of at least 1 MΩ as required.
10. Pulled-up inside the LSI when there is no input.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1701 of 1778
SH7280 Group, SH7243 Group
Appendix
Table A.3
Pin States (SH7286)
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
Clock
CK
O
XTAL
Master- Oscillation POE
ship
Expansion Single-
Stop
Manual Software Standby
Z
O
Z*4
O
Z*4
O
O
O
O
L
O
O
O
O
EXTAL
I
I
I
I
I
I
I
System
RES
I
I
I
I
I
I
control
MRES
Z
7
Sleep Release Detected
Function
chip
Used
I
7
I
I*
I
I
I*
I
O
O
O
O
O
O
WDTOVF
O*
BREQ
Z
I
Z
I
I
I
I
BACK
Z
O
Z
O
L
O
O
Operating
MD0, MD1
I
mode control
ASEMD0
I*
FWE
Interrupt
16 bits with ROM
9
I
I
I
I
I
I
I*10
I*10
I*10
I*10
I*10
I*10
I
I
I
I
I
I
I
NMI
I
I
I
I
I
I
I
IRQ0 to IRQ7
Z
I
I
I
I
I
IRQOUT
10
Z
O
(PE15)
Z
I
7
O
O
O*
O
(MZIZEH in HCPCR = 0)
1
H*
(MZIZEH in HCPCR = 1)
IRQOUT
Z
O
H*
1
O
O
O
O
O
Z*3
O
Z
O
O
I/O
(PE30)
Address bus A0 to A25
O
Data bus
Z
I/O
Z
I/O
Z
I/O
Z
I/O
Z
I/O
Z
I/O*6
I/O
I/O
Z
I/O*
5
I/O
I
Z
I
I
O
Z
O
O
D0 to D9,
Z
D16 to D23,
D30, D31
D10 to D15
Bus control
D24 to D29
Z
I/O
Z
WAIT
Z
I
Z
CS0, CS1
Page 1702 of 1778
H
Z
O
Z*
3
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Master- Oscillation POE
ship
Expansion Single-
Type
Pin Name
8 bits
16 bits with ROM
chip
Bus control
CS2, CS3,
Z
O
Z
Stop
Function
Sleep Release Detected
Used
Z*3
O
Z
O
O
O
Z*3
O
Z
O
2
Manual Software Standby
CS4 to CS7
BS
RASU, RASL
CASU, CASL
DQMUU,
Z
Z
O
Z*
O
O
O
2
O
O
2
Z*
2
O
Z*
O
O
3
O
Z*
Z
O
Z*
O
Z
O
Z
O
Z*3
O
Z
O
DQMUL,
DQMLU,
DQMLL
AH
AH (PE14)
Z
O
Z
O
O
Z
O*
7
O
(MZIZEH in HCPCR = 0)
3
Z*
(MZIZEH in HCPCR = 1)
REFOUT
Z
O
H/Z*1
O
O
Z
H/Z*1
FRAME
Z
O
Z*3
O
Z
O
O
RDWR
Z
O
Z*3
O
Z
O
O
RD
H
O
Z*3
O
Z
O
O
O
3
O
Z
O
O
3
O
Z
O
O
WRHH, WRHL
WRH, WRL
CKE
DMAC
DREQ0 (PD24),
Z
H
Z
Z
H
Z
O
O
Z*
Z*
2
Z*
O
2
Z*
O
O
5
Z
I
Z
I
I
I/O*
I
Z
I
Z
I
I
I*8
I
Z
I
Z
I
I
I
I
Z
O
Z
O
O
O*5
O
DREQ1 (PD25)
DREQ0 (PE0),
DREQ1 (PE2)
DREQ2,
DREQ3
DACK0 (PD26),
DACK1 (PD27)
(MZIZDH in HCPCR = 0)
O*
1
(MZIZDH in HCPCR = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1703 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
DMAC
Pin Name
8 bits
DACK0 (PE14), Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
O
O
O
O*7
O
O
O
O
O
O
O
O*8
O
DACK1 (PE15)
Z
Used
(MZIZEH in HCPCR = 0)
O*
1
(MZIZEH in HCPCR = 1)
DACK2,
Z
O
O*
Z
O
Z
1
DACK3
TEND0,
TEND1
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
MTU2
TCLKA to
Z
I
Z
I
I
I
I
Z
I/O
Z
I/O
I/O
I/O*8
Z
I/O
I/O
I/O
I/O
TCLKD
TIOC0A to
TIOC0D
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC1A
TIOC1B
Z
Z
I/O
I/O
K*1
Z
8
I/O
I/O
I/O*
I/O
I/O
I/O
I/O*8
I/O
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2A
Z
I/O
Z
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2B
TIOC3A,
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
K*
1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*7
Z
Z
TIOC3C
TIOC3B,
TIOC3D
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
Page 1704 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
MTU2
Pin Name
8 bits
TIOC4A to
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
I/O
I/O
I/O
I/O*7
Z
TIOC4D
Z
Used
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
TIC5U, TIC5V,
Z
I
Z
I
I
I
I
Z
I/O
K*1
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*5
Z
I/O
I/O
I/O*5
Z
I/O
I/O
I/O*8
Z
I/O
I/O
I/O*6
Z
I/O
I/O
I/O*5
Z
TIC5W
MTU2S
TIOC3AS,
TIOC3CS
TIOC3BS
(PD10),
(MZIZDL in HCPCR = 0)
TIOC3DS
K*
(PD11)
(MZIZDL in HCPCR = 1)
TIOC3BS
Z
I/O
(PD29),
1
Z
(MZIZDH in HCPCR = 0)
1
TIOC3DS
K*
(PD28)
(MZIZDH in HCPCR = 1)
TIOC3BS
Z
I/O
(PE5),
Z
(MZIZEL in HCPCR = 0)
1
TIOC3DS
K*
(PE6)
(MZIZEL in HCPCR = 1)
TIOC4AS
Z
I/O
(PD12),
Z
(MZIZDL in HCPCR = 0)
1
TIOC4BS
K*
(PD13),
(MZIZDL in HCPCR = 1)
TIOC4CS
(PD14),
TIOC4DS
(PD15)
TIOC4AS
Z
(PD27),
I/O
Z
(MZIZDH in HCPCR = 0)
1
TIOC4BS
K*
(PD26),
(MZIZDH in HCPCR = 1)
TIOC4CS
(PD25),
TIOC4DS
(PD24)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1705 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
MTU2S
Pin Name
8 bits
TIOC4AS
Z
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
I/O
I/O
I/O
I/O*8
Z
I
I
I
I
I
I
I
I
Z
(PE0),
(MZIZEL in HCPCR = 0)
TIOC4BS
K*
(PE1),
(MZIZEL in HCPCR = 1)
Used
1
TIOC4CS
(PE2),
TIOC4DS
(PE3)
TIC5US,
Z
I
Z
POE0 to POE8 Z
I
Z
TIC5VS,
TIC5WS
POE
SCI
SCK0 to SCK2, Z
1
I/O
K*
I/O
I/O
I/O
I/O
I
Z
I
I
I
I
O
O*1
O
O
O
O
SCK4
RXD0 to RXD2, Z
RXD4
TXD0 to TXD2, Z
TXD4
SCIF
SCK3
Z
I/O
K*1
I/O
I/O
I/O
I/O
SCK3 (PE6)
Z
I/O
Z
I/O
I/O
I/O*8
I/O
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
RXD3
Z
I
Z
I
I
I
I
TXD3
Z
O
O*1
O
O
O
O
TXD3 (PE5)
Z
O
Z
O
O
O*8
O
(MZIZEL in HCPCR = 0)
O*
1
(MZIZEL in HCPCR = 1)
SSU
SSCK
Z
I/O
K*
1
I/O
I/O
I/O
I/O
SCS
Z
I/O
K*
1
I/O
I/O
I/O
I/O
SSI
Z
I/O
Z
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSO
Page 1706 of 1778
Z
I/O
K*
1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
Pin Name
8 bits
IIC3
SCL
SDA
Master- Oscillation POE
ship
Expansion Single-
16 bits with ROM
chip
Stop
Function
Manual Software Standby
Sleep Release Detected
Used
Z
I/O
Z
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O
I/O
UBC
UBCTRG
Z
O
O*
O
O
O
O
A/D
AN0 to AN11
Z
I
Z
I
I
I
I
Converter
ADTRG
Z
I
Z
I
I
I
I
USB
USBXTAL
O
O
L
O
O
O
O
RCAN
USBEXTAL
I
I
I
I
I
I
I
USPND
Z
O
O*1
O
O
O
O
VBUS
I
I
I
I
I
I
I
USD+
Z
I/O
I
I/O
I/O
I/O
I/O
USD-
Z
I/O
I
I/O
I/O
I/O
I/O
CRx0
Z
I
Z
CTx0
I/O Port
1
PA0 to PA15,
Z
O
I
I
I
I
1
O
O
O
O
1
O*
Z
I/O
K*
I/O
I/O
I/O
I/O
PB0, PB1, PB6 Z
I/O
K*1
I/O
I/O
I/O
I/O
I
Z
PA21 to PA23
to PB9
PB2, PB3
PC0 to PC15
PD0 to PD9,
Z
Z
I/O
I
I
I
I
1
I/O
I/O
I/O
I/O
1
K*
Z
I/O
K*
I/O
I/O
I/O
I/O
Z
I/O
Z
I/O
I/O
I/O*6
Z
I/O
I/O
I/O*5
Z
PD16 to PD23,
PD30, PD31
PD10 to PD15
(MZIZDL in HCPCR = 0)
K*
1
(MZIZDL in HCPCR = 1)
PD24 to PD29
Z
I/O
Z
(MZIZDH in HCPCR = 0)
K*
1
(MZIZDH in HCPCR = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1707 of 1778
SH7280 Group, SH7243 Group
Appendix
Pin Function
Pin State
Reset State
Power-Down State
Power-On
Bus
Expansion
without ROM
Type
I/O Port
Master- Oscillation POE
ship
Expansion Single-
Pin Name
8 bits
16 bits with ROM
chip
PE4, PE7,
Z
I/O
Z
I/O
Stop
Function
Sleep Release Detected
Used
K*1
I/O
I/O
I/O
I/O
Z
I/O
I/O
I/O*8
Z
I/O
I/O
I/O*7
Z
I
I
I
I
Manual Software Standby
PE8, PE10
PE0 to PE3,
PE5, PE6
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
PE9, PE11 to
Z
I/O
PE15
Z
(MZIZEH in HCPCR = 0)
K*
1
(MZIZEH in HCPCR = 1)
PF0 to PF11
Z
I
Z
[Legend]
I:
Input
O:
Output
H:
High-level output
L:
Low-level output
Z:
High-impedance
K:
Input pins become high-impedance, and output pins retain their state.
Notes:
1. Output pins become high-impedance when the HIZ bit in standby control register 3 (STBCR3) is
set to 1.
2. Becomes output when the HIZCNT bit in the common control register (CMNCR) is set to 1.
3. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set to 1.
4. Becomes output when the HIZCKIO bit in the common control register (CMNCR) is set to 1.
5. Becomes high-impedance when the MZIZDH bit in the high-current port control register (HCPCR)
is cleared to 0.
6. Becomes high-impedance when the MZIZDL bit in the high-current port control register (HCPCR)
is cleared to 0.
7. Becomes high-impedance when the MZIZEH bit in the high-current port control register (HCPCR)
is cleared to 0.
8. Becomes high-impedance when the MZIZEL bit in the high-current port control register (HCPCR)
is cleared to 0.
9. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pull-down with a
resistance of at least 1 MΩ as required.
10. Pulled-up inside the LSI when there is no input.
Page 1708 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group
B.
Appendix
Product Code Lineup
Table B.1
Product Code Lineup
Product Type
Product
ROM
RAM
Capacity
Name
Classification
Capacity
SH7243
F-ZTAT version
128 kbytes 8 kbytes
Operating
temperature
Consumer application
−20 to +85°C R5F72433N100FP
Industrial application
−40 to +85°C R5F72433D100FP
256 kbytes 12 kbytes Consumer application
Industrial application
SH7285
F-ZTAT version
512 kbytes 24 kbytes Consumer application
Industrial application
768 kbytes 32 kbytes Consumer application
Industrial application
SH7286
F-ZTAT version
512 kbytes 24 kbytes Consumer application
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Product Code
LQFP1414-100
(FP-100UV)
−40 to +85°C R5F72434D100FP
−20 to +85°C R5F72855N100FP
−40 to +85°C R5F72855D100FP
LQFP2020-114
(FP-144LV)
−20 to +85°C R5F72856N100FP
−40 to +85°C R5F72856D100FP
−20 to +85°C R5F72865N100FP
−40 to +85°C R5F72865D100FP
Consumer application
−20 to +85°C R5F72865N100FA
Industrial application
−40 to +85°C R5F72865D100FA
−20 to +85°C R5F72866N100FP
Industrial application
−40 to +85°C R5F72866D100FP
Consumer application
−20 to +85°C R5F72866N100FA
Industrial application
−40 to +85°C R5F72866D100FA
32 kbytes Consumer application
(Package Code)
−20 to +85°C R5F72434N100FP
Industrial application
768 kbytes 32 kbytes Consumer application
1 Mbytes
Package
Application
−20 to +85°C R5F72867N100FP
Industrial application
−40 to +85°C R5F72867D100FP
Consumer application
−20 to +85°C R5F72867N100FA
Industrial application
−40 to +85°C R5F72867D100FA
LQFP2424-176
(FP-176EV)
LQFP2020-176
(FP-176AV)
LQFP2424-176
(FP-176EV)
LQFP2020-176
(FP-176AV)
LQFP2424-176
(FP-176EV)
LQFP2020-176
(FP-176AV)
Page 1709 of 1778
100
76
ZD
1
75
e
Index mark
*1
D
y
HD
*3
bp
25
51
x
26
50
Previous Code
100P6Q-A / FP-100U / FP-100UV
ZE
F
HE
RENESAS Code
PLQP0100KB-A
E
*2
JEITA Package Code
P-LQFP100-14x14-0.50
b1
bp
c1
Detail F
Terminal cross section
MASS[Typ.]
0.6g
A
Page 1710 of 1778
A2
c
L1
L
e
x
y
ZD
ZE
L
L1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Reference
Symbol
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Dimension in Millimeters
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
C.
A1
Appendix
SH7280 Group, SH7243 Group
Package Dimensions
Figure C.1 FP-100UV
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
c
144
1
ZD
e
Index mark
y
D
HD
*3
bp
36
73
x
37
72
ZE
F
E
*2
109
108
*1
Previous Code
144P6Q-A / FP-144L / FP-144LV
b1
bp
c1
Detail F
Terminal cross section
MASS[Typ.]
1.2g
A
HE
RENESAS Code
PLQP0144KA-A
A2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
A1
JEITA Package Code
P-LQFP144-20x20-0.50
L
c
L1
e
x
y
ZD
ZE
L
L1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Reference Dimension in Millimeters
Symbol
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
SH7280 Group, SH7243 Group
Appendix
Figure C.2 FP-144LV
Page 1711 of 1778
c
176
133
ZD
1
132
e
Index mark
y
*1
D
HD
*3 b
p
x
44
89
45
88
Previous Code
176P6Q-A / FP-176E / FP-176EV
ZE
F
*2
HE
E
RENESAS Code
PLQP0176KB-A
MASS[Typ.]
1.8g
b1
bp
c1
Detail F
Terminal cross section
A
JEITA Package Code
P-LQFP176-24x24-0.50
A2
Page 1712 of 1778
A1
L1
L
e
x
y
ZD
ZE
L
L1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Min Nom Max
23.9 24.0 24.1
23.9 24.0 24.1
1.4
25.8 26.0 26.2
25.8 26.0 26.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
Reference Dimension in Millimeters
Symbol
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Appendix
SH7280 Group, SH7243 Group
Figure C.3 FP-176EV
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
c
c
JEITA Package Code
P-LQFP176-20x20-0.40
176
133
e
1
132
ZD
D
HD
y
Index mark
*1
*3
bp
44
89
45
88
x
F
ZE
M
MASS[Typ.]
1.4g
E
*2
Previous Code
FP-176A/FP-176AV
A2
A1
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
c
c1
Detail F
L1
L
Terminal cross section
b1
bp
c
HE
RENESAS Code
PLQP0176LB-A
θ
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
20
20
1.40
21.8 22.0 22.2
21.8 22.0 22.2
1.70
0.05 0.10 0.15
0.13 0.18 0.23
0.16
0.12 0.17 0.22
0.15
8°
0°
0.4
0.07
0.08
1.40
1.40
0.4 0.5 0.6
1.0
Min
Reference Dimension in Millimeters
Symbol
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
SH7280 Group, SH7243 Group
Appendix
Figure C.4 FP-176AV
Page 1713 of 1778
A
Appendix
Page 1714 of 1778
SH7280 Group, SH7243 Group
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Main Revisions and Additions in this Edition
Item
Page
Revision (See Manual for Details)
Table 1.1 SH7286, SH7285,
and SH7243 Features
2 to 8 Amended
Items
CPU
Bus state
controller (BSC)
Specification
:
•
Five-stage pipeline
•
Harvard architecture
•
The following features settable for each area independently
⎯
Supports both ...
⎯
Bus size (8, ...
⎯
Number of ...
⎯
Idle wait ...
⎯
Direct connection to SRAM, SRAM interface with byte
selection, SDRAM burst ROM (clock synchronous or
asynchronous) is achieved by specifying the memory to
be connected to each area. Address/data multiplex I/O
(MPX-I/O) interface is also supported.
Port output
•
enable 2 (POE2)
Power supply
voltage
Figure 1.1 Block Diagram
(SH7243), Figure 1.2 Block
Diagram (SH7285, SH7286)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
9, 10
•
High-impedance control of high-current pins at a falling edge
or low-level input on the POE pin
VCC: 3.0 to 5.5 V, AVCC: 4.5 to 5.5 V
DrVCC:
3.0 to 3.6 V (when USB is used)
3.0 to 5.5 V (when USB is not used)
Added
Page 1715 of 1778
Item
Page
Revision (See Manual for Details)
Table 1.2 Pin Functions
16 to
19
Amended
Classification
Symbol
Function
Bus control
WRHH
Indicates a write access to bits 31 to 24 of
data of external memory or device (only in
SH7286).
WRHL
Indicates a write access to bits 23 to 16 of
data of external memory or device (only in
SH7286).
Figure 2.6 Transitions
between Processing States
61
WRH
Indicates a write access to bits 15 to 8 of
data of external memory or device.
WRL
Indicates a write access to bits 7 to 0 of data
of external memory or device.
Multi-function timer
pulse unit 2 (MTU2)
TIOC4A,
The TGRA_4 to TGRD_4 input capture
TIOC4B,
TIOC4C,
TIOC4D
input/output compare output/PWM output
pins.
Multi-function timer
pulse unit 2S (MTU2S)
TIOC4AS,
The TGRA_4S to TGRD_4S input capture
TIOC4BS,
TIOC4CS,
TIOC4DS
input/output compare output/PWM output
pins.
Synchronous serial
communication unit
(SSU)(only in SH7285
and SH7286)
SCS
Chip select input/output pin.
Amended
Manual reset from any processing state
except software standby mode
Power-on reset from any state
Manual reset state
Power-on reset state
Reset state
Reset canceled
Exception
handling state
Interrupt source or
DMA address error occurs
Bus request
cleared
Bus request
generated
Exception
handling
source
occurs
Bus-released state
Bus request
generated
Bus request
generated
Bus request
cleared
Sleep mode
Exception
handling
ends
Power-on reset
Bus request
cleared
Program execution state
STBY bit cleared
for SLEEP
instruction
STBY bit set
for SLEEP
instruction
Software standby mode
Power-down state
3.1 Selection of Operating
Modes
Page 1716 of 1778
63
Amended
For the on-chip flash memory programming mode, boot
mode, user boot mode, user program mode, and USB boot
mode (only in SH7285 and SH7286) which are on-chip
programming modes are available.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table 3.1 Selection of
Operating Modes
63
Amended
Mode No.
Mode 7
Notes:
*1*2*3
…
4. If FWE = 0 starting from power-on and until
power-on reset has been released, and if FWE
= 1 when the MCU operation has been set to
single-chip mode, transition to the user program
mode is executed in a single chip state.
3.3.3 Mode 2 (MCU
Extension Mode 2)
64
3.4 Address Map
65 to
71
4.1 Features
Added
In this mode, the on-chip ROM (flash memory) is active and
CS0 space can be used in this mode.
Amended
On-chip ROM → On-chip flash memory)
75, 76 Amended
(6) Frequency Control Register (FRQCR)
The frequency control register (FRQCR) has control
bits assigned for the following functions: clock
output/non-output from the CK pin during software
standby mode, and the frequency division ratios of the
internal clock (Iφ), bus clock (Bφ), and peripheral clock
(Pφ).
(7) MTU2S Clock Frequency Control Register (MCLKCR)
The MTU2S clock frequency control register
(MCLKCR) has control bits assigned for the following
functions: MTU2S clock (Mφ) output/non-output and
the frequency division ratio of the MTU2S clock (Mφ).
(8) AD Clock Frequency Control Register (ACLKCR)
The AD clock frequency control register (ACLKCR) has
control bits assigned for the following functions: AD
clock (Aφ) output/non-output and the frequency division
ratio of the AD clock (Aφ).
4.3 Clock Operating Modes
78
Added
Table 4.3 shows examples of the ranges of the frequency
division ratios that can be specified with FRQCR.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1717 of 1778
Item
Page
Revision (See Manual for Details)
Table 4.3 Clock Operating
Modes and Settable
Frequency Range Examples
79, 80 The table title amended
Added
Notes:
…
7. When using the MTU2S, the MTU2S clock (Mφ)
frequency must not exceed the internal clock
(Iφ) frequency and also be equal to or higher
than Pφ and Bφ. The MTU2S clock ...
4.4.1 Frequency Control
Register (FRQCR)
81
Amended
FRQCR is a 16-bit readable/writable register used to
specify the frequency division ratios for the internal clock
(Iφ), bus clock (Bφ), and peripheral clock (Pφ). FRQCR can
be accessed only in word units. After setting FRQCR to a
new value, read it to confirm that it actually holds the new
value, then execute NOP instructions for 32 cycles of Pφ.
FRQCR should be modified by a program in the on-chip
ROM or on-chip RAM. Additionally, make settings for
individual modules after setting FRQCR*.
FRQCR is initialized to H'0333 ...
When switching the division ratio of bus clock frequency,
the CK pin is fixed at low level for a cycle of an input clock
so as to prevent a hazard of switching.
Note: *
4.4.2 MTU2S Clock
Frequency Control Register
(MCLKCR)
84
A register that is initialized in software standby
mode is also initialized when the FRQCR setting
is changed.
Amended
Bit:
Initial value:
R/W:
7
6
5
4
3
2
-
-
-
-
-
-
MSDIVS[1:0]
0
R
1
R
0
R
0
R
0
R
0
R
1
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
1
0
1
R/W
This bit is always read as 0. The write value
should always be 0.
6
⎯
1
R
Reserved
This bit is always read as 1. The write value
should always be 1.
5 to 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write
value should always be 0.
Page 1718 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
4.4.3 AD Clock Frequency
Control Register (ACLKCR)
85
Amended
Bit:
Initial value:
R/W:
7
6
5
4
3
2
-
-
-
-
-
-
ASDIVS[1:0]
0
R
1
R
0
R
0
R
0
R
0
R
1
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
⎯
0
R
Reserved
1
0
1
R/W
This bit is always read as 0. The write value
should always be 0.
6
⎯
1
R
Reserved
This bit is always read as 1. The write value
should always be 1.
4.5 Changing the Frequency
87
Amended
Selecting division ratios for the frequency divider can
change the frequencies of the internal clock, bus clock,
peripheral clock, MTU2S clock, and AD clock under the
software control through the frequency control register
(FRQCR), MTU2S clock frequency control register
(MCKCR), and AD clock frequency control register
(ACLKCR). The following describes how to specify the
frequencies.
4.7 Oscillation Stop Detection 90
Added
... In addition, the high-current ports (multiplexed pins to
which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D
signals in the MTU2, the TIOC3BS, TIOC3DS, and
TIOC4AS to TIOC4DS in the MTU2S are assigned) can be
placed in high-impedance state regardless of the OSCERS
bit and PFC settings. For details, refer to appendix A, Pin
States.
Figure 4.5 Example of
Connecting a Ceramic
Resonator
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
91
Amended
Ceramic resonator: CSTCW48M0X11***-R0
(Murata Manufacturing Co., Ltd.)
Contact your Renesas Electronics sales agency for details
of Rf and Rd values.
Ta = 0 to +70°C
Page 1719 of 1778
Item
Page
(2) Exception Handling
98
Triggered by Address Errors,
Register Bank Errors,
Interrupts, and Instructions
Table 5.6 Bus Cycles and
Address Errors
105
Revision (See Manual for Details)
Amended
In the case of interrupt exception handling other than NMI
or UBC with usage of the register banks enabled, general
registers R0 to R14, control register GBR, system registers
MACH, MACL, and PR, and the vector table address offset
of the interrupt exception handling to be executed are
saved to the register banks.
Added
Bus Cycle
Type
Data
read/write
Bus
Master
Address
Bus Cycle Description Errors
CPU,
DMAC,
or DTC
Double longword data
None (normal)
accessed from a double
longword boundary
Double longword data
Address error
accessed from other
occurs
than a double longword
boundary
5.5.3 Interrupt Exception
Handling
110
Amended
In the case of interrupt exception handling other than NMI
or UBC with usage of the register banks enabled, general
registers R0 to R14, control register GBR, system registers
MACH, MACL, and PR, and the vector table address offset
of the interrupt exception handling to be executed are
saved in the register banks.
Table 5.11 Stack Status After 116
Exception Handling Ends
Amended
Exception Type
Integer division instruction
(division by zero, overflow)
5.9.4 Note When Changing
Interrupt Mask Level of
Status Register (SR) in CPU
117
Added
Figure 6.1 Block Diagram of
INTC
120
Deleted
Page 1720 of 1778
ICR2
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table 6.2 Register
Configuration
122
Deleted
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Register Name
Access Size
Interrupt control register 0
16, 32
Interrupt control register 1
16, 32
IRQ interrupt request register
16, 32
Bank control register
16, 32
Bank number register
16, 32
Interrupt priority register 01
16, 32
Interrupt priority register 02
16, 32
Interrupt priority register 05
16, 32
Interrupt priority register 06
16, 32
Interrupt priority register 07
16, 32
Interrupt priority register 08
16, 32
Interrupt priority register 09
16, 32
Interrupt priority register 10
16, 32
Interrupt priority register 11
16, 32
Interrupt priority register 12
16, 32
Interrupt priority register 13
16, 32
Interrupt priority register 14
16, 32
Interrupt priority register 15
16, 32
Interrupt priority register 16
16, 32
Interrupt priority register 17
16, 32
Interrupt priority register 18
USB-DTC transfer interrupt request register
16, 32
16, 32
Page 1721 of 1778
Item
Page
Revision (See Manual for Details)
Table 6.3 Interrupt Request
Sources and IPR01, IPR02,
and IPR05 to IPR18
123,
124
Amended
6.3.3 Interrupt Control
Register 1 (ICR1)
126
6.3.4 IRQ Interrupt Request
Register (IRQRR)
128
Register
Name
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
Interrupt
MTU2_0
MTU2_0
MTU2_1
MTU2_1
priority
register 09
(TGIA_0 to
TGID_0)
(TCIV_0,
TGIE_0,
TGIF_0)
(TGIA_1,
TGIB_1)
(TCIV_1,
TCIU_1)
Interrupt
MTU2_2
MTU2_2
MTU2_3
priority
register 10
(TGIA_2,
TGIB_2)
(TCIV_2,
TCIU_2)
(TGIA_3 to
TGID_3)
MTU2_3
(TCIV_3)
Interrupt
priority
register 11
MTU2_4
(TGIA_4 to
TGID_4)
MTU2_4
(TCIV_4)
MTU2_5
(TGIU_5,
TGIV_5,
TGIW_5)
POE2
(OEI1, OEI2)
Interrupt
MTU2S_3
(TGIA_3 to
TGID_3)
MTU2S_3
(TCIV_3)
MTU2S_4
priority
register 12
MTU2S_4
(TCIV_4)
Interrupt
MTU5S
Reserved
(TGIU_5,
TGIV_5,
TGIW_5)
POE2
(OEI3)
IIC3*1
priority
register 13
Interrupt
priority
register 18
USB*1
(USI0, USI1)
RCAN_ET*2
EP1-FIFO full
DTC transfer
end*1
(USBRXI)
EP2-FIFO
empty DTC
transfer end*1
(USBTXI)
(TGIA_4 to
TGID_4)
Table note added
Note: When the detecting condition of the IRQn input is
changed, the IRQnF flag in IRQRR is cleared to 0.
Added
Initial
Bit
Bit Name
Value
R/W
7
IRQ7F
0
R/(W)* IRQ Interrupt Request
Description
6
IRQ6F
0
R/(W)*
5
IRQ5F
0
[Clearing conditions]
R/(W)* • Cleared by reading IRQnF while IRQnF =
4
IRQ4F
0
R/(W)*
...
1, then writing 0 to IRQnF
• Cleared by executing IRQn interrupt
3
IRQ3F
0
R/(W)*
2
IRQ2F
0
R/(W)*
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
exception handling
• Cleared when DTC is activated by the
IRQn interrupt, then the DISEL bit in MRB
of DTC is set to 0
• Cleared when the setting of IRQn1S or
IRQn0S of ICR1 is changed
1: IRQn interrupt request is detected
...
Page 1722 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
6.4.1 NMI Interrupt
133
Amended
Note that during a reset and after the reset has been
canceled, the NMI pin should be fixed high for 3 tcyc.
6.4.4 IRQ Interrupts
134
Added
The IRQnF bit will be set when the setting condition is
satisfied regardless of the setting of the I3 to I0 bits in SR.
Table 6.4 Interrupt Exception 139 to Amended
Handling Vectors and
142
Interrupt Source Number
Priorities
USB
EP1-FIFO full DTC transfer end
(USBRXI)
EP2-FIFO empty DTC transfer end
(USBTXI)
MTU2
MTU2S
MTU2_0
TGIA_0
MTU2_1
TGIA_1
MTU2_2
TGIA_2
MTU2_3
TGIA_3
MTU2_4
TGIA_4
MTU2_5
TGIU_5
MTU2S_3
TGIA_3S
TGIB_3S
TGIC_3S
TGID_3S
TCIV_3S
MTU2S_4
TGIA_4S
TGIB_4S
TGIC_4S
TGID_4S
TCIV_4S
MTU2S_5
TGIU_5S
TGIV_5S
TGIW_5S
6.9.3 Handling Interrupt
162
Request Signals as DTC
Activating Sources but Not as
CPU Interrupt Sources or
DMAC Activating Sources
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Added
5. However, when the transfer counter value is 0, the
DTCE bit is cleared to 0 and interrupt requests are sent
to the CPU. The activating source is not cleared here.
6. The CPU clears the interrupt source and performs the
necessary termination processing in the interrupt
exception handling routine.
Page 1723 of 1778
Item
Page
6.10.2 In Case the NMI Pin is 163,
not in Use
164
Revision (See Manual for Details)
Added
to
6.10.4 Notes on Canceling
Software Standby Mode with
an IRQx Interrupt Request
7.5 Interrupt Source
195
Added
8.1 Features
198
Amended
Note: *
Table 8.2 Interrupt Sources,
DTC Vector Addresses, and
Corresponding DTCEs
When the transfer information is stored in the
on-chip RAM, the RAME bit in SYSCR1 must be
set to 1.
212 to Amended
214
Origin of Activation
Source
Activation Source
USB
EP1-FIFO full transfer request
(USBRXI)
EP2-FIFO empty transfer request
(USBTXI)
MTU2S_CH3
TGIA_3S
TGIB_3S
TGIC_3S
TGID_3S
MTU2S_CH4
TGIA_4S
TGIB_4S
TGIC_4S
TGID_4S
TCIV_4S
MTU2S_CH5
TGIU_5S
TGIV_5S
TGIW_5S
Page 1724 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Table 8.10 Number of Cycles 231
Required for Each Execution
State
Revision (See Manual for Details)
Amended
Object to be
Accessed
On-
On-Chip
Chip
RAM*1
Flash
Memory
On-Chip I/O
Registers
External Device*5
Bus width
32 bits
32 bits
16 bits
8 bits
16 bits 32 bits
Access cycles
1Bφ to
3Bφ*1*2
3Bφ to 4Iφ 2Pφ
+ 3Bφ*2
2Pφ
2Bφ
2Bφ
2Bφ
Exe-
1Bφ to
3Bφ*1*2
3Bφ to 4Iφ ⎯
+ 3Bφ*2
⎯
9Bφ
5Bφ
3Bφ
Vector
cution read SI
status
8 bits*
4
Notes: 1. Values for on-chip RAM. Number of cycles
varies depending on the ratio of Iφ:Bφ.
2. Values for on-chip flash memory. Number of
cycles varies depending on the ratio of Iφ:Bφ.
8.5.9 DTC Bus Release
Timing
232
Table 8.11 DTC Bus Release 233
Timing
Amended
The DTC requests the bus mastership of the internal bus (I
bus) to the bus arbiter when an activation request occurs.
The DTC releases the bus after a vector read, NOP
execution after vector read, transfer information read, a
single data transfer, or transfer information write-back.
Amended
Bus Function Extending Register
(BSCEHR) Setting
DTLOCK
DTBST
1
0
1
2
1
0
Setting 2*
Setting 3*
Notes: 1. The following restrictions apply to setting 2.
• The clock setting through the frequency control
register (FROCR) must be Iφ : Bφ : Pφ : Mφ : Aφ
= 8 : 4 : 4 : 8 : 4 or 8 : 4 : 4 : 4 : 4.
• The vector information must be stored in the
on-chip flash memory or RAM.
• The transfer information must be stored in the
on-chip RAM.
• Transfer must be between the on-chip RAM
and an on-chip peripheral module or between
the external memory and an on-chip peripheral
module.
2. The following restriction applies to setting 3.
• Use the DTPR bit in BSCEHR with this bit set to
0. Setting this bit to 1 is prohibited.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1725 of 1778
Item
Page
8.5.10 DTC Activation Priority 235
Order
Revision (See Manual for Details)
Added
If multiple DTC activation requests are generated while the
DTC is inactive, whether to start the DTC transfer from the
first activation request* or according ...
Note: *
Figure 8.17 Example of DTC 236
Activation According to
Priority
When one DTC-activation request is generated
before another, transfer starts with the first
request. When an activation request with a
higher priority is generated before a pending
DTC request is accepted, transfer starts for the
request with higher priority. Timing of DTC
request generation varies according to the
operating state of internal buses.
Added
(1) DTPR = 0
DTC is active
DTC is inactive
Transfer is started for the first activation request
Internal bus
Other than DTC
DTC
(request 3)
DTC request
Transfer is performed according to the priority
DTC
(request 1)
DTC
(request 2)
Priority
determination
(2) DTPR = 1
DTC is inactive
DTC is active
Transfer is started according to the priority
Internal bus
DTC request
8.9.1 Module Standby Mode
Setting
241
8.9.4 Chain Transfer
241
Other than DTC
DTC
(request 1)
Transfer is performed according to the priority
DTC
(request 2)
DTC
(request 3)
Priority
determination
Amended
Operation of the DTC can be disabled or enabled using the
standby control register. The initial setting is for operation
of the DTC to be enabled.
Amended
When chain transfer is used, clearing of the activation
source or DTCER is performed when the last of the chain
of data transfers is executed. SCI, SSU, RCAN-ET, SCIF,
IIC3, USB, and A/D converter interrupt/activation sources,
on the other hand, are cleared when the DTC reads from or
writes to the relevant register when the last of the chain of
data transfers is executed.
Page 1726 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
8.9.13 Note on Writing to
DTCER
243
Added
Section 9 Bus State
Controller (BSC)
All
Amended
WEn → WRxx
WEn → WRxx
Table 9.1 Pin Configuration
248,
249
Amended
Name
WRHH/DQMUU
WRHL/DQMUL
WRH/DQMLU
WRL/DQMLL
9.3.2 Setting Operating
Modes
253
9.4.2 CSn Space Bus Control 263
Register (CSnBCR) (n = 0 to
7)
Amended
Although BS, RD/WR, WRxx, and other pins are shown in
the examples of access waveforms in this section, ...
Amended
Bit
10, 9
Description
Data Bus Width Specification
:
Notes: ...
3. If area 2 or area 3 is specified as SDRAM
space, the bus width can be specified as 16
bits or 32 bits.
9.4.8 Bus Function Extending 302
Register (BSCEHR)
Amended
Bit
Description
11
DTC Burst Enable
:
Notes: ...
1. Clock setting through the frequency control
register (FRQCR) must be Iφ : Bφ : Pφ : Mφ
: Aφ = 8 : 4 : 4 : 8 : 4 or 8 : 4 : 4 : 4 : 4.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1727 of 1778
Item
Page
9.4.8 Bus Function Extending 303
Register (BSCEHR)
Revision (See Manual for Details)
Amended
Bit
Description
8
DTC Activation Priority
:
For details, see section 8.5.10, DTC Activation Priority
Order.
:
Notes: ...
4. Set this bit to 1 while DTLOCK = 0. The
DTLOCK bit should not be set to 1.
Figure 9.2 Normal Space
310
Basic Access Timing (Access
Wait 0)
Amended
WEn → WRH, WRL
Figure 9.3 Continuous
311
Access for Normal Space 1
Bus Width = 16 Bits,
Longword Access,
CSnWCR.WM Bit = 0
(Access Wait = 0, Cycle Wait
= 0)
Figure 9.4 Continuous
312
Access for Normal Space 2
Bus Width = 16 Bits,
Longword Access,
CSnWCR.WM Bit = 1
(Access Wait = 0, Cycle Wait
= 0)
Figure 9.5 Example of 32-Bit 313
Data-Width SRAM
Connection (Only SH7286)
Amended
WE3 → WRHH
WE2 → WRHL
WE1 → WRH
WE0 → WRL
Figure 9.7 Example of 8-Bit
Data-Width SRAM
Connection
314
Figure 9.8 Wait Timing for
Normal Space Access
(Software Wait Only)
315
Page 1728 of 1778
Amended
WE0 → WRL
Amended
WEn → WRH, WRL
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Figure 9.9 Wait Cycle Timing 316
for Normal Space Access
(Wait Cycle Insertion Using
WAIT Signal)
Figure 9.10 CSn Assert
Period Expansion
317
Figure 9.11 Access Timing
for MPX Space (Address
Cycle No Wait, Data Cycle
No Wait)
319
Figure 9.12 Access Timing
for MPX Space (Address
Cycle Wait 1, Data Cycle No
Wait)
320
Figure 9.13 Access Timing
for MPX Space (Address
Cycle Access Wait 1, Data
Cycle Wait 1, External Wait
1)
321
Figure 9.14 Example of 32Bit Data Width SDRAM
Connection
(RASU and CASU are Not
Used)
323
Revision (See Manual for Details)
Amended
WEn → WRH, WRL
The figure title amended
SRAM → SDRAM
Pin in the figure amended
CKIO → CK
Figure 9.15 Example of 16324
Bit Data Width SDRAM
Connection
(RASU and CASU are Used)
(2) Address Multiplexing
325
Amended
Do not specify those bits in the manner other than this
table, otherwise the operation of this LSI is not guaranteed.
A25 to A18 are not multiplexed and the original values of
address are always output at these pins.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1729 of 1778
Item
Page
Revision (See Manual for Details)
Table 9.11 Relationship
between BSZ[1:0],
A2/3ROW[1:0],
A2/3COL[1:0], and Address
Multiplex Output (1)-1
326 to Added
330
to
Table 9.13 Relationship
between BSZ[1:0],
A2/3ROW[1:0],
A2/3COL[1:0], and Address
Multiplex Output (3)
Figure 9.22 Burst Read
345
Timing (Bank Active,
Different Bank, CAS Latency
1)
Figure 9.23 Burst Read
Timing (Bank Active, Same
Row Addresses in the Same
Bank, CAS Latency 1)
346
Figure 9.24 Burst Read
Timing (Bank Active,
Different Row Addresses in
the Same Bank, CAS
Latency 1)
347
Figure 9.25 Single Write
Timing (Bank Active,
Different Bank)
348
Figure 9.26 Single Write
Timing (Bank Active, Same
Row Addresses in the Same
Bank)
349
Figure 9.27 Single Write
Timing (Bank Active,
Different Row Addresses in
the Same Bank)
350
(13) Low-Power SDRAM
361
Amended
CS3 → CSn
Added
However, since addresses written to this LSI are output
without change, set data in accord with the EMRS
specifications for the given SDRAM area.
Page 1730 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table 9.20 Relationship
between Bus Width, Access
Size, and Number of Bursts
365
Amended
Figure 9.36 Basic Access
Timing for SRAM with Byte
Selection (BAS = 0)
368
Figure 9.37 Basic Access
Timing for SRAM with Byte
Selection (BAS = 1)
369
Figure 9.38 Wait Timing for
SRAM with Byte Selection
(BAS = 1) (SW[1:0] = 01,
WR[3:0] = 0001, HW[1:0] =
01)
370
9.5.9 Burst ROM (Clock
Synchronous) Interface
372
Table 9.21 Conditions for
Determining Number of Idle
Cycles
375
9.6 Interrupt Source
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Notes: 1. When the bus width ...
2. Only the DMAC is capable of transfer with 16
bytes as the unit of access. The maximum unit
of access for the DTC and CPU is 32 bits.
Amended
WEn → WRH, WRL
Deleted
These invalid data read cycles increase the memory
access time and degrade the program execution speed and
DMA transfer speed. To prevent this problem, using 16byte read by cache fill in the cache-enabled space or 16byte read by the DMA is recommended.
385
Amended
No.
Condition
Description
Note
(5)
Read data
transfer cycle
One idle cycle is
inserted after a read
access is completed.
This idle cycle is not
generated for the first
or middle cycles in
divided access cycles.
This is neither
generated when the
WM[1:0] bits in
CSnWCR are not B'00.
One idle cycle is
always generated after
a read cycle with
SDRAM interface.
Added
Page 1731 of 1778
Item
Page
Revision (See Manual for Details)
10.1 Features
387
Amended
• Number of channels selectable: Eight channels
(channels 0 to 7) max.
CH0 to CH2 channels (SH7285, SH7243) and CH0 to
CH3 channels (SH7286) can only receive external
requests.
10.3.8 DMA Operation
Register (DMAOR)
409
Table 10.4 DMARS Settings
414
Deleted
Note: * Only 0 can be written to clear the flag after 1 is
read.
Amended
Peripheral Module
USB
USBRXI
USBTXI
RCAN_ET
RM0_0
SSU
SSTXI
SSRXI
SCIF_3
TXI3
RXI3
IIC3
TXI
RXI
Page 1732 of 1778
A/D converter_0
ADI0
MTU2_0
TGIA_0
MTU2_1
TGIA_1
MTU2_2
TGIA_2
MTU2_3
TGIA_3
MTU2_4
TGIA_4
CMT_0
CMI0
CMT_1
CMI0
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
(3) On-Chip Peripheral
Module Request
419
Amended
DMA transfer request signals from on-chip peripheral
modules to the DMAC include transmit data empty and
receive data full requests from the SCIF, A/D conversion
end transfer request from the A/D converter, compare
match transfer request from the CMT, and data transfer
requests from the IIC3, MTU2, RCAN_ET, SSU, and USB.
:
... When the IIC3 transmit is selected as the transfer
request, the transfer destination must be ICDRT; when the
IIC3 reception is selected as the transfer request, the
transfer source must be ICDRR. When the USB is selected
as the transfer request, the transfer destination must be the
USBEP2 data register (USBEPDR2). When the SSU is
selected as the transfer request, the transfer destination
must be an SS transmit data register (SSTDR0 to
SSTDR3).
Table 10.8 Selecting On-Chip 420
Peripheral Module Request
Modes with RS3 to RS0 Bits
Figure 10.6 Example of DMA 426
Transfer Timing in Dual Mode
(Transfer Source: Normal
Memory, Transfer
Destination: Normal Memory)
Amended
DMA Transfer Request
Source
DMA Transfer Request Signal
USB receive
EP1 FIFO full transfer request
(USBRXI)
USB transmit
EP2 FIFO empty transfer request
(USBTXI)
MTU2_0
TGIA_0
MTU2_1
TGIA_1
MTU2_2
TGIA_2
MTU2_3
TGIA_3
MTU2_4
TGIA_4
Amended
WEn → WRxx
Figure 10.8 Example of DMA 428
Transfer Timing in Single
Address Mode
Figure 10.18 BSC Normal
Memory Access (No Wait,
Idle Cycle 1, Longword
Access to 16-Bit Device)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
436
Page 1733 of 1778
Item
Page
Revision (See Manual for Details)
10.5 Interrupt Sources
437,
438
Added
10.6.3 CHCR Setting
to
10.6.7 Number of On-Chip
RAM Access Cycles from
DMAC
439,
440
Added
11.1 Features
441
Added
• Dead time compensation counter available in channel 5
• External pulse width measurement available in channel
5
Table 11.1 MTU2 Functions
443
11.3.5 Timer Interrupt Enable 483
Register (TIER)
• TIER_5
Amended
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
External
pulse
width
measurement
⎯
⎯
⎯
⎯
⎯
√
Amended
Bit
Bit Name
Initial
Value
R/W
Description
2
TGIE5U
0
R/W
TGR Interrupt Enable 5U
Enables or disables interrupt requests
(TGIU_5) by the CMFU5 bit when the CMFU5
bit in TSR_5 is set to 1.
:
1
TGIE5V
0
R/W
TGR Interrupt Enable 5V
Enables or disables interrupt requests
(TGIV_5) by the CMFV5 bit when the CMFV5
bit in TSR_5 is set to 1.
:
0
TGIE5W
0
R/W
TGR Interrupt Enable 5W
Enables or disables interrupt requests
(TGIU_5) by the CMFW5 bit when the CMFW5
bit in TSR_5 is set to 1.
:
11.3.9 Timer Synchronous
Clear Register S (TSYCRS)
Page 1734 of 1778
494
Amended
TSYCRS is an 8-bit readable/writable register that specifies
conditions for clearing TCNT_3 and TCNT_4 in the MTU2S
in synchronization with the MTU2. The MTU2S has one
TSYCRS in channel 3 but the MTU2 has no TSYCRS.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table 11.38 TIOC3B Output
Level Select Function
516
The table title amended
11.3.23 Timer Gate Control
Register (TGCR)
518
Added
11.3.32 Timer Waveform
Control Register (TWCR)
529
Note: When the BDC bit is set to 1 in the MTU2S, do not
set the FB bit to 0.
Amended
Bit
Description
0
Initial Output Suppression Enable
Selects the waveform output when synchronous counter clearing
occurs in complementary PWM mode. The initial output is
suppressed only when synchronous clearing occurs within the Tb
interval at the trough in complementary PWM mode. When
synchronous clearing occurs outside this interval, the initial value
specified in TOCR is output regardless of the WRE bit setting.
The initial value is also output when synchronous clearing occurs
in the Tb interval at the trough immediately after TCNT_3 and
TCNT_4 start operation.
For the Tb interval at the trough in complementary PWM mode,
see figure 11.40.
0: Outputs the initial value specified in TOCR
1: Suppresses initial output
[Setting condition]
•
Figure 11.41 Example of
572
Operation without Dead Time
When 1 is written to WRE after reading WRE = 0
Amended
Compare register TGRA_4
(k) Complementary PWM
Mode 0% and 100% Duty
Output
580
(2) MTU2S Counter Clearing 617
Caused by MTU2 Flag
Setting Source (MTU2MTU2S Synchronous
Counter Clearing)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Text is moved before figure 11.49.
Amended
The MTU2S counters can be cleared by sources for setting
the flags in TSR_0 to TSR_2 in the MTU2 through the
TSYCRS settings in the MTU2S.
Page 1735 of 1778
Item
Page
Revision (See Manual for Details)
Figure 11.85 Example of
Procedure for Specifying
MTU2S Counter Clearing by
MTU2 Flag Setting Source
617
Amended
Figure 11.86 (1) Example of
MTU2S Counter Clearing
Caused by MTU2 Flag
Setting Source (1)
618
Figure 11.86 (2) Example of
MTU2S Counter Clearing
Caused by MTU2 Flag
Setting Source (2)
618
Figure 11.88 Example of
External Pulse Width
Measurement (Measuring
High Pulse Width)
619
TSYCR_3 → TSYCRS
Amended
Pφ
TIC5U
TCNTU_5
11.7.23 Note on Output
Waveform Control at
Synchronous Counter
Clearing in Complementary
PWM Mode
658,
659
Added
Table 12.3 Register
Configuration
698,
699
Added
Register Name
Abbreviation
R/W
Timer synchronous clear register S*
TSYCRS
R/W
Note: * For detailed register descriptions, refer to section
11.3.9, Timer Synchronous Clear Register S
(TSYCRS), and figure 11.85 in section 11, MultiFunction Timer Pulse Unit 2 (MTU2).
Table 13.2 Pin Combinations 704
Amended
Pin Combination
PE9/TIOC3B and PE11/TIOC3D
PE12/TIOC4A and PE14/TIOC4C
PE13/TIOC4B and PE15/TIOC4D
Page 1736 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Figure 14.1 Block Diagram of 733
CMT
Revision (See Manual for Details)
Amended
Pφ/32
Pφ/128
Pφ/512
Clock selection
Channel 1
Bus
interface
Peripheral bus
Table 14.2 Interrupt Sources 740
Added
Figure 15.1 Block Diagram of 746
WDT
Amended
Bus interface
Peripheral bus
15.3.2 Watchdog Timer
Control/Status Register
(WTCSR)
749
15.4.2 Using Watchdog
Timer Mode
756
15.5 Interrupt Source
759
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Added
WTCSR is initialized to H'18 by a power-on reset caused
by the RES pin, an internal reset caused by the WDT, or in
software standby mode.
Added
7.
Since WTCSR is initialized by an internal reset caused
by the WDT, the TME bit in WTCSR is cleared to 0.
This makes the counter stop (be initialized). To use the
WDT in watchdog timer mode again, after clearing the
WOVF flag in WRCSR, set watchdog timer mode
again.
Added
Page 1737 of 1778
Item
Page
Revision (See Manual for Details)
15.6.4 Manual Reset in
Watchdog Timer Mode
761
Amended
When a manual reset occurs in watchdog timer mode, the
intermal bus (I bus) cycle is continued. If a manual reset
occurs while the bus is released or during DMAC burst
transfer, manual reset exception handling will be pended
until the CPU acquires the bus mastership.
However, if the duration from generation of the manual
reset to the bus cycle end is equal to or longer than the
duration of the internal manual reset activated, the
occurrence of the internal manual reset source is ignored
instead of being pended, and the manual reset exception
handling is not executed.
15.6.5 Connection of the
WDTOVF Pin
761
Amended
Bus interface
Figure 16.1 Block Diagram of 764
SCI
Added
Peripheral bus
SCBRR
Baud rate
generator
Table 16.2 Register
Configuration
766,
767
Amended
Channel
Register Name
Abbreviation
R/W
Initial
Value
0
Transmit data register_0
SCTDR_0
R/W
⎯
Serial port register_0
SCSPTR_0
R/W
H'0x
1
Transmit data register_1
SCTDR_1
R/W
⎯
(only for SH7286
and SH7285)
Receive data register_1
SCRDR_1
R
⎯
Serial port register_1
SCSPTR_1
R/W
H'0x
Transmit data register_2
SCTDR_2
R/W
⎯
Receive data register_2
SCRDR_2
R
⎯
Serial port register_2
SCSPTR_2
R/W
H'0x
4
Transmit data register_4
SCTDR_4
R/W
⎯
(only for SH7286
and SH7285)
Receive data register_4
SCRDR_4
R
⎯
2
Page 1738 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
16.3.2 Receive Data Register 767
(SCRDR)
16.3.4 Transmit Data
Register (SCTDR)
768
Revision (See Manual for Details)
Amended
Bit:
7
6
5
4
3
2
1
0
Initial value:
R/W:
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Amended
Bit:
Initial value:
R/W: R/W
16.3.7 Serial Status Register 775 to Amended
(SCSSR)
780
Bit
Description
7
:
[Setting conditions]
•
6
By a power-on reset or in module standby mode
:
[Clearing conditions]
•
5
By a power-on reset or in module standby mode
:
[Clearing conditions]
•
4
By a power-on reset or in module standby mode
:
[Clearing conditions]
•
3
By a power-on reset or in module standby mode
:
[Clearing conditions]
•
2
By a power-on reset or in module standby mode
:
[Setting conditions]
•
16.3.8 Serial Port Register
(SCSPTR)
781,
782
By a power-on reset or in module standby mode
Amended
Bit:
7
6
5
4
EIO
-
-
-
Initial value: 0
R/W: R/W
0
-
0
-
0
-
3
2
SPB1IO SPB1DT
0
R/W
W
1
0
-
SPB0DT
0
1
W
-
Bit
Bit Name
Initial
Value
R/W
Description
2
SPB1DT
Undefined
W
Clock Port Data in Serial Port
Specifies the data output through ...
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1739 of 1778
Item
Page
Revision (See Manual for Details)
Figure 16.4 Sample
Flowchart for Transmitting
Serial Data
801
Deleted
Break output?
No
Yes
Clear SPB0DT bit to 0
and set SPB0IO to 1
Clear TE bit in SCSCR to 0
End of transmission
(2) Clock
809
Added
When the SCI operates on an internal clock, it outputs the
clock signal at the SCK pin.
Eight clock pulses are output per transmitted or received
character. When the SCI is not transmitting or receiving,
the clock signal remains in the high state. However, in
reception-only operation, the synchronizing clock is output
until an overrun error occurs or the RE bit is cleared to 0. In
operations for the reception of n characters, select the
external clock as the clock source for the SCI. If the internal
clock is to be used instead, set both the RE and TE bits to
1, and then transmit n characters of dummy data during
reception of the n characters to be received.
Figure 16.12 Sample
Flowchart for Receiving
Serial Data (1)
813
Amended
Yes
Read the receive data in
SCRDR and clear RDRF flag
in SCSSR to 0
Figure 16.14 Sample
816
Flowchart for
Transmitting/Receiving Serial
Data
Page 1740 of 1778
Added
[5] Serial transmission/reception end procedure:
To finish serial transmission/reception, clear the TE
and RE bits in SCSCR to 0 simultaneously.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
16.5 SCI Interrupt Sources
and DTC
823
Amended
When the ORER, FER, or PER flag in SCSSR is set to 1,
an ERI interrupt request is generated. This request cannot
be used to activate the DTC. In processing for data
reception, generation of ERI interrupt requests can only be
enabled if generation of RXI interrupt requests is disabled.
In this case, set the RIE bit and the EIO bit in SCSPTR to
1. However, note that the DMAC or DTC will not transfer
received data since RXI interrupt requests are not
generated while the EIO bit is set to 1.
Amended
Bus interface
Figure 17.1 Block Diagram of 832
SCIF
Peripheral bus
SCBRR
Baud rate
generator
Table 17.2 Register
Configuration
834
17.3.7 Serial Status Register 851
(SCFSR)
Amended
Channel
Register Name
Abbreviation
R/W
Initial
Value
3
Serial port register_3
SCSPTR_3
R/W
H'00xx
Amended
Bit
Bit Name
Initial
Value
R/W
Description
0
DR
0
R/(W)*
Receive Data Ready
:
[Clearing conditions]
• DR is cleared to 0 when the chip
undergoes a power-on reset
• DR is cleared to 0 when all receive data
are read after 1 is read from DR and then
0 is written.
• DR is cleared to 0 when all receive data
in SCFRDR are read by the DMAC or
DTC.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1741 of 1778
Item
Page
Revision (See Manual for Details)
Table 17.8 Maximum Bit
Rates with External Clock
Input
858
Amended
17.3.11 Serial Port Register
(SCSPTR)
862,
863
Pφ (MHz)
External Input Clock
(MHz)
Maximum Bit
Rate (bits/s)
50
8.0000
8000000.0
Amended
The CPU can always read and write to SCSPTR. SCSPTR
is initialized to H'00xx by a power-on reset.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
R/W: R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
-
R
0
R
R
Bit
Bit Name
Initial
Value
R/W
Description
2
SCKDT
Undefined
W
SCK Port Data
0
SCKDT
Undefined
W
-
3
2
1
0
SCKIO SCKDT SPB2IOSPB2DT
0
R/W
-
W
0
R/W
-
W
:
Serial Port Break Data
:
Figure 17.11 Sample
Flowchart for Transmitting
Serial Data
881
Figure 17.16 Sample
886
Flowchart for
Transmitting/Receiving Serial
Data
Page 1742 of 1778
Added
[1] SCIF status check and transmit data write:
Read SCFSR and check that the TDFE and TEND
flags are set to 1, then write transmit data to the
transmit FIFO data register (SCFTDR). Read 1 from
the TDFE and TEND flags, then clear these flags to 0.
Added and deleted
[1] SCIF status check and transmit data write:
Read SCFSR and check that the TDFE and TEND
flags are set to 1, then write transmit data to SCFTDR.
Read 1 from the TDFE and TEND flags, then and clear
the TDFE and TEND flags to 0. The transition of the
TDFE flag from 0 to 1 can also be identified by a TXI
interrupt.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page
Figure 18.1 Block Diagram of 894
SSU
Revision (See Manual for Details)
Amended
Module data bus
Clock
Clock
selector
Table 18.6 Communication
Modes and Pin States of
SSCK Pin
915
Bus interface
Item
Peripheral bus
Pφ
Pφ/4
Pφ/8
Pφ/16
Pφ/32
Pφ/64
Pφ/128
Pφ/256
Deleted
Register Setting
Pin State
Communication
Mode
SSUMS
MSS
SCKS
SSCK
SSU communication
0
0
0
⎯
1
Input
0
⎯
1
Output
0
⎯
1
Input
0
⎯
1
Output
mode
1
Clock synchronous
1
0
communication mode
1
[Legend]
Not used as SSU pin
⎯:
18.6.5 Note on Master
937
Transmission and Master
Reception Operations in SSU
Mode
Added
18.6.6 Note on DTC
Transfers
Added
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
937
Page 1743 of 1778
Item
Page
Figure 19.1 Block Diagram of 940
I2C Bus Interface 3
Revision (See Manual for Details)
Amended
Transfer clock
generation
circuit
ICCR2
ICMR
Peripheral bus
ICCR1
SAR
19.3.1 I2C Bus Control
Register 1 (ICCR1)
943
Amended
Bit
Description
7
I C Bus Interface 3 Enable
0: Output from SCL and SDA is disabled. (Input to SCL
and SDA enabled.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
Reception Disable
Enables or disables the next operation when TRS is 0
and ICDRR is read. In master receive mode, when
ICDRR cannot be read before the rising edge of the 8th
clock of SCL, set the RCVD bit to 1 so that data is
received in byte units. Clear this bit to 0 in other modes.
2
When receiving data in byte units with the RCVD bit set
to 1, read from ICDRR after the fall of the ninth clock.
:
19.3.4 I2C Bus Interrupt
Enable Register (ICIER)
951
Deleted
Bit
Description
4
NACK Receive Interrupt Enable
Enables or disables the NACK detection and arbitration
lost/overrun error interrupt request (NAKI) and the
overrun error (OVE set in ICSR) interrupt request (ERI)
in the clocked synchronous format when the NACKF or
AL/OVE bit in ICSR is set. NAKI can be canceled by
clearing the NACKF, AL/OVE, or NAKIE bit to 0.
0: Disables the NACK detection and arbitration
lost/overrun error interrupt request (NAKI).
1: Enables the NACK detection and arbitration
lost/overrun error interrupt request (NAKI).
Page 1744 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
19.4.2 Master Transmit
Operation
959
Deleted
19.4.8 Using the IICRST Bit
to Reset I2C Bus Interface 3
973
Added
Figure 19.20 Sample
975
Flowchart for Master Receive
Mode
Added
1.
Set the ICE bit in ICCR1 to 1. Also, set the WAIT bit in
ICMR and bits CKS[3:0] in ICCR1. (Initial setting)
[3] Dummy-read ICDDR.*1*2
:
Notes: 1. Make sure that no interrupt will be generated
during steps [1] to [3].
2. If the RCVD bit is to be set to 1 for enabling
data reception in byte units, set it before
performing the dummy read from ICDRR.
19.5 Interrupt Requests
978
Added
In such a case, an interrupt request is not sent to the CPU.
In cases other than data transfer by the DMAC or DTC,
interrupt sources should be cleared in the exception
handling.
Table 19.6 Time for
Monitoring SCL
19.8.2 Note on Master
Receive Mode
982
983
Amended
CKS[3]
CKS[2]
Time for Monitoring SCL
1
0
39 tpcyc*
1
87 tpcyc*
Amended
Reading ICDRR around the falling edge of the 8th clock
might fail to fetch the receive data.
In addition, when RCVD is set to 1 around the falling edge
of the 8th clock and the receive buffer is full, a stop
condition may not be issued.
Use the following measure against the situations above.
• In master receive mode, read ICDRR before the rising
edge of the 8th clock.
19.8.5 Access to ICE and
IICRST Bits during I2C Bus
Operations
984,
985
Added
to
19.8.8 Note on Master
Transmit Mode
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1745 of 1778
Item
Page
Revision (See Manual for Details)
20.1 Features
987
Amended
•
Twelve A/D data registers (SH7286) or eight A/D data
registers (SH7285 and SH7243)
Four 16-bit A/D data registers (ADDR) are provided.
A/D conversion results are stored in 16-bit A/D data
registers (ADDR) that correspond to the input channels.
Figure 20.1 Block Diagram of 989
A/D Converter
Impedance-conversion circuits deleted
Table 20.2 Register
Configuration
Deleted
991,
992
20.3.1 A/D Control Registers 993
0 to 2 (ADCR_0 to ADCR_2)
Register Name
Abbreviation
R/W
A/D data register 0
ADDR0
R/W
A/D data register 1
ADDR1
R/W
A/D data register 2
ADDR2
R/W
A/D data register 3
ADDR3
R/W
A/D data register 4
ADDR4
R/W
A/D data register 5
ADDR5
R/W
A/D data register 6
ADDR6
R/W
A/D data register 7
ADDR7
R/W
A/D data register 8
ADDR8
R/W
A/D data register 9
ADDR9
R/W
A/D data register 10
ADDR10
R/W
A/D data register 11
ADDR11
R/W
Deleted
Bit
Bit Name
Initial
Value
R/W
Description
7
ADST
0
R/W
A/D Start
... In continuous scan mode, A/D conversion
is continuously performed for the selected
channels in sequence until this bit is cleared
by software, a reset, or in software standby
mode or module standby mode.
Page 1746 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
20.3.5 A/D Bypass Control
Registers 0 to 2
(ADBYPSCR_0 to
ADBYPSCR_2)
1000
Amended
For A/D conversion of group A (GrA), it can be selected
whether or not to use the sample-and-hold circuits
dedicated to the group A channels.
Setting the SH bit in ADBYPSCR_0 to 1 selects the
sample-and-hold circuits dedicated to the channels. When
the sample-and-hold circuits are not to be used, the A/D
conversion time does not include the time for sampling in
the dedicated sample-and-hold circuits. For details, refer to
section 20.4, Operation.
…
Bit
Description
0
Dedicated Sample-and-Hold Circuit Select
(ADBYPSCR_0 only)
0: Does not select the sample-and-hold circuits
1: Selects the sample-and-hold circuits
:
Figure 20.8 Example 3 of A/D 1011
Converter Operation
(Continuous Scan Mode,
Sample-and-Hold Circuit
Enabled, and Offset
Canceling Circuit Disabled)
20.7.5 Notes on Noise
Countermeasures
1024
Figure 20.14 Example of
Analog Input Pin Protection
Circuit
1024
Amended
SH bit = 1
Amended
The bypass capacitors connected to AVREF and the filter
capacitor connected to ANn should be connected to the
AVREFVSS. The 0.1-μF capacitor in figure 20.14 should be
placed close to the pin.
Amended
This LSI
AVREF
0.1 μF
AVREFVSS
Filter resistor: 100 Ω or less (reference value)
AN0 to AN11
Filter capacitor: 0.1 μF or less (reference value)
20.7.6 Permissible Signal
1024
Source Impedance to 20.7.8 to
Notes when Two A/D
1027
Modules Run Simultaneously
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Added
Page 1747 of 1778
Item
Page
Revision (See Manual for Details)
21.1 Features
1029
Amended
•
Figure 21.1 Block Diagram of 1029
D/A Converter
Output voltage of 0 V to AVREF (AVCC)
Amended
AVcc
AVREF
8-bit
D/A
DA0
DA1
AVss
Table 21.1 Pin Configuration 1030
21.4 Operation
1034
Amended
Pin Name
Symbol I/O
Function
Analog power
supply pin
AVcc
Input
Analog block power supply (pin
156)
Analog ground pin
AVss
Input
Analog block ground (pin 157)
Reference voltage
pin
AVREF
Input
D/A conversion reference voltage
Amended
Contents of DADR
256
21.5.3 Setting Analog Input
Voltage
1035
(3) Bit Configuration Register 1061
(BCR0, BCR1)
•
BCR0 (Address = H'006)
22.9 Usage Notes
Page 1748 of 1778
× AVcc
Deleted
1.
...
2.
Setting range of AVREF input voltage
Set the voltage range of the AVREF pin as AVREF =
4.5 V to AVCC when the A/D converter or D/A
converter is used, or as AVREF = AVCC when no A/D
converter or D/A converter is used.
Amended
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
BRP[7]
BRP[6]
BRP[5]
BRP[4]
BRP[3]
BRP[2]
BRP[1]
BRP[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
1098, Added
1099
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Table 23.10 Multiplexed Pins 1113
(SH7285 Port D)
Table 23.11 Multiplexed Pins 1116
(SH7286 Port D)
Table 23.12 Multiplexed Pins 1119
(SH7243 Port E)
Table 23.13 Multiplexed Pins 1121
(SH7285 Port E)
23.1.5 Port B Control
Registers H1 and L1 to L4
(PBCRH1 and PBCRL1 to
PBCRL4)
1163
Revision (See Manual for Details)
Added
Port
Function 1 (Related Module)
Function 4 (Related Module)
D
PD30 I/O (Port)
IRQOUT output (INTC)/
REFOUT output (BSC)
Added
Port
Function 1 (Related Module)
Function 4 (Related Module)
D
PD30 I/O (Port)
IRQOUT output (INTC)/
REFOUT output (BSC)
Port
Function 1 (Related Module)
Function 4 (Related Module)
E
PE15 I/O (Port)
IRQOUT output (INTC)/
REFOUT output (BSC)
Port
Function 1 (Related Module)
Function 4 (Related Module)
E
PE15 I/O (Port)
IRQOUT output (INTC)/
REFOUT output (BSC)
Added
Added
Amended
Bit
Description
2 to 0
PB12 Mode
Select the function of the
PB12/CS1/CS7/IRQ1/TXD2/CS3 pin.
:
(2) SH7285
•
Port D Control Register
H4 (PDCRH4)
1221, Added
1222
Initial
Value
Bit
Bit Name
10 to 8
PD30MD[2:0] 000
R/W
Description
R/W
PD30 Mode
Select the function of the
PD30/IRQOUT/REFOUT/TIOC3CS pin.
:
011: IRQOUT output (INTC)/REFOUT
output (BSC)*
:
Note:
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
*
IRQOUT (INTC) or REFOUT (BSC) is selected
by the IRQOUT function control register (IFCR).
Page 1749 of 1778
Item
Page
Revision (See Manual for Details)
(3) SH7286
1237
to
1239
Added
•
Port D Control Register
H4 (PDCRH4)
Bit
Bit Name
Initial
Value
R/W
Description
14 to 12
PD31MD[2:0] 000*2
R/W
PD31 Mode
10 to 8
PD30MD[2:0] 000*2
R/W
PD30 Mode
:
Select the function of the
PD30/D30/IRQOUT/REFOUT/TIOC3CS
pin.
:
011: IRQOUT output (INTC)/REFOUT
output (BSC)*1
:
6 to 4
PD29MD[2:0] 000*2
R/W
PD29 Mode
2 to 0
PD28MD[2:0] 000*2
R/W
PD28 Mode
:
:
Notes: 1. IRQOUT (INTC) or REFOUT (BSC) is selected
by the IRQOUT function control register (IFCR).
2. The initial value is 1 during the on-chip ROM
disabled 32-bit external extension mode.
(1) SH7243
•
Port E Control Register
L4 (PECRL4)
1260, Added
1262
Initial
Value
Bit
Bit Name
14 to 12
PE15MD[2:0] 000
R/W
Description
R/W
PE15 Mode
Select the function of the
PE15/DACK1/IRQOUT/REFOUT/TIOC4D
pin.
:
011: IRQOUT output (INTC)/REFOUT
output (BSC)*
:
Note:
Page 1750 of 1778
*
IRQOUT (INTC) or REFOUT (BSC) is selected
by the IRQOUT function control register (IFCR).
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
(2) SH7285
1269, Added
1270
•
Port E Control Register
L4 (PECRL4)
Revision (See Manual for Details)
Initial
Value
Bit
Bit Name
14 to 12
PE15MD[2:0] 000
R/W
Description
R/W
PE15 Mode
Select the function of the
PE15/DACK1/IRQOUT/REFOUT/TIOC4D
pin.
:
011: IRQOUT output (INTC)/REFOUT
output (BSC)*
:
Note:
(3) SH7286
•
Port E Control Register
L4 (PECRL4)
*
IRQOUT (INTC) or REFOUT (BSC) is selected
by the IRQOUT function control register (IFCR).
1277, Added
1279
Initial
Value
Bit
Bit Name
14 to 12
PE15MD[2:0] 000
R/W
Description
R/W
PE15 Mode
Select the function of the
PE15/DACK1/IRQOUT/REFOUT/TIOC4D
pin.
:
011: IRQOUT output (INTC)/REFOUT
output (BSC)*
:
Note:
Table 23.18 Pull-Up MOS
Control
1291
*
IRQOUT (INTC) or REFOUT (BSC) is selected
by the IRQOUT function control register (IFCR).
Amended
Pin Function
I/O port output, address output, CK output,
RD output (BSC), WRHH, WRHL, WRH,
WRL output (BSC),
24.1.3 Port A Port Registers
H and L (PAPRH and
PAPRL)
1303
Figure 24.10 Port D
(SH7285)
1326
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Amended
PAPRH and PAPRL are 16-bit read-only registers, which
always return the states of the pins regardless of the PFC
setting. However, when the SCIF function is selected for
PA8, the TE bit in SCSCR is 0, and the SPB2IO bit in
SCSPTR is 0, the states of the corresponding pins cannot
be read out. In SH7243, bits ...
Amended
PD30 (I/O) / TIOC3CS (I/O) / IRQOUT (output) / REFOUT
(output)
Page 1751 of 1778
Item
Page
Revision (See Manual for Details)
Figure 24.11 Port D
(SH7286)
1327
Amended
24.4.3 Port D Port Registers
H and L (PDPRH and
PDPRL)
1332
Figure 24.12 Port E
(SH7243)
1336
Figure 24.13 Port E
(SH7285)
1337
Figure 24.14 Port E
(SH7286)
1337
24.7 Usage Notes
1345
PD30 (I/O) / D30 (I/O) / TIOC3CS (I/O) / IRQOUT (output) /
REFOUT (output)
Amended
PDPRH and PDPRL are 16-bit read-only registers, which
always return the states of the pins regardless of the PFC
setting. However, when the SCIF function is selected for
PD18, the TE bit in SCSCR is 0, and the SPB2IO bit in
SCSPTR is 0, the states of the corresponding pins cannot
be read out. In SH7243, bits ...
Amended
PE15 (I/O) / DACK1 (output) / TIOC4D (I/O) / IRQOUT
(output) / REFOUT (output)
Amended
PE15 (I/O) / DACK1 (output) / TIOC4D (I/O) / IRQOUT
(output) / REFOUT (output)
Amended
PE15 (I/O) / DACK1 (output) / TIOC4D (I/O) / IRQOUT
(output) / REFOUT (output)
Figure 25.1 Block Diagram of 1348
USB
Added
Amended
DMA/DTC transfer request signals
USBRXI, USBTXI
Table 25.1 Pin Configuration 1349
and Functions
Deleted and added
Pin Name
I/O
Function
DrVcc
Input
USB power supply (3.0 V to 3.6 V, DrVCC < Vcc)*
Note:
Table 25.2 Register
Configuration
Page 1752 of 1778
1350
*
For 3.0 V ≤ Vcc ≤ 3.6 V, DrVcc = Vcc or 3.0 V ≤
DrVcc ≤ 3.6 V.
For 3.6 V ≤ Vcc ≤ 5.5 V, DrVcc ≤ 3.6 V < Vcc.
Added
Register Name
Access Size
USBEP1 data register
8, 16, 32
USBEP2 data register
8, 16, 32
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
25.3.10 USBEP1 Data
Register (USBEPDR1)
1360
Amended
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
Undefined
R
Data register for endpoint 1 transfer
Note: * 7 to 0 bits for DMA or DTC transfer.
25.3.11 USBEP2 Data
Register (USBEPDR2)
1361
Amended
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
Undefined
W
Data register for endpoint 2 transfer
Note: * 7 to 0 bits for DMA or DTC transfer.
25.3.18 USBDMA Transfer
1369
Setting Register (USBDMAR)
Added
Notes: 1. Before setting this bit, set the DME bit in
DMAOR to start DMA transfer or set the DTCE0
bit in DTCERA to start DTC transfer.
If the DME bit in DMAOR and the DTCE0 bit in
DTCERA are not set, an EP2-FIFO empty DTC
transfer end interrupt (TXF bit in USDTENDRR)
is generated.
2. Before setting this bit, set the DME bit in
DMAOR to start DMA transfer or set the DTCE1
bit in DTCERA to start DTC transfer.
If the DME bit in DMAOR and the DTCE1 bit in
DTCERA are not set, an EP1-FIFO full DTC
transfer end interrupt (RXF bit in USDTENDRR)
is generated.
Table 25.3 Interrupt Sources 1371
Amended
DMAC/DTC Activation
Register
Bit
Transfer Type
by USB Request
USBIFR0
6
Bulk-OUT (EP1)
USBRXI*1
5
Bulk-IN (EP2)
4
25.5.1 Initial Settings
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
1372
×
USBTXI*2
Added
Page 1753 of 1778
Item
Page
Revision (See Manual for Details)
Figure 25.28 Example of
USB Function Module
External Circuitry
1401
Amended
This LSI
IC that allows
voltage application
when the system (LSI)
power is off.
PB10
(PUPD)
(For On-Chip Transceiver)
3.3 V
USB module
VBUS
3.3 V
USB
connector
IC that allows
voltage application
when the system (LSI)
power is off.
VBUS
5V
USD+
USD+
USD-
USD-
GND
Note: Operation cannot be guaranteed by this example.
When the system requires countermeasures against external surge
or ESD noise, use the protection diode or noise canceler.
25.10 Example of USB
External Circuitry
1401
25.11.9 Handling of Unused
USB Pins
1404
Section 26 Flash Memory
(ROM)
1405
Page 1754 of 1778
USB
cable
Added
Note: The same voltage as the CPU voltage (Vcc) should
be applied to VBUS.
Amended
• Handle the unused pins as listed below.
If this process is not performed, correct operation of the
LSI cannot be guaranteed.
DrVcc = 3.0 V to 5.5 V
Added and deleted
This LSI has 1-Mbyte on-chip flash memory. The flash
memory has the following features.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
26.1 Features
1405, Amended
1406 :
•
Four (three in SH7243) on-board programming modes
and one off-board programming mode
:
•
High-speed reading through ROM cache
Both the user MAT and user boot MAT can be read at
high speed through the ROM cache. They can be read
only in on-chip ROM enabled mode.
:
•
Programming/erasing time
The time taken to program 256 bytes of flash memory
in a single round is tP ms (typ.), which is equivalent to
tP/256 ms per byte. The erasing time is tEs (typ.) per
block. Refer to section 31.7, Flash Memory
Characteristics.
:
•
Figure 26.1 Block Diagram of 1407
Flash Memory
Table 26.1 Relationship
between FWE and MD Pins
and Operating Modes
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
1409
Operating frequency for programming/erasing
The operating frequency for programming/erasing is
50 MHz (Pφ).
Amended
Note: *
User boot MAT cannot be used in the SH7243.
Amended
Notes:
…
4. Becomes USB boot mode if always FWE = 1
after the power has been turned on. If FWE = 0
until the reset is released and then changed to
FWE = 1 after the MCU operating mode is
determined as single-chip mode, the operating
mode transits to user program mode.
Page 1755 of 1778
Item
Page
Revision (See Manual for Details)
Table 26.2 Comparison of
Programming Modes
1410
Amended
User
Program
Mode
User Boot
USB Boot
Mode*3
Mode*3
Mode
Transition Mode setting
FWE
Mode
Mode
—
to user
mode
change and reset
setting
change
setting
setting
change and change and
reset
reset
Pin state
CK: output
Dependent
CK: output
CK: output
Programmer
Other pins: input
on user
settings
(initial
setting)
Other pins:
dedicated
pins
Boot Mode
input
(same as the
Other pins:
(same as
input (initial the states
setting)
in MCU
extension
mode 2)
states in MCU
extension mode 2)
RXD0 and TXD0:
valid
Table 26.3 Pin Configuration 1415
Programmer
Added
Input/
Pin Name
Symbol Output
Function
SCI receive data
RXD0
Serial receive data input (used in boot mode)
Input
(PA0)
Pull-up control
(SH7285 and SH7286)
RXD0
(PB6)
Input
Serial receive data input (used in boot mode)
(SH7243)
PUPD
Output
Pull-up control (used in USB boot mode)
(PB10)
USB data
USB+
(SH7285 and SH7286)
I/O
USB−
USD signal from the USB that has a
transceiver (used in USB boot mode)
(SH7285 and SH7286)
USB cable
VBUS
connection monitor
Input
Detects connection and disconnection of the
USB cable (used in USB boot mode)
(SH7285 and SH7286)
USB clock select
Input
Selects the clock supplied by the USB (used
PC0
in USB boot mode)
(SH7285 and SH7286)
Table 26.4 (1) Register
Configuration
1416
Amended
Access
Register Name
Abbreviation
R/W
Initial Value
Address
Size
Flash transfer
FTDAR
R/W
H'00
H'FFFFA806
8
RCCR
R/W
H'00000001
H'FFFC1400
32
destination address
register
ROM cache control
register
(7) ROM Cache Control
Register (RCCR)
Page 1756 of 1778
1425
Added
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
(2.1) Flash
Programming/Erasing
Frequency Parameter
(FPEFEQ: General Register
R4 of CPU)
1430
Amended
(3) Programming Execution
1434
This parameter sets the operating frequency of the CPU.
For the operating frequency of this LSI, see section 31.3.1,
Clock Timing.
Amended
:
2. The program data for the user MAT must be prepared in
the consecutive area. The program data must be in the
consecutive space which can be accessed by using the
MOV.L instruction of the CPU and is not the flash
memory space.
Table 26.7 Peripheral Clock 1443
(Pφ) Frequency that Can
Automatically Adjust Bit Rate
of This LSI
Amended
Host Bit Rate
Peripheral Clock (Pφ) Frequency That
Can Automatically Adjust LSI's Bit Rate
9,600 bps
10 to 50 MHz
19,200 bps
Figure 26.9 System
1446
Configuration Diagram when
Using USB Boot Mode
Figure 26.11
Programming/Erasing
Overview Flow
1449
(2) Programming Procedure
in User Program Mode
1451
Descriptions of (2.6)
1454
Amended
PB10 (PBIO) → PB10 (PUPD)
Amended
MOV.B instruction → MOV.L instruction
Amended
Specify Iφ = Bφ = Pφ as the frequency division ratio of an
internal clock (Iφ), a bus clock (Bφ), and a peripheral clock
(Pφ) through the frequency control register (FRQCR).
Amended
1. The current frequency of the CPU clock is set to the
FPEFEQ parameter (general register R4). The settable
FPEFEQ parameter is Iφ ≤ 50 MHz.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1757 of 1778
Item
Page
Revision (See Manual for Details)
Figure 26.14 Erasing
Procedure
1457
Amended
Start erasing procedure
program
Set FRQCR to satisfy
Iφ = Bφ = Pφ
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(3) Erasing Procedure in
User Program Mode
1457
(3.1)
Amended
:
The frequency division ratio of an internal clock (Iφ), a bus
clock (Bφ), and a peripheral clock (Pφ) is specified as Iφ =
Bφ = Pφ ≤ 50 MHz by the frequency control register
(FRQCR).
26.7.1 Switching between
User MAT and User Boot
MAT
1469
Added
:
6. ROM cache must be flushed after the MATs have been
switched.
Disable (flush) the instructions or data cached in the
ROM cache by writing 1 to the RCF bit in RCCR.
Figure 26.19 Switching
1470
between User MAT and User
Boot MAT
"(3) Write H'00000009 to RCCR." added to both
procedures.
Table 26.11 Initiation
Intervals of User Branch
Processing
Amended and deleted
Table 26.12 Initial User
Branch Processing Time
Page 1758 of 1778
1472
1472
Processing Name
Maximum Interval
Minimum Interval
Programming
1.6 ms
TBD
Erasing
12 ms
TBD
Amended and deleted
Processing Name
Maximum Interval
Minimum Interval
Programming
1.6 ms
TBD
Erasing
12 ms
TBD
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
(k) New Bit Rate Selection
1486, Amended
1487 No. of multipliers → Multiplier type count
•
Command H'3F (1 byte): New bit rate selection
•
Size (1 byte): The total length of the bit rate, input
frequency, number of multiplier types, and multiplier
fields
:
•
Multiplier type count (1 byte): The number of selectable
frequency multiplier types for the device.
:
26.9 Programmer Mode
1512
Amended
Use a PROM programmer that supports the Renesas 512Kbyte flash memory on-chip MCU device type
(FZTAT512DV5A/FZTAT1024DV5A).
Table 28.1 States of PowerDown Modes
1517
Amended
Power-Down Mode
Canceling Procedure
Module standby
function
•
Clear MSTP bit to 0
•
Power-on reset (only for H-UDI,
UBC, DMAC, and DTC)
28.3.4 Standby Control
Register 4 (STBCR4)
1525
Amended
28.3.5 Standby Control
Register 5 (STBCR5)
1526
28.3.6 Standby Control
Register 6 (STBCR6)
1527, Amended
1528 STBCR6 is initialized to H'DF by a power-on reset but
retains its previous value ...
STBCR4 is initialized to H'F6 by a power-on reset but
retains its previous value ...
Amended
STBCR5 is initialized to H'FF by a power-on reset but
retains its previous value ...
Bit 4: RCAN → RCAN-ET
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1759 of 1778
Item
Page
Table 28.4 Register States in 1535
Software Standby Mode
Revision (See Manual for Details)
Amended and deleted
Module Name
A/D converter (ADC)
All registers
⎯
Serial communication
interface with FIFO (SCIF)
⎯
All registers
Note: *
28.4.3 Module Standby
Function
1536
Registers
Whose Content
is Retained
Initialized
Registers
The A/D converter register values become
undetermined.
Amended and deleted
(1) Transition to Module Standby Function
:
The register states are the same as those in software
standby mode. For details of register states, refer to section
30.3, Register States in Each Operating Mode.
However, the states of the CMT and DAC registers are
exceptional. In the CMT, ... in module standby mode.
(2) Canceling Module Standby Function
The module standby function can be canceled by clearing
the MSTP bits to 0, or by a power-on reset (only possible
for H-UDI, UBC, DMAC, and DTC).
28.5 Usage Notes
1537
Added
Table 29.4 Reset
Configuration
1544
Added
ASEMD0*1
RES
TRST
Chip State
H
H
L
H-UDI reset only (normal operation)
H
Normal operation
30.1 Register Addresses (by 1548
functional module, in order of to
1571
the corresponding section
numbers)
Fully amended
30.2 Register Bits
1572
to
1602
Fully amended
30.3 Register States in Each 1603
Operating Mode
to
1620
Fully amended
Page 1760 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table 31.1 Absolute
Maximum Ratings
1621
Amended
Item
Symbol
Value
Power supply voltage (Internal)
VCC
−0.3 to +7.0
DrVCC
−0.3 to +7.0
Table 31.2 DC
1622, Amended
Characteristics (1) [Common 1623
Item
Items]
Symbol
3
USB power supply*
Reference power
supply current
DrVCC
During A/D conversion
AIref
Waiting for A/D conversion
Notes: ...
3. 3.0 V ≤ DrVCC ≤ VCC when the USB is not used.
Table 31.3 Permissible
Output Currents
1625
Table 31.4 Maximum
Operating Frequency
1626
Amended
Notes: 1. TIOC3B, TIOC3D, TIOC4A to TIOC4D,
TIOC3BS, TIOC3DS, and TIOC4AS to
TIOC4DS: IOL = 15 mA (Max)/-IOH = 5 mA ...
Amended
Item
Symbol
Operating
frequency
MTU2S (Mφ)
f
AD (Aφ)
Figure 31.2 CK Clock Input
Timing
1628
Deleted
Table 31.6 Control Signal
Timing
1630
Amended and added
Bφ = 50 MHz
Item
Symbol
Min.
Max.
MRES pulse width
tMRESW
20*2
⎯
IRQ pulse width
tIRQW
4*
⎯
NMI pulse width
tNMIW
4*3
⎯
3
Notes: ...
Since the CK width is initialized by the RES pin,
tcyc becomes the initial value.
3. The clock ratio of Bφ:Pφ = 4:1.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1761 of 1778
Item
Page
Revision (See Manual for Details)
Figure 31.7 Interrupt Signal
Input Timing
1631
Amended
CK
tRESH/tMRESH tRESS/tMRESS
VIH
RES
MRES
VIL
tNMIH
tNMIS
VIH
NMI
VIL
tIRQH
tIRQS
tNMIW
VIH
IRQ7 to IRQ0
VIL
tIRQW
Table 31.7 Bus Timing
1633
to
1635
Figure 31.10 Basic Bus
1636
Timing for Normal Space (No
Wait)
Fully amended
Added
tRSD
tRSD
tAH
tCSH
RD
tRDH1
tACC
Read
D31 to D0
tRDS1
tOE
tWED1
tWED1
tAH
tCSH
WRxx
tWDH4
Write
tWDD1
tWDH1
D31 to D0
Figure 31.11 Basic Bus
Timing for Normal Space
(One Software Wait Cycle)
1637
Added
tCSS
tRWD1
tRWD1
RD/WR
tRSD
tRSD
tAH
tCSH
RD
tRDH1
tACC
Read
D31 to D0
tOE
tWED1
tWED1
tAH
tCSH
WRxx
Write
tRDS1
tWDH4
tWDD1
tWDH1
D31 to D0
Page 1762 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Figure 31.12 Basic Bus
Timing for Normal Space
(One External Wait Cycle)
1638
Amended
tCSS
tRWD1
tRWD1
RD/WR
tRSD
tRSD
tAH
RD
tCSH
Read
tACC
D31 to D0
tRDS1
tRDH1
tOE
tWED1
tWED1
tAH
WRxx
tCSH
tWDH4
Write
tWDD1
tWDH1
D31 to D0
Figure 31.13 Basic Bus
Timing for Normal Space
(One Software Wait Cycle,
External Wait Cycle Valid
(WM Bit = 0), No Idle Cycle)
1639
Amended
tRWD1
tCSS
tCSS
tRWD1
tRWD1
tRWD1
RD/WR
tRSD
tRSD
RD
tAH
tRSD
tRSD
tCSH
Read
tCSH
t
tRDS1 RDH1
tACC
tAH
tACC
tRDS1
tRDH1
D15 to D0
tOE
tOE
tWED1
tWED1
tAH
tWED1
tWED1
tCSH
Write
tAH
tCSH
WRxx
tWDD1
tWDH1
tWDD1
tWDH1
tWDH4
D15 to D0
Figure 31.14 MPX-I/O
Interface Bus Cycle (Three
Address Cycles, One
Software Wait Cycle, One
External Wait Cycle)
1640
Amended
tWED1
WRH, WRL
Write
tMAD
D15 to D0
Figure 31.15 Bus Cycle of
1641
SRAM with Byte Selection
(SW = 1 Cycle, HW = 1
Cycle, One Asynchronous
External Wait Cycle, BAS = 0
(Write Cycle UB/LB Control))
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
tWED1
tWDHC
tWDD1
tWDH1
tMAH
Address
Data
Amended
tWED1
tWED1
WRx
Page 1763 of 1778
Item
Page
Revision (See Manual for Details)
Figure 31.16 Bus Cycle of
1642
SRAM with Byte Selection
(SW = 1 Cycle, HW = 1
Cycle, One Asynchronous
External Wait Cycle, BAS = 1
(Write Cycle WE Control))
Amended
Figure 31.17 Burst ROM
1643
Read Cycle (One Software
Wait Cycle, One
Asynchronous External Burst
Wait Cycle, Two-Cycle Burst)
Amended
tWED2
tWED2
WRx
WRx
31.3.6 Multi Function Timer
Pulse Unit 2 (MTU2) Timing
and
31.3.7 Multi Function Timer
Pulse Unit 2S (MTU2S)
Timing
1665, Added
1666
Figure 31.45 Input Clock
Timing
1669
Added
tSCKr
tSCKW
VIH
VIH
VIH
VIL
SCK0 to SCK2,
SCK4
Figure 31.46 SCI
Input/Output Timing
1670
tSCKf
VIH
VIL
VIL
tScyc
Added
SCI I/O timing (clocked synchronous mode)
tscyc
SCK0 to SCK2, SCK4
(input/output)
tTXD
TXD0 to TXD2, TXD4
(transmit data)
tRXS
tRXH
RXD0 to RXD2, RXD4
(receive data)
SCI I/O timing (asynchronous mode)
T1
VOH
Tn
VOH
CK
tTXD
TXD0 to TXD2, TXD4
(transmit data)
tRXS
tRXH
RXD0 to RXD2, RXD4
(receive data)
Page 1764 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table 31.15 SCIF Module
Timing
1671
Amended
Item
Input clock cycle
(clocked
Symbol Min.
Max.
Figure
tScyc
⎯
Figure
6
synchronous)
31.47
2tpcyc + 5
⎯
Transmit data delay time (asynchronous) tTXD
⎯
3tpcyc + 20
Receive data setup time (asynchronous) tRXS
3tpcyc + 20
⎯
Figure
31.48
Receive data hold time (asynchronous)
2tpcyc + 5
⎯
Figure
Receive data hold time (clocked
tRXH
Figure
synchronous)
31.48
Figure
31.48
tRXH
31.48
Figure 31.48 SCIF
Input/Output Timing in
Clocked Synchronous Mode
1672
Replaced
Table 31.16 Serial
Communication Unit (SSU)
Timing
1673
Amended
Item
Clock high pulse
Master
Symbol Min.
Max.
Figure
tHI
35
⎯
Figures
35
⎯
35
⎯
35
⎯
width
Slave
Clock low pulse
width
Master
tLO
Slave
Clock rise time
tRISE
⎯
15
Clock fall time
tFALL
⎯
15
tSU
15
⎯
30
⎯
⎯
20
⎯
35
Data input setup
time
Data output delay
time
Master
Slave
Master
Slave
tOD
31.49,
31.50,
31.51,
31.52
Note: tpcyc indicates peripheral clock (Pφ) cycle.
The above values are for a TTL output. The above
values are not guaranteed for an open-drain output.
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1765 of 1778
Item
Page
2
Table 31.18 I C Bus Interface 1677
3 Timing
Revision (See Manual for Details)
Amended
Specifications
Item
Min.
Typ.
Max.
Unit
SCL input cycle time
12 tpcyc*1 + 600
⎯
⎯
ns
SCL input high pulse width
3 tpcyc*1 + 300
⎯
⎯
ns
SCL input low pulse width
5 tpcyc*1 + 300
⎯
⎯
ns
SCL, SDA input rise time
⎯
⎯
300
ns
SCL, SDA input fall time
⎯
⎯
300
ns
SCL, SDA input spike pulse
⎯
⎯
1 tpcyc*1
ns
1 tpcyc*1 + 20
⎯
⎯
ns
removal time*2
Data input setup time
Table 31.22 A/D Converter
Characteristics
1683
Amended
Item
Test Condition
Absolute
Sample & hold circuits
accuracy
are in use
Sample & hold circuits
VAN = AVREFVSS + 0.25 V to AVREF – 0.25 V
VAN = AVREFVSS to AVREF
are not in use
Table 31.24 USB
Characteristics (USD+ and
USD- Pins) when Using OnChip Transceiver
1685
Table 31.25 Flash Memory
Characteristics
1687
31.8 Usage Notes
Page 1766 of 1778
Added
Note: When the USB is not used, connect DrVss to GND
and DrVcc to Vcc.
USD− and USD+ should be left open. In this case,
DrVcc = 3.0 V to 5.5 V.
1688
Amended
Item
Min.
Typ.
Max.
Unit
Programming time*1*2
⎯
2
20
ms/256 bytes
Added
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Item
Page
Revision (See Manual for Details)
Table A.1 Pin States
(SH7243)
1689, Amended
1691
Pin Function
Pin State
Power-Down State
Table A.2 Pin States
(SH7285)
Type
Pin Name
Software Standby
POE Function
Used
Clock
CK
Z*4
O
MTU2
TIOC0A to TIOC0D
Z
(MZIZEL in HCPCR = 0)
K*1
(MZIZEL in HCPCR = 1)
Z
TIOC1B
Z
(MZIZEL in HCPCR = 0)
K*1
(MZIZEL in HCPCR = 1)
I/O
TIOC2A
Z
(MZIZEL in HCPCR = 0)
K*1
(MZIZEL in HCPCR = 1)
I/O
1695, Amended
1697
Pin Function
Pin State
Power-Down State
POE Function
Type
Pin Name
Software Standby
Used
Clock
CK
Z*4
O
MTU2
TIOC1B
Z
I/O
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2A
I/O
Z
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Page 1767 of 1778
Item
Page
Revision (See Manual for Details)
Table A.3 Pin States
(SH7286)
1702
to
1704
Amended and added
Pin Function
Pin State
Power-Down State
POE
Function
Type
Clock
Pin Name
CK
Sleep
Used
4
O
O
3
Software Standby
Z*
Address bus
A0 to A25
Z*
O
O
Bus control
WAIT
Z
I
I
REFOUT
H/Z*1
O
H/Z*1
TIOC1B
Z
I/O
I/O
I/O
I/O
MTU2
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
TIOC2A
Z
(MZIZEL in HCPCR = 0)
K*
1
(MZIZEL in HCPCR = 1)
Page 1768 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Index
Numerics
16-bit/32-bit displacement ........................ 33
A
A/D conversion time............................. 1015
A/D converter (ADC) ............................. 987
A/D converter activation......................... 627
A/D converter activation by MTU2
and MTU2S .......................................... 1016
A/D converter characteristics................ 1683
A/D converter start request delaying
function................................................... 608
A/D trigger input timing ....................... 1678
Absolute accuracy................................. 1021
Absolute address....................................... 33
Absolute address accessing....................... 33
Absolute maximum ratings................... 1621
AC characteristics................................. 1626
AC characteristics measurement
conditions ............................................. 1682
Access size and data alignment .............. 305
Access wait control................................. 315
Address errors......................................... 105
Address map ........................................... 250
Address multiplexing.............................. 325
Addressing modes..................................... 34
Arithmetic operation instructions ............. 52
Auto-refreshing....................................... 351
Auto-request mode ................................. 417
B
Banked register and input/output of
banks....................................................... 156
Bit manipulation instructions.................... 60
Bit synchronous circuit ........................... 980
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Block transfer mode ................................ 224
Boot mode............................................. 1442
Branch instructions ................................... 57
Break detection and processing....... 827, 889
Break on data access cycle...................... 191
Break on instruction fetch cycle.............. 190
Burst mode.............................................. 430
Burst ROM (clock asynchronous)
interface .................................................. 364
Burst ROM (clock synchronous)
interface .................................................. 372
Bus arbitration......................................... 380
Bus state controller (BSC) ...................... 245
Bus timing............................................. 1633
Bus-released state...................................... 62
C
Calculating exception handling vector
table addresses ........................................ 100
CAN interface ....................................... 1041
CAN sleep mode ................................... 1083
Cascaded operation ................................. 542
Caution on period setting ........................ 643
Chain transfer.......................................... 225
Changing the frequency .......................... 755
Clock frequency control circuit................. 75
Clock operating mode and settable
frequency range......................................... 79
Clock operating modes ............................. 78
Clock pulse generator (CPG) .................... 73
Clock synchronous mode ................ 763, 808
Clock timing ......................................... 1627
Clocked synchronous serial format......... 968
CMCNT count timing ............................. 739
Compare match timer (CMT) ................. 733
Complementary PWM mode .................. 562
Page 1769 of 1778
Conflict between byte-write and
count-up processes of CMCNT .............. 744
Conflict between NMI Interrupt and
DTC Activation ...................................... 242
Conflict between word-write and
count-up processes of CMCNT .............. 743
Conflict between write and
compare-match processes of CMCNT.... 742
Continuous scan mode.......................... 1008
Control signal timing ............................ 1630
Control transfer..................................... 1375
Controller area network (RCAN-ET) ... 1037
Controller area network timing............. 1676
CPU .......................................................... 23
Crystal oscillator....................................... 75
CSn assert period expansion................... 317
Cycle steal mode..................................... 428
D
D/A converter (DAC) ........................... 1029
D/A converter characteristics ............... 1684
D/A output hold function in software
standby mode........................................ 1035
Data format in registers ............................ 28
Data formats in memory ........................... 28
Data transfer controller (DTC) ............... 197
Data transfer instructions.......................... 48
Data transfer with interrupt request
signals..................................................... 160
DC characteristics................................. 1622
Dead time compensation ........................ 620
Definition of time quanta...................... 1059
Definitions of A/D conversion
accuracy................................................ 1021
Delayed branch instructions ..................... 31
Direct memory access controller
(DMAC) ................................................. 387
Displacement accessing............................ 33
Divider...................................................... 75
Page 1770 of 1778
DMA transfer flowchart.......................... 416
DMAC and DTC activation .................... 626
DMAC module timing .......................... 1664
DREQ pin sampling timing .................... 433
DTC activation by interrupt .................... 237
DTC activation sources........................... 210
DTC bus release timing .......................... 232
DTC execution status.............................. 230
DTC vector address ................................ 212
Dual address mode.................................. 425
E
Effective address calculation .................... 34
Electrical characteristics ....................... 1621
Endian ..................................................... 305
EP1 bulk-OUT transfer ......................... 1381
EP2 bulk-IN transfer............................. 1382
EP3 interrupt-IN transfer ...................... 1384
Equation for getting SCBRR value......... 852
Error protection..................................... 1467
Example of USB external circuitry....... 1401
Exception handling ................................... 95
Exception handling state ........................... 62
Exception handling vector table................ 99
Exception source generation
immediately after delayed branch
instruction ............................................... 114
Exceptions triggered by instructions....... 111
External pulse width measurement ......... 619
External request mode............................. 417
External trigger input timing................. 1017
F
Fixed mode ............................................. 421
Flash memory (ROM)........................... 1405
Flash memory configuration ................. 1411
Full-scale error...................................... 1021
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
G
General illegal instructions ..................... 113
General registers ....................................... 23
Global base register (GBR) ...................... 25
H
Halt mode ............................................. 1083
Hardware protection ............................. 1466
H-UDI commands................................. 1542
H-UDI interrupt ............................ 133, 1545
H-UDI related pin timing...................... 1680
H-UDI reset .......................................... 1545
I
I/O port timing ...................................... 1679
I/O ports................................................ 1295
I2C bus format......................................... 958
I2C bus interface 3 (IIC3) ....................... 939
ID Reorder ............................................ 1052
IIC3 module timing .............................. 1677
Immediate data ......................................... 32
Immediate data accessing ......................... 32
Immediate data format.............................. 29
Initial user branch processing time ....... 1472
Initial values of control registers .............. 27
Initial values of general registers .............. 27
Initial values of system registers............... 27
Initiation intervals of user branch
processing ............................................. 1472
Input sampling and A/D conversion
time ....................................................... 1013
Instruction features ................................... 30
Instruction format ..................................... 39
Instruction set ........................................... 43
Integer division instructions ................... 113
Interrupt controller (INTC)..................... 119
Interrupt exception handling................... 110
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Interrupt exception handling vectors
and priorities ........................................... 137
Interrupt priority level............................. 109
Interrupt response time ........................... 149
IRQ interrupts ......................................... 134
J
Jump table base register (TBR)................. 25
L
Load-store architecture ............................. 30
Local acceptance filter mask
(LAFM)................................................. 1049
Location of transfer information and
DTC vector table..................................... 210
Logic operation instructions...................... 55
M
Mailbox................................................. 1040
Mailbox control..................................... 1040
Mailbox structure .................................. 1044
Manual reset.................................. 104, 1518
Master receive operation......................... 961
Master transmit operation ....................... 959
MCU extension mode ............................... 64
MCU operating modes .............................. 63
Message control field............................ 1045
Message data fields ............................... 1050
Message receive sequence .................... 1090
Message transmission sequence............ 1087
Micro processor interface (MPI)........... 1040
Module standby function ...................... 1536
Module standby mode
setting...................................... 241, 829, 936
MPX-I/O interface .................................. 318
MTU2 functions...................................... 442
MTU2 interrupts ..................................... 625
Page 1771 of 1778
MTU2 output pin initialization............... 660
MTU2–MTU2S synchronous
operation ................................................. 613
MTU2S functions ................................... 693
Multi-function timer pulse unit 2
(MTU2) .................................................. 441
Multi-function timer pulse unit 2S
(MTU2S) ................................................ 693
Multiplexed pins (port A) ..................... 1101
Multiplexed pins (port B) ..................... 1105
Multiplexed pins (port C) ..................... 1109
Multiplexed pins (port D) ..................... 1111
Multiplexed pins (port E) ..................... 1119
Multiplexed pins (port F)...................... 1124
Multiply and accumulate register high
(MACH) ................................................... 26
Multiply and accumulate register low
(MACL).................................................... 26
Multiply/Multiply-and-accumulate
operations ................................................. 31
Multiprocessor communication
function................................................... 817
N
NMI interrupt.......................................... 133
Noise filter .............................................. 972
Nonlinearity error ................................. 1021
Normal space interface ........................... 310
Normal transfer mode............................. 221
Note on changing operating mode............ 72
Note on using an external crystal
resonator ................................................... 94
Notes on board design .......................... 1023
Notes on noise countermeasures........... 1024
O
Offset error ........................................... 1021
On-board programming mode .............. 1442
Page 1772 of 1778
On-chip peripheral module interrupts ..... 135
On-chip peripheral module request......... 419
On-chip RAM ....................................... 1513
Operation in asynchronous mode............ 868
Operation in clocked synchronous
mode ....................................................... 878
Output load circuit ................................ 1682
P
Page conflict ......................................... 1515
Pin function controller (PFC)................ 1101
Pin states of this LSI in each
processing state ..................................... 1689
PLL circuit ................................................ 75
POE2 interrupt source............................. 731
POE2 module timing ............................ 1667
Port output enable 2 (POE2) ................... 701
Power-down modes............................... 1517
Power-down state...................................... 62
Power-on reset ...................................... 1518
Procedure register (PR)............................. 26
Processing of USB standard
commands ............................................. 1385
Product code lineup .............................. 1709
Program counter (PC) ............................... 26
Program execution state............................ 62
Programmer mode................................. 1512
Q
Quantization error ................................. 1021
R
RCAN-ET bit rate calculation .............. 1062
RCAN-ET interrupt sources ................. 1094
RCAN-ET memory map ....................... 1042
RCAN-ET reset sequence ..................... 1082
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Receive data sampling timing and
receive margin (asynchronous mode) ..... 890
Reconfiguration of Mailbox ................. 1092
Register addresses
(by functional module, in order of the
corresponding section numbers) ........... 1548
Register bank error exception
handling .......................................... 107, 159
Register bank errors................................ 107
Register bank exception.......................... 159
Register banks................................... 27, 155
Register bits .......................................... 1572
Register states in each operating
mode ..................................................... 1603
Registers
ABACK0 .......................................... 1076
ACLKCR.............................................. 85
ADANSR_0 to ADANSR_2 .............. 999
ADBYPSCR_0 to ADBYPSCR_2 ... 1000
ADCR_0 to ADCR_2 ......................... 993
ADDR0 to ADDR11......................... 1001
ADSR_0 to ADSR_2.......................... 996
ADSTRGR_0 to ADSTRGR_2 .......... 997
BAMR ........................ 170, 174, 178, 182
BAR............................ 169, 173, 177, 181
BBR ............................ 171, 175, 179, 183
BCR0, BCR1 .................................... 1059
BRCR ................................................. 185
BSCEHR..................................... 209, 301
CHCR ................................................. 398
CMCNT .............................................. 738
CMCOR.............................................. 738
CMCSR .............................................. 736
CMNCR.............................................. 256
CMSTR............................................... 735
CRA.................................................... 204
CRB .................................................... 205
CSnBCR (n = 0 to 7) .......................... 259
CSnWCR (n = 0 to 7) ......................... 264
DACR ............................................... 1032
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
DADR0 ............................................. 1031
DADR1 ............................................. 1031
DAR (DMAC) .................................... 396
DAR (DTC) ........................................ 203
DMAOR.............................................. 409
DMARS0 to DMARS3 ....................... 413
DMATCR ........................................... 397
DPFR ................................................ 1428
DTCCR ............................................... 207
DTCERA to DTCERE ........................ 206
DTCVBR ............................................ 209
FCCS................................................. 1418
FEBS................................................. 1439
FECS................................................. 1421
FKEY ................................................ 1422
FMATS ............................................. 1423
FMPAR............................................. 1434
FMPDR............................................. 1435
FPCS ................................................. 1421
FPEFEQ ............................................ 1430
FPFR ............................. 1433, 1436, 1440
FRQCR ................................................. 81
FTDAR ............................................. 1424
FUBRA ............................................. 1431
GSR................................................... 1057
HCPCR ............................................. 1287
IBCR ................................................... 129
IBNR................................................... 130
ICCR1 ................................................. 943
ICCR2 ................................................. 946
ICDRR ................................................ 956
ICDRS................................................. 956
ICDRT ................................................ 955
ICIER .................................................. 950
ICMR .................................................. 948
ICR0.................................................... 125
ICR1.................................................... 126
ICSR.................................................... 952
ICSR1.................................................. 706
ICSR2.................................................. 711
Page 1773 of 1778
ICSR3 ................................................. 716
IFCR ................................................. 1289
IMR .................................................. 1069
IPR01, IPR02, IPR05 to IPR18 .......... 123
IRQRR................................................ 127
IRR ................................................... 1064
MBIMR0 .......................................... 1078
MCLKCR ............................................. 84
MCR ................................................. 1051
MRA................................................... 200
MRB ................................................... 201
NF2CYC............................................. 957
OCSR1................................................ 710
OCSR2................................................ 715
OSCCR................................................. 86
PACRH2........................1129, 1134, 1144
PACRL1 ........................1134, 1142, 1154
PACRL2 ........................1133, 1140, 1151
PACRL3 ........................1132, 1139, 1149
PACRL4 ........................1129, 1136, 1146
PADRH ............................................ 1298
PADRL ............................................. 1298
PAIORH ........................................... 1128
PAIORL............................................ 1128
PAPCRH........................1156, 1157, 1159
PAPCRL ........................1157, 1158, 1160
PAPRH ............................................. 1303
PAPRL.............................................. 1303
PBCRH1 ........................1162, 1167, 1175
PBCRL1 ........................1166, 1172, 1184
PBCRL2 ........................1165, 1171, 1182
PBCRL3 ........................1163, 1169, 1180
PBCRL4 ........................1162, 1168, 1177
PBDRH............................................. 1310
PBDRL ............................................. 1310
PBIORH ........................................... 1161
PBIORL............................................ 1161
PBPCRH........................1186, 1187, 1188
PBPCRL ........................1186, 1187, 1189
PBPRH ............................................. 1316
Page 1774 of 1778
PBPRL .............................................. 1316
PCCRL1.................................. 1197, 1206
PCCRL2.................................. 1195, 1204
PCCRL3.................................. 1193, 1202
PCCRL4.................................. 1190, 1199
PCDRL ............................................. 1322
PCIORL ............................................ 1190
PCPCRL ........................................... 1208
PCPRL .............................................. 1324
PDCRH1 ....................... 1211, 1226, 1244
PDCRH2 ....................... 1210, 1225, 1242
PDCRH3 ....................... 1210, 1223, 1239
PDCRH4 ....................... 1210, 1220, 1237
PDCRL1 ....................... 1218, 1235, 1253
PDCRL2 ....................... 1215, 1233, 1251
PDCRL3 ....................... 1213, 1231, 1249
PDCRL4 ....................... 1211, 1229, 1246
PDDRH............................................. 1328
PDDRL ............................................. 1328
PDIORH ........................................... 1209
PDIORL............................................ 1209
PDPCRH....................... 1255, 1256, 1258
PDPCRL ....................... 1255, 1257, 1259
PDPRH ............................................. 1332
PDPRL.............................................. 1332
PECRL1........................ 1266, 1275, 1283
PECRL2........................ 1264, 1273, 1281
PECRL3........................ 1262, 1271, 1279
PECRL4........................ 1260, 1268, 1277
PEDRL.............................................. 1338
PEIORL ............................................ 1259
PEPCRL............................................ 1286
PEPRL .............................................. 1340
PFDRL.............................................. 1342
POECR1 ............................................. 720
POECR2 ............................................. 721
RCCR................................................ 1425
RDAR ................................................. 407
RDMATCR......................................... 408
REC................................................... 1069
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
RFPR0 .............................................. 1077
RSAR.................................................. 406
RTCNT ............................................... 299
RTCOR............................................... 300
RTCSR ............................................... 297
RXPR0.............................................. 1076
SAR (DMAC)..................................... 395
SAR (DTC)......................................... 203
SAR (IIC3) ......................................... 955
SCBRR (SCI) ..................................... 784
SCBRR (SCIF) ................................... 852
SCFCR................................................ 859
SCFDR ............................................... 861
SCFRDR............................................. 835
SCFSR ................................................ 844
SCFTDR ............................................. 836
SCLSR................................................ 863
SCRDR (SCI) ..................................... 767
SCRSR (SCIF).................................... 834
SCSCR (SCI)...................................... 772
SCSCR (SCIF).................................... 840
SCSDCR............................................. 783
SCSEMR ............................................ 865
SCSMR (SCI) ..................................... 768
SCSMR (SCIF)................................... 837
SCSPTR (SCI).................................... 781
SCSPTR (SCIF).................................. 862
SCSSR ................................................ 775
SCTDR (SCI) ..................................... 768
SCTSR (SCI) ...................................... 768
SCTSR (SCIF).................................... 835
SDBPR ............................................. 1541
SDCR.................................................. 293
SDIR ................................................. 1541
SPOER................................................ 718
SSCR2 ................................................ 906
SSCRH ............................................... 897
SSCRL................................................ 899
SSER................................................... 901
SSMR ................................................. 900
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SSRDR0 to SSRDR3 .......................... 909
SSSR ................................................... 903
SSTDR0 to SSTDR3........................... 908
SSTRSR .............................................. 910
STBCR.............................................. 1521
STBCR2............................................ 1522
STBCR3............................................ 1523
STBCR4............................................ 1525
STBCR5............................................ 1526
STBCR6............................................ 1527
SYSCR1............................................ 1529
SYSCR2............................................ 1531
TADCOBRA_4................................... 499
TADCOBRB_4................................... 499
TADCORA_4 ..................................... 499
TADCORB_4 ..................................... 499
TADCR............................................... 496
TBTER................................................ 524
TBTM ................................................. 491
TCBR .................................................. 521
TCDR.................................................. 520
TCNT .................................................. 500
TCNTCMPCLR.................................. 478
TCNTS................................................ 519
TCR..................................................... 452
TCSYSTR........................................... 505
TDDR.................................................. 520
TDER .................................................. 526
TEC................................................... 1069
TGCR.................................................. 517
TGR .................................................... 500
TICCR................................................. 493
TIER.................................................... 479
TIOR ................................................... 459
TITCNT .............................................. 523
TITCR................................................. 521
TMDR................................................. 456
TOCR1................................................ 510
TOCR2................................................ 513
TOER .................................................. 509
Page 1775 of 1778
TOLBR............................................... 516
TRWER .............................................. 508
TSR..................................................... 484
TSTR .................................................. 501
TSYCRS ............................................. 494
TSYR.................................................. 503
TWCR ................................................ 527
TXACK0 .......................................... 1075
TXCR0 ............................................. 1074
TXPR1, TXPR0................................ 1072
UMSR0............................................. 1079
USBDASTS...................................... 1366
USBDMAR ...................................... 1368
USBEPDR0i ..................................... 1358
USBEPDR0o .................................... 1358
USBEPDR0s..................................... 1359
USBEPDR1 ...................................... 1360
USBEPDR2 ...................................... 1361
USBEPDR3 ...................................... 1362
USBEPSTL....................................... 1370
USBEPSZ0o ..................................... 1362
USBEPSZ1 ....................................... 1363
USBFCLR ........................................ 1367
USBIER0.......................................... 1356
USBIER1.......................................... 1357
USBIFR0 .......................................... 1351
USBIFR1 .......................................... 1353
USBISR0 .......................................... 1354
USBISR1 .......................................... 1355
USBTRG .......................................... 1364
USDTENDRR .................................... 132
WRCSR .............................................. 752
WTCNT.............................................. 748
WTCSR .............................................. 749
Relationship between refresh requests
and bus cycles......................................... 355
Repeat transfer mode .............................. 222
Reset configuration............................... 1544
Reset state................................................. 62
Reset-synchronized PWM mode ............ 559
Page 1776 of 1778
Restoration from bank............................. 157
Restoration from stack ............................ 158
Restriction on DMAC and DTC usage ... 889
RISC-type instruction set.......................... 30
Round-robin mode .................................. 421
S
Saving to bank ........................................ 156
Saving to stack ........................................ 158
SCI interrupt sources .............................. 823
SCIF interrupt sources ............................ 887
SCIF module timing.............................. 1671
SCSPTR and SCI pins ............................ 824
SDRAM interface ................................... 322
Self-refreshing ........................................ 353
Sending a break signal .................... 827, 889
Serial communication interface (SCI)..... 763
Serial communication interface with
FIFO (SCIF)............................................ 831
Setting analog input voltage.................. 1035
Shift instructions ....................................... 56
Sign extension of word data...................... 30
Single address mode ............................... 427
Single chip mode ...................................... 64
Single-cycle scan mode......................... 1003
Slave receive operation ........................... 966
Slave transmit operation ......................... 963
Sleep mode............................................ 1533
Slot illegal instructions ........................... 112
Software protection............................... 1467
Software standby mode......................... 1534
SRAM interface with byte selection ....... 367
SSU Interrupt sources ............................. 935
SSU mode ............................................... 916
Stack after interrupt exception
handling .................................................. 148
Stack status after exception handling
ends ......................................................... 115
Stall operations ..................................... 1386
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
Standby control circuit.............................. 75
Status register (SR)................................... 24
Supported DMA transfers....................... 424
Synchronous serial communication unit
(SSU) ...................................................... 893
System control instructions....................... 58
T
T bit .......................................................... 31
TAP controller ...................................... 1543
TDO output timing ............................... 1544
Test mode settings ................................ 1080
The address map for each mailbox ....... 1043
The address map for the operating modes 65
Timing to clear an interrupt source......... 163
Transfer clock ......................................... 911
Transfer information read skip
function................................................... 220
Transfer information writeback skip
function................................................... 221
Trap instructions ..................................... 112
Types of exception handling and
priority order............................................. 95
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
U
UBC trigger timing ............................... 1663
Unconditional branch instructions with
no delay slot .............................................. 31
USB characteristics............................... 1685
USB function module ........................... 1347
User boot mode ..................................... 1461
User break controller (UBC)................... 165
User break interrupt ................................ 133
User debugging interface (H-UDI) ....... 1539
User MAT ............................................. 1412
User program mode............................... 1449
Using interval timer mode....................... 758
Using watchdog timer mode ................... 756
V
Vector base register (VBR)....................... 25
W
Wait between access cycles .................... 373
Watchdog timer (WDT) .......................... 745
Watchdog timer timing ......................... 1668
Page 1777 of 1778
Page 1778 of 1778
R01UH0229EJ0300 Rev.3.00
Mar 23, 2011
SH7280 Group, SH7243 Group User’s Manual: Hardware
Publication Date: Rev.1.00
Rev.3.00
Published by:
Jun 26, 2008
Mar 23, 2011
Renesas Electronics Corporation
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2011 Renesas Electronics Corporation. All rights reserved.
Colophon 1.1
SH7280 Group, SH7243 Group
R01UH0229EJ0300
(Previous Number:REJ09B0393-0100)