R5S72680W266FP#V0

User's Manual 32 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7268 Group, SH7269 Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series SH7268 SH7269 www.renesas.com R5S7268 R5S7269 Rev.3.00 Oct 2016 Page ii of civ Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. “Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. “High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (2012.4) Page iii of cvi General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual. • The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. • The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. • The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. • When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. • The characteristics of Microprocessing unit or Microcontroller unit products in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product. Page iv of cvi Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. States and Handling of Pins 10. Appendix • Package Dimensions, etc. 11. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 12. Index Page v of cvi Preface This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users. Refer to the SH-2A, SH2A-FPU Software Manual for a detailed description of the instruction set. Notes on reading this manual:  In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.  In order to understand the details of the CPU's functions Read the SH-2A, SH2A-FPU Software Manual.  In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 51, List of Registers. Page vi of cvi  Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and do not refer to specific data in this manual. Page vii of cvi  Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: Initial value: R/W: 15 14 ⎯ ⎯ 13 12 11 ASID2 ASID1 ASID0 10 9 8 7 6 5 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Q 3 2 1 ACMP2 ACMP1 ACMP0 0 IFE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name − − Initial Value R/W Description 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function. 10 − 0 R Reserved This bit is always read as 0. 9 − 1 R Reserved This bit is always read as 1. − 0 15 14 Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. The bit or field is readable. R: "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. The bit or field is writable. W: (5) Description Describes the function of the bit or field and specifies the values for writing. All trademarks and registered trademarks are the property of their respective owners. Page viii of cvi Main Revisions for This Edition Revised items due to the version upgrade from Rev.2.00 to Rev.3.00 Item Page Revision (See Manual for Details) Table 1.1 SH7268/7269 Features 11 Table amended Items Specification Video display : controller 4 :  Input video control Horizontal noise reduction (NR), brightness adjustment and gain adjustment using matrix operation Table 1.2 Product Lineup 16 Table amended Table 1.3 Pin Functions 26, 28 Table amended Classification Multi-function timer pulse unit 2 Symbol Function TIOC4A, The TGRA_4 to TGRD_4 input capture input/output compare output/PWM output pins. TIOC4B, TIOC4C, TIOC4D USB 2.0 host/function module REFRIN Connected to USBAPVss via 5.6-kΩ ± 1% resistance (SH7268 and SH7269 products in QFP packages). Connected to Vss via 5.6-kΩ ± 1% resistance (SH7269 products in BGA packages). Table 1.4 List of Pins 41 Table amended SH7269 Function 1 Function 2 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Symbol I/O 95 117 W16 BIAS I   Page ix of cvi Item Page Revision (See Manual for Details) Figure 1.3 (2) Simplified Circuit Diagram (TTL AND Input Buffer) 51 Figure amended PAD TTL input data TTL input enable Table 10.6 16-Bit External Device Access and Data Alignment in Big Endian 325 Table 10.9 16-Bit External Device Access and Data Alignment in Little Endian 328 Table 10.24 Number of Idle Cycles Inserted between Access Cycles to Different Memory Types 405 Table amended Operation Longword access at address 0 1st access at address 0 2nd access at address 2 Table amended Operation Longword access at address 0 1st access at address 0 2nd access at address 2 Table amended Next Cycle Byte Burst ROM MPX- SRAM Byte SRAM Burst ROM Previous Cycle SRAM (Asynchronous) I/O (BAS = 0) (BAS = 1) SDRAM PCMCIA (Synchronous) SRAM 0 0 0 0/1*1 0/1*1 0 0 1 1 0 0 1 1 0 0 0/1*1 0/1*1 Burst ROM 1 0 0 1 0 0/1* 1 1 0 1 1 0/1* (asynchronous) MPX-I/O Byte SRAM 0 0 1 0 0/1*1 0/1*1 1/2*1 0/1*1 0/1* 1 1 0/1* 1 (BAS = 0) Byte SRAM 0 0 (BAS = 1) Section 12 Abbreviations for register names 12.1 Features Section 12 All TCNT0, TCNT1, TCNT2, TCNT3, and TCNT4 have been respectively changed to TCNT_0, TCNT_1, TCNT_2, TCNT_3, and TCNT_4. 475 Description amended  25 interrupt sources Page x of cvi Item Page Revision (See Manual for Details) 12.3.23 Timer Cycle Data Register (TCDR) 542 Description amended Figure 12.20 Cascaded Operation Setting Procedure 564 12.4.8 Complementary PWM Mode 594 TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value (a value of two times TDDR + 3 or greater) as the TCDR register value. Amended [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'111 to select TCNT_2 overflow/underflow counting. Description amended In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: (2) Outline of Complementary PWM Mode Operation With dead time: TGRA_3 set value = TCDR set value + TDDR set value (g) PWM Cycle Setting TCDR set value > two times TDDR + 2 Without dead time: TGRA_3 set value = TCDR set value + 1 TCDR set value > 4 12.4.8 Complementary PWM Mode 599 If compare-match c occurs first following compare-match a, as shown in figure 12.47, compare-match b is ignored, and the negative phase is turned on by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). (2) Outline of Complementary PWM Mode Operation (j) Complementary PWM Mode PWM Output Generation Method Figure 12.46 Example of Complementary PWM Mode Waveform Output (1) Description amended 600 Amended [Before amendment] TGR3A_3 [After amendment] TGRA_3 Page xi of cvi Item Page Revision (See Manual for Details) Figure 12.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) 620 Figure amended (2)When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt TGIA_3 interrupt generation TGIA_3 interrupt generation TCNT_3 TCNT_4 Buffer register rewrite timing Buffer transferenabled period TITCR[6:4] 2 TITCNT[6:4] 0 1 2 0 1 Buffer register Data Data1 Temporary register Data Data1 General register Data Data1 Note: * The MD bits 3 to 0 = 1101 in TMDR_3, buffer transfer at the crest is selected. The skipping count is set to two. T3AEN and T4VEN are set to 1 and 0. 12.8.2 Reset Start Operation 660 Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0) 778 Page xii of cvi Description amended The output pins of this module (TIOC*) are initialized low by a power-on reset and in deep standby mode. Since the pin functions are selected using the general I/O ports, when the general I/O port is set, the pin states at that point are output to the ports. Table amended P1 (MHz) 50 Bit Rate (bits/s) n N 600 2 162 -0.15 1200 2 80 2400 1 162 -0.15 4800 1 80 9600 0 162 -0.15 60 Error (%) n 0.47 0.47 N 66.67 Error (%) n N Error (%) 2 194 0.16 2 97 1 194 0.16  97 1 108 -0.45 0 194 0.16 0 216 0.01 -0.35 -0.35 2 216 0.01 2 108 -0.45 1 216 0.01 Item Page Revision (See Manual for Details) 17.3.9 Data Control Register (SPDCR) 838 Table amended Bit 7 19.4.1 Common Control Register (CMNCR) 959 to 601 Bit Name Description TXDMY Dummy Data Transmission Enable Enables or disables dummy data transmission. When communication is performed with this bit set to 1, dummy data is transmitted from the MOSI pin and a serial communication can be performed even if there is no transmit data in the transmit buffer. Specifically, if there is no transmit data in the transmit buffer and this bit is set to 1, dummy data is transferred to the shift register. Data previously transmitted from the pin is used as dummy data. If this bit is set to 1 after the initialization and a transfer is performed, the transmitted dummy data is undefined. 0: Disables dummy data transmission. 1: Enables dummy data transmission. Note: This bit is valid only in the master mode. Table amended Bit Bit Name Description 23, 22 MOIIO3[1:0] 21, 20 MOIIO2[1:0] SPBSSL Output Idle Value Fix SPBIO3_0, SPBIO3_1 Fixes output values of SPBIO3_0 and SPBIO3_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z SPBSSL Output Idle Value Fix SPBIO2_0, SPBIO2_1 Fixes output values of SPBIO2_0 and SPBIO2_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z Page xiii of cvi Item Page 19.4.1 Common Control Register (CMNCR) 959 to 601 Page xiv of cvi Revision (See Manual for Details) Bit Bit Name Description 19, 18 MOIIO1[1:0] 17, 16 MOIIO0[1:0] 15, 14 IO3FV[1:0] 13, 12 IO2FV[1:0] SPBSSL Output Idle Value Fix SPBIO1_0, SPBIO1_1 Fixes output values of SPBIO1_0 and SPBIO1_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z SPBSSL Output Idle Value Fix SPBIO0_0, SPBIO0_1 Fixes output values of SPBIO0_0 and SPBIO0_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z SPBIO3_0, SPBIO3_1 Fixed Value for 1bit/2-bit Size Fixes the output value of SPBIO3_0 and SPBIO3_1 pins for 1-bit/2-bit size. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z SPBIO2_0, SPBIO2_1 Fixed Value for 1bit/2-bit Size Fixes the output value of SPBIO2_0 and SPBIO2_1 pins for 1-bit/2-bit size. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z Item Page 19.4.1 Common Control Register (CMNCR) 959 to 601 19.4.4 Data Read Control Register (DRCR) 968 19.4.14 SPI Mode Read Data Register 0 (SMRDR0) 986 Revision (See Manual for Details) Bit Bit Name Description 9, 8 IO0FV[1:0] SPBIO0_0, SPBIO0_1 Fixed Value for 1-bit Size Input Fixes the output value of SPBIO0_0 and SPBIO0_1 pins for 1-bit size input. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is HiZ, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z Description amended The bits should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Description amended SMRDR0 is a 32-bit register that stores the read data in SPI operating mode. Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. 19.4.15 SPI Mode Read Data Register 1 (SMRDR1) 987 Description amended This register is enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected). Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. 19.4.16 SPI Mode Write Data Register 0 (SMWDR0) 988 Description amended SMWDR0 is a 32-bit register that sets the write data in SPI operating mode. Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. Page xv of cvi Item Page Revision (See Manual for Details) 19.4.17 SPI Mode Write Data Register 1 (SMWDR1) 989 Description amended This register is enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected). Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. Table 19.8 Pin Status (2) 1017 Table amended Transfer Data External Address Space Read Operation SPI Operation SPIRE Bit = 1, SPIWE Bit = 0 Table 19.9 Pin Status (3) 1017 Pin 1-bit Size 2-bit Size 4-bit Size 1-bit Size 2-bit Size 4-bit Size SPBIO2_0, SPBIO2_1 IO2FV bit IO2FV bit value Input IO2FV bit IO2FV bit Input value value SPBIO3_0, SPBIO3_1 IO3FV bit IO3FV bit value Input IO3FV bit IO3FV bit value value value value Input Table amended Transfer Data SPI Operation SPIRE Bit = 0, SPIWE Bit = 1 21.5.1 Limitations from Underflow or Overflow during DMA Operation Page xvi of cvi 1113 SPIRE Bit = 1, SPIWE Bit = 1 Pin 1-bit Size 2-bit Size 4-bit Size 1-bit Size 2-bit Size 4-bit Size SPBIO2_0, SPBIO2_1 IO2FV bit IO2FV bit value Output IO2FV bit Setting prohibited Setting prohibited SPBIO3_0, SPBIO3_1 IO3FV bit IO3FV bit value Output Setting prohibited Setting prohibited value value value IO3FV bit value Description added After this, if reception had been in progress, write 0 to the error status flag bit to clear the error status, set the direct memory access controller again and restart the transfer. For transmission, issue a software reset and execute the procedure to start again. Item Page Revision (See Manual for Details) 21.5.3 Limits on TDM mode and WS Continue Mode 1113, 1114 Description added If TDM mode or WS continue mode setting is changed, the operation of the SSISCK and SSIWS signals immediately after switching are not guaranteed. If it affects the device to be connected, do not change the setting dynamically. To temporarily halt and restart transmission while the WS continue mode is enabled (SSITDMR.CONT = 1), after writing to the transmit FIFO data register (SSIFTDR) a multiple of two times, use the transmit underflow error interrupt or the corresponding error status flag (SSISR.TUIRQ) to confirm that an error has occurred, and then write 0 to the TEN bit of the SSISCR register. Note that after the transmit underflow error, the last value written to SSIFTDR will be repeatedly sent as long as SSISCR.TEN = 1. Therefore, write a dummy value as the last data for transmission or mute the signal by writing 1 to the MUEN bit of the SSISCR register. To restart transmission, do not apply a software reset; after writing 0 to the error status flag bit to clear it, use the idle mode status flag (SSISR.IDST) to confirm that this module is in the idle state, and then write 1 to the TEN bit of the SSISCR register. 26.3.6 Decoding Option Setting Control Register (CROMCTL4) 1384 Bit table amended Bit: Initial value: R/W: 7 6 5 - LINK2 - 0 R/W 0 R/W 0 R/W 4 3 ER0SEL NO_ECC 0 R/W 0 R/W 2 1 - - 0 - 0 R/W 0 R/W 0 R/W Page xvii of cvi Item Page Revision (See Manual for Details) 26.3.6 Decoding Option Setting Control Register (CROMCTL4) 1385 Table amended Bit 26.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5) 1391 26.3.41 Automatic Buffering Setting Control Register 0 (CBUFCTL0) 1408 Description 7  6 LINK2 Reserved The write value may be 0 or 1. When read, this bit has the value previously written to it. Link Block Detection Condition 0: The block is regarded as a link block when either run-out 1 or 2 and both run-in 3 and 4 have been detected. 1: The block is regarded as a link block when two out of run-out 1 and 2 and “link” have been detected. When this bit is set to 1, buffering control for link blocks is disabled (link blocks are processed as normal sectors). The condition for setting of the LINK_ON bit in CROMST5 is decoding of the link sector. Table amended Bit 3 Bit Name Description LINK_ON This bit is set to 1 when a link block was recognized in link block determination. For the criteria for link block determination, refer to the LINK2 bit in the CROMCTL4 register. When this bit is set to 1, buffering control is performed according to the setting of the CBUF_LINK bit in the CBUFCTL0 register. Bit table amended Bit: 7 6 5 CBUF_ AUT CBUF_ EN - 0 R/W 0 R/W 0 R/W Initial value: R/W: 1409 Page xviii of cvi Bit Name 2 1 0 CBUF_MD[1:0] 4 3 CBUF_ TS CBUF_ Q - 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W Table amended Bit Bit Name Description 5  Reserved This bit is always read as 0.The write value should always be 0. Item Page Revision (See Manual for Details) 26.6.3 Link Blocks 1435 Description amended Forcibly stop decoding, set the CROMSY0 register to place the decoder in external sync mode, and retry decoding by specifying the MSF value stored above + 7 as the MSF value for the target sector. The start sector address will be the address where RUN_OUT is stored + 7 when CBUF_LINK = 0, and the address where RUN_OUT is stored when CBUF_LINK = 1. 28.1 Features 1465 28.3.1 Common Control Register (FLCMNCR) Note added  Sector access mode*: Performs a read or write in sector units by specifying a sector address. By specifying the number of sectors, the continuous physical sectors can be read or written. (2) Access Modes: This module can select one of the following two access modes. Note: * The controller of this LSI chip is not capable of reading data in sector access mode. 1471, 1472 Table amended Bit Bit Name Description 11, 10 ACM[1:0] Access Mode Specification 1 and 0 Specify access mode. 00: Command access mode 01: Sector access mode* 10: Setting prohibited 11: Setting prohibited Note: * The controller is not capable of reading data in sector access mode. 28.3.6 Data Counter Register (FLDTCNTR) 1480 Table amended Bit 11 to 0 Bit Name Description DTCNT Data Count Specification Specify the number of bytes of data to be read or written in command access mode. (Up to 2048 + 64 bytes can be specified for writing, and up to 128 bytes for reading.) [11:0] 29.1 Features (5) Pipe Configuration 1510 Description amended  Transfer conditions that can be set for each pipe: PIPE0: Control transfer (default control pipe: DCP), 256-byte fixed single buffer Page xix of cvi Item Page Revision (See Manual for Details) Table 29.1 USB Pin Configuration 1511 Table amended Category Reference resistor 29.3.28 DCP Configuration Register (DCPCFG) 1582, 1583 Name Function Reference input Reference resistor connection pin This pin should be connected to USBAPVss through a 5.6 kΩ ±1% resistor (SH7268 and SH7269 products in QFP packages). This pin should be connected to Vss through a 5.6 kΩ ±1% resistor (SH7269 products in BGA packages). Bit table amended Bit: 15 14 13 12 11 10 9 — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 CNTMD SHTNAK 0 R/W 0 R/W 6 5 4 3 2 1 0 — — DIR — — — — 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Table amended Bit Initial Bit Name Value 15 to 9  All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 8 CNTMD 0 R/W Continuous Transfer Mode Specifies whether the DCP operates in continuous transfer mode or not. 0: Non-continuous transfer mode 1: Continuous transfer mode Change the setting of this bit only when CSSTS = 0 and PID = NAK, and no pipe has been selected using the CURPIPE bits. When changing the setting of this bit after USB communication using the DCP, write 1 to BCLR and clear the FIFO buffer assigned to the DCP in addition to ensuring that the above three registers are in the states indicated. Before changing the setting of this bit after changing the DCP’s PID bit from BUF to NAK, confirm that the values of CSSTS and PBUSY are 0. However, it is not necessary for this module to confirm the state of the PBUSY bit if the value of the PID bit has already been changed to NAK. Page xx of cvi Item Page 29.3.28 DCP Configuration Register (DCPCFG) 1583 Revision (See Manual for Details) Bit Initial Bit Name Value R/W Description 7 SHTNAK 0 R/W Disable Pipe when Transfer Finishes Specifies whether the PID bit is changed to NAK when a transfer finishes while the DCP is operating in the receive direction. 0: Continue using pipe after transfer finishes. 1: Disable pipe when transfer finishes. When this bit is set to 1, this module changes the PID bit corresponding to the DCP to NAK when it determines that a transfer to the DCP has finished. This module determines that a transfer has finished when a short packet of data (or a zero-length packet) is received successfully. Change the setting of this bit only when CSSTS = 0 and PID = NAK. Before changing the setting of this bit after changing the DCP’s PID bit from BUF to NAK, confirm that the values of CSSTS and PBUSY are 0. However, it is not necessary for this module to confirm the state of the PBUSY bit if the value of the PID bit has already been changed to NAK. 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Table 29.13 Operation of This Module depending on PID Setting (when Function Controller Function is Selected) 1622 Table amended PID 00 (NAK) Transfer Type Bulk or interrupt Transfer Direction Operation of This Module (DIR Bit) Operation does not Returns NAK in response to the depend on the setting. token from the USB host. For the operation when ATREPM is 1, refer to the description of the ATREPM bit. Page xxi of cvi Item Page Revision (See Manual for Details) 29.4.1 System Control and Oscillation Control 1639 Description added This module incorporates a pull-up resistor for the D+ signal and a pull-down resistor for the D+ and D- signals. These signals can be pulled up or down using the DPRPU and DRPD bits in SYSCFG. (4) USB Data Bus Resistor Control When the function controller function is selected, set the DPRPU bit in the SYSCFG register to 1 and pull up the D+ signal after recognizing a connection to the USB host. When disconnection of the USB host is recognized, manipulate the DPRPU and DCFM bits as follows: (1) Clear the DPRPU bit to 0. (2) Wait a minimum of 1 s. (3) Set the DCFM bit to 1. (4) Wait a minimum of 200 ns. (5) Clear the DCFM bit to 0. Table 29.17 Pipe Setting Items 1667 Table amended Register Name DCPCFG PIPECFG Bit Name CNTMD SHTNAK 29.4.3 Pipe Control (1) Pipe Control Register Switching Procedures Page xxii of cvi 1670 Remarks DCP: Can be set PIPE1 and PIPE2: Can be set (only when bulk transfer has been selected). PIPE3 to PIPE5: Can be set DCP: Can be set PIPE1 and PIPE2: Can be set (only when bulk transfer has been selected) PIPE3 to PIPE5: Can be set Note added 4. Wait until the corresponding PBUSY bit is cleared to 0. Note: The PBUSY bit may remain set to 1 if the device is detached while USB transaction processing is in progress. Item Page Revision (See Manual for Details) 29.4.4 FIFO Buffer Memory 1676 Description deleted and amended Figure 29.9 shows an example of a FIFO buffer memory map for this module. The FIFO buffer memory is an area shared by the CPU and this module. In the FIFO buffer memory status, there are times when the access right to the buffer memory is allocated to the user system (CPU side), and times when it is allocated to this module (SIE side). (1) FIFO Buffer Memory Allocation The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise one block, and the memory areas are set using the first block number of the number of blocks (specified using the BUFNMB and BUFSIZE bits in PIPEBUF). Independent buffer memory areas should be set for each pipe. Each memory area can be set using the first block number and the number of blocks (specified using the BUFNMB and BUFSIZE bits in PIPEBUF), where one block comprises 64 bytes. When continuous transfer mode has been selected using the CNTMD bit in PIPECFG, the BUFSIZE bits should be set so that the buffer memory size should be an integral multiple of the maximum packet size. When double buffer mode has been selected using the DBLB bit in PIPECFG, two planes of the memory area specified using the BUFSIZE bits in PIPEBUF can be assigned to a single pipe. 29.4.4 FIFO Buffer Memory 1677 (1) FIFO Buffer Memory Allocation (a) Buffer Status 29.4.4 FIFO Buffer Memory (1) FIFO Buffer Memory Allocation (e) Buffer Memory Specifications (Single/Double Setting) Description amended Tables 29.18 and 29.19 show the buffer status. The buffer memory status can be confirmed using the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. The access direction for the buffer memory can be specified using either the DIR bit in PIPECFG or the ISEL bit in CFIFOSEL (when DCP is selected). 1680 Description amended Either a single or double buffer can be selected for PIPE1 to PIPE5, using the DBLB bit in PIPECFG. The double buffer is a function that assigns two memory areas specified with the BUFSIZE bit in PIPEBUF to the same pipe. Figure 29.10 shows an example of buffer memory settings for this module. Page xxiii of cvi Item Page Revision (See Manual for Details) 29.4.4 FIFO Buffer Memory 1681 Description amended Either the continuous transfer mode or the non-continuous transfer mode can be selected, using the CNTMD bit in DCPCFG and PIPECFG. This selection is valid for DCP and PIPE1 to PIPE5. (1) FIFO Buffer Memory Allocation (f) Buffer Memory Operation (Continuous Transfer Setting) Table 29.22 Relationship between Transfer Mode Settings by CNTMD Bit and Timings at which Reading Data or Transmitting Data from FIFO Buffer is Enabled 1682 Table amended Continuous or NonContinuous Transfer Mode Method of Determining if Reading or Transmitting Data is Enabled Non-continuous transfer In the receiving direction (DIR = 0), reading data from the FIFO buffer is enabled when: (CNTMD = 0)  This module receives one packet. In the transmitting direction (DIR = 1), transmitting data from the FIFO buffer is enabled when:  In the transmitting direction (DIR = 1), transmitting data from the FIFO buffer is Data of the maximum packet size is written to the FIFO buffer. or  Continuous transfer (CNTMD = 1) Data of the short packet size (including 0-byte data) is written to the FIFO buffer and then writes 1 to BVAL. In the receiving direction (DIR = 0), reading data from the FIFO buffer is enabled when:  The number of the data bytes received in the FIFO buffer assigned to the selected pipe becomes the same as the number of assigned data bytes (DCP: fixed at 256 bytes, pipes 1 to 5 (BUFSIZE + 1)  64).  This module receives a short packet other than a zero-length packet.  This module receives a zero-length packet when data is already stored in the FIFO buffer assigned to the selected pipe. or  This module receives the number of packets equal to the transaction counter value specified for the selected pipe (PIPE1 to PIPE5 only). In the transmitting direction (DIR = 1), transmitting data from the FIFO buffer is enabled when:  The number of the data bytes written to the FIFO buffer becomes the same as the number of data bytes in a single FIFO buffer plane assigned to the selected pipe. or Page xxiv of cvi  The number of data bytes less than the size of a single FIFO buffer plane (including 0-byte data) assigned to the selected pipe is written to the FIFO buffer and then 1 is written to BVAL.  In a DMA transfer, the DMA transfer end sampling enable (TENDE) bit is set to 1, a number of data bytes less than the size of a single FIFO buffer plane assigned to the selected pipe (or 0 bytes) is written to the FIFO buffer and the DMA transfer end signal is received when the last byte is written (PIPE1 to PIPE5 only). Item Page Revision (See Manual for Details) 29.4.4 FIFO Buffer Memory 1685 Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory access direction conforms to the DIR bit in PIPECFG. The ISEL bit determines this only for the (2) FIFO Port Functions DCP. (a) FIFO Port Selection Figure 29.19 Relationship between (µ) Frames and Expected Token Reception when IITV = 1 1705 Figure amended USB bus PID bit setting Token S O F S O F S O F NAK BUF Token Token reception reception is not waited is not waited O U T D A T A 0 BUF Token reception is waited S O F S O F BUF O U T S O F S O F D A T A 0 BUF Token Token reception reception is not waited is waited O U T D A T A 0 BUF BUF Token reception is not waited Token reception is waited Interval counter started Figure 30.5 Example of Vertical Active Image Period (59.94 Hz (525i)) 1727 Figure amended 266 is not included 265 266 267 268 269 270 271 272 273 SRCTOP(5:0) = 18 [lines] SRCTOP(5:0) = 24 [lines] 30.4.14 Digital Clamp Control Register 1 (DCPCR1) 1752 Description amended 3. Set clamp offset level of the signal to be monitored to Min value (−512 for BLANKLEVEL_Y, (−32 for BLANKLEVEL_CB/CR). (2) Digital Clamp Pulse Position Check Control Figure 30.15 Digital Clamp Timing (Horizontal) 1760 Figure amended DCPPOS_Y/C  27 (usec) DCPWIDTH  27 (usec) Horz. Sync Clamp Pulse Video Signal colorburst synctip Page xxv of cvi Item Page Revision (See Manual for Details) 30.4.23 Burst Lock/Chroma Decoding Control Register (BTLCR) 1765 Title amended and description amended DEFAULTSYS sets the default color system when automatic judgement of the color system for use in chroma decoding is not possible. (5) Default Color System during Chroma Decoding Table 30.15 Default Color System 30.4.25 ACC Control Register 1 (ACCCR1) 1765 Table title amended Table amended 1772 DEFAULTSYS Default Color System 0 NTSC 1 PAL 2 SECAM 3 Not specified Description amended ACCLEVEL sets the burst amplitude of the chroma signal after gain correction. ACCLEVEL is valid only when ACCMODE = 0. (4) ACC Level Control Figure 30.20 Example of R-Y Axis Correction 1777 Figure amended R-Y Axis offset +11.25 [deg.] (Max: +11.25 [deg.]) Normal (Center) R-Y R-Y Axis offset 11.25 [deg.] (Max: 11.25 [deg.]) R-Y R-Y Red Yellow Magenta B-Y B-Y Green 11.25 deg. Blue Cyan 11.25 [deg.] < Axis < 11.25 [deg.] Page xxvi of cvi B-Y 11.25 deg. Item Page Revision (See Manual for Details) Figure 30.21 Example of Hue Adjustment (TINT) Correction 1778 Figure amended +45 [deg.] (Max: +180 [deg.]) 45 [deg.] (Max: 180 [deg.]) Normal (Center) R-Y R-Y R-Y Red Yellow Magenta B-Y B-Y Green 45deg. Blue Cyan B-Y 45deg. 180 [deg.]  HUE  +180 [deg.] 30.4.62 Chroma Filter TAP Coefficient (WA_F0 to WA_F8) Registers for Y/C Separation (YCTWA_F0 to YCTWA_F8) 1831 Description amended FIL2_2D_WA_F0 to FIL2_2D_WA_F8[12:0] control twodimensional cascade broadband (3.58/4.43/SECAMDR)/TAKEOFF filter TAP coefficient 0 to 8. (1) TwoDimensional Cascade Broadband (3.58/4.43/SECAMDR)/TAKE-OFF Filter TAP Coefficient 0 to 8 Control Page xxvii of cvi Item Page Revision (See Manual for Details) 30.4.63 Chroma Filter TAP Coefficient (WB_F0 to WB_F8) Registers for Y/C Separation 1833 Description amended FIL2_2D_WB_F0 to FIL2_2D_WB_F8[12:0] control twodimensional cascade broadband (SECAM-DB) filter TAP coefficient 0 to 8. (YCTWB_F0 to YCTWB_F8) (1) Two-Dimensional Cascade Broadband (SECAM-DB) Filter TAP Coefficient 0 to 8 Control 30.4.64 Chroma Filter TAP Coefficient (NA_F0 to NA_F8) Registers for Y/C Separation (YCTNA_F0 to YCTNA_F8) 1835 Description amended FIL2_2D_NA_F0 to FIL2_2D_NA_F8[12:0] control twodimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient 0 to 8. (1) Two-Dimensional Cascade Narrowband (3.58/4.43/SECAMDR) Filter TAP Coefficient 0 to 8 Control 30.4.65 Chroma Filter TAP Coefficient (NB_F0 to NB_F8) Registers for Y/C Separation (YCTNB_F0 to YCTNB_F8) (1) Two-Dimensional Cascade Narrowband (SECAM-DB) Filter TAP Coefficient 0 to 8 Control Page xxviii of cvi 1837 Description amended FIL2_2D_NB_F0 to FIL2_2D_NB_F8[12:0] control twodimensional cascade narrowband (SECAM-DB) filter TAP coefficient 0 to 8. Item Page Revision (See Manual for Details) 30.5.3 Sync Separator Circuit 1855 Description added The phases of the Hsync and Vsync signals are adjusted according to the result of detecting the field, and output of the Vsync signal from the sync separator circuit is delayed by one horizontal period. When having video display controller 4 capture the output signal from this module, take the above delay into consideration and set SCL0_DS2.RES_VS (vertical position setting for video signal capturing) as follows. (10) Timing Adjustment and Signal Detection Block VSYNC + (V backporch - 2) lines Figure 30.31 Block Diagram of Y/C Separator Circuit 1857 Figure amended (1) (2) Horizontal and vertical filter Line delay Video signal (3) (4) 3 lines Table 30.40 Recommended Settings for TwoDimensional Y/C Filters (SECAM) 1866 (7) Horizontal (6) (5) Y (9) /vertical value Y Over-range Horizontal Correlation and vertical detection generation processing C signal signal mixing value mixing C signal for Y generation Horizontal and vertical correlation detection Correlation value Correlation detection filter Correlation detection value C (8) Cascade filter SECAM C SECAM Cascade Filter Bypass 1873 Y for Y generation Table amended Bit Name Table 30.41 Recommended Setting Common to Various Color Formats Horizontal /vertical value Operation Cascade Filter TAKE-OFF 1 Stage 2 Stages Filter TAKE-OFF Bypass Bit Name Operation 1 Stage 2 Stages Filter Table amended Register Bit Recommended Value (Decimal) DCPCR5 DCPEND 2 RGORCR1 RADJ_O_LEVEL0 928 RGORCR2 RADJ_U_LEVEL0 32 RGORCR5 RADJ_O_LEVEL2 992 RGORCR6 RADJ_U_LEVEL2 64 Page xxix of cvi Item Page Revision (See Manual for Details) Table 30.42 Recommended Setting for Each Color Format 1877 Table amended NTSC-443 (60 Hz) PAL-60 256 16 241 1428 256 16 241 1428 692 792 592 692 792 592 NOVCD60 VCDDEFAULT VCDWINDOW VCDOFFSET 1 0 2 30 15 1 0 2 30 15 DEFAULTSYS NONTSC358 NONTSC443 NOPALM NOPALN NOPAL443 NOSECAM 0 1 0 1 1 1 1 1 1 1 1 1 0 1 ACC level setting ACCCR1 ACCLEVEL 220 230 AGC level setting AGCCR1 AGCLEVEL 230 242 Register Bit Capturing position setting TGCR1 SRCLEFT TGCR2 SRCTOP SRCHEIGHT TGCR3 SRCWIDTH Horizontal AFC setting HAFCCR1 HAFCTYP HAFCCR2 HAFCMAX HAFCCR3 HAFCMIN Vertical countdown setting VCDWCR1 NOVCD50 BCO setting BTLCR Page xxx of cvi Item Page Revision (See Manual for Details) Table 30.42 Recommended Setting for Each Color Format 1878 Table amended NTSC-443 (60 Hz) PAL-60 2 8 4 3 16 8 32 6 8 6 6 3 5 1 6 6 0 0 2 8 3 4 63 2 32 10 15 10 3 3 8 0 0 0 0 0 DET2_MIX_Y 2 0 FIL2_MODE_2D 1 0 FIL2_NARROW_2D 1 1 Register Bit Y/C separation setting YCSCR3 K15 K13 K11 YCSCR4 K16 K14 K12 YCSCR5 K22A K21A YCSCR6 K22B K21B YCSCR7 K23B K23A K24 YCSCR9 DET2_ON HSEL_MIX_Y VSEL_MIX_Y HVSEL_MIX_Y YCSCR12 DET2_MIX_C Page xxxi of cvi Item Page Revision (See Manual for Details) Figure 32.5 BT601 Vertical Timing (625 Lines/50.00 Hz) 1901 Figure amended TOP (First) field Quoted from ITU-R BT.470-6 25H +  2.5H 622 623 2.5H 624 625 1 2 0V BOTTOM field 2.5H 3 4 5 6 7 23 24 TOP field HS VS FLD BOTTOM (Second) field 25H +  2.5H 309 310 311 2.5H 312 313 314 0V TOP field 2.5H 315 316 317 318 319 320 336 337 BOTTOM field HS VS FLD Figure 32.6 BT601 Vertical Timing (525 Lines/59.94 Hz) 1903 Figure amended TOP (First) field Quoted from ITU-R BT.470-6 19 to 21H +  3.0H 525 BOTTOM field 1 2 0V 3.0H 3 4 3.0H 5 6 7 8 9 10 21 22 TOP field HS VS FLD BOTTOM (Second) field 19 to 21H +  3.0H 262 TOP field HS VS FLD Page xxxii of cvi 263 0V 264 3.0H 265 266 BOTTOM field 267 3.0H 268 269 270 271 272 273 283 284 Item Page Revision (See Manual for Details) Table 32.16 YCbCr/RGB Signal Reception Timing 1912 Table amended Item Description Vertical valid period start position (V_BP) From Vsync reference to the head of the video image: 5 lines or more From the end of the video image to the Vsync 1 reference: 4 lines or more* From the end of the video image to the Hsync 2 reference: 16 CLK or more* Between vertical synchronization signals: 2047 lines or less Between horizontal synchronization signals: 2047 CLK or less Vertical valid period end position (V_FP) Horizontal valid period end position (H_FP) Number of vertical lines (V_BP+V_ACTIVE+V_FP) Number of horizontal pixels (H_BP+H_ACTIVE+H_FP) Notes: 1. When V_FP is below 4 lines, the setting of INP_DLY_ADJ.INP_VS_DLY_L[2:0] should be adjusted so that V_FP is at least 4 lines. 2. When H_FP is below 16 CLK, the settings of INP_DLY_ADJ.INP_VS_DLY[7:0], INP_HS_DLY[7:0], and INP_ FLD_DLY[7:0] should be adjusted so that H_FP is at least 16 CLK. Table 33.7 Control of Image Area to be Captured 1961 33.1.4 Setting Angle of View 1962 (2) Generating a Full-Screen Enable Signal Table amended Register Bit Name Name Description SCL0_DS2 RES_VS[10:0] Vertical Position Setting for Video Signal Capturing (VSYNC + (V backporch - 1) lines) Note: The set value should be four or more (lines). RES_VS + RES_VW should be equal to or less than 2039 (lines). Description amended The vertical front porch should be set to four or more lines, and the horizontal front porch should be 16 or more clock cycles. Page xxxiii of cvi Item Page Revision (See Manual for Details) Table 33.8 FullScreen Enable Control 1962 Table amended Register Name Bit Name SCL0_FRC7 RES_F_HW [10:0] Description Horizontal Enable Signal Width for Full Screen (pixel-clock cycles) Notes: 1. RES_F_HS + RES_F_HW should be equal to or less than 2015 (clock cycles). 2. The set value should be equal to (horizontal signal width for full screen + 2) when serial RGB output is selected as an LCD output signal. Figure 33.8 Enable Settings 1964 Figure amended Setting the area of input image to be captured Input Vsync signal Input Hsync signal RES_HS RES_HW RES_VS +1 Image area to be captured RES_VW Page xxxiv of cvi Item Page Revision (See Manual for Details) Table 33.15 Vertical Scale Down Control 1972 Table amended Table 33.20 Settings for Field Determination Signal Control 1980 Register Name SCL0_DS7 Bit Name RES_OUT_V W[10:0] Table amended Input Signal Rotation Progressive  Interlace Normal Horizontal mirroring 180° rotation 90° rotation 270° rotation 33.1.11 IP Conversion (3) Switching of the Field Determination Signal (R version only) 1981 Description Number of Valid Lines in Vertical Direction Output by Scaling-Down Control Block (lines) This bit setting is used for the number of lines to be written to the frame buffer. When SCL1_WR1.RES_LOOP is 0 (frame write mode), these bits specify the number of lines for one frame. When SCL1_WR1.RES_LOOP is 1 (line write mode), these bits specify the number of lines for writing in a ring configuration. Vertical Processing  Vertical scale down Vertical scale up Frame Buffer   One plane or less Two planes or more (Horizontal input  → vertical output) scale down (Horizontal input Two planes or more → vertical output) scale up RES_FLD_ DLY_SEL   0 1  1 Newly added (3) Switching of the Field Determination Signal (R version only) The source of the field determination signal to be output to the scaling-up control block can be switched. Page xxxv of cvi Item Page Revision (See Manual for Details) Table 33.22 Switching the Field Determination Signal 1981 Table added Table 33.29 Frame Buffer Transfer Mode 1987 Register Initial Name Bit Name Value Description SCL0_ FRC8 RES_US_ 0 FLD Table amended Register Name SCL1_WR1 Table 33.30 Frame Buffer Writing Control 1987 Register Name (4) Frame Buffer Write Addresses 1988 Bit Name Description RES_BST_MD Transfer Burst Length for Frame Buffer Writing 0: 32-byte transfer (4 bursts) 1: 128-byte transfer (16 bursts) Table amended SCL1_WR5 33.1.16 Writing to Frame Buffer Field Determination Signal Switching 0: The field determination signal is generated by the synchronization control block. 1: Frame number to be read (0: top field, 1: bottom field) Note: When RES_FLM_MD is 0, set this bit to 0. Bit Name RES_WENB Description Frame Buffer Write Enable After making the setting to enable writing, writing starts from the second frame. 0: Frame buffer writing is disabled. 1: Frame buffer writing is enabled. Description added Frame buffer addresses are specified using the base address, line offset address, frame offset address, data size of a line, and the number of lines in a frame. The frame buffer address generation mode is selectable (R version only). Page xxxvi of cvi Item Page Revision (See Manual for Details) Table 33.32 Frame Buffer Write Address Control 1989 Table amended Figure 33.14 Data Arrangement in Frame Buffer 1990 Register Initial Bit Name Value Name SCL1_ RES_ 0 WR1 FLM_MD Description Frame Buffer Address Generation Mode Select 0: RES_BASE + RES_FLM_OFF  frame number 1: RES_BASE + RES_FLM_OFF  field information (top field: 0; bottom field: 1) Note: This bit should be set to 0 when a progressive signal is being input. When the setting of this bit is 1, the setting for frame buffers should be for the use of two. This bit is only provided in the R version. In products other than the R version, this bit is always read as 0, and when writing, the value written should always be 0. Figure amended Input Vsync signal Input Hsync signal RES_HS RES_HW RES_VS +1 Image area to be captured RES_VW Table 33.33 Frame Buffer Write Control 1992 Table amended Register Name SCL1_WR7 Bit Name RES_FLM_ CNT[9:0] Description Frame Number of Frame Immediately Before That Currently Being Accessed Page xxxvii of cvi Item Page Revision (See Manual for Details) Table 33.37 Register Configuration of the Scaler 1996 Table amended 33.2.8 Full-Screen Horizontal Size Register (SCL0_FRC7) 2007 Initial Value Access Address Size Name Abbreviation R/W Full-screen horizontal size register SCL0_FRC7 R/W H'0090 H'FFFF 0280 751C 32/16 Field determination signal switching register (R version only) SCL0_FRC8 R/W H'0000 H'FFFF 0011 7520 32/16 Vsync detection register SCL0_FRC9 R H'0000 H'FFFF 0000 7524 32/16 Table amended Bit Bit Name Description 10 to 0 RES_F_HW Horizontal Enable Signal Width for Full Screen (pixelclock cycles) [10:0] Notes: 1. RES_F_HS + RES_F_HW should be equal to or less than 2015 (clock cycles). 2. The set value should be equal to (horizontal signal width for full screen + 2) when serial RGB output is selected as an LCD output signal. 33.2.9 Field Determination Signal Switching Register (SCL0_FRC8) (R version only) 2008 Newly added 33.2.12 Vertical Capture Size Register (SCL0_DS2) 2011 Table amended Page xxxviii of cvi Bit 26 to 16 Bit Name RES_VS [10:0] Description Vertical Position Setting for Video Signal Capturing (VSYNC + (V backporch – 1) lines) Note: The set value should be four or more (lines). RES_VS + RES_VW should be equal to or less than 2039 (lines). Item Page Revision (See Manual for Details) 33.2.16 Vertical Scaling Register (SCL0_DS6) 2015 Note amended 33.2.17 ScalingDown Control Block Output Size Register (SCL0_DS7) 2016 33.2.25 Frame Buffer Read Select Register (SCL0_US8) 2024 Note: These bits updated when the SCL0_VEN_A and SCL0_VEN_B bits in the SCL0 register update control register (SCL0_UPDATE) are 1. Accordingly, even a scaled-up graphics display requires both an input Vsync signal and output Vsync signal. Table amended Bit 26 to 16 Bit Name Description RES_OUT Number of Valid Lines in Vertical Direction _VW[10:0] Output by Scaling-down Control Block (lines) This bit setting is used for the number of lines to be written to the frame buffer. When SCL1_WR1.RES_LOOP is 0 (frame write mode), specify the number of lines for one frame. When SCL1_WR1.RES_LOOP is 1 (line write mode), specify the number of lines for repeated write. Note: The RES_OUT_VW value should be aligned in 4-line units and equal to or smaller than the RES_VW value. Note amended RES_IBUS_SYNC_SEL is updated when the values of the SCL0_VEN_B and SCL0_VEN_D bits in the SCL0 register update control register (SCL0_UPDATE) are both 1. RES_DISP_ON is updated when the value of the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page xxxix of cvi Item Page Revision (See Manual for Details) 33.2.28 Writing Mode Register (SCL1_WR1) 2027, 2028 Bit table amended 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2        RES_FLM _MD  -RES_DS_WR_MD[2:0] - Bit: - RES_MD[1:0] 1 0 RES_ LOOP RES_ BST_MD Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R R/W R/W R/W R/W R/W R/W R/W Table amended Bit Initial Bit Name Value 31 to 9  All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 8 RES_FL 0 R/W M_MD Frame Buffer Address Generation Mode Select 0: RES_BASE + RES_FLM_OFF × frame number 1: RES_BASE + RES_FLM_OFF × field information (top field: 0; bottom field: 1) Note: This bit should be set to 0 when a progressive signal is being input. When the setting of this bit is 1, the setting for frame buffers should be for the use of two. This bit is only provided in the R version. In products other than the R version, this bit is always read as 0, and when writing, the value written should always be 0. 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 RES_BS 0 R/W T_MD Transfer Burst Length for Frame Buffer Writing 0: 32-byte transfer (4 bursts) 1: 128-byte transfer (16 bursts) Note: RES_FLM_MD, RES_LOOP, and RES_BST_MD are updated when the SCL1_VEN_B bit in the SCL1 register update control register (SCL1_UPDATE) is 1. RES_DS_WR_MD and RES_MD are updated when the SCL1_VEN_A and SCL1_VEN_B bits in the SCL1 register update control register (SCL1_UPDATE) are 1. Page xl of cvi Item Page Revision (See Manual for Details) 33.2.32 Frame Sub-Sampling Register (SCL1_WR5) 2034 Table amended 33.2.34 Write Detection Register (SCL1_WR7) 2036 33.3.1 Scaling Setting Example for 525i Video Input and VGA-Size (640  480) Video Output 2058 Section title amended Table 33.38 Input and Output Angles for 525i Video Input and VGA-Size (640  480) Video Output 2058 Table title amended 33.3.1 Scaling Setting Exa mple for 525i Video Input and VGA-Size (640  480) Video Output 2058 Bit 0 Bit Name RES_ WENB Description Frame Buffer Write Enable After making the setting to enable writing, writing starts from the second frame. 0: Frame buffer writing is disabled. 1: Frame buffer writing is enabled. Table amended Bit 9 to 0 Bit Name Description RES_FLM Frame Number of Frame Immediately Before _CNT[9:0] That Currently Being Accessed Table amended Input Signal Output Signal Signal Format 1440 × 240 640 × 480 YCbCr Description amended RATIO_org = round (1440 ÷ 640 × 4096) = 9216  = (9216 × (640 − 1) − (1440 − 1) × 4096) ÷ (640 − 1) = −8.01 Horizontal scaling ratio = round (9216 − (−8.01)) = 9225 (2) Horizontal Scaling (Horizontal Scale Down, Scaling Filter: 2Tap Linear) Page xli of cvi Item Page Revision (See Manual for Details) 33.3.1 Scaling Setting Example for 525i Video Input and VGA-Size (640  480) Video Output 2058 Description deleted The scaling rate for folding can be calculated as shown below. RATIO_org = round (120 ÷ 240 × 4096) = 2048  = (2048 × (240 − 1) − (120 − 1) × 4096) ÷ (240 − 1) = 8.56 Horizontal scaling ratio = round (2048 − (8.56)) = 2039 (2) Horizontal Scaling (Horizontal Scale Up, Scaling Filter: 2-Tap Linear) 33.3.1 Scaling Setting Example for 525i Video Input and VGA-Size (640  480) Video Output 2059 Description amended RATIO_org = round (240 ÷ 480 × 4096) = 2048  = (2048 × (480 − 1) − (240 − 1) × 4096) ÷ (480 − 1) = 4.27 Vertical scaling ratio = round (2048 − (4.07)) = 2044 (3) Vertical Scaling (Vertical Scale Up, Scaling Filter: 2Tap Linear) Figure 35.9 Graphics Planes with GR_DISP_ SEL Set to 3 2134 35.1.10 Display with Alpha Blending in a Rectangular Area 2137 35.1.14 Alpha Blending Calculation 2143 Description amended Current graphics and lower-layer graphics are blended and Displayed using the following formula ( × = 0 to 255): (Current graphics ×  + lower graphics × (255 - ))/255 Description amended Then, each time the Vsync signal rises for the number of times set with the GR_ARC_RATE[7:0] bits + 1, the value of the GR_ARC_COEF[7:0] bit is added to or subtracted from the α value. Description amended Alpha blending of two input signals is performed using the α value as described below (rounded up if the result includes a decimal fraction). G output = (G value × α value + G input of the lower-layer graphics × (255 − α value)) ÷ 256 B output = (B value × α value + B input of the lower-layer graphics × (255 − α value)) ÷ 256 R output = (R value × α value + R input of the lower-layer graphics × (255 − α value)) ÷ 256 Page xlii of cvi Item Page Revision (See Manual for Details) Figure 35.12 Data Arrangement in CLUT Table 2143 Figure amended Table 35.28 CLUT Table Configuration 2148 35.2.3 Frame Buffer Control Register 1 (Graphics 2) (GR2_FLM1) 31 24 23  value 2151 16 R value 15 8 G value 7 0 B value Table amended Name Abbreviation R/W Graphics 1 CLUT table GR1_CLUTT R/W Graphics 2 CLUT table GR2_CLUTT R/W Graphics 3 CLUT table GR3_CLUTT R/W Note amended GR2_LN_OFF_DIR and GR2_FLM_SEL are updated when GR2_IBUS_VEN in GR2_UPDATE is 1. GR2_BST_MD is updated when GR2_IBUS_VEN is 1, and GR2_IBUS_VEN and GR2_P_VEN in GR2_UPDATE are 1. Page xliii of cvi Item Page Revision (See Manual for Details) Table 36.5 Gamma Correction 2204 to 2206 Table amended Register Name GAM_G_AREA1 to GAM_G_AREA8 Bit Name GAM_G_TH_01 to GAM_G_TH_31 [7:0] GAM_B_AREA1 GAM_B_TH_01 to to GAM_B_AREA8 GAM_B_TH_31 [7:0] GAM_R_AREA1 GAM_R_TH_01 to to GAM_R_AREA8 GAM_R_TH_31 [7:0] 36.2.4 Area Setting Register G1 in Gamma Correction Block (GAM_G_AREA1) Page xliv of cvi 2246 Description Start Threshold of Area 1 to 31 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area*1 < Threshold of current area < Threshold of next area*2 *1: GAM_G_TH_01 is 0 *2: GAM_G_TH_31 is  255 : : Start Threshold of Area 1 to 31 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area*1 < Threshold of current area < Threshold of next area*2 *1: GAM_B_TH_01 is 0 *2: GAM_B_TH_31 is  255 : : Start Threshold of Area 1 to 31 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area*1 < Threshold of current area < Threshold of next area*2 *1: GAM_B_TH_01 is 0 *2: GAM_B_TH_31 is  255 : : Table amended Bit 23 to 16 Bit Name GAM_G_TH_01 [7:0] 15 to 8 GAM_G_TH_02 [7:0] 7 to 0 GAM_G_TH_03 [7:0] Description Start Threshold of Area 1 of G Signal Unsigned (0 to 255 [LSB]) 0 < Threshold of current area < Threshold of next area Start Threshold of Area 2 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 3 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area d Item Page Revision (See Manual for Details) 36.2.5 Area Setting Register G2 in Gamma Correction Block (GAM_G_AREA2) 2247 Table amended 36.2.6 Area Setting Register G3 in Gamma Correction Block (GAM_G_AREA3) 2248 Bit 31 to 24 Bit Name GAM_G_TH_04 [7:0] 23 to 16 GAM_G_TH_05 [7:0] 15 to 8 GAM_G_TH_06 [7:0] 7 to 0 GAM_G_TH_07 [7:0] Description Start Threshold of Area 4 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 5 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 6 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 7 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area d Table amended Bit 31 to 24 Bit Name GAM_G_TH_08 [7:0] Description Start Threshold of Area 8 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_09 [7:0] Start Threshold of Area 9 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_10 [7:0] Start Threshold of Area 10 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_11 [7:0] Start Threshold of Area 11 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Page xlv of cvi Item Page Revision (See Manual for Details) 36.2.7 Area Setting Register G4 in Gamma Correction Block (GAM_G_AREA4) 2249 Table amended Bit 31 to 24 23 to 16 15 to 8 7 to 0 36.2.8 Area Setting Register G5 in Gamma Correction Block (GAM_G_AREA5) 2250 GAM_G_TH_13 [7:0] GAM_G_TH_14 [7:0] GAM_G_TH_15 [7:0] Description Start Threshold of Area 12 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 13 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 14 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 15 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area of of of of Table amended Bit 31 to 24 23 to 16 15 to 8 7 to 0 Page xlvi of cvi Bit Name GAM_G_TH_12 [7:0] Bit Name GAM_G_TH_16 [7:0] GAM_G_TH_17 [7:0] GAM_G_TH_18 [7:0] GAM_G_TH_19 [7:0] Description Start Threshold of Area 16 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 17 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 18 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 19 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area of of of of Item Page Revision (See Manual for Details) 36.2.9 Area Setting Register G6 in Gamma Correction Block (GAM_G_AREA6) 2251 Table amended Bit 31 to 24 23 to 16 15 to 8 7 to 0 36.2.10 Area Setting Register G7 in Gamma Correction Block (GAM_G_AREA7) 2252 Bit Name GAM_G_TH_20 [7:0] GAM_G_TH_21 [7:0] GAM_G_TH_22 [7:0] GAM_G_TH_23 [7:0] Description Start Threshold of Area 20 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 21 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 22 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area Start Threshold of Area 23 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold current area < Threshold of next area of of of of Table amended Bit 31 to 24 Bit Name GAM_G_TH_24 [7:0] 23 to 16 GAM_G_TH_25 [7:0] 15 to 8 GAM_G_TH_26 [7:0] 7 to 0 GAM_G_TH_27 [7:0] Description Start Threshold of Area 24 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 25 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 26 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 27 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Page xlvii of cvi Item Page Revision (See Manual for Details) 36.2.11 Area Setting Register G8 in Gamma Correction Block (GAM_G_AREA8) 2253 Table amended 36.2.14 Area Setting Register B1 in Gamma Correction Block (GAM_B_AREA1) Page xlviii of cvi 2258 Bit 31 to 24 Bit Name GAM_G_TH_28 [7:0] 23 to 16 GAM_G_TH_29 [7:0] 15 to 8 GAM_G_TH_30 [7:0] 7 to 0 GAM_G_TH_31 [7:0] Description Start Threshold of Area 28 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 29 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 30 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 31 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area  255 Table amended Bit 23 to 16 Bit Name GAM_B_TH_01 [7:0] 15 to 8 GAM_B_TH_02 [7:0] 7 to 0 GAM_B_TH_03 [7:0] Description Start Threshold of Area 1 of B Signal Unsigned (0 to 255 [LSB]) 0 < Threshold of current area < Threshold of next area Start Threshold of Area 2 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 3 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area d Item Page Revision (See Manual for Details) 36.2.15 Area Setting Register B2 in Gamma Correction Block (GAM_B_AREA2) 2259 Table amended 36.2.16 Area Setting Register B3 in Gamma Correction Block (GAM_B_AREA3) 2260 Bit 31 to 24 Bit Name GAM_B_TH_04 [7:0] 23 to 16 GAM_B_TH_05 [7:0] 15 to 8 GAM_B_TH_06 [7:0] 7 to 0 GAM_B_TH_07 [7:0] Description Start Threshold of Area 4 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 5 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 6 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 7 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area d Table amended Bit 31 to 24 Bit Name GAM_B_TH_08 [7:0] 23 to 16 GAM_B_TH_09 [7:0] 15 to 8 GAM_B_TH_10 [7:0] 7 to 0 GAM_B_TH_11 [7:0] Description Start Threshold of Area 8 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 9 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 10 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 11 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Page xlix of cvi Item Page Revision (See Manual for Details) 36.2.17 Area Setting Register B4 in Gamma Correction Block (GAM_B_AREA4) 2261 Table amended 36.2.18 Area Setting Register B5 in Gamma Correction Block (GAM_B_AREA5) Page l of cvi 2262 Bit 31 to 24 Bit Name GAM_B_TH_12 [7:0] 23 to 16 GAM_B_TH_13 [7:0] 15 to 8 GAM_B_TH_14 [7:0] 7 to 0 GAM_B_TH_15 [7:0] Description Start Threshold of Area 12 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 13 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 14 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 15 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Table amended Bit 31 to 24 Bit Name GAM_B_TH_16 [7:0] 23 to 16 GAM_B_TH_17 [7:0] 15 to 8 GAM_B_TH_18 [7:0] 7 to 0 GAM_B_TH_19 [7:0] Description Start Threshold of Area 16 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 17 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 18 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 19 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Item Page Revision (See Manual for Details) 36.2.19 Area Setting Register B6 in Gamma Correction Block (GAM_B_AREA6) 2263 Table amended 36.2.20 Area Setting Register B7 in Gamma Correction Block (GAM_B_AREA7) 2264 Bit 31 to 24 Bit Name GAM_B_TH_20 [7:0] 23 to 16 GAM_B_TH_21 [7:0] 15 to 8 GAM_B_TH_22 [7:0] 7 to 0 GAM_B_TH_23 [7:0] Description Start Threshold of Area 20 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 21 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 22 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 23 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Table amended Bit 31 to 24 Bit Name GAM_B_TH_24 [7:0] 23 to 16 GAM_B_TH_25 [7:0] 15 to 8 GAM_B_TH_26 [7:0] 7 to 0 GAM_B_TH_27 [7:0] Description Start Threshold of Area 24 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 25 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 26 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 27 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Page li of cvi Item Page Revision (See Manual for Details) 36.2.21 Area Setting Register B8 in Gamma Correction Block (GAM_B_AREA8) 2265 Table amended 36.2.24 Area Setting Register R1 in Gamma Correction Block (GAM_R_AREA1) Page lii of cvi 2270 Bit 31 to 24 Bit Name GAM_B_TH_28 [7:0] 23 to 16 GAM_B_TH_29 [7:0] 15 to 8 GAM_B_TH_30 [7:0] 7 to 0 GAM_B_TH_31 [7:0] Description Start Threshold of Area 28 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 29 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 30 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 31 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area  255 Table amended Bit 23 to 16 Bit Name GAM_R_TH_01 [7:0] 15 to 8 GAM_R_TH_02 [7:0] 7 to 0 GAM_R_TH_03 [7:0] Description Start Threshold of Area 1 of R Signal Unsigned (0 to 255 [LSB]) 0 < Threshold of current area < Threshold of next area Start Threshold of Area 2 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 3 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area d Item Page Revision (See Manual for Details) 36.2.25 Area Setting Register R2 in Gamma Correction Block (GAM_R_AREA2) 2271 Table amended 36.2.26 Area Setting Register R3 in Gamma Correction Block (GAM_R_AREA3) 2272 Bit 31 to 24 Bit Name GAM_R_TH_04 [7:0] 23 to 16 GAM_R_TH_05 [7:0] 15 to 8 GAM_R_TH_06 [7:0] 7 to 0 GAM_R_TH_07 [7:0] Description Start Threshold of Area 4 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 5 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 6 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 7 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area d Table amended Bit 31 to 24 Bit Name GAM_R_TH_08 [7:0] 23 to 16 GAM_R_TH_09 [7:0] 15 to 8 GAM_R_TH_10 [7:0] 7 to 0 GAM_R_TH_11 [7:0] Description Start Threshold of Area 8 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 9 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 10 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 11 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Page liii of cvi Item Page Revision (See Manual for Details) 36.2.27 Area Setting Register R4 in Gamma Correction Block (GAM_R_AREA4) 2273 Table amended 36.2.28 Area Setting Register R5 in Gamma Correction Block (GAM_R_AREA5) Page liv of cvi 2274 Bit 31 to 24 Bit Name GAM_R_TH_12 [7:0] 23 to 16 GAM_R_TH_13 [7:0] 15 to 8 GAM_R_TH_14 [7:0] 7 to 0 GAM_R_TH_15 [7:0] Description Start Threshold of Area 12 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 13 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 14 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 15 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Table amended Bit 31 to 24 Bit Name GAM_R_TH_16 [7:0] 23 to 16 GAM_R_TH_17 [7:0] 15 to 8 GAM_R_TH_18 [7:0] 7 to 0 GAM_R_TH_19 [7:0] Description Start Threshold of Area 16 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 17 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 18 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 19 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Item Page Revision (See Manual for Details) 36.2.29 Area Setting Register R6 in Gamma Correction Block (GAM_R_AREA6) 2275 Table amended 36.2.30 Area Setting Register R7 in Gamma Correction Block (GAM_R_AREA7) 2276 Bit 31 to 24 Bit Name GAM_R_TH_20 [7:0] 23 to 16 GAM_R_TH_21 [7:0] 15 to 8 GAM_R_TH_22 [7:0] 7 to 0 GAM_R_TH_23 [7:0] Description Start Threshold of Area 20 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 21 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 22 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 23 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Table amended Bit 31 to 24 Bit Name GAM_R_TH_24 [7:0] 23 to 16 GAM_R_TH_25 [7:0] 15 to 8 GAM_R_TH_26 [7:0] 7 to 0 GAM_R_TH_27 [7:0] Description Start Threshold of Area 24 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 25 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 26 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 27 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Page lv of cvi Item Page Revision (See Manual for Details) 36.2.31 Area Setting Register R8 in Gamma Correction Block (GAM_R_AREA8) 2277 Table amended Table 37.2 Interrupt Clear/Hold Settings 2312, 2313 Bit 31 to 24 Bit Name GAM_R_TH_28 [7:0] 23 to 16 GAM_R_TH_29 [7:0] 15 to 8 GAM_R_TH_30 [7:0] 7 to 0 GAM_R_TH_31 [7:0] Table amended Register Name SYSCNT_INT2 Register Name SYSCNT_INT2 SYSCNT_INT1 Table 37.3 Interrupt Output On/Off Settings 2314 Bit Name INT_STA0 INT_STA1 INT_STA2 INT_STA3 INT_STA4 Initial Value 0 0 0 0 0 INT_STA5 0 Bit Name INT_STA6 INT_STA7 INT_STA8 Initial Value 0 0 0 Bit Name INT_OUT0_ON INT_OUT1_ON INT_OUT2_ON INT_OUT3_ON INT_OUT4_ON Initial Value 0 0 0 0 0 INT_OUT5_ON INT_OUT6_ON INT_OUT7_ON INT_OUT8_ON 0 0 0 0 Table amended Register Name SYSCNT_INT4 SYSCNT_INT3 Page lvi of cvi Description Start Threshold of Area 28 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 29 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 30 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Start Threshold of Area 31 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area  255 Item Page Revision (See Manual for Details) Table 39.2 Pixel Format 2348 Table amended Bits in DOCMPMR 32 bits/pixel ARGB8888 CMPBT 0 RGB888 16 bits/pixel 41.2.30 JPEG Interrupt Enable Register 1 (JINTE1) 2400 48.2.18 Port E Data Register 0 (PEDR0) 2616 Arbitrary Arbitrary   Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 — — — — — — — — — — — — — — — — 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — CBTEN DIN LEN — — DOU DBTEN JINEN TLEN 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R/W 0 R/W 0 R R 0 R R Undefined Undefined Undefined Undefined Undefined Initial value: R/W(compress): R/W(decompress): 2477 1 CMPDAUF [7:0]  Bit table amended Initial value: R/W(compress): R/W(decompress): Table 43.4 Relationship between Tone Frequency and Output Error RGB565 CMPDFA [7:0]  0 R/W 0 R/W 16 0 R/W Table amended Tone Frequency SFS[7:0] TONE[6:0] Error (%) 1318.50 ED 8 0.005 2637.00 ED 4 0.005 5274.00 ED 2 0.005 Table amended Bit 7 Bit Name 6 PE6DR 5 PE5DR 4 PE4DR 3 PE3DR 2 PE2DR 1 PE1DR 0 PE0DR PE7DR Description See table 48.16. Bits 7 to 4 are reserved in the SH7268 Group. These bits are always read as 1. The write value should always be 1. Page lvii of cvi Item Page Revision (See Manual for Details) 48.2.19 Port E Port Register 0 (PEPR0) 2617 Table amended 49.3.4 Deep Standby Mode 2727 Bit Name 6 PE6PR 5 PE5PR 4 PE4PR 3 PE3PR 2 PE2PR 1 PE1PR 0 PE0PR PE7PR Description The pin state is returned. These bits cannot be modified. Bits 7 to 4 are reserved in the SH7268 Group. These bits are always read as 1. Description amended Deep standby mode is canceled by interrupts (NMI or realtime clock alarm interrupt), change on the pins for canceling, or a reset (power-on reset). The realtime clock alarm interrupt can always cancel deep standby mode regardless of the interrupt priority level or the settings of the status register (SR) in the CPU and of the alarm interrupt enable flag (RCR1.AIE). When canceling the mode by a source other than a reset, a power-on reset exception handling is executed instead of an interrupt exception handling. (2) Canceling Deep Standby Mode 51.1 Register Addresses (by functional module, in order of the corresponding section numbers)cd-rom Bit 7 2790 Table amended Number Register Name Abbreviation of Bits Address Size Video display Full-screen vertical size SCL0_FRC6 32 H'FFFF7518 16, 32 controller 4 register SCL0_FRC7 32 H'FFFF751C 16, 32 SCL0_FRC8 32 H'FFFF7520 16, 32 Full-screen horizontal size register Field determination signal switching register (R version only) Page lviii of cvi Access Module Name Item Page Revision (See Manual for Details) 51.2 Register Bits 2867, 2868, 2875, 2893, 2896 Table amended Module Register Bit Bit Bit Bit Bit Bit Bit Bit Name Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 CD-ROM CROMCTL4  LINK2  EROSEL NO_ECC    CROMCTL5        MSF_LBA CBUFCTL0 CBUF_AUT CBUF_EN  CBUF_MD[1] CBUF_MD[0] CBUF_TS CBUF_Q  DCPCFG      CNTMD decoder _SEL USB 2.0   host/function SHTNAK        Video display SCL0_FRC8         controller 4 (R version                      RES_US_F   module only) LD SCL1_WR1                        RES_FLM _MD (R version only)  51.3 Register States in Each Operating Mode 2957, 2958 RES_DS_ RES_DS_ WR_MD[2] WR_MD[1] WR_MD[0] RES_MD[1] RES_DS_ RES_MD[0] RES_LOOP RES_BST _MD Table amended Manual Deep Software Module Module Name Register Abbreviation Reset Power-On Reset Standby Standby Standby Sleep Multi-function All registers Initialized Retained Initialized Retained Initialized Retained RCR3 Retained Retained Retained Retained Retained Retained timer pulse unit 2 Realtime clock Table 52.5 Clock Timing 2976 Table amended Item Symbol Min. Max. Unit Figure Real time clock oscillation settling time tROSC  3 s Figure 52.6 Page lix of cvi Item Page Revision (See Manual for Details) Figure 52.3 Power-On Oscillation Settling Time 2977 Figure amended Oscillation settling time CKIO, Internal clock Power Supply* Power Supply Min. tOSC1 RES TRST tMDH MD_BOOT2, MD_BOOT1, MD_BOOT0 MD_CLK0 Note: * PVcc, Vcc, PLLVcc, AVcc, USBAPVcc, USBDPVcc, USBAVcc, USBPVcc, USBUVcc, VDAVcc Note that SH7269 products in BGA packages do not have USBDVcc, USBUVcc, and USBDPVcc pins. Figure 52.5 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ) 2978 Figure amended Standby period Oscillation settling time CKIO, Internal clock tNMIW, tIRQW NMI, IRQ tOSC2 Figure 52.11 Basic Bus Timing for Normal Space 2985 T1 2987 Twx Ta2 Ta3 T1 Tw Twx T2 CKIO 3023 Table amended and note amended Item Symbol Min. Max. Unit Figure SPBCLK clock cycle tSPBcyc 2 2 tbcyc Figure 52.53 Note: tbcyc indicates the bus clock (B) cycle. Page lx of cvi T2 Figure amended Ta1 (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) Table 52.15 SPI Multi I/O Bus Controller Timing Tw CKIO (One Software Wait Cycle, One External Wait Cycle) Figure 52.13 MPX-I/O Interface Bus Cycle Figure amended Item Page Revision (See Manual for Details) 52.4.23 AC Characteristics Measurement Conditions 3049 Description amended Table 53.1 Pin States 3053, 3056  I/O signal reference level: PVCC/2, the minimum values of VIH, VT+, and VOH, and the maximum values of VIL, VT-, and VOL (refer to the individual timing chart) Table amended Pin Function Pin State Pin State Retained* 2 Power-Down State Normal EBUSKEEPE* State (Other than (Other Type Pin Name Clock EXTAL* XTAL* 6 CKIO Boot than Power- States On at Right) Reset* 6 3 1 Power States at Right) -On 0 1 Deep Standby Standby * Mode 4 5 I I I I/Z* O O O O/L* 0 O/Z* 7 Other O/Z* 7 O/Z* 7 Software Reset Mode I 5 O/L* O/Z* 7 5 O/Z* 7 O/Z* 7 O/Z* 7 O O O O/Z* I   TxD7 to TxD0 O/Z  O/Z* O/Z* O/Z* RxD7 (PE7, PJ25), I   Z Z mode 7 than above AUDIO_CLK Serial Z 9 Z 9 9 communication interface with FIFO RxD6 to RxD0 Table 53.2 Pin States while the Bus Mastership is Released 3066 Description amended [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance : Condition under which the pin function is not selectable 3067 Note amended 2. After the chip has shifted to the power-on reset state from deep standby mode by the input on the NMI pin and so on, or by the realtime clock alarm interrupt, the pins retain the state until the IOKEEP bit in the deep standby cancel source flag register (DSFR) is cleared (see section 49, Power-Down Modes). Page lxi of cvi Item Page Revision (See Manual for Details) Table 53.5 Handling of Pins in Deep Standby Mode 3070 Table amended Pin Handling REFRIN Connect this pin to USBAPVss via 5.6 kΩ ± 1% resistor (SH7268 and SH7269 products in QFP packages). Connect this pin to Vss via 5.6 kΩ ± 1% resistor (SH7269 products in BGA packages). Connect these pins to VDAVss via 0.1-F capacitor. VRT, VRB 3073 Figure amended 218 PF18 219 PJ11 220 PJ12 221 PJ13 222 PVcc 223 PF19 224 Vss 225 PF20 226 Vcc 227 PF21 228 PF22 229 PF23 230 PD0 231 PVcc 232 PJ24 233 Vss 234 PD1 235 PD2 236 PD3 237 PJ25 238 PJ26 239 PJ27 240 PVcc 241 Vss 242 PD4 243 PD5 244 PD6 245 PD7 246 PD8 247 PD9 248 PD10 249 PD11 250 PVcc 251 PD12 252 Vss 253 PD13 254 PD14 255 PD15 256 MD_CLK0 PLQP0256LB-A Top view 1 PC1 2 PVcc 3 PC2 4 PC3 5 PC4 6 PC5 7 PVcc 8 PC6 9 Vss 10 PC7 11 Vcc 12 PC8 13 PB1 14 PB2 15 PB3 16 PJ14 17 PVcc 18 PJ15 19 Vss 20 PB4 21 Vcc 22 PJ16 23 PJ17 24 PJ18 25 PB5 26 PB6 27 PVcc 28 PB7 29 Vss 30 PB8 31 Vcc 32 PB9 33 PB10 34 PB11 35 PB12 36 PJ19 Figure 53.2 Example of Externally Allocated Capacitors in the SH7269 (QFP) Group Page lxii of cvi Contents Section 1 Overview ................................................................................................1 1.1 1.2 1.3 1.4 1.5 1.6 SH7268/7269 Features .......................................................................................................... 1 Product Lineup .................................................................................................................... 16 Block Diagram .................................................................................................................... 17 Pin Assignment ................................................................................................................... 18 Pin Functions ...................................................................................................................... 21 List of Pins .......................................................................................................................... 34 Section 2 CPU ......................................................................................................57 2.1 2.2 2.3 2.4 2.5 Register Configuration ........................................................................................................ 57 2.1.1 General Registers ................................................................................................ 57 2.1.2 Control Registers ................................................................................................ 58 2.1.3 System Registers ................................................................................................. 60 2.1.4 Register Banks .................................................................................................... 61 2.1.5 Initial Values of Registers ................................................................................... 61 Data Formats ....................................................................................................................... 62 2.2.1 Data Format in Registers .................................................................................... 62 2.2.2 Data Formats in Memory .................................................................................... 62 2.2.3 Immediate Data Format ...................................................................................... 63 Instruction Features............................................................................................................. 64 2.3.1 RISC-Type Instruction Set .................................................................................. 64 2.3.2 Addressing Modes .............................................................................................. 68 2.3.3 Instruction Format............................................................................................... 73 Instruction Set ..................................................................................................................... 77 2.4.1 Instruction Set by Classification ......................................................................... 77 2.4.2 Data Transfer Instructions................................................................................... 83 2.4.3 Arithmetic Operation Instructions ...................................................................... 87 2.4.4 Logic Operation Instructions .............................................................................. 90 2.4.5 Shift Instructions ................................................................................................. 91 2.4.6 Branch Instructions ............................................................................................. 92 2.4.7 System Control Instructions ................................................................................ 93 2.4.8 Floating-Point Operation Instructions ................................................................. 95 2.4.9 FPU-Related CPU Instructions ........................................................................... 97 2.4.10 Bit Manipulation Instructions ............................................................................. 98 Processing States................................................................................................................. 99 Page lxiii of cvi Section 3 Floating-Point Unit (FPU) ................................................................. 101 3.1 3.2 3.3 3.4 3.5 Features ............................................................................................................................. 101 Data Formats..................................................................................................................... 102 3.2.1 Floating-Point Format ....................................................................................... 102 3.2.2 Non-Numbers (NaN) ........................................................................................ 105 3.2.3 Denormalized Numbers .................................................................................... 106 Register Descriptions ........................................................................................................ 107 3.3.1 Floating-Point Registers ................................................................................... 107 3.3.2 Floating-Point Status/Control Register (FPSCR) ............................................. 108 3.3.3 Floating-Point Communication Register (FPUL) ............................................. 110 Rounding .......................................................................................................................... 111 FPU Exceptions ................................................................................................................ 112 3.5.1 FPU Exception Sources .................................................................................... 112 3.5.2 FPU Exception Handling .................................................................................. 112 Section 4 Boot Mode ......................................................................................... 115 4.1 4.2 4.3 4.4 Features ............................................................................................................................. 115 Boot Mode and Pin Function Setting ................................................................................ 116 Operation .......................................................................................................................... 117 4.3.1 Boot Modes 0 and 1 .......................................................................................... 117 4.3.2 Boot Mode 2 ..................................................................................................... 117 4.3.3 Boot Mode 3 ..................................................................................................... 119 4.3.4 Boot Mode 4 ..................................................................................................... 121 4.3.5 Boot Mode 5 ..................................................................................................... 122 Notes ................................................................................................................................. 124 4.4.1 Boot Related Pins ............................................................................................. 124 Section 5 Clock Pulse Generator ....................................................................... 125 5.1 5.2 5.3 5.4 5.5 5.6 Features ............................................................................................................................. 125 Input/Output Pins .............................................................................................................. 129 Clock Mode ...................................................................................................................... 130 Register Descriptions ........................................................................................................ 132 5.4.1 Frequency Control Register (FRQCR) ............................................................. 132 Changing the Frequency ................................................................................................... 135 5.5.1 Changing the Division Ratio............................................................................. 135 Usage of the Clock Pins .................................................................................................... 136 5.6.1 In the Case of Inputting an External Clock ....................................................... 136 5.6.2 In the Case of Using a Crystal Resonator ......................................................... 137 5.6.3 In the Case of Not Using the Clock Pin ............................................................ 137 Page lxiv of cvi 5.7 5.8 5.9 Oscillation Stabilizing Time ............................................................................................. 138 5.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator ........................ 138 5.7.2 Oscillation Stabilizing Time of the PLL circuit ................................................ 138 Notes on Board Design ..................................................................................................... 139 5.8.1 Note on Using a PLL Oscillation Circuit .......................................................... 139 Definition of Modulation Rate and Frequency in the SSCG Specification....................... 140 Section 6 Exception Handling ...........................................................................141 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Overview........................................................................................................................... 141 6.1.1 Types of Exception Handling and Priority........................................................ 141 6.1.2 Exception Handling Operations ........................................................................ 142 6.1.3 Exception Handling Vector Table..................................................................... 144 Resets ................................................................................................................................ 147 6.2.1 Input/Output Pins .............................................................................................. 147 6.2.2 Types of Reset .................................................................................................. 147 6.2.3 Power-On Reset ................................................................................................ 149 6.2.4 Manual Reset .................................................................................................... 150 Address Errors .................................................................................................................. 152 6.3.1 Address Error Sources ...................................................................................... 152 6.3.2 Address Error Exception Handling ................................................................... 153 Register Bank Errors ......................................................................................................... 153 6.4.1 Register Bank Error Sources ............................................................................. 153 6.4.2 Register Bank Error Exception Handling ......................................................... 153 Interrupts ........................................................................................................................... 154 6.5.1 Interrupt Sources ............................................................................................... 154 6.5.2 Interrupt Priority Level ..................................................................................... 155 6.5.3 Interrupt Exception Handling ........................................................................... 156 Exceptions Triggered by Instructions ............................................................................... 157 6.6.1 Types of Exceptions Triggered by Instructions ................................................ 157 6.6.2 Trap Instructions ............................................................................................... 158 6.6.3 Slot Illegal Instructions ..................................................................................... 158 6.6.4 General Illegal Instructions ............................................................................... 159 6.6.5 Integer Division Exceptions .............................................................................. 159 6.6.6 FPU Exceptions ................................................................................................ 160 When Exception Sources Are Not Accepted .................................................................... 161 Stack Status after Exception Handling Ends ..................................................................... 161 Usage Notes ...................................................................................................................... 163 6.9.1 Value of Stack Pointer (SP) .............................................................................. 163 6.9.2 Value of Vector Base Register (VBR) .............................................................. 163 6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 163 Page lxv of cvi 6.9.4 6.9.5 Interrupt Control via Modification of Interrupt Mask Bits ............................... 163 Note before Exception Handling Begins Running ............................................ 164 Section 7 Interrupt Controller ............................................................................ 167 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Features ............................................................................................................................. 167 Input/Output Pins .............................................................................................................. 169 Register Descriptions ........................................................................................................ 170 7.3.1 Interrupt Priority Registers 01, 02, 05 to 26 (IPR01, IPR02, IPR05 to IPR26) 172 7.3.2 Interrupt Control Register 0 (ICR0) .................................................................. 175 7.3.3 Interrupt Control Register 1 (ICR1) .................................................................. 177 7.3.4 Interrupt Control Register 2 (ICR2) .................................................................. 178 7.3.5 IRQ Interrupt Request Register (IRQRR) ......................................................... 179 7.3.6 PINT Interrupt Enable Register (PINTER) ....................................................... 180 7.3.7 PINT Interrupt Request Register (PIRR) .......................................................... 181 7.3.8 Bank Control Register (IBCR).......................................................................... 182 7.3.9 Bank Number Register (IBNR) ........................................................................ 183 Interrupt Sources ............................................................................................................... 184 7.4.1 NMI Interrupt.................................................................................................... 184 7.4.2 User Break Interrupt ......................................................................................... 185 7.4.3 User Debugging Interface Interrupt .................................................................. 185 7.4.4 IRQ Interrupts ................................................................................................... 185 7.4.5 PINT Interrupts ................................................................................................. 186 7.4.6 On-Chip Peripheral Module Interrupts ............................................................. 187 Interrupt Exception Handling Vector Table and Priority .................................................. 189 Operation .......................................................................................................................... 205 7.6.1 Interrupt Operation Sequence ........................................................................... 205 7.6.2 Stack after Interrupt Exception Handling ......................................................... 208 Interrupt Response Time................................................................................................... 209 Register Banks .................................................................................................................. 216 7.8.1 Banked Register and Input/Output of Banks .................................................... 217 7.8.2 Bank Save and Restore Operations ................................................................... 217 7.8.3 Save and Restore Operations after Saving to All Banks ................................... 219 7.8.4 Register Bank Exception .................................................................................. 220 7.8.5 Register Bank Error Exception Handling ......................................................... 220 Data Transfer with Interrupt Request Signals ................................................................... 221 7.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not Direct Memory Access Controller Activating ............................................................................. 222 7.9.2 Handling Interrupt Request Signals as Sources for Activating Direct Memory Access Controller but Not CPU Interrupt ......................................................................... 222 Usage Note ....................................................................................................................... 223 Page lxvi of cvi 7.10.1 Timing to Clear an Interrupt Source ................................................................. 223 Section 8 User Break Controller ........................................................................225 8.1 8.2 8.3 8.4 8.5 Features ............................................................................................................................. 225 Input/Output Pin ............................................................................................................... 227 Register Descriptions ........................................................................................................ 228 8.3.1 Break Address Register (BAR) ......................................................................... 229 8.3.2 Break Address Mask Register (BAMR) ........................................................... 230 8.3.3 Break Data Register (BDR) .............................................................................. 231 8.3.4 Break Data Mask Register (BDMR) ................................................................. 232 8.3.5 Break Bus Cycle Register (BBR)...................................................................... 233 8.3.6 Break Control Register (BRCR) ....................................................................... 235 Operation .......................................................................................................................... 239 8.4.1 Flow of the User Break Operation .................................................................... 239 8.4.2 Break on Instruction Fetch Cycle...................................................................... 240 8.4.3 Break on Data Access Cycle ............................................................................. 241 8.4.4 Value of Saved Program Counter ..................................................................... 242 8.4.5 Usage Examples ................................................................................................ 243 Usage Notes ...................................................................................................................... 246 Section 9 Cache .................................................................................................247 9.1 9.2 9.3 9.4 Features ............................................................................................................................. 247 9.1.1 Cache Structure ................................................................................................. 247 Register Descriptions ........................................................................................................ 250 9.2.1 Cache Control Register 1 (CCR1) .................................................................... 250 9.2.2 Cache Control Register 2 (CCR2) .................................................................... 252 Operation .......................................................................................................................... 256 9.3.1 Searching Cache ............................................................................................... 256 9.3.2 Read Access ...................................................................................................... 258 9.3.3 Prefetch Operation (Only for Operand Cache) ................................................. 258 9.3.4 Write Operation (Only for Operand Cache)...................................................... 259 9.3.5 Write-Back Buffer (Only for Operand Cache).................................................. 259 9.3.6 Coherency of Cache and External Memory or Large-Capacity On-Chip RAM ......................................................................... 261 Memory-Mapped Cache ................................................................................................... 262 9.4.1 Address Array ................................................................................................... 262 9.4.2 Data Array ........................................................................................................ 263 9.4.3 Usage Examples ................................................................................................ 265 9.4.4 Usage Notes ...................................................................................................... 266 Page lxvii of cvi Section 10 Bus State Controller ........................................................................ 267 10.1 10.2 10.3 10.4 10.5 Features ............................................................................................................................. 267 Input/Output Pins .............................................................................................................. 270 Area Overview .................................................................................................................. 272 10.3.1 Address Map ..................................................................................................... 272 10.3.2 Data Bus Width, Endian Specification, and Related Pin Setting for Each Area Depending on Boot Mode.......................................................... 273 Register Descriptions ........................................................................................................ 275 10.4.1 Common Control Register (CMNCR) .............................................................. 277 10.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 5) ................................. 281 10.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 5) .............................. 286 10.4.4 SDRAM Control Register (SDCR) ................................................................... 315 10.4.5 Refresh Timer Control/Status Register (RTCSR) ............................................. 319 10.4.6 Refresh Timer Counter (RTCNT) ..................................................................... 321 10.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 322 Operation .......................................................................................................................... 323 10.5.1 Endian/Access Size and Data Alignment.......................................................... 323 10.5.2 Normal Space Interface .................................................................................... 330 10.5.3 Access Wait Control ......................................................................................... 335 10.5.4 CSn Assert Period Expansion ........................................................................... 337 10.5.5 MPX-I/O Interface ............................................................................................ 338 10.5.6 SDRAM Interface ............................................................................................. 343 10.5.7 Burst ROM (Clocked Asynchronous) Interface ................................................ 385 10.5.8 SRAM Interface with Byte Selection ............................................................... 388 10.5.9 PCMCIA Interface ............................................................................................ 393 10.5.10 Burst ROM (Clocked Synchronous) Interface .................................................. 398 10.5.11 Wait between Access Cycles ............................................................................ 399 10.5.12 Bus Arbitration ................................................................................................. 407 10.5.13 Others................................................................................................................ 410 Section 11 Direct Memory Access Controller................................................... 413 11.1 11.2 11.3 Features ............................................................................................................................. 413 Input/Output Pins .............................................................................................................. 416 Register Descriptions ........................................................................................................ 417 11.3.1 DMA Source Address Registers (SAR) ............................................................ 426 11.3.2 DMA Destination Address Registers (DAR) .................................................... 426 11.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 427 11.3.4 DMA Channel Control Registers (CHCR) ....................................................... 427 11.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 438 11.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 439 Page lxviii of cvi 11.4 11.5 11.3.7 DMA Reload Transfer Count Registers (RDMATCR)..................................... 440 11.3.8 DMA Operation Register (DMAOR) ............................................................... 441 11.3.9 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7) .............. 445 Operation .......................................................................................................................... 451 11.4.1 Transfer Flow .................................................................................................... 451 11.4.2 DMA Transfer Requests ................................................................................... 453 11.4.3 Channel Priority ................................................................................................ 461 11.4.4 DMA Transfer Types ........................................................................................ 461 11.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 470 Usage Notes ...................................................................................................................... 473 11.5.1 Timing of DACK and TEND Outputs .............................................................. 473 Section 12 Multi-Function Timer Pulse Unit 2 .................................................475 12.1 12.2 12.3 Features ............................................................................................................................. 475 Input/Output Pins .............................................................................................................. 480 Register Descriptions ........................................................................................................ 481 12.3.1 Timer Control Register (TCR) .......................................................................... 485 12.3.2 Timer Mode Register (TMDR) ......................................................................... 489 12.3.3 Timer I/O Control Register (TIOR) .................................................................. 492 12.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 510 12.3.5 Timer Status Register (TSR) ............................................................................. 513 12.3.6 Timer Buffer Operation Transfer Mode Register (TBTM) ............................... 518 12.3.7 Timer Input Capture Control Register (TICCR) ............................................... 519 12.3.8 Timer A/D Converter Start Request Control Register (TADCR) ..................... 521 12.3.9 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) .................................................................. 524 12.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4)............................................................. 524 12.3.11 Timer Counter (TCNT) ..................................................................................... 525 12.3.12 Timer General Register (TGR) ......................................................................... 525 12.3.13 Timer Start Register (TSTR) ............................................................................ 526 12.3.14 Timer Synchronous Register (TSYR) ............................................................... 527 12.3.15 Timer Read/Write Enable Register (TRWER) ................................................. 529 12.3.16 Timer Output Master Enable Register (TOER) ................................................ 530 12.3.17 Timer Output Control Register 1 (TOCR1) ...................................................... 532 12.3.18 Timer Output Control Register 2 (TOCR2) ...................................................... 535 12.3.19 Timer Output Level Buffer Register (TOLBR) ................................................ 538 12.3.20 Timer Gate Control Register (TGCR) .............................................................. 539 12.3.21 Timer Subcounter (TCNTS) ............................................................................. 541 12.3.22 Timer Dead Time Data Register (TDDR) ......................................................... 542 Page lxix of cvi 12.4 12.5 12.6 12.7 12.3.23 Timer Cycle Data Register (TCDR) ................................................................. 542 12.3.24 Timer Cycle Buffer Register (TCBR)............................................................... 543 12.3.25 Timer Interrupt Skipping Set Register (TITCR) ............................................... 543 12.3.26 Timer Interrupt Skipping Counter (TITCNT) ................................................... 545 12.3.27 Timer Buffer Transfer Set Register (TBTER) .................................................. 546 12.3.28 Timer Dead Time Enable Register (TDER) ..................................................... 548 12.3.29 Timer Waveform Control Register (TWCR) .................................................... 549 12.3.30 Bus Master Interface ......................................................................................... 550 Operation .......................................................................................................................... 551 12.4.1 Basic Functions ................................................................................................. 551 12.4.2 Synchronous Operation..................................................................................... 557 12.4.3 Buffer Operation ............................................................................................... 559 12.4.4 Cascaded Operation .......................................................................................... 563 12.4.5 PWM Modes ..................................................................................................... 568 12.4.6 Phase Counting Mode ....................................................................................... 573 12.4.7 Reset-Synchronized PWM Mode ..................................................................... 580 12.4.8 Complementary PWM Mode ............................................................................ 583 12.4.9 A/D Converter Start Request Delaying Function.............................................. 622 12.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ................................................................................................ 626 Interrupt Sources ............................................................................................................... 627 12.5.1 Interrupt Sources and Priorities ........................................................................ 627 12.5.2 Activation of Direct Memory Access Controller .............................................. 629 12.5.3 A/D Converter Activation ................................................................................. 629 Operation Timing.............................................................................................................. 631 12.6.1 Input/Output Timing ......................................................................................... 631 12.6.2 Interrupt Signal Timing .................................................................................... 638 Usage Notes ...................................................................................................................... 642 12.7.1 Module Standby Mode Setting ......................................................................... 642 12.7.2 Input Clock Restrictions ................................................................................... 642 12.7.3 Caution on Period Setting ................................................................................. 643 12.7.4 Contention between TCNT Write and Clear Operations .................................. 643 12.7.5 Contention between TCNT Write and Increment Operations ........................... 644 12.7.6 Contention between TGR Write and Compare Match ...................................... 645 12.7.7 Contention between Buffer Register Write and Compare Match ..................... 646 12.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 647 12.7.9 Contention between TGR Read and Input Capture........................................... 648 12.7.10 Contention between TGR Write and Input Capture .......................................... 649 12.7.11 Contention between Buffer Register Write and Input Capture ......................... 650 Page lxx of cvi 12.7.12 12.8 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection ........................................................................................................ 650 12.7.13 Counter Value during Complementary PWM Mode Stop ................................ 652 12.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 652 12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 653 12.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 654 12.7.17 Contention between Overflow/Underflow and Counter Clearing ..................... 655 12.7.18 Contention between TCNT Write and Overflow/Underflow ............................ 656 12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode ................................................................. 656 12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode...................................................................... 657 12.7.21 Interrupts in Module Standby Mode ................................................................. 657 12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection ........ 657 12.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode ...................... 658 Output Pin Initialization for Multi-Function Timer Pulse Unit 2 ..................................... 660 12.8.1 Operating Modes............................................................................................... 660 12.8.2 Reset Start Operation ........................................................................................ 660 12.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc. .............. 661 12.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. ............................................................. 662 Section 13 Compare Match Timer .....................................................................693 13.1 13.2 13.3 13.4 13.5 Features ............................................................................................................................. 693 Register Descriptions ........................................................................................................ 694 13.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 695 13.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 696 13.2.3 Compare Match Counter (CMCNT) ................................................................. 698 13.2.4 Compare Match Constant Register (CMCOR) ................................................. 698 Operation .......................................................................................................................... 699 13.3.1 Interval Count Operation .................................................................................. 699 13.3.2 CMCNT Count Timing ..................................................................................... 699 Interrupts ........................................................................................................................... 700 13.4.1 Interrupt Sources and DMA Transfer Requests ................................................ 700 13.4.2 Timing of Compare Match Flag Setting ........................................................... 700 13.4.3 Timing of Compare Match Flag Clearing ......................................................... 701 Usage Notes ...................................................................................................................... 702 13.5.1 Conflict between Write and Compare-Match Processes of CMCNT ............... 702 13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 703 Page lxxi of cvi 13.5.3 13.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT ................. 704 Compare Match between CMCNT and CMCOR ............................................. 704 Section 14 Watchdog Timer .............................................................................. 705 14.1 14.2 14.3 14.4 14.5 Features ............................................................................................................................. 705 Input/Output Pin ............................................................................................................... 706 Register Descriptions ........................................................................................................ 707 14.3.1 Watchdog Timer Counter (WTCNT)................................................................ 707 14.3.2 Watchdog Timer Control/Status Register (WTCSR) ........................................ 708 14.3.3 Watchdog Reset Control/Status Register (WRCSR) ........................................ 711 14.3.4 Notes on Register Access ................................................................................. 712 Usage ................................................................................................................................ 714 14.4.1 Canceling Software Standby Mode .................................................................. 714 14.4.2 Using Watchdog Timer Mode .......................................................................... 714 14.4.3 Using Interval Timer Mode .............................................................................. 716 Usage Notes ...................................................................................................................... 717 14.5.1 Timer Variation ................................................................................................ 717 14.5.2 Prohibition against Setting H'FF to WTCNT.................................................... 717 14.5.3 Interval Timer Overflow Flag ........................................................................... 717 14.5.4 System Reset by WDTOVF Signal................................................................... 718 14.5.5 Manual Reset in Watchdog Timer Mode .......................................................... 718 14.5.6 Internal Reset in Watchdog Timer Mode.......................................................... 718 Section 15 Realtime Clock ................................................................................ 719 15.1 15.2 15.3 Features ............................................................................................................................. 719 Input/Output Pin ............................................................................................................... 721 Register Descriptions ........................................................................................................ 722 15.3.1 64-Hz Counter (R64CNT) ................................................................................ 723 15.3.2 Second Counter (RSECCNT) ........................................................................... 724 15.3.3 Minute Counter (RMINCNT) ........................................................................... 725 15.3.4 Hour Counter (RHRCNT) ................................................................................ 726 15.3.5 Day of Week Counter (RWKCNT) .................................................................. 727 15.3.6 Date Counter (RDAYCNT) .............................................................................. 728 15.3.7 Month Counter (RMONCNT) .......................................................................... 729 15.3.8 Year Counter (RYRCNT) ................................................................................. 730 15.3.9 Second Alarm Register (RSECAR) .................................................................. 731 15.3.10 Minute Alarm Register (RMINAR) .................................................................. 732 15.3.11 Hour Alarm Register (RHRAR) ....................................................................... 733 15.3.12 Day of Week Alarm Register (RWKAR) ......................................................... 734 15.3.13 Date Alarm Register (RDAYAR) ..................................................................... 735 Page lxxii of cvi 15.4 15.5 15.3.14 Month Alarm Register (RMONAR) ................................................................. 736 15.3.15 Year Alarm Register (RYRAR) ........................................................................ 737 15.3.16 Control Register 1 (RCR1) ............................................................................... 738 15.3.17 Control Register 2 (RCR2) ............................................................................... 740 15.3.18 Control Register 3 (RCR3) ............................................................................... 742 15.3.19 Control Register 5 (RCR5) ............................................................................... 743 15.3.20 Frequency Register H/L (RFRH/L) .................................................................. 744 Operation .......................................................................................................................... 746 15.4.1 Initial Settings of Registers after Power-On ..................................................... 746 15.4.2 Setting Time...................................................................................................... 746 15.4.3 Reading Time.................................................................................................... 747 15.4.4 Alarm Function ................................................................................................. 748 Usage Notes ...................................................................................................................... 749 15.5.1 Register Writing during Count.......................................................................... 749 15.5.2 Use of Realtime Clock Periodic Interrupts ....................................................... 749 15.5.3 Transition to Standby Mode after Setting Register ........................................... 749 15.5.4 Usage Notes when Writing to and Reading the Register .................................. 750 Section 16 Serial Communication Interface with FIFO ....................................751 16.1 16.2 16.3 16.4 16.5 Features ............................................................................................................................. 751 Input/Output Pins .............................................................................................................. 754 Register Descriptions ........................................................................................................ 755 16.3.1 Receive Shift Register (SCRSR)....................................................................... 759 16.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 759 16.3.3 Transmit Shift Register (SCTSR) ..................................................................... 760 16.3.4 Transmit FIFO Data Register (SCFTDR) ......................................................... 760 16.3.5 Serial Mode Register (SCSMR) ........................................................................ 761 16.3.6 Serial Control Register (SCSCR) ...................................................................... 764 16.3.7 Serial Status Register (SCFSR) ........................................................................ 768 16.3.8 Bit Rate Register (SCBRR) .............................................................................. 776 16.3.9 FIFO Control Register (SCFCR) ...................................................................... 782 16.3.10 FIFO Data Count Set Register (SCFDR) .......................................................... 785 16.3.11 Serial Port Register (SCSPTR) ......................................................................... 786 16.3.12 Line Status Register (SCLSR) .......................................................................... 789 16.3.13 Serial Extension Mode Register (SCEMR)....................................................... 790 Operation .......................................................................................................................... 791 16.4.1 Overview........................................................................................................... 791 16.4.2 Operation in Asynchronous Mode .................................................................... 794 16.4.3 Operation in Clock Synchronous Mode ............................................................ 805 Interrupts ........................................................................................................................... 814 Page lxxiii of cvi 16.6 Usage Notes ...................................................................................................................... 815 16.6.1 SCFTDR Writing and TDFE Flag .................................................................... 815 16.6.2 SCFRDR Reading and RDF Flag ..................................................................... 815 16.6.3 Restriction on Direct Memory Controller Usage .............................................. 816 16.6.4 Break Detection and Processing ....................................................................... 816 16.6.5 Sending a Break Signal ..................................................................................... 816 16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 816 16.6.7 Selection of Base Clock in Asynchronous Mode.............................................. 818 Section 17 Renesas Serial Peripheral Interface ................................................. 819 17.1 17.2 17.3 17.4 Features ............................................................................................................................. 819 Input/Output Pins .............................................................................................................. 822 Register Descriptions ........................................................................................................ 823 17.3.1 Control Register (SPCR) .................................................................................. 825 17.3.2 Slave Select Polarity Register (SSLP) .............................................................. 827 17.3.3 Pin Control Register (SPPCR) .......................................................................... 828 17.3.4 Status Register (SPSR) ..................................................................................... 830 17.3.5 Data Register (SPDR) ....................................................................................... 833 17.3.6 Sequence Control Register (SPSCR) ................................................................ 834 17.3.7 Sequence Status Register (SPSSR) ................................................................... 836 17.3.8 Bit Rate Register (SPBR) ................................................................................. 837 17.3.9 Data Control Register (SPDCR) ....................................................................... 838 17.3.10 Clock Delay Register (SPCKD)........................................................................ 840 17.3.11 Slave Select Negation Delay Register (SSLND) .............................................. 841 17.3.12 Next-Access Delay Register (SPND) ............................................................... 842 17.3.13 Command Register (SPCMD) .......................................................................... 843 17.3.14 Buffer Control Register (SPBFCR) .................................................................. 848 17.3.15 Buffer Data Count Setting Register (SPBFDR) ................................................ 850 Operation .......................................................................................................................... 851 17.4.1 Overview of Operations .................................................................................... 851 17.4.2 Pin Control ........................................................................................................ 852 17.4.3 System Configuration Example ........................................................................ 853 17.4.4 Transfer Format ................................................................................................ 856 17.4.5 Data Format ...................................................................................................... 858 17.4.6 Error Detection ................................................................................................. 870 17.4.7 Initialization ...................................................................................................... 875 17.4.8 SPI Operation.................................................................................................... 876 17.4.9 Error Handling .................................................................................................. 889 17.4.10 Loopback Mode ................................................................................................ 890 17.4.11 Interrupt Sources ............................................................................................... 891 Page lxxiv of cvi Section 18 Renesas Quad Serial Peripheral Interface ........................................893 18.1 18.2 18.3 18.4 Features ............................................................................................................................. 893 Input/Output Pins .............................................................................................................. 895 Register Descriptions ........................................................................................................ 896 18.3.1 Control Register (SPCR)................................................................................... 899 18.3.2 Slave Select Polarity Register (SSLP) .............................................................. 900 18.3.3 Pin Control Register (SPPCR) .......................................................................... 901 18.3.4 Status Register (SPSR) ..................................................................................... 903 18.3.5 Data Register (SPDR) ....................................................................................... 906 18.3.6 Sequence Control Register (SPSCR) ................................................................ 907 18.3.7 Sequence Status Register (SPSSR) ................................................................... 908 18.3.8 Bit Rate Register (SPBR).................................................................................. 909 18.3.9 Data Control Register (SPDCR) ....................................................................... 911 18.3.10 Clock Delay Register (SPCKD)........................................................................ 912 18.3.11 Slave Select Negation Delay Register (SSLND) .............................................. 913 18.3.12 Next-Access Delay Register (SPND)................................................................ 914 18.3.13 Command Register n (SPCMDn) (n = 0 to 3)................................................... 915 18.3.14 Buffer Control Register (SPBFCR) .................................................................. 921 18.3.15 Buffer Data Count Register (SPBDCR)............................................................ 923 18.3.16 Transfer Data Length Multiplier Setting Register n (SPBMULn) (n = 0, 1, 2, 3) ........................................................................... 924 Operation .......................................................................................................................... 925 18.4.1 Overview of Operations .................................................................................... 925 18.4.2 Pin Control ........................................................................................................ 927 18.4.3 Transfer Format ................................................................................................ 928 18.4.4 Transfer Data .................................................................................................... 931 18.4.5 Non-Normal Transfer Operations ..................................................................... 938 18.4.6 Initialization ...................................................................................................... 939 18.4.7 SPI Operation.................................................................................................... 939 18.4.8 Interrupt Sources ............................................................................................... 953 18.4.9 Loopback Mode ................................................................................................ 954 Section 19 SPI Multi I/O Bus Controller ...........................................................955 19.1 19.2 19.3 19.4 Features ............................................................................................................................. 955 Block Diagram .................................................................................................................. 956 Input/Output Pins .............................................................................................................. 957 Register Descriptions ........................................................................................................ 958 19.4.1 Common Control Register (CMNCR) .............................................................. 959 19.4.2 SSL Delay Register (SSLDR) ........................................................................... 964 19.4.3 Bit Rate Register (SPBCR) ............................................................................... 966 Page lxxv of cvi 19.5 19.6 19.4.4 Data Read Control Register (DRCR) ................................................................ 968 19.4.5 Data Read Command Setting Register (DRCMR)............................................ 970 19.4.6 Data Read Extended Address Setting Register (DREAR) ................................ 971 19.4.7 Data Read Option Setting Register (DROPR) .................................................. 973 19.4.8 Data Read Enable Setting Register (DRENR) .................................................. 974 19.4.9 SPI Mode Control Register (SMCR) ................................................................ 977 19.4.10 SPI Mode Command Setting Register (SMCMR) ............................................ 979 19.4.11 SPI Mode Address Setting Register (SMADR) ................................................ 980 19.4.12 SPI Mode Option Setting Register (SMOPR)................................................... 981 19.4.13 SPI Mode Enable Setting Register (SMENR) .................................................. 982 19.4.14 SPI Mode Read Data Register 0 (SMRDR0) .................................................... 986 19.4.15 SPI Mode Read Data Register 1 (SMRDR1) .................................................... 987 19.4.16 SPI Mode Write Data Register 0 (SMWDR0) .................................................. 988 19.4.17 SPI Mode Write Data Register 1 (SMWDR1) .................................................. 989 19.4.18 Common Status Register (CMNSR) ................................................................. 990 Operation .......................................................................................................................... 991 19.5.1 System Configuration ....................................................................................... 991 19.5.2 Address Map ..................................................................................................... 992 19.5.3 32-bit Serial Flash Addresses............................................................................ 993 19.5.4 Data Alignment ................................................................................................. 994 19.5.5 Operating Modes .............................................................................................. 995 19.5.6 External Address Space Read Mode ................................................................. 995 19.5.7 Read Cache ..................................................................................................... 1000 19.5.8 SPI Operating Mode ....................................................................................... 1001 19.5.9 Transfer Format .............................................................................................. 1006 19.5.10 Data Format .................................................................................................... 1008 19.5.11 Data Pin Control ............................................................................................. 1016 19.5.12 SPBSSL Pin Control ....................................................................................... 1018 19.5.13 Flags................................................................................................................ 1019 Usage Note ..................................................................................................................... 1019 19.6.1 Note on Transfer Start from SPBSSL Hold State in SPI Operation Mode ..... 1019 Section 20 I2C Bus Interface 3......................................................................... 1021 20.1 20.2 20.3 Features ........................................................................................................................... 1021 Input/Output Pins ............................................................................................................ 1023 Register Descriptions ...................................................................................................... 1024 20.3.1 I2C Bus Control Register 1 (ICCR1) ............................................................... 1025 20.3.2 I2C Bus Control Register 2 (ICCR2) ............................................................... 1028 20.3.3 I2C Bus Mode Register (ICMR) ...................................................................... 1030 20.3.4 I2C Bus Interrupt Enable Register (ICIER) ..................................................... 1032 Page lxxvi of cvi 20.4 20.5 20.6 20.7 20.3.5 I2C Bus Status Register (ICSR) ....................................................................... 1034 20.3.6 Slave Address Register (SAR) ........................................................................ 1037 20.3.7 I2C Bus Transmit Data Register (ICDRT)....................................................... 1037 20.3.8 I2C Bus Receive Data Register (ICDRR) ........................................................ 1038 20.3.9 I2C Bus Shift Register (ICDRS) ...................................................................... 1038 20.3.10 NF2CYC Register (NF2CYC) ........................................................................ 1039 Operation ........................................................................................................................ 1040 20.4.1 I2C Bus Format ................................................................................................ 1040 20.4.2 Master Transmit Operation ............................................................................. 1041 20.4.3 Master Receive Operation............................................................................... 1043 20.4.4 Slave Transmit Operation ............................................................................... 1045 20.4.5 Slave Receive Operation ................................................................................. 1048 20.4.6 Clocked Synchronous Serial Format............................................................... 1049 20.4.7 Noise Filter ..................................................................................................... 1053 20.4.8 Example of Use ............................................................................................... 1054 Interrupt Requests ........................................................................................................... 1058 Bit Synchronous Circuit.................................................................................................. 1059 Usage Notes .................................................................................................................... 1061 20.7.1 Note on Setting for Multi-Master Operation ................................................... 1061 20.7.2 Note on Master Receive Mode........................................................................ 1061 20.7.3 Note on Setting ACKBT in Master Receive Mode ......................................... 1062 20.7.4 Note on the States of Bits MST and TRN when Arbitration is Lost ............... 1062 20.7.5 Note on I2C-Bus Interface Master Receive Mode ........................................... 1062 20.7.6 Note on IICRST and BBSY bits ..................................................................... 1062 20.7.7 Note on Issuance of Stop Conditions in Master Transmit Mode while ACKE = 1 ............................................................................................. 1062 Section 21 Serial Sound Interface ....................................................................1063 21.1 21.2 21.3 Features ........................................................................................................................... 1063 Input/Output Pins ............................................................................................................ 1065 Register Description ....................................................................................................... 1066 21.3.1 Control Register (SSICR) ............................................................................... 1069 21.3.2 Status Register (SSISR) .................................................................................. 1077 21.3.3 Transmit Data Register (SSITDR) .................................................................. 1081 21.3.4 Receive Data Register (SSIRDR) ................................................................... 1081 21.3.5 FIFO Control Register (SSIFCR) ................................................................... 1082 21.3.6 FIFO Status Register (SSIFSR) ...................................................................... 1085 21.3.7 Transmit FIFO Data Register (SSIFTDR) ...................................................... 1088 21.3.8 Receive FIFO Data Register (SSIFRDR) ....................................................... 1089 21.3.9 TDM Mode Register (SSITDMR) .................................................................. 1090 Page lxxvii of cvi 21.4 21.5 Operation Description ..................................................................................................... 1091 21.4.1 Bus Format...................................................................................................... 1091 21.4.2 Non-Compressed Modes................................................................................. 1093 21.4.3 TDM Mode ..................................................................................................... 1103 21.4.4 WS Continue Mode ........................................................................................ 1104 21.4.5 Operation Modes ............................................................................................ 1105 21.4.6 Transmit Operation ......................................................................................... 1106 21.4.7 Receive Operation .......................................................................................... 1109 21.4.8 Serial Bit Clock Control ................................................................................. 1112 Usage Notes .................................................................................................................... 1113 21.5.1 Limitations from Underflow or Overflow during DMA Operation ................ 1113 21.5.2 Note on Changing Mode from Master Transceiver to Master Receiver ......... 1113 21.5.3 Limits on TDM mode and WS Continue Mode .............................................. 1113 Section 22 Serial I/O with FIFO ...................................................................... 1115 22.1 22.2 22.3 22.4 Features ........................................................................................................................... 1115 Input/Output Pins ............................................................................................................ 1117 Register Descriptions ...................................................................................................... 1118 22.3.1 Mode Register (SIMDR) ................................................................................ 1119 22.3.2 Control Register (SICTR) ............................................................................... 1121 22.3.3 Transmit Data Register (SITDR) .................................................................... 1124 22.3.4 Receive Data Register (SIRDR) ..................................................................... 1125 22.3.5 Status Register (SISTR) .................................................................................. 1126 22.3.6 Interrupt Enable Register (SIIER) .................................................................. 1131 22.3.7 FIFO Control Register (SIFCTR) ................................................................... 1133 22.3.8 Clock Select Register (SISCR) ....................................................................... 1135 22.3.9 Transmit Data Assign Register (SITDAR) ..................................................... 1136 22.3.10 Receive Data Assign Register (SIRDAR) ...................................................... 1138 Operation ........................................................................................................................ 1139 22.4.1 Serial Clocks ................................................................................................... 1139 22.4.2 Serial Timing .................................................................................................. 1140 22.4.3 Transfer Data Format ...................................................................................... 1141 22.4.4 Register Allocation of Transfer Data .............................................................. 1142 22.4.5 FIFO................................................................................................................ 1144 22.4.6 Transmit and Receive Procedures ................................................................... 1146 22.4.7 Interrupts ......................................................................................................... 1151 22.4.8 Transmit and Receive Timing ......................................................................... 1153 Page lxxviii of cvi Section 23 Controller Area Network ...............................................................1157 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 Summary ......................................................................................................................... 1157 23.1.1 Overview......................................................................................................... 1157 23.1.2 Scope............................................................................................................... 1157 23.1.3 Audience ......................................................................................................... 1157 23.1.4 References....................................................................................................... 1158 23.1.5 Features ........................................................................................................... 1158 Architecture .................................................................................................................... 1159 Programming Model - Overview .................................................................................... 1162 23.3.1 Memory Map .................................................................................................. 1162 23.3.2 Mailbox Structure ........................................................................................... 1164 23.3.3 Control Registers ............................................................................................ 1180 23.3.4 Mailbox Registers ........................................................................................... 1201 23.3.5 Timer Registers ............................................................................................... 1215 Application Note ............................................................................................................. 1228 23.4.1 Test Mode Settings ......................................................................................... 1228 23.4.2 Configuration of This Module ........................................................................ 1230 23.4.3 Message Transmission Sequence .................................................................... 1234 23.4.4 Message Receive Sequence ............................................................................ 1249 23.4.5 Reconfiguration of Mailbox ............................................................................ 1251 Interrupt Sources ............................................................................................................. 1253 DMAC Interface ............................................................................................................. 1254 CAN Bus Interface.......................................................................................................... 1255 Setting I/O Ports.............................................................................................................. 1256 Usage Notes .................................................................................................................... 1259 23.9.1 Notes on Port Setting for Multiple Channels Used as Single Channel with 64 or 96 Mailboxes ................................................................................. 1259 Section 24 IEBusTM Controller .........................................................................1261 24.1 24.2 24.3 Features ........................................................................................................................... 1261 24.1.1 IEBus Communications Protocol .................................................................... 1263 24.1.2 Communications Protocol ............................................................................... 1267 24.1.3 Transfer Data (Data Field Contents) ............................................................... 1275 24.1.4 Bit Format ....................................................................................................... 1278 24.1.5 Configuration .................................................................................................. 1279 Input/Output Pins ............................................................................................................ 1280 Register Descriptions ...................................................................................................... 1281 24.3.1 IEBus Control Register (IECTR) .................................................................... 1283 24.3.2 IEBus Command Register (IECMR) .............................................................. 1284 Page lxxix of cvi 24.4 24.5 24.6 24.7 24.8 24.3.3 IEBus Master Control Register (IEMCR) ....................................................... 1286 24.3.4 IEBus Master Unit Address Register 1 (IEAR1) ............................................ 1288 24.3.5 IEBus Master Unit Address Register 2 (IEAR2) ............................................ 1289 24.3.6 IEBus Slave Address Setting Register 1 (IESA1)........................................... 1289 24.3.7 IEBus Slave Address Setting Register 2 (IESA2)........................................... 1290 24.3.8 IEBus Transmit Message Length Register (IETBFL) .................................... 1290 24.3.9 IEBus Reception Master Address Register 1 (IEMA1) .................................. 1291 24.3.10 IEBus Reception Master Address Register 2 (IEMA2) .................................. 1292 24.3.11 IEBus Receive Control Field Register (IERCTL) .......................................... 1293 24.3.12 IEBus Receive Message Length Register (IERBFL) ...................................... 1294 24.3.13 IEBus Lock Address Register 1 (IELA1) ....................................................... 1294 24.3.14 IEBus Lock Address Register 2 (IELA2) ....................................................... 1295 24.3.15 IEBus General Flag Register (IEFLG)............................................................ 1296 24.3.16 IEBus Transmit Status Register (IETSR) ....................................................... 1299 24.3.17 IEBus Transmit Interrupt Enable Register (IEIET) ........................................ 1303 24.3.18 IEBus Receive Status Register (IERSR) ......................................................... 1305 24.3.19 IEBus Receive Interrupt Enable Register (IEIER).......................................... 1309 24.3.20 IEBus Clock Selection Register (IECKSR) .................................................... 1310 24.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128) ................... 1312 24.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128) .................... 1313 Data Format .................................................................................................................... 1314 24.4.1 Transmission Format ...................................................................................... 1314 24.4.2 Reception Format............................................................................................ 1315 Software Control Flows .................................................................................................. 1316 24.5.1 Initial Setting .................................................................................................. 1316 24.5.2 Master Transmission ....................................................................................... 1317 24.5.3 Slave Reception .............................................................................................. 1318 24.5.4 Master Reception ............................................................................................ 1319 24.5.5 Slave Transmission ......................................................................................... 1320 Operation Timing............................................................................................................ 1321 24.6.1 Master Transmit Operation ............................................................................. 1321 24.6.2 Slave Receive Operation ................................................................................. 1322 24.6.3 Master Receive Operation .............................................................................. 1323 24.6.4 Slave Transmit Operation ............................................................................... 1324 Interrupt Sources ............................................................................................................. 1325 Usage Notes .................................................................................................................... 1327 24.8.1 Note on Operation when Transfer is Incomplete after Transfer of the Maximum Number of Bytes .......................................... 1327 Page lxxx of cvi Section 25 Renesas SPDIF Interface ...............................................................1329 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.10 25.11 25.12 25.13 Overview......................................................................................................................... 1329 Features ........................................................................................................................... 1329 Functional Block Diagram .............................................................................................. 1330 Input/Output Pins ............................................................................................................ 1331 Renesas SPDIF (IEC60958) Frame Format .................................................................... 1331 Register ........................................................................................................................... 1333 Register Descriptions ...................................................................................................... 1334 25.7.1 Control Register (CTRL) ................................................................................ 1334 25.7.2 Status Register (STAT) ................................................................................... 1339 25.7.3 Transmitter Channel 1 Audio Register (TLCA) ............................................. 1343 25.7.4 Transmitter Channel 2 Audio Register (TRCA) ............................................. 1344 25.7.5 Transmitter DMA Audio Data Register (TDAD) ........................................... 1345 25.7.6 Transmitter User Data Register (TUI) ............................................................ 1346 25.7.7 Transmitter Channel 1 Status Register (TLCS) .............................................. 1347 25.7.8 Transmitter Channel 2 Status Register (TRCS) .............................................. 1349 25.7.9 Receiver Channel 1 Audio Register (RLCA).................................................. 1351 25.7.10 Receiver Channel 2 Audio Register (RRCA) ................................................. 1352 25.7.11 Receiver DMA Audio Data (RDAD).............................................................. 1353 25.7.12 Receiver User Data Register (RUI) ................................................................ 1354 25.7.13 Receiver Channel 1 Status Register (RLCS) .................................................. 1355 25.7.14 Receiver Channel 2 Status Register (RRCS) .................................................. 1357 Functional Description—Transmitter ............................................................................. 1359 25.8.1 Transmitter Module ........................................................................................ 1359 25.8.2 Transmitter Module Initialization ................................................................... 1360 25.8.3 Initial Settings for Transmitter Module .......................................................... 1360 25.8.4 Transmitter Module Data Transfer ................................................................. 1361 Functional Description—Receiver .................................................................................. 1363 25.9.1 Receiver Module ............................................................................................. 1363 25.9.2 Receiver Module Initialization........................................................................ 1364 25.9.3 Receiver Module Data Transfer ...................................................................... 1364 Disabling the Module...................................................................................................... 1367 25.10.1 Transmitter and Receiver Idle ......................................................................... 1367 Compressed Mode Data .................................................................................................. 1367 References....................................................................................................................... 1367 Usage Notes .................................................................................................................... 1368 25.13.1 Clearing TUIR ................................................................................................ 1368 25.13.2 Frequency of Clock Input for Audio ............................................................... 1368 Page lxxxi of cvi Section 26 CD-ROM Decoder......................................................................... 1369 26.1 26.2 26.3 Features ........................................................................................................................... 1369 26.1.1 Formats Supported by CD-ROM Decoder...................................................... 1370 Block Diagrams .............................................................................................................. 1371 Register Descriptions ...................................................................................................... 1375 26.3.1 Enable Control Register (CROMEN) ............................................................. 1378 26.3.2 Sync Code-Based Synchronization Control Register (CROMSY0) ............... 1379 26.3.3 Decoding Mode Control Register (CROMCTL0) .......................................... 1380 26.3.4 EDC/ECC Check Control Register (CROMCTL1) ........................................ 1382 26.3.5 Automatic Decoding Stop Control Register (CROMCTL3)........................... 1383 26.3.6 Decoding Option Setting Control Register (CROMCTL4) ............................ 1384 26.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5) ........ 1386 26.3.8 Sync Code Status Register (CROMST0) ........................................................ 1387 26.3.9 Post-ECC Header Error Status Register (CROMST1).................................... 1388 26.3.10 Post-ECC Subheader Error Status Register (CROMST3) .............................. 1389 26.3.11 Header/Subheader Validity Check Status Register (CROMST4) ................... 1390 26.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5) ................................................................................................... 1391 26.3.13 ECC/EDC Error Status Register (CROMST6) ............................................... 1392 26.3.14 Buffer Status Register (CBUFST0) ................................................................ 1394 26.3.15 Decoding Stoppage Source Status Register (CBUFST1) ............................... 1395 26.3.16 Buffer Overflow Status Register (CBUFST2) ................................................ 1396 26.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00) ................... 1396 26.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01) ................... 1397 26.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02) ................................................................................ 1397 26.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03) ....................... 1398 26.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00) .................................................................................................................... 1398 26.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01) .................................................................................................................... 1399 26.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02).............................................................................. 1399 26.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03).............................................................................. 1400 26.3.25 Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04).............................................................................. 1400 26.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05).............................................................................. 1401 Page lxxxii of cvi 26.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06) .............................................................................. 1401 26.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07) .............................................................................. 1402 26.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20).................. 1402 26.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21) ................. 1403 26.3.31 Post-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD22) ................................................................................ 1403 26.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23) ..................... 1404 26.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20) .............................................................................. 1404 26.3.34 Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21) .............................................................................. 1405 26.3.35 Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22) .................................................................................................................... 1405 26.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23) .................................................................................................................... 1406 26.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24) .................................................................................................................... 1406 26.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25) .............................................................................. 1407 26.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26) .............................................................................. 1407 26.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27) .............................................................................. 1408 26.3.41 Automatic Buffering Setting Control Register 0 (CBUFCTL0) ..................... 1408 26.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1).................................................................................... 1410 26.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2).................................................................................... 1410 26.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3).................................................................................... 1411 26.3.45 ISY Interrupt Source Mask Control Register (CROMST0M) ........................ 1411 26.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST) ......................... 1412 26.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) .................................. 1413 26.3.48 Serial Sound Interface Data Control Register (SSI)........................................ 1413 26.3.49 Interrupt Flag Register (INTHOLD) ............................................................... 1416 26.3.50 Interrupt Source Mask Control Register (INHINT) ........................................ 1417 26.3.51 CD-ROM Decoder Stream Data Input Register (STRMDIN0) ...................... 1418 26.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN2) ...................... 1418 Page lxxxiii of cvi 26.4 26.5 26.6 26.3.53 CD-ROM Decoder Stream Data Output Register (STRMDOUT0) ............... 1419 Operation ........................................................................................................................ 1420 26.4.1 Endian Conversion for Data in the Input Stream ............................................ 1420 26.4.2 Sync Code Maintenance Function .................................................................. 1421 26.4.3 Error Correction .............................................................................................. 1426 26.4.4 Automatic Decoding Stop Function................................................................ 1427 26.4.5 Buffering Format ............................................................................................ 1428 26.4.6 Target-Sector Buffering Function ................................................................... 1430 Interrupt Sources ............................................................................................................. 1432 26.5.1 Interrupt and DMA Transfer Request Signals ................................................ 1432 26.5.2 Timing of Status Registers Updates ................................................................ 1434 Usage Notes .................................................................................................................... 1434 26.6.1 Stopping and Resuming Buffering Alone during Decoding ........................... 1434 26.6.2 When CROMST0 Status Register Bits are Set ............................................... 1434 26.6.3 Link Blocks..................................................................................................... 1435 26.6.4 Stopping and Resuming CD-DSP Operation .................................................. 1435 26.6.5 Note on Clearing the IREADY Flag ............................................................... 1435 26.6.6 Note on Stream Data Transfer (1) ................................................................... 1436 26.6.7 Note on Stream Data Transfer (2) ................................................................... 1436 Section 27 A/D Converter ............................................................................... 1437 27.1 27.2 27.3 27.4 27.5 27.6 27.7 Features ........................................................................................................................... 1437 Input/Output Pins ............................................................................................................ 1439 Register Descriptions ...................................................................................................... 1440 27.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1441 27.3.2 A/D Control/Status Register (ADCSR) .......................................................... 1442 Operation ........................................................................................................................ 1446 27.4.1 Single Mode .................................................................................................... 1446 27.4.2 Multi Mode ..................................................................................................... 1449 27.4.3 Scan Mode ...................................................................................................... 1451 27.4.4 A/D Converter Activation by External Trigger or Multi-Function Timer Pulse Unit 2................................................................ 1454 27.4.5 Input Sampling and A/D Conversion Time .................................................... 1454 27.4.6 External Trigger Input Timing ........................................................................ 1457 Interrupt Sources and DMA Transfer Request ............................................................... 1458 Definitions of A/D Conversion Accuracy ....................................................................... 1459 Usage Notes .................................................................................................................... 1460 27.7.1 Module Standby Mode Setting ....................................................................... 1460 27.7.2 Setting Analog Input Voltage ......................................................................... 1460 27.7.3 Notes on Board Design ................................................................................... 1460 Page lxxxiv of cvi 27.7.4 27.7.5 27.7.6 27.7.7 Processing of Analog Input Pins ..................................................................... 1461 Permissible Signal Source Impedance ............................................................ 1462 Influences on Absolute Precision .................................................................... 1463 Note on Usage in Scan Mode and Multi Mode ............................................... 1463 Section 28 NAND Flash Memory Controller ..................................................1465 28.1 28.2 28.3 28.4 28.5 28.6 28.7 Features ........................................................................................................................... 1465 Input/Output Pins ............................................................................................................ 1468 Register Descriptions ...................................................................................................... 1469 28.3.1 Common Control Register (FLCMNCR)........................................................ 1470 28.3.2 Command Control Register (FLCMDCR) ...................................................... 1473 28.3.3 Command Code Register (FLCMCDR).......................................................... 1476 28.3.4 Address Register (FLADR) ............................................................................ 1477 28.3.5 Address Register 2 (FLADR2) ....................................................................... 1479 28.3.6 Data Counter Register (FLDTCNTR)............................................................. 1480 28.3.7 Data Register (FLDATAR)............................................................................. 1481 28.3.8 Interrupt DMA Control Register (FLINTDMACR) ....................................... 1482 28.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ................................... 1487 28.3.10 Ready Busy Timeout Counter (FLBSYCNT) ................................................. 1488 28.3.11 Data FIFO Register (FLDTFIFO) ................................................................... 1489 28.3.12 Control Code FIFO Register (FLECFIFO) ..................................................... 1490 28.3.13 Transfer Control Register (FLTRCR) ............................................................. 1491 28.3.14 Bus Hold Time Setting Register (FLHOLDCR) ............................................. 1492 Operation ........................................................................................................................ 1493 28.4.1 Access Sequence ............................................................................................. 1493 28.4.2 Operating Modes............................................................................................. 1493 28.4.3 Register Setting Procedure .............................................................................. 1494 28.4.4 Command Access Mode ................................................................................. 1495 28.4.5 Sector Access Mode........................................................................................ 1499 28.4.6 Status Read ..................................................................................................... 1504 Interrupt Sources ............................................................................................................. 1505 DMA Transfer Specifications ......................................................................................... 1505 Usage Notes .................................................................................................................... 1506 28.7.1 External Bus Mastership Release Timing ....................................................... 1506 28.7.2 Usage Notes for the SNAND Bit .................................................................... 1507 Section 29 USB 2.0 Host/Function Module ....................................................1509 29.1 29.2 29.3 Features ........................................................................................................................... 1509 Input/Output Pins ............................................................................................................ 1511 Register Description ....................................................................................................... 1513 Page lxxxv of cvi 29.4 29.3.1 System Configuration Control Register (SYSCFG) ....................................... 1516 29.3.2 CPU Bus Wait Setting Register (BUSWAIT) ................................................ 1521 29.3.3 System Configuration Status Register (SYSSTS)........................................... 1522 29.3.4 Device State Control Register (DVSTCTR) ................................................... 1523 29.3.5 Test Mode Register (TESTMODE) ................................................................ 1529 29.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) .............. 1532 29.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) .......................................... 1533 29.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)........... 1535 29.3.9 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ...... 1543 29.3.10 Interrupt Enable Register 0 (INTENB0) ......................................................... 1547 29.3.11 Interrupt Enable Register 1 (INTENB1) ......................................................... 1549 29.3.12 BRDY Interrupt Enable Register (BRDYENB) ............................................. 1551 29.3.13 NRDY Interrupt Enable Register (NRDYENB) ............................................. 1552 29.3.14 BEMP Interrupt Enable Register (BEMPENB) .............................................. 1554 29.3.15 SOF Output Configuration Register (SOFCFG) ............................................. 1555 29.3.16 Interrupt Status Register 0 (INTSTS0) ........................................................... 1557 29.3.17 Interrupt Status Register 1 (INTSTS1) ........................................................... 1562 29.3.18 BRDY Interrupt Status Register (BRDYSTS) ................................................ 1568 29.3.19 NRDY Interrupt Status Register (NRDYSTS) ............................................... 1570 29.3.20 BEMP Interrupt Status Register (BEMPSTS) ................................................ 1572 29.3.21 Frame Number Register (FRMNUM)............................................................. 1573 29.3.22 Frame Number Register (UFRMNUM) ....................................................... 1576 29.3.23 USB Address Register (USBADDR).............................................................. 1577 29.3.24 USB Request Type Register (USBREQ) ........................................................ 1578 29.3.25 USB Request Value Register (USBVAL) ...................................................... 1579 29.3.26 USB Request Index Register (USBINDX) ..................................................... 1580 29.3.27 USB Request Length Register (USBLENG) .................................................. 1581 29.3.28 DCP Configuration Register (DCPCFG) ........................................................ 1582 29.3.29 DCP Maximum Packet Size Register (DCPMAXP) ...................................... 1584 29.3.30 DCP Control Register (DCPCTR) .................................................................. 1585 29.3.31 Pipe Window Select Register (PIPESEL) ....................................................... 1595 29.3.32 Pipe Configuration Register (PIPECFG) ........................................................ 1596 29.3.33 Pipe Buffer Setting Register (PIPEBUF) ........................................................ 1603 29.3.34 Pipe Maximum Packet Size Register (PIPEMAXP) ....................................... 1606 29.3.35 Pipe Timing Control Register (PIPEPERI) ..................................................... 1608 29.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) ......................................... 1610 29.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)......... 1631 29.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) .................... 1633 29.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A) ........... 1635 Operation ........................................................................................................................ 1638 Page lxxxvi of cvi 29.5 29.4.1 System Control and Oscillation Control ......................................................... 1638 29.4.2 Interrupt Functions .......................................................................................... 1643 29.4.3 Pipe Control .................................................................................................... 1666 29.4.4 FIFO Buffer Memory...................................................................................... 1676 29.4.5 Control Transfers (DCP) ................................................................................. 1691 29.4.6 Bulk Transfers (PIPE1 to PIPE5).................................................................... 1694 29.4.7 Interrupt Transfers (PIPE6 to PIPE9) ............................................................. 1696 29.4.8 Isochronous Transfers (PIPE1 and PIPE2) ..................................................... 1697 29.4.9 SOF Interpolation Function ............................................................................ 1709 29.4.10 Pipe Schedule.................................................................................................. 1710 Usage Notes .................................................................................................................... 1712 29.5.1 Power Supply for USB Transceiver ................................................................ 1712 Section 30 Digital Video Decoder ...................................................................1713 30.1 30.2 30.3 30.4 Features ........................................................................................................................... 1713 Block Diagram ................................................................................................................ 1715 Input/Output Pins ............................................................................................................ 1716 Register Descriptions ...................................................................................................... 1717 30.4.1 ADC Control Register 1 (ADCCR1) .............................................................. 1722 30.4.2 Timing Generation Control Register 1 (TGCR1) ........................................... 1723 30.4.3 Timing Generation Control Register 2 (TGCR2) ........................................... 1724 30.4.4 Timing Generation Control Register 3 (TGCR3) ........................................... 1725 30.4.5 Sync Separation Control Register 1 (SYNSCR1) ........................................... 1729 30.4.6 Sync Separation Control Register 2 (SYNSCR2) ........................................... 1735 30.4.7 Sync Separation Control Register 3 (SYNSCR3) ........................................... 1737 30.4.8 Sync Separation Control Register 4 (SYNSCR4) ........................................... 1739 30.4.9 Sync Separation Control Register 5 (SYNSCR5) ........................................... 1741 30.4.10 Horizontal AFC Control Register 1 (HAFCCR1) ........................................... 1743 30.4.11 Horizontal AFC Control Register 2 (HAFCCR2) ........................................... 1746 30.4.12 Horizontal AFC Control Register 3 (HAFCCR3) ........................................... 1748 30.4.13 Vertical Countdown Control Register 1 (VCDWCR1)................................... 1749 30.4.14 Digital Clamp Control Register 1 (DCPCR1) ................................................. 1751 30.4.15 Digital Clamp Control Register 2 (DCPCR2) ................................................. 1753 30.4.16 Digital Clamp Control Register 3 (DCPCR3) ................................................. 1755 30.4.17 Digital Clamp Control Register 4 (DCPCR4) ................................................. 1756 30.4.18 Digital Clamp Control Register 5 (DCPCR5) ................................................. 1757 30.4.19 Digital Clamp Control Register 6 (DCPCR6) ................................................. 1758 30.4.20 Digital Clamp Control Register 7 (DCPCR7) ................................................. 1759 30.4.21 Digital Clamp Control Register 8 (DCPCR8) ................................................. 1760 30.4.22 Noise Detection Control Register (NSDCR) .................................................. 1761 Page lxxxvii of cvi 30.4.23 30.4.24 30.4.25 30.4.26 30.4.27 30.4.28 30.4.29 30.4.30 30.4.31 30.4.32 30.4.33 30.4.34 30.4.35 30.4.36 30.4.37 30.4.38 30.4.39 30.4.40 30.4.41 30.4.42 30.4.43 30.4.44 30.4.45 30.4.46 30.4.47 30.4.48 30.4.49 30.4.50 30.4.51 30.4.52 30.4.53 30.4.54 30.4.55 30.4.56 30.4.57 30.4.58 30.4.59 30.4.60 30.4.61 Page lxxxviii of cvi Burst Lock/Chroma Decoding Control Register (BTLCR) ............................ 1763 Burst Gate Pulse Control Register (BTGPCR) ............................................... 1768 ACC Control Register 1 (ACCCR1)............................................................... 1770 ACC Control Register 2 (ACCCR2)............................................................... 1774 ACC Control Register 3 (ACCCR3)............................................................... 1775 TINT Control Register (TINTCR) .................................................................. 1777 Y/C Delay/Chroma Decoding Control Register (YCDCR) ............................ 1779 AGC Control Register 1 (AGCCR1) .............................................................. 1781 AGC Control Register 2 (AGCCR2) .............................................................. 1784 Peak Limiter Control Register (PKLIMTCR)................................................. 1785 Over-Range Control Register 1 (RGORCR1)................................................. 1788 Over-Range Control Register 2 (RGORCR2)................................................. 1789 Over-Range Control Register 3 (RGORCR3)................................................. 1790 Over-Range Control Register 4 (RGORCR4)................................................. 1791 Over-Range Control Register 5 (RGORCR5)................................................. 1792 Over-Range Control Register 6 (RGORCR6)................................................. 1793 Over-Range Control Register 7 (RGORCR7)................................................. 1794 Feedback Control Register for Horizontal AFC Phase Comparator (AFCPFCR) .................................................................................................... 1796 Register Update Enable Register (RUPDCR) ................................................. 1798 Sync Separation Status/Vertical Cycle Read Register (VSYNCSR) .............. 1799 Horizontal Cycle Read Register (HSYNCSR)................................................ 1801 Digital Clamp Read Register 1 (DCPSR1) ..................................................... 1802 Digital Clamp Read Register 2 (DCPSR2) ..................................................... 1803 Noise Detection Read Register (NSDSR) ....................................................... 1804 Chroma Decoding Read Register 1 (CROMASR1)........................................ 1805 Chroma Decode Read Register 2 (CROMASR2) ........................................... 1807 Sync Separation Read Register (SYNCSSR).................................................. 1809 AGC Control Read Register 1 (AGCCSR1) ................................................... 1810 AGC Control Read Register 2 (AGCCSR2) ................................................... 1811 Y/C Separation Control Register 3 (YCSCR3)............................................... 1812 Y/C Separation Control Register 4 (YCSCR4)............................................... 1813 Y/C Separation Control Register 5 (YCSCR5)............................................... 1814 Y/C Separation Control Register 6 (YCSCR6)............................................... 1815 Y/C Separation Control Register 7 (YCSCR7)............................................... 1816 Y/C Separation Control Register 8 (YCSCR8)............................................... 1818 Y/C Separation Control Register 9 (YCSCR9)............................................... 1820 Y/C Separation Control Register 11 (YCSCR11) ........................................... 1824 Y/C Separation Control Register 12 (YCSCR12) ........................................... 1825 Digital Clamp Control Register 9 (DCPCR9)................................................. 1828 30.4.62 30.5 30.6 30.7 Chroma Filter TAP Coefficient (WA_F0 to WA_F8) Registers for Y/C Separation (YCTWA_F0 to YCTWA_F8) ........................ 1830 30.4.63 Chroma Filter TAP Coefficient (WB_F0 to WB_F8) Registers for Y/C Separation (YCTWB_F0 to YCTWB_F8)......................... 1832 30.4.64 Chroma Filter TAP Coefficient (NA_F0 to NA_F8) Registers for Y/C Separation (YCTNA_F0 to YCTNA_F8) .......................... 1834 30.4.65 Chroma Filter TAP Coefficient (NB_F0 to NB_F8) Registers for Y/C Separation (YCTNB_F0 to YCTNB_F8) .......................... 1836 30.4.66 Luminance (Y) Signal Gain Control Register (YGAINCR) ........................... 1838 30.4.67 Color Difference (Cb) Signal Gain Control Register (CBGAINCR) .............. 1839 30.4.68 Color Difference (Cr) Signal Gain Control Register (CRGAINCR) .............. 1840 30.4.69 PGA Register Update (PGA_UPDATE) ........................................................ 1841 30.4.70 PGA Control Register (PGACR) .................................................................... 1842 30.4.71 ADC Control Register 2 (ADCCR2) .............................................................. 1844 Operation ........................................................................................................................ 1845 30.5.1 Overview......................................................................................................... 1845 30.5.2 A/D Converter for Video Signal Input ............................................................ 1847 30.5.3 Sync Separator Circuit .................................................................................... 1850 30.5.4 Burst Controlled Oscillator (BCO) ................................................................. 1855 30.5.5 Y/C Separator Circuit ..................................................................................... 1857 30.5.6 Chroma Decoding Circuit ............................................................................... 1867 30.5.7 Digital Clamp Circuit...................................................................................... 1869 30.5.8 Output Control Circuit .................................................................................... 1871 Recommended Setting .................................................................................................... 1873 Connection Example ....................................................................................................... 1879 Section 31 Video Display Controller 4 (1): Overview ...................................1881 31.1 31.2 31.3 31.4 31.5 Features ........................................................................................................................... 1881 Block Diagram ................................................................................................................ 1885 Input/Output Pins ............................................................................................................ 1886 Clocks ............................................................................................................................. 1887 Hsync and Vsync Signals................................................................................................ 1888 Section 32 Video Display Controller 4 (2): Input Controller .........................1891 32.1 Input Controller Functions .............................................................................................. 1891 32.1.1 Overview of Functions.................................................................................... 1891 32.1.2 Updating Registers of External Signal Input Block and Sync Signal Adjustment Block ....................................................................... 1892 32.1.3 Selecting Input Signals ................................................................................... 1893 32.1.4 Controlling Externally Input Video Signals .................................................... 1894 Page lxxxix of cvi 32.2 32.3 32.1.5 Selecting Clock Edge for Externally Input Signals......................................... 1895 32.1.6 Externally Input Sync Signal Inversion Control ............................................. 1895 32.1.7 Bit Allocation of Externally Input Video Image Signals ................................ 1896 32.1.8 Typical Signal Timing of BT601 Format ....................................................... 1901 32.1.9 Typical Signal Timing of BT656 Format ....................................................... 1904 32.1.10 SAV/EAV Code in BT656 Format ................................................................. 1906 32.1.11 BT656/BT601 Format Setting ........................................................................ 1910 32.1.12 YCbCr444/RBG888/666/565 Input Timing ................................................... 1912 32.1.13 Field Differentiation and Vsync Signal Phase Adjustment ............................. 1914 32.1.14 Vsync Signal Delay Adjustment in Line Units ............................................... 1915 32.1.15 Sync Signal Delay Adjustment ....................................................................... 1916 32.1.16 Horizontal Noise Reduction............................................................................ 1916 32.1.17 Color Matrix ................................................................................................... 1920 Register Descriptions ...................................................................................................... 1925 32.2.1 External Input Block Register Update Control Register (INP_UPDATE) ..... 1927 32.2.2 Input Select Control Register (INP_SEL_CNT) ............................................. 1927 32.2.3 External Input Sync Signal Control Register (INP_EXT_SYNC_CNT) ........ 1930 32.2.4 Vsync Signal Phase Adjustment Register (INP_VSYNC_PH_ADJ) ............. 1932 32.2.5 Sync Signal Delay Adjustment Register (INP_DLY_ADJ) ........................... 1932 32.2.6 Image Quality Adjustment Block Register Update Control Register (IMGCNT_UPDATE) .................................................................................... 1934 32.2.7 NR Control Register 0 (IMGCNT_NR_CNT0).............................................. 1935 32.2.8 NR Control Register 1 (IMGCNT_NR_CNT1).............................................. 1937 32.2.9 Image Quality Adjustment Block Matrix Mode Register (IMGCNT_MTX_MODE) ............................................................................. 1939 32.2.10 Image Quality Adjustment Block Matrix YG Adjustment Register 0 (IMGCNT_MTX_YG_ADJ0) ........................................................................ 1940 32.2.11 Image Quality Adjustment Block Matrix YG Adjustment Register 1 (IMGCNT_MTX_YG_ADJ1) ........................................................................ 1941 32.2.12 Image Quality Adjustment Block Matrix CBB Adjustment Register 0 (IMGCNT_MTX_CBB_ADJ0) ...................................................................... 1942 32.2.13 Image Quality Adjustment Block Matrix CBB Adjustment Register 1 (IMGCNT_MTX_CBB_ADJ1) ...................................................................... 1943 32.2.14 Image Quality Adjustment Block Matrix CRR Adjustment Register 0 (IMGCNT_MTX_CRR_ADJ0) ...................................................................... 1944 32.2.15 Image Quality Adjustment Block Matrix CRR Adjustment Register 1 (IMGCNT_MTX_CRR_ADJ1) ...................................................................... 1945 Usage Methods ............................................................................................................... 1946 Input Format Adjustment Method .................................................................. 1946 32.3.1 Usage Method of Conversion Color Matrix ................................................... 1950 32.3.2 Page xc of cvi Section 33 Video Display Controller 4 (3): Scaler .........................................1951 33.1 33.2 Scaler .............................................................................................................................. 1951 33.1.1 Overview of Functions.................................................................................... 1951 33.1.2 Register Control .............................................................................................. 1952 33.1.3 Synchronization Control ................................................................................. 1954 33.1.4 Setting Angle of View .................................................................................... 1961 33.1.5 Scaling Settings............................................................................................... 1965 33.1.6 Horizontal Prefilter ......................................................................................... 1968 33.1.7 Horizontal Scale-Down ................................................................................... 1968 33.1.8 Vertical Scale-Down ....................................................................................... 1970 33.1.9 Horizontal Scale Up ........................................................................................ 1973 33.1.10 Vertical Scale-Up ............................................................................................ 1975 33.1.11 IP Conversion ................................................................................................. 1977 33.1.12 Trimming ........................................................................................................ 1982 33.1.13 Screen Synthesis ............................................................................................. 1983 33.1.14 Selecting Format for Writing Video Image Signals to Frame Buffer ............. 1985 33.1.15 Horizontal Mirroring and Rotation ................................................................. 1986 33.1.16 Writing to Frame Buffer ................................................................................. 1987 33.1.17 Selecting a Scaling-up Process or Graphics 1 Process .................................... 1993 33.1.18 Reading from Frame Buffer ............................................................................ 1995 Register Descriptions ...................................................................................................... 1996 33.2.1 SCL0 Register Update Control Register (SCL0_UPDATE) .......................... 1999 33.2.2 Mask Control Register (SCL0_FRC1) ............................................................ 2001 33.2.3 Missing Vsync Compensation Control Register (SCL0_FRC2) ..................... 2002 33.2.4 Output Sync Select Register (SCL0_FRC3) ................................................... 2003 33.2.5 Free-Running Period Control Register (SCL0_FRC4) ................................... 2004 33.2.6 Output Delay Control Register (SCL0_FRC5) ............................................... 2005 33.2.7 Full-Screen Vertical Size Register (SCL0_FRC6).......................................... 2006 33.2.8 Full-Screen Horizontal Size Register (SCL0_FRC7) ..................................... 2007 33.2.9 Field Determination Signal Switching Register (SCL0_FRC8) (R version only) ...................................................................... 2008 33.2.10 Vsync Detection Register (SCL0_FRC9) ....................................................... 2009 33.2.11 Scaling-Down Control Register (SCL0_DS1) ................................................ 2010 33.2.12 Vertical Capture Size Register (SCL0_DS2) .................................................. 2011 33.2.13 Horizontal Capture Size Register (SCL0_DS3) .............................................. 2012 33.2.14 Horizontal Scale Down Register (SCL0_DS4) ............................................... 2013 33.2.15 Initial Vertical Phase Register (SCL0_DS5)................................................... 2014 33.2.16 Vertical Scaling Register (SCL0_DS6) .......................................................... 2015 33.2.17 Scaling-Down Control Block Output Size Register (SCL0_DS7) .................. 2016 33.2.18 Scaling-Up Control Register (SCL0_US1) ..................................................... 2017 Page xci of cvi 33.3 33.2.19 Output Image Vertical Size Register (SCL0_US2) ........................................ 2018 33.2.20 Output Image Horizontal Size Register (SCL0_US3) .................................... 2019 33.2.21 Scaling-Up Control Block Input Size Register (SCL0_US4) ......................... 2020 33.2.22 Horizontal Scale Up Register (L0_US5) ........................................................ 2021 33.2.23 Horizontal Scale Up Initial Phase Register (SCL0_US6) ............................... 2022 33.2.24 Trimming Register (SCL0_US7) .................................................................... 2023 33.2.25 Frame Buffer Read Select Register (SCL0_US8) ........................................... 2024 33.2.26 Background Color Register (SCL0_OVR1) ................................................... 2025 33.2.27 SCL1 Register Update Control Register (SCL1_UPDATE) .......................... 2026 33.2.28 Writing Mode Register (SCL1_WR1) ............................................................ 2027 33.2.29 Write Address Register 1 (SCL1_WR2) ......................................................... 2029 33.2.30 Write Address Register 2 (SCL1_WR3) ......................................................... 2030 33.2.31 Write Address Register 3 (SCL1_WR4) ......................................................... 2032 33.2.32 Frame Sub-Sampling Register (SCL1_WR5) ................................................. 2033 33.2.33 Bit Reduction Register (SCL1_WR6)............................................................. 2035 33.2.34 Write Detection Register (SCL1_WR7) ......................................................... 2036 33.2.35 Graphics 1 Register Update Control Register (GR1_UPDATE) .................... 2037 33.2.36 Frame Buffer Read Control Register (Graphics 1) (GR1_FLM_RD) ............ 2038 33.2.37 Frame Buffer Control Register 1 (Graphics 1) (GR1_FLM1) ........................ 2039 33.2.38 Frame Buffer Control Register 2 (Graphics 1) (GR1_FLM2) ........................ 2041 33.2.39 Frame Buffer Control Register 3 (Graphics 1) (GR1_FLM3) ........................ 2042 33.2.40 Frame Buffer Control Register 4 (Graphics 1) (GR1_FLM4) ........................ 2043 33.2.41 Frame Buffer Control Register 5 (Graphics 1) (GR1_FLM5) ........................ 2044 33.2.42 Frame Buffer Control Register 6 (Graphics 1) (GR1_FLM6) ........................ 2045 33.2.43 Alpha Blending Control Register 1 (Graphics 1) (GR1_AB1) ....................... 2047 33.2.44 Alpha Blending Control Register 2 (Graphics 1) (GR1_AB2) ....................... 2049 33.2.45 Alpha Blending Control Register 3 (Graphics 1) (GR1_AB3) ....................... 2050 33.2.46 Alpha Blending Control Register 7 (Graphics 1) (GR1_AB7) ....................... 2051 33.2.47 Alpha Blending Control Register 8 (Graphics 1) (GR1_AB8) ....................... 2052 33.2.48 Alpha Blending Control Register 9 (Graphics 1) (GR1_AB9) ....................... 2053 33.2.49 Alpha Blending Control Register 10 (Graphics 1) (GR1_AB10) ................... 2054 33.2.50 Alpha Blending Control Register 11 (Graphics 1) (GR1_AB11) ................... 2055 33.2.51 Background Color Control Register (Graphics 1) (GR1_BASE) ................... 2056 33.2.52 CLUT Table Control Register (Graphics 1) (GR1_CLUT) ............................ 2057 Usage Method ................................................................................................................. 2058 33.3.1 Scaling Setting Example for 525i Video Input and VGA-Size (640 x 480) Video Output ............................................................. 2058 33.3.2 Scaling Setting Example for Graphics Display ............................................... 2063 33.3.3 Scaling Setting Example for Scaled-up Graphics Display .............................. 2066 Page xcii of cvi Section 34 Video Display Controller 4 (4): Image Quality Improver ............2071 34.1 34.2 34.3 Image Quality Improver .................................................................................................. 2071 34.1.1 Overview of Functions.................................................................................... 2071 34.1.2 Register Update Control ................................................................................. 2071 34.1.3 Black Stretch ................................................................................................... 2072 34.1.4 Enhancer ......................................................................................................... 2074 34.1.5 Color Matrix ................................................................................................... 2082 Register Description ....................................................................................................... 2086 34.2.1 Register Update Control Register in Image Quality Improver (ADJ_UPDATE) ............................................................................................. 2088 34.2.2 Black Stretch Register (ADJ_BKSTR_SET) .................................................. 2089 34.2.3 Enhancer Timing Adjustment Register 1 (ADJ_ENH_TIM1)........................ 2090 34.2.4 Enhancer Timing Adjustment Register 2 (ADJ_ENH_TIM2)........................ 2091 34.2.5 Enhancer Timing Adjustment Register 3 (ADJ_ENH_TIM3)........................ 2092 34.2.6 Enhancer Sharpness Register 1 (ADJ_ENH_SHP1) ....................................... 2093 34.2.7 Enhancer Sharpness Register 2 (ADJ_ENH_SHP2) ....................................... 2094 34.2.8 Enhancer Sharpness Register 3 (ADJ_ENH_SHP3) ....................................... 2095 34.2.9 Enhancer Sharpness Register 4 (ADJ_ENH_SHP4) ....................................... 2096 34.2.10 Enhancer Sharpness Register 5 (ADJ_ENH_SHP5) ....................................... 2097 34.2.11 Enhancer Sharpness Register 6 (ADJ_ENH_SHP6) ....................................... 2098 34.2.12 Enhancer LTI Register 1 (ADJ_ENH_LTI1) .................................................. 2099 34.2.13 Enhancer LTI Register 2 (ADJ_ENH_LTI2) .................................................. 2100 34.2.14 Matrix Mode Register in Image Quality Improver (ADJ_MTX_MODE) ...... 2101 34.2.15 Matrix YG Control Register 0 in Image Quality Improver (ADJ_MTX_YG_ADJ0)................................................................................. 2102 34.2.16 Matrix YG Control Register 1 in Image Quality Improver (ADJ_MTX_YG_ADJ1)................................................................................. 2103 34.2.17 Matrix CBB Control Register 0 in Image Quality Improver (ADJ_MTX_CBB_ADJ0) .............................................................................. 2104 34.2.18 Matrix CBB Control Register 1 in Image Quality Improver (ADJ_MTX_CBB_ADJ1) .............................................................................. 2105 34.2.19 Matrix CRR Control Register 0 in Image Quality Improver (ADJ_MTX_CRR_ADJ0) .............................................................................. 2106 34.2.20 Matrix CRR Control Register 1 in Image Quality Improver (ADJ_MTX_CRR_ADJ1) .............................................................................. 2107 Usage Method ................................................................................................................. 2108 34.3.1 Black Stretch Usage Method .......................................................................... 2108 34.3.2 LTI Processing of Enhancer............................................................................ 2109 34.3.3 Sharpness Processing of Enhancer .................................................................. 2110 34.3.4 Setting Method for Color Matrix Data Conversion ........................................ 2111 Page xciii of cvi Section 35 Video Display Controller 4 (5): Image Synthesizer ...................... 2113 35.1 35.2 Image Synthesizer ........................................................................................................... 2113 35.1.1 Overview of Functions.................................................................................... 2113 35.1.2 Graphics Data Read Control ........................................................................... 2115 35.1.3 Setting Graphics Display Area........................................................................ 2129 35.1.4 Interrupt Generation at Specified Line............................................................ 2131 35.1.5 Formats of Frame Buffer Read Signals and Corresponding Alpha Blending Types............................................................ 2131 35.1.6 Display Selection ............................................................................................ 2133 35.1.7 Background Color Display Processing ........................................................... 2135 35.1.8 Lower-Layer Graphics Display Processing .................................................... 2135 35.1.9 Current Graphics Display Processing ............................................................. 2135 35.1.10 Display with Alpha Blending in a Rectangular Area ...................................... 2136 35.1.11 RGB-Index Chroma-Key Processing .............................................................. 2139 35.1.12 CLUT-Index Chroma-Key Processing............................................................ 2141 35.1.13 Display with Alpha Blending in One-Pixel Units ........................................... 2143 35.1.14 Alpha Blending Calculation............................................................................ 2143 35.1.15 CLUT Table .................................................................................................... 2143 Register Descriptions ...................................................................................................... 2145 35.2.1 Graphics 2 Register Update Control Register (GR2_UPDATE) .................... 2149 35.2.2 Frame Buffer Read Control Register (Graphics 2) (GR2_FLM_RD) ............ 2150 35.2.3 Frame Buffer Control Register 1 (Graphics 2) (GR2_FLM1) ........................ 2151 35.2.4 Frame Buffer Control Register 2 (Graphics 2) (GR2_FLM2) ........................ 2152 35.2.5 Frame Buffer Control Register 3 (Graphics 2) (GR2_FLM3) ........................ 2153 35.2.6 Frame Buffer Control Register 4 (Graphics 2) (GR2_FLM4) ........................ 2154 35.2.7 Frame Buffer Control Register 5 (Graphics 2) (GR2_FLM5) ........................ 2155 35.2.8 Frame Buffer Control Register 6 (Graphics 2) (GR2_FLM6) ........................ 2156 35.2.9 Alpha Blending Control Register 1 (Graphics 2) (GR2_AB1) ....................... 2158 35.2.10 Alpha Blending Control Register 2 (Graphics 2) (GR2_AB2) ....................... 2159 35.2.11 Alpha Blending Control Register 3 (Graphics 2) (GR2_AB3) ....................... 2160 35.2.12 Alpha Blending Control Register 4 (Graphics 2) (GR2_AB4) ....................... 2161 35.2.13 Alpha Blending Control Register 5 (Graphics 2) (GR2_AB5) ....................... 2162 35.2.14 Alpha Blending Control Register 6 (Graphics 2) (GR2_AB6) ....................... 2163 35.2.15 Alpha Blending Control Register 7 (Graphics 2) (GR2_AB7) ....................... 2164 35.2.16 Alpha Blending Control Register 8 (Graphics 2) (GR2_AB8) ....................... 2165 35.2.17 Alpha Blending Control Register 9 (Graphics 2) (GR2_AB9) ....................... 2166 35.2.18 Alpha Blending Control Register 10 (Graphics 2) (GR2_AB10) ................... 2167 35.2.19 Alpha Blending Control Register 11 (Graphics 2) (GR2_AB11) ................... 2168 35.2.20 Background Color Control Register (Graphics 2) (GR2_BASE) ................... 2169 35.2.21 CLUT Table Control Register (Graphics 2) (GR2_CLUT) ............................ 2170 Page xciv of cvi 35.2.22 35.2.23 35.2.24 35.2.25 35.2.26 35.2.27 35.2.28 35.2.29 35.2.30 35.2.31 35.2.32 35.2.33 35.2.34 35.2.35 35.2.36 35.2.37 35.2.38 35.2.39 35.2.40 35.2.41 35.2.42 35.2.43 35.3 Status Monitor Register (Graphics 2) (GR2_MON) ....................................... 2171 Graphics 3 Register Update Control Register (GR3_UPDATE) .................... 2172 Frame Buffer Read Control Register (Graphics 3) (GR3_FLM_RD)............. 2173 Frame Buffer Control Register 1 (Graphics 3) (GR3_FLM1) ........................ 2174 Frame Buffer Control Register 2 (Graphics 3) (GR3_FLM2) ........................ 2175 Frame Buffer Control Register 3 (Graphics 3) (GR3_FLM3) ........................ 2176 Frame Buffer Control Register 4 (Graphics 3) (GR3_FLM4) ........................ 2177 Frame Buffer Control Register 5 (Graphics 3) (GR3_FLM5) ........................ 2178 Frame Buffer Control Register 6 (Graphics 3) (GR3_FLM6) ........................ 2178 Alpha Blending Control Register 1 (Graphics 3) (GR3_AB1) ....................... 2180 Alpha Blending Control Register 2 (Graphics 3) (GR3_AB2) ....................... 2182 Alpha Blending Control Register 3 (Graphics 3) (GR3_AB3) ....................... 2183 Alpha Blending Control Register 4 (Graphics 3) (GR3_AB4) ....................... 2184 Alpha Blending Control Register 5 (Graphics 3) (GR3_AB5) ....................... 2185 Alpha Blending Control Register 6 (Graphics 3) (GR3_AB6) ....................... 2186 Alpha Blending Control Register 7 (Graphics 3) (GR3_AB7) ....................... 2187 Alpha Blending Control Register 8 (Graphics 3) (GR3_AB8) ....................... 2188 Alpha Blending Control Register 9 (Graphics 3) (GR3_AB9) ....................... 2189 Alpha Blending Control Register 10 (Graphics 3) (GR3_AB10) ................... 2190 Alpha Blending Control Register 11 (Graphics 3) (GR3_AB11) ................... 2191 Background Color Control Register (Graphics 3) (GR3_BASE) ................... 2192 CLUT Table and Interrupt Control Register (Graphics 3) (GR3_CLUT_INT) .................................................................... 2193 35.2.44 Status Monitor Register (Graphics 3) (GR3_MON) ....................................... 2194 Usage Method ................................................................................................................. 2195 35.3.1 Mute Image ..................................................................................................... 2195 35.3.2 Alpha Blending in Rectangular Area .............................................................. 2195 Section 36 Video Display Controller 4 (6): Output Controller.......................2197 36.1 36.2 Output Controller ............................................................................................................ 2197 36.1.1 Overview of Functions.................................................................................... 2197 36.1.2 Register Update Control ................................................................................. 2198 36.1.3 Route Selection ............................................................................................... 2199 36.1.4 Panel Brightness Adjustment .......................................................................... 2199 36.1.5 Contrast Adjustment ....................................................................................... 2200 36.1.6 Gamma Correction .......................................................................................... 2201 36.1.7 Dither Process ................................................................................................. 2207 36.1.8 Output Format Conversion ............................................................................. 2210 36.1.9 LCD TCON .................................................................................................... 2218 Register Descriptions ...................................................................................................... 2234 Page xcv of cvi 36.2.1 36.2.2 36.2.3 36.2.4 36.2.5 36.2.6 36.2.7 36.2.8 36.2.9 36.2.10 36.2.11 36.2.12 36.2.13 36.2.14 36.2.15 36.2.16 36.2.17 36.2.18 36.2.19 36.2.20 36.2.21 36.2.22 36.2.23 36.2.24 36.2.25 36.2.26 36.2.27 36.2.28 36.2.29 36.2.30 36.2.31 36.2.32 36.2.33 36.2.34 Page xcvi of cvi Register Update Control Register G in Gamma Correction Block (GAM_G_UPDATE) ...................................................................................... 2241 Function Switch Register in Gamma Correction Block (GAM_SW) ............. 2242 Table Setting Register G1 to G16 in Gamma Correction Block (GAM_G_LUT1 to GAM_G_LUT16) ........................................................... 2243 Area Setting Register G1 in Gamma Correction Block (GAM_G_AREA1).. 2246 Area Setting Register G2 in Gamma Correction Block (GAM_G_AREA2).. 2247 Area Setting Register G3 in Gamma Correction Block (GAM_G_AREA3).. 2248 Area Setting Register G4 in Gamma Correction Block (GAM_G_AREA4).. 2249 Area Setting Register G5 in Gamma Correction Block (GAM_G_AREA5).. 2250 Area Setting Register G6 in Gamma Correction Block (GAM_G_AREA6).. 2251 Area Setting Register G7 in Gamma Correction Block (GAM_G_AREA7).. 2252 Area Setting Register G8 in Gamma Correction Block (GAM_G_AREA8).. 2253 Register Update Control Register B in Gamma Correction Block (GAM_B_UPDATE) ...................................................................................... 2254 Table Setting Register B1 to B16 in Gamma Correction Block (GAM_B_LUT1 to GAM_B_LUT16) ........................................................... 2255 Area Setting Register B1 in Gamma Correction Block (GAM_B_AREA1) .. 2258 Area Setting Register B2 in Gamma Correction Block (GAM_B_AREA2) .. 2259 Area Setting Register B3 in Gamma Correction Block (GAM_B_AREA3) .. 2260 Area Setting Register B4 in Gamma Correction Block (GAM_B_AREA4) .. 2261 Area Setting Register B5 in Gamma Correction Block (GAM_B_AREA5) .. 2262 Area Setting Register B6 in Gamma Correction Block (GAM_B_AREA6) .. 2263 Area Setting Register B7 in Gamma Correction Block (GAM_B_AREA7) .. 2264 Area Setting Register B8 in Gamma Correction Block (GAM_B_AREA8) .. 2265 Register Update Control Register R in Gamma Correction Block (GAM_R_UPDATE) ...................................................................................... 2266 Table Setting Register R1 to R16 in Gamma Correction Block (GAM_R_LUT1 to GAM_R_LUT16) ........................................................... 2267 Area Setting Register R1 in Gamma Correction Block (GAM_R_AREA1) .. 2270 Area Setting Register R2 in Gamma Correction Block (GAM_R_AREA2) .. 2271 Area Setting Register R3 in Gamma Correction Block (GAM_R_AREA3) .. 2272 Area Setting Register R4 in Gamma Correction Block (GAM_R_AREA4) .. 2273 Area Setting Register R5 in Gamma Correction Block (GAM_R_AREA5) .. 2274 Area Setting Register R6 in Gamma Correction Block (GAM_R_AREA6) .. 2275 Area Setting Register R7 in Gamma Correction Block (GAM_R_AREA7) .. 2276 Area Setting Register R8 in Gamma Correction Block (GAM_R_AREA8) .. 2277 TCON Register Update Control Register (TCON_UPDATE) ....................... 2278 TCON Reference Timing Setting Register (TCON_TIM) ............................. 2279 TCON Vertical Timing Setting Register A1 (TCON_TIM_STVA1)............. 2280 36.3 36.2.35 TCON Vertical Timing Setting Register A2 (TCON_TIM_STVA2) ............. 2281 36.2.36 TCON Vertical Timing Setting Register B1 (TCON_TIM_STVB1) ............. 2282 36.2.37 TCON Vertical Timing Setting Register B2 (TCON_TIM_STVB2) ............. 2283 36.2.38 TCON Horizontal Timing Setting Register STH1 (TCON_TIM_STH1) ....... 2284 36.2.39 TCON Horizontal Timing Setting Register STH2 (TCON_TIM_STH2) ....... 2285 36.2.40 TCON Horizontal Timing Setting Register STB1 (TCON_TIM_STB1) ....... 2286 36.2.41 TCON Horizontal Timing Setting Register STB2 (TCON_TIM_STB2) ....... 2287 36.2.42 TCON Horizontal Timing Setting Register CPV1 (TCON_TIM_CPV1) ...... 2288 36.2.43 TCON Horizontal Timing Setting Register CPV2 (TCON_TIM_CPV2) ...... 2289 36.2.44 TCON Horizontal Timing Setting Register POLA1 (TCON_TIM_POLA1) . 2290 36.2.45 TCON Horizontal Timing Setting Register POLA2 (TCON_TIM_POLA2) . 2291 36.2.46 TCON Horizontal Timing Setting Register POLB1 (TCON_TIM_POLB1) . 2293 36.2.47 TCON Horizontal Timing Setting Register POLB2 (TCON_TIM_POLB2) . 2294 36.2.48 TCON Data Enable Polarity Setting Register (TCON_TIM_DE) .................. 2296 36.2.49 Register Update Control Register in Output Controller (OUT_UPDATE) .... 2297 36.2.50 Output Interface Register (OUT_SET) ........................................................... 2298 36.2.51 Brightness (DC) Correction Register 1 (OUT_BRIGHT1) ............................ 2300 36.2.52 Brightness (DC) Correction Register 2 (OUT_BRIGHT2) ............................ 2301 36.2.53 Contrast (Gain) Correction Register (OUT_CONTRAST)............................. 2302 36.2.54 Panel Dither Register (OUT_PDTHA) ........................................................... 2303 36.2.55 Output Phase Control Register (OUT_CLK_PHASE) ................................... 2305 Usage Methods ............................................................................................................... 2307 36.3.1 Gamma Correction Adjustment Method ......................................................... 2307 36.3.2 Dither Usage Method ...................................................................................... 2307 36.3.3 Output Format Adjustment Method ................................................................ 2308 Section 37 Video Display Controller 4 (7): System Controller .......................2311 37.1 37.2 System Controller ........................................................................................................... 2311 37.1.1 Overview of Functions.................................................................................... 2311 37.1.2 Interrupt Control ............................................................................................. 2311 37.1.3 Panel Clock Control ........................................................................................ 2315 37.1.4 CLUT Table Read Select Signal Status Flag .................................................. 2318 Register Descriptions ...................................................................................................... 2319 37.2.1 Interrupt Control Register 1 (SYSCNT_INT1)............................................... 2320 37.2.2 Interrupt Control Register 2 (SYSCNT_INT2)............................................... 2321 37.2.3 Interrupt Control Register 3 (SYSCNT_INT3)............................................... 2324 37.2.4 Interrupt Control Register 4 (SYSCNT_INT4)............................................... 2325 37.2.5 Panel Clock Control Register (SYSCNT_PANEL_CLK) .............................. 2327 37.2.6 CLUT Table Read Select Signal Status Register (SYSCNT_CLUT) ............. 2328 Page xcvii of cvi Section 38 Image Renderer (IMR-LS) ............................................................ 2329 Section 39 Display Out Comparison Unit ....................................................... 2331 39.1 39.2 39.3 39.4 39.5 39.6 Features ........................................................................................................................... 2331 Block Diagram ................................................................................................................ 2332 Register Descriptions ...................................................................................................... 2333 39.3.1 Control Register (DOCMCR) ......................................................................... 2334 39.3.2 Status Register (DOCMSTR) ......................................................................... 2335 39.3.3 Status Clear Register (DOCMCLSTR) ........................................................... 2336 39.3.4 Interrupt Enable Register (DOCMIENR) ....................................................... 2337 39.3.5 Operation Parameter Setting Register (DOCMPMR) ..................................... 2338 39.3.6 Expected CRC Code Register (DOCMECRCR) ............................................ 2340 39.3.7 Calculated CRC Code Value Register (DOCMCCRCR) ............................... 2340 39.3.8 Horizontal Start Position Setting Register (DOCMSPXR) ............................. 2341 39.3.9 Vertical Start Position Setting Register (DOCMSPYR) ................................. 2342 39.3.10 Horizontal Size Setting Register (DOCMSZXR) ........................................... 2343 39.3.11 Vertical Size Setting Register (DOCMSZYR) ............................................... 2344 39.3.12 CRC Code Initialization Register (DOCMCRCIR) ........................................ 2345 Operation ........................................................................................................................ 2346 39.4.1 Overview of Operations .................................................................................. 2346 39.4.2 System Configuration ..................................................................................... 2346 39.4.3 CRC Calculation Method................................................................................ 2347 39.4.4 Graphics Data Selection for CRC Code Generation ....................................... 2347 39.4.5 Pixel Format.................................................................................................... 2348 39.4.6 Rectangular Area Settings .............................................................................. 2349 39.4.7 CRC Calculation Time Period and Comparison Timing ................................ 2351 39.4.8 Register Update Timing .................................................................................. 2352 39.4.9 Operation Flow ............................................................................................... 2353 Interrupt .......................................................................................................................... 2355 Usage Note ..................................................................................................................... 2355 39.6.1 Expected CRC Value ...................................................................................... 2355 39.6.2 Expansion Control Functionality .................................................................... 2355 Section 40 OpenVG-Compliant Renesas Graphics Processor ..................... 2357 40.1 40.2 Specification ................................................................................................................... 2357 Usage Note ..................................................................................................................... 2357 Section 41 JPEG Codec Unit........................................................................... 2359 41.1 41.2 Features ........................................................................................................................... 2359 Register Descriptions ...................................................................................................... 2361 Page xcviii of cvi 41.2.1 41.2.2 41.2.3 41.2.4 41.2.5 41.2.6 41.2.7 41.2.8 41.2.9 41.2.10 41.2.11 41.2.12 41.2.13 41.2.14 41.2.15 41.2.16 41.2.17 41.2.18 41.2.19 41.2.20 41.2.21 41.2.22 41.2.23 41.2.24 41.2.25 41.2.26 41.2.27 41.2.28 41.3 41.4 JPEG Code Mode Register (JCMOD) ............................................................ 2363 JPEG Code Command Register (JCCMD) ..................................................... 2364 JPEG Code Quantization Table Number Register (JCQTN) .......................... 2366 JPEG Code Huffman Table Number Register (JCHTN) ................................ 2367 JPEG Code DRI Upper Register (JCDRIU) ................................................... 2368 JPEG Code DRI Lower Register (JCDRID) ................................................... 2369 JPEG Code Vertical Size Upper Register (JCVSZU) ..................................... 2370 JPEG Code Vertical Size Lower Register (JCVSZD) .................................... 2371 JPEG Code Horizontal Size Upper Register (JCHSZU) ................................. 2372 JPEG Coded Horizontal Size Lower Register (JCHSZD) .............................. 2373 JPEG Code Data Count Upper Register (JCDTCU) ....................................... 2374 JPEG Code Data Count Middle Register (JCDTCM) ..................................... 2375 JPEG Code Data Count Lower Register (JCDTCD) ...................................... 2376 JPEG Interrupt Enable Register 0 (JINTE0) ................................................... 2377 JPEG Interrupt Status Register 0 (JINTS0) .................................................... 2379 JPEG Code Decode Error Register (JCDERR) ............................................... 2380 JPEG Code Reset Register (JCRST) ............................................................... 2381 JPEG Interface Compression Control Register (JIFECNT) ............................ 2382 JPEG Interface Compression Source Address Register (JIFESA) .................. 2385 JPEG Interface Compression Line Offset Register (JIFESOFST) .................. 2386 JPEG Interface Compression Destination Address Register (JIFEDA) .......... 2387 JPEG Interface Compression Source Line Count Register (JIFESLC)........... 2388 JPEG Interface Decompression Control Register (JIFDCNT)........................ 2389 JPEG Interface Decompression Source Address Register (JIFDSA).............. 2394 JPEG Interface Decompression Line Offset Register (JIFDDOFST) ............. 2395 JPEG Interface Decompression Destination Address Register (JIFDDA)...... 2396 JPEG Interface Decompression Source Data Count Register (JIFDSDC) ...... 2397 JPEG Interface Decompression Destination Line Count Register (JIFDDLC) ............................................................................. 2398 41.2.29 JPEG Interface Decompression  Set Register (JIFDADT) ........................... 2399 41.2.30 JPEG Interrupt Enable Register 1 (JINTE1) ................................................... 2400 41.2.31 JPEG Interrupt Status Register 1 (JINTS1) .................................................... 2402 Operation ........................................................................................................................ 2404 41.3.1 Compression ................................................................................................... 2404 41.3.2 Decompression................................................................................................ 2414 41.3.3 Output Pixel Format in Decompression .......................................................... 2423 41.3.4 Storing Image Data ......................................................................................... 2428 Interrupts ......................................................................................................................... 2429 41.4.1 Compression/Decompression Process Interrupt Request (JEDI) .................... 2429 41.4.2 Data Transfer Interrupt Request (JDTI) .......................................................... 2430 Page xcix of cvi 41.5 41.6 Bus Reset Processing ...................................................................................................... 2432 Usage Notes .................................................................................................................... 2433 41.6.1 Pixel Format YCbCr ....................................................................................... 2433 Section 42 Sampling Rate Converter .............................................................. 2435 42.1 42.2 42.3 42.4 42.5 Features ........................................................................................................................... 2435 Register Descriptions ...................................................................................................... 2437 42.2.1 Input Data Register (SRCID) .......................................................................... 2438 42.2.2 Output Data Register (SRCOD)...................................................................... 2439 42.2.3 Input Data Control Register (SRCIDCTRL) .................................................. 2440 42.2.4 Output Data Control Register (SRCODCTRL) .............................................. 2442 42.2.5 Control Register (SRCCTRL)......................................................................... 2444 42.2.6 Status Register (SRCSTAT) ........................................................................... 2450 Operation ........................................................................................................................ 2455 42.3.1 Initial Setting .................................................................................................. 2455 42.3.2 Data Input ....................................................................................................... 2456 42.3.3 Data Output..................................................................................................... 2458 Interrupts ......................................................................................................................... 2460 Usage Notes .................................................................................................................... 2461 42.5.1 Notes on Accessing Registers ......................................................................... 2461 42.5.2 Notes on Flush Processing .............................................................................. 2461 Section 43 Sound Generator ............................................................................ 2463 43.1 43.2 43.3 43.4 43.5 43.6 Features ........................................................................................................................... 2463 Input/Output Pins ............................................................................................................ 2464 Register Descriptions ...................................................................................................... 2464 43.3.1 Sound Generator Control Register 1 (SGCR1) ............................................... 2467 43.3.2 Sound Generator Control Status Register (SGCSR) ....................................... 2469 43.3.3 Sound Generator Control Register 2 (SGCR2) ............................................... 2470 43.3.4 Sound Generator Loudness Register (SGLR) ................................................. 2471 43.3.5 Sound Generator Tone Frequency Register (SGTFR) .................................... 2471 43.3.6 Sound Generator Reference Frequency Register (SGSFR) ............................ 2472 Operation ........................................................................................................................ 2473 43.4.1 Base Operation................................................................................................ 2473 43.4.2 Tone Frequency Setting .................................................................................. 2477 43.4.3 Auto Attenuator Function ............................................................................... 2478 43.4.4 Output Waveform ........................................................................................... 2479 Interrupt Source .............................................................................................................. 2479 Usage Note ..................................................................................................................... 2480 43.6.1 Module Stop Mode Settings ........................................................................... 2480 Page c of cvi Section 44 SD Host Interface...........................................................................2481 Section 45 MMC Host Interface ......................................................................2483 45.1 45.2 45.3 45.4 45.5 45.6 45.7 Features ........................................................................................................................... 2483 Input/Output Pins ............................................................................................................ 2484 Register Descriptions ...................................................................................................... 2485 45.3.1 Command Setting Register (CE_CMD_SET) ................................................ 2486 45.3.2 Argument Register (CE_ARG) ....................................................................... 2490 45.3.3 Argument Register for Automatically-Issued CMD12 (CE_ARG_CMD12) . 2490 45.3.4 Command Control Register (CE_CMD_CTRL)............................................. 2491 45.3.5 Transfer Block Setting Register (CE_BLOCK_SET) ..................................... 2492 45.3.6 Clock Control Register (CE_CLK_CTRL) ..................................................... 2493 45.3.7 Buffer Access Configuration Register (CE_BUF_ACC)................................ 2495 45.3.8 Response Registers 3 to 0 (CE_RESP3 to CE_RESP0) ................................. 2496 45.3.9 Response Register for Automatically-Issued CMD12 (CE_RESP_CMD12) . 2498 45.3.10 Data Register (CE_DATA) ............................................................................. 2498 45.3.11 Interrupt Flag Register (CE_INT) ................................................................... 2499 45.3.12 Interrupt Enable Register (CE_INT_EN)........................................................ 2506 45.3.13 Status Register 1 (CE_HOST _STS1) ............................................................ 2509 45.3.14 Status Register 2 (CE_HOST _STS2) ............................................................ 2510 45.3.15 DMA Mode Setting Register (CE_DMA_MODE) ......................................... 2513 45.3.16 Card Detection/Port Control Register (CE_DETECT) ................................... 2514 45.3.17 Special Mode Setting Register (CE_ADD_MODE) ....................................... 2516 45.3.18 Version Register (CE_VERSION).................................................................. 2517 Interrupt Requests ........................................................................................................... 2518 DMA Specifications ....................................................................................................... 2519 45.5.1 DMA for Buffer Writing ................................................................................. 2519 45.5.2 DMA for Buffer Reading ................................................................................ 2519 Operation ........................................................................................................................ 2520 45.6.1 Command/Response Formats ......................................................................... 2520 45.6.2 Data Block Format .......................................................................................... 2521 45.6.3 Buffer Structure and Buffer Accesses ............................................................. 2522 45.6.4 Automatic CMD12 Issuance ........................................................................... 2524 45.6.5 Operation in the Case of Error/Timeout.......................................................... 2525 Examples of Setting ........................................................................................................ 2526 45.7.1 Legends ........................................................................................................... 2526 45.7.2 Command Transmission ................................................................................. 2527 45.7.3 Command Transmission  Response Reception ........................................... 2528 45.7.4 Command Transmission  Response Reception (with Response Busy) ....... 2529 45.7.5 Single-Block Read .......................................................................................... 2531 Page ci of cvi 45.8 45.7.6 Multi-Block Read ........................................................................................... 2532 45.7.7 Multi-Block Read (with Automatic CMD12 Issuance) .................................. 2533 45.7.8 Single-Block Write ......................................................................................... 2534 45.7.9 Multi-Block Write .......................................................................................... 2535 45.7.10 Multi-Block Write (with Automatic CMD12 Issuance) ................................. 2536 45.7.11 Forcible Termination ...................................................................................... 2537 45.7.12 Setting Values of CE_CMD_SET .................................................................. 2538 Usage Note ..................................................................................................................... 2540 45.8.1 Card Detection ................................................................................................ 2540 Section 46 Motor Control PWM Timer........................................................... 2541 46.1 46.2 46.3 46.4 46.5 46.6 Features ........................................................................................................................... 2541 Input/Output Pins ............................................................................................................ 2543 Register Descriptions ...................................................................................................... 2544 46.3.1 PWM Control Register_n (PWCR_n) (n = 1, 2) ............................................. 2545 46.3.2 PWM Polarity Register_n (PWPR_n) (n = 1, 2) ............................................. 2547 46.3.3 PWM Counter_n (PWCNT_n) (n = 1, 2)........................................................ 2547 46.3.4 PWM Cycle Register_n (PWCYR_n) (n = 1, 2) ............................................. 2548 46.3.5 PWM Duty Registers_nA, nC, nE, nG (PWDTR_nA, PWDTR_nC, PWDTR_nE, PWDTR_nG) (n = 1, 2) ............................................................ 2549 46.3.6 PWM Buffer Registers_nA, nC, nE, nG (PWBFR_nA, PWBFR_nC, PWBFR_nE, PWBFR_nG) (n = 1, 2) ............................................................. 2552 46.3.7 PWM Buffer Transfer Control Register (PWBTCR)...................................... 2553 Bus Master Interface ....................................................................................................... 2554 46.4.1 16-Bit Data Registers ...................................................................................... 2554 46.4.2 8-Bit Data Registers ........................................................................................ 2554 Operation ........................................................................................................................ 2555 46.5.1 PWM Operation .............................................................................................. 2555 46.5.2 Buffer Transfer Control .................................................................................. 2556 Usage Note ..................................................................................................................... 2557 46.6.1 Conflict between Buffer Register Write and Compare Match ........................ 2557 Section 47 On-Chip RAM ............................................................................... 2559 47.1 47.2 Features ........................................................................................................................... 2559 Usage Notes .................................................................................................................... 2562 47.2.1 Page Conflict .................................................................................................. 2562 47.2.2 RAME and RAMWE Bits .............................................................................. 2562 47.2.3 Data Retention ................................................................................................ 2563 Page cii of cvi Section 48 General Purpose I/O Ports .............................................................2565 48.1 48.2 Features ........................................................................................................................... 2565 Register Descriptions ...................................................................................................... 2575 48.2.1 Port A I/O Register 0 (PAIOR0) ..................................................................... 2578 48.2.2 Port A Data Register 0 (PADR0) .................................................................... 2578 48.2.3 Port A Port Register 0 (PAPR0) ..................................................................... 2579 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5) ...................................... 2580 48.2.5 Port B I/O Registers 0, 1 (PBIOR0, PBIOR1) ................................................ 2592 48.2.6 Port B Data Registers 0, 1 (PBDR0, PBDR1) ................................................ 2593 48.2.7 Port B Port Registers 0, 1 (PBPR0, PBPR1) ................................................... 2595 48.2.8 Port C Control Registers 0 to 2 (PCCR0 to PCCR2) ...................................... 2597 48.2.9 Port C I/O Register 0 (PCIOR0) ..................................................................... 2600 48.2.10 Port C Data Register 0 (PCDR0) .................................................................... 2601 48.2.11 Port C Port Register 0 (PCPR0) ...................................................................... 2602 48.2.12 Port D Control Register 0 to 3 (PDCR0 to PDCR3) ....................................... 2603 48.2.13 Port D I/O Register 0 (PDIOR0) ..................................................................... 2609 48.2.14 Port D Port Register 0 (PDDR0) ..................................................................... 2610 48.2.15 Port D Port Register 0 (PDPR0) ..................................................................... 2612 48.2.16 Port E Control Registers 0, 1 (PECR0, PECR1) ............................................. 2613 48.2.17 Port E I/O Register 0 (PEIOR0)...................................................................... 2615 48.2.18 Port E Data Register 0 (PEDR0) ..................................................................... 2616 48.2.19 Port E Port Register 0 (PEPR0) ...................................................................... 2617 48.2.20 Port F Control Registers 0 to 6 (PFCR0 to PFCR6) ....................................... 2618 48.2.21 Port F I/O Registers 0, 1 (PFIOR0, PFIOR1) ................................................. 2627 48.2.22 Port F Data Registers 0, 1 (PFDR0, PFDR1) .................................................. 2628 48.2.23 Port F Port Registers 0, 1 (PFPR0, PFPR1) .................................................... 2630 48.2.24 Port G Control Registers 0 to 6 (PGCR0 to PGCR6) ..................................... 2632 48.2.25 Port G I/O Registers 0, 1 (PGIOR0, PGIOR1) ............................................... 2644 48.2.26 Port G Data Registers 0, 1 (PGDR0, PGDR1) ................................................ 2645 48.2.27 Port G Port Registers 0, 1 (PGPR0, PGPR1) .................................................. 2647 48.2.28 Port H Control Registers 0, 1 (PHCR0, PHCR1)............................................ 2650 48.2.29 Port H Port Register 0 (PHPR0) ..................................................................... 2652 48.2.30 Port J Control Registers 0 to 7 (PJCR0 to PJCR7: Available Only in the SH7269 Group) ..................................................................................... 2653 48.2.31 Port J I/O registers 0, 1 (PJIOR0, PJIOR1: Available Only in the SH7269 Group) ..................................................................................... 2665 48.2.32 Port J Data Registers 0, 1 (PJDR0, PJDR1: Available Only in the SH7269 Group) ..................................................................................... 2666 Page ciii of cvi 48.2.33 48.2.34 Port J Port Registers 0, 1 (PJPR0, PJPR1: Available Only in the SH7269 Group) ..................................................................................... 2669 Serial Sound Interface Noise Canceler Control Register (SNCR) .................. 2672 Section 49 Power-Down Modes ...................................................................... 2675 49.1 49.2 49.3 49.4 Features ........................................................................................................................... 2675 49.1.1 Power-Down Modes ....................................................................................... 2675 Register Descriptions ...................................................................................................... 2678 49.2.1 Standby Control Register 1 (STBCR1)........................................................... 2679 49.2.2 Standby Control Register 2 (STBCR2)........................................................... 2680 49.2.3 Standby Control Register 3 (STBCR3)........................................................... 2681 49.2.4 Standby Control Register 4 (STBCR4)........................................................... 2683 49.2.5 Standby Control Register 5 (STBCR5)........................................................... 2686 49.2.6 Standby Control Register 6 (STBCR6)........................................................... 2688 49.2.7 Standby Control Register 7 (STBCR7)........................................................... 2690 49.2.8 Standby Control Register 8 (STBCR8)........................................................... 2692 49.2.9 Standby Control Register 9 (STBCR9)........................................................... 2694 49.2.10 Standby Control Register 10 (STBCR10) ....................................................... 2696 49.2.11 Software Reset Control Register 1 (SWRSTCR1).......................................... 2698 49.2.12 Software Reset Control Register 2 (SWRSTCR2).......................................... 2700 49.2.13 System Control Register 1 (SYSCR1) ............................................................ 2701 49.2.14 System Control Register 2 (SYSCR2) ............................................................ 2702 49.2.15 System Control Register 3 (SYSCR3) ............................................................ 2703 49.2.16 System Control Register 4 (SYSCR4) ............................................................ 2705 49.2.17 System Control Register 5 (SYSCR5) ............................................................ 2706 49.2.18 On-Chip Data-Retention RAM Area Setting Register (RRAMKP) ............... 2708 49.2.19 Deep Standby Control Register (DSCTR) ...................................................... 2709 49.2.20 Deep Standby Cancel Source Select Register (DSSSR) ................................. 2711 49.2.21 Deep Standby Cancel Edge Select Register (DSESR) .................................... 2714 49.2.22 Deep Standby Cancel Source Flag Register (DSFR) ...................................... 2716 49.2.23 XTAL Crystal Oscillator Gain Control Register (XTALCTR) ...................... 2719 Operation ........................................................................................................................ 2720 49.3.1 Sleep Mode ..................................................................................................... 2720 49.3.2 Software Standby Mode.................................................................................. 2721 49.3.3 Software Standby Mode Application Example ............................................... 2724 49.3.4 Deep Standby Mode........................................................................................ 2725 49.3.5 Module Standby Function ............................................................................... 2731 49.3.6 Adjustment of XTAL Crystal Oscillator Gain ................................................ 2731 Usage Notes .................................................................................................................... 2732 49.4.1 Usage Notes on Setting Registers ................................................................... 2732 Page civ of cvi 49.4.2 Usage Notes when the Realtime Clock is not Used ........................................ 2732 Section 50 User Debugging Interface ..............................................................2733 50.1 50.2 50.3 50.4 50.5 50.6 50.7 Features ........................................................................................................................... 2733 Input/Output Pins ............................................................................................................ 2734 Description of the Boundary Scan TAP Controller ........................................................ 2735 50.3.1 Bypass Register (BSBPR)............................................................................... 2735 50.3.2 Instruction Register (BSIR) ............................................................................ 2735 50.3.3 Boundary Scan Register (SDBSR) ................................................................. 2736 50.3.4 ID Register (BSID) ......................................................................................... 2742 Description of the Emulation TAP Controller ................................................................ 2743 50.4.1 Bypass Register (SDBPR) .............................................................................. 2743 50.4.2 Instruction Register (SDIR) ............................................................................ 2743 Operation ........................................................................................................................ 2745 50.5.1 TAP Controller ............................................................................................... 2745 50.5.2 Reset Configuration ........................................................................................ 2746 50.5.3 TDO Output Timing ....................................................................................... 2746 50.5.4 User Debugging Interface Reset ..................................................................... 2747 50.5.5 User Debugging Interface Interrupt ................................................................ 2747 Boundary Scan ................................................................................................................ 2748 50.6.1 Supported Instructions .................................................................................... 2748 50.6.2 Notes ............................................................................................................... 2749 Usage Notes .................................................................................................................... 2750 Section 51 List of Registers .............................................................................2751 51.1 51.2 51.3 Register Addresses (by functional module, in order of the corresponding section numbers) ............................................................................................................. 2753 Register Bits.................................................................................................................... 2810 Register States in Each Operating Mode ........................................................................ 2957 Section 52 Electrical Characteristics ...............................................................2961 52.1 52.2 52.3 52.4 Absolute Maximum Ratings ........................................................................................... 2961 Power-On/Power-Off Sequence...................................................................................... 2962 DC Characteristics .......................................................................................................... 2963 AC Characteristics .......................................................................................................... 2974 52.4.1 Clock Timing .................................................................................................. 2974 52.4.2 Control Signal Timing .................................................................................... 2979 52.4.3 Bus Timing ..................................................................................................... 2981 52.4.4 UBC Timing ................................................................................................... 3012 52.4.5 Direct Memory Access Controller Timing ..................................................... 3013 Page cv of cvi 52.5 52.6 52.4.6 Multi-Function Timer Pulse Unit 2 Timing .................................................... 3014 52.4.7 Watchdog Timer Timing ................................................................................ 3015 52.4.8 Serial Communication Interface with FIFO Timing ....................................... 3016 52.4.9 Renesas Serial Peripheral Interface Timing .................................................... 3017 52.4.10 Renesas Quad Serial Peripheral Interface Timing .......................................... 3021 52.4.11 SPI Multi I/O Bus Controller Timing ............................................................. 3023 52.4.12 I2C Bus Interface 3 Timing ............................................................................. 3026 52.4.13 Serial Sound Interface Timing ........................................................................ 3028 52.4.14 Serial I/O with FIFO Timing .......................................................................... 3030 52.4.15 A/D Converter Timing .................................................................................... 3032 52.4.16 NAND Type Flash Memory Controller Timing ............................................. 3033 52.4.17 USB 2.0 Host/Function Module Timing ......................................................... 3038 52.4.18 Video Display Controller 4 Timing ................................................................ 3041 52.4.19 SD Host Interface Timing ............................................................................... 3044 52.4.20 MMC Host Interface Timing .......................................................................... 3045 52.4.21 General Purpose I/O Ports Timing .................................................................. 3046 52.4.22 User Debugging Interface Timing .................................................................. 3047 52.4.23 AC Characteristics Measurement Conditions ................................................. 3049 A/D Converter Characteristics ........................................................................................ 3050 Video Characteristics of A/D Converter for the Input of Video Signals ........................ 3051 Section 53 States and Handling of Pins ........................................................... 3053 53.1 53.2 53.3 53.4 Pin States ........................................................................................................................ 3053 Treatment of Unused Pins............................................................................................... 3068 Handling of Pins in Deep Standby Mode........................................................................ 3070 Recommended Combination of Bypass Capacitor ......................................................... 3072 Appendix ........................................................................................................... 3075 A. Package Dimensions ....................................................................................................... 3075 Index ................................................................................................................. 3079 Page cvi of cvi SH7268 Group, SH7269 Group Section 1 Overview Section 1 Overview 1.1 SH7268/7269 Features This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes a Renesas-original RISC CPU as its core, and the peripheral functions required to configure a system. The CPU in this LSI is an SH-2A CPU, which provides upward compatibility for SH-1, SH-2, and SH-2E CPUs at object code level. It has a RISC-type instruction set, superscalar architecture, and Harvard architecture, for superior rates of instruction execution. In addition, an independent 32-bit internal-bus architecture enhances data processing power. This CPU brings the user the ability to set up high-performance systems with strong functionality at less expense than was achievable with previous microcontrollers, and is even able to handle realtime control applications requiring high-speed characteristics. This LSI has a floating-point unit and cache. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a 64-Kbyte RAM for high-speed operation, a 2.5-Mbyte large-capacity RAM (128-Kbytes are shared by the data-retention RAM), dataretention RAM, multi-function timer pulse unit 2, compare match timer, realtime clock, serial communication interface with FIFO, I2C bus interface 3, serial sound interface, clocked synchronous serial I/O with FIFO*2, controller area network*2, IEBusTM*1 controller, Renesas SPDIF interface, Renesas serial peripheral interface, Renesas quad serial peripheral interface, SPI multi I/O bus controller, CD-ROM decoder, A/D converter, NAND flash memory controller, USB 2.0 host/function, digital video decoder, video display controller 4, image renderer, display out comparison unit, OpenVG*3-compliant Renesas graphics processor, JPEG codec unit, sampling rate converter, sound generator, SD host interface, MMC host interface, motor control PWM timer, interrupt controller modules, and general I/O ports. This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. The features of this LSI are listed in table 1.1. Notes: 1. IEBus (Inter Equipment Bus) is a trademark of Renesas Electronics Corporation. 2. This module is included or not depending on the product code. 3. OpenVG is a trademark of Khronos Group Inc. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Table 1.1 SH7268/7269 Features Items Specification CPU  Renesas original SuperH architecture  Compatible with SH-1, SH-2, and SH-2E at object code level  32-bit internal data bus  Support of an abundant register-set  Sixteen 32-bit general registers  Four 32-bit control registers  Four 32-bit system registers  Register bank for high-speed response to interrupts  RISC-type instruction set (upward compatible with SH series)  Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability  Load/store architecture  Delayed branch instructions  Instruction set based on C language Page 2 of 3092  Superscalar architecture to execute two instructions at one time including a floating-point unit  Instruction execution time: Up to two instructions/cycle  Address space: 4 Gbytes  Internal multiplier  Five-stage pipeline  Harvard architecture R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Floating-point unit  Floating-point co-processor included  Supports single-precision (32-bit) and double-precision (64-bit)  Supports data type and exceptions that conforms to IEEE754 standard  Two rounding modes: Round to nearest and round to zero  Two denormalization modes: Flush to zero  Floating-point registers  Sixteen 32-bit floating-point registers (single-precision  16 words or double-precision  8 words)  Two 32-bit floating-point system registers  Supports FMAC (multiplication and accumulation) instructions  Supports FDIV (division) and FSQRT (square root) instructions  Supports FLDI0/FLDI1 (load constant 0/1) instructions  Instruction execution time  Latency (FMAC/FADD/FSUB/FMUL): Three cycles (singleprecision), eight cycles (double-precision)  Pitch (FMAC/FADD/FSUB/FMUL): One cycle (single-precision), six cycles (double-precision) Note: FMAC only supports single-precision Cache memory Interrupt controller  Five-stage pipeline  Instruction cache: 8 Kbytes  Operand cache: 8 Kbytes  128-entry/way, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache  Write-back, write-through, LRU replacement algorithm  Way lock function available (only for operand cache); ways 2 and 3 can be locked  Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to PINT0)  On-chip peripheral interrupts: Priority level set for each module  16 priority levels available  Register bank enabling fast register saving and restoring in interrupt processing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Bus state controller  Address space divided into six areas (0 to 5), each a maximum of 64 Mbytes  The following features settable for each area independently  Bus size (8, 16, or 32 bits): Available sizes depend on the area.  Number of access wait cycles (different wait cycles can be specified for read and write access cycles in some areas)  Idle wait cycle insertion (between the same area access cycles or different area access cycles)  Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or asynchronous). The address/data multiplexed I/O (MPX) interface is also available.  PCMCIA interface  Outputs a chip select signal (CS0 to CS5) according to the target area (CS assert or negate timing can be selected by software)  SDRAM refresh Auto refresh or self refresh mode selectable  SDRAM burst access Direct memory access  controller  Sixteen channels; external requests are available for one of them. Can be activated by on-chip peripheral modules  Burst mode and cycle steal mode  Intermittent mode available (16 and 64 cycles supported)  Transfer information can be automatically reloaded Clock pulse generator  Clock mode: Input clock can be selected from external input (EXTAL) or crystal resonator  Input clock can be multiplied by 20 (max.) by the internal PLL circuit  Peak values of EMI noise can be reduced by the on-chip SSCG circuit.  Four types of clocks generated:  CPU clock (I): Maximum 266.67 MHz  Internal bus clock (B): Maximum 133.33 MHz  Peripheral clock 1 (P1): Maximum 66.67 MHz  Peripheral clock 0 (P0): Maximum 33.33 MHz Watchdog timer Page 4 of 3092  On-chip one-channel watchdog timer  A counter overflow can reset the LSI R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Power-down modes  Four power-down modes provided to reduce the power consumption in this LSI  Sleep mode  Software standby mode  Deep standby mode  Module standby mode Multi-function timer pulse unit 2  Maximum 16 lines of pulse inputs/outputs based on five channels of 16-bit timers  18 output compare and input capture registers  Input capture function  Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes  Synchronization of multiple counters  Complementary PWM output mode  Non-overlapping waveforms output for 3-phase inverter control  Automatic dead time setting  0% to 100% PWM duty value specifiable  A/D converter start request delaying function  Interrupt skipping at crest or trough  Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty value  Phase counting mode Two-phase encoder pulse counting available Compare match timer  Realtime clock Two-channel 16-bit counters  Four types of clock can be selected (P0/8, P0/32, P0/128, and P0/512)  DMA transfer request or interrupt request can be issued when a compare match occurs  Internal clock, calendar function, alarm function  Interrupts can be generated at intervals of 1/64 s by the 32.768-kHz on-chip crystal oscillator R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 5 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Serial communication  interface with FIFO  Renesas serial peripheral interface Renesas quad serial peripheral interface SPI multi I/O bus controller I2C bus interface 3 Page 6 of 3092 Eight channels Clocked synchronous or asynchronous mode selectable  Simultaneous transmission and reception (full-duplex communication) supported  Dedicated baud rate generator  Separate 16-byte FIFO registers for transmission and reception  Modem control function (SH7268: channel 1, SH7269: channels 1, 5, and 7 in asynchronous mode)  Two channels  SPI operation  Master mode and slave mode selectable  Programmable bit length, clock polarity, and clock phase can be selected.  Consecutive transfers  MSB first/LSB first selectable  Maximum transfer rate: 33.33 Mbps  Two channels  Connectable to serial flash memory with multiple I/O functionality (single/dual/quad)  Programmable bit length, clock polarity, and clock phase can be selected.  Consecutive transfers  MSB first/LSB first selectable  Maximum transfer rate: 266.67 Mbps  Up to two serial flash memories with multiple I/O bus sizes (single/dual/quad) can be connected.  External address space read mode (built-in read cache)  SPI operating mode  Clock polarity and clock phase can be selected.  Maximum transfer rate: 533.33 Mbps (with two serial flash memories connected)  SH7268: two channels, SH7269: four channels  Master mode and slave mode supported R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Items Section 1 Overview Specification Serial sound interface  SH7268: four-channel, SH7269: six-channel bidirectional serial transfer  Duplex communication (channel 0)  Support of various serial audio formats  Support of master and slave functions  Generation of programmable word clock and bit clock  Multi-channel formats  Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats  Support of eight-stage FIFO for transmission and reception  Support of TDM mode  Support of WS continue mode in which the SSIWS signal is not stopped. Serial I/O with FIFO  Note: This module is not included in the SH7268 Group. Support of 16-stage 32-bits FIFOs independently for transmission and reception  8-bit monaural/16-bit monaural/16-bit stereo audio input and output  Connectable to linear, audio, or A-Law or -Law CODEC chip  Support of master and slave functions Controller area network  Three channels  TTCAN level 1 supports for all channels Note: This module is included or not depending on the product code.  BOSCH 2.0B active compatible  Buffer size: transmit/receive  31, receive only  1  Two or more controller area network channels can be assigned to one bus to increase number of buffers with a granularity of 32 channels  31 Mailboxes for transmission or reception R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 7 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Items Specification TM IEBus controller  IEBus protocol control (layer 2) supported  Half-duplex asynchronous communications  Multi-master system  Broadcast communications function  Selectable mode (three types) with different transfer speeds  On-chip buffers (dual port RAM) for data transmission and reception that enable up to 128 bytes of consecutive transmission/reception (maximum number of transfer bytes in mode 2)  Operating frequency  1/2 divided clocks of 12 MHz or 12.58 MHz.  1/3 divided clocks of 18 MHz or 18.87 MHz.  1/4 divided clocks of 24 MHz or 25.16 MHz.  1/5 divided clocks of 30 MHz or 31.45 MHz.  1/6 divided clocks of 36 MHz or 37.74 MHz.  1/7 divided clocks of 42 MHz or 44.03 MHz.  1/8 divided clock of 48 MHz. Renesas SPDIF interface Page 8 of 3092         Support of IEC60958 standard (stereo and consumer use modes only) Sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz Audio word sizes of 16 to 24 bits per sample Biphase mark encoding Double buffered data Parity encoded serial data Simultaneous transmit and receive Receiver autodetects IEC 61937 compressed mode data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Items Specification CD-ROM decoder         NAND flash memory controller    Support of five formats: Mode 0, mode 1, mode 2, mode 2 form 1, and mode 2 form 2 Sync codes detection and protection (Protection: When a sync code is not detected, it is automatically inserted.) Descrambling ECC correction  P, Q, PQ, and QP correction  PQ or QP correction can be repeated up to three times EDC check Performed before and after ECC Mode and form are automatically detected Link sectors are automatically detected Buffering data control Buffering CD-ROM data including Sync code is transferred in specified format, after the data is descrambled, corrected by ECC, and checked by EDC.  Direct-connected memory interface with NAND-type flash memory Read/write in sectors Two types of transfer modes: Command access mode and sector access mode (512-byte data + 16-byte management code) Interrupt request and DMA transfer request  Supports flash memory requiring 5-byte addresses (2 Gbits and more) USB 2.0 host/function  module  Conforms to the Universal Serial Bus Specification Revision 2.0  480-Mbps and 12-Mbps transfer rates provided (function mode)  On-chip 8-Kbyte RAM as communication buffers R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 480-Mbps, 12-Mbps, and 1.5-Mbps transfer rates provided (host mode) Page 9 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Digital video decoder  Video input Composite video input (CVBS)  A/D converter for video signal input VIN1 and VIN2 pin input selection Sync tip clamp Programmable gain amplifier (PGA) (1.835 to 8.023 dB) 10-bit precision pipelined A/D converter  Sync separation Noise reduction LPF, auto level control sync slicer, horizontal auto frequency control (AFC), vertical count-down, interlace detection, auto gain control (AGC)/peak limiter control  Y/C separation NTSC 2D, PAL 2D, SECAM 1D supported.  Chroma-key decoding NTSC, PAL, SECAM supported. Color killer, auto color control (ACC), TINT correction, R-Y axis correction  Digital clamp Pedestal clamp (Y), center clamp (Cb/Cr), noise detection  Adjustment of output gain Contrast: 0 to approximately 2 times Color (Cb/Cr independently): 0 to approximately 2 times  Video input interface: One channel can be selected from the followings. BT601, BT656 format (NTSC/PAL) input: Input clock: 27 MHz/54 MHz Digital pin input: YCbCr444, RGB888, RGB666, RGB565 Digital pin input size: Maximum input video image size to be set*: 1024 pixels  1024 lines (horizontal  vertical) Note: * Depends on the AC characteristics of the connected device. Examples of input video image size : SVGA (800  600), WVGA (800  480), VGA (640  480), WQVGA (480  240), QVGA (320  240, 240  320) Composite video (CVBS) signal input decoded by the digital video decoder Video display controller 4 Page 10 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Video display controller 4  Input video control Horizontal noise reduction (NR), brightness adjustment and gain adjustment using matrix operation  Scaling control Vertical and horizontal scaling up or down of input video possible at a desired ratio (scaling up of graphics also possible ) Scaling up ratio: 1 to 8; scaling down ratio: 1/8 to 1 Interpolation: Hold or linear selectable 2D IP conversion: 2D IP conversion through separately setting the initial phases for the top and bottom fields  Video recording Output pixel format: YCbCr422, RGB888, RGB565 Output field rate: 1/1, 1/2, 1/4, 1/8 Rotation: Horizontal mirroring and 90/180/270 rotation for YCbCr422 and RGB565 (exclusive control for rotation and image renderer) Maximum video image size to be stored: 1 size of input video image  Output video control Black stretch: Black area stretched according to Y signal state Enhancer capability: LTI (transient improvement) and sharpness (contour emphasis) for Y signal  Three graphics layers (one of them also for input video) Available input pixel formats 1 bit/pixel: CLUT1 4 bits/pixel: CLUT4 8 bits/pixel: CLUT8 16 bits/pixel: YCbCr422, RGB565, ARGB1555, ARGB4444 32 bits/pixel: ARGB8888, RGB888  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Superimposition Alpha blending in a rectangular area: Input video, layer 1, and layer 2 blended according to the transparency percentage  (fade-in and fade-out function available) Chroma key function: Mixing based on transparency percentage  using the specified RGB and CLUT value Pixel-base alpha blending: Alpha blending for each pixel based on transparency percentage  Page 11 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Video display controller 4  Panel output control Panel output correction: Brightness adjustment and contrast adjustment, gamma correction, panel dithering TCON: Various timing output for LCD panel driving provided by a total of seven vertical and horizontal panel driver signals Panel output pixel format: RGB888, RGB666, RGB565, serial RGB Output video image size: Maximum output video image size to be set*: 1999 pixels  2035 lines (horizontal  vertical) Note: * Depends on the AC characteristics of the display panel. Examples of output video image size: SVGA (800  600), WVGA (800  480), VGA (640  480), WQVGA (480  240), QVGA (320  240, 240  320)  Frame buffer Large-capacity on-chip RAM and external SDRAM can be used. Note: When using external SDRAM, display may not be possible if the bus bandwidth is insufficient. Therefore, it is recommended that the frame buffer be allocated in the large-capacity on-chip RAM.  Refers to the video captured data as two-dimensional texture data and draws a shape by performing texture mapping for an arbitrary shape divided into triangular objects.  Display list system  Drawing functions Texture mapping, bilinear filtering, automatic coordinate generation (and relative coordinate input)  Instruction system Draw instruction: TRI for drawing a triangle Control instructions: TRAP, INT, NOP, SYNCM, SYNCW, WTL, and WTS  Drawing space Destination coordinates: 0  X  1,023, 0  Y  1,023 Source coordinates: 0  u  1,023, 0  v  1,023 Image renderer Page 12 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Display out comparison unit  Calculates the CRC code of an arbitrary graphics plane and compares it with the pre-calculated CRC code.  Specifies the rectangular area in an arbitrary graphics plane selected from three graphics planes and one plane of the graphics data obtained after  blending of the video display controller 4.  Pixel Format 32 bits/pixel: ARGB8888/RGB888/RGB666 16 bits/pixel: RGB565 OpenVG-compliant Renesas graphics processor  OpenVG, which is an open 2D vector graphics API, can be processed. JPEG codec unit  Compression and decompression method conforming to the JPEG baseline standard within the range described in this document.  Operational precision: Conforming to JPEG Part 2, ISO-IEC10918-2  Pixel format: Compression: YCbCr422 Decompression: YCbCr444, YCbCr422, YCbCr411, YCbCr420 Output pixel format to the buffer: YCbCr422, ARGB8888, RGB565  Four quantization tables provided  Four Huffman tables provided (two tables for AC coefficients and two tables for DC coefficients)  Markers supported: SOI, SOF0, SOS, DQT, DHT, DRI, RSTm, and EOI  Image data rate: Max. 133.33 Mbytes/s (at 66.67-MHz operation)  Three channels  Data format: 32-bit stereo (16 bits each to L/R), 16-bit monaural  Input sampling rate: 8/11.025/12/16/22.05/24/32/44.1/48 kHz  Output sampling rate: 32/44.1/48 kHz, 8/16 kHz (input sampling rate: 44.1 kHz) Sampling rate converter  Processes can be accelerated in OpenVG stage 2 to stage 8 using the dedicated hardware and programmable shader. Note: When using the OpenVG graphics processor and JPEG codec unit at the same time, it is necessary to implement exclusive bus access control in software to ensure that they do not access the bus simultaneously. Operation cannot be guaranteed if the OpenVG graphics processor and JPEG codec unit access the bus simultaneously. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 13 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Items Specification Sound generator  Capable of adjusting sound volume using 8-bit PWM output  Four types of operating clocks (P0/2, P0/4, P0/8, and P0/16) can be selected.  Frequency settings in the 31-Hz to 20-kHz range with precision of 1% or less  Automatic attenuator function can be selected  Two channels  SD memory I/O card interface (1-/4-bits SD bus)  Error check function: CRC7 (command), CRC16 (data)  Interrupt requests SD host interface  Card access interrupt  SDIO access interrupt  Card detect interrupt  DMA transfer requests  SD_BUF write  SD_BUF read  Card detection function, write protect supported  Interface to multi-media card (MMC)  Data bus: 1-/4-/8-bit MMC mode  Interrupt requests: card detection, error/time-out, and normal operation  DMA transfer requests: CE_DATA write and CE_DATA read  Card detection function  SH7268: 101 I/Os, 4 inputs with open-drain outputs, and 6 inputs  SH7269: 133 I/Os, 8 inputs with open-drain outputs, and 8 inputs  Input or output can be selected for each bit  10-bit resolution  SH7268: Six input channels, SH7269: Eight input channels  A/D conversion request by the external trigger or timer trigger Motor control PWM timer  Two 10-bit PWM channels, each with eight outputs User break controller  Two break channels  Address, data value, access mode, and data size assignable as break conditions.  E10A emulator support  JTAG-standard pin assignment MMC host interface General I/O ports A/D converter User debugging interface Page 14 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Items Specification On-chip RAM  64-Kbyte memory for high-speed operation (16 Kbytes  4)  2.5-Mbyte large capacity memory for video display/recording and work (128-Kbytes are used for data retention)  128-Kbyte memory for data retention (16 Kbytes  2, 32 Kbytes  1, 64 Kbytes  1) Boot modes  SH7268/SH7269: Six boot modes (boot modes 0 to 5) Boot mode 0: Booting from memory (bus width: 16 bits) connected to CS0 area Boot mode 1: Booting from memory (bus width: 32 bits) connected to CS0 area Boot mode 2: Booting from a NAND flash memory Boot mode 3: Booting from a serial flash memory Boot mode 4: Booting from a NAND flash memory with SD controller Boot mode 5: Booting from a NAND flash memory with MMC controller Power supply voltage  Vcc: 1.15 to 1.35 V  PVcc: 3.0 to 3.6 V  SH7268 208-pin QFP, 28-mm square, 0.5-mm pitch JEITA package code: P-LQFP208-28  28-0.50 Renesas code: PLQP0208KB-A  SH7269 (QFP) 256-pin QFP, 28-mm square, 0.4-mm pitch JEITA package code: P-LQFP256-28  28-0.40 Renesas code: PLQP0256LB-A  SH7269 (BGA) 272-pin BGA (16 thermal balls), 17-mm square, 0.8-mm pitch JEITA package code: P-LFBGA272-17  17-0.80 Renesas code: PRBG0272GA-A Packages R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 15 of 3092 SH7268 Group, SH7269 Group Section 1 Overview 1.2 Product Lineup Table 1.2 Product Lineup Product Classification Product Code SH7268 Group R5S72680 W266FP Improved functionality for video display controller 4 Controller Area Network No Included R5S72681 W266FP Included R5S72680 P266FP Not included R5S72681 P266FP Included R5S72680 RW266FP Yes* Included R5S72681 RP266FP SH7269 Group R5S72690 W266FP Regular specifications (-20 to +85°C) Package New application Suitable substitute 208-pin QFP Recommended - Not recommended R5S72680W2 66FP Not recommended R5S72681P26 6FP Recommended - Recommended - Recommended - Recommended - Not recommended R5S72690W2 66FP Not recommended R5S72691P26 6FP Recommended - Recommended - Not recommended R5S72690W2 66BG Not recommended R5S72691P26 6BG Recommended - Recommended - Recommended - Recommended - Recommended - Wide-range specifications (-40 to +85°C) Regular specifications (-20 to +85°C) 208-pin QFP Wide-range specifications (-40 to +85°C) No Included R5S72691 W266FP Included R5S72690 P266FP Not included R5S72691 P266FP Included R5S72690 W266BG Included R5S72691 W266BG Included R5S72690 P266BG Not included R5S72691 P266BG Included R5S72690 RW266FP Operating Temperature Yes* Included Regular specifications (-20 to +85°C) 256-pin QFP Wide-range specifications (-40 to +85°C) Regular specifications (-20 to +85°C) 272-pin BGA Wide-range specifications (-40 to +85°C) Regular specifications (-20 to +85°C) R5S72691 RP266FP Wide-range specifications (-40 to +85°C) R5S72690 RW266BG Regular specifications (-20 to +85°C) R5S72691 RP266BG Wide-range specifications (-40 to +85°C) 256-pin QFP 272-pin BGA Note: * This product is referred to as the “R version” in this manual. Page 16 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 1.3 Section 1 Overview Block Diagram SH-2A CPU core Floating-point unit CPU instruction fetch bus (F bus) 32 bits CPU memory access bus (M bus) Peripheral bus 0 Peripheral bus 0 Instruction cache memory 8KB Operand cache memory 8KB High-speed on-chip RAM 64KB User break controller Image renderer Peripheral bus 1 Peripheral bus 0 OpenVG™compliant Renesas graphics processor JPEG codec unit Port Cache controller DREQ input DACK output TEND output Port Port DMA controller CPU bus (CPU clock) Video display controller 4 Video input LCD interface I/O UBCTRG output Internal CPU bus (IC-BUS) Internal DMA bus (ID-BUS) Internal graphic bus (IV1-BUS) Internal graphic bus (IV2-BUS) Internal graphic bus (IV3-BUS) Internal graphic bus (IV4-BUS) Internal graphic bus (RGP1-BUS) Internal graphic bus (RGP2-BUS) Internal graphic bus (RGP3-BUS) Internal graphic bus (RGP4-BUS) 32 bits 64 bits Bus state controller Large-capacity on-chip RAM0 Large-capacity on-chip RAM1 Large-capacity on-chip RAM2 Large-capacity on-chip RAM3 Large-capacity on-chip RAM4 Large-capacity on-chip RAM5 Peripheral bus 2 controller Peripheral bus 1 controller Peripheral bus 0 controller SPI multi I/O bus controller Port Port External bus I/O Internal bus (Internal bus clock) Serial I/O Peripheral bus 1 (Peripheral clock 1) Peripheral bus 2 (Peripheral clock 1) 32 bits 32 bits Renesas serial peripheral interface USB 2.0 host/function module CD-ROM decoder Renesas SPDIF interface A/D Converter Renesas quad serial peripheral interface Serial communication interface with FIFO SD host interface Port Port Port Port Port Port Port Port Serial I/O USB bus I/O USB_X1 input USB_X2 output Serial I/O audio clock input Analog input ADTRG input Serial I/O Serial I/O SD interface I/O MMC interface I/O Peripheral bus 0 (Peripheral clock 0) Interrupt controller Multi-funciton timer pulse unit 2 Watchdog timer Realtime clock I2C bus interface 3 Port Port 32 bits Clock pulse generator MMC host interface Port Port Port EXTAL input XTAL output CKIO output Clock mode input RES input NMI input IRQ input PINT input Timer pulse I/O Display out comparison unit Compare match timer WDTOVF output RTC_X1 input RTC_X2 output Digital video decoder Sound generator Port Port Analog input Timer pulse VIDEO_X1 input output VIDEO_X2 output Motor control PWM timer Serial sound interface Clocked synchronous serial I/O with FIFO Controller area network TM IEBus controller Port Port Port Port Port I2C bus I/O Serial I/O audio clock input Serial I/O audio clock input CAN bus I/O IEBus I/O audio clock input Sampling rate converter NAND flash memory controller User debugging interface Power-down mode control General I/O port Port Port Port Port Timer pulse output JTAG I/O General I/O Flash memory interface I/O Figure 1.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 17 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Pin Assignment 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 PG27/LCD_TCON2/LCD_EXTCLK PG26/LCD_TCON1 PG25/LCD_TCON0 PG24/LCD_CLK PG23/LCD_DATA23/LCD_TCON6/TxD5/AUDATA3 PG22/LCD_DATA22/LCD_TCON5/RxD5/AUDSYNC Vcc PG21/DV_DATA7/LCD_DATA21/LCD_TCON4/TxD4/AUDATA2 Vss PG20/DV_DATA6/LCD_DATA20/LCD_TCON3/RxD4 PVcc PG19/DV_DATA5/LCD_DATA19/SPDIF_OUT/SCK5 PG18/DV_DATA4/LCD_DATA18/SPDIF_IN/SCK4 Vcc PG17/WE3/ICIOWR/AH/DQMUU/LCD_DATA17/AUDATA1 Vss PG16/WE2/ICIORD/DQMUL/LCD_DATA16/AUDATA0 PG15/D31/LCD_DATA15/PINT7 PG14/D30/LCD_DATA14/PINT6 PG13/D29/LCD_DATA13/PINT5 Vcc PG12/D28/LCD_DATA12/PINT4 Vss PG11/D27/LCD_DATA11/PINT3/TIOC3D PVcc PG10/D26/LCD_DATA10/PINT2/TIOC3C PG9/D25/LCD_DATA9/PINT1/TIOC3B Vcc PG8/D24/LCD_DATA8/PINT0/TIOC3A Vss PG7/D23/LCD_DATA7/IRQ7/TIOC2B PG6/D22/LCD_DATA6/IRQ6/TIOC2A PG5/D21/LCD_DATA5/IRQ5/TIOC1B PG4/D20/LCD_DATA4/IRQ4/TIOC1A Vcc PG3/D19/LCD_DATA3/IRQ3/TIOC0D Vss AUDIO_X1 AUDIO_X2 PVcc PG2/D18/LCD_DATA2/IRQ2/TIOC0C Vss PG1/D17/LCD_DATA1/IRQ1/TIOC0B Vcc PG0/D16/LCD_DATA0/IRQ0/TIOC0A Vss TCK TMS TDI TDO ASEBRKAK/ASEBRK TRST 1.4 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Vcc PC8/CS3/TxD7/CTx1/CTx0&CTx1 PB1/A1/TIOC0A PB2/A2/TIOC0B PB3/A3/TIOC0C Vss PB4/A4/TIOC0D Vcc PB5/A5/TIOC1A PB6/A6/TIOC1B PVcc PB7/A7/TIOC2A Vss PB8/A8/TIOC2B Vcc PB9/A9/TIOC3A PB10/A10/TIOC3B PB11/A11/TIOC3C PB12/A12/TIOC3D Vss PB13/A13/QIO2_1/SPBIO2_1 Vcc PB14/A14/QIO3_1/SPBIO3_1 PB15/A15/QIO2_0/SPBIO2_0 PVcc PB16/A16/QIO3_0/SPBIO3_0 Vss PB17/A17/QSPCLK_0/RSPCK0/SPBCLK Vcc PB18/A18/QSSL_0/SSL00/SPBSSL PB19/A19/QMO_0/QIO0_0/MOSI0/SPBMO_0/SPBIO0_0 PB20/A20/QMI_0/QIO1_0/MISO0/SPBMI_0/SPBIO1_0 Vss PB21/A21/CRx2/IERxD Vcc PB22/A22/CTx2/IETxD/CS4 PC0/CS0/MD_BOOT2 PVcc CKIO Vss PA0/MD_BOOT0 Vcc VIDEO_X2 VIDEO_X1 PVcc USB_X2 USB_X1 USBUVss USBUVcc USBAVss USBAVcc USBAPVcc USBAPVss REFRIN USBDVss USBDVcc VBUS DP DM USBDPVss USBDPVcc RES PLLVss PLLVss XTAL EXTAL PLLVcc Vcc ASEMD Vss NMI PVcc PE3/SDA1/TCLKD/ADTRG/DV_HSYNC PE2/SCL1/TCLKC/IOIS16/DV_VSYNC PE1/SDA0/TCLKB/AUDIO_CLK/DV_CLK PE0/SCL0/TCLKA/LCD_EXTCLK PA1/MD_BOOT1 6 7 8 9 10 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 PC5/RAS/CRx0/CRx0/CRx1/CRx2/IRQ0 PVcc PC6/CAS/SCK7/CTx0/CTx0&CTx1&CTx2 Vss PC7/CKE/RxD7/CRx1/CRx0/CRx1/IRQ1 AVref AVcc AVss PH5/AN5/PINT5/LCD_EXTCLK PH4/AN4/PINT4 PH3/AN3/PINT3 PH2/AN2/PINT2 PH1/AN1/PINT1 PH0/AN0/PINT0 BIAS VRB VRT VIN2 VIN1 VDAVss VDAVcc Vss 1 2 3 4 5 208-pin QFP Top view 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 PC1/RD PVcc PC2/RD/WR/SCK6 PC3/WE0/DQMLL/RxD6 PC4/WE1/WE/DQMLU/TxD6 PF0/BREQ/QSPCLK_1/RSPCK1/TIOC4A/DREQ0/AUDCK PVcc PF1/BACK/QSSL_1/SSL10/TIOC4B/DACK0 Vss PF2/WAIT/QMO_1/QIO0_1/MOSI1/TIOC4C/TEND0/SPBMO_1/SPBIO0_1 PF3/CS2/QMI_1/QIO1_1/MISO1/TIOC4D/AUDIO_XOUT/SPBMI_1/SPBIO1_1 PF4/CS5/CE1A/SSISCK0/SGOUT_0 PF5/SSIWS0/SGOUT_1 PF6/CE2A/SSITxD0/SGOUT_2 PF7/SSIRxD0/RxD0/SGOUT_3/CTS1 PF8/A23/TxD0 PF9/BS/DV_DATA0/SCK0/MMC_D4/RTS1 PVcc PF10/CS1/SSISCK1/DV_DATA1/SCK1/MMC_D5 Vss PF11/SSIWS1/DV_DATA2/RxD1/MMC_D6 PF12/SSIDATA1/DV_DATA3/TxD1/MMC_D7 PF13/A24/SSISCK2/SCK2 PF14/A25/SSIWS2/RxD2 PF15/A0/SSIDATA2/WDTOVF/TxD2/UBCTRG PF16/SD_CD_0/FCE/IRQ4/MMC_CD PF17/SD_WP_0/FRB/IRQ5 PF18/SD_D1_0/SSISCK3/IRQ6/MMC_D1 PVcc PF19/SD_D0_0/SSIWS3/IRQ7/MMC_D0 Vss PF20/SD_CLK_0/SSIDATA3/MMC_CLK Vcc PF21/SD_CMD_0/SCK3/MMC_CMD PF22/SD_D3_0/RxD3/MMC_D3 PF23/SD_D2_0/TxD3/MMC_D2 PD0/D0/PWM1A PD1/D1/PWM1B PD2/D2/PWM1C PD3/D3/PWM1D PVcc Vss PD4/D4/FRE/PWM1E PD5/D5/FCLE/PWM1F PD6/D6/FALE/PWM1G PD7/D7/FWE/PWM1H PD8/D8/NAF0/PWM2A PD9/D9/NAF1/PWM2B PD10/D10/NAF2/PWM2C PD11/D11/NAF3/PWM2D PVcc PD12/D12/NAF4/PWM2E Vss PD13/D13/NAF5/PWM2F PD14/D14/NAF6/PWM2G PD15/D15/NAF7/PWM2H MD_CLK0 Figure 1.2 (1) Pin Assignment for the SH7268 Group Page 18 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PC5/RAS/CRx0/CRx0/CRx1/CRx2/IRQ0 PVcc PC6/CAS/SCK7/CTx0/CTx0&CTx1&CTx2 Vss PC7/CKE/RxD7/CRx1/CRx0/CRx1/IRQ1 Vcc PC8/CS3/TxD7/CTx1/CTx0&CTx1 PB1/A1/TIOC0A PB2/A2/TIOC0B PB3/A3/TIOC0C PJ14/DV_DATA14/LCD_DATA14/PINT6/PWM2G/TxD6 PVcc PJ15/DV_DATA15/LCD_DATA15/PINT7/PWM2H/TxD7 Vss PB4/A4/TIOC0D Vcc PJ16/DV_DATA16/LCD_DATA16/RSPCK0/TIOC0A/SIOFSCK PJ17/DV_DATA17/LCD_DATA17/SSL00/TIOC0B/SIOFSYNC PJ18/DV_DATA18/LCD_DATA18/MOSI0/TIOC0C/SIOFTxD PB5/A5/TIOC1A PB6/A6/TIOC1B PVcc PB7/A7/TIOC2A Vss PB8/A8/TIOC2B Vcc PB9/A9/TIOC3A PB10/A10/TIOC3B PB11/A11/TIOC3C PB12/A12/TIOC3D PJ19/DV_DATA19/LCD_DATA19/MISO0/TIOC0D/SIOFRxD/AUDIO_XOUT PVcc PJ20/DV_DATA20/LCD_DATA20/LCD_TCON3/IRQ0/CRx2/CRx0/CRx1/CRx2 Vss PB13/A13/QIO2_1/SPBIO2_1 Vcc PJ21/DV_DATA21/LCD_DATA21/LCD_TCON4/IRQ1/CTx2/CTx0&CTx1&CTx2 PJ22/DV_DATA22/LCD_DATA22/LCD_TCON5/IRQ2/CRx1/CRx0/CRx1 PJ23/DV_DATA23/LCD_DATA23/LCD_TCON6/IRQ3/CTx1/CTx0&CTx1 PB14/A14/QIO3_1/SPBIO3_1 PB15/A15/QIO2_0/SPBIO2_0 PVcc PB16/A16/QIO3_0/SPBIO3_0 Vss PB17/A17/QSPCLK_0/RSPCK0/SPBCLK Vcc PB18/A18/QSSL_0/SSL00/SPBSSL PB19/A19/QMO_0/QIO0_0/MOSI0/SPBMO_0/SPBIO0_0 PB20/A20/QMI_0/QIO1_0/MISO0/SPBMI_0/SPBIO1_0 Vss PB21/A21/CRx2/IERxD Vcc PB22/A22/CTx2/IETxD/CS4 PC0/CS0/MD_BOOT2 PVcc CKIO Vss PA0/MD_BOOT0 Vcc PF0/BREQ/QSPCLK_1/RSPCK1/TIOC4A/DREQ0/AUDCK PVcc PF1/BACK/QSSL_1/SSL10/TIOC4B/DACK0 Vss PF2/WAIT/QMO_1/QIO0_1/MOSI1/TIOC4C/TEND0/SPBMO_1/SPBIO0_1 PF3/CS2/QMI_1/QIO1_1/MISO1/TIOC4D/AUDIO_XOUT/SPBMI_1/SPBIO1_1 PF4/CS5/CE1A/SSISCK0/SGOUT_0 PF5/SSIWS0/SGOUT_1 PF6/CE2A/SSITxD0/SGOUT_2 PF7/SSIRxD0/RxD0/SGOUT_3/CTS1 PF8/A23/TxD0 PF9/BS/DV_DATA0/SCK0/MMC_D4/RTS1 PVcc PF10/CS1/SSISCK1/DV_DATA1/SCK1/MMC_D5 Vss PF11/SSIWS1/DV_DATA2/RxD1/MMC_D6 PF12/SSIDATA1/DV_DATA3/TxD1/MMC_D7 PF13/A24/SSISCK2/SCK2 PF14/A25/SSIWS2/RxD2 PF15/A0/SSIDATA2/WDTOVF/TxD2/UBCTRG PVcc PJ10/DV_DATA10/LCD_DATA10/PINT2/PWM2C/SCK5 Vss PF16/SD_CD_0/FCE/IRQ4/MMC_CD PF17/SD_WP_0/FRB/IRQ5 PF18/SD_D1_0/SSISCK3/IRQ6/MMC_D1 PJ11/DV_DATA11/LCD_DATA11/PINT3/PWM2D/SCK6 PJ12/DV_DATA12/LCD_DATA12/PINT4/PWM2E/SCK7 PJ13/DV_DATA13/LCD_DATA13/PINT5/PWM2F/TxD5 PVcc PF19/SD_D0_0/SSIWS3/IRQ7/MMC_D0 Vss PF20/SD_CLK_0/SSIDATA3/MMC_CLK Vcc PF21/SD_CMD_0/SCK3/MMC_CMD PF22/SD_D3_0/RxD3/MMC_D3 PF23/SD_D2_0/TxD3/MMC_D2 PD0/D0/PWM1A PVcc PJ24/SGOUT_0/SSISCK4/LCD_TCON3/SPDIF_IN/SCK7 Vss PD1/D1/PWM1B PD2/D2/PWM1C PD3/D3/PWM1D PJ25/SGOUT_1/SSIWS4/LCD_TCON4/SPDIF_OUT/RxD7 PJ26/SGOUT_2/SSIDATA4/LCD_TCON5/TxD7 PJ27/SGOUT_3/TIOC1A/CTS7 PVcc Vss PD4/D4/FRE/PWM1E PD5/D5/FCLE/PWM1F PD6/D6/FALE/PWM1G PD7/D7/FWE/PWM1H PD8/D8/NAF0/PWM2A PD9/D9/NAF1/PWM2B PD10/D10/NAF2/PWM2C PD11/D11/NAF3/PWM2D PVcc PD12/D12/NAF4/PWM2E Vss PD13/D13/NAF5/PWM2F PD14/D14/NAF6/PWM2G PD15/D15/NAF7/PWM2H MD_CLK0 PC1/RD PVcc PC2/RD/WR/SCK6 PC3/WE0/DQMLL/RxD6 PC4/WE1/WE/DQMLU/TxD6 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 PG27/LCD_TCON2/LCD_EXTCLK PG26/LCD_TCON1 PG25/LCD_TCON0 PG24/LCD_CLK PG23/LCD_DATA23/LCD_TCON6/TxD5/AUDATA3 PG22/LCD_DATA22/LCD_TCON5/RxD5/AUDSYNC Vcc PG21/DV_DATA7/LCD_DATA21/LCD_TCON4/TxD4/AUDATA2 Vss PG20/DV_DATA6/LCD_DATA20/LCD_TCON3/RxD4 PVcc PG19/DV_DATA5/LCD_DATA19/SPDIF_OUT/SCK5 PG18/DV_DATA4/LCD_DATA18/SPDIF_IN/SCK4 PJ9/DV_DATA9/LCD_DATA9/PINT1/PWM2B/RTS5 PJ8/DV_DATA8/LCD_DATA8/PINT0/PWM2A/CTS5 PJ7/DV_DATA7/LCD_DATA7/SD_D2_1/PWM1H Vcc PG17/WE3/ICIOWR/AH/DQMUU/LCD_DATA17/AUDATA1 Vss PJ6/DV_DATA6/LCD_DATA6/SD_D3_1/PWM1G PVcc PJ5/DV_DATA5/LCD_DATA5/SD_CMD_1/PWM1F PG16/WE2/ICIORD/DQMUL/LCD_DATA16/AUDATA0 PG15/D31/LCD_DATA15/PINT7 PG14/D30/LCD_DATA14/PINT6 PG13/D29/LCD_DATA13/PINT5 Vcc PG12/D28/LCD_DATA12/PINT4 Vss PG11/D27/LCD_DATA11/PINT3/TIOC3D PVcc PG10/D26/LCD_DATA10/PINT2/TIOC3C PG9/D25/LCD_DATA9/PINT1/TIOC3B PJ4/DV_DATA4/LCD_DATA4/SD_CLK_1/PWM1E PJ3/DV_DATA3/LCD_DATA3/SD_D0_1/PWM1D PJ2/DV_DATA2/LCD_DATA2/SD_D1_1/PWM1C Vcc PG8/D24/LCD_DATA8/PINT0/TIOC3A Vss PJ1/DV_DATA1/LCD_DATA1/SD_WP_1/PWM1B PVcc PJ0/DV_DATA0/LCD_DATA0/SD_CD_1/PWM1A PG7/D23/LCD_DATA7/IRQ7/TIOC2B PG6/D22/LCD_DATA6/IRQ6/TIOC2A PG5/D21/LCD_DATA5/IRQ5/TIOC1B PG4/D20/LCD_DATA4/IRQ4/TIOC1A Vcc PG3/D19/LCD_DATA3/IRQ3/TIOC0D Vss AUDIO_X1 AUDIO_X2 PVcc PG2/D18/LCD_DATA2/IRQ2/TIOC0C Vss PG1/D17/LCD_DATA1/IRQ1/TIOC0B Vcc PG0/D16/LCD_DATA0/IRQ0/TIOC0A Vss TCK TMS TDI TDO ASEBRKAK/ASEBRK TRST SH7268 Group, SH7269 Group Section 1 Overview 194 195 196 197 198 199 200 201 202 203 204 205 206 193 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 256-pin QFP Top view 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AVref PH7/AN7/PINT7 AVcc PH6/AN6/PINT6 AVss PH5/AN5/PINT5/LCD_EXTCLK PH4/AN4/PINT4 PH3/AN3/PINT3 PH2/AN2/PINT2 PH1/AN1/PINT1 PH0/AN0/PINT0 BIAS VRB VRT VIN2 VIN1 VDAVss VDAVcc Vss VIDEO_X2 VIDEO_X1 PVcc USB_X2 USB_X1 USBUVss USBUVcc USBAVss USBAVcc USBAPVcc USBAPVss REFRIN USBDVss USBDVcc VBUS DP DM USBDPVss USBDPVcc RTC_X2 RTC_X1 RES PLLVss PLLVss XTAL EXTAL PLLVcc Vcc ASEMD Vss NMI PVcc PE7/SDA3/RxD7 PE6/SCL3/RxD6 PE5/SDA2/RxD5/DV_HSYNC PE4/SCL2/RxD4/DV_VSYNC PE3/SDA1/TCLKD/ADTRG/DV_HSYNC PE2/SCL1/TCLKC/IOIS16/DV_VSYNC PE1/SDA0/TCLKB/AUDIO_CLK/DV_CLK PE0/SCL0/TCLKA/LCD_EXTCLK PJ31/DV_CLK PJ30/SSIDATA5/TIOC2B/IETxD PJ29/SSIWS5/TIOC2A/IERxD PJ28/SSISCK5/TIOC1B/RTS7 PA1/MD_BOOT1 Figure 1.2 (2) Pin Assignment for the SH7269 Group (QFP) Page 19 of 3092 SH7268 Group, SH7269 Group Section 1 Overview 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A A B B C C D D E E F F 272-pin BGA (16 thermal balls) G G Top perspective view H H J J K K L L M M N N P P R R T T U U V V W W Y Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 1.2 (3) Pin Assignment for the SH7269 Group (BGA) Page 20 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 1.5 Table 1.3 Section 1 Overview Pin Functions Pin Functions Classification Symbol I/O Name Function Power supply Vcc I Power supply Power supply pins. All the Vcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Vss I Ground Ground pins. All the Vss pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. PVcc I Power supply for I/O circuits Power supply for I/O pins. All the PVcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. PLLVcc I Power supply for PLL Power supply for the on-chip PLL oscillator. PLLVss I Ground for PLL Ground pin for the on-chip PLL oscillator. Note: SH7269 (BGA) Group products do not have this pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 21 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function Clock EXTAL I External clock Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. XTAL O Crystal Connected to a crystal resonator. CKIO O System clock I/O Supplies the system clock to external devices. AUDIO_CLK I External clock for audio Input pin of external clock for audio. A clock input to the divider is selected from an oscillation clock input on this pin or pins AUDIO_X1 and AUDIO_X2. AUDIO_X1 I AUDIO_X2 O Crystal resonator/ external clock for audio Pins connected to a crystal resonator for audio. An external clock can be input on pin AUDIO_X1. A clock input to the divider is selected from an oscillation clock input on these pins or the AUDIO_CLK pin. Clock AUDIO_XOUT O AUDIO_X1 clock output Output for the on-chip crystal oscillator on AUDIO_X1 or the external clock signal. Operating mode control MD_BOOT2 I Mode set Sets the operating mode. Do not change the signal levels on these pins while the RES pin is asserted or until the mode is fixed, after the negation. MD_CLK0 I Clock mode set Switches the SSCG circuit on or off. ASEMD I ASE mode If a low level is input at the ASEMD pin while the RES pin is asserted, ASE mode is entered; if a high level is input, product chip mode is entered. MD_BOOT1 MD_BOOT0 In ASE mode, the E10A-USB emulator function is enabled. When this function is not in use, fix it high. Page 22 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function System control RES I Power-on reset This LSI enters the power-on reset state when this signal goes low. WDTOVF O Watchdog timer overflow Outputs an overflow signal from the watchdog timer. BREQ I Bus-mastership request A low level is input to this pin when an external device requests the release of the bus mastership. BACK O Bus-mastership request acknowledge Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. NMI I Non-maskable interrupt Non-maskable interrupt request pin. Fix it high when not in use. IRQ7 to IRQ0 I Interrupt requests 7 Maskable interrupt request pins. to 0 Level-input or edge-input detection can be selected. When the edge-input detection is selected, the rising edge, falling edge, or both edges can also be selected. PINT7 to PINT0 I Interrupt requests 7 Maskable interrupt request pins. to 0 Only level-input detection can be selected. Address bus A25 to A0 O Address bus Data bus D31 to D0 I/O Data bus Interrupts R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Outputs addresses. Bidirectional data bus. Page 23 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol Bus control Page 24 of 3092 I/O Name Function CS5 to CS0 O Chip select 5 to 0 Chip-select signals for external memory or devices. RD O Read Indicates that data is read from an external device. RD/WR O Read/write Read/write signal. BS O Bus start Bus-cycle start signal. AH O Address hold Address hold timing signal for the device that uses the address/data-multiplexed bus. WAIT I Wait Inserts a wait cycle into the bus cycles during access to the external space. WE0 O Byte select Indicates a write access to bits 7 to 0 of data of external memory or device. WE1 O Byte select Indicates a write access to bits 15 to 8 of data of external memory or device. WE2 O Byte select Indicates a write access to bits 23 to 16 of data of external memory or device. WE3 O Byte select Indicates a write access to bits 31 to 24 of data of external memory or device. DQMLL O Byte select Selects bits D7 to D0 when SDRAM is connected. DQMLU O Byte select Selects bits D15 to D8 when SDRAM is connected. DQMUL O Byte select Selects bits D23 to D16 when SDRAM is connected. DQMUU O Byte select Selects bits D31 to D24 when SDRAM is connected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Classification Symbol Bus control I/O Name Function RAS O RAS Connected to the RAS pin when SDRAM is connected. CAS O CAS Connected to the CAS pin when SDRAM is connected. CKE O CK enable Connected to the CKE pin when SDRAM is connected. CE1A O Lower byte select for PCMCIA card Connected to PCMCIA card select signals D7 to D0. CE2A O Upper byte select for PCMCIA card Connected to PCMCIA card select signals D15 to D8. ICIOWR O Write strobe for PCMCIA Connected to the PCMCIA I/O write strobe signal. ICIORD O Read strobe for PCMCIA Connected to the PCMCIA I/O read strobe signal. WE O Write strobe for PCMCIA memory Connected to the PCMCIA memory write strobe signal. IOIS16 I PCMCIA dynamic bus sizing Indicates 16-bit I/O of the PCMCIA. I DMA-transfer request Input pin to receive external requests for DMA transfer. O DMA-transfer request accept Output pin for signals indicating acceptance of external requests from external devices. TEND0 O DMA-transfer end output Output pin for DMA transfer end. TCLKA, TCLKB, TCLKC, TCLKD I Timer clock input External clock input pins for the timer. TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O Input capture/ output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A, TIOC1B I/O Input capture/ output compare (channel 1) The TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins. TIOC2A, TIOC2B I/O Input capture/ output compare (channel 2) The TGRA_2 and TGRB_2 input capture input/output compare output/PWM output pins. Direct memory DREQ0 access controller DACK0 Multi-function timer pulse unit 2 Section 1 Overview R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 25 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function Multi-function timer pulse unit 2 TIOC3A, TIOC3B, TIOC3C, TIOC3D I/O Input capture/ output compare (channel 3) The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O Input capture/ output compare (channel 4) The TGRA_4 to TGRD_4 input capture input/output compare output/PWM output pins. I Connected to 32.768-kHz crystal resonator. Realtime clock RTC_X1 RTC_X2 O Crystal resonator for realtime clock/ external clock The RTC_X1 pin can also be used to input an external clock. The RTC_X1 and RTC_X2 pins are not implemented on the SH7268. Serial TxD7 to TxD0 communication RxD7 to RxD0 interface with SCK7 to SCK0 FIFO RTS7, RTS5, RTS1, O Transmit data Data output pins. I Receive data Data input pins. I/O Serial clock Clock input/output pins. O Modem control pins. Transmit request Only RTS1 can be used in the SH7268 Group. CTS7, CTS5, CTS1 I Transmit enable Modem control pins. Only CTS1 can be used in the SH7268 Group. Renesas serial MOSI1, MOSI0 peripheral MISO1, MISO0 interface RSPCK1, RSPCK0 Renesas quad serial peripheral interface Page 26 of 3092 I/O Data Data I/O pins. I/O Data Data I/O pins. I/O Clock Clock I/O pins. SSL00, SSL10 I/O Slave select Slave select I/O pins. QMO_0/QIO0_0, QMO_1/QIO0_1 I/O Data Data I/O pins. QMI_0/QIO1_0, QMI_1/QIO1_1 I/O Data Data I/O pins. QIO2_0, QIO2_1 I/O Data Data I/O pins. QIO3_0, QIO3_1 I/O Data Data I/O pins. QSPCLK_0, QSPCLK_1 O Clock Clock output pins. QSSL_0, QSSL_1 O Slave select Slave select output pins. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function SPI multi I/O bus controller SPBCLK O Clock Clock output pins. SPBSSL O Slave select Slave select output pins. I2C bus interface 3 SPBMO_0/SPBIO0_0, I/O Data SPBMI_0/SPBIO1_0, SPBIO2_0, SPBIO3_0 Data I/O pins. SPBMO_1/SPBIO0_1, I/O Data SPBMI_1/SPBIO1_1, SPBIO2_1, SPBIO3_1 Data I/O pins. SCL3 to SCL0 Serial clock I/O pins. I/O Serial clock pin Only SCL1 and SCL0 can be used in the SH7268 Group. SDA3 to SDA0 I/O Serial data pin Serial data I/O pins. Only SDA1 and SDA0 can be used in the SH7268 Group. Serial sound interface SSITxD0 O Data output Serial data output pin. SSIRxD0 I Data input Serial data input pin. SSIDATA5 to SSIDATA1 I/O Data I/O Serial data I/O pins. Only SSIDATA3 to SSIDATA1 can be used in the SH7268 Group. SSISCK5 to SSISCK0 I/O SSI clock I/O I/O pins for serial clocks. Only SSISCK3 to SSISCK0 can be used in the SH7268 Group. SSIWS5 to SSIWS0 I/O SSI clock LR I/O I/O pins for word selection. Only SSIWS3 to SSIWS0 can be used in the SH7268 Group. Clocked synchronous serial I/O with FIFO SIOFTxD O Data output Data output pin. SIOFRxD I Data input Data input pin. SIOFSCK I/O I/O clock Clock I/O pin. SIOFSYNC I/O I/O chip select I/O pin for chip selection. O CAN bus transmit data Output pins for transmit data on the CAN bus. I CAN bus receive data Output pins for receive data on the CAN bus. Controller area CTx2 to CTx0 network CRx2 to CRx0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 27 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol TM IEBus controller Renesas SPDIF interface NAND flash memory controller USB 2.0 host/function module I/O Name TM Function IETxD O IEBus controller transmit data Output pin for transmit data on IEBusTM controller. IERxD I IEBusTM controller receive data Input pin for receive data on IEBusTM controller. SPDIF_OUT O Output data Transmit data output pin. SPDIF_IN I Input data Receive data input pin. FALE O Flash memory address latch enable Asserted for address output and negated for data I/O. FRE O Flash memory read Reads data at falling edge. enable FCE O Flash memory chip Enables the flash memory enable connected to this LSI. FCLE O Flash memory command latch enable Asserted at command output. FRB I Flash memory ready/busy High level indicates ready state and low level indicates busy state. FWE O Flash memory write Flash memory latches enable commands, addresses, and data at falling edge. NAF7 to NAF0 I/O Flash memory data Data I/O pins. DP I/O USB 2.0 host/function module D+ data D+ data pin for USB 2.0 host/function module bus. DM I/O USB 2.0 host/function module D– data D– data pin for USB 2.0 host/function module bus. VBUS I VBUS input Connected to Vbus on USB 2.0 host/function module bus. REFRIN I Reference input Connected to USBAPVss via 5.6-k  1% resistance (SH7268 and SH7269 products in QFP packages). Connected to Vss via 5.6-k  1% resistance (SH7269 products in BGA packages). Page 28 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function USB 2.0 host/function module USB_X1 I USB_X2 O Crystal resonator/ external clock for USB 2.0 host/function module Connected to a crystal resonator for USB 2.0 host/function module. An external clock signal may also be input to the USB_X1 pin. USBAPVcc I Power supply for transceiver analog pins Power supply for pins. USBAPVss I Ground for transceiver analog pins Ground for pins. I Power supply for transceiver digital pins Power supply for pins. I Ground for transceiver digital pins Ground for pins. USBAVcc I Power supply for transceiver analog core Power supply for core. USBAVss I Ground for transceiver analog core Ground for core. I Power supply for transceiver digital core Power supply for core. Note: SH7269 (BGA) Group products do not have this pin. USBDPVcc Note: SH7269 (BGA) Group products do not have this pin. USBDPVss Note: SH7269 (BGA) Group products do not have this pin. Note: SH7269 (BGA) Group products do not have this pin. USBDVcc Note: SH7269 (BGA) Group products do not have this pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 29 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function USB 2.0 host/function module I Ground for transceiver digital core Ground for core. I 480-MHz power supply for USB 2.0 host/function module Power supply for 480-MHz sections I 480-MHz ground for Ground for 480-MHz sections USB 2.0 host/function module VIN1, VIN2 I Composite video Composite video signal (CVBS) signal (CVBS) input input pins. VIDEO_X1 I VIDEO_X2 O Crystal resonator/ external clock for digital video decoder Connected to a crystal resonator for digital video decoder. An external clock signal may also be input to the VIDEO_X1 pin. VRT O TOP reference voltage TOP reference voltage pin for the A/D converter to input video signals. USBDVss Note: SH7269 (BGA) Group products do not have this pin. USBUVcc Note: SH7269 (BGA) Group products do not have this pin. USBUVss Note: SH7269 (BGA) Group products do not have this pin. Digital video decoder Connected to VDAVss via 0.1-F capacitor. VRB O BOTTOM reference BOTTOM reference voltage pin voltage for the A/D converter to input video signals. Connected to VDAVss via 0.1-F capacitor. BIAS I Reference voltage Reference voltage pin for the A/D converter to input video signals. Connected to VDAVss via 24-k  1% resistance. Page 30 of 3092 VDAVcc I Analog power supply Power supply pin for the A/D converter to input video signals. VDAVss I Analog ground Ground pin for the A/D converter to input video signals. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function Video display controller 4 LCD_DATA23 to LCD_DATA0 O Output data Data output pins for panel. LCD_TCON6 to LCD_TCON0 O Panel timing adjustment output Output pins for panel timing adjustment LCD_CLK O Panel clock Panel clock output pin. LCD_EXTCLK I Panel clock source Panel clock source input pin. DV_DATA23 to DV_DATA0 I Input data Data input pins for graphics data. DV_VSYNC I VSYNC input VSYNC input pin. DV_HSYNC I HSYNC input HSYNC input pin. DV_CLK I Input clock Clock input signal pin for graphics data. Only DV_DATA_7 to DV_DATA0 can be used in the SH7268 Group. Sound generator SGOUT3 to SGOUT0 O Sound generator output Sound generator output pins. SD host interface SD_CLK_0, SD_CLK_1 O SD clock Output pins for SD clock. SD_CMD_0, SD_CMD_1 I/O SD command Only SD_CLK_0 can be used in the SH7268 Group. SD command output and response input signals. Only SD_CMD_0 can be used in the SH7268 Group. SD_D3_0 to SD_D0_0 I/O SD data SD data bus signals. Only SD_D3_0 to SD_D0_0 can be used in the SH7268 Group. SD_D3_1 to SD_D0_1 SD_CD_0, SD_CD_1 I SD card detection SD card detection. Only SD_CD_0 can be used in the SH7268 Group. SD_WP_0, SD_WP_1 I SD write protection SD write protection signals. Only SD_WP_0 can be used in the SH7268 Group. MMC host interface MMC_CLK O MMC clock Output pin for MMC clock. MMC_CMD I/O MMC command MMC command output and response input signal. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 31 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function MMC host interface MMC_D7 to MMC_D0 I/O MMC data MMC data bus signals. MMC_CD I MMC card detection MMC card detection. Motor control PWM timer PWM1H to PWM1A O Timer output PWM output pins. A/D converter AN7 to AN0 I Analog input pins Analog input pins. PWM2H to PWM2A Only AN5 to AN0 can be used in the SH7268 Group. A/D converter General I/O ports ADTRG I A/D conversion trigger input External trigger input pin for starting A/D conversion. AVcc I Analog power supply Power supply pin for A/D converter. AVss I Analog ground Ground pin for A/D converter. AVref I Analog reference voltage Reference voltage pin for A/D converter. PA1, PA0, I/O General port PB22 to PB1, PC8 to PC0, PD15 to PD0, PF23 to PF0, PG27 to PG0, PJ31 to PJ0 101 general I/O port pins in the SH7268 Group. PE7 to PE0 8 input port pins with open-drain output. I/O General port 133 general I/O port pins in the SH7269 Group. Only PA1, PA0, PB22 to PB1, PC8 to PC0, PD15 to PD0, PF23 to PF0, and PG27 to PG0 can be used in the SH7268 Group. Only PE3 to PE0 can be used in the SH7268 Group. PH7 to PH0 I General port 8 general input port pins. Only PH5 to PH0 can be used in the SH7268 Group. User debugging interface Page 32 of 3092 TCK I Test clock Test-clock input pin. TMS I Test mode select Test-mode select signal input pin. TDI I Test data input Serial input pin for instructions and data. TDO O Test data output Serial output pin for instructions and data. TRST I Test reset Initialization-signal input pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Classification Symbol I/O Name Function Emulator interface AUDATA3 to AUDATA0 O Data Branch source or destination address output pins. AUDCK O Clock Sync-clock output pin. AUDSYNC O Sync signal Data start-position acknowledgesignal output pin. ASEBRKAK O Break mode acknowledge Indicates that the E10A-USB emulator has entered its break mode. ASEBRK I Break request E10A-USB emulator break input pin. UBCTRG O User break trigger output User break condition match trigger output pin. User break controller R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 33 of 3092 SH7268 Group, SH7269 Group Section 1 Overview 1.6 List of Pins Table 1.4 List of Pins Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 1 1 C1 PC1 I(s)/O RD O     2 2  PVcc 3 3 E2 PC2 I(s)/O RD/WR O SCK6 I(s)/O   4 4 E3 PC3 I(s)/O WE0/DQMLL O RxD6 I(s)   5 5 F4 PC4 I(s)/O WE1/WE/DQMLU O TxD6 O   6 6 D1 PC5 I(s)/O RAS O   CRx0 I(s) 7 7  PVcc 8 8 F2 PC6 I(s)/O CAS O SCK7 I(s)/O CTx0 O 9 9  Vss 10 10 F3 PC7 I(s)/O CKE O RxD7 I(s) CRx1 I(s) 11 11  Vcc 12 12 E1 PC8 I(s)/O CS3 O TxD7 O CTx1 O 13 13 G4 PB1 I(s)/O A1 O TIOC0A I(s)/O   14 14 G2 PB2 I(s)/O A2 O TIOC0B I(s)/O   15 15 G3 PB3 I(s)/O A3 O TIOC0C I(s)/O   Function 5 Function 6 Function 7 SH7268 Pin No. SH7269 SH7269 BGA Pin No. Pin No. Symbol I/O Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 1 1       (7) C1 2 2  3 3 E2       (7) 4 4 E3       (7) 5 5 F4       (7) 6 6 D1 CRx0/CRx1/CRx2 I(s) IRQ0 I(s)   (7) 7 7  8 8 F2 CTx0&CTx1&CTx2 O     (7) 9 9  10 10 F3 CRx0/CRx1 I(s) IRQ1 I(s)   (7) 11 11  12 12 E1 CTx0&CTx1 O     (7) 13 13 G4       (7) 14 14 G2       (7) 15 15 G3       (7) Page 34 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O  16 F1 PJ14 I(s)/O DV_DATA14 I(s) LCD_DATA14 O PINT6 I(s)  17  PVcc  18 H2 PJ15 I(s)/O DV_DATA15 I(s) LCD_DATA15 O PINT7 I(s) I(s)/O A4 O TIOC0D I(s)/O   LCD_DATA16 O RSPCK0 I(s)/O 16 19  Vss 17 20 H3 PB4 18 21  Vcc  22 G1 PJ16 I(s)/O DV_DATA16 I(s)  23 J3 PJ17 I(s)/O DV_DATA17 I(s) LCD_DATA17 O SSL00 I(s)/O  24 J2 PJ18 I(s)/O DV_DATA18 I(s) LCD_DATA18 O MOSI0 I(s)/O 19 25 H1 PB5 I(s)/O A5 O TIOC1A I(s)/O   20 26 K2 PB6 I(s)/O A6 O TIOC1B I(s)/O   I(s)/O A7 O TIOC2A I(s)/O   I(s)/O A8 O TIOC2B I(s)/O   21 27  PVcc 22 28 J1 PB7 23 29  Vss 24 30 K3 PB8 Function 5 Function 6 Function 7 SH7268 Pin No. SH7269 SH7269 BGA Pin No. Pin No. Symbol I/O Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3  16 F1 PWM2G O TxD6 O   (7)  17   18 H2 PWM2H O TxD7 O   (7) 16 19  17 20 H3       (7) 18 21   22 G1 TIOC0A I(s)/O SIOFSCK I(s)/O   (7)  23 J3 TIOC0B I(s)/O SIOFSYNC I(s)/O   (7)  24 J2 TIOC0C I(s)/O SIOFTxD O   (7) 19 25 H1       (7) 20 26 K2       (7)       (7)       (7) 21 27  22 28 J1 23 29  24 30 K3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 35 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 25 31  Vcc 26 32 K1 27 33 L1 Function 2 Function 3 I/O Symbol I/O PB9 I(s)/O A9 O PB10 I(s)/O A10 O Symbol Function 4 I/O Symbol I/O TIOC3A I(s)/O   TIOC3B I(s)/O   28 34 L2 PB11 I(s)/O A11 O TIOC3C I(s)/O   29 35 M1 PB12 I(s)/O A12 O TIOC3D I(s)/O    36 L3 PJ19 I(s)/O DV_DATA19 I(s) LCD_DATA19 O MISO0 I(s)/O  37  PVcc  38 M2 PJ20 I(s)/O DV_DATA20 I(s) LCD_DATA20 O LCD_TCON3 O 30 39  Vss 31 40 N1 PB13 I(s)/O A13 O QIO2_1 I(s)/O   32 41  Vcc  42 N2 PJ21 I(s)/O DV_DATA21 I(s) LCD_DATA21 O LCD_TCON4 O  43 M3 PJ22 I(s)/O DV_DATA22 I(s) LCD_DATA22 O LCD_TCON5 O  44 P1 PJ23 I(s)/O DV_DATA23 I(s) LCD_DATA23 O LCD_TCON6 O 33 45 P2 PB14 I(s)/O A14 O QIO3_1 I(s)/O   SH7268 Pin No. SH7269 SH7269 BGA Pin No. Pin No. 25 31  26 32 27 33 28 29 Function 5 Function 6 Function 7 Symbol I/O Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 K1       (7) L1       (7) 34 L2       (7) 35 M1       (7)  36 L3 TIOC0D I(s)/O SIOFRxD I(s) AUDIO_XOUT O (7)  37  IRQ0 I(s) CRx2 I(s) CRx0/CRx1/CRx2 I(s) (7)     SPBIO2_1 (7)  38 M2 30 39  31 40 N1 32 41   42 N2 IRQ1 I(s) CTx2 O CTx0&CTx1&CTx2 O (7)  43 M3 IRQ2 I(s) CRx1 I(s) CRx0/CRx1 I(s) (7)  44 P1 IRQ3 I(s) CTx1 O CTx0&CTx1 O (7) 33 45 P2     SPBIO3_1 I(s)/O (7) Page 36 of 3092 I(s)/O R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 34 46 R1 PB15 I(s)/O A15 O QIO2_0 I(s)/O   I(s)/O A16 O QIO3_0 I(s)/O   I(s)/O A17 O QSPCLK_0 O RSPCK0 I(s)/O O SSL00 I(s)/O 35 47  PVcc 36 48 R2 PB16 37 49  Vss 38 50 T1 PB17 39 51  Vcc 40 52 P3 PB18 I(s)/O A18 O QSSL_0 41 53 P4 PB19 I(s)/O A19 O QMO_0/QIO0_0 I(s)/O MOSI0 I(s)/O 42 54 T2 PB20 I(s)/O A20 O QMI_0/QIO1_0 I(s)/O MISO0 I(s)/O I(s)/O A21 O CRx2 I(s) IERxD I(s) 43 55  Vss 44 56 R3 PB21 45 57  Vcc 46 58 U2 PB22 I(s)/O A22 O CTx2 O IETxD O 47 59 T3 PC0 I(s)/O CS0 O MD_BOOT2 I(s)   48 60  PVcc Function 5 Function 6 Function 7 SH7268 Pin No. SH7269 SH7269 BGA Pin No. Pin No. Symbol I/O Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 34 46 R1     SPBIO2_0 I(s)/O (7) 35 47  36 48 R2     SPBIO3_0 I(s)/O (7)     SPBCLK O (7) O (7) 37 49  38 50 T1 39 51  40 52 P3     SPBSSL 41 53 P4     SPBMO_0/SPBIO0_0 I(s)/O (7) 42 54 T2     SPBMI_0/SPBIO1_0 I(s)/O (7) 43 55  44 56 R3       (7) 45 57  46 58 U2 CS4 O     (7) 47 59 T3       (7) 48 60  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 37 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 49 61 V1 CKIO O       I(s)/O MD_BOOT0 I(s)     I(s)/O MD_BOOT1 I(s)     50 62  Vss 51 63 R4 PA0 52 64  Vcc 53 65 U5 PA1  66 Y2 PJ28 I(s)/O   SSISCK5 I(s)/O    67 W3 PJ29 I(s)/O   SSIWS5 I(s)/O    68 V4 PJ30 I(s)/O   SSIDATA5 I(s)/O    69 Y3 PJ31 I(s)/O DV_CLK I(s)     54 70 W4 PE0 I(s)/O(o) SCL0 I(s)/O(o) TCLKA I(s) LCD_EXTCLK I(s) 55 71 V6 PE1 I(s)/O(o) SDA0 I(s)/O(o) TCLKB I(s) AUDIO_CLK I(s) 56 72 Y4 PE2 I(s)/O(o) SCL1 I(s)/O(o) TCLKC I(s) IOIS16 I(s) 57 73 V5 PE3 I(s)/O(o) SDA1 I(s)/O(o) TCLKD I(s) ADTRG I(s)  74 V7 PE4 I(s)/O(o) SCL2 I(s)/O(o) RxD4 I(s) DV_VSYNC I(s)  75 W5 PE5 I(s)/O(o) SDA2 I(s)/O(o) RxD5 I(s) DV_HSYNC I(s) Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3       (5)       (7) U5       (7) 66 Y2 TIOC1B I(s)/O RTS7 I(s)/O   (7) 67 W3 TIOC2A I(s)/O IERxD I(s)   (7)  68 V4 TIOC2B I(s)/O IETxD O   (7)  69 Y3       (7) 49 61 V1 50 62  51 63 R4 52 64  53 65   54 70 W4       (9) 55 71 V6 DV_CLK I(s)     (9) 56 72 Y4 DV_VSYNC I(s)     (9) 57 73 V5 DV_HSYNC I(s)     (9)  74 V7       (9)  75 W5       (9) Page 38 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O  76 W7 PE6 I(s)/O(o) SCL3 I(s)/O(o) RxD6 I(s)    77 U7 PE7 I(s)/O(o) SDA3 I(s)/O(o) RxD7 I(s)   58 78  PVcc 59 79 V8 NMI I(s)       60 80  Vss 61 81 W6 ASEMD I(s)       62 82  Vcc 63 83 U6 PLLVcc 64 84 Y5 EXTAL I       65 85 Y6 XTAL O       66 86  PLLVss 67 87  PLLVss 68 88 W9 RES I(s)        89 W8 RTC_X1 I        90 Y8 RTC_X2 O       Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O  76 Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 W7       (9)       (9)       (3)       (1) (10)  77 U7 58 78  59 79 V8 60 80  61 81 W6 62 82  63 83 U6 64 84 Y5       65 85 Y6       66 86  67 87  68 88 W9       (1)  89 W8       (11)  90 Y8       R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 39 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 69 91  USBDPVcc Function 2 Function 3 Function 4 I/O Symbol I/O Symbol I/O Symbol I/O 70 92  USBDPVss 71 93 Y9 DM I/O       72 94 Y10 DP I/O       73 95 W10 VBUS I       74 96  USBDVcc 75 97  USBDVss 76 98 U11 REFRIN I       77 99  USBAPVss 78 100 V11 USBAPVcc 79 101 V12 USBAVcc 80 102  USBAVss 81 103  USBUVcc 82 104  USBUVss 83 105 Y12 USB_X1 I       84 106 W12 USB_X2 O       Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O 69 91 Function 6 Function 7 Symbol I/O Symbol I/O  70 92  71 93 Y9       72 94 Y10       73 95 W10       74 96  75 97  76 98 U11       77 99  78 100 V11 79 101 V12 80 102  81 103  82 104  83 105 Y12       84 106 W12       Page 40 of 3092 Simplified Circuit Diagram Figure 1.3 (10) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 85 107  PVcc 86 108 Y14 87 109 W14 Function 2 Function 3 Function 4 I/O Symbol I/O Symbol I/O Symbol I/O VIDEO_X1 I       VIDEO_X2 O       I(a)       88 110  Vss 89 111 U13 VDAVcc 90 112 U15 VDAVss 91 113 Y15 VIN1 92 114 Y16 VIN2 I(a)       93 115 W15 VRT O       94 116 W13 VRB O       95 117 W16 BIAS I       96 118 V14 PH0 I(s) AN0 I(a) PINT0 I(s)   97 119 V15 PH1 I(s) AN1 I(a) PINT1 I(s)   98 120 Y17 PH2 I(s) AN2 I(a) PINT2 I(s)   Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 (10) 85 107  86 108 Y14       87 109 W14       88 110  89 111 U13 90 112 U15 91 113 Y15       92 114 Y16       93 115 W15       94 116 W13       95 117 W16       96 118 V14       (4) 97 119 V15       (4) 98 120 Y17       (4) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 41 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 99 121 V17 PH3 I(s) AN3 I(a) PINT3 I(s)   100 122 V16 PH4 I(s) AN4 I(a) PINT4 I(s)   101 123 W17 PH5 I(s) AN5 I(a) PINT5 I(s) LCD_EXTCLK I(s) 102 124 W18 AVss  125 U14 PH6 I(s) AN6 I(a) PINT6 I(s)   103 126 Y18 AVcc  127 U16 PH7 I(s) AN7 I(a) PINT7 I(s)   104 128 Y19 AVref 105 129 V20 TRST I(s)       106 130 U19 ASEBRKAK/ASEBRK I(s)/O       107 131 U20 TDO       O 108 132 T18 TDI I       109 133 R17 TMS I       110 134 T19 TCK I       111 135  Vss Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 99 121 V17       (4) 100 122 V16       (4) 101 123 W17       (4) 102 124 W18  125 U14       (4) 103 126 Y18  127 U16       (4) 104 128 Y19 105 129 V20       (3) 106 130 U19       (7) 107 131 U20       (5) 108 132 T18       (2) 109 133 R17       (2) 110 134 T19       (2) 111 135  Page 42 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 112 136 R18 PG0 I(s)/O D16 I/O LCD_DATA0 O IRQ0 I(s) I(s)/O D17 I/O LCD_DATA1 O IRQ1 I(s) I(s)/O D18 I/O LCD_DATA2 O IRQ2 I(s) 113 137  Vcc 114 138 R19 PG1 115 139  Vss 116 140 P18 PG2 117 141  PVcc 118 142 T20 AUDIO_X2 O       119 143 R20 AUDIO_X1 I       120 144  Vss 121 145 P17 PG3 I(s)/O D19 I/O LCD_DATA3 O IRQ3 I(s) 122 146  Vcc 123 147 N18 PG4 I(s)/O D20 I/O LCD_DATA4 O IRQ4 I(s) 124 148 P19 PG5 I(s)/O D21 I/O LCD_DATA5 O IRQ5 I(s) 125 149 P20 PG6 I(s)/O D22 I/O LCD_DATA6 O IRQ6 I(s) 126 150 M18 PG7 I(s)/O D23 I/O LCD_DATA7 O IRQ7 I(s) Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O 112 136 R18 113 137  114 138 R19 115 139  116 140 P18 Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 TIOC0A I(s)/O     (8) TIOC0B I(s)/O     (8) TIOC0C I(s)/O     (8) (10) 117 141  118 142 T20       119 143 R20       120 144  121 145 P17 TIOC0D I(s)/O     (8) 122 146  123 147 N18 TIOC1A I(s)/O     (8) 124 148 P19 TIOC1B I(s)/O     (8) 125 149 P20 TIOC2A I(s)/O     (8) 126 150 M18 TIOC2B I(s)/O     (8) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 43 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O  151 N19 PJ0 I(s)/O DV_DATA0 I(s) LCD_DATA0 O SD_CD_1 I(s)  152  PVcc  153 N20 PJ1 I(s)/O DV_DATA1 I(s) LCD_DATA1 O SD_WP_1 I(s) I(s)/O D24 I/O LCD_DATA8 O PINT0 I(s) I(s)/O DV_DATA2 I(s) LCD_DATA2 O SD_D1_1 I(s)/O 127 154  Vss 128 155 L18 PG8 129 156  Vcc  157 M19 PJ2  158 M20 PJ3 I(s)/O DV_DATA3 I(s) LCD_DATA3 O SD_D0_1 I(s)/O  159 L20 PJ4 I(s)/O DV_DATA4 I(s) LCD_DATA4 O SD_CLK_1 O 130 160 L19 PG9 I(s)/O D25 I/O LCD_DATA9 O PINT1 I(s) 131 161 K20 PG10 I(s)/O D26 I/O LCD_DATA10 O PINT2 I(s) I(s)/O D27 I/O LCD_DATA11 O PINT3 I(s) I(s)/O D28 I/O LCD_DATA12 O PINT4 I(s) 132 162  PVcc 133 163 K18 PG11 134 164  Vss 135 165 K19 PG12 Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O  151  152   153 N20 N19 Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 PWM1A O     (7) PWM1B O     (7) TIOC3A I(s)/O     (8) PWM1C O     (7) 127 154  128 155 L18 129 156   157 M19  158 M20 PWM1D O     (7)  159 L20 PWM1E O     (7) 130 160 L19 TIOC3B I(s)/O     (8) 131 161 K20 TIOC3C I(s)/O     (8) TIOC3D I(s)/O     (8)       (8) 132 162  133 163 K18 134 164  135 165 K19 Page 44 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 136 166  Vcc 137 167 J20 138 168 J19 139 169 140 170   Function 2 Function 3 Function 4 I/O Symbol I/O Symbol I/O Symbol I/O PG13 I(s)/O D29 I/O LCD_DATA13 O PINT5 I(s) PG14 I(s)/O D30 I/O LCD_DATA14 O PINT6 I(s) H20 PG15 I(s)/O D31 I/O LCD_DATA15 O PINT7 I(s) H19 PG16 I(s)/O WE2/ICIORD/DQMUL O LCD_DATA16 O   171 G20 PJ5 I(s)/O DV_DATA5 I(s) LCD_DATA5 O SD_CMD_1 I(s)/O 172  PVcc  173 H18 PJ6 I(s)/O DV_DATA6 I(s) LCD_DATA6 O SD_D3_1 I(s)/O 141 174  Vss 142 175 H17 PG17 I(s)/O WE3/ICIOWR/AH/DQMUU O LCD_DATA17 O   143 176  Vcc  177 G17 PJ7 I(s)/O DV_DATA7 I(s) LCD_DATA7 O SD_D2_1 I(s)/O  178 G19 PJ8 I(s)/O DV_DATA8 I(s) LCD_DATA8 O PINT0 I(s)  179 F20 PJ9 I(s)/O DV_DATA9 I(s) LCD_DATA9 O PINT1 I(s) 144 180 G18 PG18 I(s)/O DV_DATA4 I(s) LCD_DATA18 O SPDIF_IN I(s) Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3      (8)      (8)       (8)     AUDATA0 O (7) PWM1F O     (7) PWM1G O     (7)     AUDATA1 O (7) G17 PWM1H O     (7) G19 PWM2A O CTS5 I(s)/O   (7) 136 166  137 167 J20  138 168 J19  139 169 H20 140 170 H19  171 G20  172   173 H18 141 174  142 175 H17 143 176   177  178  179 F20 PWM2B O RTS5 I(s)/O   (7) 144 180 G18 SCK4 I(s)/O     (7) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 45 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 145 181 F19 PG19 I(s)/O DV_DATA5 I(s) LCD_DATA19 O SPDIF_OUT O I(s)/O DV_DATA6 I(s) LCD_DATA20 O LCD_TCON3 O I(s)/O DV_DATA7 I(s) LCD_DATA21 O LCD_TCON4 O 146 182  PVcc 147 183 E20 PG20 148 184  Vss 149 185 F17 PG21 150 186  Vcc 151 187 F18 PG22 I(s)/O   LCD_DATA22 O LCD_TCON5 O 152 188 E19 PG23 I(s)/O   LCD_DATA23 O LCD_TCON6 O 153 189 D20 PG24 I(s)/O   LCD_CLK O   154 190 E18 PG25 I(s)/O   LCD_TCON0 O   155 191 C20 PG26 I(s)/O   LCD_TCON1 O   156 192 D19 PG27 I(s)/O   LCD_TCON2 O LCD_EXTCLK I(s) 157 193 A18 PF0 I(s)/O BREQ I(s) QSPCLK_1 O RSPCK1 I(s)/O I(s)/O BACK O QSSL_1 O SSL10 I(s)/O 158 194  PVcc 159 195 C17 PF1 Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O 145 181 F19 146 182  147 183 E20 148 184  149 185 F17 Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 SCK5 I(s)/O     (7) RxD4 I(s)     (7) TxD4 O   AUDATA2 O (7)  AUDSYNC O (7) 150 186  151 187 F18 RxD5 I(s)  152 188 E19 TxD5 O   AUDATA3 O (7) 153 189 D20       (7) 154 190 E18       (7) 155 191 C20       (7) 156 192 D19       (7) 157 193 A18 TIOC4A I(s)/O DREQ0 I(s) AUDCK O (7) TIOC4B I(s)/O DACK0 O   (7) 158 194  159 195 C17 Page 46 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 160 196  Vss Function 2 I/O Symbol I/O Function 3 Function 4 Symbol I/O Symbol I/O 161 197 C15 PF2 I(s)/O WAIT I(s) QMO_1/QIO0_1 I(s)/O MOSI1 I(s)/O 162 198 A17 PF3 I(s)/O CS2 O QMI_1/QIO1_1 I(s)/O MISO1 I(s)/O 163 199 B16 PF4 I(s)/O CS5/CE1A O SSISCK0 I(s)/O   164 200 B17 PF5 I(s)/O   SSIWS0 I(s)/O   165 201 D14 PF6 I(s)/O CE2A O SSITxD0 O   166 202 A16 PF7 I(s)/O   SSIRxD0 I(s)   167 203 C16 PF8 I(s)/O A23 O     168 204 B15 PF9 I(s)/O BS O   DV_DATA0 I(s) I(s)/O CS1 O SSISCK1 I(s)/O DV_DATA1 I(s) I(s)/O   SSIWS1 I(s)/O DV_DATA2 I(s) 169 205  PVcc 170 206 A15 PF10 171 207  Vss 172 208 C14 PF11 173 209 D13 PF12 I(s)/O   SSIDATA1 I(s)/O DV_DATA3 I(s) 174 210 B14 PF13 I(s)/O A24 O SSISCK2 I(s)/O   Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol TEND0 O SPBMO_1/SPBIO0_1 I(s)/O (7) O SPBMI_1/SPBIO1_1 I(s)/O (7) O   (7) O   (7) O   (7) SGOUT_3 O CTS1 I(s)/O (7)     (7) MMC_D4 I(s)/O RTS1 I(s)/O (7) I(s)/O MMC_D5 I(s)/O   (7) 160 196  161 197 C15 TIOC4C I(s)/O 162 198 A17 TIOC4D I(s)/O AUDIO_XOUT 163 199 B16   SGOUT_0 164 200 B17   SGOUT_1 165 201 D14   SGOUT_2 166 202 A16 RxD0 I(s) 167 203 C16 TxD0 O 168 204 B15 SCK0 I(s)/O 169 205  170 206 A15 SCK1 171 207  I/O Simplified Circuit Diagram Figure 1.3 172 208 C14 RxD1 I(s) MMC_D6 I(s)/O   (7) 173 209 D13 TxD1 O MMC_D7 I(s)/O   (7) 174 210 B14 SCK2 I(s)/O     (7) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 47 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 175 211 A14 PF14 I(s)/O A25 O SSIWS2 I(s)/O   176 212 B13 PF15 I(s)/O A0 O SSIDATA2 I(s)/O WDTOVF O  213  PVcc  214 C13 PJ10 I(s)/O DV_DATA10 I(s) LCD_DATA10 O PINT2 I(s)  215  Vss 177 216 A13 PF16 I(s)/O SD_CD_0 I(s)   FCE O 178 217 A12 PF17 I(s)/O SD_WP_0 I(s)   FRB I(s) 179 218 B12 PF18 I(s)/O SD_D1_0 I(s)/O SSISCK3 I(s)/O    219 C11 PJ11 I(s)/O DV_DATA11 I(s) LCD_DATA11 O PINT3 I(s)  220 A11 PJ12 I(s)/O DV_DATA12 I(s) LCD_DATA12 O PINT4 I(s)  221 B11 PJ13 I(s)/O DV_DATA13 I(s) LCD_DATA13 O PINT5 I(s) I(s)/O SD_D0_0 I(s)/O SSIWS3 I(s)/O   I(s)/O SD_CLK_0 O SSIDATA3 I(s)/O   180 222  PVcc 181 223 C12 PF19 182 224  Vss 183 225 A10 PF20 Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 175 211 A14 RxD2 I(s)     (7) 176 212 B13 TxD2 O UBCTRG O   (7)  213   214 C13 PWM2C O SCK5 I(s)/O   (7)  215  177 216 A13 IRQ4 I(s) MMC_CD I(s)   (7) 178 217 A12 IRQ5 I(s)     (7) 179 218 B12 IRQ6 I(s) MMC_D1 I(s)/O   (7)  219 C11 PWM2D O SCK6 I(s)/O   (7)  220 A11 PWM2E O SCK7 I(s)/O   (7)  221 B11 PWM2F O TxD5 O   (7) 180 222  181 223 C12 IRQ7 I(s) MMC_D0 I(s)/O   (7) 182 224  183 225 A10   MMC_CLK O   (7) Page 48 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 184 226  Vcc Function 2 I/O Symbol Function 3 Function 4 I/O Symbol I/O Symbol I/O 185 227 B10 PF21 I(s)/O SD_CMD_0 I(s)/O     186 228 A9 PF22 I(s)/O SD_D3_0 I(s)/O     187 229 D9 PF23 I(s)/O SD_D2_0 I(s)/O     188 230 B9 PD0 I/O D0 I/O   PWM1A O  231  PVcc  232 A8 PJ24 I(s)/O SGOUT_0 O SSISCK4 I(s)/O LCD_TCON3 O  233  Vss 189 234 C9 PD1 I/O D1 I/O   PWM1B O 190 235 B8 PD2 I/O D2 I/O   PWM1C O 191 236 A7 PD3 I/O D3 I/O   PWM1D O  237 B7 PJ25 I(s)/O SGOUT_1 O SSIWS4 I(s)/O LCD_TCON4 O  238 C8 PJ26 I(s)/O SGOUT_2 O SSIDATA4 I(s)/O LCD_TCON5 O  239 A6 PJ27 I(s)/O SGOUT_3 O     192 240  PVcc Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 O MMC_CMD I(s)/O   (7) RxD3 I(s) MMC_D3 I(s)/O   (7) TxD3 I(s)/O MMC_D2 I(s)/O   (7)       (6) SPDIF_IN I(s) SCK7 I(s)/O   (7) 184 226  185 227 B10 SCK3 186 228 A9 187 229 D9 188 230 B9  231   232 A8  233  189 234 C9       (6) 190 235 B8       (6) 191 236 A7       (6)  237 B7 SPDIF_OUT O RxD7 I(s)   (7)  238 C8   TxD7 O   (7)  239 A6 TIOC1A I(s)/O CTS7 I(s)/O   (7) 192 240  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 49 of 3092 SH7268 Group, SH7269 Group Section 1 Overview Function 1 SH7268 Pin No. SH7269 Pin No. SH7269 BGA Pin No. Symbol 193 241  Vss Function 2 I/O Symbol Function 3 I/O Symbol Function 4 I/O Symbol I/O 194 242 B6 PD4 I/O D4 I/O FRE O PWM1E O 195 243 D8 PD5 I/O D5 I/O FCLE O PWM1F O 196 244 C7 PD6 I/O D6 I/O FALE O PWM1G O 197 245 A5 PD7 I/O D7 I/O FWE O PWM1H O 198 246 B5 PD8 I/O D8 I/O NAF0 I/O PWM2A O 199 247 C5 PD9 I/O D9 I/O NAF1 I/O PWM2B O 200 248 D7 PD10 I/O D10 I/O NAF2 I/O PWM2C O 201 249 A4 PD11 I/O D11 I/O NAF3 I/O PWM2D O I/O D12 I/O NAF4 I/O PWM2E O I/O D13 I/O NAF5 I/O PWM2F O 202 250  PVcc 203 251 C6 PD12 204 252  Vss 205 253 C4 PD13 206 254 B4 PD14 I/O D14 I/O NAF6 I/O PWM2G O 207 255 A3 PD15 I/O D15 I/O NAF7 I/O PWM2H O 208 256 B3 MD_CLK0 I(s)       Function 5 SH7269 SH7268 SH7269 BGA Pin No. Pin No. Pin No. Symbol I/O Function 6 Function 7 Symbol I/O Symbol I/O Simplified Circuit Diagram Figure 1.3 193 241  194 242 B6       (6) 195 243 D8       (6) 196 244 C7       (6) 197 245 A5       (6) 198 246 B5       (6) 199 247 C5       (6) 200 248 D7       (6) 201 249 A4       (6) 202 250  203 251 C6       (6) 204 252  205 253 C4       (6) 206 254 B4       (6) 207 255 A3       (6) 208 256 B3       (1) Page 50 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview [Legend] (s): Schmitt (a): Analog (o): Open drain Note: Pins to which the PVcc, Vcc, and Vss functions can be allocated on SH7269 (BGA) Group products are listed below. PVcc: A19, B1, B18, C2, D2, D3, D11, D12, D15, D16, E4, J17, J18, N3, N4, T17, U18, V19, W20, Y11 Vcc: A2, B20, C19, D5, D6, D18, E17, H4, J4, M17, N17, T4, U3, U10, V2, V10, W1 Vss: A1, A20, B2, B19, C3, C10, C18, D4, D10, D17, J9, J10, J11, J12, K4, K9, K10, K11, K12, K17, L4, L9, L10, L11, L12, L17, M4, M9, M10, M11, M12, U1, U4, U8, U9, U12, U17, V3, V9, V13, V18, W2, W11, W19, Y1, Y7, Y13, Y20 PAD Schmitt input data Figure 1.3 (1) Simplified Circuit Diagram (Schmitt Input Buffer) PAD TTL input data TTL input enable Figure 1.3 (2) Simplified Circuit Diagram (TTL AND Input Buffer) PAD Schmitt input data Schmitt input enable Figure 1.3 (3) Simplified Circuit Diagram (Schmitt AND Input Buffer) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 51 of 3092 SH7268 Group, SH7269 Group Section 1 Overview A/D analog input enable PAD A/D analog input data Schmitt input data Schmitt input enable Figure 1.3 (4) Simplified Circuit Diagram (Schmitt OR Input and A/D Input Buffer) Latch enable Output enable PAD Output data Figure 1.3 (5) Simplified Circuit Diagram (Output Buffer with Enable, with Latch) Latch enable Output enable PAD Output data TTL input data TTL input enable Figure 1.3 (6) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, with Latch) Page 52 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview Latch enable Output enable PAD Output data Schmitt input data Schmitt input enable Figure 1.3 (7) Simplified Circuit Diagram (Bidirectional Buffer, Schmitt AND Input, with Latch) Latch enable Output enable PAD Output data TTL input data TTL input enable Schmitt input data Schmitt input enable Figure 1.3 (8) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, Schmitt AND Input, with Latch) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 53 of 3092 SH7268 Group, SH7269 Group Section 1 Overview PAD Output data Schmitt input data Schmitt input enable Figure 1.3 (9) Simplified Circuit Diagram (Open Drain Output and Schmitt OR Input Buffer) Input clock XOUT (XTAL, AUDIO_X2, USB_X2) XIN (EXTAL, AUDIO_X1, USB_X1) Input enable Figure 1.3 (10) Simplified Circuit Diagram (Oscillation Buffer 1) Page 54 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 1 Overview XOUT (RTC_X2) Input clock XIN (RTC_X1) Input enable Figure 1.3 (11) Simplified Circuit Diagram (Oscillation Buffer 2) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 55 of 3092 Section 1 Overview Page 56 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and restoring the status register (SR) and program counter (PC) in exception handling is accomplished by referencing the stack using R15. 31 0 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 57 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area. 31 14 13 9 8 7 6 5 4 3 2 1 0 BO CS M Q I[3:0] S T 31 Status register (SR) 0 GBR Global base register (GBR) 31 0 VBR Vector base register (VBR) 0 31 TBR Jump table base register (TBR) Figure 2.2 Control Registers (1) Status Register (SR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - BO CS - - - M Q - - S T 0 R 0 R/W 0 R/W 0 R 0 R 0 R R/W R/W 0 R 0 R R/W R/W Initial value: R/W: Page 58 of 3092 I[3:0] 1 R/W 1 R/W 1 R/W 1 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name Initial Value 31 to 15  All 0 Section 2 CPU R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 14 BO 0 R/W BO Bit Indicates that a register bank has overflowed. 13 CS 0 R/W CS Bit Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-limit value or fallen below the saturation lower-limit value. 12 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 M  R/W M Bit 8 Q  R/W Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. 7 to 4 I[3:0] 1111 R/W 3, 2  All 0 R Interrupt Mask Level Reserved These bits are always read as 0. The write value should always be 0. 1 S  R/W S Bit Specifies a saturation operation for a MAC instruction. 0 T  R/W T Bit True/false condition or carry/borrow bit (2) Global Base Register (GBR) GBR is referenced as the base address in a GBR-referencing MOV instruction. (3) Vector Base Register (VBR) VBR is referenced as the branch destination base address in the event of an exception or an interrupt. (4) Jump Table Base Register (TBR) TBR is referenced as the start address of a function table located in memory in a JSR/N@@(disp8,TBR) table-referencing subroutine call instruction. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 59 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.1.3 System Registers The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or multiply and accumulate operations. PR stores the return address from a subroutine procedure. PC points four bytes ahead of the current instruction and controls the flow of the processing. 31 0 Multiply and accumulate register high (MACH) and multiply and accumulate register low (MACL): Store the results of multiply or multiply and accumulate operations. 0 Procedure register (PR): Stores the return address from a subroutine procedure. 0 Program counter (PC): Indicates the four bytes ahead of the current instruction. MACH MACL 31 PR 31 PC Figure 2.3 System Registers (1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate Register Low (MACL) MACH and MACL are used as the addition value in a MAC instruction, and store the result of a MAC or MUL instruction. (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC points four bytes ahead of the instruction being executed. Page 60 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.1.4 Section 2 CPU Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 7.8, Register Banks. 2.1.5 Initial Values of Registers Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers Classification General registers Control registers System registers R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Register Initial Value R0 to R14 Undefined R15 (SP) Value of the stack pointer in the vector address table SR Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined GBR, TBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC Value of the program counter in the vector address table Page 61 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 0 Longword Figure 2.4 Data Format in Registers 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in sign-extended or zero-extended form. A word operand should be accessed at a word boundary (an even address of multiple of two bytes: address 2n), and a longword operand at a longword boundary (an even address of multiple of four bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any address. Only big-endian byte order can be selected for the data format. Data formats in memory are shown in figure 2.5. Address m + 1 Address m 31 23 Byte Address 2n Address 4n Address m + 3 Address m + 2 15 Byte 7 Byte Word 0 Byte Word Longword Big endian Figure 2.5 Data Formats in Memory Page 62 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.2.3 Section 2 CPU Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction. The MOVI20 instruction stores immediate data in the destination register in sign-extended form. The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it in the destination register in sign-extended form. Word or longword immediate data is not located in the instruction code, but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. See examples given in section 2.3.1 (10), Immediate Data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 63 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease of use. (3) One Instruction per State Each basic instruction can be executed in one cycle using the pipeline system. (4) Data Length Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data in memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It is also handled as longword data. Table 2.2 Sign Extension of Word Data SH2-A CPU MOV.W ADD .DATA.W Description @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD H'1234 instruction. Example of Other CPU ADD.W #H'1234,R0 Note: @(disp, PC) accesses the immediate data. (5) Load-Store Architecture Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Page 64 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 2 CPU Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. This reduces disturbance of the pipeline control when a branch is taken. In a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution such as register updating excluding the actual branch operation, is performed in the order of delayed branch instruction  delay slot instruction. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.3 Delayed Branch Instructions SH-2A CPU Description Example of Other CPU BRA TRGET R1,R0 R1,R0 Executes the ADD before branching to TRGET. ADD.W ADD BRA TRGET (7) Unconditional Branch Instructions with No Delay Slot The SH-2A additionally features unconditional branch instructions in which a delay slot instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code size. (8) Multiply/Multiply-and-Accumulate Operations 16-bit  16-bit  32-bit multiply operations are executed in one to two cycles. 16-bit  16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit  32-bit 64-bit multiply and 32-bit  32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four cycles. (9) T Bit The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 65 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Table 2.4 T Bit SH-2A CPU Description Example of Other CPU CMP/GE R1,R0 T bit is set when R0  R1. CMP.W R1,R0 BT TRGET0 BGE TRGET0 BF TRGET1 The program branches to TRGET0 when R0  R1 and to TRGET1 when R0 < R1. BLT TRGET1 ADD #1,R0 T bit is not changed by ADD. SUB.W #1,R0 CMP/EQ #0,R0 T bit is set when R0 = 0. BEQ TRGET BT TRGET The program branches if R0 = 0. (10) Immediate Data Byte immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for 21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a register. Table 2.5 Immediate Data Accessing Classification SH-2A CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOVI20 #H'1234,R0 MOV.W #H'1234,R0 20-bit immediate MOVI20 #H'12345,R0 MOV.L #H'12345,R0 28-bit immediate MOVI20S #H'12345,R0 MOV.L #H'1234567,R0 OR #H'67,R0 MOV.L @(disp,PC),R0 MOV.L #H'12345678,R0 32-bit immediate Example of Other CPU ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Page 66 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU (11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in register indirect addressing mode. With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also possible to transfer immediate data located in the instruction code to a register and to reference the data in register indirect addressing mode. However, when referencing data using an absolute address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register. Table 2.6 Absolute Address Accessing Classification SH-2A CPU Up to 20 bits MOVI20 #H'12345,R1 MOV.B @R1,R0 MOVI20S #H'12345,R1 OR #H'67,R1 MOV.B @R1,R0 MOV.L @(disp,PC),R1 MOV.B @R1,R0 .DATA.L H'12345678 21 to 28 bits 29 bits or more Example of Other CPU MOV.B @H'12345,R0 MOV.B @H'1234567,R0 MOV.B @H'12345678,R0 .................. (12) 16-Bit/32-Bit Displacement When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indexed indirect register addressing mode. Table 2.7 Displacement Accessing Classification SH-2A CPU Example of Other CPU 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 MOV.W @(H'1234,R1),R2 .................. .DATA.W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H'1234 Page 67 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Register direct Rn Register indirect @Rn The effective address is register Rn. (The operand is the contents of register Rn.) Rn The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn Rn + 1/2/4 Rn 1/2/4 Page 68 of 3092 (After instruction execution) Byte: Rn + 1  Rn Longword: Rn + 4  Rn The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn – 1/2/4 Rn Word: Rn + 2  Rn + 1/2/4 Register indirect @-Rn with predecrement  The effective address is the contents of register Rn. Rn Rn Register indirect @Rn+ with postincrement Equation – Rn – 1/2/4 Byte: Rn – 1  Rn Word: Rn – 2  Rn Longword: Rn – 4  Rn (Instruction is executed with Rn after this calculation) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Addressing Mode Instruction Format Register indirect @(disp:4, with Rn) displacement Section 2 CPU Effective Address Calculation Equation The effective address is the sum of Rn and a 4-bit displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Byte: Rn + disp Rn disp (zero-extended) Word: Rn + disp  2 Longword: Rn + disp  4 Rn + disp × 1/2/4 + × 1/2/4 Register indirect @(disp:12, The effective address is the sum of Rn and a 12with Rn) bit displacement displacement (disp). The value of disp is zeroextended. Rn + Rn + disp Byte: Rn + disp Word: Rn + disp Longword: Rn + disp disp (zero-extended) Indexed register @(R0,Rn) indirect The effective address is the sum of Rn and R0. Rn + R0 Rn + Rn + R0 R0 GBR indirect with displacement @(disp:8, GBR) The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) + Byte: GBR + disp Word: GBR + disp  2 Longword: GBR + disp  4 GBR + disp × 1/2/4 × 1/2/4 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 69 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Equation Indexed GBR indirect @(R0, GBR) The effective address is the sum of GBR value and R0. GBR + R0 GBR + GBR + R0 R0 TBR duplicate indirect with displacement @@ (disp:8, TBR) The effective address is the sum of TBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and is multiplied by 4. Contents of address (TBR + disp  4) TBR disp (zero-extended) TBR + + disp × 4 × (TBR 4 PC indirect with @(disp:8, displacement PC) + disp × 4) The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. Word: PC + disp  2 Longword: PC & H'FFFFFFFC + disp  4 PC & H'FFFFFFFC (for longword) + disp (zero-extended) PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 × 2/4 Page 70 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation PC relative disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). Equation PC + disp  2 PC disp (sign-extended) + PC + disp × 2 × 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC + disp 2 PC disp (sign-extended) + PC + disp × 2 × 2 Rn The effective address is the sum of PC value and Rn. PC + Rn PC + PC + Rn Rn R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 71 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Immediate #imm:20 Equation The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended.  31 19 0 Signimm (20 bits) extended The 20-bit immediate data (imm) for the MOVI20S  instruction is shifted by eight bits to the left, the upper bits are sign-extended, and the lower bits are padded with zero. 31 27 8 0 imm (20 bits) 00000000 Sign-extended Page 72 of 3092 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended.  #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended.  #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled.  #imm:3 The 3-bit immediate data (imm) for the BAND, BOR,  BXOR, BST, BLD, BSET, and BCLR instructions indicates the target bit location. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.3.3 Section 2 CPU Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows:      xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Table 2.9 Instruction Formats Instruction Formats 0 format 15 Source Operand Destination Operand Example   NOP  nnnn: Register direct MOVT Rn Control register or system register nnnn: Register direct STS MACH,Rn R0 (Register direct) nnnn: Register direct DIVU R0,Rn Control register or system register nnnn: Register indirect with predecrement STC.L SR,@-Rn mmmm: Register direct R15 (Register indirect with predecrement) MOVMU.L Rm,@-R15 R15 (Register indirect with postincrement) nnnn: Register direct MOVMU.L @R15+,Rn 0 xxxx xxxx xxxx xxxx n format 15 xxxx 0 nnnn xxxx xxxx R0 (Register direct) nnnn: (Register indirect with postincrement) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 MOV.L R0,@Rn+ Page 73 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Instruction Formats m format 15 0 xxxx mmmm xxxx xxxx nm format 15 0 xxxx nnnn mmmm xxxx md format 15 0 xxxx xxxx Page 74 of 3092 mmmm dddd Source Operand Destination Operand mmmm: Register direct Control register or system register LDC mmmm: Register indirect with postincrement Control register or system register LDC.L @Rm+,SR mmmm: Register indirect  JMP mmmm: Register indirect with predecrement R0 (Register direct) MOV.L @-Rm,R0 Example Rm,SR @Rm mmmm: PC relative  using Rm BRAF Rm mmmm: Register direct nnnn: Register direct ADD Rm,Rn mmmm: Register direct nnnn: Register indirect MOV.L Rm,@Rn mmmm: Register MACH, MACL indirect with postincrement (multiplyand-accumulate) nnnn*: Register indirect with postincrement (multiplyand-accumulate) MAC.W @Rm+,@Rn+ mmmm: Register indirect with postincrement nnnn: Register direct MOV.L @Rm+,Rn mmmm: Register direct nnnn: Register indirect with predecrement MOV.L Rm,@-Rn mmmm: Register direct nnnn: Indexed register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rm),R0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU Source Operand Instruction Formats nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx nnnn mmmm 32 xxxx nnnn mmmm xxxx 15 xxxx dddd dddd dddd 16 0 d format 15 0 xxxx xxxx dddd R0 (Register direct) nnnndddd: Register indirect with displacement dddd 15 0 xxxx dddd dddd mmmmdddd: Register indirect with displacement nnnn: Register direct mmmm: Register direct nnnndddd: Register MOV.L indirect with Rm,@(disp12,Rn) displacement mmmmdddd: Register indirect with displacement nnnn: Register direct dddddddd: GBR indirect with displacement R0 (Register direct) MOV.L @(disp,GBR),R0 15 0 xxxx nnnn dddd dddd R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 MOV.L @(disp,Rm),Rn MOV.L @(disp12,Rm),Rn MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (Register direct) MOVA @(disp,PC),R0 dddddddd: TBR duplicate indirect with displacement  JSR/N @@(disp8,TBR) dddddddd: PC relative  BF label dddddddddddd: PC  relative BRA label dddddddd: PC relative with displacement MOV.L @(disp,PC),Rn dddd nd8 format MOV.B R0,@(disp,Rn) nnnndddd: Register MOV.L indirect with Rm,@(disp,Rn) displacement R0 (Register direct) dddddddd: GBR indirect with displacement d12 format Example mmmm: Register direct dddd nmd12 format Destination Operand nnnn: Register direct (label = disp + PC) Page 75 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Instruction Formats Source Operand Destination Operand Example i format iiiiiiii: Immediate Indexed GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Register direct) AND #imm,R0 iiiiiiii: Immediate  TRAPA #imm iiiiiiii: Immediate nnnn: Register direct ADD 15 xxxx xxxx iiii 0 iiii ni format 15 #imm,Rn 0 xxxx nnnn iiii iiii ni3 format 15 0 xxxx xxxx nnnn x iii ni20 format 32 xxxx nnnn iiii xxxx 15 iiii iiii iiii iiii 16 nnnn: Register direct  iii: Immediate BLD #imm3,Rn  nnnn: Register direct BST iii: Immediate #imm3,Rn iiiiiiiiiiiiiiiiiiii: Immediate nnnn: Register direct MOVI20 #imm20, Rn 0 nid format 32 xxxx nnnn xiii xxxx 15 xxxx dddd dddd dddd Note: * 16 0 nnnndddddddddddd:  Register indirect with displacement iii: Immediate  BLD.B #imm3,@(disp12,Rn) nnnndddddddddddd: BST.B Register indirect with #imm3,@(disp12,Rn) displacement iii: Immediate In multiply-and-accumulate instructions, nnnn is the source register. Page 76 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU 2.4 Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Classification Types Operation Code Function No. of Instructions Data transfer MOV 62 13 Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Reverse stack transfer MOVA Effective address transfer MOVI20 20-bit immediate data transfer MOVI20S 20-bit immediate data transfer 8-bit left-shit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 MOVML R0–Rn register save/restore MOVMU Rn–R14 and PR register save/restore MOVRT T bit inversion and transfer to Rn MOVT T bit transfer MOVU Unsigned data transfer NOTT T bit inversion PREF Prefetch to operand cache SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected Page 77 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Classification Types Arithmetic operations 26 Operation Code Function No. of Instructions ADD Binary addition 40 ADDC Binary addition with carry ADDV Binary addition with overflow check CMP/cond Comparison Page 78 of 3092 CLIPS Signed saturation value comparison CLIPU Unsigned saturation value comparison DIVS Signed division (32  32) DIVU Unsigned division (32  32) DIV1 One-step division DIV0S Initialization of signed one-step division DIV0U Initialization of unsigned one-step division DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, double-precision multiply-and-accumulate operation MUL Double-precision multiply operation MULR Signed multiplication with result storage in Rn MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Classification Types Logic operations Shift Branch 6 12 10 Section 2 CPU Operation Code Function No. of Instructions AND Logical AND 14 NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set XOR Exclusive OR ROTL One-bit left rotation ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAD Dynamic arithmetic shift SHAL One-bit arithmetic left shift SHAR One-bit arithmetic right shift SHLD Dynamic logical shift SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift SHLRn n-bit logical right shift BF Conditional branch, conditional delayed branch 15 (branch when T = 0) BT Conditional branch, conditional delayed branch (branch when T = 1) BRA Unconditional delayed branch BRAF Unconditional delayed branch BSR Delayed branch to subroutine procedure BSRF Delayed branch to subroutine procedure JMP Unconditional delayed branch JSR Branch to subroutine procedure 16 Delayed branch to subroutine procedure RTS Return from subroutine procedure Delayed return from subroutine procedure RTV/N R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Return from subroutine procedure with Rm  R0 transfer Page 79 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Classification Types System control 14 Operation Code Function No. of Instructions CLRT T bit clear 36 CLRMAC MAC register clear LDBANK Register restoration from specified register bank entry LDC Load to control register LDS Load to system register NOP No operation RESBANK Register restoration from register bank Floating-point 19 instructions Page 80 of 3092 RTE Return from exception handling SETT T bit set SLEEP Transition to power-down mode STBANK Register save to specified register bank entry STC Store control register data STS Store system register data TRAPA Trap exception handling FABS Floating-point absolute value FADD Floating-point addition FCMP Floating-point comparison FCNVDS Conversion from double-precision to singleprecision FCNVSD Conversion from single-precision to double precision FDIV Floating-point division FLDI0 Floating-point load immediate 0 FLDI1 Floating-point load immediate 1 48 FLDS Floating-point load into system register FPUL FLOAT Conversion from integer to floating-point FMAC Floating-point multiply and accumulate operation FMOV Floating-point data transfer FMUL Floating-point multiplication FNEG Floating-point sign inversion R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Classification Types Floating-point 19 instructions FPU-related CPU instructions 2 Bit manipulation 10 Section 2 CPU Operation Code Function No. of Instructions FSCHG SZ bit inversion 48 FSQRT Floating-point square root FSTS Floating-point store from system register FPUL FSUB Floating-point subtraction FTRC Floating-point conversion with rounding to integer LDS Load into floating-point system register STS Store from floating-point system register BAND Bit AND BCLR Bit clear BLD Bit load BOR Bit OR BSET Bit set BST Bit store BXOR Bit exclusive OR 8 14 BANDNOT Bit NOT AND Total: 112 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 BORNOT Bit NOT OR BLDNOT Bit NOT load 253 Page 81 of 3092 SH7268 Group, SH7269 Group Section 2 CPU The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Execution States T Bit Value when no wait states are inserted.*1 Value of T bit after instruction is executed. Instruction Instruction Code Operation Indicated by mnemonic. Indicated in MSB  LSB order. Indicates summary of operation. [Legend] [Legend] [Legend] Explanation of Symbols Rm: Source register mmmm: Source register , : Transfer direction : No change Rn: Destination register nnnn: Destination register 0000: R0 0001: R1 ......... (xx): Memory operand imm: Immediate data disp: Displacement*2 1111: R15 iiii: Immediate data dddd: Displacement M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: Exclusive logical OR of each bit ~: Logical NOT of each bit n: n-bit right shift Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory  register) is the same as the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by 1, 2, or 4. For details, refer to the SH-2A, SH2A-FPU Software Manual. Page 82 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.4.2 Section 2 CPU Data Transfer Instructions Table 2.11 Data Transfer Instructions Compatibility Execution SH2, Cycles T Bit SH2E SH4 SH-2A 1110nnnniiiiiiii imm  sign extension  Rn 1  Yes Yes Yes 1001nnnndddddddd (disp  2 + PC)  sign 1  Yes Yes Yes Instruction Instruction Code MOV #imm,Rn MOV.W @(disp,PC),Rn Operation extension  Rn MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp  4 + PC)  Rn 1  Yes Yes Yes MOV Rm,Rn 0110nnnnmmmm0011 Rm  Rn 1  Yes Yes Yes MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm  (Rn) 1  Yes Yes Yes MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm  (Rn) 1  Yes Yes Yes MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm  (Rn) 1  Yes Yes Yes MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm)  sign extension  Rn 1  Yes Yes Yes MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm)  sign extension  Rn 1  Yes Yes Yes MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm)  Rn 1  Yes Yes Yes MOV.B Rm,@-Rn 0010nnnnmmmm0100 Rn-1  Rn, Rm  (Rn) 1  Yes Yes Yes MOV.W Rm,@-Rn 0010nnnnmmmm0101 Rn-2  Rn, Rm  (Rn) 1  Yes Yes Yes MOV.L Rm,@-Rn 0010nnnnmmmm0110 Rn-4  Rn, Rm  (Rn) 1  Yes Yes Yes MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm)  sign extension  Rn, 1  Yes Yes Yes  Yes Yes Yes 1  Yes Yes Yes Rm + 1  Rm MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm)  sign extension  Rn, 1 Rm + 2  Rm @Rm+,Rn 0110nnnnmmmm0110 (Rm)  Rn, Rm + 4  Rm MOV.B R0,@(disp,Rn) 10000000nnnndddd R0  (disp + Rn) 1  Yes Yes Yes MOV.W R0,@(disp,Rn) 10000001nnnndddd R0  (disp  2 + Rn) 1  Yes Yes Yes MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm  (disp  4 + Rn) 1  Yes Yes Yes MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm)  sign extension 1  Yes Yes Yes 1  Yes Yes Yes MOV.L  R0 MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp  2 + Rm)  sign extension  R0 MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp  4 + Rm)  Rn 1  Yes Yes Yes MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm  (R0 + Rn) 1  Yes Yes Yes MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm  (R0 + Rn) 1  Yes Yes Yes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 83 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execution Instruction Instruction Code MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn Operation SH2, Cycles T Bit SH2E SH4 SH-2A 0000nnnnmmmm0110 Rm  (R0 + Rn) 1  Yes Yes Yes 0000nnnnmmmm1100 (R0 + Rm)  1  Yes Yes Yes 1  Yes Yes Yes sign extension  Rn MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm)  sign extension  Rn MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm)  Rn 1  Yes Yes Yes MOV.B R0,@(disp,GBR) 11000000dddddddd R0  (disp + GBR) 1  Yes Yes Yes MOV.W R0,@(disp,GBR) 11000001dddddddd R0  (disp  2 + GBR) 1  Yes Yes Yes MOV.L R0,@(disp,GBR) 11000010dddddddd R0  (disp  4 + GBR) 1  Yes Yes Yes MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR)  1  Yes Yes Yes 1  Yes Yes Yes Yes Yes Yes sign extension  R0 MOV.W @(disp,GBR),R0 11000101dddddddd (disp  2 + GBR)  sign extension  R0 MOV.L @(disp,GBR),R0 11000110dddddddd (disp  4 + GBR)  R0 1  MOV.B R0,@Rn+ 0100nnnn10001011 R0  (Rn), Rn + 1  Rn 1  Yes MOV.W R0,@Rn+ 0100nnnn10011011 R0  (Rn), Rn + 2  Rn 1  Yes MOV.L R0,@Rn+ 0100nnnn10101011 R0  Rn), Rn + 4  Rn 1  Yes MOV.B @-Rm,R0 0100mmmm11001011 Rm-1  Rm, (Rm)  1  Yes 1  Yes 1  Yes 1  Yes 1  Yes 1  Yes 1  Yes 1  Yes sign extension  R0 MOV.W @-Rm,R0 0100mmmm11011011 Rm-2  Rm, (Rm)  sign extension  R0 0100mmmm11101011 Rm-4  Rm, (Rm)  R0 MOV.L @-Rm,R0 MOV.B Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm  (disp + Rn) 0000dddddddddddd MOV.W Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm  (disp  2 + Rn) 0001dddddddddddd MOV.L Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm  (disp  4 + Rn) 0010dddddddddddd MOV.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm)  0100dddddddddddd sign extension  Rn MOV.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp  2 + Rm)  0101dddddddddddd sign extension  Rn Page 84 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execution Instruction Instruction Code Operation SH2, Cycles T Bit SH2E SH4 SH-2A 1  Yes MOV.L @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp  4 + Rm)  Rn MOVA @(disp,PC),R0 11000111dddddddd disp  4 + PC  R0 1  MOVI20 #imm20,Rn 0000nnnniiii0000 imm  sign extension  Rn 1  Yes 1  Yes 1 to 16  Yes 1 to 16  Yes 1 to 16  Yes 1 to 16  Yes Yes 0110dddddddddddd Yes Yes Yes iiiiiiiiiiiiiiii MOVI20S #imm20,Rn 0000nnnniiii0001 imm Rm (unsigned), 1 CMP/PL Rn 0011nnnnmmmm0111 0100nnnn00010101 When Rn > Rm (signed), Comparison Otherwise, 0  T Rm,Rn Com- 1T 1T CMP/GT Com- 1T result 1 Com- 1T parison Otherwise, 0  T result When Rn > 0, 1  T 1 Otherwise, 0  T Comparison result CMP/PZ Rn 0100nnnn00010001 When Rn  0, 1  T 1 Otherwise, 0  T Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When any bytes are equal, 1 Com- 1T parison Otherwise, 0  T result Page 87 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit CLIPS.B 0100nnnn10010001 When Rn > (H'0000007F), 1  Yes 1  Yes 1  Yes 1  Yes Rn SH2E SH4 SH-2A (H'0000007F)  Rn, 1  CS when Rn < (H'FFFFFF80), (H'FFFFFF80)  Rn, 1  CS CLIPS.W Rn 0100nnnn10010101 When Rn > (H'00007FFF), (H'00007FFF)  Rn, 1  CS When Rn < (H'FFFF8000), (H'FFFF8000)  Rn, 1  CS CLIPU.B Rn 0100nnnn10000001 When Rn > (H'000000FF), (H'000000FF)  Rn, 1  CS CLIPU.W Rn 0100nnnn10000101 When Rn > (H'0000FFFF), (H'0000FFFF)  Rn, 1  CS DIV1 Rm,Rn 0011nnnnmmmm0100 1-step division (Rn  Rm) 1 Calcu- Yes Yes Yes Yes Yes Yes Yes lation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn  Q, 1 MSB of Rm  M, M ^ Q  T Calcu- Yes lation result DIV0U DIVS 0000000000011001 R0,Rn 0100nnnn10010100 0  M/Q/T 1 0 Signed operation of Rn  R0 36  Yes Unsigned operation of Rn  R0 34  Yes Yes  Rn 32  32  32 bits DIVU R0,Rn 0100nnnn10000100  Rn 32  32  32 bits DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn  Rm 2  Yes Yes Yes 2  Yes Yes Yes 1 Compa Yes Yes Yes  MACH, MACL 32  32  64 bits DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn  Rm  MACH, MACL 32  32  64 bits DT EXTS.B Rn Rm,Rn 0100nnnn00010000 0110nnnnmmmm1110 Rn – 1  Rn When Rn is 0, 1  T -rison When Rn is not 0, 0  T result Byte in Rm is 1  Yes Yes Yes 1  Yes Yes Yes sign-extended  Rn EXTS.W Rm,Rn 0110nnnnmmmm1111 Word in Rm is sign-extended  Rn Page 88 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A EXTU.B 0110nnnnmmmm1100 Byte in Rm is 1  Yes Yes Yes 1  Yes Yes Yes 4  Yes Yes Yes 3  Yes Yes Yes 2  Yes Yes Yes Rm,Rn zero-extended  Rn EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended  Rn MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn)  (Rm) + MAC  MAC 32  32 + 64  64 bits MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn)  (Rm) + MAC  MAC 16  16 + 64  64 bits MUL.L Rm,Rn 0000nnnnmmmm0111 Rn  Rm  MACL 32  32  32 bits MULR R0,Rn 0100nnnn10000000 R0  Rn  Rn 2 Yes 32  32  32 bits MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn  Rm 1  Yes Yes Yes 1  Yes Yes Yes  MACL 16  16  32 bits MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn  Rm  MACL 16  16  32 bits NEG Rm,Rn 0110nnnnmmmm1011 0-Rm  Rn 1  Yes Yes Yes NEGC Rm,Rn 0110nnnnmmmm1010 0-Rm-T  Rn, borrow  T 1 Borrow Yes Yes Yes SUB Rm,Rn 0011nnnnmmmm1000 Rn-Rm  Rn 1  Yes Yes Yes SUBC Rm,Rn 0011nnnnmmmm1010 Rn-Rm-T  Rn, borrow  T 1 Borrow Yes Yes Yes SUBV Rm,Rn 0011nnnnmmmm1011 Rn-Rm  Rn, underflow  T 1 Over- Yes Yes Yes flow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 89 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.4.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm  Rn 1  Yes Yes Yes AND #imm,R0 11001001iiiiiiii R0 & imm  R0 1  Yes Yes Yes AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm  3  Yes Yes Yes 1  Yes Yes Yes (R0 + GBR) Rm,Rn 0110nnnnmmmm0111 ~Rm  Rn OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm  Rn 1  Yes Yes Yes OR #imm,R0 11001011iiiiiiii R0 | imm  R0 1  Yes Yes Yes OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm  3  Yes Yes Yes 3 Test Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes NOT (R0 + GBR) TAS.B @Rn 0100nnnn00011011 When (Rn) is 0, 1  T Otherwise, 0  T, result 1  MSB of(Rn) TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm 1 When the result is 0, 1  T Test result Otherwise, 0  T TST #imm,R0 11001000iiiiiiii R0 & imm 1 When the result is 0, 1  T Test result Otherwise, 0  T TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm 3 When the result is 0, 1  T Test result Otherwise, 0  T XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm  Rn 1  Yes Yes Yes XOR #imm,R0 11001010iiiiiiii R0 ^ imm  R0 1  Yes Yes Yes XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm  3  Yes Yes Yes (R0 + GBR) Page 90 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.4.5 Section 2 CPU Shift Instructions Table 2.14 Shift Instructions Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A ROTL Rn 0100nnnn00000100 T  Rn  MSB 1 MSB Yes Yes Yes ROTR Rn 0100nnnn00000101 LSB  Rn  T 1 LSB Yes Yes Yes ROTCL Rn 0100nnnn00100100 T  Rn  T 1 MSB Yes Yes Yes ROTCR Rn 0100nnnn00100101 T  Rn  T 1 LSB Yes Yes Yes SHAD Rm,Rn 0100nnnnmmmm1100 When Rm  0, Rn > |Rm|  [MSB  Rn] SHAL Rn 0100nnnn00100000 T  Rn  0 1 MSB Yes Yes Yes SHAR Rn 0100nnnn00100001 MSB  Rn  T 1 LSB Yes Yes Yes SHLD Rm,Rn 0100nnnnmmmm1101 When Rm  0, Rn > |Rm|  [0  Rn] SHLL Rn 0100nnnn00000000 T  Rn  0 1 MSB Yes Yes Yes SHLR Rn 0100nnnn00000001 0  Rn  T 1 LSB Yes Yes Yes SHLL2 Rn 0100nnnn00001000 Rn > 2  Rn 1  Yes Yes Yes SHLL8 Rn 0100nnnn00011000 Rn > 8  Rn 1  Yes Yes Yes SHLL16 Rn 0100nnnn00101000 Rn > 16  Rn 1  Yes Yes Yes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 91 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.4.6 Branch Instructions Table 2.15 Branch Instructions Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A BF 10001011dddddddd When T = 0, disp  2 + PC  3/1*  Yes Yes Yes 2/1*  Yes Yes Yes 3/1*  Yes Yes Yes 2/1*  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes label PC, When T = 1, nop BF/S label 10001111dddddddd Delayed branch When T = 0, disp  2 + PC  PC, When T = 1, nop BT label 10001001dddddddd When T = 1, disp  2 + PC  PC, When T = 0, nop BT/S label 10001101dddddddd Delayed branch When T = 1, disp  2 + PC  PC, When T = 0, nop BRA label 1010dddddddddddd Delayed branch, disp  2 + PC  PC BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC  PC BSR label 1011dddddddddddd Delayed branch, PC  PR, disp  2 + PC  PC BSRF Rm 0000mmmm00000011 Delayed branch, PC  PR, Rm + PC  PC JMP @Rm 0100mmmm00101011 Delayed branch, Rm  PC 2  Yes Yes Yes JSR @Rm 0100mmmm00001011 Delayed branch, PC  PR, 2  Yes Yes Yes PC-2  PR, Rm  PC 3  Yes PC-2  PR, 5  Yes 2  Rm  PC JSR/N @Rm JSR/N @@(disp8,TBR) 10000011dddddddd 0100mmmm01001011 (disp  4 + TBR)  PC RTS RTS/N RTV/N Note: Rm * 0000000000001011 Delayed branch, PR  PC 0000000001101011 PR  PC 3  Yes 0000mmmm01111011 Rm  R0, PR  PC 3  Yes Yes Yes Yes One cycle when the program does not branch. Page 92 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.4.7 Section 2 CPU System Control Instructions Table 2.16 System Control Instructions Compatibility Execution T Bit SH2E SH4 0T 1 0 Yes Yes Yes 0  MACH,MACL 1  Yes Yes Yes (Specified register bank entry) 6  Instruction Code Operation CLRT 0000000000001000 CLRMAC 0000000000101000 0100mmmm11100101 LDBANK @Rm,R0 SH2, Cycles Instruction SH-2A Yes  R0 LDC Rm,SR 0100mmmm00001110 Rm  SR 3 LSB LDC Rm,TBR 0100mmmm01001010 Rm  TBR 1  LDC Rm,GBR 0100mmmm00011110 Rm  GBR 1  LDC Rm,VBR 0100mmmm00101110 Rm  VBR 1 LDC.L @Rm+,SR 0100mmmm00000111 (Rm)  SR, Rm + 4  Rm 5 LDC.L @Rm+,GBR 0100mmmm00010111 (Rm)  GBR, Rm + 4  Rm LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH LDS Yes Yes Yes Yes Yes Yes Yes  Yes Yes Yes LSB Yes Yes Yes 1  Yes Yes Yes (Rm)  VBR, Rm + 4  Rm 1  Yes Yes Yes 0100mmmm00001010 Rm  MACH 1  Yes Yes Yes Rm,MACL 0100mmmm00011010 Rm  MACL 1  Yes Yes Yes LDS Rm,PR 0100mmmm00101010 Rm  PR 1  Yes Yes Yes LDS.L @Rm+,MACH 0100mmmm00000110 (Rm)  MACH, Rm + 4  Rm 1  Yes Yes Yes LDS.L @Rm+,MACL 0100mmmm00010110 (Rm)  MACL, Rm + 4  Rm 1  Yes Yes Yes LDS.L @Rm+,PR 0100mmmm00100110 (Rm)  PR, Rm + 4  Rm 1  Yes Yes Yes NOP 0000000000001001 No operation 1  Yes Yes Yes RESBANK 0000000001011011 Bank  R0 to R14, GBR, 9*  6  Yes Yes Yes Yes MACH, MACL, PR RTE 0000000000101011 Delayed branch, stack area  PC/SR SETT 0000000000011000 1T 1 1 Yes Yes Yes SLEEP 0000000000011011 Sleep 5  Yes Yes Yes 0100nnnn11100001 R0  7  STBANK R0,@Rn Yes (specified register bank entry) STC SR,Rn 0000nnnn00000010 SR  Rn 2  STC TBR,Rn 0000nnnn01001010 TBR  Rn 1  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Yes Yes Yes Yes Page 93 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A STC GBR,Rn 0000nnnn00010010 GBR  Rn 1  Yes Yes Yes STC VBR,Rn 0000nnnn00100010 VBR  Rn 1  Yes Yes Yes STC.L SR,@-Rn 0100nnnn00000011 Rn-4  Rn, SR  (Rn) 2  Yes Yes Yes STC.L GBR,@-Rn 0100nnnn00010011 Rn-4  Rn, GBR  (Rn) 1  Yes Yes Yes STC.L VBR,@-Rn 0100nnnn00100011 Rn-4  Rn, VBR  (Rn) 1  Yes Yes Yes STS MACH,Rn 0000nnnn00001010 MACH  Rn 1  Yes Yes Yes STS MACL,Rn 0000nnnn00011010 MACL  Rn 1  Yes Yes Yes STS PR,Rn 0000nnnn00101010 PR  Rn 1  Yes Yes Yes STS.L MACH,@-Rn 0100nnnn00000010 Rn-4  Rn, MACH  (Rn) 1  Yes Yes Yes STS.L MACL,@-Rn 0100nnnn00010010 Rn-4  Rn, MACL  (Rn) 1  Yes Yes Yes STS.L PR,@-Rn 0100nnnn00100010 Rn-4  Rn, PR  (Rn) 1  Yes Yes Yes TRAPA #imm 11000011iiiiiiii PC/SR  stack area, 5  Yes Yes Yes (imm  4 + VBR)  PC Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory  register) is the same as the register used by the next instruction. * In the event of bank overflow, the number of cycles is 19. Page 94 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.4.8 Section 2 CPU Floating-Point Operation Instructions Table 2.17 Floating-Point Operation Instructions Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit FABS FRn 1111nnnn01011101 |FRn|  FRn 1  FABS DRn 1111nnn001011101 |DRn|  DRn 1  FADD FRm, FRn 1111nnnnmmmm0000 FRn + FRm  FRn 1  FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm  DRn 6  FCMP/EQ FRm, FRn 1111nnnnmmmm0100 (FRn = FRm)? 1:0  T 1 Com- SH2E SH4 FPU Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes parison result FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn = DRm)? 1:0  T 2 Comparison result FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn > FRm)? 1:0  T 1 Com- Yes parison result FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn > DRm)? 1:0  T 2 Comparison result FCNVDS DRm, FPUL 1111mmm010111101 (float) DRm  FPUL 2  Yes Yes FCNVSD FPUL, DRn 1111nnn010101101 (double) FPUL  DRn 2  Yes Yes FDIV FRm, FRn 1111nnnnmmmm0011 FRn/FRm  FRn 10  Yes Yes FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm  DRn 23  Yes Yes FLDI0 FRn 1111nnnn10001101 0  00000000  FRn 1  Yes Yes Yes FLDI1 FRn 1111nnnn10011101 0  3F800000  FRn 1  Yes Yes Yes FLDS FRm, FPUL 1111mmmm00011101 FRm  FPUL 1  Yes Yes Yes FLOAT FPUL,FRn 1111nnnn00101101 (float)FPUL  FRn 1  Yes Yes Yes FLOAT FPUL,DRn 1111nnn000101101 (double)FPUL  DRn 2  Yes Yes FMAC FR0,FRm,FRn 1111nnnnmmmm1110 FR0  FRm+FRn  1  Yes Yes Yes Yes Yes Yes Yes Yes Yes FRn FMOV FRm, FRn 1111nnnnmmmm1100 FRm  FRn 1  FMOV DRm, DRn 1111nnn0mmm01100 DRm  DRn 2  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 95 of 3092 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit SH2E SH4 FPU FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 (R0 + Rm)  FRn 1  Yes Yes Yes FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0 + Rm)  DRn 2  Yes Yes FMOV.S @Rm+, FRn 1111nnnnmmmm1001 (Rm)  FRn, Rm+=4 1  FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm)  DRn, Rm += 8 2  Yes Yes Yes Yes FMOV.S @Rm, FRn 1111nnnnmmmm1000 (Rm)  FRn 1  Yes Yes FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm)  DRn 2  Yes Yes FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 (disp  4 + Rm)  FRn 1  Yes FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 (disp  8 + Rm)  DRn 2  Yes Yes Yes 0111dddddddddddd 0111dddddddddddd FMOV.S FRm, @(R0,Rn) 1111nnnnmmmm0111 FRm  (R0 + Rn) 1  FMOV.D DRm, @(R0,Rn) 1111nnnnmmm00111 DRm  (R0 + Rn) 2  FMOV.S FRm, @-Rn 1111nnnnmmmm1011 Rn-=4, FRm  (Rn) 1  FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn-=8, DRm  (Rn) 2  FMOV.S FRm, @Rn 1111nnnnmmmm1010 FRm  (Rn) 1  FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm  (Rn) 2  FMOV.S FRm, 0011nnnnmmmm0001 FRm  (disp  4 + Rn) 1  Yes DRm  (disp  8 + Rn) 2  Yes @(disp12,Rn) 0011dddddddddddd FMOV.D 0011nnnnmmm00001 DRm, @(disp12,Rn) 0011dddddddddddd FMUL FRm, FRn 1111nnnnmmmm0010 FRn  FRm  FRn 1  FMUL DRm, DRn 1111nnn0mmm00010 DRn  DRm  DRn 6  FNEG FRn 1111nnnn01001101 -FRn  FRn 1  FNEG DRn 1111nnn001001101 -DRn  DRn 1 1111001111111101 FPSCR.SZ=~FPSCR.S FSCHG Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes  Yes Yes 1  Yes Yes Yes Z FSQRT FRn 1111nnnn01101101 FRn  FRn 9  Yes Yes FSQRT DRn 1111nnn001101101 DRn  DRn 22  Yes Yes FSTS FPUL,FRn 1111nnnn00001101 FPUL  FRn 1  Yes Yes Yes FSUB FRm, FRn 1111nnnnmmmm0001 FRn-FRm  FRn 1  Yes Yes Yes Page 96 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 2 CPU Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit FSUB DRm, DRn 1111nnn0mmm00001 DRn-DRm  DRn 6  FTRC FRm, FPUL 1111mmmm00111101 (long)FRm  FPUL 1  FTRC DRm, FPUL 1111mmm000111101 (long)DRm  FPUL 2  2.4.9 FPU-Related CPU Instructions SH2E Yes SH4 FPU Yes Yes Yes Yes Yes Yes Table 2.18 FPU-Related CPU Instructions Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit LDS Rm,FPSCR 0100mmmm01101010 Rm  FPSCR 1 LDS Rm,FPUL 0100mmmm01011010 Rm  FPUL LDS.L @Rm+, FPSCR 0100mmmm01100110 LDS.L @Rm+, FPUL 0100mmmm01010110 (Rm)  FPUL, Rm+=4 STS FPSCR, Rn 0000nnnn01101010 STS FPUL,Rn STS.L STS.L SH2E SH4 FPU  Yes Yes Yes 1  Yes Yes Yes (Rm)  FPSCR, Rm+=4 1  Yes Yes Yes 1  Yes Yes Yes FPSCR  Rn 1  Yes Yes Yes 0000nnnn01011010 FPUL  Rn 1  Yes Yes Yes FPSCR,@-Rn 0100nnnn01100010 Rn-=4, FPCSR  (Rn) 1  Yes Yes Yes FPUL,@-Rn 0100nnnn01010010 Rn-=4, FPUL  (Rn) 1  Yes Yes Yes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 97 of 3092 SH7268 Group, SH7269 Group Section 2 CPU 2.4.10 Bit Manipulation Instructions Table 2.19 Bit Manipulation Instructions Compatibility ExecuInstruction BAND.B #imm3,@(disp12,Rn) tion SH2, Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A 0011nnnn0iii1001 (imm of (disp + Rn)) & T  3 Ope- Yes ration 0100dddddddddddd result BANDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) & T  T 3 Ope- Yes ration 1100dddddddddddd result BCLR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0  (imm of (disp + Rn)) 3  Yes  Yes Ope- Yes 0000dddddddddddd BCLR #imm3,Rn 10000110nnnn0iii 0  imm of Rn 1 BLD.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 (imm of (disp + Rn))  3 ration 0011dddddddddddd result BLD #imm3,Rn 10000111nnnn1iii imm of Rn  T 1 Ope- Yes ration result BLDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) 1011dddddddddddd T 3 Ope- Yes ration result BOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ( imm of (disp + Rn)) | T  T 3 Ope- Yes ration 0101dddddddddddd result BORNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~( imm of (disp + Rn)) | T  T 3 Ope- Yes ration 1101dddddddddddd result BSET.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1  ( imm of (disp + Rn)) 3  Yes 0001dddddddddddd BSET #imm3,Rn 10000110nnnn1iii 1  imm of Rn 1  Yes BST.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 T  (imm of (disp + Rn)) 3  Yes 0010dddddddddddd BST #imm3,Rn 10000111nnnn0iii T  imm of Rn 1  Yes BXOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 (imm of (disp + Rn)) ^ T  T 3 Ope- Yes 0110dddddddddddd ration result Page 98 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 2.5 Section 2 CPU Processing States The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Manual reset from any state Power-on reset from any state Manual reset state Power-on reset state Reset state NMI interrupt, realtime clock alarm interrupt, change in the level of a pin that initiates release, and power-on reset Reset canceled Interrupt source or DMA address error occurs Exception handling state Bus request cleared Exception handling Bus request source generated occurs Bus-released state Bus request generated Bus request generated Bus request cleared Sleep mode NMI interrupt or IRQ interrupt occurs Exception handling ends Bus request cleared Program execution state STBY bit cleared for SLEEP instruction STBY bit set and DEEP bit cleared for SLEEP instruction Software standby mode STBY and DEEP bits set for SLEEP instruction Deep standby mode Power-down state Figure 2.6 Transitions between Processing States R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 99 of 3092 Section 2 CPU (1) SH7268 Group, SH7269 Group Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception handling vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception handling vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. (3) Program Execution State In the program execution state, the CPU sequentially executes the program. (4) Power-Down State In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP instruction places the CPU in sleep mode, software standby mode, or deep standby mode. (5) Bus-Released State In the bus-released state, the CPU releases bus to a device that has requested it. Page 100 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) Section 3 Floating-Point Unit (FPU) 3.1 Features The FPU has the following features.  Conforms to IEEE754 standard  16 single-precision floating-point registers (can also be referenced as eight double-precision registers)  Two rounding modes: Round to nearest and round to zero  Denormalization modes: Flush to zero  Five exception sources: Invalid operation, divide by zero, overflow, underflow, and inexact  Comprehensive instructions: Single-precision, double-precision, and system control R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 101 of 3092 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) 3.2 Data Formats 3.2.1 Floating-Point Format A floating-point number consists of the following three fields:  Sign (s)  Exponent (e)  Fraction (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 3.1 and 3.2. 31 30 s 23 0 22 f e Figure 3.1 Format of Single-Precision Floating-Point Number 63 62 s 52 0 51 e f Figure 3.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin – 1 to Emax + 1. The two values Emin – 1 and Emax + 1 are distinguished as follows. Emin – 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). Table 3.1 shows Emin and Emax values. Page 102 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Table 3.1 Section 3 Floating-Point Unit (FPU) Floating-Point Number Formats and Parameters Parameter Single-Precision Double-Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias +127 +1023 Emax +127 +1023 Emin –126 –1022 Floating-point number value v is determined as follows: If E = Emax + 1 and f  0, v is a non-number (NaN) irrespective of sign s If E = Emax + 1 and f = 0, v = (–1)s (infinity) [positive or negative infinity] If Emin  E  Emax , v = (–1)s2E (1.f) [normalized number] If E = Emin – 1 and f  0, v = (–1)s2Emin (0.f) [denormalized number] If E = Emin – 1 and f = 0, v = (–1)s0 [positive or negative zero] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 103 of 3092 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) Table 3.2 shows the ranges of the various numbers in hexadecimal notation. Table 3.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFF FFFF to H'7FC0 0000 H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 Quiet non-number H'7FBF FFFF to H'7F80 0001 H'7FF7 FFFF FFFF FFFF to H'7FF0 0000 0000 0001 Positive infinity H'7F80 0000 H'7FF0 0000 0000 0000 Positive normalized number H'7F7F FFFF to H'0080 0000 H'7FEF FFFF FFFF FFFF to H'0010 0000 0000 0000 Positive denormalized number H'007F FFFF to H'0000 0001 H'000F FFFF FFFF FFFF to H'0000 0000 0000 0001 Positive zero H'0000 0000 H'0000 0000 0000 0000 Negative zero H'8000 0000 H'8000 0000 0000 0000 Negative denormalized number H'8000 0001 to H'807F FFFF H'8000 0000 0000 0001 to H'800F FFFF FFFF FFFF Negative normalized number H'8080 0000 to H'FF7F FFFF H'8010 0000 0000 0000 to H'FFEF FFFF FFFF FFFF Negative infinity H'FF80 0000 H'FFF0 0000 0000 0000 Quiet non-number H'FF80 0001 to H'FFBF FFFF H'FFF0 0000 0000 0001 to H'FFF7 FFFF FFFF FFFF Signaling non-number H'FFC0 0000 to H'FFFF FFFF H'FFF8 0000 0000 0000 to H'FFFF FFFF FFFF FFFF Page 104 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 3.2.2 Section 3 Floating-Point Unit (FPU) Non-Numbers (NaN) Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:  Sign bit: Don't care  Exponent field: All bits are 1  Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0. 31 30 x 23 11111111 22 0 Nxxxxxxxxxxxxxxxxxxxxxx N = 1: sNaN N = 0: qNaN Figure 3.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value.  When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.  When the EN.V bit in FPSCR is 1, an invalid operation exception will generate FPU exception processing. In this case, the contents of the operation destination register are unchanged. If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit in FPSCR. An exception will not be generated in this case. The qNAN values as operation results are as follows:  Single-precision qNaN: H'7FBF FFFF  Double-precision qNaN: H'7FF7 FFFF FFFF FFFF See the individual instruction descriptions for details of floating-point operations when a nonnumber (NaN) is input. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 105 of 3092 Section 3 Floating-Point Unit (FPU) 3.2.3 SH7268 Group, SH7269 Group Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. In the SH2A-FPU, the DN bit in the status register FPSCR is always set to 1, therefore a denormalized number (source operand or operation result) is always flushed to 0 in a floatingpoint operation that generates a value (an operation other than copy, FNEG, or FABS). When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is processed as it is. See the individual instruction descriptions for details of floating-point operations when a denormalized number is input. Page 106 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) 3.3 Register Descriptions 3.3.1 Floating-Point Registers Figure 3.4 shows the floating-point register configuration. There are sixteen 32-bit floating-point registers FPR0 to FPR15, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14. The correspondence between FRPn and the reference name is determined by the PR and SZ bits in FPSCR. Refer figure 3.4. 1. Floating-point registers, FPRi (16 registers) FPR0 to FPR15 2. Single-precision floating-point registers, FRi (16 registers) FR0 to FR15 indicate FPR0 to FPR15 3. Double-precision floating-point registers or single-precision floating-point vector registers in pairs, DRi (8 registers) A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} Reference name Register name Transfer instruction case: FPSCR.SZ = 0 FPSCR.SZ = 1 Operation instruction case: FPSCR.PR = 0 FPSCR.PR = 1 FR0 DR0 FR1 FR2 DR2 FR3 FR4 DR4 FR5 FR6 DR6 FR7 FR8 DR8 FR9 FR10 DR10 FR11 FR12 DR12 FR13 FR14 DR14 FR15 FPR0 FPR1 FPR2 FPR3 FPR4 FPR5 FPR6 FPR7 FPR8 FPR9 FPR10 FPR11 FPR12 FPR13 FPR14 FPR15 Figure 3.4 Floating-Point Registers R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 107 of 3092 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) 3.3.2 Floating-Point Status/Control Register (FPSCR) FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 - - - - - - - - - QIS - SZ PR DN Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 1 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Cause Initial value: 0 R/W: R/W 0 R/W Enable 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Flag 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17 16 Cause 0 R/W 0 R/W 1 0 RM1 RM0 0 R/W 1 R/W Bit Bit Name Initial Value R/W Description 31 to 23  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 22 QIS 0 R/W Nonnunerical Processing Mode 0: Processes qNaN or  as such 1: Treats qNaN or  as the same as sNaN (valid only when FPSCR.Enable.V = 1) 21  0 R Reserved This bit is always read as 0. The write value should always be 0. 20 SZ 0 R/W Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) 19 PR 0 R/W Precision Mode 0: Floating-point instructions are executed as singleprecision operations 1: Floating-point instructions are executed as doubleprecision operations (graphics support instructions are undefined) 18 DN 1 R Denormalization Mode (Always fixed to 1 in SH2AFPU) 1: Denormalized number is treated as zero Page 108 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) Bit Bit Name Initial Value R/W Description 17 to 12 Cause H'00 R/W 11 to 7 Enable H'00 R/W 6 to 2 Flag H'00 R/W FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time floating-point operation instruction is executed, the FPU exception cause field is cleared to 0 first. When an FPU exception on floating-point operation occurs, the bits corresponding to the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. As the bits corresponding to FPU exception enable filed are sets to 1, FPU exception processing occurs. For bit allocations of each field, see table 3.3. 1 RM1 0 R/W 0 RM0 1 R/W Table 3.3 Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved Bit Allocation for FPU Exception Handling Field Name FPU Error (E) Invalid Division Operation (V) by Zero (Z) Overflow Underflow Inexact (O) (U) (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag None field Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Note: No FPU error occurs in the SH2A-FPU. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 109 of 3092 Section 3 Floating-Point Unit (FPU) 3.3.3 SH7268 Group, SH7269 Group Floating-Point Communication Register (FPUL) Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register that is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number, the processing flow is as follows: R1  (LDS instruction)  FPUL  (single-precision FLOAT instruction)  FR1 Page 110 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 3.4 Section 3 Floating-Point Unit (FPU) Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. Which of the two rounding methods is to be used is determined by the RM bits in FPSCR. FPSCR.RM[1:0] = 00: Round to Nearest FPSCR.RM[1:0] = 01: Round to Zero (1) Round to Nearest The operation result is rounded to the nearest expressible value. If there are two nearest expressible values, the one with an LSB of 0 is selected. If the unrounded value is 2Emax (2 – 2–P) or more, the result will be infinity with the same sign as the unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. (2) Round to Zero The digits below the round bit of the unrounded value are discarded. If the unrounded value is larger than the maximum expressible absolute value, the value will become the maximum expressible absolute value. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 111 of 3092 Section 3 Floating-Point Unit (FPU) 3.5 FPU Exceptions 3.5.1 FPU Exception Sources SH7268 Group, SH7269 Group FPU exceptions may occur on floating-point operation instruction and the exception sources are as follows:  FPU error (E): When FPSCR.DN = 0 and a denormalized number is input (No error occurs in the SH2A-FPU)  Invalid operation (V): In case of an invalid operation, such as NaN input  Division by zero (Z): Division with a zero divisor  Overflow (O): When the operation result overflows  Underflow (U): When the operation result underflows  Inexact exception (I): When overflow, underflow, or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled. When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the corresponding bit in the FPU exception flag field remains unchanged. 3.5.2 FPU Exception Handling FPU exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No error occurs in the SH2A-FPU)  Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation  Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor  Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result overflow  Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result underflow  Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation result Page 112 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 3 Floating-Point Unit (FPU) These possibilities of each exceptional handling on floating-point operation are shown in the individual instruction descriptions. All exception events that originate in the floating-point operation are assigned as the same FPU exceptional handling event. The meaning of an exception generated by floating-point operation is determined by software by reading from FPSCR and interpreting the information it contains. Also, the destination register is not changed when FPU exception handling operation occurs. Except for the above, the FPU disables exception handling. In every processing, the bit corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the operation result.  Invalid operation (V): qNaN is generated as the result.  Division by zero (Z): Infinity with the same sign as the unrounded value is generated.  Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated.  Underflow (U): Zero with the same sign as the unrounded value is generated.  Inexact exception (I): An inexact result is generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 113 of 3092 Section 3 Floating-Point Unit (FPU) Page 114 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 4 Boot Mode Section 4 Boot Mode This LSI can be booted from the memory connected to the CS0 space, the NAND flash memory, the serial flash memory, the NAND flash memory with an SD controller, and the NAND flash memory with an MMC controller. 4.1 Features  Six boot modes Boot mode 0: Boots the LSI from the memory (bus width: 16 bits) connected to the CS0 space Boot mode 1: Boots the LSI from the memory (bus width: 32 bits) connected to the CS0 space Boot mode 2: Boots the LSI from the NAND flash memory Boot mode 3: Boots the LSI from the serial flash memory Boot mode 4: Boots the LSI from the NAND flash memory with the SD controller*1 Boot mode 5: Boots the LSI from the NAND flash memory with the MMC controller*2 Notes: 1. It is possible to boot the LSI from the embedded SD (eSD) defined by the SD specification part 1 eSD addendum version 2.10 standard. 2. It is possible to boot the LSI from the eMMC device corresponding to the boot operating mode of the JEDEC standard JESD84 A44 (MMCA 4.4) Standard. (It is not possible to boot the LSI from the MMC card.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 115 of 3092 SH7268 Group, SH7269 Group Section 4 Boot Mode 4.2 Boot Mode and Pin Function Setting This LSI can determine the boot mode using external pins when RES is low. The external pin settings for selecting the boot mode are shown in table 4.1. Table 4.1 External Pin (MD_BOOT2 to MD_BOOT0) Settings and Corresponding Boot Modes MD_BOOT2 MD_BOOT1 MD_BOOT0 Boot Mode * 0 0 Boot Mode 0 Boots the LSI from the memory (bus width: 16 bits) connected to the CS0 space. * 1 0 Boot Mode 1 Boots the LSI from the memory (bus width: 32 bits) connected to the CS0 space. 0 0 1 Boot Mode 2 Boots the LSI from the NAND flash memory connected to the NAND flash memory controller. 1 0 1 Boot Mode 3 Boots the LSI from the serial flash memory connected to channel 0 (PB20 to PB17) of the Renesas serial peripheral interface. Booting this LSI chip over the channel 0 (PJ19 to PJ16) of the Renesas serial peripheral interface is impossible. 0 1 1 Boot Mode 4 Boots the LSI from the flash memory with the SD controller connected to channel 0 of the SD host interface. 1 1 1 Boot Mode 5 Boots the LSI from the flash memory with the MMC controller connected to the MMC host interface. Page 116 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 4.3 Operation 4.3.1 Boot Modes 0 and 1 Section 4 Boot Mode In boot modes 0 and 1, this LSI is booted from the memory connected to the CS0 space. In this mode, this LSI operates as follows: After the power-on reset is canceled, the initial value (execution start address) of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table located in the memory connected to the CS0 space, then program execution is started. 4.3.2 Boot Mode 2 In boot mode 2, booting up is from NAND flash memory, which is connected to the NAND flash memory controller. Suitable NAND flash memory has a large block size (2048  64) and takes five-byte addresses (has a capacity of 2 GB or greater). The flow of initiation in boot mode 2 is as described below. (1) Execution from on-Chip ROM of the Program for Boot Initiation After release from the power-on reset state, the CPU executes the boot initiation program that has been stored in on-chip ROM (and is not publicly disclosed). (2) Transfer of the Loader Program The 8-KB loader program is transferred from NAND flash memory, which is connected to the NAND flash memory controller, to the first location of the high-speed on-chip RAM. Transfer and checking by the loader program proceed as follows. (a) A search is conducted to find the block which holds the loader program. Block addresses 0 to 1023 (max.) (b) The 8-KB (16-sector) loader program is read out and transferred to high-speed on-chip RAM. Once transfer of the loader program has been completed, execution by the CPU jumps to highspeed on-chip RAM so that it can start executing the transferred loader program. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 117 of 3092 SH7268 Group, SH7269 Group Section 4 Boot Mode (3) Transfer of an Application Program (as Desired) The loader program employs the NAND flash memory controller to transfer the data to be deployed from NAND flash memory to on-chip RAM or external RAM. Figure 4.1 is a schematic view of the specifications for boot mode 2. This LSI (1) Program execution Read request On-chip ROM for boot initiation (not publicly disclosed) High-speed on-chip RAM H'FFF8 0000 Read request H'FFF8 1FFF NAND flash memory controller (2) (a) Search for the loader program NAND flash memory Loader program (8 KB) (2) (b) Loading into highspeed on-chip RAM Read Application program Loader program (8 KB) (3) Loading into external or on-chip RAM On-chip RAM External RAM Application program Application program Figure 4.1 Schematic View of Specification for Boot Mode 2 Page 118 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 4 Boot Mode Figure 4.2 shows the locations where the loader program is stored. Store the loader program in sectors 0 to 15 of the loader block. Read out the loader program in sectors. NAND flash memory Highest Search in blocks 0 to 1023 (max.) Sectors 0 to 15 Loader program Lowest Figure 4.2 Locations where the Loader Program is Stored 4.3.3 Boot Mode 3 In boot mode 3, booting up is from serial flash memory, which is connected to channel 0 of the Renesas serial peripheral interface. The flow of initiation in boot mode 3 is as described below. (1) Execution from on-Chip ROM of the Program for Boot Initiation After release from the power-on reset state, the CPU executes the boot initiation program that has been stored in on-chip ROM (and is not publicly disclosed). (2) Transfer of the Loader Program Starting with transfer from the respective first locations, the 8-KB loader program is transferred from serial flash memory, which is connected to channel 0 of the Renesas serial peripheral interface, to high-speed on-chip RAM. Once transfer of the loader program has been completed, execution by the CPU jumps to highspeed on-chip RAM so that it can start executing the transferred loader program. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 119 of 3092 SH7268 Group, SH7269 Group Section 4 Boot Mode (3) Transfer of an Application Program (as Desired) The loader program employs the Renesas serial peripheral interface to transfer the data to be deployed from serial flash memory to on-chip RAM or external RAM. Figure 4.3 is a schematic view of the specification for boot mode 3. This LSI (1) Program execution Read request On-chip ROM for boot initiation (not publicly disclosed) High-speed on-chip RAM H'FFF8 0000 H'FFF8 1FFF Loader program (8 KB) Renesas serial peripheral interface Channel 0* Serial flash memory Loader program (8 KB) Read (2) Loading into high-speed on-chip RAM Read Read request (3) Loading into external or on-chip RAM On-chip RAM Application program External RAM Application program Application program Note: * Booting the LSI is only possible by using the pins which also function as PB20 to PB17. Figure 4.3 Schematic View of Specification for Boot Mode 3 Page 120 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 4.3.4 Section 4 Boot Mode Boot Mode 4 In boot mode 4, booting up is from flash memory with the SD controller, which is connected to channel 0 of the SD host interface. The flow of initiation in boot mode 4 is as described below. (1) Execution from on-Chip ROM of the Program for Boot Initiation After release from the power-on reset state, the CPU executes the boot initiation program that has been stored in on-chip ROM (and is not publicly disclosed). (2) Transfer of the Loader Program The 16-KB loader program is transferred from flash memory with the SD controller, which is connected to channel 0 of the SD host interface, to the first location (page 0) of the high-speed onchip RAM. Page 1 of the high-speed on-chip RAM is also used as the work memory for boot process. Once transfer of the loader program has been completed, execution by the CPU jumps to page 0 of the high-speed on-chip RAM so that it can start executing the transferred loader program. (3) Transfer of an Application Program (as Desired) The loader program employs the SD host interface to transfer the data to be deployed from flash memory with the SD controller to on-chip RAM or external RAM. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 121 of 3092 SH7268 Group, SH7269 Group Section 4 Boot Mode Figure 4.4 is a schematic view of the specification for boot mode 4. This LSI NAND flash memory with SD controller (1) Program execution On-chip ROM for boot initiation (not publicly disclosed) Channel 0 High-speed on-chip RAM (page 0) H'FFF8_0000 H'FFF8_3FFF Loader program (16 KB) Loader program (16 KB) Read request SD host interface Read request (2) Loading into high-speed on-chip RAM Application program Read High-speed on-chip RAM (page 1) H'FFF8_4000 Work memory for boot process (16 KB) H'FFF8_7FFF (3) Loading into external or on-chip RAM On-chip RAM External RAM Application program Application program Figure 4.4 Schematic View of Specification for Boot Mode 4 4.3.5 Boot Mode 5 In boot mode 5, booting up is from flash memory with the MMC controller, which is connected to the MMC host interface. The flow of initiation in boot mode 5 is as described below. (1) Execution from on-Chip ROM of the Program for Boot Initiation After release from the power-on reset state, the CPU executes the boot initiation program that has been stored in on-chip ROM (and is not publicly disclosed). (2) Transfer of the Loader Program The 16-KB loader program is transferred from flash memory with the MMC controller, which is connected to the MMC host interface, to the first location (page 0) of the high-speed on-chip RAM with the MMC data bus width of 4 bits. Page 1 of the high-speed on-chip RAM is also used as the work memory for boot process. Once transfer of the loader program has been completed, execution by the CPU jumps to page 0 of the high-speed on-chip RAM so that it can start executing the transferred loader program. Page 122 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 4 Boot Mode Transfer of an Application Program (as Desired) The loader program employs the MMC host interface to transfer the data to be deployed from flash memory with the MMC controller to on-chip RAM or external RAM. Figure 4.5 is a schematic view of the specification for boot mode 5. This LSI NAND flash memory with MMC controller (1) Program execution On-chip ROM for boot initiation (not publicly disclosed) High-speed on-chip RAM (page 0) H'FFF8_0000 H'FFF8_3FFF Loader program (16 KB) Loader program (16 KB) Read request MMC host interface Read request (2) Loading into high-speed on-chip RAM Application program Read High-speed on-chip RAM (page 1) H'FFF8_4000 Work memory for boot process (16 KB) H'FFF8_7FFF (3) Loading into external or on-chip RAM On-chip RAM External RAM Application program Application program Figure 4.5 Schematic View of Specification for Boot Mode 5 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 123 of 3092 Section 4 Boot Mode 4.4 Notes 4.4.1 Boot Related Pins SH7268 Group, SH7269 Group The initial states and output states in deep standby mode of the pins related to CS0 space memory read, NAND flash memory controller, channel 0 of the Renesas serial peripheral interface, channel 0 of the SD host interface, and the MMC host interface are different in each boot mode. For details, refer to section 10, Bus State Controller, section 48, General Purpose I/O Ports, and section 49, Power-Down Modes. Page 124 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator Section 5 Clock Pulse Generator This LSI has a clock pulse generator that generates a CPU clock (I), internal bus clock (B), peripheral clock 0 (P0), and peripheral clock 1 (P1). The clock pulse generator consists of a crystal oscillator, PLL circuits, and divider circuits. 5.1 Features  Four clocks generated independently A CPU clock (I) for the CPU and cache; an internal bus clock (B) for the I-Bus; peripheral clock 0 (P0) for the on-chip peripheral modules; peripheral clock 1 (P1 = CKIO) for the external bus interface  Frequency change function CPU and internal bus clock frequencies can be changed independently using the PLL (phase locked loop) circuits and divider circuits within this module. Frequencies are changed by software using frequency control register (FRQCR) settings.  Power-down mode control The clock can be stopped in sleep mode, software standby mode, and deep standby mode, and specific modules can be stopped using the module standby function. For details on clock control in the power-down modes, see section 49, Power-Down Modes.  SSCG function The CPU's internal PLL (phase locked loop) circuit includes an SSCG (spread spectrum clock generator). The SSCG can be used to decrease the peak value of EMI (electromagnetic interference) noise by frequency modulation, that is, by slightly modulating the output frequency. The specification of the SSCG for this LSI is as follows.  Specification of SSCG (1) Modulation waveform (modulation profile) : Triangle wave (2) Type of spreading : Down-spreading (3) Modulation rate : -2.5 (fixed) (4) Modulation frequency : 20.00 to 26.67 KHz (frequency on the EXTAL pin  500) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 125 of 3092 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator Figure 5.1 shows a block diagram of the clock pulse generator. Divider 1 CPU clock (Iφ Max: 266.67 MHz) x1 XTAL Crystal oscillator PLL circuit (x20) x 1/2 x 1/4 EXTAL Internal Bus clock (Bφ Max: 133.33 MHz) SSCG circuit Peripheral clock 0 (P0φ Max: 33.33 MHz) x 1/8 Peripheral clock 1 (P1φ Max: 66.67 MHz) External Bus clock (CKIO Max: 66.67 MHz) Peripheral clock 1C (P1φ Max: 66.67 MHz) Peripheral clock 0C (P0φ Max: 33.33 MHz) x 1/4 x 1/8 Control unit MD_CLK0 Clock frequency control circuit Standby control circuit FRQCR Bus interface Peripheral bus [Legend] FRQCR: Frequency control register Peripheral clocks 0C and 1C: Not modulated even when the SSCG function is enabled. Figure 5.1 Block Diagram Page 126 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator The blocks of this module function as follows: (1) Crystal Oscillator The crystal oscillator is used in which the crystal resonator is connected to the XTAL/EXTAL pin. (2) PLL Circuit The PLL circuit is capable of multiplying the frequency of the input clock signal from the crystal oscillator or EXTAL pin by 20. (3) Divider 1 Divider 1 generates a clock signal whose operating frequency can be used for the CPU clock, internal bus clock, peripheral clock 0, and peripheral clock 1. The division ratio of the CPU clock and the internal bus clock is set by the frequency control register. The division ratios for peripheral clocks 1 and 0 are fixed to 1/4 and 1/8, respectively. (4) Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency using the frequency control register (FRQCR). (5) Standby Control Circuit The standby control circuit controls the states of the on-chip oscillation circuit and other modules during clock switching, or sleep, software standby or deep standby mode. In addition, the standby control register is provided to control the power-down mode of other modules. For details on the standby control register, see section 49, Power-Down Modes. (6) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode and the frequency division ratio of the CPU clock (I) and the internal bus clock (B). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 127 of 3092 Section 5 Clock Pulse Generator (7) SH7268 Group, SH7269 Group SSCG Circuit Operation of the SSCG circuit is switched on or off (enabled or disabled) by the MD_CLK0 pin. When the SSCG function is disabled, all of the internal clock frequencies are fixed, i.e. not modulated. When the SSCG function is enabled, the frequencies of clock signals supplied to peripheral modules other than those listed below are modulated. Peripheral modules to which non-modulated clock signals are supplied: IEBus controller, multi-function timer pulse unit 2, serial communications interface with FIFO, controller area network, compare match timer, motor control PWM timer, and sound generator. Page 128 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 5.2 Section 5 Clock Pulse Generator Input/Output Pins Table 5.1 lists the clock pulse generator pins and their functions. Table 5.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name Symbol Mode control pin MD_CLK0 Input Crystal input/output XTAL pins (clock input pins) Clock output pin I/O Function Enables or disables the SSCG circuit. Output Connected to the crystal resonator. (Leave this pin open when the crystal resonator is not in use.) EXTAL Input Connected to the crystal resonator or used to input external clock. CKIO Output Clock output pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 129 of 3092 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator 5.3 Clock Mode Table 5.2 indicates the input/output clock frequency. Table 5.3 shows the usable frequency ranges. Table 5.2 Input/Output Clock Frequency Clock I/O Source Output EXTAL or crystal resonator CKIO PLL Circuit On/Off ON (20) CKIO Frequency (EXTAL or crystal resonator)  5 Clock is input from the EXTAL pin or the crystal oscillator. The PLL circuit shapes waveforms and multiples the frequency, and then supplies the clock to the LSI. The oscillating frequency for the crystal resonator and EXTAL pin input clock ranges from 10 to 13.333 MHz. The frequency range of CKIO is from 50 to 66.67 MHz. Page 130 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Table 5.3 Section 5 Clock Pulse Generator Settable Frequency Ranges PLL Frequency Multiplier Selectable Frequency Range (MHz) Ratio of Internal Clock Frequencies FRQCR Input Setting*1 PLL Circuit (I : B : P1 : P0)*2 Clock*3 H'x015 ON (×20) 20 : 10 : 5 : 5/2 H'x035 ON (×20) 20 : 5 : 5 : 5/2 Output Internal Bus Peripheral Peripheral Clock (CKIO CPU Clock Pin) (I) Clock (B) Clock 1 (P1) Clock 0 (P0) 50 to 66.67 25 to 33.33 10 to 13.333 50 to 66.67 10 to 13.333 50 to 66.67 200 to 100 to 266.66 133.33 200 to 50 to 66.67 50 to 66.67 25 to 33.33 50 to 66.67 25 to 33.33 266.66 H'x115 H'x135 ON (×20) ON (×20) 10 : 10 : 5 : 5/2 10 : 5 : 5 : 5/2 10 to 13.333 50 to 66.67 10 to 13.333 50 to 66.67 100 to 100 to 133.33 133.33 100 to 50 to 66.67 50 to 66.67 25 to 33.33 50 to 66.67 50 to 66.67 25 to 33.33 133.33 H'x335 ON (×20) Notes: 1. 2. 3. Caution: 5 : 5 : 5 : 5/2 10 to 13.333 50 to 66.67 50 to 66.67 x in the FRQCR register setting depends on the set value in bits 12, 13, and 14. The ratio of clock frequencies, where the input clock frequency is assumed to be 1. The frequency of the EXTAL pin input clock or the crystal resonator Do not use this LSI for frequency settings other than those in table 5.3. The SSCG function of the chip is switched on or off by the setting of the MD_CLK0 pin while the RES pin is being held low. The following table shows the correspondence between SSCG operation and pin settings. Note that the pin setting does not affect the PLL frequency multipliers and division ratios for individual clock signals. Table 5.4 SSCG Operation Setting MD_CLK0 Pin Setting SSCG Operation 0 Off 1 On R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 131 of 3092 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator 5.4 Register Descriptions Table 5.5 shows the register configuration of the clock pulse generator. Table 5.5 Register Configuration Register Name Abbreviation R/W Initial Value Address Frequency control register H'0335 H'FFFE0010 16 5.4.1 FRQCR R/W Access Size Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin during normal operation mode, release of bus mastership, change of gain of crystal oscillator for the XTAL pin, software standby mode, and standby mode cancellation. The register specifies the frequency division ratio for the CPU clock (I) and internal bus clock (B). FRQCR is accessed by word. Bit: Initial value: R/W: 15 14 13 - CKO EN2 CKOEN[1:0] 12 0 R 0 R/W 0 R/W 0 R/W 11 10 - - 0 R 0 R 9 8 7 6 - - 0 R 0 R IFC[1:0] 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 5 4 3 2 1 BFC[1:0] - - - - 0 R 1 R 0 R 1 R 1 R/W 1 R/W 0 This bit is always read as 0. The write value should always be 0. 14 CKOEN2 0 R/W Clock Output Enable 2 Specifies whether the CKIO pin outputs clock signals or is fixed to the low level when the gain of the crystal oscillator for the XTAL pin is changed. If this bit is set to 1, the CKIO pin is fixed to the low level when the gain of the crystal oscillator for the XTAL pin is changed. Therefore, the malfunction of an external circuit caused by an unstable CKIO clock while changing the gain of the crystal oscillator for the XTAL pin can be prevented. 0: Unstable clock output 1: Low-level output Page 132 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator Initial Value Bit Bit Name 13, 12 CKOEN[1:0] 00 R/W Description R/W Clock Output Enable These bits specify whether the CKIO pin outputs clock signals, or is set to a fixed level or high impedance (Hi-Z) during normal operation mode, release of bus mastership, deep standby mode, standby mode, or cancellation of standby mode. If these bits are set to 01, the CKIO pin is fixed at low during deep standby mode, software standby mode, or cancellation of software standby mode. Therefore, the malfunction of an external circuit caused by an unstable CKIO clock during cancellation of software standby mode can be prevented. Table 5.6 lists CKOEN[1:0] settings. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 IFC[1:0] 11 R/W CPU Clock Frequency Division Ratio These bits specify the frequency division ratio of the CPU clock with respect to the output frequency of PLL circuit. 00: 1 time 01: 1/2 time 10: Reserved (setting prohibited) 11: 1/4 time 7, 6  0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 BFC[1:0] 11 R/W Internal Bus Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal bus clock with respect to the output frequency of PLL circuit. 00: Reserved (setting prohibited) 01: 1/2 time 10: Reserved (setting prohibited) 11: 1/4 time 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 133 of 3092 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 2  1 R Reserved This bit is always read as 1. The write value should always be 1.  1 0 R Reserved This bit is always read as 0. The write value should always be 0.  0 1 R Reserved This bit is always read as 1. The write value should always be 1. Table 5.6 CKOEN[1:0] Settings Setting Normal Operation Release of Bus Mastership Software Standby Mode Deep Standby Mode* 00 Output Output off (Hi-Z) Output off (Hi-Z) Output off (Hi-Z) 01 Output Output Low-level output Low-level output 10 Output Output Output (unstable clock output) Low-level or high-level output Output off (Hi-Z) Output off (Hi-Z) Output off (Hi-Z) Output off (Hi-Z) 11 Note: * Note that the first cycle of the output CKIO clock may be missing after release from deep standby. Page 134 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 5.5 Section 5 Clock Pulse Generator Changing the Frequency The frequency of the CPU clock (I) and internal bus clock (B) can be changed by changing the division rate of divider. The division rate can be changed by software through the frequency control register (FRQCR). 5.5.1 Changing the Division Ratio The division rate of divider can be changed by the following operation. 1. In the initial state, IFC[1:0]  B'11 and BFC[1:0] = B'11. 2. Set the desired value in the IFC[1:0] and BFC[1:0] bits. Note that if the wrong value is set, this LSI will malfunction. 3. After the register bits (IFC[1:0] and BFC[1:0]) have been set, the clock is supplied of the new division ratio. Note: When executing the SLEEP instruction after the frequency has been changed, be sure to read the frequency control register (FRQCR) three times before executing the SLEEP instruction. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 135 of 3092 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator 5.6 Usage of the Clock Pins For the connection of a crystal resonator or the input of a clock signal, this LSI circuit has the pins listed in table 5.7. With regard to these pins, take care on the following points. Furthermore, Xin pin and Xout pin are used in this section to refer to the pins listed in the table. Table 5.7 Clock Pins Xin Pins (Used for Connection of a Crystal Resonator Xout Pins and Input of External Clock Signals) (Used for Connection of a Crystal Resonator) EXTAL XTAL USB_X1 USB_X2 AUDIO_X1 AUDIO_X2 RTC_X1 RTC_X2 VIDEO_X1 VIDEO_X2 5.6.1 In the Case of Inputting an External Clock An example of the connection of an external clock is shown in figure 5.2. In cases where the Xout pin is left open state, take the parasitic capacitance as less than 10 pF. This LSI External clock input Xin Open state Xout Figure 5.2 Example of the Connection of an External Clock Page 136 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 5.6.2 Section 5 Clock Pulse Generator In the Case of Using a Crystal Resonator An example of the connection of crystal resonator is shown in figure 5.3. Place the crystal resonator and capacitors (CL1 and CL2) as close to pins Xin and Xout as possible. Furthermore, to avoid inductance so that oscillation is correct, use the points where the capacitors are connected to the crystal resonator in common and do not place wiring patterns close to these components. Since the design of the user board is closely connected with the effective characteristics of the crystal resonator, refer to the example of connection of the crystal resonator that is introduced in this section and perform thorough evaluation on the user side as well. The rated value of the crystal resonator will vary with the floating capacitances and so on of the crystal resonator and mounted circuit, so proceed with decisions on the basis of full discussions with the maker of the crystal resonator. Ensure that voltages applied to the clock pins do not exceed the maximum rated values. Although the feedback resistor is included in this LSI, an external feedback resistor may be required in some cases. This depends on the characteristics of the crystal resonator. Set the parameters (of resistors and capacitors) with thorough evaluation on the user side. This LSI CL1 Xin Crystal resonator CL2 ROF RIF Xout ROD RID To internal sections Figure 5.3 Example of the Connection of a Crystal Resonator 5.6.3 In the Case of Not Using the Clock Pin In cases where the pins are not in use, fix the level on the Xin pin (pull it up or down, or connect it to the power-supply or ground level), and leave the Xout pin open state. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 137 of 3092 Section 5 Clock Pulse Generator SH7268 Group, SH7269 Group 5.7 Oscillation Stabilizing Time 5.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator In the case of using a crystal resonator, please wait longer than the oscillation stabilizing time at the following cases, to keep the oscillation stabilizing time of the on-chip crystal oscillator (In the case of inputting an external clock input, it is not necessary).  Power on  Releasing the software standby mode or deep standby mode by RES pin  Changing from halting oscillation to running oscillation by power-on reset or register setting (AUDIO_X1, RTC_X1)  Changing the gain of the on-chip crystal oscillator by RES pin (EXTAL) 5.7.2 Oscillation Stabilizing Time of the PLL circuit The clock from EXTAL is supplied to the PLL circuit. So, regardless of whether using a crystal resonator or inputting an external clock from EXTAL, please wait longer than the oscillation stabilizing time at the following cases, to keep the oscillation stabilizing time of the PLL circuit.  Power on (in the case of using the crystal resonator)/start inputting external clock (in the case of inputting the external clock)  Releasing the software standby mode or deep standby mode by RES pin [Remarks] The oscillation stabilizing time is kept by the counter running in the LSI at the following cases.  Releasing the software standby mode or deep standby mode by the other than RES pin  Changing the gain of the on-chip crystal oscillator by the register setting (EXTAL) Page 138 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 5.8 Notes on Board Design 5.8.1 Note on Using a PLL Oscillation Circuit Section 5 Clock Pulse Generator In the PLLVcc connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interferences. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pins and the digital power supply pins Vcc and PVcc should not supply the same resources on the board if at all possible. Ensure that PLLVcc has the same electric potential as PVcc. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 139 of 3092 SH7268 Group, SH7269 Group Section 5 Clock Pulse Generator 5.9 Definition of Modulation Rate and Frequency in the SSCG Specification The SSCG circuit can be used to decrease the peak value of electromagnetic interference noise by frequency modulation, i.e. by slightly modulating the output frequency. In this case, the rate of change in the frequency and the size of the change to the input clock frequency are defined as the modulation rate and modulation frequency, respectively. Figure 5.4 shows the modulation rate and modulation frequency. Frequency Output signal 1/modulation frequency Center frequency (f0) Time (f0 -2.5%) Modulation rate Figure 5.4 Definition of SSCG Modulation Rate and Frequency Page 140 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 6 Exception Handling Section 6 Exception Handling 6.1 Overview 6.1.1 Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 6.1 shows their priorities. When several exception handling sources occur at once, they are processed according to the priority shown. Table 6.1 Types of Exception Handling and Priority Order Type Exception Handling Priority Reset Power-on reset High Manual reset Address error CPU address error DMA address error Instruction FPU exception Integer division exception (division by zero) Integer division exception (overflow) Register bank error Bank underflow Interrupt NMI Bank overflow User break User debugging interface IRQ PINT R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Low Page 141 of 3092 SH7268 Group, SH7269 Group Section 6 Exception Handling Type Exception Handling Priority Instruction Trap instruction (TRAPA instruction) High General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed branch instruction*1 (including FPU instructions and FPU-related CPU instructions in FPU module standby state), instructions that rewrite the 2 3 PC* , 32-bit instructions* , RESBANK instruction, DIVS instruction, and DIVU instruction) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N. 3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. 6.1.2 Exception Handling Operations The exception handling sources are detected and start processing according to the timing shown in table 6.2. Table 6.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Timing of Source Detection and Start of Handling Reset Power-on reset Starts when the RES pin changes from low to high, when the user debugging interface reset negate command is set after the user debugging interface reset assert command has been set, or when the watchdog timer overflows. Manual reset Starts when the watchdog timer overflows. Address error Interrupts Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Register bank Bank underflow error Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. Bank overflow Page 142 of 3092 In the state where saving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the interrupt controller is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 6 Exception Handling Exception Source Timing of Source Detection and Start of Handling Instructions Trap instruction Starts from the execution of a TRAPA instruction. General illegal instructions Starts from the decoding of undefined code anytime except immediately after a delayed branch instruction (delay slot) (including FPU instructions and FPU-related CPU instructions in FPU module standby state). Slot illegal instructions Starts from the decoding of undefined code placed directly after a delayed branch instruction (delay slot) (including FPU instructions and FPU-related CPU instructions in FPU module standby state), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Integer division exceptions Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value (H'80000000) by 1. FPU exceptions Starts when detecting invalid floating point operation exception defined by IEEE standard 754, division-by-zero exception, overflow, underflow, or inexact exception. Instructions Also starts when qNaN or  is input to the source for a floating point operation instruction when the QIS bit in FPSCR is set. When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 6.1.3, Exception Handling Vector Table, for more information. The vector base register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of the interrupt controller is also initialized to 0. The floating point status/control register (FPSCR) is initialized to H'00040001 by a power-on reset. The program begins running from the PC address fetched from the exception handling vector table. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 143 of 3092 Section 6 Exception Handling (2) SH7268 Group, SH7269 Group Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts, and Instructions SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling other than NMI and user break with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved to the register banks. In the case of exception handling due to address errors, register bank errors, NMI interrupts, user break interrupts, or instructions, saving to a register bank is not performed. When saving is performed to all register banks, automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the interrupt controller is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the interrupt controller is 1), register bank overflow exception will be generated. In the case of interrupt exception handling, the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start address is then fetched from the exception handling vector table and the program begins running from that address. 6.1.3 Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception handling, the start addresses of the exception service routines are fetched from the exception handling vector table, which is indicated by this vector table address. Page 144 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 6 Exception Handling Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector table addresses are calculated. Table 6.3 Exception Handling Vector Table Vector Numbers Vector Table Address Offset PC 0 H'00000000 to H'00000003 SP 1 H'00000004 to H'00000007 PC 2 H'00000008 to H'0000000B SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved by system) 5 H'00000014 to H'00000017 Slot illegal instruction 6 H'00000018 to H'0000001B (Reserved by system) 7 H'0000001C to H'0000001F 8 H'00000020 to H'00000023 CPU address error 9 H'00000024 to H'00000027 DMA address error 10 H'00000028 to H'0000002B NMI 11 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 FPU exception 13 H'00000034 to H'00000037 User debugging interface 14 H'00000038 to H'0000003B Bank overflow 15 H'0000003C to H'0000003F Bank underflow 16 H'00000040 to H'00000043 Integer division exception (division by zero) 17 H'00000044 to H'00000047 Integer division exception (overflow) 18 H'00000048 to H'0000004B (Reserved by system) 19 H'0000004C to H'0000004F Exception Sources Power-on reset Manual reset Interrupts : Trap instruction (user vector) 31 H'0000007C to H'0000007F 32 H'00000080 to H'00000083 : 63 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 : : H'000000FC to H'000000FF Page 145 of 3092 SH7268 Group, SH7269 Group Section 6 Exception Handling Exception Sources External interrupts (IRQ, PINT), on-chip peripheral module interrupts* Vector Numbers Vector Table Address Offset 64 H'00000100 to H'00000103 : 511 Note: * Table 6.4 : H'000007FC to H'000007FF The vector numbers and vector table address offsets for each external interrupt and onchip peripheral module interrupt are given in table 7.4 in section 7, Interrupt Controller. Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number)  4 Address errors, register bank errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number)  4 Notes: 1. Vector table address offset: See table 6.3. 2. Vector number: See table 6.3. Page 146 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.2 Resets 6.2.1 Input/Output Pins Section 6 Exception Handling Table 6.5 shows the pin configuration. Table 6.5 Pin Configuration Pin Name Symbol I/O Function Power-on reset RES Input When this pin is driven low, this LSI shifts to the poweron reset processing 6.2.2 Types of Reset A reset is the highest-priority exception handling source. There are two kinds of reset, power-on and manual. As shown in table 6.6, the CPU state is initialized in both a power-on reset and a manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip peripheral module registers except a few registers are also initialized by a power-on reset, but not by a manual reset. Table 6.6 Reset States Conditions for Transition to Reset State Internal States On-Chip Large- Watchdog User Debugging On-Chip Timer Capacity RAM On-Chip (Excluding Data Other High-Speed On-Chip Data Retention Modules RAM RAM Type RES Interface Command Overflow CPU Power- Low   Initialized Initialized Initialized or Initialized or on reset High User debugging  Retention RAM) Initialized or Retained Retained Retained contents*2 contents*3 contents*4, *5 Initialized Initialized Initialized or Initialized or Initialized or interface reset assert Retained Retained Retained command is set contents*2 contents*3 contents*4 High Command other than user debugging Power-on Initialized * 1 reset interface reset assert is Initialized or Initialized or Initialized or Retained Retained Retained contents*2 contents*3 contents*4 Retained Retained contents set Manual reset High Command other than user debugging Manual reset Initialized *1 contents Retained contents interface reset assert is set R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 147 of 3092 Section 6 Exception Handling SH7268 Group, SH7269 Group Notes: 1. 2. 3. 4. See section 51.3, Register States in Each Operating Mode. Data are retained when the setting of either the RAME or RAMWE bit is disabled. Data are retained when the setting of either the VRAME or VRAMWE bit is disabled. Data are retained when the setting of any of the VRAME, VRAMWE, or RRAMWE bits is disabled. 5. When the deep standby mode is canceled by a power-on reset, the data cannot be retained. Page 148 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.2.3 (1) Section 6 Exception Handling Power-On Reset Power-On Reset by Means of RES Pin When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc when the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip peripheral module registers are initialized. See section 53.1, Pin States, for the status of individual pins during the power-on reset state. In the power-on reset state, power-on reset exception handling starts when the RES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of the interrupt controller is also initialized to 0. FPSCR is initialized to H'00040001 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. (2) Power-On Reset by Means of User Debugging Interface Reset Assert Command When the user debugging interface reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of the user debugging interface reset assert command is equivalent to power-on reset by means of the RES pin. Setting the user debugging interface reset negate command cancels the power-on reset state. The time required between the user debugging interface reset assert command and the user debugging interface reset negate command is the same as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state generated by the user debugging interface reset assert command, setting the user debugging interface reset negate command starts power-on reset exception handling. The CPU operates in the same way as when a power-on reset was caused by the RES pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 149 of 3092 Section 6 Exception Handling (3) SH7268 Group, SH7269 Group Power-On Reset Initiated by Watchdog Timer When a setting is made for a power-on reset to be generated in watchdog timer mode of the watchdog timer, and WTCNT of the watchdog timer overflows, this LSI enters the power-on reset state. In this case, WRCSR of the watchdog timer and FRQCR of the clock pulse generator are not initialized by the reset signal generated by the watchdog timer. If a reset caused by the RES pin or the user debugging interface reset assert command occurs simultaneously with a reset caused by watchdog timer overflow, the reset caused by the RES pin or the user debugging interface reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the watchdog timer, the CPU operates in the same way as when a power-on reset was caused by the RES pin. 6.2.4 (1) Manual Reset Manual Reset Initiated by Watchdog Timer When a setting is made for a manual reset to be generated in watchdog timer mode of the watchdog timer, and WTCNT of the watchdog timer overflows, this LSI enters the manual reset state. When manual reset exception processing is started by the watchdog timer, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of interrupt controller is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Page 150 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 6 Exception Handling Note in Manual Reset When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during burst transfer by the direct memory access controller, manual reset exception handling will be deferred until the CPU acquires the bus. The CPU and the BN bit in IBNR of the interrupt controller are initialized by a manual reset. The FPU and other modules are not initialized. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 151 of 3092 SH7268 Group, SH7269 Group Section 6 Exception Handling 6.3 Address Errors 6.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 6.7. Table 6.7 Bus Cycles and Address Errors Bus Cycle Bus Master Type Instruction fetch CPU Data read/write Note: * CPU or direct memory access controller Bus Cycle Description Address Errors Instruction fetched from even address None (normal) Instruction fetched from odd address Address error occurs Instruction fetched from other than on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* None (normal) Instruction fetched from on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Address error occurs Word data accessed from even address None (normal) Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs Double longword data accessed from double longword boundary None (normal) Double longword data accessed from other than double longword boundary Address error occurs Byte or word data accessed in on-chip peripheral module space* None (normal) Longword data accessed in 16-bit on-chip peripheral module space* None (normal) Longword data accessed in 8-bit on-chip peripheral module space* None (normal) See section 10, Bus State Controller, for details of the on-chip peripheral module space and on-chip RAM space. Page 152 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.3.2 Section 6 Exception Handling Address Error Exception Handling When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the address error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 6.4 Register Bank Errors 6.4.1 Register Bank Error Sources (1) Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the interrupt controller is set to 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. (2) Bank Underflow Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving has not been performed to register banks. 6.4.2 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a bank overflow, and the start address of the executed RESBANK instruction for a bank underflow. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 153 of 3092 Section 6 Exception Handling SH7268 Group, SH7269 Group To prevent multiple interrupts from occurring at a bank overflow, the priority level of the interrupt that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 6.5 Interrupts 6.5.1 Interrupt Sources The sources that start interrupt exception handling are divided into NMI, user break, user debugging interface, IRQ, PINT, and on-chip peripheral modules. Each interrupt source is allocated a different vector number and vector table offset. See table 7.4 in section 7, Interrupt Controller, for more information on vector numbers and vector table address offsets. Page 154 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.5.2 Section 6 Exception Handling Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller determines their relative priorities and starts exception handling according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of user break and user debugging interface interrupts is 15. Priority levels of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt priority registers 01, 02, and 05 to 26 (IPR01, IPR02, and IPR05 to IPR26) of the interrupt controller as shown in table 6.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 7.3.1, Interrupt Priority Registers 01, 02, 05 to 26 (IPR01, IPR02, IPR05 to IPR26), for details of IPR01, IPR02, and IPR05 to IPR26. Table 6.8 Interrupt Priority Order Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. User debugging interface 15 Fixed priority level. IRQ 0 to 15 Set with interrupt priority registers 01, 02, and 05 to 26 (IPR01, IPR02, and IPR05 to IPR26). PINT On-chip peripheral module R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 155 of 3092 Section 6 Exception Handling 6.5.3 SH7268 Group, SH7269 Group Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR). When an interrupt is accepted, interrupt exception handling begins. In interrupt exception handling, the CPU fetches the exception service routine start address which corresponds to the accepted interrupt from the exception handling vector table, and saves SR and the program counter (PC) to the stack. In the case of interrupt exception handling other than NMI and user break with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved in the register banks. In the case of exception handling due to address errors, NMI interrupts, user break interrupts, or instructions, saving is not performed to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the interrupt controller is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the interrupt controller is 1), register bank overflow exception occurs. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. See section 7.6, Operation, for further details of interrupt exception handling. Page 156 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 6 Exception Handling 6.6 Exceptions Triggered by Instructions 6.6.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, integer division exceptions, and FPU exceptions, as shown in table 6.9. Table 6.9 Types of Exceptions Triggered by Instructions Type Source Instruction Trap instruction TRAPA Slot illegal instructions Undefined code placed immediately after a delayed branch instruction (delay slot) (including FPU instructions and FPU-related CPU instructions in FPU module standby state), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. General illegal instructions Undefined code anywhere besides in a delay slot (including FPU instructions and FPU-related CPU instructions in FPU module standby state) Integer division exceptions Division by zero DIVU, DIVS Negative maximum value  (1) DIVS FPU exceptions Starts when detecting invalid FADD, FSUB, FMUL, FDIV, FMAC, operation exception defined by FCMP/EQ, FCMP/GT, FLOAT, FTRC, IEEE754, division-by-zero FCNVDS, FCNVSD, FSQRT exception, overflow, underflow, or inexact exception. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 157 of 3092 Section 6 Exception Handling 6.6.2 SH7268 Group, SH7269 Group Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 6.6.3 Slot Illegal Instructions An instruction placed immediately after a delayed branch instruction is called the “instruction placed in a delay slot”. When the instruction placed in the delay slot is undefined code (including FPU instructions and FPU-related CPU instructions in FPU module standby state), an instruction that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded. When the FPU has entered a module standby state, the floating point operation instruction and FPU-related CPU instructions are handled as undefined codes. If these instructions are placed in a delay slot and then decoded, a slot illegal instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code, the instruction that rewrites the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Page 158 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.6.4 Section 6 Exception Handling General Illegal Instructions When an undefined code, including FPU instructions and FPU-related CPU instructions in FPU module standby state, placed anywhere other than immediately after a delayed branch instruction, i.e., in a delay slot, is decoded, general illegal instruction exception handling starts. When the FPU has entered a module standby state, the floating point instruction and FPU-related CPU instructions are handled as undefined codes. If these instructions are placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) and then decoded, general illegal instruction exception handling starts. In general illegal instruction exception handling, the CPU handles general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot illegal instructions, however, the program counter value stored is the start address of the undefined code. 6.6.5 Integer Division Exceptions When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception are DIVU and DIVS. The only source instruction of overflow exception is DIVS, and overflow exception occurs only when the negative maximum value is divided by 1. The CPU operates as follows: 1. The exception service routine start address which corresponds to the integer division exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the integer division instruction at which the exception occurred. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 159 of 3092 Section 6 Exception Handling 6.6.6 SH7268 Group, SH7269 Group FPU Exceptions An FPU exception handling is generated when the V, Z, O, U or I bit in the FPU exception enable field (Enable) of the floating point status/control register (FPSCR) is set. This indicates the occurrence of an invalid operation exception defined by the IEEE standard 754, a division-by-zero exception, overflow (in the case of an instruction for which this is possible), underflow (in the case of an instruction for which this is possible), or inexact exception (in the case of an instruction for which this is possible). The floating point operation instructions that may cause an FPU exception handling are FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and FSQRT. An FPU exception handling is generated only when the corresponding FPU exception enable bit (Enable) is set. When the FPU detects an exception source in floating point operation, FPU operation is halted and generation of an FPU exception handling is reported to the CPU. When exception handling is started, the CPU operations are as follows. 1. The start address of the exception service routine which corresponds to the FPU exception handling that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. This jump is not a delayed branch. The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an FPU exception handling has been accepted, and remains set until explicitly cleared by the user through an instruction. The FPU exception source field (Cause) of FPSCR changes each time a floating point operation instruction is executed. When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in FPSCR is also set, FPU exception handling is generated when qNAN or  is input to a floating point operation instruction source. Page 160 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.7 Section 6 Exception Handling When Exception Sources Are Not Accepted When an address error, FPU exception, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 6.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 6.10 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction* Note: * 6.8 Address Error Floating-Point Unit Register Bank Exception Error (Overflow) Interrupt Not accepted Not accepted Not accepted Not accepted Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 6.11. Table 6.11 Stack Status after Exception Handling Ends Exception Type Stack Status Address error SP Address of instruction after executed instruction 32 bits SR 32 bits Address of instruction after executed instruction 32 bits SR 32 bits Interrupt SP R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 161 of 3092 SH7268 Group, SH7269 Group Section 6 Exception Handling Exception Type Stack Status Register bank error (overflow) SP Address of instruction after executed instruction 32 bits SR 32 bits Start address of relevant RESBANK instruction 32 bits SR 32 bits Address of instruction after TRAPA instruction 32 bits SR 32 bits Jump destination address of delayed branch instruction 32 bits SR 32 bits Start address of general illegal instruction 32 bits SR 32 bits Start address of relevant integer division instruction 32 bits SR 32 bits Address of instruction after executed instruction 32 bits SR 32 bits Register bank error (underflow) SP Trap instruction SP Slot illegal instruction SP General illegal instruction SP Integer division exception SP FPU exception SP Page 162 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 6.9 Usage Notes 6.9.1 Value of Stack Pointer (SP) Section 6 Exception Handling The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 6.9.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.) and address error exception handling will start up as soon as the first exception handling is ended. Address errors will then also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. 6.9.4 Interrupt Control via Modification of Interrupt Mask Bits When enabling interrupts by changing the interrupt mask bits (I3 to I0) of the status register (SR) using the LDC or LDC.L instructions, interrupts might not be accepted during the execution of the 5 instructions immediately after the LDC/LDC.L instruction. Therefore, when enabling/disabling interrupts by changing the interrupt mask bits (I3 to I0) of the status register (SR) using LDC/LDC.L instructions, please place at least 5 instructions between the interrupt-enable instruction and the interrupt-disable instruction. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 163 of 3092 Section 6 Exception Handling 6.9.5 SH7268 Group, SH7269 Group Note before Exception Handling Begins Running Before exception handling begins running, the exception handling vector table must be stored in a memory, and the CPU must be able to access the memory. So, if the exception handling is generated  Ex. 1: when the exception handling vector table is stored in an external address space, but the settings of bus state controller and general I/O ports to access the external address space have been not completed yet, or  Ex. 2: when the exception handling vector table is stored in the on-chip RAM, but the vector base register (VBR) has been not changed to the on-chip RAM address yet, the CPU fetches an unintended value as the execution start address, and starts executing programs from unintended address. (1) Manual Reset Before the settings necessary to access the external CS0 space are completed, the manual reset should not be generated. When a manual reset is generated, the CPU fetches the execution start address from the location at the offset for the manual reset (H'00000008) in the vector table, that is, always from the external CS0 space. Additionally, in the case that no memory is connected to the external CS0 space in boot modes 2 to 5, the manual reset should not be generated. (2) NMI Interrupt Before the exception handling vector table is stored in a memory and the settings necessary to access the memory are completed, the settings to permit the interrupts should not be done. Specially in boot modes 2 to 5, the VBR is kept as the initial value H'00000000 in the period of the boot operation (before the transfer of the loader program is completed and the CPU jumps to the on-chip high-speed RAM). Before the VBR is changed or the settings necessary to access the external address space are completed in the loader program, the settings to permit the interrupts should not be done. (3) Interrupts Other Than NMI Before the exception handling vector table is stored in a memory and the settings necessary to access the memory are completed, the settings to permit the interrupts should not be done. Page 164 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 6 Exception Handling The Other Exceptions Before the exception handling vector table is stored in a memory and the settings necessary to access the memory are completed, the exception handling should not be generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 165 of 3092 Section 6 Exception Handling Page 166 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Section 7 Interrupt Controller The interrupt controller ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The interrupt controller registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 7.1 Features  16 levels of interrupt priority can be set. By setting the 24 interrupt priority registers, the priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request sources.  NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as the noise canceler function.  Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 167 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Figure 7.1 shows a block diagram. NMI IRQ7 to IRQ0 PINT7 to PINT0 Direct memory access controller USB 2.0 host/function module Video display controller 4 Compare match timer Bus state controller Watchdog timer Multi-function timer pulse unit 2 Motor control PWM timer A/D converter Serial sound interface Renesas SPDIF interface I2C bus interface 3 Serial communication interface with FIFO Serial I/O with FIFO Renesas serial peripheral interface Controller area network IEBusTM controller CD-ROM decoder NAND flash memory controller SD host interface Realtime clock Sampling rate converter Renesas quad serial peripheral interface User break Image renderer JPEG codec unit Display out comparison unit OpenVGTM-compliant Renesas graphics processor MMC host interface Sound generator Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Comparator SR I3 I2 I1 I0 CPU Priority identifier ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR IPR01, IPR02, IPR05 to IPR26 Bus interface Interrupt controller Peripheral bus Module bus [Legend] ICR0: ICR1: ICR2: IRQRR: PINTER: PIRR: IBCR: IBNR: IPR01, IPR02, IPR05 to IPR26: Interrupt request Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register PINT interrupt enable register PINT interrupt request register Bank control register Bank number register Interrupt priority registers 01, 02, 05 to 26 Figure 7.1 Block Diagram Page 168 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.2 Section 7 Interrupt Controller Input/Output Pins Table 7.1 shows the pin configuration. Table 7.1 Pin Configuration Pin Name Symbol I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt request input pins IRQ7 to IRQ0 Input Input of maskable interrupt request signals PINT7 to PINT0 Input R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 169 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.3 Register Descriptions Table 7.2 shows the register configuration. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 7.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Interrupt control register 0 ICR0 R/W *1 H'FFFE0800 16, 32 Interrupt control register 1 ICR1 R/W H'0000 H'FFFE0802 16, 32 Interrupt control register 2 ICR2 R/W H'0000 H'FFFE0804 16, 32 H'0000 H'FFFE0806 16, 32 2 IRQ interrupt request register IRQRR R/(W)* PINT interrupt enable register PINTER R/W H'0000 H'FFFE0808 16, 32 PINT interrupt request register PIRR R H'0000 H'FFFE080A 16, 32 Bank control register IBCR R/W H'0000 H'FFFE080C 16, 32 Bank number register IBNR R/W H'0000 H'FFFE080E 16, 32 Interrupt priority register 01 IPR01 R/W H'0000 H'FFFE0818 16, 32 Interrupt priority register 02 IPR02 R/W H'0000 H'FFFE081A 16, 32 Interrupt priority register 05 IPR05 R/W H'0000 H'FFFE0820 16, 32 Interrupt priority register 06 IPR06 R/W H'0000 H'FFFE0C00 16, 32 Interrupt priority register 07 IPR07 R/W H'0000 H'FFFE0C02 16, 32 Interrupt priority register 08 IPR08 R/W H'0000 H'FFFE0C04 16, 32 Interrupt priority register 09 IPR09 R/W H'0000 H'FFFE0C06 16, 32 Interrupt priority register 10 IPR10 R/W H'0000 H'FFFE0C08 16, 32 Interrupt priority register 11 IPR11 R/W H'0000 H'FFFE0C0A 16, 32 Interrupt priority register 12 IPR12 R/W H'0000 H'FFFE0C0C 16, 32 Interrupt priority register 13 IPR13 R/W H'0000 H'FFFE0C0E 16, 32 Interrupt priority register 14 IPR14 R/W H'0000 H'FFFE0C10 16, 32 Interrupt priority register 15 IPR15 R/W H'0000 H'FFFE0C12 16, 32 Interrupt priority register 16 IPR16 R/W H'0000 H'FFFE0C14 16, 32 Interrupt priority register 17 IPR17 R/W H'0000 H'FFFE0C16 16, 32 Interrupt priority register 18 IPR18 R/W H'0000 H'FFFE0C18 16, 32 Interrupt priority register 19 IPR19 R/W H'0000 H'FFFE0C1A 16, 32 Interrupt priority register 20 IPR20 R/W H'0000 H'FFFE0C1C 16, 32 Page 170 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Register Name Abbreviation R/W Initial Value Address Access Size Interrupt priority register 21 IPR21 R/W H'0000 H'FFFE0C1E 16, 32 Interrupt priority register 22 IPR22 R/W H'0000 H'FFFE0C20 16, 32 Interrupt priority register 23 IPR23 R/W H'0000 H'FFFE0C22 16, 32 Interrupt priority register 24 IPR24 R/W H'0000 H'FFFE0C24 16, 32 Interrupt priority register 25 IPR25 R/W H'0000 H'FFFE0C26 16, 32 Interrupt priority register 26 IPR26 R/W H'0000 H'FFFE0C28 16, 32 Notes: 1. When the NMI pin is high, becomes H'8001; when low, becomes H'0001. 2. Only 0 can be written after reading 1, to clear the flag. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 171 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.3.1 Interrupt Priority Registers 01, 02, 05 to 26 (IPR01, IPR02, IPR05 to IPR26) IPR01, IPR02, and IPR05 to IPR26 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. Table 7.3 shows the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR05 to IPR26. Bit: Initial value: R/W: Table 7.3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR26 Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPR01 IRQ0 IRQ1 IRQ2 IRQ3 IPR02 IRQ4 IRQ5 IRQ6 IRQ7 IPR05 PINT7 to PINT0 Reserved Reserved Reserved IPR06 Direct memory access controller channel 0 Direct memory access controller channel 1 Direct memory access controller channel 2 Direct memory access controller channel 3 IPR07 Direct memory access controller channel 4 Direct memory access controller channel 5 Direct memory access controller channel 6 Direct memory access controller channel 7 IPR08 Direct memory access controller channel 8 Direct memory access controller channel 9 Direct memory access controller channel 10 Direct memory access controller channel 11 IPR09 Direct memory access controller channel 12 Direct memory access controller channel 13 Direct memory access controller channel 14 Direct memory access controller channel 15 IPR10 USB 2.0 host/function module Video display controller 4 Video display controller 4 Video display controller 4 IPR11 Image renderer JPEG codec unit Display out comparison unit OpenVGcompliant Renesas graphics processor Page 172 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPR12 Compare match timer channel 0 Compare match timer channel 1 Bus state controller Watchdog timer IPR13 Multi-function timer pulse unit 2 channel 0 (TGI0A to TGI0D) Multi-function timer pulse unit 2 channel 0 (TCI0V, TGI0E, TGI0F) Multi-function timer pulse unit 2 channel 1 (TGI1A, TGI1B) Multi-function timer pulse unit 2 channel 1 (TGI1V, TGI1U) IPR14 Multi-function timer pulse unit 2 channel 2 (TGI2A, TGI2B) Multi-function timer pulse unit 2 channel 2 (TGI2V, TGI2U) Multi-function timer pulse unit 2 channel 3 (TGI3A to TGI3D) Multi-function timer pulse unit 2 channel 3 (TGI3V) IPR15 Multi-function timer pulse unit 2 channel 4 (TGI4A to TGI4D) Multi-function timer Motor control pulse unit 2 PWM timer channel 4 channel 1 (TGI4V) Motor control PWM timer channel 2 IPR16 Sound generator channel 0 Sound generator channel 1 Sound generator channel 0 IPR17 A/D converter Serial sound Serial sound Serial sound interface channel 0 interface channel 1 interface channel 2 IPR18 Serial sound Serial sound Serial sound Renesas SPDIF interface channel 3 interface channel 4 interface channel 5 interface IPR19 I2C bus interface 3 I2C bus interface 3 I2C bus interface 3 I2C bus interface 3 channel 0 channel 1 channel 2 channel 3 IPR20 Channel 0 for serial communication interface with FIFO Channel 1 for serial communication interface with FIFO Channel 2 for serial communication interface with FIFO Channel 3 for serial communication interface with FIFO IPR21 Channel 4 for serial communication interface with FIFO Channel 5 for serial communication interface with FIFO Channel 6 for serial communication interface with FIFO Channel 7 for serial communication interface with FIFO IPR22 Clocksynchronized serial I/O module with FIFO Controller area Controller area Controller area network channel 0 network channel 1 network channel 2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Sound generator channel 2 Page 173 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Register Name Bits 15 to 12 IPR23 Renesas serial Renesas serial Renesas quad Renesas quad peripheral peripheral serial peripheral serial peripheral interface channel 0 interface channel 1 interface channel 0 interface channel 1 IPR24 IEBusTM controller CD-ROM decoder NAND flash MMC host memory controller interface IPR25 SD host interface channel 0 SD host interface channel 1 IPR26 Sampling rate Sampling rate Sampling rate Reserved converter channel converter channel converter channel 0 1 2 Page 174 of 3092 Bits 11 to 8 Bits 7 to 4 Realtime clock Bits 3 to 0 Reserved R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller As shown in table 7.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set. Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the highest level). 7.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMIL - - - - - - NMIE - - - - - - NMIF NMIM *1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W)*2 Notes: 1. 1 when the NMI pin is high, and 0 when the NMI pin is low. 2. Only 0 can be written to this bit. Bit Bit Name Initial Value R/W Description 15 NMIL * R NMI Input Level Sets the level of the signal input at the NMI pin. The NMI pin level can be obtained by reading this bit. This bit cannot be modified. 0: Low level is input to NMI pin 1: High level is input to NMI pin 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 175 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Bit Bit Name Initial Value R/W Description 1 NMIF 0 R NMI Interrupt Request This bit indicates the status of the NMI interrupt request. This bit cannot be modified. 0: NMI interrupt request has not occurred [Clearing conditions]  Cleared by changing NMIE of ICR0  Cleared by executing NMI interrupt exception handling 1: NMI interrupt request is detected [Setting condition]  0 NMIM 1 Edge corresponding to NMIE of ICR0 has occurred at NMI pin R/(W) NMI Mask *2 Selects whether to enable interrupt request input to external interrupt input pin NMI. 0: NMI input interrupt request is enabled 1: NMI input interrupt request is masked Page 176 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.3.3 Section 7 Interrupt Controller Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 IRQ71S 0 R/W IRQ Sense Select 14 IRQ70S 0 R/W 13 IRQ61S 0 R/W These bits select whether interrupt signals corresponding to pins IRQ7 to IRQ0 are detected by a low level, falling edge, rising edge, or both edges. 12 IRQ60S 0 R/W 11 IRQ51S 0 R/W 10 IRQ50S 0 R/W 9 IRQ41S 0 R/W 8 IRQ40S 0 R/W 7 IRQ31S 0 R/W 6 IRQ30S 0 R/W 5 IRQ21S 0 R/W 4 IRQ20S 0 R/W 3 IRQ11S 0 R/W 2 IRQ10S 0 R/W 1 IRQ01S 0 R/W 0 IRQ00S 0 R/W 00: Interrupt request is detected on low level of IRQn input 01: Interrupt request is detected on falling edge of IRQn input 10: Interrupt request is detected on rising edge of IRQn input 11: Interrupt request is detected on both edges of IRQn input [Legend] n = 7 to 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 177 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7 to PINT0 individually: low level or high level. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 PINT7S 0 R/W PINT Sense Select 6 PINT6S 0 R/W 5 PINT5S 0 R/W These bits select whether interrupt signals corresponding to pins PINT7 to PINT0 are detected by a low level or high level. 4 PINT4S 0 R/W 3 PINT3S 0 R/W 2 PINT2S 0 R/W 1 PINT1S 0 R/W 0 PINT0S 0 R/W 0: Interrupt request is detected on low level of PINTn input 1: Interrupt request is detected on high level of PINTn input [Legend] n = 7 to 0 Page 178 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.3.5 Section 7 Interrupt Controller IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W 15 to 8  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 R/(W)* IRQ Interrupt Request R/(W)* These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. R/(W)* Level detection: R/(W)* 0: IRQn interrupt request has not occurred R/(W)* [Clearing condition] R/(W)*  IRQn input is high R/(W)* 1: IRQn interrupt has occurred [Setting condition] R/(W)*  IRQn input is low Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions]  Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF  Cleared by executing IRQn interrupt exception handling 1: IRQn interrupt request is detected [Setting condition]  Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin [Legend] n = 7 to 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 179 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.3.6 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit register that enables interrupt request inputs to external interrupt input pins PINT7 to PINT0. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 PINT7E 0 R/W PINT Enable 6 PINT6E 0 R/W 5 PINT5E 0 R/W These bits select whether to enable interrupt request inputs to external interrupt input pins PINT7 to PINT0. 4 PINT4E 0 R/W 3 PINT3E 0 R/W 2 PINT2E 0 R/W 1 PINT1E 0 R/W 0 PINT0E 0 R/W 0: PINTn input interrupt request is disabled 1: PINTn input interrupt request is enabled [Legend] n = 7 to 0 Page 180 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.3.7 Section 7 Interrupt Controller PINT Interrupt Request Register (PIRR) PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 7 PINT7R 0 R PINT Interrupt Request 6 PINT6R 0 R 5 PINT5R 0 R These bits indicate the status of the PINT7 to PINT0 interrupt requests. 4 PINT4R 0 R 3 PINT3R 0 R 2 PINT2R 0 R 1 PINT1R 0 R 0 PINT0R 0 R 0: No interrupt request at PINTn pin 1: Interrupt request at PINTn pin [Legend] n = 7 to 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 181 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.3.8 Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 E15 0 R/W Enable 14 E14 0 R/W 13 E13 0 R/W 12 E12 0 R/W These bits enable or disable use of register banks for interrupt priority levels 15 to 1. However, use of the register bank is always disabled by a user break interrupt. 11 E11 0 R/W 0: Use of register banks is disabled 10 E10 0 R/W 1: Use of register banks is enabled 9 E9 0 R/W 8 E8 0 R/W 7 E7 0 R/W 6 E6 0 R/W 5 E5 0 R/W 4 E4 0 R/W 3 E3 0 R/W 2 E2 0 R/W 1 E1 0 R/W 0  0 R Bit: Reserved This bit is always read as 0. The write value should always be 0. Page 182 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.3.9 Section 7 Interrupt Controller Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to BN0. Bit: 15 14 BE[1:0] 0 R/W 13 12 11 10 9 8 7 6 5 4 BOVE - - - - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: 0 R/W Bit Bit Name Initial Value R/W Description 15, 14 BE[1:0] 00 R/W Register Bank Enable 3 2 1 0 BN[3:0] 0 R 0 R 0 R 0 R These bits enable or disable use of register banks. 00: Use of register banks is disabled for all interrupts. The setting of IBCR is ignored. 01: Use of register banks is enabled for all interrupts except NMI and user break. The setting of IBCR is ignored. 10: Reserved (setting prohibited) 11: Use of register banks is controlled by the setting of IBCR. 13 BOVE 0 R/W Register Bank Overflow Enable Enables of disables register bank overflow exception. 0: Generation of register bank overflow exception is disabled 1: Generation of register bank overflow exception is enabled 12 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 BN[3:0] 0000 R Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the register bank indicated by these bits, and BN is incremented by 1. After BN is decremented by 1 due to execution of a RESBANK (restore from register bank) instruction, restoration from the register bank is performed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 183 of 3092 Section 7 Interrupt Controller 7.4 SH7268 Group, SH7269 Group Interrupt Sources There are six types of interrupt sources: NMI, user break, user debugging interface, IRQ, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level 0, that interrupt is masked at all times. 7.4.1 NMI Interrupt The NMI interrupt has a priority level of 16 and is accepted at all times when the NMI mask bit (NMIM) in interrupt control register 0 (ICR0) is enabled. NMI interrupt requests are edgedetected, and the NMI edge select bit (NMIE) in ICR0 selects whether the rising edge or falling edge is detected. Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. When the NMIM bit in ICR0 is set to 1 (NMI interrupt request is masked), the NMI interrupt is not generated, however the NMI edge corresponding to NMIE bit of ICR0 is detected and the NMI interrupt request is retained until the interrupt request is accepted. The status of the interrupt request can be checked by reading the NMI interrupt request bit (NMIF) in the ICR0. If 0 is written to the NMIM bit (NMI interrupt request is enabled) when the NMIF bit is set to 1, the NMI interrupt request that is retained is accepted. Once the NMIM bit is set to 0 (NMI interrupt request is enabled), the NMIM bit cannot be set to 1 again, because only 0 can be written to the NMIM bit. When the NME bit is changed, the NMI interrupt request that is retained is cleared. When canceling software standby mode by the NMI interrupt, set the NMIM bit to 0 to enable the NMI interrupt request after confirming that the NMI interrupt request has been cleared in the NMIF. If software standby mode is entered when the NMIM bit is 1 (NMI interrupt request is masked), the NMI interrupt cannot cancel software standby mode. In this case, the NMI edge cannot be detected in software standby mode and the NMI interrupt is not generated even if software standby mode is canceled by cancel source other than NMI. When the NMI pin keeps level (low level after the falling edge or high level after the rising edge) in software standby mode until software standby mode is canceled by cancel source other than NMI (until the clock is initiated after the oscillation settling), that edge of the NMI in software standby mode can be detected. When deep standby mode is entered, deep standby mode is canceled by the NMI interrupt regardless of the NMI mask bit setting. NMIM bit is initialized by a power-on reset after canceling deep standby mode. When a sleep instruction is to be executed after 0 has been written to the NMIM bit (enabling the NMI), read the value of the NMIM bit before executing the sleep instruction. Page 184 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.4.2 Section 7 Interrupt Controller User Break Interrupt A user break interrupt which occurs when a break condition set in the user break controller matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user break interrupts, see section 8, User Break Controller. 7.4.3 User Debugging Interface Interrupt The user debugging interface interrupt has a priority level of 15, and occurs at serial input of a user debugging interface interrupt instruction. User debugging interface interrupt requests are edge-detected and retained until they are accepted. The user debugging interface interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user debugging interface interrupts, see section 50, User Debugging Interface. 7.4.4 IRQ Interrupts IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority registers 01 and 02 (IPR01 and IPR02). When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the interrupt controller while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the interrupt controller when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the interrupt controller. The result of IRQ interrupt request detection is retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request detection. The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted IRQ interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the IRQ interrupt request register (IRQRR) so as not to accidentally receive the interrupt request again. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 185 of 3092 Section 7 Interrupt Controller 7.4.5 SH7268 Group, SH7269 Group PINT Interrupts PINT interrupts are input from pins PINT7 to PINT0. Input of the interrupt requests is enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register (PINTER). For the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control register 2 (ICR2). A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0 interrupts by bits 15 to 12 in interrupt priority register 05 (IPR05). When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is sent to the interrupt controller while the PINT7 to PINT0 pins are low. An interrupt request signal is stopped being sent to the interrupt controller when the PINT7 to PINT0 pins are driven high. The status of the interrupt requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the PINT interrupt request register (PIRR). The above description also applies to when using high-level sensing, except for the polarity being reversed. The PINT interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the PINT interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the PINT interrupt request register (PIRR) so as not to accidentally receive the interrupt request again. Page 186 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.4.6 Section 7 Interrupt Controller On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:                              Direct memory access controller USB 2.0 host/function module Video display controller 4 Image renderer Display out comparison unit JPEG codec unit OpenVG-compliant Renesas graphics processor Compare match timer Bus state controller Watchdog timer Multi-function timer pulse unit 2 Motor control PWM timer Sound generator A/D converter Serial sound interface Renesas SPDIF interface I2C bus interface 3 Serial communication interface with FIFO Clock-synchronized serial I/O module with FIFO Renesas serial peripheral interface Renesas quad serial peripheral interface Controller area network IEBusTM controller CD-ROM decoder NAND flash memory controller SD host interface MMC host interface Realtime clock Sampling rate converter R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 187 of 3092 Section 7 Interrupt Controller SH7268 Group, SH7269 Group As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from 0 to 15 can be set for each module by interrupt priority registers 05 to 26 (IPR05 to IPR26). The on-chip peripheral module interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip peripheral module interrupt. Page 188 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.5 Section 7 Interrupt Controller Interrupt Exception Handling Vector Table and Priority Table 7.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and vector table address offsets. In interrupt exception handling, the interrupt exception service routine start address is fetched from the vector table indicated by the vector table address. For details of calculation of the vector table address, see table 6.4 in section 6, Exception Handling. The priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 26 (IPR01, IPR02, and IPR05 to IPR26). However, if two or more interrupts specified by the same IPR among IPR05 to IPR26 occur, the priorities are defined as shown in the IPR setting unit internal priority of table 7.4, and the priorities cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priorities indicated in table 7.4. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 189 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Table 7.4 Interrupt Exception Handling Vectors and Priorities Interrupt Vector Vector Table IPR Setting Interrupt Priority Corresponding IPR Unit Internal Interrupt Source Vector Address Offset (Initial Value) (Bit) Priority Default Priority NMI 11 16   High   15   0 to 15 (0) IPR01 (15 to 12)  0 to 15 (0) IPR01 (11 to 8)  0 to 15 (0) IPR01 (7 to 4)  0 to 15 (0) IPR01 (3 to 0)  0 to 15 (0) IPR02 (15 to 12)  0 to 15 (0) IPR02 (11 to 8)  0 to 15 (0) IPR02 (7 to 4)  0 to 15 (0) IPR02 (3 to 0)  0 to 15 (0) IPR05 (15 to 12) 1 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 User debug interface 14 H'00000038 to 15 H'0000003B IRQ IRQ0 64 H'00000100 to H'00000103 IRQ1 65 H'00000104 to H'00000107 IRQ2 66 H'00000108 to H'0000010B IRQ3 67 H'0000010C to H'0000010F IRQ4 68 H'00000110 to H'00000113 IRQ5 69 H'00000114 to H'00000117 IRQ6 70 H'00000118 to H'0000011B IRQ7 71 H'0000011C to H'0000011F PINT PINT0 80 H'00000140 to H'00000143 PINT1 81 H'00000144 to 2 H'00000147 PINT2 82 H'00000148 to 3 H'0000014B PINT3 83 H'0000014C to 4 H'0000014F PINT4 84 H'00000150 to H'00000153 Page 190 of 3092 5 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Vector Table IPR Setting Interrupt Priority Corresponding IPR Unit Internal Interrupt Source Vector Address Offset (Initial Value) (Bit) Priority Default Priority PINT 85 0 to 15 (0) IPR05 (15 to 12) 6 High PINT5 H'00000154 to H'00000157 PINT6 86 H'00000158 to 7 H'0000015B PINT7 87 H'0000015C to 8 H'0000015F Direct Channel 0 DEI0 108 memory H'000001B0 to 0 to 15 (0) IPR06 (15 to 12) 1 H'000001B3 access HEI0 109 controller H'000001B4 to 2 H'000001B7 Channel 1 DEI1 112 H'000001C0 to 0 to 15 (0) IPR06 (11 to 8) 1 H'000001C3 HEI1 113 H'000001C4 to 2 H'000001C7 Channel 2 DEI2 116 H'000001D0 to 0 to 15 (0) IPR06 (7 to 4) 1 H'000001D3 HEI2 117 H'000001D4 to 2 H'000001D7 Channel 3 DEI3 120 H'000001E0 to 0 to 15 (0) IPR06 (3 to 0) 1 H'000001E3 HEI3 121 H'000001E4 to 2 H'000001E7 Channel 4 DEI4 124 H'000001F0 to 0 to 15 (0) IPR07 (15 to 12) 1 H'000001F3 HEI4 125 H'000001F4 to 2 H'000001F7 Channel 5 DEI5 128 H'00000200 to 0 to 15 (0) IPR07 (11 to 8) 1 H'00000203 HEI5 129 H'00000204 to 2 H'00000207 Channel 6 DEI6 132 H'00000210 to 0 to 15 (0) IPR07 (7 to 4) 1 H'00000213 HEI6 133 H'00000214 to H'00000217 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 2 Low Page 191 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Interrupt Source Direct Channel 7 DEI7 IPR Setting Interrupt Priority Corresponding IPR Unit Internal Vector Address Offset (Initial Value) (Bit) Priority Default Priority 136 0 to 15 (0) IPR07 (3 to 0) 1 High Vector Table memory H'00000220 to H'00000223 access HEI7 137 controller H'00000224 to 2 H'00000227 Channel 8 DEI8 140 H'00000230 to 0 to 15 (0) IPR08 (15 to 12) 1 H'00000233 HEI8 141 H'00000234 to 2 H'00000237 Channel 9 DEI9 144 H'00000240 to 0 to 15 (0) IPR08 (11 to 8) 1 H'00000243 HEI9 145 H'00000244 to 2 H'00000247 Channel DEI10 148 10 H'00000250 to 0 to 15 (0) IPR08 (7 to 4) 1 H'00000253 HEI10 149 H'00000254 to 2 H'00000257 Channel DEI11 152 11 H'00000260 to 0 to 15 (0) IPR08 (3 to 0) 1 H'00000263 HEI11 153 H'00000264 to 2 H'00000267 Channel DEI12 156 12 H'00000270 to 0 to 15 (0) IPR09 (15 to 12) 1 H'00000273 HEI12 157 H'00000274 to 2 H'00000277 Channel DEI13 160 13 H'00000280 to 0 to 15 (0) IPR09 (11 to 8) 1 H'00000283 HEI13 161 H'00000284 to 2 H'00000287 Channel DEI14 164 14 H'00000290 to HEI14 165 H'00000294 to H'00000297 Page 192 of 3092 0 to 15 (0) IPR09 (7 to 4) 1 H'00000293 2 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Direct Channel memory 15 access DEI15 168 H'000002A0 to 0 to 15 (0) IPR09 (3 to 0) 1 High H'000002A3 HEI15 169 controller USB 2.0 Section 7 Interrupt Controller H'000002A4 to 2 H'000002A7 USBI 170 host/ H'000002A8 to 0 to 15 (0) IPR10 (15 to 12)  0 to 15 (0) IPR10 (11 to 8) 1 H'000002AB function module Video VI_VSYNC 171 display controller 4 H'000002AC to H'000002AF LO_VSYNC 172 H'000002B0 to 2 H'000002B3 VSYNCERR 173 H'000002B4 to 3 H'000002B7 VLINE 174 H'000002B8 to 0 to 15 (0) IPR10 (7 to 4) 1 H'000002BB VFIELD 175 H'000002BC to 2 H'000002BF VBUFERR1 176 H'000002C0 to 0 to 15 (0) IPR10 (3 to 0) 1 H'000002C3 VBUFERR2 177 H'000002C4 to 2 H'000002C7 VBUFERR3 178 H'000002C8 to 3 H'000002CB VBUFERR4 179 H'000002CC to 4 H'000002CF Image IMRI 180 renderer R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H'000002D0 to H'000002D3 0 to 15 (0) IPR11 (15 to 12)  Low Page 193 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Vector Table Address IPR Setting Interrupt Priority Corresponding IPR Unit Internal Interrupt Source Vector Offset (Initial Value) (Bit) Priority Default Priority JPEG 181 0 to 15 (0) IPR11 (11 to 8) 1 High JEDI codec unit H'000002D4 to H'000002D7 JDTI 182 H'000002D8 to 2 H'000002DB Display out CMPI 183 comparison H'000002DC to 0 to 15 (0) IPR11 (7 to 4)  0 to 15 (0) IPR11 (3 to 0) 1 H'000002DF unit OpenVG- INT3 184 compliant Renesas H'000002E0 to H'000002E3 INT2 185 graphics H'000002E4 to 2 H'000002E7 processor INT1 186 H'000002E8 to 3 H'000002EB INT0 187 H'000002EC to 4 H'000002EF Compare Channel match timer 0 Channel CMI0 188 CMI1 189 1 Bus state CMI H'000002F0 to 0 to 15 (0) IPR12 (15 to 12)  0 to 15 (0) IPR12 (11 to 8)  0 to 15 (0) IPR12 (7 to 4)  0 to 15 (0) IPR12 (3 to 0)  0 to 15 (0) IPR13 (15 to 12) 1 H'000002F3 H'000002F4 to H'000002F7 190 controller H'000002F8 to H'000002FB Watchdog timer ITI 191 H'000002FC to H'000002FF Multi- Channel function timer 0 pulse unit 2 TGI0A 192 H'00000300 to H'00000303 TGI0B 193 H'00000304 to 2 H'00000307 TGI0C 194 H'00000308 to 3 H'0000030B TGI0D 195 H'0000030C to H'0000030F Page 194 of 3092 4 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Vector Table Address Interrupt Source Multi- Channel function timer 0 pulse unit 2 Vector Offset TCI0V 196 H'00000310 to IPR Setting Interrupt Priority Corresponding IPR Unit Internal (Initial Value) (Bit) Priority Default Priority 0 to 15 (0) IPR13 (11 to 8) 1 High H'00000313 TGI0E 197 H'00000314 to 2 H'00000317 TGI0F 198 H'00000318 to 3 H'0000031B Channel TGI1A 199 1 H'0000031C to 0 to 15 (0) IPR13 (7 to 4) 1 H'0000031F TGI1B 200 H'00000320 to 2 H'00000323 TCI1V 201 H'00000324 to 0 to 15 (0) IPR13 (3 to 0) 1 H'00000327 TCI1U 202 H'00000328 to 2 H'0000032B Channel TGI2A 203 2 H'0000032C to 0 to 15 (0) IPR14 (15 to 12) 1 H'0000032F TGI2B 204 H'00000330 to 2 H'00000333 TCI2V 205 H'00000334 to 0 to 15 (0) IPR14 (11 to 8) 1 H'00000337 TCI2U 206 H'00000338 to 2 H'0000033B Channel TGI3A 207 3 H'0000033C to 0 to 15 (0) IPR14 (7 to 4) 1 H'0000033F TGI3B 208 H'00000340 to 2 H'00000343 TGI3C 209 H'00000344 to 3 H'00000347 TGI3D 210 H'00000348 to 4 H'0000034B TCI3V 211 H'0000034C to H'0000034F R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 to 15 (0) IPR14 (3 to 0)  Low Page 195 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Vector Table Address Interrupt Source Multi- Vector Offset Channel 4 TGI4A 212 function timer H'00000350 to IPR Setting Interrupt Priority Corresponding IPR Unit Internal Default (Initial Value) (Bit) Priority Priority 0 to 15 (0) IPR15 (15 to 12) 1 High H'00000353 pulse unit 2 TGI4B 213 H'00000354 to 2 H'00000357 TGI4C 214 H'00000358 to 3 H'0000035B TGI4D 215 H'0000035C to 4 H'0000035F TCI4V 216 H'00000360 to 0 to 15 (0) IPR15 (11 to 8)  0 to 15 (0) IPR15 (7 to 4)  0 to 15 (0) IPR15 (3 to 0)  0 to 15 (0) IPR16 (15 to 12)  0 to 15 (0) IPR16 (11 to 8)  0 to 15 (0) IPR16 (7 to 4)  0 to 15 (0) IPR16 (3 to 0)  0 to 15 (0) IPR17 (15 to 12)  H'00000363 Motor control Channel 1 217 PWM timer H'00000364 to H'00000367 Channel 2 218 H'00000368 to H'0000036B Sound Channel 0 219 generator H'0000036C to H'0000036F Channel 1 220 H'00000370 to H'00000373 Channel 2 221 H'00000374 to H'00000377 Channel 3 222 H'00000378 to H'0000037B A/D converter ADI 223 H'0000037C to H'0000037F Page 196 of 3092 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Interrupt Source Vector Serial 224 Channel 0 SSIF0 sound IPR Setting Vector Table Address Interrupt Priority Corresponding Unit Internal Offset (Initial Value) IPR (Bit) Priority Default Priority H'00000380 to 0 to 15 (0) IPR17 (11 to 8) 1 High H'00000383 interface SSIRXI0 225 H'00000384 to 2 H'00000387 SSITXI0 226 H'00000388 to 3 H'0000038B Channel 1 SSII1 227 H'0000038C to 0 to 15 (0) IPR17 (7 to 4) 1 H'0000038F SSIRTI1 228 H'00000390 to 2 H'00000393 Channel 2 SSII2 229 H'00000394 to 0 to 15 (0) IPR17 (3 to 0) 1 H'00000397 SSIRTI2 230 H'00000398 to 2 H'0000039B Channel 3 SSII3 231 H'0000039C to 0 to 15 (0) H'0000039F SSIRTI3 232 IPR18 (15 to 1 12) H'000003A0 to 2 H'000003A3 Channel 4 SSII4 233 H'000003A4 to 0 to 15 (0) IPR18 (11 to 8) 1 H'000003A7 SSIRTI4 234 H'000003A8 to 2 H'000003AB Channel 5 SSII5 235 H'000003AC to 0 to 15 (0) IPR18 (7 to 4) 1 H'000003AF SSIRTI5 236 H'000003B0 to 2 H'000003B3 Renesas SPDIFI SPDIF interface R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 237 H'000003B4 to 0 to 15 (0) IPR18 (3 to 0)  H'000003B7 Low Page 197 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Interrupt Source 2 I C bus Vector Channel 0 STPI0 238 interface 3 IPR Setting Vector Table Address Interrupt Priority Corresponding Unit Internal Offset (Initial Value) IPR (Bit) Priority Default Priority H'000003B8 to 0 to 15 (0) IPR19 (15 to 1 High H'000003BB NAKI0 239 12) H'000003BC to 2 H'000003BF RXI0 240 H'000003C0 to 3 H'000003C3 TXI0 241 H'000003C4 to 4 H'000003C7 TEI0 242 H'000003C8 to 5 H'000003CB Channel 1 STPI1 243 H'000003CC to 0 to 15 (0) IPR19 (11 to 8) 1 H'000003CF NAKI1 244 H'000003D0 to 2 H'000003D3 RXI1 245 H'000003D4 to 3 H'000003D7 TXI1 246 H'000003D8 to 4 H'000003DB TEI1 247 H'000003DC to 5 H'000003DF Channel 2 STPI2 248 H'000003E0 to 0 to 15 (0) IPR19 (7 to 4) 1 H'000003E3 NAKI2 249 H'000003E4 to 2 H'000003E7 RXI2 250 H'000003E8 to 3 H'000003EB TXI2 251 H'000003EC to 4 H'000003EF TEI2 252 H'000003F0 to H'000003F3 Page 198 of 3092 5 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Vector Table Interrupt Source 2 I C bus Channel interface 3 3 STPI3 IPR Setting Interrupt Priority (Initial Corresponding Unit Internal Default Vector Address Offset Value) IPR (Bit) Priority Priority 253 0 to 15 (0) IPR19 (3 to 0) 1 High H'000003F4 to H'000003F7 NAKI3 254 H'000003F8 to 2 H'000003FB RXI3 255 H'000003FC to 3 H'000003FF TXI3 256 H'00000400 to 4 H'00000403 TEI3 257 H'00000404 to 5 H'00000407 Serial Channel communi- 0 cation interface BRI0 258 H'00000408 to 0 to 15 (0) IPR20 (15 to 12) 1 H'0000040B ERI0 259 with FIFO H'0000040C to 2 H'0000040F RXI0 260 H'00000410 to 3 H'00000413 TXI0 261 H'00000414 to 4 H'00000417 Channel BRI1 262 1 H'00000418 to 0 to 15 (0) IPR20 (11 to 8) 1 H'0000041B ERI1 263 H'0000041C to 2 H'0000041F RXI1 264 H'00000420 to 3 H'00000423 TXI1 265 H'00000424 to 4 H'00000427 Channel BRI2 266 2 H'00000428 to 0 to 15 (0) PR20 (7 to 4) 1 H'0000042B ERI2 267 H'0000042C to 2 H'0000042F RXI2 268 H'00000430 to 3 H'00000433 TXI2 269 H'00000434 to H'00000437 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 4 Low Page 199 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector Interrupt Source Serial Channel communi- 3 cation interface BRI3 IPR Setting Interrupt Priority (Initial Corresponding Unit Internal Default Vector Address Offset Value) IPR (Bit) Priority Priority 270 0 to 15 (0) PR20 (3 to 0) 1 High Vector Table H'00000438 to H'0000043B ERI3 271 with FIFO H'0000043C to 2 H'0000043F RXI3 272 H'00000440 to 3 H'00000443 TXI3 273 H'00000444 to 4 H'00000447 Channel BRI4 274 4 H'00000448 to 0 to 15 (0) IPR21 (15 to 12) 1 H'0000044B ERI4 275 H'0000044C to 2 H'0000044F RXI4 276 H'00000450 to 3 H'00000453 TXI4 277 H'00000454 to 4 H'00000457 Channel BRI5 278 5 H'00000458 to 0 to 15 (0) IPR21 (11 to 8) 1 H'0000045B ERI5 279 H'0000045C to 2 H'0000045F RXI5 280 H'00000460 to 3 H'00000463 TXI5 281 H'00000464 to 4 H'00000467 Channel BRI6 282 6 H'00000468 to 0 to 15 (0) IPR21 (7 to 4) 1 H'0000046B ERI6 283 H'0000046C to 2 H'0000046F RXI6 284 H'00000470 to 3 H'00000473 TXI6 285 H'00000474 to H'00000477 Page 200 of 3092 4 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector IPR Setting Unit Interrupt Source Serial Channel 7 BRI7 Vector Table Interrupt Priority (Initial Corresponding Internal Vector Address Offset Value) IPR (Bit) Priority Default Priority 286 H'00000478 to 0 to 15 (0) IPR21 (3 to 0) 1 High communi- H'0000047B cation interface ERI7 287 with FIFO H'0000047C to 2 H'0000047F RXI7 288 H'00000480 to 3 H'00000483 TXI7 289 H'00000484 to 4 H'00000487 Clock- SIOFI 290 synchronized H'00000488 to 0 to 15 (0) IPR22 (15 to 12)  0 to 15 (0) IPR22 (11 to 8) 1 H'0000048B serial I/O module with FIFO Controller area Channel 0 ERS0 291 network H'0000048C to H'0000048F OVR0 292 H'00000490 to 2 H'00000493 RM00 293 H'00000494 to 3 H'00000497 RM10 294 H'00000498 to 4 H'0000049B SLE0 295 H'0000049C to 5 H'0000049F Channel 1 ERS1 296 H'000004A0 to 0 to 15 (0) IPR22 (7 to 4) 1 H'000004A3 OVR1 297 H'000004A4 to 2 H'000004A7 RM01 298 H'000004A8 to 3 H'000004AB RM11 299 H'000004AC to 4 H'000004AF SLE1 300 H'000004B0 to H'000004B3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 5 Low Page 201 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector IPR Setting Unit Interrupt Source Controller area Channel 2 ERS2 Vector Table Interrupt Priority (Initial Corresponding Internal Vector Address Offset Value) IPR (Bit) Priority Default Priority 301 H'000004B4 to 0 to 15 (0) IPR22 (3 to 0) 1 High network H'000004B7 OVR2 302 H'000004B8 to 2 H'000004BB RM02 303 H'000004BC to 3 H'000004BF RM12 304 H'000004C0 to 4 H'000004C3 SLE2 305 H'000004C4 to 5 H'000004C7 Renesas serial Channel 0 SPEI0 306 peripheral H'000004C8 to 0 to 15 (0) IPR23 (15 to 12) 1 H'000004CB interface SPRI0 307 H'000004CC to 2 H'000004CF SPTI0 308 H'000004D0 to 3 H'000004D3 Channel 1 SPEI1 309 H'000004D4 to 0 to 15 (0) IPR23 (11 to 8) 1 H'000004D7 SPRI1 310 H'000004D8 to 2 H'000004DB SPTI1 311 H'000004DC to 3 H'000004DF Renesas quad Channel 0 SPEI0 312 serial H'000004E0 to 0 to 15 (0) IPR23 (7 to 4) 1 H'000004E3 peripheral SPRI0 313 interface H'000004E4 to 2 H'000004E7 SPTI0 314 H'000004E8 to 3 H'000004EB Channel 1 SPEI1 315 H'000004EC to 0 to 15 (0) IPR23 (3 to 0) 1 H'000004EF SPRI1 316 H'000004F0 to 2 H'000004F3 SPTI1 317 H'000004F4 to H'000004F7 Page 202 of 3092 3 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector IPR Setting Interrupt Interrupt Source TM IEBus Unit Priority (Initial Corresponding Internal Vector Vector Table Address Offset Value) IPR (Bit) Priority Default Priority IEB 318 H'000004F8 to H'000004FB 0 to 15 (0) IPR24 (15 to 12)  High ISY 319 H'000004FC to H'000004FF 0 to 15 (0) IPR24 (11 to 8) 1 IERR 320 H'00000500 to H'00000503 2 ITARG 321 H'00000504 to H'00000507 3 ISEC 322 H'00000508 to H'0000050B 4 IBUF 323 H'0000050C to H'0000050F 5 IREADY 324 H'00000510 to H'00000513 FLSTEI 325 H'00000514 to H'00000517 FLTENDI 326 H'00000518 to H'0000051B 2 FLTREQ0I 327 H'0000051C to H'0000051F 3 FLTREQ1I 328 H'00000520 to H'00000523 4 MMC0 329 H'00000524 to H'00000527 MMC1 330 H'00000528 to H'0000052B 2 MMC2 331 H'0000052C to H'0000052F 3 SDHI0_3 332 H'00000530 to H'00000533 SDHI0_0 333 H'00000534 to H'00000537 2 SDHI0_1 334 H'00000538 to H'0000053B 3 SDHI1_3 335 H'0000053C to H'0000053F SDHI1_0 336 H'00000540 to H'00000543 2 SDHI1_1 337 H'00000544 to H'00000547 3 ARM 338 H'00000548 to H'0000054B PRD 339 H'0000054C to H'0000054F 2 CUP 340 H'00000550 to H'00000553 3 controller CD-ROM decoder NAND flash memory 6 0 to 15 (0) IPR24 (7 to 4) 1 controller MMC host interface SD host Channel 0 interface Channel 1 Realtime clock R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR24 (3 to 0) IPR25 (15 to 12) IPR25 (11 to 8) IPR25 (7 to 4) 1 1 1 1 Low Page 203 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Interrupt Vector IPR Setting Interrupt Interrupt Source Sampling Channel 0 rate Vector Unit Vector Table Address Priority (Initial Corresponding Internal Offset Value) IPR (Bit) Priority Default Priority 0 to 15 (0) IPR26 (15 to 12) 1 High OVF0 341 H'00000554 to H'00000557 UDF0 342 H'00000558 to H'0000055B 2 CEF0 343 H'0000055C to H'0000055F 3 ODFI0 344 H'00000560 to H'00000563 4 IDEI0 345 H'00000564 to H'00000567 5 OVF1 346 H'00000568 to H'0000056B UDF1 347 H'0000056C to H'0000056F 2 CEF1 348 H'00000570 to H'00000573 3 converter Channel 1 Channel 2 Page 204 of 3092 0 to 15 (0) IPR26 (11 to 8) 1 ODFI1 349 H'00000574 to H'00000577 4 IDEI1 350 H'00000578 to H'0000057B 5 OVF2 351 H'0000057C to H'0000057F UDF2 352 H'00000580 to H'00000583 2 CEF2 353 H'00000584 to H'00000587 3 ODFI2 354 H'00000588 to H'0000058B 4 IDEI2 355 H'0000058C to H'0000058F 5 0 to 15 (0) IPR26 (7 to 4) 1 Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.6 Operation 7.6.1 Interrupt Operation Sequence Section 7 Interrupt Controller The sequence of interrupt operations is described below. Figure 7.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers 01, 02, and 05 to 26 (IPR01, IPR02, and IPR05 to IPR26). Lower priority interrupts are ignored*. If two of these interrupts have the same priority level or if multiple interrupts occur within a single IPR, the interrupt with the highest priority is selected, according to the default priority and IPR setting unit internal priority shown in table 7.4. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (figure 7.4). 5. The interrupt exception service routine start address is fetched from the exception handling vector table corresponding to the accepted interrupt. 6. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt is copied to bits I3 to I0 in SR. 7. The program counter (PC) is saved onto the stack. 8. The CPU jumps to the fetched interrupt exception service routine start address and starts executing the program. The jump that occurs is not a delayed branch. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 205 of 3092 Section 7 Interrupt Controller SH7268 Group, SH7269 Group Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 7.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-sensing are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt request register (IRQRR). For details, see section 7.4.4, IRQ Interrupts. Interrupts held pending due to edge-sensing are cleared by a power-on reset. Page 206 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Program execution state No Interrupt? Yes No NMI? Yes No User break? Yes User debug interface interrupt? Yes No Level 15 interrupt? Yes Yes No Level 14 interrupt? I3 to I0 ≤ level 14? No No Yes Level 1 interrupt? I3 to I0 ≤ level 13? No No Yes Yes I3 to I0 = level 0? No Read exception handling vector table Save SR to stack Copy accept-interrupt level to I3 to I0 Save PC to stack Branch to interrupt exception service routine Figure 7.2 Interrupt Operation Flow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 207 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.6.2 Stack after Interrupt Exception Handling Figure 7.3 shows the stack after interrupt exception handling. Address 4n – 8 PC*1 32 bits 4n – 4 SR 32 bits SP*2 4n Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executed instruction Always make sure that SP is a multiple of 4. Figure 7.3 Stack after Interrupt Exception Handling Page 208 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.7 Section 7 Interrupt Controller Interrupt Response Time Table 7.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 7.4 and 7.5 show examples of pipeline operation when banking is disabled. Figures 7.6 and 7.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 7.8 and 7.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 7.5 Interrupt Response Time Number of States Serial USB 2.0 Communi- User host/ cation Peripheral User Debugging IRQ, function Interface Modules 3 Peripheral Item NMI break Interface PINT module with FIFO 1* Modules 2* Time from occurrence of interrupt 2 Icyc  3 Icyc 2 Icyc  2 Icyc  2 Icyc  2 Icyc  2 Icyc  2 Icyc  1 P0cyc 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc 1 P1cyc 1 P0cyc request until interrupt controller identifies 2 P1cyc priority, compares it with mask bits in + SR, and sends interrupt request signal 1 P0cyc 1 P0cyc 2 P1cyc 4 Remarks to CPU Time from input No register of interrupt banking request signal to Min. 3 Icyc + m1 + m2 Max. 4 Icyc + 2(m1 + m2) + m3 Min. is when the interrupt wait time is CPU until zero. sequence Max. is when a currently being higher-priority executed is interrupt completed, request has interrupt occurred during exception interrupt handling starts, exception and first handling. instruction in interrupt exception service routine is fetched R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 209 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Number of States Serial Item NMI Time from input Register of interrupt banking request signal to without Min. Max.   USB 2.0 Communi- User host/ cation Peripheral User Debugging IRQ, function Interface Modules break Interface module with FIFO 1* PINT 3 Icyc + m1 + m2 12 Icyc + m1 + m2 3 Peripheral Modules 2* 4 Remarks Min. is when the interrupt wait time is CPU until register bank zero. sequence overflow Max. is when currently being an interrupt executed is request has completed, occurred during interrupt execution of exception the RESBANK instruction. handling starts, and first instruction in interrupt exception service routine Register banking with register bank overflow is fetched Min. Max.   3 Icyc + m1 + m2 3 Icyc + m1 + m2 + 19(m4) Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Page 210 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Number of States Serial Item Interrupt No register response banking Min. time USB 2.0 Communi- User host/ cation Peripheral Peripheral User Debugging function Interface Modules Modules NMI break Interface IRQ, PINT module with FIFO 1*3 2*4 Remarks 5 Icyc + 6 lcyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 266-MHz 2 P1cyc + m1 + m2 1 P0cyc + 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc + operation* * : m1 + m2 1 P0cyc + 2 P1cyc + 1 P1cyc 1 P0cyc m1 + m2 0.029 to 0.101 s m1 + m2 m1 + m2 + m1 + m2 + m1 + m2 1 P0cyc + m1 + m2 Max. 6 Icyc + 7 Icyc + 6 Icyc + 6 Icyc + 6 Icyc + 6 Icyc + 6 Icyc + 6 Icyc + 266-MHz 2 P1cyc + 2(m1 + 1 P0cyc + 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc + operation* * : 1 P0cyc + m2) + m3 2(m1 + m2) 1 P0cyc + 2 P1cyc + 1 P1cyc + 1 P0cyc + 2(m1 + 0.044 to 0.116 s 2(m1 + + m3 m2) + m3 Register Min. 1 2  2(m1 + m2) 2(m1 + m2) 2(m1 + m2) 2(m1 + m2) m2) + m3 + m3 + m3 + m3 + m3 1 2 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 266-MHz banking 1 P0cyc + 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc + operation* * : without m1 + m2 1 P0cyc + 2 P1cyc + 1 P1cyc + 1 P0cyc + m1 + m2 0.041 to 0.101 s m1 + m2 m1 + m2 + m1 + m2 + m1 + m2 14 Icyc + 14 Icyc + 14 Icyc + 14 Icyc + 14 Icyc + 14 Icyc + 266-MHz 1 P0cyc + 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc + operation* * : m1 + m2 1 P0cyc + 2 P1cyc + 1 P1cyc + 1 P0cyc + m1 + m2 0.075 to 0.135 s m1 + m2 m1 + m2 m1 + m2 m1 + m2 register bank overflow Register Max. Min.   1 2 1 2 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 266-MHz banking with 1 P0cyc + 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc + operation* * : register bank m1 + m2 1 P0cyc + 2 P1cyc + 1 P1cyc + 1 P0cyc + m1 + m2 0.041 to 0.102 s m1 + m2 m1 + m2 m1 + m2 m1 + m2 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 5 Icyc + 266-MHz 1 P0cyc + 3 P1cyc + 2 Bcyc + 4 Bcyc + 4 Bcyc + 2 Bcyc + operation* * : m1 + m2 + 1 P0cyc + 2 P1cyc + 1 P1cyc + 1 P0cyc + m1 + m2 + 0.112 to 0.173 s 19(m4) m1 + m2 + m1 + m2 + m1 + m2 + m1 + m2 + 19(m4) 19(m4) 19(m4) 19(m4) 19(m4) overflow Max. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  1 2 1 2 Page 211 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Notes: m1 to m4 are the number of states needed for the following memory accesses. m1: Vector address read (longword read) m2: SR save (longword write) m3: PC save (longword write) m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. 1. In the case that m1 = m2 = m3 = m4 = 1 Icyc. 2. In the case that (I, B, P1, P0) = (266.67 MHz, 133.33 MHz, 66.67 MHz, 33.33 MHz). 3. Compare match timer, motor control PWM timer, multi-function timer pulse unit 2, TM controller area network, IEBus controller, and sound generator. 4. Peripheral modules other than USB 2.0 host/function module, serial communication interface with FIFO, and peripheral modules 1. Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 P1cyc + P0cyc 3 Icyc m1 m2 m3 M M M IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) F: Instruction fetch. Instruction is fetched from memory in which program is stored. D: Instruction decoding. Fetched instruction is decoded. E: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. M: Memory access. Memory data access is performed. Figure 7.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking) Page 212 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 2 Icyc + 3 P1cyc + P0cyc 1 Icyc + m1 + 2(m2) + m3 3 Icyc + m1 IRQ F D E E m1 m2 m3 M M M First instruction in interrupt exception service routine First instruction in multiple interrupt exception service routine D F D E E m1 m2 M M M F D Multiple interrupt acceptance Interrupt acceptance [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.5 Example of Pipeline Operation for Multiple Interrupts (No Register Banking) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 P1cyc + P0cyc 3 Icyc m1 m2 m3 M M M E F D IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.6 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking without Register Bank Overflow) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 213 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 2 Icyc + 3 P1cyc + P0cyc 9 Icyc 3 Icyc + m1 + m2 IRQ F RESBANK instruction D E E E E E E E E Instruction (instruction replacing interrupt exception handling) E D E E m1 m2 m3 M M M E F D First instruction in interrupt exception service routine Interrupt acceptance [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Figure 7.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 P1cyc + P0cyc 3 Icyc m1 m2 m3 M M M ... M F ... ... IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E D [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow) Page 214 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 2 Icyc + 3 P1cyc + P0cyc 2 Icyc + 17(m4) 1 Icyc + m1 + m2 + 2(m4) IRQ RESBANK instruction F D Instruction (instruction replacing interrupt exception handling) E M M M ... M m4 m4 M M W D E E First instruction in interrupt exception service routine m1 m2 m3 M M M ... F ... D Interrupt acceptance [Legend] m1: m2: m3: m4: Vector address read Saving of SR (stack) Saving of PC (stack) Restoration of banked registers Figure 7.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking with Register Bank Overflow) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 215 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller 7.8 Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 7.10 shows the register bank configuration. Registers Register banks General registers R0 R1 : : R0 R1 Interrupt generated (save) R14 R15 Bank 0 Bank 1 .... Bank 14 : : R14 GBR Control registers System registers SR GBR VBR TBR MACH MACL PR PC RESBANK instruction (restore) MACH MACL PR VTO Bank control registers (interrupt controller) Bank control register IBCR Bank number register IBNR : Banked register Note: VTO: Vector table address offset Figure 7.10 Overview of Register Bank Configuration Page 216 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.8.1 (1) Section 7 Interrupt Controller Banked Register and Input/Output of Banks Banked Register The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset are banked. (2) Input/Output of Banks This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in lastout (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place in the reverse order, beginning from the last bank saved to. 7.8.2 (1) Bank Save and Restore Operations Saving to Bank Figure 7.11 shows register bank save operations. The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU: a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the interrupt is generated. b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN, bank i. c. The BN value is incremented by 1. Register banks +1 (c) BN (a) Bank 0 Bank 1 : : Bank i Bank i + 1 : : Registers R0 to R14 (b) GBR MACH MACL PR VTO Bank 14 Figure 7.11 Bank Save Operations R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 217 of 3092 SH7268 Group, SH7269 Group Section 7 Interrupt Controller Figure 7.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the interrupt exception service routine. 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 M M M IRQ Instruction (instruction replacing interrupt exception handling) F D E E E (1) VTO, PR, GBR, MACL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 (4) R4, R5, R6, R7 Saved to bank Overrun fetch (5) R0, R1, R2, R3 F First instruction in interrupt exception service routine F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.12 Bank Save Timing (2) Restoration from Bank The RESBANK (restore from register bank) instruction is used to restore data saved in a register bank. After restoring data from the register banks with the RESBANK instruction at the end of the interrupt exception service routine, execute the RTE instruction to return from interrupt exception service routine. Page 218 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.8.3 Section 7 Interrupt Controller Save and Restore Operations after Saving to All Banks If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register banks, automatic saving to the stack is performed instead of register bank saving if the BOVE bit in the bank number register (IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception occurs and data is not saved to the stack. Save and restore operations when using the stack are as follows: (1) Saving to Stack 1. The status register (SR) and program counter (PC) are saved to the stack during interrupt exception handling. 2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14, R13, …, R1, and R0. 3. The register bank overflow bit (BO) in SR is set to 1. 4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. (2) Restoration from Stack When the RESBANK (restore from register bank) instruction is executed with the register bank overflow bit (BO) in SR set to 1, the CPU operates as follows: 1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14, PR, GBR, MACH, and MACL. 2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 219 of 3092 Section 7 Interrupt Controller 7.8.4 SH7268 Group, SH7269 Group Register Bank Exception There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all of the register banks, an interrupt for which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number register (IBNR) remains set to the bank count of 15 and saving is not performed to the register bank. (2) Register Bank Underflow This exception occurs if the RESBANK (restore from register bank) instruction is executed when no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH, MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number register (IBNR) remains set to 0. 7.8.5 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. When this happens, the CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a register bank overflow, and the start address of the executed RESBANK instruction for a register bank underflow. To prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. Program execution starts from the exception service routine start address. Page 220 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.9 Section 7 Interrupt Controller Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the direct memory access controller and transfer data. Interrupt sources that are designated to activate the direct memory access controller are masked without being input to the interrupt controller. The mask condition is as follows: Mask condition = DME  (DE0  interrupt source select 0 + DE1  interrupt source select 1 + DE2  interrupt source select 2 + DE3  interrupt source select 3 + DE4  interrupt source select 4 + DE5  interrupt source select 5 + DE6  interrupt source select 6 + DE7  interrupt source select 7 + DE8  interrupt source select 8 + DE9  interrupt source select 9 + DE10  interrupt source select 10 + DE11  interrupt source select 11 + DE12  interrupt source select 12 + DE13  interrupt source select 13 + DE14  interrupt source select 14 + DE15  interrupt source select 15) Figure 7.13 shows a block diagram of interrupt control. Here, DME is bit 0 in DMAOR of the direct memory access controller, and DEn (n = 0 to 15) is bit 0 in CHCR_0 to CHCR_15 of the direct memory access controller. For details, see section 11, Direct Memory Access Controller. Interrupt source Interrupt source flag clearing (by the direct memory access controller) Direct memory access controller Interrupt source (not specified as a direct memory access controller activating source) Interrupt controller CPU interrupt request CPU Figure 7.13 Interrupt Control Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 221 of 3092 Section 7 Interrupt Controller 7.9.1 SH7268 Group, SH7269 Group Handling Interrupt Request Signals as Sources for CPU Interrupt but Not Direct Memory Access Controller Activating 1 Do not select direct memory access controller activating sources or clear the DME bit to 0. If, direct memory access controller activating sources are selected, clear the DE bit to 0 for the relevant channel of the direct memory access controller. 2. When interrupts occur, interrupt requests are sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt exception service routine. 7.9.2 Handling Interrupt Request Signals as Sources for Activating Direct Memory Access Controller but Not CPU Interrupt 1. Select direct memory access controller activating sources and set both the DE and DME bits to 1. This masks CPU interrupt sources regardless of the interrupt priority register settings. 2. Activating sources are applied to the direct memory access controller when interrupts occur. 3. The direct memory access controller clears the interrupt sources when starting transfer. Page 222 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 7.10 Usage Note 7.10.1 Timing to Clear an Interrupt Source Section 7 Interrupt Controller The interrupt source flags should be cleared in the interrupt exception service routine. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 7.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read* the interrupt source flag after it has been cleared, and then execute an RTE instruction. Note: * When clearing the USB 2.0 host/function module interrupt source flag, read the flag three times after clearing it. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 223 of 3092 Section 7 Interrupt Controller Page 224 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 8 User Break Controller Section 8 User Break Controller The user break controller provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Instruction fetch or data read/write (bus cycle (CPU or direct memory access controller) selection in the case of data read/write), data size, data contents, address value, and stop timing in the case of instruction fetch are break conditions that can be set in this module. Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is performed by issuing bus cycles on the memory access bus (M bus). The internal bus (I bus) consists of the internal CPU bus, on which the CPU issues bus cycles, and the internal DMA bus, on which the direct memory access controller issues bus cycles. This module monitors the C bus and I bus. 8.1 Features 1. The following break comparison conditions can be set. Number of break channels: two channels (channels 0 and 1) User break can be requested as the independent condition on channels 0 and 1.  Address Comparison of the 32-bit address is maskable in 1-bit units. One of the four address buses (F address bus (FAB), M address bus (MAB), internal CPU address bus (ICAB), and internal DMA address bus (IDAB)) can be selected.  Data Comparison of the 32-bit data is maskable in 1-bit units. One of the three data buses (M data bus (MDB), internal CPU data bus (ICDB), and internal DMA data bus (IDDB)) can be selected.  Bus selection when I bus is selected Internal CPU bus or internal DMA bus  Bus cycle Instruction fetch (only when C bus is selected) or data access  Read/write  Operand size Byte, word, and longword 2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt exception processing is set before or after an instruction is executed. 3. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 225 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller Figure 8.1 shows a block diagram. Access control Internal bus (I bus) Internal DMA bus Internal CPU bus IDDB IDAB ICDB ICAB CPU bus (C bus) CPU CPU memory instruction access bus fetch bus MDB MAB Internal CPU bus FAB Access comparator BBR_0 BAR_0 Address comparator Data comparator BAMR_0 BDR_0 BDMR_0 Channel 0 Access comparator BBR_1 BAR_1 Address comparator Data comparator BAMR_1 BDR_1 BDMR_1 Channel 1 BRCR Control User break interrupt request UBCTRG pin output [Legend] BBR: Break bus cycle register BAR: Break address register BAMR: Break address mask register BDR: Break data register BDMR: Break data mask register BRCR: Break control register Figure 8.1 Block Diagram Page 226 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.2 Section 8 User Break Controller Input/Output Pin Table 8.1 shows the pin configuration. Table 8.1 Pin Configuration Pin Name Symbol I/O Function User break trigger output UBCTRG Output Indicates that a setting condition is satisfied on either channel 0 or 1 of this module. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 227 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller 8.3 Register Descriptions Table 8.2 shows a register configuration. Five control registers for each channel and one common control register for channel 0 and channel 1 are available. A register for each channel is described as BAR_0 for the BAR register in channel 0. Table 8.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 Break address register_0 BAR_0 R/W H'00000000 H'FFFC0400 32 Break address mask register_0 BAMR_0 R/W H'00000000 H'FFFC0404 32 Break bus cycle register_0 BBR_0 R/W H'0000 H'FFFC04A0 16 Break data register_0 BDR_0 R/W H'00000000 H'FFFC0408 Break data mask register_0 BDMR_0 R/W H'00000000 H'FFFC040C 32 Break address register_1 BAR_1 R/W H'00000000 H'FFFC0410 32 Break address mask register_1 BAMR_1 R/W H'00000000 H'FFFC0414 32 Break bus cycle register_1 BBR_1 R/W H'0000 H'FFFC04B0 16 Break data register_1 BDR_1 R/W H'00000000 H'FFFC0418 Break data mask register_1 BDMR_1 R/W H'00000000 H'FFFC041C 32 Break control register BRCR R/W H'00000000 H'FFFC04C0 32 1 Common Page 228 of 3092 32 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.3.1 Section 8 User Break Controller Break Address Register (BAR) BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in each channel. The control bits CD[1:0] and CP[1:0] in the break bus cycle register (BBR) select one of the four address buses for a break condition. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BA31 to BA0 All 0 R/W R/W Description Break Address Store an address on the CPU address bus (FAB or MAB) or internal address bus (ICAB or IDAB) specifying break conditions. When the C bus and instruction fetch cycle are selected by BBR, specify an FAB address in bits BA31 to BA0. When the C bus and data access cycle are selected by BBR, specify an MAB address in bits BA31 to BA0. When the internal CPU bus (I bus) is selected by BBR, specify an ICAB address in bits BA31 to BA0. When the internal DMA bus (I bus) is selected by BBR, specify an IDAB address in bits BA31 to BA0. Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 229 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller 8.3.2 Break Address Mask Register (BAMR) BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address bits specified by BAR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Initial value: R/W: 0 R/W 0 R/W Bit Bit Name 31 to 0 BAM31 to BAM0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Address Mask 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Specify bits masked in the break address bits specified by BAR (BA31 to BA0). 0: Break address bit BAn is included in the break condition 1: Break address bit BAn is masked and not included in the break condition Note: n = 31 to 0 Page 230 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.3.3 Section 8 User Break Controller Break Data Register (BDR) BDR is a 32-bit readable/writable register. The control bits CD[1:0] and CP[1:0] in the break bus cycle register (BBR) select one of the three data buses for a break condition. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BD31 to BD0 All 0 R/W R/W Description Break Data Bits Store data which specifies a break condition. When the C bus is selected by BBR, specify the break data on MDB in bits BD31 to BD0. When the internal CPU bus (I bus) is selected by BBR, specify an ICDB address in bits BD31 to BD0. When the internal DMA bus (I bus) is selected by BBR, specify an IDDB address in bits BD31 to BD0. Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 231 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller 8.3.4 Break Data Mask Register (BDMR) BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits specified by BDR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16 Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0 Initial value: R/W: 0 R/W 0 R/W Bit Bit Name 31 to 0 BDM31 to BDM0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Data Mask 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Specify bits masked in the break data bits specified by BDR (BD31 to BD0). 0: Break data bit BDn is included in the break condition 1: Break data bit BDn is masked and not included in the break condition Note: n = 31 to 0 Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0. Page 232 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.3.5 Section 8 User Break Controller Break Bus Cycle Register (BBR) BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupt requests, (2) including or excluding of the data bus value, (3) internal CPU bus or internal DMA bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions. Bit: Initial value: R/W: 15 14 13 12 11 10 - - UBID DBE - - 0 R 0 R 0 R/W 0 R/W 0 R 0 R Bit Bit Name Initial Value R/W 15, 14  All 0 R 9 8 7 CP[1:0] 0 R/W 0 R/W 6 CD[1:0] 0 R/W 0 R/W 5 4 ID[1:0] 0 R/W 0 R/W 3 2 1 RW[1:0] 0 R/W 0 SZ[1:0] 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 13 UBID 0 R/W User Break Interrupt Disable Disables or enables user break interrupt requests when a break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12 DBE 0 R/W Data Break Enable Selects whether the data bus condition is included in the break conditions. 0: Data bus condition is not included in break conditions 1: Data bus condition is included in break conditions 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 233 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 9, 8 CP[1:0] 00 R/W I-Bus Bus Select Select the bus when the bus cycle of the break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). 00: Condition comparison is not performed 01: Break condition is the internal CPU bus 10: Break condition is the internal DMA bus 11: Break condition is the internal CPU bus 7, 6 CD[1:0] 00 R/W C Bus Cycle/I Bus Cycle Select Select the C bus cycle or I bus cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID[1:0] 00 R/W Instruction Fetch/Data Access Select Select the instruction fetch cycle or data access cycle as the bus cycle of the break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW[1:0] 00 R/W Read/Write Select Select the read cycle or write cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle Page 234 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 1, 0 SZ[1:0] 00 R/W Operand Size Select Select the operand size of the bus cycle for the break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access 8.3.6 Break Control Register (BRCR) BRCR sets the following conditions: 1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle is set before or after instruction execution. 2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied. 3. Specifies whether a trigger signal is output to the UBCTRG pin when a break condition is satisfied. BRCR is a 32-bit readable/writable register that has break condition match flags and bits for setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid (previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag bit to be cleared and 1 to all other flag bits. Bit: Initial value: R/W: Bit: 31 30 29 28 27 26 25 24 23 22 21 20 - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - PCB1 PCB0 - - - - - 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R SCMFC SCMFC SCMFD SCMFD 0 1 0 1 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 20  All 0 R Reserved 0 R/W 19 18 UTOD1 UTOD0 17 16 CKS[1:0] These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 235 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 19 UTOD1 0 R/W UBCTRG Output Disable 1 Specifies whether a trigger signal is output to the UBCTRG pin when a break condition for channel 1 is satisfied. 0: Outputs a trigger signal to the UBCTRG pin when a break condition for channel 1 is satisfied 1: Does not output a trigger signal to the UBCTRG pin when a break condition for channel 1 is satisfied 18 UTOD0 0 R/W UBCTRG Output Disable 0 Specifies whether a trigger signal is output to the UBCTRG pin when a break condition for channel 0 is satisfied. 0: Outputs a trigger signal to the UBCTRG pin when a break condition for channel 0 is satisfied 1: Does not output a trigger signal to the UBCTRG pin when a break condition for channel 0 is satisfied 17, 16 CKS[1:0] 00 R/W Clock Select Specifies the pulse width output to the UBCTRG pin when a break condition is satisfied. 00: Pulse width of UBCTRG is one cycle of peripheral clock 1. 01: Pulse width of UBCTRG is two cycles of peripheral clock 1. 10: Pulse width of UBCTRG is four cycles of peripheral clock 1. 11: Pulse width of UBCTRG is eight cycles of peripheral clock 1. 15 SCMFC0 0 R/W C Bus Cycle Condition Match Flag 0 When the C bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 0 does not match 1: The C bus cycle condition for channel 0 matches Page 236 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 14 SCMFC1 0 R/W C Bus Cycle Condition Match Flag 1 When the C bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 1 does not match 1: The C bus cycle condition for channel 1 matches 13 SCMFD0 0 R/W I Bus Cycle Condition Match Flag 0 When the I bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 0 does not match 1: The I bus cycle condition for channel 0 matches 12 SCMFD1 0 R/W I Bus Cycle Condition Match Flag 1 When the I bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 1 does not match 1: The I bus cycle condition for channel 1 matches 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 PCB1 0 R/W PC Break Select 1 Selects the break timing of the instruction fetch cycle for channel 1 as before or after instruction execution. 0: PC break of channel 1 is generated before instruction execution 1: PC break of channel 1 is generated after instruction execution 5 PCB0 0 R/W PC Break Select 0 Selects the break timing of the instruction fetch cycle for channel 0 as before or after instruction execution. 0: PC break of channel 0 is generated before instruction execution 1: PC break of channel 0 is generated after instruction execution R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 237 of 3092 SH7268 Group, SH7269 Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 4 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 238 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.4 Operation 8.4.1 Flow of the User Break Operation Section 8 User Break Controller The flow from setting of break conditions to user break interrupt exception handling is described below: 1. The break address is set in a break address register (BAR). The masked address bits are set in a break address mask register (BAMR). The break data is set in the break data register (BDR). The masked data bits are set in the break data mask register (BDMR). The bus break conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set to 00. The relevant break control conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBR, and branch after reading from the last written register. The newly written register values become valid from the instruction at the branch destination. 2. In the case where the break conditions are satisfied and the user break interrupt request is enabled, this module sends a user break interrupt request to the interrupt controller sets the C bus condition match flag (SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel, and outputs a pulse to the UBCTRG pin with the width set by the CKS[1:0] bits. Setting the UBID bit in BBR to 1 enables external monitoring of the trigger output without requesting user break interrupts. 3. On receiving a user break interrupt request signal, the interrupt controller determines its priority. Since the user break interrupt has a priority level of 15, it is accepted when the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are checked, and condition match flags are set if the conditions match. For details on ascertaining the priority, see section 7, Interrupt Controller. 4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been satisfied. Clear the condition match flags during the user break interrupt exception processing routine. The interrupt occurs again if this operation is not performed. 5. There is a chance that the break set in channel 0 and the break set in channel 1 occur around the same time. In this case, there will be only one user break request to the interrupt controller but these two break channel match flags may both be set. 6. When selecting the I bus as the break condition, note as follows:  Whether or not an access issued on the C bus by the CPU is issued on the internal CPU bus depends on the cache settings. Regarding the I bus operation under cache conditions, see table 9.8 in section 9, Cache. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 239 of 3092 Section 8 User Break Controller SH7268 Group, SH7269 Group  When a break condition is specified for the I bus, only the data access cycle is monitored. The instruction fetch cycle (including the cache renewal cycle) is not monitored.  Only data access cycles are issued for the internal DMA bus cycles.  If a break condition is specified for the I bus, even when the condition matches in an internal CPU bus cycle resulting from an instruction executed by the CPU, at which instruction the user break interrupt request is to be accepted cannot be clearly defined. 8.4.2 Break on Instruction Fetch Cycle 1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBR), the break condition is the FAB bus instruction fetch cycle. Whether a start of user break interrupt exception processing is set before or after the execution of the instruction can then be selected with the PCB0 or PCB1 bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear BA0 bit in the break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1. 2. A break for instruction fetch which is set as a break before instruction execution occurs when it is confirmed that the instruction has been fetched and will be executed. This means a break does not occur for instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the user break interrupt request is not received until the execution of the first instruction at the branch destination. Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When setting a break condition for break after instruction execution, the instruction set with the break condition is executed and then the break is generated prior to execution of the next instruction. As with pre-execution breaks, a break does not occur with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, the user break interrupt request is not received until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated. Page 240 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.4.3 Section 8 User Break Controller Break on Data Access Cycle 1. If the C bus is specified as a break condition for data access break, condition comparison is performed for the addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles on the bus specified by the I bus select bits, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the internal CPU bus, see 6 in section 8.4.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 8.3. Table 8.3 Access Size Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BAR), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size in the break bus cycle register (BBR). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in the four bytes at bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 of the break data register (BDR) and break data mask register (BDMR). To specify word data for this case, set the same data in the two words at bits 31 to 16 and 15 to 0. 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the data access cycle is selected, the instruction at which the break will occur cannot be determined. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 241 of 3092 Section 8 User Break Controller 8.4.4 SH7268 Group, SH7269 Group Value of Saved Program Counter When a user break interrupt request is received, the address of the instruction from where execution is to be resumed is saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access cycle is specified as a break condition, the instruction at which the break should occur cannot be uniquely determined. 1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved to the stack. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved to the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition: The address after executing several instructions of the instruction that matched the break condition is saved to the stack. Page 242 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 8.4.5 (1) Section 8 User Break Controller Usage Examples Break Condition Specified for C Bus Instruction Fetch Cycle (Example 1-1)  Register specifications BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Address: H'00000404, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2)  Register specifications BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415, BAMR_1 = H'00000000, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000000 Address: H'00027128, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/write/word Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel 0, a user break does not occur since instruction fetch is not a write cycle. On channel 1, a user break does not occur since instruction fetch is performed for an even address. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 243 of 3092 Section 8 User Break Controller SH7268 Group, SH7269 Group (Example 1-3)  Register specifications BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_0 = H'0054, BAR_1= H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Address: H'00008404, Address mask: H'00000FFF Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. (2) Break Condition Specified for C Bus Data Access Cycle (Example 2-1)  Register specifications BAR_0 = H'00123456, BAMR_0 = H'00000000, BBR_0 = H'0064, BAR_1= H'000ABCDE, BAMR_1 = H'000000FF, BBR_1 = H'106A, BDR_1 = H'A512A512, BDMR_1 = H'00000000, BRCR = H'00000000 Address: H'00123456, Address mask: H'00000000 Bus cycle: C bus/data access/read (operand size is not included in the condition) Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: C bus/data access/write/word On channel 0, a user break occurs with longword read from address H'00123456, word read from address H'00123456, or byte read from address H'00123456. On channel 1, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Page 244 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 8 User Break Controller Break Condition Specified for I Bus Data Access Cycle (Example 3-1)  Register specifications BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0194, BAR_1= H'00055555, BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F, BRCR = H'00000000 Address: H'00314156, Address mask: H'00000000 Bus cycle: Internal CPU bus/instruction fetch/read (operand size is not included in the condition) Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: Internal DMA bus/data access/write/byte On channel 0, the setting of the internal CPU bus/instruction fetch is ignored. On channel 1, a user break occurs when the direct memory access controller writes byte data H'7x in address H'00055555 on the internal DMA bus (access via the internal CPU bus does not generate a user break). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 245 of 3092 Section 8 User Break Controller 8.5 SH7268 Group, SH7269 Group Usage Notes 1. The CPU can read from or write to this module registers via the internal CPU bus. Accordingly, during the period from executing an instruction to rewrite this module register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when this module register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. This module cannot monitor the C bus, internal CPU, and internal DMA bus cycles in the same channel. 3. When a user break interrupt request and another exception source occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 6.1 in section 6, Exception Handling. If an exception source with higher priority occurs, the user break interrupt request is not received. 4. Note the following when a break occurs in a delay slot. If a pre-execution break is set at a delay slot instruction, the user break interrupt request is not received immediately before execution of the branch destination. 5. User breaks are disabled during module standby mode. Do not read from or write to this module registers during module standby mode; the values are not guaranteed. 6. Do not set an address within an interrupt exception handling routine whose interrupt priority level is at least 15 (including user break interrupts) as a break address. 7. Do not set break after instruction execution for the SLEEP instruction or for the delayed branch instruction where the SLEEP instruction is placed at its delay slot. 8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are placed. If the address of the lower 16 bits is set and a break before instruction execution is set as a break condition, the break is handled as a break after instruction execution. 9. Do not set a user break before instruction execution for the instruction following the DIVU or DIVS instruction. If a user break before instruction execution is set for the instruction following the DIVU or DIVS instruction and an exception or interrupt occurs during execution of the DIVU or DIVS instruction, a user break occurs before instruction execution even though execution of the DIVU or DIVS instruction is halted. Page 246 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 9 Cache Section 9 Cache 9.1 Features  Capacity Instruction cache: 8 Kbytes Operand cache: 8 Kbytes  Structure: Instructions/data separated, 4-way set associative  Way lock function (only for operand cache): Way 2 and way 3 are lockable  Line size: 16 bytes  Number of entries: 128 entries/way  Write system: Write-back/write-through selectable  Replacement method: Least-recently-used (LRU) algorithm 9.1.1 Cache Structure The cache separates data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. In each way, each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes  4). The data capacity per way is 2 Kbytes (16 bytes  128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure 9.1 shows the operand cache structure. The instruction cache structure is the same as the operand cache structure except for not having the U bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 247 of 3092 SH7268 Group, SH7269 Group Section 9 Cache Address array (ways 0 to 3) Entry 0 V U Tag address Entry 1 . . . . . . Entry 127 23 (1 + 1 + 21) bits LRU Data array (ways 0 to 3) 0 LW0 LW1 LW2 LW3 0 1 1 . . . . . . . . . . . . 127 127 128 (32 × 4) bits 6 bits LW0 to LW3: Longword data 0 to 3 Figure 9.1 Operand Cache Structure (1) Address Array The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit (only for operand cache) indicates whether the entry has been written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the access to external memory or large-capacity on-chip RAM. It consists of 21 bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 10, Bus State Controller), and therefore the upper three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in software standby mode. The tag address is not initialized by a power-on reset or manual reset or in software standby mode. (2) Data Array Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on reset or manual reset or in software standby mode. Page 248 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 9 Cache LRU With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way that has been least recently accessed. Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between LRU and way replacement is shown in table 9.1 when the cache lock function (only for operand cache) is not used (concerning the case where the cache lock function is used, see section 9.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 9.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 9.1. The LRU bits are initialized to B'000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Table 9.1 LRU and Way Replacement (Cache Lock Function Not Used) LRU (Bits 5 to 0) Way to be Replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 249 of 3092 SH7268 Group, SH7269 Group Section 9 Cache 9.2 Register Descriptions Table 9.2 shows the register configuration of the cache. Table 9.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Cache control register 1 CCR1 R/W H'00000000 H'FFFC1000 32 Cache control register 2 CCR2 R/W H'00000000 H'FFFC1004 32 9.2.1 Cache Control Register 1 (CCR1) The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or write-back mode for operand cache. Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - ICF - - ICE - - - - OCF - WT OCE 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W Initial value: R/W: Page 250 of 3092 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 9 Cache Bit Bit Name Initial Value R/W Description 31 to 12  All 0 R 11 ICF 0 R/W 10, 9  All 0 R 8 ICE 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Flush Writing 1 flushes all instruction cache entries (clears the V and LRU bits of all instruction cache entries to 0). Always reads 0. Write-back to the external memory or the large-capacity on-chip RAM is not performed when the instruction cache is flushed. Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Enable Indicates whether the instruction cache function is enabled/disabled. 0: Instruction cache disable 1: Instruction cache enable 7 to 4  All 0 R 3 OCF 0 R/W 2  0 R 1 WT 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Operand Cache Flush Writing 1 flushes all operand cache entries (clears the V, U, and LRU bits of all operand cache entries to 0). Always reads 0. Write-back to the external memory or the large-capacity on-chip RAM is not performed when the operand cache is flushed. Reserved This bit is always read as 0. The write value should always be 0. Write Through Selects write-back mode or write-through mode. 0: Write-back mode 1: Write-through mode 0 OCE 0 R/W Operand Cache Enable Indicates whether the operand cache function is enabled/disabled. 0: Operand cache disable 1: Operand cache enable R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 251 of 3092 SH7268 Group, SH7269 Group Section 9 Cache 9.2.2 Cache Control Register 2 (CCR2) CCR2 is used to enable or disable the cache locking function for operand cache and is valid in cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to 1. In non-cache-locking mode, the cache locking function is invalid. When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF @Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The relationship between the setting of each bit and a way, to be replaced when the prefetch instruction is executed, are listed in table 9.3. On the other hand, when the prefetch instruction is executed and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1 specified in cache locking mode while one-line data already exists in way 0 which is specified by Rn, a cache hit occurs and data is not fetched to way 3. In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in CCR2 and ways to be replaced are listed in table 9.4. Programs that change the contents of CCR2 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR2. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - LE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: W3 W3 LOAD* LOCK 0 R/W 0 R/W W2 W2 LOAD* LOCK 0 R/W 0 R/W Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Page 252 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 9 Cache Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock Enable Controls the cache locking function. 0: Not cache locking mode 1: Cache locking mode 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 W3LOAD* 0 R/W Way 3 Load 8 W3LOCK 0 R/W Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD = 1 and W3LOCK = 1 in cache locking mode, the data is always loaded into way 3. Under any other condition, the cache miss data is loaded into the way to which LRU points.  7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 W2LOAD* 0 R/W Way 2 Load 0 W2LOCK 0 R/W Way 2 Lock When a cache miss occurs by the prefetch instruction while W2LOAD = 1 and W2LOCK =1 in cache locking mode, the data is always loaded into way 2. Under any other condition, the cache miss data is loaded into the way to which LRU points. Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 253 of 3092 SH7268 Group, SH7269 Group Section 9 Cache Table 9.3 LE Way to be Replaced when a Cache Miss Occurs in PREF Instruction W3LOAD* W3LOCK W2LOAD* W2LOCK Way to be Replaced 0 x x x x Decided by LRU (table 9.1) 1 x 0 x 0 Decided by LRU (table 9.1) 1 x 0 0 1 Decided by LRU (table 9.5) 1 0 1 x 0 Decided by LRU (table 9.6) 1 0 1 0 1 Decided by LRU (table 9.7) 1 0 x 1 1 Way 2 1 1 1 0 x Way 3 [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 9.4 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction LE W3LOAD* W3LOCK W2LOAD* W2LOCK Way to be Replaced 0 x x x x Decided by LRU (table 9.1) 1 x 0 x 0 Decided by LRU (table 9.1) 1 x 0 x 1 Decided by LRU (table 9.5) 1 x 1 x 0 Decided by LRU (table 9.6) 1 x 1 x 1 Decided by LRU (table 9.7) [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 9.5 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 0) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0 Page 254 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Table 9.6 Section 9 Cache LRU and Way Replacement (when W2LOCK = 0 and W3LOCK = 1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 Table 9.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 255 of 3092 Section 9 Cache 9.3 SH7268 Group, SH7269 Group Operation Operations for the operand cache are described here. Operations for the instruction cache are similar to those for the operand cache except for the address array not having the U bit, and there being no prefetch operation or write operation, or a write-back buffer. 9.3.1 Searching Cache If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is accessed, the cache will be searched to see if the desired data is in the cache. Figure 9.2 illustrates the method by which the cache is searched. Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits 31 to 11 of the address used to access memory are compared with the read tag address. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V  1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V  0), a cache miss occurs. Figure 9.2 shows a hit on way 1. Page 256 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 9 Cache Access address 31 11 10 4 3 21 0 Entry selection Longword (LW) selection Data array (ways 0 to 3) Address array (ways 0 to 3) Entry 0 V Entry 0 U Tag address LW0 LW1 LW2 LW3 Entry 1 Entry 1 . . . . . . . . . . . . . . . . . . Entry 127 Entry 127 CMP0 CMP1 CMP2 CMP3 Hit signal (way 1) [Legend] CMP0 to CMP3: Comparison circuits 0 to 3 Figure 9.2 Cache Search Scheme R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 257 of 3092 Section 9 Cache 9.3.2 (1) SH7268 Group, SH7269 Group Read Access Read Hit In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. (2) Read Miss An internal bus cycle starts and the entry is updated. The way replaced follows table 9.4. Entries are updated in 16-byte units. When the desired data that caused the miss is loaded from the external memory or the large-capacity on-chip RAM to the cache, the data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the entry to be replaced by updating the entry in writeback mode is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. Cache update operation and write-back operation to the memory are performed in wrap-around mode. When the lower four bits of the address of readmiss data are H'4, for example, cache update operation and write-back operation to the memory are performed in the following order of the lower 4-bit value of address: H'4  H'8  H'C  H'0. 9.3.3 (1) Prefetch Operation (Only for Operand Cache) Prefetch Hit LRU is updated so that the hit way becomes the latest. The contents in other caches are not modified. No data is transferred to the CPU. (2) Prefetch Miss No data is transferred to the CPU. The way to be replaced follows table 9.3. Other operations are the same as those in the case of read miss. Page 258 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 9.3.4 (1) Section 9 Cache Write Operation (Only for Operand Cache) Write Hit In a write access in write-back mode, the data is written to the cache and no write cycle to the external memory or the large-capacity on-chip RAM is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit way becomes the latest. In write-through mode, the data is written to the cache and a write cycle to the external memory or the large-capacity on-chip RAM is issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way becomes the latest. (2) Write Miss In write-back mode, an internal bus cycle starts when a write miss occurs, and the entry is updated. The way to be replaced follows table 9.4. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. Cache update operation and write-back operation to the memory are performed in wrap-around mode. When the lower four bits of the address of write-miss data are H'4, for example, cache update operation and write-back operation to the memory are performed in the following order of the lower 4-bit value of address: H'4  H'8  H'C  H'0. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory or the large-capacity on-chip RAM. 9.3.5 Write-Back Buffer (Only for Operand Cache) When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory or the large-capacity on-chip RAM. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to the external memory or the large-capacity onchip RAM. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 9.3 shows the configuration of the write-back buffer. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 259 of 3092 SH7268 Group, SH7269 Group Section 9 Cache A (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 A (31 to 4): Physical address written to external memory (upper three bits are 0) Longword 0 to 3: One line of cache data to be written to external memory Figure 9.3 Write-Back Buffer Configuration Operations in sections 9.3.2 to 9.3.5 are summarized in table 9.8. Table 9.8 Cache Operations Write-Back Mode/ Cache Hit/ Write-Through Cycle Miss Mode U Bit RAM (Through Internal Bus) Cache Contents   Not generated Not updated   Cache update cycle is Updated to new values by cache generated update cycle x Not generated Not updated  Cache update cycle is Updated to new values by cache generated update cycle Cache update cycle is Updated to new values by cache generated update cycle Cache update cycle is Updated to new values by cache generated. Then write-back update cycle Instruction Instruction Hit cache Access to External Memory CPU or Large-Capacity On-Chip fetch Miss Operand Prefetch/ cache read Hit Either mode is available Miss Write-through mode Write-back mode 0 1 cycle in write-back buffer is generated. Write Hit Write-through  mode Write-back mode x Write cycle CPU issue is Updated to new values by write generated. cycle the CPU issues Not generated Updated to new values by write cycle the CPU issues Miss Write-through  mode Write-back mode Write cycle CPU issue is Not updated* generated. 0 Cache update cycle is Updated to new values by cache generated update cycle. Subsequently updated again to new values in write cycle CPU issues. 1 Page 260 of 3092 Cache update cycle is Updated to new values by cache generated. Then write-back update cycle. Subsequently cycle in write-back buffer is updated again to new values in generated. write cycle CPU issues. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 9 Cache [Legend] x: Don't care. Note: Cache update cycle: 16-byte read access Write-back cycle in write-back buffer: 16-byte write access * Neither LRU updated. LRU is updated in all other cases. 9.3.6 Coherency of Cache and External Memory or Large-Capacity On-Chip RAM Use software to ensure coherency between the cache and the external memory or the largecapacity on-chip RAM. When memory shared by this LSI and another device is mapped in the cache-enabled space, operate the memory-mapped cache to invalidate and write back as required. The same operation should be performed for the memory shared by the CPU and the direct memory access controller in this LSI. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 261 of 3092 Section 9 Cache 9.4 SH7268 Group, SH7269 Group Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 9.4.1 Address Array To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. In the address field, specify the entry address for selecting the entry, the W bit for selecting the way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is fixed at longword, specify B'00 for bits 1 and 0 of the address. The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always specify 0 for the upper three bits (bits 31 to 29) of the tag address. For the address and data formats, see figure 9.4. The following three operations are possible for the address array. (1) Address Array Read The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry address specified by the address and the entry corresponding to the way. For the read operation, associative operation is not performed regardless of whether the associative bit (A bit) specified by the address is 1 or 0. (2) Address-Array Write (Non-Associative Operation) When the associative bit (A bit) in the address field is cleared to 0, write the tag address, LRU bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address specified by the address and the entry corresponding to the way. When writing to a cache line for which the U bit = 1 and the V bit = 1 in the operand cache address array, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. Page 262 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 9 Cache Write-back operation to the memory is performed in the following order of the lower 4-bit value of address: H'0  H'4  H'8  H'C. (3) Address-Array Write (Associative Operation) When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field are compared with the tag address that is specified by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that has a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. Write-back operation to the memory is performed in the following order of the lower 4-bit value of address: H'0  H'4  H'8  H'C. 9.4.2 Data Array To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. Specify the entry address for selecting the entry, the L bit indicating the longword position within the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword, specify B'00 for bits 1 and 0 of the address. For the address and data formats, see figure 9.4. The following two operations are possible for the data array. Information in the address array is not modified by this operation. (1) Data Array Read The data specified by the L bit in the address is read from the entry address specified by the address and the entry corresponding to the way. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 263 of 3092 SH7268 Group, SH7269 Group Section 9 Cache (2) Data Array Write The longword data specified by the data is written to the position specified by the L bit in the address from the entry address specified by the address and the entry corresponding to the way. 1. Instruction cache 2. Operand cache 1.1 Address array access 2.1 Address array access (a) Address specification (a) Address specification Read access 31 23 22 Read access 13 12 11 10 111100000 *----------* Write access 31 23 22 4 Entry address W 3 2 1 0 31 0 * 0 0 111100001 *----------* 3 2 1 0 31 A * 0 0 111100001 *----------* 3 2 1 0 31 X X X V 0 0 0 Tag address (28 to 11) E 13 12 11 10 W 4 Entry address W 4 Entry address 4 11 10 9 29 28 0 0 0 Tag address (28 to 11) E LRU 23 22 13 12 11 10 W 4 Entry address 4 11 10 9 29 28 LRU 1.2 Data array access (both read and write accesses) 2.2 Data array access (both read and write accesses) (a) Address specification (a) Address specification 23 22 2 1 0 * 0 0 13 12 11 10 111100010 *----------* W 4 3 2 1 0 A * 0 0 (b) Data specification (both read and write accesses) (b) Data specification (both read and write accesses) 31 3 0 Write access 13 12 11 10 111100000 *----------* 31 23 22 3 Entry address 2 L 1 0 31 0 0 111100011 *----------* 23 22 13 12 11 10 W Entry address 4 3 2 1 0 X X U V 1 0 0 0 3 2 L (b) Data specification (b) Data specification 31 0 Longword data 31 0 Longword data [Legend] *: Don't care E: Bit 10 of entry address for read, don't care for write X: 0 for read, don't care for write Figure 9.4 Specifying Address and Data for Memory-Mapped Cache Access Page 264 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 9.4.3 (1) Section 9 Cache Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. An example when a write data is specified in R0 and an address is specified in R1 is shown below. ; R0=H'0110 0010; tag address(28-11)=B'0 0001 0001 0000 0000 0, U=0, V=0 ; R1=H'F080 0088; operand cache address array access, entry=B'000 1000, A=1 ; MOV.L R0,@R1 (2) Reading the Data of a Specific Entry The data section of a specific cache entry can be read by the memory mapping cache access. The longword indicated in the data field of the data array in figure 9.4 is read into the register. An example when an address is specified in R0 and data is read in R1 is shown below. ; R0=H'F100 004C; instruction cache data array access, entry=B'000 0100, ; Way=0, longword address=3 ; MOV.L @R0,R1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 265 of 3092 Section 9 Cache 9.4.4 SH7268 Group, SH7269 Group Usage Notes 1. Programs that access memory-mapped cache of the operand cache should be placed in a cachedisabled space. Programs that access memory-mapped cache of the instruction cache should be placed in a cache-disabled space, and in each of the beginning and the end of that, two or more read accesses to on-chip peripheral modules or external address space (cache-disabled address) should be executed. 2. Rewriting the address array contents so that two or more ways are hit simultaneously is prohibited. Operation is not guaranteed if the address array contents are changed so that two or more ways are hit simultaneously. 3. Registers and memory-mapped cache can be accessed only by the CPU and not by the direct memory access controller. Page 266 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Section 10 Bus State Controller The bus state controller outputs control signals for various types of memory and external devices that are connected to the external address space. The functions of this module enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 10.1 Features 1. External address space  A maximum of 64 Mbytes for each of areas CS0 to CS5.  Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clocked synchronous or asynchronous), MPX-I/O, SDRAM memory type, and PCMCIA interface for each address space.  Can select the data bus width (8, 16, or 32 bits) for each of address spaces.  Controls insertion of wait cycles for each address space.  Controls insertion of wait cycles for each read access and write access.  Can set independent idle cycles during the continuous access for five cases: read-write (in same space/different spaces), read-read (in same space/different spaces), the first cycle is a write access. 2. Normal space interface  Supports the interface that can directly connect to the SRAM. 3. Burst ROM interface (clocked asynchronous)  High-speed access to the ROM that has the page mode function. 4. MPX-I/O interface  Can directly connect to a peripheral LSI that needs an address/data multiplexing. 5. SDRAM interface  Can set the SDRAM in up to two areas.  Multiplex output for row address/column address.  Efficient access by single read/single write.  High-speed access in bank-active mode.  Supports an auto-refresh and self-refresh.  Supports a power-down mode.  Issues MRS and EMRS commands. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 267 of 3092 Section 10 Bus State Controller SH7268 Group, SH7269 Group 6. PCMCIA direct interface  Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver. 4.2 (PCMCIA2.1 Rev. 2.1).  Wait-cycle insertion controllable by program. 7. SRAM interface with byte selection  Can connect directly to a SRAM with byte selection. 8. Burst ROM interface (clocked synchronous)  Can connect directly to a burst ROM of the clocked synchronous type. 9. Bus arbitration  Shares all of the resources with other CPU and outputs the bus enable after receiving the bus request from external devices. 10. Refresh function  Supports the auto-refresh and self-refresh functions.  Specifies the refresh interval using the refresh counter and clock selection.  Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 11. Usage as interval timer for refresh counter  Generates an interrupt request at compare match. Page 268 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller BREQ BACK Bus request from NAND flash memory controller Bus use enable for NAND flash memory controller WAIT Bus mastership controller Wait controller Internal bus Figure 10.1 shows a block diagram of this module. CMNCR . . . CS0WCR . . . CS0 to CS5 A25 to A0, D31 to D0, BS, RD/WR, RD, WE3 to WE0, RAS, CAS, CKE, DQMxx, AH, IOIS16, CE2A Area controller . . . CS0BCR . . . CS5BCR . . . Module bus CS5WCR Memory controller SDCR RTCSR RTCNT Refresh controller Comparator RTCOR BSC [Legend] CMNCR: CSnWCR: CSnBCR: SDCR: RTCSR: RTCNT: RTCOR: Common control register CSn space wait control register (n = 0 to 5) CSn space bus control register (n = 0 to 5) SDRAM control register Refresh timer control/status register Refresh timer counter Refresh time constant register Figure 10.1 Block Diagram of Bus State Controller R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 269 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.2 Input/Output Pins Table 10.1 shows the pin configuration. Table 10.1 Pin Configuration Name I/O Function A25 to A0 Output Address bus D31 to D0 I/O Data bus BS Output Bus cycle start CS0 to CS4 Output Chip select CS5/CE1A Output Chip select Function as PCMCIA card select signals for D7 to D0 when PCMCIA is used. CE2A Output Function as PCMCIA card select signals for D15 to D8. RD/WR Output Read/write Connects to WE pins when SDRAM or SRAM with byte selection is connected. RD Output Read pulse signal (read data output enable signal) Functions as a strobe signal for indicating memory read cycles when PCMCIA is used. WE3/DQMUU/ICIOWR/ AH Output Indicates that D31 to D24 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D31 to D24 when SDRAM is connected. Functions as a strobe signal for indicating I/O write cycles when PCMCIA is used. Functions as the address hold signal when the MPX-I/O is used. WE2/DQMUL/ICIORD Output Indicates that D23 to D16 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D23 to D16 when SDRAM is connected. Functions as a strobe signal for indicating I/O read cycles when PCMCIA is used. Page 270 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Name I/O Function WE1/DQMLU/WE Output Indicates that D15 to D8 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D15 to D8 when SDRAM is connected. Functions as a strobe signal for indicating memory write cycles when PCMCIA is used. WE0/DQMLL Output Indicates that D7 to D0 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D7 to D0 when SDRAM is connected. RAS Output Connects to RAS pin when SDRAM is connected. CAS Output Connects to CAS pin when SDRAM is connected. CKE Output Connects to CKE pin when SDRAM is connected. WAIT Input External wait input BREQ Input Bus request input BACK Output Bus enable output IOIS16 Input Indicates 16-bit I/O of PCMIA. Enabled only in little endian mode. The pin should be driven low in big endian mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 271 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.3 Area Overview 10.3.1 Address Map In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cache-disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address. External address spaces CS0 to CS5 are cache-enabled when internal address A29 = 0 or cachedisabled when A29 = 1. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 10.2 Address Map Internal Address Space Memory to be Connected Cache H'00000000 to H'03FFFFFF CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) Cache-enabled H'04000000 to H'07FFFFFF CS1 Normal space, SRAM with byte selection H'08000000 to H'0BFFFFFF CS2 Normal space, SRAM with byte selection, SDRAM H'0C000000 to H'0FFFFFFF CS3 Normal space, SRAM with byte selection, SDRAM H'10000000 to H'13FFFFFF CS4 Normal space, SRAM with byte selection, burst ROM (asynchronous) H'14000000 to H'17FFFFFF CS5 Normal space, SRAM with byte selection, MPX-I/O, PCMCIA H'18000000 to H'1FFFFFFF Other SPI multi I/O bus space, large-capacity on-chip RAM, reserved area* H'20000000 to H'23FFFFFF CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) H'24000000 to H'27FFFFFF CS1 Normal space, SRAM with byte selection H'28000000 to H'2BFFFFFF CS2 Normal space, SRAM with byte selection, SDRAM H'2C000000 to H'2FFFFFFF CS3 Normal space, SRAM with byte selection, SDRAM H'30000000 to H'33FFFFFF CS4 Normal space, SRAM with byte selection, burst ROM (asynchronous) H'34000000 to H'37FFFFFF CS5 Normal space, SRAM with byte selection, MPX-I/O, PCMCIA Page 272 of 3092 Cache-disabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Internal Address Space Memory to be Connected Cache H'38000000 to H'3FFFFFFF Other SPI multi I/O bus space, large-capacity on-chip RAM, reserved area* Cache-disabled H'40000000 to H'FFFFFFFF Other High-speed on-chip RAM, on-chip peripheral modules, reserved area*  Note: 10.3.2 * For the large-capacity on-chip RAM space and high-speed on-chip RAM space, access the addresses shown in section 47, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 51, List of Registers. Do not access addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed. Data Bus Width, Endian Specification, and Related Pin Setting for Each Area Depending on Boot Mode The initial state of data bus width, endian specification, and settings of the pins related to this module depends on boot mode. For boot mode, refer to section 4, Boot Mode. In boot modes 0 and 1, the state of area 0 is fixed to the state with bus width of 16 or 32 bits and big endian, because this LSI is started up by the program stored in the ROM connected to area 0. The initial states of areas 1 to 5 are the same as that of area 0, but can be changed by the program. Immediately after a power-on reset in these modes, some of the address and data-bus signals and the CS0 and RD signals are automatically selected by default as the functions of the corresponding pins, since these signals are required to read ROM data from area 0. With the exception of these pins, the general purpose pin function is selected by default, and other required pin functions must be specified by the program. Read access to area 0 is only permitted before the pin settings are completed. In boot modes 2 to 5, the state of areas 0 to 5 can be changed from the initial state by the program, because the LSI is started by the program stored in the NAND flash memory, the serial flash memory, the NAND flash memory with the SD controller, or the NAND flash memory with the MMC controller. Since pin functions related to this module are not set automatically, they need to be set by the program. Do not access external address spaces before the pin settings are completed. Table 10.3 shows the initial state by areas 0 to 5 in boot modes 0, 1, and 2 to 5. The sample access waveforms shown in this section include the pins such as BS, RD/WR, and WEn. They are the waveforms when pin functions are assigned to the general I/O ports. For example, when 16-bit bus width is used in boot mode 1, setting for pin A1 is needed. When 8-bit bus width is used, setting for pins A1 and A0 is also needed. For details on pin function settings, see section 48, General Purpose I/O Ports. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 273 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.3 Initial States by Areas in Boot Modes 0, 1, and 2 to 5 Boot Mode Item Area 0 Areas 1 to 5 0 Data bus width Fixed to 16 bits. Not changeable. 16 bits. Can be changed by program. Endian specification Fixed to big endian. Not changeable. Big endian. Can be changed by program. Settings of pins related to this module Pins A20 to A1, D15 to D0, CS0, and RD are set automatically. Other pins need to be set by program. Data bus width Fixed to 32 bits. Not changeable. 32 bits. Can be changed by program. Endian specification Fixed to big endian. Not changeable. Big endian. Can be changed by program. Settings of pins related to this module Pins A20 to A2, D31 to D0, CS0, and RD are set automatically. Other pins need to be set by program. Data bus width 32 bits. Can be changed by program. Endian specification Big endian. Can be changed by program. Settings of pins related to this module General I/O function. For external bus access, all the necessary pins need to be set by program. 1 2 to 5 Notes: 1. In boot mode 0 or 1, if a boot ROM that uses higher-order address lines than A21 is connected, the circuit board must include pull-down resistors for those address lines. 2. The data-bus width may be limited by the type of memory in use. For details, section 10.4.2, CSn Space Bus Control Register (CSnBCR) (n = 0 to 5). 3. Since the CS4 and A22 pin functions are assigned to the same pin, area 4 and modules requiring A22 and higher-order address lines cannot be used at the same time. Page 274 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.4 Section 10 Bus State Controller Register Descriptions Table 10.4 shows the register configuration of this module. Do not access the areas until settings of the connected memory interface are completed. Table 10.4 Register Configuration R/W Initial Value Address Access Size Common control register CMNCR R/W H'00001010 H'FFFC0000 32 CS0 space bus control register CS0BCR R/W H'36DB0400* H'FFFC0004 32 CS1 space bus control register CS1BCR R/W H'36DB0400* H'FFFC0008 32 CS2 space bus control register CS2BCR R/W H'36DB0400* H'FFFC000C 32 CS3 space bus control register CS3BCR R/W H'36DB0400* H'FFFC0010 32 CS4 space bus control register CS4BCR R/W H'36DB0400* H'FFFC0014 32 CS5 space bus control register CS5BCR R/W H'36DB0400* H'FFFC0018 32 CS0 space wait control register CS0WCR R/W H'00000500 H'FFFC0028 32 CS1 space wait control register CS1WCR R/W H'00000500 H'FFFC002C 32 CS2 space wait control register CS2WCR R/W H'00000500 H'FFFC0030 32 CS3 space wait control register CS3WCR R/W H'00000500 H'FFFC0034 32 CS4 space wait control register CS4WCR R/W H'00000500 H'FFFC0038 32 CS5 space wait control register CS5WCR R/W H'00000500 H'FFFC003C 32 Register Name R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Abbreviation Page 275 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Register Name Abbreviation R/W Initial Value Address Access Size SDRAM control register SDCR R/W H'00000000 H'FFFC004C 32 Refresh timer control/status register RTCSR R/W H'00000000 H'FFFC0050 32 Refresh timer counter RTCNT R/W H'00000000 H'FFFC0054 32 Refresh time constant register RTCOR R/W H'00000000 H'FFFC0058 32 Note: * H'36DB0400 in boot mode 0; H'36DB0600 in boot modes 1 to 5 Page 276 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.4.1 Section 10 Bus State Controller Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 - - - - BLOCK Initial value: R/W: 0 R 0 R 0 R 1 R 0 R/W Bit Bit Name Initial Value R/W Description 31 to 13  All 0 R Reserved DPRTY[1:0] 0 R/W 0 R/W DMAIW[2:0] 0 R/W 0 R/W 0 R/W 5 4 3 2 1 0 DMA IWA - - - HIZ MEM HIZ CNT* 0 R/W 1 R 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 12  1 R Reserved This bit is always read as 1. The write value should always be 1. 11 BLOCK 0 R/W Bus Lock Specifies whether or not the BREQ signal is received. 0: Receives BREQ. 1: Does not receive BREQ. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 277 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Initial Value Bit Bit Name 10, 9 DPRTY[1:0] 00 R/W Description R/W DMA Burst Transfer Priority Specify the priority for a refresh request/bus mastership request during DMA burst transfer. 00: Accepts a refresh request and bus mastership request during DMA burst transfer. 01: Accepts a refresh request but does not accept a bus mastership request during DMA burst transfer. 10: Accepts neither a refresh request nor a bus mastership request during DMA burst transfer. 11: Reserved (setting prohibited) 8 to 6 DMAIW[2:0] 000 R/W Wait states between access cycles when DMA single address transfer is performed. Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Page 278 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 5 DMAIWA 0 R/W Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. However, when the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after an access to an external device with DACK, even when the continuous access cycles to an external device with DACK are performed. 0: Idle cycles inserted when another device drives the data bus after an external device with DACK drove it. 1: Idle cycles always inserted after an access to an external device with DACK 4  1 R Reserved This bit is always read as 1. The write value should always be 1. 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in software standby mode or deep standby mode for A25 to A0, BS, CSn, CE2A, RD/WR, WEn/DQMxx/AH, and RD. At bus-released state, these pin are high-impedance states regardless of the setting value of the HIZMEM bit. 0: High impedance in software standby mode or deep standby mode. 1: Driven in software standby mode or deep standby mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 279 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 0 HIZCNT* 0 R/W High-Z Control Specifies the state in software standby mode, deep standby mode, or bus-released state for CKE, RAS, and CAS. 0: High impedance in software standby mode, deep standby mode, or bus-released state for CKE, RAS, and CAS. 1: Driven in software standby mode, deep standby mode, or bus-released state for CKE, RAS, and CAS. Note: * For High-Z control of CKIO, see section 5, Clock Pulse Generator. Page 280 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.4.2 Section 10 Bus State Controller CSn Space Bus Control Register (CSnBCR) (n = 0 to 5) CSnBCR is a 32-bit readable/writable register that specifies the memory connected to each space, the number of idle cycles between bus cycles, and the bus width. Do not access external memory for the corresponding area until CSnBCR initial setting and pin setting are completed. Idle cycles may be inserted even when they are not specified. For details, see section 10.5.11, Wait between Access Cycles. Bit: 31 30 - Initial value: R/W: 0 R 0 R/W Bit: 15 14 - Initial value: R/W: 0 R 29 28 27 IWW[2:0] 1 R/W 1 R/W 13 12 TYPE[2:0] 0 R/W 0 R/W 26 25 24 IWRWD[2:0] 22 21 20 19 18 IWRRD[2:0] 17 16 IWRRS[2:0] 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 11 10 9 8 7 6 5 4 3 2 1 0 BSZ[1:0] - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ENDIAN 0 R/W 23 IWRWS[2:0] 0 R/W 1* R/W 0* R/W Note: * B'10 in boot mode 0; B'11 in boot mode 1 to 5. Bit Bit Name Initial Value R/W Description 31  0 R 30 to 28 IWW[2:0] 011 R/W Reserved This bit is always read as 0. The write value should always be 0. Idle Cycles between Write-Read Cycles and WriteWrite Cycles These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 281 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Initial Value Bit Bit Name 27 to 25 IWRWD[2:0] 011 R/W R/W Description Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous access cycles switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 24 to 22 IWRWS[2:0] 011 R/W Idle Cycles for Read-Write in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Page 282 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Initial Value Bit Bit Name 21 to 19 IWRRD[2:0] 011 R/W Description R/W Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles switch between different space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 18 to 16 IWRRS[2:0] 011 R/W Idle Cycles for Read-Read in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 15  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 283 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 14 to 12 TYPE[2:0] 000 R/W Specify the type of memory connected to a space. 000: Normal space 001: Burst ROM (clock asynchronous) 010: MPX-I/O 011: SRAM with byte selection 100: SDRAM 101: PCMCIA 110: Reserved (setting prohibited) 111: Burst ROM (clock synchronous) For details for memory type in each area, see table 10.2. Note: When connecting the burst ROM to the CS0 space in boot modes 0 and 1, change the CS0WCR register to the settings by the burst ROM CS0WCR uses and then set TYPE[2:0] to the burst ROM setting. In boot modes 2 to 5, memory access should be performed after setting CS0BCR and CS0WCR. 11 ENDIAN 0 R/W Endian Setting Specifies the arrangement of data in a space. 0: Arranged in big endian 1: Arranged in little endian Note: Little endian cannot be set for area 0 in boot modes 0 and 1. In this case, this bit of CS0BCR is always read as 0. The write value should always be 0. Page 284 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10, 9 BSZ[1:0] 10* R/W Data Bus Width Specification Specify the data bus widths of spaces. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size For MPX-I/O, selects bus width by address Notes: 1. If area 5 is specified as MPX-I/O, the bus width can be specified as 8 bits or 16 bits by the address according to the SZSEL bit in CS5WCR by specifying the BSZ[1:0] bits to 11. The fixed bus width can be specified as 8 bits or 16 bits 2. In boot modes 0 and 1, the BSZ[1:0] bits settings in CS0BCR are ignored. 3. If area 5 is specified as PCMCIA space, the bus width can be specified as either 8 bits or 16 bits. 4. If area 2 or area 3 is specified as SDRAM space, the bus width can be specified as either 16 bits or 32 bits. 5. If area 0 is specified as clocked synchronous burst ROM space, the bus width can be specified as either 16 bits or 32 bits.  8 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * B'10 in boot mode 0; B'11 in boot modes 1 to 5. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 285 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 5) CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. (1) Normal Space, SRAM with Byte Selection, and MPX-I/O  CS0WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - -* BAS - - -* -* Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 1 0 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21 * 0 R/W Reserved Set this bit to 0 when the interfaces for normal space or for SRAM with byte selection are used. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 6 5 4 3 2 WM - - - - 0 R/W 0 R 0 R 0 R 0 R HW[1:0] 0 R/W 0 R/W 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19, 18  Page 286 of 3092 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 17, 16 * All 0 R/W Reserved Set these bits to 0 when the interfaces for normal space or for SRAM with byte selection are used. 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS0 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS0 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 287 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored  5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 Delay Cycles from RD, WEn Negation to Address, CS0 Negation R/W Specify the number of delay cycles from RD and WEn negation to address and CS0 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Note: * In boot modes 0 and 1, to connect the burst ROM to the CS0 space and switch to burst ROM interface after activation, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits 20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the reserved bits other than above bits.  CS1WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - - BAS - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 1 0 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 18 17 16 WW[2:0] 6 5 4 3 2 WM - - - - 0 R/W 0 R 0 R 0 R 0 R HW[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. Page 288 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 289 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] Page 290 of 3092 00 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller  CS2WCR, CS3WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - BAS - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 0 - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved WR[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 16 6 5 4 3 2 1 WM - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 291 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 292 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller  CS4WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - - BAS - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 1 0 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W 31 to 21  All 0 R SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 18 17 16 WW[2:0] 6 5 4 3 2 WM - - - - 0 R/W 0 R 0 R 0 R 0 R HW[1:0] 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 293 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Page 294 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Page 295 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller  CS5WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - SZSEL MPXW/ BAS - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 0 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 18 17 16 WW[2:0] 6 5 4 3 2 1 WM - - - - HW[1:0] 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 21 20 SZSEL MPXW Page 296 of 3092 0 0 R/W R/W MPX-I/O Interface Bus Width Specification Specifies an address to select the bus width when the BSZ[1:0] of CS5BCR are specified as 11. This bit is valid only when area 5 is specified as MPX-I/O. 0: Selects the bus width by address A14 1: Selects the bus width by address A21 The relationship between the SZSEL bit and bus width selected by A14 or A21 are summarized below. SZSEL A14 A21 Bus Width 0 0 Not affected 8 bits 0 1 Not affected 16 bits 1 Not affected 0 8 bits 1 Not affected 1 16 bits MPX-I/O Interface Address Wait This bit setting is valid only when area 5 is specified as MPX-I/O. Specifies the address cycle insertion wait for MPX-I/O interface. 0: Inserts no wait cycle 1: Inserts 1 wait cycle R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select This bit setting is valid only when area 5 is specified as SRAM with byte selection. Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS5 Assertion to RD, WE Assertion These bits specify the number of delay cycles from address and CS5 assertion to RD and WEn assertion when area 5 is specified as normal space or SRAM with byte selection. They specify the number of delay cycles from address cycle (Ta3) to RD and WEn assertion when area 5 is specified as MPX-I/O. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 297 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] Page 298 of 3092 00 R/W Delay Cycles from RD, WEn Negation to Address, CS5 Negation These bits specify the number of delay cycles from RD and WEn negation to address and CS5 negation when area 5 is specified as normal space or SRAM with byte selection. They specify the number of delay cycles from RD and WEn negation to CS5 negation when area 5 is specified as MPX-I/O. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 10 Bus State Controller Burst ROM (Clocked Asynchronous)  CS0WCR Bit: 31 30 29 28 27 26 25 24 23 22 - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved W[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 21 20 19 18 - - 0 R/W 0 R 0 R 0 R/W 0 R/W 0 BST[1:0] 17 16 BW[1:0] 6 5 4 3 2 1 WM - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 21, 20 BST[1:0] 00 R/W Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11, because B'11 setting is reserved. Bus Width BST[1:0] Burst count 8 bits 00 16 burst  one time 01 4 burst  four times 00 8 burst  one time 01 2 burst  four times 10 4-4 or 2-4-2 burst xx 4 burst  one time 16 bits 32 bits 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 299 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 7 W[3:0] Page 300 of 3092 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 301 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller  CS4WCR Bit: 31 30 29 28 27 26 25 24 23 22 - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved SW[1:0] 0 R/W W[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 21 20 19 18 - - 0 R/W 0 R 0 R 0 R/W 0 R/W 0 BST[1:0] 17 16 BW[1:0] 6 5 4 3 2 1 WM - - - - HW[1:0] 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 21, 20 BST[1:0] 00 R/W Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11, because B'11 setting is reserved. Bus Width BST[1:0] Burst count 8 bits 00 16 burst  one time 01 4 burst  four times 00 8 burst  one time 01 2 burst  four times 10 4-4 or 2-4-2 burst xx 4 burst  one time 16 bits 32 bits 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Page 302 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 303 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 (3) HW[1:0] 00 Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R/W SDRAM*  CS2WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - A2CL[1:0] - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved 1 R/W 0 R/W 16 These bits are always read as 0. The write value should always be 0. 10  1 R Reserved This bit is always read as 1. The write value should always be 1. 9  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 304 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 8, 7 A2CL[1:0] 10 R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles  6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection.  CS3WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 4 3 2 1 0 - Initial value: R/W: 0 R WTRP[1:0]* 0 R/W 0 R/W 9 8 7 6 5 - WTRCD[1:0]* - A3CL[1:0] - - 0 R 0 R/W 0 R 0 R 0 R 1 R/W 1 R/W 0 R/W TRWL[1:0]* 0 R/W 0 R/W - 0 R WTRC[1:0]* 0 R/W 0 R/W Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. Bit Bit Name Initial Value R/W 31 to 15  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 305 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Initial Value Bit Bit Name 14, 13 WTRP[1:0]* 00 R/W Description R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles as shown below.  From the start of auto-precharge and issuing of ACTV command for the same bank  From issuing of the PRE/PALL command to issuing of the ACTV command for the same bank  Till entering the power-down mode or deep powerdown mode  From the issuing of PALL command to issuing REF command in auto refresh mode  From the issuing of PALL command to issuing SELF command in self refresh mode The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD[1:0] 01 * R/W Number of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 306 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4, 3 TRWL[1:0]* 00 R/W Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum auto-precharge startup wait cycles as shown below.  Cycle number from the issuance of the WRITA command by this LSI until the completion of autoprecharge in the SDRAM. Equivalent to the cycle number from the issuance of the WRITA command until the issuance of the ACTV command. Confirm that how many cycles are required between the WRITA command receive in the SDRAM and the auto-precharge activation, referring to each SDRAM data sheet. And set the cycle number so as not to exceed the cycle number specified by this bit.  Cycle number from the issuance of the WRIT command until the issuance of the PRE command. This is the case when accessing another low address in the same bank in bank active mode. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 307 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Initial Value Bit Bit Name 1, 0 WTRC[1:0]* 00 R/W Description R/W Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the periods shown below.  From the issuance of the REF command until the issuance of the ACTV/REF/MRS command  From releasing self-refresh until the issuance of the ACTV/REF/MRS command. The setting for areas 2 and 3 is common. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection. Page 308 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 10 Bus State Controller PCMCIA  CS5WCR Bit: 31 30 29 28 27 26 25 24 23 22 - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 - TED[3:0] PCW[3:0] Initial value: R/W: 0 R Bit Bit Name Initial Value R/W 31 to 22  All 0 R 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 21 20 19 18 17 16 - - - - 0 R/W 0 R 0 R 0 R 0 R 3 2 1 0 SA[1:0] 6 5 4 WM - - 0 R 0 R 0 R TEH[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 SA[1:0] 00 R/W Space Attribute Specification Select memory card interface or I/O card interface when PCMCIA interface is selected. SA1: 0: Selects memory card interface for the space for A25 = 1. 1: Selects I/O card interface for the space for A25 = 1. SA0: 0: Selects memory card interface for the space for A25 = 0. 1: Selects I/O card interface for the space for A25 = 0. 19 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 309 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 14 to 11 TED[3:0] 0000 R/W Number of Delay Cycles from Address Output to RD/WE Assertion Specify the number of delay cycles from address output to RD/WE assertion for the memory card or to ICIORD/ICIOWR assertion for the I/O card in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Page 310 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 PCW[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 311 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 3 to 0 TEH[3:0] 0000 R/W Delay Cycles from RD/WE Negation to Address Specify the number of address hold cycles from RD/WE negation for the memory card or those from ICIORD/ICIOWR negation for the I/O card in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Page 312 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 10 Bus State Controller Burst ROM (Clocked Synchronous)  CS0WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 0 - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 18  All 0 R Reserved W[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 17 16 BW[1:0] 6 5 4 3 2 1 WM - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 313 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 314 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.4.4 Section 10 Bus State Controller SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit: 31 30 29 28 27 26 25 24 23 22 21 - - - - - - - - - - - A2ROW[1:0] - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - DEEP - RFSH RMODEPDOWN BACTV - - - 0 R 0 R 0 R/W 0 R 0 R/W 0 R 0 R 0 R Initial value: R/W: 0 R/W Bit Bit Name Initial Value R/W 31 to 21  All 0 R 0 R/W 0 R/W 20 19 A3ROW[1:0] 0 R/W 0 R/W 18 17 16 A2COL[1:0] 0 R/W 0 R/W 1 0 - A3COL[1:0] 0 R 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 20, 19 A2ROW[1:0] 00 R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 18  0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 A2COL[1:0] 00 R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 315 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low-power SDRAM enters the deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11 RFSH 0 R/W Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh 10 RMODE 0 R/W Refresh Control Specifies whether to perform auto-refresh or selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed Page 316 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 9 PDOWN 0 R/W Power-Down Mode Specifies whether the SDRAM will enter the powerdown mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters the power-down mode. 0: The SDRAM does not enter the power-down mode after being accessed. 1: The SDRAM enters the power-down mode after being accessed. 8 BACTV 0 R/W Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be set only for area 3. When both areas 2 and 3 are set to SDRAM, specify the auto-precharge mode. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4, 3 A3ROW[1:0] 00 R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 317 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Initial Value Bit Bit Name 1, 0 A3COL[1:0] 00 R/W Description R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) Page 318 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.4.5 Section 10 Bus State Controller Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on reset. Note that there is an error in the time until the compare match flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value other than B'000. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - CMF CMIE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved 7 CMF 0 R/W Compare Match Flag CKS[2:0] 0 R/W 0 R/W 16 RRC[2:0] 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied. 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables CMF interrupt requests when the CMF bit in RTCSR is set to 1. 0: Disables CMF interrupt requests. 1: Enables CMF interrupt requests. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 319 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 5 to 3 CKS[2:0] 000 R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: CKIO/4 010: CKIO/16 011: CKIO/64 100: CKIO/256 101: CKIO/1024 110: CKIO/2048 111: CKIO/4096 2 to 0 RRC[2:0] 000 R/W Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: 1 time 001: 2 times 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) Page 320 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.4.6 Section 10 Bus State Controller Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - 16 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved These bits are always read as 0. 7 to 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 All 0 R/W 8-Bit Counter Page 321 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.4.7 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests are counted by using timer interrupts while refresh is performed periodically. When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - 16 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 31 to 8  All 0 R Description Reserved These bits are always read as 0. 7 to 0 Page 322 of 3092 All 0 R/W 8-Bit Counter R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.5 Operation 10.5.1 Endian/Access Size and Data Alignment Section 10 Bus State Controller This LSI supports both big endian, in which the most significant byte (MSB) of data is that in the direction of the 0th address, and little endian, in which the least significant byte (LSB) is that in the direction of the 0th address. In the initial state after a power-on reset, all areas will be in big endian mode. Endian mode can be changed by setting the CSnBCR register as long as the target space is not being accessed. Data bus width can be selected from 8 bits, 16 bits, and 32 bits for the normal memory and SRAM with byte selection. Data bus width can be selected from 16 bits and 32 bits for SDRAM. Two data bus widths (8 bits and 16 bits) are available for the PCMCIA interface. For MPX-I/O, the data bus width is fixed to either 8 or 16 bits, or made selectable as 8 bits or 16 bits by one of the address lines. Endian specification and data bus width varies depending on boot mode. For details, refer to section 10.3.2, Data Bus Width, Endian Specification, and Related Pin Setting for Each Area Depending on Boot Mode. Data alignment is performed in accordance with the data bus width selected for the device. This also means that four read operations are required to read longword data from a byte-width device. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 10.5 to 10.10 show the relationship between device data width and access unit. Note that the correspondence between addresses and strobe signals for the 32-bit bus width and 16-bit bus width depends on the endian setting. For example, with big endian and a 16-bit bus width, WE1 corresponds to the 0th address, which is represented by WE0 when little endian has been selected. Since instructions are fetched with both 32- and 16-bit accesses, their alignment in the little-endian area is difficult. Execute instructions from big-endian area. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 323 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.5 32-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3, WE2, WE1, WE0, DQMUU DQMUL DQMLU DQMLL Byte access at address 0 Data 7 to 0    Assert    Byte access at address 1  Data 7 to 0    Assert   Byte access at address 2   Data 7 to 0    Assert  Byte access at address 3    Data 7 to 0    Assert Word access at address 0 Data 15 Data 7 to 8 to 0   Assert Assert   Word access at address 2  Data 15 Data 7 to 8 to 0   Assert Assert Longword access at address 0 Data 31 Data 23 Data 15 Data 7 to 24 to 16 to 8 to 0 Assert Assert Assert Assert Operation Page 324 of 3092  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.6 16-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3, WE2, WE1, WE0, DQMUU DQMUL DQMLU DQMLL Byte access at address 0   Data 7 to 0    Assert  Byte access at address 1    Data 7 to 0    Assert Byte access at address 2   Data 7 to 0    Assert  Byte access at address 3    Data 7 to 0    Assert Word access at address 0   Data 15 Data 7 to 8 to 0   Assert Assert Word access at address 2   Data 15 Data 7 to 8 to 0   Assert Assert Longword access at address 0 1st access at address 0   Data 31 Data 23  to 24 to 16  Assert Assert 2nd access at address 2   Data 31 Data 7 to 24 to 0   Assert Assert R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 325 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.7 8-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3, WE2, WE1, WE0, DQMUU DQMUL DQMLU DQMLL Byte access at address 0    Data 7 to 0    Assert Byte access at address 1    Data 7 to 0    Assert Byte access at address 2    Data 7 to 0    Assert Byte access at address 3    Data 7 to 0    Assert Word access at address 0 1st access at address 0    Data 15  to 8   Assert 2nd access at address 1    Data 7 to 0    Assert 1st access at address 0    Data 15  to 8   Assert 2nd access at address 1    Data 7 to 0    Assert 1st access at address 0    Data 31  to 24   Assert 2nd access at address 1    Data 23  to 16   Assert 3rd access at address 2    Data 15  to 8   Assert 4th access at address 3    Data 7 to 0    Assert Word access at address 2 Longword access at address 0 Page 326 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.8 32-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3, WE2, WE1, WE0, DQMUU DQMUL DQMLU DQMLL Byte access at address 0    Data 7 to 0    Assert Byte access at address 1   Data 7 to 0    Assert  Byte access at address 2  Data 7 to 0    Assert   Byte access at address 3 Data 7 to 0    Assert    Word access at address 0   Data 15 Data 7 to 8 to 0   Assert Assert Word access at address 2 Data 15 Data 7 to 8 to 0  Assert Assert   Longword access at address 0 Data 31 Data 23 Data 15 Data 7 to 24 to 16 to 8 to 0 Assert Assert Assert Assert R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  Page 327 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.9 16-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3, WE2, WE1, WE0, DQMUU DQMUL DQMLU DQMLL Byte access at address 0    Data 7 to 0    Assert Byte access at address 1   Data 7 to 0    Assert  Byte access at address 2    Data 7 to 0    Assert Byte access at address 3   Data 7 to 0    Assert  Word access at address 0   Data 15 Data 7 to 8 to 0   Assert Assert Word access at address 2   Data 15 Data 7 to 8 to 0   Assert Assert Longword access at address 0 1st access at address 0   Data 15 Data 7 to 8 to 0   Assert Assert 2nd access at address 2   Data 31 Data 23  to 24 to 16  Assert Assert Page 328 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.10 8-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3, WE2, WE1, WE0, DQMUU DQMUL DQMLU DQMLL Byte access at address 0    Data 7 to 0    Assert Byte access at address 1    Data 7 to 0    Assert Byte access at address 2    Data 7 to 0    Assert Byte access at address 3    Data 7 to 0    Assert Word access at address 0 1st access at address 0    Data 7 to 0    Assert 2nd access at address 1    Data 15  to 8   Assert 1st access at address 0    Data 7 to 0    Assert 2nd access at address 1    Data 15  to 8   Assert 1st access at address 0    Data 7 to 0    Assert 2nd access at address 1    Data 15  to 8   Assert 3rd access at address 2    Data 23  to 16   Assert 4th access at address 3    Data 31  to 24   Assert Word access at address 2 Longword access at address 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 329 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.5.2 (1) Normal Space Interface Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 10.5.8, SRAM Interface with Byte Selection. Figure 10.2 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 T2 CKIO A25 to A0 CSn RD/WR Read RD D31 to D0 RD/WR Write WEn D31 to D0 BS DACKn * Note: * The waveform for DACKn is when active low is specified. Figure 10.2 Normal Space Basic Access Timing (Access Wait 0) There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always Page 330 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller read in case of a 32-bit device. 16 bits are always read in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is asserted. It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer with this signal, to avoid output collision. Figures 10.3 and 10.4 show the basic timings in continuous access to normal space. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait (figure 10.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 10.4). T1 T2 Tnop T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 10.3 Continuous Access to Normal Space (1) Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 331 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 10.4 Continuous Access to Normal Space (2) Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) Page 332 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller 128K × 8-bit SRAM This LSI A2 CSn RD D31 A0 I/O0 WE A16 CS OE I/O7 ... D0 WE0 A0 ... D8 WE1 D7 ... D16 WE2 D15 ... ... D24 WE3 D23 CS OE I/O7 ... ... ... A16 ... A18 I/O0 WE ... A16 A0 ... CS OE I/O7 I/O0 WE ... A16 A0 ... CS OE I/O7 I/O0 WE Figure 10.5 Example of 32-Bit Data-Width SRAM Connection R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 333 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 128K × 8-bit SRAM This LSI A1 CSn RD D15 A0 CS OE I/O7 •••• •••• I/O0 WE •••• D8 WE1 D7 •••• A16 •••• A17 A16 •••• D0 WE0 •••• A0 CS OE I/O7 I/O0 WE Figure 10.6 Example of 16-Bit Data-Width SRAM Connection 128K × 8-bit SRAM This LSI A0 CS RD OE D7 I/O7 ... A0 CSn ... ... A16 ... A16 D0 I/O0 WE0 WE Figure 10.7 Example of 8-Bit Data-Width SRAM Connection Page 334 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.5.3 Section 10 Bus State Controller Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 1, 4, and 5 to insert wait cycles independently in read access and in write access. Areas 0, 2, and 3 have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 10.8. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.8 Wait Timing for Normal Space Access (Software Wait Only) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 335 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.9. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. T1 Tw Tw Wait states inserted by WAIT signal Twx T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.9 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT Signal) Page 336 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.5.4 Section 10 Bus State Controller CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 10.10 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.10 CSn Assert Period Expansion R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 337 of 3092 Section 10 Bus State Controller 10.5.5 SH7268 Group, SH7269 Group MPX-I/O Interface Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed. Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous access cycles. Address output is increased to 3 cycles by setting the MPXW bit in CS5WCR to 1. The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and low in the write cycle. The data cycle is the same as that in a normal space access. The delay cycles specified by SW[1:0] are inserted between the Ta3 and T1 cycles. The delay cycles specified by HW[1:0] are added after the T2 cycle. Timing charts are shown in figures 10.11 to 10.13. Page 338 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Ta1 Ta2 Ta3 T1 T2 CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 Address Data WEn Write D15/D7 to D0 Address Data BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.11 (1) Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 339 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Ta1 Ta2 Ta3 Th T1 T2 Tf CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 Address Data WEn Write D15/D7 to D0 Address Data BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.11 (2) Access Timing for MPX Space (Address Cycle No Wait, Assert Extension Cycle 1.5, Data Cycle No Wait, Negate Extension Cycle 1.5) Page 340 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Ta1 Tadw Ta2 Ta3 T1 T2 CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 Address Data WEn Write D15/D7 to D0 Address Data BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 341 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Ta1 Tadw Ta2 Ta3 T1 Tw Twx T2 CKIO A25 to A0 CS5 RD/WR AH RD Read D15/D7 to D0 Address Data WEn Write D15/D7 to D0 Address Data WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.13 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) Page 342 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.5.6 (1) Section 10 Bus State Controller SDRAM Interface SDRAM Direct Connection The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid only when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM is 16 bits or 32 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals. These commands supports:            NOP Auto-refresh (REF) Self-refresh (SELF) All banks pre-charge (PALL) Specified bank pre-charge (PRE) Bank active (ACTV) Read (READ) Read with pre-charge (READA) Write (WRIT) Write with pre-charge (WRITA) Write mode register (MRS, EMRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, see section 10.5.1, Endian/Access Size and Data Alignment. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 343 of 3092 Section 10 Bus State Controller SH7268 Group, SH7269 Group Figures 10.14 and 10.15 show examples of the connection of the SDRAM with the LSI. 64M SDRAM (1M × 16-bit × 4-bank) A2 CKE CKIO CSn ... RAS CAS RD/WR D31 ... D16 DQMUU DQMUL D15 D0 DQMLU DQMLL ... A13 A0 CKE CLK CS RAS CAS WE I/O15 ... ... A15 I/O0 DQMU DQML A13 ... This LSI A0 CKE CLK CS ... RAS CAS WE I/O15 I/O0 DQMU DQML Figure 10.14 Example of 32-Bit Data Width SDRAM Connection Page 344 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller 64M SDRAM (1M × 16-bit × 4-bank) A1 CKE CKIO CSn ... RAS CAS RD/WR D15 D0 DQMLU DQMLL A13 ... ... A14 A0 CKE CLK CS RAS CAS WE I/O15 ... This LSI I/O0 DQMU DQML Figure 10.15 Example of 16-Bit Data Width SDRAM Connection R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 345 of 3092 Section 10 Bus State Controller (2) SH7268 Group, SH7269 Group Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR and bits A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 10.11 to 10.16 show the relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0 = B'11), A0 of SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on. Page 346 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A25 A17 A16 A24 A16 A15 A23 SDRAM Pin Function Unused A15 A22* 2 A22*2 A12 (BA1) A13 A21* 2 A21* 2 A11 (BA0) A12 A20 L/H*1 A10/AP Specifies address/precharge A11 A19 A11 A9 Address A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 A9 A1 A0 A8 A0 A14 Specifies bank Unused Example of connected memory 64-Mbit product (512 Kwords  32 bits  4 banks, column 8 bits product): 1 16-Mbit product (512 Kwords  16 bits  2 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 347 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A25 A17 A16 A24 SDRAM Pin Function Unused A16 A23* 2 A23*2 A13 (BA1) A14 A22* 2 2 A12 (BA0) A13 A21 A13 A11 Address A12 A20 L/H*1 A10/AP Specifies address/precharge A11 A19 A11 A9 Address A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 A1 A9 A1 A0 A8 A0 A15 A22* Specifies bank Unused Example of connected memory 128-Mbit product (1 Mwords  32 bits  4 banks, column 8 bits product): 1 64-Mbit product (1 Mwords  16 bits  4 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 348 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A26 A17 A16 A25 SDRAM Pin Function Unused A16 A24* 2 A24*2 A13 (BA1) A14 A23* 2 2 A12 (BA0) A13 A22 A13 A11 Address A12 A21 L/H*1 A10/AP Specifies address/precharge A11 A20 A11 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 A10 A1 A0 A9 A0 A15 A23* Specifies bank Unused Example of connected memory 256-Mbit product (2 Mwords  32 bits  4 banks, column 9 bits product): 1 128-Mbit product (2 Mwords  16 bits  4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 349 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.12 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A27 A17 A16 A26 SDRAM Pin Function Unused A16 A25* 2 A25*2 A13 (BA1) A14 A24* 2 2 A12 (BA0) A13 A23 A13 A11 Address A12 A22 L/H*1 A10/AP Specifies address/precharge A11 A21 A11 A9 Address A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 A1 A11 A1 A0 A10 A0 A15 A24* Specifies bank Unused Example of connected memory 512-Mbit product (4 Mwords  32 bits  4 banks, column 10 bits product): 1 256-Mbit product (4 Mwords  16 bits  4 banks, column 10 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 350 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.13 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3) Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A26 A17 A25* 2 A15 A24* 2 A14 A23 A16 SDRAM Pin Function Unused 2 A14 (BA1) A24* 2 A13 (BA0) A14 A12 A25* Specifies bank Address A13 A22 A13 A11 A12 A21 L/H*1 A10/AP Specifies address/precharge A11 A20 A11 A9 Address A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 A1 A10 A1 A0 A9 A0 Unused Example of connected memory 512-Mbit product (4 Mwords  32 bits  4 banks, column 9 bits product): 1 256-Mbit product (4 Mwords  16 bits  4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 351 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.14 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A25 A17 A16 A24 A16 A15 A23 A15 A14 A22 A14 SDRAM Pin Function Unused A13 A21 A21 A12 A20*2 A20*2 1 A11 (BA0) Specifies bank A11 A19 L/H* A10/AP Specifies address/precharge A10 A18 A10 A9 Address A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 A0 A8 A0 Unused Example of connected memory 16-Mbit product (512 Kwords  16 bits  2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 352 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.14 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (4)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A25 A17 A16 A24 A16 A15 A23 SDRAM Pin Function Unused A15 A22* 2 A22*2 A13 (BA1) A13 A21* 2 A21* 2 A12 (BA0) A12 A20 A12 A11 Address A14 1 Specifies bank A11 A19 L/H* A10/AP Specifies address/precharge A10 A18 A10 A9 Address A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 A0 A8 A0 Unused Example of connected memory 64-Mbit product (1 Mwords  16 bits  4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 353 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.15 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A26 A17 A16 A25 A16 A15 A24 SDRAM Pin Function Unused A15 A23* 2 A23*2 A13 (BA1) A13 A22* 2 A22* 2 A12 (BA0) A12 A21 A12 A11 Address A14 1 Specifies bank A11 A20 L/H* A10/AP Specifies address/precharge A10 A19 A10 A9 Address A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 A0 A9 A0 Unused Example of connected memory 128-Mbit product (2 Mwords  16 bits  4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 354 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.15 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A27 A17 A16 A26 A16 A15 A25 SDRAM Pin Function Unused A15 A24* 2 A24*2 A13 (BA1) A13 A23* 2 A23* 2 A12 (BA0) A12 A22 A12 A11 Address A14 1 Specifies bank A11 A21 L/H* A10/AP Specifies address/precharge A10 A20 A10 A9 Address A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 A0 A10 A0 Unused Example of connected memory 256-Mbit product (4 Mwords  16 bits  4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 355 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.16 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A26 A17 A16 A25 SDRAM Pin Function Unused A16 A24* 2 A24*2 A14 (BA1) A14 A23* 2 A23* 2 A13 (BA0) A13 A22 A13 A12 A12 A21 A12 A11 A11 A20 L/H* A10/AP Specifies address/precharge A10 A19 A10 A9 Address A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 A0 A9 A0 A15 1 Specifies bank Address Unused Example of connected memory 256-Mbit product (4 Mwords  16 bits  4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 356 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.16 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (6)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A27 A17 A16 A26 SDRAM Pin Function Unused A16 A25* 2 A25*2 A14 (BA1) A14 A24* 2 A24* 2 A13 (BA0) A13 A23 A13 A12 A12 A22 A12 A11 A11 A21 L/H* A10/AP Specifies address/precharge A10 A20 A10 A9 Address A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 A0 A10 A0 A15 1 Specifies bank Address Unused Example of connected memory 512-Mbit product (8 Mwords  16 bits  4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 357 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller (3) Burst Read A burst read occurs in the following cases with this LSI.     Access size in reading is larger than data bus width. 16-byte transfer in cache miss. 16-byte transfer in the direct memory access controller 32-byte transfer in the OpenVG-compliant Renesas graphics processor, image renderer, and video display controller 4  128-byte transfer in the video display controller 4 This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that is connected to a 16-bit data bus. This access is called the burst read with the burst number 8. Table 10.17 shows the relationship between the access size and the number of bursts. Table 10.17 Relationship between Access Size and Number of Bursts Bus Width 16 bits 32 bits Page 358 of 3092 Access Size Number of Bursts 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 32 bytes 16 128 bytes 64 8 bits 1 16 bits 1 32 bits 1 16 bytes 4 32 bytes 8 128 bytes 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Figures 10.16 and 10.17 show timing charts in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM in variable frequencies. Figure 10.17 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 359 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.16 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) Page 360 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tr Section 10 Bus State Controller Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.17 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD[1:0] = 1 Cycle, Auto Pre-Charge) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 361 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller (4) Single Read A read access ends in one cycle when data exists in a cache-disabled space and the data bus width is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst length 1, only the required data is output. A read access that ends in one cycle is called single read. Figure 10.18 shows the single read basic timing. Tr Tc1 Td1 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.18 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge) Page 362 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 10 Bus State Controller Burst Write A burst write occurs in the following cases in this LSI.      Access size in writing is larger than data bus width. Write-back of the cache 16-byte transfer in the direct memory access controller 32-byte transfer in the video display controller 4 128-byte transfer in the video display controller 4 This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 8 times to write 16-byte continuous data to the SDRAM that is connected to a 16-bit data bus. This access is called burst write with the burst number 8. The relationship between the access size and the number of bursts is shown in table 10.17. Figure 10.19 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the auto-precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 363 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tr Tc1 Tc2 Tc3 Tc4 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.19 Basic Timing for Burst Write (Auto Pre-Charge) Page 364 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 10 Bus State Controller Single Write A write access ends in one cycle when data is written in a cache-disabled space and the data bus width is larger than or equal to access size. As a single write or burst write with burst length 1 is set in SDRAM, only the required data is output. The write access that ends in one cycle is called single write. Figure 10.20 shows the single write basic timing. Tr Tc1 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.20 Single Write Basic Timing (Auto-Precharge) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 365 of 3092 Section 10 Bus State Controller (7) SH7268 Group, SH7269 Group Bank Active The SDRAM bank function can be used to support high-speed access to the same row address. When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for area 3. When area 3 is set to bank-active mode, area 2 should be set to normal space or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM, auto precharge mode must be set. When the bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As SDRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 10.21, a burst read cycle for the same row address in figure 10.22, and a burst read cycle for different row addresses in figure 10.23. Similarly, a single write cycle without auto-precharge is shown in figure 10.24, a single write cycle for the same row address in figure 10.25, and a single write cycle for different row addresses in figure 10.26. In figure 10.22, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle. Page 366 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller When bank active mode is set, if only access cycles to the respective banks in the area 3 space are considered, as long as access cycles to the same row address continue, the operation starts with the cycle in figure 10.21 or 10.24, followed by repetition of the cycle in figure 10.22 or 10.25. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, the bus cycle in figure 10.23 or 10.26 is executed instead of that in figure 10.22 or 10.25. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.21 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 367 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tnop Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.22 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) Page 368 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tp Section 10 Bus State Controller Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.23 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 369 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tr Tc1 CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.24 Single Write Timing (Bank Active, Different Bank) Page 370 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tnop Tc1 CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.25 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 371 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tp Tpw Tr Tc1 CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.26 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) (8) Refreshing This module has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. Page 372 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (a) Section 10 Bus State Controller Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, and then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an autorefresh is performed for the number of times specified by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.27 shows the auto-refresh cycle timing. After starting the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 373 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tp Tpw Trr Trc Trc Trc CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 Hi-z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.27 Auto-Refresh Timing Page 374 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 10 Bus State Controller Self-refreshing Self-refresh mode is a kind of standby mode, in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR. Self-refresh timing is shown in figure 10.28. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, autorefreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when selfrefresh mode is cleared. If the transition from clearing of self-refresh mode to the start of autorefreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby state by setting the HIZCNT bit in CMNCR to 1. When the multiplication rate for the PLL circuit is changed, the CKIO output will become unstable or will be fixed low. For details on the CKIO output, see section 5, Clock Pulse Generator. The contents of SDRAM can be retained by placing the SDRAM in the self-refresh state before changing the multiplication rate. The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 375 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tp Tpw Trr Trc Trc Trc CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 Hi-z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.28 Self-Refresh Timing Page 376 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (9) Section 10 Bus State Controller Relationship between Refresh Requests and Bus Cycles If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. If the external bus does not return the bus for a period longer than the specified refresh interval, refresh cannot be executed and the SDRAM contents may be lost. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the refresh is completed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 377 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller (10) Power-Down Mode If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel the power-down mode. Figure 10.29 shows the access timing in power-down mode. Power-down Tnop Tr Tc1 Td1 Tde Tap Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.29 Power-Down Mode Access Timing Page 378 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller (11) Power-On Sequence In order to use SDRAM, mode setting must first be made for SDRAM after the pose interval specified for the SDRAM to be used after powering on. The pose interval should be obtained by a power-on reset generating circuit or software. To perform SDRAM initialization correctly, the registers of this module must first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a word write to address H'FFFC4000 + X for area 2 SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write or burst read/burst write (CAS latency 2 to 3, wrap type = sequential, and burst length 1) supported by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 10.18. In this time 0 is output at the external address pins of A12 or later. Table 10.18 Access Address in SDRAM Mode Register Write  Setting for Area 2 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC4440 H'0000440 3 H'FFFC4460 H'0000460 2 H'FFFC4880 H'0000880 3 H'FFFC48C0 H'00008C0 32 bits Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC4040 H'0000040 3 H'FFFC4060 H'0000060 2 H'FFFC4080 H'0000080 3 H'FFFC40C0 H'00000C0 32 bits R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 379 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller  Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC5440 H'0000440 3 H'FFFC5460 H'0000460 32 bits 2 H'FFFC5880 H'0000880 3 H'FFFC58C0 H'00008C0 Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC5040 H'0000040 3 H'FFFC5060 H'0000060 2 H'FFFC5080 H'0000080 3 H'FFFC50C0 H'00000C0 32 bits Mode register setting timing is shown in figure 10.30. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. One or more idle cycles are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer than the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Page 380 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tp PALL Tpw Section 10 Bus State Controller Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx Hi-Z D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.30 SDRAM Mode Write Timing (Based on JEDEC) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 381 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller (12) Low-Power SDRAM The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which the data in a work area other than the specific area can be lost without severe repercussions. For details, please refer to the Data Sheet for the low-power SDRAM to be used. The low-power SDRAM supports the extension mode register in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the extension mode register write command (EMRS). The EMRS command is issued according to the conditions specified in table below. For example, if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> REF  8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS. Table 10.19 Output Addresses when EMRS Command Is Issued Access Data Write Access Size MRS EMRS Command Command Issue Address Issue Address H'FFFC4XX0 H'******** 16 bits H'0000XX0  CS3 MRS H'FFFC5XX0 H'******** 16 bits H'0000XX0  CS2 MRS + EMRS H'FFFC4XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC5XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC4XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC5XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY Command to be Issued Access Address CS2 MRS (with refresh) CS3 MRS + EMRS (with refresh) CS2 MRS + EMRS (without refresh) CS3 MRS + EMRS (without refresh) Page 382 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tp PALL Tpw Section 10 Bus State Controller Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop Temw EMRS Tnop CKIO A25 to A0 BA1*1 BA0*2 A12/A11*3 CSn RAS CAS RD/WR DQMxx D31 to D0 Hi-Z BS DACKn*4 Notes: 1. Address pin to be connected to pin BA1 of SDRAM. 2. Address pin to be connected to pin BA0 of SDRAM. 3. Address pin to be connected to pin A10 of SDRAM. 4. The waveform for DACKn is when active low is specified. Figure 10.31 EMRS Command Issue Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 383 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller  Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed. Tp Tpw Tdpd Trc Trc Trc Trc Trc CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 Hi-Z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.32 Deep Power-Down Mode Transition Timing Page 384 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.5.7 Section 10 Bus State Controller Burst ROM (Clocked Asynchronous) Interface The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clocked asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent access cycles are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles, addresses are changed at the falling edge of the CKIO. For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the BW1 and BW0 bits in CSnWCR is inserted. In the access to the burst ROM (clocked asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that does not perform the burst operation in the burst ROM (clocked asynchronous) interface, access timing is same as a normal space. Table 10.20 lists a relationship between bus width, access size, and the number of bursts. Figure 10.33 shows a timing chart. Table 10.20 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count 8 bits 8 bits Not affected 1 1 16 bits Not affected 2 1 32 bits Not affected 4 1 16 bytes 00 16 1 01 4 4 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 385 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count 16 bits 8 bits Not affected 1 1 16 bits Not affected 1 1 32 bits Not affected 2 1 16 bytes 00 8 1 01 2 4 10* 4 2 2, 4, 2 3 8 bits Not affected 1 1 16 bits Not affected 1 1 32 bits Not affected 1 1 16 bytes Not affected 4 1 32 bits Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in CSnWCR are 10, the number of bursts and access count depend on the access start address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4 or H'xxxC, 2-4-2 burst access is performed. Page 386 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller T1 Tw Tw T2B Twb T2B Twb T2B Twb T2 CKIO A25 to A0 CSn RD/WR RD D31 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.33 Burst ROM Access Timing (Clocked Asynchronous) (Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 387 of 3092 Section 10 Bus State Controller 10.5.8 SH7268 Group, SH7269 Group SRAM Interface with Byte Selection The SRAM interface with byte selection is a memory interface that outputs the byte selection signal (WEn) in both read and write bus cycles. This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte selection is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 10.34. In write access, data is written to the memory according to the timing of the byteselection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 10.35 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 10.36 shows the access timing when a software wait is specified. Page 388 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller T2 T1 CKIO A25 to A0 CSn WEn RD/WR RD Read D31 to D0 RD/WR RD Write High D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.34 Basic Access Timing for SRAM with Byte Selection (BAS = 0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 389 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller T1 T2 CKIO A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.35 Basic Access Timing for SRAM with Byte Selection (BAS = 1) Page 390 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Th T1 Tw T2 Tf CKIO A25 to A0 CSn WEn RD/WR Read RD D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.36 Wait Timing for SRAM with Byte Selection (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 391 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 64K × 16-bit SRAM This LSI A15 ... ... A17 A2 A0 CSn CS RD OE RD/WR WE I/O15 ... ... D31 D16 I/O0 WE3 UB WE2 LB ... D15 ... A15 D0 WE1 A0 WE0 CS OE WE ... I/O15 I/O0 UB LB Figure 10.37 Example of Connection with 32-Bit Data-Width SRAM with Byte Selection 64K × 16-bit SRAM This LSI A16 . .. A1 A15 .. . A0 CSn CS RD OE RD/WR D15 .. . D0 WE1 WE0 WE I/O .. 15 . I/O 0 UB LB Figure 10.38 Example of Connection with 16-Bit Data-Width SRAM with Byte Selection Page 392 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 10.5.9 Section 10 Bus State Controller PCMCIA Interface With this LSI, area 5 can be used for the IC memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1 Rev. 2.1) by specifying bits TYPE[2:0] in CS5BCR to B'101. In addition, the bits SA[1:0] in CS5WCR assign the upper or lower 32 Mbytes of area 5 to IC memory card or I/O card interface. For example, if the bits SA1 and SA0 in CS5WCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes of area 5 are used for IC memory card interface and the lower 32 Mbytes are used for I/O card interface. When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the bits BSZ[1:0] in CS5BCR. Figure 10.39 shows an example of connection between this LSI and a PCMCIA card. To enable hot swapping (insertion and removal of the PCMCIA card with the system power turned on), tristate buffers must be connected between the bus interface of this LSI and the PCMCIA card. In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined. Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI. PC card (memory or I/O) This LSI A25 to A0 G A25 to A0 D7 to D0 D15 to D8 D7 to D0 RD/WR CS5/CE1A CE2A G DIR D15 to D8 G DIR CE1 CE2 RD OE WE1/WE WE/PGM ICIORD IORD ICIOWR IOWR REG (Output port) REG G WAIT WAIT IOIS16 IOIS16 Card detector CD1, CD2 Figure 10.39 Example of PCMCIA Interface Connection R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 393 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller (1) Basic Timing for Memory Card Interface Figure 10.40 shows the basic timing of the PCMCIA IC memory card interface. When area 5 is specified as the PCMCIA interface, the bus is accessed with the IC memory card interface according to the SA[1:0] bit settings in CS5WCR. If the external bus frequency (CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable signals (CE1A, CE2A), and write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this LSI enables the setup times and hold times for area 5 to be specified independently, using CS5WCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware wait using the WAIT pin can be inserted. Figure 10.41 shows the PCMCIA memory bus wait timing. Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS Figure 10.40 Basic Access Timing for PCMCIA Memory Card Interface Page 394 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tpcm0 Section 10 Bus State Controller Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS WAIT Figure 10.41 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1) A port is used to generate the REG signal that switches between the common memory and attribute memory. As shown in the example in figure 10.42, when the total memory space necessary for the common memory and attribute memory is 32 Mbytes or less, pin A24 can be used as the REG signal to allocate a 16-Mbyte common memory space and a 16-Mbyte attribute memory space. For 32-Mbyte capacity (I/O port is used for REG) Area 5: H'14000000 Attribute memory/common memory Area 5: H'16000000 I/O space For 16-Mbyte capacity (A24 is used for REG) Area 5: H'14000000 Area 5: H'15000000 Area 5: H'16000000 Attribute memory Common memory I/O space H'17000000 Figure 10.42 Example of PCMCIA Space Allocation (CS5WCR.SA[1:0] = B'10) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 395 of 3092 Section 10 Bus State Controller (2) SH7268 Group, SH7269 Group Basic Timing for I/O Card Interface Figures 10.43 and 10.44 show the basic timing for the PCMCIA I/O card interface. When accessing an I/O card through the PCMCIA interface, be sure to access the space as cachedisabled. Switching between I/O card and IC memory card interfaces in the respective address spaces is accomplished by the SA[1:0] bit settings in CS5WCR. The IOIS16 pin can be used for dynamic adjustment of the width of the I/O bus in access to an I/O card via the PCMCIA interface when little endian mode has been selected. When the bus width of area 5 is set to 16 bits and the IOIS16 signal is driven high during a cycle of word-unit access to the I/O card bus, the bus width will be recognized as 8 bits and only 8 bits of data will be accessed during the current cycle of the I/O card bus. Operation will automatically continue with access to the remaining 8 bits of data. The IOIS16 signal is sampled on falling edges of the CKIO in Tpci0 as well as all Tpci0w cycles for which the TED3 to TED0 bits are set to 1.5 cycles or more, and the CE2A signal is updated after 1.5 cycles of the CKIO signal from the sampling point of Tpci0. Ensure that the IOIS16 signal is defined at all sampling points and does not change along the way. Set the TED3 to TED0 bits to satisfy the requirement of the PC card in use with regard to setup timing from ICIORD or ICIOWR to CE1. The basic waveforms for dynamic bus-size adjustment are shown in figure 10.44. Since the IOIS16 signal is not supported in big endian mode, the IOIS16 signal should be fixed to the low level when big endian mode has been selected. Page 396 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS Figure 10.43 Basic Access Timing for PCMCIA I/O Card Interface Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CE1A CE2A RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS WAIT IOIS16 Figure 10.44 Dynamic Bus-Size Adjustment Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 397 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.5.10 Burst ROM (Clocked Synchronous) Interface The burst ROM (clocked synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0. In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR. While the burst ROM (clocked synchronous) is accessed, the BS signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. When the bus width is 16 bits, the burst length must be specified as 8. When the bus width is 32 bits, the burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width for the burst ROM. The burst ROM interface performs burst operations for all read access. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, it is recommended using a 16-byte read by cache fill in the cache-enabled spaces or 16-byte read by the DMA. The burst ROM interface performs write access in the same way as normal space access. T1 Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2 CKIO A25 to A0 CS0 RD/WR RD D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.45 Burst ROM Access Timing (Clocked Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) Page 398 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.5.11 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting idle (wait) cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by the WM bit in CSnWCR, bits IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and IWRRS2 to IWRRS 0 in CSnBCR, and bits DMAIW2 to DMAIW0 and DMAIWA in CMNCR. The conditions for setting the idle cycles between access cycles are shown below. 1. 2. 3. 4. 5. 6. Continuous access cycles are write-read or write-write Continuous access cycles are read-write for different spaces Continuous access cycles are read-write for the same space Continuous access cycles are read-read for different spaces Continuous access cycles are read-read for the same space Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single address transfer is followed by any type of access (DMAIWA = 1) For the specification of the number of idle cycles between access cycles described above, refer to the description of each register. Besides the idle cycles between access cycles specified by the registers, idle cycles must be inserted to interface with the internal bus or to obtain the minimum pulse width for a multiplexed pin (WEn). The following gives detailed information about the idle cycles and describes how to estimate the number of idle cycles. The number of idle cycles on the external bus from CSn negation to CSn or CSm assertion is described below. Here, CSn and CSm also include CE2A for PCMCIA. There are eight conditions that determine the number of idle cycles on the external bus as shown in table 10.21. The effects of these conditions are shown in figure 10.46. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 399 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.21 Conditions for Determining Number of Idle Cycles No. Condition Description [1] DMAIW[2:0] in CMNCR These bits specify the number of 0 to 12 idle cycles for DMA single address transfer. This condition is effective only for single address transfer and generates idle cycles after the access is completed. When 0 is specified for the number of idle cycles, the DACK signal may be asserted continuously. This causes a discrepancy between the number of cycles detected by the device with DACK and the direct memory access controller transfer count, resulting in a malfunction. [2] IW***[2:0] in CSnBCR These bits specify the number of 0 to 12 idle cycles for access other than single address transfer. The number of idle cycles can be specified independently for each combination of the previous and next cycles. For example, in the case where reading CS1 space followed by reading other CS space, the bits IWRRD[2:0] in CS1BCR should be set to B'100 to specify six or more idle cycles. This condition is effective only for access cycles other than single address transfer and generates idle cycles after the access is completed. Do not set 0 for the number of idle cycles between memory types which are not allowed to be accessed successively. [3] SDRAM-related These bits specify precharge 0 to 3 bits in completion and startup wait cycles CSnWCR and idle cycles between commands for SDRAM access. This condition is effective only for SDRAM access and generates idle cycles after the access is completed Page 400 of 3092 Range Note Specify these bits in accordance with the specification of the target SDRAM. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller No. Condition Description [4] WM in CSnWCR This bit enables or disables external 0 or 1 WAIT pin input for the memory types other than SDRAM. When this bit is cleared to 0 (external WAIT enabled), one idle cycle is inserted to check the external WAIT pin input after the access is completed. When this bit is set to 1 (disabled), no idle cycle is generated. [5] Read data transfer cycle One idle cycle is inserted after a 0 or 1 read access is completed. This idle cycle is not generated for the first or middle cycles in divided access cycles. This is neither generated when the HW[1:0] bits in CSnWCR are not B'00. One idle cycle is always generated after a read cycle with SDRAM or PCMCIA interface. [6] Internal bus External bus access requests from 0 or idle cycles, etc. the CPU or the direct memory larger access controller and their results are passed through the internal bus. The external bus enters idle state during internal bus idle cycles or while a bus other than the external bus is being accessed. This condition is not effective for divided access cycles, which are generated by the bus state controller when the access size is larger than the external data bus width. The number of internal bus idle cycles may not become 0 depending on the I:B:CKIO clock ratio. Tables 10.22 and 10.23 show the relationship between the clock ratio and the minimum number of internal bus idle cycles. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Range Note Page 401 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller No. Condition Description Range Note [7] Write data wait During write access, a write cycle is 0 or 1 cycles executed on the external bus only after the write data becomes ready. This write data wait period generates idle cycles before the write cycle. Note that when the previous cycle is a write cycle and the internal bus idle cycles are shorter than the previous write cycle, write data can be prepared in parallel with the previous write cycle and therefore, no idle cycle is generated (write buffer effect). For write  write or write  read access cycles, successive access cycles without idle cycles are frequently available due to the write buffer effect described in the left column. If successive access cycles without idle cycles are not allowed, specify the minimum number of idle cycles between access cycles through CSnBCR. [8] Idle cycles between different memory types The number of idle cycles depends on the target memory types. See table 10.24. To ensure the minimum pulse width 0 to 2 on the signal-multiplexed pins, idle cycles may be inserted before access after memory types are switched. For some memory types, idle cycles are inserted even when memory types are not switched. In the above conditions, a total of four conditions, that is, condition [1] or [2] (either one is effective), condition [3] or [4] (either one is effective), a set of conditions [5] to [7] (these are generated successively, and therefore the sum of them should be taken as one set of idle cycles), and condition [8] are generated at the same time. The maximum number of idle cycles among these four conditions become the number of idle cycles on the external bus. To ensure the minimum idle cycles, be sure to make register settings for condition [1] or [2]. Page 402 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller CKIO External bus idle cycles Previous access Next access CSn Idle cycle before access Idle cycle after access [1] DMAIW[2:0] setting in CMNCR [2] IWW[2:0] setting in CSnBCR IWRWD[2:0] setting in CSnBCR IWRWS[2:0] setting in CSnBCR IWRRD[2:0] setting in CSnBCR IWRRS[2:0] setting in CSnBCR [3] WTRP[1:0] setting in CSnWCR TRWL[1:0] setting in CSnWCR WTRC[1:0] setting in CSnWCR Either one of them is effective Condition [1] or [2] Either one of them is effective Condition [3] or [4] [4] WM setting in CSnWCR [5] Read data transfer [6] Internal bus idle cycles, etc. [7] Write data wait Set of conditions [5] to [7] [8] Idle cycles between Condition [8] different memory types Note: A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7], and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of cycles among these four conditions become the number of idle cycles. Figure 10.46 Idle Cycle Conditions Table 10.22 Minimum Number of Idle Cycles on Internal Bus (CPU Operation) Clock Ratio (I:B:CKIO) CPU Operation 4:2:1 4:1:1 2:2:1 2:1:1 1:1:1 Write  write 1 2 2 2 3 Write  read 0 0 0 0 0 Read  write 1 2 2 2 3 Read  read 0 0 1 0 1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 403 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.23 Minimum Number of Idle Cycles on Internal Bus (Direct Memory Access Controller Operation) Clock Ratio (B:CKIO) Transfer Mode Read/Write Operation 2:1 1:1 Dual address Write  write* 0 0 Write  read 0 0 Read  write 0 0 Read  read*1 0 0 Single address (level detection for DREQ)*2 Write  write 3 6 Read  read 2 5 Single address 2 (edge detection for DREQ)* Write  write 0 1 Read  read 1 2 1 Notes: 1. The write  write and read  read operations in dual address mode indicate that transfer is divided up into more than one transfer cycle for execution. 2. In single address mode, "write" means transfer from a device with DACK to an external memory and "read" means transfer from an external memory to a device with DACK. Page 404 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller Table 10.24 Number of Idle Cycles Inserted between Access Cycles to Different Memory Types Next Cycle Byte Previous Cycle SRAM Burst ROM SRAM 0 Burst ROM MPX- Byte SRAM SRAM (Asynchronous) I/O (BAS = 0) 0 1 0 (BAS = 1) 1 0/1* 1 Burst ROM SDRAM PCMCIA (Synchronous) 1 0 0 1 0/1* 0 0 1 0 0/1* 0/1* 0 0 1 1 0 1 1 1 1 1 (asynchronous) MPX-I/O Byte SRAM 1 1 0 0 1 0 0/1* 0/1* 0 0 0/1*1 0/1*1 1/2*1 0/1*1 0 0 0/1*1 0/1*1 1 1 2 1 0 1 1 (BAS = 0) Byte SRAM (BAS = 1) SDRAM 0 2 2 PCMCIA 0 0 1 0 0/1* 0/1* 0 0 Burst ROM 0 0 1 0 1 1 0 0 (synchronous) Notes: 1. The number of idle cycles is determined by the setting of the CSnWCR.HW[1:0] bits on the previous cycle. The number of idle cycles will be the number shown at the left when HW[1:0]  B'00, will be the number shown at the right when HW[1:0] = B'00. Also, for CSn spaces for which the CSnWCR.HW[1:0] bits do not exist, the number of idle cycles shown at the right will be used. 2. The number of idle cycles is determined by the setting of the CSnWCR.TEH[3:0] bits on the previous cycle. The number of idle cycles will be the number shown at the left when TEH[3:0]  B'0000, will be the number shown at the right when TEH[3:0] = B'0000. Figure 10.47 shows sample estimation of idle cycles between access cycles. In the actual operation, the idle cycles may become shorter than the estimated value due to the write buffer effect or may become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU instruction execution or CPU register conflicts. Please consider these errors when estimating the idle cycles. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 405 of 3092 SH7268 Group, SH7269 Group Section 10 Bus State Controller Sample Estimation of Idle Cycles between Access Cycles This example estimates the idle cycles for data transfer from the CS1 space to CS2 space by CPU access. Transfer is repeated in the following order: CS1 read → CS1 read → CS2 write → CS2 write → CS1 read → ... • Conditions The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0. In CS1WCR and CS2WCR, the WM bit is set to 1 (external WAIT pin disabled) and the HW[1:0] bits are set to 00 (CS negation is not extended). Iφ:Bφ:CKIOφ is set to 4:1:1, and no other processing is done during transfer. For both the CS1 and CS2 spaces, normal SRAM devices are connected, the bus width is 32 bits, and access size is also 32 bits. The idle cycles generated under each condition are estimated for each pair of access cycles. In the following table, R indicates a read cycle and W indicates a write cycle. R→R R→W W→W W→R [1] or [2] 0 0 0 0 CSnBCR is set to 0. [3] or [4] 0 0 0 0 The WM bit is set to 1. [5] 1 1 0 0 Generated after a read cycle. [6] 0 2 2 0 See the Iφ:Bφ:CKIOφ = 4:1:1 columns in table 10.22. [7] 0 1 0 0 No idle cycle is generated for the second time due to the write buffer effect. [5] + [6] + [7] 1 4 2 0 [8] 0 0 0 0 Value for SRAM → SRAM access Estimated idle cycles 1 4 2 0 Maximum value among conditions [1] or [2], [3] or [4], [5] + [6] + [7], and [8] Actual idle cycles 1 4 2 1 The estimated value does not match the actual value in the W → R cycles because the internal idle cycles due to condition [6] is estimated as 0 but actually an internal idle cycle is generated due to execution of a loop condition check instruction. Condition Note Figure 10.47 Comparison between Estimated Idle Cycles and Actual Value Page 406 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller 10.5.12 Bus Arbitration The bus arbitration of this LSI has the bus mastership in the normal state and releases the bus mastership after receiving a bus request from another device. Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The states that do not allow bus mastership release are shown below. 1. 2. 3. 4. 5. 6. 7. 8. 9. 16-byte transfer because of a cache miss During write-back operation for the cache Between the read and write cycles of a TAS instruction Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 16-byte transfer by the direct memory access controller 32-byte transfer by the OpenVG-compliant Renesas graphics processor, image renderer, and video display controller 4 128-byte transfer by the video display controller 4 Setting the BLOCK bit in CMNCR to 1 During access to the external flash memory by the NAND flash memory controller Moreover, by using DPRTY bit in CMNCR, whether the bus mastership request is received or not can be selected during burst transfer by the direct memory access controller. The LSI has the bus mastership until a bus request is received from another device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the external device has released the bus, it negates the BACK signal and resumes the bus usage. With the SDRAM interface, all bank pre-charge commands (PALLs) are issued when active banks exist and the bus is released after completion of a PALL command. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 407 of 3092 Section 10 Bus State Controller SH7268 Group, SH7269 Group The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals (BS, CSn, RAS, CAS, CKE, DQMxx, WEn, RD, and RD/WR) are placed in the high-impedance state at subsequent rising edges of CKIO. These bus control signals are driven high one or more cycles before they are placed in the high-impedance state. Bus request signals are sampled at the falling edge of CKIO. Note that CKE, RAS, and CAS can be continued to be driven at the previous value even in the bus-released state by setting the HIZCNT bit in CMNCR. The sequence for reclaiming the bus mastership from an external device is described below. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO where address and data signals are driven. Figure 10.48 shows the bus arbitration timing. When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership should be returned. If the bus mastership is not returned for a specified refreshing period or longer, the contents of SDRAM cannot be guaranteed because a refreshing cannot be executed. While releasing the bus mastership, the SLEEP instruction (to enter sleep mode, deep standby mode, or software standby mode), as well as a manual reset, cannot be executed until the LSI obtains the bus mastership. The BREQ input signal is ignored in software standby mode or deep standby mode and the BACK output signal is placed in the high impedance state. If the bus mastership request is required in this state, the bus mastership must be released by pulling down the BACK pin to enter software standby mode or deep standby mode. The bus mastership release (BREQ signal for high level negation) after the bus mastership request (BREQ signal for low level assertion) must be performed after the bus usage permission (BACK signal for low level assertion). If the BREQ signal is negated before the BACK signal is asserted, only one cycle of the BACK signal is asserted depending on the timing of the BREQ signal to be negated and this may cause a bus contention between the external device and the LSI. Page 408 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller CKIO BREQ BACK A25 to A0 D31 to D0 CSn Other bus control signals Figure 10.48 Bus Arbitration Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 409 of 3092 Section 10 Bus State Controller SH7268 Group, SH7269 Group 10.5.13 Others (1) Reset This module can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal clock. All control registers are initialized. In software standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. (2) Access from the Side of the LSI Internal Bus Master There are three types of LSI internal buses: a CPU bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the CPU bus. The bus state controller and internal bus masters other than the CPU are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory are connected bidirectionally to the CPU bus and internal bus. Access from the CPU bus to the internal bus is enabled but access from the internal bus to the CPU bus is disabled. This gives rise to the following problems. On-chip bus masters such as the direct memory access controller other than the CPU can access internal memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. In a cache-enabled space, if the CPU initiates read access, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword access cycles to perform a cache fill operation on the external interface. For a cache-disabled space, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of an on-chip peripheral module, the cycle is initiated through the internal bus and peripheral bus. The read data is sent to the CPU via the peripheral bus, internal bus, and CPU bus. Page 410 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 10 Bus State Controller In a write cycle for the cache-enabled space, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller incorporates a one-stage write buffer, it can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the bus state controller functions in the same way for an access by a bus master other than the CPU such as the direct memory access controller. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next read cycle will not be initiated until the previous write cycle is completed. Changing the registers in this module while the write buffer is operating may disrupt correct write access. Therefore, do not change the registers in this module immediately after a write access. If this change becomes necessary, do it after executing a dummy read of the write data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 411 of 3092 Section 10 Bus State Controller (3) SH7268 Group, SH7269 Group On-Chip Peripheral Module Access To access an on-chip module register, two or more peripheral module clock (P0 or P1) cycles are required. Care must be taken in system design. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to the software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR1 register to 1. However a dummy read of the STBCR1 register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR1 register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. (4) External Flash Memory Access by NAND Flash Memory Controller In this product, a part of the external data bus is used also as data bus for the NAND flash memory controller. The use of the data bus is controlled by the NAND flash memory controller. Memory access by the NAND flash memory controller is started after the preceding access to the external device by this module is completed. If an access to the external device by this module occurs during the access by the NAND flash memory controller, it must wait until the completion of the access by the NAND flash memory controller. When a memory access request by the NAND flash memory controller and an external bus release request conflict with each other, the request accepted first has higher priority. When the two requests occur at the same time, the access by the NAND flash memory controller has higher priority. Auto-refresh operation and self-refresh operation are executed even during a memory access by the NAND flash memory controller. Page 412 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Section 11 Direct Memory Access Controller Direct Memory Access Controller can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 11.1 Features  Number of channels: 16 channels (channels 0 to 15) selectable One channel (channel 0) can receive external requests.  4-Gbyte physical address space  Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes (longword  4)  Maximum transfer count: 16,777,216 transfers (24 bits)  Address mode: Dual address mode and single address mode are supported.  Transfer requests  External request  On-chip peripheral module request  Auto request The following modules can issue on-chip peripheral module requests.  Serial communication interface with FIFO: 16 sources  I2C bus interface 3: eight sources  A/D converter: one source  Multi-function timer pulse unit 2: five sources  Compare match timer: two sources  USB 2.0 host/function module: two sources  NAND flash memory controller: two sources  Controller area network: three sources  Serial sound interface: seven sources  Sampling rate converter: six sources  Sound generator: four sources  Renesas SPDIF interface: two sources  CD-ROM decoder: one source  SD host interface: four sources  MMC host interface: two sources  Renesas serial peripheral interface: four sources R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 413 of 3092 Section 11 Direct Memory Access Controller       SH7268 Group, SH7269 Group  Renesas quad serial peripheral interface: four sources  Clock synchronous serial I/O with FIFO: two sources  Motor control PWM timer: two sources Selectable bus modes  Cycle steal mode (normal mode or intermittent mode)  Burst mode Selectable channel priority levels: The channel priority levels are selectable between two fixed modes. Interrupt request: An interrupt request can be sent to the CPU on completion of half- or fulldata transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to the CPU when half of the initially specified DMA transfer is completed. External request detection: There are following four types of DREQ input detection.  Low level detection  High level detection  Rising edge detection  Falling edge detection Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. Support of reload functions in DMA transfer information registers: DMA transfer using the same information as the current transfer can be repeated automatically without specifying the information again. Modifying the reload registers during DMA transfer enables next DMA transfer to be done using different transfer information. The reload function can be enabled or disabled independently in each channel or reload register. Page 414 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Figure 11.1 shows the block diagram of this module. RDMATCR_n On-chip memory Iteration control On-chip peripheral module Register control DMATCR_n RSAR_n Internal bus Peripheral bus SAR_n Start-up control RDAR_n DAR_n DMA transfer request signal CHCR_n DMA transfer acknowledge signal HEIn DEIn Interrupt controller Request priority control DMAOR DMARS0 to DMARS7 External ROM Bus interface External RAM External device (memory mapped) External device (with acknowledge) Bus state controller DREQ0 DACK0, TEND0 [Legend] RDMATCR: DMA reload transfer count register DMATCR: DMA transfer count register RSAR: DMA reload source address register SAR: DMA source address register RDAR: DMA reload destination address register DAR: DMA destination address register DMA channel control register CHCR: DMA operation register DMAOR: DMARS0 to DMARS7: DMA extension resource selectors 0 to 7 DMA transfer half-end interrupt request to the CPU HEIn: DMA transfer end interrupt request to the CPU DEIn: n = 0 to 15 Figure 11.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 415 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller 11.2 Input/Output Pins Table 11.1 lists the pin configuration of this module. This module has pins for one channel (channel 0) for external bus use. Table 11.1 Pin Configuration Channel Name Abbreviation I/O Function 0 DMA transfer request DREQ0 I DMA transfer request input from an external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to an external device DMA transfer end TEND0 O DMA transfer end output for channel 0 Page 416 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.3 Section 11 Direct Memory Access Controller Register Descriptions This module has the registers listed in table 11.2. There are four control registers and three reload registers for each channel, and one common control register is used by all channels. In addition, there is one extension resource selector per two channels. Each channel number is expressed in the register names, as in SAR_0 for SAR in channel 0. Table 11.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 DMA source address register_0 SAR_0 R/W H'00000000 H'FFFE1000 16, 32 DMA destination address register_0 DAR_0 R/W H'00000000 H'FFFE1004 16, 32 DMA transfer count register_0 DMATCR_0 R/W H'00000000 H'FFFE1008 16, 32 DMA channel control register_0 CHCR_0 R/W*1 H'00000000 H'FFFE100C 8, 16, 32 DMA reload source address register_0 RSAR_0 R/W H'00000000 H'FFFE1100 16, 32 DMA reload destination RDAR_0 address register_0 R/W H'00000000 H'FFFE1104 16, 32 1 DMA reload transfer count register_0 RDMATCR_0 R/W H'00000000 H'FFFE1108 16, 32 DMA source address register_1 SAR_1 R/W H'00000000 H'FFFE1010 16, 32 DMA destination address register_1 DAR_1 R/W H'00000000 H'FFFE1014 16, 32 DMA transfer count register_1 DMATCR_1 R/W H'00000000 H'FFFE1018 16, 32 DMA channel control register_1 CHCR_1 R/W*1 H'00000000 H'FFFE101C 8, 16, 32 DMA reload source address register_1 RSAR_1 R/W H'00000000 H'FFFE1110 16, 32 DMA reload destination RDAR_1 address register_1 R/W H'00000000 H'FFFE1114 16, 32 H'00000000 16, 32 DMA reload transfer count register_1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 RDMATCR_1 R/W H'FFFE1118 Page 417 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 2 DMA source address register_2 SAR_2 R/W H'00000000 H'FFFE1020 16, 32 DMA destination address register_2 DAR_2 R/W H'00000000 H'FFFE1024 16, 32 DMA transfer count register_2 DMATCR_2 R/W H'00000000 H'FFFE1028 16, 32 DMA channel control register_2 CHCR_2 R/W*1 H'00000000 H'FFFE102C 8, 16, 32 DMA reload source address register_2 RSAR_2 R/W H'00000000 H'FFFE1120 16, 32 DMA reload destination RDAR_2 address register_2 R/W H'00000000 H'FFFE1124 16, 32 3 DMA reload transfer count register_2 RDMATCR_2 R/W H'00000000 H'FFFE1128 16, 32 DMA source address register_3 SAR_3 R/W H'00000000 H'FFFE1030 16, 32 DMA destination address register_3 DAR_3 R/W H'00000000 H'FFFE1034 16, 32 DMA transfer count register_3 DMATCR_3 R/W H'00000000 H'FFFE1038 16, 32 DMA channel control register_3 CHCR_3 R/W*1 H'00000000 H'FFFE103C 8, 16, 32 DMA reload source address register_3 RSAR_3 R/W H'00000000 H'FFFE1130 16, 32 DMA reload destination RDAR_3 address register_3 R/W H'00000000 H'FFFE1134 16, 32 H'00000000 16, 32 DMA reload transfer count register_3 Page 418 of 3092 RDMATCR_3 R/W H'FFFE1138 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 4 DMA source address register_4 SAR_4 R/W H'00000000 H'FFFE1040 16, 32 DMA destination address register_4 DAR_4 R/W H'00000000 H'FFFE1044 16, 32 DMA transfer count register_4 DMATCR_4 R/W H'00000000 H'FFFE1048 16, 32 DMA channel control register_4 CHCR_4 R/W*1 H'00000000 H'FFFE104C 8, 16, 32 DMA reload source address register_4 RSAR_4 R/W H'00000000 H'FFFE1140 16, 32 DMA reload destination RDAR_4 address register_4 R/W H'00000000 H'FFFE1144 16, 32 DMA reload transfer count register_4 RDMATCR_4 R/W H'00000000 H'FFFE1148 16, 32 DMA source address register_5 SAR_5 R/W H'00000000 H'FFFE1050 16, 32 DMA destination address register_5 DAR_5 R/W H'00000000 H'FFFE1054 16, 32 DMA transfer count register_5 DMATCR_5 R/W H'00000000 H'FFFE1058 16, 32 DMA channel control register_5 CHCR_5 R/W*1 H'00000000 H'FFFE105C 8, 16, 32 DMA reload source address register_5 RSAR_5 R/W H'00000000 H'FFFE1150 16, 32 DMA reload destination RDAR_5 address register_5 R/W H'00000000 H'FFFE1154 16, 32 RDMATCR_5 R/W H'00000000 H'FFFE1158 16, 32 5 DMA reload transfer count register_5 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 419 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 6 DMA source address register_6 SAR_6 R/W H'00000000 H'FFFE1060 16, 32 DMA destination address register_6 DAR_6 R/W H'00000000 H'FFFE1064 16, 32 DMA transfer count register_6 DMATCR_6 R/W H'00000000 H'FFFE1068 16, 32 DMA channel control register_6 CHCR_6 R/W*1 H'00000000 H'FFFE106C 8, 16, 32 DMA reload source address register_6 RSAR_6 R/W H'00000000 H'FFFE1160 16, 32 DMA reload destination RDAR_6 address register_6 R/W H'00000000 H'FFFE1164 16, 32 DMA reload transfer count register_6 RDMATCR_6 R/W H'00000000 H'FFFE1168 16, 32 DMA source address register_7 SAR_7 R/W H'00000000 H'FFFE1070 16, 32 DMA destination address register_7 DAR_7 R/W H'00000000 H'FFFE1074 16, 32 DMA transfer count register_7 DMATCR_7 R/W H'00000000 H'FFFE1078 16, 32 DMA channel control register_7 CHCR_7 R/W*1 H'00000000 H'FFFE107C 8, 16, 32 DMA reload source address register_7 RSAR_7 R/W H'00000000 H'FFFE1170 16, 32 DMA reload destination RDAR_7 address register_7 R/W H'00000000 H'FFFE1174 16, 32 RDMATCR_7 R/W H'00000000 H'FFFE1178 16, 32 7 DMA reload transfer count register_7 Page 420 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 8 DMA source address register_8 SAR_8 R/W H'00000000 H'FFFE1080 16, 32 DMA destination address register_8 DAR_8 R/W H'00000000 H'FFFE1084 16, 32 DMA transfer count register_8 DMATCR_8 R/W H'00000000 H'FFFE1088 16, 32 DMA channel control register_8 CHCR_8 R/W*1 H'00000000 H'FFFE108C 8, 16, 32 DMA reload source address register_8 RSAR_8 R/W H'00000000 H'FFFE1180 16, 32 DMA reload destination RDAR_8 address register_8 R/W H'00000000 H'FFFE1184 16, 32 DMA reload transfer count register_8 RDMATCR_8 R/W H'00000000 H'FFFE1188 16, 32 DMA source address register_9 SAR_9 R/W H'00000000 H'FFFE1090 16, 32 DMA destination address register_9 DAR_9 R/W H'00000000 H'FFFE1094 16, 32 DMA transfer count register_9 DMATCR_9 R/W H'00000000 H'FFFE1098 16, 32 DMA channel control register_9 CHCR_9 R/W*1 H'00000000 H'FFFE109C 8, 16, 32 DMA reload source address register_9 RSAR_9 R/W H'00000000 H'FFFE1190 16, 32 DMA reload destination RDAR_9 address register_9 R/W H'00000000 H'FFFE1194 16, 32 RDMATCR_9 R/W H'00000000 H'FFFE1198 16, 32 9 DMA reload transfer count register_9 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 421 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Access Size Channel Register Name Abbreviation R/W Initial Value Address 10 DMA source address register_10 SAR_10 R/W H'00000000 H'FFFE10A0 16, 32 DMA destination address register_10 DAR_10 R/W H'00000000 H'FFFE10A4 16, 32 DMA transfer count register_10 DMATCR_10 R/W H'00000000 H'FFFE10A8 16, 32 DMA channel control register_10 CHCR_10 R/W*1 H'00000000 H'FFFE10AC 8, 16, 32 DMA reload source address register_10 RSAR_10 R/W H'00000000 H'FFFE11A0 16, 32 DMA reload destination RDAR_10 address register_10 R/W H'00000000 H'FFFE11A4 16, 32 DMA reload transfer count register_10 RDMATCR_10 R/W H'00000000 H'FFFE11A8 16, 32 DMA source address register_11 SAR_11 R/W H'00000000 H'FFFE10B0 16, 32 DMA destination address register_11 DAR_11 R/W H'00000000 H'FFFE10B4 16, 32 DMA transfer count register_11 DMATCR_11 R/W H'00000000 H'FFFE10B8 16, 32 DMA channel control register_11 CHCR_11 R/W*1 H'00000000 H'FFFE10BC 8, 16, 32 DMA reload source address register_11 RSAR_11 R/W H'00000000 H'FFFE11B0 16, 32 DMA reload destination RDAR_11 address register_11 R/W H'00000000 H'FFFE11B4 16, 32 RDMATCR_11 R/W H'00000000 H'FFFE11B8 16, 32 11 DMA reload transfer count register_11 Page 422 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Access Size Channel Register Name Abbreviation R/W Initial Value Address 12 DMA source address register_12 SAR_12 R/W H'00000000 H'FFFE10C0 16, 32 DMA destination address register_12 DAR_12 R/W H'00000000 H'FFFE10C4 16, 32 DMA transfer count register_12 DMATCR_12 R/W H'00000000 H'FFFE10C8 16, 32 DMA channel control register_12 CHCR_12 R/W*1 H'00000000 H'FFFE10CC 8, 16, 32 DMA reload source address register_12 RSAR_12 R/W H'00000000 H'FFFE11C0 16, 32 DMA reload destination RDAR_12 address register_12 R/W H'00000000 H'FFFE11C4 16, 32 DMA reload transfer count register_12 RDMATCR_12 R/W H'00000000 H'FFFE11C8 16, 32 DMA source address register_13 SAR_13 R/W H'00000000 H'FFFE10D0 16, 32 DMA destination address register_13 DAR_13 R/W H'00000000 H'FFFE10D4 16, 32 DMA transfer count register_13 DMATCR_13 R/W H'00000000 H'FFFE10D8 16, 32 DMA channel control register_13 CHCR_13 R/W*1 H'00000000 H'FFFE10DC 8, 16, 32 DMA reload source address register_13 RSAR_13 R/W H'00000000 H'FFFE11D0 16, 32 DMA reload destination RDAR_13 address register_13 R/W H'00000000 H'FFFE11D4 16, 32 RDMATCR_13 R/W H'00000000 H'FFFE11D8 16, 32 13 DMA reload transfer count register_13 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 423 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Access Size Channel Register Name Abbreviation R/W Initial Value Address 14 DMA source address register_14 SAR_14 R/W H'00000000 H'FFFE10E0 16, 32 DMA destination address register_14 DAR_14 R/W H'00000000 H'FFFE10E4 16, 32 DMA transfer count register_14 DMATCR_14 R/W H'00000000 H'FFFE10E8 16, 32 DMA channel control register_14 CHCR_14 R/W*1 H'00000000 H'FFFE10EC 8, 16, 32 DMA reload source address register_14 RSAR_14 R/W H'00000000 H'FFFE11E0 16, 32 DMA reload destination RDAR_14 address register_14 R/W H'00000000 H'FFFE11E4 16, 32 DMA reload transfer count register_14 RDMATCR_14 R/W H'00000000 H'FFFE11E8 16, 32 DMA source address register_15 SAR_15 R/W H'00000000 H'FFFE10F0 16, 32 DMA destination address register_15 DAR_15 R/W H'00000000 H'FFFE10F4 16, 32 DMA transfer count register_15 DMATCR_15 R/W H'00000000 H'FFFE10F8 16, 32 DMA channel control register_15 CHCR_15 R/W*1 H'00000000 H'FFFE10FC 8, 16, 32 DMA reload source address register_15 RSAR_15 R/W H'00000000 H'FFFE11F0 16, 32 DMA reload destination RDAR_15 address register_15 R/W H'00000000 H'FFFE11F4 16, 32 RDMATCR_15 R/W H'00000000 H'FFFE11F8 16, 32 15 DMA reload transfer count register_15 Page 424 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Abbreviation R/W Access Size Channel Register Name Initial Value Address Common DMA operation register DMAOR R/W*2 H'0000 H'FFFE1200 8, 16 0 and 1 DMA extension resource selector 0 DMARS0 R/W H'0000 H'FFFE1300 16 2 and 3 DMA extension resource selector 1 DMARS1 R/W H'0000 H'FFFE1304 16 4 and 5 DMA extension resource selector 2 DMARS2 R/W H'0000 H'FFFE1308 16 6 and 7 DMA extension resource selector 3 DMARS3 R/W H'0000 H'FFFE130C 16 8 and 9 DMA extension resource selector 4 DMARS4 R/W H'0000 H'FFFE1310 16 10 and 11 DMA extension resource selector 5 DMARS5 R/W H'0000 H'FFFE1314 16 12 and 13 DMA extension resource selector 6 DMARS6 R/W H'0000 H'FFFE1318 16 14 and 15 DMA extension resource selector 7 DMARS7 R/W H'0000 H'FFFE131C 16 Notes: 1. For the HE and TE bits in CHCR_n, only 0 can be written to clear the flags after 1 is read. 2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 425 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller 11.3.1 DMA Source Address Registers (SAR) The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in single address mode, SAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 11.3.2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - 16 - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DMA Destination Address Registers (DAR) The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data of an external device with DACK is transferred in single address mode, DAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 426 of 3092 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.3.3 Section 11 Direct Memory Access Controller DMA Transfer Count Registers (DMATCR) The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: 11.3.4 16 DMA Channel Control Registers (CHCR) The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the DMA transfer mode. The DO, AM, AL, DL, DS, and TL bits which specify the DREQ, DACK, and TEND external pin functions can be read and written to in channel 0, but they are reserved in channels 1 to 15. Bit: Initial value: R/W: Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TC - RLD SAR RLD DAR - DAF SAF - DO TL - TE MASK HE HIE AM AL 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R 0 0 0 R/W R/(W)* R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 DM[1:0] Initial value: R/W: 0 R/W 0 R/W SM[1:0] 0 R/W 0 R/W RS[3:0] 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 DL DS TB 0 R/W 0 R/W 0 R/W 4 3 TS[1:0] 0 R/W 0 R/W 2 1 0 IE TE DE 0 0 0 R/W R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 427 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 31 TC 0 R/W Transfer Count Mode Specifies whether to transmit data once or for the count specified in DMATCR by one transfer request. This function is valid only in on-chip peripheral module request mode. Note that when this bit is set to 0, the TB bit must not be set to 1 (burst mode). This bit (TC) must not be set to 1 if a module other than the multifunction timer pulse unit 2, the compare match timer, the controller area network, the CD-ROM decoder, or the A/D converter is selected as a source of transfer requests. 0: Transmits data once by one transfer request 1: Transmits data for the count specified in DMATCR by one transfer request 30  0 R Reserved This bit is always read as 0. The write value should always be 0. 29 RLDSAR 0 R/W SAR Reload Function ON/OFF Enables (ON) or disables (OFF) the function to reload SAR and DMATCR. 0: Disables (OFF) the function to reload SAR and DMATCR 1: Enables (ON) the function to reload SAR and DMATCR 28 RLDDAR 0 R/W DAR Reload Function ON/OFF Enables (ON) or disables (OFF) the function to reload DAR and DMATCR. 0: Disables (OFF) the function to reload DAR and DMATCR 1: Enables (ON) the function to reload DAR and DMATCR 27  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 428 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 26 DAF 0 R/W Fixed Destination Address 16-Byte Transfer Enabled when the transfer size (set in TS[1:0]) is 16 bytes and the destination address mode (set in DM[1:0]) is fixed address. 0: 16 bytes of data are transferred to the address. Transfer destination addresses for the writing of data are the addresses specified in the DAR, and that address plus H'0, H'4, H'8, and H'C. 1: Four bytes of data are transferred four times to the address specified in DAR. The transfer destination address for the writing of data is fixed to the address specified in the DAR. This function is only for use with the CD-ROM decoder, the USB 2.0 host/function module, the sampling rate converter, the Renesas quad serial peripheral interface, the SD host interface, and the MMC host interface. 25 SAF 0 R/W Fixed Source Address 16-Byte Transfer Enabled when the transfer size (set in TS[1:0]) is 16 bytes and the source address mode (set in SM[1:0]) is fixed address. 0: 16 bytes of data are transferred from the address. Transfer source addresses for the reading of data are the addresses specified in the SAR, and that address plus H'0, H'4, H'8, and H'C. 1: Four bytes of data are transferred four times from the address specified in SAR. The transfer source address for the reading of data is fixed to the address specified in the SAR. This function is only for use with the CD-ROM decoder, the USB 2.0 host/function module, the sampling rate converter, the Renesas quad serial peripheral interface, the SD host interface, and the MMC host interface. 24  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 429 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 23 DO 0 R/W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in level detection by CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 22 TL 0 R/W Transfer End Level Specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: Low-active output from TEND 1: High-active output from TEND 21  0 R Reserved This bit is always read as 0. The write value should always be 0. 20 TEMASK 0 R/W TE Set Mask Specifies that DMA transfer does not stop even if the TE bit is set to 1. If this bit is set to 1 along with the bit for SAR/DAR reload function, DMA transfer can be performed until the transfer request is cancelled. In auto request mode or when a rising/falling edge of the DREQ signal is detected in external request mode, the setting of this bit is ignored and DMA transfer stops if the TE bit is set to 1. Note that this function is enabled only when either the RLDSAR bit or the RLDDAR bit is set to 1. 0: DMA transfer stops if the TE bit is set 1: DMA transfer does not stop even if the TE bit is set Page 430 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W 19 HE 0 R/(W)* Half-End Flag Description This bit is set to 1 when the transfer count reaches half of the DMATCR value that was specified before transfer starts. If DMA transfer ends because of an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR before the transfer count reaches half of the DMATCR value that was specified before transfer starts, the HE bit is not set to 1. If DMA transfer ends due to an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR after the HE bit is set to 1, the bit remains set to 1. To clear the HE bit, write 0 to it after HE = 1 is read. 0: DMATCR > (DMATCR set before transfer starts)/2 during DMA transfer or after DMA transfer is terminated [Clearing condition]  Writing 0 after reading HE = 1. 1: DMATCR  (DMATCR set before transfer starts)/2 18 HIE 0 R/W Half-End Interrupt Enable Specifies whether to issue an interrupt request to the CPU when the transfer count reaches half of the DMATCR value that was specified before transfer starts. When the HIE bit is set to 1, this module requests an interrupt to the CPU when the HE bit becomes 1. 0: Disables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 1: Enables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 431 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 17 AM 0 R/W Acknowledge Mode Specifies whether DACK and TEND are output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK and TEND are always output regardless of the specification by this bit. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: DACK and TEND output in read cycle (dual address mode) 1: DACK and TEND output in write cycle (dual address mode) 16 AL 0 R/W Acknowledge Level Specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: Low-active output from DACK 1: High-active output from DACK Page 432 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 15, 14 DM[1:0] 00 R/W Destination Address Mode These bits select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address 01: Destination address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer) 10: Destination address is decremented (–1 in byteunit transfer, –2 in word-unit transfer, –4 in longword-unit transfer, setting prohibited in 16byte-unit transfer) 11: Setting prohibited 13, 12 SM[1:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00 R/W Source Address Mode These bits select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer) 10: Source address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longwordunit transfer, setting prohibited in 16-byte-unit transfer) 11: Setting prohibited Page 433 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 11 to 8 RS[3:0] 0000 R/W Resource Select These bits specify which transfer requests will be sent to this module. The changing of transfer request source should be done in the state when DMA enable bit (DE) is set to 0. 0000: External request, dual address mode 0001: Setting prohibited 0010: External request/single address mode External address space  External device with DACK 0011: External request/single address mode External device with DACK  External address space 0100: Auto request 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1000: DMA extension resource selector 1001: Controller area network, channel 0 1010: Controller area network, channel 1 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Note: External request specification is valid only in CHCR_0. External request should not be specified for channels CHCR_1 to CHCR_15. Page 434 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 7 DL 0 R/W DREQ Level 6 DS 0 R/W DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0. These bits are reserved in CHCR_1 to CHCR_15; they are always read as 0 and the write value should always be 0. If the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by these bits is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge 5 TB 0 R/W Transfer Bus Mode Specifies the bus mode at DMA transfer. Note that the burst mode must not be selected when TC = 0. 0: Cycle steal mode 1: Burst mode 4, 3 TS[1:0] 00 R/W Transfer Size These bits specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte unit 01: Word unit (two bytes) 10: Longword unit (four bytes) 11: 16-byte (four longword) unit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 435 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 2 IE 0 R/W Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Disables an interrupt request 1: Enables an interrupt request 1 TE 0 R/(W)* Transfer End Flag This bit is set to 1 when DMATCR becomes 0 and DMA transfer ends. The TE bit is not set to 1 in the following cases.  DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0.  DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR). To clear the TE bit, write 0 after reading TE = 1. Even if the DE bit is set to 1 while the TEMASK bit is 0 and this bit is 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been terminated [Clearing condition]  Writing 0 after reading TE = 1 1: DMA transfer ends by the specified count (DMATCR = 0) Page 436 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 0 DE 0 R/W DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this case, all of the bits TE, NMIF in DMAOR, and AE must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. If the DREQ signal is detected by low/high level in external request mode, or in peripheral module request mode, the NMIF bit and the AE bit must be 0 if the TEMASK bit is 1. If the TEMASK bit is 0, the TE bit must also be 0. If the DREQ signal is detected by a rising/falling edge in external request mode, all of the bits TE, NMIF, and AE must be 0 as in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 437 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller 11.3.5 DMA Reload Source Address Registers (RSAR) The DMA reload source address registers (RSAR) are 32-bit readable/writable registers. When the SAR reload function is enabled, the RSAR value is written to the source address register (SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RSAR during the current DMA transfer. When the SAR reload function is disabled, RSAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 438 of 3092 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.3.6 Section 11 Direct Memory Access Controller DMA Reload Destination Address Registers (RDAR) The DMA reload destination address registers (RDAR) are 32-bit readable/writable registers. When the DAR reload function is enabled, the RDAR value is written to the destination address register (DAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDAR during the current DMA transfer. When the DAR reload function is disabled, RDAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 16 Page 439 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller 11.3.7 DMA Reload Transfer Count Registers (RDMATCR) The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers. When the SAR/DAR reload function is enabled, the RDMATCR value is written to the transfer count register (DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDMATCR during the current DMA transfer. When the SAR/DAR reload function is disabled, RDMATCR is ignored. The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0. As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: Page 440 of 3092 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.3.8 Section 11 Direct Memory Access Controller DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register also shows the DMA transfer status. Bit: Initial value: R/W: 15 14 - - 0 R 0 R 13 12 CMS[1:0] 0 R/W 0 R/W 11 10 - - 0 R 0 R 9 8 PR[1:0] 0 R/W 0 R/W 7 6 5 4 3 2 1 0 - - - - - AE NMIF DME 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)* R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 CMS[1:0] 00 R/W Cycle Steal Mode Select These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermittent mode valid. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer for every 16 cycles of B clock. 11: Intermittent mode 64 Executes one DMA transfer for every 64 cycles of B clock. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 441 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 9, 8 PR[1:0] 00 R/W Priority Mode These bits select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11 > CH12 > CH13 > CH14 > CH15 01: Fixed mode 2: CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11 > CH4 > CH12 > CH5 > CH13 > CH6 > CH14 > CH7 > CH15 10: Setting prohibited 11: Setting prohibited 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 AE 0 R/(W)* Address Error Flag Indicates whether an address error has occurred by this module. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. 0: No address error occurred by this module 1: Address error occurred by this module [Clearing condition]  Page 442 of 3092 Writing 0 after reading AE = 1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 1 NMIF 0 R/(W)* NMI Flag Indicates that an NMI interrupt occurred. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. Even if the NMI interrupt is input while this module is not in operation, the NMIF bit is set to 1. 0: No NMI interrupt 1: NMI interrupt occurred [Clearing condition] Writing 0 after reading NMIF = 1 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfer on all channels. If the DME bit and DE bit in CHCR are set to 1, DMA transfer is enabled. However, transfer is enabled only when the TE bit in CHCR of the transfer corresponding channel, the NMIF bit in DMAOR, and the AE bit are all cleared to 0. Clearing the DME bit to 0 can terminate the DMA transfer on all channels. 0: DMA transfer is disabled on all channels 1: DMA transfer is enabled on all channels Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 443 of 3092 Section 11 Direct Memory Access Controller SH7268 Group, SH7269 Group If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If fixed mode 2 is specified, the channel priority is specified as CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11 > CH4 > CH12 > CH5 > CH13 > CH6 > DH14 > CH7 > CH15. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11 > CH12 > CH13 > CH14 > CH15. The internal operation of this module for an address error is as follows:  No address error: Read (source to interior of this module)  Write (interior of this module to destination)  Address error in source address: Nop  Nop  Address error in destination address: Read  Nop Page 444 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.3.9 Section 11 Direct Memory Access Controller DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7) The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that specify the source of the DMA transfer request from peripheral modules in each channel. DMARS0 to DMARS7 are for channels 0 and 1, 2 and 3, 4 and 5, 6 and 7, 8 and 9, 10 and 11, 12 and 13, and 14 and 15, respectively. Table 11.3 shows the specifiable combinations. DMARS can specify the following transfer request sources (The following modules can issue onchip peripheral module requests):                    Serial communication interface with FIFO: 16 sources I2C bus interface 3: eight sources A/D converter: one source Multi-function timer pulse unit 2: five sources Compare match timer: two sources USB 2.0 host/function module: two sources NAND flash memory controller: two sources Controller area network: three sources Serial sound interface: seven sources Sampling rate converter: six sources Sound generator: four sources Renesas SPDIF interface: two sources CD-ROM decoder: one source SD host interface: four sources MMC host interface: two sources Renesas serial peripheral interface: four sources Renesas quad serial peripheral interface: four sources Clock synchronous serial I/O with FIFO: two sources Motor control PWM timer: two sources Three transfer request sources for the controller area network do not need to be specified by these registers, for they can be specified using the RS3 to RS0 bits in the DMA channel control register (CHCR). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 445 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller  DMARS0 Bit: 15 14 13 12 11 10 CH1 MID[5:0] Initial value: R/W: 0 R/W 0 R/W 9 8 7 6 CH1 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 5 4 3 2 CH0 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 1 0 CH0 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS1 Bit: 15 14 CH3 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH3 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH2 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH2 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS2 Bit: 15 14 CH5 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH5 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH4 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH4 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS3 Bit: 15 14 CH7 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH7 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH6 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH6 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS4 Bit: 15 14 CH9 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH9 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH8 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH8 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS5 Bit: 15 14 CH11 MID[5:0] Initial value: R/W: 0 R/W Page 446 of 3092 0 R/W 0 R/W 0 R/W CH11 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W CH10 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W CH10 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller  DMARS6 Bit: 15 14 13 12 11 10 CH13 MID[5:0] Initial value: R/W: 0 R/W 0 R/W 9 8 7 6 CH13 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 5 4 3 2 1 CH12 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 0 CH12 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS7 Bit: 15 14 CH15 MID[5:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W CH15 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W CH14 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W CH14 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W Transfer requests from the various modules specify MID and RID as shown in table 11.3. Table 11.3 DMARS Settings Peripheral Module Setting Value for One Channel ({MID, RID}) MID RID Function USB 2.0 host/function H'03 module B'000000 B'11 Channel 0 FIFO H'07 B'000001 B'11 Channel 1 FIFO Renesas SPDIF interface H'09 B'000010 B'01 Transmit H'0A B'000010 B'10 Receive SD host interface 0 H'11 B'000100 B'01 SD_BUF write B'10 SD_BUF read B'01 SD_BUF write B'10 SD_BUF read B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'11  H'12 SD host interface 1 H'A9 B'101010 H'AA MMC host interface H'AD B'101011 H'AE Clock synchronous serial I/O with FIFO H'19 B'000110 H'1A Serial sound interface H'21 Channel 0 H'22 B'001000 Serial sound interface H'27 Channel 1 B'001001 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 447 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Peripheral Module Setting Value for One Channel ({MID, RID}) MID RID Function Serial sound interface H'2B Channel 2 B'001010 B'11  Serial sound interface H'2F Channel 3 B'001011 B'11  Serial sound interface H'B9 Channel 4 B'101110 B'01  Serial sound interface H'BD Channel 5 B'101111 B'01  Motor control PWM timer Channel 1 H'33 B'001100 B'11  Motor control PWM timer Channel 2 H'37 B'001101 B'11  Sound generator 0 H'C5 B'110001 B'01  Sound generator 1 H'C9 B'110010 B'01  Sound generator 2 H'CD B'110011 B'01  Sound generator 3 H'D5 B'110101 B'01  Sampling rate converter Channel 0 H'41 B'010000 B'01 Input data FIFO empty B'10 Output data FIFO full Sampling rate converter Channel 1 H'45 B'01 Input data FIFO empty B'10 Output data FIFO full Sampling rate converter Channel 2 H'B5 B'01 Input data FIFO empty B'10 Output data FIFO full Renesas serial peripheral interface Channel 0 H'51 B'01 Transmit B'10 Receive Renesas serial peripheral interface Channel 1 H'55 B'01 Transmit B'10 Receive Page 448 of 3092 H'42 B'010001 H'46 B'101101 H'B6 B'010100 H'52 H'56 B'010101 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Setting Value for One Channel ({MID, RID}) MID RID Function Renesas quad serial peripheral interface Channel 0 H'A1 B'101000 B'01 Transmit B'10 Receive Renesas quad serial peripheral interface Channel 1 H'A5 B'01 Transmit B'10 Receive I2C bus interface 3 Channel 0 H'61 I2C bus interface 3 Channel 0 H'61 Peripheral Module 2 I C bus interface 3 Channel 1 2 I C bus interface 3 Channel 2 2 H'A2 B'101001 H'A6 B'011000 H'62 B'011000 H'62 H'65 B'011001 H'66 H'69 B'011010 H'6A I C bus interface 3 Channel 3 H'C1 CD-ROM decoder H'73 B'110000 B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'011100 B'11  Serial communication H'81 interface with FIFO H'82 Channel 0 B'100000 B'01 Transmit B'10 Receive Serial communication H'85 interface with FIFO H'86 Channel 1 B'100001 Serial communication H'89 interface with FIFO H'8A Channel 2 B'100010 Serial communication H'8D interface with FIFO H'8E Channel 3 B'100011 Serial communication H'91 interface with FIFO H'92 Channel 4 B'100100 Serial communication H'95 interface with FIFO H'96 Channel 5 B'100101 H'C2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive Page 449 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Peripheral Module Setting Value for One Channel ({MID, RID}) MID RID Function Serial communication H'99 interface with FIFO H'9A Channel 6 B'100110 B'01 Transmit B'10 Receive Serial communication H'9D interface with FIFO H'9E Channel 7 B'100111 B'01 Transmit B'10 Receive A/D converter H'B3 B'101100 B'11  NAND flash memory controller H'BB B'101110 B'11 Transmit/ receive data H'BF B'101111 B'11 Transmit/ receive control code Multi-function timer pulse unit 2 Channel 0 H'E3 B'111000 B'11  Multi-function timer pulse unit 2 Channel 1 H'E7 B'111001 B'11  Multi-function timer pulse unit 2 Channel 2 H'EB B'111010 B'11  Multi-function timer pulse unit 2 Channel 3 H'EF B'111011 B'11  Multi-function timer pulse unit 2 Channel 4 H'F3 B'111100 B'11  Compare match timer H'FB Channel 0 B'111110 B'11  Compare match timer H'FF Channel 1 B'111111 B'11  When MID or RID other than the values listed in table 11.3 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to RS0) in CHCR0 to CHCR15 have been set to B'1000. Otherwise, even if DMARS has been set, the transfer request source is not accepted. Page 450 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.4 Section 11 Direct Memory Access Controller Operation When there is a DMA transfer request, this module starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, the burst mode or the cycle steal mode can be selected. 11.4.1 Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), three reload registers (RSAR, RDAR, RDMATCR) and DMA extension resource selector (DMARS) are set for the target transfer conditions, this module transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0), AE = 0, NMIF = 0). 2. When a transfer request comes and transfer is enabled, this module transfers one transfer unit of data (depending on the settings of the TS1 and TS0 bits). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1. 4. When transfer has been completed for the specified count (when DMATCR reaches 0) while the TEMASK bit is 0, the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. When DMATCR reaches 0 while the TEMASK bit is 1, the TE bit is set to 1 and then the values set in RSAR, RDAR and RDMATCR are reloaded in SAR, DAR and DMATCR, respectively to continue transfer operation until the DMA transfer request is cancelled. 5. When an address error in this module or an NMI interrupt is generated, the transfer is terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 451 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Figure 11.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Transfer request occurs?*1 No *2 Yes *3 Bus mode, transfer request mode, DREQ detection system Transfer (one transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated No DMATCR = 0? No Yes DMATCR = 1/2 ? Yes TE = 1 HE = 1 DEI interrupt request (when IE = 1) HEI interrupt request (when HE = 1) When reload function is enabled, RSAR → SAR, RDAR → DAR, and RDMATCR → DMATCR When the TC bit in CHCR is 0, or for a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. For a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. NMIF = 1 or AE = 1 or DE = 0 or DME = 0? NMIF = 1 or AE = 1 or DE = 0 or DME = 0? No No In DREQ detection by level in external Yes Yes request mode, or in on-chip peripheral module request mode, TEMASK = 1? Yes No Transfer end Normal end Transfer terminated Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the DE and DME bits are set to 1. 2. DREQ level detection in burst mode (external request) or cycle steal mode. 3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode. Figure 11.2 DMA Transfer Flowchart Page 452 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.4.2 Section 11 Direct Memory Access Controller DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated in external devices and on-chip peripheral modules that are neither the transfer source nor destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_15 and DMARS0 to DMARS7. (1) Auto-Request Mode When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows this module to automatically generate a transfer request signal internally. When the DE bits in CHCR_0 to CHCR_15 and the DME bit in DMAOR are set to 1, the transfer begins so long as the TE bits in CHCR_0 to CHCR_15, and the AE and NMIF bits in DMAOR are 0. (2) External Request Mode In this mode a transfer is performed at the request signal (DREQ0) of an external device. Choose one of the modes shown in table 11.4 according to the application system. When the DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0), AE = 0, NMIF = 0 for level detection; DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0 for edge detection), DMA transfer is performed upon a request at the DREQ input. Table 11.4 Selecting External Request Modes with the RS Bits RS[3] RS[2] RS[1] RS[0] Address Mode Transfer Source Transfer Destination 0 0 0 0 Dual address mode Any Any 0 0 1 0 Single address mode External memory, memory-mapped external device 1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 External device with DACK External device with DACK External memory, memory-mapped external device Page 453 of 3092 Section 11 Direct Memory Access Controller SH7268 Group, SH7269 Group Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in CHCR_0 as shown in table 11.5. The source of the transfer request does not have to be the data transfer source or destination. When DREQ is detected by a rising/falling edge and DMA transfer is performed in burst mode, the transfer continues until DMATCR reaches 0 by one DMA transfer request. In cycle steal mode, one DMA transfer is performed by one request. Table 11.5 Selecting External Request Detection with DL and DS Bits CHCR DL Bit DS Bit Detection of External Request 0 0 Low-level detection 1 Falling-edge detection 0 High-level detection 1 Rising-edge detection 1 When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again enters the request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK.  Overrun 0: Transfer is terminated after the same number of transfer has been performed as requests.  Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 11.6 Selecting External Request Detection with DO Bit CHCR DO Bit External Request 0 Overrun 0 1 Overrun 1 Page 454 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 11 Direct Memory Access Controller On-Chip Peripheral Module Request In this mode, the transfer is performed in response to the DMA transfer request signal from an onchip peripheral module. Table 11.7 lists the DMA transfer request signals sent from on-chip peripheral modules to this module. If DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0), AE = 0, and NMIF = 0) in on-chip peripheral module request mode, DMA transfer is started by a transfer request signal. In on-chip peripheral module request mode, there are cases where transfer source or destination is fixed. For details, see table 11.7. Table 11.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits CHCR DMARS RS[3:0] MID DMA Transfer Request RID Source DMA Transfer Request Signal Transfer Source Transfer Bus Destination Mode 1001 Any Any Controller area network Channel 0 RM0 (reception end) MB0 Any 1010 Any Any Controller area network Channel 1 RM0 (reception end) MB0 Any 1011 Any Any Controller area network Channel 2 RM0 (reception end) MB0 Any 1000 000000 11 USB_DMA0 (receive FIFO in channel 0 full) D0FIFO Any USB_DMA0 (transmit FIFO in channel 0 empty) Any D0FIFO USB_DMA1 (receive FIFO in channel 1 full) D1FIFO Any USB_DMA1 (transmit FIFO in channel 1 empty) Any D1FIFO USB 2.0 host/function module 000001 11 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Cycle steal Page 455 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller CHCR DMARS RS[3:0] MID 1000 DMA Transfer Request RID Source 000010 01 Transfer DMA Transfer Request Signal Source Renesas SPDIF SPDIFTXI Any interface (DMA transfer from transmission module) 10 SPDIFRXI Transfer Bus Destination Mode TDAD RDAD Any SD_BUF write Any Data register SD_BUF read Data register Any SD_BUF write Any Data register SD_BUF read Data register Any Transmit data empty Any Data register Receive data full Data register Any Clock synchronous serial I/O with FIFO TXI transmit data transfer) Any SITDR RXI (receive data transfer) SIRDR Any Serial sound interface Channel 0 SSITXI0 (transmit data empty) Any SSIFTDR_0 SSIRXI0 (receive data full) SSIFRDR_0 Any Serial sound interface Channel 1 SSIRTI1 (transmit data empty) Any SSIRTI1 (receive data full) SSIFRDR_1 Any Serial sound interface Channel 2 SSIRTI2 (transmit data empty) Any SSIRTI2 (receive data full) SSIFRDR_2 Any Serial sound interface Channel 3 SSIRTI3 (transmit data empty) Any SSIRTI3 (receive data full) SSIFRDR_3 Any Cycle steal (DMA transfer to reception module) 000100 01 SD host interface 0 10 101010 01 SD host interface 1 10 101011 01 MMC host interface 10 000110 01 10 001000 01 10 001001 11 001010 11 001011 11 Page 456 of 3092 SSIFTDR_1 SSIFTDR_2 SSIFTDR_3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group CHCR DMARS RS[3:0] MID 1000 DMA Transfer Request RID Source Section 11 Direct Memory Access Controller 101100 01 Transfer DMA Transfer Request Signal Source Transfer Bus Destination Mode Serial sound interface Channel 4 SSIRTI4 (transmit data empty) SSIRTI4 (receive data full) SSIFTDR_4 Cycle steal SSIFRDR_4 Any Serial sound interface Channel 5 SSIRTI5 (transmit data empty) Any SSIRTI5 (receive data full) SSIFRDR_5 Any 001100 11 Motor control PWM timer Channel 1 CMI1 (PWM compare match) Any PWBFR1 001101 11 Motor control PWM timer Channel 2 CMI2 (PWM compare match) Any PWBFR2 110001 01 Sound generator SGDEI0 0 Any SGLR_0 110010 01 Sound generator SGDEI1 1 Any SGLR_1 110011 01 Sound generator SGDEI2 2 Any SGLR_2 110101 01 Sound generator SGDEI3 3 Any SGLR_3 010000 01 Sampling rate converter Channel 0 IDEI0 (input data empty) Any SRCIDR_0 ODFI0 (output data full) SRCODR_0 Any Sampling rate converter Channel 1 IDEI1 (input data empty) Any ODFI1 (output data full) SRCODR_1 Any Sampling rate converter Channel 2 IDEI2 (input data empty) Any ODFI2 (output data full) SRCODR_2 Any Renesas serial peripheral interface Channel 0 SPTI0 (transmit buffer empty) Any SPDR_0 SPRI0 (receive buffer full) SPDR_0 Any 101111 01 10 010001 01 10 101101 01 10 010100 01 10 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Any SSIFTDR_5 SRCIDR_1 SRCIDR_2 Page 457 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller CHCR DMARS Transfer DMA Transfer Request Signal Source Transfer Bus Destination Mode SPTI1 (transmit buffer empty) Any SPDR_1 SPRI1 (receive buffer full) SPDR_1 Any Renesas quad SPTI0 (transmit buffer empty) serial peripheral SPRI0 (receive buffer full) interface Channel 0 Any SPDR_0 SPDR_0 Any Renesas quad SPTI1 (transmit buffer empty) serial peripheral SPRI1 (receive buffer full) interface Channel 1 Any SPDR_1 SPDR_1 Any Any ICDRT_0 ICDRR_0 Any Any ICDRT_1 ICDRR_1 Any Any ICDRT_2 ICDRR_2 Any I C bus interface TXI3 (transmit data empty) 3 RXI3 (receive data full) Channel 3 Any ICDRT_3 ICDRR_3 Any 011100 11 CD-ROM decoder IREADY (decode end) STRMDOUT Any 100000 01 Serial communication interface with FIFO Channel 0 TXI0 (transmit FIFO data empty) Any Serial communication interface with FIFO Channel 1 TXI1 (transmit FIFO data empty) Any RS[3:0] MID 1000 DMA Transfer Request RID Source 010101 01 10 101000 01 10 101001 01 10 011000 01 10 011001 01 10 011010 01 10 110000 01 10 10 100001 01 10 Page 458 of 3092 Renesas serial peripheral interface Channel 1 2 I C bus interface TXI0 (transmit data empty) 3 RXI0 (receive data full) Channel 0 2 I C bus interface TXI1 (transmit data empty) 3 RXI1 (receive data full) Channel 1 2 I C bus interface TXI2 (transmit data empty) 3 RXI2 (receive data full) Channel 2 2 RXI0 (receive FIFO data full) RXI1 (receive FIFO data full) Cycle steal Cycle steal or burst SCFTDR_0 Cycle steal SCFRDR_0 Any SCFTDR_1 SCFRDR_1 Any R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group CHCR DMARS RS[3:0] MID 1000 DMA Transfer Request RID Source Section 11 Direct Memory Access Controller 100010 01 10 100011 01 10 100100 01 10 100101 01 10 100110 01 10 100111 01 10 Transfer DMA Transfer Request Signal Source Serial communication interface with FIFO Channel 2 TXI2 (transmit FIFO data empty) Any Serial communication interface with FIFO Channel 3 TXI3 (transmit FIFO data empty) Any Serial communication interface with FIFO Channel 4 TXI4 (transmit FIFO data empty) Any Serial communication interface with FIFO Channel 5 TXI5 (transmit FIFO data empty) Any Serial communication interface with FIFO Channel 6 TXI6 (transmit FIFO data empty) Any Serial communication interface with FIFO Channel 7 TXI7 (transmit FIFO data empty) Any RXI2 (receive FIFO data full) RXI3 (receive FIFO data full) RXI4 (receive FIFO data full) RXI5 (receive FIFO data full) RXI6 (receive FIFO data full) Transfer Bus Destination Mode SCFTDR_2 Cycle steal SCFRDR_2 Any SCFTDR_3 SCFRDR_3 Any SCFTDR_4 SCFRDR_4 Any SCFTDR_5 SCFRDR_5 Any SCFTDR_6 SCFRDR_6 Any SCFTDR_7 RXI7 (receive FIFO data full) SCFRDR_7 Any 101100 11 A/D converter ADI (A/D conversion end) ADDR Any 101110 11 NAND flash memory controller Data part Transmission FIFO data empty Any FLDTFIFO Data part Reception FIFO data full FLDTFIFO Any Control code part Transmission FIFO data empty Any FLECFIFO Control code part Reception FIFO data full FLECFIFO Any 101111 11 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 459 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller CHCR DMARS RS[3:0] MID 1000 DMA Transfer Request RID Source Transfer DMA Transfer Request Signal Source Transfer Bus Destination Mode 111000 11 Multi-function timer pulse unit 2 Channel 0 TGI0A Any (input capture or compare match) Any 111001 11 Multi-function timer pulse unit 2 Channel 1 TGI1A Any (input capture or compare match) Any 111010 11 Multi-function timer pulse unit 2 Channel 2 TGI2A Any (input capture or compare match) Any 111011 11 Multi-function timer pulse unit 2 Channel 3 TGI3A Any (input capture or compare match) Any 111100 11 Multi-function timer pulse unit 2 Channel 4 TGI4A Any (input capture or compare match) Any 111110 11 Compare match CMI0 (compare match) timer Channel 0 Any Any 111111 11 Compare match CMI1 (compare match) timer Channel 1 Any Any Page 460 of 3092 Cycle steal or burst R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.4.3 Section 11 Direct Memory Access Controller Channel Priority When this module receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode 1 and fixed mode 2) are selected. In these mode, the priority levels among the channels are as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11> CH12> CH13 > CH14 > CH15 Fixed mode 2: CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11> CH4 > CH12 > CH5 > CH13 > CH6> CH14 > CH7 > CH15 These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR). 11.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to the transfer source and destination. A data transfer timing depends on the bus mode, which is the cycle steal mode or burst mode. This module supports the transfers shown in table 11.8. Table 11.8 Supported DMA Transfers Transfer Destination External Device with Transfer Source DACK External device with DACK Not available External Memory MemoryOn-Chip Mapped Peripheral External Device Module On-Chip Memory Dual, single Dual, single Not available Not available External memory Dual, single Dual Dual Dual Dual Memory-mapped Dual, single external device Dual Dual Dual Dual On-chip peripheral module Not available Dual Dual Dual Dual On-chip memory Not available Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is available only for on-chip peripheral modules that support longword access. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 461 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller (1) Address Modes (a) Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selected) by an address. The transfer source and destination can be located externally or internally. SAR Data bus DAR Memory Address bus Direct memory access controller DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in this module. In the transfer between external memories as shown in figure 11.3, data is read to this module from one external memory in a data read cycle, and then that data is written to the other external memory in a data write cycle. Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the direct memory access controller. SAR Data bus DAR Memory Address bus Direct memory access controller First bus cycle Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the direct memory access controller is written to the transfer destination module. Second bus cycle Figure 11.3 Data Flow of Dual Address Mode Page 462 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Figure 11.4 shows an example of DMA transfer timing in dual address mode. CKIO A25 to A0 Transfer source address Transfer destination address CSn D15 to D0 RD WEn DACKn (Active-low) Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 11.4 Example of DMA Transfer Timing in Dual Mode (Transfer Source: Normal Memory, Transfer Destination: Normal Memory) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 463 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller (b) Single Address Mode In single address mode, both the transfer source and destination are external devices, either of them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In this mode, this module performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 11.5, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus External data bus This LSI Direct memory access controller External memory External device with DACK DACK DREQ Data flow (from memory to device) Data flow (from device to memory) Figure 11.5 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Page 464 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller Figure 11.6 shows an example of DMA transfer timing in single address mode. CK A25 to A0 Address output to external memory space CSn Select signal to external memory space WEn Write strobe signal to external memory space Data output from external device with DACK D15 to D0 DACKn DACK signal (active-low) to external device with DACK (a) External device with DACK → External memory space (normal memory) CK A25 to A0 Address output to external memory space CSn Select signal to external memory space RD Read strobe signal to external memory space Data output from external memory space D15 to D0 DACKn DACK signal (active-low) to external device with DACK (b) External memory space (normal memory) → External device with DACK Figure 11.6 Example of DMA Transfer Timing in Single Address Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 465 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller (2) Bus Modes There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel control registers (CHCR). (a) Cycle Steal Mode  Normal mode In normal mode of cycle steal, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer request occurs, the bus mastership is obtained from another bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is repeated until the transfer end conditions are satisfied. The cycle-steal normal mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. Figure 11.7 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer conditions shown in the figure are;  Dual address mode  DREQ low level detection DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMA DMA Read/Write CPU DMA DMA CPU Read/Write Figure 11.7 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)  Intermittent Mode 16 and Intermittent Mode 64 In intermittent mode of cycle steal, this module returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next transfer request occurs after that, this module obtains the bus mastership from other bus master after waiting for 16 or 64 cycles of B clock. This module then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal. When this module obtains again the bus mastership, DMA transfer may be postponed in case of entry updating due to cache miss. Page 466 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller The cycle-steal intermittent mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in all channels. Figure 11.8 shows an example of DMA transfer timing in cycle-steal intermittent mode. Transfer conditions shown in the figure are;  Dual address mode  DREQ low level detection DREQ More than 16 or 64 Bφ clock cycles (depending on the state of bus used by bus master such as CPU) Bus cycle CPU CPU CPU DMA DMA CPU CPU Read/Write DMA DMA CPU Read/Write Figure 11.8 Example of DMA Transfer in Cycle-Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) (b) Burst Mode In burst mode, once this module obtains the bus mastership, it does not release the bus mastership and continues to perform transfer until the transfer end condition is satisfied. In external request mode with low-level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus mastership is passed to another bus master after the DMA transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Figure 11.9 shows DMA transfer timing in burst mode. DREQ Bus cycle CPU CPU CPU DMA DMA DMA DMA Read Write Read Write CPU CPU Figure 11.9 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 467 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller (3) Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 11.9 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Dual Single Request Mode Bus Transfer Mode Size (Bits) Usable Channels External B/C 8/16/32/128 0 External device with DACK and memory- External mapped external device B/C 8/16/32/128 0 Transfer Category External device with DACK and external memory External memory and external memory All*4 B/C 8/16/32/128 0 to 15*3 External memory and memory-mapped external device All*4 B/C 8/16/32/128 0 to 15*3 Memory-mapped external device and memory-mapped external device All*4 B/C 8/16/32/128 0 to 15*3 External memory and on-chip peripheral module All*1 B/C*5 8/16/32/128*2 0 to 15*3 Memory-mapped external device and on-chip peripheral module All*1 B/C*5 8/16/32/128*2 0 to 15*3 On-chip peripheral module and on-chip peripheral module All*1 B/C*5 8/16/32/128*2 0 to 15*3 On-chip memory and on-chip memory All*4 B/C 8/16/32/128 0 to 15*3 On-chip memory and memory-mapped external device All*4 B/C 8/16/32/128 0 to 15*3 On-chip memory and on-chip peripheral module All*1 B/C*5 8/16/32/128*2 0 to 15*3 On-chip memory and external memory All*4 B/C 8/16/32/128 0 to 15*3 External device with DACK and external memory External B/C 8/16/32/128 0 External device with DACK and memory- External mapped external device B/C 8/16/32/128 0 [Legend] B: Burst C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. However, in the case of internal module request, along with the exception of the multi-function timer pulse unit 2 and the compare match timer as the transfer request source, the requesting module must be designated as the transfer source or the transfer destination. Page 468 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller 2. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 3. If the transfer request is an external request, channel 0 is only available. 4. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, however, the compare match timer and the multi-function timer pulse unit 2 are only available. 5. In the case of on-chip peripheral module request, only cycle steal except for the CD-ROM decoder, the multi-function timer pulse unit 2, and the compare match timer as the transfer request source. (4) Bus Mode and Channel Priority In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0. When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1, channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of this is shown in figure 11.10. When multiple channels are in burst mode, data transfer on the channel that has the highest priority is given precedence. When DMA transfer is being performed on multiple channels, the bus mastership is not released to another bus-master device until all of the competing burst-mode transfers have been completed. CPU CPU DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 CH0 CH1 CH0 Direct memory access controller CH1 Burst mode Direct memory access controller CH0 and CH1 Cycle steal mode DMA CH1 DMA CH1 Direct memory access controller CH1 Burst mode CPU CPU Priority: CH0 > CH1 CH0: Cycle steal mode CH1: Burst mode Figure 11.10 Bus State when Multiple Channels are Operating R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 469 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller 11.4.5 (1) Number of Bus Cycles and DREQ Pin Sampling Timing Number of Bus Cycles When this module is the bus master, the number of bus cycles is controlled by the bus state controller in the same way as when the CPU is the bus master. For details, see section 10, Bus State Controller. (2) DREQ Pin Sampling Timing Figures 11.11 to 11.14 show the DREQ input sampling timings in each bus mode. CKIO Bus cycle DREQ (Rising) CPU CPU 1st acceptance DMA CPU 2nd acceptance Non sensitive period DACK (Active-high) Acceptance start Figure 11.11 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) CPU CPU DMA 1st acceptance CPU 2nd acceptance Non sensitive period DACK (Active-high) Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU CPU 1st acceptance DMA CPU 2nd acceptance Non sensitive period Acceptance start Figure 11.12 Example of DREQ Input Detection in Cycle Steal Mode Level Detection Page 470 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller CKIO Bus cycle CPU CPU DMA DMA Burst acceptance DREQ (Rising) Non sensitive period DACK (Active-high) Figure 11.13 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO CPU Bus cycle CPU DMA 2nd acceptance 1st acceptance DREQ (Overrun 0 at high level) Non sensitive period DACK (Active-high) Acceptance start CKIO CPU Bus cycle CPU DMA 2nd acceptance 1st acceptance DREQ (Overrun 1 at high level) DMA 3rd acceptance Non sensitive period DACK (Active-high) Acceptance start Acceptance start Figure 11.14 Example of DREQ Input Detection in Burst Mode Level Detection Figure 11.15 shows the TEND output timing. CKIO End of DMA transfer Bus cycle DMA CPU DMA CPU CPU DREQ DACK TEND Figure 11.15 Example of DMA Transfer End Signal Timing (Cycle Steal Mode Level Detection) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 471 of 3092 SH7268 Group, SH7269 Group Section 11 Direct Memory Access Controller The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is made to an 8-bit or 16-bit external device, or when word access is made to an 8-bit external device. When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS signal for data alignment as shown in figure 11.16. Figures 11.11 to 11.15 show the cases where DACK and TEND are not divided in the DMA transfer. T1 T2 Taw T1 T2 CKIO Address CS RD Data WEn DACKn (Active low) TEND (Active low) WAIT Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles, TEND is also divided. Figure 11.16 Bus State Controller Normal Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) Page 472 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 11.5 Usage Notes 11.5.1 Timing of DACK and TEND Outputs Section 11 Direct Memory Access Controller When the external memory is the MPX-I/O, the DACK output is asserted with the timing of the data cycle. For details, see section 10.5.5, MPX-I/O Interface in section 10, Bus State Controller. When the memory is other than the MPX-I/O, the DACK output is asserted with the same timing as the corresponding CS signal. The TEND output does not depend on the type of memory and is always asserted with the same timing as the corresponding CS signal. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 473 of 3092 Section 11 Direct Memory Access Controller Page 474 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Section 12 Multi-Function Timer Pulse Unit 2 This LSI has an on-chip multi-function timer pulse unit 2 that comprises five 16-bit timer channels. 12.1 Features  Maximum 16 pulse input/output lines  Selection of eight counter input clocks for each channel  The following operations can be set:  Waveform output at compare match  Input capture function  Counter clear operation  Multiple timer counters (TCNT) can be written to simultaneously  Simultaneous clearing by compare match and input capture is possible  Register simultaneous input/output is possible by synchronous counter operation  A maximum 12-phase PWM output is possible in combination with synchronous operation  Buffer operation settable for channels 0, 3, and 4  Phase counting mode settable independently for each of channels 1 and 2  Cascade connection operation  Fast access via internal 16-bit bus  25 interrupt sources  Automatic transfer of register data  A/D converter start trigger can be generated  Module standby mode can be settable  A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible.  AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible.  In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 475 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.1 Functions of Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Count clock P0/1 P0/4 P0/16 P0/64 TCLKA TCLKB TCLKC TCLKD P0/1 P0/4 P0/16 P0/64 P0/256 TCLKA TCLKB P0/1 P0/4 P0/16 P0/64 P0/1024 TCLKA TCLKB TCLKC P0/1 P0/4 P0/16 P0/64 P0/256 P0/1024 TCLKA TCLKB P0/1 P0/4 P0/16 P0/64 P0/256 P0/1024 TCLKA TCLKB General registers TGRA_0 TGRB_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 General registers/ buffer registers TGRC_0 TGRD_0 TGRF_0   TGRC_3 TGRD_3 TGRC_4 TGRD_4 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output                Input capture function      Synchronous operation      PWM mode 1      PWM mode 2      Complementary PWM mode      Reset PWM mode      AC synchronous motor drive mode      Page 476 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Phase counting mode      Buffer operation      Activation of direct TGR compare memory access match or input controller capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow A/D converter start trigger TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_0 compare match or input capture TGRE_0 compare match Interrupt sources TCNT_4 underflow (trough) in complementary PWM mode 7 sources 4 sources 4 sources 5 sources 5 sources        Compare Compare Compare match or match or match or match or input capture input capture input capture input capture input capture 0A 1A 2A 3A 4A Compare  Compare  Compare   Compare match or match or match or match or input capture input capture input capture input capture input capture 0B 1B 2B 3B 4B Compare  match or  Compare Overflow  Underflow  Overflow  Underflow Compare  match or input capture input capture 3C  Compare match or Compare 4C  Compare match or match or match or input capture input capture input capture 0D 3D 4D Compare match 0E  Compare match or 0C  Compare match or input capture  Compare  Overflow  Overflow or underflow Compare match 0F  Overflow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 477 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 A/D converter start request delaying function      A/D converter start request at a match between TADCORA_4 and TCNT_4  A/D converter start request at a match between TADCORB_4 and TCNT_4 Interrupt skipping function     Skips  Skips TCIV_4 interrupts TGRA_3 compare match interrupts [Legend] : Available : Not available Page 478 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TGRD TGRD TGRB TGRC TGRB TGRC TCBR TDDR TCNT TCDR TGRA TCNT TGRA TCNTS TGRF TGRE TGRD TGRB TGRB TGRB A/D converter conversion start signal TGRC TCNT TCNT TGRA TCNT TGRA BUS I/F Module data bus TSYR TSTR TSR TIER TSR TIER TSR TIER TIOR TIOR TIORL TIORH Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 Peripheral bus TGRA TSR TIER TIER TGCR TSR TMDR TIORL TIORH TIORL TIORH TOER TOCR Channel 3 Channel 4 TCR TMDR TCR TMDR Channel 1 TCR TMDR Channel 0 TCR Control logic for channels 0 to 2 Channel 2 Common Control logic Clock input Internal clock: P0φ/1 P0φ/4 P0φ/16 P0φ/64 P0φ/256 P0φ/1024 External clock: TCLKA TCLKB TCLKC TCLKD Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B TCR Control logic for channels 3 and 4 Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D TMDR Figure 12.1 shows a block diagram. Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2 [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Figure 12.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 479 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 12.2 SH7268 Group, SH7269 Group Input/Output Pins Table 12.2 shows the pin configuration. Table 12.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input) TIOC0A I/O TGRA_0 input capture input/output compare output/PWM output pin TIOC0B I/O TGRB_0 input capture input/output compare output/PWM output pin TIOC0C I/O TGRC_0 input capture input/output compare output/PWM output pin TIOC0D I/O TGRD_0 input capture input/output compare output/PWM output pin 0 1 2 3 4 TIOC1A I/O TGRA_1 input capture input/output compare output/PWM output pin TIOC1B I/O TGRB_1 input capture input/output compare output/PWM output pin TIOC2A I/O TGRA_2 input capture input/output compare output/PWM output pin TIOC2B I/O TGRB_2 input capture input/output compare output/PWM output pin TIOC3A I/O TGRA_3 input capture input/output compare output/PWM output pin TIOC3B I/O TGRB_3 input capture input/output compare output/PWM output pin TIOC3C I/O TGRC_3 input capture input/output compare output/PWM output pin TIOC3D I/O TGRD_3 input capture input/output compare output/PWM output pin TIOC4A I/O TGRA_4 input capture input/output compare output/PWM output pin TIOC4B I/O TGRB_4 input capture input/output compare output/PWM output pin TIOC4C I/O TGRC_4 input capture input/output compare output/PWM output pin TIOC4D I/O TGRD_4 input capture input/output compare output/PWM output pin Note: For the pin configuration in complementary PWM mode, see table 12.54 in section 12.4.8, Complementary PWM Mode. Page 480 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.3 Section 12 Multi-Function Timer Pulse Unit 2 Register Descriptions Table 12.3 shows the register configuration. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 12.3 Register Configuration Channel Register Name 0 1 Abbreviation R/W Initial value Address Access Size Timer control register_0 TCR_0 R/W H'00 H'FFFE4300 8 Timer mode register_0 TMDR_0 R/W H'00 H'FFFE4301 8 Timer I/O control register H_0 TIORH_0 R/W H'00 H'FFFE4302 8 Timer I/O control register L_0 TIORL_0 R/W H'00 H'FFFE4303 8 Timer interrupt enable register_0 TIER_0 R/W H'00 H'FFFE4304 8 Timer status register_0 TSR_0 R/W H'C0 H'FFFE4305 8 Timer counter_0 TCNT_0 R/W H'0000 H'FFFE4306 16 Timer general register A_0 TGRA_0 R/W H'FFFF H'FFFE4308 16 Timer general register B_0 TGRB_0 R/W H'FFFF H'FFFE430A 16 Timer general register C_0 TGRC_0 R/W H'FFFF H'FFFE430C 16 Timer general register D_0 TGRD_0 R/W H'FFFF H'FFFE430E 16 Timer general register E_0 TGRE_0 R/W H'FFFF H'FFFE4320 16 Timer general register F_0 TGRF_0 R/W H'FFFF H'FFFE4322 16 Timer interrupt enable register TIER2_0 2_0 R/W H'00 H'FFFE4324 8 Timer status register 2_0 TSR2_0 R/W H'C0 H'FFFE4325 8 Timer buffer operation transfer TBTM_0 mode register_0 R/W H'00 H'FFFE4326 8 Timer control register_1 TCR_1 R/W H'00 H'FFFE4380 8 Timer mode register_1 TMDR_1 R/W H'00 H'FFFE4381 8 Timer I/O control register_1 TIOR_1 R/W H'00 H'FFFE4382 8 Timer interrupt enable register_1 TIER_1 R/W H'00 H'FFFE4384 8 Timer status register_1 TSR_1 R/W H'C0 H'FFFE4385 8 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 481 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Channel Register Name Abbreviation R/W Initial value Address Access Size 1 Timer counter_1 TCNT_1 R/W H'0000 H'FFFE4386 16 Timer general register A_1 TGRA_1 R/W H'FFFF H'FFFE4388 16 Timer general register B_1 TGRB_1 R/W H'FFFF H'FFFE438A 16 Timer input capture control register TICCR R/W H'00 H'FFFE4390 8 Timer control register_2 TCR_2 R/W H'00 H'FFFE4000 8 Timer mode register_2 TMDR_2 R/W H'00 H'FFFE4001 8 Timer I/O control register_2 TIOR_2 R/W H'00 H'FFFE4002 8 Timer interrupt enable register_2 TIER_2 R/W H'00 H'FFFE4004 8 2 3 4 Timer status register_2 TSR_2 R/W H'C0 H'FFFE4005 8 Timer counter_2 TCNT_2 R/W H'0000 H'FFFE4006 16 Timer general register A_2 TGRA_2 R/W H'FFFF H'FFFE4008 16 Timer general register B_2 TGRB_2 R/W H'FFFF H'FFFE400A 16 Timer control register_3 TCR_3 R/W H'00 H'FFFE4200 8 Timer mode register_3 TMDR_3 R/W H'00 H'FFFE4202 8 Timer I/O control register H_3 TIORH_3 R/W H'00 H'FFFE4204 8 Timer I/O control register L_3 TIORL_3 R/W H'00 H'FFFE4205 8 Timer interrupt enable register_3 TIER_3 R/W H'00 H'FFFE4208 8 Timer status register_3 TSR_3 R/W H'C0 H'FFFE422C 8 Timer counter_3 TCNT_3 R/W H'0000 H'FFFE4210 16 Timer general register A_3 TGRA_3 R/W H'FFFF H'FFFE4218 16 Timer general register B_3 TGRB_3 R/W H'FFFF H'FFFE421A 16 Timer general register C_3 TGRC_3 R/W H'FFFF H'FFFE4224 16 Timer general register D_3 TGRD_3 R/W H'FFFF H'FFFE4226 16 Timer buffer operation transfer TBTM_3 mode register_3 R/W H'00 H'FFFE4238 8 Timer control register_4 TCR_4 R/W H'00 H'FFFE4201 8 Timer mode register_4 TMDR_4 R/W H'00 H'FFFE4203 8 Timer I/O control register H_4 TIORH_4 R/W H'00 H'FFFE4206 8 Timer I/O control register L_4 TIORL_4 R/W H'00 H'FFFE4207 8 Page 482 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Channel Register Name Abbreviation R/W Initial value Address Access Size 4 Timer interrupt enable register_4 TIER_4 R/W H'00 H'FFFE4209 8 Timer status register_4 TSR_4 R/W H'C0 H'FFFE422D 8 Timer counter_4 TCNT_4 R/W H'0000 H'FFFE4212 Timer general register A_4 TGRA_4 R/W H'FFFF H'FFFE421C 16 Timer general register B_4 TGRB_4 R/W H'FFFF H'FFFE421E 16 Timer general register C_4 TGRC_4 R/W H'FFFF H'FFFE4228 Timer general register D_4 TGRD_4 R/W H'FFFF H'FFFE422A 16 Timer buffer operation transfer TBTM_4 mode register_4 R/W H'00 H'FFFE4239 8 Timer A/D converter start request control register TADCR R/W H'0000 H'FFFE4240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 R/W H'FFFF H'FFFE4244 16 Timer A/D converter start request cycle set register B_4 TADCORB_4 R/W H'FFFF H'FFFE4246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 R/W H'FFFF H'FFFE4248 16 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 R/W H'FFFF H'FFFE424A 16 TSTR R/W H'00 H'FFFE4280 8 Timer synchronous register TSYR R/W H'00 H'FFFE4281 8 Timer read/write enable register TRWER R/W H'01 H'FFFE4284 8 Common Timer start register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 16 16 Page 483 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Channel Register Name Initial value Address Access Size R/W H'C0 H'FFFE420A 8 R/W H'00 H'FFFE420E 8 8 Abbreviation R/W Common Timer output master enable TOER to 3 and register 4 Timer output control register 1 TOCR1 Timer output control register 2 TOCR2 R/W H'00 H'FFFE420F Timer gate control register TGCR R/W H80 H'FFFE420D 8 Timer cycle data register TCDR R/W H'FFFF H'FFFE4214 16 Timer dead time data register TDDR R/W H'FFFF H'FFFE4216 16 Timer subcounter TCNTS R H'0000 H'FFFE4220 16 Timer cycle buffer register TCBR R/W H'FFFF H'FFFE4222 16 Timer interrupt skipping set register TITCR R/W H'00 H'FFFE4230 8 Timer interrupt skipping counter TITCNT R H'00 H'FFFE4231 8 Timer buffer transfer set register TBTER R/W H'00 H'FFFE4232 8 Timer dead time enable register TDER R/W H'01 H'FFFE4234 8 Timer waveform control register TWCR R/W H'00 H'FFFE4260 8 Timer output level buffer register TOLBR R/W H'00 H'FFFE4236 8 Page 484 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.3.1 Section 12 Multi-Function Timer Pulse Unit 2 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. This module has a total of five TCR registers, one each for channels 0 to 4. TCR register settings should be conducted only when TCNT operation is stopped. Bit: 7 6 5 CCLR[2:0] Initial value: 0 R/W: R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 5 CCLR[2:0] 000 R/W 4 3 2 CKEG[1:0] 0 R/W 0 R/W 0 R/W 1 0 TPSC[2:0] 0 R/W 0 R/W 0 R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 12.4 and 12.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P0/4 both edges = P0/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P0/4 or slower. When P0/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 12.6 to 12.9 for details. [Legend] x: Don't care R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 485 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3, 4 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input capture*2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 12.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Bit 6 Reserved*2 CCLR1 Bit 5 CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Page 486 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.6 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on P0/1 1 Internal clock: counts on P0/4 0 Internal clock: counts on P0/16 1 Internal clock: counts on P0/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input Table 12.7 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on P0/1 1 Internal clock: counts on P0/4 0 Internal clock: counts on P0/16 1 Internal clock: counts on P0/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 Internal clock: counts on P0/256 1 Counts on TCNT_2 overflow/underflow 1 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 487 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.8 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on P0/1 1 Internal clock: counts on P0/4 0 Internal clock: counts on P0/16 1 Internal clock: counts on P0/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on P0/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 12.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3, 4 0 0 0 Internal clock: counts on P0/1 1 Internal clock: counts on P0/4 0 Internal clock: counts on P0/16 1 Internal clock: counts on P0/64 0 Internal clock: counts on P0/256 1 Internal clock: counts on P0/1024 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 Page 488 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.3.2 Section 12 Multi-Function Timer Pulse Unit 2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. This module has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: Initial value: R/W: 7 6 5 4 - BFE BFB BFA 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7  0 R 3 2 1 0 MD[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 6 BFE 0 R/W Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. TGRF compare match is generated when TGRF is used as the buffer register. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 489 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated in a mode other than complementary PWM. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated in a mode other than complementary PWM. TGRC compare match is generated when in complementary PWM mode. When compare match for channel 4 occurs during the Tb period in complementary PWM mode, TGFC is set. Therefore, set the TGIEC bit in the timer interrupt enable register 4 (TIER_4) to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 12.10 for details. Page 490 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.10 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Setting prohibited 0 PWM mode 1 1 PWM mode 2*1 0 Phase counting mode 1*2 1 Phase counting mode 2*2 0 Phase counting mode 3*2 1 Phase counting mode 4*2 0 Reset synchronous PWM mode*3 1 Setting prohibited 1 X Setting prohibited 0 0 Setting prohibited 1 Complementary PWM mode 1 (transmit at crest)*3 0 Complementary PWM mode 2 (transmit at trough)*3 1 Complementary PWM mode 2 (transmit at crest and trough)*3 1 1 0 1 1 0 1 0 1 [Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 491 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. This module has a total of eight TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2. TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.  TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: 7 6 5 4 3 IOB[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 2 1 0 IOA[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4 IOB[3:0] 0000 R/W I/O Control B0 to B3 0 R/W 0 R/W Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: 3 to 0 IOA[3:0] 0000 R/W Table 12.11 Table 12.13 Table 12.14 Table 12.15 Table 12.17 I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Page 492 of 3092 Table 12.19 Table 12.21 Table 12.22 Table 12.23 Table 12.25 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  TIORL_0, TIORL_3, TIORL_4 Bit: 7 6 5 4 3 IOD[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 2 1 0 IOC[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3 0 R/W 0 R/W Specify the function of TGRD. See the following tables. TIORL_0: Table 12.12 TIORL_3: Table 12.16 TIORL_4: Table 12.18 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 12.20 TIORL_3: Table 12.24 TIORL_4: Table 12.26 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 493 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.11 TIORH_0 (Channel 0) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 Output compare register 1 1 0 TIOC0B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 494 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.12 TIORL_0 (Channel 0) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC0D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register*2 Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 495 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.13 TIOR_1 (Channel 1) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 Output compare register 1 1 0 TIOC1B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 496 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.14 TIOR_2 (Channel 2) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 Output compare register 1 1 0 TIOC2B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 497 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.15 TIORH_3 (Channel 3) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_3 Function 0 0 0 0 Output compare register 1 1 0 TIOC3B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 498 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.16 TIORL_3 (Channel 3) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_3 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC3D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register*2 Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 499 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.17 TIORH_4 (Channel 4) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_4 Function 0 0 0 0 Output compare register 1 1 0 TIOC4B Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 500 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.18 TIORL_4 (Channel 4) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_4 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC4D Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register*2 Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 501 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.19 TIORH_0 (Channel 0) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 Output compare register 1 1 0 TIOC0A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 502 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.20 TIORL_0 (Channel 0) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC0C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register*2 Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 503 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.21 TIOR_1 (Channel 1) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 Output compare register 1 1 0 TIOC1A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 504 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.22 TIOR_2 (Channel 2) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 Output compare register 1 1 0 TIOC2A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 505 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.23 TIORH_3 (Channel 3) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_3 Function 0 0 0 0 Output compare register 1 1 0 TIOC3A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 506 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.24 TIORL_3 (Channel 3) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_3 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC3C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register*2 Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 507 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.25 TIORH_4 (Channel 4) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_4 Function 0 0 0 0 Output compare register 1 1 0 TIOC4A Pin Function Output retained* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 508 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.26 TIORL_4 (Channel 4) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_4 Function 0 0 0 0 Output compare 2 register* 1 1 0 TIOC4C Pin Function Output retained*1 Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register*2 Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 509 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. This module has six TIER registers, two for channel 0 and one each for channels 1 to 4.  TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 Bit: 7 6 5 4 3 2 1 0 TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 TTGE 0 R/W A/D Converter Start Request Enable Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled 6 TTGE2 0 R/W A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled Page 510 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 511 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  TIER2_0 Bit: 7 6 5 4 3 2 TTGE2 - - - - - 0 R 0 R 0 R 0 R 0 R Initial value: 0 R/W: R/W 1 0 TGIEF TGIEE 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 TTGE2 0 R/W A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGIEF 0 R/W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled 0 TGIEE 0 R/W TGR Interrupt Enable E Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled Page 512 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.3.5 Section 12 Multi-Function Timer Pulse Unit 2 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. This module has six TSR registers, two for channel 0 and one each for channels 1 to 4.  TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TCFD - TCFU TCFV TGFD TGFC TGFB TGFA 1 R 1 R 0 0 0 0 0 0 R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6  1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 R/(W)*1 Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]  When 0 is written to TCFU after reading TCFU = 1*2 [Setting condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When the TCNT value underflows (changes from H'0000 to H'FFFF) Page 513 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit 4 Bit Name TCFV Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Clearing condition]  When 0 is written to TCFV after reading TCFV = 1*2 [Setting condition]  3 TGFD 0 When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. R/(W)*1 Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]  When 0 is written to TGFD after reading TGFD = 1*2 [Setting conditions] Page 514 of 3092  When TCNT = TGRD and TGRD is functioning as output compare register  When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 2 Bit Name TGFC Initial Value 0 Section 12 Multi-Function Timer Pulse Unit 2 R/W Description 1 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]  When 0 is written to TGFC after reading TGFC = 1*2 [Setting conditions] 1 TGFB 0  When TCNT = TGRC and TGRC is functioning as output compare register  When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register 1 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Clearing condition]  When 0 is written to TGFB after reading TGFB = 1*2 [Setting conditions] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  When TCNT = TGRB and TGRB is functioning as output compare register  When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register Page 515 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit 0 Bit Name TGFA Initial Value 0 R/W Description 1 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Clearing conditions]  When the direct memory access controller is activated by TGIA interrupt  When 0 is written to TGFA after reading TGFA = 1*2 [Setting conditions]  When TCNT = TGRA and TGRA is functioning as output compare register  When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag. 2. If the next flag is set before TGFA is cleared to 0 after reading TGFA = 1, TGFA remains 1 even when 0 is written to. In this case, read TGFA = 1 again to clear TGFA to 0. Page 516 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  TSR2_0 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - TGFF TGFE 1 R 1 R 0 R 0 R 0 R 0 R 0 0 R/(W)*1 R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGFF 0 R/(W)*1 Compare Match Flag F Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Clearing condition]  When 0 is written to TGFF after reading TGFF = 1*2 [Setting condition]  0 TGFE 0 When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register R/(W)*1 Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Clearing condition]  When 0 is written to TGFE after reading TGFE = 1*2 [Setting condition]  When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag. 2. If the next flag is set before TGFA is cleared to 0 after reading TGFA = 1, TGFA remains 1 even when 0 is written to. In this case, read TGFA = 1 again to clear TGFA to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 517 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.6 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. This module has three TBTM registers, one each for channels 0, 3, and 4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - TTSE TTSB TTSA 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 3  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 2 TTSE 0 R/W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared 1 TTSB 0 R/W Timing Select B Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel 0 TTSA 0 R/W Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel Page 518 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.3.7 Section 12 Multi-Function Timer Pulse Unit 2 Timer Input Capture Control Register (TICCR) TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. This module has one TICCR in channel 1. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - I2BE I2AE I1BE I1AE 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 4  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 3 I2BE 0 R/W Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions 2 I2AE 0 R/W Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions 1 I1BE 0 R/W Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 519 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 0 I1AE 0 R/W Input Capture Enable Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions Page 520 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.3.8 Section 12 Multi-Function Timer Pulse Unit 2 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. This module has one TADCR in channel 4. Bit: 15 14 BF[1:0] Initial value: 0 R/W: R/W 0 R/W 13 12 11 10 9 8 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE 0 R/W 0* R/W 0 R/W 0* R/W 0* R/W 0* R/W 0* R/W 0* R/W Note: * Do not set to 1 when complementary PWM mode is not selected. Bit Bit Name Initial Value R/W Description 15, 14 BF[1:0] 00 R/W TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 12.27. 13 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 UT4AE 0 R/W Up-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation 6 DT4AE 0* R/W Down-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 521 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 5 UT4BE 0 R/W Up-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation 4 DT4BE 0* R/W Down-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation 3 ITA3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping 2 ITA4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping 1 ITB3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping Page 522 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 0 ITB4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 12.27 Setting of Transfer Timing by Bits BF1 and BF0 Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.*1 1 0 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.*2 1 1 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.*2 Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 523 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.9 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. 12.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. Page 524 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.11 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. This module has five TCNT counters, one each for channels 0 to 4. The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. Bit: 15 Initial value: 0 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. 12.3.12 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. This module has eighteen TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 525 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.13 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit: 7 6 5 4 3 2 1 0 CST4 CST3 - - - CST2 CST1 CST0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 CST4 0 R/W Counter Start 4 and 3 R/W These bits select operation or stoppage for TCNT. 6 CST3 0 Description If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 CST2 0 R/W Counter Start 2 to 0 1 CST1 0 R/W These bits select operation or stoppage for TCNT. 0 CST0 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation Page 526 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.14 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: 7 6 SYNC4 SYNC3 Initial value: 0 R/W: R/W 0 R/W 5 4 3 - - - 0 R 0 R 0 R 2 1 0 SYNC2 SYNC1 SYNC0 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 SYNC4 0 R/W Timer Synchronous operation 4 and 3 6 SYNC3 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 527 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 2 SYNC2 0 R/W Timer Synchronous operation 2 to 0 1 SYNC1 0 R/W 0 SYNC0 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Page 528 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.15 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - RWE 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W Bit Bit Name Initial Value R/W 7 to 1  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RWE 1 R/W Read/Write Enable Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition]  When 0 is written to the RWE bit after reading RWE = 1  Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT_4. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 529 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.16 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Set TOER when count operation of TCNT channels 3 and 4 is halted. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - OE4D OE4C OE3D OE4B OE4A OE3B 1 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled Page 530 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 0 OE3B 0 R/W Master Enable TIOC3B This bit enables/disables the TIOC3B pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 12.3.17, Timer Output Control Register 1 (TOCR1), and section 12.3.18, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable output for this module in other than complementary PWM or reset-synchronized PWM mode. When these bits are set to 0, low level is output. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 531 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.17 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - PSYE - - TOCL TOCS OLSN OLSP 0 R 0 R/W 0 R 0 R 0 0 R/(W)*3 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W 7  0 R Description Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 532 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 3 Bit Name TOCL Initial value 0 Section 12 Multi-Function Timer Pulse Unit 2 R/W Description 3 R/(W)* TOC Register Write Protection*1 This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled 2 TOCS 0 R/W TOC Select This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected 1 OLSN 0 R/W Output Level Select N*2*4 This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 12.28. 0 OLSP 0 R/W Output Level Select P*2 This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 12.29. Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 2. Clearing the TOCS0 bit to 0 makes this bit setting valid. 3. After power-on reset, 1 can be written only once. After 1 has been written, 0 cannot be written. 4. If there is no dead time, the reverse phase output is the inversion of the forward phase. Set OLSP and OLSN to the same value. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 533 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.28 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count 0 1 High level Low level High level Low level Low level High level Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Table 12.29 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3, and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Time Positive phase output Initial output Reverse phase output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Figure 12.2 Complementary PWM Mode Output Level Example Page 534 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.18 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 6 BF[1:0] Initial value: 0 R/W: R/W 0 R/W 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7, 6 BF[1:0] 00 R/W TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 12.30. 5 OLS3N 0 R/W Output Level Select 3N* This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode. See table 12.31. 4 OLS3P 0 R/W Output Level Select 3P* This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode. See table 12.32. 3 OLS2N 0 R/W Output Level Select 2N* This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode. See table 12.33. 2 OLS2P 0 R/W Output Level Select 2P* This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode. See table 12.34. 1 OLS1N 0 R/W Output Level Select 1N* This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode. See table 12.35. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 535 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial value R/W Description 0 OLS1P 0 R/W Output Level Select 1P* This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode. See table 12.36. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. If there is no dead time, the reverse phase output is the inversion of the forward phase. Set OLSiP and OLSiN to the same value (i = 1, 2, or 3). Table 12.30 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description BF1 BF0 Complementary PWM Mode 0 0 Does not transfer data from the Does not transfer data from the buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2. 0 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared 1 0 Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Setting prohibited 1 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Setting prohibited Reset-Synchronized PWM Mode Table 12.31 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Page 536 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.32 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level Up Count 0 1 High level Low level Low level High level Low level High level High level Low level Down Count Table 12.33 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 12.34 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Table 12.35 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 537 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.36 TIOC4B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count 0 1 High level Low level Low level High level Low level High level High level Low level Down Count 12.3.19 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7 6 - - 0 R 0 R 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7, 6  All 0 R Reserved 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 5 OLS3N 0 R/W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2. 4 OLS3P 0 R/W Specifies the buffer value to be transferred to the OLS3P bit in TOCR2. 3 OLS2N 0 R/W Specifies the buffer value to be transferred to the OLS2N bit in TOCR2. 2 OLS2P 0 R/W Specifies the buffer value to be transferred to the OLS2P bit in TOCR2. 1 OLS1N 0 R/W Specifies the buffer value to be transferred to the OLS1N bit in TOCR2. 0 OLS1P 0 R/W Specifies the buffer value to be transferred to the OLS1P bit in TOCR2. Page 538 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Figure 12.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [1] [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. Set TOCR2 [2] [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Set TOLBR [3] Figure 12.3 PWM Output Level Setting Procedure in Buffer Operation 12.3.20 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - BDC N P FB WF VF UF 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W 7  1 R Description Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 539 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial value R/W Description 5 N 0 R/W Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with channel-0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (setting values of UF, VF, and WF in TGCR). 2 WF 0 R/W Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 12.37. 1 VF 0 R/W 0 UF 0 R/W Page 540 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.37 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D WF VF UF U Phase V Phase W Phase U Phase V Phase W Phase 0 0 1 1 0 1 0 OFF OFF OFF OFF OFF OFF 1 ON OFF OFF OFF OFF ON 0 OFF ON OFF ON OFF OFF 1 OFF ON OFF OFF OFF ON 0 OFF OFF ON OFF ON OFF 1 ON OFF OFF OFF ON OFF 0 OFF OFF ON ON OFF OFF 1 OFF OFF OFF OFF OFF OFF 12.3.21 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 541 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.22 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 12.3.23 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value (a value of two times TDDR + 3 or greater) as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. Page 542 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.24 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 12.3.25 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. This module has one TITCR. Bit: 7 6 T3AEN Initial value: 0 R/W: R/W 5 4 3ACOR[2:0] 0 R/W 0 R/W 3 2 T4VEN 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 T3AEN 0 R/W T3AEN 1 0 4VCOR[2:0] 0 R/W 0 R/W 0 R/W Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 12.38. 3 T4VEN 0 R/W T4VEN Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 543 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Initial value Bit Bit Name 2 to 0 4VCOR[2:0] 000 R/W Description R/W These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 12.39. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TICNT). Table 12.38 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description 0 0 0 Does not skip TGIA_3 interrupts. 0 0 1 Sets the TGIA_3 interrupt skipping count to 1. 0 1 0 Sets the TGIA_3 interrupt skipping count to 2. 0 1 1 Sets the TGIA_3 interrupt skipping count to 3. 1 0 0 Sets the TGIA_3 interrupt skipping count to 4. 1 0 1 Sets the TGIA_3 interrupt skipping count to 5. 1 1 0 Sets the TGIA_3 interrupt skipping count to 6. 1 1 1 Sets the TGIA_3 interrupt skipping count to 7. Table 12.39 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 Bit 1 Bit 0 4VCOR2 4VCOR1 4VCOR0 Description 0 0 0 Does not skip TCIV_4 interrupts. 0 0 1 Sets the TCIV_4 interrupt skipping count to 1. 0 1 0 Sets the TCIV_4 interrupt skipping count to 2. 0 1 1 Sets the TCIV_4 interrupt skipping count to 3. 1 0 0 Sets the TCIV_4 interrupt skipping count to 4. 1 0 1 Sets the TCIV_4 interrupt skipping count to 5. 1 1 0 Sets the TCIV_4 interrupt skipping count to 6. 1 1 1 Sets the TCIV_4 interrupt skipping count to 7. Page 544 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.26 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. This module has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: 7 6 - Initial value: R/W: 5 4 3ACNT[2:0] 0 R Bit Bit Name Initial Value R/W 7  0 R 0 R 0 R 3 2 - 0 R 0 R 1 0 4VCNT[2:0] 0 R 0 R 0 R Description Reserved This bit is always read as 0. 6 to 4 3ACNT[2:0] 000 R TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions] 3  0 R  When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR  When the T3AEN bit in TITCR is cleared to 0  When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 Reserved This bit is always read as 0. 2 to 0 4VCNT[2:0] 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions]  When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR  When the T4VEN bit in TITCR is cleared to 0  When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Note: To clear the TITCNT, clear the bits T3AEN and T4VEN in TITCR to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 545 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.27 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. This module has one TBTER. Bit: Initial value: R/W: 7 6 5 4 3 2 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 2  All 0 R 1 0 BTE[1:0] 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 12.40. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR Page 546 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.40 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description 0 0 Enables transfer from the buffer registers to the temporary registers*1 and does not link the transfer with interrupt skipping operation. 0 1 Disables transfer from the buffer registers to the temporary registers. 1 0 Links transfer from the buffer registers to the temporary registers with interrupt skipping operation.*2 1 1 Setting prohibited Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 12.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 547 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.28 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. This module has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - TDER 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W) Bit Bit Name Initial Value R/W 7 to 1  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TDER 1 R/(W) Dead Time Enable Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition]  Note: * When 0 is written to TDER after reading TDER = 1 TDDR must be set to 1 or a larger value. Page 548 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.3.29 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: 7 6 5 4 3 2 1 0 CCE - - - - - - WRE 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W) Initial value: 0* R/W: R/(W) Note: * Do not set to 1 when complementary PWM mode is not selected. Bit Bit Name Initial Value R/W Description 7 CCE 0* R/(W) Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition]  6 to 1  All 0 R When 1 is written to CCE after reading CCE = 0 Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 549 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 0 WRE 0 R/(W) Initial Output Suppression Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The initial output is suppressed only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 12.40. 0: Outputs the initial value specified in TOCR 1: Suppresses initial output [Setting condition]  Note: * When 1 is written to WRE after reading WRE = 0 Do not set to 1 when complementary PWM mode is not selected. 12.3.30 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. Page 550 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.4 Operation 12.4.1 Basic Functions Section 12 Multi-Function Timer Pulse Unit 2 Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select functions for external pins of this module using the general I/O ports. (1) Counter Operation When one of bits CST0 to CST4 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure Figure 12.4 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Operation selection Select counter clock [1] Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Free-running counter Periodic counter [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 12.4 Example of Counter Operation Setting Procedure R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 551 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (b) SH7268 Group, SH7269 Group Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the TCNT counters of this module are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, this module requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 12.5 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 12.5 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, this module requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Page 552 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Figure 12.6 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 12.6 Periodic Counter Operation (2) Waveform Output by Compare Match This module can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match Figure 12.7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Start count operation [3] [3] Set the CST bit in TSTR to 1 to start the count operation. Figure 12.7 Example of Setting Procedure for Waveform Output by Compare Match R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 553 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (b) Examples of Waveform Output Operation: Figure 12.8 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB 0 output No change Figure 12.8 Example of 0 Output/1 Output Operation Figure 12.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 12.9 Example of Toggle Output Operation Page 554 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 12 Multi-Function Timer Pulse Unit 2 Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, P0/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P0/1 is selected. (a) Example of Input Capture Operation Setting Procedure Figure 12.10 shows an example of the input capture operation setting procedure. Input selection Select input capture input [1] [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 12.10 Example of Input Capture Operation Setting Procedure R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 555 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (b) Example of Input Capture Operation Figure 12.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 12.11 Example of Input Capture Operation Page 556 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.4.2 Section 12 Multi-Function Timer Pulse Unit 2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 12.12 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 12.12 Example of Synchronous Operation Setting Procedure R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 557 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (2) Example of Synchronous Operation Figure 12.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 12.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOC0A TIOC1A TIOC2A Figure 12.13 Example of Synchronous Operation Page 558 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.4.3 Section 12 Multi-Function Timer Pulse Unit 2 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 12.41 shows the register combinations used in buffer operation. Table 12.41 Register Combinations in Buffer Operation Channel 0 3 4 Timer General Register Buffer Register TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRE_0 TGRF_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 TGRA_4 TGRC_4 TGRB_4 TGRD_4  When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 12.14. Compare match signal Buffer register Timer general register Comparator TCNT Figure 12.14 Compare Match Buffer Operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 559 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 12.15. Input capture signal Buffer register Timer general register TCNT Figure 12.15 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 12.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation Select TGR function [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Start count [3] Figure 12.16 Example of Buffer Operation Setting Procedure Page 560 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (2) Examples of Buffer Operation (a) When TGR is an output compare register Figure 12.17 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. In this example, the TTSA bit in TBTM is cleared to 0. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 12.4.5, PWM Modes. TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 TGRC_0 H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 12.17 Example of Buffer Operation (1) (b) When TGR is an input capture register Figure 12.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 561 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 12.18 Example of Buffer Operation (2) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer timing is one of the following cases.  When TCNT overflows (H'FFFF to H'0000)  When H'0000 is written to TCNT during counting  When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note: TBTM must be modified only while TCNT stops. Figure 12.19 shows an operation example in which PWM mode 1 is designated for channel 0 and buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. The TTSA bit in TBTM_0 is set to 1. Page 562 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCNT_0 value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 H'0000 TGRC_0 Time H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 H'0520 TIOCA Figure 12.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing 12.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 12.42 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 12.42 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). The edge detection that is the condition for input capture uses a signal representing the logical OR of the original input pin and the added input pins. For details, see (4) Cascaded Operation Example (c). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 563 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 For input capture in cascade connection, refer to section 12.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection. Table 12.43 shows the TICCR setting and input capture input pins. Table 12.43 TICCR Setting and Input Capture Input Pins Target Input Capture TICCR Setting Input Capture Input Pins Input capture from TCNT_1 to TGRA_1 I2AE bit = 0 (initial value) TIOC1A I2AE bit = 1 TIOC1A, TIOC2A Input capture from TCNT_1 to TGRB_1 I2BE bit = 0 (initial value) TIOC1B I2BE bit = 1 TIOC1B, TIOC2B Input capture from TCNT_2 to TGRA_2 I1AE bit = 0 (initial value) TIOC2A I1AE bit = 1 TIOC2A, TIOC1A Input capture from TCNT_2 to TGRB_2 I1BE bit = 0 (initial value) TIOC2B I1BE bit = 1 TIOC2B, TIOC1B (1) Example of Cascaded Operation Setting Procedure Figure 12.20 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'111 to select TCNT_2 overflow/ underflow counting. Cascaded operation Set cascading [1] Start count [2] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 12.20 Cascaded Operation Setting Procedure (2) Cascaded Operation Example (a) Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. Page 564 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0000 TCNT_1 0001 0002 0001 0001 0000 FFFF 0000 Figure 12.21 Cascaded Operation Example (a) (3) Cascaded Operation Example (b) Figure 12.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used. TCNT_2 value H'FFFF H'C256 H'6128 H'0000 Time H'0512 TCNT_1 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 H'0512 TGRA_2 H'0513 H'C256 As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing. Figure 12.22 Cascaded Operation Example (b) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 565 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (4) Cascaded Operation Example (c) Figure 12.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'FFFF H'C256 H'9192 H'6128 H'2064 H'0000 TCNT_1 Time H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 H'0512 TGRA_2 H'6128 H'0513 H'2064 H'0514 H'C256 H'9192 When one of the input pin signals is high-level, the edge of the other input pin signal cannot be the input capture condition. Figure 12.23 Cascaded Operation Example (c) Page 566 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 12 Multi-Function Timer Pulse Unit 2 Cascaded Operation Example (d) Figure 12.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1. TCNT_0 value Compare match between TCNT_0 and TGRA_0 TGRA_0 Time H'0000 TCNT_2 value H'FFFF H'D000 H'0000 Time H'0512 TCNT_1 H'0513 TIOC1A TIOC2A TGRA_1 H'0513 TGRA_2 H'D000 Figure 12.24 Cascaded Operation Example (d) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 567 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 12.4.5 SH7268 Group, SH7269 Group PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.  PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.  PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 12.44. Page 568 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Table 12.44 PWM Output Registers and Output Pins Output Pins Channel 0 Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOC0A TIOC0A TGRB_0 TGRC_0 TIOC0B TIOC0C TGRD_0 1 TGRA_1 TIOC0D TIOC1A TGRB_1 2 TGRA_2 TGRA_3 TIOC2A TIOC3A TGRA_4 TIOC3C TGRD_4 Cannot be set Cannot be set TIOC4A TGRB_4 TGRC_4 Cannot be set Cannot be set TGRD_3 4 TIOC2A TIOC2B TGRB_3 TGRC_3 TIOC1A TIOC1B TGRB_2 3 TIOC0C Cannot be set Cannot be set TIOC4C Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 569 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (1) Example of PWM Mode Setting Procedure Figure 12.25 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] Start count [6] Figure 12.25 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 12.26 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. Page 570 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group TCNT value Section 12 Multi-Function Timer Pulse Unit 2 Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 12.26 Example of PWM Mode Operation (1) Figure 12.27 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 12.27 Example of PWM Mode Operation (2) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 571 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Figure 12.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 TIOCA 100% duty 0% duty Figure 12.28 Example of PWM Mode Operation (3) Page 572 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.4.6 Section 12 Multi-Function Timer Pulse Unit 2 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 12.45 shows the correspondence between external clock pins and channels. Table 12.45 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 12.29 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. Phase counting mode Select phase counting mode [1] Start count [2] [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 12.29 Example of Phase Counting Mode Setting Procedure R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 573 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (2) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 12.30 shows an example of phase counting mode 1 operation, and table 12.46 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.30 Example of Phase Counting Mode 1 Operation Table 12.46 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Page 574 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 12 Multi-Function Timer Pulse Unit 2 Phase counting mode 2 Figure 12.31 shows an example of phase counting mode 2 operation, and table 12.47 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.31 Example of Phase Counting Mode 2 Operation Table 12.47 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care High level Don't care Low level Down-count [Legend] : Rising edge : Falling edge R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 575 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (c) Phase counting mode 3 Figure 12.32 shows an example of phase counting mode 3 operation, and table 12.48 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.32 Example of Phase Counting Mode 3 Operation Table 12.48 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Page 576 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (d) Section 12 Multi-Function Timer Pulse Unit 2 Phase counting mode 4 Figure 12.33 shows an example of phase counting mode 4 operation, and table 12.49 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.33 Example of Phase Counting Mode 4 Operation Table 12.49 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level Don't care High level High level Down-count Low level High level Don't care Low level [Legend] : Rising edge : Falling edge R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 577 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (3) SH7268 Group, SH7269 Group Phase Counting Mode Application Example Figure 12.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Page 578 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 TGRA_0 (speed control period) + - TGRC_0 (position control period) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 12.34 Phase Counting Mode Application Example R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 579 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 12.4.7 SH7268 Group, SH7269 Group Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT_3 functions as an upcounter. Table 12.50 shows the PWM output pins used. Table 12.51 shows the settings of the registers. Table 12.50 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description 3 TIOC3B PWM output pin 1 TIOC3D PWM output pin 1' (negative-phase waveform of PWM output 1) 4 TIOC4A PWM output pin 2 TIOC4C PWM output pin 2' (negative-phase waveform of PWM output 2) TIOC4B PWM output pin 3 TIOC4D PWM output pin 3' (negative-phase waveform of PWM output 3) Table 12.51 Register Settings for Reset-Synchronized PWM Mode Register Description of Setting TCNT_3 Initial setting of H'0000 TCNT_4 Initial setting of H'0000 TGRA_3 Set count cycle for TCNT_3 TGRB_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins TGRA_4 Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins TGRB_4 Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Page 580 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 12 Multi-Function Timer Pulse Unit 2 Procedure for Selecting the Reset-Synchronized PWM Mode Figure 12.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. Reset-synchronized PWM mode Stop counting [1] [2] Set bits TPSC2-TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2-CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. Select counter clock and counter clear source [2] Brushless DC motor control setting [3] Set TCNT [4] Set TGR [5] PWM cycle output enabling, PWM output level setting [6] Set reset-synchronized PWM mode [7] Enable waveform output [8] PFC setting [9] [7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. Start count operation [10] [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. Reset-synchronized PWM mode [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X ≤ TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 11.3. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Figure 12.35 Procedure for Selecting Reset-Synchronized PWM Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 581 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (2) SH7268 Group, SH7269 Group Reset-Synchronized PWM Mode Operation Figure 12.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 comparematch occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT_3 and TCNT_4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 12.36 Reset-Synchronized PWM Mode Operation Example (When TOCR’s OLSN = 1 and OLSP = 1) Page 582 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.4.8 Section 12 Multi-Function Timer Pulse Unit 2 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval are also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 12.52 shows the PWM output pins used. Table 12.53 shows the settings of the registers used. Table 12.52 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOC3A Toggle output synchronized with PWM period (or I/O port) TIOC3B PWM output pin 1 TIOC3C I/O port* TIOC3D PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) TIOC4A PWM output pin 2 TIOC4B PWM output pin 3 TIOC4C PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) TIOC4D PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) 4 Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 583 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group Table 12.53 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU 3 TCNT_3 Start of up-count from value set in dead time register Maskable by TRWER setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting* TGRB_3 PWM output 1 compare register Maskable by TRWER setting* TGRC_3 TGRA_3 buffer register Always readable/writable TGRD_3 PWM output 1/TGRB_3 buffer register Always readable/writable TCNT_4 Up-count start, initialized to H'0000 Maskable by TRWER setting* TGRA_4 PWM output 2 compare register Maskable by TRWER setting* TGRB_4 PWM output 3 compare register Maskable by TRWER setting* TGRC_4 PWM output 2/TGRA_4 buffer register Always readable/writable TGRD_4 PWM output 3/TGRB_4 buffer register Always readable/writable Timer dead time data register (TDDR) Set TCNT_4 and TCNT_3 offset value (dead time value) Maskable by TRWER setting* Timer cycle data register (TCDR) Set TCNT_4 upper limit value (1/2 carrier cycle) Maskable by TRWER setting* Timer cycle buffer register (TCBR) TCDR buffer register Always readable/writable Subcounter (TCNTS) Subcounter for dead time generation Read-only Temporary register 1 (TEMP1) PWM output 1/TGRB_3 temporary register Not readable/writable Temporary register 2 (TEMP2) PWM output 2/TGRA_4 temporary register Not readable/writable Temporary register 3 (TEMP3) PWM output 3/TGRB_4 temporary register Not readable/writable 4 Note: * Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register). Page 584 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 12 Multi-Function Timer Pulse Unit 2 TDDR TGRC_3 TCBR TGRA_3 TCDR Comparator TCNT_3 Match signal TCNTS TCNT_4 PWM output 2 PWM output 3 PWM output 4 PWM output 6 TGRB_4 Temp 3 Match signal TGRA_4 TGRB_3 Temp 1 Temp 2 TGRC_4 PWM output 1 PWM output 5 Comparator TGRD_3 PWM cycle output Output controller TCNT_4 underflow interrupt TGRA_3 comparematch interrupt SH7268 Group, SH7269 Group TGRD_4 : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 12.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 585 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (1) Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 12.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. Complementary PWM mode Stop count operation [1] Counter clock, counter clear source selection [2] Brushless DC motor control setting [3] TCNT setting [4] [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2-CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. Inter-channel synchronization setting [5] TGR setting [6] Enable/disable dead time generation [7] Dead time, carrier cycle setting [8] PWM cycle output enabling, PWM output level setting [9] Complementary PWM mode setting [10] Enable waveform output [11] setting StartPFC count operation [12] [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the timer cycle data register (TCDR) and timer cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 11.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. Start count operation [13] [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Figure 12.38 Example of Complementary PWM Mode Setting Procedure Page 586 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 12 Multi-Function Timer Pulse Unit 2 Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 12.39 illustrates counter operation in complementary PWM mode, and figure 12.40 shows an example of complementary PWM mode operation. (a) Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT_3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT_4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT_4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 587 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group TCNT_3 TCNT_4 TCNTS Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TCNTS TDDR H'0000 Time Figure 12.39 Complementary PWM Mode Counter Operation (b) Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 12.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.40 shows an example in which the mode is selected in which the change is made in the trough. Page 588 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 In the tb interval (tb1 in figure 12.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS— and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 589 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 Ta Tb1 Ta Tb2 Ta TGRA_3 TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 H'6400 H'0080 Temporary register TEMP2 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 12.40 Example of Complementary PWM Mode Operation Page 590 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (c) Section 12 Multi-Function Timer Pulse Unit 2 Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 12.54 Registers and Counters Requiring Initialization Register/Counter Set Value TGRC_3 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER) TCBR 1/2 PWM carrier cycle TGRD_3, TGRC_4, TGRD_4 Initial PWM duty value for each phase TCNT_4 H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 591 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (d) SH7268 Group, SH7269 Group PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. (e) Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. (f) Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 12.41 shows an example of operation without dead time. Page 592 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Transfer from temporary register to compare register Transfer from temporary register to compare register Ta Tb1 Ta Tb2 Ta TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Temporary register TEMP2 Data1 Data2 Compare register TGRA_4 Data1 Data2 Output waveform Output waveform Output waveform is active-low. Figure 12.41 Example of Operation without Dead Time R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 593 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (g) PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value TCDR set value > two times TDDR + 2 Without dead time: TGRA_3 set value = TCDR set value + 1 TCDR set value > 4 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 12.42 illustrates the operation when the PWM cycle is updated at the crest. See (h) Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 12.42 Example of PWM Cycle Updating Page 594 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (h) Section 12 Multi-Function Timer Pulse Unit 2 Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 595 of 3092 Page 596 of 3092 GR Temp_R BR H'0000 TGRC_4 TGRA_4 TGRA_3 Counter value data1 data1 data1 Transfer from temporary register to compare register data2 data2 data2 Transfer from temporary register to compare register Data update timing: counter crest and trough data3 data3 Transfer from temporary register to compare register data3 data4 data4 Transfer from temporary register to compare register data4 data5 data5 Transfer from temporary register to compare register data6 data6 data6 Transfer from temporary register to compare register : Compare register : Buffer register Time Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group Figure 12.43 Example of Data Update in Complementary PWM Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (i) Section 12 Multi-Function Timer Pulse Unit 2 Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 12.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 12.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TGRA_4 TDDR Time Dead time Initial output Positive phase output Negative phase output Active level Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 12.44 Example of Initial Output in Complementary PWM Mode (1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 597 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGRA_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 12.45 Example of Initial Output in Complementary PWM Mode (2) Page 598 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (j) Section 12 Multi-Function Timer Pulse Unit 2 Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and compare register. While TCNTS is counting, compare register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 12.46 to 12.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a  b  c  d (or c  d  a'  b'), as shown in figure 12.46. If compare-matches deviate from the a  b  c  d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c  d  a'  b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 12.47, comparematch b is ignored, and the negative phase is turned on by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 12.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 599 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 T2 period T1 period T1 period TGRA_3 c d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 12.46 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGRA_3 c d TCDR a b a b TDDR H'0000 Positive phase Negative phase Figure 12.47 Example of Complementary PWM Mode Waveform Output (2) Page 600 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR a b TDDR c a' d b' H'0000 Positive phase Negative phase Figure 12.48 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period c TGRA_3 T1 period d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 12.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 601 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR a b a b TDDR H'0000 c d Positive phase Negative phase Figure 12.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period c TGRA_3 T1 period d TCDR a b TDDR H'0000 Positive phase Negative phase Figure 12.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Page 602 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 c b' Positive phase d a' Negative phase Figure 12.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 T2 period c ad T1 period b TCDR TDDR H'0000 Positive phase Negative phase Figure 12.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 603 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (k) Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 12.49 to 12.53 show output examples. 100% duty output is performed when the compare register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the compare register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. (l) Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 12.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT_4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 12.54 Example of Toggle Output Waveform Synchronized with PWM Output Page 604 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (m) Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 12.55 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TCNTS TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 12.55 Counter Clearing Synchronized with Another Channel R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 605 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (n) SH7268 Group, SH7269 Group Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 12.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 12.56) immediately after the counters start operation, initial value output is not suppressed. When using the initial output suppression function, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. If synchronous clearing occurs with the compare registers set to a value less than twice the setting of TDDR, the PWM output dead time may be too short (or nonexistent) or illegal active-level PWM negative-phase output may occur during the initial output suppression interval. For details, see section 12.7.23, Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode. Page 606 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Counter start Tb interval Tb interval Tb interval TGRA_3 TCNT_3 TCDR TGRB_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Figure 12.56 Timing for Synchronous Counter Clearing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 607 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 12.57. Output waveform control at synchronous counter clearing Stop count operation Set TWCR and complementary PWM mode [1] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [2] [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Start count operation [3] Output waveform control at synchronous counter clearing Figure 12.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Page 608 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 12.58 to 12.61 show examples of output waveform control in which this module operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 12.58 to 12.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 12.56, respectively. Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 12.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 12.56; Bit WRE of TWCR is 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 609 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 12.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 12.56; Bit WRE of TWCR is 1) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 12.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 12.56; Bit WRE of TWCR is 1) Page 610 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Bit WRE = 1 Synchronous clearing TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 12.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 12.56; Bit WRE of TWCR is 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 611 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (o) Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 12.62 illustrates an operation example. Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest) 2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to SYNC4 bits in the timer synchronous register (TSYR) to 1). 3. Do not set the PWM duty value to H'0000. 4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1. Counter cleared by TGRA_3 compare match TGRA_3 TCDR TGRB_3 TDDR H'0000 Output waveform Output waveform Output waveform is active-high. Figure 12.62 Example of Counter Clearing Operation by TGRA_3 Compare Match Page 612 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (p) Section 12 Multi-Function Timer Pulse Unit 2 Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 12.63 to 12.66 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with the general I/O ports). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 12.63 Example of Output Phase Switching by External Input (1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 613 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 External input SH7268 Group, SH7269 Group TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 12.64 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 12.65 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) Page 614 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group TGCR Section 12 Multi-Function Timer Pulse Unit 2 UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 12.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) (q) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 615 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (3) Interrupt Skipping in Complementary PWM Mode Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER). For the linkage with buffer registers, refer to description (c), Buffer Transfer Control Linked with Interrupt Skipping, below. A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in coordination with interrupt skipping by making settings in the timer A/D converter request control register (TADCR). For the linkage with the A/D converter start request delaying function, refer to section 12.4.9, A/D Converter Start Request Delaying Function. The setting of the timer interrupt skipping setting register (TITCR) must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. (a) Example of Interrupt Skipping Operation Setting Procedure Figure 12.67 shows an example of the interrupt skipping operation setting procedure. Figure 12.68 shows the periods during which interrupt skipping count can be changed. [1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register (TITCR) to 0 to clear the skipping counter. Interrupt skipping Clear interrupt skipping counter [1] Set skipping count and enable interrupt skipping [2] [2] Specify the interrupt skipping count within the range from 0 to 7 times in bits 3ACOR2 to 3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and enable interrupt skipping through bits T3AEN and T4VEN. Note: The setting of TITCR must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. Figure 12.67 Example of Interrupt Skipping Operation Setting Procedure Page 616 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCNT_3 TCNT_4 Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Figure 12.68 Periods during which Interrupt Skipping Count can be Changed (b) Example of Interrupt Skipping Operation Figure 12.69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR). Interrupt skipping period Interrupt skipping period TGIA_3 interrupt flag set signal Skipping counter 00 01 02 03 00 01 02 03 TGFA_3 flag Figure 12.69 Example of Interrupt Skipping Operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 617 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (c) SH7268 Group, SH7269 Group Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER). Figure 12.70 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the temporary register. Figure 12.71 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer register to the temporary register outside the buffer transfer-enabled period. Depending on the rewrite timing from the interrupt generation to the buffer register, there are two types of the transfer timing such as from the buffer register to the temporary register and from the temporary register to the general register. Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register (TITCR). Figure 12.72 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period. Note: This function must always be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never performed. Page 618 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCNT_3 TCNT_4 data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Buffer register Data1 Data2 (1) Temporary register (3) Data* Data2 (2) General register Data* Data2 Buffer transfer is suppressed [Legend] (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. Note: * When buffer transfer at the crest is selected. Figure 12.70 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 619 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (1)When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt TGIA_3 interrupt generation TGIA_3 interrupt generation TCNT_3 TCNT_4 Buffer register rewrite timing Buffer register rewrite timing Buffer transferenabled period TITCR[6:4] 2 TITCNT[6:4] 0 1 2 0 1 Buffer register Data Data1 Data2 Temporary register Data Data1 Data2 General register Data Data1 Data2 (2)When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt TGIA_3 interrupt generation TGIA_3 interrupt generation TCNT_3 TCNT_4 Buffer register rewrite timing Buffer transferenabled period TITCR[6:4] TITCNT[6:4] 2 0 1 2 0 1 Buffer register Data Data1 Temporary register Data Data1 General register Data Data1 Note: * The MD bits 3 to 0 = 1101 in TMDR_3, buffer transfer at the crest is selected. The skipping count is set to two. T3AEN and T4VEN are set to 1 and 0. Figure 12.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) Page 620 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Skipping counter 3ACNT 0 Skipping counter 4VCNT 1 0 2 1 3 2 0 3 1 0 2 1 3 2 0 3 Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) Note: * The MD bits 3 to 0 = 1111 in TMDR_3, buffer transfer at the crest and the trough is selected. The skipping count is set to three. T3AEN and T4VEN are set to 1. Figure 12.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period (4) Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection function. (a) Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following:  TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 621 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.4.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by setting the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR.  Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 12.73 shows an example of procedure for specifying the A/D converter start request delaying function. [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) A/D converter start request delaying function Set A/D converter start request cycle [1] • Set the timing of transfer from cycle set buffer register • Set linkage with interrupt skipping • Enable A/D converter start request delaying function A/D converter start request delaying function [2] [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register. • Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE. • Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. Figure 12.73 Example of Procedure for Specifying A/D Converter Start Request Delaying Function Page 622 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2  Basic Operation Example of A/D Converter Start Request Delaying Function Figure 12.74 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting. Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register TADCORA_4 TCNT_4 TADCOBRA_4 A/D converter start request (TRG4AN) (Complementary PWM mode) Figure 12.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation  Buffer Transfer The data in the timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D converter start request control register (TADCR_4).  A/D Converter Start Request Delaying Function Linked with Interrupt Skipping A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR). Figure 12.75 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up counting and down counting and A/D converter start requests are linked with interrupt skipping. Figure 12.76 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up counting and A/D converter start requests are linked with interrupt skipping. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 623 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 01 00 02 01 00 02 01 00 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * (UT4AE/DT4AE = 1) When the interrupt skipping count is set to two. Figure 12.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Page 624 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter 00 TCIV_4 interrupt skipping counter 01 00 02 01 00 02 01 00 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * UT4AE = 1 DT4AE = 0 When the interrupt skipping count is set to two. Figure 12.76 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 625 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 12.77 shows an example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). TGRA_4 Tdead Upper arm signal Lower arm signal Inverter output monitor signal Tdelay Dead time delay signal Up-count/down-count signal (udflg) TCNT[15:0] TGR[15:0] 3DE7 3E5B 3DE7 3ED3 3E5B 3ED3 3F37 3FAF 3F37 3FAF Figure 12.77 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation Page 626 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.5 Interrupt Sources 12.5.1 Interrupt Sources and Priorities Section 12 Multi-Function Timer Pulse Unit 2 This module has three kinds of interrupt sources; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 7, Interrupt Controller. Table 12.55 lists the interrupt sources of this module. Table 12.55 Interrupts of Multi-Function Timer Pulse Unit 2 Channel Name 0 TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible TGIB_0 TGRB_0 input capture/compare match TGFB_0 Not possible TGIC_0 TGRC_0 input capture/compare match TGFC_0 Not possible TGID_0 TGRD_0 input capture/compare match TGFD_0 Not possible TCIV_0 TCFV_0 Not possible TGIE_0 TGRE_0 compare match TGFE_0 Not possible TGIF_0 1 Interrupt Source Activation of Direct Memory Interrupt Access Flag Controller Priority TCNT_0 overflow TGRF_0 compare match High TGFF_0 Not possible TGIA_1 TGRA_1 input capture/compare match TGFA_1 Possible TGIB_1 TGRB_1 input capture/compare match TGFB_1 Not possible TCIV_1 TCNT_1 overflow TCFV_1 Not possible TCIU_1 TCNT_1 underflow TCFU_1 Not possible R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Low Page 627 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Channel Name 2 TGIA_2 TGRA_2 input capture/compare match TGFA_2 Possible TGIB_2 TGRB_2 input capture/compare match TGFB_2 Not possible TCIV_2 TCNT_2 overflow TCFV_2 Not possible TCIU_2 TCNT_2 underflow TCFU_2 Not possible TGIA_3 TGRA_3 input capture/compare match TGFA_3 Possible TGIB_3 TGRB_3 input capture/compare match TGFB_3 Not possible TGIC_3 TGRC_3 input capture/compare match TGFC_3 Not possible TGID_3 TGRD_3 input capture/compare match TGFD_3 Not possible TCIV_3 TCFV_3 Not possible TGIA_4 TGRA_4 input capture/compare match TGFA_4 Possible TGIB_4 TGRB_4 input capture/compare match TGFB_4 Not possible TGIC_4 TGRC_4 input capture/compare match TGFC_4 Not possible TGID_4 TGRD_4 input capture/compare match TGFD_4 Not possible TCIV_4 TCFV_4 Not possible 3 4 Interrupt Source Activation of Direct Memory Interrupt Access Flag Controller Priority TCNT_3 overflow TCNT_4 overflow/underflow High Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. This module has eighteen input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, and two each for channels 1 and 2. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. This module has five overflow interrupts, one for each channel. Page 628 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 12 Multi-Function Timer Pulse Unit 2 Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. This module has two underflow interrupts, one each for channels 1 and 2. 12.5.2 Activation of Direct Memory Access Controller The direct memory access controller can be activated by the TGRA input capture/compare match interrupt in each channel. For details, see section 11, Direct Memory Access Controller. In this module, a total of five TGRA input capture/compare match interrupts can be used as direct memory access controller activation sources, one each for channels 0 to 4. 12.5.3 A/D Converter Activation The A/D converter can be activated by one of the following three methods in this module. Table 12.56 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions.  When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1  When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from this module is selected as the trigger in the A/D converter, A/D conversion will start. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 629 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 (2) SH7268 Group, SH7269 Group A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0 The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from this module is selected as the trigger in the A/D converter, A/D conversion will start. (3) A/D Converter Activation by A/D Converter Start Request Delaying Function The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 12.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from this module is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from this module is selected as the trigger in the A/D converter when TRG4BN is generated. Table 12.56 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal TGRA_0 and TCNT_0 Input capture/compare match TRGAN TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4 TCNT_4 Trough in complementary PWM mode TGRE_0 and TCNT_0 Compare match TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 TRG4BN Page 630 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.6 Operation Timing 12.6.1 Input/Output Timing (1) Section 12 Multi-Function Timer Pulse Unit 2 TCNT Count Timing Figure 12.78 shows TCNT count timing in internal clock operation, and Figure 12.79 shows TCNT count timing in external clock operation (normal mode), and Figure 12.80 shows TCNT count timing in external clock operation (phase counting mode). P0φ Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 Figure 12.78 Count Timing in Internal Clock Operation P0φ External clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 Figure 12.79 Count Timing in External Clock Operation P0φ External clock Rising edge Falling edge TCNT input clock TCNT N-1 N N-1 Figure 12.80 Count Timing in External Clock Operation (Phase Counting Mode) (2) Output Compare Output Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 631 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 12.81 shows output compare output timing (normal mode and PWM mode) and Figure 12.82 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). P0φ TCNT input clock TCNT TGR N N+1 N Compare match signal TIOC pin Figure 12.81 Output Compare Output Timing (Normal Mode/PWM Mode) P0φ TCNT input clock TCNT N TGR N N+1 Compare match signal TIOC pin Figure 12.82 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Page 632 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 12 Multi-Function Timer Pulse Unit 2 Input Capture Signal Timing Figure 12.83 shows input capture signal timing. P0φ Input capture input Input capture signal N TCNT N+1 N+2 N TGR N+2 Figure 12.83 Input Capture Input Signal Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 633 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 12.84 shows the timing when counter clearing on compare match is specified, and Figure 12.85 shows the timing when counter clearing on input capture is specified. P0φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 12.84 Counter Clear Timing (Compare Match) P0φ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 12.85 Counter Clear Timing (Input Capture) Page 634 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 12 Multi-Function Timer Pulse Unit 2 Buffer Operation Timing Figures 12.86 to 12.88 show the timing in buffer operation. P0φ TCNT n n+1 TGRA, TGRB n N TGRC, TGRD N Compare match buffer signal Figure 12.86 Buffer Operation Timing (Compare Match) P0φ Input capture signal TCNT N N+1 TGRA, TGRB n N N+1 n N TGRC, TGRD Figure 12.87 Buffer Operation Timing (Input Capture) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 635 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 P0φ n H'0000 TGRA, TGRB, TGRE n N TGRC, TGRD, TGRF N TCNT TCNT clear signal Buffer transfer signal Figure 12.88 Buffer Transfer Timing (when TCNT Cleared) (6) Buffer Transfer Timing (Complementary PWM Mode) Figures 12.89 to 12.91 show the buffer transfer timing in complementary PWM mode. P0φ H'0000 TCNTS TGRD_4 write signal Temporary register transfer signal Buffer register n Temporary register n N N Figure 12.89 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) Page 636 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 P0φ TCNTS P-x P H'0000 TGRD_4 write signal Buffer register n N Temporary register n N Figure 12.90 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) P0φ TCNTS P−1 P H'0000 Buffer transfer signal Temporary register N Compare register n N Figure 12.91 Transfer Timing from Temporary Register to Compare Register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 637 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.6.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 12.92 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. P0φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 12.92 TGI Interrupt Timing (Compare Match) Page 638 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 12 Multi-Function Timer Pulse Unit 2 TGF Flag Setting Timing in Case of Input Capture Figure 12.93 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. P0φ Input capture signal N TCNT TGR N TGF flag TGI interrupt Figure 12.93 TGI Interrupt Timing (Input Capture) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 639 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (3) TCFV Flag/TCFU Flag Setting Timing Figure 12.94 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 12.95 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. P0φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 12.94 TCIV Interrupt Setting Timing P0φ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 12.95 TCIU Interrupt Setting Timing Page 640 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 12 Multi-Function Timer Pulse Unit 2 Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the direct memory access controller is activated, the flag is cleared automatically. Figure 12.96 shows the timing for status flag clearing by the CPU, and Figure 12.97 shows the timing for status flag clearing by the direct memory access controller. TSR write cycle T1 T2 P0φ TSR address Address Write signal Status flag Interrupt request signal Figure 12.96 Timing for Status Flag Clearing by CPU Direct memory access controller read cycle Direct memory access controller write cycle P0φ, Bφ Address Source address Destination address Status flag Interrupt request signal Flag clear signal Figure 12.97 Timing for Status Flag Clearing by Direct Memory Access Controller Activation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 641 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7 Usage Notes 12.7.1 Module Standby Mode Setting Operation of this module can be disabled or enabled using the standby control register. The initial setting is for the operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 49, Power-Down Modes. 12.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. This module will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 12.98 shows the input clock conditions in phase counting mode. Overlap Phase Phase differdifference Overlap ence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 12.98 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Page 642 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.7.3 Section 12 Multi-Function Timer Pulse Unit 2 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where 12.7.4 P0 (N + 1) f: P0: N: Counter frequency Peripheral clock operating frequency TGR set value Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 12.99 shows the timing in this case. TCNT write cycle T2 T1 P0φ Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 12.99 Contention between TCNT Write and Clear Operations R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 643 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 12.100 shows the timing in this case. TCNT write cycle T2 T1 P0φ Address TCNT address Write signal TCNT input clock TCNT N M TCNT write data Figure 12.100 Contention between TCNT Write and Increment Operations Page 644 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.7.6 Section 12 Multi-Function Timer Pulse Unit 2 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 12.101 shows the timing in this case. TGR write cycle T2 T1 P0φ TGR address Address Write signal Compare match signal TCNT N N+1 TGR N M TGR write data Figure 12.101 Contention between TGR Write and Compare Match R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 645 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data after write. Figure 12.102 shows the timing in this case. TGR write cycle T1 T2 P0φ Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register TGR N M N Figure 12.102 Contention between Buffer Register Write and Compare Match Page 646 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.7.8 Section 12 Multi-Function Timer Pulse Unit 2 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 12.103 shows the timing in this case. TGR write cycle T1 T2 P0φ Buffer register address Address Write signal TCNT clear signal Buffer transfer signal Buffer register TGR Buffer register write data N M N Figure 12.103 Contention between Buffer Register Write and TCNT Clear R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 647 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.9 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer. Figure 12.104 shows the timing in this case. TGR read cycle T2 T1 P0φ Address TGR address Read signal Input capture signal TGR Internal data bus N M N Figure 12.104 Contention between TGR Read and Input Capture Page 648 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 12.105 shows the timing in this case. TGR write cycle T2 T1 P0φ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 12.105 Contention between TGR Write and Input Capture R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 649 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 12.106 shows the timing in this case. Buffer register write cycle T2 T1 P0φ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 12.106 Contention between Buffer Register Write and Input Capture 12.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 12.107. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Page 650 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 TCNT write cycle T1 T2 P0φ Address TCNT_2 address Write signal TCNT_2 H'FFFE H'FFFF N N+1 TCNT_2 write data TGRA_2 to TGRB_2 H'FFFF Ch2 comparematch signal A/B Disabled TCNT_1 input clock TCNT_1 M TGRA_1 M Ch1 comparematch signal A TGRB_1 N M Ch1 input capture signal B TCNT_0 P TGRA_0 to TGRD_0 Q P Ch0 input capture signal A to D Figure 12.107 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 651 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 12.108. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 12.108 Counter Value during Complementary PWM Mode Stop 12.7.14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register. Page 652 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 12.109 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT_3 Point a TGRC_3 Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, TGRD_4 Point b TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 12.109 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 653 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 12.110 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 12.110 Reset Synchronous PWM Mode Overflow Flag Page 654 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.111 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. P0φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF TCFV Disabled Figure 12.111 Contention between Overflow and Counter Clearing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 655 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 12.112 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 P0φ TCNT address Address Write signal TCNT write data TCNT TCFV flag H'FFFF M Disabled Figure 12.112 Contention between TCNT Write and Overflow 12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode. Page 656 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00. 12.7.21 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the direct memory access controller activation source. Interrupts should therefore be disabled before entering module standby mode. 12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 657 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 12.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode In complementary PWM mode, when output waveform control during synchronous counter clearing is enabled (WRE in the TWCR register set to 1), the following problems may occur when condition (1) or condition (2), below, is satisfied.  Dead time for the PWM output pins may be too short (or nonexistent).  Active-level output from the PWM negative-phase pins may occur outside the correct activelevel output interval Condition (1): When synchronous clearing occurs in the PWM output dead time interval within initial output suppression interval (10) (figure 12.113). Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or (11) and TGRB_3  TDDR, TGRA_4  TDDR, or TGRB_4  TDDR is true (figure 12.114) Synchronous clearing TGRA_3 (10) (11) (10) TCNT_3 (11) Tb interval Tb interval TCNT_4 TGR TDDR 0 PWM output (positive phase) PWM output (negative phase) TDDR Shortened dead time Initial output suppression Dead time Note: PWM output is low-active. Figure 12.113 Condition (1) Synchronous Clearing Example Page 658 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 Synchronous clearing (10) TGRA_3 (11) (10) (11) TCNT_3 Tb interval Tb interval TCNT_4 TDDR TGR 0 PWM output (positive phase) PWM output (negative phase) Active-level output occurs at synchronous clearing even though no active-level output interval has been set. Nonexistent dead time Initial output suppression Dead time Note: PWM output is low-active. Figure 12.114 Condition (2) Synchronous Clearing Example The following workaround can be used to avoid these problems. When using synchronous clearing, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 659 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group 12.8 Output Pin Initialization for Multi-Function Timer Pulse Unit 2 12.8.1 Operating Modes This module has the following six operating modes. Waveform output is possible in all of these modes.       Normal mode (channels 0 to 4) PWM mode 1 (channels 0 to 4) PWM mode 2 (channels 0 to 2) Phase counting modes 1 to 4 (channels 1 and 2) Complementary PWM mode (channels 3 and 4) Reset-synchronized PWM mode (channels 3 and 4) The output pin initialization method for each of these modes is described in this section. 12.8.2 Reset Start Operation The output pins of this module (TIOC*) are initialized low by a power-on reset and in deep standby mode. Since the pin functions are selected using the general I/O ports, when the general I/O port is set, the pin states at that point are output to the ports. When this module output is selected by the general I/O port immediately after a reset, the initial output level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the general I/O port setting should be made after the initialization of the output pins is completed. Note: Channel number and port notation are substituted for *. Page 660 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 12.8.3 Section 12 Multi-Function Timer Pulse Unit 2 Operation in Case of Re-Setting Due to Error during Operation, etc. If an error occurs during operation of this module, the module output should be cut by the system. Cutoff is performed by switching the pin output to port output with the general I/O port and outputting the inverse of the active level. The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. This module has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 12.57. Table 12.57 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (2) (3) (4) (5) (6) PWM1 (7) (8) (9) (10) (11) (12) PWM2 (13) (14) (15) (16) None None PCM (17) (18) (19) (20) None None CPWM (21) (22) None None (23) (24) (25) RPWM (26) (27) None None (28) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 661 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 12.8.4 SH7268 Group, SH7269 Group Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc.  When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.  In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1.  In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2.  In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again.  In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again.  When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 12.57. The active level is assumed to be low. Page 662 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 12 Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 12.115 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.115 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, the module output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set the multi-function timer pulse unit 2 output with the general I/O port. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the general I/O port and output the inverse of the active level. The count operation is stopped by TSTR. Not necessary when restarting in normal mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 663 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.116 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.116 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.115. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, and then switch to PWM mode 1.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Page 664 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 12 Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 12.117 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.117 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 12.115. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, and then switch to PWM mode 2.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 665 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 12.118 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 13 14 12 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.118 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12.115. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Page 666 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 12 Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.119 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting. 12 11 10 9 7 8 6 4 5 3 (18) 13 1 2 14 15 (16) (17) RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) occurs (PORT) (0) (1 init (MTU2) (1) (normal) (1) (CPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.119 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.115. 11. 12. 13. 14. 15. 16. 17. 18. Initialize the normal mode waveform generation section with TIOR. Disable operation of the normal mode waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 667 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.120 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. 6 4 5 3 1 2 PFC TSTR RESET TMDR TOER TIOR (1 init (MTU2) (1) (normal) (1) 0 out) 7 Match 10 9 8 PFC TSTR Error occurs (PORT) (0) 12 11 18 13 14 15 16 17 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.120 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 12.115. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set the multi-function timer pulse unit 2 output with the general I/O port. 18. Operation is restarted by TSTR. Page 668 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (7) Section 12 Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 12.121 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.121 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, the module output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the general I/O port and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 669 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 12.122 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Not initialized (TIOC*B) Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.122 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.121. 11. 12. 13. 14. Not necessary when restarting in PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 670 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (9) Section 12 Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 12.123 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.123 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 12.121. 11. 12. 13. 14. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 671 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 12.124 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 13 14 12 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.124 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12.121. 11. 12. 13. 14. Set phase counting mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Page 672 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.125 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting. 1 2 14 15 16 17 18 3 19 5 4 6 7 8 9 10 11 12 13 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.125 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.121. 11. 12. 13. 14. 15. 16. 17. 18. 19. Set normal mode for initialization of the normal mode waveform generation section. Initialize the PWM mode 1 waveform generation section with TIOR. Disable operation of the PWM mode 1 waveform generation section with TIOR. Disable channel 3 and 4 output with TOER. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 673 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.126 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. 13 6 7 8 9 10 11 12 1 2 3 4 5 14 15 16 17 18 19 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (PWM1) (1) (1 init (MTU2) (1) (RPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.126 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 12.125. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set the multi-function timer pulse unit 2 output with the general I/O port. 19. Operation is restarted by TSTR. Page 674 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 12.127 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (normal) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.127 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, the module output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set the multi-function timer pulse unit 2 output with the general I/O port. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the general I/O port and output the inverse of the active level. The count operation is stopped by TSTR. Set normal mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 675 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 12.128 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Not initialized (TIOC*B) Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.128 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 12.127. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 676 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 12.129 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A Not initialized (cycle register) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.129 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 12.127. 10. 11. 12. 13. Not necessary when restarting in PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 677 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 12.130 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PCM) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.130 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12.127. 10. 11. 12. 13. Set phase counting mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 678 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 12.131 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (normal) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.131 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. After a reset, the module output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set the multi-function timer pulse unit 2 output with the general I/O port. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the general I/O port and output the inverse of the active level. The count operation is stopped by TSTR. Set in normal mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 679 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.132 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Not initialized (TIOC*B) Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.132 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 12.131. 10. 11. 12. 13. Set PWM mode 1. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 680 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 12.133 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.133 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 12.131. 10. 11. 12. 13. Set PWM mode 2. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 681 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 12.134 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PCM) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.134 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12.131. 10. 11. 12. 13. Not necessary when restarting in phase counting mode. Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 682 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 12.135 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.135 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, the module output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set the multi-function timer pulse unit 2 output with the general I/O port. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the general I/O port and output the inverse of the active level. The count operation is stopped by TSTR. (This module outputs the same value as the complementary PWM output initial value.) Set normal mode. (This module outputs a low-level signal.) Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 683 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.136 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.136 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.135. 11. 12. 13. 14. Set PWM mode 1. (This module outputs a low-level signal.) Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 684 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.137 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.137 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.135. 11. Set the multi-function timer pulse unit 2 output with the general I/O port. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 685 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 SH7268 Group, SH7269 Group (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.138 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). 1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.138 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.135. 11. Set normal mode and make new settings. (This module outputs a low-level signal.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set the multi-function timer pulse unit 2 output with the general I/O port. 17. Operation is restarted by TSTR. Page 686 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.139 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode. 13 12 11 10 9 7 8 6 4 5 17 1 2 3 14 15 16 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU2) (1) (RPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.139 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 12.135. 11. Set normal mode. (This module outputs a low-level signal.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set the multi-function timer pulse unit 2 output with the general I/O port. 17. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 687 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (26) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 12.140 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.140 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. After a reset, the module output is low and ports are in the high-impedance state. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronized PWM. Enable channel 3 and 4 output with TOER. Set the multi-function timer pulse unit 2 output with the general I/O port. The count operation is started by TSTR. The reset-synchronized PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the general I/O port and output the inverse of the active level. The count operation is stopped by TSTR. (This module outputs the same value as the resetsynchronized PWM output initial value.) Set normal mode. (The positive phase output from this module is low, and negative phase output is high.) Initialize the pins with TIOR. Set the multi-function timer pulse unit 2 output with the general I/O port. Operation is restarted by TSTR. Page 688 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (27) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.141 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.141 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.140. 11. Set PWM mode 1. (The positive phase output from this module is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 689 of 3092 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.142 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in complementary PWM mode after resetting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 14 15 16 8 9 10 11 12 13 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.142 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.140. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The cyclic output pin of this module outputs a low-level signal.) 14. Enable channel 3 and 4 output with TOER. 15. Set the multi-function timer pulse unit 2 output with the general I/O port. 16. Operation is restarted by TSTR. Page 690 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 12 Multi-Function Timer Pulse Unit 2 (29) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.143 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in reset-synchronized PWM mode after resetting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.143 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 12.140. 11. Set the multi-function timer pulse unit 2 output with the general I/O port. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 691 of 3092 Section 12 Multi-Function Timer Pulse Unit 2 Page 692 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 13 Compare Match Timer Section 13 Compare Match Timer This LSI has an on-chip compare match timer module consisting of two-channel 16-bit timers. This module has a 16-bit counter, and can generate interrupts at set intervals. 13.1 Features  Independent selection of four counter input clocks at two channels Any of four internal clocks (P0/8, P0/32, P0/128, and P0/512) can be selected.  Selection of DMA transfer request or interrupt request generation on compare match by direct memory access controller setting  When not in use, this module can be stopped by halting its clock supply to reduce power consumption. Figure 13.1 shows a block diagram. Clock selection P0φ/8 P0φ/32 P0φ/128 P0φ/512 Clock selection Channel 0 Module bus CMCNT_1 Comparator Control circuit CMCSR_1 CMCNT_0 Comparator CMCOR_0 CMCSR_0 Control circuit CMSTR CMI1 P0φ/8 P0φ/32 P0φ/128 P0φ/512 CMCOR_1 CMI0 Channel 1 Bus interface Compare match timer Peripheral bus [Legend] CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match constant register Compare match counter Compare match interrupt Figure 13.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 693 of 3092 SH7268 Group, SH7269 Group Section 13 Compare Match Timer 13.2 Register Descriptions Table 13.1 shows the register configuration. Table 13.1 Register Configuration Abbreviation R/W Initial Value Address Access Size Common Compare match timer start register CMSTR R/W H'0000 H'FFFEC000 16 0 Compare match timer control/ status register_0 CMCSR_0 R/W H'0000 H'FFFEC002 16 Compare match counter_0 CMCNT_0 R/W H'0000 H'FFFEC004 8, 16 Compare match constant register_0 CMCOR_0 R/W H'FFFF H'FFFEC006 8, 16 Compare match timer control/ status register_1 CMCSR_1 R/W H'0000 H'FFFEC008 16 Compare match counter_1 CMCNT_1 R/W H'0000 H'FFFEC00A 8, 16 Compare match constant register_1 CMCOR_1 R/W H'FFFF H'FFFEC00C 8, 16 Channel 1 Register Name Page 694 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 13.2.1 Section 13 Compare Match Timer Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - STR1 STR0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Specifies whether compare match counter_1 operates or is stopped. 0: Counting by CMCNT_1 is stopped 1: Counting by CMCNT_1 is started 0 STR0 0 R/W Count Start 0 Specifies whether compare match counter_0 operates or is stopped. 0: Counting by CMCNT_0 is stopped 1: Counting by CMCNT_0 is started R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 695 of 3092 SH7268 Group, SH7269 Group Section 13 Compare Match Timer 13.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - CMF CMIE - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 R/(W)* R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 1 0 CKS[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition]  When 0 is written to CMF after reading CMF = 1 1: CMCNT and CMCOR values match 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 696 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 13 Compare Match Timer Bit Bit Name Initial Value R/W Description 1, 0 CKS[1:0] 00 R/W Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral clock (P0). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS[1:0]. 00: P0/8 01: P0/32 10: P0/128 11: P0/512 Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 697 of 3092 SH7268 Group, SH7269 Group Section 13 Compare Match Timer 13.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS[1:0] in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 by clearing any channels of the counter start bit from 1 to 0 in the compare match timer start register (CMSTR). Bit: Initial value: R/W: 13.2.4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Compare Match Constant Register (CMCOR) CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Page 698 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 13 Compare Match Timer 13.3 Operation 13.3.1 Interval Count Operation When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 13.2 shows the operation of the compare match counter. CMCNT value Counter cleared by compare match with CMCOR CMCOR H'0000 Time Figure 13.2 Counter Operation 13.3.2 CMCNT Count Timing One of four clocks (P0/8, P0/32, P0/128, and P0/512) obtained by dividing the peripheral clock (P0) can be selected with the CKS1 and CKS0 bits in CMCSR. Figure 13.3 shows the timing. Peripheral clock (P0φ) Internal clock Count clock Clock N CMCNT Clock N+1 N N+1 Figure 13.3 Count Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 699 of 3092 Section 13 Compare Match Timer 13.4 Interrupts 13.4.1 Interrupt Sources and DMA Transfer Requests SH7268 Group, SH7269 Group This module has channels and each of them to which a different vector address is allocated has a compare match interrupt. When both the compare match flag (CMF) and the interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 7, Interrupt Controller. Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out, another interrupt will be generated. By setting the interrupt controller, the direct memory access controller can be activated when a compare match interrupt is requested. In this case, an interrupt is not issued to the CPU. If the setting to activate the direct memory access controller has not been made, an interrupt request is sent to the CPU. The CMF bit is automatically cleared to 0 when data is transferred by the direct memory access controller. 13.4.2 Timing of Compare Match Flag Setting When CMCOR and CMCNT match, a compare match signal is generated at the last state in which the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 13.4 shows the timing of CMF bit setting. Page 700 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 13 Compare Match Timer Peripheral clock (P0φ) Clock N+1 Counter clock CMCNT N CMCOR N 0 Compare match signal Figure 13.4 Timing of CMF Setting 13.4.3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of the direct memory access controller being activated, the CMF bit is automatically cleared to 0 when data is transferred by the direct memory access controller. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 701 of 3092 SH7268 Group, SH7269 Group Section 13 Compare Match Timer 13.5 Usage Notes 13.5.1 Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 13.5 shows the timing to clear the CMCNT counter. CMCSR write cycle T1 T2 Peripheral clock (P0φ) Address signal CMCNT Internal write signal Counter clear signal CMCNT N H'0000 Figure 13.5 Conflict between Write and Compare Match Processes of CMCNT Page 702 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 13.5.2 Section 13 Compare Match Timer Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 13.6 shows the timing to write to CMCNT in words. CMCSR write cycle T1 T2 Peripheral clock (P0φ) Address signal CMCNT Internal write signal CMCNT count-up enable signal CMCNT N M Figure 13.6 Conflict between Word-Write and Count-Up Processes of CMCNT R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 703 of 3092 SH7268 Group, SH7269 Group Section 13 Compare Match Timer 13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has priority over the count-up. In this case, the count-up is not performed. The byte data on the other side, which is not written to, is also not counted and the previous contents are retained. Figure 13.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNTH in bytes. CMCSR write cycle T1 T2 Peripheral clock (P0φ) Address signal CMCNTH Internal write signal CMCNT count-up enable signal CMCNTH N M CMCNTL X X Figure 13.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 13.5.4 Compare Match between CMCNT and CMCOR Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. Page 704 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 14 Watchdog Timer Section 14 Watchdog Timer This LSI includes the watchdog timer, which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. This module can simultaneously generate an internal reset signal for the entire LSI. This module is a single channel timer that counts up the clock oscillation settling period when the system leaves software standby mode. It can also be used as a general watchdog timer or interval timer. 14.1 Features  Can be used to ensure the clock oscillation settling time This module is used in leaving software standby mode.  Can switch between watchdog timer mode and interval timer mode.  Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode, the WDTOVF signal is output externally. It is possible to select whether to reset the LSI internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset type.  Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows.  Choice of eight counter input clocks Eight clocks (P0  1 to P0  1/16384) that are obtained by dividing the peripheral clock can be selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 705 of 3092 SH7268 Group, SH7269 Group Section 14 Watchdog Timer Figure 14.1 shows a block diagram. Watchdog timer Standby cancellation Standby mode Standby control Peripheral clock Divider Interrupt request Interrupt control Clock selection Clock selector WDTOVF Internal reset request* Reset control Overflow WRCSR WTCSR Clock WTCNT Bus interface [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter WRCSR: Watchdog reset control/status register Note: * The internal reset signal can be generated by making a register setting. Figure 14.1 Block Diagram 14.2 Input/Output Pin Table 14.1 shows the pin configuration. Table 14.1 Pin Configuration Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs the counter overflow signal in watchdog timer mode Page 706 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 14.3 Section 14 Watchdog Timer Register Descriptions Table 14.2 shows the register configuration. Table 14.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Watchdog timer counter WTCNT R/W H'00 H'FFFE0002 16* Watchdog timer control/status register WTCSR R/W H'18 H'FFFE0000 16* Watchdog reset control/status register WRCSR R/W H'1F H'FFFE0004 16* Note: 14.3.1 * For the access size, see section 14.3.4, Notes on Register Access. Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode. Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read from WTCNT. Note: The method for writing to WTCNT differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: Initial value: R/W: R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 707 of 3092 SH7268 Group, SH7269 Group Section 14 Watchdog Timer 14.3.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. When used to count the clock oscillation settling time for canceling software standby mode, it retains its value after counter overflow. Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from WTCSR. Note: The method for writing to WTCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: 7 6 5 4 3 IOVF WT/IT TME - - 0 R/W 0 R/W 1 R 1 R Initial value: 0 R/W: R/(W) 2 1 0 CKS[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 IOVF 0 R/(W) Interval Timer Overflow 0 R/W Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT overflow in interval timer mode [Clearing condition]  Page 708 of 3092 When 0 is written to IOVF after reading IOVF R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 14 Watchdog Timer Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether to use this module as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: When the WTCNT overflows in watchdog timer mode, the WDTOVF signal is output externally. If this bit is modified when this module is running, the up-count may not be performed correctly. 5 TME 0 R/W Timer Enable Starts and stops timer operation. Clear this bit to 0 when using this module in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 709 of 3092 SH7268 Group, SH7269 Group Section 14 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 to 0 CKS[2:0] 000 R/W Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (P0). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P0) is 33.33 MHz. Bits 2 to 0 Clock Ratio Overflow Cycle 000: 1  P0 7.7 s 001: 1/64  P0 490 s 010: 1/128  P0 979 s 011: 1/256  P0 2.0 ms 100: 1/512  P0 3.9 ms 101: 1/1024  P0 7.8 ms 110: 1/4096  P0 31 ms 111: 1/16384  P0 125 ms Note: If bits CKS[2:0] are modified when this module is running, the up-count may not be performed correctly. Ensure that these bits are modified only when this module is not running. Page 710 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 14.3.3 Section 14 Watchdog Timer Watchdog Reset Control/Status Register (WRCSR) WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. 7 6 5 4 3 2 1 WOVF RSTE RSTS - - - - - Initial value: 0 R/W: R/(W) 0 R/W 0 R/W 1 R 1 R 1 R 1 R 1 R Bit: 0 Bit Bit Name Initial Value R/W Description 7 WOVF 0 R/(W) Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode [Clearing condition]  When 0 is written to WOVF after reading WOVF 6 RSTE 0 R/W Reset Enable Selects whether to generate a signal to reset the LSI internally if WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Not reset when WTCNT overflows* 1: Reset when WTCNT overflows Note: * LSI not reset internally, but WTCNT and WTCSR reset within this module. 5 RSTS 0 R/W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 to 0  All 1 R Reserved These bits are always read as 1. The write value should always be 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 711 of 3092 SH7268 Group, SH7269 Group Section 14 Watchdog Timer 14.3.4 Notes on Register Access The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write 15 WTCSR write 8 15 Address: H'FFFE0000 0 7 H'5A Address: H'FFFE0002 Write data 8 7 H'A5 0 Write data Figure 14.2 Writing to WTCNT and WTCSR Page 712 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 14 Watchdog Timer Writing to WRCSR WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte transfer or longword transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 14.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Address: H'FFFE0004 7 H'A5 Address: H'FFFE0004 Writing to the RSTE and RSTS bits 8 15 0 H'00 8 7 H'5A 0 Write data Figure 14.3 Writing to WRCSR (3) Reading from WTCNT, WTCSR, and WRCSR WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address H'FFFE0004. Byte transfer instructions must be used for reading from these registers. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 713 of 3092 Section 14 Watchdog Timer 14.4 Usage 14.4.1 Canceling Software Standby Mode SH7268 Group, SH7269 Group This module can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (This module does not operate when resets are used for canceling, so keep the RES or MRES pin low until clock oscillation settles.) 1. Before making a transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. After setting the STBY and DEEP bits of the standby control register 1 (STBCR1: see section 49, Power-Down Modes) to 1 and 0 respectively, the execution of a SLEEP instruction puts the system in software standby mode and clock operation then stops. 4. This module starts counting by detecting the edge change of the NMI signal. 5. When the module count overflows, the clock pulse generator starts supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 14.4.2 Using Watchdog Timer Mode 1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, this module sets the WOVF flag in WRCSR to 1, and the WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 64  P0 clock cycles. 5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for 128  P0 clock cycles. 6. When an overflow reset of this module is generated simultaneously with a reset input on the RES pin, the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0. Page 714 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 14 Watchdog Timer WTCNT value Overflow H'FF H'00 Time H'00 written in WTCNT WT/IT = 1 TME = 1 WOVF = 1 WT/IT = 1 TME = 1 WDTOVF and internal reset generated H'00 written in WTCNT WDTOVF signal 64 × P0φ clock cycles Internal reset signal* 128 × P0φ clock cycles [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 14.4 Operation in Watchdog Timer Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 715 of 3092 SH7268 Group, SH7269 Group Section 14 Watchdog Timer 14.4.3 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, this module sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the interrupt controller. The counter then resumes counting. WTCNT value Overflow Overflow Overflow Overflow H'FF H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI [Legend] ITI: Interval timer interrupt request generation Figure 14.5 Operation in Interval Timer Mode Page 716 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 14.5 Section 14 Watchdog Timer Usage Notes Pay attention to the following points when using this module in either the interval timer or watchdog timer mode. 14.5.1 Timer Variation After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the peripheral clock, P0, while the longest is the result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time difference is referred to as timer variation. This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation. 14.5.2 Prohibition against Setting H'FF to WTCNT When the value in WTCNT reaches H'FF, this module assumes that an overflow has occurred. Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or reset will occur immediately, regardless of the current clock selection by the CKS[2:0] bits. 14.5.3 Interval Timer Overflow Flag When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared. Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a value other than H'FF. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 717 of 3092 SH7268 Group, SH7269 Group Section 14 Watchdog Timer 14.5.4 System Reset by WDTOVF Signal If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly. Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 14.6. Reset input (Low active) Reset signal to entire system (Low active) RES WDTOVF Figure 14.6 Example of System Reset Circuit Using WDTOVF Signal 14.5.5 Manual Reset in Watchdog Timer Mode When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset occurs while the bus is released or during burst transfer by the direct memory access controller, manual reset exception handling will be pended until the CPU acquires the bus mastership. 14.5.6 Internal Reset in Watchdog Timer Mode When an internal reset is generated by an overflow of the watchdog timer counter (WTCNT) in watchdog timer mode, the watchdog reset control/status register (WRCSR) is not initialized and the WOVF bit is set to 1. When the value of the WOVF bit is 1, no internal reset is generated when a WTCNT overflow occurs. Page 718 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock Section 15 Realtime Clock This LSI has a realtime clock and a 32.768-kHz crystal oscillator. 15.1 Features  Clock and calendar functions (BCD format): Seconds, minutes, hours, date, day of the week, month, and year.  1-Hz to 64-Hz timer (binary format) 64-Hz counter indicates the state of the divider circuit between 64 Hz and 1 Hz  Start/stop function  30-second adjust function  Alarm interrupt: Frame comparison of seconds, minutes, hours, date, day of the week, month, and year can be used as conditions for the alarm interrupt  Periodic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds  Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read  Automatic leap year adjustment  The external clock signal for the internal signal or dedicated for the clock function can be selected as the operating clock signal for the clock function.  Recovery from deep standby mode can be performed by an alarm interrupt. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 719 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock Figure 15.1 shows the block diagram. RTC_X1 32.768 kHz Crystal oscillator 128 Hz Prescaler R64CNT RSECCNT RSECAR RMINCNT RMINAR RHRCNT RHRAR RDAYCNT RDAYAR RWKCNT RWKAR RMONCNT RMONAR RYRCNT RYRAR XTAL RCR5 Bus interface Crystal oscillator RFRH RFRL Operation control circuit RCR1 RCR2 Peripheral bus RTC_X2 EXTAL Interrupt control circuit RCR3 ARM PRD Interrupt signals CUP [Legend] RSECCNT: RMINCNT: RHRCNT: RWKCNT: RDAYCNT: RMONCNT: RYRCNT: R64CNT: RFRH/L: Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter 64-Hz counter Frequency register RSECAR: RMINAR: RHRAR: RWKAR: RDAYAR: RMONAR: RYRAR: RCR1: RCR2: RCR3: RCR5: Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date alarm register Month alarm register Year alarm register Control register 1 Control register 2 Control register 3 Control register 5 Figure 15.1 Block Diagram Page 720 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.2 Section 15 Realtime Clock Input/Output Pin Table 15.1 shows the pin configuration. Table 15.1 Pin Configuration Pin Name Symbol I/O Description Realtime clock crystal resonator pin/ external clock RTC_X1 Input RTC_X2 Output Connects 32.768-kHz crystal resonator for this module, and enables to input the external clock to the RTC_X1 pin. Internal clock crystal resonator/ external clock EXTAL Input XTAL Output R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Connects crystal resonator used for internal operation. For details, see section 5, Clock Pulse Generator. Page 721 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3 Register Descriptions Table 15.2 shows the register configuration. Table 15.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size 64-Hz counter R64CNT R H'xx H'FFFE6000 8 Second counter RSECCNT R/W H'xx H'FFFE6002 8 Minute counter RMINCNT R/W H'xx H'FFFE6004 8 Hour counter RHRCNT R/W H'xx H'FFFE6006 8 Day of week counter RWKCNT R/W H'xx H'FFFE6008 8 Date counter RDAYCNT R/W H'xx H'FFFE600A 8 Month counter RMONCNT R/W H'xx H'FFFE600C 8 Year counter RYRCNT R/W H'xxxx H'FFFE600E 16 Second alarm register RSECAR R/W H'xx H'FFFE6010 8 Minute alarm register RMINAR R/W H'xx H'FFFE6012 8 Hour alarm register RHRAR R/W H'xx H'FFFE6014 8 Day of week alarm register RWKAR R/W H'xx H'FFFE6016 8 Date alarm register RDAYAR R/W H'xx H'FFFE6018 8 Month alarm register RMONAR R/W H'xx H'FFFE601A 8 Year alarm register RYRAR R/W H'xxxx H'FFFE6020 16 Control register 1 RCR1 R/W H'xx H'FFFE601C 8 Control register 2 RCR2 R/W H'09 H'FFFE601E 8 Control register 3 RCR3 R/W H'x0 H'FFFE6024 8 Control register 5 RCR5 R/W H'xx H'FFFE6026 8 Frequency register H RFRH R/W H'xxxx H'FFFE602A 16 Frequency register L RFRL R/W H'xxxx H'FFFE602C 16 Page 722 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.3.1 Section 15 Realtime Clock 64-Hz Counter (R64CNT) R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz. Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed at the same time is indicated. In this case, the R64CNT should be read again after writing 0 to the CF bit in RCR1 since the read value is not valid. After the RESET bit or ADJ bit in the control register 2 (RCR2) is set to 1, the divider circuit is initialized and R64CNT is initialized. BIt: 7 6 5 4 3 - 1Hz 2Hz 4Hz 8Hz Initial value: 0 R/W: R 2 1 0 16Hz 32Hz 64Hz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Name Initial Value R/W 7  0 R R R R R R R R Description Reserved This bit is always read as 0. The write value should always be 0. 6 1 Hz Undefined R 5 2 Hz Undefined R 4 4 Hz Undefined R 3 8 Hz Undefined R 2 16 Hz Undefined R 1 32 Hz Undefined R 0 64 Hz Undefined R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Indicate the state of the divider circuit between 64 Hz and 1 Hz. Page 723 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.2 Second Counter (RSECCNT) RSECCNT is used for setting/counting in the BCD-coded second section. The count operation is performed by a carry for each second of the 64-Hz counter. The assignable range is from 00 through 59 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 - 5 4 3 10 seconds Initial value: 0 R/W: R 2 1 0 1 second Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value R/W 7  0 R R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 10 seconds Undefined R/W Counting Ten's Position of Seconds Counts on 0 to 5 for 60-seconds counting. 3 to 0 1 second Undefined R/W Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. Page 724 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.3.3 Section 15 Realtime Clock Minute Counter (RMINCNT) RMINCNT is used for setting/counting in the BCD-coded minute section. The count operation is performed by a carry for each minute of the second counter. The assignable range is from 00 through 59 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 - 5 4 3 10 minutes Initial value: 0 R/W: R 2 1 0 1 minute Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value R/W 7  0 R R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 0.The write value should always be 0. 6 to 4 10 minutes Undefined R/W Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minutes counting. 3 to 0 1 minute Undefined R/W Counting One's Position of Minutes Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 725 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.4 Hour Counter (RHRCNT) RHRCNT is used for setting/counting in the BCD-coded hour section. The count operation is performed by a carry for each 1 hour of the minute counter. The assignable range is from 00 through 23 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 5 - - 10 hours Initial value: 0 0 R/W: R R Bit Bit Name Initial Value R/W 7, 6  All 0 R 4 3 2 1 0 1 hour Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 5, 4 10 hours Undefined R/W Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. 3 to 0 1 hour Undefined R/W Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position. Page 726 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.3.5 Section 15 Realtime Clock Day of Week Counter (RWKCNT) RWKCNT is used for setting/counting day of week section. The count operation is performed by a carry for each day of the date counter. The assignable range is from 0 through 6 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 5 4 3 - - - - - Day Undefined Undefined Undefined Initial value: 0 0 0 0 0 R/W: R R R R R Bit Bit Name Initial Value R/W 7 to 3  All 0 R 2 R/W 1 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 Day Undefined R/W Day-of-Week Counting Day-of-week is indicated with a binary code. 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 727 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.6 Date Counter (RDAYCNT) RDAYCNT is used for setting/counting in the BCD-coded date section. The count operation is performed by a carry for each day of the hour counter. The assignable range is from 01 through 31 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. The range of date changes with each month and in leap years. Confirm the correct setting. Leap years are recognized by dividing the year counter (RYRCNT) values by 400, 100, and 4 and obtaining a fractional result of 0. BIt: 7 6 5 - - 10 days Initial value: 0 0 R/W: R R Bit Bit Name Initial Value R/W 7, 6  All 0 R 4 3 2 1 0 1 day Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 5, 4 10 days Undefined R/W 3 to 0 1 day Undefined R/W Counting Ten's Position of Dates Counting One's Position of Dates Counts on 0 to 9 once per date. When a carry is generated, 1 is added to the ten's position. Page 728 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.3.7 Section 15 Realtime Clock Month Counter (RMONCNT) RMONCNT is used for setting/counting in the BCD-coded month section. The count operation is performed by a carry for each month of the date counter. The assignable range is from 01 through 12 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 5 4 - - - 10 months Undefined Undefined Undefined Undefined Undefined Initial value: 0 0 0 R/W: R R R Bit Bit Name Initial Value R/W 7 to 5  All 0 R R/W 3 2 1 0 1 month R/W R/W R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 4 10 months Undefined R/W 3 to 0 1 month Undefined R/W Counting Ten's Position of Months Counting One's Position of Months Counts on 0 to 9 once per month. When a carry is generated, 1 is added to the ten's position. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 729 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.8 Year Counter (RYRCNT) RYRCNT is used for setting/counting in the BCD-coded year section. The count operation is performed by a carry for each year of the month counter. The assignable range is from 0000 through 9999 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 15 14 13 12 1000 years 11 10 9 8 100 years 7 6 5 4 3 10 years 2 1 0 1 year Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 15 to 12 1000 years Undefined R/W Description Counting Thousand's Position of Years 11 to 8 100 years Undefined R/W Counting Hundred's Position of Years 7 to 4 10 years Undefined R/W Counting Ten's Position of Years 3 to 0 1 year Undefined R/W Counting One's Position of Years Page 730 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.3.9 Section 15 Realtime Clock Second Alarm Register (RSECAR) RSECAR is an alarm register corresponding to the BCD-coded second counter RSECCNT. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 59  ENB bits (practically in BCD), otherwise operation errors occur. BIt: 7 6 ENB Initial value: 5 4 3 10 seconds 2 1 0 1 second Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RSECCNT value is performed. 6 to 4 10 seconds Undefined R/W Ten's position of seconds setting value 3 to 0 1 second Undefined R/W One's position of seconds setting value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R/W Description Page 731 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.10 Minute Alarm Register (RMINAR) RMINAR is an alarm register corresponding to the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 59  ENB bits (practically in BCD), otherwise operation errors occur. BIt: 7 6 ENB Initial value: 5 4 3 10 minutes 2 1 0 1 minute Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RMINCNT value is performed. 6 to 4 10 minutes Undefined R/W Ten's position of minutes setting value 3 to 0 1 minute Undefined R/W One's position of minutes setting value Page 732 of 3092 R/W Description R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.11 Hour Alarm Register (RHRAR) RHRAR is an alarm register corresponding to the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 23  ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 ENB - 10 hours Undefined R/W: R/W Bit Bit Name Initial Value 7 ENB Undefined R/W 6  0 R/W R 0 R 4 3 2 1 0 1 hour Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, a comparison with the RHRCNT value is performed. Reserved This bit is always read as 0. The write value should always be 0. 5, 4 10 hours Undefined R/W Ten's position of hours setting value 3 to 0 1 hour Undefined R/W One's position of hours setting value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 733 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.12 Day of Week Alarm Register (RWKAR) RWKAR is an alarm register corresponding to the BCD-coded day of week counter RWKCNT. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 0 through 6 + ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 4 3 ENB - - - - Day Undefined Undefined Undefined Undefined R/W: R/W Bit Bit Name Initial Value 7 ENB Undefined R/W 6 to 3  All 0 R/W R 0 0 0 0 R R R R 2 R/W 1 R/W 0 R/W Description When this bit is set to 1, a comparison with the RWKCNT value is performed. Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 Day Undefined R/W Day of Week Setting Value 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited) Page 734 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.13 Date Alarm Register (RDAYAR) RDAYAR is an alarm register corresponding to the BCD-coded date counter RDAYCNT. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 01 through 31 + ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 ENB - 10 days Undefined R/W: R/W Bit Bit Name Initial Value 7 ENB Undefined R/W 6  0 R/W R 0 R 4 3 2 1 0 1 day Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, a comparison with the RDAYCNT value is performed. Reserved This bit is always read as 0. The write value should always be 0. 5, 4 10 days Undefined R/W Ten's position of dates setting value 3 to 0 1 day Undefined R/W One's position of dates setting value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 735 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.14 Month Alarm Register (RMONAR) RMONAR is an alarm register corresponding to the BCD-coded month counter RMONCNT. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 01 through 12 + ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 4 ENB - - 10 months 0 0 Undefined Undefined Undefined Undefined Undefined R R Undefined R/W: R/W Bit Bit Name Initial Value 7 ENB Undefined R/W 6, 5  All 0 R/W R R/W 3 2 1 0 1 month R/W R/W R/W R/W Description When this bit is set to 1, a comparison with the RMONCNT value is performed. Reserved These bits are always read as 0. The write value should always be 0. 4 10 months Undefined R/W Ten's position of months setting value 3 to 0 1 month Undefined R/W One's position of months setting value Page 736 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.15 Year Alarm Register (RYRAR) RYRAR is an alarm register corresponding to the year counter RYRCNT. The assignable range is from 0000 through 9999 (practically in BCD), otherwise operation errors occur. BIt: 15 14 13 12 1000 years 11 10 9 8 100 years 7 6 5 4 3 10 years 2 1 0 1 year Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 12 1000 years Undefined R/W Thousand's position of years setting value 11 to 8 100 years Undefined R/W Hundred's position of years setting value 7 to 4 10 years Undefined R/W Ten's position of years setting value 3 to 0 1 year Undefined R/W One's position of years setting value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 737 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.16 Control Register 1 (RCR1) RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. The CF flag remains undefined until the divider circuit is reset (the RESET and ADJ bits in RCR2 are set to 1). When using the CF flag, make sure to reset the divider circuit beforehand. The AF flag remains undefined until the value is set to an alarm register and a counter. When using the AF flag, make sure to set the alarm register and counter beforehand. BIt: Initial value: 7 6 5 4 3 2 1 0 CF - - CIE AIE - - AF Undefined R/W: R/W Bit Bit Name Initial Value 7 CF Undefined R/W R/W 0 0 0 0 0 0 Undefined R R R/W R/W R R R/W Description Carry Flag Status flag that indicates that a carry has occurred. CF is set to 1 when a count-up to 64-Hz occurs at the second counter carry or 64-Hz counter read. A count register value read at this time cannot be guaranteed; another read is required. 0: No carry of 64-Hz counter by second counter or 64Hz counter [Clearing condition] When 0 is written to CF 1: Carry of 64-Hz counter by second counter or 64 Hz counter [Setting condition] When the second counter or 64-Hz counter is read during a carry occurrence by the 64-Hz counter, or 1 is written to CF. 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 738 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock Bit Bit Name Initial Value R/W Description 4 CIE 0 R/W Carry Interrupt Enable Flag When the carry flag (CF) is set to 1, the CIE bit enables interrupts. 0: A carry interrupt is not generated when the CF flag is set to 1 1: A carry interrupt is generated when the CF flag is set to 1 3 AIE 0 R/W Alarm Interrupt Enable Flag When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. 0: An alarm interrupt is not generated when the AF flag is set to 1 1: An alarm interrupt is generated when the AF flag is set to 1 2, 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 AF Undefined R/W Alarm Flag The AF flag is set when the alarm time, which is set by an alarm register (ENB bit in RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR is set to 1), and counter match. 0: Alarm register and counter not match [Clearing condition] When 0 is written to AF. 1: Alarm register and counter match* [Setting condition] When alarm register (only a register with ENB bit set to 1) and counter match Note: R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 * Writing 1 holds previous value. Page 739 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.17 Control Register 2 (RCR2) RCR2 is a register for periodic interrupt control, 30-second adjustment, divider circuit RESET, and count control. RCR2 is initialized by a power-on reset or in deep standby mode. Bits other than the RTCEN and START bits are initialized by a manual reset. BIt: 7 6 5 PEF Initial value: 0 R/W: R/W 4 PES[2:0] 3 2 RTCEN ADJ 1 0 RESET START 0 0 0 1 0 0 1 R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 PEF 0 R/W Periodic Interrupt Flag Indicates interrupt generation with the period designated by the PES2 to PES0 bits. When set to 1, PEF generates periodic interrupts. 0: Interrupts not generated with the period designated by the bits PES2 to PES0. [Clearing condition] When 0 is written to PEF 1: Interrupts generated with the period designated by the PES2 to PES0 bits. [Setting condition] When an interrupt is generated with the period designated by the bits PES0 to PES2 or when 1 is written to the PEF flag Page 740 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock Bit Bit Name Initial Value R/W 6 to 4 PES[2:0] 000 R/W Description Interrupt Enable Flags These bits specify the periodic interrupt. 000: No periodic interrupts generated 001: Setting prohibited 010: Periodic interrupt generated every 1/64 second 011: Periodic interrupt generated every 1/16 second 100: Periodic interrupt generated every 1/4 second 101: Periodic interrupt generated every 1/2 second 110: Periodic interrupt generated every 1 second 111: Periodic interrupt generated every 2 seconds 3 RTCEN 1 R/W RTC_X1 Clock Control Controls the function of RTC_X1 pin. 0: Halts the on-chip crystal oscillator/disables the external clock input. 1: Runs the on-chip crystal oscillator/enables the external clock input. 2 ADJ 0 R/W 30-Second Adjustment When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit (prescaler and R64CNT) will be simultaneously reset. This bit always reads 0. 0: Runs normally. 1: 30-second adjustment. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 741 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock Bit Bit Name Initial Value R/W Description 1 RESET 0 R/W Reset Writing 1 to this bit initializes the divider circuit, the R64CNT register, the alarm register, the RCR3 register, bits CF and AF in RCR1, and bit PEF in RCR2. In this case, the RESET bit is automatically reset to 0 after 1 is written to and the above registers are reset. Thus, there is no need to write 1 to this bit. This bit is always read as 0. 0: Runs normally. 1: Divider circuit is reset. 0 START 1 R/W Start Halts and restarts the counter (clock). 0: Second/minute/hour/day/week/month/year counter halts. 1: Second/minute/hour/day/week/month/year counter runs normally. 15.3.18 Control Register 3 (RCR3) When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. BIt: Initial value: 7 6 5 4 3 2 1 ENB - - - - - - - Undefined 0 0 0 0 0 0 0 R R R R R R R R/W: R/W Bit Bit Name Initial Value 7 ENB Undefined R/W 6 to 0  All 0 R/W R 0 Description When this bit is set to 1, comparison of the year alarm register (RYRAR) and the year counter (RYRCNT) is performed. Reserved These bits are always read as 0. The write value should always be 0. Page 742 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.19 Control Register 5 (RCR5) When the RCKSEL[1:0] bits in RCR5 are set to 00, the RTC_X1 clock pulses are counted; when the RCKSEL[1:0] bits are set to 01, the EXTAL clock pulses are counted to implement the clock function. Bit: Initial value: R/W: Bit Bit Name 7 to 2  7 6 5 4 3 2 - - - - - - RCKSEL[1:0] 0 R 0 R 0 R 0 R 0 R 0 R Undefined Undefined Initial Value R/W Description All 0 R Reserved 1 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 1, 0 RCKSEL[1:0] Undefined R/W Operation clock select Operation clock can be selected from RTC_X1 or EXTAL. The setting of these bits should not be switched during operation. 00: Selects RTC_X1. 01: Selects EXTAL. 10: Setting prohibited. 11: Setting prohibited. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 743 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.3.20 Frequency Register H/L (RFRH/L) RFRH/L is a 16-bit readable/writable register. The "frequency comparison value" is set in RFC[18:0] so that a 128-Hz clock is generated when the realtime clock operates at the EXTAL clock frequency. Change the "frequency comparison value" according to the EXTAL clock frequency. The calculation method is shown below. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 SEL64 - - - - - - - - - - - - RFC[18:16] Initial value: Undefined R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Undefined Undefined Undefined 14 13 12 11 10 9 8 7 6 5 4 3 Bit: 15 18 17 16 R/W R/W R/W 2 1 0 RFC[15:0] Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 31 SEL64 Undefined R/W R/W Description 64-Hz Divider Select Indicates the operating clock that the EXTAL clock frequency is dividable by 64-Hz and not dividable by 128-Hz. 0: EXTAL clock frequency is dividable by 128-Hz. 1: EXTAL clock frequency is dividable by 64-Hz and not dividable by 128-Hz. 30 to 19  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 18 to 0 RFC[18:0] Undefined R/W Frequency comparison value Sets the comparison value to generate operation clock from the EXTAL clock frequency. Page 744 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 15 Realtime Clock Method for calculating "frequency comparison value".  EXTAL clock frequency is dividable by 128-Hz RFC[18:0]  (EXTAL clock frequency) / 128 Clear the SEL64 bit to 0 in this case.  EXTAL clock frequency is dividable by 64-Hz and not dividable by 128-Hz RFC[18:0]  (EXTAL clock frequency) / 64 Set the SEL64 bit to 1 in this case. (2) Setting Example Table 15.3 Setting Example Clock Frequency EXTAL R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SEL64 Setting Value RFC Setting Value 10 MHz 0 H'1312D 11 MHz 1 H'29F63 12 MHz 0 H'16E36 13 MHz 1 H'31975 Page 745 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.4 Operation Usage of this module is shown below. 15.4.1 Initial Settings of Registers after Power-On All the registers should be initialized after the power is turned on. 15.4.2 Setting Time Figure 15.2 shows how to set the time when the clock is stopped. Stop clock, select input clock, reset divider circuit Set seconds, minutes, hour, day, day of the week, month, and year Start clock Write 0 to START and 1 to RESET in the RCR2 register. When EXTAL is selected for input clock, set also RCR5 and RFRH/L. Order is irrelevant Write 1 to START in the RCR2 register Figure 15.2 Setting Time Page 746 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 15.4.3 Section 15 Realtime Clock Reading Time Figure 15.3 shows how to read the time. Disable the carry interrupt Clear the carry flag Write 0 to CIE in RCR1 Write 0 to CF in RCR1 (Set AF in RCR1 to 1 so that alarm flag is not cleared.) Read all the counter registers to be read Read RCR1 and check CF bit Yes Carry flag = 1? No (a) To read the time without using interrupts Clear the carry flag Enable the carry interrupt Clear the carry flag Write 1 to CIE in RCR1 Write 0 to CF in RCR1 (Set AF in RCR1 to 1 so that alarm flag is not cleared.) Read all the counter registers to be read Yes interrupt No Disable the carry interrupt Write 0 to CIE in RCR1 (b) To read the time using interrupts Figure 15.3 Reading Time If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 15.3 shows the method of reading the time without using interrupts; part (b) in figure 15.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 747 of 3092 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.4.4 Alarm Function Figure 15.4 shows how to use the alarm function. Clock running Disable alarm interrupt Write 0 to AIE in RCR1 to prevent errorneous interrupt Set alarm time Clear alarm flag Enable alarm interrupt Always reset, since the flag may have been set while the alarm time was being set. Write 1 to AIE in RCR1 Monitor alarm time (wait for interrupt or check alarm flag) Figure 15.4 Using Alarm Function Alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. Set the ENB bit in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is not placed to 0. When the clock and alarm times match, 1 is set in the AF bit in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is set in the AIE bit in RCR1, an interrupt is generated when an alarm occurs. The alarm flag is set when the clock and alarm times match. However, the alarm flag can be cleared by writing 0. Page 748 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 15 Realtime Clock 15.5 Usage Notes 15.5.1 Register Writing during Count The following registers cannot be written to during a count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCONT The count must be stopped before writing to any of the above registers. 15.5.2 Use of Realtime Clock Periodic Interrupts The method of using the periodic interrupt function is shown in figure 15.5. A periodic interrupt can be generated periodically at the interval set by bits PES2 to PES0 in RCR2. When the time set by bits PES2 to PES0 has elapsed, the PEF is set to 1. The PEF is cleared to 0 upon periodic interrupt generation or when bits PES2 to PES0 are set. Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. Set PES, clear PEF Set PES2 to PES0 and clear PEF to 0 in RCR2 Elapse of time set by PES Clear PEF Clear PEF to 0 Figure 15.5 Using Periodic Interrupt Function 15.5.3 Transition to Standby Mode after Setting Register When a transition to standby mode is made after registers in this module are set, sometimes counting is not performed correctly. In case the registers are set, be sure to make a transition to standby mode after performing one dummy read of the register. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 749 of 3092 Section 15 Realtime Clock 15.5.4 SH7268 Group, SH7269 Group Usage Notes when Writing to and Reading the Register  When reading a counter register such as the seconds counter and the RCR2 register after having writing to the given register, dummy-read the register twice before reading the actual value. The register contents from before the write are returned by the two dummy reads, and the third read returns the register contents reflecting the write.  Registers other than the above can be read immediately after a write and the written value is reflected. Page 750 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Section 16 Serial Communication Interface with FIFO This LSI has an eight-channel serial communication interface with FIFO that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication. 16.1 Features  Asynchronous serial communication:  Serial data communication is performed by start-stop in character units. This module can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Receive error detection: Parity, framing, and overrun errors  Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the serial port register when a framing error occurs.  Clock synchronous serial communication:  Serial data communication is synchronized with a clock signal. This module can communicate with other chips having a clock synchronous communication function. There is one serial data communication format.  Data length: 8 bits  Receive error detection: Overrun errors  Full duplex communication: The transmitting and receiving sections are independent, so this module can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions.  On-chip baud rate generator with selectable bit rates  Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 751 of 3092 Section 16 Serial Communication Interface with FIFO SH7268 Group, SH7269 Group  Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFOdata-full interrupt, and receive-error interrupts are requested independently.  When this module is not in use, it can be stopped by halting the clock supplied to it, saving power.  In asynchronous mode, on-chip modem control functions (RTS and CTS) (only channel 1 on SH7268, only channels 1, 5, and 7 on SH7269).  The quantity of data in the transmit and receive FIFO data registers and the number of receive errors of the receive data in the receive FIFO data register can be ascertained.  A time-out error (DR) can be detected when receiving in asynchronous mode.  In asynchronous mode, the base clock frequency can be either 16 or 8 times the bit rate.  When an internal clock is selected as a clock source and the SCK pin is used as an input pin in asynchronous mode, either normal mode or double-speed mode can be selected for the baud rate generator. Page 752 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Figure 16.1 shows a block diagram. Note that some channels do not have CTS and RTS pins. Module data bus SCFTDR (16 stages) SCSMR SCBRR SCLSR SCEMR Bus interface SCFRDR (16 stages) Peripheral bus SCFDR SCFCR RxD SCRSR Baud rate generator SCFSR SCTSR SCSCR P1φ/16 SCSPTR P1φ/64 Transmission/reception control TxD Clock Parity generation Parity check SCK P1φ P1φ/4 External clock TXI RXI ERI BRI CTS RTS Serial communication interface with FIFO [Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register SCEMR: Serial extension mode register SCFSR: Serial status register SCBRR: Bit rate register SCSPTR: Serial port register SCFCR: FIFO control register SCFDR: FIFO data count set register SCLSR: Line status register Figure 16.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 753 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.2 Input/Output Pins Table 16.1 shows the pin configuration. Table 16.1 Pin Configuration Channel Pin Name Symbol 0 to 7 1, 5, 7 * Function Serial clock pins SCK0 to SCK7 I/O Clock I/O Receive data pins RxD0 to RxD7 Input Receive data input Transmit data pins TxD0 to TxD7 Output Transmit data output Request to send pins RTS1, RTS5*, RTS7* I/O Request to send CTS1, CTS5*, CTS7* I/O Clear to send Clear to send pins Note: I/O Pins RTS5, CTS5, RTS7, and CTS7 cannot be used in the SH7268 Group. Page 754 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 16.3 Section 16 Serial Communication Interface with FIFO Register Descriptions This module has the following registers. Table 16.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 Serial mode register_0 SCSMR_0 R/W H'0000 H'E8007000 16 Bit rate register_0 SCBRR_0 R/W H'FF H'E8007004 8 Serial control register_0 SCSCR_0 R/W H'0000 H'E8007008 16 Transmit FIFO data register_0 SCFTDR_0 W Undefined H'E800700C 8 Serial status register_0 SCFSR_0 R/(W)*1 H'0060 Receive FIFO data register_0 SCFRDR_0 R Undefined H'E8007014 8 FIFO control register_0 SCFCR_0 R/W H'0000 H'E8007018 16 FIFO data count register_0 SCFDR_0 R H'0000 H'E800701C 16 Serial port register_0 SCSPTR_0 R/W H'0050 H'E8007020 16 Line status register_0 SCLSR_0 R/(W)*2 H'0000 H'E8007024 16 Serial extension mode register_0 SCEMR_0 R/W H'0000 H'E8007028 16 Serial mode register_1 SCSMR_1 R/W H'0000 H'E8007800 16 Bit rate register_1 SCBRR_1 R/W H'FF H'E8007804 8 Serial control register_1 SCSCR_1 R/W H'0000 H'E8007808 16 Transmit FIFO data register_1 SCFTDR_1 W Undefined H'E800780C 8 Serial status register_1 SCFSR_1 R/(W)*1 H'0060 Receive FIFO data register_1 SCFRDR_1 R Undefined H'E8007814 8 FIFO control register_1 SCFCR_1 R/W H'0000 H'E8007818 16 FIFO data count register_1 SCFDR_1 R H'0000 H'E800781C 16 Serial port register_1 R/W H'0050 H'E8007820 16 1 SCSPTR_1 2 H'E8007010 H'E8007810 16 16 Line status register_1 SCLSR_1 R/(W)* H'0000 H'E8007824 16 Serial extension mode register_1 SCEMR_1 R/W H'E8007828 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H'0000 Page 755 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Channel Register Name Abbreviation R/W Initial Value Address Access Size 2 Serial mode register_2 SCSMR_2 R/W H'0000 H'E8008000 16 Bit rate register_2 SCBRR_2 R/W H'FF H'E8008004 8 Serial control register_2 SCSCR_2 R/W H'0000 H'E8008008 16 Transmit FIFO data register_2 SCFTDR_2 W Undefined H'E800800C 8 Serial status register_2 SCFSR_2 R/(W)*1 H'0060 Receive FIFO data register_2 SCFRDR_2 R Undefined H'E8008014 8 FIFO control register_2 SCFCR_2 R/W H'0000 H'E8008018 16 FIFO data count register_2 SCFDR_2 R H'0000 H'E800801C 16 Serial port register_2 SCSPTR_2 R/W H'0050 H'E8008020 16 Line status register_2 SCLSR_2 R/(W)*2 H'0000 H'E8008024 16 Serial extension mode register_2 SCEMR_2 R/W H'0000 H'E8008028 16 Serial mode register_3 SCSMR_3 R/W H'0000 H'E8008800 16 Bit rate register_3 SCBRR_3 R/W H'FF H'E8008804 8 Serial control register_3 SCSCR_3 R/W H'0000 H'E8008808 16 Transmit FIFO data register_3 SCFTDR_3 W Undefined H'E800880C 8 Serial status register_3 SCFSR_3 R/(W)*1 H'0060 Receive FIFO data register_3 SCFRDR_3 R Undefined H'E8008814 8 FIFO control register_3 SCFCR_3 R/W H'0000 H'E8008818 16 FIFO data count register_3 SCFDR_3 R H'0000 H'E800881C 16 Serial port register_3 R/W H'0050 H'E8008820 16 3 SCSPTR_3 2 H'E8008010 H'E8008810 16 16 Line status register_3 SCLSR_3 R/(W)* H'0000 H'E8008824 16 Serial extension mode register_3 SCEMR_3 R/W H'E8008828 16 Page 756 of 3092 H'0000 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Channel Register Name Abbreviation R/W Initial Value Address Access Size 4 Serial mode register_4 SCSMR_4 R/W H'0000 H'E8009000 16 Bit rate register_4 SCBRR_4 R/W H'FF H'E8009004 8 Serial control register_4 SCSCR_4 R/W H'0000 H'E8009008 16 Transmit FIFO data register_4 SCFTDR_4 W Undefined H'E800900C 8 Serial status register_4 SCFSR_4 R/(W)*1 H'0060 Receive FIFO data register_4 SCFRDR_4 R Undefined H'E8009014 8 FIFO control register_4 SCFCR_4 R/W H'0000 H'E8009018 16 FIFO data count register_4 SCFDR_4 R H'0000 H'E800901C 16 Serial port register_4 SCSPTR_4 R/W H'0050 H'E8009020 16 Line status register_4 SCLSR_4 R/(W)*2 H'0000 H'E8009024 16 Serial extension mode register_4 SCEMR_4 R/W H'0000 H'E8009028 16 Serial mode register_5 SCSMR_5 R/W H'0000 H'E8009800 16 Bit rate register_5 SCBRR_5 R/W H'FF H'E8009804 8 Serial control register_5 SCSCR_5 R/W H'0000 H'E8009808 16 Transmit FIFO data register_5 SCFTDR_5 W Undefined H'E800980C 8 Serial status register_5 SCFSR_5 R/(W)*1 H'0060 Receive FIFO data register_5 SCFRDR_5 R Undefined H'E8009814 8 FIFO control register_5 SCFCR_5 R/W H'0000 H'E8009818 16 FIFO data count register_5 SCFDR_5 R H'0000 H'E800981C 16 Serial port register_5 R/W H'0050 H'E8009820 16 5 SCSPTR_5 2 H'E8009010 H'E8009810 16 16 Line status register_5 SCLSR_5 R/(W)* H'0000 H'E8009824 16 Serial extension mode register_5 SCEMR_5 R/W H'E8009828 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H'0000 Page 757 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Channel Register Name Abbreviation R/W Initial Value Address 6 Serial mode register_6 SCSMR_6 R/W H'0000 H'E800A000 16 Bit rate register_6 SCBRR_6 R/W H'FF H'E800A004 8 Serial control register_6 SCSCR_6 R/W H'0000 H'E800A008 16 Transmit FIFO data register_6 SCFTDR_6 W Undefined H'E800A00C 8 Serial status register_6 SCFSR_6 R/(W)*1 H'0060 Receive FIFO data register_6 SCFRDR_6 R Undefined H'E800A014 8 FIFO control register_6 SCFCR_6 R/W H'0000 H'E800A018 16 FIFO data count register_6 SCFDR_6 R H'0000 H'E800A01C 16 Serial port register_6 SCSPTR_6 R/W H'0050 H'E800A020 16 Line status register_6 SCLSR_6 R/(W)*2 H'0000 H'E800A024 16 Serial extension mode register_6 SCEMR_6 R/W H'0000 H'E800A028 16 Serial mode register_7 SCSMR_7 R/W H'0000 H'E800A800 16 Bit rate register_7 SCBRR_7 R/W H'FF H'E800A804 8 Serial control register_7 SCSCR_7 R/W H'0000 H'E800A808 16 Transmit FIFO data register_7 SCFTDR_7 W Undefined H'E800A80C 8 Serial status register_7 SCFSR_7 R/(W)*1 H'0060 Receive FIFO data register_7 SCFRDR_7 R Undefined H'E800A814 8 FIFO control register_7 SCFCR_7 R/W H'0000 H'E800A818 16 FIFO data count register_7 SCFDR_7 R H'0000 H'E800A81C 16 Serial port register_7 R/W H'0050 H'E800A820 16 7 SCSPTR_7 2 Access Size H'E800A010 16 H'E800A810 16 Line status register_7 SCLSR_7 R/(W)* H'0000 H'E800A824 16 Serial extension mode register_7 SCEMR_7 R/W H'E800A828 16 H'0000 Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that cannot be modified. 2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be modified. Page 758 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 16.3.1 Section 16 Serial Communication Interface with FIFO Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the receive FIFO data register (SCFRDR). The CPU cannot read or write to SCRSR directly. 16.3.2 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Receive FIFO Data Register (SCFRDR) SCFRDR is a 16-byte FIFO register that stores serial receive data. The reception of one byte of serial data is complete when the received data is moved from the receive shift register (SCRSR) to SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When SCFRDR is full of receive data, subsequent serial data is lost. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: R R R R R R R R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 759 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.3 Transmit Shift Register (SCTSR) SCTSR transmits serial data. Transmit data is loaded from the transmit FIFO data register (SCFTDR) into SCTSR, then the data is transmitted serially from the TxD pin, LSB (bit 0) first. After one data byte has been transmitted, the next transmit data is automatically loaded from SCFTDR into SCTSR and transmission is started again. The CPU cannot read from or write to SCTSR directly. 16.3.4 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Transmit FIFO Data Register (SCFTDR) SCFTDR is a 16-byte FIFO register that stores data for serial transmission. When the transmit shift register (SCTSR) empty is detected, transmit data written in the SCFTDR is moved to SCTSR and serial transmission is started. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. Page 760 of 3092 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: W W W W W W W W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 16.3.5 Section 16 Serial Communication Interface with FIFO Serial Mode Register (SCSMR) SCSMR specifies the serial communication format and selects the clock source for the baud rate generator. The CPU can always read from and write to SCSMR. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - C/A CHR PE O/E STOP - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W 15 to 8  All 0 R 1 0 CKS[1:0] 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 7 C/A 0 R/W Communication Mode Selects operating mode from asynchronous and clock synchronous modes. 0: Asynchronous mode 1: Clock synchronous mode 6 CHR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 R/W Character Length Selects 7-bit or 8-bit data length in asynchronous mode. In the clock synchronous mode, the data length is always 8 bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted. Page 761 of 3092 Section 16 Serial Communication Interface with FIFO SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. 4 O/E 0 R/W Parity Mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 1 0: Even parity* 2 1: Odd parity* Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Page 762 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select Select the internal clock source of the on-chip baud rate generator. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.8, Bit Rate Register (SCBRR). 00: P1 01: P1/4 10: P1/16 11: P1/64 Note: P1: Peripheral clock R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 763 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.6 Serial Control Register (SCSCR) SCSCR enables/disables the transmitter/receiver operation and interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - TIE RIE TE RE REIE - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 1 0 CKE[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial status register (SCFSR) is set to1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled* Note: Page 764 of 3092 * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 6 RIE 0 R/W Receive Interrupt Enable Enables or disables the receive FIFO data full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled 1: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled* Note: 5 TE 0 R/W * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Transmit Enable Enables or disables the serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1. Page 765 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receive Enable Enables or disables the serial receiver. 0: Receiver disabled*1 1: Receiver enabled*2 Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock is detected in clock synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1. 3 REIE 0 R/W Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: Page 766 of 3092 * ERI or BRI interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable Select the clock source and enable or disable clock output from the SCK pin. Depending on CKE[1:0], the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clock synchronous mode, set the C/A bit in SCSMR to 1, and then set CKE[1:0].  Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is either 16 or 8 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is either 16 or 8 times the bit rate.) 11: Setting prohibited  Clock synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 767 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.7 Serial Status Register (SCFSR) SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive FIFO data register, and the lower 8 bits indicate the status flag indicating operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). The PER flag (bits 15 to 12 and bit 2) and the FER flag (bits 11 to 8 and bit 3) are read-only bits that cannot be written. Bit: 15 14 13 12 11 10 PER[3:0] Initial value: R/W: 0 R 0 R 0 R 9 8 FER[3:0] 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR 0 R 0 R 0 1 1 0 R/(W)* R/(W)* R/(W)* R/(W)* 0 0 R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15 to 12 PER[3:0] 0000 R Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 after the ER bit in SCFSR is set, represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER[3:0] shows 0000. 11 to 8 FER[3:0] 0000 R Number of Framing Errors Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 after the ER bit in SCFSR is set, represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER[3:0] shows 0000. Page 768 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 7 ER 0 R/(W)* Receive Error Description Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity.*1 0: Receiving is in progress or has ended normally [Clearing conditions]  ER is cleared to 0 a power-on reset  ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred. [Setting conditions]  ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive operation*2  ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCFRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 769 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 6 TEND 1 R/(W)* Transmit End Description Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition]  TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR*1 1: End of transmission [Setting conditions]  TEND is set to 1 when the chip is a power-on reset  TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR)  TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Note: 1. Do not use this bit as a transmit end flag when the direct memory access controller writes data to SCFTDR due to a TXI interrupt request. Page 770 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 5 TDFE 1 R/(W)* Transmit FIFO Data Empty Description Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG[1:0] bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions]  TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written  TDFE is cleared to 0 when direct memory access controller is activated by transmit FIFO data empty interrupt (TXI) and write data exceeding the specified transmission trigger number to SCFTDR 1: The quantity of transmit data in SCFTDR is less than or equal to the specified transmission trigger number*1 [Setting conditions]  TDFE is set to 1 by a power-on reset  TDFE is set to 1 when the quantity of transmit data in SCFTDR becomes less than or equal to the specified transmission trigger number as a result of transmission Note: 1. Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 771 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 4 BRK 0 R/(W)* Break Detection Description Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions]  BRK is cleared to 0 when the chip is a power-on reset  BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK 1: Break signal received*1 [Setting condition]  BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data Note: 1. When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. 3 FER 0 R Framing Error Indication Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions]  FER is cleared to 0 when the chip undergoes a power-on reset  FER is cleared to 0 when no framing error is present in the next data read from SCFRDR 1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition]  Page 772 of 3092 FER is set to 1 when a framing error is present in the next data read from SCFRDR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 2 PER 0 R Parity Error Indication Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions]  PER is cleared to 0 when the chip undergoes a power-on reset  PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1: A receive parity error occurred in the next data read from SCFRDR [Setting condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 PER is set to 1 when a parity error is present in the next data read from SCFRDR Page 773 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 1 RDF 0 R/(W)* Receive FIFO Data Full Description Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG[1:0] bits in the FIFO control register (SCFCR). 0: The quantity of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions]  RDF is cleared to 0 by a power-on reset, standby mode  RDF is cleared to 0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written  RDF is cleared to 0 when the direct memory access controller is activated by receive FIFO data full interrupt (RXI) and read SCFRDR until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number 1: The quantity of receive data in SCFRDR is more than the specified receive trigger number [Setting condition]  RDF is set to 1 when a quantity of receive data more than the specified receive trigger number is stored in SCFRDR*1 Note: 1. As SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read when RDF is 1 becomes the specified receive trigger number. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR. Page 774 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 0 DR 0 R/(W)* Receive Data Ready Description Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clock synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions]  DR is cleared to 0 when the chip undergoes a power-on reset  DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written.  DR is cleared to 0 when all receive data are read after the direct memory access controller is activated by receive FIFO data full interrupt (RXI). 1: Next receive data has not been received [Setting condition]  DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the 1 elapse of 15 ETU from the last stop bit.* Note: 1. This is equivalent to 1.5 frames with the 8bit, 1-stop-bit format. (ETU: elementary time unit) Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 775 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.8 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that is used with the CKS1 and CKS0 bits in the serial mode register (SCSMR) and the BGDM and ABCS bits in the serial extension mode register (SCEMR) to determine the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. Each channel has independent baud rate generator control, so different values can be set in eight channels. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The SCBRR setting is calculated as follows:  Asynchronous mode: When baud rate generator operates in normal mode (when the BGDM bit of SCEMR is 0): N= P1φ × 106 − 1 (Operation on a base clock with a frequency of 16 times 64 × 22n-1 × B the bit rate) N= P1φ × 106 − 1 (Operation on a base clock with a frequency of 8 times 32 × 22n-1 × B the bit rate) When baud rate generator operates in double speed mode (when the BGDM bit of SCEMR is 1): N= P1φ × 106 − 1 (Operation on a base clock with a frequency of 16 times 32 × 22n-1 × B the bit rate) N= P1φ × 106 − 1 (Operation on a base clock with a frequency of 8 times 16 × 22n-1 × B the bit rate) Page 776 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO  Clock synchronous mode: N= B: N: P1: n: P1φ × 106 − 1 8 × 22n-1 × B Bit rate (bits/s) SCBRR setting for baud rate generator (0  N  255) (The setting must satisfy the electrical characteristics.) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n  0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.) Table 16.3 SCSMR Settings SCSMR Settings n Clock Source CKS[1] CKS[0] 0 P1 0 0 1 P1/4 0 1 2 P1/16 1 0 3 P1/64 1 1 The bit rate error in asynchronous mode is given by the following formula: When baud rate generator operates in normal mode (the BGDM bit of SCEMR is 0): Error (%) = Error (%) = P1φ × 106 (N + 1) × B × 64 × 22n-1 − 1 × 100 (Operation on a base clock with a frequency of 16 times the bit rate) P1φ × 106 − 1 × 100 (Operation on a base clock with a frequency of (N + 1) × B × 32× 22n-1 8 times the bit rate) When baud rate generator operates in double speed mode (the BGDM bit of SCEMR is 1): Error (%) = P1φ × 106 − 1 × 100 (Operation on a base clock with a frequency of (N + 1) × B × 32× 22n-1 16 times the bit rate) Error (%) = P1φ × 106 − 1 × 100 (Operation on a base clock with a frequency of (N + 1) × B × 16× 22n-1 8 times the bit rate) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 777 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Table 16.4 lists the sample SCBRR settings in asynchronous mode in which a base clock frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator operates in normal mode (the BGDM bit in SCEMR is 1), and table 16.5 lists the sample SCBRR settings in clock synchronous mode. Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0) P1 (MHz) 50 60 Bit Rate (bits/s) n N Error () 110 3 221 –0.02 150 3 162 300 3 600 66.67 n N Error () n N Error () –0.15 3 194 0.16 3 216 0.01 80 0.47 3 97 –0.35 3 108 –0.45 2 162 -0.15 2 194 0.16 2 216 0.01 1200 2 80 0.47 2 97 –0.35 2 108 -0.45 2400 1 162 -0.15 1 194 0.16 1 216 0.01 4800 1 80 0.47 1 97 –0.35 1 108 –0.45 9600 0 162 -0.15 0 194 0.16 0 216 0.01 19200 0 80 0.47 0 97 –0.35 0 108 –0.45 31250 0 49 0.00 0 59 0.00 0 66 –0.50 38400 0 40 –0.76 0 48 –0.35 0 53 0.47 [Legend] Blank: No setting possible : Setting possible, but error occurs Note: The error rate should be  1 . Page 778 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Table 16.5 Bit Rates and SCBRR Settings (Clock Synchronous Mode) P1 (MHz) 50 Bit Rate (bits/s) n N 500   1000 3 2500 60 66.67 n N n N 194 3 233   3 77 3 93 3 103 5000 2 155 2 187 2 207 10000 2 77 2 93 2 103 25000 1 124 1 149 1 166 50000 1 62 1 74 1 82 100000 0 124 0 149 0 166 250000 0 49 0 59 0 66 500000 0 24 0 29   1000000   0 14   2000000       [Legend] Blank: No setting possible : Setting possible, but error occurs R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 779 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Table 16.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 16.7 lists the maximum bit rates in asynchronous mode when the external clock input is used. Table 16.8 lists the maximum bit rates in clock synchronous mode when the external clock input is used (when tScyc  12tpcyc*). Note: * Make sure that the electrical characteristics of this LSI and that of a connected LSI are satisfied. Table 16.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P1 (MHz) BGDM ABCS n N Maximum Bit Rate (bits/s) 50 0 0 0 0 1562500 1 0 0 3125000 0 0 0 3125000 1 0 0 6250000 0 0 0 0 1875000 1 0 0 3750000 1 0 0 0 3750000 1 0 0 7500000 0 0 0 2083333 1 0 0 4166667 0 0 0 4166667 1 0 0 8333333 1 60 66.67 0 1 Page 780 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Table 16.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) P1 (MHz) External Input Clock (MHz) 50 12.5000 60 66.67 15.0000 16.6667 Settings ABCS Maximum Bit Rate (bits/s) 0 781250 1 1562500 0 937500 1 1875000 0 1041667 1 2083333 Table 16.8 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode, tScyc  12 tpcyc) P1 (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 50 4.1667 4166666.7 60 5.0000 5000000.0 66.67 5.5556 5555555.5 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 781 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.9 FIFO Control Register (SCFCR) SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. Bit: Initial value: R/W: 15 14 13 12 11 - - - - - 0 R 0 R 0 R 0 R 0 R 10 9 8 RSTRG[2:0] 0 R/W 0 R/W 7 6 5 RTRG[1:0] 0 R/W Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved 0 R/W 0 R/W 4 3 TTRG[1:0] 0 R/W 0 R/W 2 1 0 MCE TFRST RFRST LOOP 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 8 RSTRG[2:0] 000 R/W RTS Output Active Trigger When the quantity of receive data in receive FIFO data register (SCFRDR) becomes more than the number shown below, RTS signal is set to high. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 Page 782 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 7, 6 RTRG[1:0] 00 R/W Receive FIFO Data Trigger  Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO register (SCFRDR) is increased more than the set trigger number shown below.  Asynchronous mode  Clock synchronous mode 00: 1 01: 4 10: 8 11: 14 00: 1 01: 2 10: 8 11: 14 Note: 5, 4 TTRG[1:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00 R/W In clock synchronous mode, to transfer the receive data using the direct memory access controller, set the receive trigger number to 1. If set to other than 1, CPU must read the receive data left in SCFRDR. Transmit FIFO Data Trigger Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag is set to 1 when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of empty bytes in SCFTDR when the TDFE flag is set to 1. Page 783 of 3092 Section 16 Serial Communication Interface with FIFO SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 3 MCE 0 R/W Modem Control Enable Enables modem control signals CTS and RTS. The MCE bit should always be cleared to 0 for channels 0 and 2 to 7 on the SH7268 and channels 0, 2, 3, 4, and 6 on the SH7269, and when in clock synchronous mode on the SH7268 and SH7269 regardless of the channel. 0: Modem signal disabled* 1: Modem signal enabled Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. 2 TFRST 0 R/W Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset. 1 RFRST 0 R/W Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset. 0 LOOP 0 R/W Loop-Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and internally connects the RTS pin and CTS pin and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled Page 784 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.10 FIFO Data Count Set Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. Bit: Initial value: R/W: 15 14 13 - - - 0 R 0 R 0 R 12 11 10 9 8 T[4:0] 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved 7 6 5 - - - 0 R 0 R 0 R 4 3 2 1 0 0 R 0 R R[4:0] 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 12 to 8 T[4:0] 00000 R 7 to 5  All 0 R T4 to T0 bits indicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 R[4:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00000 R R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data. Page 785 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.11 Serial Port Register (SCSPTR) SCSPTR controls input/output and data of pins multiplexed to the functions of this module. Bits 7 and 6 can control input/output data of RTS pin. Bits 5 and 4 can control input/output data of CTS pin. Bits 3 and 2 can control input/output data of SCK pin. Bits 1 and 0 can input data from RxD pin and output data to TxD pin, so they control break of serial transmitting/receiving. The CPU can always read and write to SCSPTR. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IOSPB2DT Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 RTSIO 0 R/W RTS Port Input/Output Indicates input or output of the serial port RTS pin. When the RTS pin is actually used as a port outputting the RTSDT bit value, the MCE bit in SCFCR should be cleared to 0. 0: RTSDT bit value not output to RTS pin 1: RTSDT bit value output to RTS pin 6 RTSDT 1 R/W RTS Port Data Indicates the input/output data of the serial port RTS pin. Input/output is specified by the RTSIO bit. For output, the RTSDT bit value is output to the RTS pin. The RTS pin status is read from the RTSDT bit regardless of the RTSIO bit setting. However, RTS input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level Page 786 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 5 CTSIO 0 R/W CTS Port Input/Output Indicates input or output of the serial port CTS pin. When the CTS pin is actually used as a port outputting the CTSDT bit value, the MCE bit in SCFCR should be cleared to 0. 0: CTSDT bit value not output to CTS pin 1: CTSDT bit value output to CTS pin 4 CTSDT 1 R/W CTS Port Data Indicates the input/output data of the serial port CTS pin. Input/output is specified by the CTSIO bit. For output, the CTSDT bit value is output to the CTS pin. The CTS pin status is read from the CTSDT bit regardless of the CTSIO bit setting. However, CTS input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level 3 SCKIO 0 R/W SCK Port Input/Output Indicates input or output of the serial port SCK pin. When the SCK pin is actually used as a port outputting the SCKDT bit value, the CKE[1:0] bits in SCSCR should be cleared to 0. 0: SCKDT bit value not output to SCK pin 1: SCKDT bit value output to SCK pin 2 SCKDT 0 R/W SCK Port Data Indicates the input/output data of the serial port SCK pin. Input/output is specified by the SCKIO bit. For output, the SCKDT bit value is output to the SCK pin. The SCK pin status is read from the SCKDT bit regardless of the SCKIO bit setting. However, SCK input/output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 787 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 1 SPB2IO 0 R/W Serial Port Break Input/Output Indicates input or output of the serial port TxD pin. When the TxD pin is actually used as a port outputting the SPB2DT bit value, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value not output to TxD pin 1: SPB2DT bit value output to TxD pin 0 SPB2DT Page 788 of 3092 0 R/W Serial Port Break Data Indicates the input data of the RxD pin and the output data of the TxD pin used as serial ports. Input/output is specified by the SPB2IO bit. When the TxD pin is set to output, the SPB2DT bit value is output to the TxD pin. The RxD pin status is read from the SPB2DT bit regardless of the SPB2IO bit setting. However, RxD input and TxD output must be set in the PFC. 0: Input/output data is low level 1: Input/output data is high level R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - ORER 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally*1 [Clearing conditions]  ORER is cleared to 0 when the chip is a power-on reset  ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1: An overrun error has occurred*2 [Setting condition]  ORER is set to 1 when the next serial receiving is finished while the receive FIFO is full of 16-byte receive data. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) retains the data before an overrun error has occurred, and the next received data is discarded. When the ORER bit is set to 1, the next serial reception cannot be continued. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 789 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.3.13 Serial Extension Mode Register (SCEMR) The CPU can always read from or write to SCEMR. Setting the BGDM bit in this register to 1 allows the baud rate generator in this module operates in double-speed mode when asynchronous mode is selected (by setting the C/A bit in SCSMR to 0) and an internal clock is selected as a clock source and the SCK pin is set as an input pin (by setting the CKE[1:0] bits in SCSCR to 00). Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - BGDM - - - - - - ABCS 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 BGDM 0 R/W Baud Rate Generator Double-Speed Mode When the BGDM bit is set to 1, the baud rate generator in this module operates in double-speed mode. This bit is valid only when asynchronous mode is selected by setting the C/A bit in SCSMR to 0 and an internal clock is selected as a clock source and the SCK pin is set as an input pin by setting the CKE[1:0] bits in SCSCR to 00. In other settings, this bit is invalid (the baud rate generator operates in normal mode regardless of the BGDM setting). 0: Normal mode 1: Double-speed mode 6 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ABCS 0 R/W Base Clock Select in Asynchronous Mode This bit selects the base clock frequency within a bit period in asynchronous mode. This bit is valid only in asynchronous mode (when the C/A bit in SCSMR is 0). 0: Base clock frequency is 16 times the bit rate 1: Base clock frequency is 8 times the bit rate Page 790 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 16.4 Operation 16.4.1 Overview Section 16 Serial Communication Interface with FIFO For serial communication, this module has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. This module has a 16-stage FIFO buffer for both transmission and receptions, reducing the overhead of the CPU, and enabling continuous high-speed communication. Furthermore, channel 1 on the SH7268, and channels 1, 5, and 7 on the SH7269, have RTS and CTS signals for use as modem control signals. The transmission format is selected in the serial mode register (SCSMR), as shown in table 16.9. The clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.10. (1) Asynchronous Mode  Data length is selectable: 7 or 8 bits  Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.  In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks.  The number of stored data bytes is indicated for both the transmit and receive FIFO registers.  An internal or external clock can be selected as the clock source.  When an internal clock is selected, this module operates using the clock of on-chip baud rate generator.  When an external clock is selected, the external clock input must have a frequency 16 or 8 times the bit rate. (The on-chip baud rate generator is not used.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 791 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO (2) Clock Synchronous Mode  The transmission/reception format has a fixed 8-bit data length.  In receiving, it is possible to detect overrun errors (ORER).  An internal or external clock can be selected as the clock source.  When an internal clock is selected, this module operates using the clock of the on-chip baud rate generator, and outputs this clock to external devices as the synchronous clock.  When an external clock is selected, this module operates on the input external synchronous clock not using the on-chip baud rate generator. Table 16.9 SCSMR Settings and Communication Formats SCSMR Settings Communication Format Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 8 bits Not set 1 bit Asynchronous 1 1 2 bits 0 Set 1 1 0 2 bits 0 7 bits Not set 1 1 x x 0 x 1 bit 2 bits Set 1 1 1 bit 1 bit 2 bits Clock synchronous 8 bits Not set None [Legend] x: Don't care Page 792 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Table 16.10 SCSMR and SCSCR Settings and Clock Source Selection SCSMR SCSCR Transmit/Receive Clock Bit 7 C/A Bit 1, 0 CKE[1:0] Mode Clock Source SCK Pin Function 0 00 Asynchronous Internal This module does not use the SCK pin. 01 1 Outputs a clock with a frequency 16/8 times the bit rate 10 External 11 Setting prohibited 0x 10 11 Clock synchronous Inputs a clock with frequency 16/8 times the bit rate Internal Outputs the serial clock External Inputs the serial clock Setting prohibited [Legend] x: Don't care Note: When using the baud rate generator in double-speed mode (BGMD = 1), select asynchronous mode by setting the C/A bit to 0, and select an internal clock as a clock source and the SCK pin is not used (the CKE[1:0] bits set to 00). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 793 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections in this module are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. This module monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, this module synchronizes at the falling edge of the start bit. This module samples each data bit on the eighth or fourth pulse of a clock with a frequency 16 or 8 times the bit rate. Receive data is latched at the center of each bit. Idle state (mark state) 1 (LSB) Serial data 0 Start bit 1 bit D0 (MSB) D1 D2 D3 D4 D5 D6 D7 Transmit/receive data 7 or 8 bits 1 0/1 1 1 Parity bit Stop bit 1 bit or none 1 or 2 bits One unit of transfer data (character or frame) Figure 16.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) Page 794 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 16 Serial Communication Interface with FIFO Transmit/Receive Formats Table 16.11 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 16.11 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR PE STOP Serial Transmit/Receive Format and Frame Length 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 START 8-bit data STOP 0 0 1 START 8-bit data STOP STOP 0 1 0 START 8-bit data P STOP 0 1 1 START 8-bit data P STOP STOP 1 0 0 START 7-bit data STOP 1 0 1 START 7-bit data STOP STOP 1 1 0 START 7-bit data P STOP 1 1 1 START 7-bit data P STOP STOP [Legend] START: Start bit STOP: Stop bit P: Parity bit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 795 of 3092 Section 16 Serial Communication Interface with FIFO (2) SH7268 Group, SH7269 Group Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in the serial control register (SCSCR). For clock source selection, refer to table 16.10, SCSMR and SCSCR Settings and Clock Source Selection. When an external clock is input at the SCK pin, it must have a frequency equal to 16 or 8 times the desired bit rate. When this module operates on an internal clock, it can output a clock signal on the SCK pin. The frequency of this output clock is 16 or 8 times the desired bit rate. (3) Transmitting and Receiving Data  Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize this module as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. The operation becomes unreliable if the clock is stopped. Page 796 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Figure 16.3 shows a sample flowchart for initialization. Start of initialization Clear the TE and RE bits in SCSCR to 0 [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. Set the TFRST and RFRST bits in SCFCR to 1 [2] Set the data transfer format in SCSMR. After reading flags ER, DR, and BRK in SCFSR, and each flag in SCLSR, write 0 to clear them Set the CKE1 and CKE0 bits in SCSCR (leaving bits TIE, RIE, TE, and RE cleared to 0) [1] Set data transfer format in SCSMR [2] Set the BGDM and ABCS bits in SCEMR Set value in SCBRR [3] Set the RTRG1, RTRG0, TTRG1, TTRG0, and MCE bits in SCFCR, and clear TFRST and RFRST bits to 0 Set the general I/O port external pins used SCK, TxD, RxD [4] Set the TE and RE bits in SCSCR to 1, and set the TIE, RIE, and REIE bits [5] End of initialization [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [4] Sets the general I/O port external pins used. Set as RxD input at receiving and TxD at transmission. However, no setting for SCK pin is required when CKE[1:0] is 00. In the case when internal synchronous clock output is set, the SCK pin starts outputting the clock at this stage. [5] Set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. Figure 16.3 Sample Flowchart for Initialization R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 797 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO  Transmitting Serial Data (Asynchronous Mode) Figure 16.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling transmission. Start of transmission [1] Status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and read 1 from the TDFE and TEND flags, then clear to 0. The quantity of transmit data that can be written is 16 - (transmit trigger set number). Read TDFE flag in SCFSR TDFE = 1? No Yes Write transmit data in SCFTDR, and read 1 from TDFE flag and TEND flag in SCFSR, then clear to 0 All data transmitted? [1] No [2] Yes [3] Break output during serial transmission: To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. Read TEND flag in SCFSR TEND = 1? [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. No Yes Break output? No Yes Clear SPB2DT to 0 and set SPB2IO to 1 [3] In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by the upper 8 bits of SCFDR. Clear TE bit in SCSCR to 0 End of transmission Figure 16.4 Sample Flowchart for Transmitting Serial Data Page 798 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO In serial transmission, this module operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the data is transferred from SCFTDR to the transmit shift register (SCTSR). Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCFTDR transmit data is checked at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 799 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Figure 16.5 shows an example of the operation for transmission. 1 Serial data Start bit 0 Data D0 D1 D7 Parity bit Stop bit Start bit 0/1 1 0 Parity bit Data D0 D1 D7 Stop bit 0/1 1 Idle state (mark state) 1 TDFE TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 16.5 Example of Transmit Operation (8-Bit Data, Parity, 1 Stop Bit) 4. When modem control is enabled on channel 1 on the SH7268, or on channel 1, 5, or 7 on the SH7269, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 16.6 shows an example of the operation when modem control is used. Parity Stop bit bit Start bit Serial data TxD 0 D0 D1 D7 0/1 Start bit 0 D0 D1 D7 0/1 CTS Drive high before stop bit Figure 16.6 Example of Operation Using Modem Control (CTS) Page 800 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO  Receiving Serial Data (Asynchronous Mode) Figures 16.7 and 16.8 show sample flowcharts for serial reception. Use the following procedure for serial data reception after enabling reception. [1] Receive error handling and break detection: Start of reception Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No [1] Yes Error handling [2] Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 All data received? Yes Clear RE bit in SCSCR to 0 End of reception [2] Status check and receive data read: Read SCFSR and check that RDF flag = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by a receive FIFO data full interrupt (RXI). RDF = 1? No Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD pin. [3] [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR. Figure 16.7 Sample Flowchart for Receiving Serial Data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 801 of 3092 Section 16 Serial Communication Interface with FIFO SH7268 Group, SH7269 Group Error handling No ORER = 1? Yes Overrun error handling No ER = 1? Yes Receive error handling • Whether a framing error or parity error has occurred in the receive data that is to be read from the receive FIFO data register (SCFRDR) can be ascertained from the FER and PER bits in the serial status register (SCFSR). • When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. No BRK = 1? Yes Break handling No DR = 1? Yes Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR to 0 End Figure 16.8 Sample Flowchart for Receiving Serial Data (cont) Page 802 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO In serial reception, this module operates as described below. 1. The transmission line is monitored, and if a 0 start bit is detected, internal synchronization is performed and reception is started. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, this module carries out the following checks. A. Stop bit check: Checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. Checks whether receive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: Checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: Checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing error occurs, reception is not suspended. 4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 803 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Figure 16.9 shows an example of the operation for reception. 1 Serial data Start bit Data D0 0 D1 D7 Parity bit Stop bit Start bit 0/1 1 0 Parity bit Data D0 D1 D7 0/1 Stop bit 1 1 Idle state (mark state) RDF RXI interrupt request FER Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler One frame ERI interrupt request generated by receive error Figure 16.9 Example of Receive Operation (8-Bit Data, Parity, 1 Stop Bit) 5. When modem control is enabled on channel 1 on the SH7268, or on channel 1, 5, or 7 on the SH7269, the RTS signal is output when SCFRDR is empty. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR exceeds the number set for the RTS output active trigger. Figure 16.10 shows an example of the operation when modem control is used. Start bit Serial data RxD 0 Parity bit D0 D1 D2 D7 0/1 Start bit 1 0 Parity bit D0 D1 D7 0/1 RTS Figure 16.10 Example of Operation Using Modem Control (RTS) Page 804 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 16.4.3 Section 16 Serial Communication Interface with FIFO Operation in Clock Synchronous Mode In clock synchronous mode, data is transmitted and received in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The transmitter and receiver in this module are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 16.11 shows the general format in clock synchronous serial communication. One unit of transfer data (character or frame) * * Serial clock LSB Serial data Don't care Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Note: * High except in continuous transfer Figure 16.11 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clock synchronous mode, data is received in synchronization with the rising edge of the serial clock. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 805 of 3092 Section 16 Serial Communication Interface with FIFO (1) SH7268 Group, SH7269 Group Transmit/Receive Formats The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as the transmit/receive clock. When this module operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When transmission or reception is not performed, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive FIFO data trigger number. (3) Transmitting and Receiving Data  Initialization (Clock Synchronous Mode) Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize this module. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents. Page 806 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Figure 16.12 shows a sample flowchart for initialization. Start of initialization Clear TE and RE bits in SCSCR to 0 [1] [2] Set the data transfer format in SCSMR. Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer [3] Set CKE[1:0]. After reading ER, DR, and BRK flags in SCFSR, write 0 to clear them Set data transfer format in SCSMR [1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set CKE[1:0] in SCSCR (leaving TIE, RIE, TE, and RE bits cleared to 0) [3] Set value in SCBRR [4] Set RTRG[1:0] and TTRG[1:0] bits in SCFCR, and clear TFRST and RFRST bits to 0 Set the general I/O port external pins used SCK, TxD, RxD [5] Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits [6] [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. [5] Sets the general I/O port external pins used. Set as RxD input at receiving and TxD at transmission. [6] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE, and REIE bits to enable the TxD, RxD, and SCK pins to be used. When transmitting, the TxD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCK pin at this point. End of initialization Figure 16.12 Sample Flowchart for Initialization R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 807 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO  Transmitting Serial Data (Clock Synchronous Mode) Figure 16.13 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling transmit operation. Start of transmission [1] Status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Clear the TDFE and TEND flags to 0 after reading them as 1. Read TDFE flag in SCFSR TDFE = 1? No [2] Serial transmission continuation procedure: Yes Write transmit data to SCFTDR, read TDFE and TEND flags in SCFSR as 1, and then clear the flags to 0 All data transmitted? To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [1] No [2] Yes Read TEND flag in SCFSR TEND = 1? No Yes Clear TE bit in SCSCR to 0 End of transmission Figure 16.13 Sample Flowchart for Transmitting Serial Data Page 808 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO In serial transmission, this module operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the data is transferred from SCFTDR to the transmit shift register (SCTSR). Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is generated. If clock output mode is selected, eight synchronous clock pulses are output. If an external clock source is selected, data is output in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCFTDR transmit data is checked at the timing for sending the MSB (bit 7). If data is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the next frame is started. If there is no data, the TxD pin holds the state after the TEND flag in SCFSR is set to 1 and the MSB (bit 7) is sent. 4. After the end of serial transmission, the SCK pin is held in the high state. Figure 16.14 shows an example of transmit operation. Serial clock LSB Bit 0 Serial data Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDFE TEND TXI interrupt request Data written to SCFTDR TXI and TDFE flag cleared interrupt to 0 by TXI interrupt request handler One frame Figure 16.14 Example of Transmit Operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 809 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO  Receiving Serial Data (Clock Synchronous Mode) Figures 16.15 and 16.16 show sample flowcharts for receiving serial data. Use the following procedure for serial data reception after enabling receive operation. When switching from asynchronous mode to clock synchronous mode without initialization, make sure that ORER, PER, and FER are cleared to 0. Start of reception [1] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. Read ORER flag in SCLSR ORER = 1? Yes [1] No Read RDF flag in SCFSR No Error handling [2] RDF = 1? [2] Status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by a receive FIFO data full interrupt (RXI). Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCFRDR. However, the RDF bit is cleared to 0 automatically when an RXI interrupt activates the direct memory access controller to read the data in Figure 16.15 Sample Flowchart for Receiving Serial Data (1) Page 810 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Error handling No ORER = 1? Yes Overrun error handling Clear ORER flag in SCLSR to 0 End Figure 16.16 Sample Flowchart for Receiving Serial Data (2) In serial reception, this module operates as described below. 1. Reception is started in synchronization with serial clock input or output. 2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After the data reception, whether the receive data can be loaded from SCRSR into SCFRDR or not is checked. If this check is passed, the RDF flag is set to 1 and the received data is stored in SCFRDR. If the check is not passed (overrun error is detected), further reception is prevented. 3. After setting RDF to 1, if the receive FIFO data full interrupt enable bit (RIE) is set to 1 in SCSCR, a receive-data-full interrupt (RXI) request is generated. If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in SCSCR is also set to 1, a break interrupt (BRI) request is generated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 811 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO Figure 16.17 shows an example of receive operation. Serial clock LSB Serial data Bit 7 MSB Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDF ORER RXI interrupt request Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler RXI interrupt request BRI interrupt request by overrun error One frame Figure 16.17 Example of Receive Operation Page 812 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO  Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode) Figure 16.18 shows a sample flowchart for transmitting and receiving serial data simultaneously. Use the following procedure for the simultaneous transmission/reception of serial data, after enabling transmit/receive operation. [1] Status check and transmit data write: Initialization Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR. Clear the TDFE and TEND flags to 0 after reading them as 1. The transition of the TDFE flag from 0 to 1 can also be identified by a transmit FIFO data Start of transmission and reception Read TDFE flag in SCFSR empty interrupt (TXI). [2] Receive error handling: No TDFE = 1? Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. Yes Write transmit data to SCFTDR, read TDFE and TEND flags in SCFSR as 1, and then clear the flags to 0 [1] [3] Status check and receive data read: Read SCFSR and check that RDF flag = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by a Read ORER flag in SCLSR Yes ORER = 1? [2] No Error handling Read RDF flag in SCFSR No RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 No [3] receive FIFO data full interrupt (RXI). [4] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0. All data received? Yes Clear TE and RE bits in SCSCR to 0 [4] Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1. End of transmission and reception Figure 16.18 Sample Flowchart for Transmitting/Receiving Serial Data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 813 of 3092 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16.5 Interrupts This module has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive FIFO data full (RXI), and break (BRI). Table 16.12 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXI interrupt request is generated. The direct memory access controller can be activated and data transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the CPU. When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set to 1, an RXI interrupt request is generated. The direct memory access controller can be activated and data transfer performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU. The RXI interrupt request caused by the DR flag is generated only in asynchronous mode. When the RIE bit is set to 0 and the REIE bit is set to 1, this module requests only an ERI or a BRI interrupt without requesting an RXI interrupt. The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data in SCFRDR. Table 16.12 Interrupt Sources Interrupt Source Description Direct Memory Access Controller Priority on Activation Reset Release BRI Interrupt initiated by break (BRK) or overrun error (ORER) Not possible ERI Interrupt initiated by receive error (ER) Not possible RXI Interrupt initiated by receive FIFO data full (RDF) or Possible data ready (DR) TXI Interrupt initiated by transmit FIFO data empty (TDFE) Page 814 of 3092 High Possible Low R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 16.6 Section 16 Serial Communication Interface with FIFO Usage Notes Note the following when using this module. 16.6.1 SCFTDR Writing and TDFE Flag The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG[1:0] in the FIFO control register (SCFCR). After the TDFE flag is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE flag clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR). 16.6.2 SCFRDR Reading and RDF Flag The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG[1:0] in the FIFO control register (SCFCR). After RDF flag is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR exceeds the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. The RDF flag should therefore be cleared to 0 after being read as 1 after reading the number of the received data in the receive FIFO data register (SCFRDR) which is less than the trigger number. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 815 of 3092 Section 16 Serial Communication Interface with FIFO 16.6.3 SH7268 Group, SH7269 Group Restriction on Direct Memory Controller Usage When the direct memory access controller writes data to SCFTDR due to a TXI interrupt request, the state of the TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer end flag in such a case. 16.6.4 Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the receive operation is continued. 16.6.5 Sending a Break Signal The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work. During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and SPB2DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD pin. 16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) This module operates on a base clock with a frequency 16 or 8 times the bit rate. In reception, the falling edge of the start bit is sampled at the base clock to perform synchronization internally. Receive data is latched at the rising edge of the eighth or fourth base clock pulse. When this module operates on a base clock with a frequency 16 times the bit rate, the receive data is sampled at the timing shown in figure 16.19. Page 816 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 16 Serial Communication Interface with FIFO 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 16.19 Receive Data Sampling Timing in Asynchronous Mode (Operation on a Base Clock with a Frequency 16 Times the Bit Rate) The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = (0.5 − D − 0.5 1 ) − (L − 0.5) F − (1 + F) × 100 % 2N N Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16 or 8) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0, D = 0.5 and N = 16, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 − 1/(2 × 16)) × 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 817 of 3092 Section 16 Serial Communication Interface with FIFO 16.6.7 SH7268 Group, SH7269 Group Selection of Base Clock in Asynchronous Mode In this LSI, when asynchronous mode is selected, the base clock frequency within a bit period can be set to the frequency 16 or 8 times the bit rate by setting the ABCS bit in SCEMR. Note that, however, if the base clock frequency 8 times the bit rate is used, receive margin is decreased as calculated using equation 1 in section 16.6.6, Receive Data Sampling Timing and Receive Margin (Asynchronous Mode). If the desired bit rate can be set simply by setting SCBRR and the CKS1and CKS0 bits in SCSMR, it is recommended to use the base clock frequency within a bit period 16 times the bit rate (by setting the ABCS bit in SCEMR to 0). If an internal clock is selected as a clock source and the SCK pin is not used, the bit rate can be increased without decreasing receive margin by selecting double-speed mode for the baud rate generator (setting the BGDM bit in SCEMR to 1). Page 818 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Section 17 Renesas Serial Peripheral Interface This LSI includes two-channel Renesas serial peripheral interfaces. This module is capable of full-duplex serial communication. 17.1 Features This module has the following features.  SPI transfer functions Use of MOSI (master out/slave in), MISO (master in/slave out), SSL (slave select), and RSPCK (SPI clock) signals allow for serial communications through SPI operation (four-wire method). Capable of serial communications in master/slave mode Supports mode fault error detection (only in SPI slave mode) Supports overrun error detection (only in SPI slave mode) Switching of the polarity of the serial transfer clock Switching of the clock phase of serial transfer  Data format MSB-first/LSB-first selectable Transfer bit-length is selectable as 8, 16, or 32 bits.  Bit rate RSPCK can be divided by a maximum of 4096 in master mode RSPCK can be generated by dividing P1 by the on-chip baud rate generator. An externally input clock can be used as a serial clock.  Buffer configuration 8 bytes for transmission and 32 bytes for reception. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 819 of 3092 Section 17 Renesas Serial Peripheral Interface SH7268 Group, SH7269 Group  SSL control function One SSL signal for each channel In master mode, outputs SSL signal. In slave mode, inputs SSL signal. Controllable delay from SSL output assertion to RSPCK operation (RSPCK delay) Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units) Controllable delay from RSPCK stoppage to SSL output negation (SSL negation delay) Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units) Controllable wait for next-access SSL output assertion (next-access delay) Range: 1 to 8 RSPCK cycles (set in RSPCK-cycle units) Function for changing SSL polarity  Control in master transfer A transfer of up to four commands can be executed sequentially in looped execution. For each command, the following can be set: SSL signal value, bit rate, RSPCK polarity/phase, transfer data length, LSB/MSB first, burst, RSPCK delay, SSL negation delay, and next-access delay. A transfer can be initiated by writing to the transmit buffer. A transfer can be initiated by clearing the SPTEF bit. MOSI signal value specifiable in SSL negation  Interrupt sources Maskable interrupt sources: Receive interrupt (receive buffer full) Transmit interrupt (transmit buffer empty) Error interrupt (mode fault, overrun)  Others Provides loop back mode Provides a function for disabling (initializing) this module Page 820 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bus interface Peripheral bus Module data bus SPRX (FIFO structure) 32 bytes SPBR SPCR SPTX (FIFO structure) 8 bytes SSLP Baud rate generator SPPCR SPSR P1φ SPDCR SPCKD Shift register SSLND SPND SPCMD SPBFCR Selector SPBFDR MOSI Normal Loopback MISO Normal Master Transmission/ reception controller Slave Clock Master Loopback Loopback Slave SPTI SPRI SPEI Normal SSL RSPCK [Legend] SPCR: SSLP: SPPCR: SPSR: SPSCR: SPSSR: SPDCR: SPCKD: SSLND: SPND: Control register Slave select polarity register Pin control register Satus register Sequence control register Sequence status register Data control register Cock delay register Slave select negate delay register Next-access delay register SPCMD: SPBR: SPTX: SPRX: SPBFCR: SPBFDR: SPTI: SPRI: SPEI: Command register Bit rate register Transmission buffer (Data register write side) Receive buffer (Data register read side) Buffer control register Buffer data count setting register Transmit interrupt Receive interrupt Error interrupt Figure 17.1 Block Diagram (for One Channel) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 821 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.2 Input/Output Pins Table 17.1 shows the pin configuration. This module automatically switches the input/output direction of the SSL pin. SSL is set as an output in master mode and as an input in slave mode. Pins RSPCK, MOSI, and MISO are automatically set as inputs or outputs according to the setting of master or slave and the level input on SSL (see section 17.4.2, Pin Control). Table 17.1 Pin Configuration Channel Pin Name Pin Name I/O Function 0 Clock pin RSPCK0 I/O Clock input/output Master transmit data pin MOSI0 I/O Master transmit data Slave transmit data pin MISO0 I/O Slave transmit data Slave select 0 pin SSL00 I/O Slave selection Clock pin RSPCK1 I/O Clock input/output Master transmit data pin MOSI1 I/O Master transmit data Slave transmit data pin MISO1 I/O Slave transmit data Slave select 0 pin SSL10 I/O Slave selection 1 Note: In the description of the pins, the channel is omitted and pin names are described as RSPICK, MOSI, MISO, and SSL. Page 822 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.3 Section 17 Renesas Serial Peripheral Interface Register Descriptions Table 17.2 shows the register configuration. These registers enable this module to perform the following controls: specifying master/slave modes, specifying a transfer format, and controlling the transmitter and receiver. Table 17.2 Register Configuration Channel Register Name Abbreviation*1 R/W Initial Value Address 0 Access Size Control register_0 SPCR_0 R/W H'00 H'E800E000 8, 16 Slave select polarity register_0 SSLP_0 R/W H'00 H'E800E001 8, 16 Pin control register_0 SPPCR_0 R/W H'00 H'E800E002 8, 16 2 Status register_0 SPSR_0 R/(W)* H'60 H'E800E003 8, 16 Data register_0 SPDR_0 R/W Undefined H'E800E004 8, 16, 32 Sequence control register_0 SPSCR_0 R/W H'00 H'E800E008 8, 16 Sequence status register_0 SPSSR_0 R H'00 H'E800E009 8, 16 Bit rate register_0 SPBR_0 R/W H'FF H'E800E00A 8, 16 Data control register_0 SPDCR_0 R/W H'20 H'E800E00B 8, 16 Clock delay register_0 SPCKD_0 R/W H'00 H'E800E00C 8, 16 Slave select negation delay SSLND_0 register_0 R/W H'00 H'E800E00D 8, 16 Next-access delay register_0 SPND_0 R/W H'00 H'E800E00E 8 Command register_00 SPCMD_00 R/W H'070D H'E800E010 16 Command register_01 SPCMD_01 R/W H'070D H'E800E012 16 Command register_02 SPCMD_02 R/W H'070D H'E800E014 16 Command register_03 SPCMD_03 R/W H'070D H'E800E016 16 Buffer control register_0 SPBFCR_0 R/W H’00 H'E800E020 8, 16 Buffer data count setting register_0 SPBFDR_0 R H'0000 H'E800E022 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 823 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Channel Register Name Abbreviation*1 R/W Initial Value Address Access Size 1 Control register_1 SPCR_1 R/W H'00 H'E800E800 8, 16 Slave select polarity register_1 SSLP_1 R/W H'00 H'E800E801 8, 16 Pin control register_1 SPPCR_1 R/W H'00 H'E800E802 8, 16 Status register_1 SPSR_1 R/(W)*2 H'60 H'E800E803 8, 16 Data register_1 SPDR_1 R/W Undefined H'E800E804 8, 16, 32 Sequence control register_1 SPSCR_1 R/W H'00 H'E800E808 8, 16 Sequence status register_1 SPSSR_1 R H'00 H'E800E809 8, 16 Bit rate register_1 SPBR_1 R/W H'FF H'E800E80A 8, 16 Data control register_1 SPDCR_1 R/W H'20 H'E800E80B 8, 16 Clock delay register_1 SPCKD_1 R/W H'00 H'E800E80C 8, 16 Slave select negation delay SSLND_1 register_1 R/W H'00 H'E800E80D 8, 16 Next-access delay register_1 SPND_1 R/W H'00 H'E800E80E 8 Command register_10 SPCMD_10 R/W H'070D H'E800E810 16 Command register_11 SPCMD_11 R/W H'070D H'E800E812 16 Command register_12 SPCMD_12 R/W H'070D H'E800E814 16 Command register_13 SPCMD_13 R/W H'070D H'E800E816 16 Buffer control register_1 SPBFCR_1 R/W H’00 H’E800E820 8, 16 Buffer data count setting register_1 SPBFDR_1 R H'0000 H'E800E822 16 Notes: 1. In the description of the register names, the channel is omitted. 2. Only 0 can be written to clear the flag. Page 824 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.3.1 Section 17 Renesas Serial Peripheral Interface Control Register (SPCR) SPCR sets the operating mode. If the MSTR and MODFEN bits are changed while the function of this module is enabled by setting the SPE bit to 1, subsequent operations cannot be guaranteed. Bit: 7 6 3 2 1 0 SPRIE SPE SPTIE SPEIE 5 4 MSTR MOD FEN ⎯ ⎯ Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 SPRIE 0 R/W Receive Interrupt Enable Enables or disables generation of receive interrupt requests (SPRI) when the number of receive data units in the receive buffer (SPRX) is equal to or greater than the specified receive buffer data triggering number and the SPRF flag in SPSR is set to 1. 0: Disables the generation of receive interrupt requests. 1: Enables the generation of receive interrupt requests. 6 SPE 0 R/W Function Enable Setting this bit to 1 enables the module function. When the MODF bit in the status register (SPSR) is 1, the SPE bit cannot be set to 1 (see section 17.4.6, Error Detection). Setting the SPE bit to 0 disables the module function, and initializes a part of the module function (see section 17.4.7, Initialization). 0: Disables the module function 1: Enables the module function R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 825 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 5 SPTIE 0 R/W Transmit Interrupt Enable Enables or disables generation of transmit interrupt requests (SPTI) when the number of transmit data units in the transmit buffer (SPTX) is equal to or less than the specified transmit buffer data triggering number and the SPTEF flag in SPSR is set to 1. 0: Disables the generation of transmit interrupt requests. 1: Enables the generation of transmit interrupt requests. 4 SPEIE 0 R/W Error Interrupt Enable Enables or disables the generation of error interrupt requests when this module detects a mode fault error and sets the MODF bit in the status register (SPSR) to 1, or when this module detects an overrun error and sets the OVRF bit in SPSR to 1 (see section 17.4.6, Error Detection). 0: Disables the generation of error interrupt requests. 1: Enables the generation of error interrupt requests. Note: This bit is valid only in SPI slave mode. 3 MSTR 0 R/W Master/Slave Mode Select Selects master/slave mode. According to MSTR bit settings, this module determines the direction of pins RSPCK, MOSI, MISO, and SSL pins. 0: Slave mode 1: Master mode 2 MODFEN 0 R/W Mode Fault Error Detection Enable Enables or disables the detection of a mode fault error (see section 17.4.6, Error Detection). 0: Disables the detection of a mode fault error 1: Enables the detection of a mode fault error Note: This bit is valid only in SPI slave mode. When master mode is specified with the MSTR bit, this bit should always be cleared to 0. 1, 0  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. Page 826 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.3.2 Section 17 Renesas Serial Peripheral Interface Slave Select Polarity Register (SSLP) SSLP sets the polarity of the SSL signal. If the SSL0P bit is changed while the function of this module is enabled by setting the SPE bit in the control register (SPCR) to 1, subsequent operations cannot be guaranteed. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SSL0P 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 0 SSL0P 0 R/W SSL Signal Polarity Setting Sets the polarity of the SSL signal. The value of SSL0P indicates the active polarity of the SSL signal. 0: SSL signal 0-active 1: SSL signal 1-active R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 827 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.3 Pin Control Register (SPPCR) SPPCR sets the modes of the pins. If the contents of this register are changed while the function of this module is enabled by setting the SPE bit in the control register (SPCR) to 1, subsequent operations cannot be guaranteed. Bit: Initial value: R/W: 7 6 ⎯ ⎯ 0 R 0 R 5 4 MOIFE MOIFV 0 R/W 0 R/W 3 2 1 0 ⎯ ⎯ ⎯ SPLP 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 5 MOIFE 0 R/W MOSI Idle Value Fixing Enable Fixes the MOSI output value when this module in master mode is in an SSL negation period (including the SSL retention period during a burst transfer). When MOIFE is 0, this module outputs the last data from the previous serial transfer during the SSL negation period. When MOIFE is 1, this module outputs the fixed value set in the MOIFV bit to the MOSI bit. 0: MOSI output value equals final data from previous transfer 1: MOSI output value equals the value set in the MOIFV bit 4 MOIFV 0 R/W MOSI Idle Fixed Value If the MOIFE bit is 1 in master mode, this module, according to MOIFV bit settings, determines the MOSI signal value during the SSL negation period (including the SSL retention period during a burst transfer). 0: MOSI Idle fixed value equals 0 1: MOSI Idle fixed value equals 1 3 to 1  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. Page 828 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 0 SPLP 0 R/W Loopback When the SPLP bit is set to 1, this module shuts off the path between the MISO pin and the shift register, and between the MOSI pin and the shift register, and connects (reverses) the input path and the output path for the shift register. 0: Normal mode 1: Loopback mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 829 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.4 Status Register (SPSR) SPSR indicates the operating status. Bit: 7 SPRF Initial value: R/W: 6 5 TEND SPTEF 0 R 1 R 1 R 4 3 2 1 0 ⎯ ⎯ MODF ⎯ OVRF 0 R 0 R 0 R/(W)* 0 R 0 R/(W)* Note: * Only 0 can be written to clear the flag after reading 1. Bit Bit Name Initial Value R/W Description 7 SPRF 0 R Receive Buffer Full Flag Indicates that the number of receive data units in the receive buffer (SPRX) is equal to or greater than the receive buffer data triggering number specified in the buffer control register (SPBFCR). 0: The number of receive data units in the receive buffer is less than the receive buffer data triggering number. 1: The number of receive data units in the receive buffer is equal to or greater than the receive buffer data triggering number. [Clearing conditions]  The receive buffer data is read until the number of data units in the receive buffer becomes less than the specified receive buffer data triggering number.  Receive buffer data reset is enabled.  Power-on reset [Setting condition]  Page 830 of 3092 The number of data units in the receive buffer is equal to or greater than the specified receive buffer data triggering number. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 6 TEND 1 R Transmit End This bit is set to 1 when transmission is completed, and this bit is 0 when transmission is not completed. [Clearing condition]  When transmit data are moved from the transmit register to the shift register. [Setting condition]  5 SPTEF 1 R When the number of data units in the transmit buffer (SPTX) is zero when a serial transfer is completed. Transmit Buffer Empty Flag Indicates that the number of transmit data units in the transmit buffer (SPTX) is equal to or less than the transmit buffer data triggering number specified in the buffer control register (SPBFCR). 0: The number of transmit data units in the transmit buffer is equal to or greater than the specified transmit buffer data triggering number. 1: The number of transmit data units in the transmit buffer is less than the specified transmit buffer data triggering number. [Clearing condition]  When data is written to the transmit buffer until the number of transmit data units in the transmit buffer exceeds the specified transmit buffer data triggering number. [Setting conditions] 4, 3  All 0 R  When the number of transmit data units in the transmit buffer is less than the specified transmit buffer data triggering number.  When transmit buffer data reset is enabled.  Power-on reset Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 831 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W 2 MODF 0 R/(W)* Mode Fault Error Flag Description Indicates the occurrence of a mode fault error. If the MODFEN bit is set to 1 when this module is in slave mode and the SSL pin is negated before the RSPCK cycle necessary for data transfer ends, this module detects a mode fault error. The active level of the SSL signal is determined by the SSL0P bit in the slave select polarity register (SSLP). [Clearing conditions]  SPSR is read when the MODF bit is 1, and then 0 is written to the MODF bit.  Power-on reset 0: No mode fault error occurred 1: A mode fault error occurred Note: This bit is valid only in SPI slave mode.  1 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 0 OVRF 0 R/(W)* Overrun Error Flag Indicates the occurrence of an overrun error. If a serial transfer ends when there is not enough space for receiving the specified length of data in the receive buffer (SPRX), this module detects an overrun error, and sets the OVRF bit to 1. [Clearing conditions]  SPSR is read when the OVRF bit is 1, and then 0 is written to the OVRF bit.  Power-on reset 0: No overrun error occurred 1: An overrun error occurred Note: This bit is valid only in SPI slave mode. Note: * Only 0 can be written to clear the flag after reading 1. Page 832 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.3.5 Section 17 Renesas Serial Peripheral Interface Data Register (SPDR) SPDR is a buffer that holds data for transmission and reception. The transmit buffer (SPTX) and receive buffer (SPRX) are independent and are mapped to SPDR. SPDR should be read or written to in byte, word, or longword units according to the access width specification bit (SPLW) in the data control register (SPDCR). The bit length to be used is determined by the data length specification bits (SPB3 to SPB0) in the command register (SPCMD). When data is written to SPDR, the data will be written to the transmit buffer from SPDR if the transmit buffer has a space equal to or more than the SPDR access width. If there is not enough space, data will not be written to the transmit buffer. Even if an attempt is made to write data to the buffer, the data is ignored. When data is read from SPDR, receive data in the receive buffer will be read. If SPDR is read when there is no receive data in the receive buffer, the read value is undefined. When SPDR is written to with the longword-, word-, or byte-access width, the transmit data should be written to the following bits. If data is written to the other bits, the data is not guaranteed.  Longword: Bits 31 to 0  Word: Bits 31 to 16  Byte: Bits 31 to 24 When SPDR is read with the longword-, word-, or byte-access width, the receive data should be read from the following bits. If data is read from the other bits, the data is not guaranteed.  Longword: Bits 31 to 0  Word: Bits 31 to 16  Byte: Bits 31 to 24 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 833 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16 Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 8 7 6 5 4 3 2 1 0 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 17.3.6 Sequence Control Register (SPSCR) SPSCR sets the sequence controlled method when this module operates in master mode. If the contents of SPSCR are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SPS LN1 SPS LN0 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. Page 834 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 1 SPSLN1 0 R/W Sequence Length Specification 0 SPSLN0 0 R/W These bits specify a sequence length when this module in master mode performs sequential operations. This module in master mode changes command registers 0 to 3 (SPCMD0 to SPCMD3) to be referenced and the order in which they are referenced according to the sequence length that is set in the SPSLN1 and SPSLN0 bits. The relationship among the setting of bits SPSLN1 and SPSLN0, sequence length, and SPCMD0 to SPCMD3 referenced by this module is shown below. In slave mode, SPCMD0 is always referenced. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Sequence Length Referenced SPCMD # 00: 1 00… 01: 2 010… 10: 3 0120… 11: 4 01230… Page 835 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.7 Sequence Status Register (SPSSR) SPSSR indicates the sequence control status when this module operates in master mode. Bit: Initial value: R/W: 7 6 5 4 3 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved 1 0 SPCP1 SPCP0 0 R 0 R The write value should always be 0. Otherwise, operation cannot be guaranteed. 1 SPCP1 0 R Command Pointer 0 SPCP0 0 R During sequence control, these bits indicate one of the command registers 0 to 3 (SPCMD0 to SPCMD3) that is currently pointed to by the pointer. The relationship between the setting of SPCP1 and SPCP0 and SPCMD0 to SPCMD3 is shown below. For the sequence control, see section 17.4.8 (1) (c), Sequence Control. 00: SPCMD0 01: SPCMD1 10: SPCMD2 11: SPCMD3 Page 836 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.3.8 Section 17 Renesas Serial Peripheral Interface Bit Rate Register (SPBR) SPBR sets the bit rate in master mode. If the contents of SPBR are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3 2 1 0 SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W When this module is used in slave mode, the bit rate depends on the bit rate of the input clock regardless of the settings of SPBR and BRDV. The bit rate is determined by combinations of SPBR settings and the bit settings in the BRDV1 and BRDV0 bits in the command registers (SPCMD0 to SPCMD3). The equation for calculating the bit rate is given below. In the equation, n denotes an SPBR setting (0, 1, 2, …, 255), and N denotes bit settings in the bits BRDV1 and BRDV0 (0, 1, 2, 3). f (P1φ) Bit rate = 2 × (n + 1) × 2N Table 17.3 shows examples of the relationship between the SPBR register and BRDV1 and BRDV0 bit settings. Table 17.3 Relationship between SPBR and BRDV1 and BRDV0 Settings Bit Rate SPBR (n) BRDV[1:0] (N) Division Ratio P1 = 50 MHz P1 = 60 MHz P1 = 66.67 MHz 0 0 2 25.0 Mbps 30.0 Mbps 33.33 Mbps 1 0 4 12.5 Mbps 15.0 Mbps 16.67 Mbps 2 0 6 8.33 Mbps 10.0 Mbps 11.11 Mbps 3 0 8 6.25 Mbps 7.50 Mbps 8.33 Mbps 4 0 10 5.00 Mbps 6.00 Mbps 6.67 Mbps 5 0 12 4.16 Mbps 5.00 Mbps 5.56 Mbps 5 1 24 2.08 Mbps 2.50 Mbps 2.78 Mbps 5 2 48 1.04 Mbps 1.25 Mbps 1.39 Mbps 5 3 96 520 kbps 625 kbps 694.48 kbps 255 3 4096 12.20 kbps 14.64 kbps 16.28 kbps R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 837 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.9 Data Control Register (SPDCR) SPDCR selects the width to access SPDR from longword-, word-, and byte-width, and enables or disables dummy data transmission for the master mode operation. If the contents of SPDCR are changed while bit TEND in the status register (SPSR) indicates that transmission is not completed, the subsequent operation cannot be guaranteed. Bit: 7 6 5 TXDMY SPLW1 SPLW0 Initial value: 0 R/W: R/W 0 R/W 1 R/W 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 TXDMY 0 R/W Dummy Data Transmission Enable Enables or disables dummy data transmission. When communication is performed with this bit set to 1, dummy data is transmitted from the MOSI pin and a serial communication can be performed even if there is no transmit data in the transmit buffer. Specifically, if there is no transmit data in the transmit buffer and this bit is set to 1, dummy data is transferred to the shift register. If this bit is set to 1 and a transfer is performed, the transmitted dummy data is undefined. 0: Disables dummy data transmission. 1: Enables dummy data transmission. Note: This bit is valid only in the master mode. Page 838 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 6 SPLW1 0 R/W Access Width Specification 5 SPLW0 1 R/W Specifies the width for accessing the data register (SPDR). If the length of data transferred to SPDR does not agree with these bit settings, operation is not guaranteed. 00: Setting prohibited 01: SPDR is accessed in bytes. 10: SPDR is accessed in words. 11: SPDR is accessed in longwords. 4 to 0  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 839 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.10 Clock Delay Register (SPCKD) SPCKD sets a period from the beginning of SSL signal assertion to RSPCK oscillation (RSPCK delay) when the SCKDEN bit in the command register (SPCMD) is 1. If the contents of SPCKD are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed. When using this module in slave mode, set B'000 to SCKDL2 to SCKDL0. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ SCK DL2 SCK DL1 SCK DL0 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 2 SCKDL2 0 R/W RSPCK Delay Setting 1 SCKDL1 0 R/W 0 SCKDL0 0 R/W These bits set an RSPCK delay value when the SCKDEN bit in SPCMD is 1. The relationship between the setting of SCKDL2 to SCKDL0 and the RSPCK delay value is shown below. 000: 1 RSPCK 001: 2 RSPCK 010: 3 RSPCK 011: 4 RSPCK 100: 5 RSPCK 101: 6 RSPCK 110: 7 RSPCK 111: 8 RSPCK Page 840 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.11 Slave Select Negation Delay Register (SSLND) SSLND sets a period (SSL negation delay) from the transmission of a final RSPCK edge to the negation of the SSL signal during a serial transfer by this module in master mode. If the contents of SSLND are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed. When using this module in slave mode, set B'000 to SLNDL2 to SLNDL0. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ SLN DL2 SLN DL1 SLN DL0 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 2 SLNDL2 0 R/W SSL Negation Delay Setting 1 SLNDL1 0 R/W 0 SLNDL0 0 R/W These bits set an SSL negation delay when the SLNDEN bit in SPCMD is 1. The relationship between the setting of SLNDL2 to SLNDL0 and the SSL negation delay value is shown below. 000: 1 RSPCK 001: 2 RSPCK 010: 3 RSPCK 011: 4 RSPCK 100: 5 RSPCK 101: 6 RSPCK 110: 7 RSPCK 111: 8 RSPCK R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 841 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.12 Next-Access Delay Register (SPND) SPND sets a non-active period (next-access delay) after termination of a serial transfer when the SPNDEN bit in the command register (SPCMD) is 1. If the contents of SPND are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be guaranteed. When using this module in slave mode, set B'000 to SPNDL2 to SPNDL0. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ SPN DL2 SPN DL1 SPN DL0 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 2 SPNDL2 0 R/W Next-Access Delay Setting 1 SPNDL1 0 R/W 0 SPNDL0 0 R/W These bits set a next-access delay when the SPNDEN bit in SPCMD is 1. The relationship between the setting of SPNDL2 to SPNDL0 and the next-access delay value is shown below. 000: 1 RSPCK  2 P1 001: 2 RSPCK  2 P1 010: 3 RSPCK  2 P1 011: 4 RSPCK  2 P1 100: 5 RSPCK  2 P1 101: 6 RSPCK  2 P1 110: 7 RSPCK  2 P1 111: 8 RSPCK  2 P1 Page 842 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.13 Command Register (SPCMD) Each channel has four command registers (SPCMD0 to SPCMD3). SPCMD0 to SPCMD3 are used to set a transfer format for master mode operation. Some of the bits in SPCMD0 are used to set a transfer mode for slave mode operation. In master mode, this module sequentially references SPCMD0 to SPCMD3 according to the settings in bits SPSLN1 and SPSLN0 in the sequence control register (SPSCR), and executes the serial transfer that is set in the referenced SPCMD. While bit TEND in the status register (SPSR) indicates that transmission is not completed, correct operation of this module cannot be guaranteed if SPCMD is changed that is referred by this module. SPCMD referenced by this module in master mode can be checked by means of bits SPCP1 and SPCP0 in the sequence status register (SPSSR). When the function of this module in slave mode is enabled, operation cannot be guaranteed if the value set in SPCMD0 is changed. Bit: 15 14 13 12 11 10 9 8 SCK DEN SLN DEN SPN DEN LSBF SPB3 SPB2 SPB1 SPB0 Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 3 2 1 Bit: 7 6 5 4 SSLKP ⎯ ⎯ ⎯ Initial value: 0 R/W: R/W 0 R 0 R 0 R BRDV1 BRDV0 CPOL 1 R/W 1 R/W 0 R/W 0 CPHA 1 R/W Bit Bit Name Initial Value R/W Description 15 SCKDEN 0 R/W RSPCK Delay Setting Enable Sets the period from the point this module in master mode activates the SSL signal until the RSPCK starts oscillation (RSPCK delay). If the SCKDEN bit is 0, this module sets the RSPCK delay to 1 RSPCK. If the SCKDEN bit is 1, this module starts the oscillation of RSPCK at an RSPCK delay in compliance with the clock delay register (SPCKD) settings. To use this module in slave mode, the SCKDEN bit should be set to 0. 0: An RSPCK delay of 1 RSPCK 1: An RSPCK delay equal to SPCKD settings. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 843 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 14 SLNDEN 0 R/W SSL Negation Delay Setting Enable Sets the period from the point this module in master mode stops RSPCK oscillation until this module sets the SSL signal inactive (SSL negation delay). If the SLNDEN bit is 0, this module sets the SSL negation delay to 1 RSPCK. If the SLNDEN bit is 1, this module negates the SSL signal at an SSL negation delay in compliance with the slave select negation delay register (SSLND) settings. To use this module in slave mode, the SLNDEN bit should be set to 0. 0: An SSL negation delay of 1 RSPCK 1: An SSL negation delay equal to SSLND settings. 13 SPNDEN 0 R/W Next-Access Delay Enable Sets the period from the point this module in master mode terminates a serial transfer and sets the SSL signal inactive until this module enables the SSL signal assertion for the next access (next-access delay). If the SPNDEN bit is 0, this module sets the next-access delay to 1 RSPCK + 2 P1. If the SPNDEN bit is 1, this module inserts a next-access delay in compliance with the next-access delay register (SPND) settings. To use this module in slave mode, the SPNDEN bit should be set to 0. 0: A next-access delay of 1 RSPCK  2 P1 1: A next-access delay equal to SPND settings. Page 844 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 12 LSBF 0 R/W LSB First Sets the data format in master mode or slave mode to MSB first or LSB first. 0: MSB first 1: LSB first 11 SPB3 0 R/W Data Length Setting 10 SPB2 1 R/W 9 SPB1 1 R/W These bits set a transfer data length in master mode or slave mode. 8 SPB0 1 R/W 0100 to 0111: 8 bits 1111: 16 bits 0010, 0011: 32 bits Others: Setting prohibited 7 SSLKP 0 R/W SSL Signal Level Keeping When this module in master mode performs a serial transfer, this bit specifies whether the SSL signal level for the current command is to be kept or negated between the SSL negation timing associated with the current command and the SSL assertion timing associated with the next command. To use this module in slave mode, the SSLKP bit should be set to 0. 0: Negates the SSL signal upon completion of transfer. 1: Keeps the SSL signal level from the end of the transfer until the beginning of the next access. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 845 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 6 to 4  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 3 BRDV1 1 R/W Bit Rate Division Setting 2 BRDV0 1 R/W These bits are used to determine the bit rate. A bit rate is determined by combinations of bits BRDV1 and BRDV 0 and the settings in the bit rate register (SPBR) (see section 17.3.8, Bit Rate Register (SPBR)). The settings in SPBR determine the base bit rate. The settings in bits BRDV1 and BRDV0 are used to select a bit rate which is obtained by dividing the base bit rate by 1, 2, 4, or 8. In the bits SPCMD0 to SPCMD3, different BRDV1 and BRDV0 settings can be specified. This permits the execution of serial transfers at a different bit rate for each command. 00: Select the base bit rate 01: Select the base bit rate divided by 2 10: Select the base bit rate divided by 4 11: Select the base bit rate divided by 8 Page 846 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 1 CPOL 0 R/W RSPCK Polarity Setting Sets an RSPCK polarity in master or slave mode. When data communication is performed between the Renesas serial peripheral interface module and the other modules, the same RSPCK polarity should be set for both modules. 0: RSPCK = 0 when idle 1: RSPCK = 1 when idle 0 CPHA 1 R/W RSPCK Phase Setting Sets an RSPCK phase in master or slave mode. When data communication is performed between the Renesas serial peripheral interface module and the other modules, the same RSPCK phase should be set for both modules. 0: Data sampling on odd edge, data variation on even edge 1: Data variation on odd edge, data sampling on even edge R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 847 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.14 Buffer Control Register (SPBFCR) SPBFCR resets the number of data units in the transmit buffer (SPTX) or receive buffer (SPRX) and sets the number of triggering data units. Bit: 7 6 TXRST RXRST Initial value: 0 R/W: R/W 0 R/W 5 4 TXTRG[1:0] 0 R/W 0 R/W 3 ⎯ 0 R 2 1 0 RXTRG[2:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 TXRST 0 R/W Transmit Buffer Data Reset Resets the transmit buffer to an empty state. Transmit data in the transmit buffer becomes invalid when this bit is set to 1. 0: Disables the reset operation*. 1: Enables the reset operation Note: The reset operation is performed after a power-on reset. 6 RXRST 0 R/W Receive Buffer Data Reset Resets the receive buffer to an empty state. Receive data in the receive buffer becomes invalid when this bit is set to 1. 0: Disables the reset operation*. 1: Enables the reset operation Note: The reset operation is performed after a power-on reset. Page 848 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Initial Value Bit Bit Name 5, 4 TXTRG[1:0] 00 R/W Description R/W Transmit Buffer Data Triggering Number Specifies the timing at which the transmit buffer empty state is determined, that is when the SPTEF flag in the status register is set. When the number of bytes of data in the transmit buffer (SPTX) is equal to or less than the specified triggering number, the SPTEF flag is set to 1. 00: 7 bytes (1)* 01: 6 bytes (2)* 10: 4 bytes (4)* 11: 0 bytes (8)* Note: The value in the parenthesis shows the number of available bytes in the transmit buffer (SPTX). 3  0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 2 to 0 RXTRG[2:0] 000 R/W Receive Buffer Data Triggering Number Specifies the timing at which the receive buffer full state is determined, that is when the SPRF flag in the status register is set. When the number of bytes of data in the receive buffer (SPRX) is equal to or greater than the specified triggering number, the SPRF flag is set to 1. 000: 1 byte (31)* 001: 2 bytes (30)* 010: 4 bytes (28)* 011: 8 bytes (24)* 100: 16 bytes (16)* 101: 24 bytes (8)* 110: 32 bytes (0)* 111: 5 bytes (27)* Note: * The value in the parenthesis shows the number of available bytes in the receive buffer (SPRX). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 849 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.3.15 Buffer Data Count Setting Register (SPBFDR) SPBFDR indicates the number of data units stored in the transmit buffer (SPTX) and receive buffer (SPRX). The upper eight bits indicate the number of transmit data units in SPTX and the lower eight bits indicate the number of receive data units in SPRX. Bit: 15 14 13 12 ⎯ ⎯ ⎯ ⎯ 0 R 0 R 0 R 0 R 0 R 5 4 3 Initial value: R/W: Bit: 7 6 ⎯ ⎯ 0 R 0 R Initial value: R/W: 11 10 9 8 T[3:0] 0 R 0 R 0 R 2 1 0 0 R 0 R 0 R R[5:0] 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 12  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 11 to 8 T[3:0] 0000 R Indicates the number of bytes of data to be transmitted in SPTX. B'0000 indicates that SPTX is empty. B'1000 indicates that SPTX is full. 7, 6  All 0 R Reserved The write value should always be 0. Otherwise, operation cannot be guaranteed. 5 to 0 R[5:0] 000000 R Shows the number of bytes of received data in SPTX. B'000000 indicates that SPRX is empty. B'100000 indicates that SPRX is full. Page 850 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.4 Section 17 Renesas Serial Peripheral Interface Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data. 17.4.1 Overview of Operations This module is capable of serial transfers in slave mode and master mode. A particular mode of this module can be selected by using the MSTR bit in the control register (SPCR). Table 17.4 gives the relationship between the modes and SPCR settings, and a description of each mode. Table 17.4 Relationship between Modes and SPCR and Description of Each Mode Mode Slave (SPI Operation) Master (SPI Operation) MSTR bit setting 0 1 MODFEN bit setting 0 or 1 0 RSPCK signal Input Output MOSI signal Input Output MISO signal Output/Hi-Z Input SSL signal Input Output SSL polarity modification function Supported Supported Transfer rate Up to P1/8 Up to P1/2 Clock source RSPCK input On-chip baud rate generator Clock polarity Two Two Clock phase Two Two First transfer bit MSB/LSB MSB/LSB Transfer data length 8, 16, or 32 bits 8, 16, or 32 bits Burst transfer Possible (CPHA = 1) Possible (CPHA = 0,1) RSPCK delay control Not supported Supported SSL negation delay control Not supported Supported Next-access delay control Not supported Supported Transfer activation method SSL input active or RSPCK oscillation Transmit buffer is written when SPE = 1 Sequence control Not supported Supported R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 851 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Mode Slave (SPI Operation) Master (SPI Operation) Transmit buffer empty detection Supported Supported Receive buffer full detection Supported Supported Overrun error detection Supported Not Supported Mode fault error detection Supported (MODFEN = 1) Not supported 17.4.2 Pin Control According to the MSTR bit in the control register (SPCR), this module can automatically switch pin directions and output modes. Table 17.5 shows the relationship between pin states and bit settings. Table 17.5 Relationship between Pin States and Bit Settings Pin State*1 Mode Pin Master mode (SPI operation) (MSTR = 1) RSPCK CMOS output SSL CMOS output MOSI CMOS output MISO Input RSPCK Input SSL Input Slave mode (SPI operation) (MSTR = 0) MOSI Input MISO* CMOS output/Hi-Z Note: When SSL is at the non-active level or the SPE bit in SPCR is clear to 0, the pin state is Hi-Z. This module in master mode (SPI operation) determines MOSI signal values during the SSL negation period (including the SSL retention period during a burst transfer) according to MOIFE and MOIFV bit settings in SPPCR, as shown in table 17.6. Table 17.6 MOSI Signal Value Determination during SSL Negation Period MOIFE MOIFV MOSI Signal Value during SSL Negation Period 0 0, 1 Final data from previous transfer 1 0 Always 0 1 1 Always 1 Page 852 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.4.3 (1) Section 17 Renesas Serial Peripheral Interface System Configuration Example Master/Slave (with This LSI Acting as Master) Figure 17.2 shows a master/slave system configuration example when this LSI is used as a master. In master/slave configuration, the SSL output of this LSI (master) is not used. The SSL input of the slave is fixed to the low level, and the slave is always maintained in a selected state. In the transfer format corresponding to the case where the CPHA bit in the control register (SPCR) is 0, there are slave devices for which the SSL signal cannot be fixed to the active level. In situations where the SSL signal cannot be fixed, the SSL output of this LSI should be connected to the SSL input of the slave device. This LSI (master) always drives the RSPCK and MOSI. The slave always drives the MISO. This LSI (master) Slave RSPCK RSPCK MOSI MOSI MISO MISO SSL SSL Figure 17.2 Master/Slave Configuration Example (This LSI = Master) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 853 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface (2) Master/Slave (with This LSI Acting as Slave) Figure 17.3 shows a master/slave system configuration example when this LSI is used as a slave. When this LSI is to operate as a slave, the SSL pin is used as SSL input. The master always drives the RSPCK and MOSI. This LSI (slave) always drives the MISO. When SSL is at the non-active level, the pin state is Hi-Z. In the slave configuration in which the CPHA bit in the command register (SPCMD) is set to 1, the SSL input of this LSI (slave) is fixed to the 0 level, this LSI (slave) is always maintained in a selected state, and in this manner it is possible to execute serial transfer (figure 17.4). Master This LSI (slave) RSPCK RSPCK MOSI MOSI MISO MISO SSL SSL Figure 17.3 Master/Slave Configuration Example (This LSI = Slave) Master This LSI (slave, CPHA = 1) RSPCK RSPCK MOSI MOSI MISO MISO SSL SSL Figure 17.4 Master/Slave Configuration Example (This LSI = Slave, CPHA = 1) Page 854 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 17 Renesas Serial Peripheral Interface Master/Multi-Slave (with This LSI Acting as Slave) Figure 17.5 shows a master/multi-slave system configuration example when this LSI is used as a slave. In the example of figure 17.5, the system is comprised of an master and two LSIs (slave X and slave Y). The RSPCK and MOSI outputs of the master are connected to the RSPCK and MOSI inputs of the LSIs (slave X and slave Y). The MISO outputs of the LSIs (slave X and slave Y) are all connected to the MISO input of the master. SSLX and SSLY outputs of the master are connected to the SSL inputs of the LSIs (slave X and slave Y), respectively. The master always drives RSPCK, MOSI, SSLX, and SSLY. Of the LSIs (slave X and slave Y), the slave that receives low level input into the SSL0 input drives MISO. Master This LSI (slave X) RSPCK RSPCK MOSI MOSI MISO MISO SSLX SSL SSLY This LSI (slave Y) RSPCK MOSI MISO SSL Figure 17.5 Master/Multi-Slave Configuration Example (This LSI = Slave) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 855 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.4.4 (1) Transfer Format CPHA = 0 Figure 17.6 shows a sample transfer format for the serial transfer of 8-bit data when the CPHA bit in the command register (SPCMD) is 0. In figure 17.6, RSPCK (CPOL = 0) indicates the RSPCK signal waveform when the CPOL bit in SPCMD is 0; RSPCK (CPOL = 1) indicates the RSPCK signal waveform when the CPOL bit is 1. The sampling timing represents the timing at which this module fetches serial transfer data into the shift register. The input/output directions of the signals depend on the settings of this module. For details, see section 17.4.2, Pin Control. When the CPHA bit is 0, the driving of valid data to the MOSI and MISO signals commences at an SSL signal assertion timing. The first RSPCK signal change timing that occurs after the SSL signal assertion becomes the first transfer data fetching timing. After this timing, data is sampled at every 1 RSPCK cycle. The change timing for MOSI and MISO signals is always 1/2 RSPCK cycle after the transfer data fetch timing. The settings in the CPOL bit do not affect the RSPCK signal operation timing; they only affect the signal polarity. t1 denotes a period from an SSL signal assertion to RSPCK oscillation (RSPCK delay). t2 denotes a period from the cessation of RSPCK oscillation to an SSL signal negation (SSL negation delay). t3 denotes a period in which SSL signal assertion is suppressed for the next transfer after the end of serial transfer (next-access delay). t1, t2, and t3 are controlled by a master device running on the system. For a description of t1, t2, and t3 when this module is in master mode, see section 17.4.3 (1), Master/Slave (with This LSI Acting as Master). Start End Serial transfer period RSPCK cycle 1 2 3 4 5 6 7 8 RSPCK (CPOL = 0) RSPCK (CPOL = 1) Sampling timing MOSI MISO SSL t1 t2 t3 Figure 17.6 Transfer Format (CPHA = 0) Page 856 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 17 Renesas Serial Peripheral Interface CPHA = 1 Figure 17.7 shows a sample transfer format for the serial transfer of 8-bit data when the CPHA bit in the command register (SPCMD) is 1. In figure 17.7, RSPCK (CPOL = 0) indicates the RSPCK signal waveform when the CPOL bit in SPCMD is 0; RSPCK (CPOL = 1) indicates the RSPCK signal waveform when the CPOL bit is 1. The sampling timing represents the timing at which this module fetches serial transfer data into the shift register. The input/output directions of the signals depend on the modes (master or slave). For details, see section 17.4.2, Pin Control. When the CPHA bit is 1, the driving of invalid data to the MOSI and MISO signals commences at an SSL signal assertion timing. The driving of valid data to the MOSI and MISO signals commences at the first RSPCK signal change timing that occurs after the SSL signal assertion. After this timing, data is updated at every 1 RSPCK cycle. The transfer data fetch timing is always 1/2 RSPCK cycle after the data update timing. The settings in the CPOL bit do not affect the RSPCK signal operation timing; they only affect the signal polarity. t1, t2, and t3 are the same as those in the case of CPHA = 0. For a description of t1, t2, and t3 when this module is in master mode, see section 17.4.3 (1), Master/Slave (with This LSI Acting as Master). Start RSPCK cycle End Serial transfer period 1 2 3 4 5 6 7 8 RSPCK (CPOL = 0) RSPCK (CPOL = 1) Sampling timing MOSI MISO SSL t1 t2 t3 Figure 17.7 Transfer Format (CPHA = 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 857 of 3092 Section 17 Renesas Serial Peripheral Interface 17.4.5 SH7268 Group, SH7269 Group Data Format The data format depends on the settings in the command register (SPCMD). Irrespective of MSB/LSB first, this module treats the range from the LSB of the data register (SPDR) to the assigned data length as transfer data. (1) MSB First Transfer (32-Bit Data) Figure 17.8 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 32-bit data length MSB-first data transfer. The CPU or direct memory access controller writes T31 to T00 to the transmit buffer of SPDR. If the shift register is empty, this module copies the data in the transmit buffer to the shift register, and fully populates the shift register. When serial transfer starts, this module outputs data from the MSB (bit 31) of the shift register, and shifts in the data from the LSB (bit 0) of the shift register. When the RSPCK cycle required for the serial transfer of 32 bits has passed, data R31 to R00 is stored in the shift register. In this state, this module copies the data from the shift register to the receive buffer, and empties the shift register. If the receive buffer does not have a space for the receive data length after the receive data has been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary space in the receive buffer. If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer, received data R31 to R00 is shifted out from the shift register. Page 858 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Transfer start Transmit buffer (SPTX) Bit 31 Bit 0 T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00 Copy Output T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00 Bit 31 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 0 R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00 Input Copy R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00 Bit 31 Bit 0 Receive buffer (SPRX) Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 17.8 MSB First Transfer (32-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 859 of 3092 Section 17 Renesas Serial Peripheral Interface (2) SH7268 Group, SH7269 Group MSB First Transfer (16-Bit Data) Figure 17.9 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 16-bit data length MSB-first data transfer. The CPU or direct memory access controller writes T15 to T00 to the transmit buffer. If the shift register is empty, this module copies the data in the transmit buffer to the shift register, and fully populates the shift register. When serial transfer starts, this module outputs data from bit 15 of the shift register, and shifts in the data from the LSB (bit 0) of the shift register. When the RSPCK cycle required for the serial transfer of 16 bits has passed, received data R15 to R00 is stored in bits 15 to 0 of the shift register. After completion of the serial transfer, data that existed before the transfer is retained in bits 31 to 16 in the shift register. In this state, this module copies the data from the shift register to the receive buffer, and empties the shift register. If the receive buffer does not have a space for the receive data length after receive data has been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary space in the receive buffer. If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer, received data R15 to R00 is shifted out from the shift register. Page 860 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Transmit buffer (SPTX) Transfer start Bit 15 Bit 0 T15 T14 T13 T12 T11 T03 T02 T01 T00 Copy Output T15 T14 T13 T12 T11 T03 T02 T01 T00 T15 T14 T13 T12 T11 T03 T02 T01 T00 Bit 31 Bit 15 Shift register Bit 0 Transfer end Shift register Bit 31 Bit 15 Bit 0 T15 T14 T13 T12 T11 T03 T02 T01 T00 R15 R14 R13 R12 R11 R03 R02 R01 R00 Input Copy R15 R14 R13 R12 R11 R03 R02 R01 R00 Receive buffer (SPRX) Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 17.9 MSB First Transfer (16-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 861 of 3092 Section 17 Renesas Serial Peripheral Interface (3) SH7268 Group, SH7269 Group MSB First Transfer (8-Bit Data) Figure 17.10 shows the operation of the transmit buffer (SPDR) and the shift register when this module performs an 8-bit data length MSB-first data transfer. The CPU or direct memory access controller writes T07 to T00 to the transmit buffer. If the shift register is empty, this module copies the data in the transmit buffer to the shift register, and fully populates the shift register. When serial transfer starts, this module outputs data from bit 7 of the shift register, and shifts in the data from the LSB (bit 0) of the shift register. When the RSPCK cycle required for the serial transfer of 8 bits has passed, received data R07 to R00 is stored in bits 7 to 0 of the shift register. After completion of the serial transfer, data that existed before the transfer is retained in bits 31 to 8 in the shift register. In this state, this module copies the data from the shift register to the receive buffer, and empties the shift register. If the receive buffer does not have a space for the receive data length after receive data has been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary area in the receive buffer. If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer, received data R07 to R00 is shifted out from the shift register. Page 862 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Transmit buffer (SPTX) Transfer start Bit 7 Bit 0 T07 T06 T05 T04 T03 T02 T01 T00 Copy Output T07 T06 T05 T00 T07 T06 T01 T00 T00 T01 T00 T07 T06 T11 T01 T00 Bit 31 Bit 7 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 7 Bit 0 T07 T06 T05 T04 T03 T02 T01 T00 R07 R06 R05 R04 R03 R02 R01 R00 Input Copy R07 R06 R05 R04 R03 R02 R01 R00 Receive buffer (SPRX) Note: Output = MOSI (master)/MISO (slave), input = MOSI (master)/MISO (slave) Figure 17.10 MSB First Transfer (8-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 863 of 3092 Section 17 Renesas Serial Peripheral Interface (4) SH7268 Group, SH7269 Group LSB First Transfer (32-Bit Data) Figure 17.11 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 32-bit data length LSB-first data transfer. The CPU or direct memory access controller writes T31 to T00 to the transmit buffer. If the shift register is empty, this module reverses the order of the bits of the data in the transmit buffer, copies it to the shift register, and fully populates the shift register. When serial transfer starts, this module outputs data from the MSB (bit 31) of the shift register, and shifts in the data from the LSB (bit 0) of the shift register. When the RSPCK cycle required for the serial transfer of 32 bits has passed, data R00 to R31 is stored in the shift register. In this state, this module copies the data, in which the order of the bits is reversed, from the shift register to the receive buffer, and empties the shift register. If the receive buffer does not have a space for the receive data length after receive data has been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary space in the receive buffer. If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer of the SPDR, received data R00 to R31 is shifted out from the shift register. Page 864 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Transfer start Transmit buffer (SPTX) T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00 Copy Output T00 T01 T02 T03 T04 T05 T06 T07 T23 T23 T24 T25 T26 T27 T28 T29 T30 T31 Bit 31 Shift register Transfer end Shift register R00 R01 R02 R03 R04 R05 R06 R07 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Input Copy R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00 Bit 31 Receive buffer (SPRX) Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 17.11 LSB First Transfer (32-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 865 of 3092 Section 17 Renesas Serial Peripheral Interface (5) SH7268 Group, SH7269 Group LSB First Transfer (16-Bit Data) Figure 17.12 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs a 16-bit data length LSB-first data transfer. The CPU or direct memory access controller writes T15 to T00 to the transmit buffer. If the shift register is empty, this module reverses the order of the bits of the data in the transmit buffer, copies it to the shift register, and fully populates the shift register. When serial transfer starts, this module outputs data from the MSB (bit 31) of the shift register, and shifts in the data from bit 16 of the shift register. When the RSPCK cycle required for the serial transfer of 16 bits has passed, received data R00 to R15 is stored in bits 31 to 16 of the shift register. After completion of the serial transfer, data that existed before the transfer is retained in bits 15 to 0 of the shift register. In this state, this module copies the data, in which the order of the bits is reversed, from the shift register to the receive buffer of SPDR, and empties the shift register. If the receive buffer does not have a space for the receive data length after receive data has been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary space in the receive buffer. If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer of SPDR, received data R00 to R15 is shifted out from the shift register. Page 866 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Transfer start Transmit buffer (SPTX) Bit 15 Bit 0 T15 T14 T13 T12 T11 T03 T02 T01 T00 Copy Output T00 T01 T02 T03 T04 T12 T13 T14 Bit 31 T15 T00 T01 T02 T03 T11 T12 T13 T14 T15 Bit 15 Shift register Bit 0 Transfer end Input Shift register Bit 31 Bit 0 R00 R01 R02 R03 R04 R12 R13 R14 R15 T00 T01 T02 T03 T11 T12 T13 T14 T15 Bit 16 Copy R15 R14 R13 R12 R11 R03 R02 R01 R00 Receive buffer (SPRX) Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 17.12 LSB First Transfer (16-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 867 of 3092 Section 17 Renesas Serial Peripheral Interface (6) SH7268 Group, SH7269 Group LSB First Transfer (8-Bit Data) Figure 17.13 shows the operation of the transmit buffer (SPTX) and the shift register when this module performs an 8-bit data length LSB-first data transfer. The CPU or direct memory access controller writes T07 to T00 to the transmit buffer. If the shift register is empty, this module reverses the order of the bits of the data in the transmit buffer, copies it to the shift register, and fully populates the shift register. When serial transfer starts, this module outputs data from the MSB (bit 31) of the shift register, and shifts in the data from bit 24 of the shift register. When the RSPCK cycle required for the serial transfer of 8 bits has passed, received data R00 to R07 is stored in bits 31 to 24 of the shift register. After completion of the serial transfer, data that existed before the transfer is retained in bits 23 to 0 of the shift register. In this state, this module copies the data, in which the order of the bits is reversed, from the shift register to the receive buffer of SPDR, and empties the shift register. If the receive buffer does not have a space for the receive data length after the receive data has been copied from the shift register to the receive buffer, another serial transfer will not be started. In order to start another serial transfer, data for the receive data length should be read from the receive buffer to secure the necessary space in the receive buffer. If another serial transfer is started before the CPU or direct memory access controller writes to the transmit buffer of SPDR, received data R00 to R07 is shifted out from the shift register. Page 868 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Transfer start Transmit buffer (SPTX) Bit 7 Bit 0 T07 T06 T05 T04 T03 T02 T01 T00 Copy Output T00 T01 T00 T07 T00 T05 T06 T07 T05 T06 T07 T00 T01 T11 T06 T07 Bit 31 Bit 7 Bit 0 Shift register Transfer end Input Shift register Bit 31 Bit 0 R00 R01 R02 R03 R04 R05 R06 R07 T00 T01 T02 T03 T04 T05 T06 T07 Bit 24 Copy R07 R06 R05 R04 R03 R02 R01 R00 Receive buffer (SPRX) Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 17.13 LSB First Transfer (8-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 869 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.4.6 Error Detection In the normal serial transfer, the data written from the data register (SPDR) to the transmit buffer is serially transmitted, and the serially received data can be read from the receive buffer of SPDR. If access is made to SPDR, depending on the status of the transmit buffer/receive buffer or the status at the beginning or end of serial transfer, in some cases non-normal transfers can be executed. If a non-normal transfer operation occurs, this module detects the event as an overrun error or a mode fault error. Table 17.7 shows the relationship between non-normal transfer operations and the error detection function. Table 17.7 Relationship between Non-Normal Transfer Operations and Error Detection Function Occurrence Condition Operation Error Detection A SPDR is written when the transmit buffer is full. Missing write data. None B Serial transfer is started in slave mode Data received in previous when transmit data is still not loaded on serial transfer is serially the shift register. transmitted. C SPDR is read when the receive buffer is empty. The output data is undefined. None D Serial transfer terminates when the receive buffer is full. Missing serial receive data. E The SSL input signal is negated during Serial transfer suspended. serial transfer in slave mode. Missing send/receive data. None Overrun error (only in slave mode) Mode fault error Operation disabled. Page 870 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface On operation A shown in table 17.7, this module does not detect an error. Whether SPDR can be written to or not can be checked using the T[3:0] bits in the buffer data count setting register (SPBFDR). Likewise, this module does not detect an error on operation B. In a serial transfer that was started before the shift register was updated, this module sends the data that was received in the previous serial transfer, and does not treat the operation indicated in B as an error. Note that the received data from the previous serial transfer is retained in the receive buffer of SPDR, thus it can be correctly read. Similarly, this module does not detect an error on operation C. To prevent extraneous data from being read, the number of receive data units stored in the receive buffer should be read from the R[5:0] bits in the buffer data count setting register (SPBFDR). An overrun error shown in D is described in section 17.4.6 (1), Overrun Error. A mode fault error shown in E is described in section 17.4.6 (2), Mode Fault Error. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 871 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface (1) Overrun Error If serial transfer ends when the receive buffer of the data register (SPDR) is full, this module detects an overrun error, and sets the OVRF bit in SPSR to 1. When the OVRF bit is 1, this module does not copy data from the shift register to the receive buffer so that the data prior to the occurrence of the error is retained in the receive buffer. To reset the OVRF bit in SPSR to 0, either perform a power-on reset, or write a 0 to the OVRF bit after SPSR has been read with the OVRF bit set to 1. Figure 17.14 shows an example of operation of the SPRF and OVRF bits in SPSR. The SPSR and SPDR accesses shown in figure 17.14 indicates the condition of accesses to SPSR and SPDR, respectively, where I denotes an idle cycle, W a write cycle, and R a read cycle. In the example of figure 17.14, this module performs an 8-bit serial transfer in which the CPHA bit in the command register (SPCMD) is 1, and CPOL is 0. The numbers given under the RSPCK waveform represent the number of RSPCK cycles (i.e., the number of transferred bits). I SPSR access SPDR access R R I I W I SPRF (1) (2) (3) (4) OVRF RSPCK (CPHA = 1, CPOL= 0) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Figure 17.14 SPRF and OVRF Bit Operation Example Page 872 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface The operation of the flags at the timing shown in steps (1) to (4) in the figure is described below. 1. If a serial transfer terminates when the receive buffer does not have a space for the receive data length, this module detects an overrun error, and sets the OVRF bit to 1. This module does not copy the data in the shift register to the receive buffer. 2. The OVFR bit is not cleared even when SPDR is read and thus the number of data bytes in the receive buffer becomes less than the number of the receive buffer data triggering number specified by the RXTRG bits. 3. If the serial transfer terminates in an overrun error state, this module determines that the shift register is empty; in this manner, data transfer is enabled from the transmit buffer to the shift register. 4. If 0 is written to the OVRF bit after SPSR is read with OVRF = 1, this module clears the OVRF bit. The occurrence of an overrun can be checked either by reading SPSR or by using an error interrupt and reading SPSR. When using an error interrupt, set the SPEIE bit in the control register (SPCR) to 1. When executing a serial transfer without using an error interrupt, measures should be taken to ensure the early detection of overrun errors, such as reading SPSR immediately after SPDR is read. The OVRF bit is cleared to 0 under the following conditions:  After SPSR is read in a condition in which the OVRF bit is set to 1, 0 is written to the OVRF bit.  Power-on reset Note: When the receive buffer has area enough to store receive data with an overrun error, this module receives receive data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 873 of 3092 Section 17 Renesas Serial Peripheral Interface (2) SH7268 Group, SH7269 Group Mode Fault Error When the MSTR bit is 0, this module operates in slave mode. This module detects a mode fault error if the SSL input signal is negated during the serial transfer period (from the time the driving of valid data is started to the time the final valid data is fetched) when the MODFEN bit is 1 in slave mode. Upon detecting a mode fault error, this module stops driving of the output signals and clears the SPE bit in SPCR to 0. When the SPE bit is cleared to 0, the function of this module is disabled and this module stops driving external signals. For details of disabling the function of this module by clearing the SPE bit to 0, see section 17.4.7, Initialization. The occurrence of a mode fault error can be checked either by reading SPSR or by using an error interrupt and reading SPSR. When using an error interrupt, set the SPEIE bit in the control register (SPCR) to 1. To detect a mode fault error without using an error interrupt, it is necessary to poll SPSR. When the MODF bit is 1, writing 1 to the SPE bit is ignored. To enable the function of this module after the detection of a mode fault error, the MODF bit must be set to 0. The MODF bit is cleared to 0 under the following conditions:  After SPSR is read in a condition where the MODF bit has turned 1, 0 is written to the MODF bit.  Power-on reset Page 874 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.4.7 Section 17 Renesas Serial Peripheral Interface Initialization If 0 is written to the SPE bit in the control register (SPCR) or this module clears the SPE bit to 0 because of the detection of a mode fault error, this module disables the module function, and initializes a part of the module function. When a power-on reset is generated, this module initializes all of the module function. An explanation of initialization by the clearing of the SPE bit follows. (1) Initialization by Clearing SPE Bit When the SPE bit in SPCR is cleared, this module performs the following initialization:     Suspending any serial transfer that is being executed Stopping the driving of output signals (Hi-Z) in slave mode Initializing the internal state Initializing the TEND bit in SPSR Initialization by the clearing of the SPE bit does not initialize the control bits of this module. For this reason, this module can be started in the same transfer mode as prior to the initialization if the SPE bit is re-set to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 875 of 3092 Section 17 Renesas Serial Peripheral Interface 17.4.8 (1) SH7268 Group, SH7269 Group SPI Operation Multi-Master Mode Operation This section explains the operation in multi-master mode. (a) Starting Serial Transfer A serial transfer is started when transmit data is copied from the transmit buffer to the shift register, the shift register becomes full, and the receive buffer has a space for the receive data length. If transmit data has already been written to the shift register, data is not copied from the transmit buffer to the shift register. For details of the transfer format, see section 17.4.4, Transfer Format. (b) Terminating Serial Transfer Irrespective of the CPHA bit in the command register (SPCMD), this module terminates the serial transfer after transmitting an RSPCK edge corresponding to the final sampling timing. After the serial transfer is completed, receive data is copied from the shift register to the receive buffer. If the receive buffer does not have a space for the receive data length after receive data is copied from the shift register to the receive buffer, another serial transfer will not be performed. In order to perform another serial transfer, data for the receive data length should be read from the receive buffer to secure the space for the receive data. It should be noted that the final sampling timing varies depending on the bit length of transfer data. In master mode, the data length depends on the settings in bits SPB3 to SPB0 in SPCMD. For details on the transfer format, see section 17.4.4, Transfer Format. Page 876 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (c) Section 17 Renesas Serial Peripheral Interface Sequence Control The transfer format that is employed in master mode is determined by the sequence control register (SPSCR), command registers 0 to 3 (SPCMD0 to SPCMD3), the bit rate register (SPBR), the clock delay register (SPCKD), the slave select negation delay register (SSLND), and the nextaccess delay register (SPND). SPSCR is a register used to determine the sequence configuration for serial transfers that are executed by this module in master mode. The following items are set in command registers SPCMD0 to SPCMD3: SSL output signal value, MSB/LSB first, data length, some of the bit rate settings, RSPCK polarity/phase, whether SPCKD is to be referenced, whether SSLND is to be referenced, and whether SPND is to be referenced. SPBR holds some of the bit rate settings; SPCKD, a clock delay value; SSLND, an SSL negation delay; and SPND, a next-access delay value. According to the sequence length that is assigned to SPSCR, this module makes up a sequence comprised of a part or all of SPCMD0 to SPCMD3. This module contains a pointer to the SPCMD that makes up the sequence. The value of this pointer can be checked by reading bits SPCP1 and SPCP0 in the sequence status register (SPSSR). When the SPE bit in the control register (SPCR) is set to 1 and the function of this module is enabled, this module loads the pointer to the commands in SPCMD0, and incorporates the SPCMD0 settings into the transfer format at the beginning of serial transfer. This module increments the pointer each time the next-access delay period for a data transfer ends. Upon completion of the serial transfer that corresponds to the final command comprising the sequence, this module sets the pointer in SPCMD0, and in this manner the sequence is executed repeatedly. Determine transfer format Sequence determined Refer to SCKD, SSLND, and SPND (if necessary) SPSCR SPCMD0 SCKD SSLND SPND H'02 SPCMD1 H'01 H'00 H'02 RSPCK delay = 2 RSPCK SSL negate delay = 1 RSPCK Next-access delay = 3 RSPCK + 2 P1φ Pointer SPCP1 and SPCP0 SPCMD2 SPCMD3 H'E700 Sequence is formed in SPCMD0 to SPCMD2 SCKD, SSLND, and SPND must be referenced. MSB first, 8 bits, SSL not retained, base division ratio = 1 CPOL = 0, CPHA = 0 Figure 17.15 Determination Procedure of Serial Transfer Mode in Master Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 877 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface (d) Burst Transfer If the SSLKP bit in the command register (SPCMD) that this module references during the current serial transfer is 1, this module keeps the SSL signal level during the serial transfer until the beginning of the SSL signal assertion for the next serial transfer. If the SSL signal level for the next serial transfer is the same as the SSL signal level for the current serial transfer, this module can execute continuous serial transfers while keeping the SSL signal assertion status (burst transfer). Figure 17.16 shows an example of an SSL signal operation for the case where a burst transfer is implemented using SPCMD0 and SPCMD1 settings. The text below explains operations (1) to (7) as depicted in figure 17.16. It should be noted that the polarity of the SSL output signal depends on the settings in the slave select polarity register (SSLP). 1. 2. 3. 4. Based on SPCMD0, this module asserts the SSL signal and inserts RSPCK delays. Serial transfers are executed according to SPCMD0. SSL negation delays are inserted. Because the SSLKP bit in SPCMD0 is 1, this module keeps the SSL signal value on SPCMD0. This period is sustained, at the shortest, for a period equal to the next-access delay of SPCMD0. If the shift register is empty after the passage of a minimum period, this period is sustained until such time as the transmit data is stored in the shift register for another transfer. 5. Based on SPCMD1, this module asserts the SSL signal and inserts RSPCK delays. 6. Serial transfers are executed according to SPCMD1. 7. Because the SSLKP bit in SPCMD1 is 0, this module negates the SSL signal. In addition, a next-access delay is inserted according to SPCMD1. RSPCK (CPHA = 1, CPOL = 0) SSL (1) (2) (3) (4) (5) (6) (7) Figure 17.16 Example of Burst Transfer Operation using SSLKP Bit Page 878 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface If the SSL signal settings in the SPCMD in which 1 is assigned to the SSLKP bit are different from the SSL signal output settings in the SPCMD to be used in the next transfer, this module switches the SSL signal status to SSL signal assertion ((5) in figure 17.16) corresponding to the command for the next transfer. Notice that if such an SSL signal switching occurs, the slaves that drive the MISO signal compete, and the possibility arises of the collision of signal levels. This module in master mode references within the module the SSL signal operation for the case where the SSLKP bit is not used. Even when the CPHA bit in SPCMD is 0, this module can accurately start serial transfers by asserting the SSL signal for the next transfer. For this reason, burst transfers in master mode can be executed irrespective of CPHA bit settings (see section 17.4.8 (2), Slave Mode Operation). (e) RSPCK Delay (t1) The RSPCK delay value in master mode depends on SCKDEN bit settings in the command register (SPCMD) and on clock delay register (SPCKD) settings. This module determines the SPCMD to be referenced during serial transfer by pointer control, and determines an RSPCK delay value during serial transfer by using the SCKDEN bit in the selected SPCMD and SPCKD, as shown in table 17.8. For a definition of RSPCK delay, see section 17.4.4, Transfer Format. Table 17.8 Relationship among SCKDEN and SPCKD Settings and RSPCK Delay Values SCKDEN SPCKD RSPCK Delay Value 0 000 to 111 1 RSPCK 1 000 1 RSPCK 001 2 RSPCK 010 3 RSPCK 011 4 RSPCK 100 5 RSPCK 101 6 RSPCK 110 7 RSPCK 111 8 RSPCK R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 879 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface (f) SSL Negation Delay (t2) The SSL negation delay value in master mode depends on SLNDEN bit settings in the command register (SPCMD) and on SSL negation delay register (SSLND) settings. This module determines the SPCMD to be referenced during serial transfer by pointer control, and determines an SSL negation delay value during serial transfer by using the SLNDEN bit in the selected SPCMD and SSLND, as shown in table 17.9. For a definition of SSL negation delay, see section 17.4.4, Transfer Format. Table 17.9 Relationship among SLNDEN and SSLND Settings and SSL Negation Delay Values SLNDEN SSLND SSL Negation Delay Value 0 000 to 111 1 RSPCK 1 000 1 RSPCK 001 2 RSPCK 010 3 RSPCK 011 4 RSPCK 100 5 RSPCK 101 6 RSPCK 110 7 RSPCK 111 8 RSPCK Page 880 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (g) Section 17 Renesas Serial Peripheral Interface Next-Access Delay (t3) The next-access delay value in master mode depends on SPNDEN bit settings in the command register (SPCMD) and on next-access delay register (SPND) settings. This module determines the SPCMD to be referenced during serial transfer by pointer control, and determines a next-access delay value during serial transfer by using the SPNDEN bit in the selected SPCMD and SPND, as shown in table 17.10. For a definition of next-access delay, see section 17.4.4, Transfer Format. Table 17.10 Relationship among SPNDEN and SPND Settings and Next-Access Delay Values SPNDEN SPND Next-Access Delay Value 0 000 to 111 1 RSPCK  2 P1 1 000 1 RSPCK  2 P1 001 2 RSPCK  2 P1 010 3 RSPCK  2 P1 011 4 RSPCK  2 P1 100 5 RSPCK  2 P1 101 6 RSPCK  2 P1 110 7 RSPCK  2 P1 111 8 RSPCK  2 P1 (h) Initialization Flowchart Figure 17.17 is a flowchart illustrating an example of initialization in SPI operation when this module is used in master mode. For a description of how to set up the interrupt controller, direct memory access controller, and input/output ports, see the descriptions given in the individual blocks. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 881 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface Start of intialization in master mode Set the pin control register (SPPCR) Set the bit rate register (SPBR) Set the data control register (SPDCR) Set the RSPCK delay register (SPCKD) • Sets MOSI signal value when transfer is in idle state. • Sets transfer bit rate. • Sets access width. • Sets RSPCK delay value. Set the slave select negate delay register (SSLND) • Sets SSL negate delay value. Set the next-access delay register (SPND) • Sets next-access delay value. Set the command registers 0 to 3 (SPCMD0 to SPCMD3) Set the interrupt controller Set the direct memory access controller Set the control register (SPCR) • Sets SSL signal level. • Sets RSPCK delay enable. • Sets SSL negate delay enable. • Sets next-access delay enable. • Sets MSB or LSB first. • Sets data length. • Sets transfer bit rate. • Sets clock phase. • Sets clock polarity. (when using an interrupt) (when using the direct memory access controller) • Sets master mode. • Sets interrupt mask. End of intialization in master mode Figure 17.17 Example of Initialization Flowchart in Master Mode Page 882 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (i) Section 17 Renesas Serial Peripheral Interface Transfer Operation Flowchart Figure 17.18 is a flowchart illustrating a transfer in SPI operation when this module is used in master mode. End of initialization in master mode No Transmit buffer has transmit data YES Copy transmit data from transmit buffer to shift register No Receive buffer has a space for receive data YES Start serial transfer RSPCK cycle count Shorter than data length Equal to data length Receive buffer has a space for receive data No RSPCK stopped YES Copy received data from shift register to receive buffer YES Receive buffer has a space for receive data No Update command pointer Yes Continue serial transfer No End of transfer Figure 17.18 Transfer Operation Flowchart in Master Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 883 of 3092 Section 17 Renesas Serial Peripheral Interface (2) Slave Mode Operation (a) Starting Serial Transfer SH7268 Group, SH7269 Group If this module detects an SSL input signal assertion when the CPHA bit in the command register 0 (SPCMD0) is 0, this module is required to start driving valid data to the MISO output signal. For this reason, when the CPHA bit is 0, the asserting of the SSL input signal triggers the start of a serial transfer. If this module detects the first RSPCK edge in an SSL signal asserted condition when the CPHA bit is 1, this module is required to start driving valid data to the MISO output signal. For this reason, when the CPHA bit is 1, the first RSPCK edge in an SSL signal asserted condition triggers the start of a serial transfer. When detecting the start of a serial transfer in a condition in which the shift register is empty, this module changes the status of the shift register to "full", so that data cannot be copied from the transmit buffer to the shift register when serial transfer is in progress. If the shift register was full before the serial transfer started, this module leaves the status of the shift register intact, in the full state. Irrespective of CPHA bit settings, this module starts driving MISO output signals at the SSL signal assertion timing. Whether the data output from this module is valid or invalid differs depending on CPHA bit settings. For details on the transfer format, see section 17.4.4, Transfer Format. The polarity of the SSL input signal depends on the setting of the SSL0P bit in the slave select polarity register (SSLP). Page 884 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 17 Renesas Serial Peripheral Interface Terminating Serial Transfer Irrespective of the CPHA bit in the command register 0 (SPCMD0), this module terminates the serial transfer after detecting an RSPCK edge corresponding to the final sampling timing. When the receive buffer has an enough space for receive data, this module copies received data from the shift register to the receive buffer of the data register (SPDR) upon termination of the serial transfer. Irrespective of the value of the SPRF bit, this module changes the status of the shift register to "empty" upon termination of the serial transfer. If this module detects an SSL input signal negation from the beginning of serial transfer to the end of serial transfer, a mode fault error occurs (see section 17.4.6, Error Detection). The final sampling timing changes depending on the bit length of the transfer data. In slave mode, the data length depends on the settings in bits SPB3 to SPB0 bits in SPCMD0. The polarity of the SSL input signal depends on the setting in the SSL0P bit in the slave select polarity register (SSLP). For details on the transfer format, see section 17.4.4, Transfer Format. (c) Notes on Slave Operations If the CPHA bit in the command register 0(SPCMD0) is 0, this module starts serial transfers when it detects the assertion edge for an SSL input signal. In the type of configuration shown in figure 17.4 as an example, if this module is used in single-slave mode, the SSL signal is always fixed at active state. Therefore, when the CPHA bit is set to 0, this module cannot correctly start a serial transfer. To correctly execute send/receive operation in a configuration in which the SSL input signal is fixed at active state, the CPHA bit should be set to 1. When it is necessary to set the CPHA bit to 0, the SSL input signal should not be fixed. (d) Burst Transfer If the CPHA bit in the command register 0 (SPCMD0) is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion state for the SSL input signal. If the CPHA bit is 1, the period from the first RSPCK edge to the sampling timing for the reception of the final bit in an SSL signal active state corresponds to a serial transfer period. Even when the SSL input signal remains at the active level, this module can accommodate burst transfers because it can detect the start of access. If the CPHA bit is 0, for the reason given in section 17.4.8 (2) (c), Notes on Slave Operations, second and subsequent serial transfers during the burst transfer cannot be executed correctly. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 885 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface (e) Initialization Flowchart Figure 17.19 is a flowchart illustrating an example of initialization in SPI operation when this module is used in slave mode. For a description of how to set up the interrupt controller, direct memory access controller, and input/output ports, see the descriptions given in the individual blocks. Start of intialization in slave mode Set the pin control register (SPPCR) Set the slave select polarity register (SSLP) Set the data control register (SPDCR) • Sets polarity of SSL input signal • Sets access width. Set the command register 0 (SPCMD0) • Sets MSB or LSB first. • Sets data length. • Sets clock phase. • Sets clock polarity. Set interrupt controller (when using an interrupt) Set the direct memory access controller (when using the direct memory access controller) Set the control register (SPCR) • Sets slave mode. • Sets mode fault error detection. • Sets interrupt mask. End of intialization in slave mode Figure 17.19 Example of Initialization Flowchart in Slave Mode Page 886 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (f) Section 17 Renesas Serial Peripheral Interface Transfer Operation Flowchart (CPHA = 0) Figure 17.20 is a flowchart illustrating a transfer in SPI operation when this module is used in slave mode with the CPHA bit in the command register 0 (SPCMD0) set to 0. End of initialization in slave mode MISO Hi-Z Negate SSL input level Assert Start serial transfer Shorter than data length RSPCK cycle count Equal to data length Error occurred Overrun error status SSL input level No error Assert Negate Receive buffer status Full Detect mode fault error Empty Copy received data from the shift register to the receive buffer Error occurred Overrun error status No error Error handling Assert SSL input level Negate Yes Continue serial transfer No End of transfer Error handling Figure 17.20 Transfer Operation Flowchart in Slave Mode (CPHA = 0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 887 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface (g) Transfer Operation Flowchart (CPHA = 1) Figure 17.21 is a flowchart illustrating a transfer in SPI operation when this module is used in slave mode with the CPHA bit in the command register 0 (SPCMD0) and the MODFEN bit in the control register (SPCR) set to 1, respectively. The subsequent operation is not guaranteed when the serial transfer is started with the MODFEN bit set to 0 and the SSL input level is negated with the number of RSPCK cycles shorter than the data length. End of initialization in slave mode MISO Hi-Z Negate SSL input level Assert MISO output No change RSPCK input level Changed Start serial transfer Assert Shorter than data length RSPCK cycle count Equal to data length SSL input level Error occurred Overrun error status Negate No error Receive buffer status Empty Detect mode fault error Full Copy received data from the shift register to the receive buffer Overrun error status Error occurred No error Error handling Yes Continue data transfer No End of transfer Error handling Figure 17.21 Transfer Operation Flowchart in Slave Mode (CPHA = 1) Page 888 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 17.4.9 Section 17 Renesas Serial Peripheral Interface Error Handling Figures 17.22 and 17.23 show the error handling. The following error handling is used to return from the error state after an error in master or slave mode. Overrun error occurred. User handling Clear the OVRF bit. Read receive data before the overrun error Check that OVRF = 0 and SPRF = 0 End of overrun error handing Figure 17.22 Error Handling (Overrun Error) Mode fault error occurred. User handling Clear the MODF bit. Set the SPE bit to 1. End of mode fault error handing Figure 17.23 Error Handling (Mode Fault Error) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 889 of 3092 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.4.10 Loopback Mode When 1 is written to the SPLP bit in the pin control register (SPPCR), this module shuts off the path between the MISO pin and the shift register, and between the MOSI pin and the shift register, and connects the input path and the output path (reversed) of the shift register. This is called loopback mode. When a serial transfer is executed in loopback mode, the transmit data becomes the received data. Figure 17.24 shows the configuration of the shift register input/output paths for the case where this module in master mode is set in loopback mode. Shift Register Selector Normal Normal Master Loopback Slave Normal Master Loopback Slave MOSI Loopback MISO Figure 17.24 Configuration of Shift Register Input/Output Paths in Loopback Mode (Master Mode) Page 890 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 17 Renesas Serial Peripheral Interface 17.4.11 Interrupt Sources This module has interrupt sources of receive buffer full, transmit buffer empty, mode fault, and overrun. In addition, the direct memory access controller can be activated by the receive buffer full or transmit buffer empty interrupt for data transfer. Table 17.11 shows the interrupt sources. When any of the interrupt conditions in table 17.11 is met, an interrupt is generated. The interrupt sources should be cleared with data transfer by the CPU or direct memory access controller. Table 17.11 Interrupt Sources Name Interrupt Source Abbreviation Interrupt Condition Activation of Direct Memory Access Controller SPRI Receive buffer full RXI (SPRIE = 1)  (SPRF = 1) Possible SPTI Transmit buffer empty TXI (SPTIE = 1)  (SPTEF = 1) Possible SPEI Mode fault MOI (SPEIE = 1)  (MODF = 1)  Overrun OVI (SPEIE = 1)  (OVRF = 1)  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 891 of 3092 Section 17 Renesas Serial Peripheral Interface Page 892 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Section 18 Renesas Quad Serial Peripheral Interface This LSI includes two-channel Renesas quad serial peripheral interfaces. 18.1 Features This module has the following features.  Capable of communications to the serial flash memory through single-/dual-/quad-SPI operation Single-SPI operation Use of MO (master out), MI (master in), QSSL (slave select), and QSPCLK (SPI clock) signals allow for communications to the serial flash memory through SPI operation (fourwire method). QMO output pin and QMI input pin QSSL and QSPCLK serve as output pins. Dual-SPI operation Use of QIO1, QIO0, QSSL, and QSPCLK signals allow for serial communications through SPI operation (four-wire method). Bidirectional QIO1 and QIO0 pins QSSL and QSPCLK serve as output pins. Quad-SPI operation Use of QIO3 to QIO0, QSSL, and QSPCLK signals allow for serial communications through SPI operation (six-wire method). Bidirectional QIO3 to QIO0 pins QSSL and QSPCLK serve as output pins  Transfer data length Transfer data length is selectable from 8 bits to 128 Gbits Data is continuously transferred one through 4,294,967,296 times in 8-, 16-, or 32-bit units  Bit rate QSPCLK can be divided by a maximum of 4080 (divide 2 or more in transmission) QSPCLK can be generated by dividing P1 by the on-chip baud rate generator. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 893 of 3092 Section 18 Renesas Quad Serial Peripheral Interface SH7268 Group, SH7269 Group  Buffer configuration 8 bits  32 buffers for transmission and 8 bits  32 buffers for reception  Shift registers 32 bits each for transmission and reception  QSSL control function Controllable delay from QSSL output assertion to QSPCLK operation (clock delay) Range: 0 and 1.5 to 8.5 QSPCLK cycles (set in QSPCLK-cycle units) Controllable delay from QSPCLK stoppage to QSSL output negation (QSSL negation delay) Range: 0 to 8 QSPCLK cycles (set in QSPCLK-cycle units) Controllable wait for next-access QSSL output assertion (next-access delay) Range: 0 to 8 QSPCLK cycles (set in QSPCLK-cycle units) Capable of holding QSSL output value from transfer end to next access Function for changing QSSL polarity  Transfer control A transfer of up to four commands can be executed sequentially in looped execution. Single-SPI or dual-/quad-SPI write operation: A transfer can be started when data is written to the transmit buffer while the SPI function is enabled. Dual-/quad-SPI read operation: A transfer can be started when the SPI function is enabled while there is enough space for receiving the specified length of data in the receive buffer. QIO3 to QIO0 and QMO output values can be specified during QSSL negation QIO3 and QIO2 output values can be specified in single-/dual-SPI modes  Interrupt sources Maskable interrupt sources: Receive buffer full interrupt Transmit buffer empty interrupt  Others Provides loop back mode Provides a function for initializing this module Page 894 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.2 Section 18 Renesas Quad Serial Peripheral Interface Input/Output Pins Table 18.1 shows the pin configuration. Table 18.1 Pin Configuration Channel Pin Name Pin Name I/O Function 0 Clock pin QSPCLK_0 O Clock output Master transmit data/data 0 pin* QMO_0/ QIO0_0 I/O Master transmit data/data 0 Master input data/data 1 pin*2 QMI_0/ QIO1_0 I/O Master input data/data 1 Data 2 pin*3 QIO2_0 I/O Data 2 3 QIO3_0 I/O Data 3 QSSL_0 O Slave selection QSPCLK_1 O Clock output Master transmit data/data 0 pin* QMO_1/ QIO0_1 I/O Master transmit data/data 0 Master input data/data 1 pin*2 QMI_1/ QIO1_1 I/O Master input data/data 1 Data 2 pin*3 QIO2_1 I/O Data 2 3 QIO3_1 I/O Data 3 QSSL_1 O Slave selection 2 Data 3 pin* Slave select pin 1 Clock pin 2 Data 3 pin* Slave select pin Notes: 1. In the description of the pins, the channel is omitted and pin names are described as QSPCLK, QMO/QIO0, QMI/QIO1, QIO2, QIO3, and QSSL. 2. In single-SPI mode, QMO and QMI are enabled; QIO0 and QIO1 in dual-/quad-SPI modes. 3. In single-/dual-SPI modes, fixed value according to register setting is output; QIO2 and QIO3 in quad-SPI mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 895 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3 Register Descriptions Table 18.2 shows the register configuration. Table 18.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 Control register_0 SPCR_0 R/W H'00 H'E8033800 8, 16, 32 Slave select polarity register_0 SSLP_0 R/W H'00 H'E8033801 8, 16, 32 Pin control register_0 SPPCR_0 R/W H'06 H'E8033802 8, 16, 32 Status register_0 SPSR_0 R H'60 H'E8033803 8, 16, 32 Data register_0 SPDR_0 R/W Undefined H'E8033804 8, 16, 32 Sequence control register_0 SPSCR_0 R/W H'00 H'E8033808 8, 16, 32 Sequence status register_0 SPSSR_0 R H'00 H'E8033809 8, 16, 32 Bit rate register_0 SPBR_0 R/W H'FF H'E803380A 8, 16, 32 Data control register_0 SPDCR_0 R/W H'00 H'E803380B 8, 16, 32 Clock delay register_0 SPCKD_0 R/W H'00 H'E803380C 8, 16, 32 Slave select negation delay register_0 SSLND_0 R/W H'00 H'E803380D 8, 16, 32 Next-access delay register_0 SPND_0 R/W H'00 H'E803380E 8, 16, 32 Command register 0_0 SPCMD0_0 R/W H'E001 H'E8033810 16, 32 Command register 1_0 SPCMD1_0 R/W H'E001 H'E8033812 16, 32 Command register 2_0 SPCMD2_0 R/W H'E001 H'E8033814 16, 32 Command register 3_0 SPCMD3_0 R/W H'E001 H'E8033816 16, 32 Buffer control register_0 SPBFCR_0 R/W H'00 H'E8033818 8, 16, 32 Buffer data count register_0 SPBDCR_0 R H'0000 H'E803381A 16, 32 Transfer data length multiplier setting register 0_0 SPBMUL0_0 R/W Page 896 of 3092 H'00000001 H'E803381C 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Channel Register Name Abbreviation R/W Initial Value 0 Transfer data length multiplier setting register 1_0 SPBMUL1_0 R/W H'00000001 H'E8033820 32 Transfer data length multiplier setting register 2_0 SPBMUL2_0 R/W H'00000001 H'E8033824 32 Transfer data length multiplier setting register 3_0 SPBMUL3_0 R/W H'00000001 H'E8033828 32 Control register_1 SPCR_1 R/W H'00 H'E8034000 8, 16, 32 Slave select polarity register_1 SSLP_1 R/W H'00 H'E8034001 8, 16, 32 Pin control register_1 SPPCR_1 R/W H'06 H'E8034002 8, 16, 32 Status register_1 SPSR_1 R H'60 H'E8034003 8, 16, 32 Data register_1 SPDR_1 R/W Undefined H'E8034004 8, 16, 32 Sequence control register_1 SPSCR_1 R/W H'00 H'E8034008 8, 16, 32 Sequence status register_1 SPSSR_1 R H'00 H'E8034009 8, 16, 32 Bit rate register_1 SPBR_1 R/W H'FF H'E803400A 8, 16, 32 Data control register_1 SPDCR_1 R/W H'00 H'E803400B 8, 16, 32 Clock delay register_1 SPCKD_1 R/W H'00 H'E803400C 8, 16, 32 Slave select negation delay register_1 SSLND_1 R/W H'00 H'E803400D 8, 16, 32 Next-access delay register_1 SPND_1 R/W H'00 H'E803400E 8, 16, 32 Command register 0_1 SPCMD0_1 R/W H'E001 H'E8034010 16, 32 Command register 1_1 SPCMD1_1 R/W H'E001 H'E8034012 16, 32 Command register 2_1 SPCMD2_1 R/W H'E001 H'E8034014 16, 32 Command register 3_1 SPCMD3_1 R/W H'E001 H'E8034016 16, 32 Buffer control register_1 SPBFCR_1 R/W H'00 H'E8034018 8, 16, 32 Buffer data count register_1 R H'0000 H'E803401A 16, 32 1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SPBDCR_1 Address Access Size Page 897 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Channel Register Name Abbreviation R/W Initial Value 1 Transfer data length multiplier setting register 0_1 SPBMUL0_1 R/W H'00000001 H'E803401C 32 Transfer data length multiplier setting register 1_1 SPBMUL1_1 R/W H'00000001 H'E8034020 32 Transfer data length multiplier setting register 2_1 SPBMUL2_1 R/W H'00000001 H'E8034024 32 Transfer data length multiplier setting register 3_1 SPBMUL3_1 R/W H'00000001 H'E8034028 32 Address Access Size Note: In the description of the register names, the channel is omitted. Page 898 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.3.1 Section 18 Renesas Quad Serial Peripheral Interface Control Register (SPCR) SPCR sets the operating mode. 7 Bit: 6 5 SPRIE SPE SPTIE Initial Value: 0 R/W: R/W 4 3 2 1 0      0 0 0 0 0 0 0 R/W R/W R R/W R R R Bit Bit Name Initial Value R/W Description 7 SPRIE 0 R/W Receive Interrupt Enable Enables or disables generation of receive interrupt requests when the number of receive data units in the receive buffer is equal to or greater than the specified receive buffer data triggering number and the receive buffer full flag (SPRFF) in the status register (SPSR) is set to 1. 0: Disables the generation of receive interrupt requests. 1: Enables the generation of receive interrupt requests. 6 SPE 0 R/W SPI Function Enable Setting this bit to 1 enables the SPI module function. Setting this bit to 0 initializes a part of the module function. 0: Disables the module function 1: Enables the module function 5 SPTIE 0 R/W 4  0 R Transmit Interrupt Enable Enables or disables generation of transmit interrupt requests when the number of transmit data units in the transmit buffer is equal to or less than the specified transmit buffer data triggering number and the transmit buffer empty flag (SPTEF) in SPSR is set to 1. 0: Disables the generation of transmit interrupt requests. 1: Enables the generation of transmit interrupt requests. Reserved This bit is always read as 0. The write value should always be 0. 3  0 R/W Reserved The write value should always be 1. Otherwise, operation cannot be guaranteed. 2 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 899 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.2 Slave Select Polarity Register (SSLP) SSLP sets the polarity of the QSSL signal. If the contents of SSLP are modified while the SPE bit in the control register (SPCR) is set to 1, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3 2 1 0        SSLP Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 SSLP 0 R/W QSSL Signal Polarity Setting Sets the polarity of the QSSL signal. 0: QSSL signal low-active 1: QSSL signal high-active Page 900 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.3.3 Section 18 Renesas Quad Serial Peripheral Interface Pin Control Register (SPPCR) SPPCR sets the modes of the pins. If the contents of SPPCR are modified while the SPE bit in SPCR is set to 1, the subsequent operation cannot be guaranteed. Bit: 7 6   5 4 MOIFE MOIFV 3  2 1 0 IO3FV IO2FV SPLP Initial Value: 0 0 0 0 0 1 1 0 R/W: R R R/W R/W R R/W R/W R/W Bit Bit Name Initial Value R/W 7, 6  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 5 MOIFE 0 R/W Data Output Idle Value Fixing Enable Fixes the pin output value in a QSSL negation period or the QSSL keeping period during a burst transfer. In singleSPI mode, this bit setting applies to QMO. In dual-SPI mode, this bit setting applies to QIO1 and QIO0. In quadSPI mode, this bit setting applies to QIO3 to QIO0. 0: Output value equals final data from previous transfer 1: Output value equals the value set in the MOIFV bit Note: In dual-/quad-SPI modes, QIO1 and QIO0/QIO3 to QIO0 are driven to the Hi-Z state regardless of this bit setting (see section 18.4.2, Pin Control). 4 MOIFV 0 R/W Data Output Idle Fixed Value If the data output idle value fixing enable bit (MOIFE) is 1, this module, according to data output idle fixed value (MOIFV) bit settings, determines the output value during the QSSL negation period. 0: Output pin idle fixed value equals 0 1: Output pin idle fixed value equals 1 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 901 of 3092 Section 18 Renesas Quad Serial Peripheral Interface SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 IO3FV 1 R/W Single-/Dual-SPI Mode QIO3 Output Fixed Value Fixes the output direction of the QIO3 pin in single-/dualSPI modes. This bit is valid only in single-/dual-SPI modes, and is not affected by the MOIFE or MOIFV bit values. 0: QIO3 output fixed value equals 0 1: QIO3 output fixed value equals 1 1 IO2FV 1 R/W Single-/Dual-SPI Mode QIO2 Output Fixed Value Fixes the output direction of the QIO2 pin in single-/dualSPI modes. This bit is valid only in single-/dual-SPI modes, and is not affected by the MOIFE or MOIFV bit values. 0: QIO2 output fixed value equals 0 1: QIO2 output fixed value equals 1 0 SPLP 0 R/W Loopback Mode When the SPLP bit is set to 1, this module shuts off the path between the data I/O pin and the transmit/receive shift register, and connects the input path and the output path for the transmit/receive shift register. 0: Normal mode 1: Loopback mode Note: When the loopback mode is specified in dual-/quadSPI modes, the SPI read/write access setting bit (SPRW) in command registers 0 to 3 (SPCMD0 to SPCMD3) should be set to 0 (write operation). Page 902 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.3.4 Section 18 Renesas Quad Serial Peripheral Interface Status Register (SPSR) SPSR indicates the operating status. 7 Bit: 6 5 SPRFF TEND SPTEF 4 3 2 1 0      Initial Value: 0 1 1 0 0 0 0 0 R/W: R R R R R R R R Bit Bit Name Initial Value R/W Description 7 SPRFF 0 R Receive Buffer Full Flag Indicates that the number of receive data units in the receive buffer is equal to or greater than the receive buffer data triggering number specified in the buffer control register. 0: The number of receive data units in the receive buffer is less than the receive buffer data triggering number. 1: The number of receive data units in the receive buffer is equal to or greater than the receive buffer data triggering number. [Clearing conditions]  The receive buffer data is read until the number of data units in the receive buffer becomes less than the specified receive buffer data triggering number.  Receive buffer data reset is enabled.  Power-on reset [Setting condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 The number of data units in the receive buffer is equal to or greater than the specified receive buffer data triggering number. Page 903 of 3092 Section 18 Renesas Quad Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 6 TEND 1 R Transmit End Flag SH7268 Group, SH7269 Group This bit is set to 1 when transmission is completed, and this bit is 0 when transmission is not completed. [Clearing conditions]  When transmit data are moved from the transmit register to the transmit shift register.  When data reception is started in dual-/quad-SPI modes. [Setting condition] Page 904 of 3092  When the number of data units in the transmit buffer is zero when a serial transfer is completed (except when the dummy transmission enable bit (TXDMY) is set to 1).  When there is not enough space for receiving the specified length of data in the receive buffer when a serial transfer is completed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 5 SPTEF 1 R Transmit Buffer Empty Flag Indicates that the number of transmit data units in the transmit buffer is equal to or less than the transmit buffer data triggering number specified in the buffer control register. 0: The number of transmit data units in the transmit buffer exceeds the specified transmit buffer data triggering number. 1: The number of transmit data units in the transmit buffer is equal to or less than the specified transmit buffer data triggering number. [Clearing condition]  When data is written to the transmit buffer until the number of transmit data units in the transmit buffer exceeds the specified transmit buffer data triggering number. [Setting conditions] 4 to 0  All 0 R  When the number of transmit data units in the transmit buffer is equal to or less than the specified transmit buffer data triggering number.  When transmit buffer data reset is enabled.  Power-on reset Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 905 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.5 Data Register (SPDR) SPDR accesses transmit/receive data buffer. The transmit buffer (SPTXB) and receive buffer (SPRXB) are independent and are mapped to SPDR. When data is written to SPDR, the data will be written to the transmit buffer. When data is read from SPDR, the data will be read from the receive buffer. SPDR should be read or written to in byte, word, or longword units. When SPDR is read or written to with the longword-, word-, or byte-access width, the receive or transmit data should be read from or written to the following bits. Longword: Bits 31 to 0 Word: Bits 31 to 16 Byte: Bits 31 to 24 Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SPD31 SPD30 SPD29 SPD28 SPD27SPD26 SPD25SPD24 SPD23 SPD22 SPD21 SPD20 SPD19SPD18 SPD17SPD16 Initial Value: R/W: Bit: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPD15 SPD14 SPD13 SPD12 SPD11SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 Initial Value: R/W: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Page 906 of 3092 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.3.6 Section 18 Renesas Quad Serial Peripheral Interface Sequence Control Register (SPSCR) SPSCR sets the sequence controlled method. If the contents of SPSCR are modified while the SPE bit in SPCR is 1, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3 2       1 0 SPSC1SPSC0 Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 SPSC1 0 R/W Sequence Control Specification 0 SPSC0 0 R/W These bits specify sequential operations. This module references SPCMD0 to SPCMD3 in the order according to these bit settings. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00: 00… 01: 010… 10: 0120… 11: 01230… Page 907 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.7 Sequence Status Register (SPSSR) SPSSR indicates the sequence control status. Bit: 7 6 5 4 3 2       1 0 SPSS1 SPSS0 Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 SPSS1 0 R Sequence Status 0 SPSS0 0 R During sequence control, these bits indicate one of SPCMD0 to SPCMD3 that is currently referenced. 00: SPCMD0 01: SPCMD1 10: SPCMD2 11: SPCMD3 Page 908 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.3.8 Section 18 Renesas Quad Serial Peripheral Interface Bit Rate Register (SPBR) SPBR sets the bit rate. If the contents of SPBR are modified while the SPE bit in SPCR is 1, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3 2 1 0 SPBR7 SPBR6 SPBR5 SPBR4 SPBR3 SPBR2 SPBR1 SPBR0 Initial Value: 1 R/W: R/W 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W The bit rate is determined by combinations of SPBR settings and the bit settings in the bit rate division setting bits (BRDV1 and BRDV0) in SPCMD0 to SPCMD3. When SPBR is set to 0, the base bit rate is selected. The equation for calculating the bit rate when SPBR is not 0 is given below. In the equation, n denotes an SPBR setting (1, …, 255), and N denotes bit settings in the bits BRDV1 and BRDV0 (0, 1, 2, 3). Bit rate = R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 f (P1) 2 × n × 2N Page 909 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Table 18.3 shows examples of the relationship between SPBR and BRDV1 and BRDV0 bit settings. Table 18.3 Relationship between SPBR and BRDV1 and BRDV0 Settings Bit Rate SPBR (n) BRDV[1:0] (N) Division Ratio P1 = 50 MHz P1 = 66.67 MHz 0 0 1 50.0 Mbps 66.67 Mbps 1 0 2 25.0 Mbps 33.33 Mbps 2 0 4 12.50 Mbps 16.67 Mbps 3 0 6 8.33 Mbps 11.11 Mbps 4 0 8 6.25 Mbps 8.33 Mbps 5 0 10 5.00 Mbps 6.67 Mbps 6 0 12 4.16 Mbps 5.56 Mbps 6 1 24 2.08 Mbps 2.78 Mbps 6 2 48 1.04 Mbps 1.39 Mbps 6 3 96 520 kbps 694.48 kbps 255 3 4080 12.25 kbps 16.34 kbps Note: In transmission, set SPBR and BRDV that the division ratio of QSPCLK is 2 or more. Page 910 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.3.9 Section 18 Renesas Quad Serial Peripheral Interface Data Control Register (SPDCR) SPDCR enables or disables dummy data transmission. 7 6 5 4 3 2 1 0 TXDMY        Bit: 0 0 0 0 0 0 0 0 R/W R R R R R R R Initial Value: R/W: Bit Bit Name Initial Value R/W Description 7 TXDMY 0 R/W Dummy Data Transmission Enable Enables or disables dummy data transmission from the QMO pin in single-SPI mode and the transmit buffer is empty. Specifically, if this bit is set to 1 when the transmit buffer is empty, 0 is output from the QMO pin as dummy data. This bit setting can be changed while the transmit end flag (TEND) in SPSR is 1. Otherwise, operation cannot be guaranteed. 0: Disables dummy data transmission. 1: Enables dummy data transmission. 6 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 911 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.10 Clock Delay Register (SPCKD) SPCKD sets a period (clock delay) from the beginning of QSSL signal assertion to QSPCLK oscillation when the QSPCLK delay setting enable bit (SCKDEN) in SPCMD0 to SPCMD3 is 1. If the contents of SPCKD are modified while the SPE bit in SPCR is 1, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3      2 1 0 SCKDL2 SCKDL1 SCKDL0 Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 SCKDL2 0 R/W Clock Delay Setting 1 SCKDL1 0 R/W 0 SCKDL0 0 R/W These bits set a period (clock delay) from the beginning of QSSL signal assertion to QSPCLK oscillation when the SCKDEN bit in SPCMD0 to SPCMD3 is 1. 000: 1.5 QSPCLK cycles 001: 2.5 QSPCLK cycles 010: 3.5 QSPCLK cycles 011: 4.5 QSPCLK cycles 100: 5.5 QSPCLK cycles 101: 6.5 QSPCLK cycles 110: 7.5 QSPCLK cycles 111: 8.5 QSPCLK cycles Page 912 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.11 Slave Select Negation Delay Register (SSLND) SSLND sets a period (QSSL negation delay) from the transmission of a final QSPCLK edge to the negation of the QSSL signal during a serial transfer when the QSSL negation delay setting enable bit (SLNDEN) in SPCMD0 to SPCMD3 is 1. If the contents of SSLND are modified while the SPE bit in SPCR is 1, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3      2 1 0 SLNDL2 SLNDL1 SLNDL0 Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 SLNDL2 0 R/W QSSL Negation Delay Setting 1 SLNDL1 0 R/W 0 SLNDL0 0 R/W These bits set a period (QSSL negation delay) from the transmission of a final QSPCLK edge to the negation of the QSSL signal during a serial transfer when the SLNDEN bit in SPCMD0 to SPCMD3 is 1. 000: 1 QSPCLK cycle 001: 2 QSPCLK cycles 010: 3 QSPCLK cycles 011: 4 QSPCLK cycles 100: 5 QSPCLK cycles 101: 6 QSPCLK cycles 110: 7 QSPCLK cycles 111: 8 QSPCLK cycles R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 913 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.12 Next-Access Delay Register (SPND) SPND sets a period (next-access delay) from termination of a serial transfer to the beginning of the next serial transfer when the next-access delay enable bit (SPNDEN) in SPCMD0 to SPCMD3 is 1. If the contents of SPND are modified while the SPE bit in SPCR is 1, the subsequent operation cannot be guaranteed. Bit: 7 6 5 4 3      2 1 0 SPNDL2 SPNDL1 SPNDL0 Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 SPNDL2 0 R/W Next-Access Delay Setting 1 SPNDL1 0 R/W 0 SPNDL0 0 R/W These bits set a period (next-access delay) from termination of a serial transfer to the beginning of the next serial transfer when the SPNDEN bit in SPCMD0 to SPCMD3 is 1. 000: 1 QSPCLK cycle 001: 2 QSPCLK cycles 010: 3 QSPCLK cycles 011: 4 QSPCLK cycles 100: 5 QSPCLK cycles 101: 6 QSPCLK cycles 110: 7 QSPCLK cycles 111: 8 QSPCLK cycles Page 914 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.13 Command Register n (SPCMDn) (n = 0 to 3) Each channel has four command registers (SPCMD0 to SPCMD3). SPCMD0 to SPCMD3 are used to set a transfer format. This module sequentially references SPCMD0 to SPCMD3 according to the settings in the sequence control register (SPSCR), and executes the serial transfer that is set in the referenced SPCMD. If the contents of currently referred-to SPCMD are modified while the TEND bit in SPSR indicates that communication has not been completed, the subsequent operation cannot be guaranteed. The currently referred-to SPCMD can be checked by reading the sequence status register (SPSSR). Bit: 15 14 13 12 SCKDEN SLNDEN SPNDEN Initial Value: 1 R/W: R/W 11 10 9 8 7 6 LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD 1 5 SPIMOD 0 4 3 2 1 0 SPRW BRDV1 BRDV0 CPOL CPHA 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 SCKDEN 1 R/W Clock Delay Setting Enable Sets a period (clock delay) from the beginning of QSSL signal assertion to QSPCLK oscillation. If this bit is 0, this module sets the clock delay to 0 QSPCLK cycle. If this bit is 1, this module starts QSPCLK oscillation in compliance with the clock delay register (SPCKD) settings. For the continuous access in which QSSL is kept asserted over the multiple commands, this bit can be set to 0 only when the pertinent command is the second or subsequent one. Otherwise, this bit should be set to 1. 0: A clock delay of 0 QSPCLK cycle 1: A clock delay equal to SPCKD settings. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 915 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 14 SLNDEN 1 R/W QSSL Negation Delay Setting Enable Sets a period (QSSL negation delay) from QSPCLK oscillation stoppage to QSSL signal negation. If this bit is 0, this module sets the QSSL negation delay to 0 QSPCLK cycle. If this bit is 1, this module negates the QSSL signal in compliance with the slave select negation delay register (SSLND) settings. For the continuous access in which QSSL is kept asserted over the multiplier commands, this bit can be set to 0 only when the pertinent command is not the last one. Otherwise, this bit should be set to 1. 0: An QSSL negation delay of 0 QSPCLK cycle 1: An QSSL negation delay equal to SSLND settings. 13 SPNDEN 1 R/W Next-Access Delay Enable Sets the period (next-access delay) from termination of a serial transfer to the beginning of the next serial transfer. If this bit is 0, this module sets the nextaccess delay to 0 QSPCLK cycle. If this bit is 1, this module starts next serial transfer in compliance with the next-access delay register (SPND) settings. For the continuous access in which QSSL is kept asserted over the multiple commands, this bit can be set to 0 only when the pertinent command is not the last one. Otherwise, this bit should be set to 1. 0: A next-access delay of 0 QSPCLK cycle. 1: A next-access delay equal to SPND settings. 12 LSBF 0 R/W LSB First Sets the data format to MSB first or LSB first. 0: MSB first 1: LSB first Page 916 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 11 SPB3 0 R/W Transfer Data Length Setting 10 SPB2 0 R/W 9 SPB1 0 R/W 8 SPB0 0 R/W These bits set the basic transfer data length for serial transfer. For LSB-first transfer, the transfer data is reversed within the data width specified with these bits. The actual amount of data to be transferred is determined by multiplying the value set with these bits by the value set with SPBMUL0 to SPBMUL3. 0000: 8 bits (1 byte) 0001: 16 bits (2 bytes) 0010: 32 bits (4 bytes) 0011 to 1111: Setting prohibited 7 SSLKP 0 R/W QSSL Signal Level Keeping Specifies whether the QSSL signal level for the current command is to be kept or not from the end of the transfer for the current command to the beginning of the transfer for the next command. Setting this bit to 1 enables a transition to the next access while the QSSL signal is kept asserted. 0: Negates all QSSL signals upon completion of transfer. 1: Keeps the QSSL signal level from the end of the transfer to the beginning of the next access. 6 SPIMOD1 0 R/W SPI Operating Mode 5 SPIMOD0 0 R/W These bits select the operating mode from single-, dual-, or quad-SPI. 00: Single-SPI 01: Dual-SPI 10: Quad-SPI 11: Setting prohibited 4 SPRW 0 R/W SPI Read/Write Access Sets an access direction in dual-/quad-SPI modes. This bit is invalid in single-SPI mode 0: Write operation (QIO1 and QIO0/QIO3 to QIO0: Output) 1: Read operation (QIO1 and QIO0/QIO3 to QIO0: Input) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 917 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Bit Bit Name Initial Value R/W Description 3 BRDV1 0 R/W 2 BRDV0 0 R/W Bit Rate Frequency Division Setting The settings of this field and of the bit rate register (SPBR) together determine the bit rate. The base bit rate depends on the setting of the SPBR. The setting of this field selects division of the base bit rate by one, two, four, or eight. Individual BRDV [1:0] values can be set in each of command registers 0 to 3. Therefore, serial transfers can be at different bit rates for each of the commands. 00: Base bit rate 01: Two division of the base 10: Four division of the base 11: Eight division of the base Note: In transmission, set SPBR and these bits that the division ratio of QSPCLK is 2 or more. 1 CPOL 0 R/W QSPCLK Polarity Setting Sets an QSPCLK polarity. When data communication is performed between the Renesas quad serial peripheral interface module and the other modules, the same QSPCLK polarity should be set for both modules. 0: Positive (QSPCLK = 0 when idle) 1: Negative (QSPCLK = 1 when idle) 0 CPHA 1 R/W QSPCLK Phase Setting Sets an QSPCLK edge for latching and shifting data to be transferred. When data communication is performed between the Renesas quad serial peripheral interface module and the other modules, the same QSPCLK edge should be set for both modules. 0: Data latch on odd edge, data shift on even edge 1: Data shift on odd edge, data latch on even edge Note: The first QSPCLK edge is treated as the first edge. Page 918 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Reference: Some serial flash memory datasheets refer to QSPCLK specifications, which are determined by what this document refers to as CPOL and CPHA bits, as SPI modes 0 to 3. Assuming that SPI modes 0 to 3 are controlled by SPI mode bits [1:0], CPOL and CPHA in this document correspond to SPI mode bits 1 and 0, respectively. In this module, the initial values of CPOL and CPHA are 0 and 1, respectively, selecting SPI mode 1 as the initial mode. Notes: 1. When setting any or all of the clock delay period, QSSL negation delay period, and next-access delay period to 0, be sure to set SSLKP to 1 to select the continuous access in which QSSL is not negated. Otherwise, operation cannot be guaranteed. For the method of setting the various delay periods for the continuous access in which QSSL is not negated, see below. 2. For the continuous access in which QSSL is not negated, QSPCLK clock stopping is followed by the QSSL negation delay period, next-access delay period, and next command clock delay period, in this order. When setting any of the QSSL negation delay setting enable bit (SLNDEN), next-access delay enable bit (SPNDEN), and clock delay setting enable bit (SCKDEN) to 0, be sure to set the bit corresponding to the later period prior to the bit corresponding to the earlier period. (1) (2) (3) QSPCLK QSSL In the above figure, (1), (2), and (3) refer to the QSSL negation delay period, next-access delay period, and next command clock delay period, respectively. When setting any of these bits to 0, be sure to set (3) first. In other words, setting 1 after 0 as in (1), (2), (3)  0, 0, 1, 0, 1, 1, 0, 1, 0 … is prohibited. Allowed setting is (1), (2), (3)  1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0. If set otherwise, operation cannot be guaranteed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 919 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Notes: 1. When changing BRDV[1:0] or CPOL for each command for the continuous access in which the QSSL level is held, be sure to insert the QSSL negation delay period, nextaccess delay period, and clock delay period between commands. Otherwise, operation cannot be guaranteed. 2. A clock polarity changing point may be detected as a clock edge if CPOL is changed with the QSSL level held. Clock polarity changing point QSPCLK QSSL Note: When changing SPIMOD[1:0] or CPHA for each command for the continuous access in which the QSSL level is held, be sure to insert one cycle or more between commands. Otherwise, operation cannot be guaranteed. (This also applies to write-to-read or read-to-write switching in dual-/quad-SPI modes.) In the figure below, the data line is driven during the command n period if command n is for dual-/quad-SPI write access. Delay period QSPCLK QSSL Command n Page 920 of 3092 Command n+1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.14 Buffer Control Register (SPBFCR) SPBFCR resets the number of data units in the transmit buffer (SPTXB) or receive buffer (SPRXB) and sets the number of triggering data units. 7 Bit: 6 5 4 TXRST RXRST TXTRG1 TXTRG0 Initial Value: R/W: 3  2 1 0 RXTRG2 RXTRG1 RXTRG0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 TXRST 0 R/W Transmit Buffer Data Reset Invalidates transmit data in the transmit buffer and resets the transmit buffer to an empty state. 0: Allows the transmit buffer normal operation. 1: Resets the transmit buffer. 6 RXRST 0 R/W Receive Buffer Data Reset Invalidates receive data in the receive buffer and resets the receive buffer to an empty state. 0: Allows the receive buffer normal operation. 1: Resets the receive buffer. 5 TXTRG1 0 R/W Transmit Buffer Data Triggering Number 4 TXTRG0 0 R/W Specifies the timing at which the transmit buffer empty state is determined, that is when the SPTEF flag in the status register is set. When the number of bytes of data in the transmit buffer (SPTXB) is equal to or less than the specified triggering number, the SPTEF flag is set to 1. 00: 31 bytes (1 byte available) 01: 30 bytes (2 bytes available) 10: 28 bytes (4 bytes available) 11: 0 bytes (32 bytes available) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 921 of 3092 Section 18 Renesas Quad Serial Peripheral Interface SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 RXTRG2 0 R/W Receive Buffer Data Triggering Number 1 RXTRG1 0 R/W 0 RXTRG0 0 R/W Specifies the timing at which the receive buffer full state is determined, that is when the SPRFF flag in the status register is set. When the number of bytes of data in the receive buffer (SPRXB) is equal to or greater than the specified triggering number, the SPRFF flag is set to 1. 000: 1 byte (31 bytes available) 001: 2 bytes (30 bytes available) 010: 4 bytes (28 bytes available) 011: 5 bytes (27 bytes available) 100: 8 bytes (24 bytes available) 101: 16 bytes (16 bytes available) 110: 24 bytes (8 bytes available) 111: 32 bytes (0 byte available) Page 922 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.15 Buffer Data Count Register (SPBDCR) SPBDCR indicates the number of data units stored in the transmit buffer (SPTXB) and receive buffer (SPRXB). The upper eight bits indicate the number of transmit data units in the transmit buffer and the lower eight bits indicate the number of receive data units in the receive buffer. Bit: 15 14   13 12 11 10 9 8 TXBC5 TXBC4 TXBC3 TXBC2 TXBC1 TXBC0 7 6   5 4 3 2 1 0 RXBC5 RXBC4 RXBC3 RXBC2 RXBC1 RXBC0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 to 8 TXBC[5:0] 000000 R Transmit Data Byte Counter Indicates the number of transmit data bytes in the transmit data buffer (SPTXB). B'000000 indicates that SPTXB is empty. B'100000 indicates that SPTXB is full. 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 RXBC[5:0] 000000 R Receive Data Byte Counter Indicates the number of receive data bytes in the receive data buffer (SPRXB). B'000000 indicates that SPRXB is empty. B'100000 indicates that SPRXB is full. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 923 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.3.16 Transfer Data Length Multiplier Setting Register n (SPBMULn) (n = 0, 1, 2, 3) SPBMUL0 to SPBMUL3 set the number of times to transfer the specific length of data defined by the transfer data length setting bits (SPB[3:0]) in SPCMD0 to SPCMD3. SPBMUL0 to SPBMUL3 correspond to SPCMD0 to SPCMD3, respectively. If a command register is referred to while the TEND bit in SPSR indicates that communication has not been completed and SPBMUL corresponding to the referred-to command register is modified, the subsequent operation is not guaranteed. The currently referred-to command register can be checked by reading the sequence status register (SPSSR). Bit: 31 30 29 28 27 26 25 24 23 22 21 SPBMUL [31:24] Initial Value: 0 R/W: R/W Bit: 15 0 R/W: R/W 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPBMUL [15:8] Initial Value: 20 SPBMUL [23:16] SPBMUL [7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 0 SPBMUL [31:0] Initial Value R/W Description H'00000001 R/W Transfer Data Length Multiplier Setting These bits set the multiplier for transfer data; that is, the number of times to transfer the specific length of data defined by SPB3 to SPB0 bits in SPCMD0 to SPCMD3. The actual amount of data to be transferred is determined by SPB[3:0] SPBMUL[31:0]. Setting these bits to H'00000000 allows the defined size of data to be transferred 4,294,967,296 times. Page 924 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.4 Section 18 Renesas Quad Serial Peripheral Interface Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data, and the QSSL negation period means the idle period. 18.4.1 Overview of Operations This module is capable of serial transfers in single-/dual-/quad-SPI modes. Table 18.4 gives the features of single-/dual-/quad-SPI modes. Table 18.4 Features of Each SPI Mode Single-SPI Dual-SPI Quad-SPI Number of data lines One input line and one output line Two IO lines Four IO lines Data line direction Single-directional Bidirectional Bidirectional Simultaneous transmission/reception Supported Not supported Not supported R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 925 of 3092 Section 18 Renesas Quad Serial Peripheral Interface SH7268 Group, SH7269 Group Table 18.5 gives the overview of operation. Table 18.5 Overview of Operation Items Specification QSPCLK signal Output QMO signal (single-SPI) Output QMI signal (single-SPI) Input QIO1 and QIO0 (dual-SPI)/ QIO3 to QIO0 (quad-SPI) Input/output QSSL signal Output Switching QSSL polarity Supported Transfer rate Up to P1 Clock source On-chip baud rate generator Clock polarity Positive/negative Clock phase Latch at rising/output at falling Latch at falling/output at rising Transfer bit order MSB first/LSB first Transfer data length (8/16/32)  (1 to 4,294,967,296) bits Burst transfer Supported QSPCLK delay control Supported QSSL negation delay control Supported Next-access delay control Supported Transfer start method Writing data to the transmit buffer when SPE = 1 There is space in the receive buffer when SPE = 1* Sequence control Supported Transmit buffer empty detection Supported Receive buffer full detection Supported Note: * During single-SPI operation and dual-/quad-SPI mode write operation, a transfer is started by setting SPE to 1 and writing data to the transmit buffer. During dual-/quadSPI mode read operation, a transfer is started by setting SPE to 1 when there is space for the specified length of data in the receive buffer. Page 926 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.4.2 Section 18 Renesas Quad Serial Peripheral Interface Pin Control This module automatically switches the pin states according to the status after write/read transfer in single-/dual-/quad-SPI mode. The status of the data pins (QMO/QMI/QIO[3:0]) in the idle state depends on the MOIFE and MOIFV bit settings, the single-/dual-SPI mode QIO3 output fixed value bit (IO3FV) setting in, and the single-/dual-SPI mode QIO2 output fixed value bit (IO2FV) setting. Table 18.6 shows the pin states in single-SPI mode. Table 18.7 shows the pin states in dual-/quad-SPI modes. Table 18.6 Pin States in Single-SPI Mode Items Single-SPI Mode QSSL Output QSPCLK Output QMO Output QMI Input QMO in the idle state MOIFE = 0: Final output value MOIFE = 1: MOIFV setting value QMI in the idle state  QIO2 IO2FV setting value output or not used QIO3 IO3FV setting value output or not used R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 927 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Table 18.7 Pin States in Dual-/Quad-SPI Mode Items Dual-SPI Mode Quad-SPI Mode QSSL Output Output QSPCLK Output Output QIO0 I/O I/O QIO1 I/O I/O QIO2 IO2FV setting value output or not used I/O QIO3 IO3FV setting value output or not used I/O After writing: After writing: QIO0 in the idle state MOIFE = 0: Final output value MOIFE = 0: Final output value MOIFE = 1: MOIFV setting value MOIFE = 1: MOIFV setting value After reading: Hi-Z After reading: Hi-Z QIO1 in the idle state After writing: After writing: MOIFE = 0: Final output value MOIFE = 0: Final output value MOIFE = 1: MOIFV setting value MOIFE = 1: MOIFV setting value After reading: Hi-Z After reading: Hi-Z QIO2 in the idle state QIO3 in the idle state 18.4.3 IO2FV setting value output or not used After writing: IO3FV setting value output or not used After writing: MOIFE = 0: Final output value MOIFE = 1: MOIFV setting value After reading: Hi-Z MOIFE = 0: Final output value MOIFE = 1: MOIFV setting value After reading: Hi-Z Transfer Format The SPI has four clock settings determined by the QSPCLK polarity setting (CPOL) and QSPCLK phase setting (CPHA) bits in SPCMD0 to SPCMD3. Figure 18.1 shows the data latch/shift timing based on each setting in an 8-bit MSB first transfer. In figure 18.1, L indicates the latch timing and S indicates the shift timing. DATA corresponds to QMI/QMO in single-SPI mode; QIO1 and QIO0 in dual-SPI mode; or QIO3 to QIO0 in quad-SPI mode. tckd indicates the clock delay period when the SCKDEN bit in SPCMD0 to SPCMD3 is set to 1. Similarly, tslnd indicates the QSSL negation delay period when the SLNDEN bit in SPCMD0 to SPCMD3 is set to 1, and tspnd indicates the next-access delay period when the SPNDEN bit in SPCMD0 to SPCMD3 is set to 1. Page 928 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface CPOL = 0 (Positive polarity) CPHA = 0 (latch at rising, shift at falling) L S L S L S L S L S L S L S L D5 D4 D3 D2 D1 D0 S L S L QSPCLK QSSL D7 DATA D6 CPOL = 0 (Positive polarity) CPHA = 1 (shift at rising, latch at falling) S L S L S L S L S L S L QSPCLK QSSL D7 DATA D6 D5 D4 D3 D2 D1 D0 CPOL = 1 (Negative polarity) CPHA = 0 (latch at falling, shift at rising) L S L S L S L S L S L S L S L D7 D6 D5 D4 D3 D2 D1 D0 S L S L QSPCLK QSSL DATA CPOL = 1 (Negative polarity) CPHA = 1 (shift at falling, latch at rising) S L S L S L S L S L S L QSPCLK QSSL D7 DATA D6 D5 D4 D3 D2 D1 tckd D0 tslnd tspnd Note: When QSSL is low-active Figure 18.1 SPI Clock Setting and Transfer Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 929 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Note that when the base bit rate is used, transmission and reception when CPHA = 0 is not available. The following describes 8-bit MSB first transfer in single-/dual-/quad-SPI modes when CPOL = 0 and CPHA = 0. (1) Single-SPI Mode Figure 18.2 shows the transfer format in single-SPI mode. This mode provides transmission and reception simultaneously. Since one data line is used for serial communication both in transmission and reception, the communication speed is 1 bit per QSPCLK clock cycle. Transfer data is specified using SPCMD0 to SPCMD3. For details of transfer data, see section 18.4.4, Transfer Data. QSPCLK QSSL QMO T7 T6 T5 T4 T3 T2 T1 T0 QMI R7 R6 R5 R4 R3 R2 R1 R0 Figure 18.2 Transfer Format in Single-SPI Format (2) Dual-SPI Mode Figure 18.3 shows the transfer format in dual-SPI mode. This mode only provides operation of a single direction, that is, either transmission or reception. Transmission or reception can be set using the SPI read/write access setting bit (SPRW) in SPCMD0 to SPCMD3. Transmission is carried out by write operation and reception by read operation. The IO directions of QIO1 and QIO0 are switched accordingly. Since two data lines are used for serial communication both in transmission and reception, the communication speed is 2 bits per QSPCLK clock cycle. The start bit of the transfer data is output from QIO1. Transfer data is specified using SPCMD0 to SPCMD3. For details of transfer data, see section 18.4.4, Transfer Data. QSPCLK QSSL QIO1 D7 D5 D3 D1 QIO0 D6 D4 D2 D0 Figure 18.3 Transfer Format in Dual-SPI Format Page 930 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 18 Renesas Quad Serial Peripheral Interface Quad-SPI Mode Figure 18.4 shows the transfer format in quad-SPI mode. This mode provides operation of a single direction, that is, either transmission or reception. Transmission or reception can be set using the SPRW bit in SPCMD0 to SPCMD3. Transmission and reception are accomplished by writing and reading, respectively. The IO directions of QIO3 to QIO0 are switched accordingly. Since four data lines are used for serial communication both in transmission and reception, the communication speed is 4 bits per QSPCLK clock cycle. The start bit of the transfer data is output from QIO3. Transfer data is specified using SPCMD0 to SPCMD3. For details of transfer data, see section 18.4.4, Transfer Data. QSPCLK QSSL QIO3 D7 D3 QIO2 D6 D2 QIO1 D5 D1 QIO0 D4 D0 Figure 18.4 Transfer Format in Quad-SPI Format 18.4.4 Transfer Data The data format is determined by the SPB3 to SPB0 and the LSB first (LSBF) bits in SPCMD0 to SPCMD3 and SPBMUL0 to SPBMUL3. In both MSB first and LSB first transfers, this module treats the specified size of data beginning at the MSB of the transmit shift register as transmit data, and the specified length of data beginning at the LSB of the receive shift register as receive data, regardless of whether the actual arrangement is MSB or LSB-first. The following sections describe MSB first and LSB first transfers in 32-bit, 16-bit, and 8-bit data units. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 931 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface (1) MSB First Transfer (32-Bit Data) Figure 18.5 shows the operation of the transmit buffer and transmit shift register, and the receive shift register and receive buffer when this module performs a 32-bit MSB-first data transfer. For data transmission, the CPU or direct memory access controller writes 32-bit transmit data to the transmit buffer (SPTXB). If the transmit shift register is empty, this module copies the data with MSB-aligned in the transmit buffer to the transmit shift register, and fills the transmit shift register. When data transmission is started, this module outputs data beginning at the MSB (bit 31) of the transmit shift register, and when the QSPCLK clock cycle required for the serial transfer of 32 bits has passed, the transmit shift register becomes empty. For data reception, data received from the data pin is stored in the receive shift register beginning at the LSB (bit 0). When the QSPCLK clock cycle required for the serial transfer of 32 bits has passed, the receive shift register becomes full. If the receive buffer (SPRXB) has a space for 32 bits or more, this module copies the 32-bit data beginning at the LSB from the receive shift register to the receive buffer, and empties the receive shift register. If the receive buffer does not have a space for 32 bits or more, data reception is not carried out. In order to start reception, the specified length of data should be read from the receive buffer to secure the space for 32 bits or more in the receive buffer. In actual transfer, this operation is repeated for the number of times defined by SPBMUL0 to SPBMUL3. Transmit buffer (SPTXB) T31 T30 T29 T28 T27 T26 ... ... ... T27 T26 ... ... ... T31 T30 T29 T28 R27 R26 ... ... ... T05 T04 T03 T02 T01 T00 ... T05 T04 T03 T02 T01 T00 ... R05 R04 R03 R02 R01 R00 ... R05 R04 R03 R02 R01 R00 Copy Transmit shift register Output ... Receive shift register R31 R30 R29 R28 Receive buffer (SPRXB) R31 R30 R29 R28 Input Copy R27 R26 ... ... ... Figure 18.5 MSB First Transfer (32-Bit Data) Page 932 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 18 Renesas Quad Serial Peripheral Interface MSB First Transfer (16-Bit Data) Figure 18.6 shows the operation of the transmit buffer and transmit shift register, and the receive shift register and receive buffer when this module performs a 16-bit MSB-first data transfer. For data transmission, the CPU or direct memory access controller writes 16-bit transmit data to the transmit buffer (SPTXB). If the transmit shift register is empty, this module copies the data with MSB-aligned in the transmit buffer to the transmit shift register, and fills the transmit shift register. When data transmission is started, this module outputs data beginning at the MSB (bit 31) of the transmit shift register, and when the QSPCLK clock cycle required for the serial transfer of 16 bits has passed, the transmit shift register becomes empty. For data reception, data received from the data pin is stored in the receive shift register beginning at the LSB (bit 0). When the QSPCLK clock cycle required for the serial transfer of 16 bits has passed, the receive shift register becomes full. If the receive buffer (SPRXB) has a space for 16 bits or more, this module copies the 16-bit data beginning at the LSB from the receive shift register to the receive buffer, and empties the receive shift register. If the receive buffer does not have a space for 16 bits or more, data reception is not carried out. In order to start reception, the specified length of data should be read from the receive buffer to secure the space for 16 bits or more in the receive buffer. In actual transfer, this operation is repeated for the number of times defined by SPBMUL0 to SPBMUL3. Transmit buffer (SPTXB) T15 T14 T13 ... ... T15 T14 T13 ... T01 T00 Copy Transmit shift register Output T02 ... T02 T01 T00 xxx xxx xxx ... ... xxx xxx xxx ... xxx xxx xxx R15 R14 R13 ... ... R02 R01 R00 R01 R00 Receive shift register xxx xxx xxx ... Copy Receive buffer (SPRXB) R15 R14 R13 ... Input ... R02 Figure 18.6 MSB First Transfer (16-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 933 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface (3) MSB First Transfer (8-Bit Data) Figure 18.7 shows the operation of the transmit buffer and transmit shift register, and the receive shift register and receive buffer when this module performs an 8-bit MSB-first data transfer. For data transmission, the CPU or direct memory access controller writes 8-bit transmit data to the transmit buffer (SPTXB). If the transmit shift register is empty, this module copies the data with MSB-aligned in the transmit buffer to the transmit shift register, and fills the transmit shift register. When data transmission is started, this module outputs data beginning at the MSB (bit 31) of the transmit shift register, and when the QSPCLK clock cycle required for the serial transfer of 8 bits has passed, the transmit shift register becomes empty. For data reception, data received from the data pin is stored in the receive shift register beginning at the LSB (bit 0). When the QSPCLK clock cycle required for the serial transfer of 8 bits has passed, the receive shift register becomes full. If the receive buffer (SPRXB) has a space for 8 bits or more, this module copies the 8-bit data beginning at the LSB from the receive shift register to the receive buffer, and empties the receive shift register. If the receive buffer does not have a space for 8 bits or more, data reception is not carried out. In order to start reception, data for the specified length of data should be read from the receive buffer to secure the space for 8 bits or more in the receive buffer. In actual transfer, this operation is repeated for the number of times defined by SPBMUL0 to SPBMUL3. Transmit buffer (SPTXB) T07 T06 T05 T04 Transmit shift register Output T07 T06 T05 T04 T03 T02 T01 T00 Copy T03 T02 T01 T00 xxx xxx xxx ... ... xxx xxx xxx ... xxx xxx xxx R07 R06 R05 R04 R03 R02 R01 R00 R01 R00 Receive shift register xxx xxx xxx ... Receive buffer (SPRXB) R07 R06 R05 R04 Input Copy R03 R02 Figure 18.7 MSB First Transfer (8-Bit Data) Page 934 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 18 Renesas Quad Serial Peripheral Interface LSB First Transfer (32-Bit Data) Figure 18.8 shows the operation of the transmit buffer and transmit shift register, and the receive shift register and receive buffer when this module performs a 32-bit LSB-first data transfer. For data transmission, the CPU or direct memory access controller writes 32-bit transmit data to the transmit buffer (SPTXB). If the transmit shift register is empty, this module reverses the bit order in the 32-bit transmit data, copies it with MSB-aligned to the transmit shift register, and fills the transmit shift register. When data transmission is started, this module outputs data beginning at the MSB (bit 31) of the transmit shift register, and when the QSPCLK clock cycle required for the serial transfer of 32 bits has passed, the transmit shift register becomes empty. For data reception, data received from the data pin is stored in the receive shift register beginning at the LSB (bit 0). When the QSPCLK clock cycle required for the serial transfer of 32 bits has passed, the receive shift register becomes full. If the receive buffer (SPRXB) has a space for 32 bits or more, this module reverses the order of the bits of the 32-bit data, copies it beginning at the LSB from the receive shift register to the receive buffer, and empties the receive shift register. If the receive buffer does not have a space for 32 bits or more, data reception is not carried out. In order to start reception, the specified length of data should be read from the receive buffer to secure the space for 32 bits or more in the receive buffer. In actual transfer, this operation is repeated for the number of times defined by SPBMUL0 to SPBMUL3. Transmit buffer (SPTXB) T31 T30 T29 T28 T27 T26 ... ... ... T04 T05 ... ... ... T00 T01 T02 T03 R04 R05 ... ... ... R27 R26 ... ... ... T05 T04 T03 T02 T01 T00 ... T26 T27 T28 T29 T30 T31 ... R26 R27 R28 R29 R30 R31 R05 R04 R03 R02 R01 R00 Copy Transmit shift register Output ... Receive shift register R00 R01 R02 R03 Copy Receive buffer (SPRXB) R31 R30 R29 R28 Input ... Figure 18.8 LSB First Transfer (32-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 935 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface (5) LSB First Transfer (16-Bit Data) Figure 18.9 shows the operation of the transmit buffer and transmit shift register, and the receive shift register and receive buffer when this module performs a 16-bit LSB-first data transfer. For data transmission, the CPU or direct memory access controller writes 16-bit transmit data to the transmit buffer (SPTXB). If the transmit shift register is empty, this module reverses the bit order in the 16-bit transmit data, copies it with MSB-aligned to the transmit shift register, and fills the transmit shift register. When data transmission is started, this module outputs data beginning at the MSB (bit 31) of the transmit shift register, and when the QSPCLK clock cycle required for the serial transfer of 16 bits has passed, the transmit shift register becomes empty. For data reception, data received from the data pin is stored in the receive shift register beginning at the LSB (bit 0). When the QSPCLK clock cycle required for the serial transfer of 16 bits has passed, the receive shift register becomes full. If the receive buffer (SPRXB) has a space for 16 bits or more, this module reverses the bit order in the 16-bit data, copies it beginning at the LSB from the receive shift register to the receive buffer, and empties the receive shift register. If the receive buffer does not have a space for 16 bits or more, data reception is not carried out. In order to start reception, the specified length of data should be read from the receive buffer to secure the space for 16 bits or more in the receive buffer. In actual transfer, this operation is repeated for the number of times defined by SPBMUL0 to SPBMUL3. Transmit buffer (SPTXB) T15 T14 T13 ... ... ... ... T00 T01 T02 ... ... T01 T00 T13 T14 T15 xxx xxx xxx ... ... xxx xxx xxx xxx xxx xxx R00 R01 R02 ... ... R13 R14 R15 R01 R00 Copy Transmit shift register Output T02 Receive shift register xxx xxx xxx Receive buffer (SPRXB) R15 R14 R13 ... Input Copy ... R02 Figure 18.9 LSB First Transfer (16-Bit Data) Page 936 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 18 Renesas Quad Serial Peripheral Interface LSB First Transfer (8-Bit Data) Figure 18.10 shows the operation of the transmit buffer and transmit shift register, and the receive shift register and receive buffer when this module performs an 8-bit LSB-first data transfer. For data transmission, the CPU or direct memory access controller writes 8-bit transmit data to the transmit buffer (SPTXB). If the transmit shift register is empty, this module reverses the bit order in the 8-bit transmit data, copies it with MSB-aligned to the transmit shift register, and fills the transmit shift register. When data transmission is started, this module outputs data beginning at the MSB (bit 31) of the transmit shift register, and when the QSPCLK clock cycle required for the serial transfer of 8 bits has passed, the transmit shift register becomes empty. For data reception, data received from the data pin is stored in the received shift register beginning at the LSB (bit 0). When the QSPCLK clock cycle required for the serial transfer of 8 bits has passed, the receive shift register becomes full. If the receive buffer (SPRXB) has a space for 8 bits or more, this module reverses the bit order in the 8-bit data, copies it beginning at the LSB from the receive shift register to the receive buffer, and empties the receive shift register. If the receive buffer does not have a space for 8 bits or more, data reception is not carried out. In order to start reception, the specified length of data should be read from the receive buffer to secure the space for 8 bits or more in the receive buffer. In actual transfer, this operation is repeated for the number of times defined by SPBMUL0 to SPBMUL3. Transmit buffer (SPTXB) T07 T06 T05 T04 T00 T01 T02 T02 T01 T00 Copy Transmit shift register Output T03 T03 T04 T05 T06 T07 xxx xxx xxx ... ... xxx xxx xxx ... xxx xxx xxx R00 R01 R02 R03 R04 R05 R06 R07 R01 R00 Receive shift register xxx xxx xxx ... Receive buffer (SPRXB) R07 R06 R05 R04 Input Copy R03 R02 Figure 18.10 LSB First Transfer (8-Bit Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 937 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.4.5 Non-Normal Transfer Operations In the normal serial transfer, the data written from SPDR to the transmit buffer is serially transmitted, and the serially received data can be read from the receive buffer of SPDR. If access is made to SPDR, depending on the status of the transmit buffer/receive buffer, in some cases nonnormal transfers can be executed. Table 18.8 shows the relationship between non-normal transfer operations. Table 18.8 Relationship between Non-Normal Transfer Operations Occurrence Condition Operation A SPDR is written when the transmit buffer is full. Missing write data. B SPDR is read when the receive buffer is The output data is undefined. empty. On operation A shown in table 18.8, whether SPDR can be written to or not can be checked using the transmit data byte counter bits (TXBC[5:0]) in the buffer data count register (SPBDCR). Similarly, on operation B shown in table 18.8, whether the valid data is stored in the receive buffer or not can be checked by reading the receive data byte counter bits (RXBC[5:0]) in SPBDCR. Page 938 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.4.6 Section 18 Renesas Quad Serial Peripheral Interface Initialization If 0 is written to the SPE bit in SPCR, this module disables the module function, and initializes a part of the module function. When a power-on reset is generated, this module initializes all of the module function. When the SPE bit in SPCR is cleared to 0, this module performs the following initialization:      Suspending any serial transfer that is being executed Initializing the transmit shift register and the receive shift register Initializing the internal state machine Initializing the sequence Initializing the TEND bit in SPSR Initialization by the clearing of the SPE bit to 0 does not initialize the control bits of this module and the transmit/receive buffer. For this reason, this module can be started in the same transfer mode as prior to the initialization if the SPE bit is re-set to 1. However, clearing the SPE bit to 0 initializes the transmit shift register and the receive shift register and allows the data that is being transferred to be discarded. 18.4.7 SPI Operation The operating modes of this module are listed below.  Single-SPI mode  Dual-SPI mode/quad-SPI mode The operation in each mode is described below. (1) Single-SPI Mode (a) Starting Serial Transfer The serial transfer start conditions are: there is the specified length of data in the transmit buffer; and there is space for the specified length of data in the receive buffer. (b) Terminating Serial Transfer Irrespective of the clock setting, this module terminates the serial transfer after transmitting an QSPCLK edge corresponding to the final sampling timing. After the serial transfer is completed, receive data is copied from the receive shift register to the receive buffer. If there is not enough space for the specified length of data in the receive buffer after receive data is copied from the receive shift register to the receive buffer, another serial transfer will not be performed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 939 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface (c) Sequence Control In single-SPI mode, according to the sequence length that is assigned to the sequence control register (SPSCR), this module makes up a sequence comprised of a part or all of SPCMD0 to SPCMD3 and SPBMUL0 to SPBMUL3. This module contains a pointer to the SPCMD that makes up the sequence. The value of this pointer can be checked by reading SPSSR. When the SPE bit in SPCR is set to 1 and the function of this module is enabled, this module loads the pointer to the commands in SPCMD0, and incorporates the SPCMD0 and SPBMUL0 settings into the transfer format at the beginning of serial transfer. This module increments the pointer each time the next-access delay period for a data transfer that corresponds to the referenced SPCMD0 to SPCMD3 ends. Upon completion of the serial transfer that corresponds to the final command comprising the sequence, this module sets the pointer in SPCMD0, and in this manner the sequence is executed repeatedly. The following items are set in command registers SPCMD0 to SPCMD3: basic transfer data length, MSB or LSB first, clock settings, some of the bit rate settings, SPI transfer mode and transfer direction (only in dual-/quad-SPI modes), whether QSSL level is held, a clock delay period, an QSSL negation delay period, and a next-access delay period. The total amount of data to be transferred is determined by multiplying the basic length of data to be transferred by the value set with SPBMUL0 to SPBMUL3. Figure 18.11 shows an operation example when SPSCR is set to H'02, and the sequence is configured based on SPCMD0 to SPCMD2 settings. In figure 18.11, shaded areas of QMO/QMI indicate invalid data. Periods (1) to (3) in figure 18.11 indicate the followings. (1) Clock delay period (SPCKD) setting value = B'000 (1.5 QSPCLK cycles) (2) QSSL negation delay period (QSSLND) setting value = B'000 (1 QSPCLK cycle) (3) Next-access delay period (SPND) setting value = B'000 (1 QSPCLK cycle) QSPCLK (CPOL = 0, CPHA = 0) (1) (2) (3) QSSL (Low-active) QMO/QMI SPCMD0 SPCMD1 SPCMD2 Figure 18.11 Sequence Control Operation Page 940 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (d) Section 18 Renesas Quad Serial Peripheral Interface Burst Transfer This module can execute burst transfer with the following two methods in single-SPI mode. One method uses the SPB[3:0] bits in SPCMD0 to SPCMD3 and SPBMUL0 to SPBMUL3. Setting SPB[3:0] to select 8, 16, or 32 bits and setting SPBMUL0 to SPBMUL3 to select one through 4,294,967,296 allows the specified length of data to be continuously transferred for the specified times, where the length is specified by SPB[3:0] and the number of times is specified by SPBMUL0 to SPBMUL3. However, if the transmit buffer (SPTXB) becomes empty during transfer, or the receive buffer (SPRXB) has no longer a space enough to receive the specified length of data defined by SPB[3:0], the clock is stopped until transfer is resumed. Figure 18.12 shows a burst transfer example in which SPB[3:0] are set to select 32 bits and SPBMUL to select four times thus specifying 128 bits as a total transfer data amount. The following describes operations (1) to (4) in the figure. (1) First 32-bit data transfer (2) Second 32-bit data transfer (3) When the transmit buffer becomes empty or the receive buffer has no longer a space for 32 or more bits, the clock is stopped. Here, the QMO continues outputting the previous value. When data is written to the transmit buffer or an enough space is created in the receive buffer, the clock output is resumed to restart transfer. (4) Third and fourth 32-bit data transfer QSPCLK (CPOL = 0, CPHA =0) QSSL (Low-active) QMO/QMI D0 D1 D2 (1) D30 D31 D32D33 D34 (2) D62 D63 D D 126 127 D64 D65 D66 (3) (4) Figure 18.12 Burst Transfer Example in which Total Transfer Data Amount is 128 Bits (Single-SPI Mode Used) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 941 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface In the other method, QSSL is kept asserted after a serial transfer is completed until the next serial transfer. Setting the QSSL signal level keeping bit (SSLKP) to 1 in SPCMD0 to SPCMD3 allows the QSSL signal to be kept asserted after the transfer corresponding to the pertinent command register is completed until the next transfer. Figure 18.13 shows a burst transfer example in which the QSSL signal level keeping function is used. The following describes operations (1) to (6) in the figure. (1) Clock delay period according to the SPCMD0 setting. The setting must be made so that the delay period should be at least 1.5 QSPCLK cycles for the first transfer in the burst transfer. (2) QSSL negation delay period according to the SPCMD0 setting. Since SSLKP is set to 1, QSSL is not negated even after QSSL negation delay period is over. The QSSL negation delay period depends on the SLNDEN bit setting in SPCMD0. When SLNDEN is 1, the QSSL negation delay period is determined by the SSLND setting, and the delay period is 0 QSPCLK cycle when SLNDEN is 0. (3) Next-access delay period according to the SPCMD0 setting. Since SSLKP is set to 1, QSSL is not negated even during the next-access delay period. The next-access delay period depends on the SPNDEN bit setting in SPCMD0. When SPNDEN is 1, the next-access delay period is determined by the SPND setting, and the delay period is 0 QSPCLK cycle when SPNDEN is 0. (4) Clock delay period according to the SPCMD1 setting. The clock delay period depends on the SCKDEN bit setting in SPCMD1. When SCKDEN is 1, the clock delay period is determined by the SPCKD setting, and the delay period is 0 QSPCLK cycle when SCKDEN is 0. (5) QSSL negation delay period according to the SPCMD1 setting. The setting must be made so that the delay period should be at least one QSPCLK cycle for the last transfer in the burst transfer. Since SSLKP in SPCMD1 is set to 0, QSSL is negated after QSSL negation delay period is over. (6) Next-access delay period according to the SPCMD1 setting. The setting must be made so that the delay period should be at least one QSPCLK cycle for the last transfer in the burst transfer. Be sure to set SSLKP to 0 to negate QSSL. (2) (3) (4) (1) (5) (6) QSPCLK (CPOL = 0, CPHA = 0) QSSL (Low-active) SPCMD0 SPCMD1 Figure 18.13 Burst Transfer Example in which QSSL Signal Level Keeping Function is Used (Single-SPI Mode) Page 942 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Note the following when specifying a burst transfer using this method. Periods (2) to (4) must be inserted without fail when changing the clock frequency division ratio or clock polarity through command update. When the clock frequency division ratio is changed, period (4) may be advanced or delayed with respect to the set value. At least period (2) must be inserted when changing the clock phase or transfer mode (single-/dual/quad-SPI) through command update (changing dual-/quad-SPI includes changing read/write operation). (e) Initialization Flowchart Figure 18.14 is a flowchart illustrating an example of initialization in SPI operation when this module is used in single-SPI mode. For a description of how to set up the interrupt controller and direct memory access controller, see the descriptions given in the individual blocks. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 943 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Start of initialization in singleSPI mode Set the slave select polarity register (SSLP) Sets QSSL signal level. Set the pin control register (SPPCR) Sets QMO signal value when transfer is in idle state. Set the bit rate register (SPBR) Set the clock delay register (SPCKD) Set the slave select negation delay register (SSLND) Set the next-access delay register (SPND) Sets transfer bit rate. Sets clock delay value. Sets QSSL negation delay value. Sets next-access delay value. Set the command registers 0 to 3 (SPCMD0 to SPCMD3) Sets clock delay enable. Sets QSSL negation delay enable. Sets next-access delay enable. Sets MSB or LSB first. Sets transfer data length. Sets transfer data length multiplier. Sets transfer bit rate. Sets transfer mode. Sets clock. Set the transfer data length multiplier setting registers 0 to 3 (SPBMUL0 to SPBMUL3) Sets transfer data length. Set the interrupt controller (when using an interrupt) Set the direct memory access controller Set the control register (SPCR) (when using the direct memory access controller) Enables SPI function. Sets interrupt mask. End of initialization in singleSPI mode Figure 18.14 Example of Initialization Flowchart in Single-SPI Mode Page 944 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (f) Section 18 Renesas Quad Serial Peripheral Interface Transfer Operation Flowchart Figure 18.15 is a flowchart illustrating a transfer in SPI operation when this module is used in single-SPI mode. Burst transfer by setting the transfer data length is also executed based on this flowchart. End of initialization in singleSPI mode Transmit buffer has the specified length of data NO YES Copy transmit data from transmit buffer to transmit shift register Receive buffer has a space for the specified length of data NO YES Start serial transfer QSPCLK cycle count < Shorter than transfer data length = Equal to transfer data length Copy receive data from receive shift register to receive buffer Update command pointer YES Continue serial transfer NO End of transfer Figure 18.15 Transfer Operation Flowchart in Single-SPI Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 945 of 3092 Section 18 Renesas Quad Serial Peripheral Interface (2) Dual-SPI/Quad-SPI Mode (a) Starting Serial Transfer SH7268 Group, SH7269 Group In dual-/quad-SPI modes, the serial transfer start condition is different depending on the data transfer direction (transmission or reception). In data transmission, the serial transfer start condition is that there is the specified length of data in the transmit buffer. In data reception, the serial transfer start condition is that there is a space for the specified length of data in the receive buffer. (b) Terminating Serial Transfer Irrespective of data transmission or reception, this module terminates the serial transfer after transmitting an QSPCLK edge corresponding to the final sampling timing. During idle cycles in dual-/quad-SPI modes, the IO pins are controlled differently depending on whether it is after write or read operation. Specifically, the IO pins output either the last output data or the fixed level depending on the register setting after write operation, whereas the IO pins are driven to the Hi-Z state after read operation. Figure 18.16 shows an example of the pin states after quad-SPI mode access is completed. The following describes operations (1) and (2) in the figure. (1) During write operation, QIO0 to QIO3 serve as output pins. Thus, when QSSL is negated upon completion of write operation, QIO0 to QIO3 output different values depending on the value of MOIFE in the SPPCR. Specifically, the IO pins output the level specified by MOIFV when MOIFE is 1, whereas the IO pins output the last output data when MOIFE is 0. (2) During read operation, QIO0 to QIO3 serve as input pins. Thus, when QSSL is negated upon completion of read operation, QIO0 to QIO3 are driven to Hi-Z state irrespective of the values of MOIFE and MOIFV. For details on the pin control in dual-/quad-SPI modes, see section 18.4.2, Pin Control. Page 946 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface QSPCLK (CPOL = 0, CPHA = 1) QSSL (Low-active) QIO0 QIO1 QIO2 QIO3 Write operation (1) Read operation (2) Figure 18.16 Example of Pin States after Quad-SPI Mode Access is Completed (c) Sequence Control As with the single-SPI mode, in dual-/quad-SPI modes, according to the sequence length that is assigned to SPSCR, this module makes up a sequence comprised of SPCMD0 to SPCMD3 and SPBMUL0 to SPBMUL3. For details on operation, see section 18.4.7 (1) (c), Sequence Control. Dual-/quad-SPI modes only provide operation of a single direction, that is, either transmission or reception for serial transfer. Transmission or reception is set using the SPI read/write access setting bit (SPRW) in SPCMD0 to SPCMD3. One of the three operating modes including dual-SPI mode, quad-SPI mode, and single-SPI mode is set using the SPI operating mode setting bits (SPIMOD[1:0]) in SPCMD0 to SPCMD3. Combining these bits allow switching single-SPI mode, dual-SPI mode transmission/reception, and quad-SPI mode transmission/reception to control sequence. Figure 18.17 shows an example of sequence configuration with transfer mode switching. QSPCLK (CPOL = 0, CPHA = 0) QSSL (Low-active) QMO/QIO0 QMI/QIO1 QIO2 Pin control register (SPPCR) setting value QIO3 Pin control register (SPPCR) setting value SPCMD0 single-SPI SPCMD1 dual-SPI transmission SPCMD2 quad-SPI reception Figure 18.17 Example of Sequence Configuration with Transfer Mode Switching R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 947 of 3092 Section 18 Renesas Quad Serial Peripheral Interface SH7268 Group, SH7269 Group Note the following when configuring a sequence in dual-/quad-SPI modes. When all the commands configuring a sequence are dual-/quad-SPI read operations, the sequential operation is continued as long as the receive buffer has an enough space for the receive data. To terminate read operation, clear the SPE bit to 0 in SPCR after receiving the required length of data, or execute write operation for the last sequence to empty the transmit buffer. (d) Burst Transfer This module can execute burst transfer with the following two methods in dual/quad SPI modes. One method uses the SPB[3:0] bits in SPCMD0 to SPCMD3 and SPBMUL0 to SPBMUL3. As with the single-SPI mode, setting SPB[3:0] to select 8, 16, or 32 bits and setting SPBMUL0 to SPBMUL3 to select one through 4,294,967,296 allows the specified length of data to be continuously transferred for the specified times, where the length is specified by SPB[3:0] and the number of times is specified by SPBMUL0 to SPBMUL3. However, if the transmit buffer (SPTXB) becomes empty during transfer, or the receive buffer (SPRXB) has no longer a space enough to receive the specified length of data defined by SPB[3:0], the clock is stopped until transfer is resumed. This method is effective to transfer a large amount of data in dual-/quad SPI modes. Figure 18.18 shows a burst transfer example in which SPB[3:0] are set to select 32 bits and SPBMUL to select four times thus specifying 128 bits as a total transfer data amount. The following describes operations (1) to (4) in the figure. (1) First 32-bit data transfer (2) Second 32-bit data transfer (3) When the transmit buffer becomes empty or the receive buffer has no longer a space for 32 or more bits, the clock is stopped. Here, when QIO3 to QIO0 serve as output pins, QIO3 to QIO0 continue outputting the previous value. When QIO3 to QIO0 serve as input pins, the inputs to QIO3 to QIO0 depend on the output value of the device to communicate with. When data is written to the transmit buffer or an enough space is created in the receive buffer, the clock output is resumed to restart transfer. (4) Third and fourth 32-bit data transfer Page 948 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface QSPCLK (CPOL = 0, CPHA = 0) QSSL (Low-active) QIO3 D0 D4 D8 D24 D28 D32D36 D40 D56 D60 D64 D68 D72 D D 120 124 QIO2 D1 D5 D9 D25 D29 D33D37 D41 D57 D61 D65 D69 D73 D D 121 125 QIO1 D2 D6 D10 D26 D30 D34D38 D42 D58 D62 D66 D70 D74 D D 122 126 QIO0 D3 D7 D11 D27 D31 D35D39 D43 D59 D63 D67 D71 D75 D D 123 127 (1) (2) (3) (4) Figure 18.18 Burst Transfer Example in which Total Transfer Data Amount is 128 Bits (Quad-SPI Mode) The other method uses the QSSL signal level keeping function as in single-SPI mode. Since this method allows switching the SPI transfer modes (single-/dual-/quad-SPI) during a transfer, it is particularly convenient when used with serial flash memory, where command data is written in single-SPI mode and data to be stored in memory is written in quad-SPI mode. Note, however, that at least one delay cycle should be inserted between transfers when switching the SPI transfer modes. Figure 18.19 shows a burst transfer example in which both single-SPI and quad-SPI modes are used. The following describes operations (1) to (6) in the figure. (1) Clock delay period according to the SPCMD0 setting. The setting must be made so that the delay period should be at least 1.5 QSPCLK cycles for the first transfer in the burst transfer. (2) QSSL negation delay period according to the SPCMD0 setting. Since SSLKP in SPCMD0 is set to 1, QSSL is not negated even after QSSL negation delay period is over. The QSSL negation delay period depends on the SLNDEN bit setting in SPCMD0. When SLNDEN is 1, the QSSL negation delay period is determined by the SSLND setting, and the delay period is 0 QSPCLK cycle when SLNDEN is 0. (3) Next-access delay period according to the SPCMD0 setting. Since SSLKP is set to 1, QSSL is not negated even during the next-access delay period. The next-access delay period depends on the SPNDEN bit setting in SPCMD0. When SPNDEN is 1, the next-access delay period is determined by the SPND setting, and the delay period is 0 QSPCLK cycle when SPNDEN is 0. Up to this period, the data pin is driven according to the SPCMD0 setting. (4) Clock delay period according to the SPCMD1 setting. The clock delay period depends on the SCKDEN bit setting in SPCMD1. When SCKDEN is 1, the clock delay period is determined by the SPCKD setting, and the delay period is 0 QSPCLK cycle when SCKDEN is 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 949 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface (5) QSSL negation delay period according to the SPCMD1 setting. The setting must be made so that the delay period should be at least one QSPCLK cycle for the last transfer in the burst transfer. Since SSLKP in SPCMD1 is set to 0, QSSL is negated after QSSL negation delay period is over. (6) Next-access delay period according to the SPCMD1 setting. The setting must be made so that the delay period should be at least one QSPCLK cycle for the last transfer in the burst transfer. Be sure to set SSLKP to 0 to negate QSSL. (1) (2) (3) (4) (5) (6) QSPCLK (CPOL = 0, CPHA = 0) QSSL (Low-active) QMO/QIO0 QMI/QIO1 QIO2 Pin control register (SPPCR) setting value QIO3 Pin control register (SPPCR) setting value SPCMD0 single-SPI SPCMD1 quad-SPI Figure 18.19 Burst Transfer Example in which QSSL Signal Level Keeping Function is Used (Single- and Quad-SPI Modes Used) Note the following when specifying a burst transfer using this method. Periods (2) to (4) must be inserted without fail when changing the clock frequency division ratio or clock polarity through command update. When the clock frequency division ratio is changed, period (4) may be advanced or delayed with respect to the set value. At least period (2) must be inserted when changing the clock phase or transfer mode (single-/ dual-/quad-SPI) through command update (changing dual-/quad-SPI includes changing read/write operation). (e) Initialization Flowchart Figure 18.20 is a flowchart illustrating an example of initialization in SPI operation when this module is used in dual-/quad-SPI mode. For a description of how to set up the interrupt controller and direct memory access controller, see the descriptions given in the individual blocks. Page 950 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface Start of initialization in dual-/ quad-SPI mode Set the slave select polarity register (SSLP) Sets QSSL signal level. Set the pin control register (SPPCR) Sets QIO3 to QIO0 signal values when transfer is in idle state. Set the bit rate register (SPBR) Set the clock delay register (SPCKD) Set the slave select negation delay register (SSLND) Set the next-access delay register (SPND) Sets transfer bit rate. Sets clock delay value. Sets QSSL negation delay value. Sets next-access delay value. Set the command registers 0 to 3 (SPCMD0 to SPCMD3) Sets SPI operating mode. Sets clock delay enable. Sets QSSLnegation delay enable. Sets next-access delay enable. Sets MSB or LSB first. Sets transfer data length. Sets transfer bit rate. Sets transfer mode. Sets clock. Set the transfer data length multiplier setting registers 0 to 3 (SPBMUL0 to SPBMUL3) Sets transfer data length. Set the interrupt controller (when using an interrupt) Set the direct memory access controller Set the control register (SPCR) (when using the direct memory access controller) Enables SPI function. Sets interrupt mask. End of initialization in dual-/ quad-SPI mode Figure 18.20 Example of Initialization Flowchart in Dual-/Quad-SPI Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 951 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface (f) Transfer Operation Flowchart Figure 18.21 is a flowchart illustrating a transfer in SPI operation when this module is used in dual-/quad-SPI mode. End of initialization in dual-/ quad-SPI mode Write Read Write/read Transmit buffer has the specified length of data Receive buffer has a space for the specified length of data NO YES NO YES Copy transmit data from transmit buffer to transmit shift register Start serial transfer Start serial transfer QSPCLK cycle count < Shorter than transfer data length = Equal to transfer data length QSPCLK cycle count Copy receive data from receive shift register to receive buffer < Shorter than transfer data length = Equal to transfer data length Assert Assert QSSL signal level QSSL signal level Negate Negate Output the last data or fixed value from the QIO pin according to register setting Drive the QIO pin to Hi-Z state Update command pointer YES Continue serial transfer NO End of transfer Figure 18.21 Transfer Operation Flowchart in Dual-/Quad-SPI Mode Page 952 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 18.4.8 Section 18 Renesas Quad Serial Peripheral Interface Interrupt Sources This module has interrupt sources of receive buffer full and transmit buffer empty. In addition, the direct memory access controller can be activated by the receive buffer full or transmit buffer empty interrupt for data transfer. Table 18.9 shows the interrupt sources. When any of the interrupt conditions in table 18.9 is met, an interrupt is generated. The interrupt sources should be cleared with data transfer by the CPU or direct memory access controller. Table 18.9 Interrupt Sources Name Interrupt Source Abbreviation Interrupt Condition Activation of Direct Memory Access Controller SPRI Receive buffer full RXI (SPRIE = 1)  (SPRFF = 1) Possible SPTI Transmit buffer empty TXI (SPTIE = 1)  (SPTEF = 1) Possible R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 953 of 3092 SH7268 Group, SH7269 Group Section 18 Renesas Quad Serial Peripheral Interface 18.4.9 Loopback Mode This module provides loopback mode for testing. Writing 1 to the loopback mode bit (SPLP) in the pin control register (SPPCR) enables loopback mode. In loopback mode, this module disconnects the paths between the transmit/receive shift registers and the QMI/QMO and QIO3 to QIO0 pins, and connects the outputs from the transmit shift register to the inputs to the receive shift register instead. Figure 18.22 shows a schematic internal connection in loopback mode. Single-SPI output circuit QMO/QIO0 Transmit shift register Dual-SPI output circuit Data pin control circuit Quad-SPI output circuit Single-SPI input circuit Receive shift register QMI/QIO1 QIO2 Dual-SPI input circuit QIO3 Quad-SPI input circuit Normal mode Loopback mode Figure 18.22 Schematic Internal Connection in Loopback Mode Page 954 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Section 19 SPI Multi I/O Bus Controller The SPI multi I/O bus controller outputs control signals to the serial flash memory connected to the SPI multi I/O bus space, thus enabling direct connection of the serial flash memory. 19.1 Features This module allows the connected serial flash memory to be accessed by directly reading the SPI multi I/O bus space, or using SPI mode to transmit and receive data.  Serial Flash Memory Interface Up to two serial flash memories can be connected. A data bus size of 1 bit, 2 bits, or 4 bits can be selected for one serial flash memory device.  External Address Space Read Mode A maximum of 8-Gbyte address space is supported (when two serial flash memories are connected) The SPBSSL pin can be automatically controlled through access address monitoring Efficient data reception due to built-in read cache (64-bit line  16 entries)  SPI Operating Mode Desired read/write access to serial flash memory possible  Bit rate SPBCLK is generated by frequency division of B by internal baud rate generator SPBCLK frequency division ratio can only be set to 2  SPBSSL Pin Control Delay from SPBSSL signal assertion to SPBCLK operation (clock delay) can be set Range: 1 to 8 SPBCLK cycles (set in SPBCLK-cycle units) SPBSSL polarity can be changed R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 955 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.2 Block Diagram Figure 19.1 shows a block diagram of this module. Internal bus Bφ Bus interface Control register Read cache CMNCR SSLDR SPBCR DRCR DRCMR DREAR DROPR DRENR SMCR SMCMR SMADR SMOPR SMENR SMRDR0 SMRDR1 SMWDR0 SMWDR1 CMNSR Transmit data buffer Module data bus Transmit data shift register Receive data shift register Transmission/ reception control Baud rate generator Selector SPBMO_0/SPBIO0_0 SPBMI_0/SPBIO1_0 SPBIO2_0 SPBIO3_0 SPBMO_1/SPBIO0_1 SPBMI_1/SPBIO1_1 SPBIO2_1 SPBIO3_1 SPBSSL SPBCLK Figure 19.1 Block Diagram Page 956 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.3 Section 19 SPI Multi I/O Bus Controller Input/Output Pins Table 19.1 shows the pin configuration. Table 19.1 Pin Configuration Channel Pin Name Symbol I/O Function Common Clock pin SPBCLK Output Clock output Slave select pin SPBSSL Output Slave selection Data 0 pin SPBMO_0/ SPBIO0_0 I/O Master transmit data/data 0 Data 1 pin SPBMI_0/ SPBIO1_0 I/O Master input data/data 1 Data 2 pin SPBIO2_0 I/O Data 2 Data 3 pin SPBIO3_0 I/O Data 3 Data 0 pin SPBMO_1/ SPBIO0_1 I/O Master transmit data/data 0 Data 1 pin SPBMI_1/ SPBIO1_1 I/O Master input data/data 1 Data 2 pin SPBIO2_1 I/O Data 2 Data 3 pin SPBIO3_1 I/O Data 3 0 1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 957 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4 Register Descriptions Table 19.2 shows the register configuration. Table 19.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Common control register CMNCR R/W H'00AA4000 H'FFFC1C00 32 SSL delay register SSLDR R/W H'00000000 H'FFFC1C04 32 Bit rate register SPBCR R/W H'00000003 H'FFFC1C08 32 Data read control register DRCR R/W H'00000000 H'FFFC1C0C 32 Data read command setting register DRCMR R/W H'00000000 H'FFFC1C10 32 Data read extended address setting register DREAR R/W H'00000000 H'FFFC1C14 32 Data read option setting register DROPR R/W H'00000000 H'FFFC1C18 32 Data read enable setting register DRENR R/W H'00004700 H'FFFC1C1C 32 SPI mode control register SMCR R/W H'00000000 H'FFFC1C20 32 SPI mode command setting register SMCMR R/W H'00000000 H'FFFC1C24 32 SPI mode address setting register SMADR R/W H'00000000 H'FFFC1C28 32 SPI mode option setting register SMOPR R/W H'00000000 H'FFFC1C2C 32 SPI mode enable setting register SMENR R/W H'00004000 H'FFFC1C30 32 SPI mode read data register 0 SMRDR0 R Undefined H'FFFC1C38 8, 16, 32 SPI mode read data register 1 SMRDR1 R Undefined H'FFFC1C3C 8, 16, 32 SPI mode write data register 0 SMWDR0 R/W H'00000000 H'FFFC1C40 8, 16, 32 SPI mode write data register 1 SMWDR1 R/W H'00000000 H'FFFC1C44 8, 16, 32 Common status register CMNSR R H'00000001 H'FFFC1C48 32 Page 958 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.4.1 Section 19 SPI Multi I/O Bus Controller Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the SPI multi I/O bus controller. The settings of this register are reflected both in external address space read mode and SPI operating mode. The settings of this register should be changed when the SSLF flag in CMNSR is 0; otherwise, the operation cannot be guaranteed. Bit: 31 MD Initial value: 0 R/W: R/W Bit: 15 30 29 28 27 26 25 24 - - - - - - - MOIIO3[1:0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 14 13 12 11 10 9 8 7 - - IO0FV[1:0] - 0 R 0 R IO3FV[1:0] Initial value: 0 R/W: R/W 1 R/W IO2FV[1:0] 0 R/W 0 R/W 0 R/W 23 0 R/W 0 R 22 21 20 MOIIO2[1:0] 0 R/W 1 R/W 0 R/W 6 5 4 CPHAT CPHAR SSLP 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 MD 0 R/W Operating Mode Switch 0 R/W 19 18 17 MOIIO1[1:0] 16 MOIIO0[1:0] 1 R/W 0 R/W 1 R/W 0 R/W 1 0 3 2 CPOL - 0 R/W 0 R BSZ[1:0] 0 R/W 0 R/W Switches the operating modes. 0: External address space read mode 1: SPI operating mode 30 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23, 22 MOIIO3[1:0] 10 R/W SPBSSL Output Idle Value Fix SPBIO3_0, SPBIO3_1 Fixes output values of SPBIO3_0 and SPBIO3_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 959 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Initial Value Bit Bit Name 21, 20 MOIIO2[1:0] 10 R/W Description R/W SPBSSL Output Idle Value Fix SPBIO2_0, SPBIO2_1 Fixes output values of SPBIO2_0 and SPBIO2_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z 19, 18 MOIIO1[1:0] 10 R/W SPBSSL Output Idle Value Fix SPBIO1_0, SPBIO1_1 Fixes output values of SPBIO1_0 and SPBIO1_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z 17, 16 MOIIO0[1:0] 10 R/W SPBSSL Output Idle Value Fix SPBIO0_0, SPBIO0_1 Fixes output values of SPBIO0_0 and SPBIO0_1 in SPBSSL negation period. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z Page 960 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 15, 14 IO3FV[1:0] 01 R/W SPBIO3_0, SPBIO3_1 Fixed Value for 1-bit/2-bit Size Fixes the output value of SPBIO3_0 and SPBIO3_1 pins for 1-bit/2-bit size. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z 13, 12 IO2FV[1:0] 00 R/W SPBIO2_0, SPBIO2_1 Fixed Value for 1-bit/2-bit Size Fixes the output value of SPBIO2_0 and SPBIO2_1 pins for 1-bit/2-bit size. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 IO0FV[1:0] 00 R/W SPBIO0_0, SPBIO0_1 Fixed Value for 1-bit Size Input Fixes the output value of SPBIO0_0 and SPBIO0_1 pins for 1-bit size input. 00: Output value 0 01: Output value 1 10: Output value is the value of the immediately previous bit (or the pin is Hi-Z, if Hi-Z was the state in the immediately previous bit period). 11: Output value Hi-Z 7  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 961 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 6 CPHAT 0 R/W Output Shift Sets the SPBCLK edge of the output data. CPHAT and CPHAR should be set according to the description of CPHAR. 0: Data transmission at even edge 1: Data transmission at odd edge 5 CPHAR 0 R/W Input Latch Sets the SPBCLK edge of the reception data. CPHAT and CPHAR should be set according to the following table. 0: Data reception at odd edge 1: Data reception at even edge CPHAT and CPHAR Setting 4 SSLP 0 R/W CPHAT COHAR 0 0 Setting enabled 0 1 Setting enabled 1 0 Setting prohibited 1 1 Setting enabled SPBSSL Signal Polarity Sets the polarity of SPBSSL signal. 0: Active low SPBSSL signal 1: Active high SPBSSL signal 3 CPOL 0 R/W SPBSSL Negation Period SPBCLK Output Direction Sets the SPBCLK output direction during SPBSSL negation period. 0: SPBCLK output is 0 during SPBSSL negation period. 1: SPBCLK output is 1 during SPBSSL negation period. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 962 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 1, 0 BSZ[1:0] 00 R/W Data Bus Size Specifies the number of serial flash memories to be connected. 00: 1 memory 01: 2 memories 1X: Setting prohibited Note: After changing (the value of) this bit, all the entries in the read cache must be cleared by setting the RCF bit in DRCR to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 963 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.2 SSL Delay Register (SSLDR) SSLDR is a 32-bit register that adjusts the timing between the SPBSSL signal and the SPBCLK signal. The settings of this register are reflected both in external address space read mode and SPI operating mode. The settings of this register should be changed when the SSLF flag in CMNSR is 0; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 10 9 8 7 6 5 4 3 2 - - - - - 0 R 0 R 0 R 0 R 0 R - 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R SLNDL[2:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 19  All 0 R Reserved 18 17 16 SPNDL[2:0] 0 R/W 0 R/W 1 0 SCKDL[2:0] 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 18 to 16 SPNDL[2:0] 000 R/W Next Access Delay Sets the period from transfer end to next transfer start (next access). 000: 1 SPBCLK cycle Other than above: Setting prohibited 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 SLNDL[2:0] 000 R/W SPBSSL Negation Delay Sets the period from the time the last SPBCLK edge is sent of a transfer to SPBSSL pin negation (SPBSSL negation delay). 000: 1.5 SPBCLK cycles Other than above: Setting prohibited Page 964 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 SCKDL[2:0] 000 R/W Clock Delay Sets the period from SPBSSL pin assertion to SPBCLK oscillation (clock delay). 000: 1 SPBCLK cycle 001: 2 SPBCLK cycles 010: 3 SPBCLK cycles 011: 4 SPBCLK cycles 100: 5 SPBCLK cycles 101: 6 SPBCLK cycles 110: 7 SPBCLK cycles 111: 8 SPBCLK cycles R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 965 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.3 Bit Rate Register (SPBCR) SPBCR is a 32-bit register that sets the bit rate. The settings of this register are reflected both in external address space read mode and SPI operating mode. The settings of this register should be changed when the SSLF flag in CMNSR is 0; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - BRDV[1:0] 0 R 0 R 0 R 0 R 0 R 0 R - SPBR[7:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W Initial Value R/W Description 31 to 16  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 to 8 SPBR[7:0] All 0 R/W Bit Rate Sets the bit rate. The bit rate is determined by a combination of these bits with the BRDV[1:0] bits. For details, see table 19.3, Relationship between SPBR[7:0] and BRDV[1:0] Settings. 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BRDV[1:0] 11 R/W Bit Rate Frequency Division Sets the bit rate. The bit rate is determined by a combination of these bits with the SPBR[7:0] bits. The SPBR value is used to set the base bit rate. The BRDV value is used to select a division ratio of the base bit rate from among no division and 2. 00: Base bit rate 01: Base bit rate divided by 2 Other than above: Setting prohibited Bit Bit Name Page 966 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 19 SPI Multi I/O Bus Controller Bit Rate SPBR[7:0] and BRDV[1:0] are used for setting the bit rate. Setting the division ratio to 2 is only enabled. Table 19.3 Relationship between SPBR[7:0] and BRDV[1:0] Settings Bit Rate SPBR[7:0] BRDV[1:0] Division Ratio B = 66.67 MHz B = 133.33 MHz 0 1 2 33.33 Mbps 66.66 Mbps 1 0 2 33.33 Mbps 66.66 Mbps R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 967 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.4 Data Read Control Register (DRCR) DRCR is a 32-bit register that sets the operation in external address space read mode. The bits should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit: 15 - 19 18 17 16 RBURST[3:0] 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - RCF RBE - - - - - - - SSLE Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 31 to 20  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 19 to 16 RBURST [3:0] 0000 R/W Read Data Burst Length Sets the burst length (data unit count) when reading. This bit is enabled when the RBE bit is set to 1. 0000: 1 data unit 0001: 2 continuous data units : 1110: 15 continuous data units 1111: 16 continuous data units One data unit is 64 bits long. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 968 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 9 RCF 0 W Read Cache Flush When 1 is written to this bit, all the entries in the read cache are cleared. This bit is always read as 0. Note: After writing 1 to the RCF bit to clear the read cache, perform the external address space read after reading the contents of the DRCR register. 8 RBE 0 R/W Read Burst Turns burst ON or OFF when reading. 0: Data is read according to the access size. 1: Read cache is enabled, and as many data units as the burst count specified in RBURST[3:0] bits is read. 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 SSLE 0 R/W SPBSSL Negation Sets the conditions for SPBSSL negation during read burst. SPBSSL is negated for each access during normal read. 0: SPBSSL is negated after transfer of data set in burst length. 1: SPBSSL is negated when the accessed address is not continuous with the previously transferred address. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 969 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.5 Data Read Command Setting Register (DRCMR) DRCMR is a 32-bit register that sets the commands issued in external address space read mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit: 15 7 6 5 - 14 13 12 11 10 9 8 - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 23 22 21 20 19 18 17 16 CMD[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 4 3 2 1 0 0 R/W 0 R/W 0 R/W OCMD[7:0] 0 R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 23 to 16 CMD[7:0] H'00 R/W Command Sets the command. 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 OCMD[7:0] H'00 R/W Optional Command Sets the optional command. Page 970 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.4.6 Section 19 SPI Multi I/O Bus Controller Data Read Extended Address Setting Register (DREAR) DREAR is a 32-bit register that sets the address when the serial flash address is output in 32-bit mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 - 23 22 21 20 19 18 17 16 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0 EAV[7:0] 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved EAC[2:0] 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 971 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 23 to 16 EAV[7:0] H'00 R/W 32-Bit Extended Upper Address Fixed Value Sets the upper address bit values of the external address specified by the EAC[2:0] bits when the serial flash address is output in 32-bit mode. Bit 0 corresponds to the serial flash address bit [25], and bit 7 corresponds to the bit [32]. This setting is valid when the ADE[3] bit in DRENR is 1. When EAC[2:0] are 000, serial flash address [32:25] fixed values should be set to EAV[7:0]. When EAC[2:0] are 001, serial flash address [32:26] fixed values should set to EAV[7:1]. (1) When BSZ[1:0] in CMNCR = 00 (one serial flash memory connected) Serial flash addresses [31:0] are used for accessing. (2) When BSZ[1:0] in CMNCR = 01 (two serial flash memories connected) Serial flash addresses [32:1] are used for accessing. 15 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 EAC[2:0] 000 R/W 32-Bit Extended External Address Valid Range Sets the range of the external address to be used as serial flash address when the serial flash address is output in 32-bit mode. This setting is valid when the ADE[3] bit in DRENR is 1. 000: External address bits [24:0] enabled 001: External address bits [25:0] enabled Other than above: Setting prohibited Page 972 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.4.7 Section 19 SPI Multi I/O Bus Controller Data Read Option Setting Register (DROPR) DROPR is a 32-bit register that sets the option data in external address space read mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 OPD3[7:0] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 0 R/W 0 R/W 0 R/W 0 R/W 19 18 17 16 OPD2[7:0] OPD1[7:0] Initial value: 0 R/W: R/W 20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 4 3 2 1 0 0 R/W 0 R/W 0 R/W OPD0[7:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 24 OPD3[7:0] H'00 R/W Option Data 3 23 to 16 OPD2[7:0] H'00 R/W Option Data 2 0 R/W 0 R/W 0 R/W 0 R/W Sets the option data 3. Sets the option data 2. 15 to 8 OPD1[7:0] H'00 R/W Option Data 1 Sets the option data 1. 7 to 0 OPD0[7:0] H'00 R/W Option Data 0 Sets the option data 0. Note: OPD3, OPD2, OPD1, and OPD0 are output in this order. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 973 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.8 Data Read Enable Setting Register (DRENR) DRENR is a 32-bit register that sets the bit size of the command, optional command, address, option data, and read data in external address space read mode and enables the output of all except the read data. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 CDB[1:0] Initial value: 0 R/W: R/W Bit: 15 28 27 26 - - 0 R/W 0 R 0 R 0 R/W 11 10 9 OCDB[1:0] 0 R/W 0 R/W 14 13 12 - CDE - OCDE Initial value: 0 R/W: R 1 R/W 0 R 0 R/W 25 24 23 22 - - 0 R/W 0 R 0 R 0 R/W 8 7 6 5 ADB[1:0] 1 R/W Bit Bit Name Initial Value R/W 31, 30 CDB[1:0] 00 R/W 20 19 18 - - 0 R/W 0 R 0 R 0 R/W 0 R/W 4 3 2 1 0 - - - - 0 R 0 R 0 R 0 R OPDB[1:0] OPDE[3:0] ADE[3:0] 0 R/W 21 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17 16 DRDB[1:0] Description Command Bit Size Sets the command size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 29, 28 OCDB[1:0] 00 R/W Optional Command Bit Size Sets the optional command size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 27, 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 974 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 25, 24 ADB[1:0] 00 R/W Address Bit Size Sets the address size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 23, 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 OPDB[1:0] 00 R/W Option Data Bit Size Sets the option data size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 DRDB[1:0] 00 R/W Data Read Bit Size Sets the data read size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 CDE 1 R/W Command Enable Sets the command to be output. 0: Command output disabled 1: Command output enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 975 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 OCDE 0 R/W Optional Command Enable Sets the optional command to be output. 0: Optional command output disabled 1: Optional command output enabled 11 to 8 ADE[3:0] 0111 R/W Address Enable Sets the address to be output. Be sure to use the following setting; otherwise, the operation is not guaranteed. (1) BSZ[1:0] in CMNCR = 00 (one serial flash memory connected) 0000: Output disabled 0111: Address[23:0] 1111: Address[31:0] Other than above: Setting prohibited (2) BSZ[1:0] in CMNCR = 01 (two serial flash memories connected) 0000: Output disabled 0111: Address[24:1] 1111: Address[32:1] Other than above: Setting prohibited 7 to 4 OPDE[3:0] 0000 R/W Option Data Enable Sets the option data to be output. Use only the settings given below. Otherwise, the operation cannot be guaranteed. 0000: Output disabled 1000: OPD3 1100: OPD3, OPD2 1110: OPD3, OPD2, OPD1 1111: OPD3, OPD2, OPD1, OPD0 Other than above: Setting prohibited 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 976 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.4.9 Section 19 SPI Multi I/O Bus Controller SPI Mode Control Register (SMCR) SMCR is a 32-bit register that sets the operation in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 2 1 - 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - SSLKP - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 9  All 0 R Reserved SPIRE SPIWE 0 R/W 0 R/W 0 SPIE 0 W These bits are always read as 0. The write value should always be 0. 8 SSLKP 0 R/W SPBSSL Signal Level Determines the SPBSSL status after the end of transfer. 0: SPBSSL signal is negated at the end of transfer. 1: SPBSSL signal level is maintained from the end of transfer to the start of next access. Note: When the transfer data bit size is set to 2 bits or 4 bits with the SPIDB[1:0] bits, the SPIRE and SSLKP bits should not be set to 1 at the same time. 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 977 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 2 SPIRE 0 R/W Data Read Enable Enables reading in SPI operating mode. 0: Data reading disabled 1: Data reading enabled Note: When the transfer data bit size is set to 2 bits or 4 bits with the SPIDB[1:0] bits, the SPIRE and SPIWE bits should not be set to 1 at the same time. 1 SPIWE 0 R/W Data Write Enable Enables writing in SPI operating mode. 0: Data writing disabled 1: Data writing enabled Note: When the transfer data bit size is set to 2 bits or 4 bits with the SPIDB[1:0] bits, the SPIRE and SPIWE bits should not be set to 1 at the same time. 0 SPIE 0 W SPI Data Transfer Enable Data is transferred by setting this bit to 1. This bit is enabled only when the TEND bit in CMNSR is set to 1. The operation cannot be guaranteed when this bit is set to 1 with the TEND bit set to 0. If this bit is set to 1 at the t3 period, data transfer is started after the end of the t3 period. This bit is always read as 0. Note: When SPBSSL is negated, the command, optional command, address, and option data that are output enabled are output even if the SPIRE and SPIWE bits are cleared to 0. When SPBSSL is asserted, follow 19.6.1 Note on Transfer Start from SPBSSL Hold State in SPI Operation Mode Page 978 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.10 SPI Mode Command Setting Register (SMCMR) SMCMR is a 32-bit register that sets the commands issued in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit: 15 7 6 5 - 14 13 12 11 10 9 8 - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 23 22 21 20 19 18 17 16 CMD[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 4 3 2 1 0 0 R/W 0 R/W 0 R/W OCMD[7:0] 0 R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 23 to 16 CMD[7:0] H'00 R/W Command Sets the command. 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 OCMD[7:0] H'00 R/W Optional Command Sets the optional command. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 979 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.11 SPI Mode Address Setting Register (SMADR) SMADR is a 32-bit register that sets the addresses in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 ADR[31:24] Initial value: 0 R/W: R/W Bit: 15 20 19 18 17 16 ADR[23:16] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ADR[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 24 ADR[31:24] H'00 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W Address Sets the value of bits 31 to 24 when the serial flash address is output in 32-bit units. This setting is valid when ADE[3] in SMENR is 1. 23 to 0 ADR[23:0] H'000000 R/W Address Sets the address. Page 980 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.12 SPI Mode Option Setting Register (SMOPR) SMOPR is a 32-bit register that sets the option data in SPI operating mode. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 OPD3[7:0] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 0 R/W 0 R/W 0 R/W 0 R/W 19 18 17 16 OPD2[7:0] OPD1[7:0] Initial value: 0 R/W: R/W 20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 4 3 2 1 0 0 R/W 0 R/W 0 R/W OPD0[7:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 24 OPD3[7:0] H'00 R/W Option Data 3 23 to 16 OPD2[7:0] H'00 R/W Option Data 2 0 R/W 0 R/W 0 R/W 0 R/W Sets the option data 3. Sets the option data 2. 15 to 8 OPD1[7:0] H'00 R/W Option Data 1 Sets the option data 1. 7 to 0 OPD0[7:0] H'00 R/W Option Data 0 Sets the option data 0. Note: OPD3, OPD2, OPD1, and OPD0 are output in this order. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 981 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.13 SPI Mode Enable Setting Register (SMENR) SMENR is a 32-bit register that sets the bit size of the command, optional command, address, option data, and transfer data in SPI operating mode and enables their output. Disabling all of the command, optional command, address, option data, and transfer data is prohibited. At least one of them must be enabled. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 CDB[1:0] Initial value: 0 R/W: R/W Bit: 15 28 27 26 - - 0 R/W 0 R 0 R 0 R/W 11 10 9 OCDB[1:0] 0 R/W 0 R/W 14 13 12 - CDE - OCDE Initial value: 0 R/W: R 1 R/W 0 R 0 R/W 25 24 23 22 - - 0 R/W 0 R 0 R 0 R/W 8 7 6 5 ADB[1:0] ADE[3:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W 31, 30 CDB[1:0] 00 R/W 21 20 19 18 - - 0 R/W 0 R 0 R 0 R/W 0 R/W 4 3 2 1 0 OPDB[1:0] OPDE[3:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17 16 SPIDB[1:0] SPIDE[3:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description Command Bit Size Sets the command size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 29, 28 OCDB[1:0] 00 R/W Optional Command Bit Size Sets the optional command size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 27, 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 982 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 25, 24 ADB[1:0] 00 R/W Address Bit Size Sets the address size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 23, 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 OPDB[1:0] 00 R/W Option Data Bit Size Sets the option data size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 SPIDB[1:0] 00 R/W Transfer Data Bit Size Sets the transfer data size in bit units. 00: 1 bit 01: 2 bits 10: 4 bits 11: Setting prohibited 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 CDE 1 R/W Command Enable Sets the command to be output. 0: Command output disabled 1: Command output enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 983 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 OCDE 0 R/W Optional Command Enable Sets the optional command to be output. 0: Optional command output disabled 1: Optional command output enabled 11 to 8 ADE[3:0] 0000 R/W Address Enable Sets the address to be output. Use only the settings given below. Otherwise, the operation cannot be guaranteed. 0000: Output disabled 0100: ADR[23:16] 0110: ADR[23:8] 0111: ADR[23:0] 1111: ADR[31:0] Other than above: Setting prohibited 7 to 4 OPDE[3:0] 0000 R/W Option Data Enable Sets the option data to be output. Use only the settings given below. Otherwise, the operation cannot be guaranteed. 0000: Output disabled 1000: OPD3 1100: OPD3, OPD2 1110: OPD3, OPD2, OPD1 1111: OPD3, OPD2, OPD1, OPD0 Other than above: Setting prohibited Page 984 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Bit Bit Name Initial Value R/W Description 3 to 0 SPIDE[3:0] 0000 R/W Transfer Data Enable Sets valid transfer data. Valid data differs depending on the BSZ[1:0] bit setting in CMNCR. The following settings must be used. Otherwise, the operation is not guaranteed. (1) BSZ[1:0] bits in CMNCR = 00 (one serial flash memory connected) 0000: Not transferred 1000: 8 bits transferred (enables DATA[31:24]) 1100: 16 bits transferred (enables DATA[31:16]) 1111: 32 bits transferred (enables DATA[31:0]) Other than above: Setting prohibited (2) BSZ[1:0] bits in CMNCR = 01 (two serial flash memories connected) 0000: Not transferred 1000: 16 bits transferred (enables DATA[63:48]) 1100: 32 bits transferred (enables DATA[63:32]) 1111: 64 bits transferred (enables DATA[63:0]) Other than above: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 985 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.14 SPI Mode Read Data Register 0 (SMRDR0) SMRDR0 is a 32-bit register that stores the read data in SPI operating mode. Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. The settings of this register should be read when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA0[31:16] Initial value: UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA0[15:0] Initial value: UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined R/W: R R R R R R R R R R R R R R R R Bit Bit Name 31 to 0 RDATA0 [31:0] Initial Value R/W Undefined R Description Read Data Holds the data read in SPI operating mode. Data bits differ depending on the BSZ[1:0] bit setting in CMNCR. BSZ[1:0] = 00: Read data[31:0]. BSZ[1:0] = 01: Read data[63:32]. Note: The contents of this register and SMRDR1 are modified upon completion of reception in SPI operating mode. Be sure to read data when reception in SPI operating mode is completed. Page 986 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.15 SPI Mode Read Data Register 1 (SMRDR1) SMRDR1 is a 32-bit register that stores the read data in SPI operating mode. This register is enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected). Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. The settings of this register should be read when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDATA1[31:16] Initial value: UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDATA1[15:0] Initial value: UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined R/W: R R R R R R R R R R R R R R R R Bit Bit Name 31 to 0 RDATA1 [31:0] Initial Value R/W Undefined R Description Read Data Holds the data read in SPI operating mode. Enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected). BSZ[1:0] = 01: Read data[31:0]. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 987 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.16 SPI Mode Write Data Register 0 (SMWDR0) SMWDR0 is a 32-bit register that sets the write data in SPI operating mode. Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDATA0[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W WDATA0[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W Bit Bit Name 31 to 0 WDATA0 [31:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Write Data Holds the data written in SPI operating mode. Data bits differ depending on the BSZ[1:0] bit setting in CMNCR. BSZ[1:0] = 00: Write data[31:0]. BSZ[1:0] = 01: Write data[63:32]. Page 988 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.17 SPI Mode Write Data Register 1 (SMWDR1) SMWDR1 is a 32-bit register that sets the write data in SPI operating mode. This register is enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected). Access to this register should be performed in the same size as the transfer size specified in the SPIDE[3:0] bits in the SPI mode enable setting register (SMENR). Be sure to access from address 0. The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be guaranteed. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDATA1[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W WDATA1[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W Bit Bit Name 31 to 0 WDATA1 [31:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Write Data Holds the data written in SPI operating mode. Enabled when the BSZ[1:0] bits in CMNCR are set to 01 (two serial flash memories connected) and disabled when the BSZ[1:0] bits in CMNCR are set to 00 (one serial flash memory connected). BSZ[1:0] = 01: Write data[31:0]. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 989 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.4.18 Common Status Register (CMNSR) CMNSR is a 32-bit register that holds flags indicating the operating state. The settings of this register are reflected both in external address space read mode and SPI operating mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - SSLF TEND Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R Bit Bit Name Initial Value R/W Description 31 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 SSLF 0 R SPBSSL Pin Monitor 0: SPBSSL pin is negated 1: SPBSSL pin is asserted 0 TEND 1 R Transfer End Flag Indicates whether the data transfer has ended. 0: Indicates that data transfer is in progress 1: Indicates that data transfer has ended Page 990 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.5 Operation 19.5.1 System Configuration Section 19 SPI Multi I/O Bus Controller With this module, one or two serial flash memories can be directly connected (data size of 1, 2, and 4 bits). The number of connected memories can be selected using the BSZ[1:0] bits in CMNCR. Examples of system configuration with one serial flash memory connected and two serial flash memories connected are shown in figures 19.2 and 19.3, respectively. This LSI SPBSSL SPBCLK SPBMO_0/SPBIO0_0 SPBMI_0/SPBIO1_0 SPBIO2_0 SPBIO3_0 Serial flash memory CS# SCK SI/IO0 SO/IO1 W#/IO2 HOLD#/IO3 Figure 19.2 System Configuration Example with 4-Bit Data Size and One Serial Flash Memory Connected (BSZ[1:0] Bits in CMNCR = 00) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 991 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller This LSI Serial flash memory SPBSSL SPBCLK SPBMO_0/SPBIO0_0 SPBMI_0/SPBIO1_0 SPBIO2_0 SPBIO3_0 CS# SCK SI/IO0 SO/IO1 W#/IO2 HOLD#/IO3 Serial flash memory CS# SCK SI/IO0 SO/IO1 W#/IO2 HOLD#/IO3 SPBMO_1/SPBIO0_1 SPBMI_1/SPBIO1_1 SPBIO2_1 SPBIO3_1 Figure 19.3 System Configuration Example with 4-Bit Data Size and Two Serial Flash Memories Connected (BSZ[1:0] Bits in CMNCR = 01) 19.5.2 Address Map In external address space read mode, the serial flash connected is assigned in the SPI multi I/O bus space. A maximum accessible address space differs depending on the number of serial flash memories connected. In combination with DREAR, a maximum of 4 Gbytes can be accessed when one serial flash memory is connected, and a maximum of 8 Gbytes can be accessed when two memories are connected. Table 19.4 Address Map Number of Serial Flash Memories Connected Internal Address Cache Max. Access Area 1 H'18000000 to H'1BFFFFFF Enabled 4 Gbytes H'38000000 to H'3BFFFFFF Disabled H'18000000 to H'1BFFFFFF Enabled H'38000000 to H'3BFFFFFF Disabled 2 Page 992 of 3092 8 Gbytes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.5.3 Section 19 SPI Multi I/O Bus Controller 32-bit Serial Flash Addresses Since the SPI multi I/O bus space is 64 Mbytes, only a part of the 32-bit serial flash address area can be directly accessed. Here, the fixed value set in the pertinent register is used as the upper bit value of a 32-bit address. To output serial flash addresses in 32 bits, set the ADE[3] bit in DRENR to 1, set the range of the external addresses used as the serial flash addresses to the EAC[2:0] bits in DREAR, and set the upper bit value of the 32-bit address as the fixed value to the EAV[7:0] bits in DREAR. When EAC[2:0] = 000 EAV [7:0] bits External address bits [24:0] 7 0 Serial flash address 32 0 25 24 When EAC[2:0] = 001 EAV [7:0] bits External address bits [25:0] 7 0 Serial flash address 32 26 25 0 Figure 19.4 32-Bit Address Setting Setting the ADE[3] bit in DRENR to 1 allows the serial flash address to be output using [31:0] bits. When EAC[2:0] = 000, external address bits [24:0] are valid; set the value for [32:25] bits to EAV[7:0]. When EAC[2:0] = 001, external address bits [25:0] are valid; set the value for [32:26] bits to EAV[7:1]. The address bits actually used for access depend on the number of serial flash memories connected. When one serial flash memory is connected, address bits [31:0] are used and when two memories are connected, address bits [32:1] are used. Note: When the capacity of the serial flash memory used is smaller than 4 Gbytes, keep the following point in mind. If an access spreads over the last address of the serial flash in burst mode (RBE bit in DRECR = 1), the access address does not agree with the internal address of the serial flash. To prevent this, software should appropriately manage the accessible address areas for the serial flash memory used according to the memory capacity. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 993 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.5.4 Data Alignment When two serial flash memories are connected, the serial flash memory connected to the pin SPBIO3_0-SPBIO0_0 has the address 2n and the serial flash memory connected to the pin SPBIO3_1-SPBIO0_1 has the address 2n + 1. The data should be accessed in word or larger units. It cannot be accessed in byte units. Data alignment when two serial flash memories are connected is shown in table 19.5. Table 19.5 Data Alignment when Two Serial Flash Memories are Connected Serial Flash Memory Operation SPBIO3_0 to SPBIO0_0 Pins SPBIO3_1 to SPBIO0_1 Pins Word access to address 0 Data 15 to 8 Data 7 to 0 Word access to address 2 Data 15 to 8 Data 7 to 0 Longword access to address 0 1 word (address 0) Data 31 to 24 Data 23 to 16 2 words (address 2) Data 15 to 8 Data 7 to 0 1 word (address 0) Data 63 to 56 Data 55 to 48 Double-longword access to address 0 Page 994 of 3092 2 words (address 2) Data 47 to 40 Data 39 to 32 3 words (address 4) Data 31 to 24 Data 23 to 16 4 words (address 6) Data 15 to 8 Data 7 to 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 19.5.5 Section 19 SPI Multi I/O Bus Controller Operating Modes This module has two operating modes: external address space read mode and SPI operating mode. In external address space read mode, a read access to the SPI multi I/O bus space is converted into SPI communication and data is received. After data acquisition, data is returned to the bus master that is the issuing source. For details, see section 19.5.6, External Address Space Read Mode. In SPI operating mode, arbitrary SPI communication is carried out using register settings. For details, see section 19.5.8, SPI Operating Mode. 19.5.6 External Address Space Read Mode A read access to the SPI multi I/O bus space can be converted into SPI communication in external address space read mode. Further, the commands, optional commands, and option data issued for reading can be modified using registers. In external address space read mode, either normal read operation or burst read operation can be selected. The transfer format is determined based on the common control register (CMNCR), SSL delay register (SSLDR), bit rate setting register (SPBCR), data read control register (DRCR), data read command setting register (DRCMR), data read extended address setting register (DREAR), data read option setting register (DROPR), and data read enable setting register (DRENR). (1) Normal Read Operation When the RBE bit in DRCR is set to 0, normal read operation is performed. In the normal read operation, the data of 8 bits, 16 bits, 32 bits, and 64 bits are read for respectively a byte, a word, and a longword, and a double-longword read access. Here, a byte access is enabled only when one serial flash memory is connected. After reading, the SPBSSL pin is negated. The normal read operation timing is shown in figure 19.5. t1 is the time period from SPBSSL pin assertion to SPBCLK oscillation (clock delay), t2 is the time period from transmission of the last SPBCLK edge of a transfer to SPBSSL pin negation (SPBSSL negation delay), and t3 is the time period from one transfer end to the next transfer start (next access). For details of t1, t2, and t3, see section 19.5.9, Transfer Format. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 995 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller SPI multi I/O bus space access t1 t2 t3 SPBSSL SPBCLK SPBMO_0 Command SPBMI_0 Address Read data 8/16/32/64 bits Flags SSLF bit TE ND bit Figure 19.5 Normal Read Operation Timing (2) Burst Read Operation When the RBE bit in DRCR is set to 1, burst read operation is performed. Read cache is enabled in the burst read operation. For read cache operation, see section 19.5.7, Read Cache. For reading bytes, words, longwords or double-longwords, the read cache is first referred to for the data. When the read cache contains the data, the data is read from the read cache without accessing the serial flash memory. When the read cache does not contain the data, burst read operation is performed in the serial flash memory and the read data is stored in the read cache. The data transfer length at that time is 64 bits  RBURST[3:0] bits and the data is always read from the 64-bit boundary. The SPBSSL pin status after data transfer can be selected by using the SSLE bit in DRCR. When the SSLE bit is set to 0, the SPBSSL pin is negated after data transfer. For an operation performed when the SSLE bit is set to 1, see (3) Burst Read Operation with Automatic SPBSSL Negation, just below. A pattern diagram of this operation and a burst read operation timing diagram when SSLE bit is set to 0 are shown in figures 19.6 and 19.7. Page 996 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller This LSI Internal bus This module Serial flash memory Read cache (1) (2) (a) (2) (b) (2) (c) (1) When the read cache contains the data The data is read from the read cache without performing SPI communication. (2) When the read cache does not contain the data (a) The read cache is accessed to confirm that the data is not in the read cache. (b) The data is read from the serial flash memory and the read data is stored in the read cache. (c) The data is read from the read cache. Figure 19.6 Burst Read Operation SPI multi I/O bus space access t1 t2 t3 SPBSSL SPBCLK SPBMO_0 Comma nd Address Read data SPBMI_0 Read data 64 bits 64 bits 64 × RBU RST (read burst len gth) bits Flags SSLF bit TEND bit Figure 19.7 Burst Read Operation Timing (SSLE Bit = 0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 997 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller (3) Burst Read Operation with Automatic SPBSSL Negation When SSLE bit in DRCR is set to 1, this module does not negate the SPBSSL pin after the burst read transfer. When accessing the next time, if the address is continuous with the previous read address, the burst read operation is performed without issuing the command, optional command, address, or option data. If the address is not continuous with the previous read address, the SPBSSL pin is once negated and the burst read operation is performed after issuing the command, optional command, address, or option data. Burst read timing diagrams for continuous address and non-continuous address are shown in figures 19.8 and 19.9. SPI multi I/O bus space access t1 t2 Wait for data read t1 t2 SPBSSL SPBCLK SPBMO_0 Command SPBMI_0 Address Read data Read data 64 × RBURST bits 64 × RBURST bits Flags SSLF bit TEND bit Figure 19.8 Burst Read Timing for Continuous Address (SSLE Bit = 1) SPI multi I/O bus space access SPI multi I/O bus space access t1 t2 SPBSSL Wait for data read t3 t2 t1 SPBCLK SPBMO_0 Command SPBMI_0 Address Command Address Read data Read data 64 × RBURST bits 64 × RBURST bit Flags SSLF bit TEND bit Figure 19.9 Burst Read Timing for Non-Continuous Address (SSLE Bit = 1) For negation of SPBSSL to complete the data transfer with this operation, follow the procedures shown below. 1. Clear the SSLE bit in DRCR to 0. 2. Flush the read cache. 3. Execute a (dummy) read access. Page 998 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 19 SPI Multi I/O Bus Controller Initial Setting Flow An example of an initial setting flow in external address space read mode is shown in figure 19.10. External address space read mode Initial setting start Set CMNCR. • Set external address space read mode. • Set the fixed value of the pins during SPBSSL output idle and that for 1-bit/2-bit size. • Set the SPBCLK edges for output shift and input latch. • Set the SPBSSL signal polarity. • Set the SPBCLK output direction during SPBSSL negation. • Set the number of serial flash memories connected. Set SSLDR. • Set the various delay timing. Set SPBCR. • Set the transfer bit rate. Set DRCR. • Set the normal read or burst read operation. • Set the SPBSSL negation during burst read operation. • Set the burst length during burst read operation. Set DRCMR. • Set the command/optional command when reading. Set DREAR. • Set the address when the serial flash address is output in 32-bit units. (only when DRENR.ADE[3] = 1) Set DROPR. • Set the option data when reading. Set DRENR. • Enable the transfer data. • Set the transfer data size in bit units. External address space read mode Initial setting end Figure 19.10 Example of Initial Setting Flow in External Address Space Read Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 999 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.5.7 Read Cache This module has a simple built-in read cache. The read cache can be used during external address space read mode and burst read operation. The read cache is configured with a line size of 64 bits and 16 entries. Read cache configuration is shown in figure 19.11. Address array Entry 0 V Tag address Data array Byte Byte Byte Entry 1 Entry 15 31 (1 + 30) bits 64 bits Figure 19.11 Read Cache Configuration (1) Address Array The V bit indicates whether the entry data is valid. When the V bit is 1, the data is valid and when V bit is 0, the data is invalid. The tag address bits hold the address used for the serial flash memory. Address bits 32 to 3 are used for the purpose. Address bits 23 to 3 are enabled when address output is 24 bits and one serial flash memory is connected; and address bits 24 to 3 are enabled when two serial flash memories are connected. Address bits 31 to 3 are enabled when address output is 32 bits and one serial flash memory is connected; and address bits 32 to 3 are enabled when two serial flash memories are connected. (2) Data Array It retains the 64-bit read data. Registration in the read cache is performed in line units. Page 1000 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 19 SPI Multi I/O Bus Controller Read Operation In case of read-hit, data is read from the read cache. In case of read-miss, after the 64 × RBURST (read burst length) data is read from the serial flash memory and the read cache is updated, the data is returned to the bus master. (4) Data Replacement The write pointer is used to update data. In case of read-miss, the RBURST (read burst length) portion data is replaced starting at the entry specified by the write pointer. In other words, the data is replaced in the storage order of the data. Whether data is referred to or not will not affect the replacement order of data. 19.5.8 SPI Operating Mode This module can carry out an arbitrary SPI operation by using the register settings. The transfer format is determined based on the common control register (CMNCR), SSL delay register (SSLDR), bit rate setting register (SPBCR), SPI mode control register (SMCR), SPI mode command setting register (SMCMR), SPI mode address setting register (SMADR), SPI mode option setting register (SMOPR), and SPI mode enable setting register (SMENR), SPI mode read data register (SMRDR), and SPI mode write data register (SMWDR). This mode can be used for reading the status of the serial flash memory and writing to the serial flash memory. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1001 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller (1) Transfer Start The transfer of data is started in the set transfer format by setting the SPIE bit in SMCR to 1. When write operation is enabled, the SPI mode write data register is transmitted to the serial flash memory. When read operation is enabled, data read from the serial flash memory is stored into the SPI mode read data register. The SPI operation timing is shown in figure 19.12. SPIE=“1” SPIE=“1” t1 t2 t3 t2 t3 t1 SPBSSL SPBCLK SPBMO_0 Command Address SPBMI_0 Write data (SMWDR) Command Address Read data (SMRDR) Write data (SMWDR) Read data (SMRDR) Flags SSLF bit TEND bit Figure 19.12 SPI Operation Timing (2) Read/Write Enable  Read operation: Data can be read by setting the SPIRE bit in SMCR to 1. The read data is stored into SMRDR.  Write operation: Data can be written by setting the SPIWE bit in SMCR to 1. The data stored in SMWDR is output. When the data size is set to 1 bit using the SPIDB[1:0] bits in SMENR, data can be transmitted and received by setting the SPIRE and SPIWE bits to 1. However, when the data size is set to 2 or 4 bits by using the SPIDB[1:0] bits, only one of the SPIRE and SPIWE bits should be enabled. The operation is not guaranteed if both the bits are enabled. Page 1002 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 19 SPI Multi I/O Bus Controller Retention of SPBSSL Pin Assertion By setting the SSLKP bit in SMCR to 1, assertion of the SPBSSL pin can be continued till the next transfer. With this function, the transfer can be carried out continuously with the SPBSSL kept in the asserted state. Note: When the transfer data size is set to 2 or 4 bits in SPI mode, this function is not available. The data transfer timing using the SSLKP bit is shown in figure 19.13. SPIE= “1” SSLKP=“1” SPBSSL kept asserted t2 t3 t1 SPBSSL SPIE= “1” SSLKP=“0” SPBSSL is negated t1 t2 t3 SPBSSL signal level kept SPBCLK SPBMO_0 Command Address SPBMI_0 Write data (SMWDR) Read data (SMRDR) Command Address Write data (SMWDR) Read data (SMRDR) Setting SSLKP bit Flags SSLF bit TEND bit Figure 19.13 Data Transfer Timing using the SSLKP Bit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1003 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller (4) Initial Setting Flow An example of an initial setting flow in SPI operating mode is shown in figure 19.14. SPI operating mode Initial setting start Set CMNCR. • Set SPI operating mode. • Set the fixed value of the pins during SPBSSL output idle and that for 1-bit/2-bit size. • Set the SPBCLK edges for output shift and input latch. • Set the SPBSSL signal polarity. • Set the SPBCLK output direction during SPBSSL negation. • Set the number of serial flash memories connected. Set SSLDR. • Set the various delay timing. Set SPBCR. • Set the transfer bit rate. SPI operating mode Initial setting end Figure 19.14 Example of Initial Setting Flow in SPI Operating Mode Page 1004 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 19 SPI Multi I/O Bus Controller Data Transfer Setting Flow An example of a data transfer setting flow in SPI operating mode is shown in figure 19.15. SPI operating mode Initial setting end Set SMCR, SMCMR, SMADR, SMOPR, SMENR, SMWDR0, and SMWDR1. Set the SPIE bit in SMCR to 1. Dummy-read CMNSR four times No Is the TEND bit in CMNSR is 1? • Set the SPBSSL signal level to be kept. • Enable data reading or data writing. • Set the command/optional command/address/option data when reading. • Enable the transfer data and set the transfer data size in bit units. • Set the write data (valid when the SPIWE bit in SMCR is set to 1). • Transfer the data when the SPIE bit is set to 1. • To ensure sufficient time for the TEND bit to become 0 after setting of the SPIE bit to 1, dummy-read CMNSR four times. • After data transfer, the TEND bit is set to 1. Yes Read from SMRDR0 and SMRDR1. Yes • Read the data (valid when the SPIRE bit in SMCR is set to 1). Is transfer continued? No SPI operating mode Transfer operation end Figure 19.15 Example of a Data Transfer Setting Flow in SPI Operating Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1005 of 3092 Section 19 SPI Multi I/O Bus Controller 19.5.9 (1) SH7268 Group, SH7269 Group Transfer Format SPBSSL Pin Enable Polarity Control The enable polarity of the SPBSSL pin can be changed with the SSLP bit in CMNCR. (2) SPBCLK Output The SPBCLK output direction during SPBSSL negation can be set with the CPOL bit in CMNCR. (3) Data Transmission and Reception Timing The data transmission timing can be set to odd or even edge with the CPHAT bit in CMNCR. Similarly, the data reception timing can be set to odd or even edge with the CPHAR bit in CMNCR. (4) Delay Period t1 is the time period from SPBSSL pin assertion to SPBCLK oscillation (clock delay). t2 is the time period till the SPBSSL signal negation after the SPBCLK oscillation is stopped (SPBSSL negation delay). t3 is the time period required to prevent SPBSSL signal assertion for the next transfer after the end of the previous transfer (next access delay). t2 and t3 are set to 1.5 SPBCLK cycles and 1 SPBCLK cycle, respectively. Page 1006 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller t1 t2 t3 SPBCLK (CPOL = 0) SPBCLK (CPOL = 1) Output pin (CPHAT = 0) Output pin (CPHAT = 1) Sampling (CPHAR = 0) Sampling (CPHAR = 1) SPBSSL (SSLP = 0) SPBSSL (SSLP = 1) Figure 19.16 Transfer Format R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1007 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.5.10 Data Format This module can input and output data in the order of command, optional command, address, option data, and data. (1) Data Registers Table 19.6 shows the input and output data. Table 19.6 Data Registers Data External Address Space Read Operation SPI Operation Command (8 bits) CMD[7:0] bits in DRCMR CMD[7:0] bits in SMCMR Optional command (8 bits) OCMD[7:0] bits in DRCMR OCMD[7:0] bits in SMCMR Address (32/24 bits) BSZ[1:0] = 00 (one flash memory connected) 32 bits: DREAR.EAV[6:1 to 0] bits + lower [25 to 24:0] bits of the read address. 24 bits: Lower [23:0] bits of the read address 32 bits: ADR[31:0] bits in SMADR 24 bits: ADR[23:0] bits in SMADR BSZ[1:0] = 01 (two flash memories connected) 32 bits: DREAR.EAV[7:1 to 0] bits + lower [25 to 24:1] bits of the read address. 24 bits: Lower [24:1] bits of the read address Option data (8 bits  4) DROPR Transfer data Normal read: 8, 16, 32, and 64 bits Read: SMRDR0, SMRDR1 Burst read: 64  RBURST bits Page 1008 of 3092 SMOPR Write: SMWDR0, SMWDR1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 19 SPI Multi I/O Bus Controller Data Enable In external address space read mode, transfer enable or disable of the command, optional command, address, and option data can be controlled with the CDE, OCDE, ADE[3:0], and OPDE[3:0] bits in DRENR, respectively. Similarly, in SPI operating mode, enable or disable of the command, optional command, address, option data, and transfer data can be controlled with the CDE, OCDE, ADE[3:0], OPDE[3:0], and SPIDE[3:0] bits in SMENR, respectively. However, disabling all the above parameters is prohibited in SPI operating mode. At least one of them must be enabled. For the address and option data in external address space read mode; and the address, option data, and transfer data in SPI operating mode, the enable bit setting allowed is determined according to the transfer data size. For the allowed setting combinations of the enable bits and transfer data size, refer to the description of the pertinent register. If data is disabled, that data is skipped, and input and output of the next data is carried out. The command, optional command, address, and option data are always output. In external address space read mode, data is always input; and in SPI operating mode, input and output of data is determined based on the settings of the SPIRE and SPIWE bits in SMCR. Optional Command command Option data Address Transfer data Data In external address space read mode (EAV[7:0]+) read address CMD OCMD CMD OCMD In external address space read mode CDE OCDE ADE[3] ADE[2] ADE[1] ADE[0] OPDE[3] OPDE[2]OPDE[1]OPDE[0] In SPI operating mode CDE OCDE ADE[3] ADE[2] ADE[1] SPIDE ADE[0] OPDE[3] OPDE[2]OPDE[1]OPDE[0] [3] In SPI operating mode ADR [31:24] ADR [23:16] ADR [15:8] ADR [7:0] OPD3 OPD2 OPD1 OPD0 OPD3 OPD2 OPD1 OPD0 Data read length DATA[3] DATA[2] DATA[1] DATA[0] Enable 8 bits 8 bits 32 bits/24 bits 8/16/24/32 bits Always enabled SPIDE [2] SPIDE SPIDE [0] [1] Data length Figure 19.17 Data and Enable R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1009 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller (3) Bit Size In external address space read mode, the size of the command, optional command, address, option data, and the read data in bit units is respectively controlled with the CDB[1:0], OCDB[1:0], ADB[1:0], OPDB[1:0], DRDB[1:0] bits in DRENR. Similarly, in SPI operating mode, the size of the command, optional command, address, option data, and read write data in bit units is controlled with the CDB[1:0], OCDB[1:0], ADB[1:0], OPDB[1:0], and SPIDB[1:0] bits in SMENR. (a) 1-bit Size When the size is set to 1 bit, SPBMI_0 and SPBMI_1 pins will be the input pins and SPBMO_0 and SPBMO_1 pins will be the output pins. SPBIO2_0, SPBIO2_1, SPBIO3_0, and SPBIO3_1 pins are not used. Figures 19.18 and 19.19 show the transfer format examples. t1 t2 t3 SPBSSL SPBCLK SPBMO_0 T7 T6 T5 T4 T3 T2 T1 T0 SPBMI_0 R7 R6 R5 R4 R3 R2 R1 R0 Figure 19.18 Transfer Format Example with 1-Bit Data Size and One Serial Flash Memory Connected Page 1010 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller t1 t2 t3 SPBSSL SPBCLK SPBMO_0 T15 T14 T13 T12 T11 T10 T9 T8 SPBMI_0 R15 R14 R13 R12 R11 R10 R9 R8 SPBMO_1 T7 T6 T5 T4 T3 T2 T1 T0 SPBMI_1 R7 R6 R5 R4 R3 R2 R1 R0 Figure 19.19 Transfer Format Example with 1-Bit Data Size and Two Serial Flash Memories Connected R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1011 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller (b) 2-bit Size When the size is set to 2 bits, SPBIO0_0, SPBIO0_1, SPBIO1_0, and SPBIO1_1 pins will be either the input pins or the output pins. SPBIO2_0, SPBIO2_1, SPBIO3_0, and SPBIO3_1 pins are not used. Figures 19.20 and 19.21 show the transfer format examples. t1 t2 t3 SPBSSL SPBCLK SPBIO1_0 D7 D5 D3 D1 SPBIO0_0 D6 D4 D2 D0 Figure 19.20 Transfer Format Example with 2-Bit Data Size and One Serial Flash Memory Connected Page 1012 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller t1 t2 t3 SPBSSL SPBCLK SPBIO1_0 D15 D13 D11 D9 SPBIO0_0 D14 D12 D10 D8 SPBIO1_1 D7 D5 D3 D1 SPBIO0_1 D6 D4 D2 D0 Figure 19.21 Transfer Format Example with 2-Bit Data Size and Two Serial Flash Memories Connected R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1013 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller (c) 4-bit Size When the size is set to 4 bits, SPBIO0_0, SPBIO0_1, SPBIO1_0, SPBIO1_1, SPBIO2_0, SPBIO2_1, SPBIO3_0, and SPBIO3_1 pins will be either the input pins or the output pins. Figures 19.22 and 19.23 show the transfer format examples. t1 t2 t3 SPBSSL SPBCLK SPBIO3_0 D7 D3 SPBIO2_0 D6 D2 SPBIO1_0 D5 D1 SPBIO0_0 D4 D0 Figure 19.22 Transfer Format Example with 4-Bit Data Size and One Serial Flash Memory Connected Page 1014 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller t1 t2 t3 SPBSSL SPBCLK SPBIO3_0 D15 D11 SPBIO2_0 D14 D10 SPBIO1_0 D13 D9 SPBIO0_0 D12 D8 SPBIO3_1 D7 D3 SPBIO2_1 D6 D2 SPBIO1_1 D5 D1 SPBIO0_1 D4 D0 Figure 19.23 Transfer Format Example with 4-Bit Data Size and Two Serial Flash Memories Connected R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1015 of 3092 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.5.11 Data Pin Control With this module, the status of pins can be automatically changed based on the data size to be used and the read/write settings. The pin status during the SPBSSL negation can be set with the MOIIO3, MOIIO2, MOIIO1, and MOIIO0 bits in CMNCR. The SPBSSL and SPBCLK pins are always output pins. The status of respective pins is specified in tables 19.7 to 19.9. Table 19.7 Pin Status (1) SPBSSL Assertion Command, Optional Command, Address, Option Data SPBSSL Negation 1-bit Size 2-bit Size 4-bit Size SPBMO_0/ SPBIO0_0, SPBMO_1/ SPBIO0_1 MOIIO0 bit value Output Output Output SPBMI_0/ SPBIO1_0, SPBMI_1/ SPBIO1_1 MOIIO1 bit value Hi-Z Output Output SPBIO2_0, SPBIO2_1 MOIIO2 bit value IO2FV bit value IO2FV bit value Output SPBIO3_0, SPBIO3_1 MOIIO3 bit value IO3FV bit value IO3FV bit value Output Pin Page 1016 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller Table 19.8 Pin Status (2) Transfer Data External Address Space Read Operation SPI Operation SPIRE Bit = 1, SPIWE Bit = 0 Pin 1-bit Size 2-bit Size 4-bit Size 1-bit Size 2-bit Size 4-bit Size SPBMO_0/ SPBIO0_0, SPBMO_1/ SPBIO0_1 IO0FV bit value Input Input IO0FV bit value Input Input SPBMI_0/ SPBIO1_0, SPBMI_1/ SPBIO1_1 Input Input Input Input Input Input SPBIO2_0, SPBIO2_1 IO2FV bit value IO2FV bit value Input IO2FV bit value IO2FV bit value Input SPBIO3_0, SPBIO3_1 IO3FV bit value IO3FV bit value Input IO3FV bit value IO3FV bit value Input Table 19.9 Pin Status (3) Transfer Data SPI Operation SPIRE Bit = 0, SPIWE Bit = 1 SPIRE Bit = 1, SPIWE Bit = 1 Pin 1-bit Size 2-bit Size 4-bit Size 1-bit Size 2-bit Size 4-bit Size SPBMO_0/ SPBIO0_0, SPBMO_1/ SPBIO0_1 Output Output Output Output Setting prohibited Setting prohibited SPBMI_0/ SPBIO1_0, SPBMI_1/ SPBIO1_1 Hi-Z Output Output Input Setting prohibited Setting prohibited SPBIO2_0, SPBIO2_1 IO2FV bit value IO2FV bit value Output IO2FV bit value Setting prohibited Setting prohibited SPBIO3_0, SPBIO3_1 IO3FV bit value IO3FV bit value Output IO3FV bit value Setting prohibited Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1017 of 3092 Section 19 SPI Multi I/O Bus Controller SH7268 Group, SH7269 Group 19.5.12 SPBSSL Pin Control Negation conditions of the SPBSSL pin are as follows. (1) External Address Space Read Mode (a) Normal read operation (RBE bit in DRCR = 0) SPBSSL negated after completing the data transfer and t2 cycle. (b) Burst read without automatic SPBSSL negation (RBE bit in DRCR = 1, SSLE bit in DRCR = 0) SPBSSL negated after completing the data transfer and t2 cycle. (c) Burst read with automatic SPBSSL negation (RBE bit in DRCR = 1, SSLE bit in DRCR = 1)  SPBSSL negated after t2 cycle when the read address is not continuous with the previously read address (2) SPI Operating Mode (a) SPBSSL pin assertion not retained (SSLKP bit in SMCR = 0) SPBSSL negated after completing the data transfer and t2 cycle. (b) SPBSSL pin assertion retained (SSLKP bit in SMCR = 1) SPBSSL not negated. When to be negated, data should be transferred after setting the SSLKP bit to 0. Page 1018 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 19 SPI Multi I/O Bus Controller 19.5.13 Flags This module has two flag bits SSLF and TEND in CMNSR. These bits are read-only bits. (1) SSLF Bit This bit indicates the SPBSSL pin status. The status is 1 when the SPBSSL is asserted, and the status is 0 when the SPBSSL is negated. (2) TEND Bit This bit indicates whether transfer of data is in progress or the transfer of data has ended. During t1 time period, data transfer, and t2 time period, the TEND bit is read as 0 to indicate that the transfer of data is in progress. When other than the above, the TEND bit is read as 1 to indicate that transfer of data has ended. (3) Register Re-writing Timing The status of the SSLF and TEND bits determines the register re-writing timing. Table 19.10 lists the re-writing timing of various registers. Table 19.10 Re-writing Timing of Various Registers Flag Re-writable Registers Remarks SSLF = 0 Registers CMNCR, SSLDR, SPBCR, and DRCR When the SPBSSL pin is negated TEND = 1 Registers DRCMR, DREAR, DROPR, DRENR, SMCR, SMCMR, SMADR, SMOPR, SMENR, SMWDR0, and SMWDR1 At the end of transfer 19.6 Usage Note 19.6.1 Note on Transfer Start from SPBSSL Hold State in SPI Operation Mode In SPI operation mode, set the SPIWE bit in the SMCR register to 1 when starting transfer with command, optional command, address, and option data while the SPBSSL pin is being asserted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1019 of 3092 Section 19 SPI Multi I/O Bus Controller Page 1020 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 20 I2C Bus Interface 3 Section 20 I2C Bus Interface 3 The I2C bus interface 3 conforms to and provides a subset of the Philips I2C (Inter-IC) bus interface functions. However, the configuration of the registers that control the I2C bus differs partly from the Philips register configuration. The I2C bus interface 3 has four channels. 20.1 Features  Selection of I2C format or clocked synchronous serial format  Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. I2C bus format:  Start and stop conditions generated automatically in master mode  Selection of acknowledge output levels when receiving  Automatic loading of acknowledge bit when transmitting  Bit synchronization function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed.  Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection  The direct memory access controller can be activated by a transmit-data-empty request or receive-data-full request to transfer data.  Direct bus drive Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive function is selected. Clocked synchronous serial format:  Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error  The direct memory access controller can be activated by a transmit-data-empty request or receive-data-full request to transfer data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1021 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Figure 20.1 shows a block diagram. Transfer clock generation circuit Transmission/ reception control circuit Output control SCL ICCR1 ICCR2 ICMR Noise filter Output control SDA ICDRS Peripheral bus ICDRT SAR Address comparator Noise canceler ICDRR NF2CYC Bus state decision circuit Arbitration decision circuit [Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: NF2CYC: ICSR ICIER I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register NF2CYC register Interrupt generator Interrupt request Figure 20.1 Block Diagram Page 1022 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group 20.2 Input/Output Pins Table 20.1 shows the pin configuration. Table 20.1 Pin Configuration Pin Name Symbol I/O Function Serial clock SCL0 to SCL3 I/O I2C serial clock input/output Serial data SDA0 to SDA3 I/O I2C serial data input/output Figure 20.2 shows an example of I/O pin connections to external circuits. PVcc* PVcc* SCL in SCL SCL SDA SDA SCL out SDA in SCL in SCL out SCL SDA (Master) SCL SDA SDA out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Note: * Turn on/off PVcc for the I2C bus power supply and for this LSI simultaneously. Figure 20.2 External Circuit Connections of I/O Pins R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1023 of 3092 Section 20 I2C Bus Interface 3 20.3 SH7268 Group, SH7269 Group Register Descriptions Table 20.2 shows the register configuration. Table 20.2 Register Configuration Channel Register Name 0 I2C bus control register 1 Access Size ICCR1_0 R/W H'00 H'FFFEE000 8 ICCR2_0 R/W H'7D H'FFFEE001 8 2 ICMR_0 R/W H'38 H'FFFEE002 8 2 ICIER_0 R/W H'00 H'FFFEE003 8 2 I C bus status register ICSR_0 R/W H'00 H'FFFEE004 8 Slave address register SAR_0 R/W H'00 H'FFFEE005 8 I C bus transmit data register ICDRT_0 R/W H'FF H'FFFEE006 8 I2C bus receive data register ICDRR_0 R/W H'FF H'FFFEE007 8 NF2CYC register I C bus mode register I C bus interrupt enable register 2 NF2CYC_0 R/W H'00 H'FFFEE008 8 2 ICCR1_1 R/W H'00 H'FFFEE400 8 2 ICCR2_1 R/W H'7D H'FFFEE401 8 2 ICMR_1 R/W H'38 H'FFFEE402 8 2 ICIER_1 R/W H'00 H'FFFEE403 8 2 I C bus status register ICSR_1 R/W H'00 H'FFFEE404 8 Slave address register SAR_1 R/W H'00 H'FFFEE405 8 I2C bus transmit data register ICDRT_1 R/W H'FF H'FFFEE406 8 I C bus receive data register ICDRR_1 R/W H'FF H'FFFEE407 8 NF2CYC register I C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register 2 2 Initial Value Address 2 I C bus control register 2 1 Abbreviation R/W NF2CYC_1 R/W H'00 H'FFFEE408 8 2 ICCR1_2 R/W H'00 H'FFFEE800 8 2 ICCR2_2 R/W H'7D H'FFFEE801 8 2 ICMR_2 R/W H'38 H'FFFEE802 8 2 ICIER_2 R/W H'00 H'FFFEE803 8 I C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register 2 I C bus status register ICSR_2 R/W H'00 H'FFFEE804 8 Slave address register SAR_2 R/W H'00 H'FFFEE805 8 I2C bus transmit data register ICDRT_2 R/W H'FF H'FFFEE806 8 I C bus receive data register ICDRR_2 R/W H'FF H'FFFEE807 8 NF2CYC register NF2CYC_2 R/W H'00 H'FFFEE808 8 2 Page 1024 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Channel Register Name 3 I2C bus control register 1 Initial Value Address Access Size ICCR1_3 R/W H'00 H'FFFEEC00 8 2 ICCR2_3 R/W H'7D H'FFFEEC01 8 2 ICMR_3 R/W H'38 H'FFFEEC02 8 2 ICIER_3 R/W H'00 H'FFFEEC03 8 I C bus control register 2 I C bus mode register I C bus interrupt enable register 2 I C bus status register ICSR_3 R/W H'00 H'FFFEEC04 8 Slave address register SAR_3 R/W H'00 H'FFFEEC05 8 2 ICDRT_3 R/W H'FF H'FFFEEC06 8 2 I C bus receive data register ICDRR_3 R/W H'FF H'FFFEEC07 8 NF2CYC register NF2CYC_3 R/W H'00 H'FFFEEC08 8 I C bus transmit data register 20.3.1 Abbreviation R/W I2C Bus Control Register 1 (ICCR1) ICCR1 is an 8-bit readable/writable register that enables or disables the I2C bus interface 3, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit: Initial value: R/W: 7 6 5 4 ICE RCVD MST TRS 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 CKS[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface 3 Enable 0 R/W 0: SCL and SDA output is disabled. (Input to SCL and SDA is enabled.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable Enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1025 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 5 MST 0 R/W Master/Slave Select 4 TRS 0 R/W Transmit/Receive Select In master mode with the I2C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. When seven bits after the start condition is issued in slave receive mode match the slave address set to SAR and the 8th bit is set to 1, TRS is automatically set to 1. If an overrun error occurs in master receive mode with the clocked synchronous serial format, MST is cleared and the mode changes to slave receive mode. Operating modes are described below according to MST and TRS combination. When clocked synchronous serial format is selected and MST = 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode 3 to 0 CKS[3:0] 0000 R/W Transfer Clock Select These bits should be set according to the necessary transfer rate (table 20.3) in master mode. Page 1026 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Table 20.3 Transfer Rate NF2CYC ICCR1 Transfer Rate (kHz) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CKS4 CKS3 CKS2 CKS1 CKS0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: Clock P0/44 P0/52 P0/64 P0/72 P0/84 P0/92 P0/100 P0/108 P0/176 P0/208 P0/256 P0/288 P0/336 P0/368 P0/400 P0/432 P0/352 P0/416 P0/512 P0/576 P0/672 P0/736 P0/800 P0/864 P0/704 P0/832 P0/1024 P0/1152 P0/1344 P0/1472 P0/1600 P0/1728 P0 = 25.00 MHz P0 = 33.33 MHz 568.18 480.77 390.63 347.22 297.62 271.74 250.00 231.48 142.05 120.19 97.66 86.81 74.40 67.93 62.50 57.87 71.02 60.10 48.83 43.40 37.20 33.97 31.25 28.94 35.51 30.05 24.41 21.70 18.60 16.98 15.63 14.47 757.50 640.96 520.78 462.92 396.79 362.28 333.30 308.61 189.38 160.24 130.20 115.73 99.20 90.57 83.33 77.15 94.69 80.12 65.10 57.86 49.60 45.29 41.66 38.58 47.34 40.06 32.55 28.93 24.80 22.64 20.83 19.29 The settings should satisfy external specifications. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1027 of 3092 Section 20 I2C Bus Interface 3 20.3.2 SH7268 Group, SH7269 Group I2C Bus Control Register 2 (ICCR2) ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus. Bit: Initial value: R/W: 7 6 2 1 BBSY SCP SDAO SDAOP SCLO 5 4 - IICRST - 0 R/W 1 R/W 1 R/W 1 R 0 R/W 1 R 1 R/W Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 3 1 R 0 Enables to confirm whether the I2C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial format, this 2 bit is always read as 0. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. 6 SCP 1 R/W Start/Stop Issue Condition Disable Controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. Even if 1 is written to this bit, the data will not be stored. Page 1028 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance). 4 SDAOP 1 R/W SDAO Write Protect Controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0. This bit is always read as 1. 3 SCLO 1 R SCL Output Level Monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. 2  1 R Reserved This bit is always read as 1. The write value should always be 1. 1 IICRST 0 R/W Control Part Reset Resets bits BC[2:0] in ICMR and internal circuits. If this bit is set to 1 when hang-up occurs because of communication failure during I2C bus operation, bits BC[2:0] in ICMR and internal circuits can be reset. 0  1 R Reserved This bit is always read as 1. The write value should always be 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1029 of 3092 Section 20 I2C Bus Interface 3 20.3.3 SH7268 Group, SH7269 Group I2C Bus Mode Register (ICMR) ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bits BC[2:0] are initialized to H'0 by the IICRST bit in ICCR2. Bit: Initial value: R/W: 7 6 5 4 3 MLS - - - BCWP 0 R/W 0 R 1 R 1 R 1 R/W 2 1 0 BC[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0 R/W 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used. 6  0 R Reserved This bit is always read as 0. The write value should always be 0. 5, 4  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 3 BCWP 1 R/W BC Write Protect Controls the BC[2:0] modifications. When modifying the BC[2:0] bits, this bit should be cleared to 0. In clocked synchronous serial mode, the BC[2:0] bits should not be modified. 0: When writing, values of the BC[2:0] bits are set. 1: When reading, 1 is always read. When writing, settings of the BC[2:0] bits are invalid. Page 1030 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 to 0 BC[2:0] 000 R/W Bit Counter These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Should be made between transfer frames. If these bits are set to a value other than B'000, the setting should be made while the SCL pin is low. The bit value returns to B'000 automatically at the end of a data transfer including the acknowledge bit. And the value becomes B'111 automatically after the stop condition detection. These bits are cleared by a power-on reset and in software standby mode and module standby mode. These bits are also cleared by setting the IICRST bit of ICCR2 to 1. With the clocked synchronous serial format, these bits should not be modified. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 I2C Bus Format Clocked Synchronous Serial Format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bit 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits Page 1031 of 3092 Section 20 I2C Bus Interface 3 20.3.4 SH7268 Group, SH7269 Group I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits received. Bit: Initial value: R/W: 7 6 5 4 3 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 TIE 0 R/W 2 1 0 R 0 0 R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1 or 0, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable Enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable Enables or disables the receive data full interrupt request (RXI) when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) are disabled. 1: Receive data full interrupt request (RXI) are enabled. Page 1032 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable Enables or disables the NACK detection and arbitration lost/overrun error interrupt request (NAKI) when the NACKF or AL/OVE bit in ICSR is set. NAKI can be canceled by clearing the NACKF, AL/OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled. 3 STIE 0 R/W Stop Condition Detection Interrupt Enable Enables or disables the stop condition detection interrupt request (STPI) when the STOP bit in ICSR is set. 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. 2 ACKE 0 R/W Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted. 1 ACKBR 0 R Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. This bit can be canceled by setting the BBSY bit in ICCR2 to 1. 0: Receive acknowledge = 0 1: Receive acknowledge = 1 0 ACKBT 0 R/W Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1033 of 3092 Section 20 I2C Bus Interface 3 20.3.5 SH7268 Group, SH7269 Group I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status. Bit: Initial value: R/W: 7 6 1 0 TDRE TEND RDRF NACKF STOP AL/OVE 5 4 AAS ADZ 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 3 0 R/W 2 0 R/W Bit Bit Name Initial Value R/W Description 7 TDRE 0 R/W Transmit Data Register Empty [Clearing conditions]  When 0 is written in TDRE after reading TDRE = 1  When data is written to ICDRT [Setting conditions]     6 TEND 0 R/W When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When the start condition (including retransmission) is issued When slave mode is changed from receive mode to transmit mode Transmit End [Clearing conditions]  When 0 is written in TEND after reading TEND = 1  When data is written to ICDRT [Setting conditions]   Page 1034 of 3092 When the ninth clock of SCL rises with the I2C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clocked synchronous serial format R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 5 RDRF 0 R/W Receive Data Full [Clearing conditions]  When 0 is written in RDRF after reading RDRF = 1  When ICDRR is read [Setting condition]  When a receive data is transferred from ICDRS to ICDRR 4 NACKF 0 R/W No Acknowledge Detection Flag [Clearing condition]  When 0 is written in NACKF after reading NACKF =1 [Setting condition]  When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 3 STOP 0 R/W Stop Condition Detection Flag [Clearing condition]  When 0 is written in STOP after reading STOP = 1 [Setting condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When a stop condition is detected after frame transfer is completed Page 1035 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag Indicates that arbitration was lost in master mode with 2 the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface 3 detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been occupied by another master. [Clearing condition]  When 0 is written in AL/OVE after reading AL/OVE =1 [Setting conditions]  If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode  When the SDA pin outputs high in master mode while a start condition is detected  When the final bit is received with the clocked synchronous format while RDRF = 1 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA[6:0] in SAR. [Clearing condition]  When 0 is written in AAS after reading AAS = 1 [Setting conditions]  When the slave address is detected in slave receive mode  When the general call address is detected in slave receive mode. 0 ADZ 0 R/W General Call Address Recognition Flag 2 This bit is valid in slave receive mode with the I C bus format. [Clearing condition]  When 0 is written in ADZ after reading ADZ = 1 [Setting condition]  When the general call address is detected in slave receive mode Page 1036 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group 20.3.6 Slave Address Register (SAR) SAR is an 8-bit readable/writable register that selects the communications format and sets the slave address. In slave mode with the I2C bus format, if the upper seven bits of SAR match the upper seven bits of the first frame received after a start condition, this module operates as the slave device. 7 Bit: 6 5 4 3 2 1 SVA[6:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 FS 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1 SVA[6:0] 0000000 R/W Slave Address 0 R/W 0 R/W 0 R/W These bits set a unique address in these bits, differing form the addresses of other slave devices connected to the I2C bus. 0 FS 0 R/W Format Select 0: I2C bus format is selected 1: Clocked synchronous serial format is selected 20.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT while transferring data of ICDRS, continuous transfer is possible. Bit: Initial value: R/W: R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Page 1037 of 3092 Section 20 I2C Bus Interface 3 20.3.8 SH7268 Group, SH7269 Group I2C Bus Receive Data Register (ICDRR) ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. Bit: Initial value: R/W: 20.3.9 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W I2C Bus Shift Register (ICDRS) ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU. Page 1038 of 3092 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group 20.3.10 NF2CYC Register (NF2CYC) NF2CYC is an 8-bit readable/writable register that selects a transfer clock and the range of the noise filtering for the SCL and SDA pins. For details of the noise filter, see section 20.4.7, Noise Filter. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - CKS4 - - PRS NF2 CYC 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 CKS4 0 R/W Transfer Clock Select This bit should be set according to the necessary transfer rate (table 20.3) in master mode. 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 PRS 0 R/W Pulse Width Ratio Select Specifies the ratio of the high-level period to the lowlevel period for the SCL signal. 0: The ratio of high to low is 0.5 to 0.5. 1: The ratio of high to low is about 0.4 to 0.6. 0 NF2CYC 0 R/W Noise Filtering Range Select 0: The noise less than one cycle of the peripheral clock can be filtered out 1: The noise less than two cycles of the peripheral clock can be filtered out R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1039 of 3092 Section 20 I2C Bus Interface 3 20.4 SH7268 Group, SH7269 Group Operation The I2C bus interface 3 can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. I2C Bus Format 20.4.1 Figure 20.3 shows the I2C bus formats. Figure 20.4 shows the I2C bus timing. The first frame following a start condition always consists of eight bits. (a) I2C bus format (FS = 0) S SLA R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m ≥ 1) m (b) I2C bus format (Start condition retransmission, FS = 0) S SLA R/W A DATA A/A S SLA R/W A DATA 1 7 1 1 n1 1 1 7 1 1 n2 1 m1 1 A/A P 1 1 m2 n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 ≥ 1) Figure 20.3 I2C Bus Formats SDA SCL S 1-7 8 9 SLA R/W A 1-7 DATA 8 9 A 1-7 8 DATA 9 A P Figure 20.4 I2C Bus Timing [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. Page 1040 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 20.4.2 Section 20 I2C Bus Interface 3 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 20.5 and 20.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Also, set bits CKS[3:0] in ICCR1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1041 of 3092 Section 20 I2C Bus Interface 3 SCL (Master output) SH7268 Group, SH7269 Group 1 SDA (Master output) 2 Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 R/W Slave address SDA (Slave output) A TDRE TEND ICDRT Address + R/W ICDRS Data 1 Address + R/W User [2] Instruction of start processing condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 20.5 Master Transmit Mode Operation Timing (1) SCL (Master output) 9 SDA (Master output) SDA (Slave output) 1 Bit 7 2 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A 9 A/A TDRE TEND Data n ICDRT ICDRS Data n User [5] Write data to ICDRT processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 20.6 Master Transmit Mode Operation Timing (2) Page 1042 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 20.4.3 Section 20 I2C Bus Interface 3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 20.7 and 20.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICSR is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode. Note: If only one byte is received, read ICDRR (dummy-read) after the RCVD bit in ICCR1 is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1043 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SDA (Slave output) Bit 7 A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF Data 1 ICDRS Data 1 ICDRR [3] Read ICDRR User processing [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 20.7 Master Receive Mode Operation Timing (1) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR User processing Data n-1 [5] Read ICDRR after setting RCVD Data n [6] Issue stop condition [7] Read ICDRR, and clear RCVD [8] Set slave receive mode Figure 20.8 Master Receive Mode Operation Timing (2) Page 1044 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 20.4.4 Section 20 I2C Bus Interface 3 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 20.9 and 20.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS bit in ICCR1 and the TDRE bit in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is opened. 5. Clear TDRE. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1045 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Slave transmit mode Slave receive mode SCL (Master output) 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT Data 1 ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 20.9 Slave Transmit Mode Operation Timing (1) Page 1046 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 Slave receive mode 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 20.10 Slave Transmit Mode Operation Timing (2) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1047 of 3092 Section 20 I2C Bus Interface 3 20.4.5 SH7268 Group, SH7269 Group Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 20.11 and 20.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR [2] Read ICDRR (dummy read) Figure 20.11 Slave Receive Mode Operation Timing (1) Page 1048 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Read ICDRR [4] Read ICDRR Figure 20.12 Slave Receive Mode Operation Timing (2) 20.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format Figure 20.13 shows the clocked synchronous serial transfer format. The transfer data is output from the fall to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2. SCL SDA Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 20.13 Clocked Synchronous Serial Transfer Format R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1049 of 3092 Section 20 I2C Bus Interface 3 (2) SH7268 Group, SH7269 Group Transmit Operation In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 20.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1. SCL 1 2 7 8 1 7 8 1 SDA (Output) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 TRS TDRE Data 1 ICDRT ICDRS User processing Data 2 Data 1 [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS Data 3 Data 2 [3] Write data to ICDRT [3] Write data to ICDRT Figure 20.14 Transmit Mode Operation Timing Page 1050 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 20 I2C Bus Interface 3 Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to Figure 20.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data. Notes: Follow the steps below to receive only one byte with MST = 1 specified. See figure 20.16 for the operation timing. 1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) 2. Set MST = 1 while the RCVD bit in ICCR1 is 0. This causes the receive clock to be output. 3. Check if the BC2 bit in ICMR is set to 1 and then set the RCVD bit in ICCR1 to 1. This causes the SCL to be fixed to the high level after outputting one byte of the receive clock. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1051 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group SCL 1 2 7 8 1 7 8 1 2 SDA (Input) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 MST TRS RDRF Data 1 ICDRS Data 2 Data 1 ICDRR User processing Data 3 Data 2 [2] Set MST (when outputting the clock) [3] Read ICDRR [3] Read ICDRR Figure 20.15 Receive Mode Operation Timing SCL 1 2 3 4 5 6 7 8 SDA (Input) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 001 000 MST RCVD BC2 to BC0 000 [2] Set MST 111 110 101 100 011 010 [3] Set the RCVD bit after checking if BC2 = 1 Figure 20.16 Operation Timing for Receiving One Byte (MST = 1) Page 1052 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group 20.4.7 Noise Filter The logic levels at the SCL and SDA pins are routed through noise filters before being latched internally. Figure 20.17 shows a block diagram of the noise filter circuit. The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do not agree, the previous value is held. Sampling clock SCL or SDA input signal C C Q D D Latch Latch C Q Q D Latch Match detector 1 Match detector 0 Internal SCL or SDA signal NF2CYC Peripheral clock cycle Sampling clock Figure 20.17 Block Diagram of Noise Filter R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1053 of 3092 Section 20 I2C Bus Interface 3 20.4.8 SH7268 Group, SH7269 Group Example of Use Flowcharts in respective modes that use the I2C bus interface 3 are shown in figures 20.18 to 20.21. Start Initialize Read BBSY in ICCR2 [1] No BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1 [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start condition. [4] Set the first byte (slave address + R/W) of transmit data. [5] Wait for 1 byte to be transmitted. [6] Test the acknowledge transferred from the specified slave device. [7] Set the second and subsequent bytes (except for the final byte) of transmit data. [8] Wait for ICDRT empty. [9] Set the last byte of transmit data. [2] Write 1 to BBSY and 0 to SCP [3] Write transmit data in ICDRT [4] Read TEND in ICSR [5] No TEND=1 ? Yes Read ACKBR in ICIER ACKBR=0 ? No [6] [10] Wait for last byte to be transmitted. [11] Clear the TEND flag. Yes Transmit mode? Yes No Write transmit data in ICDRT Master receive mode [7] [13] Issue the stop condition. Read TDRE in ICSR No [8] [14] Wait for the creation of stop condition. TDRE=1 ? Yes No [12] Clear the STOP flag. [15] Set slave receive mode. Clear TDRE. Last byte? Yes Write transmit data in ICDRT [9] Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR [11] Clear STOP in ICSR [12] Write 0 to BBSY and SCP [13] Read STOP in ICSR No STOP=1 ? Yes Set MST and TRS in ICCR1 to 0 [14] [15] Clear TDRE in ICSR End Figure 20.18 Sample Flowchart for Master Transmit Mode Page 1054 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Master receive mode [1] Clear TEND, select master receive mode, and then clear TDRE. *1 [2] Set acknowledge to the transmit device. *1 [3] Dummy-read ICDDR. *1 [4] Wait for 1 byte to be received*2 [5] Check whether it is the (last receive - 1).*2 [6] Read the receive data. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).*2 [8] Read the (final byte - 1) of received data. [9] Wait for the last byte to be receive. Clear TEND in ICSR Clear TRS in ICCR1 to 0 [1] Clear TDRE in ICSR Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] Read RDRF in ICSR No [4] RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes [5] [10] Clear the STOP flag. [6] [11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1 [7] Set RCVD in ICCR1 to 1 Read ICDRR [14] Clear RCVD. [8] [15] Set slave receive mode. [9] Notes: 1. Make sure that no interrupt will be generated during steps [1] to [3]. 2. When the (last receive -1) is checked (when step [5] is approved), make sure that no interrupt will be generated during steps [4], [5], and [7]. Read RDRF in ICSR No RDRF=1 ? [13] Read the last byte of receive data. Yes Clear STOP in ICSR [10] Write 0 to BBSY and SCP [11] [Complement] When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. Read STOP in ICSR No [12] STOP=1 ? Yes Read ICDRR [13] Clear RCVD in ICCR1 to 0 [14] Clear MST in ICCR1 to 0 [15] End Figure 20.19 Sample Flowchart for Master Receive Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1055 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR [5] Wait for the last byte to be transmitted. [3] No TDRE=1 ? Yes Yes [6] Clear the TEND flag. [7] Set slave receive mode. Last byte? No [2] Set transmit data for ICDRT (except for the last byte). [8] Dummy-read ICDRR to release the SCL. [4] [9] Clear the TDRE flag. Write transmit data in ICDRT Read TEND in ICSR [5] No TEND=1 ? Yes Clear TEND in ICSR [6] Clear TRS in ICCR1 to 0 [7] Dummy-read ICDRR [8] Clear TDRE in ICSR [9] End Figure 20.20 Sample Flowchart for Slave Transmit Mode Page 1056 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received. Yes No Read ICDRR [5] [8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received. [6] [10] Read for the last byte of receive data. Set ACKBT in ICIER to 1 [7] Read ICDRR [8] Note: When the size of receive data is only one byte in reception, steps [2] to [6] are skipped after step [1], before jumping to step [7]. The step [8] is dummy-read in ICDRR. Read RDRF in ICSR No [9] RDRF=1 ? Yes Read ICDRR [10] End Figure 20.21 Sample Flowchart for Slave Receive Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1057 of 3092 Section 20 I2C Bus Interface 3 20.5 SH7268 Group, SH7269 Group Interrupt Requests There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost/overrun error. Table 20.4 shows the contents of each interrupt request. Table 20.4 Interrupt Requests 2 Interrupt Request Abbreviation Interrupt Condition I C Bus Format Transmit data Empty TXI (TDRE = 1)  (TIE = 1)   TEI (TEND = 1)  (TEIE = 1)   Receive data full RXI (RDRF = 1)  (RIE = 1)   STOP recognition STPI (STOP = 1)  (STIE = 1)   NACK detection NAKI {(NACKF = 1) + (AL = 1)}  (NAKIE = 1)     Transmit end Arbitration lost/ overrun error Clocked Synchronous Serial Format When the interrupt condition described in table 20.4 is 1, the CPU executes an interrupt exception handling. Note that a TXI or RXI interrupt can activate the direct memory access controller if the setting for direct memory access controller activation has been made. In such a case, an interrupt request is not sent to the CPU. Interrupt sources should be cleared in the exception handling. The TDRE and TEND bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time when the transmit data is written to ICDRT. Therefore, when the TDRE bit is cleared to 0, then an excessive data of one byte may be transmitted. Page 1058 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 20.6 Section 20 I2C Bus Interface 3 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below.  When SCL is driven to low by the slave device  When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 20.22 shows the timing of the bit synchronous circuit and table 20.5 shows the time when the SCL output changes from low to Hi-Z then SCL is monitored. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1059 of 3092 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group (a) SCL is normally driven 1 Synchronous clock * VIH SCL pin *2 Internal delay Internal SCL monitor The monitor value is high level. Time for monitoring SCL (b) When SCL is driven to low by the slave device Synchronous clock *1 SCL is driven to low by the slave device. VIH VIH SCL pin SCL is not driven to low. 2 Internal * delay Internal delay *2 Internal SCL monitor The monitor value is low level. Time for monitoring SCL The monitor value is high level. Time for monitoring SCL The monitor value is high level. Time for monitoring SCL (c) When the rising speed of SCL is lowered 1 Synchronous clock * The frequency is not the setting frequency. VIH SCL pin SCL is not driven to low. Internal SCL monitor Internal delay *2 The monitor value is low level. SCL Notes: 1. The clock is set according to table 20.3 Transfer Rate. 2. When the NF2CYC bit in NF2CYC (NF2CYC) is set to 0, the internal delay time is 3 to 4 tpcyc. When this bit is set to 1, the internal delay time is 4 to 5 tpcyc. Figure 20.22 Bit Synchronous Circuit Timing Page 1060 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 20 I2C Bus Interface 3 SH7268 Group, SH7269 Group Table 20.5 Time for Monitoring SCL CKS4 CKS3 0 0 1 1 0 1 Note: * CKS2 Time for Monitoring SCL 0 9 tpcyc* 1 21 tpcyc* 0 39 tpcyc* 1 87 tpcyc* 0 79 tpcyc* 1 175 tpcyc* 0 159 tpcyc* 1 351 tpcyc* tpcyc indicates the frequency of the peripheral clock 0 (P0). 20.7 Usage Notes 20.7.1 Note on Setting for Multi-Master Operation In multi-master operation, when the transfer rate setting for this module (ICCR1.CKS[3:0]) makes this LSI slower than the other masters, pulse cycles with an unexpected length will infrequently be output on SCL. Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other masters. 20.7.2 Note on Master Receive Mode Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data. In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer full, a stop condition may not be issued. Use either 1 or 2 below as a measure against the situations above. 1. In master receive mode, read ICDRR before the rising edge of the 8th clock. 2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1061 of 3092 Section 20 I2C Bus Interface 3 20.7.3 SH7268 Group, SH7269 Group Note on Setting ACKBT in Master Receive Mode In master receive mode operation, set ACKBT before the falling edge of the 8th SCL cycle of the last data being continuously transferred. Not doing so can lead to an overrun for the slave transmission device. 20.7.4 Note on the States of Bits MST and TRN when Arbitration is Lost When sequential bit-manipulation instructions are used to set the MST and TRS bits to select master transmission in multi-master operation, a conflicting situation where AL in ICSR = 1 but the mode is master transmit mode (MST = 1 and TRS = 1) may arise; this depends on the timing of the loss of arbitration when the bit manipulation instruction for TRS is executed. This can be avoided in either of the following ways.  In multi-master operation, use the MOV instruction to set the MST and TRS bits.  When arbitration is lost, check whether the MST and TRS bits are 0. If the MST and TRS bits have been set to a value other than 0, clear the bits to 0. 20.7.5 Note on I2C-Bus Interface Master Receive Mode After a master receive operation is completed, confirm the falling edge of the ninth clock cycle of the SCL signal and generate a stop condition or regenerate a start condition. 20.7.6 Note on IICRST and BBSY bits When 1 is written to IICRST in ICCR2, this LSI release SCL and SDA pins. Then, if the SDA level changes from low to high under the condition of SCL = high, BBSY in ICCR2 is cleared to 0 assuming that the stop condition has been issued. 20.7.7 Note on Issuance of Stop Conditions in Master Transmit Mode while ACKE = 1 When a stop condition is issued in master transmit mode while the ACKE bit in the I2C bus interrupt enable register (ICIER) is 1, the stop condition may not be normally output depending on the issued timing. To avoid this, recognize the falling edge of the ninth clock before issuance of the stop condition. The falling edge of the ninth clock can be recognized by checking the SCLO bit in the I2C control register 2 (ICCR2). Page 1062 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Section 21 Serial Sound Interface The serial sound interface is a module designed to send or receive audio data interface with various devices offering I2S bus compatibility. It also provides additional modes for other common formats, as well as support for multi-channel mode. 21.1 Features  Number of channels: Six channels  Operating mode: Non-compressed mode The non-compressed mode supports serial audio streams divided by channels.  Serves as both a transmitter and a receiver Channel 0 supports full-duplex communications.  Capable of using serial bus format  Asynchronous transfer takes place between the data buffer and the shift register.  It is possible to select a value as the dividing ratio for the clock used by the serial bus interface.  It is possible to control data transmission or reception with DMA transfer and interrupt requests.  Selects the oversampling clock input from among the following pins: AUDIO_CLK (1 to 50 MHz) AUDIO_X1, AUDIO_X2 (when connecting a crystal resonator: 10 to 50 MHz, when used to input external clock: 1 to 50 MHz)  Includes 8-stage FIFO buffers in transmitter and receiver  Supports multi-channel mode (TDM mode) in which the SSIWS signal is high only for system word 1 period.  Supports WS continue mode in which the SSIWS signal is not stopped. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1063 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Figure 21.1 shows a block diagram of this module. Peripheral bus Interrupt/DMA request Control circuit Serial audio bus Registers SSICR SSISR SSIFCR SSIFSR SSITDMR SSIFTDR (8-step FIFO) SSIFRDR (8-step FIFO) SSITDR SSIRDR SSIDATA* MSB Shift register MSB LSB LSB Shift register AUDIO_CLK Serial clock control SSISCK AUDIO_X1 Crystal oscillator Divider AUDIO_X2 SSIWS Bit counter [Legend] SSICR: SSISR: SSITDR: SSIRDR: SSITDMR: Control register Status register Transmit data register Receive data register TDM mode register SSIFCR: SSIFSR: SSIFTDR: SSIFRDR: FIFO control register FIFO status register Transmit FIFO data register Receive FIFO data register Note: * In channel 0, SSIDATA can be used independently as SSITxD for transmission and SSIRxD for reception. Figure 21.1 Block Diagram of Serial Sound Interface Page 1064 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.2 Section 21 Serial Sound Interface Input/Output Pins Table 21.1 shows the pin assignments relating to this module. Table 21.1 Pin Assignments Channel 0 1 to 5 Common Note: * Pin Name I/O Description SSISCK0* I/O Serial bit clock SSIWS0* I/O Word selection SSITxD0 Output Serial data output SSIRxD0* Input Serial data input SSISCK1 to SSISCK5* I/O Serial bit clock SSIWS1 to SSIWS5* I/O Word selection SSIDATA1 to SSIDATA5* I/O Serial data input/output AUDIO_CLK Input External clock for audio (input oversampling clock) AUDIO_X1 Input AUDIO_X2 Output Crystal resonator/external clock for audio (input oversampling clock) It is possible to select whether or not to use the noise canceler function in the input path when in slave mode. For details, see 48.2.34, Serial Sound Interface Noise Canceler Control Register (SNCR). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1065 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 21.3 Register Description Table 21.2 lists the register configuration. Note that explanation in the text does not refer to the channels. Table 21.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address 0 1 Access Size Control register 0 SSICR_0 R/W H'00000000 H'FFFF0000 8, 16, 32 Status register 0 SSISR_0 R/W*1 H'02000013 H'FFFF0004 8, 16, 32 FIFO control register 0 SSIFCR_0 R/W H'00000000 H'FFFF0010 8, 16, 32 FIFO status register SSIFSR_0 0 R/(W)*2 H'00010000 H'FFFF0014 8, 16, 32 Transmit FIFO data SSIFTDR_0 register 0 W Undefined H'FFFF0018 32 Receive FIFO data register 0 R Undefined H'FFFF001C 32 TDM mode register SSITDMR_0 0 R/W H'00000000 H'FFFF0020 8, 16, 32 Control register 1 R/W H'00000000 H'FFFF0800 8, 16, 32 SSIFRDR_0 SSICR_1 1 Status register 1 SSISR_1 R/W* H'02000013 H'FFFF0804 8, 16, 32 FIFO control register 1 SSIFCR_1 R/W H'00000000 H'FFFF0810 8, 16, 32 FIFO status register SSIFSR_1 1 R/(W)*2 H'00010000 H'FFFF0814 8, 16, 32 Transmit FIFO data SSIFTDR_1 register 1 W Undefined H'FFFF0818 32 Receive FIFO data register 1 R Undefined H'FFFF081C 32 R/W H'00000000 H'FFFF0820 8, 16, 32 SSIFRDR_1 TDM mode register SSITDMR_1 1 Page 1066 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Channel Register Name Abbreviation R/W 2 SSICR_2 R/W 3 Control register 2 Initial Value Address 1 Access Size H'00000000 H'FFFF1000 8, 16, 32 Status register 2 SSISR_2 R/W* H'02000013 H'FFFF1004 8, 16, 32 FIFO control register 2 SSIFCR_2 R/W H'00000000 H'FFFF1010 8, 16, 32 FIFO status register SSIFSR_2 2 R/(W)*2 H'00010000 H'FFFF1014 8, 16, 32 Transmit FIFO data SSIFTDR_2 register 2 W Undefined H'FFFF1018 32 Receive FIFO data register 2 R Undefined H'FFFF101C 32 TDM mode register SSITDMR_2 2 R/W H'00000000 H'FFFF1020 8, 16, 32 Control register 3 R/W H'00000000 H'FFFF1800 8, 16, 32 SSIFRDR_2 SSICR_3 1 Status register 3 SSISR_3 R/W* H'02000013 H'FFFF1804 8, 16, 32 FIFO control register 3 SSIFCR_3 R/W H'00000000 H'FFFF1810 8, 16, 32 FIFO status register SSIFSR_3 3 R/(W)*2 H'00010000 H'FFFF1814 8, 16, 32 Transmit FIFO data SSIFTDR_3 register 3 W Undefined H'FFFF1818 32 Receive FIFO data register 3 R Undefined H'FFFF181C 32 R/W H'00000000 H'FFFF1820 8, 16, 32 SSIFRDR_3 TDM mode register SSITDMR_3 3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1067 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Channel Register Name Abbreviation R/W 4 SSICR_4 R/W 5 Control register 4 Initial Value Address 1 Access Size H'00000000 H'FFFF2000 8, 16, 32 Status register 4 SSISR_4 R/W* H'02000013 H'FFFF2004 8, 16, 32 FIFO control register 4 SSIFCR_4 R/W H'00000000 H'FFFF2010 8, 16, 32 FIFO status register SSIFSR_4 4 R/(W)*2 H'00010000 H'FFFF2014 8, 16, 32 Transmit FIFO data SSIFTDR_4 register 4 W Undefined H'FFFF2018 32 Receive FIFO data register 4 R Undefined H'FFFF201C 32 TDM mode register SSITDMR_4 4 R/W H'00000000 H'FFFF2020 8, 16, 32 Control register 5 R/W H'00000000 H'FFFF2800 8, 16, 32 SSIFRDR_4 SSICR_5 1 Status register 5 SSISR_5 R/W* H'02000013 H'FFFF2804 8, 16, 32 FIFO control register 5 SSIFCR_5 R/W H'00000000 H'FFFF2810 8, 16, 32 FIFO status register SSIFSR_5 5 R/(W)*2 H'00010000 H'FFFF2814 8, 16, 32 Transmit FIFO data SSIFTDR_5 register 5 W Undefined H'FFFF2818 32 Receive FIFO data register 5 R Undefined H'FFFF281C 32 R/W H'00000000 H'FFFF2820 8, 16, 32 SSIFRDR_5 TDM mode register SSITDMR_5 5 Notes: 1. Although bits 29 to 26 in these registers can be read from or written to, bits other than these are read-only. For details, refer to section 21.3.2, Status Register (SSISR). 2. To bits 16 and 0 in these registers, only 0 can be written to clear the flags. Other bits are read-only. For details, refer to section 21.3.6, FIFO Status Register (SSIFSR). Page 1068 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.3.1 Section 21 Serial Sound Interface Control Register (SSICR) SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and sets operating mode. Bit: 31 Initial value: R/W: 30 29 28 - CKS 0 R 0 R/W 0 R/W 14 13 Bit: 15 SCKD SWSD SCKP Initial value: 0 R/W: R/W 27 26 TUIEN TOIEN RUIEN ROIEN 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 25 24 IIEN - 0 R/W 0 R 0 R/W 7 12 11 10 9 8 SWSP SPDP SDTA PDTA DEL 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 23 22 21 CHNL[1:0] 20 0 R/W 0 R/W 0 R/W 6 5 4 CKDV[3:0] 0 R/W Bit Bit Name Initial Value R/W Description 31  0 R Reserved 0 R/W 19 18 DWL[2:0] 0 R/W 0 R/W 17 16 SWL[2:0] 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 MUEN - TEN REN 0 R/W 0 R 0 R/W 0 R/W The read value is undefined. The write value should always be 0. 30 CKS 0 R/W Oversampling Clock Select Selects the clock source for oversampling. 0: AUDIO_X1 input 1: AUDIO_CLK input 29 TUIEN 0 R/W Transmit Underflow Interrupt Enable 0: Disables an underflow interrupt. 1: Enables an underflow interrupt. 28 TOIEN 0 R/W Transmit Overflow Interrupt Enable 0: Disables an overflow interrupt. 1: Enables an overflow interrupt. 27 RUIEN 0 R/W Receive Underflow Interrupt Enable 0: Disables an underflow interrupt. 1: Enables an underflow interrupt. 26 ROIEN 0 R/W Receive Overflow Interrupt Enable 0: Disables an overflow interrupt. 1: Enables an overflow interrupt. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1069 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 25 IIEN 0 R/W Idle Mode Interrupt Enable 0: Disables an idle mode interrupt. 1: Enables an idle mode interrupt. 24  0 R Reserved The read value is undefined. The write value should always be 0. 23, 22 CHNL[1:0] 00 R/W Channels [When TDM = 0] These bits show the number of channels in each system word. 00: Having one channel per system word 01: Having two channels per system word 10: Having three channels per system word 11: Having four channels per system word [When TDM = 1] These bits show the number of system words in each TDM frame. 00: Setting prohibited 01: Having four system words per TDM frame 10: Having six system words per TDM frame 11: Having eight system words per TDM frame Page 1070 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 21 to 19 DWL[2:0] 000 R/W Data Word Length These bits indicate the number of bits in a data word. 000: 8 bits 001: 16 bits 010: 18 bits 011: 20 bits 100: 22 bits 101: 24 bits 110: 32 bits 111: Setting prohibited 18 to 16 SWL[2:0] 000 R/W System Word Length These bits indicate the number of bits in a system word. 000: 8 bits 001: 16 bits 010: 24 bits 011: 32 bits 100: 48 bits 101: 64 bits 110: 128 bits 111: 256 bits 15 SCKD 0 R/W Serial Bit Clock Direction 0: Serial bit clock is input, slave mode. 1: Serial bit clock is output, master mode. Note: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited. 14 SWSD 0 R/W Serial WS Direction 0: Serial word select is input, slave mode. 1: Serial word select is output, master mode. Note: Only the following settings are allowed: (SCKD, SWSD) = (0,0) and (1,1). Other settings are prohibited. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1071 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 13 SCKP 0 R/W Serial Bit Clock Polarity 0: SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge). 1: SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge). 12 SWSP 0 R/W SCKP =0 SCKP = 1 SSIDATA input sampling timing at the time SSISCK rising SSISCK falling of reception edge edge SSIDATA output change timing at the time SSISCK falling SSISCK rising of transmission edge edge SSIWS input sampling timing at the time of SSISCK rising SSISCK falling slave mode (SWSD = 0) edge edge SSIWS output change timing at the time of SSISCK falling SSISCK rising master mode (SWSD = 1) edge edge Serial WS Polarity [When TDM = 0] 0: SSIWS is low for 1st channel, high for 2nd channel. 1: SSIWS is high for 1st channel, low for 2nd channel. [When TDM = 1] 0: SSIWS is high only for system word 1 period, low for other periods. 1: Setting prohibited 11 SPDP 0 R/W Serial Padding Polarity 0: Padding bits are low. 1: Padding bits are high. Page 1072 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 10 SDTA 0 R/W Serial Data Alignment 0: Transmitting and receiving in the order of serial data and padding bits 1: Transmitting and receiving in the order of padding bits and serial data 9 PDTA 0 R/W Parallel Data Alignment When the data word length is 32 bits, this configuration field has no meaning. This bit applies to SSIRDR in receive mode and SSITDR in transmit mode. When data word length is 8 or 16 bits: 0: The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits. 1: The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits. When data word length is 18, 20, 22, or 24 bits: 0: Parallel data (SSITDR, SSIRDR) is left-aligned. 1: Parallel data (SSITDR, SSIRDR) is right-aligned.  PDTA = 0 DWL[2:0] SSITDR/SSIRDR[31:0] 31 000 24 23 4th word 16 15 3rd word 31 001 31 0 1st word Invalid 31 12 11 0 Invalid Valid 31 100 10 9 Valid 0 Invalid 31 101 8 7 0 Invalid Valid 31 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 14 13 Valid 011 0 1st word 16 15 2nd word 010 110 8 7 2nd word 0 Valid Page 1073 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 9 PDTA 0 R/W  PDTA = 1 DWL[2:0] SSITDR/SSIRDR[31:0] 31 000 24 23 1st word 16 15 2nd word 31 001 8 7 16 15 0 1st word 2nd word 31 010 0 18 17 Valid Invalid 31 011 20 19 0 Valid Invalid 31 100 22 21 0 Valid Invalid 31 101 0 4th word 3rd word 24 23 0 Valid Invalid 31 110 8 DEL 0 R/W 0 Valid Serial Data Delay 0: 1 clock cycle delay between SSIWS and SSIDATA 1: No delay between SSIWS and SSIDATA Page 1074 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 7 to 4 CKDV[3:0] 0000 R/W Serial Oversampling Clock Division Ratio Sets the ratio between the oversampling clock (AUDIO) and the serial bit clock. When the SCKD bit is 0, the setting of these bits is ignored. The serial bit clock is used in the shift register and is supplied from the SSISCK pin. 0000: AUDIO 0001: AUDIO/2 0010: AUDIO/4 0011: AUDIO/8 0100: AUDIO/16 0101: AUDIO/32 0110: AUDIO/64 0111: AUDIO/128 1000: AUDIO/6 1001: AUDIO/12* 1010: AUDIO/24 1011: AUDIO/48* 1100: AUDIO/96* 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Note: * These bits are only settable for channel 0. Setting these bits in the registers for channels 1 to 5 is prohibited. 3 MUEN 0 R/W Mute Enable 0: This module is not muted. 1: This module is muted. Note: When this module is muted, the value of outputting serial data is re-written to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1075 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 2  0 R Reserved The read value is undefined. The write value should always be 0. 1 TEN 0 R/W Transmit Enable 0: Disables the transmit operation. 1: Enables the transmit operation. 0 REN 0 R/W Receive Enable 0: Disables the receive operation. 1: Enables the receive operation. Page 1076 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.3.2 Section 21 Serial Sound Interface Status Register (SSISR) SSISR consists of status flags indicating the operational status of this module and bits indicating the current channel numbers and word numbers. Bit: 31 30 - - 29 28 27 26 TUIRQ TOIRQ RUIRQ ROIRQ Initial value: UndefinedUndefined 0 0 0 0 R/W: R R R/(W)* R/(W)* R/(W)* R/(W)* Bit: 25 24 23 22 21 20 19 18 17 16 IIRQ - - - - - - - - - 1 R Undefined Undefined UndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined R R 15 14 13 12 11 10 9 8 7 - - - - - - - - - Initial value: UndefinedUndefinedUndefinedUndefined UndefinedUndefinedUndefinedUndefinedUndefined R/W: R R R R R R R R R R R 6 5 TCHNO[1:0] 0 R 0 R R 4 TSWNO 1 R R R 3 2 RCHNO[1:0] 0 R 0 R R R 1 0 RSWNO IDST 1 R 1 R Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored. Bit Bit Name Initial Value 31, 30  Undefined R 29 TUIRQ 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R/W Description Reserved The read value is undefined. The write value should always be 0. R/(W)* Transmit Underflow Error Interrupt Status Flag This status flag indicates that transmit data was supplied at a lower rate than was required. This bit is set to 1 regardless of the value of the TUIEN bit and can be cleared by writing 0 to this bit. If TUIRQ = 1 and TUIEN = 1, an interrupt occurs. If TUIRQ = 1, SSITDR did not have data written to it before it was required for transmission. This will lead to the same data being transmitted once more and a potential corruption of multi-channel data. As a result, this module will output erroneous data. Note: When an underflow error occurs, the current data in the data buffer of this module is transmitted until the next data is written. Page 1077 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W 28 TOIRQ 0 R/(W)* Transmit Overflow Error Interrupt Status Flag Description This status flag indicates that transmit data was supplied at a higher rate than was required. This bit is set to 1 regardless of the value of the TOIEN bit and can be cleared by writing 0 to this bit. If TOIRQ = 1 and TOIEN = 1, an interrupt occurs. If TOIRQ = 1, SSIFTDR had data written to it while the transmit FIFO is full (TDC = H'8). This will lead to the loss of data and a potential corruption of multi-channel data. 27 RUIRQ 0 R/(W)* Receive Underflow Error Interrupt Status Flag This status flag indicates that receive data was supplied at a lower rate than was required. This bit is set to 1 regardless of the value of the RUIEN bit and can be cleared by writing 0 to this bit. If RUIRQ = 1 and RUIEN = 1, an interrupt occurs. If RUIRQ = 1, SSIFRDR was read while the receive FIFO is empty (RDC = H'0).This can cause invalid receive data to be stored, which may lead to corruption of multi-channel data. 26 ROIRQ 0 R/(W)* Receive Overflow Error Interrupt Status Flag This status flag indicates that receive data was supplied at a higher rate than was required. This bit is set to 1 regardless of the value of the ROIEN bit and can be cleared by writing 0 to this bit. If ROIRQ = 1 and ROIEN = 1, an interrupt occurs. If ROIRQ = 1, SSIRDR was not read before there was new unread data written to it. This will lead to the loss of data and a potential corruption of multi-channel data. Note: When an overflow error occurs, the current data in the data buffer of this module is overwritten by the next incoming data from the SSI interface. Page 1078 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 25 IIRQ 1 R Idle Mode Interrupt Status Flag This interrupt status flag indicates whether this module is in idle state. This bit is set regardless of the value of the IIEN bit to allow polling. The interrupt can be masked by clearing IIEN, but cannot be cleared by writing to this bit. If IIRQ = 1 and IIEN = 1, an interrupt occurs. 0: This module is not in idle state. 1: This module is in idle state. 24 to 7  Undefined R Reserved The read value is undefined. The write value should always be 0. 6, 5 TCHNO [1:0] 00 R Transmit Channel Number These bits show the current channel number. These bits indicate which channel is required to be written to SSITDR. This value will change as the data is copied to the shift register, regardless of whether the data is written to SSITDR. When TDM or CONT is 1, these bits cannot be used. 4 TSWNO 1 R Transmit Serial Word Number This status bit indicates the current word number. This bit indicates which system word is required to be written to SSITDR. This value will change as the data is copied to the shift register, regardless of whether the data is written to SSITDR. When TDM or CONT is 1, this bit cannot be used. 3, 2 RCHNO [1:0] 00 R Receive Channel Number These bits show the current channel number. These bits indicate which channel the data in SSIRDR currently represents. This value will change as the data in SSIRDR is updated from the shift register. When TDM or CONT is 1, these bits cannot be used. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1079 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 1 RSWNO 1 R Receive Serial Word Number This status bit indicates the current word number. This bit indicates which system word the data in SSIRDR currently represents. This value will change as the data in SSIRDR is updated from the shift register, regardless of whether SSIRDR has been read. When TDM or CONT is 1, this bit cannot be used. 0 IDST 1 R Idle Mode Status Flag This status flag indicates that the serial bus activity has stopped. This bit is cleared to 0 if the serial bus are currently active while TEN = 1 or REN = 1. This bit is automatically set to 1 if both TEN and REN are cleared to 0 and the current system word communication is completed. Note: If the external device stops the serial bus clock before the current system word is completed, this bit is not set. Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored. Page 1080 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.3.3 Section 21 Serial Sound Interface Transmit Data Register (SSITDR) SSITDR is a 32-bit register that stores data to be transmitted. The data for transmission to be stored to SSITDR is automatically transferred from the transmit FIFO data register. Data written to this register is transferred to the shift register upon transmission request. If the data word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR. The CPU cannot read or write data from/to SSITDR. Bit: 31 Initial value: R/W: 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bit: 15 Initial value: R/W: 21.3.4 Receive Data Register (SSIRDR) SSIRDR is a 32-bit register that stores received data. The received data stored in SSIRDR is automatically transferred to the receive FIFO data register. Data in this register is transferred from the shift register each time data word is received. If the data word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit in SSICR. The CPU cannot read or write data from/to SSIRDR. Bit: 31 Initial value: R/W: 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Bit: 15 Initial value: R/W: R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1081 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 21.3.5 FIFO Control Register (SSIFCR) SSIFCR is a readable/writable 32-bit register that specifies the data trigger numbers and enables or disables FIFO data reset and interrupt requests for the transmit FIFO data register and the receive FIFO data register. SSIFCR can always be read or written by the CPU. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 6 5 4 1 0 Initial value: R/W: 14 13 12 11 10 9 8 7 - - - - - - - - TTRG[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved 0 R/W 0 R/W RTRG[1:0] 0 R/W 0 R/W 3 2 TIE RIE 0 R/W 0 R/W TFRST RFRST 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7, 6 TTRG[1:0] 00 R/W Transmit Data Trigger Number These bits specify the number of transmit data bytes in the FIFO (transmit trigger number) at which the TDE flag in the FIFO status register (SSIFSR) is set during transmission. The TDE flag is set to 1 when the number of transmit data bytes in the transmit FIFO data register (SSIFTDR) has become equal to or less than the set trigger number shown below. 00: 7 (1)* 01: 6 (2)* 10: 4 (4)* 11: 2 (6)* Note: * The values in parenthesis are the number of empty stages in SSIFTDR at which the TDE flag is set. Page 1082 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 5, 4 RTRG[1:0] 00 R/W Receive Data Trigger Number These bits specify the number of received data bytes in the FIFO (receive trigger number) at which the RDF flag in the FIFO status register (SSIFSR) is set during reception. The RDF flag is set to 1 when the number of received data bytes in the receive FIFO data register (SSIFRDR) has become equal to or greater than the set trigger number shown below. 00: 1 01: 2 10: 4 11: 6 3 TIE 0 R/W Transmit Interrupt Enable Enables or disables generation of transmit data empty interrupt (TXI) requests in the following situation: during transmission, the data for transmission in the transmit FIFO data register (SSIFTDR) is transferred to the transmit data register (SSITDR) and the number of data bytes in the transmit FIFO data register has become less than the set transmit trigger number; and thus the TDE flag in the FIFO status register (SSIFSR) is set to 1. 0: Transmit data empty interrupt (TXI) request is disabled 1: Transmit data empty interrupt (TXI) request is enabled* Note: * TXI can be cleared by clearing either the TDE flag (see the description of the TDE bit for details) or TIE bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1083 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W Description 2 RIE 0 R/W Receive Interrupt Enable Enables or disables generation of receive data full interrupt (RXI) requests when the RDF flag in the FIFO status register (SSIFSR) is set to 1 during reception. 0: Receive data full interrupt (RXI) request is disabled 1: Receive data full interrupt (RXI) request is enabled* Note: * RXI can be cleared by clearing either the RDF flag (see the description of the RDF bit for details) or RIE bit. 1 TFRST 0 R/W 0 RFRST 0 R/W Page 1084 of 3092 Transmit FIFO Data Register Reset Invalidates the data in the transmit FIFO data register (SSIFTDR) to reset the FIFO to an empty state. 0: Reset is disabled. 1: Reset is enabled. Note: FIFO is reset at a power-on reset. Receive FIFO Data Register Reset Invalidates the data in the receive FIFO data register (SSIFRDR) to reset the FIFO to an empty state. 0: Reset is disabled 1: Reset is enabled Note: FIFO is reset at a power-on reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.3.6 Section 21 Serial Sound Interface FIFO Status Register (SSIFSR) SSIFSR consists of status flags indicating the operating status of the transmit FIFO data register and the receive FIFO data register. Bit: 31 30 29 28 - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 11 10 9 Initial value: R/W: 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - TDE 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W)* 8 7 6 5 4 3 2 1 0 - - - - - - - RDF 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W)* TDC[3:0] 14 13 12 - - - - Initial value: R/W: 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 28  All 0 R Reserved RDC[3:0] 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 27 to 24 TDC[3:0] 0000 R Number of Data Bytes Stored in SSIFTDR TDC[3:0] = H'0 indicates no data for transmission. TDC[3:0] = H'8 indicates that 32 bytes of data for transmission is stored in SSIFTDR. 23 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 TDE 1 R/(W)* Transmit Data Empty Indicates that, when the FIFO is operating for transmission, the data for transmission in the transmit FIFO data register (SSIFTDR) is transferred to the transmit data register (SSITDR), the number of data bytes in the FIFO data register has become less than the transmit trigger number specified by TTRG[1:0] in the FIFO control register (SSIFCR), and thus writing of data transmission to SSIFTDR has been enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1085 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value 16 TDE 1 R/W Description R/(W)* 0: Number of data bytes for transmission in SSIFTDR is greater than the set transmit trigger number. [Clearing conditions]  0 is written to TDE after data of the number of bytes larger than the set transmit trigger number is written to SSIFTDR.  The direct memory access controller is activated by transmit data empty (TXI) interrupt, and data of the number of bytes larger than the set transmit trigger number is written to SSIFTDR. 1: Number of data bytes for transmission in SSIFTDR is equal to or less than the set transmit trigger number.* [Setting conditions]   Power-on reset Number of transmission data bytes to be stored in SSIFTDR has become equal to or less than the set transmit trigger number. Note: * Since SSIFTDR is an 8-stage FIFO register, the amount of data that can be written to it while TDE = 1 is "8 – transmit trigger number to be specified" bytes at maximum. Writing more data will be ignored. The number of data bytes in SSIFTDR is indicated in the TDC bits in SSIFSR. 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 8 RDC[3:0] 0000 R Number of Data Bytes Stored in SSIFRDR RDC[3:0] = H'0 indicates no received data. RDC[3:0] = H'8 indicates that 32 bytes of received data is stored in SSIFRDR. 7 to 1  All 0 R Reserved This bit is always read as 0. The write value should always be 0. Page 1086 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Bit Bit Name Initial Value R/W 0 RDF 0 R/(W)* Receive Data Full Description Indicates that, when the FIFO is operating for reception, the received data is transferred to the receive FIFO data register (SSIFRDR) and the number of data bytes in the FIFO data register has become greater than the receive trigger number specified by RTRG[1:0] in the FIFO control register (SSIFCR). 0: Number of received data bytes in SSIFRDR is less than the set receive trigger number. [Clearing conditions]   Power-on reset 0 is written to RDF after the receive FIFO is empty with writing 1 to RFRST.  0 is written to RDF after data is read from SSIFRDR until the number of data bytes in SSIFRDR becomes less than the set receive trigger number.  The direct memory access controller is activated by receive data full (RXI) interrupt, and data is read from SSIFRDR until the number of data bytes in SSIFRDR becomes less than the set receive trigger number. 1: Number of received data bytes in SSIFRDR is equal to or greater than the set receive trigger number. [Setting condition]  Data of the number of bytes that is equal to or greater than the set receive trigger number is stored in SSIFRDR.* Note: * Since SSIFRDR is an 8-stage FIFO register, the amount of data that can be read from it while RDF = 1 is the set receive trigger number of bytes at maximum. Continuing to read data from SSIFRDR after reading all the data will result in undefined data to be read. The number of data bytes in SSIFRDR is indicated in the RDC bits in SSIFSR. Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1087 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 21.3.7 Transmit FIFO Data Register (SSIFTDR) SSIFTDR is a FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. On detecting that the transmit data register (SSITDR) is empty, this module transfers the data for transmission written to SSIFTDR to SSITDR to start serial transmission, which can continue until SSIFTDR becomes empty. SSIFTDR can be written to by the CPU at any time. Note that when SSIFTDR is full of data (32 bytes), the next data cannot be written to it. If writing is attempted, it will be ignored and an overflow occurs. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W W W W W W W W W W W W W W W W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W W W W W W W W W W W W W W W Initial value: R/W: Initial value: R/W: W Note: * Not writable during reception. Page 1088 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.3.8 Section 21 Serial Sound Interface Receive FIFO Data Register (SSIFRDR) SSIFRDR is a FIFO register consisting of eight stages of 32-bit registers for storing serially received data. When four bytes of data have been received, this module transfers the received data in the receive data register (SSIRDR) to SSIFRDR to complete reception operation. Reception can continue until 32 bytes of data have been stored to SSIFRDR. SSIFRDR can be read by the CPU but cannot be written to. Note that when SSIFRDR is read when it stores no received data, undefined values will be read and a receive underflow occurs. After SSIFRDR becomes full of received data, the data received thereafter will be lost and a receive overflow occurs. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R Initial value: R/W: Initial value: R/W: R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1089 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 21.3.9 TDM Mode Register (SSITDMR) SSITDMR is a readable/writable 32-bit register that enables or disables TDM mode and WS continue mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 Initial value: R/W: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - CONT - - - - - - - TDM Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 31 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 CONT 0 R/W WS Continue Mode 0: Disables WS continue mode. 1: Enables WS continue mode. Note: 7 to 1  All 0 R This bit can be set only in master mode (SCKD = 1 and SWSD = 1) Reserved These bits are always read as 0. The write value should always be 0. 0 TDM 0 R/W TDM Mode 0: Disables TDM mode. 1: Enables TDM mode. Page 1090 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.4 Operation Description 21.4.1 Bus Format Section 21 Serial Sound Interface This module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus format can be selected from one of the 12 major modes shown in table 21.3. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1091 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 0 NonCompression Slave Transceiver 1 1 0 0 0 NonCompression Master Receiver 0 1 1 1 0 NonCompression Master Transmitter 1 0 1 1 0 NonCompression Master Transceiver 1 1 1 1 0 TDM Slave Receiver 0 1 0 0 1 0 TDM Slave Transmitter 1 0 0 0 1 0 TDM Slave Transceiver 1 1 0 0 1 0 TDM Master Receiver 0 1 1 1 1 0 TDM Master Transmitter 1 0 1 1 1 0 TDM Master Transceiver 1 1 1 1 1 0 Page 1092 of 3092 CHNL[1:0] 0 DWL[2:0] 0 SWL[2:0] 0 SCKP 1 SPDP NonCompression Slave Transmitter SDTA Control Bits PDTA 0 SWSP 0 CONT 0 DEL RUIEN MUEN ROIEN TDM TUIEN SWSD 1 IIEN SCKD Non0 Compression Slave Receiver TEN REN TOIEN Table 21.3 Bus Format for SSIF Module Configuration Bits Configuration Bits R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.4.2 Section 21 Serial Sound Interface Non-Compressed Modes The non-compressed modes support all serial audio streams split into channels. It supports the I2S compatible format as well as many more variants on these modes. (1) Slave Receiver This mode allows the module to receive serial data from another device. The clock and word select signal used for the serial data stream is also supplied from an external device. If these signals do not conform to the format specified in the configuration fields of this module, operation is not guaranteed. (2) Slave Transmitter This mode allows the module to transmit serial data to another device. The clock and word select signal used for the serial data stream is also supplied from an external device. If these signals do not conform to the format specified in the configuration fields of this module, operation is not guaranteed. (3) Slave Transceiver This mode allows serial data transmission and reception between this module and another device. The clock and word select signal used for the serial data stream is also supplied from an external device. If these signals do not conform to the format specified in the configuration fields of this module, operation is not guaranteed. (4) Master Receiver This mode allows the module to receive serial data from another device. The clock and word select signals are internally derived from the oversampling clock. The format of these signals is defined in the configuration fields of this module. If the incoming data does not follow the configured format, operation is not guaranteed. (5) Master Transmitter This mode allows the module to transmit serial data to another device. The clock and word select signals are internally derived from the oversampling clock. The format of these signals is defined in the configuration fields of this module. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1093 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface (6) Master Transceiver This mode allows serial data transmission and reception between this module and another device. The clock and word select signals are internally derived from the oversampling clock. The format of these signals is defined in the configuration fields of this module. (7) Operating Setting Related to Word Length All bits related to the SSICR's word length are valid in non-compressed modes. There are many configurations this module supports, but some of the combinations are shown below for the I2S compatible format, MSB-first and left-aligned format, and MSB-first and right-aligned format.  I2S Compatible Format Figures 21.2 and 21.3 demonstrate the I2S compatible format both without and with padding. Padding occurs when the data word length is smaller than the system word length. SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00 System word length = data word length SSISCK SSIWS SSIDATA LSB +1 prev. sample MSB LSB +1 LSB MSB System word 1 = data word 1 LSB next sample System word 2 = data word 2 Figure 21.2 I2S Compatible Format (without Padding) SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length SSISCK SSIWS SSIDATA MSB LSB Data word 1 System word 1 MSB Padding LSB Next Data word 2 Padding System word 2 Figure 21.3 I2S Compatible Format (with Padding) Page 1094 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Figure 21.4 shows the MSB-first and left-aligned format and figure 21.5 shows the MSB-first and right-aligned format.  MSB-first and Left-aligned Format SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length SSISCK SSIWS SSIDATA MSB LSB MSB Data word 1 Padding LSB Next Data word 2 System word 1 Padding System word 2 Figure 21.4 MSB-first and Left-aligned Format (Transmitted and Received in the Order of Serial Data and Padding Bits)  MSB-first and Right-aligned Format SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 1 System word length > data word length SSISCK SSIWS SSIDATA Prev. MSB Padding LSB Data word 1 System word 1 MSB Padding LSB Data word 2 System word 2 Figure 21.5 MSB-first and Right-aligned Format (Transmitted and Received in the Order of Padding Bits and Serial Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1095 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface (8) Multi-channel Formats Some devices extend the definition of the I2S bus specification and allow more than 2 channels to be transferred within two system words. This module supports the transfer of 4, 6, and 8 channels by using the CHNL, SWL and DWL bits only when the system word length (SWL) is greater than or equal to the data word length (DWL) multiplied by channels (CHNL). Table 21.4 shows the number of padding bits for each of the valid setting. If setting is not valid, "" is indicated instead of a number. Table 21.4 The Number of Padding Bits for Each Valid Setting Padding Bits per System DWL[2:0] 000 Word 001 010 011 100 101 110 Decoded Channels CHNL per System SWL Word [2:0] [1:0] Decoded Word Length 8 16 18 20 22 24 32 000 8 0       001 16 8 0      010 24 16 8 6 4 2 0  011 32 24 16 14 12 10 8 0 100 48 40 32 30 28 26 24 16 101 64 56 48 46 44 42 40 32 110 128 120 112 110 108 106 104 96 111 256 248 240 238 236 234 232 224 00 01 1 2 Page 1096 of 3092 000 8        001 16 0       010 24 8       011 32 16 0      100 48 32 16 12 8 4 0  101 64 48 32 28 24 20 16 0 110 128 112 96 92 88 84 80 64 111 256 240 224 220 216 212 208 192 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Padding Bits per System DWL[2:0] 000 Word CHNL [1:0] Decoded Channels Decoded per System SWL Word Word [2:0] Length 8 10 3 11 4 001 010 011 100 101 110 16 18 20 22 24 32 000 8        001 16        010 24 0       011 32 8       100 48 24 0      101 64 40 16 10 4    110 128 104 80 74 68 62 56 32 111 256 232 208 202 196 190 184 160 000 8        001 16        010 24        011 32 0       100 48 16       101 64 32 0      110 128 96 64 56 48 40 32 0 111 256 224 192 184 176 168 160 128 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1097 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface When this module acts as a transmitter, each word written to SSITDR is transmitted to the serial audio bus in the order they are written. When this module acts as a receiver, each word received by the serial audio bus is read in the order received from the SSIRDR register. Figures 21.6 to 21.8 show how the data on 4, 6, and 8 channels are transferred to the serial audio bus. Note that there are no padding bits in the first example, the second example is left-aligned and the third is right-aligned. The other conditions in these examples have been selected arbitrarily. SCKP = 0, SWSP = 0, DEL = 0, CHNL = 01, SPDP = don't care, SDTA = don't care System word length = data word length × 2 SSISCK SSIWS SSIDATA LSB MSB LSB MSB Data word 1 LSB MSB Data word 2 System word 1 LSB MSB Data word 3 LSB MSB Data word 4 LSB MSB Data word 1 LSB MSB Data word 2 Data word 3 System word 1 System word 2 LSB MSB LSB MSB Data word 4 System word 2 Figure 21.6 Multi-Channel Format (4 Channels Without Padding) SCKP = 0, SWSP = 0, DEL = 0, CHNL = 10, SPDP = 1, SDTA = 0 System word length = data word length × 3 SSISCK SSIWS LSB MSB Data word 1 LSB MSB Data word 2 System word 1 Data word 3 LSB MSB LSB MSB Data word 4 LSB MSB Data word 5 LSB Data word 6 MSB Padding MSB Padding SSIDATA System word 2 Figure 21.7 Multi-Channel Format (6 Channels with High Padding) Page 1098 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface SCKP = 0, SWSP = 0, DEL = 0, CHNL = 11, SPDP = 0, SDTA = 1 System word length = data word length × 4 SSISCK SSIWS Padding MSB LSB MSB LSB MSB Data word 2 Data word 1 LSB MSB Data word 3 LSB Data word 4 MSB Padding SSIDATA LSB MSB Data word 5 System word 1 LSB MSB Data word 6 LSB MSB Data word 7 LSB Data word 8 System word 2 Figure 21.8 Multi-Channel Format (8 Channels; Transmitting and Receiving in the Order of Serial Data and Padding Bits; with Padding) (9) Bit Setting Configuration Format Several more configuration bits in non-compressed mode are shown below. These bits are not mutually exclusive, but some combinations may not be useful for any other device. These configuration bits are described below with reference to figure 21.9. SWL = 6 bits (not attainable in SSI module, demonstration only) DWL = 4 bits (not attainable in SSI module, demonstration only) CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0 4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus. SSISCK 1st channel SSIWS SSIDATA TD28 0 0 TD31 TD30 TD29 TD28 2nd channel 0 0 TD31 TD30 TD29 TD28 0 0 TD31 Key for this and following diagrams: Arrow head indicates sampling point of receiver TDn Bit n in SSITDR 0 means a low level on the serial bus (padding or mute) 1 means a high level on the serial bus (padding) Figure 21.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1099 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface Figure 21.9 uses a system word length of 6 bits and a data word length of 4 bits. These settings are not possible with this module but are used only for clarification of the other configuration bits.  Inverted Clock As basic sample format configuration except SCKP = 1 SSISCK 1st Channel SSIWS SSIDATA TD28 0 0 TD31 TD30 TD29 TD28 2nd Channel 0 0 TD31 TD30 TD29 TD28 0 0 TD31 0 0 TD31 1 1 TD31 Figure 21.10 Inverted Clock  Inverted Word Select As basic sample format configuration except SWSP = 1 SSISCK SSIWS SSIDATA 1st Channel TD28 0 0 TD31 TD30 TD29 TD28 2nd Channel 0 0 TD31 TD30 TD29 TD28 Figure 21.11 Inverted Word Select  Inverted Padding Polarity As basic sample format configuration except SPDP = 1 SSISCK SSIWS SSIDATA TD28 2nd Channel 1st Channel 1 1 TD31 TD30 TD29 TD28 1 1 TD31 TD30 TD29 TD28 Figure 21.12 Inverted Padding Polarity Page 1100 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface  Transmitting and Receiving in the Order of Padding Bits and Serial Data; with Delay As basic sample format configuration except SDTA = 1 SSISCK SSIWS 1st Channel SSIDATA TD30 TD29 TD28 0 0 2nd Channel TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 Figure 21.13 Transmitting and Receiving in the Order of Padding Bits and Serial Data; with Delay  Transmitting and Receiving in the Order of Padding Bits and Serial Data; without Delay As basic sample format configuration except SDTA = 1 and DEL = 1 SSISCK SSIWS SSIDATA 1st Channel TD29 TD28 0 0 2nd Channel TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 Figure 21.14 Transmitting and Receiving in the Order of Padding Bits and Serial Data; without Delay  Transmitting and Receiving in the Order of Serial Data and Padding Bits; without Delay As basic sample format configuration except DEL = 1 SSISCK SSIWS SSIDATA 2nd Channel 1st Channel 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 Figure 21.15 Transmitting and Receiving in the Order of Serial Data and Padding Bits; without Delay R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1101 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface  Parallel Right-Aligned with Delay As basic sample format configuration except PDTA = 1 SSISCK SSIWS SSIDATA 2nd Channel 1st Channel TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3 TD2 TD1 TD0 0 0 TD3 0 0 0 Figure 21.16 Parallel Right-Aligned with Delay  Mute Enabled As basic sample format configuration except MUEN = 1 (TD data ignored) SSISCK SSIWS SSIDATA 2nd Channel 1st Channel 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21.17 Mute Enabled Page 1102 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.4.3 Section 21 Serial Sound Interface TDM Mode TDM mode is provided to enable connection to multi-channel devices for TDM. This mode can be set using the TDM bit in the TDM mode register (SSITDMR). In this mode, the SSIWS signal is high only for system word 1 period and low for the other periods. The pulse produced on the SSIWS signal is defined as SYNC pulse. Note that the SYNC pulse always has the positive polarity (high only for system word 1 period). Figures 21.18 and 21.19 show the TDM formats without and with padding, respectively. SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = don't care, SDTA = don't care, TDM = 1 System word length = data word length SSISCK SSIWS SSIDATA LSB MSB LSB Data word 1 = system word 1 MSB LSB MSB Data word 2 = system word 2 LSB MSB Data word 3 = system word 3 LSB Data word 4 = system word 4 MSB LSB MSB Data word 5 = system word 5 LSB MSB Data word 6 = system word 6 TDM frame Figure 21.18 TDM Format (6 system words, no padding) SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = 1, SDTA = 0, TDM = 1 System word length > data word length SSISCK SSIWS System word 1 Data word 2 System word 2 MSB LSB MSB Data word 3 System word 3 LSB Data word 4 System word 4 MSB LSB Data word 5 System word 5 MSB LSB Data word 6 MSB Padding LSB Padding Data word 1 MSB Padding LSB Padding MSB Padding SSIDATA System word 6 TDM frame Figure 21.19 TDM Format (6 system words, with padding) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1103 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 21.4.4 WS Continue Mode In WS continue mode, the SSIWS signal continues to be output irrespective whether data transfer is enabled or disabled. This mode can be set using the CONT bit in the CONT bit in the TDM mode register (SSITDMR). With this mode enabled, the SSIWS signal does not stop but continues operating even if TEN and REN bits in the control register (SSICR) are both set to 0 (transfer disabled). With this mode disabled, the SSIWS signal stops if TEN and REN bits are both set to 0. Figures 21.20 and 21.21 show the operations with WS continue mode enabled and disabled, respectively. Data transfer disabled period (TEN = 0, REN = 0) SSISCK SSIWS SSIDATA LSB MSB LSB MSB LSB MSB MSB LSB MSB Figure 21.20 WS Continue Mode Enabled Data transfer disabled period (TEN = 0, REN = 0) SSISCK SSIWS SSIDATA LSB MSB LSB Figure 21.21 WS Continue Mode Disabled Page 1104 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.4.5 Section 21 Serial Sound Interface Operation Modes There are three modes of operation: configuration, enabled and disabled. Figure 21.22 shows how the module enters each of these modes. Reset Module configuration (after reset) TEN = 1 or REN = 1 (IDST = 0) TEN = 0 and REN = 0 (IDST = 1) Module disabled (waiting until bus inactive) TEN = 0 and REN = 0 (IDST = 0) Module enabled (normal tx/rx) Figure 21.22 Operation Modes (1) Configuration Mode This mode is entered after the module is released from reset. All required configuration fields in the control register should be defined in this mode, before this module is enabled by setting the TEN and REN bits. Setting the TEN and REN bits causes the module to enter the module enabled mode. (2) Module Enabled Mode Operation of the module in this mode is dependent on the operation mode selected. For details, refer to section 21.4.6, Transmit Operation and section 21.4.7, Receive Operation, below. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1105 of 3092 Section 21 Serial Sound Interface 21.4.6 SH7268 Group, SH7269 Group Transmit Operation Transmission can be controlled either by DMA transfer or interrupt. DMA control is preferred to reduce the processor load. In DMA control mode, the processor will only receive interrupts if there is an underflow or overflow of data or if the DMA transfer has been completed. The alternative method is using the interrupts that this module generates to supply data as required. When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit indicates that the module is in the idle state. Figure 21.23 shows the transmit operation in DMA control mode, and figure 21.24 shows the transmit operation in interrupt control mode. Note: * Input clock from the SSISCK pin when SCKD = 0. Oversampling clock when SCKD = 1. Page 1106 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 21 Serial Sound Interface Transmission Using Direct Memory Access Controller Start Define SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL Release from reset, set SSICR configuration bits. Set up direct memory access controller for direct memory access. Enable error interrupt, enable transmit interrupt, enable transmit operation. TUIEN = 1, TOIEN = 1, TIE = 1, TEN = 1 Wait for an interrupt. Error interrupt? Yes No No End of DMA transfer? Yes Yes More data to be sent? No Disable transmit operation*2, disable direct memory access controller, disable an error interrupt, enable an idle interrupt. TEN = 0, TUIEN = 0, TOIEN = 0, IIEN = 1, TIE = 0 Wait for an idle interrupt from this module End*1 Notes: 1. If an error interrupt (underflow/overflow) occurs, go back to the start in the flowchart again. 2. When restarting transmission after disabling transmit operation (TEN = 0) while WS continue mode is disabled, first apply a software reset before going back to start in the flowchart. Figure 21.23 Transmission Using Direct Memory Access Controller R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1107 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface (2) Transmission Using Interrupt-Driven Data Flow Control Start Release from reset, set SSICR configuration bits. Define SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL Set up interrupt controller. Enable error interrupt, Enable transmit operation, enable interrupt, enabletransmit a data interrupt, enable enabletransmit an error operation. interrupt. TUIEN = 1, TOIEN = 1, TIE = 1, TEN = 1 For n = ((CHNL +1) x 2) Loop Wait for an interrupt. Data interrupt? No Use SSI status register bits to realign data after underflow/overflow. Yes Load data of channel n. Next channel Yes More data to be sent? No Disable transmit operation*, disable an error interrupt, enable an idle interrupt. TEN = 0, TUIEN = 0, TOIEN = 0, IIEN = 1, TIE = 0 Wait for an idle interrupt from this module End Notes: * When restarting transmission after disabling transmit operation (TEN = 0) while WS continue mode is disabled, first apply a software reset before going back to start in the flowchart. Figure 21.24 Transmission Using Interrupt-Driven Data Flow Control Page 1108 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 21.4.7 Section 21 Serial Sound Interface Receive Operation Like transmission, reception can be controlled either by DMA transfer or interrupt. Figures 21.25 and 21.26 show the flow of operation. When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit indicates that the module is in the idle state. Note: * Input clock from the SSISCK pin when SCKD = 0. Oversampling clock when SCKD = 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1109 of 3092 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface (1) Reception Using Direct Memory Access Controller Start Define SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL Release from reset, set SSICR configuration bits. Set up direct memory access controller, enable direct memory access controller. Enable error interrupt, enable receive interrupt, enable receive operation. RUIEN = 1, ROIEN = 1, RIE = 1, REN = 1 Wait for an interrupt. Error interrupt? Yes No No End of DMA transfer? Yes Yes More data to be received? No Disable receive operation, disable an error interrupt, enable an idle interrupt. REN = 0, RUIEN = 0, ROIEN = 0, IIEN = 1, RIE = 0 Wait for an idle interrupt from this module End* Note: * If an error interrupt (underflow/overflow) occurs, go back to the start in the flowchart again. Figure 21.25 Reception Using Direct Memory Access Controller Page 1110 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 21 Serial Sound Interface Reception Using Interrupt-Driven Data Flow Control Start Define SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL Release from reset, set SSICR configuration bits. Set up interrupt controller. Enable error interrupt, enable receive interrupt, enable receive operation. RUIEN = 1, ROIEN = 1, RIE = 1, REN = 1 Wait for an interrupt. Error interrupt? Yes Use SSI status register bits to realign data after underflow/overflow. No Read data from receive data register. Yes Receive more data? No Disable receive operation, disable a data interrupt, disable an error interrupt, enable an idle interrupt. REN = 0, RUIEN = 0, ROIEN = 0, IIEN = 1, RIE = 0 Wait for an idle interrupt from this module End Figure 21.26 Reception Using Interrupt-Driven Data Flow Control R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1111 of 3092 Section 21 Serial Sound Interface SH7268 Group, SH7269 Group When an underflow or overflow error condition has matched, this module can be recovered to the status before underflow or overflow condition match by using the TCHNO [1:0] and TSWNO bits in transmission and the RCHNO[1:0] and RSWNO bits in reception. When an underflow or overflow occurs, the host can read the channel number and system word number to determine what point the serial audio stream has reached. In the transmitter case, the host can skip forward through the data it wants to transmit until it finds the sample data that matches what this module is expecting to transmit next, and so resynchronize with the audio data stream. In the receiver case the host CPU can store null data to make the number of receive data items consistent until it is ready to store the sample data that this module is indicating will be received next, and so resynchronize with the audio data stream. 21.4.8 Serial Bit Clock Control This function is used to control and select which clock is used for the serial bus interface. If the serial clock direction is set to input (SCKD = 0), this module is in clock slave mode and the shift register uses the bit clock that was input to the SSISCK pin. If the serial clock direction is set to output (SCKD = 1), this module is in clock master mode, and the shift register uses the oversampling clock or a divided oversampling clock as the bit clock. The oversampling clock is divided by the ratio specified by the serial oversampling clock division ratio bits (CKDV) in SSICR for use as the bit clock by the shift register. In either case the module pin, SSISCK, is the same as the bit clock. Page 1112 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 21 Serial Sound Interface 21.5 Usage Notes 21.5.1 Limitations from Underflow or Overflow during DMA Operation If an underflow or overflow occurs while the DMA is in operation, the module should be restarted. The transmit and receive buffers in the SSIF consists of 32-bit registers that share the L and R channels. Therefore, data to be transmitted and received at the L channel may sometimes be transmitted and received at the R channel if an underflow or overflow occurs, for example, under the following condition: the control register (SSICR) has a 32-bit setting for both data word length (DWL2 to DWL0) and system word length (SWL2 to SWL0). If an error occurrence is confirmed with four types of error interrupts (transmit underflow, transmit overflow, receive underflow, and receive overflow) or the corresponding error status flag (the bits TUIRQ, TOIRQ, RUIRQ, and ROIRQ in SSISR), write 0 to the TEN or REN bit in SSICR to disable DMA transfer requests in this module, thus stopping the operation. (In this case, the direct memory access controller setting should also be stopped.) After this, if reception had been in progress, write 0 to the error status flag bit to clear the error status, set the direct memory access controller again and restart the transfer. For transmission, issue a software reset and execute the procedure to start again. 21.5.2 Note on Changing Mode from Master Transceiver to Master Receiver If a transmit underflow occurs in master transceiver mode while WS continue mode is disabled (SSITDMR.CONT = 0) and the TEN bit in SSICR is set to 0 in order to disable transmit operation, SSIWS output is broken. In order to receive seamlessly after changing mode to master receiver mode, write dummy data to SSITDR to suppress transmit underflow. 21.5.3 Limits on TDM mode and WS Continue Mode If TDM mode or WS continue mode setting is changed, the operation of the SSISCK and SSIWS signals immediately after switching are not guaranteed. If it affects the device to be connected, do not change the setting dynamically. To temporarily halt and restart transmission while the WS continue mode is enabled (SSITDMR.CONT = 1), after writing to the transmit FIFO data register (SSIFTDR) a multiple of two times, use the transmit underflow error interrupt or the corresponding error status flag (SSISR.TUIRQ) to confirm that an error has occurred, and then write 0 to the TEN bit of the SSISCR register. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1113 of 3092 Section 21 Serial Sound Interface SH7268 Group, SH7269 Group Note that after the transmit underflow error, the last value written to SSIFTDR will be repeatedly sent as long as SSISCR.TEN = 1. Therefore, write a dummy value as the last data for transmission or mute the signal by writing 1 to the MUEN bit of the SSISCR register. To restart transmission, do not apply a software reset; after writing 0 to the error status flag bit to clear it, use the idle mode status flag (SSISR.IDST) to confirm that this module is in the idle state, and then write 1 to the TEN bit of the SSISCR register. Page 1114 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Section 22 Serial I/O with FIFO This LSI includes a clock-synchronized serial I/O module with FIFO. 22.1 Features  Serial transfer  16-stage 32-bit FIFOs (independent transmission and reception)  Supports 8-bit monaural/16-bit monaural/16-bit stereo audio input and output  MSB first for data transmission  Supports a maximum of 48-kHz sampling rate  Synchronization by frame synchronization pulse  Connectable to linear, audio, or A-Law or -Law CODEC chip  Supports both master and slave modes  Serial clock  AUDIO_CLK or AUDIO_X1 can be selected as the clock source.  Interrupts: One type  DMA transfer: Two types  Transmit FIFO transfer requests and receive FIFO transfer requests R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1115 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Figure 22.1 shows a block diagram. Interrupt request Peripheral bus Bus interface Control registers Transmit FIFO (32 bits x16 stages) Receive FIFO (32 bits x16 stages) P/S S/P SIOFTxD SIOFRxD AUDIO_CLK AUDIO_X1 Baud rate generator 1/nMCLK Timing control SIOFSCK SIOFSYNC Figure 22.1 Block Diagram Page 1116 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.2 Section 22 Serial I/O with FIFO Input/Output Pins Table 22.1 shows the pin configuration. Table 22.1 Pin Configuration Pin Name I/O Function AUDIO_CLK Input External clock for audio AUDIO_X1 Input Crystal resonator/external clock for audio AUDIO_X2 Output SIOFSCK I/O Serial clock (common to transmission/reception) SIOFSYNC I/O Frame synchronous signal (common to transmission/reception) SIOFTxD Output Transmit data SIOFRxD Input Receive data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1117 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO 22.3 Register Descriptions Table 22.2 shows the register configuration. Table 22.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Mode register SIMDR R/W H'8000 H'FFFF4800 16 Clock select register SISCR R/W H'8000 H'FFFF4802 16 Transmit data assign register SITDAR R/W H'0000 H'FFFF4804 16 Receive data assign register SIRDAR R/W H'0000 H'FFFF4806 16 Control register SICTR R/W H'0000 H'FFFF480C 16 FIFO control register SIFCTR R/W* H'1000 H'FFFF4810 16 Status register SISTR R/W* H'0000 H'FFFF4814 16 Interrupt enable register SIIER R/W H'0000 H'FFFF4816 16 Transmit data register SITDR W Undefined H'FFFF4820 8, 16, 32 Receive data register SIRDR R Undefined H'FFFF4824 8, 16, 32 Note: * This register has readable/writable bits and read-only bits. For details, see descriptions for each register. Page 1118 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.3.1 Section 22 Serial I/O with FIFO Mode Register (SIMDR) SIMDR sets the operating mode for this module. Bit: 15 14 13 12 TRMD1 TRMD0 SYNCAT REDG Initial Value: 1 R/W: R/W 0 R/W 0 R/W 0 R/W 11 10 9 8 7 6 FL3 FL2 FL1 FL0 TXDIZ - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 TRMD1 1 R/W Transfer Mode 1, 0 14 TRMD0 0 R/W Select transfer mode. 5 4 SYNCAC SYNCDL 0 R/W 0 R/W 3 2 1 - - - - 0 R 0 R 0 R 0 R 0 00: Slave mode 01: Setting prohibited 10: Master mode 11: Setting prohibited 13 SYNCAT 0 R/W SIOFSYNC Pin Valid Timing Indicates the position where the SIOFSYNC signal is output. This bit is valid in master mode. 0: At the start-bit data of frame 1: At the last-bit data of slot Note: If this bit is set to 1, make sure that valid data is transmitted/received or transmitted. 12 REDG 0 R/W Receive Data Sampling Edge This bit is valid in master mode. 0: The SIOFRxD signal is sampled at the falling edge of SIOFSCK (The SIOFTxD signal is transmitted at the rising edge of SIOFSCK.) 1: The SIOFRxD signal is sampled at the rising edge of SIOFSCK (The SIOFTxD signal is transmitted at the falling edge of SIOFSCK.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1119 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 11 FL3 0 R/W Frame Length 3 to 0 10 FL2 0 R/W 00xx: Data length is 8 bits and frame length is 8 bits. 9 FL1 0 R/W 0100: Data length is 8 bits and frame length is 16 bits. 8 FL0 0 R/W 0101: Data length is 8 bits and frame length is 32 bits. 0110: Data length is 8 bits and frame length is 64 bits. 0111: Data length is 8 bits and frame length is 128 bits. 10xx: Data length is 16 bits and frame length is 16 bits. 1100: Data length is 16 bits and frame length is 32 bits. 1101: Data length is 16 bits and frame length is 64 bits. 1110: Data length is 16 bits and frame length is 128 bits. 1111: Data length is 16 bits and frame length is 256 bits. Note: When data length is specified as 8 bits, control data cannot be transmitted or received. x: Don't care 7 TXDIZ 0 R/W SIOFTxD Pin Output when Transmission is Invalid* 0: High output (1 output) when invalid 1: High-impedance state when invalid Note: Invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being output. 6  0 R Reserved This bit is always read as 0. The write value should always be 0. 5 SYNCAC 0 R/W SIOFSYNC Pin Polarity This bit is valid in master mode. 0: Active-high 1: Active-low 4 SYNCDL 0 R/W Data Pin Bit Delay for SIOFSYNC Pin Only 1-bit delay is valid in slave mode. 0: No bit delay 1: 1-bit delay 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1120 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.3.2 Section 22 Serial I/O with FIFO Control Register (SICTR) SICTR sets the operating state for this module. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SCKE FSE - - - - TXE RXE - - - - - - Initial Value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 SCKE 0 R/W Serial Clock Output Enable 1 0 TXRST RXRST 0 R/W 0 R/W This bit is valid in master mode. 0: Disables the SIOFSCK output (outputs 0) 1: Enables the SIOFSCK output  14 FSE 0 R/W If this bit is set to 1, this module initializes the baud rate generator and initiates the operation. At the same time, the clock generated by the baud rate generator is output to the SIOFSCK pin. Frame Synchronous Signal Output Enable This bit is valid in master mode. 0: Disables the SIOFSYNC output (outputs 0) 1: Enables the SIOFSYNC output  13 to 10  All 0 R If this bit is set to 1, this module initializes the frame counter and initiates the operation. Reserved These bits are always read as 0. The write value should always be 0. 9 TXE 0 R/W Transmit Enable 0: Disables data transmission from the SIOFTxD pin 1: Enables data transmission from the SIOFTxD pin    R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal). When the 1 setting for this bit becomes valid, this module issues a transmit transfer request according to the setting of the TFWM bit in SIFCTR. When transmit data is stored in the transmit FIFO, transmission of data from the SIOFTxD pin begins. This bit is initialized upon a transmit reset. Page 1121 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 8 RXE 0 R/W 7 to 2  All 0 R Receive Enable 0: Disables data reception from SIOFRxD 1: Enables data reception from SIOFRxD  This bit setting becomes valid at the start of the next frame (at the rising edge of the SIOFSYNC signal).  When the 1 setting for this bit becomes valid, this module begins the reception of data from the SIOFRxD pin. When receive data is stored in the receive FIFO, a reception transfer request is issued according to the setting of the RFWM bit in SIFCTR.  This bit is initialized upon receive reset. Reserved These bits are always read as 0. The write value should always be 0. 1 TXRST 0 R/W Page 1122 of 3092 Transmit Reset 0: Does not reset transmit operation 1: Resets transmit operation  This bit setting becomes valid immediately. This bit should be cleared to 0 before setting the register to be initialized.  When the 1 setting for this bit becomes valid, this module immediately sets the SIOFTxD pin output to 1, and initializes the following registers and data:  SITDR  Valid data in transmit FIFO  The TFEMP and TDREQ bits in SISTR  The TXE bit Note: Set this bit to 1 for more than one transfer clock period. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 0 RXRST 0 R/W Receive Reset 0: Does not reset receive operation 1: Resets receive operation  This bit setting becomes valid immediately. This bit should be cleared to 0 before setting the register to be initialized.  When the 1 setting for this bit becomes valid, this module immediately disables reception from the SIOFRxD pin, and initializes the following registers and data:  SIRDR  Valid data in receive FIFO  The RFFUL and RDREQ bits in SISTR  The RXE bit Note: Set this bit to 1 for more than one transfer clock period. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1123 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO 22.3.3 Transmit Data Register (SITDR) SITDR specifies transmit data. The data set in SITDR will be stored in the transmit FIFO. SITDR is initialized by a transmit reset caused by the TXRST bit in SICTR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SITDL[15:0] Initial Value: R/W: Bit: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SITDR[15:0] Initial Value: R/W: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined W W Bit Bit Name 31 to 16 SITDL [15:0] W W Initial Value W W R/W Undefined W W SITDR [15:0] W W W W W W W Left-Channel Transmit Data Specify data to be transmitted from the SIOFTxD pin as left-channel data. The position of the left-channel data in the transmit frame is specified by the TDLA bit in SITDAR. Undefined W These bits are valid only when the TDLE bit in SITDAR is set to 1. Right-Channel Transmit Data Specify data to be transmitted from the SIOFTxD pin as right-channel data. The position of the right-channel data in the transmit frame is specified by the TDRA bit in SITDAR.  Page 1124 of 3092 W Description  15 to 0 W These bits are valid only when the TDRE bit is set to 1 and the TLREP bit is cleared to 0 in SITDAR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.3.4 Section 22 Serial I/O with FIFO Receive Data Register (SIRDR) SIRDR reads receive data of this module. SIRDR stores data in the receive FIFO. SIRDR is initialized by a receive reset caused by the RXRST bit in SICTR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIRDL[15:0] Initial Value: R/W: Bit: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRDR[15:0] Initial Value: R/W: Bit 31 to 16 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R Initial Bit Name Value SIRDL [15:0] Undefined R R R SIRDR [15:0] R R R R/W Description R Left-Channel Receive Data R R R R R Store data received from the SIOFRxD pin as leftchannel data. The position of the left-channel data in the receive frame is specified by the RDLA bit in SIRDAR.  15 to 0 R Undefined R Right-Channel Receive Data Store data received from the SIOFRxD pin as rightchannel data. The position of the right-channel data in the receive frame is specified by the RDRA bit in SIRDAR.  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 These bits are valid only when the RDLE bit in SIRDAR is set to 1. These bits are valid only when the RDRE bit in SIRDAR is set to 1. Page 1125 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO 22.3.5 Status Register (SISTR) SISTR shows the state of this module. Each bit in this register becomes an interrupt source for this module when the corresponding bit in SIIER is set to 1. SISTR is initialized in module stop mode. Bit: 15 14 - - Initial Value: 0 R/W: R 0 R 13 12 11 10 - - 0 R 0 R TFEMP TDREQ 0 R 0 R Bit Bit Name Initial Value R/W 15  0 R 9 8 RFFUL RDREQ 0 R 0 R 7 6 5 - - - 0 R 0 R 0 R 4 3 2 1 0 FSERR TFOVF TFUDF RFUDF RFOVF 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14  0 R Reserved The read value is undefined. The write value should always be 0. 13 TFEMP 0 R Transmit FIFO Empty 0: Indicates that transmit FIFO is not empty 1: Indicates that transmit FIFO is empty  This bit is valid when the TXE bit in SICTR is 1.  If SITDR is written, this module clears this bit. Note: When this bit is set to 1, a transmit FIFO underflow may have occurred. Do not use this bit at the timing of writing to the transmit data register. Page 1126 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 12 TDREQ 0 R Transmit Data Transfer Request 0: Indicates that the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR. 1: Indicates that the size of empty space in the transmit FIFO is equal to or greater than the size specified by the TFWM bit in SIFCTR. A transmit data transfer request is issued when the empty space in the transmit FIFO exceeds the size specified by the TFWM bit in SIFCTR. When transmit data is transferred through the direct memory access controller, this bit is always cleared by an access of the direct memory access controller. If the condition for setting this bit is satisfied after the access of the direct memory access controller, this module again sets this bit to 1.   11, 10  All 0 R This bit is valid when the TXE bit in SICTR is 1. If the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR, this module clears this bit. Reserved These bits are always read as 0. The write value should always be 0. 9 RFFUL 0 R Receive FIFO Full 0: Receive FIFO not full 1: Receive FIFO full   R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 This bit is valid when the RXE bit in SICTR is 1. If SIRDR is read, this module clears this bit. Page 1127 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 8 RDREQ 0 R Receive Data Transfer Request 0: Indicates that the size of valid space in the receive FIFO is less than the size specified by the RFWM bit in SIFCTR. 1: Indicates that the size of valid space in the receive FIFO is equal to or greater than the size specified by the RFWM bit in SIFCTR. A receive data transfer request is issued when the valid space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR. When receive data is transferred through the direct memory access controller, this bit is always cleared by an access of the direct memory access controller. If the condition for setting this bit is satisfied after the access of the direct memory access controller, this module again sets this bit to 1.   7 to 5  All 0 R This bit is valid when the RXE bit in SICTR is 1. If the size of valid space in the receive FIFO is less than the size specified by the RFWM bit in SIFCTR, this module clears this bit. Reserved These bits are always read as 0. The write value should always be 0. 4 FSERR 0 R/W Frame Synchronization Error 0: Indicates that no frame synchronization error occurs 1: Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appears before the previous data transfer has been completed. If a frame synchronization error occurs, this module performs transmission or reception for slots that can be transferred.   Page 1128 of 3092 This bit is valid when the TXE or RXE bit in SICTR is 1. When this bit is set to 1, it is cleared to 0 by this module. Writing 0 to this bit is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 3 TFOVF 0 R/W Transmit FIFO Overflow 0: No transmit FIFO overflow 1: Transmit FIFO overflow A transmit FIFO overflow means that there has been an attempt to write to SITDR when the transmit FIFO is full. When an overflow of the transmit FIFO occurs, the write which caused the overflow is invalid.   2 TFUDF 0 R/W This bit is valid when the TXE bit in SICTR is 1. When this bit is set to 1, it is cleared to 0 by this module. Writing 0 to this bit is invalid. Transmit FIFO Underflow 0: No transmit FIFO underflow 1: Transmit FIFO underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty. When a transmit FIFO underflow occurs, this module repeatedly sends the previous transmit data.   1 RFUDF 0 R/W This bit is valid when the TXE bit in SICTR is 1. When this bit is set to 1, it is cleared to 0 by this module. Writing 0 to this bit is invalid. Receive FIFO Underflow 0: No receive FIFO underflow 1: Receive FIFO underflow A receive FIFO underflow means that reading of SIRDR has occurred when the receive FIFO is empty. When a receive FIFO underflow occurs, the value of data read from SIRDR is not guaranteed.   R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 This bit is valid when the RXE bit in SICTR is 1. When this bit is set to 1, it is cleared to 0 by this module. Writing 0 to this bit is invalid. Page 1129 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 0 RFOVF 0 R/W Receive FIFO Overflow 0: No receive FIFO overflow 1: Receive FIFO overflow A receive FIFO overflow means that writing has occurred due to reception operation when the receive FIFO is full. When an overflow of the receive FIFO occurs, the receive data which caused the overflow is lost.  Page 1130 of 3092 When this bit is set to 1, it is cleared to 0 by this module. Writing 0 to this bit is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.3.6 Section 22 Serial I/O with FIFO Interrupt Enable Register (SIIER) SIIER enables the issue of interrupts from this module. When a bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, this module issues an interrupt. Bit: 15 TDMAE Initial Value: 0 R/W: R/W 14 - 0 R 13 12 TFEMPE TDREQE 0 R/W 0 R/W 11 10 RDMAE - 0 R/W 0 R 9 8 RFFULE RDREQE 0 R/W 0 R/W 7 6 5 - - - 0 R 0 R 0 R 4 3 2 1 0 FSERRE TFOVFE TFUDFE RFUDFE RFOVFE 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 TDMAE 0 R/W Transmit FIFO DMA Transfer Request Enable 0 R/W 0 R/W Uses a transmit FIFO transfer request as an interrupt or a DMA transfer request. 0: Used as an interrupt to the CPU 1: Used as a DMA transfer request to the direct memory access controller 14  0 R Reserved This bit is always read as 0. The write value should always be 0. 13 TFEMPE 0 R/W Transmit FIFO Empty Enable 0: Disables interrupts due to transmit FIFO empty 1: Enables interrupts due to transmit FIFO empty 12 TDREQE 0 R/W Transmit FIFO Transfer Request Enable 0: Disables interrupts/DMA transfer requests due to transmit FIFO transfer requests 1: Enables interrupts/DMA transfer requests due to transmit FIFO transfer requests 11 RDMAE 0 R/W Receive FIFO DMA Transfer Request Enable Uses a receive FIFO transfer request as an interrupt or a DMA transfer request. 0: Used as a CPU interrupt 1: Used as a DMA transfer request to the direct memory access controller 10  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1131 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 9 RFFULE 0 R/W Receive FIFO Full Enable 0: Disables interrupts due to receive FIFO full 1: Enables interrupts due to receive FIFO full 8 RDREQE 0 R/W Receive FIFO Transfer Request Enable 0: Disables interrupts/DMA transfer requests due to receive FIFO transfer requests 1: Enables interrupts/DMA transfer requests due to receive FIFO transfer requests 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 FSERRE 0 R/W Frame Synchronization Error Enable 0: Disables interrupts due to frame synchronization error 1: Enables interrupts due to frame synchronization error 3 TFOVFE 0 R/W Transmit FIFO Overflow Enable 0: Disables interrupts due to transmit FIFO overflow 1: Enables interrupts due to transmit FIFO overflow 2 TFUDFE 0 R/W Transmit FIFO Underflow Enable 0: Disables interrupts due to transmit FIFO underflow 1: Enables interrupts due to transmit FIFO underflow 1 RFUDFE 0 R/W Receive FIFO Underflow Enable 0: Disables interrupts due to receive FIFO underflow 1: Enables interrupts due to receive FIFO underflow 0 RFOVFE 0 R/W Receive FIFO Overflow Enable 0: Disables interrupts due to receive FIFO overflow 1: Enables interrupts due to receive FIFO overflow Page 1132 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.3.7 Section 22 Serial I/O with FIFO FIFO Control Register (SIFCTR) SIFCTR indicates the area available for the transmit/receive FIFO transfer. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFWM2 TFWM1 TFWM0 TFUA4 TFUA3 TFUA2 TFUA1 TFUA0 RFWM2 RFWM1 RFWM0 RFUA4 RFUA3 RFUA2 RFUA1 RFUA0 Initial Value: 0 R/W: R/W 0 R/W 0 R/W 1 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 TFWM2 0 R/W Transmit FIFO Watermark 14 TFWM1 0 R/W 13 TFWM0 0 R/W 000: Issue a transfer request when 16 stages of the transmit FIFO are empty. 0 R 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 12 or more stages of the transmit FIFO are empty. 101: Issue a transfer request when 8 or more stages of the transmit FIFO are empty. 110: Issue a transfer request when 4 or more stages of the transmit FIFO are empty. 111: Issue a transfer request when 1 or more stages of transmit FIFO are empty.   A transfer request to the transmit FIFO is issued by the TDREQE bit in SISTR. The transmit FIFO is always used as 16 stages of the FIFO regardless of these bit settings. 12 TFUA4 1 R Transmit FIFO Usable Area 11 TFUA3 0 R 10 TFUA2 0 R Indicate the number of stages of FIFO that can be transferred as B'00000 (full) to B'10000 (empty). 9 TFUA1 0 R 8 TFUA0 0 R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1133 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 7 RFWM2 0 R/W Receive FIFO Watermark 6 RFWM1 0 R/W 5 RFWM0 0 R/W 000: Issue a transfer request when 1 stage or more of the receive FIFO are valid. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Issue a transfer request when 4 or more stages of the receive FIFO are valid. 101: Issue a transfer request when 8 or more stages of the receive FIFO are valid. 110: Issue a transfer request when 12 or more stages of the receive FIFO are valid. 111: Issue a transfer request when 16 stages of the receive FIFO are valid.   A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR. The receive FIFO is always used as 16 stages of the FIFO regardless of these bit settings. 4 RFUA4 0 R Receive FIFO Usable Area 3 RFUA3 0 R 2 RFUA2 0 R Indicate the number of stages of FIFO that can be transferred as B'00000 (empty) to B'10000 (full). 1 RFUA1 0 R 0 RFUA0 0 R Page 1134 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.3.8 Section 22 Serial I/O with FIFO Clock Select Register (SISCR) SISCR sets the serial clock generation conditions for the master clock. SISCR can be specified when the TRMD1 and TRMD0 bits in SIMDR are specified as B'10. Bit: 15 14 13 - - 0 R 0 R MSSEL Initial Value: 1 R/W: R/W 12 11 10 9 8 BRPS4 BRPS3 BRPS2 BRPS1 BRPS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 - - - - - 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 MSSEL 1 R/W Master Clock Source Selection 2 1 0 BRDV2 BRDV1 BRDV0 0 R/W 0 R/W 0 R/W 0: Uses AUDIO_X1 as the master clock 1: Uses AUDIO_CLK as the master clock The master clock is the clock input to the baud rate generator. 14, 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 BRPS4 0 R/W Prescalar Setting 11 BRPS3 0 R/W 10 BRPS2 0 R/W Set the master clock division ratio according to the count value of the prescalar of the baud rate generator. 9 BRPS1 0 R/W 8 BRPS0 0 R/W 7 to 3  All 0 R The range of settings is from B'00000 ( 1/1) to B'11111 ( 1/32). Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1135 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 2 BRDV2 0 R/W Baud rate generator’s Division Ratio Setting 1 BRDV1 0 R/W 0 BRDV0 0 R/W Set the frequency division ratio for the output stage of the baud rate generator. 000: Prescalar output  1/2 001: Prescalar output  1/4 010: Prescalar output  1/8 011: Prescalar output  1/16 100: Prescalar output  1/32 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited The final frequency division ratio of the baud rate generator is determined by BRPS  BRDV (maximum 1/1024). 22.3.9 Transmit Data Assign Register (SITDAR) SITDAR specifies the position of the transmit data in a frame (slot number). Bit: 15 14 13 12 TDLE - - - Initial Value: 0 R/W: R/W 0 R 0 R 0 R 11 10 9 8 7 6 TDLA3 TDLA2 TDLA1 TDLA0 TDRE TLREP 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 5 4 - - 0 R 0 R 3 2 1 0 TDRA3 TDRA2 TDRA1 TDRA0 0 R/W Bit Bit Name Initial Value R/W Description 15 TDLE 0 R/W Transmit Left-Channel Data Enable 0 R/W 0 R/W 0 R/W 0: Disables left-channel data transmission 1: Enables left-channel data transmission 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1136 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Bit Bit Name Initial Value R/W Description 11 TDLA3 0 R/W Transmit Left-Channel Data Assigns 3 to 0 10 TDLA2 0 R/W 9 TDLA1 0 R/W Specify the position of left-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 8 TDLA0 0 R/W 1111: Setting prohibited  7 TDRE 0 R/W Transmit data for the left channel is specified in the SITDL bit in SITDR. Transmit Right-Channel Data Enable 0: Disables right-channel data transmission 1: Enables right-channel data transmission 6 TLREP 0 R/W Transmit Left-Channel Repeat 0: Transmits data specified in the SITDR bit in SITDR as right-channel data 1: Repeatedly transmits data specified in the SITDL bit in SITDR as right-channel data   5, 4  All 0 R This bit setting is valid when the TDRE bit is set to 1. When this bit is set to 1, the SITDR settings are ignored. Reserved These bits are always read as 0. The write value should always be 0. 3 TDRA3 0 R/W Transmit Right-Channel Data Assigns 3 to 0 2 TDRA2 0 R/W 1 TDRA1 0 R/W Specify the position of right-channel data in a transmit frame as B'0000 (0) to B'1110 (14). 0 TDRA0 0 R/W 1111: Setting prohibited  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Transmit data for the right channel is specified in the SITDR bit in SITDR. Page 1137 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO 22.3.10 Receive Data Assign Register (SIRDAR) SIRDAR specifies the position of the receive data in a frame (slot number). Bit: 15 14 13 12 RDLE - - - Initial Value: 0 R/W: R/W 0 R 0 R 0 R 11 10 9 8 7 RDLA3 RDLA2 RDLA1 RDLA0 RDRE 0 R/W Bit Bit Name Initial Value R/W 15 RDLE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 6 5 4 - - - 0 R 0 R 0 R 3 2 1 0 RDRA3 RDRA2 RDRA1 RDRA0 0 R/W 0 R/W 0 R/W 0 R/W Description Receive Left-Channel Data Enable 0: Disables left-channel data reception 1: Enables left-channel data reception 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 RDLA3 0 R/W Receive Left-Channel Data Assigns 3 to 0 10 RDLA2 0 R/W 9 RDLA1 0 R/W Specify the position of left-channel data in a receive frame as B'0000 (0) to B'1110 (14). 8 RDLA0 0 R/W 1111: Setting prohibited  7 RDRE 0 R/W Receive data for the left channel is stored in the SIRDL bit in SIRDR. Receive Right-Channel Data Enable 0: Disables right-channel data reception 1: Enables right-channel data reception 6 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 RDRA3 0 R/W Receive Right-Channel Data Assigns 3 to 0 2 RDRA2 0 R/W 1 RDRA1 0 R/W Specify the position of right-channel data in a receive frame as B'0000 (0) to B'1110 (14). 0 RDRA0 0 R/W 1111: Setting prohibited  Page 1138 of 3092 Receive data for the right channel is stored in the SIRDR bit in SIRDR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.4 Operation 22.4.1 Serial Clocks (1) Section 22 Serial I/O with FIFO Master/Slave Modes The following two modes are available as a clock mode for this module.  Slave mode: SIOFSCK, SIOFSYNC input  Master mode: SIOFSCK, SIOFSYNC output (2) Baud Rate Generator: In master mode, the baud rate generator (BRG) is used to generate the serial clock. The division ratio is from 1/2 to 1/1024. Figure 22.2 shows connections for supply of the serial clock. MCLK BRG 1/2 to 1/1024MCLK AUDIO_CLK AUDIO_X1 Timing control SCKE Master SIOFSCK Figure 22.2 Serial Clock Supply Table 22.3 shows an example of serial clock frequency. Table 22.3 Serial Clock Frequency Sampling Rate Frame Length 8 kHz 44.1 kHz 48 kHz 32 bits 256 kHz 1.4112 MHz 1.536 MHz 64 bits 512 kHz 2.8224 MHz 3.072 MHz 128 bits 1.024 MHz 5.6448 MHz 6.144 MHz 256 bits 2.048 MHz 11.289 MHz 12.289 MHz R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1139 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO 22.4.2 (1) Serial Timing SIOFSYNC The SIOFSYNC is a frame synchronous signal. Figure 22.3 shows the SIOFSYNC synchronization timing. 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD Start bit data 1-bit delay Figure 22.3 Serial Data Synchronization Timing Page 1140 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 22 Serial I/O with FIFO Transmit/Receive Timing The SIOFTxD transmit timing and SIOFRxD receive timing relative to the SIOFSCK can be set as the sampling timing in the following ways. The transmit/receive timing is set using the REDG bit in SIMDR.  Falling-edge sampling  Rising-edge sampling (possible only in master mode) Figure 22.4 shows the transmit/receive timing. (a) Falling-edge sampling (a) Rising-edge sampling SIOFSCK SIOFSCK SIOFSYNC SIOFSYNC SIOFTxD SIOFTxD SIOFRxD SIOFRxD Receive timing Transmit timing Receive timing Transmit timing Figure 22.4 Transmit/Receive Timing 22.4.3 Transfer Data Format This module performs the following transfer.  Transmit/receive data: Transfer of 8-bit monaural/16-bit monaural/16-bit stereo data (1) Transfer Mode This module supports the following two transfer modes as listed in table 22.4. The transfer mode can be specified by the TRMD1 and TRMD0 bits in SIMDR. Table 22.4 Serial Transfer Modes Transfer Mode SIOFSYNC Bit Delay Slave mode Synchronous pulse SYNCDL bit Master mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1141 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO (2) Frame Length The length of the frame to be transferred by this module is specified with the FL3 to FL0 bits in SIMDR. Table 22.5 shows the relationship between the FL3 to FL0 bit settings and frame length. Table 22.5 Frame Length FL3 to FL0 Slot Length Number of Bits in a Frame Transfer Data 00xx 8 8 8-bit monaural data 0100 8 16 8-bit monaural data 0101 8 32 8-bit monaural data 0110 8 64 8-bit monaural data 0111 8 128 8-bit monaural data 10xx 16 16 16-bit monaural data 1100 16 32 16-bit monaural/stereo data 1101 16 64 16-bit monaural/stereo data 1110 16 128 16-bit monaural/stereo data 1111 16 256 16-bit monaural/stereo data Note: x: Don't care. (3) Slot Position This module can specify the position of transmit data and receive data in a frame by slot numbers. The slot number of each data is specified by the following registers.  Transmit data: SITDAR  Receive data: SIRDAR 22.4.4 Register Allocation of Transfer Data Writing and reading of transmit/receive data is performed for the following registers.  Transmit data writing: SITDR (8-, 16-, or 32-bit access)  Receive data reading: SIRDR (8-, 16-, or 32-bit access) Figure 22.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment. Page 1142 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO (a) 16-bit stereo data 31 24 23 16 15 87 L-channel data (b) 16-bit monaural data 31 24 23 0 R-channel data 16 15 87 0 16 15 87 0 (d) 16-bit stereo data (left and right same audio output) data 31 24 23 16 15 87 0 Data (c) 8-bit monaural data 31 24 23 Data Data Figure 22.5 Transmit/Receive Data Bit Alignment Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in unshaded areas is not transmitted or received. Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR. Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR. To achieve left and right same audio output while stereo is specified for transmit data, specify the TLREP bit in SITDAR. Tables 22.6 and 22.7 show the audio mode specifications for transmit data and that for receive data, respectively. Table 22.6 Audio Mode Specification for Transmit Data Bit Mode TDLE TDRE TLREP Monaural 1 0 x Stereo 1 1 0 Left and right same audio output 1 1 1 Note: x: Don't care R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1143 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Table 22.7 Audio Mode Specification for Receive Data Bit Mode RDLE RDRE Monaural 1 0 Stereo 1 1 Note: Left and right same audio mode is not supported in receive data. To execute monaural transmission or reception, use the left channel. 22.4.5 (1) FIFO Overview The transmit and receive FIFOs of this module have the following features.  16-stage 32-bit FIFOs for transmission and reception  One FIFO buffer stage is used regardless of the access size. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.) (2) Transfer Request The following FIFO transfer requests can be issued to the CPU or direct memory access controller.  Transmit request: TDREQ (transmit FIFO transfer request)  Receive request: RDREQ (receive FIFO transfer request) The conditions to issue the transmit/receive FIFO transfer requests can be specified individually. The transmit request condition is specified with the TFWM2 to TFWM0 bits in SIFCTR, and the receive FIFO transfer request is specified with the RFWM2 to RFWM0 bits in SIFCTR. Tables 22.8 and 22.9 summarize the conditions specified by SIFCTR. Page 1144 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO Table 22.8 Conditions to Issue Transmit Request TFWM2 to TFWM0 Number of Requested Stages Transmit Request Issued Used Areas 000 1 There are sixteen stages of empty area. Smallest 100 4 There are twelve or more stages of empty area. 101 8 There are eight or more stages of empty area. 110 12 There are four or more stages of empty area. 111 16 There is one or more stage of empty area. Largest Table 22.9 Conditions to Issue Receive Request RFWM2 to RFWM0 Number of Requested Stages Receive Request Issued Used Areas 000 1 There is one or more stage of valid data. Smallest 100 4 There are four stages of valid data or more. 101 8 There are eight stages of valid data or more. 110 12 There are twelve stages of valid data or more. 111 16 There are sixteen stages of valid data. Largest The number of stages of the FIFO is sixteen. Accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen FIFO stages. The transfer request is canceled when the above condition is not satisfied even if the FIFO is not empty or full. (3) Number of FIFOs The usage state of the transmit FIFO and receive FIFO are indicated by the TFUA and FRUA bits in the FIFO control register as below:  Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits in SIFCTR.  Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in SIFCTR. The above register contents indicate the possible data numbers that can be transferred by the CPU or direct memory access controller. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1145 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO 22.4.6 (1) Transmit and Receive Procedures Transmission in Master Mode Figure 22.6 shows an example of transmission settings and operation when this module is used as a master. Flow Chart No. Settings of This Module Operation of This Module Start Set SIMDR, SISCR, SITDAR, and SIFCTR Set operating mode, serial clock, slot position for transmit data, and FIFO request threshold value 2 Set the SCKE bit in SICTR to 1 Set operation start for baud rate generator 3 Start SIOFSCK output 4 Set the FSE and TXE bits in SICTR to 1 5 TDREQ = 1? 1 Output serial clock Set the start for frame synchronous Output frame synchronous signal and issue transmit signal output and enable transfer request* transmission No Yes 6 Set SITDR 7 Transmit SITDR from SIOFTXD synchronously with SIOFSYNC Transfer ended? 8 Set transmit data Transmit No Yes Set to disable transmission End transmission Clear the TXE bit in SICTR to 0 End Note: * To avoid occurrence of a transmit data underflow, the TXE bit should be set to 1 after setting the no. 6 transmit data, Figure 22.6 Example of Transmit Operation in Master Mode Page 1146 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 22 Serial I/O with FIFO Reception in Master Mode Figure 22.7 shows an example of reception settings and operation when this module is used as a master. No. Flow Chart Settings of This Module Operation of This Module Start 1 Set SIMDR, SISCR, SIRDAR, and SIFCTR Set operating mode, serial clock, slot position for receive data, and FIFO request threshold value 2 Set the SCKE bit in SICTR to 1 Set operation start for baud rate generator 3 Start SIOFSCK output 4 Set the FSE and RXE bits in SICTR to 1 5 Store SIOFRXD receive data in SIRDR synchronously with SIOFSYNC 6 RDREQ = 1? Output serial clock Set the start for frame synchronous Output frame synchronous signal output and enable signal reception Issue receive transfer request according to the receive FIFO threshold value No Reception Yes 7 Read receive data Read SIRDR Reception ended? No Yes 8 Set to disable reception End reception Clear the RXE bit in SICTR to 0 End Figure 22.7 Example of Receive Operation in Master Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1147 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO (3) Transmission in Slave Mode Figure 22.8 shows an example of transmission settings and operation for when this module is used as a slave. Flow Chart No. Settings of This Module Operation of This Module Start Set SIMDR, SISCR, SITDAR, and SIFCTR Set operating mode, serial clock, slot position for transmit data, and FIFO request threshold value 2 Set the TXE bit in SICTR to 1 Set to enable transmission 3 TDREQ = 1? 1 Issue transmit transfer request to enable transmission when frame synchronous signal is input No Yes 4 Set SITDR 5 Transmit SITDR from SIOFTXD synchronously with SIOFSYNC Transfer ended? Set transmit data No Yes 6 Transmit Set to disable transmission End transmission Clear the TXE bit in SICTR to 0 End Figure 22.8 Example of Transmit Operation in Slave Mode Page 1148 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 22 Serial I/O with FIFO Reception in Slave Mode Figure 22.9 shows an example of reception settings and operation when this module is used as a slave. No. Flow Chart Settings of This Module Operation of This Module Start Set SIMDR, SISCR, SIRDAR, and SIFCTR Set operating mode, serial clock, slot position for receive data, and FIFO request threshold value 2 Set the RXE bit in SICTR to 1 Set to enable reception 3 Store SIOFRXD receive data in SIRDR synchronously with SIOFSYNC 1 4 RDREQ = 1? Enable reception when the frame synchronous signal is input Issue receive transfer request according to the receive FIFO threshold value No Reception Yes 5 Read SIRDR 6 Reception ended? Yes Read receive data No Set to disable reception End reception Clear the RXE bit in SICTR to 0 End Figure 22.9 Example of Receive Operation in Slave Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1149 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO (5) Transmit/Receive Reset This module can separately reset the transmit and receive units by setting the following bits to 1.  Transmit reset: TXRST bit in SICTR  Receive reset: RXRST bit in SICTR Table 22.10 shows the details of initialization upon the transmit or receive reset. Table 22.10 Transmit and Receive Reset Type Objects Initialized Transmit reset SITDR Valid data in transmit FIFO The TFEMP and TDREQ bits in SISTR The TXE bit in SICTR Receive reset SIRDR Valid data in receive FIFO The RFFUL and RDREQ bits in SISTR The RXE bit in SICTR Page 1150 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.4.7 Section 22 Serial I/O with FIFO Interrupts This module has one type of interrupt. (1) Interrupt Requests Interrupts can be issued by several requests. Each source is shown as an status in SISTR. Table 22.11 lists the interrupt requests. Table 22.11 Interrupt Requests No. Classification Bit Name Function Name 1 TDREQ Transmit FIFO transfer The transmit FIFO stores data of request specified size or more. TFEMP Transmit FIFO empty The transmit FIFO is empty. RDREQ Receive FIFO transfer request The receive FIFO stores data of specified size or more. RFFUL Receive FIFO full The receive FIFO is full. TFUDF Transmit FIFO underflow Serial data transmit timing has arrived while the transmit FIFO is empty. 6 TFOVF Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full. 7 RFOVF Receive FIFO overflow Serial data is received while the receive FIFO is full. 8 RFUDF Receive FIFO underflow The receive FIFO is read while the receive FIFO is empty. 9 FSERR FS error A synchronous signal is input before the specified bit number has been passed (in slave mode). Transmission 2 3 Reception 4 5 Error Description Whether the interrupt is issued or not by the request is determined by the SIIER settings. If an interrupt request is generated when the corresponding bit in SIIER is set to 1, this module issues the interrupt. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1151 of 3092 Section 22 Serial I/O with FIFO (2) SH7268 Group, SH7269 Group Regarding Transmit and Receive Classification The transmit request and receive request are signals indicating the state; after being set, if the state of the transmit/receive FIFO changes, they are automatically cleared by this module. When the DMA transfer is used, the signal is cleared to 0 by the direct memory access controller. If the setting condition is still satisfied after the access using the direct memory access controller, it is set to 1 again. (3) Processing when Errors Occur On occurrence of each of the errors indicated as a status in SISTR, this module performs the following operations.  Transmit FIFO underflow (TFUDF) The immediately preceding transmit data is again transmitted.  Transmit FIFO overflow (TFOVF) The contents of the transmit FIFO are protected, and the write operation causing the overflow is ignored.  Receive FIFO overflow (RFOVF) Data causing the overflow is discarded and lost.  Receive FIFO underflow (RFUDF) The read value is undefined.  FS error (FSERR) The internal counter is reset according to the sync signal in which an error occurs. Page 1152 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 22.4.8 Section 22 Serial I/O with FIFO Transmit and Receive Timing Examples of serial transmission and reception with this module are shown in figures 22.10 to 22.15. (1) 8-bit Monaural Data (1) Falling edge sampling, slot No.0 used for transmit and receive data, an frame length = 8 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data SIOFRxD Slot No.0 1-bit delay Specifications: TRMD[1:0]=00 or 10, REDG=0, TDLE=1, TDLA[3:0]=0000, RDLE=1, RDLA[3:0]=0000, FL[3:0]=0000 (frame length: 8 bits) TDRE=0, TDRA[3:0]=0000, RDRE=0, RDRA[3:0]=0000 Figure 22.10 Transmit and Receive Timing (8-Bit Monaural Data (1)) (2) 8-bit Monaural Data (2) Falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 16 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data SIOFRxD Slot No.0 Slot No.1 1-bit delay Specifications: TRMD[1:0]=00 or 10, REDG=0, FL[3:0]=0100 (frame length: 16 bits) TDLA[3:0]=0000, TDRE=0, TDLE=1, TDRA[3:0]=0000, RDLA[3:0]=0000, RDRE=0, RDLE=1, RDRA[3:0]=0000 Figure 22.11 Transmit and Receive Timing (8-Bit Monaural Data (2)) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1153 of 3092 SH7268 Group, SH7269 Group Section 22 Serial I/O with FIFO (3) 16-bit Monaural Data Falling edge sampling, slot No.0 used for transmit and receive data, and frame length = 64 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD L-channel data SIOFRxD Slot No.0 Slot No.1 Slot No.2 Slot No.3 1-bit delay Specifications: TRMD[1:0]=00 or 10, REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, FL[3:0]=1101 (frame length: 64 bits) TDRA[3:0]=0000, TDRE=0, RDRA[3:0]=0000 RDRE=0, Figure 22.12 Transmit and Receive Timing (16-Bit Monaural Data) (4) 16-bit Stereo Data (1) Falling edge sampling, slot No.0 used for left channel data, slot No.1 used for right channel data, and frame length = 128 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data R-channel data Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 1 bit delay Specifications: TRMD[1:0]=00 or 10,REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, FL[3:0]=1110 (frame length: 128 bits), TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001 RDRE=1, Figure 22.13 Transmit and Receive Timing (16-Bit Stereo Data (1)) Page 1154 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 22 Serial I/O with FIFO 16-bit Stereo Data (2) Falling edge sampling, slot No.0 used for left channel data, slot No.2 used for right channel data, and frame length = 128 bits 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data Slot No.0 R-channel data Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7 1 bit delay Specifications: TRMD[1:0]=00 or 10, REDG=1, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, FL[3:0]=1110 (frame length: 128 bits) TDRA[3:0]=0010, TDRE=1, RDRA[3:0]=0010 RDRE=1, Figure 22.14 Transmit and Receive Timing (16-Bit Stereo Data (2)) (6) Synchronization-Pulse Output Mode at End of Each Slot (SYNCAT Bit = 1) Falling edge sampling, slot No.0 used for left channel data, slot No.1 used for right-channel data, and frame length = 128 bits In this mode, valid data must be set to slot No. 0. In addition, make sure that valid data is transmitted/received or transmitted. 1 frame SIOFSCK SIOFSYNC SIOFTxD SIOFRxD L-channel data R-channel data Slot No.0 Slot No.1 Slot No.2 Slot No.3 Specifications: TRMD[1:0]=00 or 10,REDG=0, TDLA[3:0]=0000, TDLE=1, RDLA[3:0]=0000, RDLE=1, SYNCAT=1 Slot No.4 Slot No.5 Slot No.6 Slot No.7 FL[3:0]=1110 (frame length: 128 bits), TDRA[3:0]=0001, TDRE=1, RDRA[3:0]=0001, RDRE=1, Figure 22.15 Transmit and Receive Timing (16-Bit Stereo Data) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1155 of 3092 Section 22 Serial I/O with FIFO Page 1156 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Section 23 Controller Area Network 23.1 Summary 23.1.1 Overview This document primarily describes the programming interface for the controller area network (Renesas CAN Time Trigger Level 1) module. It serves to facilitate the hardware/software interface so that engineers involved in this module implementation can ensure the design is successful. Deep standby mode can be canceled by change on CRxn (PC5, PC7, PJ20, PJ22) pin. For details, refer to section 49, Power-Down Modes. 23.1.2 Scope The CAN Data Link Controller function is not described in this document. It is the responsibility of the reader to investigate the CAN Specification Document (see references). The interfaces from the CAN Controller are described, in so far as they pertain to the connection with the User Interface. The programming model is described in some detail. It is not the intention of this document to describe the implementation of the programming interface, but to simply present the interface to the underlying CAN functionality. The document places no constraints upon the implementation of this module in terms of process, packaging or power supply criteria. These issues are resolved where appropriate in implementation specifications. 23.1.3 Audience In particular this document provides the design reference for software authors who are responsible for creating a CAN application using this module. In the creation of this module user interface LSI engineers must use this document to understand the hardware requirements. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1157 of 3092 Section 23 Controller Area Network 23.1.4 SH7268 Group, SH7269 Group References 1. CAN Specification Version 2.0 part A, Robert Bosch GmbH, 1991 2. CAN Specification Version 2.0 part B, Robert Bosch GmbH, 1991 3. Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany, 1997 4. Road vehicles - Controller area network (CAN): Part 1: Data link layer and physical signalling (ISO-11898-1, 2003) 5. Road vehicles - Controller area network (CAN): Part 4: Time triggered communication (ISO11898-4, 2004) 23.1.5                     Features Supports CAN specification 2.0B Bit timing compliant with ISO-11898-1 32 Mailbox version Clock frequency: Up to 33.33 MHz 31 programmable Mailboxes for transmit / receive + 1 receive-only mailbox Sleep mode for low power consumption and automatic recovery from sleep mode by detecting CAN bus activity Programmable receive filter mask (standard and extended identifier) supported by all Mailboxes Programmable CAN data rate up to 1MBit/s Transmit message queuing with internal priority sorting mechanism against the problem of priority inversion for real-time applications Data buffer access without SW handshake requirement in reception Flexible micro-controller interface Flexible interrupt structure 16-bit free running timer with flexible clock sources and pre-scaler, 3 Timer Compare Match Registers 6-bit Basic Cycle Counter for Time Trigger Transmission Timer Compare Match Registers with interrupt generation Timer counter clear / set capability Registers for Time-Trigger: Local_Time, Cycle_time, Ref_Mark, Tx_Enable Window, Ref_Trigger_Offset Flexible TimeStamp at SOF for both transmission and reception supported Time-Trigger Transmission, Periodic Transmission supported (on top of Event Trigger Transmission) Basic Cycle value can be embedded into a CAN frame and transmitted Page 1158 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 23.2 Section 23 Controller Area Network Architecture This module device offers a flexible and sophisticated way to organise and control CAN frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox, Mailbox Control, Timer, and CAN Interface. The figure below shows the block diagram of the Module. The bus interface timing is designed according to the peripheral bus I/F required for each product. CRxn CTxn CAN Interface REC Transmit Buffer BCR Receive Buffer Control Signals MCR IRR GSR IMR TTCR0 CMAX_TEW RFTROFF TSR CCR TCNTR CYCTR RFMK TCMR0 TCMR1 TCMR2 TTTSEL 16-bit Timer 32-bit internal Bus System Micro Processor Interface 16-bit peripheral bus TEC Can Core Status Signals TXPR TXACK TXCR ABACK RXPR RFPR MBIMR UMSR Mailbox Control Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 Mailbox16 Mailbox17 Mailbox18 Mailbox19 Mailbox20 Mailbox21 Mailbox22 Mailbox23 Mailbox24 Mailbox25 Mailbox26 Mailbox27 Mailbox28 Mailbox29 Mailbox30 Mailbox31 control0 LAFM DATA Mailbox 0 to 31 (RAM) Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 Mailbox16 Mailbox17 Mailbox18 Mailbox19 Mailbox20 Mailbox21 Mailbox22 Mailbox23 Mailbox24 Mailbox25 Mailbox26 Mailbox27 Mailbox28 Mailbox29 Mailbox30 Mailbox31 control1 Timestamp Tx-Trigger Time TT control Mailbox 0 to 31 (register) [Legend] n = 0 to 2 Figure 23.1 This Module Architecture R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1159 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group Important: LongWord (32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual, LongWord access means the two consecutive accesses.  Micro Processor Interface (MPI) The MPI allows communication between the Renesas CPU and this module’s registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic that detects the CAN bus activities and notifies the MPI and the other parts of this module so that this module can automatically exit the Sleep mode. It contains registers such as MCR, IRR, GSR and IMR.  Mailbox The Mailboxes consists of RAM configured as message buffers and registers. There are 32 Mailboxes, and each mailbox has the following information.  CAN message control (identifier, rtr, ide,etc)  CAN message data (for CAN Data frames)  Local Acceptance Filter Mask for reception  CAN message control (dlc)  Time Stamp for message reception/transmission  3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, AutoTransmission for Remote Request bit, New Message Control bit  Tx-Trigger Time  Mailbox Control The Mailbox Control handles the following functions.  For received messages, compare the IDs and generate appropriate RAM addresses/data to store messages from the CAN Interface into the Mailbox and set/clear appropriate registers accordingly.  To transmit event-triggered messages, run the internal arbitration to pick the correct priority message, and load the message from the Mailbox into the Tx-buffer of the CAN Interface and set/clear appropriate registers accordingly. In the case of time-triggered transmission, compare match of Tx-Trigger time invoke loading the messages.  Arbitrates Mailbox accesses between the CPU and the Mailbox Control.  Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and MBIMR. Page 1160 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  Timer The Timer function is the functional entity, which provides this module with support for transmitting messages at a specific time frame and recording the result. The Timer is a 16-bit free running up counter which can be controlled by the CPU. It provides one 16-bit Compare Match Register to compare with Local Time and two 16-bit ones to compare with Cycle Time. The Compare Match Registers can generate interrupt signals and clear the Counter. The clock period of this Timer offers a wide selection derived from the system clock or can be programmed to be incremented with one nominal bit timing of CAN Bus. Contains registers such as TCNTR, TTCR0, CMAX_TEW, RFTROFF, TSR, CCR, CYCTR, RFMK, TCMR0, TCMR1, TCMR2 and TTTSEL.  CAN Interface This block conforms to the requirements for a CAN Bus Data Link Controller which is specified in Ref. [2, 4]. It fulfils all the functions of a standard DLC as specified by the OSI 7 Layer Reference model. This functional entity also provides the registers and the logic which are specific to a given CAN bus, which includes the Receive Error Counter, Transmit Error Counter, the Bit Configuration Registers and various useful Test Modes. This block also contains functional entities to hold the data received and the data to be transmitted for the CAN Data Link Controller. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1161 of 3092 Section 23 Controller Area Network 23.3 SH7268 Group, SH7269 Group Programming Model - Overview The purpose of this programming interface is to allow convenient, effective access to the CAN bus for efficient message transfer. Please bear in mind that the user manual reports all settings allowed by this module IP. Different use of this module is not allowed. 23.3.1 Memory Map The diagram of the memory map is shown below. Page 1162 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Base address Channel 0: H'FFFE 5000 Channel 1: H'FFFE 5800 Channel 2: H'FFFE D800 Bit 15 Bit 0 H'000 Master Control Register (MCR) H'002 General Status Register(GSR) H'004 Bit Configuration Register 1 (BCR1) H'006 Bit Configuration Register 0 (BCR0) H'008 Interrupt Request Register (IRR) H'00A H'00C Interrupt Mask Register (IMR) Receive Error Counter (REC) Transmit Error Counter (TEC) H'0A0 Timer Compare Match Register 2 (TCMR2) H'0A4 Tx-Trigger Time Selection Register (TTTSEL) H'100 H'020 Transmit Pending Register (TXPR1) H'022 Transmit Pending Register (TXPR0) H'104 Transmit Cancel Register (TXCR1) H'108 Transmit Cancel Register (TXCR0) H'10A Mailbox-0 Control 0 (StdID, ExtID, Rtr, Ide) LAFM H'028 H'02A H'030 H'032 H'038 H'03A H'040 H'042 H'048 H'04A H'050 H'052 H'058 H'05A H'080 Transmit Acknowledge Register (TXACK1) Transmit Acknowledge Register (TXACK0) H'10C H'10E H'110 Abort Acknowledge Register (ABACK1) 0 2 1 Mailbox 0 Data (8 bytes) 3 4 5 6 7 Mailbox-0 Control 1 (NMC, MBC, DLC) Timestamp Abort Acknowledge Register (ABACK0) Receive Pending Register (RXPR1) Receive Pending Register (RXPR0) H'120 H'140 Remote Frame Pending Register (RFPR1) Remote Frame Pending Register (RFPR0) H'160 Mailbox-1 Control/LAFM/Data etc. Mailbox-2 Control/LAFM/Data etc. Mailbox-3 Control/LAFM/Data etc. Mailbox Interrupt Mask Register (MBIMR1) Mailbox Interrupt Mask Register (MBIMR0) Unread Message Status Register (UMSR1) Unread Message Status Register (UMSR0) Timer Trigger Control Register0 (TTCR0) H'082 H'2E0 H'300 Mailbox-15 Control/LAFM/Data etc. Mailbox-16 Control/LAFM/Data etc. Cycle Maximum/Tx-Enable Window Register (CMAX_TEW) H'086 Reference Trigger Offset Register (RFTROFF) H'084 H'088 Timer Status Register (TSR) H'08A Cycle Counter Register (CCR) H'08C Timer Counter Register (TCNTR) H'4A0 Mailbox-29 Control/LAFM/Data etc. H'08E H'090 Cycle Time Register (CYCTR) H'4C0 Mailbox-30 Control/LAFM/Data etc. Reference Mark Register (RFMK) H'4E0 Mailbox-31 Control/LAFM/Data etc. H'092 H'094 H'096 H'098 Timer Compare Match Register 0 (TCMR0) H'09A H'09C Timer Compare Match Register 1 (TCMR1) H'09E Figure 23.2 Memory Map The locations not used (between H'000 and H'4F3) are reserved and cannot be accessed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1163 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.3.2 Mailbox Structure Mailboxes play a role as message buffers to transmit/receive CAN frames. Each Mailbox is comprised of 3 identical storage fields that are 1): Message Control, 2): Local Acceptance Filter Mask, 3): Message Data. In addition some Mailboxes contain the following extra Fields: 4): Time Stamp, 5): Time Trigger configuration and 6): Time Trigger Control. The following table shows the address map for the control, LAFM, data, timestamp, Transmission Trigger Time and Time Trigger Control addresses for each mailbox. Address LAFM Data Control1 Time Stamp Trigger Time TT control Mailbox 4 bytes 4 bytes 8 bytes 2 bytes 2 bytes 2 bytes 2 bytes 0 100 – 103 (Receive Only) 104– 107 108 – 10F 110 – 111 112 – 113 No No 1 120 – 123 124 – 127 128 – 12F 130 – 131 132 – 133 No No 2 140 – 143 144 – 147 148 – 14F 150 – 151 152 – 153 No No 3 160 – 163 164 – 167 168 – 16F 170 – 171 172 – 173 No No 4 180 – 183 184 – 187 188 – 18F 190 – 191 192 – 193 No No 5 1A0 – 1A3 1A4 – 1A7 1A8 – 1AF 1B0 – 1B1 1B2 – 1B3 No No 6 1C0 – 1C3 1C4 – 1C7 1C8 – 1CF 1D0 – 1D1 1D2 – 1D3 No No 7 1E0 – 1E3 1E4 – 1E7 1E8 – 1EF 1F0 – 1F1 1F2 – 1F3 No No 8 200 – 203 204 – 207 208 – 20F 210 – 211 212 – 213 No No 9 220 – 223 224 – 227 228 – 22F 230 – 231 232 – 233 No No 10 240 – 243 244 – 247 248 – 24F 250 – 251 252 – 253 No No 11 260 – 263 264 – 267 268 – 26F 270 – 271 272 – 273 No No 12 280 – 283 284 – 287 288 – 28F 290 – 291 292 – 293 No No 13 2A0 – 2A3 2A4 – 2A7 2A8 – 2AF 2B0 – 2B1 2B2 – 2B3 No No 14 2C0 – 2C3 2C4 – 2C7 2C8 – 2CF 2D0 – 2D1 2D2 – 2D3 No No 15 2E0 – 2E3 2E4 – 2E7 2E8 – 2EF 2F0 – 2F1 2F2 – 2F3 No No 16 300 – 303 304 – 307 308 – 30F 310 – 311 No No No 17 320 – 323 324 – 327 328 – 32F 330 – 331 No No No 18 340 – 343 344 – 347 348 – 34F 350 – 351 No No No Control0 Page 1164 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Address LAFM Data Control1 Time Stamp Trigger Time TT control Mailbox 4 bytes 4 bytes 8 bytes 2 bytes 2 bytes 2 bytes 2 bytes 19 360 – 363 364 – 367 368 – 36F 370 – 371 No No No 20 380 – 383 384 – 387 388 – 38F 390 – 391 No No No 21 3A0 – 3A3 3A4 – 3A7 3A8 – 3AF 3B0 – 3B1 No No No 22 3C0 – 3C3 3C4 – 3C7 3C8 – 3CF 3D0 – 3D1 No No No 23 3E0 – 3E3 3E4 – 3E7 3E8 – 3EF 3F0 – 3F1 No No No 24 400 – 403 404 – 407 408 – 40F 410 – 411 No 414 – 415 416 – 417 25 420 – 423 424 – 427 428 – 42F 430 – 431 No 434 – 435 436 – 437 26 440 – 443 444 – 447 448 – 44F 450 – 451 No 454 – 455 456 – 457 27 460 – 463 464 – 467 468 – 46F 470 – 471 No 474 – 475 476 – 477 28 480 – 483 484 – 487 488 – 48F 490 – 491 No 494 – 495 496 – 497 29 4A0 – 4A3 4A4 – 4A7 4A8 – 4AF 4B0 – 4B1 No 30 4C0 – 4C3 4C4 – 4C7 4C8 – 4CF 4D0 – 4D1 4D2 – 4D3 4D4 – 4D5 No Control0 4B4 – 4B5 4B6 – 4B7 (Local Time) 31 4E0 – 4E3 4E4 – 4E7 4E8 – 4EF 4F0 – 4F1 4F2 – 4F3 No No (Local Time) Mailbox-0 is a receive-only box, and all the other Mailboxes can operate as both receive and transmit boxes, dependant upon the MBC (Mailbox Configuration) bits in the Message Control. The following diagram shows the structure of a Mailbox in detail. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1165 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Table 23.1 Roles of Mailboxes Event Trigger Time Trigger Remark Tx Rx Tx Rx TimeStamp Tx-Trigger Time MB31 Settable Settable  Time reference reception Available  MB30 Settable Settable Time reference Reception in Available transmission in time slave mode time master mode MB29 - 24 Settable Settable Settable Settable  Available MB23 - 16 Settable Settable  (ET) Settable   MB15 - 1 Settable Settable  (ET) Settable Available  MB0  Settable  Settable Available  Available (ET) shows that it works during merged arbitrating window, after completion of time-triggered transmission. MB0 (reception MB with timestamp) Byte: 8-bit access, Word: 16-bit access, LW (LongWord) : 32-bit access Data Bus Address H'100 + N*32 15 14 13 IDE RTR 0 12 11 10 9 8 7 6 5 4 3 2 STDID[10:0] 1 0 EXTID[17:16] Word/LW EXTID_ LAFM[17:16] Word/LW EXTID[15:0] H'102 + N*32 IDE_ H'104 + N*32 LAFM H'106 + N*32 0 0 Access Size MSG_DATA_1 Byte/Word/LW H'10A + N*32 MSG_DATA_2 MSG_DATA_3 Byte/Word H'10C + N*32 MSG_DATA_4 MSG_DATA_5 Byte/Word/LW H'10E + N*32 MSG_DATA_6 MSG_DATA_7 Byte/Word 0 0 NMC 0 0 0 MBC[2:0] LAFM Word EXTID_LAFM[15:0] MSG_DATA_0 (first Rx/Tx Byte) 0 0 0 DLC[3:0] TimeStamp[15:0] (CYCTR[15:0] or CCR[5:0]/CYCTR[15:6] at SOF) H'112 + N*32 Control 0 Word STDID_LAFM[10:0] H'108 + N*32 H'110 + N*32 Field Name Data Byte/Word Control 1 Word TimeStamp Access Size Field Name MBC[1] is fixed to "1" MB15 to 1 (MB with timestamp) Data Bus Address H'100 + N*32 15 14 13 IDE RTR 0 0 0 12 11 10 9 8 7 6 5 4 3 STDID[10:0] 2 1 0 EXTID[17:16] Word/LW EXTID_ LAFM[17:16] Word/LW EXTID[15:0] H'102 + N*32 IDE_ H'104 + N*32 LAFM H'106 + N*32 Byte/Word/LW H'108 + N*32 MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_1 MSG_DATA_2 MSG_DATA_3 Byte/Word H'10C + N*32 MSG_DATA_4 MSG_DATA_5 Byte/Word/LW H'10E + N*32 MSG_DATA_6 MSG_DATA_7 Byte/Word 0 H'112 + N*32 0 NMC ATX DART MBC[2:0] 0 LAFM Word EXTID_LAFM[15:0] H'10A + N*32 H'110 + N*32 Control 0 Word STDID_LAFM[10:0] 0 0 0 DLC[3:0] TimeStamp[15:0] (CYCTR[15:0] or CCR[5:0]/CYCTR[15:6] at SOF) Data Byte/Word Control 1 Word TimeStamp Figure 23.3 Mailbox-N Structure Page 1166 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network MB23 to 16 (MB without timestamp) Address H'100 + N*32 Data Bus 15 14 13 IDE RTR 0 12 11 10 9 8 7 6 5 4 3 2 STDID[10:0] 1 0 EXTID[17:16] EXTID[15:0] H'102 + N*32 IDE_ H'104 + N*32 LAFM H'106 + N*32 0 0 Access Size Word EXTID_ LAFM[17:16] STDID_LAFM[10:0] MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_1 H'10A + N*32 MSG_DATA_2 MSG_DATA_3 Byte/Word H'10C + N*32 MSG_DATA_4 MSG_DATA_5 Byte/Word/LW MSG_DATA_7 Byte/Word H'110 + N*32 MSG_DATA_6 0 0 NMC ATX DART MBC[2:0] 0 0 0 0 6 5 4 LAFM Byte/Word/LW H'108 + N*32 H'10E + N*32 Control 0 Word/LW Word EXTID_LAFM[15:0] Field Name Word/LW DLC[3:0] Data Byte/Word Control 1 Access Size Field Name MB29 to 24 (Time-Triggered Transmission in Time Trigger mode) Address H'100 + N*32 Data Bus 15 14 13 IDE RTR 0 0 0 12 11 10 9 8 7 3 2 STDID[10:0] 1 0 EXTID[17:16] Word/LW EXTID_ LAFM[17:16] Word/LW EXTID[15:0] H'102 + N*32 IDE_ H'104 + N*32 LAFM H'106 + N*32 Word STDID_LAFM[10:0] Word EXTID_LAFM[15:0] MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_1 H'10A + N*32 MSG_DATA_2 MSG_DATA_3 Byte/Word H'10C + N*32 MSG_DATA_4 MSG_DATA_5 Byte/Word/LW H'10E + N*32 MSG_DATA_6 MSG_DATA_7 Byte/Word 0 0 NMC ATX DART MBC[2:0] 0 0 0 DLC[3:0] 0 LAFM Byte/Word/LW H'108 + N*32 H'110 + N*32 Control 0 Byte/Word Data Control 1 H'112 + N*32 reserved - - H'114 + N*32 Tx-Triggered Time (TTT) Word Trigger Time Word TT control H'116 + N*32 TTW[1:0] offset 0 0 0 0 0 Rep_Factor Figure 23.3 Mailbox-N Structure (continued) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1167 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network MB30 (Time Reference Transmitssion in Time Trigger mode) Data Bus Address H'100 + N*32 15 14 13 IDE RTR 0 12 11 10 9 8 7 6 5 4 3 2 STDID[10:0] H'102 + N*32 1 0 EXTID[17:16] EXTID[15:0] IDE_ H'104 + N*32 LAFM H'106 + N*32 0 0 Access Size Word/LW STDID_LAFM[10:0] Word/LW MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_1 H'10A + N*32 MSG_DATA_2 MSG_DATA_3 Byte/Word H'10C + N*32 MSG_DATA_4 MSG_DATA_5 Byte/Word/LW MSG_DATA_6 0 0 NMC Byte/Word/LW MSG_DATA_7 ATX DART MBC[2:0] 0 LAFM Word H'108 + N*32 H'110 + N*32 Control 0 Word EXTID_ LAFM[17:16] EXTID_LAFM[15:0] H'10E + N*32 Field Name 0 0 Data Byte/Word DLC[3:0] 0 Byte/Word Control 1 H'112 + N*32 TimeStamp[15:0] (TCNTR at SOF) Word TimeStamp H'114 + N*32 Tx-Triggered Time (TTT) as Time Reference Word Trigger Time Access Size Field Name MB31 (Time Reference Reception in Time Trigger mode) Address H'100 + N*32 Data Bus 15 14 13 IDE RTR 0 12 11 10 9 8 6 5 4 STDID[10:0] 3 2 1 0 EXTID[17:16] Word/LW EXTID_ LAFM[17:16] Word/LW EXTID[15:0] H'102 + N*32 H'104 + N*32 7 IDE_ LAFM 0 0 Word STDID_LAFM[10:0] H'106 + N*32 Word EXTID_LAFM[15:0] H'108 + N*32 MSG_DATA_0 (first Rx/Tx Byte) MSG_DATA_1 H'10A + N*32 MSG_DATA_2 MSG_DATA_3 Byte/Word MSG_DATA_4 MSG_DATA_5 Byte/Word/LW H'10E + N*32 MSG_DATA_6 MSG_DATA_7 Byte/Word 0 H'112 + N*32 0 NMC ATX DART MBC[2:0] 0 0 0 0 LAFM Byte/Word/LW H'10C + N*32 H'110 + N*32 Control 0 DLC[3:0] TimeStamp[15:0] (TCNTR at SOF) Data Byte/Word Control 1 Word TimeStamp Figure 23.3 Mailbox-N Structure (continued) Notes: 1. All bits shadowed in grey are reserved and must be written LOW. The value returned by a read may not always be ‘0’ and should not be relied upon. 2. ATX and DART are not supported by Mailbox-0, and the MBC setting of Mailbox-0 is limited. 3. ID Reorder (MCR15) can change the order of STDID, RTR, IDE and EXTID of both message control and LAFM. Page 1168 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 23 Controller Area Network Message Control Field STDID[10:0]: These bits set the identifier (standard identifier) of data frames and remote frames. EXTID[17:0]: These bits set the identifier (extended identifier) of data frames and remote frames. RTR (Remote Transmission Request bit): Used to distinguish between data frames and remote frames. This bit is overwritten by received CAN Frames depending on Data Frames or Remote Frames. Important: Please note that, when ATX bit is set with the setting MBC = 001(bin), the RTR bit will never be set. When a Remote Frame is received, the CPU can be notified by the corresponding RFPR set or IRR[2] (Remote Frame Receive Interrupt), however, as this module needs to transmit the current message as a Data Frame, the RTR bit remains unchanged. Important: In order to support automatic answer to remote frame when MBC = 001 (bin) is used and ATX = 1 the RTR flag must be programmed to zero to allow data frame to be transmitted. Note: when a Mailbox is configured to send a remote frame request the DLC used for transmission is the one stored into the Mailbox. RTR Description 0 Data frame 1 Remote frame IDE (Identifier Extension bit): Used to distinguish between the standard format and extended format of CAN data frames and remote frames. IDE Description 0 Standard format 1 Extended format R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1169 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network  Mailbox-0 Bit: Initial value: R/W: 15 14 13 12 11 0 0 NMC 0 0 0 R 0 R 0 R/W 0 R 0 R 10 9 8 MBC[2:0] 1 R/W 7 6 5 4 0 0 0 0 3 2 1 0 DLC[3:0] 1 R 1 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 R 0 R 0 R 0 R Note: MBC[1] of MB0 is always "1".  Mailbox-31 to 1 Bit: Initial value: R/W: 15 14 13 12 11 0 0 NMC ATX DART 0 R 0 R 0 R/W 0 R/W 0 R/W 10 MBC[2:0] 1 R/W 1 R/W 1 R/W DLC[3:0] 0 R/W 0 R/W 0 R/W 0 R/W NMC (New Message Control): When this bit is set to '0', the Mailbox of which the RXPR or RFPR bit is already set does not store the new message but maintains the old one and sets the UMSR correspondent bit. When this bit is set to '1', the Mailbox of which the RXPR or RFPR bit is already set overwrites with the new message and sets the UMSR correspondent bit. Important: Please note that if a remote frame is overwritten with a data frame or vice versa could be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this case the RTR bit within the Mailbox Control Field should be relied upon. Important: Please note that when the Time Triggered mode is used NMC needs to be set to ‘1’ for Mailbox 31 to allow synchronization with all incoming reference messages even when RXPR[31] is not cleared. NMC Description 0 Overrun mode (Initial value) 1 Overwrite mode Page 1170 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network ATX (Automatic Transmission of Data Frame): When this bit is set to ‘1’ and a Remote Frame is received into the Mailbox DLC is stored. Then, a Data Frame is transmitted from the same Mailbox using the current contents of the message data and updated DLC by setting the corresponding TXPR automatically. The scheduling of transmission is still governed by ID priority or Mailbox priority as configured with the Message Transmission Priority control bit (MCR.2). In order to use this function, MBC[2:0] needs to be programmed to be ‘001’ (Bin). When a transmission is performed by this function, the DLC (Data Length Code) to be used is the one that has been received. Application needs to guarantee that the DLC of the remote frame correspond to the DLC of the data frame requested. Important: When ATX is used and MBC = 001 (Bin) the filter for the IDE bit cannot be used since ID of remote frame has to be exactly the same as that of data frame as the reply message. Important: Please note that, when this function is used, the RTR bit will never be set despite receiving a Remote Frame. When a Remote Frame is received, the CPU will be notified by the corresponding RFPR set, however, as this module needs to transmit the current message as a Data Frame, the RTR bit remains unchanged. Important: Please note that in case of overrun condition (UMSR flag set when the Mailbox has its NMC = 0) the message received is discarded. In case a remote frame is causing overrun into a Mailbox configured with ATX = 1, the transmission of the corresponding data frame may be triggered only if the related PFPR flag is cleared by the CPU when the UMSR flag is set. In such case PFPR flag would get set again. ATX Description 0 Automatic Transmission of Data Frame disabled (Initial value) 1 Automatic Transmission of Data Frame enabled DART (Disable Automatic Re-Transmission): When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. In effect, when this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is set to '0', this module tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR. DART Description 0 Re-transmission enabled (Initial value) 1 Re-Transmission disabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1171 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network MBC[2:0] (Mailbox Configuration): These bits configure the nature of each Mailbox as follows. When MBC = 111 (Bin), the Mailbox is inactive, i.e., it does not receive or transmit a message regardless of TXPR or other settings. The MBC = '110', '101' and '100' settings are prohibited. When the MBC is set to any other value, the LAFM field becomes available. Please don't set TXPR when MBC is set as reception as there is no hardware protection, and TXPR will remain set. MBC[1] of Mailbox-0 is fixed to "1" by hardware. This is to ensure that MB0 cannot be configured to transmit Messages. Data Frame MBC[2] MBC[1] MBC[0] Transmit Remote Frame Transmit Data Frame Receive Remote Frame Receive 0 0 0 Yes Yes No No   0 0 1 Yes Yes No Yes 0 1 0 No No Yes Yes 0 1 1 No No Yes No        1 0 0 Setting prohibited 1 0 1 Setting prohibited 1 1 0 Setting prohibited 1 1 1 Mailbox inactive (Initial value) Notes: * Remarks Not allowed for Mailbox-0 Time-Triggered transmission can be used Can be used with ATX* Not allowed for Mailbox-0 LAFM can be used Allowed for Mailbox-0 LAFM can be used Allowed for Mailbox-0 LAFM can be used In order to support automatic retransmission, RTR shall be "0" when MBC = 001(bin) and ATX = 1. When ATX = 1 is used the filter for IDE must not be used. Page 1172 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network DLC[3:0] (Data Length Code): These bits encode the number of data bytes from 0,1, 2, … 8 that will be transmitted in a data frame. Please note that when a remote frame request is transmitted the DLC value to be used must be the same as the DLC of the data frame that is requested. DLC[3] DLC[2] DLC[1] DLC[0] Description 0 0 0 0 Data Length = 0 bytes (Initial value) 0 0 0 1 Data Length = 1 byte 0 0 1 0 Data Length = 2 bytes 0 0 1 1 Data Length = 3 bytes 0 1 0 0 Data Length = 4 bytes 0 1 0 1 Data Length = 5 bytes 0 1 1 0 Data Length = 6 bytes 0 1 1 1 Data Length = 7 bytes 1 x x x Data Length = 8 bytes (2) Local Acceptance Filter Mask (LAFM) This area is used as Local Acceptance Filter Mask (LAFM) for receive boxes. LAFM: When MBC is set to 001, 010, 011(Bin), this field is used as LAFM Field. It allows a Mailbox to accept more than one identifier. The LAFM is comprised of two 16-bit read/write areas as follows. 15 IDE_ H'104 + N*32 LAFM 14 13 0 0 H'106 + N*32 12 11 10 9 8 7 6 5 4 3 2 STDID_LAFM[10:0] EXTID_LAFM[15:0] 1 0 EXTID_ LAFM[17:16] Word/LW LAFM Field Word Figure 23.4 Acceptance filter If a bit is set in the LAFM, then the corresponding bit of a received CAN identifier is ignored when this module searches a Mailbox with the matching CAN identifier. If the bit is cleared, then the corresponding bit of a received CAN identifier must match to the STDID/IDE/EXTID set in the mailbox to be stored. The structure of the LAFM is same as the message control in a Mailbox. If this function is not required, it must be filled with '0'. Important: This module starts to find a matching identifier from Mailbox-31 down to Mailbox-0. As soon as this module finds one matching, it stops the search. The message will be stored or not depending on the NMC and RXPR/RFPR flags. This means that, even using LAFM, a received message can only be stored into 1 Mailbox. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1173 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group Important: When a message is received and a matching Mailbox is found, the whole message is stored into the Mailbox. This means that, if the LAFM is used, the STDID, RTR, IDE and EXTID may differ to the ones originally set as they are updated with the STDID, RTR, IDE and EXTID of the received message. STD_LAFM[10:0] — Filter mask bits for the CAN base identifier [10:0] bits. STD_LAFM[10:0] Description 0 Corresponding STD_ID bit is cared 1 Corresponding STD_ID bit is "don't cared" EXT_LAFM[17:0] — Filter mask bits for the CAN Extended identifier [17:0] bits. EXT_LAFM[17:0] Description 0 Corresponding EXT_ID bit is cared 1 Corresponding EXT_ID bit is "don't cared" IDE_LAFM — Filter mask bit for the CAN IDE bit. IDE_LAFM Description 0 Corresponding IDE bit is cared 1 Corresponding IDE bit is "don't cared" (3) Message Data Fields Storage for the CAN message data that is transmitted or received. MSG_DATA[0] corresponds to the first data byte that is transmitted or received. The bit order on the CAN bus is bit 7 through to bit 0. When CMAX!= 3'b111/MBC[30] = 3'b000 and TXPR[30] is set, Mailbox-30 is configured as transmission of time reference. Its DLC must be greater than 0 and its RTR must be zero (as specified for TTCAN Level 1) so that the Cycle_count (CCR register) is embedded in the first byte of the data field instead of MSG_DATA_0[5:0] when this Mailbox starts transmission. This function shall be used when this module is enabled to work in TTCAN mode to perform a Potential Time Master role to send the Time reference message. MSG_DATA_0[7:6] is still transmitted as stored in the Mailbox. User can set MSG_DATA_0[7] when a Next_is_Gap needs to be transmitted. Page 1174 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Please note that the CCR value is only embedded on the frame transmitted but not stored back into Mailbox 30. When CMAX!= 3'b111, MBC[31] = 3'b011 and TXPR[31] is cleared, Mailbox-31 is configured as reception of time reference. When a valid reference message is received (DLC > 0) this module performs internal synchronisation (modifying its RFMK and basic cycle CCR). MB30 - 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSG_DATA_1 Next_is_Gap/Cycle_Counter (first Rx/Tx Byte) H'108 + N*32 0 Byte/Word/LW H'10A + N*32 MSG_DATA_2 MSG_DATA_3 Byte/Word H'10C + N*32 MSG_DATA_4 MSG_DATA_5 Byte/Word/LW H'10E + N*32 MSG_DATA_6 MSG_DATA_7 Byte/Word Data Figure 23.5 Message Data Field (4) Timestamp Storage for the Timestamp recorded on messages for transmit/receive. The Timestamp will be a useful function to monitor if messages are received/transmitted within expected schedule.  Timestamp Bit: 15 14 13 12 11 10 TS15 TS14 TS13 TS12 TS11 TS10 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 9 8 7 6 5 4 3 2 1 0 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Message Receive: For received messages of Mailbox-15 to 0, Timestamp always captures the CYCTR (Cycle Time Register) value or Cycle_Counter CCR[5:0] + CYCTR[15:6] value, depending on the programmed value in the bit 14 of TTCR0 (Timer Trigger Control Register 0) at SOF. For messages received into Mailboxes 30 and 31, Timestamp captures the TCNTR (Timer Counter Register) value at SOF. Message Transmit: For transmitted messages of Mailbox-15 to 1, Timestamp always captures the CYCTR (Cycle Time Register) value or Cycle_Counter CCR[5:0] + CYCTR[15:6] value, depending on the programmed value in the bit 14 of TTCR0 (Timer Trigger Control Register 0), at SOF. For messages transmitted from Mailboxes30 and 31, Timestamp captures the TCNTR (Timer Counter Register) value at SOF. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1175 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Important: Please note that the TimeStamp is stored in a temporary register. Only after a successful transmission or reception the value is then copied into the related Mailbox field. The TimeStamp may also be updated if the CPU clears RXPR[N]/RFPR[N] at the same time that UMSR[N] is set in overrun, however it can be read properly before clearing RXPR[N]/RFPR[N]. (5) Tx-Trigger Time (TTT) and Time Trigger control For Mailbox-29 to 24, when MBC is set to 000 (Bin) in time trigger mode (CMAX!= 3'b111), TxTrigger Time works as Time_Mark to determine the boundary between time windows. The TTT and TT control are comprised of two 16-bit read/write areas as follows. Mailbox-30 doesn't have TT control and works as Time_Ref. Mailbox 30 to 24 can be used for reception if not used for transmission in TT mode. However they cannot join the event trigger transmission queue when the TT mode is used.  Tx-Trigger Time Bit: 15 14 13 12 11 10 TTT15 TTT14 TTT13 TTT12 TTT11 TTT10 Initial value: R/W: 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0 TTT9 TTT8 TTT7 TTT6 TTT5 TTT4 TTT3 TTT2 TTT1 TTT0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R 0 R 0 R 0 R 0 R  Time Trigger control Bit: 15 14 13 TTW[1:0] Initial value: R/W: 0 R/W Offset[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W rep_factor[2:0] 0 R/W 0 R/W 0 R/W The following figure shows the differences between all Mailboxes supporting Time Triggered mode. MB29 to 24 15 14 13 12 11 H'114 + N*32 H'116 + N*32 10 9 8 7 6 5 4 3 2 1 0 Tx-Trigger Time (Cycle Time) Offset[5:0] TTW[1:0] 0 0 0 0 0 rep_factor[2:0] 7 6 5 4 3 2 Word Trigger Time Word TT control Word Trigger Time MB30 15 H'114 + N*32 14 13 12 11 10 9 8 1 Tx-Trigger Time (Cycle Time) 0 Figure 23.6 Tx-Trigger control field Page 1176 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  TTW[1:0] (Time Trigger Window): These bits show the attribute of time windows. Please note that once a merged arbitrating window is opened by TTW = 2'b10, the window must be closed by TTW = 2'b11. Several messages with TTW = 2'b10 may be used within the start and the end of a merged arbitrating window. TTW[1] TTW[0] Description 0 0 Exclusive window (initial value) 0 1 Arbitrating window 1 0 Start of merged arbitrating window 1 1 End of merged arbitrating window The first 16-bit area specifies the time that triggers the transmission of the message in cycle time. The second 16-bit area specifies the basic cycle in the system matrix where the transmission must start (Offset) and the frequency for periodic transmission. When the internal TTT register matches to the CYCTR value, and the internal Offset matches to CCR value transmission is attempted from the corresponding Mailbox. In order to enable this function, the CMAX (Cycle Maximum Register) must be set to a value different from 3'b111, the Timer (TCNTR) must be running (TTCR0 bit15 = 1), the corresponding MBC must be set to 3'b000 and the corresponding TXPR bit must be set. Once TXPR is set by S/W, this module does not clear the corresponding TXPR bit (among Mailbox-30 to 24) to carry on performing the periodic transmission. In order to stop the periodic transmission, TXPR must be cleared by TXCR. Please note that in this case it is possible that both TXACK and ABACK are set for the same Mailbox if TXACK is not cleared right after completion of transmission. Please refer to figure 23.7. MBI is under transmission TXPRI is kept set in Time Trigger Mode TXPRI TXACKI Both TXACKI and ABACKI are set without clearing TXACKI ABACKI TXCRI cancellation is accepted Figure 23.7 TXACK and ABACK in Time Trigger Transmission R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1177 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group Please note that for Mailbox 30 TTW is fixed to '01', Offset to '00' and rep_factor to ‘0’.The following tables report the combinations for the rep_factor and the offset. Rep_factor Description 3'b000 Every basic cycle (initial value) 3'b001 Every two basic cycle 3'b010 Every four basic cycle 3'b011 Every eight basic cycle 3'b100 Every sixteen basic cycle 3'b101 Every thirty two basic cycle 3'b110 Every sixty four basic cycle (once in system matrix) 3'b111 Reserved The Offset Field determines the first cycle in which a Time Triggered Mailbox may start transmitting its Message. Offset Description 6'b000000 Initial Offset = 1st Basic Cycle (initial value) 6'b000001 Initial Offset = 2nd Basic Cycles 6'b000010 Initial Offset = 3rd Basic Cycles 6'b000011 Initial Offset = 4th Basic Cycles 6'b000100 Initial Offset = 5th Basic Cycles   6'b111110 Initial Offset = 63rd Basic Cycles 6'b111111 Initial Offset = 64th Basic Cycles The following relation must be maintained: Cycle_Count_Maximum + 1 >= Repeat_Factor > Offset Cycle_Count_Maximum = 2CMAX - 1 Repeat_Factor = 2rep_factor Page 1178 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network CMAX, Repeat_Factor, and Offset are register values System Matrix CCR = 0 CCR = 1 offset = 1 rep_factor = 3'b010 (Repeat_Factor = 4) CMAX = 3'b100 (Cycle_Count_Max = 15) CCR = 2 CCR = 3 CCR = 4 CCR = 5 offset = 1 Repeat_Factor CCR = 6 CCR = 7 CCR = 12 CCR = 13 offset = 1 Repeat_Factor CCR = 14 CCR = 15 Figure 23.8 System Matrix Tx-Trigger Times must be set in ascending order such that the difference between them satisfies the following condition. TTT(mailbox i) –1 TTT(mailbox i-1) > TEW + Maximum frame length + 9 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1179 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.3.3 Control Registers The following sections describe control registers. The address is mapped as follow. Important: These registers can only be accessed in Word size (16-bit). Register Name Address Abbreviation Access Size (bits) Master Control Register 000 MCR 16 General Status Register 002 GSR 16 Bit Configuration Register 1 004 BCR1 16 Bit Configuration Register 0 006 BCR0 16 Interrupt Register 008 IRR 16 Interrupt Mask Register 00A IMR 16 Error Counter Register 00C TEC/REC 16 Figure 23.9 Control Registers (1) Master Control Register (MCR) The Master Control Register (MCR) is a 16-bit read/write register that controls this module.  MCR (Address = H'000) Bit: 15 14 MCR15 MCR14 Initial value: R/W: 1 R/W 0 R/W 13 12 11 - - - 0 R 0 R 0 R 10 9 8 TST[2:0] 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 MCR7 MCR6 MCR5 - - MCR2 MCR1 MCR0 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 1 R/W Bit 15 — ID Reorder (MCR15): This bit changes the order of STDID, RTR, IDE and EXTID of both message control and LAFM. Bit15: MCR15 Description 0 This module is the same as HCAN2 1 This module is not the same as HCAN2 (Initial value) Page 1180 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network MCR15 (ID Reorder) = 0 15 H'100 + N*32 14 13 12 11 10 9 8 7 6 5 4 3 RTR STDID[10:0] 0 2 1 0 IDE EXTID[17:16] Word/LW Control 0 EXTID[15:0] H'102 + N*32 H'104 + N*32 Word STDID_LAFM[10:0] 0 0 IDE_ EXTID_LAFM [17:16] LAFM LAFM Field Word EXTID_LAFM[15:0] H'106 + N*32 Word/LW MCR15 (ID Reorder) = 1 H'100 + N*32 15 14 13 IDE RTR 0 12 11 10 9 8 7 6 5 4 3 STDID[10:0] 2 1 0 EXTID[17:16] Word/LW Control 0 EXTID[15:0] H'102 + N*32 H'104 + N*32 IDE_ LAFM 0 0 STDID_LAFM[10:0] Word EXTID_LAFM [17:16] Word/LW LAFM Field EXTID_LAFM[15:0] H'106 + N*32 Word Figure 23.10 ID Reorder This bit can be modified only in reset mode. Bit 14 — Auto Halt Bus Off (MCR14): If both this bit and MCR6 are set, MCR1 is automatically set as soon as this module enters BusOff. Bit14: MCR14 Description 0 This module remains in BusOff for normal recovery sequence (128 x 11 Recessive Bits) (Initial value) 1 This module moves directly into Halt Mode after it enters BusOff if MCR6 is set. This bit can be modified only in reset mode. Bit 13 — Reserved. The written value should always be ‘0’ and the returned value is '0'. Bit 12 — Reserved. The written value should always be ‘0’ and the returned value is '0'. Bit 11 — Reserved. The written value should always be ‘0’ and the returned value is '0'. Bit 10 - 8 — Test Mode (TST[2:0]): This bit enables/disables the test modes. Please note that before activating the Test Mode it is requested to move this module into Halt mode or Reset mode. This is to avoid that the transition to Test Mode could affect a transmission/reception in progress. For details, please refer to section 23.4.1, Test Mode Settings. Please note that the test modes are allowed only for diagnosis and tests and not when this module is used in normal operation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1181 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit10: TST2 Bit9: TST1 Bit8: TST0 Description 0 0 0 Normal Mode (initial value) 0 0 1 Listen-Only Mode (Receive-Only Mode) 0 1 0 Self Test Mode 1 (External) 0 1 1 Self Test Mode 2 (Internal) 1 0 0 Write Error Counter 1 0 1 Error Passive Mode 1 1 0 Setting prohibited 1 1 1 Setting prohibited Bit 7 — Auto-wake Mode (MCR7): MCR7 enables or disables the Auto-wake mode. If this bit is set, this module automatically cancels the sleep mode (MCR5) by detecting CAN bus activity (dominant bit). If MCR7 is cleared this module does not automatically cancel the sleep mode. This module cannot store the message that wakes it up. Note: This bit can be modified only Reset or Halt mode. Bit7: MCR7 Description 0 Auto-wake by CAN bus activity disabled (Initial value) 1 Auto-wake by CAN bus activity enabled Bit 6 — Halt during Bus Off (MCR6): MCR6 enables or disables entering Halt mode immediately when MCR1 is set during Bus Off. This bit can be modified only in Reset or Halt mode. Please note that when Halt is entered in Bus Off the CAN engine is also recovering immediately to Error Active mode. Bit6: MCR6 Description 0 If MCR[1] is set, this module will not enter Halt mode during Bus Off but wait up to end of recovery sequence (Initial value) 1 Enter Halt mode immediately during Bus Off if MCR[1] or MCR[14] are asserted. Page 1182 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 5 — Sleep Mode (MCR5): Enables or disables Sleep mode transition. If this bit is set, while this module is in halt mode, the transition to sleep mode is enabled. Setting MCR5 is allowed after entering Halt mode. The two Error Counters (REC, TEC) will remain the same during Sleep mode. This mode will be exited in two ways: 1. by writing a '0' to this bit position, 2. or, if MCR[7] is enabled, after detecting a dominant bit on the CAN bus. If Auto wake up mode is disabled, this module will ignore all CAN bus activities until the sleep mode is terminated. When leaving this mode this module will synchronise to the CAN bus (by checking for 11 recessive bits) before joining CAN Bus activity. This means that, when the No.2 method is used, this module will miss the first message to receive. CAN transceivers stand-by mode will also be unable to cope with the first message when exiting stand by mode, and the S/W needs to be designed in this manner. In sleep mode only the following registers can be accessed: MCR, GSR, IRR and IMR. Important: This module is required to be in Halt mode before requesting to enter in Sleep mode. That allows the CPU to clear all pending interrupts before entering sleep mode. Once all interrupts are cleared this module must leave the Halt mode and enter Sleep mode simultaneously (by writing MCR[5] = 1 and MCR[1] = 0 at the same time). Bit 5: MCR5 Description 0 This module sleep mode released (Initial value) 1 Transition to this module sleep mode enabled Bit 4 — Reserved. The written value should always be '0' and the returned value is '0'. Bit 3 — Reserved. The written value should always be '0' and the returned value is '0'. Bit 2 — Message Transmission Priority (MCR2): MCR2 selects the order of transmission for pending transmit data. If this bit is set, pending transmit data are sent in order of the bit position in the Transmission Pending Register (TXPR). The order of transmission starts from Mailbox-31 as the highest priority, and then down to Mailbox-1 (if those mailboxes are configured for transmission). Please note that this feature cannot be used for time trigger transmission of the Mailboxes 24 to 30. If MCR2 is cleared, all messages for transmission are queued with respect to their priority (by running internal arbitration). The highest priority message has the Arbitration Field (STDID + IDE bit + EXTID (if IDE = 1) + RTR bit) with the lowest digital value and is transmitted first. The internal arbitration includes the RTR bit and the IDE bit (internal arbitration works in the same R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1183 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group way as the arbitration on the CAN Bus between two CAN nodes starting transmission at the same time). This bit can be modified only in Reset or Halt mode. Bit 2: MCR2 Description 0 Transmission order determined by message identifier priority (Initial value) 1 Transmission order determined by mailbox number priority (Mailbox-31  Mailbox-1) Bit 1—Halt Request (MCR1): Setting the MCR1 bit causes the CAN controller to complete its current operation and then enter Halt mode (where it is cut off from the CAN bus). This module remains in Halt Mode until the MCR1 is cleared. During the Halt mode, the CAN Interface does not join the CAN bus activity and does not store messages or transmit messages. All the user registers (including Mailbox contents and TEC/REC) remain unchanged with the exception of IRR0 and GSR4 which are used to notify the halt status itself. If the CAN bus is in idle or intermission state regardless of MCR6, this module will enter Halt Mode within one Bit Time. If MCR6 is set, a halt request during Bus Off will be also processed within one Bit Time. Otherwise the full Bus Off recovery sequence will be performed beforehand. Entering the Halt Mode can be notified by IRR0 and GSR4. If both MCR14 and MCR6 are set, MCR1 is automatically set as soon as this module enters BusOff. In the Halt mode, this module configuration can be modified with the exception of the Bit Timing setting, as it does not join the bus activity. MCR[1] has to be cleared by writing a '0' in order to rejoin the CAN bus. After this bit has been cleared, this module waits until it detects 11 recessive bits, and then joins the CAN bus. Notes: 1. After issuing a Halt request the CPU is not allowed to set TXPR or TXCR or clear MCR1 until the transition to Halt mode is completed (notified by IRR0 and GSR4). After MCR1 is set this can be cleared only after entering Halt mode or through a reset operation (SW or HW). 2. Transition into or recovery from HALT mode, is only possible if the BCR1 and BCR0 registers are configured to a proper Baud Rate. Bit 1: MCR1 Description 0 Clear Halt request (Initial value) 1 Halt mode transition request Page 1184 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 0 — Reset Request (MCR0): Controls resetting of this module. When this bit is changed from '0' to '1' this module controller enters its reset routine, re-initialising the internal logic, which then sets GSR3 and IRR0 to notify the reset mode. During a re-initialisation, all user registers are initialised. This module can be re-configured while this bit is set. This bit has to be cleared by writing a '0' to join the CAN bus. After this bit is cleared, this module waits until it detects 11 recessive bits, and then joins the CAN bus. The Baud Rate needs to be set up to a proper value in order to sample the value on the CAN Bus. After Power On Reset, this bit and GSR3 are always set. This means that a reset request has been made and this module needs to be configured. The Reset Request is equivalent to a Power On Reset but controlled by Software. Bit 0: MCR0 Description 0 Clear Reset Request 1 CAN Interface reset mode transition request (Initial value) (2) General Status Register (GSR) The General Status Register (GSR) is a 16-bit read-only register that indicates the status of this module.  GSR (Address = H'002) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 1 R 0 R 0 R Bits 15 to 6: Reserved. The written value should always be '0' and the returned value is '0'. Bit 5 — Error Passive Status Bit (GSR5): Indicates whether the CAN Interface is in Error Passive or not. This bit will be set high as soon as this module enters the Error Passive state and is cleared when the module enters again the Error Active state (this means the GSR5 will stay high during Error Passive and during Bus Off). Consequently to find out the correct state both GSR5 and GSR0 must be considered. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1185 of 3092 se stivT e a P Section 23 Controller Area Network SH7268 Group, SH7269 Group Bit 5: GSR5 Description 0 This module is not in Error Passive or in Bus Off status (Initial value) [Reset condition] This module is in Error Active state 1 This module is in Error Passive (if GSR0 = 0) or Bus Off (if GSR0 = 1) [Setting condition] When TEC • 128 or REC • 128 or if Error Passive Test Mode is selected Bit 4 — Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep state or not. Please note that the clearing time of this flag is not the same as the setting time of IRR12. Please note that this flag reflects the status of the CAN engine and not of the full this module IP. This module exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits sleep mode only after two additional transmission clocks on the CAN Bus. Bit 4: GSR4 Description 0 This module is not in the Halt state or Sleep state (Initial value) 1 Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1) [Setting condition] If MCR1 is set and the CAN bus is either in intermission or idle or MCR5 is set and this module is in the halt mode or this module is moving to Bus Off when MCR14 and MCR6 are both set Bit 3 — Reset Status Bit (GSR3): Indicates whether this module is in the reset state or not. Bit 3: GSR3 Description 0 This module is not in the reset state 1 Reset state (Initial value) [Setting condition] After an internal reset of this module (due to SW or HW reset) Page 1186 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 2 — Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if this module is in Bus Off or transmitting a message or an error/overload flag due to error detected during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK is set at the 7th bit of End Of Frame. GSR2 is set at the 3rd bit of intermission if there are no more messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset or halt transition. Bit 2: GSR2 Description 0 This module is in Bus Off or a transmission is in progress 1 [Setting condition] Not in Bus Off and no transmission in progress (Initial value) Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Bit 1: GSR1 Description 0 [Reset condition] When (TEC < 96 and REC < 96) or Bus Off (Initial value) 1 [Setting condition] When 96  TEC  256 or 96  REC  256 Note: REC is incremented during Bus Off to count the recurrences of 11 recessive bits as requested by the Bus Off recovery sequence. However the flag GSR1 is not set in Bus Off. Bit 0—Bus Off Flag (GSR0): Flag that indicates that this module is in the bus off state. Bit 0: GSR0 Description 0 [Reset condition] Recovery from bus off state or after a HW or SW reset (Initial value) 1 [Setting condition] When TEC  256 (bus off state) Note: Only the lower 8 bits of TEC are accessible from the user interface. The 9th bit is equivalent to GSR0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1187 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network (3) Bit Configuration Register (BCR0, BCR1) The bit configuration registers (BCR0 and BCR1) are 2 X 16-bit read/write register that are used to set CAN bit timing parameters and the baud rate pre-scaler for the CAN Interface. The Time quanta is defined as: Timequanta = 2 * BRP fclk Where: BRP (Baud Rate Pre-scaler) is the value stored in BCR0 incremented by 1 and fclk is the used peripheral clock 0 frequency.  BCR1 (Address = H'004) Bit: 15 14 13 12 TSG1[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 11 10 0 R/W 0 R 9 8 TSG2[2:0] - 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0 - - SJW[1:0] - - - BSP 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bits 15 to 12 — Time Segment 1 (TSG1[3:0] = BCR1[15:12]): These bits are used to set the segment TSEG1 (= PRSEG + PHSEG1) to compensate for edges on the CAN Bus with a positive phase error. A value from 4 to 16 time quanta can be set. Bit 15: Bit 14: Bit 13: Bit 12: TSG1[3] TSG1[2] TSG1[1] TSG1[0] Description 0 0 0 0 Setting prohibited (Initial value) 0 0 0 1 Setting prohibited 0 0 1 0 Setting prohibited 0 0 1 1 PRSEG + PHSEG1 = 4 time quanta 0 1 0 0 PRSEG + PHSEG1 = 5 time quanta : : : : : : : : : : 1 1 1 1 PRSEG + PHSEG1 = 16 time quanta Bit 11: Reserved. The written value should always be '0' and the returned value is '0'. Page 1188 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bits 10 to 8 — Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the segment TSEG2 (= PHSEG2) to compensate for edges on the CAN Bus with a negative phase error. A value from 2 to 8 time quanta can be set as shown below. Bit 10: Bit 9: Bit 8: TSG2[2] TSG2[1] TSG2[0] Description 0 0 0 Setting prohibited (Initial value) 0 0 1 PHSEG2 = 2 time quanta (conditionally prohibited) 0 1 0 PHSEG2 = 3 time quanta 0 1 1 PHSEG2 = 4 time quanta 1 0 0 PHSEG2 = 5 time quanta 1 0 1 PHSEG2 = 6 time quanta 1 1 0 PHSEG2 = 7 time quanta 1 1 1 PHSEG2 = 8 time quanta Bits 7 and 6: Reserved. The written value should always be '0' and the returned value is '0'. Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the synchronisation jump width. Bit 5: SJW[1] Bit 4: SJW[0] Description 0 0 Synchronisation Jump width = 1 time quantum (Initial value) 0 1 Synchronisation Jump width = 2 time quanta 1 0 Synchronisation Jump width = 3 time quanta 1 1 Synchronisation Jump width = 4 time quanta Bits 3 to 1: Reserved. The written value should always be '0' and the returned value is '0'. Bit 0 — Bit Sample Point (BSP = BCR1[0]): Sets the point at which data is sampled. Bit 0 : BSP Description 0 Bit sampling at one point (end of time segment 1) (Initial value) 1 Bit sampling at three points (rising edge of the last three clock cycles of PHSEG1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1189 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network  BCR0 (Address = H'006) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W BRP[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bits 8 to 15: Reserved. The written value should always be '0' and the returned value is '0'. Bits 7 to 0—Baud Rate Pre-scale (BRP[7:0] = BCR0 [7:0]): These bits are used to define the peripheral clock 0 periods contained in a Time Quantum. Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: BRP[7] BRP[6] BRP[5] BRP[4] BRP[3] BRP[2] BRP[1] BRP[0] Description 0 0 0 0 0 0 0 0 2 X peripheral clock 0 (Initial value) 0 0 0 0 0 0 0 1 4 X peripheral clock 0 0 0 0 0 0 0 1 0 6 X peripheral clock 0 : : : : : : : : : : : : : : : : 2*(register value + 1) X peripheral clock 0 1 1 1 1 1 1 1 1 512 X peripheral clock 0  Requirements of Bit Configuration Register 1-bit time (8-25 quanta) SYNC_SEG 1 PRSEG PHSEG1 PHSEG2 TSEG1 TSEG2 4-16 2-8 Quantum SYNC_SEG: Segment for establishing synchronisation of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronisation (resynchronisation) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronisation (resynchronisation) is established) TSEG1: TSG1 + 1 Page 1190 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group TSEG2: Section 23 Controller Area Network TSG2 + 1 The Bit Rate Calculation is: Bit Rate = fclk 2 × (BRP + 1) × (TSEG1 + TSEG2 + 1) Where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1 and TSG2 register values. The '+1' in the above formula is for the Sync-Seg which duration is 1 time quanta. fCLK = Peripheral clock 0 BCR Setting Constraints TSEG1min > TSEG2  SJWmax (SJW = 1 to 4) 8 < TSEG1 + TSEG2 + 1 < 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed) TSEG2 > 2 These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows that there is no allowed combination of TSEG1 and TSEG2. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1191 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 001 010 011 100 101 110 111 TSG2 2 3 4 5 6 7 8 TSEG2 TSG1 TSEG1 0011 4 No 1-3 No No No No No 0100 5 1-2 1-3 1-4 No No No No 0101 6 1-2 1-3 1-4 1-4 No No No 0110 7 1-2 1-3 1-4 1-4 1-4 No No 0111 8 1-2 1-3 1-4 1-4 1-4 1-4 No 1000 9 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1001 10 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1010 11 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1011 12 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1100 13 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1101 14 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1110 15 1-2 1-3 1-4 1-4 1-4 1-4 1-4 1111 16 1-2 1-3 1-4 1-4 1-4 1-4 1-4 Example 1: To have a Bit rate of 250 Kbps with a frequency of fclk = 25 MHz it is possible to set: BRP = 4, TSEG1 = 5, TSEG2 = 4. Then the configuration to write is BCR1 = H'4300 and BCR0 = H'0004. Example 2: To have a Bit rate of 500 Kbps with a frequency of fclk = 33 MHz it is possible to set: BRP = 2, TSEG1 = 6, TSEG2 = 4. Then the configuration to write is BCR1 = H'5300 and BCR0 = H'0002. Page 1192 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 23 Controller Area Network Interrupt Request Register (IRR) The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the various interrupt sources.  IRR (Address = H'008) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 R/W Bit 15 — Timer Compare Match Interrupt 1 (IRR15): Indicates that a Compare-Match condition occurred to the Timer Compare Match Register 1 (TCMR1). When the value set in the TCMR1 matches to Cycle Time (TCMR1 = CYCTR), this bit is set. Bit 15: IRR15 Description 0 Timer Compare Match has not occurred to the TCMR1 (Initial value) [Clearing condition] Writing 1 1 Timer Compare Match has occurred to the TCMR1 [Setting condition] TCMR1 matches to Cycle Time (TCMR1 = CYCTR) Bit 14 — Timer Compare Match Interrupt 0 (IRR14): Indicates that a Compare-Match condition occurred to the Timer Compare Match Register 0 (TCMR0). When the value set in the TCMR0 matches to Local Time (TCMR0 = TCNTR), this bit is set. Bit 14: IRR14 Description 0 Timer Compare Match has not occurred to the TCMR0 (Initial value) [Clearing condition] Writing 1 1 Timer Compare Match has occurred to the TCMR0 [Setting condition] TCMR0 matches to the Timer value (TCMR0 = TCNTR) Bit 13 - Timer Overrun Interrupt/Next_is_Gap Reception Interrupt/Message Error Interrupt (IRR13): This interrupt assumes a different meaning depending on this module mode. It indicates that:  The Timer (TCNTR) has overrun when this module is working in event-trigger mode (including test modes) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1193 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group  Time reference message with Next_is_Gap set has been received when working in timetrigger mode. Please note that when a Next_is_Gap is received the application is responsible to stop all transmission at the end of the current basic cycle (including test modes)  Message error has occurred when in test mode. Note: If a Message Overload condition occurs when in Test Mode, then this bit will not be set. Bit 13: IRR13 Description 0 Timer (TCNTR) has not overrun in event-trigger mode (including test modes) (Initial value) Time reference message with Next_is_Gap has not been received in timetrigger mode (including test modes) Message error has not occurred in test mode [Clearing condition] Writing 1 1 [Setting condition] Timer (TCNTR) has overrun and changed from H'FFFF to H'0000 in eventtrigger mode (including test modes) Time reference message with Next_is_Gap has been received in time-trigger mode (including test modes) Message error has occurred in test mode Bit 12 – Bus activity while in sleep mode (IRR12): IRR12 indicates that a CAN bus activity is present. While this module is in sleep mode and a dominant bit is detected on the CAN bus, this bit is set. This interrupt is cleared by writing a '1' to this bit position. Writing a '0' has no effect. If auto wakeup is not used and this interrupt is not requested it needs to be disabled by the related interrupt mask register. If auto wake up is not used and this interrupt is requested it should be cleared only after recovering from sleep mode. This is to avoid that a new falling edge of the reception line causes the interrupt to get set again. Please note that the setting time of this interrupt is different from the clearing time of GSR4. Bit 12: IRR12 Description 0 Bus idle state (Initial value) [Clearing condition] Writing 1 1 CAN bus activity detected in this module sleep mode [Setting condition] Dominant bit level detection on the Rx line while in sleep mode Page 1194 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 11 — Timer Compare Match Interrupt 2 (IRR11): Indicates that a Compare-Match condition occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the TCMR2 matches to Cycle Time (TCMR2 = CYCTR), this bit is set. Bit 11: IRR11 0 Description Timer Compare Match has not occurred to the TCMR2 (initial value) [Clearing condition] Writing 1 1 Timer Compare Match has occurred to the TCMR2 [Setting condition] TCMR2 matches to Cycle Time (TCMR2 = CYCTR) Bit 10 — Start of new system matrix Interrupt (IRR10): Indicates that a new system matrix is starting. When CCR = 0, this bit is set at the successful completion of reception/transmission of time reference message. Please note that when CMAX = 0 this interrupt is set at every basic cycle. Bit 10: IRR10 Description 0 A new system matrix is not starting (initial value) [Clearing condition] Writing 1 1 Cycle counter reached zero. [Setting condition] Reception/transmission of time reference message is successfully completed when CMAX!= 3'b111 and CCR = 0 Bit 9 – Message Overrun/Overwrite Interrupt Flag (IRR9): Flag indicating that a message has been received but the existing message in the matching Mailbox has not been read as the corresponding RXPR or RFPR is already set to '1' and not yet cleared by the CPU. The received message is either abandoned (overrun) or overwritten dependant upon the NMC (New Message Control) bit. This bit is cleared when all bit in UMSR (Unread Message Status Register) are cleared (by writing '1') or by setting MBIMR (MailBox interrupt Mast Register) for all UMSR flag set. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position has no effect. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1195 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group Bit 9: IRR9 Description 0 No pending notification of message overrun/overwrite [Clearing condition] Clearing of all bit in UMSR/setting MBIMR for all UMSR set (initial value) 1 A receive message has been discarded due to overrun condition or a message has been overwritten [Setting condition] Message is received while the corresponding RXPR and/or RFPR = 1 and MBIMR = 0 Bit 8 - Mailbox Empty Interrupt Flag (IRR8): This bit is set when one of the messages set for transmission has been successfully sent (corresponding TXACK flag is set) or has been successfully aborted (corresponding ABACK flag is set). In Event Triggered mode the related TXPR is also cleared and this mailbox is now ready to accept a new message data for the next transmission. In Time Trigger mode TXPR for the Mailboxes from 30 to 24 is not cleared after a successful transmission in order to keep transmitting at each programmed basic cycle. In effect, this bit is set by an OR'ed signal of the TXACK and ABACK bits not masked by the corresponding MBIMR flag. Therefore, this bit is automatically cleared when all the TXACK and ABACK bits are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit position has no effect. Bit 8: IRR8 Description 0 Messages set for transmission or transmission cancellation request NOT progressed. (Initial value) [Clearing Condition] All the TXACK and ABACK bits are cleared/setting MBIMR for all TXACK and ABACK set 1 Message has been transmitted or aborted, and new message can be stored (in TT mode Mailbox 24 to 30 can be programmed with a new message only in case of abortion) [Setting condition] When a TXACK or ABACK bit is set (if related MBIMR = 0). Page 1196 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 7 - Overload Frame (IRR7): Flag indicating that this module has detected a condition that should initiate the transmission of an overload frame. Note that in the condition of transmission being prevented, such as listen only mode, an Overload Frame will NOT be transmitted, but IRR7 will still be set. IRR7 remains asserted until reset by writing a '1' to this bit position - writing a '0' has no effect. Bit 7: IRR7 Description 0 [Clearing condition] Writing 1 (Initial value) 1 [Setting conditions] Overload condition detected Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when this module enters the Bus-off state or when this module leaves Bus-off and returns to Error-Active. The cause therefore is the existing condition TEC  256 at the node or the end of the Bus-off recovery sequence (128X11 consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit remains set even if this module node leaves the bus-off condition, and needs to be explicitly cleared by S/W. The S/W is expected to read the GSR0 to judge whether this module is in the busoff or error active status. It is cleared by writing a '1' to this bit position even if the node is still bus-off. Writing a '0' has no effect. Bit 6: IRR6 Description 0 [Clearing condition] Writing 1 (Initial value) 1 Enter Bus off state caused by transmit error or Error Active state returning from Bus-off [Setting condition] When TEC becomes  256 or End of Bus-off after 128X11 consecutive recessive bits or transition from Bus Off to Halt Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge whether this module is in Error Passive or Bus Off status. Bit 5: IRR5 Description 0 [Clearing condition] Writing 1 (Initial value) 1 Error passive state caused by transmit/receive error [Setting condition] When TEC  128 or REC  128 or Error Passive test mode is used R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1197 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group Bit 4 - Receive Error Counter Warning Interrupt Flag (IRR4): This bit becomes set if the receive error counter (REC) reaches a value greater than 95 when this module is not in the Bus Off status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect. Bit 4: IRR4 Description 0 [Clearing condition] Writing 1 (Initial value) 1 Error warning state caused by receive error [Setting condition] When REC  96 and this module is not in Bus Off Bit 3 - Transmit Error Counter Warning Interrupt Flag (IRR3): This bit becomes set if the transmit error counter (TEC) reaches a value greater than 95. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect. Bit 3: IRR3 Description 0 [Clearing condition] Writing 1 (Initial value) 1 Error warning state caused by transmit error [Setting condition] When TEC  96 Bit 2 - Remote Frame Receive Interrupt Flag (IRR2): Flag indicating that a remote frame has been received in a mailbox. This bit is set if at least one receive mailbox, with related MBIMR not set, contains a remote frame transmission request. This bit is automatically cleared when all bits in the Remote Frame Receive Pending Register (RFPR), are cleared. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect. Bit 2: IRR2 Description 0 [Clearing condition] Clearing of all bits in RFPR (Initial value) 1 At least one remote request is pending [Setting condition] When remote frame is received and the corresponding MBIMR = 0 Bit 1 – Data Frame Received Interrupt Flag (IRR1): IRR1 indicates that there are pending Data Frames received. If this bit is set at least one receive mailbox contains a pending message. This bit is cleared when all bits in the Data Frame Receive Pending Register (RXPR) are cleared, i.e. there is no pending message in any receiving mailbox. It is in effect a logical OR of the RXPR flags from each configured receive mailbox with related MBIMR not set. It is also cleared by writing a '1' to all the correspondent bit position in MBIMR. Writing to this bit has no effect. Page 1198 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 1: IRR1 Description 0 [Clearing condition] Clearing of all bits in RXPR (Initial value) 1 Data frame received and stored in Mailbox [Setting condition] When data is received and the corresponding MBIMR = 0 Bit 0 – Reset/Halt/Sleep Interrupt Flag (IRR0): This flag can get set for three different reasons. It can indicate that: 1. Reset mode has been entered after a SW (MCR0) or HW reset 2. Halt mode has been entered after a Halt request (MCR1) 3. Sleep mode has been entered after a sleep request (MCR5) has been made while in Halt mode. The GSR may be read after this bit is set to determine which state this module is in. Important: When a Sleep mode request needs to be made, the Halt mode must be used beforehand. Please refer to the MCR5 description and Figure 23.15 Halt Mode/Sleep Mode. IRR0 is set by the transition from "0" to "1" of GSR3 or GSR4 or by transition from Halt mode to Sleep mode. So, IRR0 is not set if this module enters Halt mode again right after exiting from Halt mode, without GSR4 being cleared. Similarly, IRR0 is not set by direct transition from Sleep mode to Halt Request. At the transition from Halt/Sleep mode to Transition/Reception, clearing GSR4 needs (one-bit time - TSEG2) to (one-bit time * 2 - TSEG2). In the case of Reset mode, IRR0 is set, however, the interrupt to the CPU is not asserted since IMR0 is automatically set by initialisation. Bit 0: IRR0 Description 0 [Clearing condition] Writing 1 1 Transition to S/W reset mode or transition to halt mode or transition to sleep mode (Initial value) [Setting condition] When reset/halt/sleep transition is completed after a reset (MCR0 or HW) or Halt mode (MCR1) or Sleep mode (MCR5) is requested R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1199 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network (5) Interrupt Mask Register (IMR) The interrupt mask register is a 16 bit register that protects all corresponding interrupts in the Interrupt Request Register (IRR) from generating an output signal on the IRQ. An interrupt request is masked if the corresponding bit position is set to '1'. This register can be read or written at any time. The IMR directly controls the generation of IRQ, but does not prevent the setting of the corresponding bit in the IRR.  IMR (Address = H'00A) Bit: 15 14 13 12 11 10 IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 9 8 7 6 5 4 3 2 1 0 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 to 0: Maskable interrupt sources corresponding to IRR[15:0] respectively. When a bit is set, the interrupt signal is not generated, although setting the corresponding IRR bit is still performed. Bit[15:0]: IMRn Description 0 Corresponding IRR is not masked (IRQ is generated for interrupt conditions) 1 Corresponding interrupt of IRR is masked (Initial value) (6) Transmit Error Counter (TEC) and Receive Error Counter (REC) The Transmit Error Counter (TEC) and Receive Error Counter (REC) is a 16-bit read/(write) register that functions as a counter indicating the number of transmit/receive message errors on the CAN Interface. The count value is stipulated in the CAN protocol specification Refs. [1], [2], [3] and [4]. When not in (Write Error Counter) test mode this register is read only, and can only be modified by the CAN Interface. This register can be cleared by a Reset request (MCR0) or entering to bus off. In Write Error Counter test mode (i.e. TST[2:0] = 3'b100), it is possible to write to this register. The same value can only be written to TEC/REC, and the value written into TEC is set to TEC and REC. When writing to this register, this module needs to be put into Halt Mode. This feature is only intended for test purposes. Page 1200 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  TEC/REC (Address = H'00C) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * It is only possible to write the value in test mode when TST[2:0] in MCR is 3'b100. REC is incremented during Bus Off to count the recurrences of 11 recessive bits as requested by the Bus Off recovery sequence. 23.3.4 Mailbox Registers The following sections describe Mailbox registers that control/flag individual Mailboxes. The address is mapped as follows. Important: LongWord access is carried out as two consecutive Word accesses. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1201 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 32-Mailboxes version Description Address Name Access Size (bits) Transmit Pending 1 020 TXPR1 LW Transmit Pending 0 022 TXPR0  024 026 Transmit Cancel 1 028 TXCR1 Word/LW Transmit Cancel 0 02A TXCR0 Word 02C 02E Transmit Acknowledge 1 030 TXACK1 Word/LW Transmit Acknowledge 0 032 TXACK0 Word 034 036 Abort Acknowledge 1 038 ABACK1 Word/LW Abort Acknowledge 0 03A ABACK0 Word 03C 03E Data Frame Receive Pending 1 040 RXPR1 Word/LW Data Frame Receive Pending 0 042 RXPR0 Word Remote Frame Receive Pending 1 048 RFPR1 Word/LW Remote Frame Receive Pending 0 04A RFPR0 Word 044 046 04C 04E Mailbox Interrupt Mask Register 1 050 MBIMR1 Word/LW Mailbox Interrupt Mask Register 0 052 MBIMR0 Word Unread message Status Register 1 058 UMSR1 Word/LW Unread message Status Register 0 05A UMSR0 Word 054 056 05C 05E Figure 23.11 Mailbox Registers Page 1202 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 23 Controller Area Network Transmit Pending Register (TXPR1, TXPR0) The concatenation of TXPR1 and TXPR0 is a 32-bit register that contains any transmit pending flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as two consecutive word accesses. 16-bit Peripheral bus 16-bit Peripheral bus consecutive access Temp TXPR1 H'020 Temp TXPR0 H'022 TXPR1 H'020 Data is stored into Temp instead of TXPR1. TXPR0 H'022 Longword data are stored into both TXPR1 and TXPR0 at the same time. 16-bit Peripheral bus 16-bit Peripheral bus consecutive access Temp TXPR1 H'020 TXPR0 H'022 TXPR0 is stored into Temp, when TXPR1 is read. Temp TXPR1 H'020 TXPR0 H'022 Temp is read instead of TXPR0. The TXPR1 controls Mailbox-31 to Mailbox-16, and the TXPR0 controls Mailbox-15 to Mailbox1. The CPU may set the TXPR bits to affect any message being considered for transmission by writing a '1' to the corresponding bit location. Writing a '0' has no effect, and TXPR cannot be cleared by writing a '0' and must be cleared by setting the corresponding TXCR bits. TXPR may be read by the CPU to determine which, if any, transmissions are pending or in progress. In effect there is a transmit pending bit for all Mailboxes except for the Mailbox-0. Writing a '1' to a bit location when the mailbox is not configured to transmit is not allowed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1203 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network In Event Triggered Mode this module will clear a transmit pending flag after successful transmission of its corresponding message or when a transmission abort is requested successfully from the TXCR. In Time Trigger Mode, TXPR for the Mailboxes from 30 to 24 is NOT cleared after a successful transmission, in order to keep transmitting at each programmed basic cycle. The TXPR flag is not cleared if the message is not transmitted due to the CAN node losing the arbitration process or due to errors on the CAN bus, and this module automatically tries to transmit it again unless its DART bit (Disable Automatic Re-Transmission) is set in the MessageControl of the corresponding Mailbox. In such case (DART set), the transmission is cleared and notified through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit within the Abort Acknowledgement Register (ABACK). If the status of the TXPR changes, this module shall ensure that in the identifier priority scheme (MCR2 = 0), the highest priority message is always presented for transmission in an intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus. Please refer to the Application Note for details. When this module changes the state of any TXPR bit position to a '0', an empty slot interrupt (IRR8) may be generated. This indicates that either a successful or an aborted mailbox transmission has just been made. If a message transmission is successful it is signalled in the TXACK register, and if a message transmission abortion is successful it is signalled in the ABACK register. By checking these registers, the contents of the Message of the corresponding Mailbox may be modified to prepare for the next transmission.  TXPR1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXPR1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * It is possible only to write a '1' for a Mailbox configured as transmitter. Bit 15 to 0 — Requests the corresponding Mailbox to transmit a CAN Frame. The bit 15 to 0 corresponds to Mailbox-31 to 16 respectively. When multiple bits are set, the order of the transmissions is governed by the MCR2 – CAN-ID or Mailbox number. Page 1204 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit[15:0]: TXPR1 Description 0 Transmit message idle state in corresponding mailbox (Initial value) [Clearing Condition] Completion of message transmission (for Event Triggered Messages) or message transmission abortion (automatically cleared) 1 Transmission request made for corresponding mailbox  TXPR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TXPR0[15:1] 0 - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 0 R Note: * It is possible only to write a '1' for a Mailbox configured as transmitter. Bit 15 to 1 — Indicates that the corresponding Mailbox is requested to transmit a CAN Frame. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively. When multiple bits are set, the order of the transmissions is governed by the MCR2 – CAN-ID or Mailbox number. Bit[15:1]: TXPR0 0 Description Transmit message idle state in corresponding mailbox (Initial value) [Clearing Condition] Completion of message transmission (for Event Triggered Messages) or message transmission abortion (automatically cleared) 1 Transmission request made for corresponding mailbox Bit 0— Reserved: This bit is always '0' as this is a receive-only Mailbox. Writing a '1' to this bit position has no effect. The returned value is '0'. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1205 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network (2) Transmit Cancel Register (TXCR1, TXCR0) The TXCR1 and TXCR0 are 16-bit read/conditionally-write registers. The TXCR1 controls Mailbox-31 to Mailbox-16, and the TXCR0 controls Mailbox-15 to Mailbox-1.This register is used by the CPU to request the pending transmission requests in the TXPR to be cancelled. To clear the corresponding bit in the TXPR the CPU must write a '1' to the bit position in the TXCR. Writing a '0' has no effect. When an abort has succeeded the CAN controller clears the corresponding TXPR + TXCR bits, and sets the corresponding ABACK bit. However, once a Mailbox has started a transmission, it cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN controller clears the corresponding TXPR + TXCR bit, and sets the corresponding TXACK bit, however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN controller clears the corresponding TXPR + TXCR bit, and sets the corresponding ABACK bit. If an attempt is made by the CPU to clear a mailbox transmission that is not transmit-pending it has no effect. In this case the CPU will be not able at all to set the TXCR flag.  TXCR1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCR1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only writing a ‘1’ to a Mailbox that is requested for transmission and is configured as transmit. Bit 15 to 0 — Requests the corresponding Mailbox, that is in the queue for transmission, to cancel its transmission. The bit 15 to 0 corresponds to Mailbox-31 to 16 (and TXPR1[15:0]) respectively. Bit[15:0]:TXCR1 Description 0 Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing Condition] Completion of transmit message cancellation (automatically cleared) 1 Page 1206 of 3092 Transmission cancellation request made for corresponding mailbox R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  TXCR0 Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCR0[15:1] - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 0 R Note: * Only writing a '1' to a Mailbox that is requested for transmission and is configured as transmit. Bit 15 to 1 — Requests the corresponding Mailbox, that is in the queue for transmission, to cancel its transmission. The bit 15 to 1 corresponds to Mailbox-15 to 1 (and TXPR0[15:1]) respectively. Bit[15:1]: TXCR0 Description 0 Transmit message cancellation idle state in corresponding mailbox (Initial value) [Clearing Condition] Completion of transmit message cancellation (automatically cleared) 1 Transmission cancellation request made for corresponding mailbox Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has no effect and always read back as a ‘0’. (3) Transmit Acknowledge Register (TXACK1, TXACK0) The TXACK1 and TXACK0 are 16-bit read/conditionally-write registers. These registers are used to signal to the CPU that a mailbox transmission has been successfully made. When a transmission has succeeded this module sets the corresponding bit in the TXACK register. The CPU may clear a TXACK bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect.  TXACK1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXACK1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1207 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 15 to 0 — Notifies that the requested transmission of the corresponding Mailbox has been finished successfully. The bit 15 to 0 corresponds to Mailbox-31 to 16 respectively. Bit[15:0]:TXACK1 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox has successfully transmitted message (Data or Remote Frame) [Setting Condition] Completion of message transmission for corresponding mailbox  TXACK0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - TXACK0[15:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 0 - Note: * Only when writing a '1' to clear. Bit 15 to 1 — Notifies that the requested transmission of the corresponding Mailbox has been finished successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively. Bit[15:1]:TXACK0 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox has successfully transmitted message (Data or Remote Frame) [Setting Condition] Completion of message transmission for corresponding mailbox Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has no effect and always read back as a '0'. Page 1208 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 23 Controller Area Network Abort Acknowledge Register (ABACK1, ABACK0) The ABACK1 and ABACK0 are 16-bit read/conditionally-write registers. These registers are used to signal to the CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded this module sets the corresponding bit in the ABACK register. The CPU may clear the Abort Acknowledge bit by writing a '1' to the corresponding bit location. Writing a '0' has no effect. An ABACK bit position is set by this module to acknowledge that a TXPR bit has been cleared by the corresponding TXCR bit.  ABACK1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABACK1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. Bit 15 to 0 — Notifies that the requested transmission cancellation of the corresponding Mailbox has been performed successfully. The bit 15 to 0 corresponds to Mailbox-31 to 16 respectively. Bit[15:0]:ABACK1 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox has cancelled transmission of message (Data or Remote Frame) [Setting Condition] Completion of transmission cancellation for corresponding mailbox  ABACK0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - ABACK0[15:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 0 R Note: * Only when writing a '1' to clear. Bit 15 to 1 — Notifies that the requested transmission cancellation of the corresponding Mailbox has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1209 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit[15:1]:ABACK0 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox has cancelled transmission of message (Data or Remote Frame) [Setting Condition] Completion of transmission cancellation for corresponding mailbox Bit 0 — This bit is always '0' as this is a receive-only mailbox. Writing a '1' to this bit position has no effect and always read back as a '0'. (5) Data Frame Receive Pending Register (RXPR1, RXPR0) The RXPR1 and RXPR0 are 16-bit read/conditionally-write registers. The RXPR is a register that contains the received Data Frames pending flags associated with the configured Receive Mailboxes. When a CAN Data Frame is successfully stored in a receive mailbox the corresponding bit is set in the RXPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox Configuration) to receive Data Frames. When a RXPR bit is set, it also sets IRR1 (Data Frame Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR1 is not set. Please note that these bits are only set by receiving Data Frames and not by receiving Remote frames.  RXPR1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR1[15:0] Initial value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note : * Only when writing a '1' to clear. Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position from 31 to 16 respectively. Bit[15:0]: RXPR1 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox received a CAN Data Frame [Setting Condition] Completion of Data Frame receive on corresponding mailbox Page 1210 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  RXPR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR0[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position from 15 to 0 respectively. Bit[15:0]: RXPR0 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox received a CAN Data Frame [Setting Condition] Completion of Data Frame receive on corresponding mailbox (6) Remote Frame Receive Pending Register (RFPR1, RFPR0) The RFPR1 and RFPR0 are 16-bit read/conditionally-write registers. The RFPR is a register that contains the received Remote Frame pending flags associated with the configured Receive Mailboxes. When a CAN Remote Frame is successfully stored in a receive mailbox the corresponding bit is set in the RFPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. In effect there is a bit position for all mailboxes. However, the bit may only be set if the mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a RFPR bit is set, it also sets IRR2 (Remote Frame Receive Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Please note that these bits are only set by receiving Remote Frames and not by receiving Data frames.  RFPR1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1211 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 15 to 0 — Remote Request pending flags for mailboxes 31 to 16 respectively. Bit[15:0]: RFPR1 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox received Remote Frame [Setting Condition] Completion of remote frame receive in corresponding mailbox  RFPR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR0[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. Bit 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively. Bit[15:0]: RFPR0 Description 0 [Clearing Condition] Writing '1' (Initial value) 1 Corresponding Mailbox received Remote Frame [Setting Condition] Completion of remote frame receive in corresponding mailbox (7) Mailbox Interrupt Mask Register (MBIMR) The MBIMR1 and MBIMR0 are 16-bit read/write registers. The MBIMR only prevents the setting of IRR related to the Mailbox activities, that are IRR[1] – Data Frame Received Interrupt, IRR[2] – Remote Frame Receive Interrupt, IRR[8] – Mailbox Empty Interrupt, and IRR[9] – Message OverRun/OverWrite Interrupt. If a mailbox is configured as receive, a mask at the corresponding bit position prevents the generation of a receive interrupt (IRR[1] and IRR[2] and IRR[9]) but does not prevent the setting of the corresponding bit in the RXPR or RFPR or UMSR. Similarly when a mailbox has been configured for transmission, a mask prevents the generation of an Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or abortion of transmission (IRR[8]), however, it does not prevent this module from clearing the corresponding TXPR/TXCR bit + setting the TXACK bit for successful transmission, and it does not prevent this module from clearing the corresponding TXPR/TXCR bit + setting the ABACK bit for abortion of the transmission. Page 1212 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network A mask is set by writing a '1' to the corresponding bit position for the mailbox activity to be masked. At reset all mailbox interrupts are masked.  MBIMR1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MBIMR1[15:0] Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-31 to Mailbox-16 respectively. Bit[15:0]: MBIMR1 Description 0 Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled 1 Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value)  MBIMR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W MBIMR0[15:0] Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 to 0 — Enable or disable interrupt requests from individual Mailbox-15 to Mailbox-0 respectively. Bit[15:0]: MBIMR0 Description 0 Interrupt Request from IRR1/IRR2/IRR8/IRR9 enabled 1 Interrupt Request from IRR1/IRR2/IRR8/IRR9 disabled (initial value) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1213 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network (8) Unread Message Status Register (UMSR) This register is a 32-bit read/conditionally write register and it records the mailboxes whose contents have not been accessed by the CPU prior to a new message being received. If the CPU has not cleared the corresponding bit in the RXPR or RFPR when a new message for that mailbox is received, the corresponding UMSR bit is set to '1'. This bit may be cleared by writing a '1' to the corresponding bit location in the UMSR. Writing a '0' has no effect. If a mailbox is configured as transmit box, the corresponding UMSR will not be set.  UMSR1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR1[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition has occurred for Mailboxes 31 to 16. Bit[15:0]: UMSR1 Description 0 [Clearing Condition] Writing '1' (initial value) 1 Unread received message is overwritten by a new message or overrun condition [Setting Condition] When a new message is received before RXPR or RFPR is cleared  UMSR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR0[15:0] Initial value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * Only when writing a '1' to clear. Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition has occurred for Mailboxes 15 to 0. Page 1214 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit[15:0]: UMSR0 Description 0 [Clearing Condition] Writing '1' (initial value) 1 Unread received message is overwritten by a new message or overrun condition [Setting Condition] When a new message is received before RXPR or RFPR is cleared 23.3.5 Timer Registers The Timer is 16 bits and supports several source clocks. A pre-scale counter can be used to reduce the speed of the clock. It also supports three Compare Match Registers (TCMR2, TCMR1, TCMR0). The address map is as follows. Important: These registers can only be accessed in Word size (16-bit). Description Address Name Access Size (bits) Timer Trigger Control Register 0 080 TTCR0 Word (16) Cycle Maximum/Tx-Enable Window Register 084 CMAX_TEW Word (16) Reference Trigger Offset Register 086 RFTROFF Word (16) Timer Status Register 088 TSR Word (16) Cycle Counter Register 08A CCR Word (16) Timer Counter Register 08C TCNTR Word (16) Cycle Time Register 090 CYCTR Word (16) Reference Mark Register 094 RFMK Word (16) Timer Compare Match Register 0 098 TCMR0 Word (16) Timer Compare Match Register 1 09C TCMR1 Word (16) Timer Compare Match Register 2 0A0 TCMR2 Word (16) Tx-Trigger Time Selection Register 0A4 TTTSEL Word (16) Figure 23.12 Timer Registers R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1215 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network (1) Time Trigger Control Register0 (TTCR0) The Time Trigger Control Register0 is a 16-bit read/write register and provides functions to control the operation of the Timer. When operating in Time Trigger Mode, please refer to section 23.4.3 (1), Time Triggered Transmission.  TTCR0 (Address = H'080) Bit: 15 14 13 12 11 10 TCR15 TCR14 TCR13 TCR12 TCR11 TCR10 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 - - - 0 R 0 R 0 R 6 5 4 3 2 1 0 TCR6 TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 — Enable Timer: When this bit is set, the timer TCNTR is running. When this bit is cleared, TCNTR and CCR are cleared. Bit15: TTCR0 15 Description 0 Timer and CCR are cleared and disabled (initial value) 1 Timer is running Bit 14 — TimeStamp value: Specifies if the Timestamp for transmission and reception in Mailboxes 15 to 0 must contain the Cycle Time (CYCTR) or the concatenation of CCR[5:0] + CYCTR[15:6]. This feature is very useful for time triggered transmission to monitor Rx_Trigger. This register does not affect the TimeStamp for Mailboxes 30 and 31. Bit14: TTCR0 14 Description 0 CYCTR[15:0] is used for the TimeStamp in Mailboxes 15 to 0 (initial value) 1 CCR[5:0] + CYCTR[15:6] is used for the TimeStamp in Mailboxes 15 to 0 Bit 13 — Cancellation by TCMR2: The messages in the transmission queue are cancelled by setting TXCR, when both this bit and bit12 are set and compare match occurs when this module is not in the Halt status, causing the setting of all TXCR bits with the corresponding TXPR bits set. Bit13: TTCR0 13 Description 0 Cancellation by TCMR2 compare match is disabled (initial value) 1 Cancellation by TCMR2 compare match is enabled Page 1216 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 12 — TCMR2 compare match enable: When this bit is set, IRR11 is set by TCMR2 compare match. Bit12 TTCR0 12 Description 0 IRR11 isn't set by TCMR2 compare match (initial value) 1 IRR11 is set by TCMR2 compare match Bit 11 — TCMR1 compare match enable: When this bit is set, IRR15 is set by TCMR1 compare match. Bit11 TTCR0 11 Description 0 IRR15 isn't set by TCMR1 compare match (initial value) 1 IRR15 is set by TCMR1 compare match Bit 10 — TCMR0 compare match enable: When this bit is set, IRR14 is set by TCMR0 compare match. Bit10 TTCR0 10 Description 0 IRR14 isn't set by TCMR0 compare match (initial value) 1 IRR14 is set by TCMR0 compare match Bits 9 to 7: Reserved. The written value should always be '0' and the returned value is '0'. Bit 6 — Timer Clear-Set Control by TCMR0: Specifies if the Timer is to be cleared and set to H'0000 when the TCMR0 matches to the TCNTR. Please note that the TCMR0 is also capable to generate an interrupt signal to the CPU via IRR14. Note: If this module is working in TTCAN mode (CMAX isn't 3'b111), TTCR0 bit6 has to be '0' to avoid clearing Local Time. Bit6: TTCR0 6 Description 0 Timer is not cleared by the TCMR0 (initial value) 1 Timer is cleared by the TCMR0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1217 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit5 to 0 — Timer Prescaler (TPSC[5:0]): This control field allows the timer source clock (4*[this module system clock]) to be divided before it is used for the timer. This function is available only in event-trigger mode. In time trigger mode (CMAX is not 3'b111), one nominal Bit Timing (= one bit length of CAN bus) is automatically chosen as source clock of TCNTR. The following relationship exists between source clock period and the timer period. Bit[5:0]: TPSC[5:0] Description 000000 1 X Source Clock (initial value) 000001 2 X Source Clock 000010 3 X Source Clock 000011 4 X Source Clock 000100 5 X Source Clock ...... ...... ...... ...... 111111 64 X Source Clock (2) Cycle Maximum/Tx-Enable Window Register (CMAX_TEW) This register is a 16-bit read/write register. CMAX specifies the maximum value for the cycle counter (CCR) for TT Transmissions to set the number of basic cycles in the matrix system. When the Cycle Counter reaches the maximum value (CCR = CMAX), after a full basic cycle, it is cleared to zero and an interrupt is generated on IRR.10. TEW specifies the width of Tx-Enable window.  CMAX_TEW (Address = H'084) Bit: Initial value: R/W: 15 14 13 12 11 - - - - - 0 R 0 R 0 R 0 R 0 R 10 9 8 CMAX[2:0] 1 R/W 1 R/W 1 R/W 7 6 5 4 - - - - 0 R 0 R 0 R 0 R 3 2 1 0 TEW[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Bits 15 to 11: Reserved. The written value should always be '0' and the returned value is '0'. Page 1218 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 10 to 8 — Cycle Count Maximum (CMAX): Indicates the maximum number of CCR. The number of basic cycles available in the matrix cycle for Timer Triggered transmission is (Cycle Count Maximum + 1). Unless CMAX = 3'b111, this module is in time-trigger mode and time trigger function is available. If CMAX = 3'b111, this module is in event-trigger mode. Bit[10:8]: CMAX[2:0] Description 000 Cycle Count Maximum = 0 001 Cycle Count Maximum = 1 010 Cycle Count Maximum = 3 011 Cycle Count Maximum = 7 100 Cycle Count Maximum = 15 101 Cycle Count Maximum = 31 110 Cycle Count Maximum = 63 111 CCR is cleared and this module is in event-trigger mode. (initial value) Important: Please set CMAX = 3'b111 when event-trigger mode is used. Bits 7 to 4: Reserved. The written value should always be '0' and the returned value is ‘0’. Bit 3 to 0 — Tx-Enable Window (TEW): Indicates the width of Tx-Enable Window. TEW = H'00 shows the width is one nominal Bit Timing. All values from 0 to 15 are allowed to be set. Bit[3:0]: TEW[3:0] Description 0000 The width of Tx-Enable Window = 1 (initial value) 0001 The width of Tx-Enable Window = 2 0010 The width of Tx-Enable Window = 3 0011 The width of Tx-Enable Window = 4 .... ...... .... ...... 1111 The width of Tx-Enable Window = 16 Note: The CAN core always needs a time between 1 to 2 bit timing to initiate transmission. The above values are not considering this accuracy. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1219 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network (3) Reference Trigger Offset Register (RFTROFF) This is a 8-bit read/write register that affects Tx-Trigger Time (TTT) of Mailbox-30. The TTT of Mailbox-30 is compared with CYCTR after RFTROFF extended with sign is added to the TTT. However, the value of TTT is not modified. The offset value doesn't affect others except Mailbox30.  RFTROFF (Address = H'086) Bit: 15 14 13 12 11 10 9 8 RFTROFF[7:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 - - - - - - - 0 - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 8 — Indicate the value of Reference Trigger Offset. Bits 7 to 0: Reserved. The written value should always be '0' and the returned value is '0'. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Description 0 0 0 0 0 0 0 0 Ref_trigger_offset = 0 (initial value) 0 0 0 0 0 0 0 1 Ref_trigger_offset = 1 0 0 0 0 0 0 1 0 Ref_trigger_offset = 2 . . . . . . . . 0 1 1 1 1 1 1 1 . . . . . . . . 1 1 1 1 1 1 1 1 Ref_trigger_offset = 1 1 1 1 1 1 1 1 0 Ref_trigger_offset = 2 . . . . . . . . 1 0 0 0 0 0 0 1 Ref_trigger_offset = 127 1 0 0 0 0 0 0 0 Prohibited Page 1220 of 3092 Ref_trigger_offset = 127 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 23 Controller Area Network Timer Status Register (TSR) This register is a 16-bit read-only register, and allows the CPU to monitor the Timer Compare Match status and the Timer Overrun Status.  TSR (Address = H'088) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - TSR4 TSR3 TSR2 TSR1 TSR0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bits 15 to 5: Reserved. The written value should always be '0' and the returned value is '0'. Bit 4 to 0 — Timer Status (TSR[4:0]): This read-only field allows the CPU to monitor the status of the Cycle Counter, the Timer and the Compare Match registers. Writing to this field has no effect. Bit 4 — Start of New System Matrix (TSR4): Indicates that a new system matrix is starting. When CCR = 0, this bit is set at the successful completion of reception/transmission of time reference message. Bit4: TSR4 Description 0 A new system matrix is not starting (initial value) [Clearing condition] Writing '1' to IRR10 (Cycle Counter Overflow Interrupt) 1 Cycle counter reached zero [Setting condition] When the Cycle Counter value changes from the maximum value (CMAX) to H'0. Reception/transmission of time reference message is successfully completed when CMAX!= 3'b111 and CCR = 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1221 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group Bit 3 — Timer Compare Match Flag 2 (TSR3): Indicates that a Compare-Match condition occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the TCMR2 matches to Cycle Time Register (TCMR2 = CYCTR), this bit is set if TTCR0 bit12 = 1. Please note that this bit is read-only and is cleared when IRR11 (Timer Compare Match Interrupt 2) is cleared. Bit3: TSR3 Description 0 Timer Compare Match has not occurred to the TCMR2 (Initial value) [Clearing condition] Writing '1' to IRR11 (Timer Compare Match Interrupt 1) 1 Timer Compare Match has occurred to the TCMR2 [Setting condition] TCMR2 matches to Cycle Time (TCMR2 = CYCTR), if TTCR0 bit12 = 1. Bit 2 — Timer Compare Match Flag 1 (TSR2): Indicates that a Compare-Match condition occurred to the Timer Compare Match Register 1 (TCMR1). When the value set in the TCMR1 matches to Cycle Time Register (TCMR1 = CYCTR), this bit is set if TTCR0 bit11 = 1. Please note that this bit is read-only and is cleared when IRR15 (Timer Compare Match Interrupt 1) is cleared. Bit2: TSR2 Description 0 Timer Compare Match has not occurred to the TCMR1 (Initial value) [Clearing condition] Writing '1' to IRR15 (Timer Compare Match Interrupt 1) 1 Timer Compare Match has occurred to the TCMR1 [Setting condition] TCMR1 matches to Cycle Time (TCMR1 = CYCTR), if TTCR0 bit11 = 1. Bit 1 — Timer Compare Match Flag 0 (TSR1): Indicates that a Compare-Match condition occurred to the Compare Match Register 0 (TCMR0). When the value set in the TCMR0 matches to the Timer value (TCMR0 = TCNTR), this bit is set if TTCR0 bit10 = 1. Please note that this bit is read-only and is cleared when IRR14 (Timer Compare Match Interrupt 0) is cleared. Bit1: TSR1 Description 0 Compare Match has not occurred to the TCMR0 (Initial value) [Clearing condition] Writing '1' to IRR14 (Timer Compare Match Interrupt 0) 1 Compare Match has occurred to the TCMR0 [Setting condition] TCMR0 matches to the Timer value (TCMR0 = TCNTR) Page 1222 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bit 0 — Timer Overrun/Next_is_Gap Reception/Message Error (TSR0): This flag is assigned to three different functions. It indicates that the Timer has overrun when working in event-trigger mode, time reference message with Next_is_Gap set has been received in time-trigger mode, and error detected on the CAN bus has occurred in test mode, respectively. Test mode has higher priority with respect to the other settings. Bit0: TSR0 Description 0 Timer (TCNTR) has not overrun in event-trigger mode (Initial value) Time reference message with Next_is_Gap has not been received in timetrigger mode message error has not occurred in test mode. [Clearing condition] Writing '1' to IRR13 1 [Setting condition] Timer (TCNTR) has overrun and changed from H'FFFF to H'0000 in eventtrigger mode.time reference message with Next_is_Gap has been received in time-trigger mode message error has occurred in test mode (5) Cycle Counter Register (CCR) This register is a 6-bit read/write register. Its purpose is to store the number of the basic cycle for Time -Triggered Transmissions. Its value is updated in different fashions depending if this module is programmed to work as a potential time master or as a time slave. If this module is working as (potential) time master, CCR is:  Incremented by one every time the cycle time (CYCTR) matches to Tx-Trigger Time of Mailbox-30 or  Overwritten with the value contained in MSG_DATA_0[5:0] of Mailbox 31 when a valid reference message is received. If this module is working as a time slave, CCR is only overwritten with the value of MSG_DATA_0[5:0] of Mailbox 31 when a valid reference message is received. If CMAX = 3'111, CCR is always H'0000.  CCR (Address = H'08A) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 5 4 3 2 1 0 0 R/W 0 R/W CCR[5:0] 0 R/W 0 R/W 0 R/W 0 R/W Page 1223 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Bits 15 to 6: Reserved. The written value should always be '0' and the returned value is '0'. Bit 5 to 0 — Cycle Counter Register (CCR): Indicates the number of the current Base Cycle of the matrix cycle for Timer Triggered transmission. (6) Timer Counter Register (TCNTR) This is a 16-bit read/write register that allows the CPU to monitor and modify the value of the Free Running Timer Counter. When the Timer meets TCMR0 (Timer Compare Match Register 0) + TTCR0 [6] is set to '1', the TCNTR is cleared to H'0000 and starts running again. In TimeTrigger mode, this timer can be used as Local Time and TTCR0[6] has to be cleared to work as a free running timer. Notes: 1. It is possible to write into this register only when it is enabled by the bit 15 in TTCR0. If TTCR0 bit15 = 0, TCNTR is always H'0000. 2. There could be a delay of a few clock cycles between the enabling of the timer and the moment where TCNTR starts incrementing. This is caused by the internal logic used for the pre-scaler.  TCNTR (Address = H'08C) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCNTR[15:0] Initial value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * The register can be written only when enabled in TTCR0[15]. Write operation is not allowed in Time Trigger mode (i.e. CMAX is not 3'b111). Bit 15 to 0 — Indicate the value of the Free Running Timer. (7) Cycle Time register (CYCTR) This register is a 16-bit read-only register. This register shows Cycle Time = Local Time (TCNTR) - Reference_Mark (RFMK). In ET mode this register is the exact copy of TCNTR as RFMK is always fixed to zero.  CYCTR (Address = H'090) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R CYCTR[15:0] Initial value: R/W: 0 R Page 1224 of 3092 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (8) Section 23 Controller Area Network Reference Mark Register (RFMK) This register is a 16-bit read-only register. The purpose of this register is to capture Local Time (TCNTR) at SOF of the reference message when the message is received or transmitted successfully. In ET mode this register is not used and it is always cleared to zero.  RFMK (Address = H'094) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R RFMK[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15 to 0 — Reference Mark Register (RFMK): Indicates the value of TCNTR at SOF of time reference message. (9) Timer Compare Match Registers (TCMR0, TCMR1, TCMR2) These three registers are 16-bit read/write registers and are capable of generating interrupt signals, clearing-setting the Timer value (only supported by TCMR0) or clear the transmission messages in the queue (only supported by TCMR2). TCMR0 is compared with TCNTR, however, TCMR1 and TCMR2 are compared with CYCTR. The value used for the compare can be configured independently for each register. In order to set flags, TTCR0 bit 12-10 needs to be set. In Time-Trigger mode, TTCR0 bit6 has to be cleared by software to prevent TCNTR from being cleared. TMCR0 is for Init_Watch_Trigger, and TCMR2 is for Watch_Trigger. Interrupt: The interrupts are flagged by the Bit11, Bit15 and 14 in the IRR accordingly when a Compare Match occurs, and setting these bits can be enabled by Bit12, Bit11, Bit10 in TTCR0. The generation of interrupt signals itself can be prevented by the Bit11, Bit15 and Bit14 in the IMR. When a Compare Match occurs and the IRR11 (or IRR15 or IRR14) is set, the Bit3 or Bit2 or Bit1 in the TSR (Timer Status Register) is also set. Clearing the IRR bit also clears the corresponding bit of TSR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1225 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Timer Clear-Set: The Timer value can only be cleared when a Compare Match occurs if it is enabled by the Bit6 in the TTCR0. TCMR1 and TCMR2 do not have this function. Cancellation of the messages in the transmission queue: The messages in the transmission queue can only be cleared by the TCMR2 through setting TXCR when a Compare Match occurs while this module is not in the halt status. TCMR1 and TCMR0 do not have this function.  TCMR0 (Address = H'098) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TCMR0[15:0] Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 to 0 — Timer Compare Match Register (TCMR0): Indicates the value of TCNTR when compare match occurs.  TCMR1 (Address = H'09C) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TCMR1[15:0] Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 to 0 — Timer Compare Match Register (TCMR1): Indicates the value of CYCTR when compare match occurs.  TCMR2 (Address = H'0A0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TCMR2[15:0] Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 to 0 — Timer Compare Match Register (TCMR2): Indicates the value of CYCTR when compare match occurs. Page 1226 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network (10) Tx-Trigger Time Selection Register (TTTSEL) This register is a 16-bit read/write register and specifies the Tx-Trigger Time waiting for compare match with Cycle Time. Only one bit is allowed to be set. Please don't set more bits than one, or clear all bits. This register may only be modified during configuration mode. The modification algorithm is shown in figure 23.13. Please note that this register is only indented for test and diagnosis. When not in test mode, this register must not be written to and the returned value is not guaranteed.  TTTSEL (Address = H'0A4) Bit: 15 14 13 - Initial value: R/W: 0 R 12 11 10 9 8 TTTSEL[14:8] 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 - - - - - - - 0 - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Only one bit is allowed to be set. Bit 15: Reserved. The written value should always be '0' and the returned value is '0'. Bit 14 to 8 — Specifies the Tx-Trigger Time waiting for compare match with CYCTR The bit 14 to 8 corresponds to Mailbox-30 to 24, respectively. Bits 7 to 0: Reserved. The written value should always be '0' and the returned value is '0'. CYCTR = TTT24 or MBC[24] != 0x000 MB24 CYCTR = TTT25 or MBC[25] != 0x000 MB25 CYCTR = TTT26 or MBC[26] != 0x000 MB26 CYCTR = TTT27 or MBC[27] != 0x000 MB27 CYCTR = TTT28 or MBC[28] != 0x000 MB28 CYCTR = TTT29 or reset MBC[29] != 0x000 MB29 MB30 reception/transmission of reference message CYCTR = TTT30 or MBC[30] != 0x000 or reception of reference message Figure 23.13 TTTSEL modification algorithm R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1227 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.4 Application Note 23.4.1 Test Mode Settings This module has various test modes. The register TST[2:0] (MCR[10:8]) is used to select this module test mode. The default (initialised) settings allow this module to operate in Normal mode. The following table is examples for test modes. Test Mode can be selected only while in configuration mode. The user must then exit the configuration mode (ensuring BCR0/BCR1 is set) in order to run the selected test mode. Bit10: TST2 Bit9: TST1 Bit8: TST0 Description 0 0 0 Normal Mode (initial value) 0 0 1 Listen-Only Mode (Receive-Only Mode) 0 1 0 Self Test Mode 1 (External) 0 1 1 Self Test Mode 2 (Internal) 1 0 0 Write Error Counter 1 0 1 Error Passive Mode 1 1 0 Setting prohibited 1 1 1 Setting prohibited Normal Mode: This module operates in the normal mode. Listen-Only Mode: ISO-11898 requires this mode for baud rate detection. The Error Counters are cleared and disabled so that the TEC/REC does not increase the values, and the CTxn (n = 0 to 2) Output is disabled so that this module does not generate error frames or acknowledgment bits. IRR13 is set when a message error occurs. Self Test Mode 1: This module generates its own Acknowledge bit, and can store its own messages into a reception mailbox (if required). The CRxn/CTxn (n = 0 to 2) pins must be connected to the CAN bus. Page 1228 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Self Test Mode 2: This module generates its own Acknowledge bit, and can store its own messages into a reception mailbox (if required). The CRxn/CTxn (n = 0 to 2) pins do not need to be connected to the CAN bus or any external devices, as the internal CTxn (n = 0 to 2) is looped back to the internal CRxn (n = 0 to 2). CTxn (n = 0 to 2) pin outputs only recessive bits and CRxn (n = 0 to 2) pin is disabled. Write Error Counter: TEC/REC can be written in this mode. This module can be forced to become an Error Passive mode by writing a value greater than 127 into the Error Counters. The value written into TEC is used to write into REC, so only the same value can be set to these registers. Similarly, this module can be forced to become an Error Warning by writing a value greater than 95 into them. This module needs to be in Halt Mode when writing into TEC/REC (MCR1 must be "1" when writing to the Error Counter). Furthermore this test mode needs to be exited prior to leaving Halt mode. Error Passive Mode: This module can be forced to enter Error Passive mode. Note: The REC will not be modified by implementing this Mode. However, once running in Error Passive Mode, the REC will increase normally should errors be received. In this Mode, this module will enter BusOff if TEC reaches 256 (Dec). However when this mode is used this module will not be able to become Error Active. Consequently, at the end of the Bus Off recovery sequence, this module will move to Error Passive and not to Error Active. When message error occurs, IRR13 is set in all test modes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1229 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.4.2 Configuration of This Module This module is considered in configuration mode or after a H/W (Power On Reset)/S/W (MCR[0]) reset or when in Halt mode. In both conditions this module cannot join the CAN Bus activity and configuration changes have no impact on the traffic on the CAN Bus.  After a Reset request The following sequence must be implemented to configure this module after (S/W or H/W) reset. After reset, all the registers are initialised, therefore, this module needs to be configured before joining the CAN bus activity. Please read the notes carefully. Reset Sequence Configuration Mode Power On/SW Reset*1 MCR[0] = 1 (automatically in hardware reset only) No GSR[3] = 0? IRR[0] = 1, GSR[3] = 1 (automatically) Yes Clear IRR[0] Bit RCAN-TL1 is in Tx_Rx Mode Configure MCR[15] - Set TXPR to start transmission - or stay idle to receive Clear Required IMR Bits RCAN-TL1 Timer Reg Setting Mailbox Setting (STD-ID, EXT-ID, LAFM, DLC, RTR, IDE, MBC, MBIMR, DART, ATX, NMC, Tx-Trigger Time Message-Data)*2 Transmission_Reception (Tx_Rx) Mode Detect 11 recessive bits and Join the CAN bus activity Receive*3 Transmit*3 Timer Start*4 Set Bit Timing (BCR) Clear MCR[0] Notes: 1. 2. 3. 4. SW reset could be performed at any time by setting MCR[0] = 1. Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC. If there is no TXPR set, RCAN-TL1 will receive the next incoming message. If there is a TXPR(s) set, RCAN-TL1 will start transmission of the message and will be arbitrated by the CAN bus. If it loses the arbitration, it will become a receiver. Timer can be started at any time after the Timer Control regs and Tx-Trigger Time are set. Figure 23.14 Reset Sequence Page 1230 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  Halt mode When this module is in Halt mode, it cannot take part to the CAN bus activity. Consequently the user can modify all the requested registers without influencing existing traffic on the CAN Bus. It is important for this that the user waits for this module to be in halt mode before to modify the requested registers - note that the transition to Halt Mode is not always immediate (transition will occurs when the CAN Bus is idle or in intermission). After this module transit to Halt Mode, GSR4 is set. Once the configuration is completed the Halt request needs to be released. This module will join CAN Bus activity after the detection of 11 recessive bits on the CAN Bus.  Sleep mode When this module is in sleep mode the clock for the main blocks of the IP is stopped in order to reduce power consumption. Only the following user registers are clocked and can be accessed: MCR, GSR, IRR and IMR. Interrupt related to transmission (TXACK and ABACK) and reception (RXPR and RFPR) cannot be cleared when in sleep mode (as TXACK, ABACK, RXPR and RFPR are not accessible) and must to be cleared beforehand. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1231 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network The following diagram shows the flow to follow to move this module into sleep mode. Sleep Mode Sequence flow Halt Request Write MCR[1] = 1 : Hardware operation No : Manual operation User monitor GSR[4] = 1 Yes IRR[0] = 1 Write IRR[0] = 1 IRR[0] = 0 Sleep Request Write MCR[1] = 0 & MCR[5] = 1 IRR[0] = 1 Write IRR[0] = 1 IRR[0] = 0 Sleep Mode No CAN Bus Activity CLK is STOP Yes Only MCR, GSR, IRR, IMR can be accessed. IRR[12] = 1 MCR[7] = 1 No Yes Write IRR[12] = 1 IRR[12] = 0 MCR[5] = 0 Write MCR[5] = 0 Write IRR[12] = 1 IRR[12] = 0 GSR4 = 0 No User monitor Yes Transmission/Reception Mode Page 1232 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Figure 23.15 shows allowed state transitions.  Please don't set MCR5 (Sleep Mode) without entering Halt Mode.  After MCR1 is set, please don't clear it before GSR4 is set and this module enters Halt Mode. Power On/SW Reset Reset clear MCR0 and GSR3 = 0 clear MCR1 and MCR5 Transmission Reception set MCR1*3 clear MCR5*1 clear MCR5 set MCR1*4 Halt Request except Transmitter/Receiver/BusOff, if MCR6 = 0 BusOff or except Transmitter/Receiver, if MCR6 = 1 Halt Mode Sleep Mode set MCR5 clear MCR1*2 Figure 23.15 Halt Mode/Sleep Mode Notes: 1. MCR5 can be cleared by automatically by detecting a dominant bit on the CAN Bus if MCR7 is set or by writing '0'. 2. MCR1 is cleared in SW. Clearing MCR1 and setting MCR5 have to be carried out by the same instruction. 3. MCR1 must not be cleared in SW, before GSR4 is set. MCR1 can be set automatically in HW when this module moves to Bus Off and MCR14 and MCR6 are both set. 4. When MCR5 is cleared and MCR1 is set at the same time, this module moves to Halt Request. Right after that, it moves to Halt Mode with no reception/transmission. The following table shows conditions to access registers. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1233 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Registers Mailbox Trigger Time TT control MBIMR timer MCR IRR Status Mode GSR IMR Flag_ Mailbox BCR TT_register register (ctrl0, LAFM) Reset yes yes yes Transmission yes Reception Halt Request yes no* yes yes yes 1 yes yes no* Halt yes yes no* 1 yes yes Sleep yes yes no no no Mailbox Mailbox (data) (ctrl1) yes 1 2 yes* yes 2 yes 1 2 2 yes* no* yes* yes* yes yes yes yes no no no no Notes: 1. No hardware protection. 2. When TXPR is not set. 23.4.3 Message Transmission Sequence  Message Transmission Request The following sequence is an example to transmit a CAN frame onto the bus. As described in the previous register section, please note that IRR8 is set when one of the TXACK or ABACK bits is set, meaning one of the Mailboxes has completed its transmission or transmission abortion and is now ready to be updated for the next transmission, whereas, the GSR2 means that there is currently no transmission request made (No TXPR flags set). Page 1234 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Mailbox[x] is ready to be updated for next transmission RCAN-TL1 is in Tx_Rx Mode (MBC[x] = 0) Update Message Data of Mailbox[x] Clear TXACK[x] Yes Write '1' to the TXPR[x] bit at any desired time Internal Arbitration 'x' Highest Priority? TXACK[x] set? No No Waiting for Interrupt No Waiting for Interrupt Yes IRR8 set? Yes Transmission Start CAN Bus Arbitration End Of Frame CAN Bus Figure 23.16 Transmission request  Internal Arbitration for transmission The following diagram explains how this module manages to schedule transmission-requested messages in the correct order based on the CAN identifier. 'Internal arbitration' picks up the highest priority message amongst transmit-requested messages. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1235 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Transmission Frame-1 CAN bus state RCAN-TL1 scheduler state Bus Idle SOF Tx Arb for Frame-3 Transmission Frame-3 Message EOF Interm SOF Message Tx Arb for Tx/Rx Arb for Frame-1 Frame-1 Reception Frame-2 Tx/Rx Arb for Frame-3/2 EOF Interm SOF Tx Arb for Frame-3 Tx/Rx Arb for Frame-3 Scheduler start point TXPR/TXCR/ Error/Arb-Lost Set Point 1-1 Interm: SOF: EOF: Message: 1-2 2-1 2-2 3-1 3-2 Intermission Field Start Of Frame End Of Frame Arbitration + Control + Data + CRC + Ack Field Figure 23.17 Internal Arbitration for transmission This module has two state machines. One is for transmission, and the other is for reception. 1-1: 1-2: 2-1: 2-2: 3-1: 3-2: When a TXPR bit(s) is set while the CAN bus is idle, the internal arbitration starts running immediately and the transmission is started. Operations for both transmission and reception starts at SOF. Since there is no reception frame, this module becomes transmitter. At crc delimiter, internal arbitration to search next message transmitted starts. Operations for both transmission and reception starts at SOF. Because of a reception frame with higher priority, this module becomes receiver. Therefore, Reception is carried out instead of transmitting Frame-3. At crc delimiter, internal arbitration to search next message transmitted starts. Operations for both transmission and reception starts at SOF. Since a transmission frame has higher priority than reception one, this module becomes transmitter. Internal arbitration for the next transmission is also performed at the beginning of each error delimiter in case of an error is detected on the CAN Bus. It is also performed at the beginning of error delimiters following overload frame. As the arbitration for transmission is performed at CRC delimiter, in case a remote frame request is received into a Mailbox with ATX = 1 the answer can join the arbitration for transmission only at the following Bus Idle, CRC delimiter or Error Delimiter. Depending on the status of the CAN bus, following the assertion of the TXCR, the corresponding Message abortion can be handled with a delay of maximum 1 CAN Frame. Page 1236 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 23 Controller Area Network Time Triggered Transmission This module offers a H/W support to perform communication in Time Trigger mode in line with the emerging ISO-11898-4 Level 1 Specification. This section reports the basic procedures to use this mode.  Setting Time Trigger Mode In order to set up the time trigger mode the following settings need to be used.     CMAX in CMAX_TEW must be programmed to a value different from 3'b111. Bit 15 in TTCR0 has to be set, to start TCNTR. Bit 6 in TTCR0 has to be cleared to prevent TCNTR from being cleared after a match. DART in Mailboxes used for time-triggered transmission cannot be used, since for Time Triggered Mailboxes, TXPR is not cleared to support periodic transmission.  Roles of Registers The user registers of this module can be used to handle the main functions requested by the TTCAN standard. TCNTR Local Time RFMK Ref_Mark CYCTR Cycle Time = TCNTR - RFMK RFTROFF Ref_Trigger_Offset for Mailbox-30 Mailbox-31 Mailbox dedicated to the reception of time reference message Mailbox-30 Mailbox dedicated to the transmission of time reference message when working as a potential time master Mailbox-29 to 24 Mailboxes supporting time-triggered transmission Mailbox-23 to 16 Mailboxes supporting reception without timestamp (may also be implemented as Mailboxes supporting Event Triggered transmission) Mailbox-15 to 0 Mailboxes supporting reception with timestamp timestamp (may also be implemented as Mailboxes supporting Event Triggered transmission) Tx-Trigger Time Time_Mark to specify when a message should be transmitted R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1237 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group CMAX Specifies the maximum number of basic cycles when working as potential time master TEW Specify the width of Tx_Enable TCMR0 Init_Watch_Trigger (compare match with Local Time) TCMR1 Compare match with Cycle Time to monitor users-specified events TCMR2 Watch_Trigger (compare match with Cycle Time). This can be programmed to abort all pending transmissions TTW Specifies the attribute of a time window used for transmission TTTSEL Specifies the next Mailbox waiting for transmission  Time Master/Time Slave This module can be programmed to work as a potential time master of the network or as a time slave. The following table shows the settings and the operation automatically performed by this module in each mode. Page 1238 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network mode requested setting function Time Slave TXPR[30] = 0 TCNTR is sampled at each SOF detected on the CAN Bus and stored into an internal register. When a valid Time Reference Message is received into Mailbox-31 the value of TCNTR (stored at the SOF) is copied into Ref_Mark. & MBC[30]!= 3'b000 & CMAX!= 3'b111 CCR embedded in the received Reference Message is copied to CCR. & If Next_is_Gap = 1, IRR13 is set. MBC[31] = 3'b011 (Potential) TXPR[30] = 1 Two cases are covered: Time Master & (1) When a valid Time Reference message is received into Mailbox-31 the value of TCNTR stored into an internal register at the SOF is copied into Ref_Mark. MBC[30] = 3'b000 & DLC[30] > 0 & CMAX!= 3'b111 & MBC[31] = 3'b011 CCR embedded in the received Reference Message is copied to CCR. If Next_is_Gap = 1, IRR13 is set. (2) When a Time Reference message is transmitted from Mailbox-30 the value of TCNTR stored into an internal register at the SOF is copied into Ref_Mark. CCR is incremented when TTT of Mailbox-30 matches with CYCTR . CCR is embedded into the first data byte of the time reference message { Data0[7:6], CCR[5:0] } .  Setting Tx-Trigger Time The Tx-Trigger Time(TTT) must be set in ascending order shown below, and the difference between them has to satisfy the following expressions. TEW in the following expressions is the register value. TTT (Mailbox-24) < TTT (Mailbox-25) < TTT (Mailbox-26) < TTT (Mailbox-27) < TTT (Mailbox-28) < TTT (Mailbox-29) < TTT (Mailbox-30) and TTT (Mailbox-i) – TTT (Mailbox- i-1) > TEW + the maximum frame length + 9 TTT (Mailbox-24) to TTT (Mailbox-29) correspond to Time_Marks, and TTT (Mailbox-30) corresponds to Time_Ref showing the length of a basic cycle, respectively when working as potential time master. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1239 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network The above limitation is not applied to mailboxes which are not set as time-triggered transmission. Important: Because of limitation on setting Tx-Trigger Time, only one Mailbox can be assigned to one time window. TTT24 CCR = 0 TTT25 CCR = 2 CCR = 3 Mailbox-24 (Tx) Mailbox-24 (Tx) CCR = 1 TTT24 and TTT25 Mailbox-25 (Tx) Mailbox-25 (Tx) Mailbox-24 (Tx) Mailbox-24 (Tx) Mailbox-25 (Tx) supported by RCAN-TL1 Mailbox-25 (Tx) NOT supported by RCAN-TL1 Figure 23.18 Limitation on Tx-Trigger Time The value of TCMR2 as Watch_Trigger has to be larger than TTT(Mailbox-30), which shows the length of a basic cycle. Page 1240 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network Figures 23.19 and 23.20 show examples of configurations for (Potential) Time Master and Time Slave. "L" in diagrams shows the length in time of the time reference messages. Time Master Cycle Time varies between L and Time_Ref + L Cycle Time = 0 =L = Time_Ref + L Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 copy CCR from received time reference at reception completion (no reception in Time Master) Watch_Trigger TCMR2 increment CCR (updated CCR has to be transmitted) CCR = 0 Time_Ref TTT in MB30 capture timestamp at SOF of transmission Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 Time_Ref TTT in MB30 CCR = 1 CCR = 1 Ref_Mark is updated at successful end of time reference transmission CCR = 1 Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 Time_Ref TTT in MB30 L Cycle Time = Time_Ref CCR = 2 = Time_Ref + L Figure 23.19 (Potential) Time Master R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1241 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Slave Cycle Time varies between L and Time_Ref + L Cycle Time = 0 =L = Time_Ref Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 copy CCR from received time reference Time_Ref TTT in MB30 Watch_Trigger TCMR2 CCR isn't incremented unlike time master CCR = 0 = Time_Ref + L capture timestamp at SOF of reception Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 Time_Ref TTT in MB30 Time_Mark 4 TTT in MB27 Time_Mark 5 TTT in MB28 Time_Mark 6 TTT in MB29 Time_Ref TTT in MB30 CCR = 0 Ref_Mark and CCR are updated at successful end of time reference reception CCR = 1 Time_Mark 1 TTT in MB24 Time_Mark 2 TTT in MB25 Time_Mark 3 TTT in MB26 L Cycle Time = Time_Ref = Time_Ref + L Figure 23.20 Time Slave  Function to be implemented by software Some of the TTCAN functions need to be implemented in software. The main details are reported hereafter. Please refer to ISO-11898-4 for more details.  Change from Init_Watch_Trigger to Watch_Trigger This module offers the two registers TCMR0 and TCMR2 as H/W support for Init_Watch_Trigger and Watch_Trigger respectively. The SW is requested to enable TCMR0 and disable TCMR2 up to the first reference message is detected on the CAN Bus and then disable TCMR0 and enable TCMR2.- Schedule Synchronization state machine. Only reception of Next_is_Gap interrupt is supported. The application needs to take care of stopping all transmission at the end of the current basic cycle by setting the related TXCR flags.Master-Slave Mode control. Only automatic cycle time synchronization and CCR increment is supported.  Message status count Software has to count scheduling errors for periodic messages in exclusive windows. Page 1242 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network  Message Transmission Request for Time Triggered communication When the Time Triggered mode is used communications must fulfils the ISO11898-4 requirements. The following procedure should be used.       Send this module to reset or halt mode  Set TCMR0 to the Init_Watch_Trigger (0xFFFF)  Enable TCMR0 compare match setting bit 10 of TTCR0  Set TCMR2 to the specified Watch_Trigger value  Keep TCMR2 compare match disabled by keeping cleared the bit 12 of TTCR0  Set CMAX to the requested value (different from 111 bin)  Set TEW to the requested value  Configure the necessary Mailboxes for Time Trigger transmission and reception  Set LAFM for the 3 LSBs of Mailbox 31  Configure MCR, BCR1 and BCR0 to the requested values  If working as a potential time master: Set RFTROFF to the requested Init_Ref_Offset value Set TXPR for Mailbox 30 Write H'4000 into TTTSEL  Enable the TCNTR timer through the bit 15 of TTCR0  Move to Transmission_Reception mode  Wait for the reception or transmission of a valid reference message or for TCMR0 match  If the local time reaches the value of TCMR0 the Init_Watch_Trigger is reached and the application needs to set TXCR for Mailbox 30 and start again  If the reference message is transmitted (TXACK[30] is set) set RFTROFF to zero  If a valid reference message is received (RXPR[31] is set) then: If 3 LSBs of ID of Mailbox 31 have high priority than the 3 LSBs of Mailbox 30 (if working as potential time master) keep RFTROFF to Init_Ref_Offset If 3 LSBs of ID of Mailbox 31 have lower priority than the 3 LSBs of Mailbox 30 (if working as potential time master) decrement by 1 the value in RFTROFF  Disable TCMR0 compare match by clearing bit 10 of TTCR0  Enable TCMR2 compare match by setting bit 12 of TTCR0  Only after two reference messages have been detected on the CAN Bus (transmitted or received) can the application set TXPR for the other Time Triggered Mailboxes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1243 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network If, at any time, a reference message cannot be detected on the CAN Bus, and the cycle time CYCTR reaches TCMR2, this module automatically aborts all pending transmissions (including the Reference Message). The following is the sequence to request further transmission in Time Triggered mode. Update data before next match of Tx-Trigger Time Idle (wait for Time-Trigger) Mailbox[x] is ready to be updated for next transmission Compare match Clear TXACK[x] No Bus Idle? TXACK[x] = 1 ? No Waiting for Interrupt No Waiting for Interrupt Yes Yes Transmission Start IRR8 = 1 ? No Arbitration on Bus End Of Frame CAN Bus Figure 23.21 Message transmission request S/W has to ensure that a message is updated before a Tx trigger for transmission occurs. When the CYCTR reaches to TTT (Tx-Trigger Time) of a Mailbox and CCR matches with the programmed cycle for transmission, this module immediately transfers the message into the Tx buffer. At this point, this module will attempt a transmission within the specified Time Enable Window. If this module misses this time slot, it will suspend the transmission request up to the next Tx Trigger, keeping the corresponding TXPR bit set to '1' if the transmission is periodic (Mailbox-24 to 30). There are three factors that may cause this module to miss the time slot – 1. The CAN bus currently used 2. An error on the CAN bus during the time triggered message transmission 3. Arbitration loss during the time triggered message transmission Page 1244 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network In case of Merged Arbitrating Window the slot for transmission goes from the Tx_Trig of the Mailbox opening the Window (TTW = 10 bin) to the end to the TEW of the Mailbox closing the Window (TTW = 11 bin).The TXPR can be modified at any time. This module ensures the transmission of Time Triggered messages is always scheduled correctly. However, in order to guarantee the correct schedule, there are some important rules that are :  TTT (Tx Trigger Time) can be modified during configuration mode.  TTT cannot be set outside the range of Time_Ref, which specifies the length of basic cycle. This could cause a scheduling problem.  TXPR is not automatically cleared for periodic transmission. If a periodic transmission needs to be cancelled, the corresponding TXCR bit needs to be set by the application.  Example of Time Triggered System The following diagram shows a simple example of how time trigger system works using this module in time slave mode. TTT24 CCR = 0 TTT25 Mailbox-24 (Tx) CCR = 1 TTT26 TTT27 Mailbox-24 (Tx) TTT29 Mailbox-25 to 27 (Tx) Mailbox-25 to 27 (Tx) CCR = 2 TTT28 Mailbox-28 (Tx) Mailbox-25 to 27 (Tx) Mailbox-25 to 27 (Tx) CCR = 3 Mailbox-24 (Tx) CCR = 4 Mailbox-25 to 27 (Tx) Mailbox-25 to 27 (Tx) CCR = 5 Mailbox-24 (Tx) CCR = 6 Mailbox-28 (Tx) Mailbox-25 to 27 (Tx) Mailbox-29 (Tx) Mailbox-25 to 27 (Tx) CCR = 7 time reference exclusive window merged arbitrating window exclusive window arbitrating window Figure 23.22 Example of Time trigger system as Time Slave R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1245 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network The following settings were used in the above example: rep_factor (register) Offset TTW[1:0] MBC[2:0] Mailbox-24 3'b001 6'b000000 2'b00 3'b000 Mailbox-25 3'b000 6'b000000 2'b10 3'b000 Mailbox-26 3'b000 6'b000000 2'b10 3'b000 Mailbox-27 3'b000 6'b000000 2'b11 3'b000 Mailbox-28 3'b010 6'b000001 2'b00 3'b000 Mailbox-29 3'b011 6'b000110 2'b01 3'b000 Mailbox-30    3'b111 Mailbox-31    3'b011 CMAX = 3'b011, TXPR[30] = 0 During merged arbitrating window, request by time-triggered transmission is served in the way of FCFS (First Come First Served). For example, if Mailbox-25 cannot be transmitted between TxTrigger Time 25 (TTT25) and TTT26, Mailbox-25 has higher priority than Mailbox-26 between TTT26 and 28. MBC needs to be set into 3'b111, in order to disable time-triggered transmission. If this module is Time Master, MBC[30] has to be 3'b000 and time reference window is automatically recognized as arbitrating window.  Timer Operation Figure 23.23 shows the timing diagram of the timer. By setting Tx-Trigger Time = n, time trigger transmission starts between CYCTR = n + 2 and CYCTR = n + 3. Page 1246 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network (1) Clear TCNTR by TCMR0 in Event-Trigger mode TCMR0 TCNTR n n-2 n-1 n 0 1 2 3 n+1 n+2 n+3 n+4 n+1 n+2 n+3 n+4 n+1 n+2 n+3 n+4 n+3 n+4 n+5 2 0 (2) Interrupt generation by TCMR0/1/2 in Event-Trigger mode n TCMR0/1/2 TCNTR n-2 n-1 n Flag/interrupt (3) Interrupt generation by TCMR0 in Time-Trigger mode n TCMR0 TCNTR n-2 n-1 n Flag/interrupt (4) Interrupt generation by TCMR1/2 in Time-Trigger mode n TCMR0/1/2 CYCTR n-2 n-1 n Flag/interrupt (5) Time-triggered transmission request in Time-Trigger mode, during bus idle n Tx-Trigger Time I CYCTR n-1 n n+1 TEW (register value) TEW counter n+2 2 0 1 Transmission request for MBI Transmitted message SOF Delay = (1 Bit Timing + 8 clocks) to (2 Bit Timings + 11 clocks) Figure 23.23 Timing Diagram of Timer R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1247 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group During merged arbitrating window, event-trigger transmission is served after completion of timetriggered transmission. For example, If transmission of Mailbox-25 is completed and CYCTR doesn't reach TTT26, event-trigger transmission starts based on message transmission priority specified by MCR2. TXPR of time-triggered transmission is not cleared after transmission completion, however, that of event-triggered transmission is cleared. Note: that in the case that the TXPR is not set for the Mailbox which is assigned to close the Merged Arbitrating Window (MAW), then the MAW will still be closed (at the end of the TEW following the TTT of the assigned Mailbox. Please refer to Table Roles of Mailboxes in section 23.3.2, Mailbox Structure. Page 1248 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 23.4.4 Section 23 Controller Area Network Message Receive Sequence The diagram below shows the message receive sequence. CAN Bus End Of Arbitration Field End Of Frame Controller Area Network IDLE Valid CAN-ID Received Valid CAN Frame Received N=N-1 Loop (N = 31; N ≥ 0; N = N - 1) Exit Interrupt Service Routine Compare ID with Mailbox[N] + LAFM[N] (if MBC is config to receive) Yes ID Matched? No No Yes N = 0? RXPR[N] (RFPR[N]) Already Set? Yes Store Mailbox-Number[N] and go back to idle state Interrupt signal Check and clear UMSR[N] ** Write 1 to RXPR[N] Write 1 to RFPR[N] Read Mailbox[N] Read Mailbox[N] Read RXPR[N] = 1 Read RFPR[N] = 1 Yes MSG OverWrite or OverRun? (NMC) OverWrite •Store Message by Overwriting •Set UMSR •Set IRR9 (if MBIMR[N] = 0) •Generate Interrupt Signal (if IMR9 = 0) •Set RXPR[N] (RFPR[N]) •Set IRR1 (IRR2) (if MBIMR[N] = 0) •Generate Interrupt Signal (if IMR1 (IMR2) = 0) No Check and clear UMSR[N] ** OverRun •Reject Message •Set UMSR •Set IRR9 (if MBIMR[N] = 0) •Generate Interrupt Signal (if IMR9 = 0) •Set RXPR[N] (RFPR[N]) * Interrupt signal Yes •Store Message •Set RXPR[N] (RFPR[N]) •Set IRR1 (IRR2) (if MBIMR[N] = 0) •Generate Interrupt Signal (if IMR1 (IMR2) = 0) IRR[1] set? No Read IRR Interrupt signal CPU received interrupt due to CAN Message Reception Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the message has not been updated. TimeStamp may also be updated, however it can be read properly before clearing RXPR[N]/RFPR[N]. 2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/ UMSR[N] when UMSR[N] = 1 and consider the message obsolate. Figure 23.24 Message receive sequence R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1249 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group When this module recognises the end of the Arbitration field while receiving a message, it starts comparing the received identifier to the identifiers set in the Mailboxes, starting from Mailbox-31 down to Mailbox-0. It first checks the MBC if it is configured as a receive box, and reads LAFM, and reads the CAN-ID of Mailbox-31 (if configured as receive) to finally compare them to the received ID. If it does not match, the same check takes place at Mailbox-30 (if configured as receive). Once this module finds a matching identifier, it stores the number of Mailbox-[N] into an internal buffer, stops the search, and goes back to idle state, waiting for the EndOfFrame (EOF) to come. When the 6th bit of EOF is notified by the CAN Interface logic, the received message is written or abandoned, depending on the NMC bit. No modification of configuration during communication is allowed. Entering Halt Mode is one of ways to modify configuration. If it is written into the corresponding Mailbox, including the CAN-ID, i.e., there is a possibility that the CAN-ID is overwritten by a different CAN-ID of the received message due to the LAFM used. This also implies that, if the identifier of a received message matches to ID + LAFM of 2 or more Mailboxes, the higher numbered Mailbox will always store the relevant messages and the lower numbered Mailbox will never receive messages. Therefore, the settings of the identifiers and LAFMs need to be carefully selected. With regards to the reception of data and remote frames described in the above flow diagram the clearing of the UMSR flag after the reading of IRR is to detect situations where a message is overwritten by a new incoming message stored in the same mailbox (if its NMC = 1) while the interrupt service routine is running. If during the final check of UMSR a overwrite condition is detected the message needs to be discarded and read again. In case UMSR is set and the Mailbox is configured for overrun (NMC = 0) the message is still valid, however it is obsolete as it is not reflecting the latest message monitored on the CAN Bus. Please access the full Mailbox content before clearing the related RXPR/RFPR flag. Please note that in the case a received remote frame is overwritten by a data frame, both the remote frame receive interrupt (IRR2) and data frame received interrupt (IRR1) and also the Receive Flags (RXPR and RFPR) are set. In an analogous way, the overwriting of a data frame by a remote frame, leads to setting both IRR2 and IRR1. When a message is received and stored into a Mailbox all the fields of the data not received are stored as zero. The same applies when a standard frame is received. The extended identifier part (EXTID[17:0]) is written as zero. Page 1250 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 23.4.5 Section 23 Controller Area Network Reconfiguration of Mailbox When re-configuration of Mailboxes is required, the following procedures should be taken.  Change configuration of transmit box Two cases are possible.  Change of ID, RTR, IDE, LAFM, Data, DLC, NMC, ATX, DART This change is possible only when MBC = 3'b000. Confirm that the corresponding TXPR is not set. The configuration (except MBC bit) can be changed at any time.  Change from transmit to receive configuration (MBC) Confirm that the corresponding TXPR is not set. The configuration can be changed only in Halt or reset state. Please note that it might take longer for this module to transit to halt state if it is receiving or transmitting a message (as the transition to the halt state is delayed until the end of the reception/transmission), and also this module will not be able to receive/transmit messages during the Halt state. In case this module is in the Bus Off state the transition to halt state depends on the configuration of the bit 6 of MCR and also bit and 14 of MCR.  Change configuration (ID, RTR, IDE, LAFM, Data, DLC, NMC, ATX, DART, MBC) of receiver box or Change receiver box to transmitter box The configuration can be changed only in Halt Mode. This module will not lose a message if the message is currently on the CAN bus and this module is a receiver. This module will be moving into Halt Mode after completing the current reception. Please note that it might take longer if this module is receiving or transmitting a message (as the transition to the halt state is delayed until the end of the reception/transmission), and also this module will not be able to receive/transmit messages during the Halt Mode. In case this module is in the Bus Off state the transition to halt mode depends on the configuration of the bit 6 and 14 of MCR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1251 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Method by Halt Mode RCAN-TL1 is in Tx_Rx Mode Set MCR[1] (Halt Mode) Is RCAN-TL1 Transmitter, Receiver or Bus Off? Finish current session Yes No Generate interrupt (IRR0) Read IRR0 & GSR4 as '1' RCAN-TL1 is in Halt Mode Change ID or MBC of Mailbox Clear MCR1 RCAN-TL1 is in Tx_Rx Mode The shadowed boxes need to be done by S/W (host processor) Figure 23.25 Change ID of receive box or Change receive box to transmit box Page 1252 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 23.5 Section 23 Controller Area Network Interrupt Sources Table 23.2 lists this module interrupt sources. These sources can be masked. Masking is implemented using the mailbox interrupt mask registers (MBIMR) and interrupt mask register (IMR). For details on the interrupt vector of each interrupt source, see section 7, Interrupt Controller. Table 23.2 Interrupt Sources Interrupt Description 1 ERSn* 1 OVRn* Interrupt Flag Error Passive Mode (TEC  128 or REC  128) IRR5 Bus Off (TEC  256)/Bus Off recovery IRR6 Error warning (TEC  96) IRR3 Error warning (REC  96) IRR4 Reset/halt/CAN sleep transition IRR0 Overload frame transmission IRR7 Unread message overwrite (overrun) IRR9 Start of new system matrix IRR10 TCMR2 compare match IRR11 Bus activity while in sleep mode IRR12 DMAC Activation Not possible Timer overrun/Next_is_Gap reception/message IRR13 error TCMR0 compare match IRR14 TCMR1 compare match IRR15 RM0n*1*2, Data frame reception RM1n*1*2 Remote frame reception IRR1*3 IRR2*3 SLEn*1 IRR8 Message transmission/transmission disabled (slot empty) Possible*4 Not possible Notes: 1. n = 0 to 2 2. RM0 is an interrupt generated by the remote request pending flag for mailbox 0 (RFPR0[0]) or the data frame receive flag for mailbox 0 (RXPR0[0]). RM1 is an interrupt generated by the remote request pending flag for mailbox n (RFPR0[n]) or the data frame receive flag for mailbox n (RXPR0[n]) (n = 1 to 31). 3. IRR1 is a data frame received interrupt flag for mailboxes 0 to 31, and IRR2 is a remote frame request interrupt flag for mailboxes 0 to 31. 4. The direct memory access controller is activated only by an RM0n interrupt. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1253 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.6 DMAC Interface The DMAC can be activated by the reception of a message in mailbox 0. When DMAC transfer ends after DMAC activation has been set, flags of RXPR0 and RFPR0 are cleared automatically. An interrupt request due to a receive interrupt from this module cannot be sent to the CPU in this case. Figure 23.26 shows a DMAC transfer flowchart. : Settings by user DMAC initialization DMAC enable register setting DMAC register information setting : Processing by hardware Message reception in RCAN-TL1 mailbox 0 DMAC activation End of DMAC transfer? No Yes RXPR and RFPR flags clearing DMAC interrupt enabled? No Yes Interrupt to CPU END Figure 23.26 DMAC Transfer Flowchart Page 1254 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 23.7 Section 23 Controller Area Network CAN Bus Interface A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Renesas HA13721 transceiver IC and its compatible products are recommended. Figure 23.27 shows a sample connection diagram. 120 Ω This LSI 5V HA13721 MODE CRx CTx Level shifter Vcc Rxd CANH Txd CANL NC GND CAN bus 120 Ω Note: NC: No Connection Figure 23.27 High-Speed CAN Interface Using HA13721 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1255 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.8 Setting I/O Ports The I/O ports for this module must be specified before or during the configuration mode. For details on the settings of I/O ports, see section 48, General Purpose I/O Ports. Three methods are available using three channels of this module in this LSI.  32 Mailboxes  3 channels  64 Mailboxes  1 channel (RCAN0 and RCAN1) and 32 Mailboxes  1 channel (RCAN2)  96 Mailboxes  1 channel When the 64- or 96-Mailbox method is used, see section 23.9.1, Notes on Port Setting for Multiple Channels Used as Single Channel with 64 or 96 Mailboxes. Figures 23.28, 23.29, and 23.30 show connection examples for individual port settings. Channel 0 (32 Mailboxes) CTx0 CRx0 Channel 1 (32 Mailboxes) CTx1 CRx1 Channel 2 (32 Mailboxes) CTx2 CRx2 CTx0 CRx0 CTx1 CRx1 CTx2 CRx2 Figure 23.28 Connection Example when Using Each of Channels 0, 1 and 2 Independently (32 Mailboxes  3 Channels) Page 1256 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Channel 0 (32 Mailboxes) Section 23 Controller Area Network CTx0 CRx0 Channel 1 (32 Mailboxes) CTx1 CRx1 Channel 2 (32 Mailboxes) CTx2 CRx2 CTx0&CTx1 CRx0/CRx1 CTx2 CRx2 Figure 23.29 Connection Example when Using Channels 0 and 1 as One Channel (64 Mailboxes  1 Channel) and Channel 2 as One Channel (32 Mailboxes  1 Channel) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1257 of 3092 SH7268 Group, SH7269 Group Section 23 Controller Area Network Channel 0 (32 Mailboxes) CTx0 CRx0 Channel 1 (32 Mailboxes) CTx1 CRx1 Channel 2 (32 Mailboxes) CTx2 CRx2 CTx0&CTx1&CTx2 CRx0/CRx1/CRx2 Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as One Channel (96 Mailboxes  1 Channel) Page 1258 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 23 Controller Area Network 23.9 Usage Notes 23.9.1 Notes on Port Setting for Multiple Channels Used as Single Channel with 64 or 96 Mailboxes This module in this LSI has three channels and some of these channels can be used as a single channel. When using multiple channels as a single channel with 64 or 96 Mailboxes, keep the following in mind. Channel 0 (32 mailboxes) CTx0 CRx0 Channel 1 (32 mailboxes) CTx1 CRx1 Channel 2 (32 mailboxes) CTx2 CRx2 CTx0&CTx1 CRx0/CRx1 CTx2 CRx2 Figure 23.31 Connection Example when Using Channels 0 and 1 as One Channel (64 Mailboxes  1 Channel) and Channel 2 as One Channel (32 Mailboxes  1 Channel) 1. No ACK error is detected even when any other nodes are not connected to the CAN bus. This occurs when channel 1 transmits an ACK in the ACK field in response to a message channel 0 has transmitted. Channel 1 receives a message which channel 0 has transmitted on the CAN bus and then transmits an ACK in the ACK field. After that, channel 0 receives the ACK. To avoid this, make channel 1 which is not currently used for transmission the listen-only mode (TST[2:0] = B'001) or the reset state (MCR0 = 1). With this setting, only a channel which transmits a message transmits an ACK. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1259 of 3092 Section 23 Controller Area Network SH7268 Group, SH7269 Group 2. Internal arbitration for channels 0 and 1 is independently controlled to determine the order of transmission. Although the internal arbitration is performed on 31 Mailboxes at a time, it is not performed on 64 Mailboxes at a time even though multiple channels function as a single channel. 3. Do not set the same transmission message ID in both channels 0 and 1. Two messages may be transmitted from the two channels after arbitration on the CAN bus. Page 1260 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 24 IEBusTM Controller Section 24 IEBusTM Controller This LSI has an on-chip one-channel IEBus controller. The Inter Equipment BusTM (IEBusTM)* is a small-scale digital data transfer system for inter-equipment data transfer. This LSI does not have an on-chip IEBus driver/receiver, so it is necessary to mount a dedicated driver/receiver externally. In addition, as the IERxD and IETxD pins need 3V to operate, a dedicated external level shifter is necessary. Note: * The Inter Equipment BusTM (IEBusTM) is a trademark of Renesas Electronics Corporation. 24.1 Features  IEBus protocol control (layer 2) supported  Half-duplex asynchronous communications  Multi-master system  Broadcast communications function  Selectable mode (three types) with different transfer speeds  On-chip buffers for data transmission and reception  Transmission and reception buffers: 128 bytes each  Up to 128 bytes of consecutive transmit/reception (maximum number of transfer bytes in mode 2)  Operating frequency  12 MHz, 12.58 MHz (This module uses 1/2 divided clocks of AUDIO_X1* or AUDIO_X2*.)  18 MHz, 18.87 MHz (This module uses 1/3 divided clocks of AUDIO_X1* or AUDIO_X2*.)  24 MHz, 25.16 MHz (This module uses 1/4 divided clocks of PAUDIO_X1*, or AUDIO_X2*.)  30 MHz, 31.45 MHz (This module uses 1/5 divided clocks of PAUDIO_X1*, or AUDIO_X2*.)  36 MHz, 37.74 MHz (This module uses 1/6 divided clocks of AUDIO_X1* or AUDIO_X2*.)  42 MHz, 44.03 MHz (This module uses 1/7 divided clocks of AUDIO_X1* or AUDIO_X2*.)  48 MHz (This module uses 1/8 divided clocks of AUDIO_X1* or AUDIO_X2*.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1261 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Note: * Available as this module clock input only when not used as the clock input for serial sound interface, serial I/O with FIFO, or Renesas SPDIF interface.  Module standby mode can be set. Page 1262 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.1.1 IEBus Communications Protocol An overview of the IEBus is provided below.  Communications method: Half-duplex asynchronous communications  Multi-master system All units connected to the IEBus can transfer data to other units.  Broadcast communications function (one-to-many communications)  Group broadcast communications: Broadcast communications to group unit  General broadcast communications: Broadcast communications to all units  Mode is selectable (three modes with different transfer speeds) Table 24.1 Mode Types Mode IEB*1 = 12, 18, 24*2, 30, IEB*1 = 12.58, 18.87*2, 25.16, Maximum Number of 36, 42, 48 MHz 31.45, 37.74, 44.03 MHz Transfer Bytes (byte/frame) 0 About 3.9 kbps About 4.1 kbps 16 1 About 17 kbps About 18 kbps 32 2 About 26 kbps About 27 kbps 128 Notes: 1. Peripheral clock 0 (P0), or clocks for AUDIO_X1 and AUDIO_X2 2. Oscillation frequency when this LSI is used  Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection) Priority of bus mastership is as follows.  Broadcast communications (one-to-many communications) have priority over normal communications (one-to-one communications).  A smaller master address has priority.  Communications scale  Number of units: Up to 50  Cable length: Up to 150 m (when using a twisted-pair cable) Note: The communications scale of the actual system depends on the characteristics of the externally mounted IEBus driver/receiver and the cable used. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1263 of 3092 Section 24 IEBusTM Controller (1) SH7268 Group, SH7269 Group Determination of Bus Mastership (Arbitration) A unit connected to the IEBus performs an operation to get the bus to control other units. This operation is called arbitration. In arbitration, when multiple units start transferring simultaneously, the bus mastership is given to one unit among them. Only one unit can obtain bus mastership through arbitration, so the following priority for bus mastership is determined. (a) Priority according to communications type Broadcast communications (one-to-many communications) has priority over normal communications (one-to-one communications). (b) Priority according to master address The unit with the smallest master address has priority among units of the same communications type. Example: The master address is configured with 12 bits. A unit with H'000 has the highest priority, while a unit with H'FFF has the lowest priority. Note: When a unit loses in arbitration, the unit can automatically enter retransfer mode (0 to 7 retransfer times can be selected by the RN bit in IEMCR). Page 1264 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group (2) Communications Mode The IEBus has three communications modes with different transfer speeds. Table 24.2 shows the transfer speed in each communications mode and the maximum number of transfer bytes in one communications frame. Table 24.2 Transfer Speed and Maximum Number of Transfer Bytes in Each Communications Mode 1 Effective Transfer Speed* (kbps) IEB*2 = Maximum Number IEB*2 = Communications of Transfer Bytes 12, 18, 24, 30, 36, 42, 48 12.58, 18.87, 25.16, 31.45, 3 3 Mode (bytes/frame) MHz* 37.74, 44.03 MHz* 0 16 About 3.9 About 4.1 1 32 About 17 About 18 2 128 About 26 About 27 Notes: (3) Each unit connected to the IEBus should select a communications mode prior to performing communications. Note that correct communications is not guaranteed if the master and slave units do not adopt the same communications mode. In the case of communications between a unit with IEB = 6 MHz and a unit with IEB = 6.29 MHz, correct communications are not possible even if the same communications mode is adopted. Communications must be done with the same oscillation frequency. 1. Effective transfer speed when the maximum number of transfer bytes is transmitted. 2. Peripheral clock 0 (P0), or clocks for AUDIO_X1 and AUDIO_X2 3. Oscillation frequency when this LSI is used Communications Address In the IEBus, a specific 12-bit communications address is allocated to each individual unit. A communications address is configured as follows.  Upper four bits: group number (number identifying a group to which the unit belongs)  Lower eight bits: unit number (number identifying individual units in a group) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1265 of 3092 Section 24 IEBusTM Controller (4) SH7268 Group, SH7269 Group Broadcast Communications In normal transfer, a single master unit communicates with a single slave unit, so one-to-one transfer or reception takes place. In broadcast communications, a single master unit communicates with multiple slave units. Since there are multiple slave units, no acknowledgements are returned from the slave units during communications. A broadcast bit decides whether broadcast or normal communications is done. (For details of the broadcast bit, see section 24.1.2 (1) (b), Broadcast Bit. There are two types of broadcast communications. (a) Group broadcast communications Broadcast communications is aimed at units with the same group number, meaning that those units have the same upper four bits of the communications address. (b) General broadcast communications Broadcast communications is aimed at all units regardless of group number. Group broadcast and general broadcast communications are identified by a slave address. (For details on the slave address, see section 24.1.2 (3), Slave Address Field.) Page 1266 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.1.2 Communications Protocol Figure 24.1 shows an IEBus transfer signal format. Communications data is transferred as a series of signals referred to as a communications frame. The number of data, which can be transmitted in a single communications frame and the transfer speed, differs according to the communications mode. (When IEBφ = 12, 18, 24, 30, or 36 MHz) Field name Number of bits Header 1 Master address field 1 12 Start Broad- Master bit cast address bit 1 P Slave address field 12 1 1 Control field Slave address Control bits P A 4 1 1 P A Message length field 8 1 1 Message length bits P A Data field 8 1 Data bits 1 P A 8 Data bits 1 1 P A Transfer time Mode 0 Approximately 7330 μs Approximately 1590 × N μs Mode 1 Approximately 2090 μs Approximately 410 × N μs Mode 2 Approximately 1590 μs Approximately 300 × N μs P: Parity bit (1 bit) A: Acknowledge bit (1 bit) When A = 0: ACK When A = 1: NAK N: Number of bytes Note: The value of acknowledge bit is ignored in broadcast communications. Figure 24.1 Transfer Signal Format (1) Header A header is comprised of a start bit and a broadcast bit. (a) Start Bit The start bit is a signal to inform other units of the start of data transfer. A unit attempting to start data transfer outputs a low-level signal (the start bit) for a specified period and then outputs the broadcast bit. If another unit is already outputting a start bit when a unit attempts to output a start bit, the unit waits for completion of the start bit from the other unit without outputting its own start bit, and then outputs the broadcast bit synchronized with the completion timing. Other units enter the receive state after detecting the start bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1267 of 3092 Section 24 IEBusTM Controller (b) SH7268 Group, SH7269 Group Broadcast Bit The broadcast bit is a bit to identify the type of communications: broadcast or normal. When this bit is cleared to 0, it indicates broadcast communications. When it is set to 1, it indicates normal communications. Broadcast communications includes group broadcast and general broadcast, which are identified by a value of the slave address. (For details of the slave address, see section 24.1.2 (3), Slave Address Field.) Since multiple slave units are communications destination units, in the case of broadcast communications, the acknowledge bit is not returned from each field described in (2) and below. When more than one unit starts to transfer a communications frame with the same timing, broadcast communications has priority over normal communications, and arbitration occurs. (2) Master Address Field The master address field is a field for transmitting the unit address (master address) to other units. The master address field is comprised of master address bits and a parity bit. The master address consists of 12 bits and the MSB is output first. When more than one unit start to transfer broadcast bits having the same value with the same timing, arbitration is decided by the master address field. In the master address field, self-output data and data on the bus are compared for every one-bit transfer. If the self-output master address and data on the bus are different, the unit that loses arbitration will stop its transfer and enter the receive state. Since the IEBus is configured with wired AND, the unit having the smallest master address of the units in arbitration (arbitration master) wins in arbitration. Finally, only a single unit remains in the transfer state as a master unit after outputting a 12-bit master address. Next, this master unit outputs a parity bit*, defines the master address for other units, and then enters the slave address field output state. Note: * Since even parity is used, when the number of one bit in the master address is odd, the parity bit is 1. Page 1268 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 24 IEBusTM Controller Slave Address Field The slave address field is a field to transmit an address (the slave address) of a unit (the slave unit) to be transmitted. The slave address field is comprised of slave address bits, a parity bit, and an acknowledge bit. The slave address consists of 12 bits and the MSB is output first. The parity bit is output after the 12-bit slave address is transmitted to avoid receiving the slave address accidentally. The master unit then detects the acknowledgement from the slave unit to confirm that the slave unit exists on the bus. When the acknowledgement is detected, the master unit enters the control field output state. However, the master unit enters the control field output state without detecting the acknowledgement in broadcast communications. The slave unit returns an acknowledgement when the slave addresses match and the parities of the master and slave addresses are correct. When the parity of either the master or slave address is incorrect, the slave unit decides that the master or slave address was not correctly received and does not return the acknowledgement. In this case, the master unit enters the waiting (monitor) state and communications ends. In the case of broadcast communications, the slave address is used to identify the type of broadcast communications (group or general) as follows:  When the slave address is H'FFF: General broadcast communications  When the slave address is other than H'FFF: Group broadcast communications Note: The group number is the upper 4-bit value of the slave address in group broadcast communications. (4) Control Field The control field is a field for transmitting the type and direction of the following data field. The control field is comprised of control bits, a parity bit, and an acknowledge bit. The control bits consist of four bits and the MSB is output first. The parity bit is output following the control bits. When the parity is correct, and the slave unit can implement the function required from the master unit, the slave unit returns an acknowledgement and enters the message length field output state. However, if the slave unit cannot implement the requirements from the master unit even though the parity is correct, or if the parity is not correct, the slave unit does not return an acknowledgement and returns to the waiting (monitor) state. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1269 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group The master unit enters the subsequent message length field output state after confirming the acknowledgement. When the acknowledgement is not confirmed, the master unit enters the waiting (monitor) state, and communications ends. However, in the case of broadcast communications, the master unit enters the following message length field output state without confirming the acknowledgement. For details of the contents of the control bit, see table 24.4. (5) Message Length Field The message length field is a field for specifying the number of transfer bytes. The message length field is comprised of message length bits, a parity bit, and an acknowledge bit. The message length has eight bits and the MSB is output first. Table 24.3 shows the number of transfer bytes. Table 24.3 Contents of Message Length bits Message Length bits (Hexadecimal) Number of Transfer Bytes H'01 1 byte H'02 2 bytes : : H'FF 255 bytes H'00 256 bytes Note: If a number greater than the maximum number of transfer bytes in one frame is specified, communications are done in multiple frames depending on the communications mode. In this case, the message length bits indicate the number of remaining communications data after the first transfer. In this LSI, the message length bits must be smaller than the maximum number of transfer bytes in one frame. Set these within the ranges shown below. Mode 0: 1 to 16 bytes Mode 1: 1 to 32 bytes Mode 2: 1 to 128 bytes This field operation differs depending on the value of bit 3 in the control field: master transmission (the bit 3 of the control bits is 1) or master reception (the bit 3 of the control bits is 0). Page 1270 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (a) Section 24 IEBusTM Controller Master Transmission The master unit outputs the message length bits and the parity bit. When the parity is even, the slave unit returns an acknowledgement and enters the following data field. Note that the slave unit does not return an acknowledgement in broadcast communications. When the parity is odd, the slave unit decides that the message length field is not correctly received, does not return an acknowledgement, and returns to the waiting (monitor) state. In this case, the master unit also returns to the waiting state and communications end. (b) Master Reception The slave unit outputs the message length bits and parity bit. When even parity is confirmed, the master unit returns an acknowledgement. When the parity is not correct, the master unit decides that the message length bits are not correctly received, does not return an acknowledgement, and returns to the waiting state. In this case, the slave unit also returns to the waiting state and communications end. (6) Data Field The data field is a field for data transmission/reception to and from the slave unit. The master unit transmits/receives data to and from the slave unit using the data field. The data field is comprised of data bits, a parity bit, and an acknowledge bit. The data bits consist of eight bits and the MSB is output first. The parity and acknowledge bits are output following the data bits from the master unit and slave unit, respectively. Broadcast communications are performed only for the transmission of the master unit. In this case, the acknowledge bit is ignored. Operations in master transmission and master reception are described below. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1271 of 3092 Section 24 IEBusTM Controller (a) SH7268 Group, SH7269 Group Master Transmission The master unit transmits the data bits and parity bit to the slave unit to write data from the master unit to the slave unit. The slave unit receives the data bits and parity bit, and returns an acknowledgement if the parity bit is even and the receive buffer is empty. If the parity bit is odd or the receive buffer is not empty, the slave unit does not accept the corresponding data and does not return an acknowledgement. When the slave unit does not return an acknowledgement, the master unit retransmits the data. This operation is repeated until either an acknowledgement from the slave unit is detected or the maximum number of data transfer bytes is reached. When the parity is even and the acknowledgement is output from the slave unit, the master unit transmits the subsequent data if data remains and the maximum number of transfer bytes is not exceeded. In the case of broadcast communications, the slave unit does not return the acknowledgement, and the master unit transfers data byte by byte. (b) Master Reception The master unit outputs synchronous signals corresponding to all data bits to be read from the slave unit. The slave unit outputs the data bits and parity bit on the bus in accordance with the synchronous signals from the master unit. The master unit reads the parity bit output from the slave unit, and checks the parity. If the parity is not even, or the receive buffer is not empty, the master unit rejects acceptance of the data, and does not return the acknowledgement. The master unit reads the same data repeatedly if the number of data does not exceed the maximum number of transfer bytes in one frame. If the parity is even and the receive buffer is empty, the master unit accepts data and returns an acknowledgement. The master unit reads in the subsequent data if the number of data does not exceed the maximum number of transfer bytes in one frame. Page 1272 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (7) Section 24 IEBusTM Controller Parity bit The parity bit is used to confirm that transfer data occurs with no errors. The parity bit is added to respective data of the master address, slave address, control, message length, and data bits. Even parity is used. When the number of bits having the value 1 is odd, the parity bit is 1. When the number of bits having the value 1 is even, the parity bit is 0. (8) Acknowledge bit In normal communications (single unit to single unit communications), the acknowledge bit is added in the following positions to confirm that data is correctly accepted.     At the end of the slave address field At the end of the control field At the end of the message length field At the end of the data field The acknowledge bit is defined below.  0: indicates that the transfer data is acknowledged. (ACK)  1: indicates that the transfer data is not acknowledged. (NAK) Note that the acknowledge bit is ignored in the case of broadcast communications. (a) Acknowledge bit at the End of the Slave Address Field The acknowledge bit at the end of the slave address field becomes NAK in the following cases and transfer is stopped.  When the parity of the master address or slave address bits is incorrect  When a timing error (an error in bit format) occurs  When there is no slave unit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1273 of 3092 Section 24 IEBusTM Controller (b) SH7268 Group, SH7269 Group Acknowledge bit at the End of the Control Field The acknowledge bit at the end of the control field becomes NAK in the following cases and transfer is stopped.  When the parity of the control bits is incorrect  When the bit 3 of the control bits is 1 (data write) although the slave receive buffer* is not empty  When the control bits are set to data read (H'3, H'7) although the slave transmit buffer* is empty  When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or H'F in the control bits although the slave unit has been locked  When the control bits are the locked address read (H'4, H'5) although the unit is not locked  When a timing error occurs  When the control bits are undefined Note: See section 24.1.3 (1), Slave Status Read (Control Bits: H'0, H'6). (c) Acknowledge Bit at the End of the Message Length Field The acknowledge bit at the end of the message length field becomes NAK in the following cases and transfer is stopped.  When the parity of the message length bits is incorrect  When a timing error occurs (d) Acknowledge Bit at the End of the Data Field The acknowledge bit at the end of the data field becomes NAK in the following cases and transfer is stopped.  When the parity of the data bits is incorrect*  When a timing error occurs after the previous transfer of the acknowledge bit  When the receive buffer becomes full and cannot accept further data* Note: * In this case, the data field is transferred repeatedly until the number of data reaches the maximum number of transfer bytes if the number of data does not exceed the maximum number of transfer bytes in one frame. Page 1274 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.1.3 Transfer Data (Data Field Contents) The data field contents are specified by the control bits. Table 24.4 Control Bit Contents Setting Value Bit 3*1 Bit 2 Bit 1 Bit 0 Function*2 H'0 0 0 0 0 Reads slave status (SSR) H'1 0 0 0 1 Undefined. H'2 0 0 1 0 Undefined. H'3 0 0 1 1 Reads data and locks H'4 0 1 0 0 Reads locked address (lower 8 bits) H'5 0 1 0 1 Reads locked address (upper 4 bits) H'6 0 1 1 0 Reads slave status (SSR) and unlocks H'7 0 1 1 1 Reads data H'8 1 0 0 0 Undefined. H'9 1 0 0 1 Undefined. H'A 1 0 1 0 Writes command and locks H'B 1 0 1 1 Writes data and locks H'C 1 1 0 0 Undefined. H'D 1 1 0 1 Undefined. H'E 1 1 1 0 Writes command H'F 1 1 1 1 Writes data Notes: 1. Depending on the value of bit 3 (MSB), the transfer directions of the message length bits in the following message length field and data in the data field vary. When bit 3 is 1: Data is transferred from the master unit to the slave unit. When bit 3 is 0: Data is transferred from the slave unit to the master unit. 2. H'3, H'6, H'A, and H'B are control bits to specify lock setting and cancellation. When the undefined values of H'1, H'2, H'8, H'9, H'C, and H'D are transmitted, the acknowledge signal is not returned. When the control bits received from another unit which locked are not included in table 24.5, the slave unit which has been locked by the master unit does not accept the control bits and does not return the acknowledge bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1275 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Table 24.5 Control Field for Locked Slave Unit Setting Value Bit 3 Bit 2 H'0 0 0 0 0 Reads slave status H'4 0 1 0 0 Reads locked address (upper 8 bits) H'5 0 1 0 1 Reads locked address (lower 4 bits) (1) Bit 1 Bit 0 Function Slave Status Read (Control Bits: H'0, H'6) The master unit can decide the reason the slave unit does not return the acknowledgement (ACK) by reading the slave status (H'0, H'6). The slave status indicates the result of the last communications that the slave unit performed. All slave units can provide slave status information. Figure 24.2 shows the bit configuration of the slave status. MSB LSB Bit 6 Bit 7 Bit 4 Bit Value Description Bit 7, bit 6 00 Mode 0 01 10 Mode 1 Mode 2 Bit 3 Bit 2 Bit 1 Bit 0 Indicates the highest mode supported by a unit. *1 11 For future use Bit 5 0 Fixed 0 Bit 4*2 0 Slave transmission halted 1 Slave transmission enabled Bit 3 0 Fixed 0 Bit 2 0 1 Unit is unlocked Bit 1*3 0 Unit is locked Slave receive buffer is empty 1 Slave receive buffer is not empty 0 1 Slave transmit buffer is empty Bit 0*4 Notes: Bit 5 Slave transmit buffer is not empty 1. Since this LSI can support up to mode 2, bits 6 and 7 are fixed to 10. 2. The value of bit 4 can be selected by the STE bit in the IEBus master unit address register 1 (IEAR1). 3. The slave receive buffer is a buffer which is accessed during data write (control bits: H'A, H'B, H'E, H'F). In this LSI, the slave receive buffer corresponds to the IEBus receive buffer register (IERB001 to IERB128); and bit 1 is the value of the RXBSY bit in the IEBus receive status register (IERSR). 4. The slave transmit buffer is a buffer which is accessed during data read (control bits: H'3, H'7). In this LSI, the slave transmit buffer corresponds to the IEBus transmit buffer register (IETB001 to IETB128) and bit 0 is the value of the SRQ bit in the IEBus general flag registers (IEFLG). Figure 24.2 Bit Configuration of Slave Status (SSR) Page 1276 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group (2) Data Command Transfer (Control Bits: Read (H'3, H'7), Write (H'A, H'B, H'E, H'F)) In the case of data read (H'3, H'7), data in the data buffer of the slave unit is read in the master unit. In the case of data write (H'B or H'F) or command write (H'A or H'E), data received in the slave unit is processed in accordance with the operation specification of the slave unit. Notes: 1. The user can select data and commands freely in accordance with the system. 2. H'3, H'A, or H'B may lock depending on the communications condition and status. (3) Locked Address Read (Control Bits: H'4, H'5) In the case of the locked address read (H'4 or H'5), the address (12 bits) of the master unit, which issues the lock instruction, is configured in bytes as shown in figure 24.3. MSB LSB Control bits: H'4 Control bits: H'5 Lower 8 bits Undefined Upper 4 bits Figure 24.3 Locked Address Configuration (4) Locking/Unlocking (Control Bits: Setting (H'3, H'A, H'B), Cancellation: (H'6)) The lock function is used for message transfer over multiple communications frames. A locked unit receives data only from the unit which locked it. Locking and unlocking are described below. (a) Locking When an acknowledge bit of 0 in the message length field is transmitted/received with the control bits (H'3, H'A, H'B) indicating the lock operation, and then the communications frame is completed before completion of data transmission/reception for the number of bytes specified by the message length bits, the slave unit is locked by the master unit. In this case, the bit (bit 2) relevant to locking in the byte data indicating the slave status is set to 1. Lock is set only when the number of data exceeds the maximum number of transfer bytes in one frame. Lock is not set by other error terminations. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1277 of 3092 Section 24 IEBusTM Controller (b) SH7268 Group, SH7269 Group Unlocking When the control bits indicate the lock (H'3, H'A, or H'B) or unlock (H'6) operation and the byte data for the number of bytes specified by the message length bits are transmitted/received in a single communications frame, the slave unit is unlocked by the master unit. In this case, the bit (bit 2) relevant to locking in the byte indicating the slave status is cleared to 0. Note that locking and unlocking are not done in broadcast communications. Note: * There are three ways to cause a locked unit to unlock itself.  Perform a power-on reset  Put the unit in deep standby mode  Issue an unlock command through the IEBus command register (IECMR) Note that the LCK flag in IEFLG can be used to check whether the unit is locked or unlocked. 24.1.4 Bit Format Figure 24.4 shows the bit format (conceptual diagram) configuring the IEBus communications frame. Logic 1 Logic 0 Preparation period Synchronous period Data period Halt period Active low: Logic 1 = low level and logic 0 = high level Active high: Logic 1 = high level and logic 0 = low level Figure 24.4 IEBus Bit Format (Conceptual Diagram) Each period of the bit format for use of active high signals is described below.     Preparation period: first logic 1 period (high level) Synchronous period: subsequent logic 0 period (low level) Data period: period indicating bit value (logic 1: high level, logic 0: low level) Halt period: last logic 1 period (high level) Page 1278 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group For use of active low signals, levels are reversed from the active high signals. The synchronous and data periods have approximately the same length. The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit). 24.1.5 Configuration Figure 24.5 shows the entire block configuration and table 24.6 lists the functions of each block. Transmit data buffer Transmit controller Internal bus Internal bus interface IEBbus interface Register IEBus Receive controller Receive data buffer Figure 24.5 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1279 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Table 24.6 Functions of Each Block Block Function Internal bus interface Internal bus interface IEBus interface Register Data width: 8 bits  Register access Interface conforms to IEBus specifications  Outputs data from transmit controller to IEBus in IEBus specification bit format  Picks out frame data in IEBus specification bit format to transfer to receive controller Control register Transmit controller Receive controller Transmit data buffer Receive data buffer 24.2   Register to control this module  Readable/writable from internal bus Transmits data in transmit buffer to IEBus  Generates transmit frame combining header information in register and data in transmit buffer to transmits  Detects transmit error Stores data from IEBus in receive buffer  Stores header information and data in received frame in register and receive buffer, respectively  Detects receive error Buffer for data transmission  Buffer that stores data to be transmitted to IEBus  Buffer size: 128 bytes Buffer for data reception  Buffer that stores data received from IEBus  Buffer size: 128 bytes Input/Output Pins Table 24.7 Pin Configuration Name Abbreviation I/O Function IEBus receive data pin IERxD Input Receive data input pin IEBus transmit data pin IETxD Output Transmit data output pin Page 1280 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3 Register Descriptions Table 24.8 shows the register configuration. Table 24.8 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size IEBus control register IECTR R/W H'00 H'FFFE F000 8 IEBus command register IECMR W H'00 H'FFFE F001 8 IEBus master control register IEMCR R/W H'00 H'FFFE F002 8 IEBus master unit address register 1 IEAR1 R/W H'00 H'FFFE F003 8 IEBus master unit address register 2 IEAR2 R/W H'00 H'FFFE F004 8 IEBus slave address setting register 1 IESA1 R/W H'00 H'FFFE F005 8 IEBus slave address setting register 2 IESA2 R/W H'00 H'FFFE F006 8 IEBus transmit message length register IETBFL R/W H'00 H'FFFE F007 8 IEBus reception master address register 1 IEMA1 R H'00 H'FFFE F009 8 IEBus reception master address register 2 IEMA2 R H'00 H'FFFE F00A 8 IEBus receive control field register IERCTL R H'00 H'FFFE F00B 8 IEBus receive message length register IERBFL R H'00 H'FFFE F00C 8 IEBus lock address register 1 IELA1 R H'00 H'FFFE F00E 8 IEBus lock address register 2 IELA2 R H'00 H'FFFE F00F 8 IEBus general flag register IEFLG R H'00 H'FFFE F010 8 IEBus transmit status register IETSR R/(W)* H'00 H'FFFE F011 8 IEBus transmit interrupt enable register IEIET R/W H'00 H'FFFE F012 8 IEBus receive status register IERSR R/(W)* H'00 H'FFFE F014 8 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1281 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Register Name Abbreviation R/W Initial Value Address Access Size IEBus receive interrupt enable register IEIER R/W H'00 H'FFFE F015 8 IEBus clock select register IECKSR R/W H'01 H'FFFE F018 8 IEBus transmit data buffer registers 001 to 128 IETB001 to IETB128 W Undefined H'FFFE F100 to 8 H'FFFE F17F IEBus receive data buffer registers 001 to 128 IERB001 to IERB128 R Undefined H'FFFE F200 to 8 H'FFFE F27F Note: * Only 1 can be written to clear the flag. Page 1282 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.1 IEBus Control Register (IECTR) IECTR is used to control the operation of this module. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - IOL DEE - RE - - - 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 IOL 0 R/W Input/Output Level Selects input/output pin level (polarity) for the IERxD and IETxD pins. 0: Pin input/output is set to active low. (Logic 1 is low level and logic 0 is high level.) 1: Pin input/output is set to active high. (Logic 1 is high level and logic 0 is low level.) 5 DEE 0 R/W Broadcast Receive Error Interrupt Enable If this bit is set to 1, a reception error interrupt occurs when the receive buffer is not in the receive enabled state during broadcast reception (when the RE bit is not set to 1 or the RXBSY flag is set.). At this time, the master address is stored in IEBus reception master address register 1 and 2. While this bit is 0, a reception error interrupt does not occur when the receive buffer is not in the receive enabled state, and the reception stops and enters the wait state. The master address is not saved. 0: A broadcast receive error is not generated up to the control field. 1: A broadcast receive error is generated up to the control field. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1283 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 RE 0 R/W Receive Enable Enables/disables reception. This bit must be set at the initial setting before frame reception. 0: Reception is disabled. 1: Reception is enabled. 2 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24.3.2 IEBus Command Register (IECMR) IECMR issues commands to control communications. Since this register is a write-only register, the read value is undefined. Bit: Initial value: R/W: 7 6 5 4 3 - - - - - 0 0 0 0 0 - - - - - Bit Bit Name Initial Value R/W Description 7 to 3  All 0  Reserved 2 1 0 CMD 0 W 0 W 0 W These bits are always read as 0. The write value should always be 0. Page 1284 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 to 0 CMD 000 W Command These bits issue a command to control communications. When the CMX flag in IEFLG is set after the command issuance, the command is indicated to be in execution. When the CMX flag becomes 0, the operation state is entered. 000: No operation. Operation is not affected. 001: Unlock (required from other units)*1 010: Requires communications as the master 2 011: Stops master communications* 4 100: Undefined bits* 101: Requires data transfer from the slave 3 110: Stops data transfer from the slave* 4 111: Undefined bits* Notes: 1. Do not execute this command in slave communications. 2. This command is valid during master communications (MRQ = 1). In other states, this command issuance is ignored. If this command is issued in master communications, the communications controller immediately enters the wait state. At this time, the issued master transmission request ends (MRQ = 0). 3. This command is valid during slave communications (SRQ = 1). In other states, this command issuance is ignored. Once this command is issued in slave transmission, the SRQ flag is 0 before slave transmission. Therefore, a transmit request from the master is not responded to. If a transmit request is issued during slave transmission, the transmission stops and the wait state is entered (SRQ = 0). 4. Undefined bits. Issuing this command does not affect operation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1285 of 3092 Section 24 IEBusTM Controller 24.3.3 SH7268 Group, SH7269 Group IEBus Master Control Register (IEMCR) IEMCR sets the communication conditions for master communications. Bit: 7 6 SS Initial value: R/W: 0 R/W 5 4 3 0 R/W 0 R/W 2 1 0 0 R/W 0 R/W CTL*1 RN 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 SS 0 R/W Broadcast/Normal Communications Select Selects broadcast or normal communications for master communications. 0: Broadcast communications for master communications 1: Normal communications for master communications 6 to 4 RN 000 R/W Retransmission Counts Set the number of times retransmission is done when arbitration is lost in master communications. If arbitration is lost, the TXEAL flag in IETSR is set and transmission ends. 000: 0 001: 1 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7 Page 1286 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit 3 to 0 Bit Name 1 CTL* Initial Value R/W Description 0000 R/W Control Set the control bits in the control field for master transmission. 0000: Reads slave status 0001: Undefined*3 3 0010: Undefined* 2 0011: Reads data and locks* 0100: Reads locked address (lower 8 bits) 0101: Reads locked address (upper 4 bits) 2 0110: Reads slave status and unlocks* 0111: Reads data 3 1000: Undefined* 3 1001: Undefined* 2 1010: Writes command and locks* 2 1011: Writes data and locks* 3 1100: Undefined* 1101: Undefined*3 1110: Writes command 1111: Writes data Notes: 1. CTL3 decides the data transfer direction of the message length bits in the message length field and data bits in the data field: CTL3 = 1: Transfer is from master unit to slave unit CTL3 = 0: Transfer is from slave unit to master unit 2. Control bits to lock and unlock 3. Setting prohibited. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1287 of 3092 Section 24 IEBusTM Controller 24.3.4 SH7268 Group, SH7269 Group IEBus Master Unit Address Register 1 (IEAR1) IEAR1 sets the lower four bits of the master unit address and communications mode. In master communications, the master unit address becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field. Bit: 7 6 5 4 3 IARL4 Initial value: R/W: 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 4 IARL4 0000 R/W 0 R/W 2 IMD 0 R/W 0 R/W 0 R/W 1 0 - STE 0 R 0 R/W Description Lower 4 Bits of IEBus Master Unit Address Set the lower 4 bits of the master unit address. This register becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field. 3, 2 IMD 00 R/W IEBus Communications Mode Set IEBus communications mode. 00: Communications mode 0 01: Communications mode 1 10: Communications mode 2 11: Setting prohibited 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 STE 0 R/W Slave Transmission Setting Sets bit 4 in the slave status register. Transmitting the slave status register informs the master unit that the slave transmission enabled state is entered by setting this bit to 1. Note that this bit only sets the slave status register value and does not directly affect slave transmission. 0: Bit 4 in the slave status register is 0 (slave transmission stop state) 1: Bit 4 in the slave status register is 1 (slave transmission enabled state) Page 1288 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.5 IEBus Master Unit Address Register 2 (IEAR2) IEAR2 sets the upper eight bits of the master unit address. In master communications, this register becomes the master address field value. In slave communications, this register is compared with the received slave address field. Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W IARU8 Initial value: R/W: 0 R/W 0 R/W Bit Bit Name Initial Value R/W 7 to 0 IARU8 All 0 R/W 0 R/W 0 R/W 0 R/W Description Upper 8 Bits of IEBus Master Unit Address Set the upper 8 bits of the master unit address. This register becomes the master address field value. In slave communications, the master unit address is compared with the received slave address field. 24.3.6 IEBus Slave Address Setting Register 1 (IESA1) IESA1 sets the lower four bits of the communications destination slave unit address. Bit: 7 6 5 4 ISAL4 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 - - - - 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 4 ISAL4 0000 R/W Lower 4 Bits of IEBus Slave Address These bits set the lower 4 bits of the communication destination slave unit address. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1289 of 3092 Section 24 IEBusTM Controller 24.3.7 SH7268 Group, SH7269 Group IEBus Slave Address Setting Register 2 (IESA2) IESA2 sets the upper eight bits of the communications destination slave unit address. Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W ISAU8 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 0 ISAU8 All 0 R/W Upper 8 Bits of IEBus Slave Address Set upper 8 bits of the communications destination slave unit address 24.3.8 IEBus Transmit Message Length Register (IETBFL) IETBFL sets the message length for master or slave transmission. Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W IBFL Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 0 IBFL All 0 R/W Transmit Message Length Set the message length for master transmission. Set the message length that does not exceed the maximum transmit bytes in communications mode. H'01: 1 byte H'02: 2 bytes : H'7F: 127 bytes H'80: 128 bytes H'81: Undefined* : H'FF: Undefined* H'00: Undefined* Note: * Setting prohibited Page 1290 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.9 IEBus Reception Master Address Register 1 (IEMA1) IEMA1 indicates the lower four bits of the communication destination master unit address in slave/broadcast reception. Bit: 7 6 5 4 IMAL4 Initial value: R/W: 0 R Bit Bit Name Initial Value R/W 7 to 4 IMAL4 0000 R 0 R 0 R 0 R 3 2 1 - - - 0 - 0 R 0 R 0 R 0 R Description Lower Four Bits of IEBus Reception Master Address Indicates the lower four bits of the communication destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag. If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is not in the receive enabled state at control field reception, a receive error interrupt is generated and the lower four bits of the master address are stored in IEMA1. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1291 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.10 IEBus Reception Master Address Register 2 (IEMA2) IEMA2 indicates the upper eight bits of the communications destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag in IERSR. If a broadcast receive error interrupt is selected with the DEE bit in IECTR and the receive buffer is not in the receive enabled state at control field reception, a receive error interrupt is generated and the upper eight bits of the master address are stored in IEMA2. This register cannot be modified. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R IMAU8 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 0 IMAU8 All 0 R Upper Eight Bits of IEBus Reception Master Address Indicates the upper eight bits of the communications destination master unit address in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag. If a broadcast receive error interrupt is selected by the DEE bit in IECTR and the receive buffer is not in the receive enabled state at control field reception, a receive error interrupt is generated and the upper eight bits of the master address are stored in IEMA2. Page 1292 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.11 IEBus Receive Control Field Register (IERCTL) IERCTL indicates the control field value in slave/broadcast reception. This register is enabled when slave/broadcast receive starts, and the contents are changed at the time of setting the RXS flag in IERSR. This register cannot be modified. Bit: Initial value: R/W: 7 6 5 4 - - - - 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved 3 2 1 0 0 R 0 R RCTL 0 R 0 R These bits are always read as 0. The write value should always be 0. 3 to 0 RCTL 0000 R IEBus Receive Control Field Indicates the control field value in slave/broadcast reception. This register is enabled when slave/broadcast reception starts, and the contents are changed at the time of setting the RXS flag. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1293 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.12 IEBus Receive Message Length Register (IERBFL) IERBFL indicates the message length field in slave/broadcast reception. This register is enabled when slave/broadcast receive starts, and the contents are changed at the time of setting the RXS flag in IERSR. This register cannot be modified. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R RBFL Initial value: R/W: 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 0 RBFL All 0 R IEBus Receive Message Length Indicates the contents of the message length field in slave/broadcast reception. 24.3.13 IEBus Lock Address Register 1 (IELA1) IELA1 specifies the lower eight bits of a locked address when a unit is locked. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R ILAL8 Initial value: R/W: 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 0 ILAL8 All 0 R Lower Eight Bits of IEBus Lock Address Indicates the lower eight bits of the master unit address when a unit is locked. These bits are valid only when the LCK bit in IEFLG is set. Page 1294 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.14 IEBus Lock Address Register 2 (IELA2) IELA2 specifies the upper four bits of a locked address when a unit is locked. Bit: Initial value: R/W: 7 6 5 4 - - - - 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved 3 2 1 0 0 R 0 R ILAU4 0 R 0 R These bits are always read as 0. The write value should always be 0. 3 to 0 ILAU4 0000 R Upper Four Bits of IEBus Locked Address Stores the upper four bits of the master unit address when a unit is locked. These bits are valid only when the LCK bit in IEFLG is set R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1295 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.15 IEBus General Flag Register (IEFLG) IEFLG indicates the command execution status, lock status and slave address match, and broadcast reception detection. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 CMX MRQ SRQ SRE LCK - RSS GG 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 CMX 0 R Command Execution Status Indicates the command execution status. 0: Command execution is completed 1: A command is being executed [Setting condition]  When a master communications request or slave transmit request command is issued while the MRQ, SRQ, or SRE flag is set [Clearing condition]  6 MRQ 0 R When a command execution has been completed Master Communications Request Indicates whether the unit is in the communications request state as a master unit. 0: The unit is not in the communications request state as a master unit 1: The unit is in the communications request state as a master unit [Setting condition]  When the CMX flag is cleared to 0 after the master communications request command is issued [Clearing condition]  Page 1296 of 3092 When the master communications have been completed R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 5 SRQ 0 R Slave Transmission Request Indicates whether the unit is in the transmit request state as a slave unit. 0: The unit is not in the transmit request state as a slave unit 1: The unit is in the transmit request state as a slave unit [Setting condition]  When the CMX flag is cleared to 0 after the slave transmit request command is issued. [Clearing condition]  4 SRE 0 R When a slave transmission has been completed. Slave Receive Status Indicates the execution status in slave/broadcast reception. 0: Slave/broadcast reception is not being executed 1: Slave/broadcast reception is being executed [Setting condition]  When the slave/broadcast reception is started while the RE bit in IECTR is set to 1. [Clearing condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When the slave/broadcast reception has been completed. Page 1297 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 3 LCK 0 R Lock Status Indication Set to 1 when a unit is locked by a lock request from the master unit. IELA1 and IELA2 values are valid only when this flag is set to 1. 0: A unit is unlocked 1: A unit is locked [Setting condition]  When data for the number of bytes specified by the message length is not received after the control bits that make the unit locked are received from the master unit. (The LCK flag is set to 1 only when the message length exceeds the maximum number of transfer bytes in one frame. This flag is not set by completion of other errors.) [Clearing condition]  2  0 R When an unlock condition is satisfied or when an unlock command is issued. Reserved This bit is always read as 0. The write value should always be 0. 1 RSS 0 R Receive Broadcast Bit Status Indicates the received broadcast bit value. This flag is valid when the slave/broadcast reception is started. (This flag is changed at the time of setting the RXS flag.) The previous value remains unchanged until the next slave/broadcast reception is started. 0: Received broadcast bit is 0 1: Received broadcast bit is 1 Page 1298 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 0 GG 0 R General Broadcast Reception Acknowledgement Set to 1 when the slave address is acknowledged as H'FFF in broadcast reception. Like the receive broadcast bit, this flag is valid when the slave/broadcast reception is started. (This flag is changed at the time of setting the RXS flag in IERSR.) The previous value remains unchanged until the next slave/broadcast reception is started. This flag is cleared to 0 in slave normal reception. 0: (1) A unit is in slave reception (2) When H'FFF is not acknowledged in the slave address field in broadcast reception 1: When H'FFF is acknowledged in the slave address field in broadcast reception 24.3.16 IEBus Transmit Status Register (IETSR) IETSR detects events such as transmit start, transmit normal completion, and transmit error end. Each status flag in IETSR corresponds to a bit in the IEBus transmit interrupt enable register (IEIET) that enables or disables each interrupt. This register is cleared by writing 1 to each bit. Bit: Initial value: R/W: 7 6 5 4 - TXS TXF - TXEAL TXETTME TXERO TXEACK 0 R 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* 0 R 0 0 R/(W)* R/(W)* Bit Bit Name Initial Value R/W 7  0 R 3 2 1 0 Description Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1299 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 6 TXS 0 R/(W)* Transmit Start Indicates that this module starts transmission. [Setting condition]  During master transmission, the arbitration is won and the master address field transmission is completed [Clearing condition]  When 1 is written 5 TXF 0 R/(W)* Transmit Normal Completion Indicates that data for the number of bytes specified by the message length bits has been transmitted with no error. [Setting condition]  When data for the number of bytes specified by the message length bits has been transmitted normally [Clearing condition]  When 1 is written 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 TXEAL 0 R/(W)* Arbitration Loss This module retransmits from the start bit for the number of times specified by the RN bit in IEMCR if the arbitration has been lost in master communications. If the arbitration has been lost for the specified number of times, the TXEAL is set to enter the wait state. If the arbitration has been won within retransmit for the specified number of times, this flag is not set to 1. This flag is set only when the arbitration has been lost and the wait state is entered. [Setting condition]  When the arbitration has been lost during data transmission and the transmission has been terminated [Clearing condition]  When 1 is written Page 1300 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 TXETTME 0 R/(W)* Transmit Timing Error Set to 1 if data is not transmitted at the timing specified by the IEBus protocol during data transmission. This module sets this bit and enters the wait state. [Setting condition]  When a timing error occurs during data transmission [Clearing condition]  1 TXERO 0 R/(W)* When 1 is written Overflow of Maximum Number of Transmit Bytes in One Frame Indicates that the maximum number of bytes defined by the communications mode have been transmitted because a NAK has been received from the receive unit and retransmit has been performed, or that transmission has not been completed because the message length value exceeds the maximum number of transmit bytes in one frame. This module sets this bit and enters the wait state. [Setting condition]  When the transmit has not been completed although the maximum number of bytes defined by the communications mode have been transmitted [Clearing condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When 1 is written Page 1301 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 0 TXEACK 0 R/(W)* Acknowledge Bit Status Indicates the data received in the acknowledge bit of the data field.  Acknowledge bit other than in the data field This module terminates the transmission and enters the wait state if a NAK is received. In this case, this bit is set to 1.  Acknowledge bit in the data field This module retransmits data up to the maximum number of bytes defined by the communications mode until an ACK is received from the receive unit if a NAK is received from the receive unit during data field transmission. In this case, when an ACK is received from the receive unit during retransmission, this flag is not set and transmission will be continued. When transmission is terminated without receiving an ACK, this flag is set to 1. Note: This flag is invalid in broadcast communications. [Setting condition]  When the acknowledge bit of 1 (NAK) is detected [Clearing condition]  Note: * When 1 is written Only 1 can be written to clear the flag. Page 1302 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.17 IEBus Transmit Interrupt Enable Register (IEIET) IEIET enables/disables interrupts for sources such as transmit start, transmit normal completion, and transmit error completion in IETSR. Bit: Initial value: R/W: 7 6 5 4 3 - TXSE TXFE - TXEALE 0 R 0 R/W 0 R/W 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7  0 R Reserved 2 1 TXE TXEROE TTMEE 0 R/W 0 R/W 0 TXE ACKE 0 R/W This bit is always read as 0. The write value should always be 0. 6 TXSE 0 R/W Transmit Start Interrupt Enable Enables/disables a transmit start (TXS) interrupt. 0: Disables a transmit start (TXS) interrupt 1: Enables a transmit start (TXS) interrupt 5 TXFE 0 R/W Transmit Normal Completion Interrupt Enable Enables/disables a transmit normal completion (TXF) interrupt. 0: Disables a transmit normal completion (TXF) interrupt 1: Enables a transmit normal completion (TXF) interrupt 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 TXEALE 0 R/W Arbitration Loss Interrupt Enable Enables/disables an arbitration loss (TXEAL) interrupt. 0: Disables an arbitration loss (TXEAL) interrupt 1: Enables an arbitration loss (TXEAL) interrupt R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1303 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Initial Value Bit Bit Name 2 TXETTMEE 0 R/W Description R/W Transmit Timing Error Interrupt Enable Enables/disables a transmit timing error (TXETTMEE) interrupt. 0: Disables a transmit timing error (TXETTMEE) interrupt 1: Enables a transmit timing error (TXETTMEE) interrupt 1 TXEROE 0 R/W Overflow of Maximum Number of Transmit Bytes in One Frame Interrupt Enable Enables/disables an overflow of the maximum number of transmit bytes in one frame (TXEROE) interrupt. 0: Disables an overflow of the maximum number of transmit bytes in one frame (TXEROE) interrupt 1: Enables an overflow of the maximum number of transmit bytes in one frame (TXEROE) interrupt 0 TXEACKE 0 R/W Acknowledge Bit Interrupt Enable Enables/disables an acknowledge bit (TXEACKE) interrupt. 0: Disables an acknowledge bit (TXEACKE) interrupt 1: Enables an acknowledge bit (TXEACKE) interrupt Page 1304 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.18 IEBus Receive Status Register (IERSR) IERSR detects receive busy, receive start, receive normal completion, or receive completion with an error. Each status flag in IERSR corresponds to a bit in the IEIER that enables/disables each interrupt. This register is cleared by writing 1 to each bit. Bit: 7 6 5 RXBSY RXS RXF 4 3 RXEDE RXEOVE 2 RXE RTME 1 0 RXEDLE RXEPE Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit Bit Name Initial Value R/W Description 7 RXBSY 0 R/(W)* Receive Busy Indicates that the receive data is stored in the receive data buffer (IERB001 to IERB128). Clear this bit after reading out all data. The next receive data cannot be received while this bit is set. [Setting condition]  When all receive data has been written to the receive data buffer. [Clearing condition]  6 RXS 0 R/(W)* When 1 is written Receive Start Detection Indicates that this module starts reception. [Setting condition]  When the data from the master unit to message length field has been received correctly in slave reception [Clearing condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When 1 is written Page 1305 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 5 RXF 0 R/(W)* 4 RXEDE 0 R/(W)* Receive Normal Completion Indicates that data for the number of bytes specified by the message length bits has been received normally. [Setting condition]  When data for the number of bytes specified by the message length bits has been received normally. [Clearing condition]  When 1 is written Broadcast Receive Error Indicates that data could not be received because the receive buffer is not in the receive enabled state (when the RE bit is not set to 1 or the RXBSY flag is set.) during receiving control field broadcast reception. This bit functions when the DEE bit in IECTR is set to 1. [Setting condition]  When data could not be received during broadcast reception. [Clearing condition]  When 1 is written 3 RXEOVE 0 R/(W)* Page 1306 of 3092 Receive Overrun Flag Used to indicate the overrun during data reception. This module sets this flag when this module receives the next byte data while the receive data has not been read (the RXBSY flag is not cleared). If this case, this module assumes that an overrun error has occurred and returns a NAK to the communications destination unit. The communications destination unit retransmits data up to the maximum number of transmit bytes. This module, however, returns a NAK when the RXBSY flag remains set. If the RXBSY flag is cleared to 0, this module returns an ACK, and receives the next data. In broadcast reception, if the RXBSY flag is set during data receive start, this module immediately enters the wait state. This flag becomes enabled only after the receive start flag (RXS) is set. [Setting condition]  When the next byte data is received while the RXBSY flag is not cleared. [Clearing condition]  When 1 is written R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 2 RXERTME 0 R/(W)* Receive Timing Error Set to 1 if data is not received at the time specified by the IEBus protocol during data reception. This module sets this bit and enters the wait state. This flag is enabled only after the receive start flag (RXS) is set. If this error occurs before the receive start flag (RXS) is set, this module stops communication and enters the wait state. This bit is not set in this case. [Setting condition]  When a timing error occurs during data reception [Clearing condition]  1 RXEDLE 0 R/(W)* When 1 is written Overflow of Maximum Number of Receive Bytes in One Frame Indicates that the data reception has not finished within the maximum number of bytes defined by the communications mode because of a parity error or overrun error causing the retransfer of data, or that reception has not been completed because the message length value exceeds the maximum number of receive bytes in one frame. This module sets the RXEDLE flag and enters the wait state. This flag is enabled only after the receive start flag (RXS) is set. If this error occurs before the receive start flag is set, this module stops communication and enters the wait state. This bit is not set in this case. [Setting condition]  When the reception has not been completed within the maximum number of bytes defined by communications mode. [Clearing condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When 1 is written Page 1307 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 0 RXEPE 0 R/(W)* Parity Error Indicates that a parity error has occurred during data field reception. If a parity error occurs before data field reception, this module immediately enters the wait state and the RXEPE flag is not set. If a parity error occurs when the maximum number of receive bytes in one frame have not been received, the RXEPE flag is not set yet. When a parity error occurs, this module returns a NAK to the communications destination unit via the acknowledge bit. In this case, the communications destination unit continues retransfer up to the maximum number of receive bytes in one frame and if the reception has been completed normally by clearing the parity error, the RXEPE flag is not set. If the parity error is not cleared when the reception is terminated before receiving data for the number of bytes specified by the message length, the RXEPE flag is set. In broadcast reception, if a parity error occurs during data field reception, this module enters the wait state immediately after setting the RXEPE flag. This flag is enabled only after the receive start flag (RXS) is set. If this error occurs before the receive start flag is set, this module stops communication and enters the wait state. This bit is not set in this case. [Setting condition]  When the parity bit of the last data of the data field is not correct after the maximum number of receive bytes have been received [Clearing condition]  Note: * When 1 is written Only 1 can be written to clear the flag. Page 1308 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.19 IEBus Receive Interrupt Enable Register (IEIER) IEIER enables/disables interrupts for sources such as IERSR receive busy, receive start, receive normal completion, and receive error completion. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RXBSYE RXSE RXFE RXEDEE RXE OVEE RXE RTMEE RXE DLEE RXEPEE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 RXBSYE 0 R/W Receive Busy Interrupt Enable Enables/disables a receive busy interrupt (RXBSY) 0: Disables a receive busy (RXBSY) interrupt 1: Enables a receive busy (RXBSY) interrupt 6 RXSE 0 R/W Receive Start Interrupt Enable Enables/disables a receive start (RXS) interrupt 0: Disables a receive start (RXS) interrupt 1: Enables a receive start (RXS) interrupt 5 RXFE 0 R/W Receive Normal Completion Enable Enables/disables a receive normal completion (RXF) interrupt 0: Disables a receive normal completion (RXF) interrupt 1: Enables a receive normal completion (RXF) interrupt 4 RXEDEE 0 R/W Broadcast Receive Error Interrupt Enable Enables/disables a broadcast receive error (RXEDE) interrupt 0: Disables a broadcast receive error (RXEDE) interrupt 1: Enables a broadcast receive error (RXEDE) interrupt R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1309 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 3 RXEOVEE 0 R/W Overrun Control Flag Interrupt Enable Enables/disables an overrun control flag (RXEOVE) interrupt 0: Disables an overrun control flag (RXEOVE) interrupt 1: Enables an overrun control flag (RXEOVE) interrupt 2 RXERTMEE 0 R/W Receive Timing Error Interrupt Enable Enables/disables a receive timing error (RXERTME) interrupt. 0: Disables a receive timing error (RXERTME) interrupt 1: Enables a receive timing error (RXERTME) interrupt 1 RXEDLEE 0 R/W Overflow of Maximum Number of Receive Bytes in One Frame Interrupt Enable Enables/disables an overflow of the maximum number of receive bytes in one frame (RXEDLE) interrupt 0: Disables an overflow of the maximum number of receive bytes in one frame (RXEDLE) interrupt 1: Enables an overflow of the maximum number of receive bytes in one frame (RXEDLE) interrupt 0 RXEPEE 0 R/W Parity Error Interrupt Enable Enables/disables a parity error (RXEPE) interrupt 0: Disables a parity error (RXEPE) interrupt 1: Enables a parity error (RXEPE) interrupt 24.3.20 IEBus Clock Selection Register (IECKSR) IECKSR is a readable/writable 8-bit register that specifies the clock used in this module. Bit: Initial value: R/W: Page 1310 of 3092 7 6 5 4 3 - - - CKS3 - 0 R 0 R 0 R 0 R/W 0 R 2 1 0 CKS[2:0] 0 R/W 0 R/W 1 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 CKS3 0 R/W Input Clock Selection 3*1*2 Specifies the clock for this module 0: Peripheral clock 0 (P0) 1: AUDIO_X1, AUDIO_X2 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 CKS[2:0] 001 R/W Input Clock Selection 2 to 0*1 Specifies the division ratio of the clock for this module 000: Setting prohibited 001: This module uses the 1/2 divided clock of IEB specified by CKS3 (IEB  12 MHz, 12.58 MHz). 010: This module uses the 1/3 divided clock of IEB specified by CKS3 (IEB  18 MHz, 18.87 MHz). 011: This module uses the 1/4 divided clock of IEB specified by CKS3 (IEB  24 MHz, 25.16 MHz). 100: This module uses the 1/5 divided clock of IEB specified by CKS3 (IEB  30 MHz, 31.45 MHz). 101: This module uses the 1/6 divided clock of IEB specified by CKS3 (IEB  36 MHz, 37.74 MHz). 110: This module uses the 1/7 divided clock of IEB specified by CKS3 (IEB  42 MHz, 44.03 MHz). 111: This module uses the 1/8 divided clock of IEB specified by CKS3 (IEB  48 MHz). Notes: 1. Do not change the setting of CKS3 and CKS[2:0] while IEBus is in transmit/receive operation. 2. When the CKS3 bit is set to 1, be sure to set the MSTP36 bit in STBCR3 to 0. For the setting of STBCR3, see section 49, Power-Down Modes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1311 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128) IETB001 to IETB128 are 128-byte (8  128) buffers to which data to be transmitted during master transmission is written. The initial values in IETB001 to IETB128 are undefined. Bit: 7 6 5 4 3 2 1 0 W* W* W* W* TBn Initial value: R/W: W* W* W* W* [Legend] n = 001 to 128 Bit Bit Name Initial Value 7 to 0 TBn Undefined W* R/W Description IEBus Transmit Data Buffer Data to be transmitted in the data field during master transmission is written to TB001 to TB128. Data is written starting with TB001 for the start 1-byte data, followed by TB002 and TB003 and so on according to the transmission order, and TB128 stores the last data. Note: * Writing to these bits during master transmission (MRQ in IEFLG is 1) is prohibited Page 1312 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128) IERB001 to IERB128 are 128-byte (8  128) buffers to which data to be transmitted during slave transmission is written. The initial values in IERB001 to IERB128 are undefined. Bit: 7 6 5 4 3 2 1 0 R* R* R* R* RBn Initial value: R/W: R* R* R* R* [Legend] n = 001 to 128 Bit Bit Name Initial Value 7 to 0 RBn Undefined R* R/W Description IEBus Receive Data Buffer Data in RB001 to RB128 can be read when the RXBSY bit in the IEBus receive status register (IERSR) is set to 1. Data read from RB001 to RB128 is the field data during slave receive. Receive data is written starting with RB001 for the start 1-byte data, followed by RB002 and RB003 and so on, and RB128 stores the last data. Note: * Reading these bits during slave reception (SRE in IEFLG is 1 and RXBSY in IERSR is 0) is prohibited. (Read value is undefined.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1313 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.4 Data Format 24.4.1 Transmission Format Figure 24.6 shows the relationship between the transfer format and each register during the IEBus data transmission. [In master transmission] Communications frame Master address Slave address Control bits Message length bits Data bits Register IEAR1, IEAR2 IESA1, IESA2 IEMCR IETBFL IETB001 to IETB128 Master address Slave address Control bits Message length bits Data bits IETBFL IETB001 to IETB128 [In slave transmission] Communications frame (*2) (*1) Register Notes: 1. 2. 3. IEAR1, IEAR2 (*3) In slave transmission, the received master address is not saved. If the unit is locked, address comparison performed. The received slave address is compared with IEAR1 and IEAR2, and if these addresses match, operation continues. In slave transmission, the received control bits are not saved. The received control bits are decoded to decide the subsequent operation. Figure 24.6 Relationship between Transfer Format and Each Register during IEBus Data Transmission Page 1314 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.4.2 Reception Format Figure 24.7 shows the relationship between the transfer format and each register during the IEBus data reception. [In slave reception] Communications frame Master address Slave address Control bits Message length bits Data bits IERCTL IERBFL IERB001 to IERB128 (*) Register IEMA1, IEMA2 IEAR1, IEAR2 Note: * Received slave address is compared with IEAR1 and IEAR2. If they match, the subsequent operations are performed. [In master reception] Communications frame Master address Slave address Control bits Message length bits Data bits Register IEAR1, IEAR2 IESA1, IESA2 IEMCR IERBFL IERB001 to IERB128 Figure 24.7 Relationship between Transfer Format and Each Register during IEBus Data Reception R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1315 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.5 Software Control Flows 24.5.1 Initial Setting Figure 24.8 shows the flowchart for the initial setting. START [Pin setting] IERxD, IETxD pins enable Module stop release [IECTR setting] Pin porarity setting Receive enable [IECKSR setting] Selection of clock supplied to this module [IEAR1, IEAR2 setting] Transmission mode Master address [IEIET, IEIER setting] Interrupt enable END Figure 24.8 Flowchart for Initial Setting Page 1316 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.5.2 Master Transmission Figure 24.9 shows the flowchart for master transmission. START Initial setting [IESA1, IESA2 register setting] Slave address [IEMCR register setting] Broadcast/normal selection Retransfer counts Control bits [IECMR register setting] Master communications request command Transmit error interrupt (TXE***) Transmit start interrupt Transmit start interrupt (TXS) [IETBFL register setting] Message length bits [IETB001 to IETB128 setting] Transmit data Interrupt processing IETSR[TXS] clear Transmit completion interrupt Transmit error interrupt (TXE***) Transmit completion interrupt (TXF) Interrupt processing IETSR[TXF] clear Interrupt processing IETSR[TXE***] clear END Figure 24.9 Flowchart for Master Transmission R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1317 of 3092 Section 24 IEBusTM Controller 24.5.3 SH7268 Group, SH7269 Group Slave Reception Figure 24.10 shows the flowchart for slave reception. START Initial setting Receive start interrupt Receive error interrupt (RXE***) Receive start interrupt (RXS) Interrupt processing IERSR[RXS] clear Receive completion interrupt Receive error interrupt (RXE***) Receive completion interrupt (RXF) Interrupt processing IERSR[RXF] clear Receive data read (IERB001 to IERB128) IERSR[RXBSY] clear Interrupt processing IERSR[RXE***] clear END Figure 24.10 Flowchart for Slave Reception Page 1318 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.5.4 Master Reception Figure 24.11 shows the flowchart for master reception. START Initial setting [IESA1, IESA2 register setting] Slave address [IEMCR register setting] Broadcast/normal selection Retransfer counts Control bits [IECMR register setting] Master communications request command Receive start interrupt Receive error interrupt (RXE***) Receive start interrupt (RXS) Interrupt processing IERSR[RXS] clear Receive completion interrupt Receive error interrupt (RXE***) Receive completion interrupt (RXF) Interrupt processing IERSR[RXF] clear Receive data read (IERB001 to IERB128) IERSR[RXBSY] clear Interrupt processing IETSR[TXE***] clear IERSR[RXE***] clear END Figure 24.11 Flowchart for Master Reception R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1319 of 3092 Section 24 IEBusTM Controller 24.5.5 SH7268 Group, SH7269 Group Slave Transmission Figure 24.12 shows the flowchart for slave transmission. START Initial setting [IETBFL register setting] Message length bits [IECMR register setting] Slave communications request command [IETB001 to IETB128 setting] Transmit data Transmit start interrupt Transmit error interrupt (TXE***) Transmit start interrupt (TXS) Interrupt processing IETSR[TXS] clear Transmit completion interrupt Transmit error interrupt (TXE***) Transmit completion interrupt (TXF) Interrupt processing IETSR[TXF] clear Interrupt processing IETSR[TXE***] clear END Figure 24.12 Flowchart for Slave Transmission Page 1320 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.6 Operation Timing 24.6.1 Master Transmit Operation Figure 24.13 shows the timing for master transmit operation. Slave reception DL Dn-1 Master transmission Dn HD MA SA CT DL D1 D2 Dn-1 Dn Master transmission request IECMR IEFLG CMX MRQ SRQ SRE IETSR TXS TXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field Figure 24.13 Master Transmit Operation Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1321 of 3092 Section 24 IEBusTM Controller 24.6.2 SH7268 Group, SH7269 Group Slave Receive Operation Figure 24.14 shows the timing for slave receive operation. Broadcast reception DL Dn-1 Slave reception Dn HD MA SA CT DL D1 D2 Dn-1 Dn IEFLG RSS CMX MRQ SRQ SRE IERSR RXS RXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field Figure 24.14 Slave Receive Operation Timing Page 1322 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.6.3 Master Receive Operation Figure 24.15 shows the timing for master receive operation. Slave reception DL Dn-1 Master reception Dn HD MA SA CT DL D1 D2 Dn-1 Dn Master transmission request IECMR IEFLG CMX MRQ SRQ SRE IETSR RXS RXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field Figure 24.15 Master Receive Operation Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1323 of 3092 Section 24 IEBusTM Controller 24.6.4 SH7268 Group, SH7269 Group Slave Transmit Operation Figure 24.16 shows the timing for slave transmit operation. Slave reception DL Dn-1 Slave transmission Dn HD MA SA CT DL D1 D2 Dn-1 Dn Slave transmission request IECMR IEFLG CMX MRQ SRQ SRE IETSR TXS TXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field Figure 24.16 Slave Transmit Operation Timing Page 1324 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 24.7 Section 24 IEBusTM Controller Interrupt Sources Interrupt sources for this module include the following:               Transmit start (TXS) Transmit normal completion (TXF) Arbitration loss (TXEAL) Transmit timing error (TXETTME) Overflow of the maximum number of transmit bytes in one frame (TXERO) Acknowledge bits (TXEACK) Receive busy (RXBSY) Receive start (RXS) Receive normal completion (RXF) Broadcast Receive Error (RXEDE) Receive overrun flag (RXEOVE) Receive timing error (RXERTME) Overflow of the maximum number of receive bytes in one frame (RXEDLE) Parity error (RXEPE) Each source has bits corresponding to the IEBus transmit interrupt enable register (IEIET) and the IEBus receive interrupt enable register (IEIER) and can enable/disable interrupts. Each source also has status flags corresponding to the IEBus transmit status register (IETSR) and IEBus receive status register (IERSR). Reading the status flags allows determination of the interrupt sources. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1325 of 3092 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group Figure 24.17 shows the relations between the interrupt sources. IETSR TXS IEIET TXSE TXF TXFE TXEAL TXEALE TXETTME TXETTMEE TXERO TXEROE TXEACK TXEACKE IERSR CPU IEB interrupts RXBSY IEIER RXBSYE RXS RXSE RXF RXFE RXEDE RXDEE RXEOVE RXEOVEE RXERTME RXERTMEE RXEDLE RXEDLEE RXEPE RXEPEE Figure 24.17 Relations between Interrupt Sources Page 1326 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 24 IEBusTM Controller SH7268 Group, SH7269 Group 24.8 Usage Notes 24.8.1 Note on Operation when Transfer is Incomplete after Transfer of the Maximum Number of Bytes (1) Data Transmission When the maximum number of bytes defined by the communications mode have been transmitted because a NAK has been received from the receive unit or transmission has not been completed because the message length value exceeds the maximum number of transfer bytes in one frame, this module sets the error flag and enters a wait state. At this time, transfer proceeds until the (n + 1)th byte has been transmitted, where n is the maximum number of transfer bytes. Then, when NAK is received via the acknowledge bit of the (n + 1)th byte, the TXERO flag is set. If ACK is received rather than NAK, the TXF flag is set. Figure 24.18 shows the timing of operations when the maximum number of transfer bytes is reached but transmission has not been completed. Master transmission HD MA SA CT DL D1 D2 Dn-1 Dn Dn+1 IETSR When NAK is received for Dn + 1 TXERO When ACK is received for Dn + 1 TXF [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field (n = Maximum number of transfer bytes) Figure 24.18 Timing of Operations when Transmission Has Not Been Completed Within the Maximum Number of Transfer Bytes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1327 of 3092 Section 24 IEBusTM Controller (2) SH7268 Group, SH7269 Group Data Reception When the data reception has not finished within the maximum number of bytes defined by the communications mode because of a parity error or overrun error causing the retransfer of data, or reception has not been completed because the message length value exceeds the maximum number of transfer bytes in one frame, this module sets the error flag and enters a state of waiting for the (n + 1)th byte of data, where n is the maximum number of transfer bytes. Thus, when data of the (n + 1)th byte cannot be received, the receive timing error is detected and the RXERTME flag is set. At this time, the RXEDLE flag is not set. The RXEDLE flag is set when the (n + 1)th byte is received. In the same way, when the maximum number of transfer bytes has been received and a parity error has not been cleared, and the (n + 1)th byte cannot be received, the RXERTME flag is set. At this time, the RXEPE flag is not set. The RXEPE flag is set when the (n + 1)th byte is received. Figure 24.19 shows the timing of operations when the maximum number of transfer bytes has been reached but reception is not complete. Slave reception HD MA SA CT DL D1 D2 Dn-1 Dn Dn+1 IERSR When Dn + 1 is not received RXERTME When Dn + 1 is received RXEDLE When Dn + 1 is received RXEPE [Legend] HD: MA: SA: CT: DL: Dn: Header Master address field Slave address field Control field Message length field Data field (n = Maximum number of transfer bytes) Figure 24.19 Timing of Operations when Reception Has Not Been Completed Within the Maximum Number of Transfer Bytes Page 1328 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Section 25 Renesas SPDIF Interface Overview Peripheral bus interface 25.1 SPDIF_OUT Transmitter SPDIF_IN Receiver Figure 25.1 Overview Block Diagram 25.2         Features Supports the IEC 60958 standard (stereo and consumer use modes only). Supports sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz. Supports audio word sizes of 16 to 24 bits per sample. Biphase mark encoding. Double buffered data. Parity encoded serial data. Simultaneous transmit and receive Receiver autodetects IEC 61937 compressed mode data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1329 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Functional Block Diagram Transmitter data handling Parity generator Transmitter control Frame counter Peripheral bus 25.3 BMC and preamble encoding Oversampling clock SPDIF_OUT AUDIO_X1 AUDIO_X2 AUDIO_CLK Receiver control Receiver data handling Clock recovery and frame counter Parity check SPDIF_IN BMC decode and preamble detection Figure 25.2 Functional Block Diagram Page 1330 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.4 Section 25 Renesas SPDIF Interface Input/Output Pins Table 25.1 shows the pin configuration. Table 25.1 Pin Configuration Channel Pin Name 0 SPDIF_IN Input Transmitter biphase-mark encoded SPDIF bitstream 1 SPDIF_OUT Output Receiver biphase-mark encoded SPDIF bitstream Input External clock for audio Input Crystal resonator/external clock for audio 0, 1 AUDIO_CLK (Common) AUDIO_X1 AUDIO_X2 25.5 I/O Description Output Renesas SPDIF (IEC60958) Frame Format The Renesas SPDIF frame consists of two subframes (for channels 1 and 2), each of which contains a 4-bit preamble, audio data of up to 24 bits, a V flag, a user bit, a channel status bit, and an even parity bit. Figure 25.3 shows the subframe format. According to this format, the Renesas SPDIF performs biphase-mark modulation (channel coding) that will make the transmission line's DC component a minimum value. 0 3 4 L Synchronization S Aux preamble B B/M/W 7 8 27 28 L S B M S B Audio sample word V 31 U C P V = Validity flag U = User data C = Channel status P = Parity bit Figure 25.3 Subframe Format R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1331 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Figure 25.4 shows the block format, which consists of 192 continuous frames. One block begins at the starting frame (preamble B) and ends at the 192nd frame (frame 191), and the preamble is used to identify all subframes. Each block has a total of 384 subframes, which are classified into three categories: subframe 0 indicating the beginning of a new block, subframe 1 (usually the channel 1), and subframe 2 (usually the channel 2). Usually, the music data sent and received by the SPDIF is continuous so that continuous blocks appear. 0 B 1 Channel 1 W Channel 2 M 191 Channel 1 M 0 Channel 1 W Channel 2 B 1 Channel 1 W Channel 2 M Channel 1 B = Start of block preamble W = Channel 2 preamble M = Channel 1 preamble but not start of block Figure 25.4 Block Format Table 25.2 shows the binary values of the Renesas SPDIF preambles. The polarity of these preambles differs depending on the status of the preceding symbol (parity bit). Table 25.2 Binary Preamble Values Preamble Preceding Symbol's Status = 0 Preceding Symbol's Status = 1 B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 Note: As shown in figure 25.3, the even parity bit at time slot 31 of a subframe determines the type of a preamble for one cycle of transmission. Usually, therefore, any one is selected from the set states that are sent through the Renesas SPDIF. However, IEC60958 requires decoding both types in view of connection with the preamble polarity reversed; the Renesas SPDIF has preambles decoded according to table 25.2. Channel status information is encoded at the rate of one bit per subframe, making the channel status information per block have a total of 192 bits for each of subframes 1 and 2. For the format of the channel status, refer to the IEC 60958 standard. Page 1332 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.6 Section 25 Renesas SPDIF Interface Register Table 25.3 shows the register configuration. Table 25.3 Register Configuration Channel Register Name Abbreviation Address Access Size 0 (Transmit) Transmitter channel 1 audio register TLCA H'E801 2000 32 Transmitter channel 2 audio register TRCA H'E801 2004 32 Transmitter channel 1 status register TLCS H'E801 2008 32 Transmitter channel 2 status register TRCS H'E801 200C 32 Transmitter user data register TUI H'E801 2010 32 Receiver channel 1 audio register RLCA H'E801 2014 32 Receiver channel 2 audio register 1 (Receive) RRCA H'E801 2018 32 Receiver channel 1 status register RLCS H'E801 201C 32 Receiver channel 2 status register RRCS H'E801 2020 32 Receiver user data register RUI H'E801 2024 32 0, 1 (Common) Control register CTRL H'E801 2028 32 Status register STAT H'E801 202C 32 0, 1 (Common) Transmitter DMA audio data register TDAD H'E801 2030 32 Receiver DMA audio data register RDAD H'E801 2034 32 Note: All registers are longword registers and must be accessed as such. A register diagram containing a 0 indicates that the write value should always be 0 (if the register is writeable) and that the read value should always be 0 (if readable). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1333 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7 Register Descriptions Legend: Initial Value: : R/W: R: R/WC0: R/WC1: W: —/W: 25.7.1 Register value after reset Undefined value Readable/writable register. The write value can be read. Read only register. The write value should always be 0. Readable/writable register. Writing 0 initializes the bit, but writing 1 is ignored. Readable/writable register. Writing 1 initializes the bit, but writing 0 is ignored. Write only register. Reading is prohibited. If this bit is reserved, the write value should always be 0. Write only, Read value undefined Control Register (CTRL) 31 30 29 28 27 26 - - - CKS - PB Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R 0 R/W Bit: 23 Bit: 22 Bit: 15 REIE Initial value: 0 R/W: R/W Bit: 7 Page 1334 of 3092 0 R/W 0 R/W 21 20 19 18 17 16 TDE NCSI AOS RME TME 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 TEIE UBOI UBUI CREI PAEI PREI CSEI 0 R/W 6 ABOI ABUI Initial value: 0 R/W: R/W 24 RASS RDE TASS Initial value: 0 R/W: R/W 25 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 R/W 0 5 4 RUII TUII RCSI RCBI TCSI TCBI 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Initial Value R/W Description 31 to 29  All 0 R Reserved 28 0 R/W Oversampling clock select Bit Bit Name CKS Selects oversampling clock supply source. 0: AUDIO_X1 1: AUDIO CLK 27  0 R Reserved 26 PB 0 R/W Pass Back Passes transmitter SPDIF output into SPDIF receiver in SPDIF module. 0: Pass Back disabled 1: Pass Back enabled 25, 24 RASS All 0 R/W Receiver Audio Sample Bit Size These bits Indicate the receiver audio sample bit size (16, 20, or 24 bits), for data alignment purposes. 00: 16-bit sample 01: 20-bit sample 10: 24-bit sample 11: Reserved 23, 22 TASS All 0 R/W Transmitter Audio Sample Bit Size These bits Indicate the transmitter audio sample bit size (16, 20, or 24 bits), for data alignment purposes. 00: 16-bit sample 01: 20-bit sample 10: 24-bit sample 11: Reserved 21 RDE 0 R/W Receiver DMA Enable Enables DMA requests for the receiver. 0: Receiver DMA disabled 1: Receiver DMA enabled 20 TDE 0 R/W Transmitter DMA Enable Enables the DMA requests for the transmitter. 0: Transmitter DMA disabled 1: Transmitter DMA enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1335 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name Initial Value R/W Description 19 NCSI 0 R/W New Channel Status Information Set this bit to 1 when new channel status information to be corrected is in the transmitter. 0: New channel status information has not been in transmitter 1: New channel status information has been in transmitter 18 AOS 0 R/W Audio Only Samples Clear this bit to 0 when audio channel 1 and channel 2 registers contain user information. When this bit is set to 1, all user bits are cleared to 0. 0: User information present 1: User information not present 17 RME 0 R/W Receiver Module Enable Enables the receiver module. 0: Receiver module disabled 1: Receiver module enabled 16 TME 0 R/W Transmitter Module Enable Enables the transmitter module. 0: Transmitter module disabled 1: Transmitter module enabled 15 REIE 0 R/W Receiver Error Interrupt Enable Enables the receiver error interrupts. 0: Receiver error interrupt disabled 1: Receiver error interrupt enabled 14 TEIE 0 R/W Transmitter Error Interrupt Enable Enables the transmitter error interrupts. 0: Transmitter error interrupt disabled 1: Transmitter error interrupt enabled 13 UBOI 0 R/W User Buffer Overrun Interrupt Enable Enables the user buffer overrun interrupts. 0: User buffer overrun interrupt disabled 1: User buffer overrun interrupt enabled Page 1336 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name Initial Value R/W Description 12 UBUI 0 R/W User Buffer Underrun Interrupt Enable Enables the user buffer underrun interrupts. 0: User buffer underrun interrupt disabled 1: User buffer underrun interrupt enabled 11 CREI 0 R/W Clock Recovery Error Interrupt Enable Enables the clock recovery error interrupts. 0: Clock recovery error interrupt disabled 1: Clock recovery error interrupt enabled 10 PAEI 0 R/W Parity Error Interrupt Enable Enables the parity check error interrupts. 0: Parity check error interrupt disabled 1: Parity check error interrupt enabled 9 PREI 0 R/W Preamble Error Interrupt Enable Enables the preamble check error interrupts. 0: Preamble error interrupt disabled 1: Preamble error interrupt enabled 8 CSEI 0 R/W Channel Status Error Interrupt Enable Enables the channel status error interrupts. 0: Channel status error interrupt disabled 1: Channel status error interrupt enabled 7 ABOI 0 R/W Audio Buffer Overrun Interrupt Enable Enables the receiver audio buffer overrun interrupts. 0: Audio buffer overrun interrupt disabled 1: Audio buffer overrun interrupt enabled 6 ABUI 0 R/W Audio Buffer Underrun Interrupt Enable Enables the transmitter audio buffer underrun interrupts. 0: Audio buffer underrun interrupt disabled 1: Audio buffer underrun interrupt enabled 5 RUII 0 R/W Receiver User Information Interrupt Enable Enables the receiver user information register full interrupts. 0: Receiver user information interrupt disabled 1: Receiver user information interrupt enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1337 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name Initial Value R/W Description 4 TUII 0 R/W Transmitter User Information Interrupt Enable Enables the transmitter user information register empty interrupts. 0: Transmitter user information interrupt disabled 1: Transmitter user information interrupt enabled 3 RCSI 0 R/W Receiver Channel Status Interrupt Enable Enables the receiver channel status register empty interrupts. 0: Receiver channel status interrupt disabled 1: Receiver channel status interrupt enabled 2 RCBI 0 R/W Receiver Channel Buffer Interrupt Enable Enables the receiver audio channel buffer empty interrupts. 0: Receiver audio channel interrupt disabled 1: Receiver audio channel interrupt enabled 1 TCSI 0 R/W Transmitter Channel Status Interrupt Enable Enables the transmitter channel status register empty interrupts. 0: Transmitter channel status interrupt disabled 1: Transmitter channel status interrupt enabled 0 TCBI 0 R/W Transmitter Channel Buffer Interrupt Enable Enables the transmitter audio channel buffer empty interrupts. 0: Transmitter audio channel interrupt disabled 1: Transmitter audio channel interrupt enabled Page 1338 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.7.2 Section 25 Renesas SPDIF Interface Status Register (STAT) 31 30 29 28 27 26 25 - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 23 22 21 20 19 18 17 16 - - - - - - - CMD 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 10 9 8 Bit: Initial value: R/W: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 RIS TIS UBO UBU CE 1 R 1 R 0 0 0 7 6 ABO ABU 0 0 5 4 R/WC0 R/WC0 0 R 0 R Description 31 to 17  All 0 R Reserved 16 0 R CMD 0 0 0 3 2 1 0 RUIR TUIR CSRX CBRX CSTX CBTX R/W Bit Name PARE PREE CSE R/WC0 R/WC0 R/WC0 R/WC0 R/WC0 R/WC0 Initial Value Bit 24 0 R 0 R 0 R 0 R Compressed Mode Data Sets if the data being received is compressed mode data (When bit 1 = 1 in the V flag and channel status). 0: Data is not in compressed mode 1: Data is in compressed mode 15 RIS 1 R Receiver Idle State Sets if the receiver is in the idle state. 0: Receiver is not in idle state 1: Receiver in idle state 14 TIS 1 R Transmitter Idle State Sets if the transmitter is in the idle state. 0: Transmitter is not in idle state 1: Transmitter is in idle state R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1339 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name Initial Value R/W 13 UBO 0 R/WC0 User Buffer Overrun* Description Sets if the receiver user buffer overruns. This bit is cleared by writing 0 to the register. If bit REIE and bit UBOI in the control register are set this causes an interrupt. 0: User buffer has not overrun 1: User buffer has overrun 12 UBU 0 R/WC0 User Buffer Underrun* Sets if the transmitter user buffer underrun. This bit is cleared by writing 0. If bits TEIE and UBUI in the control register are set this causes an interrupt. 0: User buffer has not underrun 1: User buffer has underrun 11 CE 0 R/WC0 Clock Error* Sets when the clock recovery falls out of synchronization. This bit is cleared by writing 0. If bits REIE and CREI in the control register are set this causes an interrupt. 0: Clock recovery stable 1: Clock recovery error 10 PARE 0 R/WC0 Parity Error* Sets when the parity checker produces a fail result. This bit is cleared by writing 0. If bits REIE and PAEI in the control register are set this causes an interrupt. 0: Parity check correct 1: Parity error 9 PREE 0 R/WC0 Preamble Error* Sets when the start of word preamble fails to appear in the correct place. This bit is cleared by writing 0. If bits REIE and PREI in the control register are set this causes an interrupt. Note: Only set after a start of block preamble has occurred. 0: Preamble is in the correct place 1: Preamble error Page 1340 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name Initial Value R/W 8 CSE 0 R/WC0 Channel Status Error* Description Sets when the channel status information is written before the 32nd frame of the current block. This bit is cleared by writing 0. If bits TEIE and CSEI in the control register are set this causes an interrupt. 0: Channel status correct 1: Channel status error 7 ABO 0 R/WC0 Audio Buffer Overrun* Indicates that the receiver audio buffer is full in both the first and second stages and that data has been overwritten. This bit is cleared by writing 0. If bits REIE and ABOI in the control register are set then this causes an interrupt. 0: Receiver audio buffer has not overrun 1: Receiver audio buffer has overrun 6 ABU 0 R/WC0 Audio Buffer Underrun* Indicates that the transmitter audio buffer is empty in both the first and second stages and that the last data transmission has been repeated. This bit is cleared by writing 0. If bits TEIE and ABUI in the control register are set then this causes an interrupt. 0: Transmitter audio buffer has not underrun 1: Transmitter audio buffer has underrun 5 RUIR 0 R Receiver User Information Register Status Indicates the status of the receiver user information register. This bit is cleared by reading from the receiver user register. If bit RUII in the control register is set then this causes an interrupt. 0: Receiver user information register is empty 1: Receiver user information register is full 4 TUIR 0 R Transmitter User Information Register Status Indicates the status of the transmitter user information register. This bit is cleared by writing to the transmitter user register. If bit TUII in the control register is set then this causes an interrupt. 0: Transmitter user information register is full 1: Transmitter user information register is empty R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1341 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name Initial Value R/W Description 3 CSRX 0 R Channel 1 and Channel 2 Status for Receiver Indicates the status of the receiver channel status registers. This bit is cleared by reading from the receiver channel status registers. If bit RCSI in the control register is set this causes an interrupt. 0: Receiver channel status registers are empty 1: Receiver channel status registers are full 2 CBRX 0 R Channel 1 and Channel 2 Buffers for Receiver Indicates the status of the receiver audio channel registers. This bit is cleared by reading from the receiver audio channel registers. If bit RCBI in the control register is set this causes an interrupt. 0: Receiver audio channel registers are empty 1: Receiver audio channel registers are full 1 CSTX 0 R Channel 1 and Channel 2 Status for Transmitter Indicates the status of the transmitter channel status registers. This bit is cleared by writing to the transmitter channel status registers. If bit TCSI in the control register is set this causes an interrupt. 0: Transmitter channel status register is full 1: Transmitter channel status register is empty 0 CBTX 0 R Channel 1 and Channel 2 Buffers for Transmitter Indicates the status of the transmitter audio channel registers. This bit is cleared by writing to the transmitter audio channel registers. If bit TCBI in the control register is set this causes an interrupt. 0: Transmitter audio channel registers are full 1: Transmitter audio channel registers are empty Note: * When an error bit is detected during DMA transfer, DMA transfer settings must be made again. In this case, the Renesas SPDIF's module enable bit (either the RME or TME bit) and the DMA enable bit (either the RDE or TDE bit) must be disabled and the error status must be cleared before making DMA transfer settings again. Then the module enable bit should be set and DMA transfer can be started again. Page 1342 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.7.3 Section 25 Renesas SPDIF Interface Transmitter Channel 1 Audio Register (TLCA) Bit: 31 30 29 28 27 26 25 24 - - - - - - - - Initial value: R/W: W W W W W W W W Bit: 23 22 21 20 19 18 17 16 Audio PCM Data Initial value: R/W: 0 W 0 W 0 W Bit: 15 14 13 0 W 0 W 0 W 0 W 0 W 12 11 10 9 8 Audio PCM Data Initial value: R/W: 0 W 0 W 0 W Bit: 7 6 5 0 W 0 W 0 W 0 W 0 W 4 3 2 1 0 0 W 0 W 0 W Audio PCM Data Initial value: R/W: 0 W 0 W 0 W 0 W 0 W Initial Value R/W Description 31 to 24   W Reserved 23 to 0 All 0 W Audio PCM Data Bit Bit Name Audio PCM Data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 LSB aligned PCM encoded audio data. Page 1343 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.4 Transmitter Channel 2 Audio Register (TRCA) Bit: 31 30 29 28 27 26 25 24 - - - - - - - - Initial value: R/W: W W W W W W W W Bit: 23 22 21 20 19 18 17 16 Audio PCM Data Initial value: R/W: 0 W 0 W 0 W Bit: 15 14 13 0 W 0 W 0 W 0 W 0 W 12 11 10 9 8 Audio PCM Data Initial value: R/W: 0 W 0 W 0 W Bit: 7 6 5 0 W 0 W 0 W 0 W 0 W 4 3 2 1 0 0 W 0 W 0 W Audio PCM Data Initial value: R/W: 0 W 0 W 0 W 0 W 0 W Initial Value R/W Description 31 to 24   W Reserved 23 to 0 All 0 W Audio PCM Data Bit Bit Name Audio PCM Data Page 1344 of 3092 LSB aligned PCM encoded audio data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.7.5 Section 25 Renesas SPDIF Interface Transmitter DMA Audio Data Register (TDAD) Bit: 31 30 29 28 27 26 25 24 - - - - - - - - Initial value: R/W: W W W W W W W W Bit: 23 22 21 20 19 18 17 16 Audio PCM Data Initial value: R/W: 0 W 0 W 0 W Bit: 15 14 13 0 W 0 W 0 W 0 W 0 W 12 11 10 9 8 Audio PCM Data Initial value: R/W: 0 W 0 W 0 W Bit: 7 6 5 0 W 0 W 0 W 0 W 0 W 4 3 2 1 0 0 W 0 W 0 W Audio PCM Data Initial value: R/W: Bit Bit Name 31 to 24  23 to 0 0 W 0 W 0 W 0 W 0 W Initial Value R/W Description  W Reserved W Audio PCM Data Audio PCM All 0 Data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 LSB aligned PCM encoded audio data. Page 1345 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.6 Transmitter User Data Register (TUI) U-bit data in subframes is written in to this register. Because U-bit data is transmitted in a sequence of subframes 1 and 2, you need to update the data on a 16-frame basis. For the contents of the user bytes refer to the appropriate standard for the device in use. The user bits to be transmitted are set in sequence starting at the LSB. Bit: 31 30 29 28 27 26 25 24 User Byte 4 Initial value: R/W: 0 W 0 W 0 W Bit: 23 22 21 0 W 0 W 0 W 0 W 0 W 20 19 18 17 16 User Byte 3 Initial value: R/W: 0 W 0 W 0 W Bit: 15 14 13 0 W 0 W 0 W 0 W 0 W 12 11 10 9 8 User Byte 2 Initial value: R/W: 0 W 0 W 0 W Bit: 7 6 5 0 W 0 W 0 W 0 W 0 W 4 3 2 1 0 0 W 0 W 0 W User Byte 1 Initial value: R/W: Bit Bit Name Initial Value 0 W 0 W 0 W 0 W 0 W R/W Description 31 to 24 User Byte 4 All 0 W U-bit information is stored here. 23 to 16 User Byte 3 All 0 W 15 to 8 User Byte 2 All 0 W 7 to 0 User Byte 1 All 0 W Page 1346 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.7.7 Section 25 Renesas SPDIF Interface Transmitter Channel 1 Status Register (TLCS) The 30-bit register stores the channel status information to be transmitted. For each channel, channel status information per frame consists of 192 bits. Because necessary data covers only the 30 bits that are set in the following register, zeros continue to be sent after the transmission of the first 30 bits. 31 30 - - Initial value: R/W: W W 0 W 0 W 0 W Bit: 23 22 21 20 19 Bit: 29 28 27 CLAC[1:0] 0 W 0 W 0 W Bit: 15 14 13 25 24 FS[3:0] 0 W 0 W 0 W 18 17 16 SRCNO[3:0] CHNO[3:0] Initial value: R/W: 26 0 W 0 W 0 W 0 W 0 W 12 11 10 9 8 0 W 0 W 0 W 0 W 3 2 1 0 0 W 0 W 0 W CATCD[7:0] Initial value: R/W: 0 W 0 W 0 W 0 W Bit: 7 6 5 4 - - 0 W 0 W Initial value: R/W: CTL[4:0] 0 W 0 W 0 W Bit Bit Name Initial Value R/W Description 31, 30   W Reserved 29, 28 CLAC[1:0] All 0 W - Clock Accuracy 00: Level 2 01: Level 1 10: Level 3 11: Reserved 27 to 24 FS[3:0] All 0 W Sample Frequency (FS) 0000: 44.1 kHz 0010: 48 kHz 0011: 32 kHz R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1347 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name 23 to 20 CHNO[3:0] Initial Value R/W Description All 0 W Channel Number 0000: Don't care 0001: A (left channel) 0010: B (right channel) 0011: C 19 to 16 SRCNO[3:0] All 0 W Source Number 0000: Don't care 0001: 1 0010: 2 0011: 3 15 to 8 CATCD[7:0] All 0 W Category Code (Example) 00000000: 2-channel general format 00000001: 2-channel compact disc (IEC 908) 00000010: 2-channel PCM encoder/decoder 00000011: 2-channel digital audio tape recorder 7, 6  All 0 W Reserved The write value should always be 0. 5 to 1 CTL[4:0] All 0 W Control The control bits are copied from the source (see IEC60958 standard). 0  0 W Reserved The write value should always be 0. Page 1348 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.7.8 Section 25 Renesas SPDIF Interface Transmitter Channel 2 Status Register (TRCS) The 30-bit register stores the channel status information to be transmitted. For each channel, channel status information per frame consists of 192 bits. Because necessary data covers only the 30 bits that are set in the following register, zeros continue to be sent after the transmission of the first 30 bits. 31 30 - - Initial value: R/W: W W 0 W 0 W 0 W Bit: 23 22 21 20 19 Bit: 29 28 27 CLAC[1:0] 0 W 0 W 0 W Bit: 15 14 13 25 24 FS[3:0] 0 W 0 W 0 W 18 17 16 SRCNO[3:0] CHNO[3:0] Initial value: R/W: 26 0 W 0 W 0 W 0 W 0 W 12 11 10 9 8 0 W 0 W 0 W 0 W 3 2 1 0 0 W 0 W 0 W CATCD[7:0] Initial value: R/W: 0 W 0 W 0 W 0 W Bit: 7 6 5 4 - - 0 W 0 W Initial value: R/W: CTL[4:0] 0 W 0 W 0 W Bit Bit Name Initial Value R/W Description 31, 30   W Reserved 29, 28 CLAC[1:0] All 0 W Clock Accuracy - 00: Level 2 01: Level 1 10: Level 3 11: Reserved 27 to 24 FS[3:0] All 0 W Sample Frequency (FS) 0000: 44.1 kHz 0010: 48 kHz 0011: 32 kHz R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1349 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name 23 to 20 CHNO[3:0] Initial Value R/W Description All 0 W Channel Number 0000: Don't care 0001: A (left channel) 0010: B (right channel) 0011: C 19 to 16 SRCNO[3:0] All 0 W Source Number 0000: Don't care 0001: 1 0010: 2 0011: 3 15 to 8 CATCD[7:0] All 0 W Category Code (Example) 00000000: 2-channel general format 00000001: 2-channel compact disc (IEC 908) 00000010: 2-channel PCM encoder/decoder 00000011: 2-channel digital audio tape recorder 7, 6  All 0 W Reserved The write value should always be 0. 5 to 1 CTL[4:0] All 0 W Control The control bits are copied from the source (see IEC60958 standard). 0  0 W Reserved The write value should always be 0. Page 1350 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.7.9 Section 25 Renesas SPDIF Interface Receiver Channel 1 Audio Register (RLCA) Bit: 31 30 29 28 27 26 25 24 - - - - - - - - Initial value: R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Audio PCM Data Initial value: R/W: 0 R 0 R 0 R Bit: 15 14 13 0 R 0 R 0 R 0 R 0 R 12 11 10 9 8 Audio PCM Data Initial value: R/W: 0 R 0 R 0 R Bit: 7 6 5 0 R 0 R 0 R 0 R 0 R 4 3 2 1 0 0 R 0 R 0 R Audio PCM Data Initial value: R/W: Bit Bit Name 31 to 24  23 to 0 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description  R Reserved R Audio PCM Data Audio PCM All 0 Data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 LSB aligned PCM encoded audio data. Page 1351 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.10 Receiver Channel 2 Audio Register (RRCA) Bit: 31 30 29 28 27 26 25 24 - - - - - - - - Initial value: R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Audio PCM Data Initial value: R/W: 0 R 0 R 0 R Bit: 15 14 13 0 R 0 R 0 R 0 R 0 R 12 11 10 9 8 Audio PCM Data Initial value: R/W: 0 R 0 R 0 R Bit: 7 6 5 0 R 0 R 0 R 0 R 0 R 4 3 2 1 0 0 R 0 R 0 R Audio PCM Data Initial value: R/W: Bit Bit Name 31 to 24  23 to 0 0 R 0 R 0 R 0 R Initial Value R/W Description  R Reserved Audio PCM All 0 Data Page 1352 of 3092 0 R R Audio PCM Data LSB aligned PCM encoded audio data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.11 Receiver DMA Audio Data (RDAD) Bit: 31 30 29 28 27 26 25 24 - - - - - - - - Initial value: R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Audio PCM Data Initial value: R/W: 0 R 0 R 0 R Bit: 15 14 13 0 R 0 R 0 R 0 R 0 R 12 11 10 9 8 Audio PCM Data Initial value: R/W: 0 R 0 R 0 R Bit: 7 6 5 0 R 0 R 0 R 0 R 0 R 4 3 2 1 0 0 R 0 R 0 R Audio PCM Data Initial value: R/W: Bit Bit Name 31 to 24  23 to 0 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description  R Reserved R Audio PCM Data Audio PCM All 0 Data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 LSB aligned PCM encoded audio data. Page 1353 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.12 Receiver User Data Register (RUI) The register stores the U-bit data received through the Renesas SPDIF. Because U-bit data is stored in a sequence of subframes 1 and 2 starting at the LSB, you need to read the data on a 16frame basis. For the contents of the user bytes refer to the appropriate standard for the device in use. Bit: 31 30 29 28 27 26 25 24 User Byte 4 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 23 22 21 20 19 18 17 16 User Byte 3 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 User Byte 2 Initial value: R/W: 0 R 0 R 0 R Bit: 7 6 5 0 R 0 R 0 R 0 R 0 R 4 3 2 1 0 0 R 0 R 0 R User Byte 1 Initial value: R/W: Bit Bit Name Initial Value 0 R 0 R 0 R 0 R 0 R R/W Description 31 to 24 User Byte 4 All 0 R U-bit information is stored here. 23 to 16 User Byte 3 All 0 R 15 to 8 User Byte 2 All 0 R 7 to 0 User Byte 1 All 0 R Page 1354 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.13 Receiver Channel 1 Status Register (RLCS) The channel status is stored starting at the register's LSB in a way that subframe 1 received from the beginning of the block is stored. For the contents of the channel status register, refer to the IEC-60958 standard. 31 30 - - Initial value: R/W: R R 0 R 0 R 0 R Bit: 23 22 21 20 19 Bit: 29 28 27 CLAC[1:0] 0 R 0 R 0 R Bit: 15 14 13 25 24 FS[3:0] 0 R 0 R 0 R 18 17 16 SRCNO[3:0] CHNO[3:0] Initial value: R/W: 26 0 R 0 R 0 R 0 R 0 R 12 11 10 9 8 0 R 0 R 0 R 0 R 3 2 1 0 0 R 0 R 0 R CATCD[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R Bit: 7 6 5 4 - - 0 R 0 R Initial value: R/W: CTL[4:0] 0 R 0 R Bit Bit Name Initial Value R/W Description 31, 30   R Reserved 29, 28 CLAC[1:0] All 0 R 0 R - Clock Accuracy 00: Level 2 01: Level 1 10: Level 3 11: Reserved 27 to 24 FS[3:0] All 0 R Sample Frequency (FS) 0000: 44.1 kHz 0010: 48 kHz 0011: 32 kHz R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1355 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name 23 to 20 CHNO[3:0] Initial Value R/W Description All 0 R Channel Number 0000: Don't care 0001: A (left channel) 0010: B (right channel) 0011: C 19 to 16 SRCNO[3:0] All 0 R Source Number 0000: Don't care 0001: 1 0010: 2 0011: 3 15 to 8 CATCD[7:0] All 0 R Category Code (Example) 00000000: 2-channel general format 00000001: 2-channel compact disc (IEC 908) 00000010: 2-channel PCM encoder/decoder 00000011: 2-channel digital audio tape recorder 7, 6  All 0 R Reserved 5 to 1 CTL[4:0] All 0 R Control The control bits are copied from the source (see IEC60958 standard). 0  Page 1356 of 3092 0 R Reserved R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface 25.7.14 Receiver Channel 2 Status Register (RRCS) The channel status is stored starting at the register's LSB in a way that subframe 2 received from the beginning of the block is stored. For the contents of the channel status register, refer to the IEC-60958 standard. 31 30 - - Initial value: R/W: R R 0 R 0 R 0 R Bit: 23 22 21 20 19 Bit: 29 28 27 CLAC[1:0] 0 R 0 R 0 R Bit: 15 14 13 25 24 FS[3:0] 0 R 0 R 0 R 18 17 16 SRCNO[3:0] CHNO[3:0] Initial value: R/W: 26 0 R 0 R 0 R 0 R 0 R 12 11 10 9 8 0 R 0 R 0 R 0 R 3 2 1 0 0 R 0 R 0 R CATCD[7:0] Initial value: R/W: 0 R 0 R 0 R 0 R Bit: 7 6 5 4 - - 0 R 0 R Initial value: R/W: CTL[4:0] 0 R 0 R Bit Bit Name Initial Value R/W Description 31, 30   R Reserved 29, 28 CLAC[1:0] All 0 R 0 R - Clock Accuracy 00: Level 2 01: Level 1 10: Level 3 11: Reserved 27 to 24 FS[3:0] All 0 R Sample Frequency (FS) 0000: 44.1 kHz 0010: 48 kHz 0011: 32 kHz R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1357 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Bit Bit Name 23 to 20 CHNO[3:0] Initial Value R/W Description All 0 R Channel Number 0000: Don't care 0001: A (left channel) 0010: B (left channel) 0011: C 19 to 16 SRCNO[3:0] All 0 R Source Number 0000: Don't care 0001: 1 0010: 2 0011: 3 15 to 8 CATCD[7:0] All 0 R Category Code (Example) 00000000: 2-channel general format 00000001: 2-channel compact disc (IEC 908) 00000010: 2-channel PCM encoder/decoder 00000011: 2-channel digital audio tape recorder 7, 6  All 0 R Reserved 5 to 1 CTL[4:0] All 0 R Control The control bits are copied from the source (see IEC60958 standard). 0  Page 1358 of 3092 0 R Reserved R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.8 Functional Description—Transmitter 25.8.1 Transmitter Module Section 25 Renesas SPDIF Interface The transmitter module transmits PCM data and auxiliary information after encoding it according to the method of biphase-mark modulation that complies with the IEC60958 standard (SPDIF). The clock for the transmitter module is an oversampling clock supplied from the outside. This clock usually selects a value that serves as an oversample at a frequency eight times larger than the clock frequency required for biphase-mark encoding. In this case, the clock frequency required to transmit 32 time slots in a subframe is 512 times as large as the sample frequency for audio data. Audio data and channel status information are first written into the module's channel 1 and then into channel 2. Generally, the channel status need to be written only when the information changes. The SPDIF module requests that the channel status be written in 30 frames -- when all the current channel status data have been transmitted. You need to write somewhere between frame 31 and the beginning of the next block of 192 frames. The audio data is stored in a double buffer arrangement. To make sure that the first stage buffer is empty, you can send an interrupt request or poll the status register. DMA transfers send channel 1 audio data on the first request and channel 2 data on the second. The channel status information is stored in the 30-bit registers of channels 1 and 2. For each channel, the channel status information per frame consists of 192 bits. Because necessary data covers only 30 bits, zeros continue to be sent after the transmission of the first 30 bits until the block is completed. User data forms a 32-bit double buffer arrangement. You can make sure that the first stage buffer is empty by either sending an interrupt request or polling the status register. Usually, information about the user data will become insufficient with the length of data between blocks. Transmission takes place in a sequence of channels 1 and 2. For the user data within a block, 384 bits are transmitted before the next block is continuously transmitted. The audio data handled by the Renesas SPDIF module is a linear PCM, making it possible to set up to 24 bits. For this reason, the V flag indicating that audio data is a linear PCM remains to be 0. The V flag involves no register-based setting. An even parity is created for each 32 bits of serial output data (excluding the preamble). Note: When transmitter user buffer underrun occurs, the current data in the buffer data of SPDIF is transmitted until the next data is filled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1359 of 3092 Section 25 Renesas SPDIF Interface 25.8.2 SH7268 Group, SH7269 Group Transmitter Module Initialization The device defaults to an idle state when it comes out of reset, or can be put into an idle state when 0 is written to the TME bit in the CTRL register. When the transmitter module is idle, it has the following settings:      The transmitter idle status bit (TIS) is set to 1, all other status bits are cleared to 0. Preamble generation is invalid. Synchronization between channels 1 and 2 is set to 0 (0 for channel 1, 1 for channel 2). Both word_count and frame_count are set to 0. The output from the biphase-mark encoder is set to 0. Channel status, user and audio data registers will retain its value prior to putting the module into idle. To exit the idle state the user must write 1 to the TME bit in the CTRL register. 25.8.3 Initial Settings for Transmitter Module When the TME bit is set to 1, the TUIR and CSTX bits are set to 1. After that, if data is written in the order of 1) TUI and 2) TLCS and TRCS, a channel status error will occur. To avoid this, be sure to write data in the order of 1) TLCS and TRCS and 2) TUI. Before writing the first audio data (write access to TLCA or TRCA by the CPU or write access to TDAD by the DMA transfer) after setting the TME bit to 1, be sure to check that the CSTX and TUIR bits are cleared by writing to TLCS, TRCS, and TUI. Page 1360 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.8.4 Section 25 Renesas SPDIF Interface Transmitter Module Data Transfer Once the transmitter module has left the idle state, it is ready for data transfer. Data transfer timing can be achieved in three ways. Either the transfer is done by interrupts, DMA requests or by polling the status register. There is a shared interrupt line (for both transmit and receive) and a single transmitter DMA request line. Figure 25.5 shows a data transfer with an interrupt for the transmitter. Start Idle Set control bit enabled (TCBI) Wait for interrupt Load left or right audio channel data Enter idle state? No Yes Set control bit disabled (TCBI) Figure 25.5 Transmitter Data Transfer Flow Diagram - Interrupt Driven R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1361 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Figure 25.6 shows a data transfer with a DMA transfer for the transmitter. Start Idle Wait for transmitter DMA request Load left or right audio channel data Yes Enter idle state? No Figure 25.6 Transmitter Data Transfer Flow Diagram—DMA Request Driven Channel status information is required to be updated when the information has changed. Because the updating needs to be done before the transmission of the next block, the channel status to be updated should be written after 30 frames have been sent; this is indicated either by an interrupt or by polling the status bit. If channel status is written before 30 frames have been sent (while current information is being sent) then an interrupt indicates that the channel status error bit (CSE) in the status register has been set. Note: 30 frames contains all the valid information in a single channel status block. Page 1362 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.9 Functional Description—Receiver 25.9.1 Receiver Module Section 25 Renesas SPDIF Interface The receiver module demodulates data and clock signals from the input encoded according to the IEC60958 standard. The encoded data, shown in linear PCM format, is stored into the audio data register. The register also stores the channel status and user information being received simultaneously as auxiliary information. The main clock for the receiver module is an oversampling clock supplied from the outside. The module operates at a frequency four times as large as the oversampling clock. Note: The oversampling clock is the same for the transmitter and receiver. Clock recovery is performed using a pulse width counter and averaging filters to produce a sampling pulse in the middle of each bit in the datastream. A clock error status bit indicates clock synchronization loss. Synchronization is achieved when a preamble occurs on the data stream for the first time. Continuous adjustment prevents jitter and/or clock drift from affecting clock recovery, provided that they fall within the clock recovery specifications. Once the clock recovery is successful the biphase-mark decoder initiates its preamble detection. The decoder searches for the start of block preamble (see table 25.2). A preamble error status bit indicates that following preambles have not appeared at the correct time, such failures are most likely caused by transmission loss or interference. Even parity checking is performed on the decoded data. A discrepancy will result in the parity error status bit being set. The SPDIF module acquires user data and channel status information in addition to audio data. The audio is stored in a double buffer arrangement. Either an interrupt request because of a full buffer or polling of the status bit will indicate when the data is ready to be read. DMA transfers receive channel 1 audio data on the first request and channel 2 data on the second. Channel status is stored in a 30-bit register. Channel status information is received at 1-bit per subframe. Therefore the registers will not be full until a total of 30 frames for each channel have been received. New channel status is compared with the current data to see if it has changed and is only read by the processor if it has. User data, which is also received at the same time, is stored into the register on a subframe basis, so that the reception is completed when 16 frames are reached. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1363 of 3092 Section 25 Renesas SPDIF Interface SH7268 Group, SH7269 Group Notes: 1. Channel status data requests do not support DMA. 2. When receiver user buffer overrun occurs, the current data in the buffer data of SPDIF is overwritten by the next incoming data from SPDIF interface. 25.9.2 Receiver Module Initialization The device defaults to an idle state when it comes out of reset, or can be put into an idle state by writing 0 to bit RME in the CTRL register. Whilst idle the module has the following settings:  The receiver idle status bit is set to 1, all other status bits are cleared to 0.  Synchronization between channels 1 and 2 is set to 0 (0 for channel 1, 1 for channel 2).  Both Word_count and frame_count are set to 0. Channel status registers, user data registers and audio data registers will retain its value prior to putting the module into idle. To exit the idle state the user must write 1 to the bit RME in the CTRL register. 25.9.3 Receiver Module Data Transfer Once the module has left the idle state it is ready for data transfer. Data transfer timing can be achieved in three ways. The transfer can be done by interrupts, or by polling the status register, or by DMA. There is a shared interrupt line (transmit and receive) and a single receiver DMA request line. Data transfer for the receiver can be interrupted by error signals caused by: 1. Clock recovery failure. 2. Transmission loss or interference – indicated by a preamble error. 3. Parity check failure. Transmission loss or interference can cause the start of subframe or start of block preamble to be misplaced or not present. Parity check failure occurs when the parity bit is incorrect, this can be caused by any of the above.  Clock Recovery Deviation The receive margin for clock recovery is based on the following equation: M= Page 1364 of 3092 0.5 − 1 D − 0.5 − (L − 0.5) F − (1 + F) × 100% 2N N R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group where Section 25 Renesas SPDIF Interface M = receive margin N = oversampling rate L = frame length = 33 D = duty cycle = 0.6 F = oversampling clock deviation = Level II accuracy = 1000 in 10e–6 Figure 25.7 indicates what the receive margin M represents Internal Clock Data M Sampling Clock Figure 25.7 Receive Margin Introducing jitter into the equation gives the following inequality. j≤ 0.5 − 1 D − 0.5 − (L − 0.5) F − (1 + F) × 100% 2N N J = clock jitter Eight times oversampling produces a receive margin = 39.25% Four times oversampling produces a receive margin = 31.75% Two times oversampling produces a receive margin = 16.75% The fastest sample frequency is 48 kHz. This requires a clock speed of 128  48 kHz = 6.144 MHz. The worst case jitter in one cycle is specified at 40 ns = 24.5% of the period. This means that an oversampling rate of 4 or more will satisfy the inequality and therefore be sufficient for clock recovery. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1365 of 3092 SH7268 Group, SH7269 Group Section 25 Renesas SPDIF Interface Figure 25.8 illustrates the receiver data transfer using interrupts. Start Idle Set control bit enabled (RCBI) Wait for interrupt Load left or right audio channel data Error detected? Yes Error handling No Enter idle state? No Yes Set control bit disabled (RCBI) Figure 25.8 Receiver Data Transfer Flow Diagram - Interrupt Driven Interrupts to indicate that the channel status information register is full occur after frame 30 has been received and only if the information has changed. When the first four bytes have been stored an interrupt occurs. Page 1366 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 25.10 Section 25 Renesas SPDIF Interface Disabling the Module 25.10.1 Transmitter and Receiver Idle The transmitter or receiver modules can be disabled by writing 0 to the idle bit in the control register (TME for the transmitter and RME for the receiver). The idle state can be detected by polling the idle bit in the status register (TIS and RIS). 25.11 Compressed Mode Data Compressed mode data is defined in the IEC 61937 specification. This module only detects compressed mode data. This is done by checking the parity flag (V flag) and bit 1 in the channel status data. If both are one then the data is in compressed mode. This is indicated by the setting of the CMD bit in the status register. Note: Only the receiver detects compressed mode data since the information is not relevant to the transmitter. 25.12 References IEC60958 Digital Audio Interface IEC61937 Compressed Mode Digital Audio Interface R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1367 of 3092 Section 25 Renesas SPDIF Interface 25.13 SH7268 Group, SH7269 Group Usage Notes 25.13.1 Clearing TUIR After TUI is written to, the TUIR bit is cleared only after transmission of a maximum of one frame is completed. When using a transmitter user information interrupt to write data to TUI, check that the TUIR bit is cleared before terminating the interrupt handling routine so that the interrupt is not unexpectedly accepted again. 25.13.2 Frequency of Clock Input for Audio The frequency of the clock input to the AUDIO_X1 and AUDIO_X2 or AUDIO_CLK must be lower than the P1 frequency. Page 1368 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Section 26 CD-ROM Decoder The CD-ROM decoder decodes streams of data transferred from the CD-DSP. When the medium is CD-DA*1, the data stream is not input to the CD-ROM decoder because it consists of PCM data. In the case of CD-ROM*2, the stream of data is input and the CD-ROM decoder performs sync code detection and maintenance, descrambling, ECC correction, and EDC checking, and outputs the resulting stream of data. However, since the stream received by the CD-ROM decoder is assumed to consist of data from a CD-ROM transferred via the serial sound interface, the decoder does not bother with the subcodes defined in the CD-DA standard. Notes: 1. Compliant with JIS S 8605 (Red Book) 2. Compliant with JIS X 6281 (Yellow Book) 26.1 Features  Sync-code detection and maintenance Detects sync codes from the CD-ROM and is capable of providing sync-code maintenance (automatic interpolation of sync codes) when the sync code cannot be detected because of defects such as scratches on the disc. Five sector-synchronization modes are supported: automatic sync maintenance mode, external sync mode, interpolated sync mode, and interpolated sync plus external sync mode.  Descrambling  ECC support P-parity-based correction, Q-parity-based correction, PQ correction, and QP correction are available. PQ correction and QP correction can be applied repeatedly up to three times. This, however, depends on the speed of the CD. For example, three iterations are possible when the CD-ROM decoder is operating at 60 MHz with a double-speed CD drive. Two buffers are provided due to the need for ECC correction. This allows parallel operation, where ECC correction is performed in one buffer while the data stream is being received in the other.  EDC checking The EDC is checked before and after correction based on the ECC. Furthermore, an operating mode is available in which, if the result of pre-correction EDC checking indicates no errors, ECC correction is not performed regardless of the result of syndrome calculation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1369 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder  Data buffering control The CD-ROM decoder outputs data to the buffer area in a specific format where the sync code is at the head of the data for each sector. 26.1.1 Formats Supported by CD-ROM Decoder This module supports the five formats shown in figure 26.1. Mode0 Sync (12 bytes) Header (4 bytes) Mode1 Sync (12 bytes) Header (4 bytes) Mode2 (not XA) Sync (12 bytes) Header (4 bytes) Mode2 Form1 Sync (12 bytes) Header (4 bytes) Sub-header (8 bytes) Mode2 Form2 Sync (12 bytes) Header (4 bytes) Sub-header (8 bytes) All 0 EDC (4 bytes) Data (2048 bytes) 0 (8 bytes) P-parity (172 bytes) Q-parity (104 bytes) EDC (4 bytes) P-parity (172 bytes) Q-parity (104 bytes) Data (2336 bytes) Data (2048 bytes) EDC (4 bytes) Data (2324 bytes) Figure 26.1 Formats Supported by CD-ROM Decoder Page 1370 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 26.2 Section 26 CD-ROM Decoder Block Diagrams Figure 26.2 is a block diagram of the CD-ROM decoder functions of this LSI and the bus bridge for connection to the bus, that is, of the elements required to implement the CD-ROM decoder function. Internal bus Bus bridge Register data Stream data input control EDC Memory (2 buffers for ECC) EDC Memory control Descrambler Sync code detection/ maintenance Stream data Mode determination ECC control Syndrome calculator Stream data output control Stream data Timing generation Core of CD-ROM decoder Interrupt and direct memory access controller activation control Interrupt controller, direct memory access controller Figure 26.2 Block Diagram The core of the CD-ROM decoder executes a series of processing required for CD-ROM decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based correction), and EDC checking. The core includes sufficient memory to hold two sectors. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1371 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Input data come from the internal bus and output data go out via the internal bus along a single line each, but the bus bridge logic sets up branches for the register access port and stream data port. The stream data from the CD-DSP are transferred via the serial sound interface to the stream data input control block. They are then subjected to descrambling, ECC correction, and EDC checking as they pass through the CD-ROM decoder. After these processes, data from one sector are obtained. The data are subsequently transferred to the stream-data buffer via the stream-data output control block. Data can be transferred by either the direct memory access controller or the CPU. Figure 26.3 is a block diagram of the bus-bridge logic. Since the input stream is transferred over the serial sound interface, transfer is relatively slow. On the other hand, data from the output stream can be transferred at high speeds because they are already in the core of the CD-ROM decoder. Since the data for output are buffered in SDRAM or other memory, they must be transferred at high speeds in order to reduce the busy rate of the SDRAM. For this reason, the data for the output stream are read out before the CD-ROM decoder receives an output stream data read request from the internal bus. This allows the accumulation of streaming data in the registers of the bus bridge, so that the data are ready for immediate output to the internal bus upon a request from the internal bus. Accordingly, the reception of a request to read from registers other than the stream-data registers after the stream data has already been read out and stored in the register of the bus bridge is possible. To cope with this, the CD-ROM decoder is provided with separate intermediary registers for the output stream-data register and the other registers. Input data from the internal bus Data for output to the internal bus Buffer control signal for the output stream-data section Input stream data Register data (write) Register data (read) Output stream data Output stream-data control signal Figure 26.3 Schematic Diagram of the Bus Bridge Page 1372 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Figure 26.4 is a schematic diagram of the stream-data input control block. The stream-data input controller contains logic that controls the stream of input data and a register that is used to change the control mode of the CD-ROM decoder. The serial sound interface mode used to transfer the stream data may affect the order (through the endian setting) or lead to padding before the data is transferred. To handle the different arrangements of data appropriately, the stream-data input control block includes a register for changing the operating mode and generates signals to control the core of the CD-ROM decoder. The data holding registers for the input stream consists of two 16-bit registers. The data holding registers are controlled according to the mode set in the control register. For example, controlling the order in which 16-bit data is supplied to the core of the CD-ROM decoder (sending the second 16-bytes first or vice versa). It is also possible to stop the supply of padding data to the core of the CD-ROM decoder. Register data Input stream data Select 16 bits Core of CD-ROM decoder Register access controller 16 bits Input stream controller Figure 26.4 Schematic Diagram of the Stream-Data Input Control Block R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1373 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Figure 26.5 is a schematic diagram of the stream-data output control block. On recognizing that one sector of CD-ROM data is ready in the core of the CD-ROM decoder, this block ensures that the output stream-data register in the bus bridge section is empty and then starts to acquire the data for output from the core of the CD-ROM decoder. Core of CD-ROM decoder Output stream data Output stream-data control signal Output stream-data protocol controller Figure 26.5 Schematic Diagram of the Stream-Data Output Control Block This block has functions related to interrupts and direct memory access controller activation control such as suspending and masking of interrupts, turning interrupt flags off after they are read, asserting the activation signal to the direct memory access controller, and negating the activation signal according to the detected amount of data that has been transferred. Page 1374 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 26.3 Section 26 CD-ROM Decoder Register Descriptions This module has the following registers. Table 26.1 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Enable control register CROMEN R/W H'00 H'E8005000 8 Sync code-based synchronization control register CROMSY0 R/W H'89 H'E8005001 8 Decoding mode control register CROMCTL0 R/W H'82 H'E8005002 8 EDC/ECC check control register CROMCTL1 R/W H'D1 H'E8005003 8 Automatic decoding stop control register CROMCTL3 R/W H'00 H'E8005005 8 Decoding option setting control register CROMCTL4 R/W H'00 H'E8005006 8 HEAD20 to HEAD22 representation control register CROMCTL5 R/W H'00 H'E8005007 8 Sync code status register CROMST0 R H'00 H'E8005008 8 Post-ECC header error status register CROMST1 R H'00 H'E8005009 8 Post-ECC subheader error status register CROMST3 R H'00 H'E800500B 8 Header/subheader validity check status register CROMST4 R H'00 H'E800500C 8 Mode determination and link sector detection status register CROMST5 R H'00 H'E800500D 8 ECC/EDC error status register CROMST6 R H'00 H'E800500E 8 Buffer status register CBUFST0 R H'00 H'E8005014 8 Decoding stoppage source status register CBUFST1 R H'00 H'E8005015 8 Buffer overflow status register CBUFST2 R H'00 H'E8005016 8 Pre-ECC correction header: minutes data register HEAD00 R H'00 H'E8005018 8 Pre-ECC correction header: seconds data register HEAD01 R H'00 H'E8005019 8 Pre-ECC correction header: frames (1/75 second) data register HEAD02 R H'00 H'E800501A 8 Pre-ECC correction header: mode data register HEAD03 R H'00 H'E800501B 8 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1375 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Name Abbreviation R/W Initial Value Address Access Size Pre-ECC correction subheader: file number (byte 16) data register SHEAD00 R H'00 H'E800501C 8 Pre-ECC correction subheader: channel number (byte 17) data register SHEAD01 R H'00 H'E800501D 8 Pre-ECC correction subheader: sub-mode (byte 18) data register SHEAD02 R H'00 H'E800501E 8 Pre-ECC correction subheader: data type (byte 19) data register SHEAD03 R H'00 H'E800501F 8 Pre-ECC correction subheader: file number (byte 20) data register SHEAD04 R H'00 H'E8005020 8 Pre-ECC correction subheader: channel number (byte 21) data register SHEAD05 R H'00 H'E8005021 8 Pre-ECC correction subheader: sub-mode (byte 22) data register SHEAD06 R H'00 H'E8005022 8 Pre-ECC correction subheader: data type (byte 23) data register SHEAD07 R H'00 H'E8005023 8 Post-ECC correction header: minutes data register HEAD20 R H'00 H'E8005024 8 Post-ECC correction header: seconds data register HEAD21 R H'00 H'E8005025 8 Post-ECC correction header: frames (1/75 second) data register HEAD22 R H'00 H'E8005026 8 Post-ECC correction header: mode data register HEAD23 R H'00 H'E8005027 8 Post-ECC correction subheader: file number (byte 16) data register SHEAD20 R H'00 H'E8005028 8 Post-ECC correction subheader: channel number (byte 17) data register SHEAD21 R H'00 H'E8005029 8 Post-ECC correction subheader: sub-mode (byte 18) data register SHEAD22 R H'00 H'E800502A 8 Post-ECC correction subheader: data type (byte 19) data register SHEAD23 R H'00 H'E800502B 8 Post-ECC correction subheader: file number (byte 20) data register SHEAD24 R H'00 H'E800502C 8 Page 1376 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Name Abbreviation R/W Initial Value Address Post-ECC correction subheader: channel number (byte 21) data register SHEAD25 R H'00 H'E800502D 8 Post-ECC correction subheader: sub-mode (byte 22) data register SHEAD26 R H'00 H'E800502E 8 Post-ECC correction subheader: data type (byte 23) data register SHEAD27 R H'00 H'E800502F 8 Automatic buffering setting control register CBUFCTL0 R/W H'04 H'E8005040 8 Automatic buffering start sector setting: minutes control register CBUFCTL1 R/W H'00 H'E8005041 8 Automatic buffering start sector setting: seconds control register CBUFCTL2 R/W H'00 H'E8005042 8 Automatic buffering start sector setting: frames control register CBUFCTL3 R/W H'00 H'E8005043 8 ISY interrupt source mask control register CROMST0M R/W H'00 H'E8005045 8 CD-ROM decoder reset control register ROMDECRST R/W H'00 H'E8005100 8 CD-ROM decoder reset status register RSTSTAT R H'00 H'E8005101 8 Serial sound interface data control register SSI R/W H'18 H'E8005102 8 Interrupt flag register INTHOLD R/W H'00 H'E8005108 8 Interrupt source mask control register INHINT R/W H'00 H'E8005109 8 CD-ROM decoder stream data input register STRMDIN0 R/W H'0000 H'E8005200 Read: 16 Write: 16/32 CD-ROM decoder stream data input register STRMDIN2 R/W H'0000 H'E8005202 16 CD-ROM decoder stream data output register STRMDOUT0 R H'0000 H'E8005204 16, 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Access Size Page 1377 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.1 Enable Control Register (CROMEN) The enable control register (CROMEN) enables subcode processing and CD-ROM decoding, and stops CD-ROM decoding forcibly. Bit: 7 6 5 SUBC_ CROM_ CROM_ EN EN STP Initial value: R/W: Initial Value Bit Bit Name 7 SUBC_EN 0 0 R/W 0 R/W 0 R/W 4 3 2 1 - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W Subcode Processing Enable 0 This bit should be set and cleared simultaneously with CROM_EN. It is automatically cleared when decoding is automatically stopped due to an abnormal condition or when CROM_STP = 1 6 CROM_EN 0 R/W CD-ROM Decoding Enable When this bit is set to 1, CD-ROM decoding starts after detection of a valid sync code. When the bit is cleared to 0, decoding stops on completion of the processing for the sector currently being decoded. This bit is automatically cleared when the automatic decode-stopping function woks or when CROM_STP = 1. 5 4 to 0 CROM_ STP 0  All 0 R/W Forcible Stop of CD-ROM Decoding When this bit is set to 1, CD-ROM decoding is stopped immediately and the SUBC_EN and CROM_EN bits are automatically reset to 0. Before decoding can resume, this bit must be cleared to 0. R/W Reserved These bits are always read as 0.The write value should always be 0. Page 1378 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 26.3.2 Section 26 CD-ROM Decoder Sync Code-Based Synchronization Control Register (CROMSY0) The sync code-based synchronization control register (CROMSY0) selects the sync code maintenance function. Bit: Initial value: R/W: 7 6 5 4 3 2 1 SY_ AUT SY_ IEN SY_ DEN - - - - 0 - 1 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 SY_AUT 1 R/W Automatic CD-ROM Sync Code Maintenance Mode When this bit is set to 1, automatic sync maintenance (insertion of sync codes) is applied to obtain the CDROM sync codes. While this bit is set, the settings of the SY_IEN and SY_DEN bits are invalid. 6 SY_IEN 0 R/W Internal Sync Signal Enable Enables the internal sync signal that is produced by the counter in the CD-ROM decoder. When this bit is set while SY_AUT = 0, synchronization of the CD-ROM data is in interpolated mode, i.e. driven by the internal counter. 5 SY_DEN 0 R/W Synchronization with External Sync Code Selects constant monitoring for the sync code in the input data and bases synchronization solely on detection of the code, regardless of the value of the internal counter. The setting of this bit is valid when SY_AUT = 0. 4  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 3  1 R/W Reserved This bit is always read as 1. The write value should always be 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1379 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name Initial Value R/W Description 2, 1  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 0  1 R/W Reserved This bit is always read as 1. The write value should always be 1. Table 26.2 Register Settings for Sync Code Maintenance Function SY_AUT SY_IEN SY_DEN Operating Mode 1   Automatic sync maintenance mode 0 0 1 External sync mode 0 1 0 Interpolated sync mode 0 1 1 Interpolated sync plus external sync mode 0 0 0 Setting prohibited 26.3.3 Decoding Mode Control Register (CROMCTL0) The decoding mode control register (CROMCTL0) enables/disables the various functions, selects criteria for mode or form determination, and specifies the sector type. The setting of this register becomes valid at the sector-to-sector transition Bit: Initial value: R/W: Initial Value Bit Bit Name 7 MD_DESC 1 7 6 5 MD_ DESC - MD_ AUTO 1 R/W 0 R/W 0 R/W R/W R/W 4 3 2 MD_ MD_ AUTOS1 AUTOS2 0 R/W 0 R/W 1 0 MD_SEC[2:0] 0 R/W 1 R/W 0 R/W Description Descrambling Function ON/OFF 0: Disables descrambling function 1: Enables descrambling function Page 1380 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name Initial Value R/W Description 6  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 5 MD_AUTO 0 R/W Automatic Mode/Form Detection ON/OFF 0: OFF 1: ON Detectable formats are Mode 0, Mode 1, Mode 2 (nonXA), Mode 2 Form 1, and Mode 2 Form 2. If the mode and form cannot be detected, the sector is taken to be in the same mode and form as the previous sector. If the mode and form of the first sector after decoding starts is undetectable, the setting of the MD_SEC[2:0] bits is used as the initial value. 4 MD_ AUTOS1 0 R/W Criteria for Mode Determination when MD_AUTO = 1 0: Mode determination is made only when the sync code is detected 1: Mode determination is always made The setting of this bit is valid only when the MD_AUTO bit is 1. If the mode cannot be determined, the mode of the previous sector is used. When this bit is cleared to 0, mode determination is made only when the sync code is detected for the sector. 3 MD_ AUTOS2 0 R/W Criteria for Mode 2 Form Determination when MD_AUTO = 1 0: The sector is assumed to be non-XA if the two form code bytes in the subheader do not match 1: No determination of XA or non-XA for the sector. The first form byte is regarded as valid. However, the two form bytes are compared, and the result is reflected in a status bit. The setting of this bit is valid only when the MD_AUTO bit is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1381 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name 2 to 0 MD_SEC [2:0] Initial Value R/W Description 010 R/W Sector Type 000: Setting prohibited 001: Mode 0 010: Mode 1 011: Long (Mode 0, Mode 1, or Mode 2 with no EDC/ECC data) 100: Setting prohibited 101: Mode 2 Form 1 110: Mode 2 Form 2 111: Mode 2 with automatic form detection If the form cannot be determined when set to B'111, it is processed as Mode 2 not XA. 26.3.4 EDC/ECC Check Control Register (CROMCTL1) The EDC/ECC check control register (CROMCTL1) controls EDC/ECC checking. The setting of this register becomes valid at the sector-to-sector transition Bit: 7 6 M2F2 EDC Initial value: R/W: Initial Value Bit Bit Name 7 M2F2EDC 1 1 R/W 5 4 MD_DEC[2:0] 1 R/W 0 R/W 1 R/W 3 2 - - 0 R/W 0 R/W 1 0 MD_PQREP[1:0] 0 R/W 1 R/W R/W Description R/W For Mode 2 Form 2, disables the EDC function for sectors where all bits of the EDC are 0. When this bit set to 1 and all bits of the EDC for a Mode 2 Form 2 sector are 0, an IERR interrupt is not generated even if the result of EDC checking is ‘fail’. Page 1382 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 6 to 4 MD_DEC [2:0] Section 26 CD-ROM Decoder Initial Value R/W Description 101 R/W EDC/ECC Checking Mode Select 000: No checking 001: EDC only 010: Q correction + EDC 011: P correction + EDC 100: QP correction + EDC 101: PQ correction + EDC 110: Setting prohibited 111: Setting prohibited 3, 2  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1, 0 MD_ PQREP [1:0] 01 R/W Number of Iterations of PQ or QP Correction Number of correction iterations when PQ- or QPcorrection is specified by MD_DEC[2:0]. 00: Setting prohibited 01: One iteration 10: Two iterations 11: Three iterations 26.3.5 Automatic Decoding Stop Control Register (CROMCTL3) The automatic decoding stop control register (CROMCTL3) is used to select abnormal conditions on which decoding will be automatically stopped. When decoding is stopped in response to any of the selected conditions, an IBUF interrupt is generated and the condition is indicated in the CBUFST1 register. The setting of this register becomes valid at the sector-to-sector transition Bit: Initial value: R/W: R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 7 6 5 4 3 2 1 STP_ ECC STP_ EDC - STP_ MD STP_ MIN - - 0 - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 1383 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name 7 Initial Value R/W Description STP_ECC 0 R/W When this bit is set to 1, decoding is stopped if an error is found to be not correctable by ECC correction. 6 STP_EDC 0 R/W When this bit is set to 1, decoding is stopped if postcorrection EDC checking indicates an error. 5  R/W Reserved 0 This bit is always read as 0. The write value should always be 0. 4 STP_MD 0 R/W When this bit is set to 1, decoding is stopped if the sector has a mode or form setting that does not match those of the immediately preceding sector. 3 STP_MIN 0 R/W When this bit is set to 1, decoding is stopped if a nonsequential minutes, seconds, or frames (1/75 second) value is encountered. 2 to 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 26.3.6 Decoding Option Setting Control Register (CROMCTL4) The decoding option setting control register (CROMCTL4) enables/disables buffering control at link block detection, specifies the information indicated by the status register, and controls the ECC correction mode. The setting of this register becomes valid at the sector-to-sector transition Bit: Initial value: R/W: Page 1384 of 3092 7 6 5 - LINK2 - 0 R/W 0 R/W 0 R/W 4 3 ER0SEL NO_ECC 0 R/W 0 R/W 2 1 - - 0 - 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name Initial Value R/W Description 7  0 R/W Reserved The write value may be either 0 or 1. When read, the value written will be returned. 6 LINK2 0 R/W Link Block Detection Condition 0: The block is regarded as a link block when either runout 1 or 2 and both run-in 3 and 4 have been detected. 1: The block is regarded as a link block when two out of run-out 1 and 2 and “link” have been detected. The condition for setting of the LINK_ON bit in CROMST5 is decoding of the link sector. 5  0 R/W Reserved This bit is always read as 0. The write value should always be 0. 4 ER0SEL 0 R/W CD-ROM Data-Related Status Register Setting Condition 0: Information is on the sector being decoded. 1: Information is on the latest sector that has been buffered. This condition affects the information given by bits 5 to 0 in the CROMST0 register, bits 7 to 1 in the CROMST4 and CROMST5 registers, and HEAD00 to HEAD02. 3 NO_ECC 0 R/W ECC correction mode when the result of the EDC check before ECC correction was ‘pass’ When this bit is set to 1, ECC correction is not performed if the result of pre-correction EDC checking is a ‘pass’, regardless of the results of syndrome calculation. 2 to 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1385 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5) The HEAD20 to HEAD22 representation control register (CROMCTL5) specifies the representation mode for HEAD20 to HEAD22. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - MSF_ LBA_SEL 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 0 MSF_LBA_ 0 SEL R/W HEAD20 to HEAD22 Representation Mode 0: Header MSF is represented in BCD (decimal) as is 1: Total sector number is represented in HEX (hexadecimal) Page 1386 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 26.3.8 Section 26 CD-ROM Decoder Sync Code Status Register (CROMST0) The sync code status register (CROMST0) indicates various status information in sync code maintenance modes Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - ST_ SYIL ST_ SYNO ST_ BLKS ST_ BLKL ST_ SECS ST_ SECL 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved These bits are always read as 0 and cannot be modified. 5 ST_SYIL 0 R Indicates that a sync code was detected at a position where the value in the word counter (used to measure intervals between sync codes) was not correct, but the sync code was ignored and not taken into account in synchronization. This bit is only valid in automatic sync maintenance mode and interpolated sync mode. 4 ST_SYNO 0 R Indicates that a sync code has not been detected despite the word counter having reached the final value, and synchronization has been continued with the aid of an interpolated sync code. This bit is only valid in automatic sync maintenance mode and interpolated sync mode. 3 ST_BLKS 0 R Indicates that a sync code was detected at a position where the value in the word counter was not correct, and the sync code was used in synchronization. This bit is only valid in automatic sync maintenance mode and external sync mode. 2 ST_BLKL 0 R Indicates that a sync code has not been detected despite the word counter having reached the final value, and the period of the sector has been prolonged. This bit is only valid in external sync mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1387 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name Initial Value R/W Description 1 ST_SECS 0 R Indicates that a sector has been processed as a short sector with the aid of interpolated sync codes. If this bit is set to 1, stop decoding immediately and retry the procedure starting from the sector prior to the currently being decoded sector. 0 ST_SECL 0 R Indicates that a sector has been processed as a long sector with the aid of interpolated sync codes. If this bit is set to 1, stop decoding immediately and retry the procedure starting from two sectors prior to the sector currently being decoded. 26.3.9 Post-ECC Header Error Status Register (CROMST1) The post-ECC header error status register (CROMST1) indicates error status in the post-ECC header. Bit: Initial value: R/W: 7 6 5 4 - - - - 0 R 0 R 0 R 0 R 3 2 1 0 ER2_ ER2_ ER2_ ER2_ HEAD0 HEAD1 HEAD2 HEAD3 Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved 0 R 0 R 0 R 0 R These bits are always read as 0 and cannot be modified. 3 ER2_ HEAD0 0 R Indicates an error in the minutes field of the header after ECC correction. 2 ER2_ HEAD1 0 R Indicates an error status in the seconds field of the header after ECC correction. 1 ER2_ HEAD2 0 R Indicates an error in the frames (1/75 second) field of the header after ECC correction. 0 ER2_ HEAD3 0 R Indicates an error in the mode field of the header after ECC correction. Page 1388 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.10 Post-ECC Subheader Error Status Register (CROMST3) The post-ECC subheader error status register (CROMST3) indicates error status in the post-ECC subheader. Bit: 7 6 5 4 3 2 ER2_ ER2_ ER2_ ER2_ ER2_ ER2_ SHEAD0 SHEAD1 SHEAD2 SHEAD3 SHEAD4 HEAD5 Initial value: R/W: Bit Bit Name 7 ER2_ SHEAD0 0 R 0 R 0 R 0 R 0 R 0 R 1 0 ER2_ HEAD6 ER2_ HEAD7 0 R 0 R Initial Value R/W Description 0 R Indicates that the subheader (file number) still has an error after ECC correction. Indicates the error of the SHEAD20 register. 6 ER2_ SHEAD1 0 R Indicates that the subheader (channel number) still has an error after ECC correction. Indicates the error of the SHEAD21 register. 5 ER2_ SHEAD2 0 R Indicates that the subheader (sub-mode) still has an error after ECC correction. Indicates the error of the SHEAD22 register. 4 ER2_ SHEAD3 0 R Indicates that the subheader (data type) still has an error after ECC correction. Indicates the error of the SHEAD23 register. 3 ER2_ SHEAD4 0 R Indicates that the subheader (file number) still has an error after ECC correction. Indicates the error of the SHEAD24 register. 2 ER2_ SHEAD5 0 R Indicates that the subheader (channel number) still has an error after ECC correction. Indicates the error of the SHEAD25 register. 1 ER2_ SHEAD6 0 R Indicates that the subheader (sub-mode) still has an error after ECC correction. Indicates the error of the SHEAD26 register. 0 ER2_ SHEAD7 0 R Indicates that the subheader (data type) still has an error after ECC correction. Indicates the error of the SHEAD27 register. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1389 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.11 Header/Subheader Validity Check Status Register (CROMST4) The header/subheader validity check status register (CROMST4) indicates errors relating to the automatic mode determination or form determination for Mode 2. Bit: 7 6 NG_MD Initial value: R/W: 0 R 5 4 3 2 1 0 NG_ NG_ NG_ NG_ NG_ NG_ NG_ MDCMP1 MDCMP2 MDCMP3 MDCMP4 MDDEF MDTIM1 MDTIM2 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 NG_MD 0 R Indicates that the sector mode could not be determined according to the automatic mode determination criteria. 6 NG_ MDCMP1 0 R Indicates a mismatch between the file number bytes (bytes 16 and 20) during the form determination for Mode 2. 5 NG_ MDCMP2 0 R Indicates a mismatch between the channel number bytes (bytes 17 and 21) during the form determination for Mode 2. 4 NG_ MDCMP3 0 R Indicates a mismatch between the sub-mode bytes (bytes 18 and 22) during the form determination for Mode 2. 3 NG_ MDCMP4 0 R Indicates a mismatch between the data-type bytes (bytes 19 and 23) during the form determination for Mode 2. 2 NG_ MDDEF 0 R Indicates that the mode and form differ from those of the previous sector. 1 NG_ MDTIM1 0 R Indicates that the minutes, seconds, or frames (1/75 second) value is out of sequence. In the continuity check for the next and subsequent sectors, the updated values will be used. 0 NG_ MDTIM2 0 R Indicates that the minutes, seconds, or frames (1/75 second) value was not a BCD value. Specifically, this bit means that any half-byte was beyond the range for BCD (i.e. was A to F), HEAD01 was greater than H'59, or HEAD02 was greater than H'74. In the continuity check for the next and subsequent sectors, interpolated values will be used. Page 1390 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5) The mode determination and link sector detection status register (CROMST5) indicates the result of automatic mode determination and link block detection. Bit: 7 6 5 ST_AMD[2:0] Initial value: R/W: 0 R 0 R 4 3 ST_MDX LINK_ON 0 R 0 R 0 R 2 1 0 LINK_ DET LINK_ SDET LINK_ OUT1 0 R 0 R 0 R Initial Value R/W Description ST_AMD [2:0] 000 R Result of Automatic Mode Determination These bits indicate the result of mode determination when the automatic mode determination function is used. 000: Automatic mode determination function is not used 001: Mode 0 010: Mode 1 011:  100: Mode 2 not XA 101: Mode 2 Form 1 110: Mode 2 Form 2 111:  4 ST_MDX 0 R Indicates that, when the mode has been manually set rather than automatically determined, the mode setting disagrees with the mode as recognized by the logic. In this case, the manually set value takes priority. 3 LINK_ON 0 R This bit is set to 1 when a link block was recognized in link block determination. For the criteria for link block determination, refer to the LINK2 bit in the CROMCTL4 register. 2 LINK_DET 0 R Indicates that a link block (run-out 1 to run-in 4) was detected. Since detection is based on the data before ECC correction, LINK_DET may also be set to 1 if data erroneously happens to contain the same code as a link block. Bit Bit Name 7 to 5 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1391 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Initial Value R/W Description LINK_ SDET 0 R Indicates that a link block was detected within seven sectors after the start of decoding. LINK_ OUT1 0 R Indicates that the sector after ECC correction has been identified as a run-out 1 sector. This bit is only valid when an IERR interrupt is not generated (i.e. when ECC correction was successful). Bit Bit Name 1 0 26.3.13 ECC/EDC Error Status Register (CROMST6) The ECC/EDC error status register (CROMST6) indicates ECC processing error or EDC check error before/after ECC correction. Bit: Initial value: R/W: 7 6 ST_ ERR - 0 R 0 R 5 4 ST_ ST_ ECCABT ECCNG 0 R 0 R 3 2 1 0 ST_ ECCP ST_ ECCQ ST_ EDC1 ST_ EDC2 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 ST_ERR 0 R Indicates that the decoded block after ECC correction contains any error (even in a single byte). 6  0 R Reserved This bit is always read as 0 and cannot be modified. 5 ST_ ECCABT Page 1392 of 3092 0 R Indicates that ECC processing was discontinued. This bit is set to 1 when a transition from sector to sector occurs while ECC correction is in progress. This does not indicate a problem for ECC correction if the BUF_NG bit in the CBUFST2 register is 0 at the same time. Whether or not this is so depends on the timing of the sector transition. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Initial Value R/W Description 0 R Indicates that error correction was not possible. ST_ECCP 0 R Bit Bit Name 4 ST_ ECCNG 3 This bit is also set to 1 on detection of a short sector. Indicates that P-parity errors were not corrected in ECC correction. This bit is only valid when synchronization is normal (the sector is neither short nor long). This bit is set to 1 when the result of syndrome calculation for P parity is non-0. 2 ST_ECCQ 0 R Indicates that Q-parity errors were not corrected in ECC correction. This bit is only valid when synchronization is normal (the sector is neither short nor long). This bit is set to 1 when the result of syndrome calculation for Q parity is other than all 0s. 1 ST_EDC1 0 R Indicates that the result of the EDC check before ECC correction was ‘fail’. This bit is also set to 1 if a short sector is encountered while EDC is enabled. 0 ST_EDC2 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R Indicates that the result of the EDC check after ECC correction was ‘fail’. Page 1393 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.14 Buffer Status Register (CBUFST0) The buffer status register (CBUFST0) indicates that the system is searching for the first sector to be buffered, or that buffering is in progress. Bit: Initial value: R/W: 7 6 5 4 3 2 1 BUF_ REF BUF_ ACT - - - - - 0 - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 BUF_REF 0 R Indicates that the search for the first sector to be buffered is in progress. This bit is only valid when the automatic buffering function is used (CBUF_AUT = 1). 6 BUF_ACT 0 R Indicates that buffering is in progress. 5 to 0  All 0 R Reserved These bits are always read as 0 and cannot be modified. Page 1394 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.15 Decoding Stoppage Source Status Register (CBUFST1) The decoding stoppage source status register (CBUFST1) indicates that decoding/buffering has been stopped due to some errors. A bit in this register can only be set when the corresponding bit in the CROMCTL3 register is set to 1. Bit: Initial value: R/W: Bit Bit Name 7 Initial Value 7 6 5 4 3 2 1 BUF_ ECC BUF_ EDC - BUF_ MD BUF_ MIN - - 0 - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R/W Description BUF_ECC 0 R Indicates that decoding and buffering have been stopped because of an error that is not correctable by using the ECC. 6 BUF_EDC 0 R Indicates that decoding and buffering have been stopped because the post-correction EDC check indicated an error. 5  R Reserved 0 This bit is always read as 0 and cannot be modified. 4 BUF_MD 0 R Indicates that decoding and buffering have been stopped because the current sector is in a mode or form differing from that of the previous sectors. 3 BUF_MIN 0 R Indicates that decoding and buffering have been stopped because a non-sequential minutes, seconds, or frames (1/75 second) value has been encountered. 2 to 0  All 0 R Reserved These bits are always read as 0 and cannot be modified. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1395 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.16 Buffer Overflow Status Register (CBUFST2) The buffer overflow status register (CBUFST2) indicates that a sector-to-sector transition occurred before data transfer to the buffer is completed. Bit: Initial value: R/W: 7 6 5 4 3 2 1 BUF_ NG - - - - - - 0 - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 BUF_NG 0 R Indicates that a sector-to-sector transition has occurred before the data transfer to the buffer is completed. This bit is set to 1 when the data of a third sector are input while data for the output stream from the CD-ROM decoder remains unread. No interrupt is generated. Once this bit has been set, its value will not recover unless it is reset by the LOGICRST bit in the ROMDECRST register. 6 to 0  All 0 R Reserved These bits are always read as 0 and cannot be modified. 26.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00) The pre-ECC correction header: minutes data register (HEAD00) indicates the minutes value in the header before ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD00[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD00 [7:0] Page 1396 of 3092 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Minutes Value in Header Before ECC Correction R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01) The pre-ECC correction header: seconds data register (HEAD01) indicates the seconds value in the header before ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD01[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD01 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Seconds Value in Header Before ECC Correction 26.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02) The pre-ECC correction header: frames (1/75 second) data register (HEAD02) indicates the frames value (1 frame = 1/75 second) in the header before ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD02[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD02 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Frames Value in Header Before ECC Correction R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1397 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03) The pre-ECC correction header: mode data register (HEAD03) indicates the mode value in the header before ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD03[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD03 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Mode value in the header before ECC correction 26.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00) The pre-ECC correction subheader: file number (byte 16) data register (SHEAD00) indicates the file number value in the subheader before ECC correction (byte 16). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD00[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD00 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Indicates file number value in the subheader before ECC correction (byte 16). For sectors not in Mode 2, this register contains the byte of data at the corresponding position. Page 1398 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01) The pre-ECC correction subheader: channel number (byte 17) data register (SHEAD01) indicates the channel number value in the subheader before ECC correction (byte 17). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD01[7:0] Initial value: R/W: 0 R Initial Value Bit Bit Name 7 to 0 SHEAD01 All 0 [7:0] 0 R 0 R 0 R 0 R R/W Description R Indicate channel number value in the subheader before ECC correction (byte 17). For sectors not in Mode 2, this register contains the byte of data at the corresponding position. 26.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02) The pre-ECC correction subheader: sub-mode (byte 18) data register (SHEAD02) indicates the sub-mode value in the subheader before ECC correction (byte 18). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD02[7:0] Initial value: R/W: Initial Value Bit Bit Name 7 to 0 SHEAD02 All 0 [7:0] 0 R 0 R 0 R 0 R 0 R R/W Description R Indicate sub-mode value in the subheader before ECC correction (byte 18). For sectors not in Mode 2, this register contains the byte of data at the corresponding position. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1399 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03) The pre-ECC correction subheader: data type (byte 19) data register (SHEAD03) indicates the data type value in the subheader before ECC correction (byte 19). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD03[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD03 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Indicate data type value in the subheader before ECC correction (byte 19). For sectors not in Mode 2, this register contains the byte of data at the corresponding position. 26.3.25 Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04) The pre-ECC correction subheader: file number (byte 20) data register (SHEAD04) indicates the file number value in the subheader before ECC correction (byte 20). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD04[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD04 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Indicate file number value in the subheader before ECC correction (byte 20). For sectors not in Mode 2, this register contains the byte of data at the corresponding position. Page 1400 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05) The pre-ECC correction subheader: channel number (byte 21) data register (SHEAD05) indicates the channel number value in the subheader before ECC correction (byte 21). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD05[7:0] Initial value: R/W: 0 R Initial Value Bit Bit Name 7 to 0 SHEAD05 All 0 [7:0] 0 R 0 R 0 R 0 R R/W Description R Indicate channel number value in the subheader before ECC correction (byte 21). For sectors not in Mode 2, this register contains the byte of data at the corresponding position. 26.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06) The pre-ECC correction subheader: sub-mode (byte 22) data register (SHEAD06) indicates the sub-mode value in the subheader before ECC correction (byte 22). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD06[7:0] Initial value: R/W: Initial Value Bit Bit Name 7 to 0 SHEAD06 All 0 [7:0] 0 R 0 R 0 R 0 R 0 R R/W Description R Sub-Mode Value in Subheader Before ECC Correction (Byte 22) For sectors not in Mode 2, this register contains the byte of data at the corresponding position. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1401 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07) The pre-ECC correction subheader: data type (byte 23) data register (SHEAD07) indicates the data type value in the subheader before ECC correction (byte 23). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD07[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD07 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Data Type Value in Subheader Before ECC Correction (Byte 23) For sectors not in Mode 2, this register contains the byte of data at the corresponding position. 26.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20) The post-ECC correction header: minutes data register (HEAD20) indicates the minutes value in the header after ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD20[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD20 [7:0] Page 1402 of 3092 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Minutes Value in Header After ECC Correction When MSF_LBA_SEL = 1, this register indicates the first byte of the total number of sectors calculated from M, S, and F. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21) The post-ECC correction header: seconds data register (HEAD21) indicates the seconds value in the header after ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD21[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD21 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Seconds Value in Header After ECC Correction When MSF_LBA_SEL = 1, this register indicates the second byte of the total number of sectors calculated from M, S, and F. 26.3.31 Post-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD22) The post-ECC correction header: frames (1/75 second) data register (HEAD22) indicates the frames value (1 frame = 1/75 seconds) in the header after ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD22[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD22 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Frames Value in Header After ECC Correction R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When MSF_LBA_SEL = 1, this register indicates the third byte of the total number of sectors calculated from M, S, and F. Page 1403 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23) The post-ECC correction header: mode data register (HEAD23) indicates the mode value in the header after ECC correction. Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R HEAD23[7:0] Initial value: R/W: Bit Bit Name 7 to 0 HEAD23 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Mode Value in Header After ECC Correction 26.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20) The post-ECC correction subheader: file number (byte 16) data register (SHEAD20) indicates the file number value in the subheader after ECC correction (byte 16). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD20[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD20 [7:0] Page 1404 of 3092 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Indicate file number value in the subheader after ECC correction (byte 16). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.34 Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21) The post-ECC correction subheader: channel number (byte 17) data register (SHEAD21) indicates the channel number value in the subheader after ECC correction (byte 17). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD21[7:0] Initial value: R/W: 0 R Initial Value Bit Bit Name 7 to 0 SHEAD21 All 0 [7:0] 0 R 0 R 0 R 0 R R/W Description R Indicate channel number value in the subheader after ECC correction (byte 17). 26.3.35 Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22) The post-ECC correction subheader: sub-mode (byte 18) data register (SHEAD22) indicates the sub-mode value in the subheader after ECC correction (byte 18). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD22[7:0] Initial value: R/W: Initial Value Bit Bit Name 7 to 0 SHEAD22 All 0 [7:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 R 0 R 0 R 0 R 0 R R/W Description R Indicates sub-mode value in the subheader after ECC correction (byte 18). Page 1405 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23) The post-ECC correction subheader: data type (byte 19) data register (SHEAD23) indicates the data type value in the subheader after ECC correction (byte 19). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD23[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD23 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Indicate data type value in the subheader after ECC correction (byte 19). 26.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24) The post-ECC correction subheader: file number (byte 20) data register (SHEAD24) indicates the file number value in the subheader after ECC correction (byte 20). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD24[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD24 [7:0] Page 1406 of 3092 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Indicate file number value in the subheader after ECC correction (byte 20). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25) The post-ECC correction subheader: channel number (byte 21) data register (SHEAD25) indicates the channel number value in the subheader after ECC correction (byte 21). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD25[7:0] Initial value: R/W: 0 R Initial Value Bit Bit Name 7 to 0 SHEAD25 All 0 [7:0] 0 R 0 R 0 R 0 R R/W Description R Indicate channel number value in the subheader after ECC correction (byte 21). 26.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26) The post-ECC correction subheader: sub-mode (byte 22) data register (SHEAD26) indicates the sub-mode value in the subheader after ECC correction (byte 22). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD26[7:0] Initial value: R/W: Initial Value Bit Bit Name 7 to 0 SHEAD26 All 0 [7:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 R 0 R 0 R 0 R 0 R R/W Description R Indicate sub-mode value in the subheader after ECC correction (byte 22). Page 1407 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27) The post-ECC correction subheader: data type (byte 23) data register (SHEAD27) indicates the data type value in the subheader after ECC correction (byte 23). Bit: 7 6 5 4 3 2 1 0 0 R 0 R 0 R SHEAD27[7:0] Initial value: R/W: Bit Bit Name 7 to 0 SHEAD27 [7:0] 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description All 0 R Data Type Value in Subheader After ECC Correction (byte 23) 26.3.41 Automatic Buffering Setting Control Register 0 (CBUFCTL0) Bit: Initial value: R/W: Bit Bit Name 7 CBUF_ AUT 7 6 5 CBUF_ AUT CBUF_ EN - 0 R/W 0 R/W 0 R/W 2 1 CBUF_MD[1:0] 4 3 CBUF_ TS CBUF_ Q - 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 Initial Value R/W Description 0 R/W Automatic Buffering Function ON/OFF When this bit is to be set or cleared while CROM_EN = 1, CBUF_EN should also be set or cleared simultaneously. Otherwise, the validity of the status indications in CBUFST0, CBUFST1 and CBUFST2 cannot be guaranteed. 0: Automatic buffering is OFF 1: Automatic buffering is ON Page 1408 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Initial Value Bit Bit Name 6 CBUF_EN 0 Section 26 CD-ROM Decoder R/W Description R/W Buffering to Buffer RAM Enable This bit turns on/off buffering in both automatic and manual buffering modes. In manual buffering mode, set this bit after generation of the ISEC interrupt. This bit is automatically reset when automatic buffering stops. 0: Buffering is OFF 1: Buffering is ON 5  0 R/W Reserved This bit is always read as 0.The write value should always be 0. 4, 3 CBUF_MD 00 [1:0] R/W Start-sector detection mode when the automatic buffering function is in use 00: The header values for the previous and current sectors must be in sequence. 01: The header value detected in the current sector must be in sequence with the interpolated value. 10: A current sector with any header value is OK. 11: Start-sector detection is based on the interpolated value even if the current sector is not detected. 2 CBUF_TS 1 R/W CBUFCTL1 to CBUFCTL3 Setting Mode 0: CBUFCTL1 to CBUFCTL3: BCD (in decimal) 1: Total number of sectors (in hexadecimal) 1 CBUF_Q 0 R/W Q-channel code buffering data specification in the case of a CRC error in the Q-channel code 0: The values for the last sector for which the CRC returned a correct result are buffered. 1: The erroneous data is buffered as is. Note: Since subcodes are not input with this LSI, always set this bit to 1. 0  0 R/W Reserved This bit is always read as 0.The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1409 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1) The automatic buffering start sector setting: minutes control register (CBUFCTL1) indicates the minutes value in the header for the first sector to be buffered. Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W BS_MIN[7:0] Initial value: R/W: Bit Bit Name 7 to 0 BS_MIN [7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Indicate setting of the minutes value in the header for the first sector to be buffered. 26.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2) The automatic buffering start sector setting: seconds control register (CBUFCTL2) indicates the seconds value in the header for the first sector to be buffered. Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W BS_SEC[7:0] Initial value: R/W: Bit Bit Name 7 to 0 BS_SEC [7:0] Page 1410 of 3092 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Indicate setting of the seconds value in the header for the first sector to be buffered. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3) The automatic buffering start sector setting: frames control register (CBUFCTL3) indicates the frames (1 frame = 1/75 second) value in the header for the first sector to be buffered Bit: 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W BS_FRM[7:0] Initial value: R/W: Bit Bit Name 7 to 0 BS_FRM [7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Indicate setting of the frames (1/75 second) value in the header for the first sector to be buffered. 26.3.45 ISY Interrupt Source Mask Control Register (CROMST0M) The ISY interrupt source mask control register (CROMST0M) masks the ISY interrupt sources specified by the bits in CROMST0. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - ST_ SYILM ST_ SYNOM ST_ BLKSM ST_ BLKLM ST_ SECSM ST_ SECLM 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7, 6  All 0 R/W Reserved These bits are always read as 0.The write value should always be 0. 5 ST_SYILM 0 R/W ISY interrupt ST_SYIL (bit 5 in the CROMST0 register) source mask 4 ST_ SYNOM 0 R/W ISY interrupt ST_SYNO (bit 4 in the CROMST0 register) source mask 3 ST_ BLKSM 0 R/W ISY interrupt ST_BLKS (bit 3 in the CROMST0 register) source mask R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1411 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name 2 Initial Value R/W Description ST_BLKLM 0 R/W ISY interrupt ST_BLKL (bit 2 in the CROMST0 register) source mask 1 ST_ SECSM 0 R/W ISY interrupt ST_SECS (bit 1 in the CROMST0 register) source mask 0 ST_ SECLM 0 R/W ISY interrupt ST_SECL (bit 0 in the CROMST0 register) source mask 26.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST) The CD-ROM decoder reset control register (ROMDECRST) resets the random logic of the CDROM decoder and clears the RAM in the CD-ROM decoder. Bit: Initial value: R/W: Initial Value Bit Bit Name 7 LOGICRST 0 7 6 5 4 3 2 1 LOGI CRST RAM RST - - - - - 0 - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W CD-ROM Decoder Random Logic Reset Signal A reset signal is output while this bit is set to 1. 6 RAMRST 0 R/W CD-ROM Decoder RAM Clearing Signal Refer to the RAMCLRST bit in the RSTSTAT register to confirm that RAM clearing is complete. 5 to 0  All 0 R/W Reserved These bits are always read as 0.The write value should always be 0. Note: Before setting LOGICRST to 1, make sure that the RAMRST bit is cleared to 0 and then write B'10000000 to this register. Page 1412 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) The CD-ROM decoder reset status register (RSTSTAT) indicates that the RAM in the CD-ROM decoder has been cleared. Bit: Initial value: R/W: Bit Bit Name 7 6 to 0 7 6 5 4 3 2 1 RAM CLRST - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial Value 0 R/W Description RAMCLRST 0 R This bit is set to 1 on completion of RAM clearing after the RAMRST bit in ROMDECRST is set to 1. The bit is cleared by writing a 0 to the RAMRST bit.  R All 0 Reserved These bits are always read as 0 and cannot be modified. 26.3.48 Serial Sound Interface Data Control Register (SSI) The serial sound interface data control register (SSI) provides various settings related to the data stream. For the operation corresponding to the setting of this register, refer to section 26.4.1, Endian Conversion for Data in the Input Stream. Bit: 7 6 BYTEND BITEND Initial value: R/W: 0 R/W 0 R/W 5 4 BUFEND0[1:0] 0 R/W 1 R/W 3 2 BUFEND1[1:0] 1 R/W 0 R/W 1 0 - - 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 BYTEND 0 R/W Specifies the endian of input data from the serial sound interface. When this bit is set to 1, byte 0 and byte 1 in STRMDIN0 are swapped. This is the same for STRMDIN2. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1413 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Bit Bit Name Initial Value R/W Description 6 BITEND 0 R/W Specifies treatment of the bit order of the input data from the serial sound interface. When this bit is set to 1, the bits within each byte are rearranged to place them in reverse order, bit 0  bit 7 to bit 7  bit 0. 5, 4 BUFEND0 01 [1:0] R/W These bits select whether to change the order of 16-bit units of data transferred from the serial sound interface or suppress the stream data. In the serial sound interface, either “padding mode” or “non-padding mode” is selectable. In non-padding mode, each 32 bits of data transferred from the serial sound interface are CD-ROM data. Since the CD-ROM decoder has two 16-bit input data registers, the order of the 16-bit data can be swapped within the 32 bits. On the other hand, in padding mode each 32 bits of data transferred from the serial sound interface includes padding. Since the padding is without meaning, it should be kept out of the input stream to the decoder. This suppression can be specified by the setting of this register. The CD-ROM decoder handles data as a stream of 16bit data, and this register controls which 16-bit portion of each 32 bits of data transferred from the serial sound interface should be input first. 00: The 16 bits of stream data that would otherwise be processed first is discarded. 01: The higher-order 16 bits of each 32 bits of data received from the serial sound interface are placed first in the stream to the decoder. 10: The lower-order 16 bits of each 32 bits of data received from the serial sound interface are placed first in the stream to the decoder. 11: Setting prohibited Page 1414 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Initial Value Bit Bit Name 3, 2 BUFEND1 10 [1:0] Section 26 CD-ROM Decoder R/W Description R/W These bits select whether to change the order of 16-bit units of data transferred from the serial sound interface or suppress the stream data. In the serial sound interface, either “padding mode” or “non-padding mode” is selectable. In non-padding mode, each 32 bits of data transferred from the serial sound interface are CD-ROM data. Since the CD-ROM decoder has two 16-bit input data registers, the order of the 16-bit data can be swapped within the 32 bits. On the other hand, in padding mode each 32 bits of data transferred from the serial sound interface includes padding. Since the padding is without meaning, it should be kept out of the input stream to the decoder. This suppression can be specified by the setting of this register. The CD-ROM decoder handles data as a stream of 16bit data, and this register controls which 16-bit portion of each 32 bits of data transferred from the serial sound interface should be input second. 00: The 16 bits of stream data that would otherwise be processed second is discarded. 01: The higher-order 16 bits of each 32 bits of data received from the serial sound interface are placed second in the stream to the decoder. 10: The higher-order 16 bits of each 32 bits of data received from the serial sound interface are placed second in the stream to the decoder. 11: Setting prohibited 1, 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1415 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.49 Interrupt Flag Register (INTHOLD) The interrupt flag register (INTHOLD) consists of various interrupt flags. Bit: Initial value: R/W: 7 6 5 4 ISEC ITARG ISY IERR IBUF IREADY 3 2 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 ISEC 0 R/W ISEC Interrupt Flag 1 0 - - 0 R/W 0 R/W Writing 0 to this bit is only possible after 1 has been read from it. 6 ITARG 0 R/W ITARG Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 5 ISY 0 R/W ISY Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 4 IERR 0 R/W IERR Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 3 IBUF 0 R/W IBUF Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 2 IREADY 0 R/W IREADY Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 1, 0  All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Page 1416 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.50 Interrupt Source Mask Control Register (INHINT) The interrupt source mask control register (INHINT) controls masking of various interrupt requests in the CD-ROM decoder. Bit: Initial value: R/W: 7 6 5 4 INH ISEC INH ITARG INH ISY INH IERR INH INH PREINH PREINH IBUF IREADY REQDM IREADY 3 2 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 INHISEC 0 R/W ISEC Interrupt Mask 1 0 R/W 0 0 R/W When set to 1, inhibits ISEC interrupt requests 6 INHITARG 0 R/W ITARG Interrupt Mask When set to 1, inhibits ITARG interrupt requests 5 INHISY 0 R/W ISY Interrupt Mask When set to 1, inhibits ISY interrupt requests 4 INHIERR 0 R/W IERR Interrupt Mask When set to 1, inhibits IERR interrupt requests 3 INHIBUF 0 R/W IBUF Interrupt Mask When set to 1, inhibits IBUF interrupt requests 2 INHIREADY 0 R/W IREADY Interrupt Mask When set to 1, inhibits IREADY interrupt requests 1 PREINH REQDM 0 R/W Inhibits setting of the DMA-transfer-request interrupt source flag for the output data stream. When this bit is set to 1, the DMA-transfer-request interrupt source is not retained. 0 PREINH IREADY 0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R/W Inhibits setting of the IREADY interrupt flag. When this bit is set to 1, the IREADY interrupt source not retained. Page 1417 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.51 CD-ROM Decoder Stream Data Input Register (STRMDIN0) The CD-ROM decoder stream data input register (STRDMIN0) holds the higher 2 bytes (from MSB) of the 4 bytes of data that is to be input to the CD-ROM decoder. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W STRMDIN[31:16] Initial value: R/W: 0 R/W 0 R/W Bit Bit Name 15 to 0 STRMDIN [31:16] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Indicate the higher 2 bytes (from MSB) of the 4-bytes of data that is to be input to the CD-ROM decoder. The CD-ROM decoder has a 4-byte wide data window as a data input register to handle the data input to this register as a stream data. The amount of data for one sector is 2352 bytes. 26.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN2) The CD-ROM decoder stream data input register (STRDMIN2) holds the lower 2 bytes (from LSB) of the 4 bytes of data that is to be input to the CD-ROM decoder. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W STRMDIN[15:0] Initial value: R/W: 0 R/W 0 R/W Bit Bit Name 15 to 0 STRMDIN [15:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Indicate the lower 2 bytes (from LSB) of the 4-bytes of data that is to be input to the CD-ROM decoder. The CD-ROM decoder has a 4-byte wide data window as a data input register to handle the data input to this register as a stream data. The amount of data for one sector is 2352 bytes. Page 1418 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.3.53 CD-ROM Decoder Stream Data Output Register (STRMDOUT0) The CD-ROM decoder stream data output register (STRMDOUT0) holds 2 bytes that is to be output from the CD-ROM decoder. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R STRMDOUT[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R Initial Value Bit Bit Name 15 to 0 STRMDOUT H'0000 [15:0] 0 R 0 R 0 R 0 R 0 R R/W Description R Indicate 2 bytes that are to be output from the CD-ROM decoder. The CD-ROM decoder has a 2-byte wide data window or set of registers for the output of decoded data. Every time the relevant register is accessed, further data of access size are output sequentially in the output format that is separately defined. The amount of data for one sector is 2768 bytes. Always read 2768 bytes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1419 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.4 Operation 26.4.1 Endian Conversion for Data in the Input Stream Stream data must be input to the core of the CD-ROM decoder in order according to the CD-ROM data format specifications. In some systems, however, the order of the data from the serial sound interface may have to be changed or the data will have been padded before transfer. To cope with this, the stream data input control section is capable of swapping the order of the data and preventing the input of padding data to the core of the CD-ROM decoder. These functions are controlled through the serial sound interface data control register (SSI). Figure 26.6 shows a case where the upper and lower 16 bits of the data, consisting of padding data plus the first 2 bytes of sync code, that is, H'000000FF, are swapped (H'00FF0000) and input to the CD-ROM decoder as the stream data. BUFEND0[1:0] = 01 H'00FF H'00FF H'00 H'FF STRMDIN0 H'00FF Core of CD-ROM decoder H'00 H'00 STRMDIN2 H'0000 BUFEND1[1:0] = 00 BYTEND = 0 Figure 26.6 Example of Padded Stream Data Control by the SSI Register Page 1420 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Figure 26.7 shows a case of input stream data that has no padding (H'12345678). The upper and lower 16 bits of data are swapped (H'56781234) for input to the CD-ROM decoder. BUFEND0[1:0] = 10 H'78 STRMDIN0 H'1234 is input first. H'5678 is input next. H'1234 H'56 H'5678 H'1234 H'5678 Core of CD-ROM decoder H'34 STRMDIN2 H'012 H'5678 H'1234 BUFEND1[1:0] = 01 BYTEND = 0 Figure 26.7 Example of Non-Padded Stream Data Control by the SSI Register 26.4.2 Sync Code Maintenance Function Each sector of CD-ROM data consists of 2352 bytes starting with H'00FFFFFFFFFFFFFFFFFFFF00 (sync code). However, a scratch on the disc or some other factor might lead to erroneous recognition of the sync code sequence at the wrong time. Conversely, a sync code might not be detected at a point where it should be detected. As a solution to these problems, the CD-ROM decoder of this LSI has a sync-code maintenance function, which operates to ignore sync codes detected at abnormal times and maintain the appearance of the sync code at the expected times when it is not actually detected on the disc. The operating modes of the sync-code maintenance function are listed below. For details on the settings, refer to section 26.3.2, Sync Code-Based Synchronization Control Register (CROMSY0), and table 26.2.     Automatic sync maintenance mode External sync mode Interpolated sync mode Interpolated sync plus external sync mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1421 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder (1) Automatic Sync Maintenance Mode In automatic sync maintenance mode, the sync code is ignored if detected within the one-sector (2352-byte) period. Furthermore, if a sync code is not detected at the point where a next sector should start, sync code maintenance is applied. If synchronization timing has changed, resynchronization is performed at the point where a sync code is detected within 2352 bytes after the change. Therefore, this mode is effective in rejecting abnormal sync patterns and following changes in synchronization timing. Note, however, that this mode cannot achieve synchronization with the first sector after a change to the synchronization timing. Figure 26.8 shows operation in the case of normal sync-code detection, figure 26.9 shows a case where a sync code is detected before a current one-sector period has elapsed, and figure 26.10 shows the case where the actual sync code is only detected some time after a full one-sector period has elapsed. Input data Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6 Sync code detection Output data Sector 1 Sector 2 Sector 3 Sector 4 Sector 6 Figure 26.8 Operation in Automatic Sync Maintenance Mode (Normal Timing) Abnormal sector Input data Sector 1 Sector 3 Sector 4 Sector 5 Sector 6 Sync code detection Re-synchronization Ignore Output data Maintain Ignore Maintain Sector 1 Sector 5 Abnormal sector Abnormal Abnormal sector sector Figure 26.9 Operation in Automatic Sync Maintenance Mode (When an Abnormally Short Sector is Encountered) Page 1422 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder Abnormal sector Input data Sector 1 Sector 3 Sector 4 Sector 5 Sync code detection Maintain Ignore Maintain Re-synchronization Sector 1 Output data Sector 4 Abnormal sector Abnormal sector Figure 26.10 Operation in Automatic Sync Maintenance Mode (When an Abnormally Long Sector is Encountered) (2) External Sync Mode In external sync mode, synchronization is always based on the sync codes in the incoming data. Even if the next sync code is not detected at the 2352nd byte, decoding does not proceed until the next sync code is detected. Accordingly, this mode is effective in that it strictly follows the external synchronization timing. Note, however, that decoding will not be performed normally when the sync-code pattern is input with abnormal timing. Figure 26.11 shows the operation in external sync mode. Input data Sync code detection Abnormal sector Sector 1 Output data Sector 3 Sector 1 Sector 4 Sector 3 Sector 5 Sector 4 Abnormal sector Figure 26.11 Operation in External Sync Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1423 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder (3) Interpolated Sync Mode In interpolated sync mode, synchronization is always driven by the internal counter after a sync code pattern has been detected at the start of decoding. Accordingly, this mode is effective when the sync patterns have been damaged. However, decoding becomes incorrect after a change to the synchronization timing, since the change in timing is not followed. Figure 26.12 shows the operation in interpolated sync mode. Abnormal sector Input data Sector 1 Sector 3 Sector 4 Sector 5 Sync code detection Maintain Ignore Maintain Ignore Maintain Ignore Maintain Sector 1 Output data Abnormal sector Abnormal sector Abnormal sector Abnormal sector Figure 26.12 Operation in Interpolated Sync Mode Page 1424 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 26 CD-ROM Decoder Interpolated Sync Plus External Sync Mode In interpolated sync plus external sync mode, synchronization is based on the detected sync code patterns as long as they are present, and if a sync pattern is not detected at the 2352nd byte, the sync code maintenance is applied. Synchronization in this mode is more quickly responsive to changes in synchronization timing than synchronization in the automatic sync maintenance mode. However, decoding still becomes incorrect when a sync pattern is input with abnormal timing. Figures 26.13 and 26.14 show the operation in interpolated sync plus external sync mode in the cases of abnormally short and long sectors, respectively. Abnormal sector Sector 1 Input data Sector 3 Sector 4 Sector 5 Sector 6 Sync code detection Maintain Output data Sector 1 Sector 3 Sector 4 Sector 5 Abnormal sector Figure 26.13 Operation in Interpolated Sync Plus External Sync Mode (When an Abnormally Short Sector is Encountered) Abnormal sector Sector 1 Input data Sector 3 Sector 4 Sector 5 Sync code detection Maintain Output data Sector 1 Sector 3 Abnormal sector Sector 4 Abnormal sector Figure 26.14 Operation in Interpolated Sync Plus External Sync Mode (When an Abnormally Long Sector is Encountered) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1425 of 3092 Section 26 CD-ROM Decoder 26.4.3 SH7268 Group, SH7269 Group Error Correction The CD-ROM decoder handles data in the formats containing information relevant to error correction, including the EDC, P parity, and Q parity. The CD-ROM decoder includes the following functions for use in error correction.  Syndrome calculation  ECC correction  EDC checking (1) Syndrome Calculation After the data of a sector in Mode 1 or Form 1 of Mode 2 has been input, the ECC is used in correction if any error is detected (the result of syndrome calculation is non-zero). After correction, the results of syndrome operation for the corrected data are output to bits ST_ECCP (P parity) and ST_ECCQ (Q parity) in the CROMST6 register, respectively. (2) ECC correction and EDC Checking For CD-ROM format data that contains EDC, P-parity, and Q-parity fields, the CD-ROM decoder performs EDC checking and ECC correction. Supported correction modes are P correction, Q correction, PQ correction (P correction followed by Q correction), and QP correction (Q correction followed by P correction). In PQ and QP correction modes, up to three iterations of correction are possible (the number of iterations is limited by the playback speed). The EDC check is performed twice, before and after correction. The mode of ECC correction and EDC checking is specified by bits MD_DEC[2:0] in the CROMCTL1 register. When the PQ or QP correction mode is selected, the number of iterations is specified by bits MD_PQREP[1:0] in the CROMCTL1 register. When the automatic mode/form detection function is in use, the sector mode determines whether or not ECC correction and EDC checking can be performed. For sectors in Mode 0 and Mode 2 (non-XA), which include neither parity bits nor EDC, ECC correction and EDC checking are not performed. For sectors in Form 2 of Mode 2, ECC correction is not performed. (a) ECC Correction When ECC correction is in use and an error in a sector is identified as non-correctable, the CDROM decoder generates an IERR interrupt and sets the ST_ECCNG bit of the CROMST6 register to 1. The CD-ROM detector also sets this bit to 1 on detecting a short sector. Page 1426 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder While the NO_ECC bit of the CROMCTL4 register is set to 1, a ‘pass’ result in pre-correction EDC checking makes the CD-ROM decoder skip ECC correction, regardless of the results of the syndrome operation. (b) EDC Checking When EDC checking is in use, checking is in line with the specified or detected sector mode and form, depending on whether or not automatic sector mode and form detection is selected. The results of EDC checking before and after correction are reflected in the ST_EDC1 and ST_EDC2 bits of the CROMST6 register, respectively. If EDC checking after ECC correction indicates that an error remains, an IERR interrupt is generated. 26.4.4 Automatic Decoding Stop Function Decoding can be stopped automatically in response to an error during the decoding of CD-ROM data. The possible conditions for automatically stopping the decoding process are listed below. The applicable conditions are specified in the CROMCTL3 register.     An error is found to be not correctable by ECC correction. Post-correction EDC checking indicates that an error remains. A change of the sector mode or form. A non-sequential MSF (minutes, seconds, frames (1/75 second)) value. When automatic stopping is set up and any of the above conditions is encountered in a certain sector, the decoding is stopped after the results of decoding for that sector have been output. After decoding has been stopped in response to a condition specified in the CROMCTL3 register, the condition can be identified by reading the CBUFST1 register. The CD-ROM decoder has buffer space for two sectors. If input of the data stream continues and the output stream of data is not read, the CD-ROM decoder stops at the point where the data of a third sector starts to be input. At this time, the BUF_NG bit in the CBUFST2 register is set to 1, but no interrupt is generated. Once the BUF_NG bit in the CBUFST2 register has been set to 1, recovery can only be accomplished by using the LOGICRST bit in the ROMDECRST register to reset the CD-ROM decoder function. When the LOGICRST bit in the ROMDECRST register is set to 1, a reset signal is output and any registers in which settings have been made are cleared to their initial values. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1427 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.4.5 Buffering Format Figure 26.15 shows the format of the output data stream produced by CD-ROM decoding. 2768 bytes A 2-byte-wide window register STRMDOUT0 is provided for the output. When this window register is accessed after decoding of a CD-ROM sector has finished, the bytes of data are output in order from the sync code. Sync code 12 bytes Header 4 bytes Subheader 8 bytes Data 2048 bytes EDC 4 bytes ECC 276 bytes Erasure 294 bytes H'00 Block error Reserved 2 bytes 108 bytes H'0000 2 bytes H'0000 2 bytes Status (See next page) 2 bytes H'0000 2 bytes Reserved 2 bytes Storage flag 2 bytes Figure 26.15 Output Data Stream Format Page 1428 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder The meanings of bits in the two-byte status field shown in figure 26.15 are given below. The values of the non-assigned bits are undefined. Status 15 14 13 PERR QERR EDCE 12 11 10 9 8 7 6 — — — — — SD SY 5 4 3 FM[2:0] 2 1 0 HD — — [Legend] PERR: Indicates that a P-parity error remains. QERR: Indicates that a Q-parity error remains. EDCE: Indicates that a remaining error was detected in post-correction EDC checking. SD: Indicates that a short sector was encountered SY: Indicates that a sync code was interpolated. FM: Indicates the data format 001: Mode 0 010: Mode 1 011: Long (format with no EDC and ECC) 100: Mode 2 (non-XA) 101: Mode 2 Form 1 110: Mode 2 Form 2 HD: Header continuity (minutes, seconds, and frames (1/75) are non-sequential) The value of the storage flag field in figure 26.15 is incremented every time the data for one sector are output. The value starts at H'0000 and wraps back around to H'0000 after incrementation reaches H'FFFF. Note that the upper byte and lower byte in the storage flag are swapped. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1429 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.4.6 Target-Sector Buffering Function In the CD-ROM decoder, the sector for output can be designated in two ways: automatic buffering, where the CD-ROM decoder itself detects the presence of target sectors, and manual buffering, where the target sector for output is designated by software and the software also recognizes the sectors buffered in the CD-ROM decoder. The following describes the procedures for setting the registers in the CD-ROM decoder to set up automatic or manual buffering. (1) Setting Up Automatic Buffering Figure 26.16 shows an example of setting up the automatic buffering. Set the relevant CD-ROM decoder registers and start input of the data stream; the CD-ROM decoder then detects the target sector and starts the output of the stream data. Start of automatic buffering setup Set both the CBUF_AUT and CBUF_EN bits in CBUFCTL0 to 1 [1] Set CBUFCTL1 [2] [1] Turn on the automatic buffering function and enable buffering in the buffer RAM. [2] Set the minutes value of the target sector. [3] Set the seconds value of the target sector. [4] Set the frame value of the target sector. Set CBUFCTL2 [3] [5] Enable subcode processing and CD-ROM decoding. Set CBUFCTL3 [4] Set both the SUBC_EN and CROM_EN bits in CROMEN to 1 [5] End of automatic buffering setup Figure 26.16 Example of Setting Up Automatic Buffering Page 1430 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 26 CD-ROM Decoder Setting Up Manual Buffering Figure 26.17 shows an example of setting up manual buffering. Each time an ISEC interrupt is generated, the software checks whether or not the sector is the target sector and starts buffering when the target sector is found. Start of automatic buffering setup Clear both the CBUF_AUT and CBUF_EN bits in CBUFCTL0 to 0 [1] [1] Turn off the automatic buffering function and disable buffering in the buffer RAM. [2] Enable subcode processing and CD-ROM decoding. Set both the CBUF_AUT and CBUF_EN bits in CBUFCTL0 to 1 [2] Generation of an ISEC interrupt [3] [3] Start input of the data stream. Read HEAD02, etc. Target sector? No Yes Set the CBUF_EN bit in CBUFCTL0 to 1 End of automatic buffering setup Figure 26.17 Example of Setting Up Manual Buffering R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1431 of 3092 Section 26 CD-ROM Decoder 26.5 Interrupt Sources 26.5.1 Interrupt and DMA Transfer Request Signals SH7268 Group, SH7269 Group Table 26.3 lists the interrupt signals and DMA transfer request signal generated by the CD-ROM decoder, along with the meanings and the modules to which the signals are connected. Table 26.3 Interrupt and DMA Transfer Request Signals Name Condition Connected To ISEC Transitions from sector to sector Interrupt controller ITARG Access to a CD-ROM sector that is not the expected target sector Interrupt controller ISY A sync code from the CD-ROM with abnormal timing Interrupt controller IERR An error that was not correctable by ECC correction or an error indicated by EDC checking after ECC correction Interrupt controller IBUF State changes in data transfer to the buffer Interrupt controller IREADY Request for data transfer to the buffer for CD-ROM Interrupt controller DMA transfer request Request for data transfer to the buffer for CD-ROM Direct memory access controller (1) ISEC Interrupt This interrupt is generated when the sync code indicates a transition from sector to sector. (2) ITARG Interrupt This interrupt is generated when the stream data transferred from the CD-DSP is not the data of the target sector. The CD-ROM decoder checks the time data in the subcode. In correct operation, data transfer is expected to start slightly before the target sector. An ITARG interrupt is generated in the following cases.  When data of a sector preceding the target sector by quite a few sectors have been transferred  When data of a sector that comes after the target sector have been transferred For the generation of this interrupt, ITARG is detected from the subcode. However, this interrupt has no meaning in this LSI because CD-ROM data are transferred from the serial sound interface. Page 1432 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 26 CD-ROM Decoder ISY Interrupt This interrupt can be generated in the following cases.  When a sync code was detected at a position where the value in the word counter (counter for checking sync code intervals) was not correct and the sync code was ignored  When a sync code has not been detected although the word counter has reached the final value and a sync code has been interpolated (for sync maintenance)  When a sync code was detected at a position where the value in the word counter (counter for checking sync code intervals) was not correct and the sync code was used in resynchronization  When a sync code has not been detected although the word counter has reached the final value, so the period taken up by the sector has been prolonged  When the sector has been processed as a short sector with the aid of interpolated sync codes  When the sector has been processed as a long sector with the aid of interpolated sync codes (4) IERR Interrupt This interrupt is generated in the following cases.  When ECC correction was incapable of correcting an error  When ECC correction was OK but the subsequent EDC check indicated an error (5) IBUF Interrupt This interrupt is generated when the following transitions occur.  Data transfer to the buffer  Data transfer complete (searching for data for the next transfer)  Data for transfer to the buffer are being searched for  Data transfer started (6) IREADY Interrupt This interrupt is generated when decoding of data for one sector is completed. This interrupt should be used to start the CPU buffering stream data for output to SDRAM. (7) DMA Transfer Request The source of direct memory access controller activation is the same as that of IREADY. An interrupt request is generated when output stream data for one sector becomes ready, and after the 2768 bytes of data shown in figure 26.15 have been transferred, the request signal is negated once. This is because a certain amount of time is required before the output data for the next sector is ready, so the transfer request from the direct memory access controller should be turned off between transfers. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1433 of 3092 Section 26 CD-ROM Decoder 26.5.2 SH7268 Group, SH7269 Group Timing of Status Registers Updates The status information registers of the CD-ROM decoder are updated on each ISEC interrupt. The sector for which information is reflected in the status registers is selected by the ER0SEL bit of the CROMCTL4 register. 26.6 Usage Notes 26.6.1 Stopping and Resuming Buffering Alone during Decoding When the data of the output stream are being not read out but operation of the CD-ROM decoder has continued until the buffers are full, the BUF_NG bit in the CBUFST2 register is set to 1; after that, the CD-ROM decoder becomes incapable of operation. To stop buffering alone, clear the CBUF_EN bit in the CBUFCTL0 register to 0. If the automatic buffering function is in use, clear the CBUF_AUT in the CBUFCTL0 register to 0 at the same time. In this case, the sectors currently in the buffers must be read out. To resume automatic buffering, set the CBUF_AUT and CBUF_EN bits in the CBUFCTL0 register at the same time. 26.6.2 When CROMST0 Status Register Bits are Set 1. When the ST_SECS bit in the CROMST0 register becomes set, stop decoding immediately and retry from one sector before the sector that was being decoded. 2. When the ST_SECL bit in the CROMST0 register becomes set, stop decoding immediately and retry from two sectors before the sector that was being decoded. Page 1434 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 26.6.3 Section 26 CD-ROM Decoder Link Blocks The CD-ROM decoder uses the header information before ECC correction to detect link blocks. Accordingly, an input data stream that contains an error may be erroneously detected as a link block. To prevent this, the following measures should be implemented in software.  During buffering (BUF_ACT = 1 in the CBUFST0 register), check the LINK_OUT1 bit in the CROMST5 register on each ISEC interrupt. If it is set to 1, check to see if an IERR interrupt has also occurred; if an IERR interrupt has not occurred, save the MFS values from the HEAD20 to HEAD23 registers. If an IERR interrupt has occurred, do not save the MSF values.  Perform the following processing for seven sectors (indicated by ISEC being generated seven times) after finding that the LINK_OUT1 bit has been set to 1. In either of cases 1 and 2 below, 1. LINK_ON = 1 (in the CROMST5 register) is confirmed at each ISEC interrupt, and LINK_ON = 1 is detected again within the subsequent two-sector period 2. LINK_ON = 1 was not detected at any ISEC interrupt Forcibly stop decoding, set the CROMSY0 register to place the decoder in external sync mode, and retry decoding by specifying the MSF value stored above + 7 as the MSF value for the target sector. The start sector address will be the address where RUN_OUT is stored + 7. 26.6.4 Stopping and Resuming CD-DSP Operation When stopping and resuming the stream data input to the CD-ROM decoder, note that the input data stream does not stop immediately before a sync code and that the CD-ROM decoder may recognize the data as incorrect when the input stream is resumed. This happens because the system holds a combination of the data up to the point where input was stopped and data that is input from the point of resumption. Take care on this point when stopping and resuming input. 26.6.5 Note on Clearing the IREADY Flag To clear the IREADY flag to 0 in interrupt processing etc., be sure to read one sector of data (2768 bytes) beforehand. If the IREADY flag is cleared to 0 before reading of one sector of data is complete, decoding of the subsequent sectors will not be possible. For recovery from this situation, write 1 to the LOGICRST bit in the CD-ROM decoder reset control register (ROMDECRST), and then clear the bit to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1435 of 3092 SH7268 Group, SH7269 Group Section 26 CD-ROM Decoder 26.6.6 Note on Stream Data Transfer (1) When reading of the stream data is slower than writing of the stream data, the buffer of the CDROM decoder will overflow. This causes the CD-ROM decoder to be abnormally stopped. Caution is required in writing and reading of the stream data. Sample combinations of stream data transfer settings are shown below. Table 26.4 Sample Combinations of Stream Data Transfer Settings Stream Input Stream Output LW/cycle-stealing transfer by direct memory access controller (without padding) (1) 16-byte/cycle-stealing transfer by direct memory access controller (16 bytes*) LW/cycle-stealing transfer by direct memory access controller (with padding) (1) Cycle-stealing transfer by direct memory access controller (16 bytes*, longword) LW write by CPU (1) Cycle-stealing transfer by direct memory access controller (16 bytes*, longword, word) (2) Burst transfer by direct memory access controller (16 bytes*, longword, word) (2) Burst transfer by direct memory access controller (16 bytes*, longword, word) (2) Burst transfer by direct memory access controller (16 bytes*, longword, word) Note: 26.6.7 * Set bit 25 in the DMA channel control register (CHCR_n) to 1, as well as making the regular settings for 16-byte transfer. Note on Stream Data Transfer (2) When reading the stream data, be sure to use either the direct memory access controller or the CPU. If both the direct memory access controller and the CPU are used for reading, the stream data may not be recognized as being in the CD-ROM format. Page 1436 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 27 A/D Converter Section 27 A/D Converter This LSI includes a 10-bit successive-approximation A/D converter allowing selection of up to eight analog input channels. 27.1           Features Resolution: 10 bits Input channels: six channels in the SH7268 Group and eight channels in the SH7269 Group Minimum conversion time: 6.0 s per channel Absolute accuracy: 5 LSB Operating modes: Three  Single mode: A/D conversion on one channel  Multi mode: A/D conversion on one to four channels or on one to eight channels (six channels in the SH7268 Group)  Scan mode: Continuous A/D conversion on one to four channels or on one to eight channels (six channels in the SH7268 Group) Data registers: Eight Conversion results are held in a 16-bit data register for each channel Sample-and-hold function A/D conversion start methods: Three  Software  Conversion start trigger from the multi-function timer pulse unit 2  External trigger signal Interrupt source An A/D conversion end interrupt (ADI) request can be generated on completion of A/D conversion. Module standby mode can be set R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1437 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter Bus interface Figure 27.1 shows a block diagram of the A/D converter. AN0* AN1* AN2* AN3* AN4* AN5* AN6 AN7 + – Peripheral bus ADCSR ADDRH ADDRF ADDRG ADDRE ADDRD ADDRB 10-bit D/A ADDRC AVSS Analog multiplexer AVref ADDRA AVCC Successiveapproximation register Module data bus Control circuit Comparator ADTRG, conversion start trigger from multi-function timer pulse unit 2 Sample-and-hold circuit ADI interrupt signal A/D converter [Legend] ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D ADDRE: A/D data register E ADDRF: A/D data register F ADDRG: A/D data register G ADDRH: A/D data register H Note: * Only AN0 to AN5 can be used in the SH7268 Group. Figure 27.1 Block Diagram of A/D Converter Page 1438 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.2 Section 27 A/D Converter Input/Output Pins Table 27.1 shows the A/D converter pins. Table 27.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVcc Input Analog power supply pin Analog ground pin AVss Input Analog ground pin and A/D conversion reference ground Analog reference voltage pin AVref Input A/D converter reference voltage pin Analog input pin 0* AN0 Input Analog input Analog input pin 1* AN1 Input Analog input pin 2* AN2 Input Analog input pin 3* AN3 Input Analog input pin 4* AN4 Input Analog input pin 5* AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input A/D external trigger input pin ADTRG Input Note: * External trigger input to start A/D conversion Only analog input pins 0 to 5 (AN0 to AN5) can be used in the SH7268 Group. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1439 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter 27.3 Register Descriptions The A/D converter has the following registers. Table 27.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size A/D data register A ADDRA R H'0000 H'E8005800 16 A/D data register B ADDRB R H'0000 H'E8005802 16 A/D data register C ADDRC R H'0000 H'E8005804 16 A/D data register D ADDRD R H'0000 H'E8005806 16 A/D data register E ADDRE R H'0000 H'E8005808 16 A/D data register F ADDRF R H'0000 H'E800580A 16 A/D data register G ADDRG R H'0000 H'E800580C 16 A/D data register H ADDRH R H'0000 H'E800580E 16 A/D control/status register ADCSR R/W H'0000 H'E8005820 16 Page 1440 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.3.1 Section 27 A/D Converter A/D Data Registers A to H (ADDRA to ADDRH) The sixteen A/D data registers, ADDRA to ADDRH, are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15 to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0. Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units. Table 27.3 indicates the pairings of analog input channels and ADDR. Bit: 15 14 13 12 11 10 9 8 7 6 5 - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 6  5 to 0 Initial Value R/W Description All 0 R Bit data (10 bits) All 0 R Reserved 4 3 2 1 0 These bits are always read as 0. The write value should always be 0. Table 27.3 Analog Input Channels and ADDR Analog Input Channel A/D Data Register where Conversion Result is Stored AN0* ADDRA AN1* ADDRB AN2* ADDRC AN3* ADDRD AN4* ADDRE AN5* ADDRF AN6 ADDRG AN7 ADDRH Note: * Only AN0 to AN5 can be used in the SH7268 Group. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1441 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter 27.3.2 A/D Control/Status Register (ADCSR) ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter, and enables or disables starting of A/D conversion by external trigger input. Bit: 15 14 13 ADIE ADST Initial value: 0 0 R/W:R/(W)*1 R/W 0 R/W ADF 12 11 10 9 8 TRGS[3:0] 0 R/W 0 R/W 0 R/W 7 6 5 CKS[2:0] 0 R/W 0 R/W 0 R/W 4 3 2 MDS[2:0] 0 R/W 0 R/W 0 R/W 1 0 CH[2:0] 0 R/W 0 R/W 0 R/W 0 R/W Note: *1 Only 0 can be written to clear the flag after 1 is read. Bit 15 Bit Name ADF Initial Value 0 R/W Description 1 R/(W)* A/D End Flag Status flag indicating the end of A/D conversion. [Clearing conditions]  Cleared by reading ADF while ADF = 1, then writing 0 to ADF  Cleared when the direct memory access controller is activated by ADI interrupt and ADDR is read [Setting conditions] 14 ADIE 0 R/W  A/D conversion ends in single mode  A/D conversion ends for the selected channels in multi mode  A/D conversion ends for the selected channels in scan mode A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE bit while A/D conversion is not being made. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled Page 1442 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 27 A/D Converter Bit Bit Name Initial Value R/W Description 13 ADST 0 R/W A/D Start Starts or stops A/D conversion. This bit remains set to 1 during A/D conversion. 0: A/D conversion is stopped 1: Single mode: A/D conversion starts. This bit is automatically cleared to 0 when A/D conversion ends on the selected channel. Multi mode: A/D conversion starts. This bit is automatically cleared to 0 when A/D conversion is completed cycling through the selected channels. Scan mode: A/D conversion starts. A/D conversion is continuously performed until this bit is cleared to 0 by software, by a power-on reset as well as by a transition to deep standby mode, software standby mode or module standby mode. 12 to 9 TRGS[3:0] 0000 R/W Timer Trigger Select These bits enable or disable starting of A/D conversion by a trigger signal. 0000: Start of A/D conversion by external trigger input is disabled 0001: A/D conversion is started by conversion trigger TRGAN from the multi-function timer pulse unit 2 0010: A/D conversion is started by conversion trigger TRG0N from the multi-function timer pulse unit 2 0011: A/D conversion is started by conversion trigger TRG4AN from the multi-function timer pulse unit 2 0100: A/D conversion is started by conversion trigger TRG4BN from the multi-function timer pulse unit 2 1001: A/D conversion is started by ADTRG Other than above: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1443 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter Bit Bit Name Initial Value R/W Description 8 to 6 CKS[2:0] 000 R/W Clock Select These bits select the A/D conversion time.*2 Set the A/D conversion time while A/D conversion is halted (ADST = 0). 000: Conversion time = 412 tcyc (maximum) 001: Conversion time = 480 tcyc (maximum) 010: Conversion time = 548 tcyc (maximum) 011, 100, 101, 110, 111: Setting prohibited 5 to 3 MDS[2:0] 000 R/W Multi-scan Mode These bits select the operating mode for A/D conversion. 0xx: Single mode 100: Multi mode: A/D conversion on 1 to 4 channels 101: Multi mode: A/D conversion on 1 to 8 channels 110: Scan mode: A/D conversion on 1 to 4 channels 111: Scan mode: A/D conversion on 1 to 8 channels Page 1444 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 27 A/D Converter Bit Bit Name Initial Value R/W Description 2 to 0 CH[2:0] 000 R/W Channel Select These bits and the MDS bits in ADCSR select the analog input channels. MDS = 100 or MDS = 101 or MDS = 111 MDS = 0xx MDS = 110 000: AN0 000: AN0 000: AN0 001: AN1 001: AN0, AN1 001: AN0, AN1 010: AN2 010: AN0 to AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 011: AN0 to AN3 100: AN4 100: AN4 100: AN0 to AN4 101: AN5 101: AN4, AN5 101: AN0 to AN5 110: AN6* 3 3 110: AN4 to AN6* 110: AN0 to AN6*3 111: AN7*3 111: AN4 to AN7*3 111: AN0 to AN7*3 [Legend] x: Don't care Notes: 1. Only 0 can be written to clear the flag after 1 is read. 2. Set the A/D conversion time to minimum or more values to meet the absolute accuracy of the A/D conversion characteristics. 3. Settings prohibited in the SH7268 Group. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1445 of 3092 Section 27 A/D Converter 27.4 SH7268 Group, SH7269 Group Operation The A/D converter uses the successive-approximation method, and the resolution is 10 bits. It has three operating modes: single mode, multi mode, and scan mode. Switching the operating mode or analog input channels must be done while the ADST bit in ADCSR is 0 to prevent incorrect operation. The ADST bit can be set at the same time as the operating mode or analog input channels are changed. 27.4.1 Single Mode Single mode should be selected when only A/D conversion on one channel is required. In single mode, A/D conversion is performed once for the specified one analog input channel, as follows: 1. A/D conversion for the selected channel starts when the ADST bit in ADCSR is set to 1 by software, the multi-function timer pulse unit 2, or external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the A/D data register corresponding to the channel. 3. After A/D conversion has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D conversion is completed, and the A/D converter becomes idle. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel selection is switched. Page 1446 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 27 A/D Converter Typical operations when a single channel (AN1) is selected in single mode are described next. Figure 27.2 shows a timing diagram for this example (the bits which are set in this example belong to ADCSR). 1. Single mode is selected, input channel AN1 is selected (CH[2:0] = 001), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADF = 1, and then writes 0 to the ADF flag. 6. The routine reads and processes the A/D conversion result (ADDRB). 7. Execution of the A/D interrupts handling routine ends. Then, when the ADST bit is set to 1, A/D conversion starts and steps 2 to 7 are executed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1447 of 3092 Page 1448 of 3092 Waiting Channel 3 (AN3) operating ADDRD ADDRC ADDRB Conversion time 1 Set* )indicate instruction execution by software. Waiting Channel 2 (AN2) operating Note: * Vertical arrows( Waiting Channel 1 (AN1) operating ADDRA Waiting A/D conversion starts Channel 0 (AN0) operating ADF ADST ADIE Set* A/D conversion result 1 Read conversion result Waiting Clear* Conversion time 2 Set* A/D conversion result 2 Read conversion result Waiting Clear* Section 27 A/D Converter SH7268 Group, SH7269 Group Figure 27.2 Example of A/D Converter Operation (Single Mode, One Channel (AN1) Selected) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.4.2 Section 27 A/D Converter Multi Mode Multi mode should be selected when performing A/D conversion once on one or more channels. In multi mode, A/D conversion is performed once for a maximum of eight specified analog input channels, as follows: 1. A/D conversion starts from the analog input channel with the lowest number (e.g. AN0, AN1, …, AN3) when the ADST bit in ADCSR is set to 1 by software, the multi-function timer pulse unit 2, or external trigger input. 2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially transferred to the A/D data register corresponding to that channel. 3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D conversion is completed, and the A/D converter becomes idle. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion is halted and the A/D converter becomes idle. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. A/D conversion is to be performed once on all the specified channels. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in multi mode are described next. Figure 27.3 shows a timing diagram for this example. 1. Multi mode is selected (MDS2 = 1, MDS1 = 0), analog input channels AN0 to AN2 are selected (CH[2:0] = 010), and A/D conversion is started (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D conversion result is transferred into ADDRA. 3. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and the ADST bit cleared to 0. 6. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1449 of 3092 Page 1450 of 3092 Waiting Waiting Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRD ADDRC ADDRB Conversion time 1 Conversion time 3 Clear* Waiting Waiting Waiting A/D conversion result 3 A/D conversion result 2 A/D conversion result 1 Conversion time 2 Note: * Vertical arrows( ) indicate instruction execution by software. Waiting Channel 1 (AN1) operating ADDRA Waiting Channel 0 (AN0) operating ADF ADST Set* A/D conversion Clear* Section 27 A/D Converter SH7268 Group, SH7269 Group Figure 27.3 Example of A/D Converter Operation (Multi Mode, Three Channels (AN0 to AN2) Selected) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.4.3 Section 27 A/D Converter Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels at all times. In scan mode, A/D conversion is performed sequentially for a maximum of eight specified analog input channels, as follows: 1. A/D conversion starts from the analog input channel with the lowest number (e.g. AN0, AN1, …, AN3) when the ADST bit in ADCSR is set to 1 by software, the multi-function timer pulse unit 2, or external trigger input. 2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially transferred to the A/D data register corresponding to that channel. 3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The A/D converter starts A/D conversion again from the channel with the lowest number. 4. The ADST bit is not cleared automatically, so steps 2. and 3. are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion halts and the A/D converter becomes idle. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. When the operating mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described as follows. Figure 27.4 shows a timing diagram for this example. 1. Scan mode is selected (MDS2 = 1, MDS1 = 1), analog input channels AN0 to AN2 are selected (CH[2:0] = 010), and A/D conversion is started (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D conversion result is transferred into ADDRA. 3. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 4. Conversion proceeds in the same way through the third channel (AN2). 5. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1451 of 3092 Section 27 A/D Converter SH7268 Group, SH7269 Group 6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI interrupt is requested at all times. To generate an interrupt on completing conversion of the third channel, clear the ADF bit to 0 after an interrupt is requested. Page 1452 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Waiting Waiting Waiting Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating Conversion time 1 Conversion time 3 Waiting *2 Clear*1 Clear*1 Waiting Waiting Waiting A/D conversion result 4 Conversion time 5 A/D conversion result 3 A/D conversion result 2 Conversion time 4 Continuous A/D conversion A/D conversion result 1 Conversion time 2 Waiting Notes: 1. Vertical arrows( )indicate instruction execution by software. 2. A/D conversion data is invalid. ADDRD ADDRC ADDRB ADDRA Waiting Channel 0 (AN0) operating ADF ADST Set*1 SH7268 Group, SH7269 Group Section 27 A/D Converter Figure 27.4 Example of A/D Converter Operation (Scan Mode, Three Channels (AN0 to AN2) Selected) Page 1453 of 3092 Section 27 A/D Converter 27.4.4 SH7268 Group, SH7269 Group A/D Converter Activation by External Trigger or Multi-Function Timer Pulse Unit 2 The A/D converter can be independently activated by an external trigger or an A/D conversion request from the multi-function timer pulse unit 2. To activate the A/D converter by an external trigger or the multi-function timer pulse unit 2, set the A/D trigger enable bits (TRGS[3:0]). When an external trigger or an A/D conversion request from the multi-function timer pulse unit 2 is generated with this bit setting, the ADST bit is set to 1 to start A/D conversion. The channel combination is determined by bits CH2 to CH0 in ADCSR. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 27.4.5 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at the A/D conversion start delay time (tD) after the ADST bit in ADCSR is set to 1, then starts conversion. Figure 27.5 shows the A/D conversion timing. Table 27.4 indicates the A/D conversion time. As indicated in figure 27.5, the A/D conversion time (tCONV) includes tD and the input sampling time(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 27.4. In multi mode and scan mode, the values given in table 27.4 apply to the first conversion. In the second and subsequent conversions, time is the values given in table 27.5. Page 1454 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 27 A/D Converter (1) P1φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address tD: A/D conversion start delay time tSPL: Input sampling time tCONV: A/D conversion time Figure 27.5 A/D Conversion Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1455 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter Table 27.4 A/D Conversion Time (Single Mode) CKS2 = 0 CKS1 = 0 CKS0 = 0 Item Symbol A/D conversion tD CKS1 = 1 CKS0 = 1 CKS0 = 0 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 15  26 17  30 19  34  97   113   129  401  412 467  480 533  548 start delay time Input sampling tSPL time A/D conversion tCONV time Note: Values in the table are represented in terms of tcyc (CKIO clock output cycle time). Table 27.5 A/D Conversion Time (Multi Mode and Scan Mode) CKS2 CKS1 CKS0 Conversion Time (tcyc) 0 0 0 384 (constant) 1 448 (constant) 0 512 (constant) 1 Note: Values in the table are represented in terms of tcyc (CKIO clock output cycle time). Page 1456 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.4.6 Section 27 A/D Converter External Trigger Input Timing A/D conversion can also be externally triggered. When the TRGS[3:0] bits in ADCSR are set to B'1001, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, regardless of the operating mode, are the same as when the ADST bit has been set to 1 by software. Figure 27.6 shows the timing. P1φ ADTRG Internal trigger signal ADST A/D conversion Figure 27.6 External Trigger Input Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1457 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter 27.5 Interrupt Sources and DMA Transfer Request The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. An ADI interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is set to 1 on completion of A/D conversion. Note that the direct memory access controller can be activated by an ADI interrupt depending on the setting of the direct memory access controller. In this case, an interrupt is not issued to the CPU. If the setting to activate the direct memory access controller has not been made, an interrupt request is sent to the CPU. Having the converted data read by the direct memory access controller in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. In single mode, set the direct memory access controller so that DMA transfer initiated by an ADI interrupt is performed only once. In the case of A/D conversion on multiple channels in scan mode or multi mode, setting the DMA transfer count to one causes DMA transfer to finish after transferring only one channel of data. To make the direct memory access controller transfer all conversion data, set the ADDR where A/D conversion data is stored as the transfer source address, and the number of converted channels as the transfer count. When the direct memory access controller is activated by ADI, the ADF bit in ADCSR is automatically cleared to 0 when data is transferred by the direct memory access controller. Table 27.6 Relationship between Interrupt Sources and DMA Transfer Request Name Interrupt Source Interrupt Flag Direct Memory Access Controller Activation ADI A/D conversion end ADF in ADCSR Possible Page 1458 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.6 Section 27 A/D Converter Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors:     Offset error Full-scale error Quantization error Nonlinearity error These four error quantities are explained below with reference to figure 27.7. In the figure, the 10bit A/D converter is illustrated as the 3-bit A/D converter for explanation. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) B'0000000000 (000 in the figure) to B'000000001 (001 in the figure)(figure 27.7, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from B'1111111110 (110 in the figure) to the maximum B'1111111111 (111 in the figure)(figure 27.7, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 27.7, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 27.7, item (4)). Note that it does not include offset, full-scale, or quantization error. Digital output Ideal A/D conversion characteristic 111 110 (2) Full-scale error Digital output Ideal A/D conversion characteristic 101 100 (4) Nonlinearity error 011 (3) Quantization error 010 001 000 0 1 2 1024 1024 [Legend] FS: Full-scale voltage 10221023 FS 10241024 Analog input voltage Actual A/D convertion characteristic (1) Offset error FS Analog input voltage Figure 27.7 Definitions of A/D Conversion Accuracy R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1459 of 3092 Section 27 A/D Converter 27.7 SH7268 Group, SH7269 Group Usage Notes When using the A/D converter, note the following points. 27.7.1 Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, see section 49, Power-Down Modes. 27.7.2 Setting Analog Input Voltage Permanent damage to the LSI may result if the following voltage ranges are exceeded. 1. Analog input range During A/D conversion, voltages on the analog input pins ANn should not go beyond the following range: AVss  ANn  AVcc (n = 0 to 7). 2. AVcc and AVss input voltages Input voltages AVcc and AVss should be PVcc  0.3 V  AVcc  PVcc and AVss = Vss. Do not leave the AVcc and AVss pins open when the A/D converter is not in use and in software standby mode. When not in use, connect AVcc to the power supply (PVcc) and AVss to the ground (Vss). 3. Setting range of AVref input voltage Set the reference voltage range of the AVref pin as 3.0 V  AVref  AVcc. 27.7.3 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input signals (AN0 to AN3), analog reference voltage (AVref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. Page 1460 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 27.7.4 Section 27 A/D Converter Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN0 to AN7), connect an input protection circuit like the one shown in figure 27.8. The circuit shown also includes a CR filter to suppress noise. This circuit is shown as an example; the circuit constants should be selected according to actual application conditions. Figure 27.9 shows an equivalent circuit diagram of the analog input ports and table 27.7 lists the analog input pin specifications. AVcc AVref *2 *1 Rin 100 Ω This LSI AN0 to AN7*3 *1 0.1 μF AVss Notes: Values are reference values. 1. 10 μF 0.01 μF 2. Rin: Input impedance 3. Only AN0 to AN5 can be used in the SH7268 Group. Figure 27.8 Example of Analog Input Protection Circuit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1461 of 3092 SH7268 Group, SH7269 Group Section 27 A/D Converter 3 kΩ To A/D converter AN0 to AN7* 20 pF Note: Values are reference values. * Only AN0 to AN5 can be used in the SH7268 Group. Figure 27.9 Analog Input Pin Equivalent Circuit Table 27.7 Analog Input Pin Ratings Item Min. Max. Unit Analog input capacitance  20 pF Allowable signal-source impedance  5 k 27.7.5 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with a large capacitance provided externally for A/D conversion in single mode, the input load will essentially comprise only the internal input resistance of 3 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 27.10). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Page 1462 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 27 A/D Converter This LSI Sensor output impedance A/D converter equivalent circuit 3 kΩ Up to 5 kΩ Sensor input Low-pass filter Cin = 15 pF C to 0.1 μF 20 pF Note: Values are reference values. Figure 27.10 Example of Analog Input Circuit 27.7.6 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to connect AVss, etc. to an electrically stable GND. Care is also required to insure that filter circuits do not interfere with digital signals on the mounting board (i.e., acting as antennas). 27.7.7 Note on Usage in Scan Mode and Multi Mode Starting conversion immediately after having stopped scan mode or multi mode operation may lead to erroneous results of conversion. To perform continuous conversion in such cases, set ADST to 0, wait for at least the A/D conversion time for a single channel to elapse, and then start conversion (ADST = 1). (The A/D conversion time for a single channel will vary according to the settings of the ADC registers.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1463 of 3092 Section 27 A/D Converter Page 1464 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Section 28 NAND Flash Memory Controller The NAND flash memory controller provides interfaces for an external NAND-type flash memory. 28.1 (1)      Features NAND-Type Flash Memory Interface Interface directly connectable to NAND-type flash memory Read or write in sector units (512 + 16 bytes) Read or write in byte units Supports large-block (2048 + 64 bytes) flash memory* Supports addresses for 2 Gbits and more by extension to 5-byte addresses Note: * This module handles 512 + 16 bytes as a sector. For products with 2048 + 64 bytepages, this module divides a page into 512 +16 bytes units (i.e. four sectors per page) for processing. (2) Access Modes: This module can select one of the following two access modes.  Command access mode: Performs an access by specifying a command to be issued from this module to flash memory, address, and data size to be input or output.  Sector access mode*: Performs a read or write in sector units by specifying a sector address. By specifying the number of sectors, the continuous physical sectors can be read or written. Note: * The controller of this LSI chip is not capable of reading data in sector access mode. (3) Sectors and Control Codes  A sector is the basic unit of access and comprised of 512-byte data and 16-byte control code fields.  User information can be written to any part of the control code field. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1465 of 3092 Section 28 NAND Flash Memory Controller (4) SH7268 Group, SH7269 Group Data Error  When a program error or erase error occurs, the error is reflected on the error source flags. Interrupts for each source can be specified. (5) Data Transfer FIFO and Data Register  The 224-byte data FIFO register (FLDTFIFO) is incorporated for data transfer of flash memory.  The 32-byte control code FIFO register (FLECFIFO) is incorporated for data transfer of control code. (6) DMA Transfer  By individually specifying the destinations of data and control code of flash memory to the direct memory access controller, data and control code can be sent to different areas. (7) Access Time  The operating clock (FCLK) on the pins for the NAND-type flash memory is generated by dividing the peripheral clock 0 (P0). The division ratio can be specified by the QTSEL bit in the common control register (FLCMNCR).  Before changing the clock pulse generator configuration, this module must be placed in a module stop state.  In NAND-type flash memory, the FRE and FWE pins operate at the frequency of FCLK. The operating frequency must be specified within the maximum operating frequency of memory to be connected. Page 1466 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Figure 28.1 shows a block diagram. Direct memory access controller Interrupt controller Peripheral bus 0 Bus state controller 32 DMA transfer requests (2 lines) Peripheral bus interface 32 NAND flash memory controller Interrupt requests (4 lines) 32 32 FIFO 256 bytes Bus mastership request acknowledge 32 Bus mastership request State machine Registers QTSEL Transmit/ receive control FCLK ×1/2 ×1/4 Peripheral Clock clock 0 pulse generator 8 8 Flash memory interface 8 Control signal NAND Flash memory Note: FCLK is the operating clock for flash memory interface signals. The division ratio is specified by register FLCMNCR. Figure 28.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1467 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.2 Input/Output Pins The pin configuration of is listed in table 28.1. Table 28.1 Pin Configuration Corresponding Flash Memory Pin Pin Name I/O NAND Type Function FCE Output CE Flash Memory Chip Enable Enables flash memory connected to this LSI. NAF7 to NAF0 I/O I/O7 to I/O0 Flash Memory Data I/O pins for command, address, and data. FCLE Output CLE Flash Memory Command Latch Enable Asserted when a command is output. FALE Output ALE Flash Memory Address Latch Enable Asserted when an address is output and negated when data is input or output. FRE Output RE Flash Memory Read Enable Reads data at the falling edge of RE. FWE Output WE Flash Memory Write Enable Flash memory latches a command, address, and data at the rising edge of WE. FRB Input R/B Flash Memory Ready/Busy Indicates ready state at high level; indicates busy state at low level. *  WP Write Protect/Reset When this pin goes low, erroneous erasure or programming at power on or off can be prevented. *  SE Spare Area Enable Used to access spare area. This pin must be fixed at low in sector access mode. Note: * Not supported in this LSI. Page 1468 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.3 Section 28 NAND Flash Memory Controller Register Descriptions Table 28.2 shows the register configuration. Table 28.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Common control register FLCMNCR R/W H'00100001 H'FFFF4000 32 Command control register FLCMDCR R/W H'00000000 H'FFFF4004 32 Command code register FLCMCDR R/W H'00000000 H'FFFF4008 32 Address register FLADR R/W H'00000000 H'FFFF400C 32 Address register 2 FLADR2 R/W H'00000000 H'FFFF403C 32 Data register FLDATAR R/W H'00000000 H'FFFF4010 32 Data counter register FLDTCNTR R/W H'00000000 H'FFFF4014 32 Interrupt DMA control register FLINTDMACR R/W H'00000000 H'FFFF4018 32 Ready busy timeout setting register FLBSYTMR R/W H'00000000 H'FFFF401C 32 Ready busy timeout counter FLBSYCNT R H'00000000 H'FFFF4020 32 Data FIFO register FLDTFIFO R/W H'xxxxxxxx H'FFFF4050 32 Control code FIFO register FLECFIFO R/W H'xxxxxxxx H'FFFF4060 32 Transfer control register FLTRCR R/W H'00 H'FFFF402C 8 R/W H'00000000 H'FFFF4038 32 Bus hold time setting register FLHOLDCR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1469 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.1 Common Control Register (FLCMNCR) FLCMNCR is a 32-bit readable/writable register that specifies access mode, and other items. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - BUSYON - - SNAND QT SEL - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 1 R 0 R 0 R/W 0 R/W 0 R Bit: 15 11 10 0 Initial value: R/W: Initial value: R/W: Bit 14 13 12 - - - - 0 R 0 R 0 R 0 R Bit Name 31 to 22  ACM[1:0] 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 NAND WF - - - - - CE - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 1 R Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21 BUSYON 0 R/W Busy Select Specifies whether to release the external bus mastership while the FRB pin is busy. The FCE pin, however, is negated regardless of the busy/ready state upon completion of a necessary process. For details, see section 28.7.1, External Bus Mastership Release Timing. 0: Holds the bus mastership while the FRB pin is busy. 1: Releases the bus mastership while the FRB pin is busy. Note: Some flash memory devices do not allow the FCE pin to be negated during the busy state. 20  1 R Reserved This bit is always read as 1. The write value should always be 1. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 1470 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Bit Bit Name Initial Value R/W Description 18 SNAND 0 R/W Large-Capacity NAND Flash Memory Select This bit is used to specify 1-Gbit or larger NAND flash memory with the page configuration of 2048 + 64 bytes. 0: When flash memory with the page configuration of 512 + 16 bytes is used. 1: When NAND flash memory with the page configuration of 2048 + 64 is used. 17 QTSEL 0 R/W Select Dividing Rates for Flash Clock Selects the dividing rate of clock FCLK in the flash memory. 0: Divides a clock (P0) provided from the clock pulse generator by two and uses it as FCLK. 1: Divides a clock (P0) provided from the clock pulse generator by four and uses it as FCLK. 16 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11, 10 ACM[1:0] 00 R/W Access Mode Specification 1 and 0 Specify access mode. 00: Command access mode 01: Sector access mode* 10: Setting prohibited 11: Setting prohibited 9 NANDWF 0 R/W NAND Wait Insertion Operation 0: Performs address or data input/output in one FCLK cycle 1: Performs address or data input/output in two FCLK cycles 8 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 CE 0 R/W Chip Enable 0: Disables the chip (Outputs high level to the FCE pin) 1: Enables the chip (Outputs low level to the FCE pin) 2, 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1471 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Bit Bit Name Initial Value R/W Description 0  1 R Reserved This bit is always read as 1. The write value should always be 1. Note: * The controller is not capable of reading data in sector access mode. Page 1472 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.3.2 Section 28 NAND Flash Memory Controller Command Control Register (FLCMDCR) FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode, specifies address issue, and specifies source or destination of data transfer. In sector access mode, FLCMDCR specifies the number of sector transfers. Bit: 31 30 ADR CNT2 Initial value: 0 R/W: R/W Bit: 15 29 28 27 SCTCNT[19:16] 26 25 24 23 22 21 20 17 16 ADR MD CDS RC DOSR - - SEL RW DOA DR ADRCNT[1:0] DOC MD2 DOC MD1 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 19 18 SCTCNT[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 ADRCNT2 0 0 R/W 0 R/W R/W R 0 R/W 0 R/W 0 R/W Description Address Issue Byte Count Specification 2 Specifies the number of bytes for the address data to be issued in address stage. This bit is used together with ADRCNT[1:0]. 0: Issue the address of byte count, specified by ADRCNT[1:0]. 1: Issue 5-byte address. ADRCNT[1:0] should be set to 00. 30 to 27 SCTCNT [19:16] 0000 R/W Sector Transfer Count Specification [19:16] These bits are extended bits of the sector transfer count specification bits (SCTCNT) 15 to 0. SCTCNT[19:16] and SCTCNT[15:0] are used together to operate as SCTCNT[19:0], the 20-bit counter. 26 ADRMD 0 R/W Sector Access Address Specification This bit is invalid in command access mode. This bit is valid only in sector access mode. 0: The value of the address register is handled as a sector address. Use this value usually in sector access. 1: The value of the address register is output as the address of flash memory. Note: Clear this bit to 0 in continuous sector access. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1473 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Bit Bit Name Initial Value R/W Description 25 CDSRC 0 R/W Data Buffer Specification Specifies the data buffer to be read from or written to in the data stage in command access mode. 0: Specifies FLDATAR as the data buffer. 1: Specifies FLDTFIFO as the data buffer. 24 DOSR 0 R/W Status Read Check Specifies whether or not the status read is performed after the second command has been issued in command access mode. 0: Performs no status read 1: Performs status read 23, 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21 SELRW 0 R/W Data Read/Write Specification Specifies the direction of read or write in data stage. 0: Read 1: Write 20 DOADR 0 R/W Address Stage Execution Specification Specifies whether or not the address stage is executed in command access mode. 0: Performs no address stage 1: Performs address stage 19, 18 ADRCNT [1:0] 00 R/W Address Issue Byte Count Specification [1:0] Specify the number of bytes for the address data to be issued in address stage. 00: Issue 1-byte address 01: Issue 2-byte address 10: Issue 3-byte address 11: Issue 4-byte address Page 1474 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Bit Bit Name Initial Value R/W Description 17 DOCMD2 0 R/W Second Command Stage Execution Specification Specifies whether or not the second command stage is executed in command access mode. 0: Does not execute the second command stage 1: Executes the second command stage 16 DOCMD1 0 R/W First Command Stage Execution Specification Specifies whether or not the first command stage is executed in command access mode. 0: Does not execute the first command stage 1: Executes the first command stage 15 to 0 SCTCNT [15:0] H'0000 R/W Sector Transfer Count Specification [15:0] Specify the number of sectors to be read continuously in sector access mode. These bits are counted down for each sector transfer end and stop when they reach 0. These bits are used together with SCTCNT[19:16]. In command access mode, these bits are H'0 0001. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1475 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.3 Command Code Register (FLCMCDR) FLCMCDR is a 32-bit readable/writable register that specifies a command to be issued in command access or sector access. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W - CMD2[7:0] Initial value: 0 R/W: R/W Bit 0 R/W Bit Name 31 to 16  0 R/W 0 R/W 16 CMD1[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 15 to 8 CMD2[7:0] H'00 R/W Second Command Data Specify a command code to be issued in the second command stage. 7 to 0 CMD1[7:0] H'00 R/W First Command Data Specify a command code to be issued in the first command stage. Page 1476 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.3.4 Section 28 NAND Flash Memory Controller Address Register (FLADR) FLADR is a 32-bit readable/writable register that specifies the value to be output as an address. The address of the size specified by ADRCNT[1:0] in the command control register is output sequentially from ADR1 in byte units. By the sector access address specification bit (ADRMD) of the command control register, it is possible to specify whether the sector number set in the address data bits is converted into an address to be output to the flash memory.  When ADRMD = 1 Bit: 31 30 29 28 27 26 25 24 23 22 21 ADR4[7:0] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 Bit 0 R/W Bit Name 0 R/W 0 R/W Initial Value 31 to 24 ADR4[7:0] H'00 0 R/W 19 18 17 16 ADR3[7:0] ADR2[7:0] Initial value: 0 R/W: R/W 20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 4 3 2 1 0 0 R/W 0 R/W 0 R/W ADR1[7:0] 0 R/W R/W R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description Fourth Address Data Specify 4th data to be output to flash memory as an address when ADRMD = 1. 23 to 16 ADR3[7:0] H'00 R/W Third Address Data Specify 3rd data to be output to flash memory as an address when ADRMD = 1. 15 to 8 ADR2[7:0] H'00 R/W Second Address Data Specify 2nd data to be output to flash memory as an address when ADRMD = 1. 7 to 0 ADR1[7:0] H'00 R/W First Address Data Specify 1st data to be output to flash memory as an address when ADRMD = 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1477 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller  When ADRMD = 0 Bit: 31 30 29 28 27 26 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 - 25 24 23 22 21 20 19 18 17 16 ADR[25:16] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ADR[15:0] Initial value: 0 R/W: R/W Bit 0 R/W Bit Name 31 to 26  0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 0 ADR[25:0] H'0000 000 R/W Sector Address Specification Specify a sector number to be accessed when ADRMD = 0. The sector number is converted into an address and is output to flash memory. When the ADRCNT2 bit in FLCMDCR = 1, the ADR[25:0] bits are valid. When the ADRCNT2 bit in FLCMDCR = 0, the ADR[17:0] bits are valid. See figure 28.11 for details.   Page 1478 of 3092 Large-block products (2048 + 64 bytes) ADR[25:2] specifies the page address and ADR[1:0] specifies the column address in sector units. ADR[1:0] = 00: 0th byte (sector 0) ADR[1:0] = 01: (512 + 16)th byte (sector 1) ADR[1:0] = 00: (1024 + 32)th byte (sector 2) ADR[1:0] = 00: (1536 + 48)th byte (sector 3) Small-block products (512 + 16 bytes) Only the page address can be specified. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.3.5 Section 28 NAND Flash Memory Controller Address Register 2 (FLADR2) FLADR2 is a 32-bit readable/writable register, and is valid when the ADRCNT2 bit in FLCMDCR is set to 1. FLADR2 specifies an address to be output in command access mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W - 14 13 12 11 10 9 8 - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 16 ADR5[7:0] 0 R/W Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 to 0 ADR5[7:0] H'00 R/W Fifth Address Data Specify 5th data to be output to flash memory as an address when ADRMD = 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1479 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.6 Data Counter Register (FLDTCNTR) FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or written in command access mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 ECFLW[7:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 - - - 0 R 0 R 0 R - Initial value: 0 R/W: R 20 19 18 17 16 DTFLW[7:0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DTCNT[11:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description 31 to 24 ECFLW [7:0] H'00 R FLECFIFO Access Count Specify the number of longwords in FLECFIFO to be read or written. These bit values are used when the CPU reads from or writes to FLECFIFO. In FLECFIFO read, these bits specify the number of longwords of the data that can be read from FLECFIFO. In FLECFIFO write, these bits specify the number of longwords of unoccupied area that can be written in FLECFIFO. 23 to 16 DTFLW [7:0] H'00 R FLDTFIFO Access Count Specify the number of longwords in FLDTFIFO to be read or written. These bit values are used when the CPU reads from or writes to FLDTFIFO. In FLDTFIFO read, these bits specify the number of longwords of the data that can be read from FLDTFIFO. In FLDTFIFO write, these bits specify the number of longwords of unoccupied area that can be written in FLDTFIFO. 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 H'000 R/W Data Count Specification Specify the number of bytes of data to be read or written in command access mode. (Up to 2048 + 64 bytes can be specified for writing, and up to 128 bytes for reading.) Bit Bit Name DTCNT [11:0] Page 1480 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.3.7 Section 28 NAND Flash Memory Controller Data Register (FLDATAR) FLDATAR is a 32-bit readable/writable register. It stores input/output data used when 0 is written to the CDSRC bit in FLCMDCR in command access mode. FLDATAR cannot be used for reading or writing of five or more bytes of contiguous data. Bit: 31 30 29 28 27 26 25 24 23 22 21 DT4[7:0] Initial value: 0 R/W: R/W Bit: 15 Bit 19 18 17 16 DT3[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W DT2[7:0] Initial value: 0 R/W: R/W 20 0 R/W Bit Name 31 to 24 DT4[7:0] 0 R/W 0 R/W 0 R/W DT1[7:0] 0 R/W Initial Value R/W H'00 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description Fourth Data Specify the 4th data to be input or output via the NAF7 to NAF0 pins. In write: Specify write data In read: Store read data 23 to 16 DT3[7:0] H'00 R/W Third Data Specify the 3rd data to be input or output via the NAF7 to NAF0 pins. In write: Specify write data In read: Store read data 15 to 8 DT2[7:0] H'00 R/W Second Data Specify the 2nd data to be input or output via the NAF7 to NAF0 pins. In write: Specify write data In read: Store read data 7 to 0 DT1[7:0] H'00 R/W First Data Specify the 1st data to be input or output via the NAF7 to NAF0 pins. In write: Specify write data In read: Store read data R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1481 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.8 Interrupt DMA Control Register (FLINTDMACR) FLINTDMACR is a 32-bit readable/writable register that enables or disables DMA transfer requests or interrupts. A transfer request from this module to the direct memory access controller is issued after each access mode has been started. Bits 9 to 5 are the flag bits that indicate various errors occurred in flash memory access and whether there is a transfer request from the FIFO. Only 0 can be written to these bits. To clear a flag, write 0 to the target flag bit and 1 to the other flag bits. Bit: 31 30 29 28 27 26 25 24 23 22 - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 Initial value: R/W: Initial value: R/W: 21 20 FIFOTRG [1:0] 0 R/W 0 R/W 19 18 AC1 CLR AC0 CLR 0 R/W 0 R/W 17 16 DREQ1 DREQ0 EN EN 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - ST ERB BTO ERB TRR EQF1 TRR EQF0 STER INTE RBER INTE TE INTE TR INTE1 TR INTE0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/W Note: * Only 0 can be written to these bits. Bit Bit Name 31 to 22  Page 1482 of 3092 Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 21, 20 FIFOTRG [1:0] Section 28 NAND Flash Memory Controller Initial Value R/W Description 00 R/W FIFO Trigger Setting Specify the condition (the byte number) for generation of FLDTFIFO and FLECFIFO transfer requests.  In flash-memory read Issue an interrupt to the CPU or issue a DMA transfer request when FLDTFIFO (FLECFIFO) stores the following number of bytes or more: 00: 4 (4) 01: 16 (16) 10: 128 (4) 11: 128 (16)  In flash-memory programming Issue an interrupt to the CPU or issue a DMA transfer request when FLDTFIFO (FLECFIFO) has the following empty area of bytes or more: 00: 4 (4) 01: 16 (16) 10: 128 (4) 11: 128 (16) Note: For DMA transfer from/to FLDTFIFO, setting 10 and 11 are prohibited. 19 AC1CLR 0 R/W FLECFIFO Clear Clears FLECFIFO. 0: Retains the FLECFIFO value. In flash-memory access, this bit should be cleared to 0. 1: Clears FLECFIFO. After FLECFIFO has been cleared, this bit should be cleared to 0. 18 AC0CLR 0 R/W FLDTFIFO Clear Clears FLDTFIFO. 0: Retains the FLDTFIFO value. In flash-memory access, this bit should be cleared to 0. 1: Clears FLDTFIFO. After FLDTFIFO has been cleared, this bit should be cleared to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1483 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Initial Value Bit Bit Name 17 DREQ1EN 0 R/W Description R/W FLECFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLECFIFO. 0: Disables the DMA transfer request issued from FLECFIFO 1: Enables the DMA transfer request issued from FLECFIFO 16 DREQ0EN 0 R/W FLDTFIFODMA Request Enable Enables or disables the DMA transfer request issued from FLDTFIFO. 0: Disables the DMA transfer request issued from the FLDTFIFO 1: Enables the DMA transfer request issued from the FLDTFIFO 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 STERB 0 R/(W)* Status Error Indicates the result of status read. This bit is set to 1 if the specific bit in the bits STAT[7:0] in FLBSYCNT is set to 1 in status read. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no status error occurs (the specific bit in the bits STAT[7:0] in FLBSYCNT is 0.) 1: Indicates that a status error occurs For details on the specific bit in STAT7 to STAT0 bits, see section 28.4.6, Status Read. 7 BTOERB 0 R/(W)* R/B Timeout Error This bit is set to 1 if an R/B timeout error occurs (the bits RBTIMCNT[19:0] in FLBSYCNT are decremented to 0). This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no R/B timeout error occurs 1: Indicates that an R/B timeout error occurs Page 1484 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Initial Value Bit Bit Name 6 TRREQF1 0 Section 28 NAND Flash Memory Controller R/W Description R/(W)* FLECFIFO Transfer Request Flag Indicates that a transfer request is issued from FLECFIFO. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no transfer request is issued from FLECFIFO 1: Indicates that a transfer request is issued from FLECFIFO 5 TRREQF0 0 R/(W)* FLDTFIFO Transfer Request Flag Indicates that a transfer request is issued from FLDTFIFO. This bit is a flag. 1 cannot be written to this bit. Only 0 can be written to clear the flag. 0: Indicates that no transfer request is issued from FLDTFIFO 1: Indicates that a transfer request is issued from FLDTFIFO 4 STERINTE 0 R/W Interrupt Enable at Status Error Enables or disables an interrupt request to the CPU when a status error has occurred. 0: Disables the interrupt request to the CPU by a status error 1: Enables the interrupt request to the CPU by a status error 3 RBERINTE 0 RW Interrupt Enable at R/B Timeout Error Enables or disables an interrupt request to the CPU when a timeout error has occurred. 0: Disables the interrupt request to the CPU by an R/B timeout error 1: Enables the interrupt request to the CPU by an R/B timeout error R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1485 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Bit Bit Name Initial Value R/W Description 2 TEINTE 0 R/W Transfer End Interrupt Enable Enables or disables an interrupt request to the CPU when a transfer has been ended (TREND bit in FLTRCR). 0: Disables the transfer end interrupt request to the CPU 1: Enables the transfer end interrupt request to the CPU 1 TRINTE1 0 R/W FLECFIFO Transfer Request Enable to CPU Enables or disables an interrupt request to the CPU by a transfer request issued from FLECFIFO. 0: Disables an interrupt request to the CPU by a transfer request from FLECFIFO. 1: Enables an interrupt request to the CPU by a transfer request from FLECFIFO. When the DMA transfer is enabled, this bit should be cleared to 0. 0 TRINTE0 0 R/W FLDTFIFO Transfer Request Enable to CPU Enables or disables an interrupt request to the CPU by a transfer request issued from FLDTFIFO. 0: Disables an interrupt request to the CPU by a transfer request from FLDTFIFO 1: Enables an interrupt request to the CPU by a transfer request from FLDTFIFO When the DMA transfer is enabled, this bit should be cleared to 0. Note: * Only 0 can be written to these bits. Page 1486 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.3.9 Section 28 NAND Flash Memory Controller Ready Busy Timeout Setting Register (FLBSYTMR) FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FRB pin is busy. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W - 19 18 17 16 RBTMOUT[19:16] RBTMOUT[15:0] Initial value: 0 R/W: R/W Bit 0 R/W Bit Name 31 to 20  0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 19 to 0 RBTMOUT H'00000 [19:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R/W Ready Busy Timeout Specify timeout time (the number of P clocks) in busy state. When these bits are set to 0, timeout is not generated. Page 1487 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.10 Ready Busy Timeout Counter (FLBSYCNT) FLBSYCNT is a 32-bit read-only register. The status of flash memory obtained by the status read is stored in the bits STAT[7:0]. The timeout time set in the bits RBTMOUT[19:0] in FLBSYTMR is copied to the bits RBTIMCNT[19:0] and counting down is started when the FRB pin is placed in a busy state. When values in the RBTIMCNT[19:0] become 0, 1 is set to the BTOERB bit in FLINTDMACR, thus notifying that a timeout error has occurred. In this case, an FLSTE interrupt request can be issued if an interrupt is enabled by the RBERINTE bit in FLINTDMACR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R STAT[7:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 19 18 17 16 RBTIMCNT[19:16] RBTIMCNT[15:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial Value R/W Description 31 to 24 STAT[7:0] All 0 R Indicate the flash memory status obtained by the status read. 23 to 20  All 0 R Reserved Bit Bit Name These bits are always read as 0. 19 to 0 RBTIMCN H'00000 T[19:0] Page 1488 of 3092 R Ready Busy Timeout Counter When the FRB pin is placed in a busy state, the values of the bits RBTMOUT[19:0] in FLBSYTMR are copied to these bits. These bits are counted down while the FRB pin is busy. A timeout error occurs when these bits are decremented to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.11 Data FIFO Register (FLDTFIFO) FLDTFIFO is used to read or write the data FIFO area. In DMA transfer, this register must be specified as the destination or source. Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match that specified in this register. When changing the read/write direction, FLDTFIFO should be cleared by setting the AC0CLR bit in FLINTDMACR before use. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DTFO[31:16] Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTFO[15:0] Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 0 DTFO [31:0] Initial Value R/W H'xxxxxxxx R/W Description Data FIFO Area Read/Write Data In write: Data in this register is written to the data FIFO area. In read: Data read from the data FIFO area is stored in this register. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1489 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.12 Control Code FIFO Register (FLECFIFO) FLECFIFO is used to read or write the control code FIFO area. In DMA transfer, data in this register must be specified as the destination (source). Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match that specified in this register. When changing the read/write direction, FLECFIFO should be cleared by setting the AC1CLR bit in FLINTDMACR before use. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECFO[31:16] Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECFO[15:0] Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 0 ECFO [31:0] Initial Value R/W H'xxxxxxxx R/W Description Control Code FIFO Area Read/Write Data In write: Data in this register is written to the control code FIFO area. In read: Data read from the control code FIFO area is stored in this register. Page 1490 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.13 Transfer Control Register (FLTRCR) Setting the TRSTRT bit to 1 initiates access to flash memory. Access completion can be checked by the TREND bit. During the transfer (from when the TRSTRT bit is set to 1 until the TREND bit is set to 1), the processing should not be forcibly ended (by setting the TRSTRT bit to 0). When reading from flash memory, TREND is set when reading from flash memory have been finished. However, if there is any read data remaining in the FIFO, the processing should not be forcibly ended until all data has been read from the FIFO. While this module has the external bus mastership and transfer is in progress, the SLEEP instruction should not be executed until the TREND bit is set and transfer is completed. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - TR STAT TR END TR STRT 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 TRSTAT 0 R Transfer State Indicates that this module has acquired the external bus mastership and that transfer is actually being performed. 0: Transfer has not been started. 1: Transfer is in progress or transfer has ended. 1 TREND 0 R/W Processing End Flag Bit Indicates that the processing performed in the specified access mode has been completed. The write value should always be 0. 0 TRSTRT 0 R/W Transfer Start By setting this bit from 0 to 1 when the TREND bit is 0, processing in the access mode specified by the access mode specification bits ACM[1:0] is initiated. 0: Stops transfer 1: Starts transfer R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1491 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.3.14 Bus Hold Time Setting Register (FLHOLDCR) FLHOLDCR specifies the external bus release frequency if any other module (including the CPU) accesses a memory under the control of the bus state controller while this module is writing to or reading from the flash memory in sector access mode. With the HOLDEN bit = 0 in this register, this module holds the external bus during transfers between the flash memory and this LSI. Note that this may cause a deadlock depending on the program code and transfer data location and usage. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - HOLDEN Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W 31 to 1  All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 0 HOLDEN 0 R/W Bus Hold Enable Specifies whether to release the external bus mastership during write to or read from the flash memory in sector access mode. 0: Holds the bus mastership during transfers. 1: Releases the bus mastership during transfers if the FIFO empty or full state is entered in sector access mode. Note: When using the FIFO in command access mode, store the control program for this module and transfer data in the on-chip RAM. Page 1492 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.4 Operation 28.4.1 Access Sequence This module performs accesses in several independent stages. For example, NAND-type flash memory programming consists of the following five stages.      First command issue stage (program setup command) Address issue stage (program address) Data stage (output) Second command issue stage (program start command) Status read stage NAND-type flash memory programming access is achieved by executing these five stages sequentially. An access to flash memory is completed at the end of the final stage (status read stage). Program First command Command/ address H'80 Address A1 A2 Data A3 A4 Second command H'10 Status read H'70 CLE ALE WE Data input Program start RE Figure 28.2 Programming Operation for NAND-Type Flash Memory and Stages For details on NAND-type flash memory read operation, see section 28.4.4, Command Access Mode. 28.4.2 Operating Modes Two operating modes are supported.  Command access mode  Sector access mode The ECC generation and error check are performed in sector access mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1493 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.4.3 Register Setting Procedure Figure 28.3 shows the register setting flow required for accessing the flash memory. Start Start the setting procedure after the current transfer has been completed No FLTRCR = All 0? Yes Set FLCMNCR Set FLCMDCR Set FLCMCDR When the fifth address data is output in command access, FLADR2 should also be set Not required in sector access Not required in reading. Not required when FLDTFIFO is used. Set FLADR Set FLDTCNTR Set FLDATAR Set FLINTDMACR Set FLBSYTMR When the external bus mastership is not released during data transfer, store the control program for this module and transfer data in the on-chip RAM in advance. Set FLHOLDCR Except FLTRCR, register settings completed? No Yes Start the transfer Set FLTRCR to H'01 Wait until the transfer is completed No TREND in FLTRCR = 1? Yes Set FLTRCR to H'00 End Note: Registers FLCMNCR to FLHOLDCR in this flow can be set in any order. Figure 28.3 Register Setting Flow Page 1494 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.4.4 Section 28 NAND Flash Memory Controller Command Access Mode Command access mode accesses flash memory by specifying a command to be issued to flash memory, address, data, read/write direction, and number of times to the registers. In this mode, I/O data can be transferred by the DMA via FLDTFIFO. (1) NAND-Type Flash Memory Access Figure 28.4 shows an example of read operation for NAND-type flash memory. In this example, the first command is specified as H'00, address data length is specified as 3 bytes, and the number of read bytes is specified as 8 bytes in the data counter. CLE ALE WE RE I/O7 to I/O0 H'00 A1 A2 A3 1 2 3 4 5 8 R/B Figure 28.4 Read Operation Timing for NAND-Type Flash Memory R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1495 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Figures 28.5 and 28.6 show examples of programming operation for NAND-type flash memory. CLE ALE WE RE I/O7 to I/O0 H'80 A1 A2 A3 1 2 3 4 5 8 R/B Figure 28.5 Programming Operation Timing for NAND-Type Flash Memory (1) CLE ALE WE RE I/O7 to I/O0 H'10 H'70 Status R/B Figure 28.6 Programming Operation Timing for NAND-Type Flash Memory (2) Page 1496 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 28 NAND Flash Memory Controller NAND-Type Flash Memory (2048 + 64 Bytes) Access Figure 28.7 shows an example of read operation for NAND-type flash memory (2048 + 64 bytes). In this example, the first command is specified as H'00, the second command is specified as H'30, and address data length is specified as 4 bytes. The number of read bytes is specified as 4 bytes in the data counter. CLE ALE WE RE H'30 H'00 A1 A2 A3 A4 I/O7 to I/O0 1 2 3 4 R/B Figure 28.7 Read Operation Timing for NAND-Type Flash Memory Figures 28.8 and 28.9 show examples of programming operation for NAND-type flash memory (2048 + 64 bytes). CLE ALE WE RE H'10 H'80 I/O7 to I/O0 A1 A2 A3 A4 1 2 3 4 R/B Figure 28.8 Programming Operation Timing for NAND-Type Flash Memory (1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1497 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller CLE ALE WE RE H'10 H'70 I/O7 to I/O0 Status R/B Figure 28.9 Programming Operation Timing for NAND-Type Flash Memory (2) Page 1498 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.4.5 Section 28 NAND Flash Memory Controller Sector Access Mode In sector access mode, flash memory can be read or programmed in sector units by specifying the sector number of the sector to be accessed. Since 512-byte data is stored in FLDTFIFO and 16-byte control code is stored in FLECFIFO, the DREQ1EN and DREQ0EN bits in FLINTDMACR can be set to transfer by the DMA. Figure 28.10 shows the relationship of DMA transfer between sectors in flash memory (data and control code) and memory on the address space. Address area Flash memory Data (512 bytes) Control code (16 bytes) This module FLDT FIFO Data area DMA (channel 0) transfer FLEC FIFO Control code area DMA (channel 1) transfer Figure 28.10 Relationship between DMA Transfer and Sector (Data and Control Code), and Memory and DMA Transfer R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1499 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller (1) Sector Address Figure 28.11 shows the relationship between the physical sector address of NAND-type flash memory and the address of flash memory. NAND-type flash memory (2048 + 64 bytes) Bit 25 Bit 25 Physical sector address Bit 0 Physical sector address bit (FLADR[25:0]) Row3 Row2 Row1 Bit 0 Col Note: FLADR[1:0] specify the boundary address for column address in the unit of 512 + 16 bytes. When NAND-type flash memory (2048 + 64 bytes) is used, set FLADR[1:0] as follows. 00: 0 byte 01: 512 + 16 bytes 10: 1024 + 32 bytes 11: 1536 + 48 bytes When ADRCNT2 = 0 Row2 Row1 Order of address output to NAND-type flash memory I/O Col Col2 Row1 Row2 Col2 0 0 0 0 0 0 Col1 0 0 0 0 0 0 [Legend] Col: Column address Row: Row address (page address) When ADRCNT2 = 1 (Bits[25:18] are valid.) Row3 Note: When FADRCNT2 = 1, FLADR[25:18] are valid. Set the invalid bit to 0 depending on the capacity of flash memory. Order of address output to NAND-type flash memory I/O Col Col2 Row1 Row2 Row3 Figure 28.11 Relationship between Sector Number and Address Expansion of NAND-Type Flash Memory Page 1500 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 28 NAND Flash Memory Controller Continuous Sector Access A series of sectors can be read or written by specifying the start sector address of NAND-type flash memory and the number of sectors to be transferred. Figure 28.12 shows an example of physical sector specification register and transfer count specification register settings when transferring logical sectors 0 to 40, which are not contiguous because of an unusable sector in NAND-type flash memory. Physical sector 0 Logical sector 0 11 12 13 11 40 40 13 Values specified in registers by the CPU. Physical sector Sector transfer count specification specification (ADR[17:0] in FLADR) (SCTCNT in FLCMDCR) Transfer start 00 12 Sector 0 to sector 11 are transferred 300 12 300 1 13 28 Transfer start Sector 12 is transferred Transfer start Sector 13 to sector 40 are transferred Figure 28.12 Sector Access when Unusable Sector Exists in Continuous Sectors R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1501 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller (3) Flash Memory Access in Sector Access Mode Figures 28.13 and 28.14 show the timing of writing to and reading from the NAND-type flash memory in sector access mode. Figure 28.13 shows the timing of writing to the 1-Gbit large-block flash memory. During the execution of sequential sector access spanning multiple pages, data are written to the flash memory with the timing shown in the figure for every page (2048 + 64 bytes). CE CLE WE ALE RE CA 80h CA PA PA (0-7) (8-11) (0-7) (8-15) 1 2 M-1 M 10h 70h Status read IO R/B M: 2112nd data Figure 28.13 Programming Operation Timing for NAND-Type Flash Memory Page 1502 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller Figure 28.14 shows the timing of reading from the 1-Gbit large-block flash memory. During the execution of sequential sector access spanning multiple pages, data are read from the flash memory with the timing shown in the figure for every page (2048 + 64 bytes). CE CLE WE ALE RE CA 00h CA PA PA (0-7) (8-11) (0-7) (8-15) 30h 1 2 M-1 M IO R/B M: 2112nd data Figure 28.14 Read Timing from NAND-Type Flash Memory (Sector Access Mode) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1503 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.4.6 Status Read This module can read the status register of an AND/NAND-type flash memory. The data in the status register is input through the I/O7 to I/O0 pins and stored in the bits STAT[7:0] in FLBSYCNT, which can be read by the CPU. If a program error or erase error is detected when the status register value is stored in the bits STAT[7:0] in FLBSYCNT, the STERB bit in FLINTDMACR is set to 1 and generates an interrupt to the CPU if the STERINTE bit in FLINTDMACR is enabled. If a status error occurs during continuous sector access, the TREND bit in FLTRCR is set to 1 and the procedure stops. (1) Status Read of NAND-Type Flash Memory The status register of NAND-type flash memory can be read by inputting command H'70 to NAND-type flash memory. If programming is executed in command access mode or sector access mode while the DOSR bit in FLCMDCR is set to 1, this module automatically inputs command H'70 to NAND-type flash memory and reads the status register of NAND-type flash memory. When the status register of NAND-type flash memory is read, the I/O7 to I/O0 pins indicate the following information as described in table 28.3. Table 28.3 Status Read of NAND-Type Flash Memory I/O Status (definition) I/O7 Program protection Description 0: Cannot be programmed 1: Can be programmed I/O6 Ready/busy 0: Busy state 1: Ready state I/O5 to I/O1 Reserved  I/O0 Program/erase 0: Pass 1: Fail Page 1504 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.5 Section 28 NAND Flash Memory Controller Interrupt Sources This module has five interrupt sources: Status error, ready/busy timeout error, transfer end, FIFO0 transfer request, and FIFO1 transfer request. Each of the interrupt sources has its corresponding interrupt flag and the interrupt can be requested independently to the CPU if the interrupt is enabled by the interrupt enable bit. Note that the status error and ready/busy timeout error use the common FLSTE interrupt to the CPU. Table 28.4 NAND Flash Memory Controller Interrupt Requests Interrupt Source Interrupt Flag Enable Bit Description Priority FLSTE interrupt STERB STERINTE Status error High BTOERB RBERINTE Ready/busy timeout error FLTEND interrupt TREND TEINTE Transfer end FLTRQ0 interrupt TRREQF0 TRINTE0 FIFO0 transfer request FLTRQ1 interrupt TRREQF1 TRINTE1 FIFO1 transfer request 28.6 Low DMA Transfer Specifications This module can request DMA transfers separately to the data area FLDTFIFO and control code area FLECFIFO. Table 28.5 summarizes DMA transfer enable or disable states in each access mode. Table 28.5 DMA Transfer Specifications Sector Access Mode Command Access Mode FLDTFIFO DMA transfer enabled DMA transfer enabled FLECFIFO DMA transfer enabled DMA transfer disabled For details on settings of the direct memory access controller, see section 11, Direct Memory Access Controller. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1505 of 3092 SH7268 Group, SH7269 Group Section 28 NAND Flash Memory Controller 28.7 Usage Notes 28.7.1 External Bus Mastership Release Timing This module negates FCE regardless of the busy/ready state when having completed a necessary process. With bit 21 (BUSYON) set to 0 in the common control register (FLCMNCR), this module negates FCE and releases the bus mastership even during the busy state upon completion of the process. With BUSYON = 0, setting bit 24 (DOSR) in the command control register (FLCMDCR) to 1 to read the status enables acquiring the bus mastership even during the busy state. CLE ALE WE RE H'80 H'10 I/O R/B CE Figure 28.15 BUSYON = 0, DOSR = 0 (Writing to Flash Memory) CLE ALE WE RE H'80 H'10 H'70 I/O R/B CE Figure 28.16 BUSYON = 0, DOSR = 1 (Writing to Flash Memory) Page 1506 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 28.7.2 Section 28 NAND Flash Memory Controller Usage Notes for the SNAND Bit When using the SNAND bit in FLCMNCR, only the first command or the second command is corresponded in spite of the setting of the DOCMD1 or DOCMD2 bit in FLCMDCR. When no command or only the first command is issued, 0 should be written in the SNAND bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1507 of 3092 Section 28 NAND Flash Memory Controller Page 1508 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Section 29 USB 2.0 Host/Function Module The USB 2.0 host/function module is a USB controller which provides capabilities as a USB host controller and USB function controller function. This module supports high-speed transfer defined by USB (universal serial bus) Specification 2.0, full-speed transfer, and low-speed transfer when used as the host controller, and supports high-speed transfer and full-speed transfer when used as the function controller. This module has a USB transceiver and supports all of the transfer types defined by the USB specification. This module has an 8-Kbyte buffer memory for data transfer, providing a maximum of ten pipes. Any endpoint numbers can be assigned to PIPE1 to PIPE9, based on the peripheral devices or user system for communication. 29.1 (1) Features Host Controller and Function Controller Supporting USB High-Speed Operation  The USB host controller and USB function controller are incorporated.  The USB host controller and USB function controller can be switched by register settings.  USB transceiver is incorporated. (2)     (3)     Reduced Number of External Pins and Space-Saving Installation On-chip D+ pull-up resistor (during USB function operation) On-chip D+ and D- pull-down resistor (during USB host operation) On-chip D+ and D- terminal resistor (during high-speed operation) On-chip D+ and D- output resistor (during full-speed operation) All Types of USB Transfers Supported Control transfer Bulk transfer Interrupt transfer (high bandwidth transfers not supported) Isochronous transfer (high bandwidth transfers not supported) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1509 of 3092 Section 29 USB 2.0 Host/Function Module (4) SH7268 Group, SH7269 Group Internal Bus Interfaces  Two DMA interface channels are incorporated. (5)      (6) Pipe Configuration On-chip 8-Kbyte buffer memory for USB communications Up to ten pipes can be selected (including the default control pipe) Programmable pipe configuration Endpoint numbers can be assigned flexibly to PIPE1 to PIPE9. Transfer conditions that can be set for each pipe: PIPE0: Control transfer (default control pipe: DCP), 256-byte fixed single buffer PIPE1 and PIPE2: Bulk transfers/isochronous transfer, continuous transfer mode, programmable buffer size (up to 2-Kbytes: double buffer can be specified) PIPE3 to PIPE5: Bulk transfer, continuous transfer mode, programmable buffer size (up to 2-Kbytes: double buffer can be specified) PIPE6 to PIPE9: Interrupt transfer, 64-byte fixed single buffer Features of the USB Host Controller  High-speed transfer (480 Mbps), full-speed transfer (12 Mbps), and low-speed transfer (1.5 Mbps) are supported.  Communications with multiple peripheral devices connected via a single HUB  Automatic response to the reset handshake  Automatic scheduling for SOF and packet transmissions  Programmable intervals for isochronous and interrupt transfers (7) Features of the USB Function Controller  Both high-speed transfer (480 Mbps) and full-speed transfer (12 Mbps) are supported.  Automatic recognition of high-speed operation or full-speed operation based on automatic response to the reset handshake  Control transfer stage control function  Device state control function  Auto response function for SET_ADDRESS request  NAK response interrupt function (NRDY)  SOF interpolation function Page 1510 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (8) Section 29 USB 2.0 Host/Function Module Other Features  Transfer ending function using transaction count  BRDY interrupt event notification timing change function (BFRE)  Function that automatically clears the buffer memory after the data for the pipe specified at the DnFIFO (n = 0 or 1) port has been read (DCLRM)  NAK setting function for response PID generated by end of transfer (SHTNAK) 29.2 Input/Output Pins Table 29.1 shows the pin configuration of the USB. Table 29.1 USB Pin Configuration Category Name Pin Name I/O Function USB bus interface DP D+ I/O of the USB on-chip transceiver USB D+ data I/O This pin should be connected to the D+ pin of the USB bus. USB D- data DM I/O D I/O of the USB on-chip transceiver This pin should be connected to the D- pin of the USB bus. VBUS monitor input VBUS input VBUS Input USB cable connection monitor pin This pin should be connected directly to the VBUS of the USB bus. Whether the VBUS is connected or disconnected can be detected. If this pin is not connected with the VBUS of the USB bus, it should be supplied with 5 V. It should be supplied with 5 V also when the host controller function is selected. Note: The VBUS cannot be supplied to connected peripheral devices. Reference Reference input resistor REFRIN Input Reference resistor connection pin This pin should be connected to USBAPVss through a 5.6 k 1% resistor (SH7268 and SH7269 products in QFP packages). This pin should be connected to Vss through a 5.6 kΩ ±1% resistor (SH7269 products in BGA packages). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1511 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Category Name Pin Name I/O Function Clock Crystal resonator for USB_X1 USB/external clock USB_X2 Power supply Transceiver block analog pin power supply USBAPVcc Input Power supply for pins Transceiver block analog pin ground* USBAPVss Input Ground for pins Transceiver block digital pin power supply* USBDPVcc Input Power supply for pins Transceiver block digital pin ground* USBDPVss Input Ground for pins Transceiver block analog core power supply USBAVcc Input Power supply for the core Transceiver block USBAVss analog core ground* Input Ground for the core Transceiver block digital core power supply* USBDVcc Input Power supply for the core Transceiver block USBDVss digital core ground* Input Ground for the core USB 480 MHz power supply* USBUVcc Input Power supply for 480-MHz operation block USB 480 MHz ground* USBUVss Input Ground for 480-MHz operation block Note: * Input This pin should be connected to crystal resonator for the USB. This pin can also be Output used for external clock input. SH7269 (BGA) Group products do not have this pin. Page 1512 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.3 Section 29 USB 2.0 Host/Function Module Register Description Table 29.2 shows the register configuration. Table 29.2 Register Configuration Register Name Abbreviation R/W Address Access Size System configuration control register SYSCFG R/W H'E801 0000 16 CPU bus wait setting register BUSWAIT R/W H'E801 0002 16 System configuration status register SYSSTS R H'E801 0004 16 Device state control register DVSTCTR R/W H'E801 0008 16 Test mode register TESTMODE R/W H'E801 000C 16 DMA0-FIFO bus configuration register D0FBCFG R/W H'E801 0010 16 DMA1-FIFO bus configuration register D1FBCFG R/W H'E801 0012 16 CFIFO port register CFIFO R/W H'E801 0014 8, 16, 32 D0FIFO port register D0FIFO R/W H'E801 0018 8, 16, 32 D1FIFO port register D1FIFO R/W H'E801 001C 8, 16, 32 CFIFO port select register CFIFOSEL R/W H'E801 0020 16 CFIFO port control register CFIFOCTR R/W H'E801 0022 16 D0FIFO port select register D0FIFOSEL R/W H'E801 0028 16 D0FIFO port control register D0FIFOCTR R/W H'E801 002A 16 D1FIFO port select register D1FIFOSEL R/W H'E801 002C 16 D1FIFO port control register D1FIFOCTR R/W H'E801 002E 16 Interrupt enable register 0 INTENB0 R/W H'E801 0030 16 Interrupt enable register 1 INTENB1 R/W H'E801 0032 16 BRDY interrupt enable register BRDYENB R/W H'E801 0036 16 NRDY interrupt enable register NRDYENB R/W H'E801 0038 16 BEMP interrupt enable register BEMPENB R/W H'E801 003A 16 SOF output configuration register SOFCFG R/W H'E801 003C 16 Interrupt status register 0 INTSTS0 R/W H'E801 0040 16 Interrupt status register 1 INTSTS1 R/W H'E801 0042 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1513 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Register Name Abbreviation R/W Address Access Size BRDY interrupt status register BRDYSTS R/W H'E801 0046 16 NRDY interrupt status register NRDYSTS R/W H'E801 0048 16 BEMP interrupt status register BEMPSTS R/W H'E801 004A 16 Frame number register FRMNUM R/W H'E801 004C 16 Frame number register UFRMNUM R H'E801 004E 16 USB address register USBADDR R H'E801 0050 16 USB request type register USBREQ R/W H'E801 0054 16 USB request value register USBVAL R/W H'E801 0056 16 USB request index register USBINDX R/W H'E801 0058 16 USB request length register USBLENG R/W H'E801 005A 16 DCP configuration register DCPCFG R/W H'E801 005C 16 DCP maximum packet size register DCPMAXP R/W H'E801 005E 16 DCP control register DCPCTR R/W H'E801 0060 16 Pipe window select register PIPESEL R/W H'E801 0064 16 Pipe configuration register PIPECFG R/W H'E801 0068 16 Pipe buffer setting register PIPEBUF R/W H'E801 006A 16 Pipe maximum packet size register PIPEMAXP R/W H'E801 006C 16 Pipe cycle control register PIPEPERI R/W H'E801 006E 16 Pipe 1 control register PIPE1CTR R/W H'E801 0070 16 Pipe 2 control register PIPE2CTR R/W H'E801 0072 16 Pipe 3 control register PIPE3CTR R/W H'E801 0074 16 Pipe 4 control register PIPE4CTR R/W H'E801 0076 16 Pipe 5 control register PIPE5CTR R/W H'E801 0078 16 Pipe 6 control register PIPE6CTR R/W H'E801 007A 16 Pipe 7 control register PIPE7CTR R/W H'E801 007C 16 Pipe 8 control register PIPE8CTR R/W H'E801 007E 16 Pipe 9 control register PIPE9CTR R/W H'E801 0080 16 Pipe 1 transaction counter enable register PIPE1TRE R/W H'E801 0090 16 Pipe 1 transaction counter register PIPE1TRN R/W H'E801 0092 16 Pipe 2 transaction counter enable register PIPE2TRE R/W H'E801 0094 16 Page 1514 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Register Name Abbreviation R/W Address Access Size Pipe 2 transaction counter register PIPE2TRN R/W H'E801 0096 16 Pipe 3 transaction counter enable register PIPE3TRE R/W H'E801 0098 16 Pipe 3 transaction counter register PIPE3TRN R/W H'E801 009A 16 Pipe 4 transaction counter enable register PIPE4TRE R/W H'E801 009C 16 Pipe 4 transaction counter register PIPE4TRN R/W H'E801 009E 16 Pipe 5 transaction counter enable register PIPE5TRE R/W H'E801 00A0 16 Pipe 5 transaction counter register PIPE5TRN R/W H'E801 00A2 16 Device address 0 configuration register DEVADD0 R/W H'E801 00D0 16 Device address 1 configuration register DEVADD1 R/W H'E801 00D2 16 Device address 2 configuration register DEVADD2 R/W H'E801 00D4 16 Device address 3 configuration register DEVADD3 R/W H'E801 00D6 16 Device address 4 configuration register DEVADD4 R/W H'E801 00D8 16 Device address 5 configuration register DEVADD5 R/W H'E801 00DA 16 Device address 6 configuration register DEVADD6 R/W H'E801 00DC 16 Device address 7 configuration register DEVADD7 R/W H'E801 00DE 16 Device address 8 configuration register DEVADD8 R/W H'E801 00E0 16 Device address 9 configuration register DEVADD9 R/W H'E801 00E2 16 Device address A configuration register DEVADDA R/W H'E801 00E4 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1515 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.1 System Configuration Control Register (SYSCFG) SYSCFG is a register that enables high-speed operation, selects the host controller function or function controller function, controls the DP and DM pins, selects an input clock, and enables operation of this module. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 — — — — — SCKE — — HSE Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W Bit Initial Bit Name Value 15 to 11  All 0 R/W Description R Reserved 6 5 4 3 DCFM DRPD DPRPU UCKF SEL 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0 UCKP UPLLE USBE SEL 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 SCKE 0 R/W USB Module Clock Enable Stops or enables supplying the clock signal to this module. 0: Stops supplying the clock signal to the USB module. 1: Enables supplying the clock signal to the USB module. When this bit is 0, only this register and the BUSWAIT register allow both writing and reading; the other registers in the USB module allows reading only. When modifying this bit while 12-MHz clock input is selected by UCKFSEL, take care on following points.   9, 8  All 0 R Before setting this bit to 1, wait for at least 1 ms after setting UPLLE to 1. When transition to software standby or USB module standby mode is made, set this bit to 0. Reserved These bits are always read as 0. The write value should always be 0. Page 1516 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Initial Bit Name Value R/W Description 7 HSE R/W High-Speed Operation Enable 0 0: High-speed operation is disabled When the function controller function is selected: Only full-speed operation is enabled. When the host controller function is selected: Fullspeed or low-speed operation is enabled. 1: High-speed operation is enabled (detected by this module) (1) When the host controller function is selected When HSE = 0, the USB port performs low-speed or full-speed operation. Set HSE to 0 when connection of a low-speed peripheral device to the USB port has been detected. When HSE = 1, this module executes the reset handshake protocol, and automatically allows the USB port to perform high-speed or full-speed operation according to the protocol execution result. This bit should be modified after detecting device connection (after detecting the ATTCH interrupt) and before executing a USB bus reset (before setting USBRESET to 1). (2) When the function controller function is selected When HSE = 0, this module performs full-speed operation. When HSE = 1, this module executes the reset handshake protocol, and automatically performs highspeed or full-speed operation according to the protocol execution result. This bit should be modified while DPRPU is 0. 6 DCFM 0 R/W Controller Function Select Selects the host controller function or function controller function. 0: Function controller function is selected. 1: Host controller function is selected. This bit should be modified while DPRPU and DPRD are 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1517 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Initial Bit Name Value R/W Description 5 DRPD R/W D/D Line Resistor Control 0 Enables or disables pulling down D+ and D- lines when the host controller function is selected. 0: Pulling down the lines is disabled. 1: Pulling down the lines is enabled. This bit should be set to 1 if the host controller function is selected, and should be set to 0 if the function controller function is selected. 4 DPRPU 0 R/W D Line Resistor Control Enables or disables pulling up D+ line when the function controller function is selected. 0: Pulling up the line is disabled. 1: Pulling up the line is enabled. Setting this bit to 1 when the function controller function is selected allows this module to pull up the D+ line to 3.3 V, thus notifying the USB host of connection. Modifying this bit from 1 to 0 allows this module to cancel pulling up the D+ line, thus notifying the USB host of disconnection. This bit should be set to 1 if the function controller function is selected, and should be set to 0 if the host controller function is selected. Note: Set this bit to 0 when the USB is disconnected. Include the following processing when this bit is changed from 1 to 0. (1) Set the DPRPU bit to 0. (2) Wait for at least 1 s. (3) Set the DCFM bit to 1. (4) Wait for at least 200 ns. (5) Set the DCFM bit to 0. 3 UCKFSEL 0 R/W Input Clock Frequency Select Selects the frequency of the clock input to this module. 0: 48-MHz clock input is selected. 1: 12-MHz clock input is selected. This bit should be modified while SCKE is 0. Note: This bit should be 1 when EXTAL is selected by UCKPSEL. Page 1518 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Initial Bit Name Value R/W Description 2 UCKPSEL 0 R/W Clock Input Pin Select Selects the clock input pin to this module. 0: USB_X1 is selected. 1: EXTAL is selected. This bit should be modified while SCKE is 0. 1 UPLLE 0 R/W USB Internal PLL Operation Enable Enables or disables operation of USB internal PLL when 12-MHz clock input is selected by UCKFSEL. 0: USB internal PLL operation is disabled. 1: USB internal PLL operation is enabled. When 48-MHz clock input is selected by UCKFSEL, setting this bit is invalid. This bit should be modified while SCKE is 0. When 12-MHz clock input is selected by UCKFSEL and a transition to software standby mode or USB module standby mode is made, set this bit to 0. 0 USBE 0 R/W USB Module Operation Enable Enables or disables operation of this module. 0: USB module operation is disabled. 1: USB module operation is enabled. Modifying this bit from 1 to 0 initializes some register bits as listed in tables 29.3 and 29.4. This bit should be modified while SCKE is 1. When the host controller function is selected, this bit should be set to 1 after setting DRPD to 1, eliminating LNST bit chattering, and checking that the USB bus has been settled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1519 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.3 Register Bits Initialized by Writing USBE = 0 (when Function Controller Function is Selected) Register Name Bit Name Remarks SYSSTS LNST The value is retained when the host controller function is selected. DVSTCTR RHST INTSTS0 DVSQ The value is retained when the host controller function is selected. USBADDR USBADDR The value is retained when the host controller function is selected. USEREQ BRequest, bmRequestType The values are retained when the host controller function is selected. USBVAL wValue The value is retained when the host controller function is selected. USBINDX wIndex The value is retained when the host controller function is selected. USBLENG wLength The value is retained when the host controller function is selected. Table 29.4 Register Bits Initialized by Writing USBE = 0 (when Host Controller Function is Selected) Register Name Bit Name DVSTCTR RHST FRMNUM FRNM The value is retained when the function controller function is selected. UFRMNUM UFRNM The value is retained when the function controller function is selected. Page 1520 of 3092 Remarks R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.3.2 Section 29 USB 2.0 Host/Function Module CPU Bus Wait Setting Register (BUSWAIT) BUSWAIT is a register that specifies the number of wait cycles to be inserted during an access from the CPU to this module. This register can be modified even when the SCKE bit in SYSCFG is 0. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 — — — — — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 3 2 1 0 BWAIT[3:0] 1 R/W 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 15 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 BWAIT[3:0] 1111 R/W CPU Bus Access Wait Specifies the number of wait cycles to be inserted during an access to a register (the same number applies to an access to a FIFO port). For details, see section 29.4.1 (5), Register Access Wait Control. 0000: 0 wait cycles (2 access cycles) : 0010: 2 wait cycles (4 access cycles) : 0100: 4 wait cycles (6 access cycles) : 1111: 15 wait cycles (17 access cycles) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1521 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.3 System Configuration Status Register (SYSSTS) SYSSTS is a register that monitors the line status (D + and D  lines) of the USB data bus. This register is initialized by a power-on reset or a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 — — — — — — — — — — — — — — LNST[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R Undefined 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Undefined* Undefined* Bit Bit Name 15 to 11  R Initial Value R/W Description All 0 Reserved R R 0 R These bits are always read as 0. The write value should always be 0.  10 Undefined R Reserved The read value is undefined. The write value should always be 0.  9 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 LNST[1:0] Undefined* R USB Data Line Status Monitor Indicates the status of the USB data bus lines (D+ and D-) as shown in table 29.5. These bits should be read after setting DPRPU to 1 to notify connection when the function controller function is selected; whereas after setting DRPD to 1 to enable pulling down the lines when the host controller function is selected. Note: * Depends on the DP and DM pin status. Page 1522 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.5 USB Data Bus Line Status LNST[1] LNST[0] During Low-Speed Operation (only when Host Controller Function is Selected) 0 0 SE0 SE0 Squelch Squelch 0 1 K state J state Unsquelch Chirp J 1 0 J state K state Invalid Chirp K 1 1 SE1 SE1 Invalid Invalid [Legend] Chirp: Squelch: Unsquelch: Chirp J: Chirp K: 29.3.4 During FullSpeed Operation During HighSpeed Operation During Chirp Operation The reset handshake protocol (RHSP) is being executed in high-speed operation enabled state (the HSE bit in SYSCFG is set to 1). SE0 or idle state High-speed J state or high-speed K state Chirp J state Chirp K state Device State Control Register (DVSTCTR) DVSTCTR is a register that controls and confirms the state of the USB data bus. This register is initialized by a power-on reset. After a USB bus reset, only the WKUP bit is initialized. Bit: 15 14 13 12 11 10 9 — — — — — — — WKUP RWUPE USBRSTRESUME UACT — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W* 0 R Bit Bit Name Initial Value R/W 15 to 9  All 0 R 8 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 2 1 0 RHST[2:0] 0 R 0 R 0 R Description Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1523 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 8 WKUP 0 R/W* Wakeup Output Enables or disables outputting the remote wakeup signal (resume signal) to the USB bus when the function controller function is selected. 0: Remote wakeup signal is not output. 1: Remote wakeup signal is output. The module controls the output time of a remote wakeup signal. When this bit is set to 1, this module clears this bit to 0 after outputting the 10-ms K state. According to the USB specification, the USB bus idle state must be kept for 5 ms or longer before a remote wakeup signal is output. If this module writes 1 to this bit right after detection of suspended state, the K state will be output after 2 ms. Note: Do not write 1 to this bit, unless the device state is in the suspended state (the DVSQ bit in the INTSTS0 register is set to 1xx) and the USB host enables the remote wakeup signal. When this bit is set to 1, the internal clock must not be stopped even in the suspended state (write 1 to this bit while SCKE is 1). This bit should be set to 0 if the host controller function is selected. Page 1524 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 RWUPE 0 R/W Remote Wakeup Detection Enable Enables or disables the downstream port peripheral device to use the remote wakeup function (resume signal output) when the host controller function is selected. 0: Downstream port remote wakeup is disabled. 1: Downstream port remote wakeup is enabled. With this bit set to 1, on detecting the remote wakeup signal, this module detects the resume signal (Kstate for 2.5 s) from the downstream port device and performs the resume process (drives the port to the K-state). With this bit set to 0, this module ignores the detected remote wakeup signal (K-state) from the peripheral device connected to the downstream port. While this bit is 1, the internal clock should not be stopped even in the suspended state (SCKE should be set to 1). Also note that the USB bus should not be reset from the suspended state (USBRST should not be set to 1); it is prohibited by USB Specification 2.0. This bit should be set to 0 if the function controller function is selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1525 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 6 USBRST 0 R/W Bus Reset Output Controls the USB bus reset signal output when the host controller function is selected. 0: USB bus reset signal is not output. 1: USB bus reset signal is output. When the host controller function is selected, setting this bit to 1 allows this module to drive the USB port to SE0 to reset the USB bus. Here, this module performs the reset handshake protocol if the HSE bit is 1. This module continues outputting SE0 while USBRST is 1 (until 0 is written to USBRST). USBRST should be 1 (= USB bus reset period) for the time defined by USB Specification 2.0. Writing 1 to this bit during communication (UACT = 1) or during the resume process (RESUME = 1) prevents this module from starting the USB bus reset process until both UACT and RESUME become 0. Write 1 to the UACT bit simultaneously with the end of the USB bus reset process (writing 0 to USBRST). This bit should be set to 0 if the function controller function is selected. 5 RESUME 0 R/W Resume Output Controls the resume signal output when the host controller function is selected. 0: Resume signal is not output. 1: Resume signal is output. Setting this bit to 1 allows this module to drive the port to the K-state and output the resume signal. This module continues outputting K-state while RESUME is 1 (until 0 is written to RESUME). RESUME should be 1 (= resume period) for the time defined by USB Specification 2.0. This bit should be set to 1 in the suspended state. Write 1 to the UACT bit simultaneously with the end of the resume process (writing 0 to RESUME). This bit should be set to 0 if the function controller function is selected. Page 1526 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 4 UACT 0 R/W USB Bus Enable Enables operation of the USB bus (controls the SOF or SOF packet transmission to the USB bus) when the host controller function is selected. 0: Downstream port is disabled (SOF/SOF transmission is disabled). 1: Downstream port is enabled (SOF/SOF transmission is enabled). With this bit set to 1, this module puts the USB port to the USB-bus enabled state and performs SOF output and data transmission and reception. This module starts outputting SOF/SOF within 1 () frame after 1 has been written to UACT. With this bit set to 0, this module enters the idle state after outputting SOF/SOF. This module sets this bit to 0 on any of the following conditions.  A DTCH interrupt is detected during communication (while UACT = 1).  An EOFERR interrupt is detected during communication (while UACT = 1). Writing 1 to this bit should be done at the end of the USB bus reset process (writing 0 to USBRST) or at the end of the resume process from the suspended state (writing 0 to RESUME). This bit should be set to 0 if the function controller function is selected. 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1527 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 2 to 0 RHST[2:0] 000 R Reset Handshake Indicates the status of the reset handshake. (1) When the host controller function is selected 000: Communication speed not determined (powered state or no connection) 1xx: Reset handshake in progress 001: Low-speed connection 010: Full-speed connection 011: High-speed connection These bits indicate 100 after 1 has been written to USBRST. If HSE has been set to 1, these bits indicate 111 as soon as this module detects Chirp-K from the peripheral device. This module fixes the value of the RHST bits when 0 is written to USBRST and this module completes SE0 driving. When the UTST bits are set to 1xxx (when a host test mode is specified), the RHST bits indicate 011. (2) When the function controller function is selected 000: Communication speed not determined 100: Reset handshake in progress 010: Full-speed connection 011: High-speed connection If HSE has been set to 1, these bits indicate 100 as soon as this module detects the USB bus reset. Then, these bits indicate 011 as soon as this module outputs Chirp-K and detects Chirp-JK from the USB host three times. If the connection speed is not fixed to high speed within 2.5 ms after Chirp-K output, these bits indicate 010. If HSE has been set to 0, these bits indicate 010 as soon as this module detects the USB bus reset. A DVST interrupt is generated as soon as this module detects the USB bus reset and then the value of the RHST bits is fixed to 010 or 011. Note: * Only 1 can be written. Page 1528 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.3.5 Section 29 USB 2.0 Host/Function Module Test Mode Register (TESTMODE) TESTMODE is a register that controls the USB test signal output during high-speed operation. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 — — — — — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 15 to 9  All 0 R 3 2 1 0 UTST[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 8  1 R Reserved This bit is always read as 1. The write value should always be 1. 7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 UTST[3:0] 0000 R/W Test Mode This module outputs the USB test signals during the high-speed operation, when these bits are written appropriate value. Table 29.6 shows test mode operation of this module. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1529 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 3 to 0 UTST[3:0] 0000 R/W (1) When the host controller function is selected These bits can be set after writing 1 to DRPD. This module outputs waveforms when both DRPD and UACT are set to 1. This module also performs highspeed termination after the UTST bits are written to.  Procedure for setting the UTST bits 1. Power-on reset. 2. Start the clock supply (Set SCKE to 1 after the crystal oscillation and the PLL for USB are settled). 3. Set DCFM and DRPD to 1 (setting HSE to 1 is not required). 4. Set USBE to 1. 5. Set the UTST bits to the appropriate value according to the test specifications. 6. Set the UACT bit to 1.  Procedure for modifying the UTST bits 1. (In the state after executing step 6 above) Set UACT and USBE to 0. 2. Set USBE to 1. 3. Set the UTST bits to the appropriate value according to the test specifications. 4. Set the UACT bit to 1. When these bits are set to Test_SE0_NAK (1011), this module does not output the SOF packet even when 1 is set to UACT. When these bits are set to Test_Force_Enable (1101), this module outputs the SOF packet when 1 is set to UACT. In this test mode, this module does not perform hardware control consequent to detection of high-speed disconnection (detection of the DTCH interrupt). When setting the UTST bits, the PID bits for all the pipes should be set to NAK. To return to normal USB communication after a test mode has been set and executed, a power-on reset should be applied. Page 1530 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 3 to 0 UTST[3:0] 0000 R/W (2) When the function controller function is selected The appropriate value should be set to these bits according to the SetFeature request from the USB host during high-speed communication. This module does not make a transition to the suspended state while these bits are 0001 to 0100. Table 29.6 Test Mode Operation UTST Bit Setting Test Mode When Function Controller Function is Selected When Host Controller Function is Selected Normal operation 0000 0000 Test_J 0001 1001 Test_K 0010 1010 Test_SE0_NAK 0011 1011 Test_Packet 0100 1100 Test_Force_Enable  1101 Reserved 0101 to 0111 1110 to 1111 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1531 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) D0FBCFG is a register that controls DMA0-FIFO bus accesses. D1FBCFG is a register that controls DMA1-FIFO bus accesses. These registers are initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — — — TENDE — — — — Initial value: 0 R/W: R 0 R 0 R 0 R Bit Bit Name 15 to 12  Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R Initial Value R/W Description All 0 R Reserved R R 0 R/W Undefined Undefined Undefined Undefined R R R R These bits are always read as 0. The write value should always be 0. 11 to 5  Undefined R Reserved The read value is undefined. The write value should always be 0. 4 TENDE 0 R/W DMA Transfer End Sampling Enable Controls acceptance of DMA transfer end signal output from the direct memory access controller on completion of a DMA transfer. For details, see section 29.4.4 (3), DMA Transfers (D0FIFO/D1FIFO Port). 0: DMA transfer end signal is not sampled. 1: DMA transfer end signal is sampled. For a DMA transfer size of 16 bytes, clear the TENDE bit to 0. 3 to 0  Undefined R Reserved The read value is undefined. The write value should always be 0. Page 1532 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.3.7 Section 29 USB 2.0 Host/Function Module FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) CFIFO, D0FIFO and D1FIFO are port registers that are used to read data from the FIFO buffer memory and writing data to the FIFO buffer memory. There are three FIFO ports: the CFIFO, D0FIFO and D1FIFO ports. Each FIFO port is configured of a port register (CFIFO, D0FIFO, D1FIFO) that handles reading of data from the FIFO buffer memory and writing of data to the FIFO buffer memory, a select register (CFIFOSEL, D0FIFOSEL, D1FIFOSEL) that is used to select the pipe assigned to the FIFO port, and a control register (CFIFOCTR, D0FIFOCTR, D1FIFOCTR). Each FIFO port has the following features.  The DCP FIFO buffer should be accessed through the CFIFO port.  Accessing the FIFO buffer using DMA transfer should be performed through the D0FIFO or D1FIFO port.  The D1FIFO and D0FIFO ports can be accessed also by the CPU.  When using functions specific to the FIFO port, the pipe number (selected pipe) specified by the CURPIPE bits cannot be changed (when the DMA transfer function is used, etc.).  Registers configuring a FIFO port do not affect other FIFO ports.  The same pipe should not be assigned to two or more FIFO ports.  There are two FIFO buffer states: the access right is on the CPU side and it is on the SIE side. When the FIFO buffer access right is on the SIE side, the FIFO buffer cannot be accessed from the CPU. These registers are initialized by a power-on reset. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIFOPORT[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W FIFOPORT[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 1533 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name 31 to 0 FIFOPORT [31:0] Initial Value R/W Description All 0 R/W FIFO Port Accessing these bits allow reading the received data from the FIFO buffer or writing the transmit data to the FIFO buffer. These bits can be accessed only while the FRDY bit in each control register (CFIFOCTR, D0FIFOCTR, or D1FIFOCTR) is 1. The valid bits in this register depend on the settings of the MBW bits (access bit width setting) and BIGEND bit (endian setting) as shown in tables 29.7 to 29.9. Table 29.7 Endian Operation in 32-Bit Access (when MBW = 10) BIGEND Bit Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0 0 N + 3 address N + 2 address N + 1 address N + 0 address 1 N + 0 address N + 1 address N + 2 address N + 3 address Table 29.8 Endian Operation in 16-Bit Access (when MBW = 01) BIGEND Bit 0 Bits 23 to 16 Writing: invalid, reading: prohibited* 1 Note: Bits 31 to 24 N + 0 address * N + 1 address Bits 15 to 8 Bits 7 to 0 N + 1 address N + 0 address Writing: invalid, reading: prohibited* Reading data from the invalid bits in a word or byte unit is prohibited. Table 29.9 Endian Operation in 8-Bit Access (when MBW = 00) BIGEND Bit 0 Bits 23 to 16 Bits 15 to 8 Writing: invalid, reading: prohibited* 1 Note: Bits 31 to 24 N + 0 address * Bits 7 to 0 N + 0 address Writing: invalid, reading: prohibited* Reading data from the invalid bits in a word or byte unit is prohibited. Page 1534 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.3.8 Section 29 USB 2.0 Host/Function Module FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL) CFIFOSEL, D0FIFOSEL and D1FIFOSEL are registers that assign the pipe to the FIFO port, and control access to the corresponding port. The same pipe should not be specified by the CURPIPE bits in CFIFOSEL, D0FIFOSEL and D1FIFOSEL. When the CURPIPE bits in D0FIFOSEL and D1FIFOSEL are cleared to B'000, no pipe is selected. The pipe number should not be changed while the DMA transfer is enabled. These registers are initialized by a power-on reset. (1) CFIFOSEL Bit: 15 RCNT Initial value: 0 R/W: R/W 14 13 12 REW — — 0 R/W* 0 R 0 R 11 10 9 8 7 6 5 4 MBW[1:0] — BIGEND — — ISEL — 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 RCNT 0 R/W Read Count Mode 3 2 1 0 CURPIPE[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Specifies the read mode for the value in the DTLN bits in CFIFOCTR. 0: The DTLN bit is cleared when all of the receive data has been read from the CFIFO. (In double buffer mode, the DTLN bit value is cleared when all the data has been read from a single plane.) 1: The DTLN bit is decremented when the receive data is read from the CFIFO. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1535 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 14 REW 0 R/W* Buffer Pointer Rewind Specifies whether or not to rewind the buffer pointer. 0: The buffer pointer is not rewound. 1: The buffer pointer is rewound. When the selected pipe is in the receiving direction, setting this bit to 1 while the FIFO buffer is being read allows re-reading the FIFO buffer from the first data (in double buffer mode, re-reading the currently-read FIFO buffer plane from the first data is allowed). Do not set REW to 1 simultaneously with modifying the CURPIPE bits. Before setting REW to 1, be sure to check that FRDY is 1. To re-write to the FIFO buffer again from the first data for the pipe in the transmitting direction, use the BCLR bit. 13, 12  Page 1536 of 3092 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 11, 10 MBW[1:0] 00 R/W CFIFO Port Access Bit Width Specifies the bit width for accessing the CFIFO port. 00: 8-bit width 01: 16-bit width 10: 32-bit width 11: Setting prohibited Once reading data is started after setting these bits, these bits should not be modified until all the data has been read. When the selected pipe is in the receiving direction, these bits should be set in the following timing:  Set the CURPIPE and MBW bits simultaneously.  When the DCP is selected (CURPIPE = B'000), set the ISEL and MBW bits simultaneously. For details, see section 29.4.4, FIFO Buffer Memory. When the selected pipe is in the transmitting direction, the bit width cannot be changed from the 8bit width to the 16-/32-bit width or from the 16-bit width to the 32-bit width while data is being written to the buffer memory. 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 BIGEND 0 R/W CFIFO Port Endian Control Specifies the byte endian for the CFIFO port. 0: Little endian 1: Big endian 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1537 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 5 ISEL 0 R/W CFIFO Port Access Direction When DCP is Selected 0: Reading from the buffer memory is selected 1: Writing to the buffer memory is selected After writing to this bit with the DCP being a selected pipe, read this bit to check that the written value agrees with the read value before proceeding to the next process. Even if an attempt is made to modify the setting of this bit during access to the FIFO buffer, the current access setting is retained until the access is completed. Then, the modification becomes effective thus enabling continuous access. Set this bit and the CURPIPE bits simultaneously. 4  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 1538 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Initial Value Bit Bit Name 3 to 0 CURPIPE[3:0] 0000 R/W Description R/W CFIFO Port Access Pipe Specification Specifies the pipe number for reading or writing data through the CFIFO port. 0000: DCP 0001: Pipe 1 0010: Pipe 2 0011: Pipe 3 0100: Pipe 4 0101: Pipe 5 0110: Pipe 6 0111: Pipe 7 1000: Pipe 8 1001: Pipe 9 Other than above: Setting prohibited After writing to these bits, read these bits to check that the written value agrees with the read value before proceeding to the next process. Do not set the same pipe number to the CURPIPE bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL. Even if an attempt is made to modify the setting of these bits during access to the FIFO buffer, the current access setting is retained until the access is completed. Then, the modification becomes effective thus enabling continuous access. Note: * Only 0 can be read and 1 can be written. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1539 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module (2) D0FIFOSEL, D1FIFOSEL Bit: 15 RCNT Initial value: 0 R/W: R/W 14 13 12 REW DCLRM DREQE 0 R/W* 0 R/W 0 R/W 11 10 MBW[1:0] 0 R/W 0 R/W 9 8 7 6 5 4 — BIG END — — — — 0 R 0 R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 RCNT 0 R/W Read Count Mode 3 2 1 0 CURPIPE[3:0] 0 R/W 0 R/W 0 R/W 0 R/W Specifies the read mode for the value in the DTLN bits in DnFIFOCTR. 0: The DTLN bit is cleared when all of the receive data has been read from the DnFIFO. (In double buffer mode, the DTLN bit value is cleared when all the data has been read from a single plane.) 1: The DTLN bit is decremented when the receive data is read from the DnFIFO. When accessing DnFIFO with the BFRE bit set to 1, set this bit to 0. 14 REW 0 R/W* Buffer Pointer Rewind Specifies whether or not to rewind the buffer pointer. 0: The buffer pointer is not rewound. 1: The buffer pointer is rewound. When the selected pipe is in the receiving direction, setting this bit to 1 while the FIFO buffer is being read allows re-reading the FIFO buffer from the first data (in double buffer mode, re-reading the currentlyread FIFO buffer plane from the first data is allowed). Do not set REW to 1 simultaneously with modifying the CURPIPE bits. Before setting REW to 1, be sure to check that FRDY is 1. To re-write to the FIFO buffer again from the first data for the pipe in the transmitting direction, use the BCLR bit. Page 1540 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 13 DCLRM 0 R/W Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read Enables or disables the buffer memory to be cleared automatically after data has been read out using the selected pipe. 0: Auto buffer clear mode is disabled. 1: Auto buffer clear mode is enabled. With this bit set to 1, this module sets BCLR to 1 for the FIFO buffer of the selected pipe on receiving a zero-length packet while the FIFO buffer assigned to the selected pipe is empty, or on receiving a short packet and reading the data while BFRE is 1. When using this module with the BRDYM bit set to 1, set this bit to 0. 12 DREQE 0 R/W DMA Transfer Request Enable Enables or disables the DMA transfer request to be issued. 0: Request disabled 1: Request enabled Before setting this bit to 1 to enable the DMA transfer request to be issued, set the CURPIPE bits. Before modifying the CURPIPE bit setting, set this bit to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1541 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 11, 10 MBW[1:0] 00 R/W FIFO Port Access Bit Width Specifies the bit width for accessing the DnFIFO port. 00: 8-bit width 01: 16-bit width 10: 32-bit width 11: Setting prohibited Once reading data is started after setting these bits, these bits should not be modified until all the data has been read. When the selected pipe is in the receiving direction, set the CURPIPE and MBW bits simultaneously. For details, see section 29.4.4, FIFO Buffer Memory. When the selected pipe is in the transmitting direction, the bit width cannot be changed from the 8-bit width to the 16-/32-bit width or from the 16-bit width to the 32-bit width while data is being written to the buffer memory. 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 BIGEND 0 R/W FIFO Port Endian Control Specifies the byte endian for the DnFIFO port. 0: Little endian 1: Big endian 7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1542 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Initial Value Bit Bit Name 3 to 0 CURPIPE[3:0] 0000 R/W Description R/W FIFO Port Access Pipe Specification Specifies the pipe number for reading or writing data through the D0FIFO/D1FIFO port. 0000: No pipe specified 0001: Pipe 1 0010: Pipe 2 0011: Pipe 3 0100: Pipe 4 0101: Pipe 5 0110: Pipe 6 0111: Pipe 7 1000: Pipe 8 1001: Pipe 9 Other than above: Setting prohibited After writing to these bits, read these bits to check that the written value agrees with the read value before proceeding to the next process. Do not set the same pipe number to the CURPIPE bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL. Even if an attempt is made to modify the setting of these bits during access to the FIFO buffer, the current access setting is retained until the access is completed. Then, the modification becomes effective thus enabling continuous access. Note: 29.3.9 * Only 0 can be read and 1 can be written. FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) CFIFOCTR, D0FIFOCTR and D1FIFOCTR are registers that determine whether or not writing to the buffer memory has been finished, the buffer accessed from the CPU has been cleared, and the FIFO port is accessible. CFIFOCTR, D0FIFOCTR, and D1FIFOCTR are used for the corresponding FIFO ports. These registers are initialized by a power-on reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1543 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit: 15 BVAL 14 13 12 BCLR FRDY — 0 R 0 R Initial value: 0 0 R/W: R/W*2 R/W*1 Bit 15 Bit Name BVAL Initial Value 0 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R DTLN[11:0] 0 R 0 R 0 R R/W R/W* 0 R 0 R 0 R 0 R Description 2 Buffer Memory Valid Flag This bit should be set to 1 when data has been completely written to the FIFO buffer on the CPU side for the pipe selected using the CURPIPE bits (selected pipe). 0: Invalid 1: Writing ended When the selected pipe is in the transmitting direction, set this bit to 1 in the following cases. Then, this module switches the FIFO buffer from the CPU side to the SIE side, enabling transmission.  To transmit a short packet, set this bit to 1 after data has been written.  To transmit a zero-length packet, set this bit to 1 before data is written to the FIFO buffer.  Set this bit to 1 after the number of data bytes has been written for the pipe in continuous transfer mode, where the number is a natural integer multiple of the maximum packet size and less than the buffer size. When the data of the maximum packet size has been written for the pipe in non-continuous transfer mode, this module sets this bit to 1 and switches the FIFO buffer from the CPU side to the SIE side, enabling transmission. When the selected pipe is in the transmitting direction, if 1 is written to BVAL and BCLR bits simultaneously, this module clears the data that has been written before it, enabling transmission of a zero-length packet. Writing 1 to this bit should be done while FRDY indicates 1 (set by this module). When the selected pipe is in the receiving direction, do not set this bit to 1. Page 1544 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 14 Bit Name BCLR Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description 1 R/W* CPU Buffer Clear This bit should be set to 1 to clear the FIFO buffer on the CPU side for the selected pipe. 0: Invalid 1: Clears the buffer memory on the CPU side. When double buffer mode is set for the FIFO buffer assigned to the selected pipe, this module clears only one plane of the FIFO buffer even when both planes are read-enabled. When the selected pipe is the DCP, setting BCLR to 1 allows this module to clear the FIFO buffer regardless of whether the FIFO buffer is on the CPU side or SIE side. To clear the buffer on the SIE side, set the PID bits for the DCP to NAK before setting BCLR to 1. When the selected pipe is not the DCP, writing 1 to this bit should be done while FRDY indicates 1 (set by this module). 13 FRDY 0 R FIFO Port Ready Indicates whether the FIFO port can be accessed. 0: FIFO port access is disabled. 1: FIFO port access is enabled. In the following cases, this module sets FRDY to 1 but data cannot be read via the FIFO port because there is no data to be read. In these cases, set BCLR to 1 to clear the FIFO buffer, and enable transmission and reception of the next data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  A zero-length packet is received when the FIFO buffer assigned to the selected pipe is empty.  A short packet is received and the data is completely read while BFRE is 1. Page 1545 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11 to 0 DTLN[11:0] H'000 R Receive Data Length Indicates the length of the receive data. While the FIFO buffer is being read, these bits indicate the different values depending on the RCNT bit value as described below.  RCNT = 0: This module sets these bits to indicate the length of the receive data until all the received data has been read from a single FIFO buffer plane. While BFRE is 1, these bits retain the length of the receive data until BCLR is set to 1 even after all the data has been read.  RCNT = 1: This module decrements the value indicated by these bits each time data is read from the FIFO buffer. (The value is decremented by one when MBW is 00, by two when MBW is 01, and by four when MBW is 10.) This module sets these bits to 0 when all the data has been read from one FIFO buffer plane. However, in double buffer mode, if data has been received in one FIFO buffer plane before all the data has been read from the other plane, this module sets these bits to indicate the length of the receive data in the former plane when all the data has been read from the latter plane. Note: When RCNT is 1, it takes 10 bus cycles for these bits to be updated after the FIFO port has been read. Notes: 1. Only 0 can be read and 1 can be written. 2. Only 1 can be written. Page 1546 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.10 Interrupt Enable Register 0 (INTENB0) INTENB0 is a register that enables or disables the various interrupts. On detecting the interrupt corresponding to the bit that has been set to 1, this module generates the USB interrupt. This module sets 1 to each status bit in INTSTS0 when a detection condition of the corresponding interrupt source has been satisfied regardless of the set value in INTENB0 (regardless of whether the interrupt output is enabled or disabled). While the status bit in INTSTS0 corresponding to the interrupt source indicates 1, this module generates the USB interrupt when the corresponding interrupt enable bit in INTENB0 is modified from 0 to 1. This register is initialized by a power-on reset. Bit: 15 14 13 12 7 6 5 4 3 2 1 0 VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE 11 10 — — — — — — — — Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 9 0 R/W 8 0 R/W Bit Bit Name Initial Value R/W Description 15 VBSE 0 R/W VBUS Interrupt Enable Enables or disables the USB interrupt request when the VBINT interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 14 RSME 0 R/W Resume Interrupt Enable* Enables or disables the USB interrupt request when the RESM interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 13 SOFE 0 R/W Frame Number Update Interrupt Enable Enables or disables the USB interrupt request when the SOFR interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1547 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 12 DVSE 0 R/W Device State Transition Interrupt Enable* Enables or disables the USB interrupt request when the DVST interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 11 CTRE 0 R/W Control Transfer Stage Transition Interrupt Enable* Enables or disables the USB interrupt request when the CTRT interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 10 BEMPE 0 R/W Buffer Empty Interrupt Enable Enables or disables the USB interrupt request when the BEMP interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 9 NRDYE 0 R/W Buffer Not Ready Response Interrupt Enable Enables or disables the USB interrupt request when the NRDY interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 8 BRDYE 0 R/W Buffer Ready Interrupt Enable Enables or disables the USB interrupt request when the BRDY interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled  7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * The RSME, DVSE, and CTRE bits can be set to 1 only when the function controller function is selected; do not set these bits to 1 to enable the corresponding interrupt output when the host controller function is selected. Page 1548 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.11 Interrupt Enable Register 1 (INTENB1) INTENB1 is a register that enables or disables the various interrupts when the host controller function is selected. On detecting the interrupt corresponding to the bit in this register that has been set to 1, this module generates the USB interrupt. This module sets 1 to each status bit in INTSTS1 when a detection condition of the corresponding interrupt source has been satisfied regardless of the set value in INTENB1 (regardless of whether the interrupt output is enabled or disabled). While the status bit in INTSTS1 corresponding to the interrupt source indicates 1, this module generates the USB interrupt when the corresponding interrupt enable bit in INTENB1 is modified from 0 to 1. When the function controller function is selected, the interrupts should not be enabled. This register is initialized by a power-on reset. Bit: 15 — Initial value: 0 R/W: R 14 13 12 11 10 9 8 7 3 2 1 0 BCHGE — DTCHE ATT CHE — — — — EOF ERRE SIGNE SACKE — — — — 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 15  0 R 6 5 0 R/W 4 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 BCHGE 0 R/W USB Bus Change Interrupt Enable Enables or disables the USB interrupt request when the BCHG interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 13  0 R Reserved This bit is always read as 0. The write value should always be 0. 12 DTCHE 0 R/W Disconnection Detection Interrupt Enable Enables or disables the USB interrupt request when the DTCH interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1549 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 11 ATTCHE 0 R/W Connection Detection Interrupt Enable Enables or disables the USB interrupt request when the ATTCH interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 10 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 EOFERRE 0 R/W EOF Error Detection Interrupt Enable Enables or disables the USB interrupt request when the EOFERR interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 5 SIGNE 0 R/W Setup Transaction Error Interrupt Enable Enables or disables the USB interrupt request when the SIGN interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 4 SACKE 0 R/W Setup Transaction Normal Response Interrupt Enable Enables or disables the USB interrupt request when the SACK interrupt is detected. 0: Interrupt request disabled 1: Interrupt request enabled 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: The INTENB1 register bits can be set to 1 only when the host controller function is selected; do not set these bits to 1 to enable the corresponding interrupt output when the function controller function is selected. Page 1550 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.12 BRDY Interrupt Enable Register (BRDYENB) BRDYENB is a register that enables or disables the BRDY bit in INTSTS0 to be set to 1 when the BRDY interrupt is detected for each pipe. On detecting the BRDY interrupt for the pipe corresponding to the bit in this register that has been set to 1, this module sets 1 to the corresponding PIPEBRDY bit in BRDYSTS and the BRDY bit in INTSTS0, and generates the BRDY interrupt. While at least one PIPEBRDY bit in BRDYSTS indicates 1, this module generates the BRDY interrupt when the corresponding interrupt enable bit in BRDYENB is modified from 0 to 1. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 10  9 8 7 6 5 4 3 2 1 0 PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE BRDYE 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 9 PIPE9BRDYE 0 R/W BRDY interrupt Enable for PIPE9 0: Interrupt output disabled 1: Interrupt output enabled 8 PIPE8BRDYE 0 R/W BRDY interrupt Enable for PIPE8 0: Interrupt output disabled 1: Interrupt output enabled 7 PIPE7BRDYE 0 R/W BRDY interrupt Enable for PIPE7 0: Interrupt output disabled 1: Interrupt output enabled 6 PIPE6BRDYE 0 R/W BRDY interrupt Enable for PIPE6 0: Interrupt output disabled 1: Interrupt output enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1551 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Initial Value Bit Bit Name 5 PIPE5BRDYE 0 R/W Description R/W BRDY interrupt Enable for PIPE5 0: Interrupt output disabled 1: Interrupt output enabled 4 PIPE4BRDYE 0 R/W BRDY interrupt Enable for PIPE4 0: Interrupt output disabled 1: Interrupt output enabled 3 PIPE3BRDYE 0 R/W BRDY interrupt Enable for PIPE3 0: Interrupt output disabled 1: Interrupt output enabled 2 PIPE2BRDYE 0 R/W BRDY interrupt Enable for PIPE2 0: Interrupt output disabled 1: Interrupt output enabled 1 PIPE1BRDYE 0 R/W BRDY interrupt Enable for PIPE1 0: Interrupt output disabled 1: Interrupt output enabled 0 PIPE0BRDYE 0 R/W BRDY interrupt Enable for PIPE0 0: Interrupt output disabled 1: Interrupt output enabled 29.3.13 NRDY Interrupt Enable Register (NRDYENB) NRDYENB is a register that enables or disables the NRDY bit in INTSTS0 to be set to 1 when the NRDY interrupt is detected for each pipe. On detecting the NRDY interrupt for the pipe corresponding to the bit in this register that has been set to 1, this module sets 1 to the corresponding PIPENRDY bit in NRDYSTS and the NRDY bit in INTSTS0, and generates the NRDY interrupt. While at least one PIPENRDY bit in NRDYSTS indicates 1, this module generates the NRDY interrupt when the corresponding interrupt enable bit in NRDYENB is modified from 0 to 1. This register is initialized by a power-on reset. Page 1552 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit: 15 14 13 12 11 10 — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 10  9 8 7 6 5 4 3 2 1 0 PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE NRDYE 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 9 PIPE9NRDYE 0 R/W NRDY Interrupt Enable for PIPE9 0: Interrupt output disabled 1: Interrupt output enabled 8 PIPE8NRDYE 0 R/W NRDY Interrupt Enable for PIPE8 0: Interrupt output disabled 1: Interrupt output enabled 7 PIPE7NRDYE 0 R/W NRDY Interrupt Enable for PIPE7 0: Interrupt output disabled 1: Interrupt output enabled 6 PIPE6NRDYE 0 R/W NRDY Interrupt Enable for PIPE6 0: Interrupt output disabled 1: Interrupt output enabled 5 PIPE5NRDYE 0 R/W NRDY Interrupt Enable for PIPE5 0: Interrupt output disabled 1: Interrupt output enabled 4 PIPE4NRDYE 0 R/W NRDY Interrupt Enable for PIPE4 0: Interrupt output disabled 1: Interrupt output enabled 3 PIPE3NRDYE 0 R/W NRDY Interrupt Enable for PIPE3 0: Interrupt output disabled 1: Interrupt output enabled 2 PIPE2NRDYE 0 R/W NRDY Interrupt Enable for PIPE2 0: Interrupt output disabled 1: Interrupt output enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1553 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Initial Value Bit Bit Name 1 PIPE1NRDYE 0 R/W Description R/W NRDY Interrupt Enable for PIPE1 0: Interrupt output disabled 1: Interrupt output enabled 0 PIPE0NRDYE 0 R/W NRDY Interrupt Enable for PIPE0 0: Interrupt output disabled 1: Interrupt output enabled 29.3.14 BEMP Interrupt Enable Register (BEMPENB) BEMPENB is a register that enables or disables the BEMP bit in INTSTS0 to be set to 1 when the BEMP interrupt is detected for each pipe. On detecting the BEMP interrupt for the pipe corresponding to the bit in this register that has been set to 1, this module sets 1 to the corresponding PIPEBEMP bit in BEMPSTS and the BEMP bit in INTSTS0, and generates the BEMP interrupt. While at least one PIPEBEMP bit in BEMPSTS indicates 1, this module generates the BEMP interrupt when the corresponding interrupt enable bit in BEMPENB is modified from 0 to 1. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 10  9 8 7 6 5 4 3 2 1 0 PIPE9 PIPE8 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 9 PIPE9BEMPE 0 Page 1554 of 3092 R/W BEMP Interrupt Enable for PIPE9 0: Interrupt output disabled 1: Interrupt output enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 8 Section 29 USB 2.0 Host/Function Module Initial Value R/W Description PIPE8BEMPE 0 R/W BEMP Interrupt Enable for PIPE8 0: Interrupt output disabled 1: Interrupt output enabled 7 PIPE7BEMPE 0 R/W BEMP Interrupt Enable for PIPE7 0: Interrupt output disabled 1: Interrupt output enabled 6 PIPE6BEMPE 0 R/W BEMP Interrupt Enable for PIPE6 0: Interrupt output disabled 1: Interrupt output enabled 5 PIPE5BEMPE 0 R/W BEMP Interrupt Enable for PIPE5 0: Interrupt output disabled 1: Interrupt output enabled 4 PIPE4BEMPE 0 R/W BEMP Interrupt Enable for PIPE4 0: Interrupt output disabled 1: Interrupt output enabled 3 PIPE3BEMPE 0 R/W BEMP Interrupt Enable for PIPE3 0: Interrupt output disabled 1: Interrupt output enabled 2 PIPE2BEMPE 0 R/W BEMP Interrupt Enable for PIPE2 0: Interrupt output disabled 1: Interrupt output enabled 1 PIPE1BEMPE 0 R/W BEMP Interrupt Enable for PIPE1 0: Interrupt output disabled 1: Interrupt output enabled 0 PIPE0BEMPE 0 R/W BEMP Interrupt Enable for PIPE0 0: Interrupt output disabled 1: Interrupt output enabled 29.3.15 SOF Output Configuration Register (SOFCFG) SOFCFG is a register that specifies the transaction-enabled time and BRDY interrupt status clear timing. This register is initialized by a power-on reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1555 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — TRNEN SEL — BRDYM — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 TRNENSEL 0 R/W Transaction-Enabled Time Select Selects the transaction-enabled time either for full- or low-speed communication, during which this module issues tokens in a frame. 0: For non-low-speed communication 1: For low-speed communication This bit is valid only when the host controller function is selected. Even when the host controller function is selected, the setting of this bit has no effect on the transaction-enabled time during high-speed communication. This bit should be set to 0 when the function controller function is selected. 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 BRDYM 0 R/W BRDY Interrupt Status Clear Timing for each Pipe Specifies the timing for clearing the BRDY interrupt status for each pipe. Set the BRDYM bit during the initial settings of the USB 2.0 host/function module (before performing data communication). Do not change the setting of the BRDYM bit after data communication starts. 0: Writing 0 clears the status. 1: This module automatically clears the status when data has been read from the FIFO buffer or data has been written to the FIFO buffer. 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1556 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.16 Interrupt Status Register 0 (INTSTS0) INTSTS0 is a register that indicates the status of the various interrupts detected. This register is initialized by a power-on reset. By a USB bus reset, the DVST and DVSQ[2:0] bits are initialized. Bit: 15 14 VBINT RESM 13 12 11 10 9 SOFR DVST CTRT BEMP NRDY 0 R 0 R Initial value: 0 0 0 0/1*1 0 R/W: R/W*7 R/W*7 R/W*7 R/W*7 R/W*7 Bit 15 Bit Name VBINT Initial Value 0 R/W R/W* 8 7 6 BRDY VBSTS 0 R 0/1*3 R 5 4 DVSQ[2:0] 0*2 R 0*2 R 3 2 VALID 0 0/1*2 R R/W*7 1 0 CTSQ[2:0] 0 R 0 R 0 R Description 7 VBUS Interrupt Status*4*5 0: VBUS interrupts not generated 1: VBUS interrupts generated This module sets this bit to 1 on detecting a level change (high to low or low to high) in the VBUS pin input value. This module sets the VBSTS bit to indicate the VBUS pin input value. When the VBUS interrupt is generated, repeat reading the VBSTS bit until the same value is read several times to eliminate chattering. 14 RESM 0 R/W*7 Resume Interrupt Status*4*5*6 0: Resume interrupts not generated 1: Resume interrupts generated When the function controller function is selected, this module sets this bit to 1 on detecting the falling edge of the signal on the DP pin in the suspended state (DVSQ = 1XX). When the host controller function is selected, the read value is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1557 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 13 Bit Name SOFR Initial Value 0 R/W Description 7 R/W* Frame Number Refresh Interrupt Status*4 0: SOF interrupts not generated 1: SOF interrupts generated (1) When the host controller function is selected This module sets this bit to 1 on updating the frame number when the UACT bit has been set to 1. (This interrupt is detected every 1 ms.) (2) When the function controller function is selected This module sets this bit to 1 on updating the frame number. (This interrupt is detected every 1 ms.) This module can detect an SOFR interrupt through the internal interpolation function even when a damaged SOF packet is received from the USB host. 12 DVST 0/1*1 R/W*7 Device State Transition Interrupt Status*4*6 0: Device state transition interrupts not generated 1: Device state transition interrupts generated When the function controller function is selected, this module updates the DVSQ value and sets this bit to 1 on detecting a change in the device state. When this interrupt is generated, clear the status before this module detects the next device state transition. When the host controller function is selected, the read value is invalid. Page 1558 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 11 Bit Name CTRT Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description 7 R/W* Control Transfer Stage Transition Interrupt Status*4*6 0: Control transfer stage transition interrupts not generated 1: Control transfer stage transition interrupts generated When the function controller function is selected, this module updates the CTSQ value and sets this bit to 1 on detecting a change in the control transfer stage. When this interrupt is generated, clear the status before this module detects the next control transfer stage transition. When the host controller function is selected, the read value is invalid. 10 BEMP 0 R Buffer Empty Interrupt Status 0: BEMP interrupts not generated 1: BEMP interrupts generated This module sets this bit to 1 when at least one PIPEBEMP bit in BEMPSTS is set to 1 among the PIPEBEMP bits corresponding to the PIPEBEMPE bits in BEMPENB to which 1 has been set (when this module detects the BEMP interrupt status in at least one pipe among the pipes for which the BEMP interrupt output is enabled). For the conditions for PIPEBEMP status assertion, refer to section 29.4.2 (3), BEMP Interrupt. This module clears this bit to 0 when 0 is written to all the PIPEBEMP bits corresponding to the PIPEBEMPE bits to which 1 has been set. This bit cannot be cleared to 0 even if 0 is written to this bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1559 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 9 NRDY 0 R Buffer Not Ready Interrupt Status 0: NRDY interrupts not generated 1: NRDY interrupts generated This module sets this bit to 1 when at least one PIPENRDY bit in NRDYSTS is set to 1 among the PIPENRDY bits corresponding to the PIPENRDYE bits in NRDYENB to which 1 has been set (when this module detects the NRDY interrupt status in at least one pipe among the pipes for which the NRDY interrupt output is enabled). For the conditions for PIPENRDY status assertion, refer to section 29.4.2 (2), NRDY Interrupt. This module clears this bit to 0 when 0 is written to all the PIPENRDY bits corresponding to the PIPENRDYE bits to which 1 has been set. This bit cannot be cleared to 0 even if 0 is written to this bit. 8 BRDY 0 R Buffer Ready Interrupt Status Indicates the BRDY interrupt status. 0: BRDY interrupts not generated 1: BRDY interrupts generated This module sets this bit to 1 when at least one PIPEBRDY bit in BRDYSTS is set to 1 among the PIPEBRDY bits corresponding to the PIPEBRDYE bits in BRDYENB to which 1 has been set (when this module detects the BRDY interrupt status in at least one pipe among the pipes for which the BRDY interrupt output is enabled). For the conditions for PIPEBRDY status assertion, refer to section 29.4.2 (1), BRDY Interrupt. This module clears this bit to 0 when 0 is written to all the PIPEBRDY bits corresponding to the PIPEBRDYE bits to which 1 has been set. This bit cannot be cleared to 0 even if 0 is written to this bit. Page 1560 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 7 Bit Name VBSTS Section 29 USB 2.0 Host/Function Module Initial Value 3 0/1* R/W Description R VBUS Input Status 0: The VBUS pin is low level. 1: The VBUS pin is high level. 6 to 4 DVSQ[2:0] 2 000/001* R Device State 000: Powered state 001: Default state 010: Address state 011: Configured state 1xx: Suspended state When the host controller function is selected, the read value is invalid. 3 VALID 0 R/W*7 USB Request Reception 0: Not detected 1: Setup packet reception When the host controller function is selected, the read value is invalid. 2 to 0 CTSQ[2:0] 000 R Control Transfer Stage 000: Idle or setup stage 001: Control read data stage 010: Control read status stage 011: Control write data stage 100: Control write status stage 101: Control write (no data) status stage 110: Control transfer sequence error 111: Setting prohibited When the host controller function is selected, the read value is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1561 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Notes: 1. 2. 3. 4. This bit is initialized to B'0 by a power-on reset and B'1 by a USB bus reset. These bits are initialized to B'000 by a power-on reset and B'001 by a USB bus reset. This bit is initialized to 0 when the level of the VBUS pin input is high and 1 when low. To clear the VBINT, RESM, SOFR, DVST, or CTRT bit, write 0 only to the bits to be cleared; write 1 to the other bits. Do not write 0 to the status bits indicating 0. 5. This module can detect a change in the status indicated by the VBINT and RESM bits even while the clock supply is stopped (while SCKE is 0), and outputs interrupts when the corresponding interrupt enable bits are enabled. Clearing the status should be done after enabling the clock supply. 6. A change in the status of the RESM, DVST, and CTRT bits occur only when the function controller function is selected; disable the corresponding interrupt enable bits (set to 0) when the host controller function is selected. 7. Only 0 can be written. 29.3.17 Interrupt Status Register 1 (INTSTS1) INTSTS1 is a register that is used to confirm interrupt status. The various interrupts indicated by the bits in this register should be enabled only when the host controller function is selected. This register is initialized by a power-on reset. Bit: 15 14 13 10 9 8 7 6 5 4 3 2 1 0 — BCHG — DTCH ATTCH 12 11 — — — — EOF ERR SIGN SACK — — — — Initial value: 0 R/W: R 0 R/W*1 0 R 0 0 R/W*1 R/W*1 0 R 0 R 0 R 0 R 0 0 0 R/W*1 R/W*1 R/W*1 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 1562 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 14 Bit Name BCHG Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description 1 R/W* USB Bus Change Interrupt Status Indicates the status of the USB bus change interrupt. 0: BCHG interrupts not generated 1: BCHG interrupts generated This module detects the BCHG interrupt when a change in the full-speed or low-speed signal level occurs on the USB port (a change from J-state, Kstate, or SE0 to J-state, K-state, or SE0), and sets this bit to 1. Here, if the corresponding interrupt enable bit has been set to 1, this module generates the interrupt. This module sets the LNST bits in SYSSTS0 to indicate the current input state of the USB port. When the BCHG interrupt is generated, repeat reading the LNST bits until the same value is read several times, and eliminate chattering. A change in the USB bus state can be detected even while the internal clock supply is stopped. When the function controller function is selected, the read value is invalid. 13  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1563 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 12 Bit Name DTCH Initial Value 0 R/W Description R/W* 1 USB Disconnection Detection Interrupt Status Indicates the status of the USB disconnection detection interrupt when the host controller function is selected. 0: DTCH interrupts not generated 1: DTCH interrupts generated This module detects the DTCH interrupt on detecting USB bus disconnection, and sets this bit to 1. Here, if the corresponding interrupt enable bit has been set to 1, this module generates the interrupt. This module detects bus disconnection based on USB Specification 2.0. After detecting the DTCH interrupt, this module controls hardware as described below (irrespective of the set value of the corresponding interrupt enable bit). Terminate all the pipes in which communications are currently carried out for the USB port and make a transition to the wait state for bus connection to the USB port (wait state for ATTCH interrupt generation). (1) Modifies the UACT bit to 0. (2) Causes a transition to the idle state. When the function controller function is selected, the read value is invalid. Page 1564 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 11 Bit Name ATTCH Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description 1 R/W* ATTCH Interrupt Status Indicates the status of the ATTCH interrupt when the host controller function is selected. 0: ATTCH interrupts not generated 1: ATTCH interrupts generated When this module has generated J-state or K-state of the full-speed or low-speed level signal for 2.5 s, this module detects the ATTCH interrupt and sets this bit to 1. Here, if the corresponding interrupt enable bit has been set to 1, this module generates the interrupt. Specifically, this module detects the ATTCH interrupt on any of the following conditions.  K-stateSE0, or SE1 changes to J-state, and Jstate continues 2.5 s.  J-state, SE0, or SE1 changes to K-state, and Kstate continues 2.5 s. When the function controller function is selected, the read value is invalid. 10 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1565 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 6 Bit Name EOFERR Initial Value 0 R/W Description R/W* 1 EOF Error Detection Interrupt Status Indicates the status of the EOFERR interrupt when the host controller function is selected. 0: EOFERR interrupt not generated 1: EOFERR interrupt generated This module detects the EOFERR interrupt on detecting that communication is not completed at the EOF2 timing prescribed by USB Specification 2.0, and sets this bit to 1. Here, if the corresponding interrupt enable bit has been set to 1, this module generates the EOFERR interrupt. After detecting the EOFERR interrupt, this module controls hardware as described below (irrespective of the set value of the corresponding interrupt enable bit). Terminate all the pipes in which communications are currently carried for the USB port and perform reenumeration of the USB port. (1) Modifies the UACT bit to 0. (2) Causes a transition to the idle state. When the function controller function is selected, the read value is invalid. Page 1566 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 5 Bit Name SIGN Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description R/W* 1 Setup Transaction Error Interrupt Status Indicates the status of the setup transaction error interrupt when the host controller function is selected. 0: SIGN interrupts not generated 1: SIGN interrupts generated This module detects the SIGN interrupt when ACK response is not returned from the peripheral device three consecutive times during the setup transactions issued by this module, and sets this bit to 1. Here, if the corresponding interrupt enable bit has been set to 1, this module generates the SIGN interrupt. Specifically, this module detects the SIGN interrupt when any of the following response conditions occur for three consecutive setup transactions.  Timeout is detected when the peripheral device has returned no response.  A damaged ACK packet is received.  A handshake other than ACK (NAK, NYET, or STALL) is received. When the function controller function is selected, the read value is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1567 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 4 Initial Value Bit Name SACK R/W Description 1 0 R/W* Setup Transaction Normal Response Interrupt Status Indicates the status of the setup transaction normal response interrupt when the host controller function is selected. 0: SACK interrupts not generated 1: SACK interrupts generated This module detects the SACK interrupt when ACK response is returned from the peripheral device during the setup transactions issued by this module, and sets this bit to 1. Here, if the corresponding interrupt enable bit has been set to 1, this module generates the SACK interrupt. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Only 0 can be written. 2. This module can detect a change in the status indicated by the BCHG bit even while the clock supply is stopped (while SCKE is 0), and outputs an interrupt when the corresponding interrupt enable bit is enabled. Clearing the status should be done after enabling the clock supply. No interrupts other than BCHG can be detected while the clock supply is stopped (while SCKE is 0). 29.3.18 BRDY Interrupt Status Register (BRDYSTS) BRDYSTS is a register that indicates the BRDY interrupt status for each pipe. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 — — — — — — PIPE9 BRDY PIPE8 BRDY Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 0 0 R/W*1 R/W*1 R/W*1 R/W*1 R/W*1 R/W*1 R/W*1 R/W*1 R/W*1 R/W*1 Page 1568 of 3092 7 6 5 4 3 2 1 0 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 BRDY BRDY BRDY BRDY BRDY BRDY BRDY BRDY R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 15 to 10  Section 29 USB 2.0 Host/Function Module Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PIPE9BRDY 0 R/W*1 BRDY Interrupt Status for PIPE9*2 0: Interrupts not generated 1: Interrupts generated 8 PIPE8BRDY 0 1 R/W* BRDY Interrupt Status for PIPE8*2 0: Interrupts not generated 1: Interrupts generated 7 PIPE7BRDY 0 1 R/W* BRDY Interrupt Status for PIPE7*2 0: Interrupts not generated 1: Interrupts generated 6 PIPE6BRDY 0 1 R/W* BRDY Interrupt Status for PIPE6*2 0: Interrupts not generated 1: Interrupts generated 5 PIPE5BRDY 0 1 R/W* BRDY Interrupt Status for PIPE5*2 0: Interrupts not generated 1: Interrupts generated 4 PIPE4BRDY 0 1 R/W* BRDY Interrupt Status for PIPE4*2 0: Interrupts not generated 1: Interrupts generated 3 PIPE3BRDY 0 R/W*1 BRDY Interrupt Status for PIPE3*2 0: Interrupts not generated 1: Interrupts generated 2 PIPE2BRDY 0 R/W* 1 BRDY Interrupt Status for PIPE2*2 0: Interrupts not generated 1: Interrupts generated R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1569 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 1 Initial Value Bit Name PIPE1BRDY R/W Description 1 0 R/W* BRDY Interrupt Status for PIPE1*2 0: Interrupts not generated 1: Interrupts generated 0 PIPE0BRDY 1 0 R/W* BRDY Interrupt Status for PIPE0*2 0: Interrupts not generated 1: Interrupts generated Notes: 1. Only 0 can be written. 2. When BRDYM is 0, clearing this bit should be done before accessing the FIFO. 29.3.19 NRDY Interrupt Status Register (NRDYSTS) NRDYSTS is a register that indicates the NRDY interrupt status for each pipe. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 — — — — — — PIPE9 NRDY PIPE8 NRDY Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name 15 to 10  7 6 5 4 3 2 1 0 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 NRDY NRDY NRDY NRDY NRDY NRDY NRDY NRDY Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 PIPE9NRDY 0 R/W* NRDY Interrupt Status for PIPE9 0: Interrupts not generated 1: Interrupts generated 8 PIPE8NRDY 0 R/W* NRDY Interrupt Status for PIPE8 0: Interrupts not generated 1: Interrupts generated Page 1570 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 PIPE7NRDY 0 R/W* NRDY Interrupt Status for PIPE7 0: Interrupts not generated 1: Interrupts generated 6 PIPE6NRDY 0 R/W* NRDY Interrupt Status for PIPE6 0: Interrupts not generated 1: Interrupts generated 5 PIPE5NRDY 0 R/W* NRDY Interrupt Status for PIPE5 0: Interrupts not generated 1: Interrupts generated 4 PIPE4NRDY 0 R/W* NRDY Interrupt Status for PIPE4 0: Interrupts not generated 1: Interrupts generated 3 PIPE3NRDY 0 R/W* NRDY Interrupt Status for PIPE3 0: Interrupts not generated 1: Interrupts generated 2 PIPE2NRDY 0 R/W* NRDY Interrupt Status for PIPE2 0: Interrupts not generated 1: Interrupts generated 1 PIPE1NRDY 0 R/W* NRDY Interrupt Status for PIPE1 0: Interrupts not generated 1: Interrupts generated 0 PIPE0NRDY 0 R/W* NRDY Interrupt Status for PIPE0 0: Interrupts not generated 1: Interrupts generated Note: * Only 0 can be written. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1571 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.20 BEMP Interrupt Status Register (BEMPSTS) BEMPSTS is a register that indicates the BEMP interrupt status for each pipe. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 — — — — — — PIPE9 BEMP PIPE8 BEMP Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name 15 to 10  Initial Value R/W All 0 R 7 6 5 4 3 2 1 0 PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0 BEMP BEMP BEMP BEMP BEMP BEMP BEMP BEMP Description Reserved These bits are always read as 0. The write value should always be 0. 9 PIPE9BEMP 0 R/W* BEMP Interrupts for PIPE9 0: Interrupts not generated 1: Interrupts generated 8 PIPE8BEMP 0 R/W* BEMP Interrupts for PIPE8 0: Interrupts not generated 1: Interrupts generated 7 PIPE7BEMP 0 R/W* BEMP Interrupts for PIPE7 0: Interrupts not generated 1: Interrupts generated 6 PIPE6BEMP 0 R/W* BEMP Interrupts for PIPE6 0: Interrupts not generated 1: Interrupts generated 5 PIPE5BEMP 0 R/W* BEMP Interrupts for PIPE5 0: Interrupts not generated 1: Interrupts generated 4 PIPE4BEMP 0 R/W* BEMP Interrupts for PIPE4 0: Interrupts not generated 1: Interrupts generated Page 1572 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 3 PIPE3BEMP 0 R/W* BEMP Interrupts for PIPE3 0: Interrupts not generated 1: Interrupts generated 2 PIPE2BEMP 0 R/W* BEMP Interrupts for PIPE2 0: Interrupts not generated 1: Interrupts generated 1 PIPE1BEMP 0 R/W* BEMP Interrupts for PIPE1 0: Interrupts not generated 1: Interrupts generated 0 PIPE0BEMP 0 R/W* BEMP Interrupts for PIPE0 0: Interrupts not generated 1: Interrupts generated Note: * Only 0 can be written. 29.3.21 Frame Number Register (FRMNUM) FRMNUM is a register that determines the source of isochronous error notification and indicates the frame number. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 CRCE — — — Initial value: 0 0 R/W: R/W* R/W* 0 R 0 R 0 R OVRN R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R FRNM[10:0] 0 R 0 R 0 R 0 R 0 R 0 R Page 1573 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 15 OVRN 0 R/W* Overrun/Underrun Detection Status Indicates whether an overrun/underrun error has been detected in the pipe during isochronous transfer. 0: No error 1: An error occurred This bit can be cleared to 0 by writing 0 to the bit. (1) When the host controller function is selected This module sets this bit to 1 on any of the following conditions.  For the isochronous transfer pipe in the transmitting direction, the time to issue an OUT token comes before all the transmit data has been written to the FIFO buffer.  For the isochronous transfer pipe in the receiving direction, the time to issue an IN token comes when no FIFO buffer planes are empty. (2) When the function controller function is selected This module sets this bit to 1 on any of the following conditions.  For the isochronous transfer pipe in the transmitting direction, the IN token is received before all the transmit data has been written to the FIFO buffer.  For the isochronous transfer pipe in the receiving direction, the OUT token is received when no FIFO buffer planes are empty. Note: This bit is provided for debugging. The system should be designed so that no overrun/underrun should occur. Page 1574 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 14 CRCE 0 R/W* Receive Data Error Indicates whether a CRC error or bit stuffing error has been detected in the pipe during isochronous transfer. Simultaneously with error detection, the internal NRDY interrupt request is generated. For details, see section 29.4.2, Interrupt Functions. 0: No error 1: An error occurred 13 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 FRNM[10:0] H'000 R Frame Number This module sets these bits to indicate the latest frame number, which is updated every time an SOF packet is issued or received (every 1 ms) Read these bits twice to check that the same value is read. Note: * Only 0 can be written. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1575 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.22 Frame Number Register (UFRMNUM) UFRMNUM is a register that indicates the frame number. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 — — — — — — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 15 to 3  All 0 R 2 1 0 UFRNM[2:0] 0 R 0 R 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 UFRNM[2:0] 000 R Frame The frame number can be confirmed. This module sets these bits to indicate the frame number during high-speed operation. During operation other than high-speed operation, this module sets these bits to B'000. Read these bits twice to check that the same value is read. Page 1576 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.23 USB Address Register (USBADDR) USBADDR is a register that indicates the USB address. This register is valid only when the function controller function is selected. When the host controller function is selected, peripheral device addresses should be set using the DEVSEL bits in PIPEMAXP. This register is initialized by a power-on reset or a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 — — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 7  All 0 R Reserved 6 5 4 3 2 1 0 0 R 0 R 0 R USBADDR[6:0] 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 6 to 0 USBADDR [6:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H'00 R USB Address When the function controller function is selected, these bits indicate the USB address assigned by the host when the SET_ADDRESS request is successfully processed. Page 1577 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.24 USB Request Type Register (USBREQ) USBREQ is a register that stores setup requests for control transfers. When the function controller function is selected, the values of bRequest and bmRequestType that have been received are stored. When the host controller function is selected, the values of bRequest and bmRequestType to be transmitted are set. This register is initialized by a power-on reset or a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 BREQUEST[7:0] 6 5 4 3 2 1 0 BMREQUESTTYPE[7:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Initial Value R/W Description H'00 R/W* Request These bits store the USB request bRequest value. (1) When the host controller function is selected The USB request data value for the setup transaction to be transmitted should be set in these bits. After setting SUREQ to 1, do not modify these bits until 0 is read from SUREQ. (2) When the function controller function is selected Indicates the USB request data value received during the setup transaction. Writing to these bits is invalid. BMREQUEST- H'00 TYPE[7:0] R/W* Bit Bit Name 15 to 8 BREQUEST [7:0] 7 to 0 Note: * Request Type These bits store the USB request bmRequestType value. (1) When the host controller function is selected The USB request type value for the setup transaction to be transmitted should be set in these bits. After setting SUREQ to 1, do not modify these bits until 0 is read from SUREQ. (2) When the function controller function is selected Indicates the USB request type value received during the setup transaction. Writing to these bits is invalid. When the function controller function is selected, these bits can only be read, and writing to these bits is invalid. When the host controller function is selected, these bits can be read and written to. Page 1578 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.25 USB Request Value Register (USBVAL) USBVAL is a register that stores setup requests for control transfers. When the function controller function is selected, the value of wValue that has been received is stored. When the host controller function is selected, the value of wValue to be transmitted is set. This register is initialized by a power-on reset or a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WVALUE[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Initial Value Bit Bit Name 15 to 0 WVALUE[15:0] H'0000 R/W Description R/W* Value These bits store the USB request wValue value. (1) When the host controller function is selected The USB request wValue value for the setup transaction to be transmitted should be set in these bits. After setting SUREQ to 1, do not modify these bits until 0 is read from SUREQ. (2) When the function controller function is selected Indicates the USB request wValue value received during the setup transaction. Writing to these bits is invalid. Note: * When the function controller function is selected, these bits can only be read, and writing to these bits is invalid. When the host controller function is selected, these bits can be read and written to. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1579 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.26 USB Request Index Register (USBINDX) USBINDEX is a register that stores setup requests for control transfers. When the function controller function is selected, the value of wIndex that has been received is stored. When the host controller function is selected, the value of wIndex to be transmitted is set. This register is initialized by a power-on reset or a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WINDEX[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name Initial Value R/W Description 15 to 0 WINDEX[15:0] H'0000 R/W* Index These bits store the USB request wIndex value. (1) When the host controller function is selected The USB request wIndex value for the setup transaction to be transmitted should be set in these bits. After setting SUREQ to 1, do not modify these bits until 0 is read from SUREQ. (2) When the function controller function is selected Indicates the USB request wIndex value received during the setup transaction. Writing to these bits is invalid. Note: * When the function controller function is selected, these bits can only be read, and writing to these bits is invalid. When the host controller function is selected, these bits can be read and written to. Page 1580 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.27 USB Request Length Register (USBLENG) USBLENG is a register that stores setup requests for control transfers. When the function controller function is selected, the value of wLength that has been received is stored. When the host controller function is selected, the value of wLength to be transmitted is set. This register is initialized by a power-on reset or a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WLENGTH[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name 15 to 0 WLENGTH [15:0] Initial Value R/W Description H'0000 R/W* Length These bits store the USB request wLength value. (1) When the host controller function is selected The USB request wLength value for the setup transaction to be transmitted should be set in these bits. After setting SUREQ to 1, do not modify these bits until 0 is read from SUREQ. (2) When the function controller function is selected Indicates the USB request wLength value received during the setup transaction. Writing to these bits is invalid. Note: * When the function controller function is selected, these bits can only be read, and writing to these bits is invalid. When the host controller function is selected, these bits can be read and written to. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1581 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.28 DCP Configuration Register (DCPCFG) DCPCFG is a register that specifies the data transfer direction for the default control pipe (DCP). This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 CNTMD SHTNAK 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved 6 5 4 3 2 1 0 — — DIR — — — — 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 8 CNTMD 0 R/W Continuous Transfer Mode Specifies whether the DCP operates in continuous transfer mode or not. 0: Non-continuous transfer mode 1: Continuous transfer mode Change the setting of this bit only when CSSTS = 0 and PID = NAK, and no pipe has been selected using the CURPIPE bits. When changing the setting of this bit after USB communication using the DCP, write 1 to BCLR and clear the FIFO buffer assigned to the DCP in addition to ensuring that the above three registers are in the states indicated. Before changing the setting of this bit after changing the DCP’s PID bit from BUF to NAK, confirm that the values of CSSTS and PBUSY are 0. However, it is not necessary for this module to confirm the state of the PBUSY bit if the value of the PID bit has already been changed to NAK. Page 1582 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 SHTNAK 0 R/W Disable Pipe when Transfer Finishes Specifies whether the PID bit is changed to NAK when a transfer finishes while the DCP is operating in the receive direction. 0: Continue using pipe after transfer finishes. 1: Disable pipe when transfer finishes. When this bit is set to 1, this module changes the PID bit corresponding to the DCP to NAK when it determines that a transfer to the DCP has finished. This module determines that a transfer has finished when a short packet of data (or a zero-length packet) is received successfully. Change the setting of this bit only when CSSTS = 0 and PID = NAK. Before changing the setting of this bit after changing the DCP’s PID bit from BUF to NAK, confirm that the values of CSSTS and PBUSY are 0. However, it is not necessary for this module to confirm the state of the PBUSY bit if the value of the PID bit has already been changed to NAK. 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 DIR 0 R/W Transfer Direction When the host controller function is selected, this bit sets the transfer direction of data stage. 0: Data receiving direction 1: Data transmitting direction When the function controller function is selected, this bit should be cleared to 0. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1583 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.29 DCP Maximum Packet Size Register (DCPMAXP) DCPMAXP is a register that specifies the maximum packet size for the DCP. This register is initialized by a power-on reset. Bit: 15 14 13 12 DEVSEL[3:0] Initial value: 0 R/W: R/W Bit 0 R/W 0 R/W Bit Name 15 to 12 DEVSEL[3:0] Page 1584 of 3092 0 R/W 11 10 9 8 7 — — — — — 0 R 0 R 0 R 0 R 0 R 6 5 4 3 2 1 0 0 R 0 R 0 R MXPS[6:0] 1 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description 0000 R/W Device Select When the host controller function is selected, these bits specify the communication target peripheral device address. 0000: Address 0000 0001: Address 0001 : : 1001: Address 1001 1010: Address 1010 Other than above: Setting prohibited These bits should be set after setting the DEVADDn register corresponding to the value to be set in these bits. For example, before setting DEVSEL to 0010 the DEVADD2 register should be set. These bits should be set while CSSTS is 0, PID is NAK, and SUREQ is 0. Before modifying these bits after modifying the PID bits for the DCP from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. When the function controller function is selected, these bits should be set to B'0000. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 to 0 MXPS[6:0] H'40 R/W Maximum Packet Size Specifies the maximum data payload (maximum packet size) for the DCP. These bits are initialized to H'40 (64 bytes). These bits should be set to the value based on the USB Specification. These bits should be set while CSSTS is 0 and PID is NAK. Before modifying these bits after modifying the PID bits for the DCP from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. While MXPS is 0, do not write to the FIFO buffer or do not set PID to BUF. 29.3.30 DCP Control Register (DCPCTR) DCPCTR is a register that is used to confirm the buffer memory status, change and confirm the data PID sequence bit, and set the response PID for the DCP. This register is initialized by a power-on reset. The CCPL and PID[1:0] bits are initialized by a USB bus reset. Bit: 15 14 13 12 11 BSTS SUREQ CSCLR CSSTS SUREQ CLR Initial value: 0 R/W: R 0 0 R/W*2 R/W*1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 R 0 R/W*1 10 9 3 2 — — SQCLR SQSET SQMON PBUSY PINGE 8 7 6 — CCPL 0 R 0 R 0 0 R/W*1 R/W*1 0 R 1 R 5 0 R 4 0 R/W 1 0 PID[1:0] 0 0 R/W*1 R/W 0 R/W Page 1585 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 15 BSTS 0 R Buffer Status Indicates whether DCP FIFO buffer access is enabled or disabled. 0: Buffer access is disabled. 1: Buffer access is enabled. The meaning of the BSTS bit depends on the ISEL bit setting as follows. 14 SUREQ 0 R/W*2  When ISEL = 0, BSTS indicates whether the received data can be read from the buffer.  When ISEL = 1, BSTS indicates whether the data to be transmitted can be written to the buffer. SETUP Token Transmission Transmits the setup packet by setting this bit to 1 when the host controller function is selected. 0: Invalid 1: Transmits the setup packet. After completing the setup transaction process, this module generates either the SACK or SIGN interrupt and clears this bit to 0. This module also clears this bit to 0 when the SUREQCLR bit is set to 1. Before setting this bit to 1, set the DEVSEL bits, USBREQ register, USBVAL register, USBINDX register, and USBLENG register appropriately to transmit the desired USB request in the setup transaction. Before setting this bit to 1, check that the PID bits for the DCP are set to NAK. After setting this bit to 1, do not modify the DEVSEL bits, USBREQ register, USBVAL register, USBINDX register, or USBLENG register until the setup transaction is completed (SUREQ = 1). Write 1 to this bit only when transmitting the setup token; for the other purposes, write 0. When the function controller function is selected, be sure to write 0 to this bit. Page 1586 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 13 Bit Name CSCLR Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description 1 R/W* C-SPLIT Status Clear for Split Transaction When the host controller function is selected, setting this bit to 1 clears the CSSTS bit to 0 for the transfer using the split transaction. In this case, the next DCP transfer restarts with the S-SPLIT. 0: Invalid 1: Clears the CSSTS bit to 0. When this bit is set to 1, this module clears the CSSTS bit to 0. For the transfer using the split transaction, to restart the next transfer with the S-SPLIT forcibly, set this bit to 1. However, for the normal split transaction, this module automatically clears the CSSTS bit to 0 upon completion of the C-SPLIT; therefore, clearing the CSSTS bit is not necessary. Controlling the CSSTS bit through this bit must be done while UACT is 0 and thus communication is halted or while no transfer is being performed with bus disconnection detected. Setting this bit to 1 while CSSTS is 0 has no effect. When the function controller function is selected, be sure to write 0 to this bit. 12 CSSTS 0 R COMPLETE SPLIT (C-SPLIT) Status of Split Transaction Indicates the C-SPLIT status of the split transaction when the host controller function is selected. 0: START-SPLIT (S-SPLIT) transaction being processed or the device not using the split transaction being processed 1: C-SPLIT transaction being processed This module sets this bit to 1 upon start of the CSPLIT and clears this bit to 0 upon detection of CSPLIT completion. When the function controller function is selected, the read value is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1587 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 11 Bit Name SUREQCLR Initial Value 0 R/W Description 1 R/W* SUREQ Bit Clear When the host controller function is selected, setting this bit to 1 clears the SUREQ bit to 0. 0: Invalid 1: Clears the SUREQ bit to 0. This bit always indicates 0. Set this bit to 1 when communication has stopped with SUREQ being 1 during the setup transaction. However, for normal setup transactions, this module automatically clears the SUREQ bit to 0 upon completion of the transaction; therefore, clearing the SUREQ bit is not necessary. Controlling the SUREQ bit through this bit must be done while UACT is 0 and thus communication is halted or while no transfer is being performed with bus disconnection detected. When the function controller function is selected, be sure to write 0 to this bit. 10, 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1588 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit 8 Bit Name SQCLR Section 29 USB 2.0 Host/Function Module Initial Value 0 R/W Description 1 R/W* Toggle Bit Clear Specifies DATA0 as the expected value of the sequence toggle bit for the next transaction during the DCP transfer. 0: Invalid 1: Specifies DATA0. This bit always indicates 0. Do not set the SQCLR and SQSET bits to 1 simultaneously. Set this bit to 1 while CSCTS is 0 and PID is NAK. Before setting this bit to 1 after modifying the PID bits for the DCP from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. 7 SQSET 0 R/W*1 Toggle Bit Set Specifies DATA1 as the expected value of the sequence toggle bit for the next transaction during the DCP transfer. 0: Invalid 1: Specifies DATA1. Do not set the SQCLR and SQSET bits to 1 simultaneously. Set this bit to 1 while CSSTS is 0 and PID is NAK. Before setting this bit to 1 after modifying the PID bits for the DCP from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1589 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 6 SQMON 1 R Sequence Toggle Bit Monitor Indicates the expected value of the sequence toggle bit for the next transaction during the DCP transfer. 0: DATA0 1: DATA1 This module allows this bit to toggle upon normal completion of the transaction. However, this bit is not allowed to toggle when a DATA-PID disagreement occurs during the transfer in the receiving direction. When the function controller function is selected, this module sets this bit to 1 (specifies DATA1 as the expected value) upon normal reception of the setup packet. When the function controller function is selected, this module does not reference to this bit during the IN/OUT transaction of the status stage, and does not allow this bit to toggle upon normal completion. 5 PBUSY 0 R Pipe Busy This bit indicates whether or not a transaction using the pertinent pipe is currently in progress. 0: The pertinent pipe is not in use by a transaction. 1: The pertinent pipe is in use by a transaction. The USB 2.0 host/function module changes the setting of the PBUSY bit from 0 to 1 when a USB transaction using the DCP starts. It clears the PBUSY bit from 1 to 0 when one transaction completes successfully. Reading this bit after setting PID to NAK allows checking that modification of the pipe settings is possible. For details, refer to section 29.4.3 (1), Pipe Control Register Switching Procedures. Page 1590 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 4 PINGE 0 R/W PING Token Issue Enable When the host controller function is selected, setting this bit to 1 allows this module to issue the PING token during transfers in the transmitting direction and start a transfer in the transmitting direction with the PING transaction. 0: Disables issuing PING token. 1: Enables normal PING operation. When having detected the ACK handshake during PING transactions, this module performs the OUT transaction as the next transaction. When having detected the NAK handshake during OUT transactions, this module performs the PING transaction as the next transaction. When the host controller function is selected, setting this bit to 0 prevents this module from issuing the PING token during transfers in the transmitting direction and only allows this module to perform OUT transactions for the transfers in the transmitting direction. These bits should be modified while CSSTS is 0 and PID is NAK. Before changing the value of this bit after changing the PID bits for the DCP from BUF to NAK, confirm that CSSTS and PBUSY are both cleared to 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. When the function controller function is selected, be sure to write 0 to this bit. 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1591 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit 2 Bit Name CCPL Initial Value 0 R/W Description 1 R/W* Control Transfer End Enable When the function controller function is selected, setting this bit to 1 enables the status stage of the control transfer to be completed. 0: Invalid 1: Completion of control transfer is enabled. When this bit is set to 1 while the corresponding PID bits are set to BUF, this module completes the control transfer stage. Specifically, during control read transfer, this module transmits the ACK handshake in response to the OUT transaction from the USB host, and outputs the zero-length packet in response to the IN transaction from the USB host during control write or no-data control transfer. However, on detecting the SET_ADDRESS request, this module operates in auto response mode from the setup stage up to the status stage completion irrespective of the setting of this bit. This module modifies this bit from 1 to 0 on receiving the new setup packet. A 1 cannot be written to this bit while VALID is 1. When the host controller function is selected, be sure to write 0 to this bit. Page 1592 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 1, 0 PID[1:0] 00 R/W Response PID Controls the response type of this module during control transfer. 00: NAK response 01: BUF response (depending on the buffer state) 10: STALL response 11: STALL response (1) When the host controller function is selected Modify the setting of these bits from NAK to BUF using the following procedure.  When the transmitting direction is set Write all the transmit data to the FIFO buffer while UACT is 1 and PID is NAK, and then set PID to BUF. After PID has been set to BUF, this module executes the OUT transaction (or PING transaction).  When the receiving direction is set Check that the FIFO buffer is empty (or empty the buffer) while UACT is 1 and PID is NAK, and then set PID to BUF. After PID has been set to BUF, this module executes the IN transaction. This module modifies the setting of these bits as follows. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  This module sets PID to STALL (11) on receiving the data of the size exceeding the maximum packet size when PID has been set to BUF.  This module sets PID to NAK on detecting a receive error such as a CRC error three consecutive times.  This module also sets PID to STALL (11) on receiving the STALL handshake. Page 1593 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 1, 0 PID[1:0] 00 R/W Even if the PID bits have been modified to NAK after this module has issued S-SPLIT of the split transaction for the selected pipe (while CSSTS indicates 1), this module continues the transaction until C-SPLIT completes. On completion of CSPLIT, this module sets PID to NAK. (2) When the function controller function is selected This module modifies the setting of these bits as follows.  This module modifies PID to NAK on receiving the setup packet. Here, this module sets VALID to 1. PID cannot be modified until VALID is set to 0.  This module sets PID to STALL (11) on receiving the data of the size exceeding the maximum packet size when PID has been set to BUF.  This module sets PID to STALL (1x) on detecting the control transfer sequence error.  This module sets PID to NAK on detecting the USB bus reset. This module does not reference to the setting of the PID bits while the SET_ADDRESS request is processed (auto processing). Notes: 1. This bit is always read as 0. Only 1 can be written. 2. Only 1 can be written. Page 1594 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.31 Pipe Window Select Register (PIPESEL) PIPE1 to PIPE 9 should be set using PIPESEL, PIPECFG, PIPEBUF, PIPEMAXP, PIPEPERI, PIPEnCTR, PIPEnTRE, and PIPEnTRN. After selecting the pipe using PIPESEL, functions of the pipe should be set using PIPECFG, PIPEBUF, PIPEMAXP, and PIPEPERI. PIPEnCTR, PIPEnTRE, and PIPEnTRN can be set regardless of the pipe selection in PIPESEL. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 — — — — — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 4  All 0 R Reserved 3 2 1 0 PIPESEL[3:0] 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 3 to 0 PIPESEL[3:0] 0000 R/W Pipe Window Select Setting 0001 to 1001to these bits, the PIPECFG, PIPEBUF, PIPEMAXP, and PIPEPERI registers, these registers indicate the information or set values of the corresponding pipe. 0000: No pipe selected 0001: PIPE1 0010: PIPE2 0011: PIPE3 0100: PIPE4 0101: PIPE5 0110: PIPE6 0111: PIPE7 1000: PIPE8 1001: PIPE9 Other than above: Setting prohibited Setting 0000 to these bits, the PIPECFG, PIPEBUF, PIPEMAXP, and PIPEPERI registers all indicate 0. Here, writing to these registers are invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1595 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.32 Pipe Configuration Register (PIPECFG) PIPECFG is a register that specifies the transfer type, buffer memory access direction, and endpoint numbers for PIPE1 to PIPE9. It also selects continuous or non-continuous transfer mode, single or double buffer mode, and whether to continue or disable pipe operation at the end of transfer. This register is initialized by a power-on reset. Bit: 15 14 TYPE[1:0] Initial value: 0 R/W: R/W Page 1596 of 3092 0 R/W 13 12 11 10 7 6 5 4 — — — BFRE DBLB CNTMD 9 8 SHT NAK — — DIR 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 3 2 1 0 EPNUM[3:0] 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 15, 14 TYPE[1:0] 00 R/W Transfer Type Selects the transfer type for the pipe selected by the PIPESEL bits (selected pipe)  PIPE1 and PIPE2 00: Pipe cannot be used 01: Bulk transfer 10: Setting prohibited 11: Isochronous transfer  PIPE3 to PIPE5 00: Pipe cannot be used 01: Bulk transfer 10: Setting prohibited 11: Setting prohibited  PIPE6 and PIPE7 00: Pipe cannot be used 01: Setting prohibited 10: Interrupt transfer 11: Setting prohibited Before setting PID to BUF for the selected pipe (before starting USB communication using the selected pipe), be sure to set these bits to the value other than 00. Modify these bits while the PID bits for the selected pipe are set to NAK. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1597 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name 13 to 11  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 BFRE 0 R/W BRDY Interrupt Operation Specification Specifies the BRDY interrupt generation timing from this module to the CPU with respect to the selected pipe. 0: BRDY interrupt upon transmitting or receiving of data 1: BRDY interrupt upon completion of reading of data This bit is valid when any of pipes 1 to 5 is selected. When this bit has been set to 1 and the selected pipe is in the receiving direction, this module detects the transfer completion and generates the BRDY interrupt on having read the pertinent packet. When the BRDY interrupt is generated with the above conditions, 1 needs to be written to BCLR. The FIFO buffer assigned to the selected pipe is not enabled for reception until 1 is written to BCLR. When this bit has been set to 1 and the selected pipe is in the transmitting direction, this module does not generate the BRDY interrupt. For details, refer to section 29.4.2 (1), BRDY Interrupt. Modify these bits while CSSTS is 0 and PID is NAK and before the pipe is selected by the CURPIPE bits. To modify these bits after completing USB communication using the selected pipe, write 1 and then 0 to ACLRM continuously to clear the FIFO buffer assigned to the selected pipe while the CSSTS, PID, and CURPIPE bits are in the abovedescribed state. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. Page 1598 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 9 DBLB 0 R/W Double Buffer Mode Selects either single or double buffer mode for the FIFO buffer used by the selected pipe. 0: Single buffer 1: Double buffer This bit is valid when PIPE1 to PIPE5 are selected. When this bit has been set to 1, this module assigns two planes of the FIFO buffer size specified by the BUFSIZE bits in PIPEBUF to the selected pipe. Specifically, the following expression determines the FIFO buffer size assigned to the selected pipe by this module. (BUFSIZE + 1)  64  (DBLB + 1) [bytes] Modify these bits while CSSTS is 0 and PID is NAK and before the pipe is selected by the CURPIPE bits. To modify these bits after completing USB communication using the selected pipe, write 1 and then 0 to ACLRM continuously to clear the FIFO buffer assigned to the selected pipe while the CSSTS, PID, and CURPIPE bits are in the abovedescribed state. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1599 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 8 CNTMD 0 R/W Continuous Transfer Mode Specifies whether to use the selected pipe in continuous transfer mode. 0: Non-continuous transfer mode 1: Continuous transfer mode This bit is valid when PIPE1 to PIPE5 are selected by the PIPESEL bits and bulk transfer is selected (TYPE = 01). Modify these bits while CSSTS is 0 and PID is NAK and before the pipe is selected by the CURPIPE bits. To modify these bits after completing USB communication using the selected pipe, write 1 and then 0 to ACLRM continuously to clear the FIFO buffer assigned to the selected pipe while the CSSTS, PID, and CURPIPE bits are in the abovedescribed state. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. Page 1600 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 SHTNAK 0 R/W Pipe Disabled at End of Transfer Specifies whether to modify PID to NAK upon the end of transfer when the selected pipe is in the receiving direction. 0: Pipe continued at the end of transfer 1: Pipe disabled at the end of transfer This bit is valid when the selected pipe is PIPE1 to PIPE5 in the receiving direction. When this bit has been set to 1 for the selected pipe in the receiving direction, this module modifies the PID bits corresponding to the selected pipe to NAK on determining the end of the transfer. This module determines that the transfer has ended on any of the following conditions.  A short packet (including a zero-length packet) is successfully received.  The transaction counter is used and the number of packets specified by the counter are successfully received. Modify these bits while CSSTS is 0 and PID is NAK. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. This bit should be cleared to 0 for the pipe in the transmitting direction. 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1601 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 4 DIR 0 R/W Transfer Direction Specifies the transfer direction for the selected pipe. 0: Receiving direction 1: Sending direction When this bit has been set to 0, this module uses the selected pipe in the receiving direction, and when this bit has been set to 1, this module uses the selected pipe in the transmitting direction. Modify these bits when the value of CSSTS is 0, the PID bits are set to NAK, and no pipe is specified by the CURPIPE bits. To modify these bits after completing USB communication using the selected pipe, write 1 and then 0 to ACLRM continuously to clear the FIFO buffer assigned to the selected pipe while the CSSTS, PID, and CURPIPE bits are in the abovedescribed state. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. 3 to 0 EPNUM[3:0] 0000 R/W Endpoint Number These bits specify the endpoint number for the selected pipe. Setting 0000 means unused pipe. Modify these bits while CSSTS is 0 and PID is NAK. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. Do not make the settings such that the combination of the set values in the DIR and EPNUM bits should be the same for two or more pipes (EPNUM = 0000 can be set for all the pipes). Page 1602 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.33 Pipe Buffer Setting Register (PIPEBUF) PIPEBUF is a register that specifies the buffer size and buffer number for PIPE1 to PIPE9. This register is initialized by a power-on reset. Bit: 15 14 — Initial value: 0 R/W: R 13 12 11 10 BUFSIZE[4:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 9 8 7 — — — 0 R 0 R 0 R 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W BUFNMB[6:0] 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1603 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name 14 to 10 BUFSIZE[4:0] Initial Value R/W Description H'00 R/W Buffer Size Specifies the size of the buffer for the pipe selected by the PIPESEL bits (selected pipe) in terms of blocks, where one block comprises 64 bytes. 00000 (H'00): 64 bytes 00001 (H'01): 128 bytes : : 11111 (H'1F): 2 Kbytes When the DBLB bit has been set to 1, this module assigns two planes of the FIFO buffer size specified by the BUFSIZE bits to the selected pipe. Specifically, the following expression determines the FIFO buffer size assigned to the selected pipe by this module. (BUFSIZE + 1)  64  (DBLB + 1) [bytes] The valid value for these bits depends on the selected pipe.  PIPE1 to PIPE5: Any value from H'00 to H'1F is valid.  PIPE6 to PIPE9: H'00 should be set. When used with CNTMD = 1, set an integer multiple of the maximum packet size to the BUFSIZE bits. Modify these bits when the value of CSSTS is 0, the PID bits are set to NAK, and no pipe is specified by the CURPIPE bits. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. 9 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1604 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 6 to 0 BUFNMB[6:0] H'00 R/W Buffer Number These bits specify the start block number of the FIFO buffers to be assigned to the selected pipe. The following blocks of FIFO buffers are assigned to the selected pipe. Block number BUFNMB to block number BUFNMB + (BUFSIZE + 1) × (DBLB + 1) - 1 Specify a value from H'04 to H'7F. When the selected pipe is one of PIPE1 to PIPE5, any value can be set to these bits according to the user system. BUFNUMB = H'00 to H'03 are used exclusively for DCP. BUFNMB = H'04 is used exclusively for PIPE6. When PIPE6 is not used, H'04 can be used for other pipes. When PIPE6 is selected, writing to these bits is invalid and H'04 is automatically assigned by this module. BUFNMB = H'05 is used exclusively for PIPE7. When PIPE7 is not used, H'05 can be used for other pipes. When PIPE7 is selected, writing to these bits is invalid and H'05 is automatically assigned by this module. BUFNUMB = H'06 is used exclusively for PIPE8. When PIPE8 is not used, H'06 can be used for other pipes. When PIPE8 is selected, writing to these bits is invalid and H'06 is automatically assigned by this module. BUFNUMB = H'07 is used exclusively for PIPE9. When PIPE9 is not used, H'07 can be used for other pipes. When PIPE9 is selected, writing to these bits is invalid and H'07 is automatically assigned by this module. Modify these bits when the value of CSSTS is 0, the PID bits are set to NAK, and no pipe is specified by the CURPIPE bits. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1605 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.34 Pipe Maximum Packet Size Register (PIPEMAXP) PIPEMAXP is a register that specifies the maximum packet size for PIPE1 to PIPE9. This register is initialized by a power-on reset. Bit: 15 14 13 12 DEVSEL[3:0] Initial value: 0 R/W: R/W Bit 0 R/W 0 R/W Bit Name 15 to 12 DEVSEL[3:0] 11 10 9 8 7 6 — 0 R/W 0 R 5 4 3 2 1 0 * R/W * R/W * R/W * R/W * R/W MXPS[10:0] * R/W * R/W * R/W * R/W Initial Value R/W Description 0000 R/W Device Select * R/W * R/W When the host controller function is selected, these bits specify the USB address of the communication target peripheral device. 0000: Address 0000 0001: Address 0001 0010: Address 0010 : : 1010: Address 1010 Other than above: Setting prohibited These bits should be set after setting the address to the DEVADDn register corresponding to the value to be set in these bits. For example, before setting DEVSEL to 0010, the address should be set to the DEVADD2 register. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. When the function controller function is selected, these bits should be set to B'0000. 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 1606 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 10 to 0 MXPS[10:0] * R/W Maximum Packet Size Specifies the maximum data payload (maximum packet size) for the selected pipe. The valid value for these bits depends on the pipe as follows. PIPE1, PIPE2: 1 byte (H'001) to 1,024 bytes (H'400) PIPE3 to PIPE5: 8 bytes (H'008), 16 bytes (H'010), 32 bytes (H'020), 64 bytes (H'040), and 512 bytes (H'200) (Bits 2 to 0 are not provided.) PIPE6 to PIPE9: 1 byte (H'001) to 64 bytes (H'040) These bits should be set to the appropriate value for each transfer type based on the USB Specification. For split transactions using the isochronous pipe, these bits should be set to 188 bytes or less. Modify these bits when the value of CSSTS is 0, the PID bits are set to NAK, and no pipe is specified by the CURPIPE bits. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. While MXPS is 0, do not write to the FIFO buffer or set PID to BUF. Note: * The initial value of MXPS is H'000 when no pipe is selected with the PIPESEL bits in PIPESEL and H'040 when a pipe is selected with the PIPESEL bit in PIPESEL. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1607 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.35 Pipe Timing Control Register (PIPEPERI) PIPEPERI is a register that selects whether the buffer is flushed or not when an interval error occurred during isochronous IN transfer, and sets the interval error detection interval for PIPE1 to PIPE9. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 — — — IFIS — — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 2 1 0 IITV[2:0] 0 R/W 0 R/W 0 R/W Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 0 R/W Isochronous IN Buffer Flush Specifies whether to flush the buffer when the pipe selected by the PIPESEL bits (selected pipe) is used for isochronous IN transfers. 0: The buffer is not flushed. 1: The buffer is flushed. When the function controller function is selected and the selected pipe is for isochronous IN transfers, this module automatically clears the FIFO buffer when this module fails to receive the IN token from the USB host within the interval set by the IITV bits in terms of () frames. In double buffer mode (DBLB = 1), this module only clears the data in the plane used earlier. This module clears the FIFO buffer on receiving the SOF packet immediately after the () frame in which this module has expected to receive the IN token. Even if the SOF packet is corrupted, this module also clears the FIFO buffer at the right timing to receive the SOF packet by using the internal interpolation. When the host controller function is selected, set this bit to 0. When the selected pipe is not for the isochronous transfer, set this bit to 0. Bit Bit Name IFIS Page 1608 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 11 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 IITV[2:0] 000 R/W Interval Error Detection Interval Specifies the interval error detection timing for the selected pipe in terms of frames, which is expressed as n-th power of 2 (n is the value to be set). As described later, the detailed functions are different in host controller mode and in function controller mode. Modify these bits when the value of CSSTS is 0, the PID bits are set to NAK, and no pipe is specified by the CURPIPE bits. Before modifying these bits after modifying the PID bits for the selected pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. Before modifying these bits after USB communication has been completed with these bits set to a certain value, set PID to NAK and then set ACLRM to 1 to initialize the interval timer. The IITV bits are invalid for PIPE3 to PIPE5; set these bits to 000 for these pipes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1609 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) PIPEnCTR is a register that is used to confirm the buffer memory status for the corresponding pipe, change and confirm the data PID sequence bit, determine whether auto response mode is set, determine whether auto buffer clear mode is set, and set a response PID for PIPE1 to PIPE9. This register can be set regardless of the pipe selection in PIPESEL. This register is initialized by a power-on reset. PID[1:0] are initialized by a USB bus reset. (1) PIPEnCTR (n = 1 to 5) Bit: 15 14 13 12 BSTS INBUFM CSCLR CSSTS Initial value: 0 R/W: R 0 R 0 R/W* 0 R 11 — 0 R 10 9 8 7 6 5 AT ACLRM SQCLR SQSET SQMON PBUSY REPM 0 R/W 0 R/W 0 0 R/W* R/W* Bit Bit Name Initial Value R/W Description 15 BSTS 0 R Buffer Status 0 R 0 R 4 3 2 — — — 0 R 0 R 0 R 1 0 PID[1:0] 0 R/W 0 R/W Indicates the FIFO buffer status for the pertinent pipe. 0: Buffer access is disabled. 1: Buffer access is enabled. The meaning of this bit depends on the settings of the DIR, BFRE, and DCLRM bits as shown in table 29.10. Page 1610 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 14 INBUFM 0 R IN Buffer Monitor Indicates the pertinent FIFO buffer status when the pertinent pipe is in the transmitting direction. 0: There is no data to be transmitted in the buffer memory. 1: There is data to be transmitted in the buffer memory. When the pertinent pipe is in the transmitting direction (DIR = 1), this module sets this bit to 1 when at least one FIFO buffer plane of data has been written. This module sets this bit to 0 when this module completes transmitting the data from the FIFO buffer plane to which all the data has been written. In double buffer mode (DBLB = 1), this module sets this bit to 0 when this module completes transmitting the data from the two FIFO buffer planes before one FIFO buffer plane of data has been written. This bit indicates the same value as the BSTS bit when the pertinent pipe is in the receiving direction (DIR = 0). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1611 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 13 CSCLR 0 R/W* C-SPLIT Status Clear Bit When the host controller function is selected, setting this bit to 1 allows this module to clear the CSSTS bit to 0. 0: Writing invalid 1: Clears the CSSTS bit to 0. For the transfer using the split transaction, to restart the next transfer with the S-SPLIT forcibly, set this bit to 1. However, for the normal split transaction, this module automatically clears the CSSTS bit to 0 upon completion of the C-SPLIT; therefore, clearing the CSSTS bit is not necessary. Controlling the CSSTS bit through this bit must be done while UACT is 0 and thus communication is halted or while no transfer is being performed with bus disconnection detected. Setting this bit to 1 while CSSTS is 0 has no effect. When the function controller function is selected, be sure to write 0 to this bit. 12 CSSTS 0 R CSSTS Status Bit Indicates the C-SPLIT status of the split transaction when the host controller function is selected. 0: START-SPLIT (S-SPLIT) transaction being processed or the transfer not using the split transaction in progress 1: C-SPLIT transaction being processed This module sets this bit to 1 upon start of the CSPLIT and clears this bit to 0 upon detection of CSPLIT completion. If the USB device is detached when processing of a C-SPLIT transaction is in progress, the CSSTS bit may remain set to 1. In such a case (DTCH = 1 detected), use the CSCLR bit to clear the CSSTS bit to 0. Indicates the valid value only when the host controller function is selected. 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 1612 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 10 ATREPM 0 R/W Auto Response Mode Enables or disables auto response mode for the pertinent pipe. 0: Auto response disabled 1: Auto response enabled When the function controller function is selected and the pertinent pipe is for bulk transfer, this bit can be set to 1. When this bit is set to 1, this module responds to the token from the USB host as described below. (1) When the pertinent pipe is for bulk IN transfer (TYPE = 01 and DIR = 1) When ATREPM = 1 and PID = BUF, this module transmits a zero-length packet in response to the IN token. This module updates (allows toggling of) the sequence toggle bit (DATA-PID) each time this module receives the ACK from the USB host (in a single transaction, IN token is received, zerolength packet is transmitted, and then ACK is received.). In this case, this module does not generate the BRDY or BEMP interrupt. (2) When the pertinent pipe is for bulk OUT transfer (TYPE = 01 and DIR = 0) When ATREPM = 1 and PID = BUF, this module returns NAK in response to the OUT (or PING) token and generates the NRDY interrupt. Modify this bit while CSSTS is 0 and PID is NAK. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1613 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 10 ATREPM 0 R/W For USB communication in auto response mode, set this bit to 1 while the FIFO buffer is empty. Do not write to the FIFO buffer during USB communication in auto response mode. When the pertinent pipe is for isochronous transfer, be sure to set this bit to 0. When the host controller function is selected, set this bit to 0. 9 ACLRM 0 R/W Auto Buffer Clear Mode Enables or disables automatic buffer clear mode for the pertinent pipe. 0: Disabled 1: Enabled (all buffers are initialized) To delete all the information assigned to the pertinent pipe from the FIFO buffer, write 1 and 0 in succession to the ACLRM bit. Table 29.11 (1) lists the information related to the USB 2.0 host/function module that is cleared by setting the ACLRM bit to 1 and then to 0 in succession. Table 29.11 (2) lists the cases in which it is necessary to do this. Modify this bit while CSSTS is 0, PID is NAK, and the pertinent pipe is not specified in the CURPIPE bits. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. Page 1614 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 8 SQCLR 0 R/W* Toggle Bit Clear This bit should be set to 1 to clear the expected value (to set DATA0 as the expected value) of the sequence toggle bit for the next transaction of the pertinent pipe. 0: Invalid 1: Specifies DATA0. Setting this bit to 1 allows this module to set DATA0 as the expected value of the sequence toggle bit of the pertinent pipe. This module always sets this bit to 0. When the host controller function is selected, setting this bit to 1 for the pipe for bulk OUT transfer, this module starts the next transfer of the pertinent pipe with the PING token. Set the SQCLR bit to 1 while CSSTS is 0 and PID is NAK. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1615 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 SQSET 0 R/W* Toggle Bit Set This bit should be set to 1 to set DATA1 as the expected value of the sequence toggle bit for the next transaction of the pertinent pipe. 0: Invalid 1: Specifies DATA1. Setting this bit to 1 allows this module to set DATA1 as the expected value of the sequence toggle bit of the pertinent pipe. This module always sets this bit to 0. Set the SQSET bit to 1 while CSSTS is 0 and PID is NAK. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. 6 SQMON 0 R Toggle Bit Confirmation Indicates the expected value of the sequence toggle bit for the next transaction of the pertinent pipe. 0: DATA0 1: DATA1 When the pertinent pipe is not for the isochronous transfer, this module allows this bit to toggle upon normal completion of the transaction. However, this bit is not allowed to toggle when a DATA-PID disagreement occurs during the receiving transfer. Page 1616 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 5 PBUSY 0 R Pipe Busy This bit indicates whether the relevant pipe is used or not for the transaction. 0: The relevant pipe is not used for the transaction. 1: The relevant pipe is used for the transaction. The USB 2.0 host/function module switches the PBUSY bit from 0 to 1 when a USB transaction using the pertinent pipe starts. It clears the PBUSY bit from 1 to 0 when one transaction completes successfully. Reading this bit after PID has been set to NAK allows checking that modification of the pipe settings is possible. For details, refer to section 29.4.3 (1), Pipe Control Register Switching Procedures. 4 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1617 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 1, 0 PID[1:0] 00 R/W Response PID Specifies the response type for the next transaction of the pertinent pipe. 00: NAK response 01: BUF response (depending on the buffer state) 10: STALL response 11: STALL response The default setting of these bits is NAK. Modify the setting to BUF to use the pertinent pipe for USB transfer. Tables 29.12 and 29.13 show the basic operation (operation when there are no errors in the transmitted and received packets) of this module depending on the PID bit setting. After modifying the setting of these bits from BUF to NAK during USB communication using the pertinent pipe, check that PBUSY is 0 to see if USB communication using the pertinent pipe has actually entered the NAK state. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. After S-SPLIT is issued (CSSTS = 1) for split transaction in the pertinent pipe, the transaction continues until C-SPLIT is completed even when the PID bits are set to NAK. This module modifies the setting of these bits as follows. Page 1618 of 3092  This module sets PID to NAK on recognizing the completion of the transfer when the pertinent pipe is in the receiving direction and the SHTNAK bit for the selected pipe has been set to 1.  This module sets PID to STALL (11) on receiving the data packet with the payload exceeding the maximum packet size of the pertinent pipe.  This module sets PID to NAK on detecting a USB bus reset when the function controller function is selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 1, 0 PID[1:0] 00 R/W  This module sets PID to NAK on detecting a receive error such as a CRC error three consecutive times when the host controller function is selected.  This module sets PID to STALL (11) on receiving the STALL handshake when the host controller function is selected. To specify each response type, set these bits as follows. Note: *  To make a transition from NAK (00) to STALL, set 10.  To make a transition from BUF (01) to STALL, set 11.  To make a transition from STALL (11) to NAK, set 10 and then 00.  To make a transition from STALL to BUF, set 00 (NAK) and then 01 (BUF). Only 0 can be read and 1 can be written. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1619 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.10 Meaning of BSTS Bit DIR Bit BFRE Bit DCLRM Bit Meaning of BSTS Bit 0 0 0 1: The received data can be read from the FIFO buffer. 0: The received data has been completely read from the FIFO buffer. 1 1 0 Setting prohibited 1: The received data can be read from the FIFO buffer. 0: BCLR has been set to 1 after the received data has been completely read from the FIFO buffer. 1 1: The received data can be read from the FIFO buffer. 0: The received data has been completely read from the FIFO buffer. 1 0 0 1: The transmit data can be written to the FIFO buffer. 0: The transmit data has been completely written to the FIFO buffer. 1 Table 29.11(1) 1 Setting prohibited 0 Setting prohibited 1 Setting prohibited Information Cleared by this Module by Setting ACLRM = 1 No. Information Cleared by ACLRM Bit Manipulation 1 All the information in the FIFO buffer assigned to the pertinent pipe (all the information in two FIFO buffer planes in double buffer mode) 2 The interval count value when the pertinent pipe is for isochronous transfer Table 29.11(2) Cases That Require Setting ACLRM to 1 No. Cases in which Clearing the Information is Necessary 1 When it is necessary to clear all the information assigned to the pertinent pipe from the FIFO buffer 2 When the interval count value is to be reset 3 When the BFRE setting is modified 4 When the DBLB setting is modified 5 When the transaction count function is forcibly terminated Page 1620 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.12 Operation of This Module depending on PID Setting (when Host Controller Function is Selected) Transfer Direction (DIR Bit) Operation of This Module PID Transfer Type 00 (NAK) Operation does not Operation does not Does not issue tokens. depend on the depend on the setting. setting. 01 (BUF) Bulk or interrupt Operation does not Issues tokens while UACT is 1 and the depend on the FIFO buffer corresponding to the setting. pertinent pipe is ready for transmission and reception. Does not issue tokens while UACT is 0 or the FIFO buffer corresponding to the pertinent pipe is not ready for transmission or reception. Isochronous Operation does not Issues tokens irrespective of the status depend on the of the FIFO buffer corresponding to the setting. pertinent pipe. 10 (STALL) or Operation does not Operation does not Does not issue tokens. 11 (STALL) depend on the depend on the setting. setting. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1621 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.13 Operation of This Module depending on PID Setting (when Function Controller Function is Selected) Transfer Direction (DIR Bit) Operation of This Module PID Transfer Type 00 (NAK) Bulk or interrupt Operation does not Returns NAK in response to the token depend on the from the USB host. setting. Isochronous Receiving direction Returns nothing in response to a token (DIR = 0) from the USB host. Transmitting direction (DIR = 1) 01 (BUF) Bulk Returns a zero-length packet in response to a token from the USB host. Receiving direction Receives data and returns ACK in (DIR = 0) response to the OUT token from the USB host if the FIFO buffer corresponding to the pertinent pipe is ready for reception. Returns NAK if not ready. Returns ACK in response to the PING token from the USB host if the FIFO buffer corresponding to the pertinent pipe is ready for reception. Returns NYET if not ready. Page 1622 of 3092 Interrupt Receiving direction Receives data and returns ACK in (DIR = 0) response to the OUT token from the USB host if the FIFO buffer corresponding to the pertinent pipe is ready for reception. Returns NAK if not ready. Bulk or interrupt Transmitting direction (DIR = 1) Isochronous Receiving direction Receives data in response to the OUT (DIR = 0) token from the USB host if the FIFO buffer corresponding to the pertinent pipe is ready for reception. Discards data if not ready. Transmits data in response to the token from the USB host if the corresponding FIFO buffer is ready for transmission. Returns NAK if not ready. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module PID Transfer Type 01 (BUF) Isochronous Transfer Direction (DIR Bit) Operation of This Module Transmitting direction (DIR = 1) 10 (STALL) or Bulk or interrupt 11 (STALL) Operation does not Returns STALL in response to the token depend on the from the USB host. setting. Isochronous (2) Transmits data in response to the token from the USB host if the corresponding FIFO buffer is ready for transmission. Transmits the zero-length packet if not ready. Operation does not Returns nothing in response to the depend on the token from the USB host. setting PIPEnCTR (n = 6 to 9) Bit: 15 14 BSTS Initial value: 0 R/W: R 11 10 — CSCLR CSSTS 13 12 — — 0 R 0 R/W* 0 R 0 R 0 R/W 9 8 7 6 5 ACLRM SQCLR SQSET SQMON PBUSY 0 R/W 0 0 R/W* R/W* Bit Bit Name Initial Value R/W Description 15 BSTS 0 R Buffer Status 0 R 0 R 4 3 2 — — — 0 R 0 R 0 R 1 0 PID[1:0] 0 R/W 0 R/W Indicates the FIFO buffer status for the pertinent pipe. 0: Buffer access is disabled. 1: Buffer access is enabled. The meaning of this bit depends on the settings of the DIR, BFRE, and DCLRM bits as shown in table 29.10. 14  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1623 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 13 CSCLR 0 R/W* C-SPLIT Status Clear Bit Setting this bit to 1 allows this module to clear the CSSTS bit of the pertinent pipe to 0. 0: Writing invalid 1: Clears the CSSTS bit to 0. For the transfer using the split transaction, to restart the next transfer with the S-SPLIT forcibly, set this bit to 1. However, for the normal split transaction, this module automatically clears the CSSTS bit to 0 upon completion of the C-SPLIT; therefore, clearing the CSSTS bit is not necessary. Controlling the CSSTS bit through this bit must be done while UACT is 0 thus communication is halted or while no transfer is being performed with bus disconnection detected. Setting this bit to 1 while CSSTS is 0 has no effect. When the function controller function is selected, be sure to write 0 to this bit. 12 CSSTS 0 R/W CSSTS Status Bit Indicates the C-SPLIT status of the split transaction when the host controller function is selected. 0: START-SPLIT (S-SPLIT) transaction being processed or the transfer not using the split transaction in progress 1: C-SPLIT transaction being processed This module sets this bit to 1 upon start of the CSPLIT and clears this bit to 0 upon detection of CSPLIT completion. Indicates the valid value only when the host controller function is selected. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1624 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 9 ACLRM 0 R/W Auto Buffer Clear Mode Enables or disables automatic buffer clear mode for the pertinent pipe. 0: Disabled 1: Enabled (all buffers are initialized) To delete all the information assigned to the pertinent pipe from the FIFO buffer, write 1 and 0 in succession to the ACLRM bit. Table 29.14 (1) lists the information related to the USB 2.0 host/function module that is cleared by setting the ACLRM bit to 1 and then to 0 in succession. Table 29.14 (2) lists the cases in which it is necessary to do this. Modify this bit while CSSTS is 0 and PID is NAK and before the pipe is selected by the CURPIPE bits. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1625 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 8 SQCLR 0 R/W* Toggle Bit Clear This bit should be set to 1 to clear the expected value (to set DATA0 as the expected value) of the sequence toggle bit for the next transaction of the pertinent pipe. 0: Invalid 1: Specifies DATA0. Setting this bit to 1 allows this module to set DATA0 as the expected value of the sequence toggle bit of the pertinent pipe. This module always sets this bit to 0. When the host controller function is selected, setting this bit to 1 for the pipe for bulk OUT transfer, this module starts the next transfer of the pertinent pipe with the PING token. Set the SQCLR bit to 1 while CSSTS is 0 and PID is NAK. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. Page 1626 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 SQSET 0 R/W* Toggle Bit Set This bit should be set to 1 to set DATA1 as the expected value of the sequence toggle bit for the next transaction of the pertinent pipe. 0: Invalid 1: Specifies DATA1. Setting this bit to 1 allows this module to set DATA1 as the expected value of the sequence toggle bit of the pertinent pipe. This module always sets this bit to 0. Set the SQSET bit to 1 while CSSTS is 0 and PID is NAK. Before modifying this bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. 6 SQMON 0 R Toggle Bit Confirmation Indicates the expected value of the sequence toggle bit for the next transaction of the pertinent pipe. 0: DATA0 1: DATA1 When the pertinent pipe is not for the isochronous transfer, this module allows this bit to toggle upon normal completion of the transaction. However, this bit is not allowed to toggle when a DATA-PID disagreement occurs during the receiving transfer. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1627 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 5 PBUSY 0 R Pipe Busy This bit indicates whether the relevant pipe is used or not for the transaction. 0: The relevant pipe is not used for the transaction. 1: The relevant pipe is used for the transaction. This module modifies this bit from 0 to 1 upon start of the USB transaction for the pertinent pipe, and clears it from 1 to 0 when one transaction completes successfully. Reading this bit after PID has been set to NAK allows checking that modification of the pipe settings is possible. For details, refer to section 29.4.3 (1), Pipe Control Register Switching Procedures. 4 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1628 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 1, 0 PID[1:0] 00 R/W Response PID Specifies the response type for the next transaction of the pertinent pipe. 00: NAK response 01: BUF response (depending on the buffer state) 10: STALL response 11: STALL response The default setting of these bits is NAK. Modify the setting to BUF to use the pertinent pipe for USB transfer. Tables 29.12 and 29.13 show the basic operation (operation when there are no errors in the transmitted and received packets) of this module depending on the PID bit setting. After modifying the setting of these bits from BUF to NAK during USB communication using the pertinent pipe, check that PBUSY is 0 to see if USB communication using the pertinent pipe has actually entered the NAK state. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. After S-SPLIT is issued (CSSTS = 1) for split transaction in the pertinent pipe, the transaction continues until C-SPLIT is completed even when the PID bits are set to NAK. This module modifies the setting of these bits as follows. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  This module sets PID to NAK on recognizing the completion of the transfer when the pertinent pipe is in the receiving direction and the SHTNAK bit for the selected pipe has been set to 1.  This module sets PID to STALL (11) on receiving the data packet with the payload exceeding the maximum packet size of the pertinent pipe.  This module sets PID to NAK on detecting a USB bus reset when the function controller function is selected. Page 1629 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 1, 0 PID[1:0] 00 R/W  This module sets PID to NAK on detecting a receive error such as a CRC error three consecutive times when the host controller function is selected.  This module sets PID to STALL (11) on receiving the STALL handshake when the host controller function is selected. To specify each response type, set these bits as follows. Note: *  To make a transition from NAK (00) to STALL, set 10.  To make a transition from BUF (01) to STALL, set 11.  To make a transition from STALL (11) to NAK, set 10 and then 00.  To make a transition from STALL to BUF, set 00 (NAK) and then 01 (BUF). Only 0 can be read and 1 can be written. Page 1630 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.14 (1) Information Cleared by this Module by Setting ACLRM = 1 No. Information Cleared by ACLRM Bit Manipulation 1 All the information in the FIFO buffer assigned to the pertinent pipe 2 When the host controller function is selected, the interval count value when the pertinent pipe is for isochronous transfer Table 29.14 (2) Cases That Require Setting ACLRM to 1 No. Cases in which Clearing the Information is Necessary 1 When it is necessary to clear all the information assigned to the pertinent pipe from the FIFO buffer 2 When the interval count value is to be reset 3 When the BFRE setting is modified 4 When the transaction count function is forcibly terminated 29.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5) PIPEnTRE is a register that enables or disables the transaction counter corresponding to PIPE1 to PIPE5, and clears the transaction counter. This register is initialized by a power-on reset. Bit: 15 14 13 12 11 10 7 6 5 4 3 2 1 0 — — — — — — TRENB TRCLR — — — — — — — — Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 0 R/W R/W*1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 10  9 8 Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1631 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 9 TRENB 0 R/W Transaction Counter Enable Enables or disables the transaction counter. 0: The transaction counter is disabled. 1: The transaction counter is enabled. For the pipe in the receiving direction, setting this bit to 1 after setting the total number of the packets to be received in the TRNCNT bits allows this module to control hardware as described below on having received the number of packets equal to the set value in the TRNCNT bits.  In continuous transmission/reception mode (CNTMD = 1), this module switches the FIFO buffer to the CPU side even if the FIFO buffer is not full on completion of reception.  While SHTNAK is 1, this module modifies the PID bits to NAK for the corresponding pipe on having received the number of packets equal to the set value in the TRNCNT bits.  While BFRE is 1, this module asserts the BRDY interrupt on having received the number of packets equal to the set value in the TRNCNT bits and then reading out the last received data. For the pipe in the transmitting direction, set this bit to 0. When the transaction counter is not used, set this bit to 0. When the transaction counter is used, set the TRNCNT bits before setting this bit to 1. Set this bit to 1 before receiving the first packet to be counted by the transaction counter. 8 TRCLR 0 R/W*1 Transaction Counter Clear Clears the current value of the transaction counter corresponding to the pertinent pipe and then sets this bit to 0. 0: Invalid 1: The current counter value is cleared. Page 1632 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Only 0 can be read and 1 can be written. 2. Modify each bit in this register while CSSTS is 0 and PID is NAK. Before modifying each bit after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. 29.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) PIPEnTRN is a transaction counter corresponding to PIPE1 to PIPE5. This register is initialized by a power-on reset, but retains the set value by a USB bus reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W TRNCNT[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 15 to 0 TRNCNT[15:0] All 0 0 R/W 0 R/W 0 R/W 0 R/W R/W Description R/W Transaction Counter When written to: Specifies the number of transactions to be transferred through DMA. When read from: Indicates the specified number of transactions if TRENB is 0. Indicates the number of currently counted transaction if TRENB is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1633 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Initial Value Bit Bit Name 15 to 0 TRNCNT[15:0] All 0 R/W Description R/W This module increments the value of these bits by one when all of the following conditions are satisfied on receiving the packet.  TRENB is 1.  (TRNCNT set value  current counter value + 1) on receiving the packet.  The payload of the received packet agrees with the set value in the MXPS bits. This module clears the value of these bits to 0 when any of the following conditions are satisfied.  All the following conditions are satisfied. TRENB is 1. (TRNCNT set value = current counter value + 1) on receiving the packet. The payload of the received packet agrees with the set value in the MXPS bits.  All the following conditions are satisfied. TRENB is 1. This module has received a short packet.  The following condition is satisfied. The TRCLR bit has been set to 1. For the pipe in the transmitting direction, set these bits to 0. When the transaction counter is not used, set these bits to 0. Modify these bits while CSSTS is 0, PID is NAK, and TRENB is 0. Before modifying these bits after modifying the PID bits for the corresponding pipe from BUF to NAK, check that CSSTS and PBUSY are 0. However, if the PID bits have been modified to NAK by this module, checking PBUSY is not necessary. To modify the value of these bits, set TRNCNT to 1 before setting TRENB to 1. Page 1634 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 29.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A) DEVADDn is a register that specifies the address and port number of the hub to which the communication target peripheral device is connected and that also specifies the transfer speed of the peripheral device for PIPE0 to PIPEA. When the host controller function is selected, this register should be set before starting communication using each pipe. The bits in this register should be modified while no valid pipes are using the settings of this register. Valid pipes refer to the ones satisfying both of condition 1 and 2 below. 1. This register is selected by the DEVSEL bits as the communication target. 2. The PID bits are set to BUF for the selected pipe or the selected pipe is the DCP with SUREQ being 1. This register is initialized by a power-on reset. Bit: 15 14 — Initial value: 0 R/W: R 13 12 11 10 UPPHUB[3:0] 0 R/W 0 R/W 0 R/W 9 8 HUBPORT[2:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 1 0 USBSPD[1:0] 7 — — — — — — 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15  0 R Reserved 6 0 R/W This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1635 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name 14 to 11 UPPHUB[3:0] Initial Value R/W Description 0000 R/W Address of Hub to which Communication Target is Connected Specifies the USB address of the hub to which the communication target peripheral device is connected. 0000: The peripheral device is directly connected to the port of this LSI. 0001 to 1010: USB address of the hub 1011 to 1111: Setting prohibited When the host controller function is selected, this module refers to the setting of these bits to generate packets for split transactions. When the function controller function is selected, set these bits to 0000. 10 to 8 HUBPORT[2:0] 000 R/W Port Number of Hub to which Communication Target is Connected Specifies the port number of the hub to which the communication target peripheral device is connected. 000: The peripheral device is directly connected to the port of this LSI. 001 to 111: Port number of the hub When the host controller function is selected, this module refers to the setting of these bits to generate packets for split transactions. When the function controller function is selected, set these bits to 000. Page 1636 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Bit Name Initial Value R/W Description 7, 6 USBSPD[1:0] 00 R/W Transfer Speed of the Communication Target Device Specifies the USB transfer speed of the communication target peripheral device. 00: DEVADDn is not used. 01: Low speed 10: Full speed 11: High speed When the host controller function is selected, this module refers to the setting of these bits to generate packets. When the function controller function is selected, set these bits to 00. 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1637 of 3092 Section 29 USB 2.0 Host/Function Module 29.4 Operation 29.4.1 System Control and Oscillation Control SH7268 Group, SH7269 Group This section describes the register operations that are necessary to the initial settings of this module, and the registers necessary for power consumption control. (1) Resets Table 29.15 lists the types of controller resets. For the initialized states of the registers following the reset operations, see section 29.3, Register Description. Table 29.15 Types of Reset Name Operation Power-on reset Low level input from the RES pin USB bus reset Automatically detected by this module from the D and D lines when the function controller function is selected (2) Controller Function Selection This module can select the host controller function or function controller function using the DCFM bit in SYSCFG. Changing the DCFM bit should be done in the initial settings immediately after a power-on reset or in the D+ pull-up disabled (DPRPU = 0) and D + /D  pull-down disabled (DRPD = 0) state. (3) Enabling High-Speed Operation This module can select a USB communication speed (communication bit rate). When the host controller function is selected, the high-speed operation or full-speed/low-speed operation can be set. When the function controller function is selected, either the high-speed operation or full-speed operation can be selected. In order to enable the high-speed operation for this module, the HSE bit in SYSCFG should be set to 1. If high-speed mode has been enabled, this module executes the reset handshake protocol, and the USB communication speed is set automatically. The results of the reset handshake can be confirmed using the RHST bit in DVSTCTR. If high-speed operation has been disabled, this module operates at full-speed or low-speed. If the function controller function is also selected, this module operates at full-speed. Changing the HSE bit should be done between the ATTCH interrupt detection and bus reset execution when the host controller function is selected, or with the D+ line pull-up disabled (DPRPU = 0) when the host controller function is selected. Page 1638 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 29 USB 2.0 Host/Function Module USB Data Bus Resistor Control Figure 29.1 shows a diagram of the connections between this module and the USB connectors. This module incorporates a pull-up resistor for the D+ signal and a pull-down resistor for the D+ and D- signals. These signals can be pulled up or down using the DPRPU and DRPD bits in SYSCFG. When the function controller function is selected, set the DPRPU bit in the SYSCFG register to 1 and pull up the D+ signal after recognizing a connection to the USB host. When disconnection of the USB host is recognized, manipulate the DPRPU and DCFM bits as follows: (1) Clear the DPRPU bit to 0. (2) Wait a minimum of 1 μs. (3) Set the DCFM bit to 1. (4) Wait a minimum of 200 ns. (5) Clear the DCFM bit to 0. This module controls the terminal resistor for the D+ and D- signals during high-speed operation and the output resistor for the signals during full-speed operation. This module automatically switches the resistor after connection with the host controller or peripheral device by means of reset handshake, suspended state and resume detection. When the function controller function is selected and the DPRPU bit in SYSCFG is cleared to 0 during communication with the host controller, the pull-up resistor (or the terminal resistor) of the USB data line is disabled, making it possible to notify the USB host of the device disconnection. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1639 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module This LSI USB connector ZPU DP D+ ZDRU ZPD DM D- ZDRU ZPD Legend ZDRU : Output impedance ZPD : Pull-down resistor ZPU : Pull-up resistor Figure 29.1 UBS Connector Connection Page 1640 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 29 USB 2.0 Host/Function Module Register Access Wait Control There is a restriction on the cycle time for accessing the registers of this module except for SYSSTS as given below. Wait-related restriction: The cycle time for successive accesses to the USB 2.0 host/function module must be a duration of at least four USB clock (48 MHz) cycles (83.33 ns). To fulfill the above restriction, a register access wait control is necessary using the BWAIT[3:0] bits in BUSWAIT. The initial value is the maximum value (access cycles = 17 clock cycles). The optimum value should be found and set. Setting example 1: When successively accessing the registers of this module Peripheral clock 1 frequency: 66.67 MHz Calculation: (2 cycles (access cycles for the registers of this module) + 1 cycle (interval between successive accesses) + BWAIT)  1/66.67 MHz  83.33 ns BWAIT = 3 Setting example 2: When sending data from the on-chip high-speed RAM to the FIFO port register through DMA transfer Peripheral clock 1 frequency: 66.67 MHz Calculation: (2 cycles (access cycles for the registers of this module) + 2 cycles (access cycles for the on-chip high-speed RAM) + BWAIT)  1/66.67 MHz  83.33 ns BWAIT = 2 (6) Input Clock Selection The UCKPSEL and UCKFSEL bits in SYSCFG can be used to select the input pin from USB_X1 or EXTAL and the input clock frequency from 48 MHz or 12 MHz for this module. Stop supply of the clock signal to the USB module (SCKE = 0) when the UCKPSEL and UCKFSEL bits are to be modified. (7) Settings for Clock Supply to the USB Module The method of setting to select the clock signal for supply to the USB module depends on the input clock frequency. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1641 of 3092 Section 29 USB 2.0 Host/Function Module (a) SH7268 Group, SH7269 Group Selecting the 48-MHz Clock Input Select the 48-MHz and USB_X1 input by setting the UCKFSEL and UCKPSEL bits in SYSCFG to 0, then set the SCKE bit to enable supply of the clock signal. The 48-MHz input can only be selected when the clock input pin USB_X1 has been set. (b) Selecting the 12-MHz Clock Input Set the UCKFSEL bit in SYSCFG to 1 and select the clock input pin by the UCKPSEL bit, then make settings for supply of the clock signal according to the following procedure. Setting example 1: When supply of the clock signal is enabled in the initial settings immediately after a power-on reset. l. Set the UPLLE bit to 1. 2. Wait for 1 ms. 3. Set the SCKE bit to 1. Setting example 2: When supply of the clock signal is stopped in the suspended state. 1. Set the SCKE bit to 0. 2. Set the UPLLE bit to 0. Setting example 3: When supplying the clock signal is enabled through recovery from the suspended state 1. Set the UPLLE bit to 1. 2. Wait for 1 ms. 3. Set the SCKE bit to 1. Note: If a USB reset is used for recovery from the suspended state when operation as a function controller and high-speed transfer is selected, set the SCKE bit to 1 in no more than 2.5 ms. Page 1642 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.4.2 Section 29 USB 2.0 Host/Function Module Interrupt Functions Table 29.16 lists the interrupt generation conditions for this module. When an interrupt generation condition is satisfied and the interrupt output is enabled using the corresponding interrupt enable register, this module issues a USB interrupt request to the interrupt controller. Table 29.16 Interrupt Generation Conditions Bit Interrupt Name Cause of Interrupt Function That Generates the Related Interrupt Status VBINT VBUS interrupt Host, RESM Resume interrupt When a change in the state of the VBUS input pin has been detected (low to high or high to low) VBSTS function When a change in the state of the USB Function bus has been detected in the suspended state  (J-state to K-state or J-state to SE0) SOFR Frame number When the host controller function is update interrupt selected: Host,  function  When an SOF packet with a different frame number has been transmitted When the function controller function is selected:  DVST Device state transition interrupt R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When an SOF packet with a different frame number is received When a device state transition is detected  A USB bus reset detected  The suspend state detected  SET_ADDRESS request received  SET_CONFIGURATION request received Function DVSQ Page 1643 of 3092 Section 29 USB 2.0 Host/Function Module Bit Interrupt Name Cause of Interrupt CTRT Control transfer When a stage transition is detected in stage transition control transfer interrupt  Setup stage completed BEMP Buffer empty interrupt  Control write transfer status stage transition  Control read transfer status stage transition  Control transfer completed  A control transfer sequence error occurred  When transmission of all of the data in the buffer memory has been completed  Page 1644 of 3092 SH7268 Group, SH7269 Group Function That Generates the Related Interrupt Status Function CTSQ Host, BEMPSTS. PIPEBEMP Function When an excessive maximum packet size error has been detected R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Bit Interrupt Name Cause of Interrupt NRDY Buffer not ready When the host controller function is interrupt selected:  When STALL is received from the peripheral side for the issued token  When a response cannot be received correctly from the peripheral side for the issued token (No response is returned three consecutive times or a packet reception error occurred three consecutive times.) Function That Generates the Related Interrupt Status Host, function NRDYSTS. PIPENRDY  When an overrun/underrun occurred during isochronous transfer When the function controller function is selected:  When a token is received while the PID bits are set to BUF and transmission is not enabled for the buffer memory  When a CRC error or a bit stuffing error occurred during data reception in isochronous transfer  When an interval error occurred during data reception in isochronous transfer BRDY Buffer ready interrupt When the buffer is ready (reading or writing is enabled) Host, function BRDYSYS PIPEBRDY BCHG Bus change interrupt When a change of USB bus state is detected Host  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1645 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Function That Generates the Interrupt Related Status Bit Interrupt Name Cause of Interrupt DTCH Device disconnection When disconnection of a peripheral device is detected Host  ATTCH Device connection detection When J-state or K-state is detected on Host the USB port for 2.5 s.  Used for checking whether a peripheral device is connected. EOFERR EOF error detection When EOF error of a peripheral device Host is detected  SACK Normal setup operation When the normal response (ACK) for the setup transaction is received Host  SIGN Setup error When a setup transaction error (no Host response or ACK packet corruption) is detected three consecutive times.  Page 1646 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Figure 29.2 shows a diagram relating to interrupts of this module. USB bus reset detected INTENB0 INTSTS0 VBSE Set_Address detected VBINT Interrupt request RSME Set_Configuration detected RESM SOFE Suspended state detected SOFR Control write data stage DVSE DVST Control read data stage CTRE CTRT BEMPE Completion of control transfer BEMP Generation circuit Control transfer error NRDYE NRDY BRDYE Control transfer setup reception BRDY BEMP interrupt enable register BCHGE b9 BCHG ... b1 b0 DTCHE ATTCH : : . . . EOFERRE b1 EOFERR SIGNE BEMP interrupt status register b9 DTCH ATTCHE b0 SIGN NRDY interrupt enable register SACKE b9 SACK INTENB1 ... b1 b0 INTSTS1 . . . b1 NRDY interrupt status register b9 : : b0 BRDY interrupt enable register b9 ... b1 b0 . . . b1 BRDY interrupt status register b9 : : b0 Figure 29.2 Items Relating to Interrupts R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1647 of 3092 Section 29 USB 2.0 Host/Function Module (1) SH7268 Group, SH7269 Group BRDY Interrupt The BRDY interrupt is generated when either of the host controller function or function controller function is selected. The following shows the conditions under which this module sets 1 to a corresponding bit in BRDYSTS. Under this condition, this module generates BRDY interrupt, if the PIPEBRDYE bit in BRDYENB that corresponds to the pipe to 1 and the BRDYE bit in INTENB0 have been set to 1. The conditions for generating and clearing the BRDY interrupt depend on the settings of the BRDYM bit and BFRE bit for the pertinent pipe as described below. (a) When the BRDYM bit is 0 and BFRE bit is 0 With these settings, the BRDY interrupt indicates that the FIFO port is accessible. On any of the following conditions, this module generates the internal BRDY interrupt request trigger and sets 1 to the PIPEBRDY bit corresponding to the pertinent pipe. (i) For the pipe in the transmitting direction:  When the DIR bit is changed from 0 to 1.  When packet transmission is completed using the pertinent pipe when write-access from the CPU to the FIFO buffer for the pertinent pipe is disabled (when the BSTS bit is read as 0). In continuous transmission/reception mode, the request trigger is generated on completion of transmitting data of one plane of the FIFO buffer.  When one FIFO buffer is empty on completion of writing data to the other FIFO buffer in double buffer mode. The request trigger is not generated until completion of writing data to the currently-written FIFO buffer plane even if transmission to the other FIFO buffer is completed.  When the hardware flushes the buffer of the pipe for isochronous transfers.  When 1 is written to the ACLRM bit, which causes the FIFO buffer to make transition from the write-disabled to write-enabled state. The request trigger is not generated for the DCP (that is, during data transmission for control transfers). Page 1648 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (ii) Section 29 USB 2.0 Host/Function Module For the pipe in the receiving direction:  When packet reception is completed successfully thus enabling the FIFO buffer to be read when read-access from the CPU to the FIFO buffer for the pertinent pipe is disabled (when the BSTS bit is read as 0). The request trigger is not generated for the transaction in which DATA-PID disagreement occurs. In continuous transmission/reception mode, the request trigger is not generated when the data is of the specified maximum packet size and the buffer has available space. When a short packet is received, the request trigger is generated even if the FIFO buffer has available space. When the transaction counter is used, the request trigger is generated on receiving the specified number of packets. In this case, the request trigger is generated even if the FIFO buffer has available space.  When one FIFO buffer is read-enabled on completion of reading data from the other FIFO buffer in double buffer mode. The request trigger is not generated until completion of reading data from the currentlyread FIFO buffer plane even if reception by the other FIFO buffer is completed. When the function controller function is selected, the BRDY interrupt is not generated in the status stage of control transfers. The PIPEBRDY interrupt status of the pertinent pipe can be cleared to 0 by writing 0 to the corresponding PIPEBRDY interrupt status bit in the BRDYSTS register. In this case, 1s should be written to the PIPEBRDY interrupt status bits for the other pipes. Be sure to clear the BRDY status before accessing the FIFO buffer. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1649 of 3092 Section 29 USB 2.0 Host/Function Module (b) SH7268 Group, SH7269 Group When the BRDYM bit is 0 and the BFRE bit is 1 With these settings, this module generates the BRDY interrupt on completion of reading all the data for a single transfer using the pipe in the receiving direction, and sets 1 to the PIPEBRDY bit corresponding to the pertinent pipe. On any of the following conditions, this module determines that the last data for a single transfer has been received.  When a short packet including a zero-length packet is received.  When the transaction counter register (TRNCNT bits) is used and the number of packets specified by the TRNCNT bits are completely received. When the pertinent data is completely read out after any of the above determination conditions has been satisfied, this module determines that all the data for a single transfer has been completely read out. When a zero-length packet is received while the FIFO buffer is empty, the USB 2.0 host/function module determines that all the data for a single transfer has been read at the point at which the FRDY bit is set to 1 and the DTLN bit cleared to 0 in the FIFO port control register. In this case, to start the next transfer, write 1 to the BCLR bit in the corresponding FIFOCTR register. With these settings, this module does not detect the BRDY interrupt for the pipe in the transmitting direction. The PIPEBRDY interrupt status of the pertinent pipe can be cleared to 0 by writing 0 to the corresponding PIPEBRDY interrupt status bit. In this case, 1s should be written to the PIPEBRDY interrupt status bits for the other pipes. In this mode, the BFRE bit setting should not be modified until all the data for a single transfer has been processed. When it is necessary to modify the BFRE bit before completion of processing, all the FIFO buffers for the pertinent pipe should be cleared using the ACLRM bit. Page 1650 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (c) Section 29 USB 2.0 Host/Function Module When the BRDYM bit is 1 and the BFRE bit is 0 With these settings, the PIPEBRDY values are linked to the BSTS bit settings for each pipe. In other words, the BRDY interrupt status bits (PIPEBRDY) are set to 1 or 0 by this module depending on the FIFO buffer status. (i) For the pipe in the transmitting direction: The BRDY interrupt status bits are set to 1 when the FIFO buffer is write-enabled and are set to 0 when write-disabled. However, the BRDY interrupt is not generated if the DCP in the transmitting direction is writeenabled. (ii) For the pipe in the receiving direction: The BRDY interrupt status bits are set to 1 when the FIFO buffer is read-enabled and are set to 0 when all the data have been read (read-disabled). When a zero-length packet is received when the FIFO buffer is empty, the pertinent bit is set to 1 and the BRDY interrupt is continuously generated until BCLR = 1 is written. With this setting, the PIPEBRDY bit cannot be cleared to 0. When BRDYM is set to 1, all of the BFRE bits (for all pipes) should be cleared to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1651 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Figure 29.3 shows the timing at which the BRDY interrupt is generated. (1) Zero-length packet reception or data packet reception when BFRE = 0 (in single buffer mode) USB bus Token Packet Data Packet ACK Handshake *1 FIFO buffer status BRDY interrupt (corresponding PIPEBRDY bit is changed) Reception enabled state Reading enabled state A BRDY interrupt is generated because reading from the buffer is enabled*2. (2) Data packet reception when BFRE = 1 (in single buffer mode) USB bus FIFO buffer status Token Packet Data Packet ACK Handshake *1 Reception enabled state BRDY interrupt (corresponding PIPEBRDY bit is changed) Reading enabled state Reading from the buffer A BRDY interrupt is generated is enabled*2. because the transfer has ended*3. (3) Packet transmission (in single buffer mode) USB bus FIFO buffer status Token Packet Data Packet ACK Handshake *1 Transmission enabled state BRDY interrupt (corresponding PIPEBRDY bit is changed) Writing enabled state A BRDY interrupt is generated because writing to the buffer is enabled. Packet transmitted by the host Packet transmitted by the peripheral module *1 In isochronous transfer, ACK Handshake is not transmitted. *2 Reading the FIFO buffer is enabled when one packet is received while there is no data to be read in the buffer memory of the CPU. *3 On any of the following conditions, this module determines that transfer has ended. (1) A short packet including zero-length packet is received (2) The number of packets equal to the value set with the transaction counter are received. Figure 29.3 Timing at which a BRDY Interrupt is Generated Page 1652 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 29 USB 2.0 Host/Function Module NRDY Interrupt On generating the internal NRDY interrupt request for the pipe whose PID bits are set to BUF, this module sets the corresponding PIPENRDY bit in NRDYSTS to 1. If the corresponding bit in NRDYENB is set to 1, this module sets the NRDY bit in INTSTS0 to 1, allowing the USB interrupt to be generated. The following describes the conditions on which this module generates the internal NRDY interrupt request for a given pipe. However, the internal NRDY interrupt request is not generated during setup transaction execution when the host controller function is selected. During setup transactions when the host controller function is selected, the SACK or SIGN interrupt is detected. The internal NRDY interrupt request is not generated during status stage execution of the control transfer when the function controller function is selected. (a) (i) When the host controller function is selected and when the connection is used in which no split transactions occur For the pipe in the transmitting direction: On any of the following conditions, this module detects the NRDY interrupt.  For the pipe for isochronous transfers, when the time to issue an OUT token comes in a state in which there is no data to be transmitted in the FIFO buffer. In this case, this module transmits a zero-length packet following the OUT token, setting the corresponding PIPENRDY bit and the OVRN bit to 1.  During communications other than setup transactions using the pipe for the transfers other than isochronous transfers, when any combination of the following two cases occur three consecutive times: 1) no response is returned from the peripheral device (when timeout is detected before detection of the handshake packet from the peripheral device) and 2) an error is detected in the packet from the peripheral device. In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the setting of the PID bits of the corresponding pipe to NAK.  During communications other than setup transactions, when the STALL handshake is received from the peripheral device (including the STALL handshake in response to PING in addition to the STALL handshake in response to OUT). In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the setting of the PID bits of the corresponding pipe to STALL (11). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1653 of 3092 Section 29 USB 2.0 Host/Function Module (ii) SH7268 Group, SH7269 Group For the pipe in the receiving direction  For the pipe for isochronous transfers, when the time to issue an IN token comes in a state     in which there is no space available in the FIFO buffer. In this case, this module discards the received data for the IN token, setting the PIPENRDY bit of the corresponding pipe and the OVRN bit to 1. When a packet error is detected in the received data for the IN token, this module also sets the CRCE bit to 1. For the pipe for the transfers other than isochronous transfers, when any combination of the following two cases occur three consecutive times: 1) no response is returned from the peripheral device for the IN token issued by this module (when timeout is detected before detection of the DATA packet from the peripheral device) and 2) an error is detected in the packet from the peripheral device. In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the setting of the PID bits of the corresponding pipe to NAK. For the pipe for isochronous transfers, when no response is returned from the peripheral device for the IN token (when timeout is detected before detection of the DATA packet from the peripheral device) or an error is detected in the packet from the peripheral device. In this case, this module sets the corresponding PIPENRDY bit to 1. (The setting of the PID bits of the corresponding pipe to NAK is not modified.) For the pipe for isochronous transfers, when a CRC error or a bit stuffing error is detected in the received data packet. In this case, this module sets the corresponding PIPENRDY bit and CRCE bit to 1. When the STALL handshake is received. In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the setting of the PID bits of the corresponding pipe to STALL. Page 1654 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) (i) Section 29 USB 2.0 Host/Function Module When the host controller function is selected and when the connection is used in which split transactions occur For the pipe in the transmitting direction:  For the pipe for isochronous transfers, when the time to issue an OUT token comes in a state in which there is no data to be transmitted in the FIFO buffer. In this case, this module transmits a zero-length packet following the OUT token, setting the corresponding PIPENRDY bit and the OVRN bit to 1 at the issuance of the start-split transaction (S-SPLIT).  For the pipe for the transfers other than isochronous transfers, when any combination of the following two cases occur three consecutive times: 1) no response is returned from the HUB for the S-SPLIT or complete-split transaction (C-SPLIT) (when timeout is detected before detection of the handshake packet from the HUB) and 2) an error is detected in the packet from the HUB. In this case, this module sets the PIPENRDY bit of the corresponding pipe to 1 and modifies the setting of the PID bits of the corresponding pipe to NAK. If the NRDY interrupt is detected when the C-SPLIT is issued, this module clears the CSSTS bit to 0.  When the STALL handshake is received in response to the C-SPLIT. In this case, this module sets the corresponding PIPENRDY bit to 1, modifies the setting of the PID bits of the corresponding pipe to STALL (11) and clears the CSSTS bit to 0. This interrupt is not detected for SETUP transactions.  When the NYET is received in response to the C-SPLIT and the microframe number = 4. In this case, this module sets the corresponding PIPENRDY bit to 1 and clears the CSSTS bit to 0 (does not modify the setting of the PID bits). (ii) For the pipe in the receiving direction:  For the pipe for isochronous transfers, when the time to issue an IN token comes in a state in which there is no space available in the FIFO buffer. In this case, this module discards the received data for the IN token, setting the corresponding PIPENRDY bit and the OVRN bit to 1 at the issuance of the S-SPLIT.  During bulk-pipe transfers or the transfers other than SETUP transactions with the DCP, when any combination of the following two cases occur three consecutive times: 1) no response is returned from the HUB for the IN token issued by this module at the issuance of S-SPLIT or C-SPLIT (when timeout is detected before detection of the DATA packet from the HUB) and 2) an error is detected in the packet from the HUB. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1655 of 3092 Section 29 USB 2.0 Host/Function Module SH7268 Group, SH7269 Group In this case, this module sets the corresponding PIPENRDY bit to 1 and modifies the setting of the PID bits of the corresponding pipe to NAK. When the condition is generated during the C-SPLIT transaction, this module clears the CSSTS bit to 0.  During the C-SPLIT transaction for the pipe for isochronous transfers or interrupt transfers, when any combination of the following two cases occur three consecutive times: 1) no response is returned from the HUB for the IN token issued by this module (when timeout is detected before detection of the DATA packet from the HUB) and 2) an error is detected in the packet from the HUB. On generating this condition for the pipe for interrupt transfers, this module sets the corresponding PIPENRDY bit to 1, modifies the setting of the PID bits of the corresponding pipe to NAK and clears the CSSTS bit to 0. On generating this condition for the pipe for isochronous transfers, this module sets the corresponding PIPENRDY bit to 1 and CRCE bit to 1, and clears the CSSTS bit to 0 (does not modify the setting of the PID bits).  During the C-SPLIT transaction, when the STALL handshake is received for the pipe for the transfers other than isochronous transfers. In this case, this module sets the corresponding PIPENRDY bit to 1, modifies the setting of the PID bits of the corresponding pipe to STALL (11) and clears the CSSTS bit to 0.  During the C-SPLIT transaction, when the NYET handshake is received for the pipe for the isochronous transfers or interrupt transfers and the microframe number = 4. In this case, this module sets the corresponding PIPENRDY bit to 1 and CRCE bit to 1, and clears the CSSTS bit to 0 (does not modify the setting of the PID bits). (c) (i) When the function controller function is selected For the pipe in the transmitting direction:  On receiving an IN token when there is no data to be transmitted in the FIFO buffer. In this case, this module generates a NRDY interrupt request at the reception of the IN token, setting the PIPENRDY bit to 1. For the pipe for the isochronous transfers in which an interrupt is generated, this module transmits a zero-length packet, setting the OVRN bit to 1. Page 1656 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (ii) Section 29 USB 2.0 Host/Function Module For the pipe in the receiving direction:  On receiving an OUT token when there is no space available in the FIFO buffer. For the pipe for the isochronous transfers in which an interrupt is generated, this module generates a NRDY interrupt request, setting the PIPENRDY bit to 1 and OVRN bit to 1. For the pipe for the transfers other than isochronous transfers in which an interrupt is generated, this module generates a NRDY interrupt request when a NAK handshake is transferred after the data following the OUT token was received, setting the PIPENRDY bit to 1. However, during re-transmission (due to DATA-PID disagreement), the NRDY interrupt request is not generated. In addition, if an error occurs in the DATA packet, the NRDY interrupt request is not generated.  On receiving a PING token when there is no space available in the FIFO buffer. In this case, this module generates a NRDY interrupt request at the reception of the PING token, setting the PIPENRDY bit to 1.  For the pipe for isochronous transfers, when a token is not received normally within an interval frame. In this case, this module generates a NRDY interrupt request, setting the PIPENRDY bit to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1657 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Figure 29.4 shows the timing at which an NRDY interrupt is generated when the function controller function is selected. (1) Data transmission (in single buffer mode) USB bus IN Token Packet *1 NAK Handshake Buffer memory status Writing enabled state (there is no data to be transmitted) NRDY interrupt (corresponding PIPENRDY bit is changed)*2 (2) Data reception: OUT token reception (in single buffer mode) USB bus OUT Token Packet Data Packet NAK Handshake *1 Buffer memory status NRDY interrupt (corresponding PIPENRDY bit is changed)*2 Reading enabled state (there is no reception enabled area) (CRC bit, etc.)*3 (3) Data reception: PING token reception (in single buffer mode) PING Packet USB bus NAK Handshake Buffer memory status Reading enabled state (there is no reception enabled area) NRDY interrupt (corresponding PIPENRDY bit is changed)*2 Packet transmitted by the host Packet transmitted by the peripheral module *1 In isochronous transfer, Handshake is not transmitted. *2 The PIPENRDY bit is changed to 1 only when the PID bit for the pertinent pipe is to 1. *3 The CRC and OVRN bits are changed only when the transfer type for the pertinent pipe is isochronous transfer. Figure 29.4 Timing at which NRDY Interrupt is Generated when Function Controller Function is Selected Page 1658 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 29 USB 2.0 Host/Function Module BEMP Interrupt On generating the BEMP interrupt for the pipe whose PID bits are set to BUF, this module sets the corresponding PIPEBEMP bit in BEMPSTS to 1. If the corresponding bit in BEMPENB is set to 1, this module sets the BEMP bit in INTSTS0 to 1, allowing the USB interrupt to be generated. The following describes the conditions on which this module generates the internal BEMP interrupt request. (a) For the pipe in the transmitting direction, when the FIFO buffer of the corresponding pipe is empty on completion of transmission (including zero-length packet transmission). In single buffer mode, the internal BEMP interrupt request is generated simultaneously with the BRDY interrupt for the pipe other than DCP. However, the internal BEMP interrupt request is not generated on any of the following conditions.  When writing data to the FIFO buffer of the CPU has already been started on completion of transmitting data of one plane in double buffer mode.  When the buffer is cleared (emptied) by setting the ACLRM or BCLR bit to 1.  When IN transfer (zero-length packet transmission) is performed during the control transfer status stage in function controller mode. (b) For the pipe in the receiving direction: When the successfully-received data packet size exceeds the specified maximum packet size. In this case, this module generates the BEMP interrupt request, setting the corresponding PIPEBEMP bit to 1, and discards the received data and modifies the setting of the PID bits of the corresponding pipe to STALL (11). Here, this module returns no response when used as the host controller, and returns STALL response when used as the function controller. However, the internal BEMP interrupt request is not generated on any of the following conditions.  When a CRC error or bit stuffing error is detected in the received data.  When a setup transaction is being performed. Writing 0 to the PIPEBEMP bit clears the status; writing 1 to the PIPEBEMP bit has no effect. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1659 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Figure 29.5 shows the timing at which a BEMP interrupt is generated when the function controller function has been selected. (1) Data transmission USB bus Buffer memory status IN Token Packet Data Packet ACK Handshake Transmission enabled state *1 Writing enabled state (there is no data to be transmitted) BRDY interrupt (corresponding PIPEBEMP bit is changed) (2) Data reception USB bus OUT Token Packet Data Packet (Maximum packet size over) STALL Handshake (*1 BRDY interrupt (corresponding PIPEBEMP bit is changed) Packet transmitted by the host Packet transmitted by the peripheral module *1 In isochronous transfer, Handshake is not transmitted. Figure 29.5 Timing at which BEMP Interrupt is Generated when Function Controller Function is Selected (4) Device State Transition Interrupt Figure 29.6 shows a diagram of this module device state transitions. This module controls device states and generates device state transition interrupts. However, recovery from the suspended state (resume signal detection) is detected by means of the resume interrupt. The device state transition interrupts can be enabled or disabled individually using INTENB0. The device state that made a transition can be confirmed using the DVSQ bit in INTSTS0. To make a transition to the default state, the device state transition interrupt is generated after the reset handshake protocol has been completed. Device state can be controlled only when the function controller function is selected. Also, the device state transition interrupts can be generated only when the function controller function is selected. Page 1660 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Suspended state detection (DVST is set to 1.) Powered state (DVSQ = 100) Suspended state (DVSQ = 100) Resume (RESM is set to 1) USB bus reset detection (DVST is set to 1.) USB bus reset detection (DVST is set to 1.) Suspended state detection (DVST is set to 1.) Default state (DVSQ = 001) Suspended state (DVSQ = 101) Resume (RESM is set to 1) SetAddress execution (DVST is set to 1.) SetAddress execution (Address = 0) (DVST is set to 1.) Suspended state detection (DVST is set to 1.) Address state (DVSQ = 010) Suspended state (DVSQ = 110) Resume (RESM is set to 1) SetConfiguration execution (configuration value = 0) (DVST is set to 1.) SetConfiguration execution (configuration value =/ 0) (DVST is set to 1.) Suspended state detection (DVST is set to 1.) Configured state (DVSQ = 011) Suspended state (DVSQ = 111) Resume (RESM is set to 1) Note: Solid line: DVST is set to 1. Dotted line: RESM is set to 1. Figure 29.6 Device State Transitions R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1661 of 3092 Section 29 USB 2.0 Host/Function Module (5) SH7268 Group, SH7269 Group Control Transfer Stage Transition Interrupt (Function Controller Function) Figure 29.7 shows a diagram of how this module handles the control transfer stage transition. This module controls the control transfer sequence and generates control transfer stage transition interrupts. Control transfer stage transition interrupts can be enabled or disabled individually using INTENB0. The transfer stage that made a transition can be confirmed using the CTSQ bit in INTSTS0. The control transfer stage transition interrupts are generated only when the function controller function is selected. The control transfer sequence errors are described below. If an error occurs, the PID bit in DCPCTR is set to B'1x (STALL). (a) During control read transfers  At the IN token of the data stage, an OUT or PING token is received when there have been no data transfers at all.  An IN token is received at the status stage  A packet is received at the status stage for which the data packet is DATAPID = DATA0 (b) During control write transfers  At the OUT token of the data stage, an IN token is received when there have been no ACK response at all  A packet is received at the data stage for which the first data packet is DATAPID = DATA0  At the status stage, an OUT or PING token is received (c) During no-data control transfers  At the status stage, an OUT or PING token is received At the control write transfer stage, if the number of receive data exceeds the wLength value of the USB request, it cannot be recognized as a control transfer sequence error. At the control read transfer status stage, packets other than zero-length packets are received by an ACK response and the transfer ends normally. When a CTRT interrupt occurs in response to a sequence error, the CTSQ = 110 value is retained until CTRT = 0 is written from the system (the interrupt status is cleared). Therefore, while CTSQ = 110 is being held, the CTRT interrupt that ends the setup stage will not be generated even if a new USB request is received. (The USB 2.0 host/function module retains the setting of the CTSQ Page 1662 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module bits when the setup stage ends, and it generates a CTRT interrupt after the interrupt status is cleared.) Setup token reception Setup token reception Setup token reception CTSQ = 000 setup stage ACK transmission 1 CTSQ = 110 control transfer sequence error CTSQ = 001 control read data stage 5 Error detection OUT token 2 CTSQ = 010 control read status stage Error detection and IN token reception are valid at all stages in the box. ACK transmission 4 CTSQ = 000 idle stage 4 ACK transmission 1 ACK transmission CTSQ = 011 control write data stage IN token 3 CTSQ = 100 control write status stage 1 CTSQ = 101 control write no data status stage ACK reception ACK reception Note: CTRT interrupts (1) Setup stage completed (2) Control read transfer status stage transition (3) Control write transfer status stage transition (4) Control transfer completed (5) Control transfer sequence error Figure 29.7 Control Transfer Stage Transitions (6) Frame Update Interrupt Figure 29.8 shows an example of the SOFR interrupt output timing of this module. With the host controller function selected, an interrupt is generated at the timing at which the frame number is updated. With the function controller function selected, the SOFR interrupt is generated when the frame number is updated. When the function controller function is selected, this module updates the frame number and generates an SOFR interrupt if it detects a new SOF packet during full-speed operation. During high-speed operation, however, this module does not update the frame number, or generates no SOFR interrupt until the module enters the SOF locked state. Also, the SOF interpolation function is not activated. The SOF lock state is the state in which SOF packets with different frame numbers are received twice continuously without error occurrence. The conditions under which the SOF lock monitoring begins and stops are as follows. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1663 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module 1. Conditions under which SOF lock monitoring begins USBE = 1 2. Conditions under which SOF lock monitoring stops USBE = 0, a USB bus reset is received, or suspended state is detected. Peripheral Device SOF interpolation µSOF packet µSOF number 6 7 0 1 2 3 4 5 6 7 3 Frame number 0 1 2 3 4 5 6 7 0 4 SOFR interrupt 1 6 SOF interpolation function µSOF lock SOF interpolation SOF interpolation µSOF packet µSOF number 7 0 1 6 7 0 7 0 1 7 0 1 2 7 0 1 µSOF lock SOFR interrupt Not locked Not locked SOF interpolation, missing Figure 29.8 Example of SOFR Interrupt Output Timing (7) VBUS Interrupt If there has been a change in the VBUS pin, the VBUS interrupt is generated. The level of the VBUS pin can be checked with the VBSTS bit in INTSTS0. Whether the host controller is connected or disconnected can be confirmed using the VBUS interrupt. However, if the system is activated with the host controller connected, the first VBUS interrupt is not generated because there is no change in the VBUS pin. (8) Resume Interrupt With the function controller function selected, the resume interrupt is generated when the USB bus state changes (from J-state to K-state, or from J-state to SE0) while the device state is the suspended state.. Recovery from the suspended state is detected by means of the resume interrupt. With the host controller function selected, the resume interrupt is not generated; use the BCHG interrupt to detect the change of the USB bus state. Page 1664 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (9) Section 29 USB 2.0 Host/Function Module BCHG Interrupt The BCHG interrupt is generated when the USB bus state has changed. The BCHG interrupt can be used to detect whether or not the peripheral device is connected when the host controller function has been selected and can also be used to detect a remote wakeup. The BCHG interrupt is generated regardless of whether the host controller function or function controller function has been selected. (10) DTCH Interrupt The DTCH interrupt is generated if disconnection of the USB bus is detected when the host controller function has been selected. This module detects bus disconnection based on USB Specification 2.0. After detecting the DTCH interrupt, this module controls hardware as described below (irrespective of the set value of the corresponding interrupt enable bit). Terminate all the pipes in which communications are currently carried out for the USB port and make a transition to the wait state for bus connection to the USB port (wait state for ATTCH interrupt generation). (a) Modifies the UACT bit to 0. (b) Puts the port into the idle state. (11) SACK Interrupt The SACK interrupt is generated when an ACK response for the transmitted setup packet has been received from the peripheral device with the host controller function selected. The SACK interrupt can be used to confirm that the setup transaction has been completed successfully. (12) SIGN Interrupt The SIGN interrupt is generated when an ACK response for the transmitted setup packet has not been correctly received from the peripheral device three consecutive times with the host controller function selected. The SIGN interrupt can be used to detect no ACK response transmitted from the peripheral device or corruption of an ACK packet. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1665 of 3092 Section 29 USB 2.0 Host/Function Module SH7268 Group, SH7269 Group (13) ATTCH Interrupt The ATTCH interrupt is generated when J-state or K-state of the full-speed or low-speed level signal is detected on the USB port for 2.5 s in host controller mode. To be more specific, the ATTCH interrupt is detected on any of the following conditions. (a) When K-state, SE0, or SE1 changes to J-state, and J-state continues 2.5 s. (b) When J-state, SE0, or SE1 changes to K-state, and K-state continues 2.5 s. (14) EOFERR Interrupt The EOFERR interrupt is generated when it is detected that communication is not completed at the EOF2 timing prescribed by USB Specification 2.0. After detecting the EOFERR interrupt, this module controls hardware as described below (irrespective of the set value of the corresponding interrupt enable bit). Terminate all the pipes in which communications are currently carried out for the pertinent port and perform re-enumeration of the pertinent port. (a) Modifies the UACT bit for the port in which an EOFERR interrupt has been detected to 0. (b) Puts the port in which an EOFERR interrupt has been generated into the idle state. 29.4.3 Pipe Control Table 29.17 lists the pipe setting items of this module. With USB data transfer, data transmission has to be carried out using the logic pipe called the endpoint. This module has ten pipes that are used for data transfer. Settings should be entered for each of the pipes in conjunction with the specifications of the system. Page 1666 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.17 Pipe Setting Items Register Name Bit Name DCPCFG TYPE Specifies the transfer type PIPE1 to PIPE9: Can be set BFRE Selects the BRDY interrupt mode PIPE1 to PIPE5: Can be set DBLB Selects a double PIPE1 to PIPE5: Can be set buffer CNTMD Selects continuous transfer or noncontinuous transfer DCP: Can be set DIR Selects transfer direction IN or OUT can be set EPNUM Endpoint number PIPE1 to PIPE9: Can be set PIPECFG Setting Contents Remarks PIPE1 and PIPE2: Can be set (only when bulk transfer has been selected). PIPE3 to PIPE5: Can be set A value other than 0000 should be set when the pipe is used. PIPEBUF SHTNAK Selects disabled DCP: Can be set state for pipe PIPE1 and PIPE2: Can be set (only when bulk when transfer transfer has been selected) ends PIPE3 to PIPE5: Can be set BUFSIZE Buffer memory size DCP: Cannot be set (fixed at 256 bytes) PIPE1 to PIPE5: Can be set (a maximum of 2 Kbytes can be specified in 64-byte units) PIPE6 to PIPE9: Cannot be set (fixed at 64 bytes) BUFNMB Buffer memory number DCP: Cannot be set (areas fixed at H'0 to H'3) PIPE1 to PIPE5: Can be set (can be specified in areas H'8 to H'7F) PIPE6 to PIPE9: Cannot be set (areas fixed at H'4 to H'7) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1667 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Register Name Bit Name DCPMAXP DEVSEL PIPEMAXP PIPEPERI Setting Contents Remarks Selects a device Referenced only when the host controller function is selected. MXPS Maximum packet Compliant with the USB standard. size IFIS Buffer flush PIPE1 and PIPE2: Can be set (only when isochronous transfer has been selected) PIPE3 to PIPE9: Cannot be set IITV Interval counter PIPE1 and PIPE2: Can be set (only when isochronous transfer has been selected) PIPE3 to PIPE5: Cannot be set PIPE6 to PIPE9: Can be set (only when the host controller function has been selected) DCPCTR BSTS Buffer status INBUFM IN buffer monitor Mounted for PIPE3 to PIPE5. SUREQ SETUP request PIPEnCTR For the DCP, receive buffer status and transmit buffer status are switched with the ISEL bit. Can be set only for the DCP. Can be controlled only when the host controller function has been selected. SUREQCLR SUREQ clear Can be set only for the DCP. Can be controlled only when the host controller function has been selected. CSCLR CSSTS clear Can be controlled only when the host controller function has been selected. CSSTS SPLIT status indication Can be referenced only when the host controller function has been selected. ATREPM Auto response mode PIPE1 to PIPE5: Can be set Page 1668 of 3092 Can be controlled only when the function controller function has been selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Register Name Bit Name Setting Contents DCPCTR ACLRM Auto buffer clear PIPE1 to PIPE9: Can be set PIPEnCTR SQCLR Sequence clear Clears the data toggle bit SQSET Sequence set Sets the data toggle bit SQMON Sequence monitor Monitors the data toggle bit PBUSY Pipe busy status PID Response PID See section 29.4.3 (6), Response PID Transaction counter enable PIPE1 to PIPE5: Can be set Current transaction counter clear PIPE1 to PIPE5: Can be set Transaction counter PIPE1 to PIPE5: Can be set PIPEnTRE TRENB TRCLR PIPEnTRN TRNCNT (1) Remarks Pipe Control Register Switching Procedures The following bits in the pipe control registers can be modified only when USB communication is disabled (PID = NAK): Registers that Should Not be Set in the USB Communication Enabled (PID = BUF) State       Bits in DCPMAXP The SQCLR, SQSET, and PINGE bits in DCPCTR Bits in PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI The ATREPM, ACLRM, SQCLR and SQSET bits in PIPEnCTR Bits in PIPEnTRE and PIPEnTRN Bits in DEVADDn Note: In addition to the above, observe the setting procedures described in the register descriptions regarding the settings of the CSCLR bit and DEVADDn register. In order to modify the above bits from the USB communication enabled (PID = BUF) state, follow the procedure shown below: 1. Generate a bit modification request with the pipe control register. 2. Modify the PID corresponding to the pipe to NAK. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1669 of 3092 Section 29 USB 2.0 Host/Function Module SH7268 Group, SH7269 Group 3. Wait until the corresponding CSSTS bit is cleared to 0 (only when the host controller function has been selected). 4. Wait until the corresponding PBUSY bit is cleared to 0. Note: The PBUSY bit may remain set to 1 if the device is detached while USB transaction processing is in progress. 5. Modify the bits in the pipe control register. The following bits in the pipe control registers can be modified only when the pertinent information has not been set by the CURPIPE bits in CFIFOSEL, D0FIFOSEL and D1FIFOSEL. Registers that Should Not be Set When CURPIPE in FIFO-PORT is set.  Bits in DCPCFG and DCPMAXP  Bits in PIPECFG, PIPEBUF, PIPEMAXP and PIPEPERI  ACLRM bit in PIPEnCTR In order to modify pipe information, the CURPIPE bits should be set to the pipes other than the pipe to be modified. For the DCP, the buffer should be cleared using BCLR after the pipe information is modified. (2) Transfer Types The TYPE bit in PIPEPCFG is used to specify the transfer type for each pipe. The transfer types that can be set for the pipes are as follows. 1. 2. 3. 4. (3) DCP: No setting is necessary (fixed at control transfer). PIPE1 and PIPE2: These should be set to bulk transfer or isochronous transfer. PIPE3 to PIPE5: These should be set to bulk transfer. PIPE6 to PIPE9: These should be set to interrupt transfer. Endpoint Number The EPNUM bit in PIPEPCFG is used to set the endpoint number for each pipe. The DCP is fixed at endpoint 0. The other pipes can be set from endpoint 1 to endpoint 15. 1. DCP: No setting is necessary (fixed at end point 0). 2. PIPE1 to PIPE9: The endpoint numbers from 1 to 15 should be selected and set. These should be set so that the combination of the DIR bit and EPNUM bit is unique. Page 1670 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 29 USB 2.0 Host/Function Module Maximum Packet Size Setting The MXPS bit in DCPMAXP and PIPEMAXP is used to specify the maximum packet size for each pipe. DCP and PIPE1 to PIPE5 can be set to any of the maximum pipe sizes defined by the USB specification. For PIPE6 to PIPE9, 64 bytes are the upper limit of the maximum packet size. The maximum packet size should be set before beginning the transfer (PID = BUF). 1. 2. 3. 4. 5. DCP: 64 should be set when using high-speed operation. DCP: Select and set 8, 16, 32, or 64 when using full-speed operation. PIPE1 to PIPE5: 512 should be set when using high-speed bulk transfer. PIPE1 to PIPE5: Select and set 8, 16, 32, or 64 when using full-speed bulk transfer. PIPE1 and PIPE2: Set a value between 1 and 1024 when using high-speed isochronous transfer. 6. PIPE1 and PIPE2: Set a value between 1 and 1023 when using full-speed isochronous transfer. 7. PIPE6 to PIPE9: Set a value between 1 and 64. The high bandwidth transfers used with interrupt transfers and isochronous transfers are not supported. (5) Transaction Counter (For PIPE1 to PIPE5 in Reading Direction) When the specified number of transactions have been completed in the data packet receiving direction, this module recognizes that the transfer has ended. The transaction counter function is available when the pipes assigned to the D0FIFO/D1FIFO port have been set in the direction of reading data from the buffer memory. Two transaction counters are provided: one is the TRNCNT register that specifies the number of transactions to be executed and the other is the current counter that internally counts the number of executed transactions. When the current counter value matches the number of the transactions specified in TRNCNT, reading the buffer memory is enabled. The current counter of the transaction counter function is initialized by the TRCLR bit, so that the transactions can be counted again starting from the beginning. The information read from TRNCNT differs depending on the setting of the TRENB bit.  TRENB = 0: The specified transaction counter value can be read.  TRENB = 1: The current counter value indicating the internally counted number of executed transactions can be read. When operating the TRCLR bit, the following should be noted.  If the transactions are being counted and PID = BUF, the current counter cannot be cleared.  If there is any data left in the buffer, the current counter cannot be cleared. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1671 of 3092 Section 29 USB 2.0 Host/Function Module (6) SH7268 Group, SH7269 Group Response PID The PID bits in DCPCTR and PIPEnCTR are used to set the response PID for each pipe. The following shows this module operation with various response PID settings: (a) Response PID settings when the host controller function is selected The response PID is used to specify the execution of transactions.  NAK setting: Using pipes is disabled. No transaction is executed.  BUF setting: Transactions are executed based on the status of the buffer memory. For OUT direction: If there are transmit data in the buffer memory, an OUT token is issued. For IN direction: If there is an area to receive data in the buffer memory, an IN token is issued.  STALL setting: Using pipes is disabled. No transaction is executed. Setup transactions for the DCP are set with the SUREQ bit. (b) Response PID settings when the function controller function is selected The response PID is used to specify the response to transactions from the host.  NAK setting: The NAK response is always returned in response to the generated transaction.  BUF setting: Responses are made to transactions based on the status of the buffer memory.  STALL setting: The STALL response is always returned in response to the generated transaction. For setup transactions, an ACK response is always returned, regardless of the PID setting, and the USB request is stored in the register. This module may carry out writing to the PID bits, depending on the results of the transaction. (a) When the host controller function has been selected and the response PID is set by hardware  NAK setting: In the following cases, PID = NAK is set and issuing of tokens is automatically stopped:  When, during a transfer other than isochronous transfer, three receive errors such as no response, bit stuffing error, or CRC error are returned in succession after token transmission.  When, during isochronous transfer, three receive errors such bit stuffing error or CRC error are returned in succession after token transmission. Page 1672 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module  When a short packet is received in the data stage of control read transfer while the SHTNAK bit in the DCPCFG register is set to 1.  If a short packet is received when the SHTNAK bit in PIPECFG has been set to 1 for bulk transfer.  If the transaction counter ended when the SHTNAK bit has been set to 1 for bulk transfer.  BUF setting: There is no BUF writing by this module.  STALL setting: In the following cases, PID = STALL is set and issuing of tokens is automatically stopped:  When STALL is received in response to the transmitted token.  When the size of the receive data packet exceeds the maximum packet size. (b) When the function controller function has been selected and the response PID is set by hardware  NAK setting: In the following cases, PID = NAK is set and NAK is always returned in response to transactions:  When the SETUP token is received normally (DCP only).  If the transaction counter ended or a short packet is received when the SHTNAK bit in PIPECFG has been set to 1 for bulk transfer.  BUF setting: There is no BUF writing by this module.  STALL setting: In the following cases, PID = STALL is set and STALL is always returned in response to transactions:  When the size of the receive data packet exceeds the maximum packet size.  When a control transfer sequence error has been detected (DCP only). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1673 of 3092 Section 29 USB 2.0 Host/Function Module (7) SH7268 Group, SH7269 Group Data PID Sequence Bit This module automatically toggles the sequence bit in the data PID when data is transferred normally in the control transfer data stage, bulk transfer and interrupt transfer. The sequence bit of the data PID that was transmitted can be confirmed with the SQMON bit in DCPCTR and PIPEnCTR. When data is transmitted, the sequence bit switches at the timing at which the ACK handshake is received. When data is received, the sequence bit switches at the timing at which the ACK handshake is transmitted. The SQCLR bit in DCPCTR and the SQSET bit in PIPEnCTR can be used to change the data PID sequence bit. When the function controller function has been selected and control transfer is used, this module automatically sets the sequence bit when a stage transition is made. The bit is set to DATA1 when the setup stage ends. In the status stage, DATA1 is returned without referencing the sequence bit. Therefore, settings are not required. However, when the host controller function has been selected and control transfer is used, the sequence bit should be set at the stage transition. For the Clearfeature request transmission or reception, the data PID sequence bit should be set, regardless of whether the host controller function or function controller function is selected. With pipes for which isochronous transfer has been set, sequence bit operation cannot be carried out using the SQSET bit. (8) Response PID = NAK Function This module has a function that disables pipe operation (PID response = NAK) at the timing at which the final data packet of a transaction is received (this module automatically distinguishes this based on reception of a short packet or the transaction counter) by setting the SHTNAK bit in PIPECFG to 1. When a double buffer is being used for the buffer memory, using this function enables reception of data packets in transfer units. If pipe operation has disabled, the pipe has to be set to the enabled state again (PID response = BUF). This function can be used only when bulk transfers are used. Page 1674 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (9) Section 29 USB 2.0 Host/Function Module Auto Transfer MODE With the pipes for bulk transfer (PIPE1 to PIPE5), when the ATREPM bit in PIPEnCTR is set to 1, a transition is made to auto response mode. During an OUT transfer (DIR = 0), OUT-NAK mode is entered, and during an IN transfer (DIR = 1), null auto response mode is entered. (a) OUT-NAK Mode With the pipes for bulk OUT transfer, NAK is returned in response to an OUT or PING token and an NRDY interrupt is output when the ATREPM bit is set to 1. To make a transition from normal mode to OUT-NAK mode, OUT-NAK mode should be specified in the pipe operation disabled state (response PID = NAK) before enabling pipe operation (response PID = BUF). After pipe operation has been enabled, OUT-NAK mode becomes valid. However, if an OUT token is received immediately before pipe operation is disabled, the token data is normally received, and an ACK is retuned to the host. To make a transition from OUT-NAK mode to normal mode, OUT-NAK mode should be canceled in the pipe operation disabled state (response PID = NAK) before enabling pipe operation (response PID = BUF). In normal mode, reception of OUT data is enabled and an ACK is returned in response to a PING token if the buffer is ready to receive data. (b) Null Auto Response Mode With the pipes for bulk IN transfer, zero-length packets are continuously transmitted when the ATREPM bit is set to 1. To make a transition from normal mode to null auto response mode, null auto response mode should be set in the pipe operation disabled state (response PID = NAK) before enabling pipe operation (response PID = BUF). After pipe operation has been enabled, null auto response mode becomes valid. Before setting null auto response mode, INBUFM = 0 should be confirmed because the mode can be set only when the buffer is empty. If the INBUFM bit is 1, the buffer should be emptied with the ACLRM bit. While a transition to null auto response mode is being made, data should not be written from the FIFO port. To make a transition from null auto response mode to normal mode, pipe operation disabled state (response PID = NAK) should be retained for the period of zero-length packet transmission (fullspeed: 10 s, high-speed: 3 s) before canceling null auto response mode. In normal mode, data can be written from the FIFO port; therefore, packet transmission to the host is enabled by enabling pipe operation (response PID = BUF). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1675 of 3092 Section 29 USB 2.0 Host/Function Module 29.4.4 (1) SH7268 Group, SH7269 Group FIFO Buffer Memory FIFO Buffer Memory Allocation Figure 29.9 shows an example of a FIFO buffer memory map for this module. The FIFO buffer memory is an area shared by the CPU and this module. In the FIFO buffer memory status, there are times when the access right to the buffer memory is allocated to the user system (CPU side), and times when it is allocated to this module (SIE side). Independent buffer memory areas should be set for each pipe. Each memory area can be set using the first block number and the number of blocks (specified using the BUFNMB and BUFSIZE bits in PIPEBUF), where one block comprises 64 bytes. When continuous transfer mode has been selected using the CNTMD bit in PIPECFG, the BUFSIZE bits should be set so that the buffer memory size should be an integral multiple of the maximum packet size. When double buffer mode has been selected using the DBLB bit in PIPECFG, two planes of the memory area specified using the BUFSIZE bits in PIPEBUF can be assigned to a single pipe. Moreover, three FIFO ports are used for access to the buffer memory (reading and writing data). A pipe is assigned to the FIFO port by specifying the pipe number using the CURPIPE bit in C/DnFIFOSEL. The buffer statuses of the various pipes can be confirmed using the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. Also, the access right of the FIFO port can be confirmed using the FRDY bit in CFIFOCTR or DnFIFOCTR. Page 1676 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module FIFO Port Buffer Memory PIPEBUF registers CFIFO Port PIPE0 BUFNMB = 0, BUFSIZE = 3 PIPE6 BUFNMB = 4, BUFSIZE = 0 PIPE7 BUFNMB = 5, BUFSIZE = 0 PIPE5 BUFNMB = 6, BUFSIZE = 3 PIPE1 BUFNMB = 10, BUFSIZE = 7 PIPE2 BUFNMB = 18, BUFSIZE = 3 PIPE3 BUFNMB = 22, BUFSIZE = 7 PIPE4 BUFNMB = 28, BUFSIZE = 2 CURPIPE = 6 D0FIFO Port CURPIPE = 1 D1FIFO Port CURPIPE = 3 Notes: When pipe 8 and pipe 9 are not in use, BUFSIZE and such are not set. Figure 29.9 Example of a Buffer Memory Map (a) Buffer Status Tables 29.18 and 29.19 show the buffer status. The buffer memory status can be confirmed using the BSTS bit in DCPCTR and the INBUFM bit in PIPEnCTR. The access direction for the buffer memory can be specified using either the DIR bit in PIPECFG or the ISEL bit in CFIFOSEL (when DCP is selected). The INBUFM bit is valid for PIPE0 to PIPE5 in the sending direction. For an IN pipe uses double buffer, the BSTS bit can be used to monitor the buffer memory status of CPU side and the INBUFM bit to monitor the buffer memory status of SIE side. In the case like the BEMP interrupt may not shows the buffer empty status because the CPU (direct memory access controller) writes data slowly, the INBUFM bit can be used to confirm the end of sending. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1677 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.18 Buffer Status Indicated by the BSTS Bit ISEL or DIR BSTS 0 (receiving direction) 0 Buffer Memory State There is no received data, or data is being received. Reading from the FIFO port is inhibited. 0 (receiving direction) 1 There is received data, or a zero-length packet has been received. Reading from the FIFO port is allowed. However, because reading is not possible when a zerolength packet is received, the buffer must be cleared. 1 (transmitting direction) 0 1 (transmitting direction) 1 The transmission has not been finished. Writing to the FIFO port is inhibited. The transmission has been finished. CPU write is allowed. Table 29.19 Buffer Status Indicated by the INBUFM Bit IDIR INBUFM Buffer Memory State 0 (receiving direction) Invalid Invalid 1 (transmitting direction) 0 The transmission has been finished. 1 (transmitting direction) 1 Page 1678 of 3092 There is no waiting data to be transmitted. The FIFO port has written data to the buffer. There is data to be transmitted R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 29 USB 2.0 Host/Function Module FIFO Buffer Clearing Table 29.20 shows the clearing of the FIFO buffer memory by this module. The buffer memory can be cleared using the three bits indicated below. Table 29.20 List of Buffer Clearing Methods Bit Name Register BCLR DCLRM ACLRM CFIFOCTR DnFIFOSEL PIPEnCTR DnFIFOCTR Function Clears the buffer memory on the CPU side In this mode, after the data of the specified pipe has been read, the buffer memory is cleared automatically. This is the auto buffer clear mode, in which all of the received packets are discarded. Clearing method Cleared by writing 1 1: Mode valid 1: Mode valid 0: Mode invalid 0: Mode invalid (c) Buffer Areas Table 29.21 shows the FIFO buffer memory map of this controller. The buffer memory has special fixed areas to which pipes are assigned in advance, and user areas that can be set by the user. The buffer for the DCP is a special fixed area that is used both for control read transfers and control write transfers. The PIPE6 to PIPE9 area is assigned in advance, but the area for pipes that are not being used can be assigned to PIPE1 to PIPE5 as a user area. The settings should ensure that the various pipes do not overlap. Note that each area is twice as large as the setting value in the double buffer. Also, the buffer size should not be specified using a value that is less than the maximum packet size. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1679 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.21 Buffer Memory Map Buffer Memory Number Buffer Size Pipe Setting Note H'0 to H'3 256 bytes Fixed area only for the DCP Single buffer, continuous transfers enabled H'4 64 bytes Fixed area for PIPE6 Single buffer H'5 64 bytes Fixed area for PIPE7 Single buffer H'6 64 bytes Fixed area for PIPE8 Single buffer H'7 64 bytes Fixed area for PIPE9 Single buffer H'8 to H'7F Up to 7616 bytes PIPE1 to PIPE5 Double buffer can be set, continuous user area transfers enabled (d) Auto Buffer Clear Mode Function With this module, all of the received data packets are discarded if the ACLRM bit in PIPEnCTR is set to 1. If a normal data packet has been received, the ACK response is returned to the host controller. This function can be set only in the buffer memory reading direction. Also, if the ACLRM bit is set to 1 and then to 0, the buffer memory of the selected pipe can be cleared regardless of the access direction. (e) Buffer Memory Specifications (Single/Double Setting) Either a single or double buffer can be selected for PIPE1 to PIPE5, using the DBLB bit in PIPECFG. The double buffer is a function that assigns two memory areas specified with the BUFSIZE bit in PIPEBUF to the same pipe. Figure 29.10 shows an example of buffer memory settings for this module. Page 1680 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Buffer memory PIPEBUF registers 64 bytes BUFSIZE = 0, DBLB = 0 64 bytes 64 bytes BUFSIZE = 0, DBLB = 1 128 bytes BUFSIZE = 1, DBLB = 0 Figure 29.10 Example of Buffer Memory Settings (f) Buffer Memory Operation (Continuous Transfer Setting) Either the continuous transfer mode or the non-continuous transfer mode can be selected, using the CNTMD bit in DCPCFG and PIPECFG. This selection is valid for DCP and PIPE1 to PIPE5. The continuous transfer mode function is a function that sends and receives multiple transactions in succession. When the continuous transfer mode is set, data can be transferred without interrupts being issued to the CPU, up to the buffer sizes assigned for each of the pipes. In the continuous sending mode, the data being written is divided into packets of the maximum packet size and sent. If the data being sent is less than the buffer size (short packet, or the integer multiple of the maximum packet size is less than the buffer size), BVAL = 1 must be set after the data being sent has been written. In the continuous reception mode, interrupts are not issued during reception of packets up to the buffer size, until the transaction counter has ended, or a short packet is received. Table 29.22 describes the relationship between the transfer mode settings by CNTMD bit and the timings at which reading data or transmitting data from the FIFO buffer is enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1681 of 3092 Section 29 USB 2.0 Host/Function Module SH7268 Group, SH7269 Group Table 29.22 Relationship between Transfer Mode Settings by CNTMD Bit and Timings at which Reading Data or Transmitting Data from FIFO Buffer is Enabled Continuous or NonContinuous Transfer Mode Method of Determining if Reading or Transmitting Data is Enabled Non-continuous transfer In the receiving direction (DIR = 0), reading data from the FIFO buffer is enabled when: (CNTMD = 0)  This module receives one packet. In the transmitting direction (DIR = 1), transmitting data from the FIFO buffer is enabled when: Continuous transfer (CNTMD = 1) Page 1682 of 3092  Data of the maximum packet size is written to the FIFO buffer. or  Data of the short packet size (including 0-byte data) is written to the FIFO buffer and then writes 1 to BVAL. In the receiving direction (DIR = 0), reading data from the FIFO buffer is enabled when:  The number of the data bytes received in the FIFO buffer assigned to the selected pipe becomes the same as the number of assigned data bytes (DCP: fixed at 256 bytes, pipes 1 to 5 (BUFSIZE + 1)  64).  This module receives a short packet other than a zero-length packet.  This module receives a zero-length packet when data is already stored in the FIFO buffer assigned to the selected pipe. or  This module receives the number of packets equal to the transaction counter value specified for the selected pipe (PIPE1 to PIPE5 only). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Continuous or NonContinuous Transfer Mode Method of Determining if Reading or Transmitting Data is Enabled Continuous transfer In the transmitting direction (DIR = 1), transmitting data from the FIFO buffer is enabled when: (CNTMD = 1)  The number of the data bytes written to the FIFO buffer becomes the same as the number of data bytes in a single FIFO buffer plane assigned to the selected pipe. or  The number of data bytes less than the size of a single FIFO buffer plane (including 0-byte data) assigned to the selected pipe is written to the FIFO buffer and then 1 is written to BVAL. In a DMA transfer, the DMA transfer end sampling enable (TENDE) bit is set to 1, a number of data bytes less than the size of a single FIFO buffer plane assigned to the selected pipe (or 0 bytes) is written to the FIFO buffer and the DMA transfer end signal is received when the last byte is written (PIPE1 to PIPE5 only).  Figure 29.11 shows an example of buffer memory operation for this module. CNTMD = 0 When packet is received CNTMD = 1 When packet is received Max Packet Size Max Packet Size Unused area Interrupt issued Max Packet Size CNTMD = 0 When packet is sent CNTMD = 1 When packet is sent Max Packet Size Max Packet Size Unused area Transmission enabled Interrupt issued Max Packet Size Transmission enabled Figure 29.11 Example of Buffer Memory Operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1683 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module (2) FIFO Port Functions Table 29.23 shows the settings for the FIFO port functions of this module. In write access, writing data until the buffer is full (or the maximum packet size for non-continuous transfers) automatically enables sending of the data. To enable sending of data before the buffer is full (or before the maximum packet size for non-continuous transfers), the BVAL bit in C/DnFIFOCTR must be set to end the writing. Also, to send a zero-length packet, the BCLR bit in the same register must be used to clear the buffer and then the BVAL bit set in order to end the writing. In read access, reception of new packets is automatically enabled if all of the data has been read. Data cannot be read when a zero-length packet is being received (DTLN = 0), so the BCLR bit in the register must be used to release the buffer. The length of the data being received can be confirmed using the DTLN bit in C/DnFIFOCTR. Table 29.23 FIFO Port Function Settings Register Name Bit Name Function C/DnFIFOSEL RCNT Selects DTLN read mode REW Buffer memory rewind (re-read, rewrite) DCLRM Automatically clears data received for a specified pipe after the data has been read For DnFIFO only DREQE Enables DMA transfers For DnFIFO only MBW FIFO port access bit width BIGEND Selects FIFO port endian ISEL FIFO port access direction CURPIPE Selects the current pipe BVAL Ends writing to the buffer memory BCLR Clears the buffer memory on the CPU side DTLN Checks the length of received data C/DnFIFOCTR Page 1684 of 3092 Note For DCP only R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (a) Section 29 USB 2.0 Host/Function Module FIFO Port Selection Table 29.24 shows the pipes that can be selected with the various FIFO ports. The pipe to be accessed is selected using the CURPIPE bit in C/DnFIFOSEL. After the pipe is selected, whether the CURPIPE value for the pipe, which was written last, can be correctly read should be checked. (If the previous pipe number is read, it indicates that the pipe modification is being executed by this module.) Then, the FIFO port can be accessed after FRDY = 1 is checked . Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory access direction conforms to the DIR bit in PIPECFG. The ISEL bit determines this only for the DCP. Table 29.24 FIFO Port Access Categorized by Pipe Pipe Access Method Port that can be Used DCP CPU access CFIFO port register PIPE1 to PIPE9 (b) CPU access CFIFO port register DMA access D0FIFO/D1FIFO port register REW Bit It is possible to temporarily stop access to the pipe currently being accessed, access a different pipe, and then continue processing using the current pipe once again. The REW bit in C/DnFIFOSEL is used for this. If a pipe is selected when the REW bit is set to 1 and at the same time the CURPIPE bit in C/DnFIFOSEL is set, the pointer used for reading from and writing to the buffer memory is reset, and reading or writing can be carried out from the first byte. Also, if a pipe is selected with 0 set for the REW bit, data can be read and written in continuation of the previous selection, without the pointer used for reading from and writing to the buffer memory being reset. To access the FIFO port, FRDY = 1 must be ensured after selecting a pipe. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1685 of 3092 Section 29 USB 2.0 Host/Function Module (c) SH7268 Group, SH7269 Group Accessing FIFO Port for Odd Data For reading data from the FIFO port, when the number of data bits to be read is smaller than the access width specified by the MBW bits in the FIFO port select registers, read the data with the specified width and discard the unnecessary bits through software. For writing data to the FIFO port, when the number of data bits to be written is smaller than the access width specified by the MBW bits in the FIFO port select registers, access the registers as shown in the following examples. In the examples, the FIFO port access width is 32 bits (MBW = 10) and 24-bit data is written to the FIFO port. Page 1686 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Example 1 for writing odd data: Writing data with 16-bit width once and then with 8-bit width once Start [1] Set MBW to 01. [1] Set the FIFO port access width to 16 bits. [2] Write data to bits 31 to 16 when BIGEND = 1, and bits 15 to 0 when BIGEND = 0. [2] Write 16-bit data to the FIFO port register. [3] Set the FIFO port access width to 8 bits. [4] Write data to bits 31 to 24 when BIGEND = 1, and bits 7 to 0 when BIGEND = 0. [3] [4] Set MBW to 00. Write 8-bit data to the FIFO port register. Writing end Figure 29.12 Example 1 for Writing Odd Data to FIFO Port Example 1 for writing odd data 2: Writing data with 8-bit width three times Start Set MBW to 00. [1] [1] Set the FIFO port access width to 8 bits. [2] Write data to bits 31 to 24 when BIGEND = 1, and bits 7 to 0 when BIGEND = 0. [2] Write 8-bit data to the FIFO port register three times. Writing end Figure 29.13 Example 2 for Writing Odd Data to FIFO Port R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1687 of 3092 Section 29 USB 2.0 Host/Function Module (d) SH7268 Group, SH7269 Group Modifying MBW Bits when the Pipe is in the Receiving Direction When the specified pipe is in the receiving direction, modify the MBW bits in the FIFO port select registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL) simultaneously with the CURPIPE bits. When the DCP is currently set (CURPIPE = 000) in the CFIFO port select register, modify the MBW bits simultaneously with the CURPIPE bits or ISEL bit. To modify only the MBW bits for the currently set pipe, follow the procedure below. Once the buffer memory starts to be read out, however, do not modify the MBW bits until the entire data has been read out. When the selected CURPIPE is in the writing direction to buffer memory, the port access width can be changed simply by setting the MBW bits. Once the buffer memory starts to be written to, however, do not modify the port access width from 8 bits to 16 or 32 bits, or from16 bits to 32 bits. When CURPIPE setting is not DCP (000) for D0FIFO, D1FIFO, or CFIFO Start [1] Set CURPIPE to 00. Read CURPIPE to check that the read value agrees with the written value. [2] [1] Set CURPIPE to the value other than the current value. [2] Set MBW to any value and set CURPIPE to the value (pipe) that has been set before step [1]. Set MBW and CURPIPE simultaneously. Read CURPIPE to check that the read value agrees with the written value. MBW modification end Figure 29.14 MBW Modification Procedure Example when CURPIPE Setting is not DCP (000) for D0FIFO, D1FIFO, or CFIFO Page 1688 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module When CURPIPE setting is DCP (000) for CFIFO Start [1] Set ISEL to 1. Read ISEL to check that the read value agrees with the written value. [2] [1] Select the writing direction. [2] Set MBW to any value and set ISEL to select the reading direction. Set MBW and ISEL simultaneously. Read ISEL to check that the read value agrees with the written value. MBW modification end Figure 29.15 MBW Modification Procedure Example When CURPIPE Setting is DCP (000) (3) DMA Transfers (D0FIFO/D1FIFO Port) (a) Overview of DMA Transfers For pipes 1 to 9, the FIFO port can be accessed using the direct memory access controller. When accessing the buffer for the pipe targeted for DMA transfer is enabled, a DMA transfer request is issued. The unit of transfer to the FIFO port should be selected using the MBW bit in DnFIFOSEL and the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected pipe should not be changed during the DMA transfer. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1689 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module (b) Auto Recognition of DMA Transfer Completion With this module, it is possible to complete FIFO data writing through DMA transfer by controlling DMA transfer end signal input. The DMA transfer end signal is output from the direct memory access controller when the controller transfers data through DMA for the times specified by the DMA transfer count register (DMATCR) of the direct memory access controller. When a transfer end signal is sampled, the module enables buffer memory transmission (the same condition as when BVAL = 1). Whether to sample the DMA transfer end signal can be specified through the TENDE bit in DnFBCFG. Note that this function cannot be used when the DMA transfer size is set to 16 bytes. (c) DnFIFO Auto Clear Mode (D0FIFO/D1FIFO Port Reading Direction) If 1 is set for the DCLRM bit in DnFIFOSEL, the module automatically clears the buffer memory of the selected pipe when reading of the data from the buffer memory has been completed. Table 29.25 shows the packet reception and buffer memory clearing processing for each of the various settings. As shown, the buffer clear conditions depend on the value set to the BFRE bit. Using the DCLRM bit eliminates the need for the buffer to be cleared even if a situation occurs that necessitates clearing of the buffer. This makes it possible to carry out DMA transfers without involving software. This function can be set only in the buffer memory reading direction. Table 29.25 Packet Reception and Buffer Memory Clearing Processing Register Setting Buffer Status When Packet is Received DCLRM  0 DCLRM  1 BFRE = 0 BFRE = 1 BFRE = 0 BFRE = 1 Buffer full Doesn't need to be cleared Doesn't need to be cleared Doesn't need to be cleared Doesn't need to be cleared Zero-length packet reception Needs to be cleared Needs to be cleared Doesn't need to be cleared Doesn't need to be cleared Normal short packet reception Doesn't need to be cleared Needs to be cleared Doesn't need to be cleared Doesn't need to be cleared Transaction count ended Doesn't need to be cleared Needs to be cleared Doesn't need to be cleared Doesn't need to be cleared Page 1690 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 29.4.5 Section 29 USB 2.0 Host/Function Module Control Transfers (DCP) Data transfers of the data stage of control transfers are done using the default control pipe (DCP). The DCP buffer memory is a 256-byte single buffer, and is a fixed area that is shared for both control reading and control writing. The buffer memory can be accessed through the CFIFO port. (1) Control Transfers when the Host Controller Function is Selected (a) Setup Stage USQREQ, USBVAL, USBINDX, and USBLENG are the registers that are used to transmit a USB request for setup transactions. Writing setup packet data to the registers and writing 1 to the SUREQ bit in DCPCTR transmits the specified data for setup transactions. Upon completion of transactions, the SUREQ bit is cleared to 0. The above USB request registers should not be modified while SUREQ = 1. The device address for setup transactions is specified using the DEVSEL bits in DCPMAXP. When the data for setup transactions has been sent, a SIGN or SACK interrupt request is generated according to the response received from the peripheral device (SIGN1 or SACK bits in INTSTS1), by means of which the result of the setup transactions can be confirmed. A data packet of DATA0 (USB request) is transmitted as the data packet for the setup transactions regardless of the setting of the SQMON bit in DCPCTR. (b) Data Stage Data transfers are done using the DCP buffer memory. The access direction of the DCP buffer memory should be specified using the ISEL bit in CFIFOSEL. Also specify the transfer direction using the DIR bit in the DCPCFG register. For the first data packet of the data stage, the data PID must be transferred as DATA1. Transaction is done by setting the data PID = DATA1 and the PID bit = BUF using the SQSET bit in DCPCTR. Completion of data transfer is detected using the BRDY or BEMP interrupts. Setting continuous transfer mode allows data transfers over multiple packets. Note that when continuous transfer mode is set for the receiving direction, the BRDY interrupt is not generated until the buffer becomes full or a short packet is received (the integer multiple of the maximum packet size, and less than 256 bytes). For control write transfers, when the number of data bytes to be sent is the integer multiple of the maximum packet size, a zero-length packet must be controlled to be sent at the end. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1691 of 3092 Section 29 USB 2.0 Host/Function Module (c) SH7268 Group, SH7269 Group Status Stage Zero-length packet data transfers are done in the direction opposite to that in the data stage. As with the data stage, data transfers are done using the DCP buffer memory. Transactions are done in the same manner as the data stage. For the data packets of the status stage, the data PID must be transferred as DATA1. The data PID should be set to DATA1 using the SQSET bit in DCPCTR. For reception of a zero-length packet, the received data length must be confirmed using the DTLN bits in CFIFOCTR after the BRDY interrupt is generated, and the buffer memory must then be cleared using the BCLR bit. (2) Control Transfers when the Function Controller Function is Selected (a) Setup Stage This module always sends an ACK response in response to a setup packet that is normal with respect to this module. The operation of this module operates in the setup stage is noted below. (i) When a new USB request is received, this module sets the following registers:  Set the VALID bit in INTSTS0 to 1.  Set the PID bit in DCPCTR to NAK.  Set the CCPL bit in DCPCTR to 0. (ii) When a data packet is received right after the SETUP packet, the USB request parameters are stored in USBREQ, USBVAL, USBINDX, and USBLENG. Response processing with respect to the control transfer should always be carried out after first setting VALID = 0. In the VALID = 1 state, PID = BUF cannot be set, and the data stage cannot be terminated. Using the function of the VALID bit, this module is able to interrupt the processing of a request currently being processed if a new USB request is received during a control transfer, and can send a response in response to the newest request. Also, this module automatically judges the direction bit (bit 8 of the bmRequestType) and the request data length (wLength) of the USB request that was received, and then distinguishes between control read transfers, control write transfers, and no-data control transfers, and controls the stage transition. For a wrong sequence, the sequence error of the control transfer stage transition interrupt is generated, and the software is notified. For information on the stage control of this module, see figure 29.7. Page 1692 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 29 USB 2.0 Host/Function Module Data Stage Data transfers corresponding to USB requests that have been received should be done using the DCP. Before accessing the DCP buffer memory, the access direction should be specified using the ISEL bit in CFIFOSEL. A transaction is executed by setting the PID bits in the DCPCTR register to BUF. The BRDY interrupt or the BEMP interrupt can be used to detect the end of data transfer. Use the BRDY interrupt to detect the end of control write transfers and the BEMP interrupt to detect the end of control read transfers. If the data being transferred is larger than the size of the DCP buffer memory, the data transfer should be carried out using the BRDY interrupt for control write transfers and the BEMP interrupt for control read transfers. With control write transfers during high-speed operation, the NYET handshake response is carried out based on the state of the buffer memory. (c) Status Stage Control transfers are terminated by setting the CCPL bit to 1 with the PID bit in DCPCTR set to PID = BUF. After the above settings have been entered, this module automatically executes the status stage in accordance with the data transfer direction determined at the setup stage. The specific procedure is as follows. (i) For control read transfers: This module receives a zero-length packet from the USB host and sends an ACK response. (ii) For control write transfers and no-data control transfers: This module sends the zero-length packet from the USB host and receives an ACK response. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1693 of 3092 Section 29 USB 2.0 Host/Function Module (d) SH7268 Group, SH7269 Group Control Transfer Auto Response Function This module automatically responds to a normal SET_ADDRESS request. If any of the following errors occur in the SET_ADDRESS request, a response is necessary. (i) bmRequestType  H'00 (ii) wIndex  H'00 (ii) wLength  H'00 (iv) wValue  H'7F (v) DVSQ  011 (Configured) For all requests other than the SET_ADDRESS request, the corresponding response is required. 29.4.6 Bulk Transfers (PIPE1 to PIPE5) The buffer memory specifications for bulk transfers (single/double buffer setting, or continuous/non-continuous transfer mode setting) can be selected. The maximum size that can be set for the buffer memory is 2 Kbytes. The buffer memory state is controlled by this module, with a response sent automatically for a PING packet/NYET handshake. (1) PING Packet Control when the Host Controller Function is Selected This module automatically sends a PING packet in the OUT direction. On receiving an ACK handshake in the initial state in which PING packet sending mode is set, this module sends an OUT packet as noted below. The module returns to PING packet sending mode when a NAK or NYET is received during an OUT transaction. 1. Sets OUT data sending mode. 2. Sends a PING packet. 3. Receives an ACK handshake. 4. Sends an OUT data packet. 5. Receives an ACK handshake. (Repeats steps 4 and 5.) 6. Sends an OUT data packet. 7. Receives an NAK/NYET handshake. 8. Sends a PING packet. Page 1694 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module This module is returned to PING packet sending mode by a power-on reset, receiving a NYET/NAK handshake, clearing the sequence toggle bits (SQCLR), and setting the buffer clear bit (ACLRM) in PIPEnCTR. (2) NYET Handshake Control when the Function Controller Function is Selected Table 29.26 lists the responses to received tokens during bulk transmission and control transmission. The USB 2.0 host/function module returns a NYET when an OUT token is received while there is only one packet of empty space in the buffer memory, during both bulk transmission and control transmission. However, an ACK is returned instead of a NYET even under the above conditions when a short packet is received. Table 29.26 List of Responses to Received Tokens Value Set Buffer for PID Bit in Memory DCPCTR State NAK/STALL BUF Token Response Note  SETUP ACK   IN/OUT/ PING NAK/STALL   SETUP ACK  RCV-BRDY1 OUT/PING ACK If an OUT token is received, a data packet is received. RCV-BRDY2 OUT NYET Notifies whether a data packet can be received RCV-BRDY2 OUT (Short) ACK Notifies whether a data packet can be received RCV-BRDY2 PING ACK Notifies that a data packet can be received RCV-NRDY OUT/PING NAK Notifies that a data packet cannot be received TRN-BRDY IN DATA0/DATA1 A data packet is transmitted TRN-NRDY IN NAK R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Notifies that a data packet cannot be transmitted Page 1695 of 3092 Section 29 USB 2.0 Host/Function Module [Legend] RCV-BRDY1: RCV-BRDY2: RCV-NRDY: TRN-BRDY: TRN-NRDY: 29.4.7 SH7268 Group, SH7269 Group When an OUT/PING token is received, there is space in the buffer memory for two or more packets. When an OUT token is received, there is only enough space in the buffer memory for one packet. When a PING token is received, there is no space in the buffer memory. When an IN token is received, there is data to be sent in the buffer memory. When an IN token is received, there is no data to be sent in the buffer memory. Interrupt Transfers (PIPE6 to PIPE9) When the function controller function is selected, this module carries out interrupt transfers in accordance with the timing controlled by the host controller. For interrupt transfers, PING packets are ignored (no responses are sent), and the ACK, NAK, and STALL responses are carried out without an NYET handshake response being made. When the host controller function is selected, this module can set the timing of issuing a token using the interval timer. At this time, this module issues an OUT token even in the OUT direction, without issuing a PING token. This module does not support high bandwidth transfers of interrupt transfers. (1) Interval Counter during Interrupt Transfers when the Host Controller Function is Selected For interrupt transfers, intervals between transactions are set in the IITV bits in PIPEPERI. This controller issues an interrupt transfer token based on the specified intervals. (a) Counter Initialization This controller initializes the interval counter under the following conditions.  Power-on reset The IITV bits are initialized.  Buffer memory initialization using the ACLRM bit The IITV bits are not initialized but the count value is. Setting the ACLRM bit to 0 starts counting from the value set in the IITV bits. Note that the interval counter is not initialized in the following case. Page 1696 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module  USB bus reset, USB suspended The IITV bits are not initialized. Setting 1 to the UACT bit starts counting from the value before entering the USB bus reset state or USB suspended state. (b) Operation when Transmission/Reception is Impossible at Token Issuance Timing This module cannot issue tokens even at token issuance timing in the following cases. In such a case, this module attempts transactions at the subsequent interval.  When the PID is set to NAK or STALL.  When the buffer memory is full at the token sending timing in the receiving (IN) direction.  When there is no data to be sent in the buffer memory at the token sending timing in the sending (OUT) direction. 29.4.8 Isochronous Transfers (PIPE1 and PIPE2) This module has the following functions pertaining to isochronous transfers. 1. 2. 3. 4. Notification of isochronous transfer error information Interval counter (specified by the IITV bit) Isochronous IN transfer data setup control (IDLY function) Isochronous IN transfer buffer flush function (specified by the IFIS bit) This module does not support the High Bandwidth transfers of isochronous transfers. When using more than one pipe simultaneously for isochronous transfers, follow the packet constraints provided in section 5.6.3, Isochronous Transfer Packet Size Constraints, in Universal Serial Bus Revision 2.0 Specification. (1) Error Detection with Isochronous Transfers This module has a function for detecting the error information noted below, so that when errors occur in isochronous transfers, software can control them. Tables 29.27 and 29.28 show the priority in which errors are confirmed and the interrupts that are generated. (a) PID errors  If the PID of the packet being received is illegal (b) CRC errors and bit stuffing errors  If an error occurs in the CRC of the packet being received, or the bit stuffing is illegal R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1697 of 3092 Section 29 USB 2.0 Host/Function Module (c) SH7268 Group, SH7269 Group Maximum packet size exceeded  The maximum packet size exceeded the set value. (d) Overrun and underrun errors  When host controller function is selected:  When using isochronous IN transfers (reception), the IN token was received but the buffer memory is not empty.  When using isochronous OUT transfers (transmission), the OUT token was transmitted, but the data was not in the buffer memory.  When function controller function is selected:  When using isochronous IN transfers (transmission), the IN token was received but the data was not in the buffer memory.  When using isochronous OUT transfers (reception), the OUT token was received, but the buffer memory was not empty. (e) Interval errors When function controller function is selected, the following cases are considered as interval errors:  During an isochronous IN transfer, the token could not be received during the interval frame.  During an isochronous OUT transfer, the OUT token was received during frames other than the interval frame. Page 1698 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.27 Error Detection when a Token is Received Detection Priority Error Generated Interrupt and Status 1 PID errors No interrupts are generated in both cases when the host controller function is selected and the function controller function is selected (ignored as a corrupted packet). 2 CRC error and bit stuffing errors No interrupts generated in both cases when the host controller function is selected and the function controller function is selected (ignored as a corrupted packet). 3 Overrun and underrun errors An NRDY interrupt is generated to set the OVRN bit in both cases when host controller function is selected and function controller function is selected. When the host controller function is selected, no tokens are transmitted. When the function controller function is selected, a zero-length packet is transmitted in response to IN token. However, no data packets are received in response to OUT token. 4 Interval errors An NRDY interrupt is generated when the function controller function is selected. It is not generated when the host controller function is selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1699 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module Table 29.28 Error Detection when a Data Packet is Received Detection Priority Order Error Generated Interrupt and Status 1 PID errors No interrupts are generated (ignored as a corrupted packet) 2 CRC error and bit stuffing errors An NRDY interrupt is generated to set the CRCE bit in both cases when the host controller function is selected and the function controller function is selected. 3 Maximum packet size exceeded error A BEMP interrupt is generated to set the PID bits to STALL in both cases when the host controller function is selected and the function controller function is selected. (2) DATA-PID This module does not support High Bandwidth transfers. When the function controller function is selected, this module operates as follows in response to the received PID. (a) IN direction     (b) OUT direction (when using full-speed operation)     (c) DATA0: Sent as data packet PID DATA1: Not sent DATA2: Not sent mDATA: Not sent DATA0: Received normally as data packet PID DATA1: Received normally as data packet PID DATA2: Packets are ignored mDATA: Packets are ignored OUT direction (when using high-speed operation)     DATA0: Received normally as data packet PID DATA1: Received normally as data packet PID DATA2: Received normally as data packet PID mDATA: Received normally as data packet PID Page 1700 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 29 USB 2.0 Host/Function Module Interval Counter The isochronous interval can be set using the IITV bits in PIPEPERI. The interval counter enables the functions shown in table 29.29 when the function controller function is selected. When the host controller function is selected, this module generates the token issuance timing. When the host controller function is selected, the interval counter operation is the same as the interrupt transfer operation. Table 29.29 Functions of the Interval Counter when the Function Controller Function is Selected Transfer Direction Function Conditions for Detection IN IN buffer flush function When an IN token cannot be normally received in the interval frame during an isochronous IN transfer OUT Notifies that a token not being received When an OUT token cannot be normally received in the interval frame during an isochronous OUT transfer The interval count is carried out when an SOF is received or for interpolated SOFs, so the isochronisms can be maintained even if an SOF is damaged. The frame interval that can be set is the 2IITV frame or 2IITV  frames. (a) Interval Counter Initialization when the Function Controller Function is Selected This module initializes the interval counter under the following conditions.  Power-on reset The IITV bit is initialized.  Buffer memory initialization using the ACLRM bit The IITV bits are not initialized but the count value is.  USB bus reset After the interval counter has been initialized, the counter is started under the following conditions 1 or 2 when a packet has been transferred normally. 1. An SOF is received following transmission of data in response to an IN token, in the PID = BUF state. 2. An SOF is received after data following an OUT token is received in the PID = BUF state. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1701 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module The interval counter is not initialized under the conditions noted below. 1. When the PID bit is set to NAK or STALL The interval timer does not stop. This module attempts the transactions at the subsequent interval. 2. The USB bus reset or the USB is suspended The IITV bit is not initialized. When the SOF has been received, the counter is restarted from the value prior to the reception of the SOF. (b) Interval Counting and Transfer Control when the Host Controller Function is Selected This module controls the interval between token issuance operations based on the IITV bit settings. Specifically, this module issues a token for a selected pipe once every 2IITV () frames. This module counts the interval every 1-ms frame for the pipes used for communications with the full-speed or low-speed peripheral devices connected to a high-speed HUB. This module starts counting the token issuance interval at the () frame following the () frame in which the PID bits have been set to BUF. USB bus PID bit setting Token S O F S O F S O F O U T D A T A 0 S O F O U T D A T A 0 NAK BUF BUF BUF Token not issued Token not issued Token issued Token issued Interval counter started Figure 29.16 Token Issuance when IITV = 0 Page 1702 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group USB bus S O F S O F S O F PID bit setting Token Section 29 USB 2.0 Host/Function Module O U T D A T A 0 S O F S O F O U T D A T A 0 S O F S O F O U T D A T A 0 NAK BUF BUF BUF BUF BUF BUF Token not issued Token not issued Token issued Token not issued Token issued Token not issued Token issued Interval counter started Figure 29.17 Token Issuance when IITV = 1 When the selected pipe is for isochronous transfers, this module carries out the operation below in addition to controlling token issuance interval. This module issues a token even when the NRDY interrupt generation condition is satisfied.  When the selected pipe is for isochronous IN transfers This module generates the NRDY interrupt when this module issues the IN token but does not receive a packet successfully from a peripheral device (no response or packet error). This module sets the OVRN bit to 1 generating the NRDY interrupt when the time to issue an IN token comes in a state in which this module cannot receive data because the FIFO buffer is full (because data is read from the FIFO buffer too late).  When the selected pipe is for isochronous OUT transfers This module sets the OVRN bit to 1 generating the NRDY interrupt and transmitting a zerolength packet when the time to issue an OUT token comes in a state in which there is no data to be transmitted in the FIFO buffer (because data is written to the FIFO buffer too late ). The token issuance interval is reset when a power-on reset is applied or the ACLRM bit is set to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1703 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module (c) Interval Counting and Transfer Control when the Function Controller Function is Selected  When the selected pipe is for isochronous OUT transfers This module generates the NRDY interrupt when this module fails to receive a data packet within the interval set by the IITV bits in terms of () frames. This module generates the NRDY interrupt when this module fails to receive a data packet because of a CRC error or other errors contained in the packet, or because of the FIFO buffer being full. This module generates the NRDY interrupt on receiving an SOF packet. Even if the SOF packet is corrupted, the internal interpolation is used and allows the interrupt to be generated at the timing to receive the SOF packet. However, when the IITV bits are set to the value other than 0, this module generates the NRDY interrupt on receiving an SOF packet for every interval after starting interval counting operation. When the PID bits are set to NAK after starting the interval timer, this module does not generate the NRDY interrupt on receiving an SOF packet. The interval counting starts at the different timing depending on the IITV bit setting as follows.  When IITV = 0: The interval counting starts at the () frame following the () frame in which the PID bits for the selected pipe has been set to BUF. USB bus PID bit setting Token S O F S O F S O F NAK Token reception is not waited O U T D A T A 0 S O F O U T D A T A 0 BUF BUF BUF Token reception is not waited Token reception is waited Token reception is waited Interval counter started Figure 29.18 Relationship between () Frames and Expected Token Reception when IITV = 0  When IITV  0: The interval counting starts on completion of successful reception of the first data packet after the PID bits for the selected pipe have been modified to BUF. Page 1704 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group USB bus S O F S O F S O F PID bit setting Token Section 29 USB 2.0 Host/Function Module NAK BUF Token Token reception reception is not waited is not waited O U T D A T A 0 BUF Token reception is waited S O F S O F BUF O U T D A T A 0 BUF Token Token reception reception is not waited is waited S O F S O F O U T D A T A 0 BUF BUF Token reception is not waited Token reception is waited Interval counter started Figure 29.19 Relationship between () Frames and Expected Token Reception when IITV = 1  When the selected pipe is for isochronous IN transfers The IFIS bit should be 1 for this use. When IFIS = 0, this module transmits a data packet in response to the received IN token irrespective of the IITV bit setting. When IFIS = 1, this module clears the FIFO buffer when this module fails to receive an IN token within the interval set by the IITV bits in terms of () frames in a state in which there is data to be transmitted in the FIFO buffer. This module also clears the FIFO buffer when this module fails to receive an IN token successfully because of a bus error such as a CRC error contained in the token. This module clears the FIFO buffer on receiving an SOF packet. Even if the SOF packet is corrupted, the internal interpolation is used and allows the FIFO buffer to be cleared at the timing to receive the SOF packet. The interval counting starts at the different timing depending on the IITV bit setting (similar to the timing during OUT transfers). The interval count clearing condition is any of the following in function controller mode.  When a power-on reset is applied.  When the ACLRM bit is set to 1.  When this module detects a USB bus reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1705 of 3092 Section 29 USB 2.0 Host/Function Module (4) SH7268 Group, SH7269 Group Setup of Data to be Transmitted using Isochronous Transfer when the Function Controller Function is Selected With isochronous data transmission using this module in function controller function, after data has been written to the buffer memory, a data packet can be sent with the next frame in which an SOF packet is detected. This function is called the isochronous transfer transmission data setup function, and it makes it possible to designate the frame from which transmission began. If a double buffer is used for the buffer memory, transmission will be enabled for only one of the two buffers even after the writing of data to both buffers has been completed, that buffer memory being the one to which the data writing was completed first. For this reason, even if multiple IN tokens are received, the only buffer memory that can be sent is one packet's worth of data. When an IN token is received, if the buffer memory is in the transmission enabled state, this module transmits the data. If the buffer memory is not in the transmission enabled state, however, a zero-length packet is sent and an underrun error occurs. Figure 29.20 shows an example of transmission using the isochronous transfer transmission data setup function with this module, when IITV = 0 (every frame) has been set. Page 1706 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module (1) Reception start 1 (transmit data is prepared before IN token reception starts) SOF SOF SOF SOF Received token Packet to be transmitted Buffer A Empty Writing Empty Buffer B Writing ended Transfer enabled Writing Writing ended (2) Reception start 2 (example 1: transmit data is prepared after IN token reception starts) SOF IN Received token Packet to be transmitted Buffer A IN Empty Writing IN Zerolength Zerolength Data -A Writing ended Transfer enabled Empty Empty Buffer B (3) Reception start 2 (example 2: transmit data is prepared after IN token reception starts) SOF SOF IN Received token Packet to be transmitted Buffer A SOF IN Zerolength Empty Writing Empty Buffer B SOF IN Data -A Writing ended Transfer enabled Writing Data -B Empty Writing ended Writing Writing ended Transfer enabled Empty (4) IN token reception at the frame other than the specified interval SOF SOF IN Received token Zerolength Packet to be transmitted Buffer A Buffer B Empty IN Writing IN Zerolength Data -A Writing Writing ended Transfer enabled Empty SOF SOF IN Empty Writing ended Data -B Writing Writing ended Transfer enabled Empty Figure 29.20 Example of Data Setup Function Operation (5) Isochronous Transfer Transmission Buffer Flush when the Function Controller Function is Selected If an SOF packet or a SOF packet is received without receiving an IN token in the interval frame during isochronous data transmission, this module operates as if an IN token had been corrupted, and clears the buffer for which transmission is enabled, putting that buffer in the writing enabled state. If a double buffer is being used and writing to both buffers has been completed, the buffer memory that was cleared is seen as the data having been sent at the same interval frame, and transmission is enabled for the buffer memory that is not discarded with SOF or SOF packets reception. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1707 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module The timing at which the operation of the buffer flush function varies depending on the value set for the IITV bit.  If IITV = 0 The buffer flush operation starts from the next frame after the pipe becomes valid.  In any cases other than IITV = 0 The buffer flush operation is carried out subsequent to the first normal transaction. Figure 29.21 shows an example of the buffer flush function of this module. When an unanticipated token is received prior to the interval frame, this module sends the written data or a zero-length packet according to the buffer state. SOF Buffer A Empty Writing Writing ended Transfer enabled Empty Writing Writing ended Buffer flush operation is carried out Buffer B Empty Writing Writing ended Transfer enabled Figure 29.21 Example of Buffer Flush Function Operation Figure 29.22 shows an example of this module generating an interval error. There are five types of interval errors, as shown below. The interval error is generated at the timing indicated by (1) in the figure, and the IN buffer flush function is activated. If an interval error occurs during an IN transfers, the buffer flush function is activated; and if it occurs during an OUT transfer, an NRDY interrupt is generated. The OVRN bit should be used to distinguish between NRDY interrupts such as received packet errors and overrun errors. In response to tokens that are shaded in the figure, responses occur based on the buffer memory status. 1. IN direction:  If the buffer is in the transmission enabled state, the data is transferred as a normal response.  If the buffer is in the transmission disabled state, a zero-length packet is sent and an underrun error occurs. 2. OUT direction:  If the buffer is in the reception enabled state, the data is received as a normal response.  If the buffer is in the reception disabled state, the data is discarded and an overrun error occurs. Page 1708 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module SOF (1) Normal transfer Token (2) Token corrupted Token (3) Packet inserted Token (4) Frame misaligned 1 Token (5) Frame misaligned 2 Token (6) Token delayed Token Token 1 Token Token 1 Token 1 Token Token Token Token Interval when IITV = 1 Token received at the specified interval Token Token received at the frame other than the specified interval Token Token Token Token Token Token Token 1 Token 1 1 Token 1 Token Figure 29.22 Example of an Interval Error Being Generated when IITV = 1 29.4.9 SOF Interpolation Function When the function controller function is selected and if data could not be received at intervals of 1 ms (when using full-speed operation) or 125 s (when using high-speed operation) because an SOF packet was corrupted or missing, this module interpolates the SOF. The SOF interpolation operation begins when the USBE and SCKE bits in SYSCFG have been set to 1 and an SOF packet is received. The interpolation function is initialized under the following conditions.  Power-on reset  USB bus reset  Suspended state detected Also, the SOF interpolation operates under the following specifications.  125 s/1 ms conforms to the results of the reset handshake protocol.  The interpolation function is not activated until an SOF packet is received.  After the first SOF packet is received, either 125 s or 1 ms is counted with an internal clock of 48 MHz, and interpolation is carried out.  After the second and subsequent SOF packets are received, interpolation is carried out at the previous reception interval.  Interpolation is not carried out in the suspended state or while a USB bus reset is being received. (With suspended transitions in high-speed operation, interpolation continues for 3 ms after the last packet is received.) This module supports the following functions based on the SOF detection. These functions also operate normally with SOF interpolation, if the SOF packet was corrupted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1709 of 3092 SH7268 Group, SH7269 Group Section 29 USB 2.0 Host/Function Module  Refreshing of the frame number and the micro-frame number  SOFR interrupt and SOF lock  Isochronous transfer interval count If an SOF packet is missing when full-speed operation is being used, the FRNM bit in FRMNUM is not refreshed. If a SOF packet is missing during high-speed operation, the UFRNM bit in UFRMNUM is refreshed. However, if a SOF packet for which the UFRNM = 000 is missing, the FRNM bit is not refreshed. In this case, the FRNM bit is not refreshed even if successive SOF packets other than UFRNM = 000 are received normally. 29.4.10 Pipe Schedule (1) Conditions for Generating a Transaction When the host controller function is selected and UACT has been set to 1, this module generates a transaction under the conditions noted in table 29.30. Table 29.30 Conditions for Generating a Transaction Conditions for Generation Transaction DIR PID IITV0 Buffer State SUREQ Setup * * * *1 1 setting Control transfer data stage, status stage, bulk transfer IN BUF Invalid Receive area exists *1 OUT BUF Invalid Send data exists *1 IN BUF Valid Receive area exists *1 OUT BUF Valid Send data exists *1 IN BUF Valid *2 *1 OUT BUF Valid *3 *1 Interrupt transfer Isochronous transfer 1 1 1 Notes: 1. Symbols () in the table indicate that the condition is one that is unrelated to the generating of tokens. "Valid" indicates that, for interrupt transfers and isochronous transfers, the condition is generated only in transfer frames that are based on the interval counter. "Invalid" indicates that the condition is generated regardless of the interval counter. 2. This indicates that a transaction is generated regardless of whether or not there is a receive area. If there was no receive area, however, the received data is destroyed. 3. This indicates that a transaction is generated regardless of whether or not there is any data to be sent. If there was no data to be sent, however, a zero-length packet is sent. Page 1710 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 29 USB 2.0 Host/Function Module Transfer Schedule This section describes the transfer scheduling within a frame of this module. After the module sends an SOF, the transfer is carried out in the sequence described below. 1. Execution of periodic transfers A pipe is searched in the order of Pipe 1  Pipe 2  Pipe 6  Pipe 7  Pipe 8  Pipe 9, and then, if the pipe is one for which an isochronous or interrupt transfer transaction can be generated, the transaction is generated. 2. Setup transactions for control transfers The DCP is checked, and if a setup transaction is possible, it is sent. 3. Execution of bulk and control transfer data stages and status stages A pipe is searched in the order of DCP  Pipe 1  Pipe 2  Pipe 3  Pipe 4  Pipe 5, and then, if the pipe is one for which a bulk or control transfer data stage or a control transfer status stage transaction can be generated, the transaction is generated. If a transfer is generated, processing moves to the next pipe transaction regardless of whether the response from the peripheral device is ACK or NAK. Also, if there is time for the transfer to be done within the frame, step 3 is repeated. (3) USB Communication Enabled Setting the UACT bit of the DVSTCTR register to 1 initiates sending of an SOF or SOF, and makes it possible to generate a transaction. Setting the UACT bit to 0 stops the sending of the SOF or SOF and initiates a suspend state. If the setting of the UACT bit is changed from 1 to 0, processing stops after the next SOF or SOF is sent. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1711 of 3092 Section 29 USB 2.0 Host/Function Module 29.5 Usage Notes 29.5.1 Power Supply for USB Transceiver SH7268 Group, SH7269 Group  Set the voltage level of power supply USBAVCC, USBDVCC*, and USBUVCC* to the same as VCC.  Set the voltage level of power supply USBAPVCC and USBDPVCC* to the same as PVCC.  Set the voltage level of ground USBAVSS*, USBDVSS*, USBUVSS*, USBAPVSS*, and USBDPVSS* to the same as VSS.  Separate analog power supplies USBAVCC, USBAVSS*, USBAPVCC, and USBAPVSS* from the digital power supplies. Note: * SH7269 (BGA) Group products do not have this pin. Page 1712 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Section 30 Digital Video Decoder 30.1 Features The digital video decoder consists of an A/D converter for video signal input, a sync separator circuit, a burst controlled oscillator (BCO), a 2D Y/C separator circuit, chroma decoding circuit, a digital clamp circuit, and an output gain adjustment circuit. Table 30.1 shows the digital video decoder functions. Table 30.1 Digital Video Decoder Functions Item Function Input signal Video signal  Composite video signal (CVBS) Functional outline        A/D converter for video signal input  VIN1 and VIN2 pin input selection  Sync tip clamp  Programmable gain amplifier (PGA) (1.835 to 8.023 dB)  10-bit precision pipelined A/D converter Sync separation  Noise reduction LPS, auto level control sync slicer, horizontal auto frequency control (AFC), vertical count-down, interlace detection, auto gain control (AGC)/peak limiter control Burst controlled oscillator (BCO)  Color sub-carrier reproduction, color system detection (For details, see table 30.3.) Y/C separation (For details, see table 30.2.)  NTSC 2D, PAL 2D, SECAM 1D Chroma decoding  Supporting NTSC, PAL SECAM  Color killer, auto color control (ACC), TINT correction, R-Y axis correction Digital clamp  Pedestal clamp (Y), center clamp (Cb/Cr), noise detection Output gain adjustment  Contrast adjustment: 0 to approx. two times  Color adjustment (Cb/Cr independent): 0 to approx. two times R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1713 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.2 Supported Y/C Separation Operation Color System Y/C Separation Operation NTSC-3.58 Two dimensional NTSC-4.43 Two dimensional PAL-M Two dimensional PAL-N Two dimensional PAL-4.43 Two dimensional SECAM One dimensional Table 30.3 Color System Detection COLORSY[1:0] FSCMODE FVMODE Detection Result 0: NTSC 0: 358 MHz Don't care NTSC-M 0: NTSC 1: 4.43 MHz Don't care NTSC-4.43 1: PAL 0: 358 MHz 0: 50 Hz PAL-N 1: PAL 0: 358 MHz 1: 60 Hz PAL-M 1: PAL 1: 4.43 MHz 0: 50 Hz PAL-B, H, I, G, D 1: PAL 1: 4.43 MHz 1: 60 Hz PAL-60 2: SECAM   SECAM 3: Unknown   Cannot be detected Page 1714 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.2 Section 30 Digital Video Decoder Block Diagram Figure 30.1 shows a block diagram of this module. This LSI A/D converter for video signal input BIAS VRT VRB Gain control Clamp VIN1 Digital control PGA VIN2 VDAVcc VDAVss A/D Noise reduction LPF, Sync slicer, Horizontal AFC, Vertical count-down, AGC/peak limiter, Signal detection HS, VS VE, HE Sync separation circuit VIDEO_X1 Crystal oscillator 27 MHz VIDEO_X2 Color sub-carrier reproduction, Color system detection BCO ACC gain, Color killer Color sub-carrier signal Color killer, Color system ACC, TINT correction, Pedestal clamp, C R-Y axis Center clamp, correction NTSC 2D, YCbCr Noise detection YCbCr PAL 2D, Y SECAM 1D Y/C separation circuit Chroma decoding Digital clamp circuit circuit Capturing position, Contrast adjustment, Color adjustment YCbCr (30 bits) Output adjustment circuit Figure 30.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1715 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.3 Input/Output Pins Table 30.4 shows the pin configuration. Table 30.4 Pin Configuration Category Name Pin Symbol I/O Description Signal Composite video signal input VIN1 Input Composite video signal (CVBS) input pin 1 VIN2 Input Composite video signal (CVBS) input pin 2 Crystal oscillator VIDEO_X1 /external clock VIDEO_X2 Input Connect to a crystal resonator for the digital video decoder. The VIDEO_X1 pin can also be used for external clock input. TOP reference voltage Output Clock Reference voltage VRT Output TOP reference voltage pin for the A/D converter for video signal input Connect to the VDAVss via a 0.1-F capacitor. BOTTOM reference voltage VRB Output BOTTOM reference voltage pin for the A/D converter for video signal input Connect to the VDAVss via a 0.1-F capacitor. Reference voltage BIAS Output Reference voltage pin for the A/D converter for video signal input Connect to the VDAVss via a 24-k 1 resistor. Power supply Analog power supply VDAVcc Input Power supply pin for the A/D converter for video signal input Analog ground VDAVss Input Ground pin for the A/D converter for video signal input Page 1716 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4 Section 30 Digital Video Decoder Register Descriptions Table 30.5 shows the register configuration. Table 30.5 Register Configuration Register Name Abbreviation R/W Address Access Size ADC control register 1 ADCCR1 R/W H'FFFFA008 16 Timing generation control register 1 TGCR1 R/W H'FFFFA00E 16 Timing generation control register 2 TGCR2 R/W H'FFFFA010 16 Timing generation control register 3 TGCR3 R/W H'FFFFA012 16 Sync separation control register 1 SYNSCR1 R/W H'FFFFA01A 16 Sync separation control register 2 SYNSCR2 R/W H'FFFFA01C 16 Sync separation control register 3 SYNSCR3 R/W H'FFFFA01E 16 Sync separation control register 4 SYNSCR4 R/W H'FFFFA020 16 Sync separation control register 5 SYNSCR5 R/W H'FFFFA022 16 Horizontal AFC control register 1 HAFCCR1 R/W H'FFFFA024 16 Horizontal AFC control register 2 HAFCCR2 R/W H'FFFFA026 16 Horizontal AFC control register 3 HAFCCR3 R/W H'FFFFA028 16 Vertical countdown control register 1 VCDWCR1 R/W H'FFFFA02A 16 Digital clamp control register 1 DCPCR1 R/W H'FFFFA030 16 Digital clamp control register 2 DCPCR2 R/W H'FFFFA032 16 Digital clamp control register 3 DCPCR3 R/W H'FFFFA034 16 Digital clamp control register 4 DCPCR4 R/W H'FFFFA036 16 Digital clamp control register 5 DCPCR5 R/W H'FFFFA038 16 Digital clamp control register 6 DCPCR6 R/W H'FFFFA03A 16 Digital clamp control register 7 DCPCR7 R/W H'FFFFA03C 16 Digital clamp control register 8 DCPCR8 R/W H'FFFFA03E 16 Noise detection control register NSDCR R/W H'FFFFA040 16 Burst lock/chroma decoding control register BTLCR R/W H'FFFFA042 16 Burst gate pulse control register BTGPCR R/W H'FFFFA044 16 ACC control register 1 ACCCR1 R/W H'FFFFA046 16 ACC control register 2 ACCCR2 R/W H'FFFFA048 16 ACC control register 3 ACCCR3 R/W H'FFFFA04A 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1717 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Name Abbreviation R/W Address Access Size TINT control register TINTCR R/W H'FFFFA04C 16 Y/C delay/chroma decoding control register YCDCR R/W H'FFFFA04E 16 AGC control register 1 AGCCR1 R/W H'FFFFA050 16 AGC control register 2 AGCCR2 R/W H'FFFFA052 16 Peak limiter control register PKLIMITCR R/W H'FFFFA054 16 Over-range control register 1 RGORCR1 R/W H'FFFFA056 16 Over-range control register 2 RGORCR2 R/W H'FFFFA058 16 Over-range control register 3 RGORCR3 R/W H'FFFFA05A 16 Over-range control register 4 RGORCR4 R/W H'FFFFA05C 16 Over-range control register 5 RGORCR5 R/W H'FFFFA05E 16 Over-range control register 6 RGORCR6 R/W H'FFFFA060 16 Over-range control register 7 RGORCR7 R/W H'FFFFA062 16 Feedback control register for horizontal AFC phase comparator AFCPFCR R/W H'FFFFA07C 16 Register update enable register RUPDCR R/W H'FFFFA07E 16 Sync separation status/vertical cycle read register VSYNCSR R H'FFFFA080 16 Horizontal cycle read register HSYNCSR R H'FFFFA082 16 Digital clamp read register 1 DCPSR1 R H'FFFFA084 16 Digital clamp read register 2 DCPSR2 R H'FFFFA086 16 Noise detection read register NSDSR R H'FFFFA08C 16 Chroma decoding read register 1 CROMASR1 R H'FFFFA08E 16 Chroma decoding read register 2 CROMASR2 R H'FFFFA090 16 Sync separation read register SYNCSSR R H'FFFFA092 16 AGC control read register 1 AGCCSR1 R H'FFFFA094 16 AGC control read register 2 AGCCSR2 R H'FFFFA096 16 Y/C separation control register 3 YCSCR3 R/W H'FFFFA104 16 Y/C separation control register 4 YCSCR4 R/W H'FFFFA106 16 Y/C separation control register 5 YCSCR5 R/W H'FFFFA108 16 Y/C separation control register 6 YCSCR6 R/W H'FFFFA10A 16 Y/C separation control register 7 YCSCR7 R/W H'FFFFA10C 16 Y/C separation control register 8 YCSCR8 R/W H'FFFFA10E 16 Page 1718 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Name Abbreviation R/W Address Access Size Y/C separation control register 9 YCSCR9 R/W H'FFFFA110 16 Y/C separation control register 11 YCSCR11 R/W H'FFFFA114 16 Y/C separation control register 12 YCSCR12 R/W H'FFFFA116 16 Digital clamp control register 9 DCPCR9 R/W H'FFFFA180 16 Chroma filter TAP coefficient (WA_F0) register for Y/C separation YCTWA_F0 R/W H'FFFFA192 16 Chroma filter TAP coefficient (WA_F1) register for Y/C separation YCTWA_F1 R/W H'FFFFA194 16 Chroma filter TAP coefficient (WA_F2) register for Y/C separation YCTWA_F2 R/W H'FFFFA196 16 Chroma filter TAP coefficient (WA_F3) register for Y/C separation YCTWA_F3 R/W H'FFFFA198 16 Chroma filter TAP coefficient (WA_F4) register for Y/C separation YCTWA_F4 R/W H'FFFFA19A 16 Chroma filter TAP coefficient (WA_F5) register for Y/C separation YCTWA_F5 R/W H'FFFFA19C 16 Chroma filter TAP coefficient (WA_F6) register for Y/C separation YCTWA_F6 R/W H'FFFFA19E 16 Chroma filter TAP coefficient (WA_F7) register for Y/C separation YCTWA_F7 R/W H'FFFFA1A0 16 Chroma filter TAP coefficient (WA_F8) register for Y/C separation YCTWA_F8 R/W H'FFFFA1A2 16 Chroma filter TAP coefficient (WB_F0) register for Y/C separation YCTWB_F0 R/W H'FFFFA1A4 16 Chroma filter TAP coefficient (WB_F1) register for Y/C separation YCTWB_F1 R/W H'FFFFA1A6 16 Chroma filter TAP coefficient (WB_F2) register for Y/C separation YCTWB_F2 R/W H'FFFFA1A8 16 Chroma filter TAP coefficient (WB_F3) register for Y/C separation YCTWB_F3 R/W H'FFFFA1AA 16 Chroma filter TAP coefficient (WB_F4) register for Y/C separation YCTWB_F4 R/W H'FFFFA1AC 16 Chroma filter TAP coefficient (WB_F5) register for Y/C separation YCTWB_F5 R/W H'FFFFA1AE 16 Chroma filter TAP coefficient (WB_F6) register for Y/C separation YCTWB_F6 R/W H'FFFFA1B0 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1719 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Name Abbreviation R/W Address Access Size Chroma filter TAP coefficient (WB_F7) register for Y/C separation YCTWB_F7 R/W H'FFFFA1B2 16 Chroma filter TAP coefficient (WB_F8) register for Y/C separation YCTWB_F8 R/W H'FFFFA1B4 16 Chroma filter TAP coefficient (NA_F0) register for Y/C separation YCTNA_F0 R/W H'FFFFA1B6 16 Chroma filter TAP coefficient (NA_F1) register for Y/C separation YCTNA_F1 R/W H'FFFFA1B8 16 Chroma filter TAP coefficient (NA_F2) register for Y/C separation YCTNA_F2 R/W H'FFFFA1BA 16 Chroma filter TAP coefficient (NA_F3) register for Y/C separation YCTNA_F3 R/W H'FFFFA1BC 16 Chroma filter TAP coefficient (NA_F4) register for Y/C separation YCTNA_F4 R/W H'FFFFA1BE 16 Chroma filter TAP coefficient (NA_F5) register for Y/C separation YCTNA_F5 R/W H'FFFFA1C0 16 Chroma filter TAP coefficient (NA_F6) register for Y/C separation YCTNA_F6 R/W H'FFFFA1C2 16 Chroma filter TAP coefficient (NA_F7) register for Y/C separation YCTNA_F7 R/W H'FFFFA1C4 16 Chroma filter TAP coefficient (NA_F8) register for Y/C separation YCTNA_F8 R/W H'FFFFA1C6 16 Chroma filter TAP coefficient (NB_F0) register for Y/C separation YCTNB_F0 R/W H'FFFFA1C8 16 Chroma filter TAP coefficient (NB_F1) register for Y/C separation YCTNB_F1 R/W H'FFFFA1CA 16 Chroma filter TAP coefficient (NB_F2) register for Y/C separation YCTNB_F2 R/W H'FFFFA1CC 16 Chroma filter TAP coefficient (NB_F3) register for Y/C separation YCTNB_F3 R/W H'FFFFA1CE 16 Chroma filter TAP coefficient (NB_F4) register for Y/C separation YCTNB_F4 R/W H'FFFFA1D0 16 Chroma filter TAP coefficient (NB_F5) register for Y/C separation YCTNB_F5 R/W H'FFFFA1D2 16 Chroma filter TAP coefficient (NB_F6) register for Y/C separation YCTNB_F6 R/W H'FFFFA1D4 16 Page 1720 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Name Abbreviation R/W Address Access Size Chroma filter TAP coefficient (NB_F7) register for Y/C separation YCTNB_F7 R/W H'FFFFA1D6 16 Chroma filter TAP coefficient (NB_F8) register for Y/C separation YCTNB_F8 R/W H'FFFFA1D8 16 Luminance (Y) signal gain control register YGAINCR R/W H'FFFFA200 16 Color difference (Cb) signal gain control register CBGAINCR R/W H'FFFFA202 16 Color difference (Cr) signal gain control register CRGAINCR R/W H'FFFFA204 16 PGA register update PGA_UPDATE R/W H'FFFFA280 16 PGA control register PGACR R/W H'FFFFA282 16 ADC control register 2 ADCCR2 R/W H'FFFFA284 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1721 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.1 ADC Control Register 1 (ADCCR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        AGC MODE         Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R R R R R R R R Bit Bit Name 15 to 9  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 AGCMODE 0 R/W A/D Converter AGC ON/OFF Control 0: AGC OFF 1: AGC ON 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (1) AGC Control The AGCMODE bit controls the AGC ON/OFF. When AGCMODE is 1, the AGC operation is performed by detecting the sync amplitude and video peak amplitude and controlling the PGA gain of the ADC. When PGACR.PGA_GAIN_SEL is 1, the PGA gain can be directly controlled with the PGACR.PGA_GAIN value. At this time, the AGCMODE setting is invalid. Setting AGCMODE to 0 and PGACR.PGA_GAIN_SEL to 0 simultaneously is prohibited. Page 1722 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.2 Section 30 Digital Video Decoder Timing Generation Control Register 1 (TGCR1) Bit: 15 14 13 12 11 10 9        8 7 6 5 4 3 2 1 0 SRCLEFT[8:0] Initial value: 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial Bit Name Value R/W Description 15 to 9  R Reserved All 0 These bits are always read as 0. The write value should always be 0. 8 to 0 SRCLEFT H'13C [8:0] R/W Left End of Input Video Signal Capturing Area Set the position from the horizontal sync reference in 27-MHz clock cycle units. Note: All the bits in this register are updated when the vertical sync signal is asserted with the NEWSETTING bit in RUPDCR being 1. (1) Timing Generation (Horizontal Start Position) Control SRCLEFT sets the start position of the horizontal enable signal of the output video signal from the horizontal sync reference in 27-MHz clock cycle units. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1723 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.3 Timing Generation Control Register 2 (TGCR2) Bit: 15 14 Initial value: 0 1 0 R/W R/W 13 12 11 10 9 8 7 6 1 0 0 0 0 1 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SRCTOP[5:0] R/W: R/W Bit Bit Name 15 to 10 SRCTOP [5:0] 9 to 0 5 4 3 2 1 0 SRCHEIGHT[9:0] Initial Value R/W Description H'14 R/W Top End of Input Video Signal Capturing Area Set the position from the vertical sync reference in one-line units. SRCHEIGHT H'0E8 R/W Height of Input Video Signal Capturing Area [9:0] Set the vertical active period in one-line units. Note: All the bits in this register are updated when the vertical sync signal is asserted with the NEWSETTING bit in RUPDCR being 1. (1) Timing Generation (Vertical Start Position) Control SRCTOP sets the start position of the vertical enable signal of the output video signal from the vertical sync reference in one-line units. (2) Timing Generation (Vertical Width) Control SRCHEIGHT sets the height of the vertical enable signal of the output video signal in one-line units. Page 1724 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.4 Section 30 Digital Video Decoder Timing Generation Control Register 3 (TGCR3) Bit: 15 14 13 12 11      10 9 8 7 6 5 4 3 2 1 0 SRCWIDTH[10:0] Initial value: 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 15 to 11  Initial Value R/W Description All 0 Reserved R These bits are always read as 0. The write value should always be 0. 10 to 0 SRCWIDTH [10:0] H'500 R/W Width of Input Video Signal Capturing Area Set the horizontal active period in 27-MHz clock cycle units. Note: All the bits in this register are updated when the vertical sync signal is asserted with the NEWSETTING bit in RUPDCR being 1. (1) Timing Generation (Horizontal Width) Control SRCHEIGHT sets the width of horizontal enable signal of the output video signal in 27-MHz clock cycle units. Figures 30.2 to 30.6 show the timings generated with the NTSC (59.94 Hz) and PAL/SECAM (50.00 Hz) formats. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1725 of 3092 SRCHEIGHT = Active area [line] SRCWIDTH = Active area [clock] SRCTOP = Start of active area [line] SH7268 Group, SH7269 Group Section 30 Digital Video Decoder SRCLEFT = Start of active area [clock] Figure 30.2 Active Image Area Setting 59.94 Hz (525i) 63.555 [usec] 1716@27.0 MHz 52.655 [usec] 1422@27.0 MHz 9.4[usec] 253@27.0MHz Overscan rate is 0% (100% display) SRCWIDTH (10:0) = 1422@27.0 MHz (100%) SRCLEFT (8:0) = 253@27.0 MHz 2.5% Overscan rate is 5% (95% display) 2.5% SRCWIDTH (10:0) = 1351@27.0 MHz (95%) SRCLEFT (8:0) = 288@27.0 MHz Figure 30.3 Example of Horizontal Active Image Period (59.94 Hz (525i)) Page 1726 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 50.00 Hz (625i) 64.000 [usec] 1728@27.0MHz 52.000 [usec] 1404@27.0MHz 10.5 [usec] 283@27.0MHz Overscan rate is 0% (100% display) SRCWIDTH (10:0) = 1404@27.0 MHz (100%) SRCLEFT (8:0) = 283@27.0 MHz 2.5% Overscan rate is 5% (95% display) 2.5% SRCWIDTH (10:0) = 1333@27.0 MHz (95%) SRCLEFT (8:0) = 319@27.0 MHz Figure 30.4 Example of Horizontal Active Image Period (50.00 Hz (625i)) 59.94Hz (525i) 518 Video ID 519 525 1 2 3 4 5 6 7 8 9 10 19 20 CCD 21 22 SRCTOP(5:0) = 18 [lines] 28 29 30 SRCHEIGHT(9:0) = 241 [lines] Overscan rate is 0 (100 display) 2.5 2.5 SRCTOP(5:0) = 24 [lines] SRCHEIGHT(9:0) = 229 [lines] Overscan rate is 5 (95 display) 266 is not included 255 256 262 263 264 265 266 267 268 269 270 271 272 273 SRCTOP(5:0) = 18 [lines] 282 Video ID CCD 283 284 285 291 292 293 SRCHEIGHT(9:0) = 241 [lines] Overscan rate is 0 (100 display) 2.5% SRCTOP(5:0) = 24 [lines] 2.5 SRCHEIGHT(9:0) = 229 [lines] Overscan rate is 5 (95 display) Figure 30.5 Example of Vertical Active Image Period (59.94 Hz (525i)) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1727 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 50.00 Hz (625i) 615 616 WSS 622 623 624 625 1 2 3 4 5 6 21 22 23 24 SRCTOP(5:0) = 23 [lines] 31 32 33 34 35 SRCHEIGHT(9:0) = 287 [lines] Overscan rate is 0 (100 display) 2.5 SRCTOP(5:0) = 30 [lines] 2.5 SRCHEIGHT(9:0) = 273 [lines] 337 344 Overscan rate is 5 (95 display) 313 is not included 302 303 310 311 312 313 314 315 316 317 318 319 SRCTOP(5:0) = 23 [lines] 334 335 336 345 346 347 SRCHEIGHT(9:0) = 287 [lines] Overscan rate is 0 (100 display) 2.5 SRCTOP(5:0) = 30 [lines] 2.5 SRCHEIGHT(9:0) = 273 [lines] Overscan rate is 5 (95 display) Figure 30.6 Example of Vertical Active Image Period (50.00 Hz (625i)) The active period width should not be larger than necessary. The settings of TGCR1 to TGCR3 such as valid period setting for the peak limiter are applied only to this module. To set the display size of the input video, SCL0_DS2 and SCL0_DS3 of the video display controller 4 scaler should be used. Page 1728 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.5 Sync Separation Control Register 1 (SYNSCR1) Bit: 15 Initial value: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLICER SLICER MODE_H[1:0] MODE_V[1:0] LPFHSYNC[2:0]   1 1 0 1 1 0 0 0 0 0 0 1 0 1 0 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W LPFVSYNC[2:0] 0 R/W: R/W Bit Section 30 Digital Video Decoder Bit Name VELOCITYSHIFT_H[3:0] Initial Value R/W Description 15 to 13 LPFVSYNC 011 [2:0] R/W Low-Pass Filter Cutoff Frequency before Vertical Sync Separation 0: None 1: 0.94 MHz 2: 0.67 MHz 3: 0.54 MHz 4: 0.47 MHz 5: 0.34 MHz 6: 0.27 MHz 7: 0.23 MHz 12 to 10 LPFHSYNC 011 [2:0] R/W Low-Pass Filter Cutoff Frequency before Horizontal Sync Separation 0: None 1: 2.15 MHz 2: 1.88 MHz 3: 1.34 MHz 4: 1.07 MHz 5: 0.94 MHz 6: 0.67 MHz 7: 0.54 MHz 9, 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1729 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Initial Value R/W Description Bit Bit Name 7 to 4 VELOCITYS 0000 R/W Reference Level Operation Speed Control for Composite HIFT_H[3:0] Sync Separation (for horizontal sync signal) 0: 1 1: 2 2: 4 3: 8 4: 16 5: 32 6: 64 7: 128 Others: 256 Standard speed (1)  High speed (256) 3, 2 SLICERMO 10 DE_H[1:0] R/W Auto-Slice Level Setting for Composite Sync Separator Circuit (for horizontal sync signal) 0: Manual setting by CSYNCSLICE_H 1: 25% of sync depth (Auto) 2: 50% of sync depth (Auto) 3: 75% of sync depth (Auto) 1, 0 SLICERMO 10 DE_V[1:0] R/W Auto-Slice Level Setting for Composite Sync Separation Circuit (for vertical sync signal) 0: Manual setting by CSYNCSLICE_V 1: 25% of sync depth (Auto) 2: 50% of sync depth (Auto) 3: 75% of sync depth (Auto) Page 1730 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Low-Pass Filter Control before Vertical Sync Separation LPFVSYNC sets the noise reduction low-pass filter for the input video signal fed to a sync separator in order to avoid sync separation error caused by noise. A low-pass filter cutoff frequency should be set not to deteriorate (i.e. to enable to detect) the composite sync signal components. Table 30.6 Low-Pass Filter Cutoff Frequency before Vertical Sync Separation For Vertical Sync Separation LPFVSYNC[2:0] t fc (MHz) 1 0.109375 0.939647766 2 0.078125 0.671176976 0.0625 0.536941581 4 0.0546875 0.469823883 5 0.0390625 0.335588488 6 0.003125 0.26847079 7 0.0273438 0.234911942 Video signal amplitude (10 bits) 3 1024 960 896 832 768 704 640 576 512 448 384 320 256 192 128 64 0 Video input fc = 0.23 MHz fc = 0.27 MHz fc = 0.34 MHz fc = 0.47 MHz fc = 0.54 MHz fc = 0.67 MHz fc = 0.94 MHz Figure 30.7 Low-Pass Filter Output Waveform Near Horizontal Sync Signal during 100 White Signal Input (Vertical: Pattern Diagram) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1731 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (2) Low-Pass Filter Control before Horizontal Sync Separation LPFHSYNC sets the noise reduction low-pass filter for the input video signal fed to a sync separator in order to avoid sync separation error caused by noise. A low-pass filter cutoff frequency should be set not to deteriorate (i.e. to enable to detect) the composite sync signal components. Table 30.7 Low-Pass Filter Cutoff Frequency before Horizontal Sync Separation For Horizontal Sync Separation t fc (MHz) 1 0.25 2.147766323 2 0.21875 1.879295533 3 0.15625 1.342353952 4 0.125 1.073883162 5 0.10938 0.939647766 6 0.07813 0.671176976 7 0.0625 0.536941581 Video signal amplitude (10 bits) LPFHSYNC[2:0] 1024 960 896 832 768 704 640 576 512 448 384 320 256 192 128 64 0 Video input fc = 0.54 MHz fc = 0.67 MHz fc = 0.94 MHz fc = 1.07 MHz fc = 1.34 MHz fc = 1.88 MHz fc = 2.15 MHz Figure 30.8 Low-Pass Filter Output Waveform Near Vertical Sync Signal during 100 White Signal Input (Horizontal: Pattern Diagram) Page 1732 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 30 Digital Video Decoder Reference Level Operation Speed Control for Sync Separation VELOCITYSHIFT_H controls the speed for automatically determining the slice level. If sync skew is caused by sync sag, it can be improved by raising the determination speed using VELOCITYSHIFT_H. (4) Horizontal Sync Slicer Control SLICERMODE_H controls composite sync signal separation from the video signals. The slice level for composite sync signal separation can be set either manually or automatically. When automatic setting is used, the level is automatically set using the sync signal amplitude detection result, which is described later. The sync slicer can be controlled separately for horizontal and vertical sync signals. (5) Vertical Sync Slicer Control SLICERMODE_V controls composite sync signal separation from the video signals. The slice level for composite sync signal separation can be set either manually or automatically. When automatic setting is used, the level is automatically set using the sync signal amplitude detection result, which is described later. The sync slicer can be controlled separately for horizontal and vertical sync signals. Horz. Sync (25%) Horz. Sync (50%) Horz. Sync (75%) Video Signal 75% 50% 25% 75% 50% 25% Figure 30.9 Auto Slice Level Setting R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1733 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Horz. Sync Video Signal ADC Bottom (0[LSB]) CSYNCSLICE Figure 30.10 Manual Slice Level Setting Page 1734 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.6 Section 30 Digital Video Decoder Sync Separation Control Register 2 (SYNSCR2) Bit: 15 14 13 12     11 10 8 9 7 6 5 4 2 3 1 0 SYNCMINDUTY_H[5:0] SYNCMAXDUTY_H[5:0] Initial value: 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 15 to 12  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 6 SYNCMAXD 001111 UTY_H[5:0] R/W Max Ratio of Horizontal Cycle to Horizontal Sync Signal Pulse Width Valid when auto slice level setting is active (SLICERMODE_H  0). 5 to 0 SYNCMIND 001010 UTY_H[5:0] R/W Min Ratio of Horizontal Cycle to Horizontal Sync Signal Pulse Width Valid when auto slice level setting is active (SLICERMODE_H  0). (1) Sync Amplitude Detection Control for Horizontal Sync Separation SYNCMAXDUTY_H and SYNCMINDUTY_H control the sync signal amplitude detection of composite sync signal included in the video signal. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1735 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.8 Auto Slice Level Register Settings for Composite Sync Separation Horizontal Horizontal Sync Period Width (sec) (sec) Video Active Period (sec) SYNCMAXDUTY _H[5:0], SYNCMAXDUTY Horizontal _V[5:0], Blanking Interval Recommended (sec) Value SYNCMINDUTY _H[5:0], SYNCMINDUTY _V[5:0] Recommended Value 525i/ 63.56 59.94 Hz 4.70 52.66 10.90 15 10 625i/ 50 Hz 4.70 52.00 12.00 15 10 64.00 Page 1736 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.7 Section 30 Digital Video Decoder Sync Separation Control Register 3 (SYNSCR3) Bit: 15 14   13 12 11 10 9 8 7 SSCLIPSEL[3:0] 6 5 4 3 2 1 0 CSYNCSLICE_H[9:0] Initial value: 0 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial Bit Name Value R/W Description 15, 14  R Reserved All 0 These bits are always read as 0. The write value should always be 0. 13 to 10 SSCLIPS 1111 EL[3:0] R/W Clipping Level Clip the video signal supplied to the vertical/horizontal sync separation low-pass filter Bit value = Clipping level (amplitude 50% to no clipping) 9 to 0 CSYNCS 001001 R/W LICE_ 0010 H[9:0] 0: 512 1: 546 2: 580 3: 614 4: 648 5: 682 6: 716 7: 750 8: 785 9: 819 10: 853 11: 887 12: 921 13: 955 14: 989 15: 1023 Slice Level for Composite Sync Signal Separation (for horizontal sync signal) Valid when manual slice level setting is active (SLICERMODE_H = 0). Setting range: 0 to 1023 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1737 of 3092 Section 30 Digital Video Decoder (1) SH7268 Group, SH7269 Group Video Signal Clipping Setting for Sync Separation For input video signals supplied to the sync separator circuit, the level to clip the high tone component of the video signal is specified to reduce amplitude-dependency of the video signal. The video clipping level should be set not to deteriorate (i.e. to enable to detect) the composite sync signal components. (2) Slice Level Setting for Horizontal Sync Separation CSYNCSLICE_H sets the slice level for sync separation. This bit is valid only when SLICERMODE_H = 0. Page 1738 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.8 Section 30 Digital Video Decoder Sync Separation Control Register 4 (SYNSCR4) Bit: 15 14 13 12     10 11 9 8 7 6 5 4 3 2 0 1 SYNCMINDUTY_V[5:0] SYNCMAXDUTY_V[5:0] Initial value: 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 15 to 12  Initial Value R/W Description All 0 Reserved R These bits are always read as 0. The write value should always be 0. 11 to 6 SYNCMAXD UTY_V[5:0] 001111 R/W Max Ratio of Horizontal Cycle to Vertical Sync Signal Pulse Width Valid when auto slice level setting is active (SLICERMODE_V  0). 5 to 0 SYNCMINDU 001010 TY_V[5:0] R/W Min Ratio of Horizontal Cycle to Horizontal Sync Signal Pulse Width Valid when auto slice level setting is active (SLICERMODE_V  0). (1) Sync Amplitude Detection Control for Vertical Sync Separation SYNCMAXDUTY_V and SYNCMINDUTY_V control the sync signal amplitude detection of composite sync signal included in the video signal. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1739 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.9 Auto Slice Level Register Settings for Composite Sync Separation Horizontal Horizontal Sync Period Width (sec) (sec) Video Active Period (sec) SYNCMAXDUTY _H[5:0], SYNCMAXDUTY Horizontal _V[5:0], Blanking Interval Recommended (sec) Value SYNCMINDUTY _H[5:0], SYNCMINDUTY _V[5:0] Recommended Value 525i/ 63.56 59.94 Hz 4.70 52.66 10.90 15 10 625i/ 50 Hz 4.70 52.00 12.00 15 10 64.00 Page 1740 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.4.9 Section 30 Digital Video Decoder Sync Separation Control Register 5 (SYNSCR5) Bit: 15 14 VSYNC DELAY Initial value: 0 R/W: R/W 13 11 12 10 9 8 6 7 VSYNCSLICE[4:0] 5 4 3 2 1 0 CSYNCSLICE_V[9:0] 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Description Bit Bit Name 15 VSYNCDE 0 LAY R/W Delays the separated vertical sync signal for 1/4 horizontal cycle. 0: Disable 1/4fH delay 1: Enable 1/4fH delay Note: Stability of the field determination result may be improved by changing VSYNCDELAY. 14 to 10 VSYNCSLI 01011 R/W Threshold for Vertical Sync Separation CE[4:0] The greater the value, the wider pulse width is needed. 9 to 0 CSYNCSLI 00100 R/W Slice Level for Composite Sync Signal Separation (for vertical CE_V[9:0] 10010 sync signal) Valid when manual slice level setting is active (SLICERMODE_V = 0). Setting range: 0 to 1023 (1) Vertical Sync Separation Control VSYNCDELAY controls the phases of vertical sync signal and horizontal sync signal. When VSYNCDELAY is 1, the stability of the field determination result may be improved by delaying the vertical sync signal for 1/4 fH. (2) Vertical Sync Separation Control VSYNCSLICE controls the threshold for separating vertical sync signal from composite sync signal. The value will be set depending on the serration pulse width of each video signal format. Table 30.10 shows the recommended set values. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1741 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.10 Recommended Threshold and Serration Pulse Width (for reference) Serration Pulse Width [sec] VSYNCSLICE[4:0] 525i/59.94Hz 27.08 10 625i/50Hz 27.30 10 (3) Vertical Sync Separation Slice Level Control CSYNCSLICE_V sets the slice level for sync separation. This bit is valid only when SLICERMODE_V = 0. Page 1742 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.10 Horizontal AFC Control Register 1 (HAFCCR1) Bit: 15 13 14 12 HAFCGAIN[3:0] Initial value: 0 R/W: R/W Bit 11 10  HAFCFRE ERUN 9 8 7 6 5 4 1 2 3 0 HAFCTYP[9:0] 1 1 0 0 0 1 0 1 0 1 1 0 1 0 0 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W 15 to 12 HAFCGAI 0110 N[3:0] R/W Description Horizontal AFC Loop Gain 0 to 5: A smaller value needs a longer time for synchronization. 6: Standard value 7 to 15: A larger value needs a shorter time for synchronization.  11 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 HAFCFRE 0 ERUN R/W Horizontal AFC Free-Run Oscillation Mode ON/OFF 0: OFF 1: ON 9 to 0 (1) HAFCTYP 10101 R/W [9:0] 10100 Horizontal AFC Center Oscillation Frequency Set an offset from 1024th clock pulse in 27-MHz clock cycle units. Horizontal AFC Loop Gain Control HAFCGAIN sets the loop gain (response speed) of the horizontal AFC. The larger the value is, the faster the response speed is. However, setting a larger value will result in more susceptibleness to noise. (2) Horizontal AFC Free-Run Control HAFCFREERUN controls the horizontal AFC free-run operation. When HAFCFREERUN is 1, the horizontal AFC operates independently of the inputs and performs free-run operation. HAFCFREERUN should usually be set to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1743 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (3) Horizontal AFC Lock Range (Horizontal) Control HAFCMIN, HAFCTYP, and HAFCMAX set the horizontal AFC center oscillation frequency and lock range. The horizontal AFC function is controlled to stabilize the horizontal sync signal when the signals are deteriorated by trick playback of VCR or a weak electric field. HAFCMIN[9:0] Min oscillation frequency of horizontal AFC HAFCTYP[9:0] Center oscillation frequency of horizontal AFC HAFCMAX[9:0] Max oscillation frequency of horizontal AFC Horizontal AFC lock range can be indicated by the following formula. HAFCMIN < HAFCTYP < HAFCMAX …(1) where HAFCMIN = HAFCTYP  allowable deviation HAFCTYP = N  M  1024 HAFCMAX = HAFCTYP + allowable deviation M: Number of clock pulses per horizontal cycle (27MHz sampling) N: Double speed setting 2 (double speed): M < 1024 1 (normal speed): M  1024 The horizontal AFC is locked if the formula indicated by (1) is satisfied. When the horizontal AFC is locked, FHLOCK in VSYNCSR is set to 1. Otherwise, FHLOCK is 0. Table 30.11 Horizontal AFC Lock Range Setting fH N-Times Signal HorizontalM fH@ Speed HAFCMAX HAFCTYP HAFCMIN Format Cycle 27.0MHz Setting [9:0] [9:0] [9:0] Deviation Unit 525i [clk] 625i 63.56 [sec] 1716 [clk] 1 64.00 [sec] 1728 [clk] 1 Page 1744 of 3092 771 692 618 79 -74 15.034 15.734 16.434 -0.700 0.700 [kHz] 785 704 629 81 [clk] 14.925 15.625 16.325 -0.700 0.700 -75 [kHz] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group HAFCMIN Section 30 Digital Video Decoder Double-speed oscillation 2 512 HAFCMAX 0 2 512 HAFCMIN Normal-speed oscillation 1024 HAFCMAX (1) (3) (1) (2) (3) 1024 27-MHz clock cycle (2) (3) Horizontal AFC lock range with DOX2HOSC = 1 (forced double-speed oscillation) Horizontal AFC lock range with DOX2HOSC = 0 and NOX2HOSC = 1 (double-speed oscillation OFF) Horizontal AFC lock range with DOX2HOSC = 0 and NOX2HOSC = 0 (double-speed oscillation ON) Figure 30.11 Horizontal AFC Lock Range (Horizontal) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1745 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.11 Horizontal AFC Control Register 2 (HAFCCR2) Bit: 15 14 13 12 HAFCSTART[3:0] Initial value: 0 R/W: R/W Bit 11 10 9 8 7 6 NOX2H DOX2H OSC OSC 5 4 3 2 1 0 HAFCMAX[9:0] 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W 15 to 12 HAFCSTART 0000 [3:0] R/W Description Start Line of Horizontal AFC Normal Operation (=VBI process end line) Start the phase comparison at the Nth line after the vertical sync signal. 11 NOX2HOSC 0 R/W Disable of Horizontal AFC Double Speed Detection 0: Auto control 1: Double speed oscillation disabled 10 DOX2HOSC 0 R/W Horizontal AFC Forced Double-Speed Oscillation 0: Auto control 1: Forced double-speed oscillation 9 to 0 (1) HAFCMAX [9:0] 1011100110 R/W Maximum Oscillation Frequency of Horizontal AFC Set an offset from 1024th clock pulse in 27-MHz clock cycle units. Horizontal AFC Lock Range (Vertical) Control HAFCSTART and HAFCEND specify the horizontal AFC operation range. The horizontal AFC operation should be normally stopped from several lines before the vertical sync signal to the vertical sync signal to avoid a malfunction occurring in the VCR head switch part. Vertical sync signal HAFCSTART Horizontal AFC hold period HAFCEND Horizontal AFC lock period Horizontal AFC hold period Figure 30.12 Horizontal AFC Lock Range (Vertical) Page 1746 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 30 Digital Video Decoder Horizontal AFC Double-Speed Control NOX2HOSC and DOX2HOSC control the horizontal AFC double speed detection. In the NTSC, PAL and SECAM formats, DOX2HOSC should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1747 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.12 Horizontal AFC Control Register 3 (HAFCCR3) Bit: 15 14 13 12 Initial value: 1 R/W: R/W Bit 11 10 9 8 7 5 6 HAFCMODE [1:0] HAFCEND[3:0] 3 4 1 2 0 HAFCMIN[9:0] 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 15 to 12 HAFCEND [3:0] Initial Value R/W Description 1000 End line of Horizontal AFC Normal Operation (=VBI process start line) R/W Stop the phase comparison at the Nth line before the vertical sync signal. 11, 10 HAFCMODE 10 [1:0] R/W Horizontal AFC VBI Period Operating Mode [1] Loop gain control for low S/N 0: Loop gain is fixed. 1: Loop gain is automatically controlled. [0] Horizontal AFC control during VBI period 0: Phase comparison is stopped during VBI period. 1: Loop gain is reduced during VBI period. 9 to 0 (1) HAFCMIN [9:0] 1010000010 R/W Min Oscillation Frequency of Horizontal AFC Set an offset from 1024th clock pulse in 27-MHz clock cycle units. Horizontal AFC Operation Control during VBI Period The malfunction caused by noise can be avoided by setting HAFCMODE[1] to 1 to reduce the loop gain for low S/N (VSYNCSR.ISNOISY = 1). The recommended value for HAFCMODE[1] is 1. HAFCMODE[0] controls the horizontal AFC operation during the VBI period. The recommended value for HAFCMODE[0] is 0. Page 1748 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.13 Vertical Countdown Control Register 1 (VCDWCR1) Bit: 15 14 13 12 11 10 9 VCDFR NOVCD NOVCD VCDDEFAULT EERUN 50 60 [1:0] Initial value: 0 R/W: R/W 8 7 6 5 4 VCDWINDOW[5:0] 3 2 1 0 VCDOFFSET[4:0] 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 15 VCDFREERUN 0 R/W Description R/W Vertical Countdown Free-Run Oscillation Mode ON/OFF 0: OFF 1: ON 14 NOVCD50 0 R/W Vertical Countdown 50-Hz Oscillation Mode OFF 0: 50-Hz oscillation ON 1: 50-Hz oscillation OFF 13 NOVCD60 0 R/W Vertical Countdown 60-Hz (59.94-Hz) Oscillation Mode OFF 0: 60-Hz oscillation ON 1: 60-Hz oscillation OFF 12, 11 VCDDEFAULT [1:0] 00 R/W Vertical Countdown Center Oscillation Frequency 0: Auto-detection 1: 50.00 Hz 2: 59.94 Hz 3: 60.00 Hz 10 to 5 4 to 0 VCDWINDOW [5:0] 010100 VCDOFFSET [4:0] 01010 R/W Vertical Countdown Sync Area Set a value in 0.1-ms units. R/W Vertical Countdown Minimum Oscillation Frequency Set the shift from the center frequency in 0.1-ms units. (1) Vertical Countdown Free-Run Operation Control VCDFREERUN controls the vertical countdown free-run operation. When VCDFREERUN is 1, the vertical countdown free-run operation is performed independently of the inputs. VCDFREERUN should usually be set to 0. (2) Vertical Countdown 50-Hz Oscillation Control R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1749 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder NOVD50 controls 50-Hz oscillation. When NOVCD50 is 1, the vertical countdown operation is not locked to 50 Hz. (3) Vertical Countdown 60-Hz Oscillation Control NOVD60 controls 60-Hz oscillation. When NOVCD60 is 1, the vertical countdown operation is not locked to 60 Hz. (4) Vertical Countdown Center Oscillation Frequency Control VCDDEFAULT sets the center frequency for the vertical countdown. Table 30.12 Vertical Countdown Operating Modes VCDDEFAULT[1:0] Operating Mode 0 Auto-detection 1 50.00 Hz 2 59.94 Hz 3 60.00 Hz (5) Vertical Countdown Lock Range Control VCDWINDOW and VCDOFFSET control the vertical countdown lock range. Figure 30.13 shows the bit settings and lock ranges. 60-Hz oscillation VCDWINDOW  0.1 ms VCDOFFSET  0.1 ms 0 16.6 ms 50-Hz oscillation VCDWINDOW  0.1 ms VCDOFFSET  0.1 ms 20.0 ms Time (1) (3) (2) (3) (1) Vertical countdown lock range with NOVCD 50 = 1 and NOVCD60 = 0 (60-Hz oscillation mode) (2) Vertical countdown lock range with NOVCD 50 = 1 (50-Hz oscillation mode) (3) Vertical countdown lock range with NOVCD 50 = 0 and NOVCD60 = 0 (auto detection mode) Figure 30.13 Vertical Countdown Lock Ranges Page 1750 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.14 Digital Clamp Control Register 1 (DCPCR1) Bit: Initial value: 15 14 13 12 11 10 DCPMO DE_Y    DCPCH ECK  1 R/W: R/W 9 8 7 6 5 4 3 2 1 0 BLANKLEVEL_Y[9:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 DCPMODE_Y 1 R/W Clamp Level Setting Mode (Y signal) 0: Manual clamp level setting 1: Auto clamp level setting 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 DCPCHECK 0 R/W Digital Clamp Pulse Position Check The offset given by BLANKLEVEL is added to the clamp position.  10 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 BLANKLEVEL_Y 0000000000 R/W Clamp Offset Level (Y signal) [9:0] Set the subtraction value. Set a value in 1-LSB units. 2s complement (1) Y-Signal Clamp Operation Control DCPMODE_Y controls the clamp level of Y signal. When DCPMODE_Y = 0, the value set by BLANKLEVEL_Y is subtracted from the video signal. Y signal output = Y signal input  BLANKLEVEL_Y When DCPMODE_Y is 1, the video signal level at the digital clamp pulse position (pedestal level) and BLANKLEVEL_Y are added together and the resulting value is subtracted from the video signal. Y signal output = Y signal input  (detected value + BLANKLEVEL_Y) (2) Digital Clamp Pulse Position Check Control R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1751 of 3092 Section 30 Digital Video Decoder SH7268 Group, SH7269 Group DCPCHECK allows the digital clamp pulse position to be displayed and checked on the screen. The following shows the steps to check the position. 1. Set DCPCHECK (digital clamp pulse position check bit) to 1. 2. Set SRCLEFT (left end of input video signal capturing area bit) and RES_HS[10:0] in SCL0_DS3 of the video display controller 4 scaler to 0. 3. Set clamp offset level of the signal to be monitored to Min value (512 for BLANKLEVEL_Y, 32 for BLANKLEVEL_CB/CR). 4. Adjust the pulse position and width using DCPPOS_Y (or DCPPOS_C) and DCPWIDTH. Page 1752 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.15 Digital Clamp Control Register 2 (DCPCR2) Bit: Initial value: 15 14 13 12 DCPMO DE_C    0 R/W: R/W 11 10 9 8 7 6 5 4 BLANKLEVEL_CB[5:0] 3 2 1 0 BLANKLEVEL_CR[5:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 DCPMODE_C 0 Clamp Level Setting Mode (Cb/Cr signal) R/W 0: Manual clamp level setting 1: Auto clamp level setting 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 6 BLANKLEVEL_CB [5:0] 000000 R/W Clamp Offset Level (Cb signal) Set the subtraction value. Set a value in 1-LSB units. 2s complement 5 to 0 BLANKLEVEL_CR [5:0] 000000 R/W Clamp Offset Level (Cr signal) Set the subtraction value. Set a value in 1-LSB units. 2s complement R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1753 of 3092 Section 30 Digital Video Decoder (1) SH7268 Group, SH7269 Group Cb/Cr-Signal Clamp Operation Control DCPMODE_C controls the clamp level of Cb/Cr-signal. When DCPMODE_C = 0, the value set by BLANKLEVEL_CB/BLANKLEVEL_CR is subtracted from the video signal. Cb signal output = Cb signal input  BLANKLEVEL_CB Cr signal output = Cr signal input  BLANKLEVEL_CR When DCPMODE_C = 1, sum of the video signal level (center level) in the digital clamp pulse position and BLANKLEVEL_CB/CR is subtracted from the video signal. Cb signal output = Cb signal input  (detected value + BLANKLEVEL_CB) Cr signal output = Cr signal input  (detected value + BLANKLEVEL_CR) Page 1754 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.16 Digital Clamp Control Register 3 (DCPCR3) Bit: 15  14 13 12 11 10 9 8 7 6 5 4 3 2 1 0             DCPRESPONSE[2:0] Initial value: 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 DCPRESPONSE 101 [2:0] 11 to 0  All 0 R/W Digital Clamp Response Speed The larger the value is, the faster the response speed is. However, that will result in more susceptibleness to noise. R Reserved These bits are always read as 0. The write value should always be 0. (1) Digital Clamp Response Speed DCPRESPONSE sets the digital clamp response speed. Though the larger value makes the response faster, that will result in more susceptibleness to noise. DCPRESPONSE is used in common to Y, Cb, and Cr signals. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1755 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.17 Digital Clamp Control Register 4 (DCPCR4) Bit: 15 12 13 14 10 11 DCPSTART[5:0] Initial value: 0 R/W: R/W 8 7 6 5 4 3 2 1 0          1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R R R R R R R R Bit Bit Name 15 to 10 9 to 0 9  Initial Value R/W Description DCPSTART 010000 [5:0] R/W Digital Clamp Start Line (in 1-line units)  R All 0 Start clamp pulses at the Nth line after the vertical sync signal. Reserved These bits are always read as 0. The write value should always be 0. Page 1756 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.18 Digital Clamp Control Register 5 (DCPCR5) Bit: 15 12 13 14 10 11 DCPEND[5:0] Initial value: 0 R/W: R/W 8 7 6 5 4 3 2 1 0          1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R R R R R R R R Initial Value R/W DCPEND [5:0] 010000 R/W  All 0 Bit Bit Name 15 to 10 9 to 0 9  Description Digital Clamp End Line (in 1-line units) Stop clamp pulses at the Nth line before the vertical sync signal. R Reserved These bits are always read as 0. The write value should always be 0. (1) Digital Clamp Pulse Control (Vertical) DCPSTART and DCPEND control the digital clamp pulses in the vertical direction. Figure 30.14 shows the bit settings and digital clamp timing. DCPSTART and DCPEND are used in common to Y, Cb, and Cr signals. Vertical sync signal DCPSTART Digital clamp pulse signal Digital clamp pulse signal output period DCPEND ... Figure 30.14 Digital Clamp Timing (Vertical) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1757 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.19 Digital Clamp Control Register 6 (DCPCR6) Bit: 15 14 13  12 11 10 9 8 DCPWIDTH[6:0] 7 6 5 4 3 2 1 0         Initial value: 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Bit Bit Name Initial Value R/W 15  0 R Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 8 DCPWIDTH 01101 R/W [6:0] 10 Digital Clamp Pulse Width Setting range: 0 to 127 Set a value in 27-MHz clock cycle units. 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1758 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.20 Digital Clamp Control Register 7 (DCPCR7) Bit: 15 14 13 12 11 10 9 8 DCPPOS_Y[7:0] Initial value: 1 R/W: R/W 7 6 5 4 3 2 1 0         0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Initial Value Bit Bit Name R/W 15 to 8 DCPPOS_Y 10100010 R/W [7:0] Description Digital Clamp Pulse Horizontal Start Position (Y signal) Setting range: 0 to 255 Set a value in 27-MHz clock cycle units. 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1759 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.21 Digital Clamp Control Register 8 (DCPCR8) Bit: 15 14 13 12 11 10 9 8 DCPPOS_C[7:0] Initial value: 0 R/W: R/W 15 to 8 6 5 4 3 2 1 0        0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Initial Bit Name Value Bit 7  R/W DCPPOS 000110 R/W _C[7:0] 11 Description Digital Clamp Pulse Horizontal Start Position (Cb/Cr signal) Setting range: 0 to 255 Set a value in 27-MHz clock cycle units. 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (1) Digital Clamp Pulse Control (Horizontal) DCPWIDTH, DCPPOS_Y, and DCPPOS_C control the digital clamp pulses in the horizontal direction. Figure 30.15 shows the bit settings and digital clamp timing. DCPPOS_Y is used for Y signal and DCPPOS_C is for Cb/Cr signal. DCPWIDTH is used in common to Y, Cb, and Cr signals. DCPPOS_Y/C  27 (usec) DCPWIDTH  27 (usec) Horz. Sync Clamp Pulse colorburst Video Signal synctip Figure 30.15 Digital Clamp Timing (Horizontal) Page 1760 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.22 Noise Detection Control Register (NSDCR) Bit: 15 14   Initial value: 0 0 0 R/W: R R R/W 13 12 5 4 3 2   10 9    0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R/W R/W R/W R/W R/W R R R/W R/W Bit Initial Bit Name Value R/W Description 15, 14  R Reserved All 0 6 11 ACFINPUT[1:0] 8 7 ACFLAGTIME[4:0] 1 0 ACFFILTER[1:0] These bits are always read as 0. The write value should always be 0. 13, 12 ACFINPU 00 T[1:0] R/W Video Signal for Autocorrelation Function 0: Y signal 1: Cb signal 2, 3: Cr signal 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 to 4 ACFLAG 00000 TIME[4:0] R/W Delay Time for Autocorrelation Function Calculation 0 to 31 clock pulses @ 27-MHz clock The NSDSR.AFCSTRENGTH value almost corresponds to noise power when the delay time is set to 0. 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 ACFFILT 00 ER[1:0] R/W Smoothing Parameter of Autocorrelation Function Data The smaller the ACFFILTER value is, the longer the time period is taken. The time period varies from 1 field to several seconds. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1761 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (1) Input for Noise Detection ACFINPUT controls inputs for noise detection. Table 30.13 Input Selection for Noise Detection ACFINPUT Input Signal 0 Y signal 1 Cb signal 2, 3 Cr signal (2) Autocorrelation Function Control for Noise Detection ACFLAGTIME controls autocorrelation function for noise detection. The NSDSR.AFCSTRENGTH value almost corresponds to noise power when the delay time is set to 0. (3) Smoothing Filter Control for Noise Detection ACFFILTER controls smoothing function for noise detection inputs. The smaller the ACFFILTER value is, the larger the field integration is (the longer time period is taken for noise detection). Page 1762 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.23 Burst Lock/Chroma Decoding Control Register (BTLCR) Bit: 15 Initial value: 0 R/W: R/W 12 13 14 LOCKRANGE [1:0] 8 9 10 11 BCOFR LOOPGAIN[1:0] LOCKLIMIT[1:0] EERUN  7 5 6 DEFAULTSYS [1:0] 4 3 2 0 1 NONTS NONTS NOPAL NOPAL NOPAL NOSEC C358 C443 M N 443 AM 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 15, 14 LOCKRANGE [1:0] Initial Value R/W Description 01 R/W Burst Lock PLL Lock Range 0: 400 Hz 1: 800 Hz 2: 1200 Hz 3: 1600 Hz 13, 12 11, 10 LOOPGAIN [1:0] 01 LOCKLIMIT [1:0] 10 R/W Burst Lock PLL Loop Gain The larger value makes the response faster, but the noise is more easily picked up. R/W Level for Burst Lock PLL to Re-Search Free-Run Frequency The larger value more easily unlocks the PLL to start research. 9 BCOFREERUN 0 R/W Burst Lock PLL Free-Run Oscillation Mode ON/OFF 0: OFF 1: ON 8  0 R Reserved This bit is always read as 0. The write value should always be 0. 7, 6 DEFAULTSYS 00 [1:0] R/W Default Color System 0: NTSC 1: PAL 2: SECAM 3: Not specified 5 NONTSC358 0 R/W NTSC-M Detection Control 0:NTSC-M detection ON 1:NTSC-M detection OFF R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1763 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Bit Bit Name Initial Value R/W Description 4 NONTSC443 0 R/W NTSC-4.43 Detection Control 0:NTSC-4.43 detection ON 1:NTSC-4.43 detection OFF 3 NOPALM 0 R/W PAL-M Detection Control 0:PAL-M detection ON 1:PAL-M detection OFF 2 NOPALN 0 R/W PAL-N Detection Control 0:PAL-N detection ON 1:PAL-N detection OFF 1 NOPAL443 0 R/W PAL-B, G, H, I, D Detection Control 0: PAL-B, G, H, I, D detection ON 1: PAL-B, G, H, I, D detection OFF 0 NOSECAM 00 R/W SECAM Detection Control 0: SECAM detection ON 1: SECAM detection OFF. (1) Lock Range of Burst Lock PLL LOCKRANGE controls the lock range of the burst lock PLL. Table 30.14 Lock Range of Burst Lock PLL LOCKRANGE Lock Range of Burst Lock PLL 0 0: 400 Hz 1 1: 800 Hz 2 2: 1200 Hz 3 3: 1600 Hz Page 1764 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 30 Digital Video Decoder Burst Lock PLL Loop Gain Control LOOPGAIN controls the loop gain of the burst lock PLL. The larger value makes the response faster, but the noise is more easily picked up. (3) Burst Lock PLL Lock Limit Control LOCKLIMIT controls the lock limit of the burst lock PLL. The larger the LOCKLIMIT value is, the more easily the PLL free-run frequency is unlocked to start re-search. (4) Burst Lock PLL Free-Run Operation Control BCOFREERUN controls the free-run operation of burst lock PLL. When BCOFREERUN is 1, the burst lock PLL performs free-run operation independently of the inputs. BCOFREERUN should usually be set to 0. (5) Default Color System during Chroma Decoding DEFAULTSYS sets the default color system when automatic judgement of the color system for use in chroma decoding is not possible. Table 30.15 Default Color System DEFAULTSYS Default Color System 0 NTSC 1 PAL 2 SECAM 3 Not specified R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1765 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (6) Color System Detection Control NONTSC358, NONTSC443, NOPALM, NOPALN, NOPAL443, and NOSECAM control the color system detection. Color system detection can be fully automatic, manual, or semi-automatic (detecting the specified color system only). If the detection result does not apply to any color system type, a color system selected by DEFAULTSYS is used for the operation. Color system detection can be controlled (ON or OFF) individually for each type. By enabling one particular color system to be detected, the color system can be fixed. Table 30.16 shows the color system detection control methods. Table 30.16 Color System Detection Control NOSECAM NOPAL443 NOPALN NOPALM NONTSC443 NONTSC358 0 0 0 0 0 0 NTSC-3.58(M) 1 1 1 1 1 0 NTSC-4.43 1 1 1 1 0 1 PAL-M 1 1 1 0 1 1 PAL-N 1 1 0 1 1 1 PAL-4.43 1 0 1 1 1 1 SECAM 0 1 1 1 1 1 Auto In auto mode, the color system detection result is stored into the register. Tables 30.17 and 30.18 show color system detection and detection result setting. Page 1766 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.17 Color System Detection Result (1) COLORSYS[1:0] FSCMODE FVMODE Detection Result 0: NTSC 0: 3.58MHz don't care NTSC-M 0: NTSC 1: 4.43MHz don't care NTSC-4.43 1: PAL 0: 3.58MHz 0: 50Hz PAL-N 1: PAL 0: 3.58MHz 1: 60Hz PAL-M 1: PAL 1: 4.43MHz 0: 50Hz PAL-B, H, I, G, D 1: PAL 1: 4.43MHz 1: 60Hz PAL-60 2: SECAM   SECAM 3: Unknown   Undetectable ISNTSC ISPAL ISSECAM Undetectable 0 0 0 NTSC 1 0 0 PAL 0 1 0 SECAM 0 0 1 Table 30.18 Color System Detection Result (2) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1767 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.24 Burst Gate Pulse Control Register (BTGPCR) Bit: 15 14 13 12 BGPCH ECK Initial value: 0 R/W: R/W 11 10 9 8 7 6 5 BGPWIDTH[6:0] 4 3 2 1 0 BGPSTART[7:0] 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 15 BGPCHECK 0 R/W Description R/W Burst Gate Pulse Position Check Displays the front and end edges of burst gate pulses by white lines. 14 to 8 7 to 0 (1) BGPWIDTH [6:0] 0100100 R/W BGPSTART [7:0] 10000010 R/W Burst Gate Pulse Width Specify the offset from the 64th clock pulse width in 27-MHz clock cycle units. Burst Gate Pulse Start Position Specify the position from the horizontal sync signal reference in 27-MHz clock cycle units. Burst Gate Pulse Control BGPWIDTH and BGPSTART control the burst gate pulse timing. The burst gate pulse position is specified to extract color burst from the video signal which is considered as a reference signal for the burst lock PLL. Usually, the burst gate pulse should be set so that it should start at the latter part of the horizontal sync signal and include the reference position in order to respond to an insert position shift of color burst caused by VCR. Page 1768 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Horizontal front porch Horizontal sync pulse Horizontal back porch Video signal Color burst Burst gate pulse BGPSTART 27.0 [usec] (BGPWIDTH 64) [usec] 27.0 Figure 30.16 Burst Gate Pulse Generation Timing (2) Burst Gate Pulse Position Check BGPCHECK controls the burst gate pulse position check on screen. The following shows the steps to check the position:  Burst gate position check: Set BGPCHECK to 1.  Input video signal capturing left end setting: Set SRCLEFT to 0 and RES_HS[10:0] in SCL0_DS3 of the video display controller 4 scaler to 0.  Adjust the pulse position and width with BGPSTART and BGPWIDTH. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1769 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.25 ACC Control Register 1 (ACCCR1) Bit: 15 14 12 13 KILLEROFFSET[3:0] Initial value: 1 R/W: R/W 10 11 ACC MODE 9 7 8 5 6 ACCMAXGAIN [1:0] 4 3 1 2 0 ACCLEVEL[8:0] 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 15 to 12 KILLEROFF 1000 SET[3:0] R/W Description R/W The levels of these bits and KILLERLEVEL are added together to be the level to turn off the color killer. This level corresponds to the Peak-to-Peak amplitude of the color burst signal. 11 ACCMODE 0 R/W ACC Operating Mode 0: Auto gain 1: Manual gain 10, 9 ACCMAXG 00 AIN[1:0] R/W Maximum ACC Gain Valid when ACCMODE = 0 (auto gain setting). 0: 6 times 1: 8 times 2: 12 times 3: 16 times 8 to 0 ACCLEVEL 10010010 R/W [8:0] 0 ACC Reference Color Burst Amplitude Valid when ACCMODE = 0 (auto gain setting). Set Peak-to-Peak amplitude in 1-LSB units. (1) Color Killer Offset Control KILLEROFFSET sets the hysteresis to make the color killer OFF. If the KILLEROFFSET value is too large, the color killer cannot be turned off as long as the burst amplitude is not large enough. If the KILLEROFFSET value is too small, the color killer is turned on and off repeatedly due to noise. The standard value is between 4 and 10. Page 1770 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Killer operation Killer OFF Killer ON KILLERLEVEL KILLERLEVEL [IRE] + KILLEROFFSET Maximum burst amplitude (quantum size) Figure 30.17 Color Killer Operation (2) ACC Operation Control ACCMODE controls the ACC operation. Table 30.19 ACC Operating Modes ACCMODE Color Gain Adjustment 0 Auto gain 1 Manual gain (3) Maximum ACC Gain Control ACCMAXGAIN controls the maximum ACC gain. ACCMAXGAIN is valid only when ACCMODE  0. Table 30.20 Maximum ACC Gain ACCMAXGAIN Maximum Color Gain 0 6 times 1 8 times 2 12 times 3 16 times R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1771 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (4) ACC Level Control ACCLEVEL sets the burst amplitude of the chroma signal after gain correction. ACCLEVEL is valid only when ACCMODE = 0. The ACC adjusts the gain so that the input chroma signal burst amplitude should be the same level as the ACCLEVEL value. Input signal Gain is computed based on the burst. Gain is automatically adjusted. ACCLEVEL Output signal Figure 30.18 ACC Level Setting [IRE] Output signal 70 40 Standard burst signal amplitude (p-p): 40 [IRE] 0 0 2.5 70 [IRE] Input signal Figure 30.19 ACC Input/Output Characteristics Page 1772 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.21 ACC Characteristics Input Burst Signal Level Output Burst Signal Level More than 24.1 [dB] Reference amplitude (variable) ± acceptable error (variable) 24.1[dB] or less Decreased in proportion to input level R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1773 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.26 ACC Control Register 2 (ACCCR2) Bit: 15 14 13 12 11      10 9 8 7 6 CHROMASUB GAIN[1:0] 5 4 3 2 1 0 CHROMAMAINGAIN[8:0] Initial value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved This bit is always read as 0. The write value should always be 0. 10, 9 CHROMAS 00 UBGAIN [1:0] R/W Chroma Manual Gain (sub) Valid when ACCMODE = 1 (manual gain setting) 0: 1 time 1: 2 times 2: 4 times 3: 8 times 8 to 0 (1) CHROMAM 10000000 R/W AINGAIN 0 [8:0] Chroma Manual Gain (main) Valid when ACCMODE = 1 (manual gain setting) The value 256 corresponds to 1 time. Chroma Gain Adjustment (Manual) Control CHROMASUBGAIN and CHROMAMAINGAIN control the chroma gain. CHROMASUBGAIN and CHROMAMAINGAIN are valid only when ACCMODE is 1. C signal output = C signal input  (CHROMASUBGAIN + CHROMAMAINGAIN/256) Page 1774 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.27 ACC Control Register 3 (ACCCR3) Bit: 15 14 13 Initial value: 0 R/W: R/W 8 7 ACCPRECIS[5:0] 4 5 6 KILLER MODE 2 3 1 0  KILLERLEVEL[5:0] 0 1 0 1 0 0 0 0 0 1 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Bit Name 15, 14 7 9 10 1 Bit 13 to 8 11 12 ACCRESPONSE [1:0] Initial Value R/W Description ACCRESPONSE 01 [1:0] R/W ACC Response Speed ACCPRECIS [5:0] 010100 R/W KILLERMODE 0 The larger value makes the response faster, but the noise is more easily picked up. ACC Gain Adjustment Accuracy Set the acceptable error level of color burst signal amplitude after ACC adjustment by 1 LSB of 10bit accuracy. R/W Forced Color Killer Mode ON/OFF 0: Auto-detection 1: Killer mode is forcedly ON. 6 to 1 0 KILLERLEVEL [5:0] 001001  0 R/W Color Killer Operation Start Point Set the half value of Peak-to-Peak amplitude by 1 LSB of 10-bit accuracy. R Reserved This bit is always read as 0. The write value should always be 0. (1) ACC Response Speed Control ACCRESPONSE controls the ACC response speed. The larger value makes the response faster, and the smaller value makes it slower. However, the large value causes the noise to be more easily picked up. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1775 of 3092 Section 30 Digital Video Decoder (2) SH7268 Group, SH7269 Group ACC Acceptable Error Range Control ACCPRECIS controls the acceptable error range of the output burst signal amplitude based on ACCLEVEL (target value). If ACCLEVEL = 236 and ACCPRECIS = 20, the ACC gain is fixed within the following range: (236  20) < Output signal burst signal amplitude < (236  20) (3) Killer Operating Mode Control KILLERMODE controls the killer operating mode. When KILLERMODE = 1, the killer is forcedly turned ON. (4) Killer Level Control KILLERLEVEL controls the level to make the killer ON. For details, see section 30.4.25 (1) Color Killer Offset Control. Page 1776 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.28 TINT Control Register (TINTCR) Bit: 15 14 13 12 11 10 9 8 7 6 TINTSUB[5:0] Initial value: 0 R/W: R/W 5 4 3 2 1 0 TINTMAIN[9:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 10 TINTSUB [5:0] 000000 Fine Adjustment of R-Y Demodulation Axis (only valid for NTSC/PAL) R/W Set a value by 360/1024 degrees. 2s complement 9 to 0 TINTMAIN [9:0] 0000000000 R/W Hue Adjustment Level (only valid for NTSC/PAL) Set a value by 360/1024 degrees. 2s complement (1) R-Y Axis Correction Control TINTSUB controls the phase of R-Y axis by 11.25 degrees. R-Y Axis offset +11.25 [deg.] (Max: +11.25 [deg.]) Normal (Center) R-Y R-Y Axis offset 11.25 [deg.] (Max: 11.25 [deg.]) R-Y R-Y Red Yellow Magenta Green 11.25 deg. B-Y B-Y B-Y Blue Cyan 11.25 deg. 11.25 [deg.] < Axis < 11.25 [deg.] Figure 30.20 Example of R-Y Axis Correction R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1777 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (2) Hue Adjustment (TINT) Correction Control TINTMAIN controls the phase of demodulation axis by 0 to 360 degrees. +45 [deg.] (Max: +180 [deg.]) 45 [deg.] (Max: 180 [deg.]) Normal (Center) R-Y R-Y R-Y Red Yellow Magenta B-Y B-Y Green 45deg. Blue Cyan B-Y 45deg. 180 [deg.]  HUE  +180 [deg.] Figure 30.21 Example of Hue Adjustment (TINT) Correction Page 1778 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.29 Y/C Delay/Chroma Decoding Control Register (YCDCR) Bit: 15 14 13 12 11 10 9        8 7 5 6 4 3  LUMADELAY[4:0] 1 2 0 CHROM DEMODMODE ALPF [1:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 to 4 LUMADELAY [4:0] 00000 R/W Luminance Signal Delay Adjustment 16 to +15 clock pulses Set a value by the 2s complement. 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 CHROMALPF 0 R/W LPF for Demodulated Chroma 0: Not used 1: Used 1, 0 DEMODMODE 10 [1:0] R/W Averaging Processing for Pre-Demodulated Line 0: No processing 1: Setting prohibited 2: For PAL 3: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1779 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (1) Y/C Delay Adjustment Control LUMADELAY controls the Y/C delay. Table 30.22 Y/C Delay Adjustment LUMADELAY Operation 31 Advances Y signal 16 [clk] : : 16 Advances Y signal 1 [clk] 0 No delay 1 Delays Y signal for 1 [clk] : : 15 Delays Y signal for 15 [clk] (2) Frequency Band Inhibition after Demodulation CHROMALPF controls frequency band inhibition after demodulation. Table 30.23 Frequency Band Inhibition after Demodulation CHROMALPF Operation 0 Frequency band inhibition filter OFF 1 Frequency band inhibition filter ON (3) Chroma Decoding Operation Control DEMODMODE controls operating modes of chroma demodulation. Table 30.24 Y/C delay adjustment DEMODMODE Operation 0 One-line demodulation 2 Two-line demodulation for PAL only 1 and 3 Setting prohibited Page 1780 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.30 AGC Control Register 1 (AGCCR1) Bit: 15 14   13 12 DORED NORED UCE UCE 11 10 9 8 7 6 5 4 3 2 1 0 AGCLEVEL[8:0] AGCRESPONSE[2:0] Initial value: 0 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 R/W: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 DUREDUCE 0 R/W Manual Control of Sync Signal Amplitude Detection during VBI Period 0: Sets sync amplitude to AGC standard value. 1: Sets AGC gain to 3/4 times the normal gain value. 12 NOREDUCE 0 R/W Control of Sync Signal Amplitude Detection during VBI Period 0: Detects sync amplitude. 1: Does not detect sync amplitude. 11 to 9 8 to 0 AGCRESPO 101 NSE[2:0] AGCLEVEL [8:0] R/W 0111011 R/W 00 AGC Response Speed The larger register value makes the response faster However, the larger value causes the noise to be more easily picked up. Sync Signal Reference Amplitude Setting range: 0 to 511 10-bit unsigned value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1781 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (1) Sync Signal Amplitude Detection during VBI Period DOREDUCE and NOREDUCE control detection of the AGC sync signal amplitude fluctuation during VBI period. Table 30.25 Sync Signal Amplitude Detection Operation during VBI Period DOREDUCE Sync Signal Amplitude Detection Operation during VBI Period 0 Sets sync amplitude to AGC standard 1 Sets AGC gain to 3/4 times the normal gain value Table 30.26 Sync Signal Amplitude Detection during VBI Period NOREDUCE Sync Signal Amplitude Detection during VBI Period 0 Detects sync amplitude. 1 Does not detect sync amplitude. (2) AGC Response Speed Control AGCRESPONSE controls the AGC response speed. The larger register value makes the response faster, and smaller value makes it slower. (The large value causes the noise to be more easily picked up.) The recommended value is 4 to avoid a malfunction caused by trick playback of VCR (fastforward play/rewind play) or a weak electric field. (3) AGC Level Control AGCLEVEL controls the AGC target level. When NTSC signals are quantized by a 10-bit A/D converter, sync signal amplitude for full range of the A/D converter can be provided by: 1023[LSB] × (40[IRE] ÷ 173[IRE]) = 236.53179[LSB] Page 1782 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.27 shows the ideal AGC level for each input signal format. Table 30.27 AGC Level Setting Values (Ideal Values) Input Signal Format AGCLEVEL[8:0] NTSC 236 PAL/SECAM 236 Table 30.28 AGC Characteristics Input Sync Signal Level Output Sync Signal Level 0 or more [dB] Increased in proportion to input level 8.52 to 0 [dB] Reference amplitude (variable) ± acceptable error (variable) 8.52 or less [dB] Decreased in proportion to input level [IRE] Output signal 70 40 Standard sync amplitude (p-p): 40 [IRE] 0 0 15 40 70 [IRE] Input signal Figure 30.22 AGC Characteristics (Sync Signal Amplitude Reference) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1783 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.31 AGC Control Register 2 (AGCCR2) Bit: 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 0           Initial value: 1 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W R R R R R R R R AGCPRECIS[5:0] Bit Bit Name Initial Value R/W Description 15, 14  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 13 to 8 7 AGCPRECIS 001010 [5:0] R/W  R 0 AGC Gain Adjustment Accuracy Set acceptable error level for sync pulse amplitude after AGC adjustment by 1 LSB of 10-bit accuracy. Reserved This bit is always read as 0. The write value should always be 0.  6 1 R Reserved This bit is always read as 1. The write value should always be 1. 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (1) AGC Acceptable Error Range Control AGCPRECIS controls the acceptable error range of the output sync signal amplitude based on AGCLEVEL (target value). If AGCLEVEL = 236 and AGCPRECIS = 10, AGC gain is fixed within the following range: (236  10) < Output sync signal amplitude < (236 + 10) In this case, the PGA gain can fall within a 2-step range. For video image with stabilized sync signal amplitude, AGCPRECIS = 4 is recommended, which enables the PGA gain to fall within a 1-step range, when the electric field is strong. For the above setting, the recommended value is 10 to avoid hunting in a weak electric field. Page 1784 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.32 Peak Limiter Control Register (PKLIMTCR) Bit: 15 14 PEAKLEVEL[1:0] Initial value: 0 R/W: R/W 13 12 PEAKATTACK [1:0] 11 9 10 PEAKRELEASE [1:0] 7 8 5 6 PEAKRATIO [1:0] 4 3 2 0 1 MAXPEAKSAMPLES[7:0] 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 15, 14 PEAKLEVEL [1:0] Initial Value R/W Description 00 R/W Peak Luminance Value to Operate Peak Limiter (video signal level) 0: Limiter OFF 1: 1008 LSB 2: 992 LSB 3: 960 LSB Peak limiter is not operated if AGC is OFF irrespective of PEAKLEVEL value. 13, 12 PEAKATTACK [1:0] 10 R/W Response Speed with Peak Limiter Gain Decreased The larger value makes the response faster. 11, 10 PEAKRELEASE [1:0] 00 R/W Response Speed with Peak Limiter Gain Increased The larger value makes the response faster. 9, 8 PEAKRATIO[1:0] 00 R/W Maximum Compression Rate of Peak Limiter 0: Compressed up to 50% 1: Compressed up to 25% 2: Compressed up to 12.5% 3: Compressed up to 0% 7 to 0 MAXPEAK SAMPLES[7:0] 00000000 R/W Allowable Number of Overflowing Pixels Set a value by 1024 pixels. Exceeding this value will start peak limiter operation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1785 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (1) Peak Limiter Level Control PEAKLEVEL controls the peak luminance limited by the peak limiter. If the number of pixels counted exceeds the value set in PEAKLEVEL and there exist pixels more than the value set in MAXPEAKSAMPLES, the peak limiter function is activated to reduce the gain. Table 30.29 Peak Limiter Level Control PEAKLEVEL Output Sync Signal Level 0 Limiter OFF 1 Peak limiter is activated at 1008 LSB 2 Peak limiter is activated at 992 LSB 3 Peak limiter is activated at 960 LSB (2) Peak Limiter Response Speed Control PEAKATTACK controls the response speed when the peak limiter gain is reduced. The larger value makes the response faster. (3) Peak Limiter Response Speed Control PEAKRELEASE controls the response speed when the peak limiter gain is increased. The larger value makes the response faster. (4) Peak Limiter Gain Down Control PEAKRATIO sets the maximum compression rate of the peak limiter. Specifically, PEAKRATIO controls the amount of gain reduction (compression ratio) using the peak limiter function. Page 1786 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.30 Peak Limiter Gain Down Control PEAKRATIO Output Sync Signal Level 0 Compressed up to 50% 1 Compressed up to 25% 2 Compressed up to 12.5% 3 Compressed up to 0% (5) Peak Limiter Determination Control MAXPEAKSAMPLES controls the number of overflowing pixels allowed. If the number of pixels counted during the vertical active period exceeds the value set in PEAKLEVEL and there exist pixels more than the value set in MAXPEAKSAMPLES, the peak limiter function is activated to reduce the gain. The maximum allowable value is obtained by MAXPEAKSAMPLES  1024. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1787 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.33 Over-Range Control Register 1 (RGORCR1) Bit: 15 14 13 12 11 10       9 7 8 5 6 4 2 3 0 1 RADJ_O_LEVEL0[9:0] Initial value: 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) RADJ_O_ LEVEL0 [9:0] 11111111 R/W 11 A/D Over-Threshold Level (Between levels 0 and 1) Level 0 (normal) to level 3 (completely over the range) are available. A/D Over-Threshold Level (Between Levels 0 and 1) Control RADJ_O_LEVEL0 controls the A/D over-threshold level (between levels 0 and 1). Figure 30.23 shows the register values and threshold levels. 3 Value for detecting an overflow RADJ_O_LEVEL2 2 RADJ_O_LEVEL1 1 RADJ_O_LEVEL0 0 0 Value for detecting an underflow RADJ_U_LEVEL2 1 RADJ_U_LEVEL1 2 RADJ_U_LEVEL0 3 Figure 30.23 Over-Range Determination Areas Page 1788 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.34 Over-Range Control Register 2 (RGORCR2) Bit: 15 14 13 12 11 10       9 7 8 6 4 5 3 2 0 1 RADJ_U_LEVEL0[9:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) RADJ_U_ LEVEL0 [9:0] 00000000 R/W 00 A/D Under-Threshold Level (Between levels 2 and 3) Level 0 (normal) to level 3 (completely under the range) are available. A/D Under-Threshold Level (Between Levels 2 and 3) Control RADJ_U_LEVEL0 controls the A/D under-threshold level (between levels 2 and 3). For the register values and threshold levels, see section 30.4.33, Over-Range Control Register 1 (RGORCR1). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1789 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.35 Over-Range Control Register 3 (RGORCR3) Bit: 15 14 13 12 11 10       9 7 8 6 5 4 2 3 0 1 RADJ_O_LEVEL1[9:0] Initial value: 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) RADJ_O_ LEVEL1 [9:0] 11111111 R/W 11 A/D Over-Threshold Level (Between levels 1 and 2) Level 0 (normal) to level 3 (completely over the range) are available. A/D Over-Threshold Level (Between Levels 1 and 2) Control RADJ_O_LEVEL1 controls the A/D over-threshold level (between levels 1 and 2). For the register values and threshold levels, see section 30.4.33, Over-Range Control Register 1 (RGORCR1). Page 1790 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.36 Over-Range Control Register 4 (RGORCR4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RADJ_U_LEVEL1[9:0] Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) RADJ_U_ LEVEL1 [9:0] 00000000 R/W 00 A/D Under-Threshold Level (Between levels 1 and 2) Level 0 (normal) to level 3 (completely under the range) are available. A/D Under -Threshold Level (Between Levels 1 and 2) Control RADJ_U_LEVEL1 controls the A/D under-threshold level (between levels 1 and 2). For the register values and threshold levels, see section 30.4.33, Over-Range Control Register 1 (RGORCR1). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1791 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.37 Over-Range Control Register 5 (RGORCR5) Bit: 6 5 4 2 3 0 1 9 8 7 0 1 1 1 1 1 1 1 1 1 1 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10       Initial value: 0 0 0 0 0 R/W: R R R R R RADJ_O_LEVEL2[9:0] Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) RADJ_O_ LEVEL2 [9:0] 11111111 R/W 11 A/D Over-Threshold Level (Between levels 2 and 3) Level 0 (normal) to level 3 (completely over the range) are available. A/D Over-Threshold Level (Between Levels 2 and 3) Control RADJ_O_LEVEL2 controls the A/D over-threshold level (between levels 2 and 3). For the register values and threshold levels, see section 30.4.33, Over-Range Control Register 1 (RGORCR1). Page 1792 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.38 Over-Range Control Register 6 (RGORCR6) Bit: 4 5 3 2 0 1 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10       Initial value: 0 0 0 0 0 R/W: R R R R R RADJ_U_LEVEL2[9:0] Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) RADJ_U_ LEVEL2 [9:0] 00000000 R/W 00 A/D Under-Threshold Level (Between levels 0 and 1) Level 0 (normal) to level 3 (completely under the range) are available. A/D Under-Threshold Level (Between Levels 0 and 1) Control RADJ_U_LEVEL2 controls the A/D under-threshold level (between levels 0 and 1). For the register values and threshold levels, see section 30.4.33, Over-Range Control Register 1 (RGORCR1). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1793 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.39 Over-Range Control Register 7 (RGORCR7) Bit: 12 13 15 14  TEST_MONI[2:0] 10 11 9 RADJ_MIX_K_FIX[2:0] 8 7 6 5 4 3 2       UCMP _SW 0 1 DCMP HWIDE _SW _SW Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R/W R/W R/W R/W R/W R/W R R R R R R R/W R/W R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 TEST_ MONI[2:0] 000 R/W Test Mode 0 to 3: Normal operation 4: Level 0 part is output as black. 5: Level 1 part is output as black. 6: Level 2 part is output as black. 7: Level 3 part is output as black. 11 to 9 RADJ_MIX_ 000 K_FIX[2:0] R/W Forced Range Over/Under Mode 0 to 3: Auto detection 4: Level 0 (normal state) 5: Fixed to level 1 (almost normal) 6: Fixed to level 2 (almost over the range) 7: Fixed to level 3 (completely over the range) 8 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 UCMP_SW 0 R/W Over-Range Detection Enable 0: Disables over-range detection 1: Enables over-range detection 1 DCMP_SW 0 R/W Under-Range Detection Enable 0: Disables under-range detection 1: Enables under-range detection 0 HWIDE_SW 1 R/W Horizontal Enlargement of Over/Under-Range Level 0: Does not provide horizontal enlargement 1: Provides horizontal enlargement Page 1794 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Over-Range Test Control TEST_MONI controls the over-range test. (2) Forced Over/Under-Range Mode Control RADJ_MIX_K_FIX controls the forced over-/under-range detection. (3) Over-Range Detection Control UCMP_SW enables the over-range detection. (4) Under-Range Detection Control DCMP_SW enables the under-range detection. (5) Horizontal Enlargement at Over/Under-Range Level HWIDE_SW controls the horizontal enlargement of the over/under-range level. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1795 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.40 Feedback Control Register for Horizontal AFC Phase Comparator (AFCPFCR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3  2 1 0            PHDET _FIX Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 R/W: R R R R R R R R R R R R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 5  All 0 R Reserved PHDET_DIV[2:0] These bits are always read as 0. The write value should always be 0. 4 PHDET_FIX 0 R/W Forcible or LOWGAIN Control 0: LOWGAIN determination result used 1: Forcibly controlled (adjusted with PHDET_DIV) 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PHDET_DIV 101 [2:0] R/W Phase Comparator Feedback Adjust for Low Sync Signal Lock Stability 0: 1/1 1: 1/2 2: 1/4 3: 1/8 4: 1/16 5: 1/32 6 and 7: Setting prohibited Page 1796 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Phase Comparator Feedback Adjust PHDET_DEV adjusts the feedback amount as the phase comparison result when the lock stability is low. The greater the denominator is, the slower the reaction speed to the signal is. 1/1 (with limitation) LOWGAIN PHDET_FIX 0 1/2 1/4 D - 1 0 0 1 - 1/8 1/16 1/32 PHDET_DIV[2:0] "000" LOWGAIN PHDET_FIX 5 1 0 PHDET_DIV [2:0] 0 1 2 3 4 5 0 1 2 3 4 5 Output 1/1 1/2 1/4 1/8 1/16 1/32 1/1 1/1 1/2 1/4 1/8 1/16 1/32 Figure 30.24 Phase Comparator Feedback Adjust R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1797 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.41 Register Update Enable Register (RUPDCR) Bit: Initial value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEWSE TTING                0 R/W: R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R Initial Value Bit Bit Name 15 NEWSETTING 0 R/W Description R/W V Update Enable for TGCR1 to TGCR3 1: Enables update. 0: Disables update. 14 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (1) V Update Enable for TGCR1 to TGCR3 NEWSETTING enables/disables TGCR1 to TGCR3 to execute V update. Page 1798 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.42 Sync Separation Status/Vertical Cycle Read Register (VSYNCSR) Bit: 15 14 12 13 11 10 9 8 7 6 4 5 FHCOU FHLOCK ISNOISY FHMODE NOSIGN FVLOCK FVMOD INTERL NT[0] AL E ACED 3 2 1 0 FVCOUNT[7:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15 FHCOUNT[0] 0 R Horizontal AFC Oscillation Cycle (bit 0) 14 FHLOCK 0 R Horizontal AFC Lock Detection Result Set a value by 1/64 of 27-MHz clock. 0: Unlocked 1: Locked 13 ISNOISY 0 R Detection Result of Low S/N Signal by Sync Separation 0: Not low S/N signal 1: Low S/N signal 12 FHMODE 0 R Speed Detection Result 0: Normal speed (525i/625i, etc.) 1: Multiplied speed (525p/625p, etc.) 11 NOSIGNAL 0 R No-Signal Detection Result 0: Vertical sync signal detected 1: No vertical sync signal detected 10 FVLOCK 0 R Vertical Countdown Lock Detection Result 0: Unlocked 1: Locked 9 FVMODE 0 R Vertical Countdown Oscillation Mode 0: 50Hz 1: 60Hz 8 INTERLACED 0 R Interlace Detection Result 0: Progressive 1: Interlace 7 to 0 FVCOUNT[7:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00000000 R Vertical Cycle Measurement Result (in 0.1-ms units) Page 1799 of 3092 Section 30 Digital Video Decoder (1) SH7268 Group, SH7269 Group Horizontal AFC Oscillation Cycle Read FHCOUNT indicates bit 0 of the horizontal AFC oscillation cycle. (2) Horizontal AFC Lock Detection Result Read FHLOCK indicates the horizontal AFC lock detection result. (3) Sync Separation Low S/N Signal Detection Result Read ISNOISY indicates the detection result of low S/N signal by sync separation. (4) Speed Detection Result Read FHMODE indicates the speed detection result. (5) No-Signal Detection Result Read NOSIGNAL indicates the no-signal detection result. (6) Vertical Countdown Lock Detection Result Read FVLOCK indicates the vertical countdown lock detection result. (7) Interlace Detection Result Read INTERFACED indicates the interlace detection result. (8) Vertical Cycle Measurement Result Read FVCOUNT indicates the vertical cycle measurement result. Page 1800 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.43 Horizontal Cycle Read Register (HSYNCSR) Bit: 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 0 FHCOUNT[16:1] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name 15 to 0 FHCOUNT [16:1] (1) Initial Value R/W Description H'0000 R Horizontal AFC Oscillation Cycle (bit 16 to bit 1) Set a value by 1/64 of 27-MHz clock. Horizontal AFC Oscillation Cycle Read FHCOUNT indicates the upper bits of the horizontal AFC oscillation cycle. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1801 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.44 Digital Clamp Read Register 1 (DCPSR1) Bit: 15 Initial value: 0 0 0 0 R/W: R R R R 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R CLAMPLEVEL_CB[5:0] Initial Value Bit Bit Name 15 to 10 CLAMPLEV 000000 EL_CB[5:0] 5 4 3 2 1 0 CLAMPLEVEL_Y[9:0] R/W Description R Digital Clamp Subtraction Value (Cb signal) Offset from the reference black level Set a value in 1-LSB units. 2s complement 9 to 0 CLAMPLEV 00000000 R EL_Y[9:0] 00 Digital Clamp Subtraction Value (Y signal) Offset from the reference black level Set a value in 1-LSB units. 2s complement (1) Reading Digital Clamp Subtraction Value of Cb Signal CLAMPLEVEL_CB indicates the digital clamp subtraction value of Cb signal. (2) Reading Digital Clamp Subtraction Value of Y in Composite Signal CLAMPLEVEL_Y indicates the digital clamp subtraction value of Y signal. Page 1802 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.45 Digital Clamp Read Register 2 (DCPSR2) Bit: 15 14 13 12 10 11 CLAMPLEVEL_CR[5:0] 9 8 7 6 5 4 3 2 1 0           Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Initial Value Bit Bit Name 15 to 10 CLAMPLEV 000000 EL_CR[5:0] R/W Description R Digital Clamp Subtraction Value (Cr signal) Offset from the reference black level Set a value in 1-LSB units. 2s complement 9 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (1) Reading Digital Clamp Subtraction Value of Cr Signal CLAMPLEVEL_CR indicates the digital clamp subtraction value of Cr signal. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1803 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.46 Noise Detection Read Register (NSDSR) Bit: 15 14 13 12 11 10 9 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R 8 7 6 5 4 3 2 1 0 ACFSTRENGTH[15:0] Initial Value Bit Bit Name 15 to 0 ACFSTREN H'0000 GTH[15:0] R/W Description R Noise Autocorrelation Strength at Digital Clamp Pulse Position (normal pedestal position) When ACFLAGTIME = 0, ACFSTRENGTH almost corresponds to the noise power. Square root and logarithm of detection result almost correspond to noise amplitude and S/N (relative value), respectively. (1) Reading Noise Autocorrelation Strength at Digital Clamp Pulse Position ACFSTRENGTH indicates the noise correlation strength at the digital clamp pulse position (normal pedestal position). Page 1804 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.47 Chroma Decoding Read Register 1 (CROMASR1) Bit: 15 14 10 12 11 FSC LOCK NO BURST 13 FSC COLORSYS[1:0] MODE 9 7 8 6 ACCSUBGAIN [1:0] 5 4 3 2 1 0 ACCMAINGAIN[8:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Initial Value Bit Bit Name 15, 14 COLORSYS 00 [1:0] R/W Description R Color System Detection Result 0: NTSC 1: PAL 2: SECAM 3: Undetectable 13 FSCMODE 0 R Color Sub-Carrier Frequency Detection Result 0: 3.58 MHz 1: 4.43 MHz 12 FSCLOCK 0 R Burst Lock PLL Lock State Detection Result 0: Unlocked 1: Locked 11 NOBURST 0 R Color Burst Detection Result 0: Color burst present 1: No color burst present 10, 9 ACCSUB GAIN[1:0] 00 R Current ACC Gain Value (Sub) 0: 1 time 1: 2 times 2: 4 times 3: 8 times 8 to 0 ACCMAIN GAIN[8:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00000000 R 0 Current ACC gain value (Main) The value 256 corresponds to 1 time. Page 1805 of 3092 Section 30 Digital Video Decoder (1) SH7268 Group, SH7269 Group Color System Detection Result Read COLORSYS indicates the color system detection result. (2) Color Sub-Carrier Frequency Detection Result Read FSCMODE indicates the color sub-carrier frequency detection result. (3) Burst Lock PLL Lock State Detection Result Read FSCLOCK indicates the lock state detection result of the burst lock PLL. (4) Color Burst Detection Result Read NOBURST indicates the color burst detection result. (5) Current ACC Gain (Sub) Value Read ACCSUBGAIN indicates the current ACC gain (sub) value. (6) Current ACC Gain (Main) Value Read ACCMAINGAIN indicates the current ACC gain (main) value. Page 1806 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.48 Chroma Decode Read Register 2 (CROMASR2) Bit: 15 14 13 12    ISSE CAM 10 11 ISPAL ISNTSC 9 8   7 6 4 5 3 2 1 0 LOCKLEVEL[7:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 ISSECAM 0 R SECAM Detection Result 0: Not SECAM signal 1: SECAM signal 11 ISPAL 0 R PAL Detection Result 0: Not PAL signal 1: PAL signal 10 ISNTSC 0 R NTSC Detection Result 0: Not NTSC signal 1: NTSC signal  9, 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 (1) LOCKLEVEL 00000000 R [7:0] Low S/N Signal Detection Result by Burst Lock PLL The larger value corresponds to a higher S/N. SECAM Signal Detection Result Read ISSECAM indicates the SECAM signal detection result. (2) PAL Signal Detection Result Read ISPAL indicates the PAL signal detection result. (3) NTSC Signal Detection Result Read ISNTSC indicates the NTSC signal detection result. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1807 of 3092 Section 30 Digital Video Decoder (4) SH7268 Group, SH7269 Group Read of Low S/N Signal Detection Result by Burst Lock PLL LOCKLEVEL indicates the low S/N signal detection result by the burst lock PLL. Page 1808 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.49 Sync Separation Read Register (SYNCSSR) Bit: 15 14 13 12 11 10    ISREDU CED   9 8 7 5 6 4 3 2 1 0 SYNCDEPTH[9:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Initial Bit Name Value Bit 15 to 13  All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 12 ISREDUC 0 ED R Sync Amplitude Detection Result during VBI Period 0: Amplitude is larger than that in image active period. 1: Amplitude is equal to that in image active period. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) SYNCDE 000000 R PTH[9:0] 0000 Sync Pulse Amplitude Detection Result Reading Sync Amplitude Detection Result during VBI Period ISREDUCED indicates the sync amplitude detection result during VBI period. (2) Reading Sync Pulse Level Amplitude Detection Result SYNCDEPTH indicates the sync pulse amplitude detection result. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1809 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.50 AGC Control Read Register 1 (AGCCSR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 HIGHSAMPLES[7:0] 4 3 2 1 0 PEAKSAMPLES[7:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Initial Value Bit Bit Name R/W 15 to 8 HIGHSAMP 00000000 R LES[7:0] Description Number of Pixels Which Have Larger Luminance Value Than Peak Luminance Limited by Peak Limiter Indicated by 1024 pixels 7 to 0 (1) PEAKSAMP 00000000 R LES[7:0] Number of Overflowing Pixels Indicated by 1024 pixels Reading Number of Pixels Which Have Larger Luminance Value Than Peak Luminance Limited by Peak Limiter HIGHSAMPLES indicates the number of pixels which have larger luminance value than the peak luminance limited by the peak limiter. (2) Number of Overflowing Pixels PEAKSAMPLES indicates the number of overflowing pixels. Page 1810 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.51 AGC Control Read Register 2 (AGCCSR2) Bit: 15 14 13 12 11 10 9 8        AGCCON VERGE 7 6 5 4 3 2 1 0 AGCGAIN[7:0] Initial value: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 AGCCONV 0 ERGE R AGC Convergence Detection Result 0: Not converged 1: Converged 7 to 0 (1) AGCGAIN [7:0] 01000000 R Current AGC Gain Value The value 64 corresponds to ×1. Reading AGC Convergence Detection Result AGCCONVERGE indicates the AGC convergence detection result. (2) Reading Current AGC Gain AGCGAIN indicates the current AGC gain. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1811 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.52 Y/C Separation Control Register 3 (YCSCR3) Bit: 15 14 12 13 11 10 Initial value: 0 R/W: R/W 9 8 7 6 5 3 4 K13[5:0] K15[3:0] 2 1 0 K11[5:0] 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 12 K15[3:0] 0010 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the horizontal BPF is applied to the narrower range. 11 to 6 K13[5:0] 001000 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the horizontal BPF is applied to the narrower range. 5 to 0 K11[5:0] 000100 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the horizontal BPF is applied to the narrower range. (1) Two-Dimensional Y/C Separation Filter Select Coefficient Control K15 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (2) Two-Dimensional Y/C Separation Filter Select Coefficient Control K13 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (3) Two-Dimensional Y/C Separation Filter Select Coefficient Control K11 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. Page 1812 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.53 Y/C Separation Control Register 4 (YCSCR4) Bit: 15 14 Initial value: 0 0 R/W 13 12 11 10 9 1 1 0 1 0 R/W R/W R/W R/W R/W K16[3:0] R/W: R/W 8 7 6 5 4 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W K14[5:0] 3 2 1 0 K12[5:0] Bit Bit Name Initial Value R/W Description 15 to 12 K16[3:0] 0011 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the horizontal BPF is applied to the narrower range. 11 to 6 K14[5:0] 010000 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the horizontal BPF is applied to the narrower range. 5 to 0 K12[5:0] 000001 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the horizontal BPF is applied to the narrower range. (1) Two-Dimensional Y/C Separation Filter Select Coefficient Control K16 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (2) Two-Dimensional Y/C Separation Filter Select Coefficient Control K14 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (3) Two-Dimensional Y/C Separation Filter Select Coefficient Control K12 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1813 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.54 Y/C Separation Control Register 5 (YCSCR5) Bit: 15 14 12 13 10 11 9 8 K22A[7:0] Initial value: 0 R/W: R/W 7 6   5 3 4 2 0 1 K21A[5:0] 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 15 to 8 K22A[7:0] 01000000 R/W R/W Description Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the narrower range.  7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 K21A[5:0] 000110 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the narrower range. (1) Two-Dimensional Y/C Separation Filter Select Coefficient Control K22A controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (2) Two-Dimensional Y/C Separation Filter Select Coefficient Control K21A controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. Page 1814 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.55 Y/C Separation Control Register 6 (YCSCR6) Bit: 15 14 13 12 11 10 9 8 K22B[7:0] Initial value: 0 R/W: R/W 7 6   5 4 3 2 1 0 K21B[5:0] 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 15 to 8 K22B[7:0] 00010000 R/W R/W Description Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the narrower range.  7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 K21B[5:0] 000110 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the narrower range. (1) Two-Dimensional Y/C Separation Filter Select Coefficient Control K22B controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (2) Two-Dimensional Y/C Separation Filter Select Coefficient Control K21B controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1815 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.56 Y/C Separation Control Register 7 (YCSCR7) Bit: 15 14 12 13 10 11 K23B[3:0] Initial value: 0 R/W: R/W 9 8 K23A[3:0] 7 6 5    3 4 2 0 1 K24[4:0] 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 12 K23B[3:0] 0110 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the narrower range. 11 to 8 K23A[3:0] 0011 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the narrower range.  7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0.  5 1 R Reserved These bits are always read as 1. The write value should always be 1. 4 to 0 K24[4:0] 00101 R/W Two-Dimensional Y/C Separation Filter Select Coefficient As the value becomes larger, the vertical BPF is applied to the wider range. (1) Two-Dimensional Y/C Separation Filter Select Coefficient Control K23B controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. (2) Two-Dimensional Y/C Separation Filter Select Coefficient Control K23A controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. Page 1816 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 30 Digital Video Decoder Two-Dimensional Y/C Separation Filter Select Coefficient Control K24 controls the two-dimensional Y/C separation filter select coefficient. For details, refer to section 30.5.5 (3), Horizontal and Vertical Correlation Detection Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1817 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.57 Y/C Separation Control Register 8 (YCSCR8) In two-dimensional Y/C separation, horizontal BPF, vertical BPF, and horizontal/vertical BPF are adaptively switched. For the horizontal BPF and horizontal/vertical BPF, horizontal properties can be selected. Bit: 15 14 13 12 11 HBPF_ HVBPF_ HBPF1_9 HVBPF1_ HFIL_ NARROW NARROW TAP_ON 9TAP_ON TAP_SEL Initial value: 1 1 R/W: R/W R/W 0 9 8 7 6 5 4 3 2 1 0            0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R 0 R/W R/W 10 Bit Bit Name Initial Value R/W 15 HBPF_NARROW 1 R/W Description Latter-Stage Horizontal BPF Select 0: Bypass 1: 17 TAP 14 HVBPF_NARROW 1 R/W Latter-Stage Horizontal/Vertical BPF Select 0: Bypass 1: 17 TAP 13 HBPF1_9TAP_ON 0 R/W Former-Stage Horizontal BPF Select (when adaptively selected) 0: 17 TAP 1: 9 TAP 12 HVBPF1_9TAP_ON 0 R/W Former-Stage Horizontal/Vertical BPF Select 0: 17 TAP 1: 9 TAP 11 HFIL_TAP_SEL 0 R/W Horizontal Filter and Horizontal/Vertical Filter Bandwidth Switch Signal 0: 17 TAP 1: 9 TAP 10 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1818 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Horizontal BPF Select Control HBPF_NARROW selects the latter-stage horizontal BPF. For details, refer to section 30.5.5 (2), Horizontal and Vertical Filter Block. (2) Horizontal/Vertical BPF Select Control HVBPF_NARROW selects the latter-stage horizontal/vertical BPF. For details, refer to section 30.5.5 (2), Horizontal and Vertical Filter Block. (3) Horizontal BPF (Broadband) Select Control HBPF1_9TAP_ON selects the former-stage horizontal BPF. For details, refer to section 30.5.5 (2), Horizontal and Vertical Filter Block. (4) Horizontal/Vertical BPF (Broadband) Select Control HVBPF1_9TAP_ON selects the former-stage horizontal/vertical BPF. For details, refer to section 30.5.5 (2), Horizontal and Vertical Filter Block. (5) Horizontal BPF Bandwidth Switch Control HFIL_TAP_SEL switches the horizontal BPF bandwidths used for mixing. For details, refer to section 30.5.5 (5), Horizontal and Vertical Signal Mixing Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1819 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.58 Y/C Separation Control Register 9 (YCSCR9) Bit: Initial value: 15 14 13 12 DET2_ ON    1 0 0 0 0 0 R R R R/W R/W R/W: R/W 11 10 9 8 7 0 0 0 0 R/W R/W R/W R/W HSEL_MIX_Y[3:0] 6 5 4 3 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W VSEL_MIX_Y[3:0] 2 1 0 HVSEL_MIX_Y[3:0] Bit Bit Name Initial Value R/W Description 15 DET2_ON 1 R/W Two-Dimensional Filter Mixing Select 0: Signals are not mixed after passing the correlation detection filter. 1: Signals are mixed after passing the correlation detection filter. 14 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 8 HSEL_MIX_ 0000 Y[3:0] R/W Mixing Ratio of Signal after Passing Horizontal Filter to Signal after Passing Former-Stage Horizontal Filter 0: Horizontal filter 100.0% 1: Horizontal filter 87.5% to former-stage horizontal filter 12.5% 2: Horizontal filter 75.0% to former-stage horizontal filter 25.0% 3: Horizontal filter 62.5% to former-stage horizontal filter 37.5% 4: Horizontal filter 50.0% to former-stage horizontal filter 50.0% 5: Horizontal filter 37.5% to former-stage horizontal filter 62.5% 6: Horizontal filter 25.0% to former-stage horizontal filter 75.0% 7: Horizontal filter 12.5% to former-stage horizontal filter 87.5% 8: Former-stage horizontal filter 100% 9 to 15: Setting prohibited Page 1820 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Initial Value Bit Bit Name 7 to 4 VSEL_MIX_ 0000 Y[3:0] R/W Description R/W Mixing Ratio of Signal after Passing Vertical Filter to Signal after Passing Former-Stage Horizontal/Vertical Filter 0: Vertical filter 100.0% 1: Vertical filter 87.5% to former-stage horizontal/vertical filter 12.5% 2: Vertical filter 75.0% to former-stage horizontal/vertical filter 25.0% 3: Vertical filter 62.5% to former-stage horizontal/vertical filter 37.5% 4: Vertical filter 50.0% to former-stage horizontal/vertical filter 50.0% 5: Vertical filter 37.5% to former-stage horizontal/vertical filter 62.5% 6: Vertical filter 25.0% to former-stage horizontal/vertical filter 75.0% 7: Vertical filter 12.5% to former-stage horizontal/vertical filter 87.5% 8: Former-stage horizontal/vertical filter 100% 9 to 15: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1821 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Bit Bit Name 3 to 0 HVSEL_MI X_Y[3:0] Initial Value R/W Description 0000 R/W Mixing Ratio of Signal after Passing Horizontal/Vertical Filter to Signal after Passing Former-Stage Horizontal/Vertical Filter 0: Horizontal/vertical filter 100.0% 1: Horizontal/vertical filter 87.5% to former-stage horizontal/vertical filter 12.5% 2: Horizontal/vertical filter 75.0% to former-stage horizontal/vertical filter 25.0% 3: Horizontal/vertical filter 62.5% to former-stage horizontal/vertical filter 37.5% 4: Horizontal/vertical filter 50.0% to former-stage horizontal/vertical filter 50.0% 5: Horizontal/vertical filter 37.5% to former-stage horizontal/vertical filter 62.5% 6: Horizontal/vertical filter 25.0% to former-stage horizontal/vertical filter 75.0% 7: Horizontal/vertical filter 12.5% to former-stage horizontal/vertical filter 87.5% 8: Former-stage horizontal/vertical filter 100% 9 to 15: Setting prohibited (1) Two-Dimensional Filter Mixing Select Control DET2_ON selects two-dimensional filter mixing. For details, refer to section 30.5.5 (5), Horizontal and Vertical Signal Mixing Block. (2) Control of Mixing Ratio of Signal after Passing Horizontal Filter to Signal after Passing Former-Stage Horizontal Filter HSEL_MIX_Y controls the mixing ratio of the signal after passing a horizontal filter to the signal after passing the former-stage horizontal filter. For details, refer to section 30.5.5 (5), Horizontal and Vertical Signal Mixing Block. Page 1822 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 30 Digital Video Decoder Control of Mixing Ratio of Signal after Passing Vertical Filter to Signal after Passing Former-Stage Horizontal/Vertical Filter VSEL_MIX_Y controls the mixing ratio of the signal after passing a vertical filter to the signal after passing the former-stage horizontal/vertical filter. For details, refer to section 30.5.5 (5), Horizontal and Vertical Signal Mixing Block. (4) Control of Mixing Ratio of Signal after Passing Horizontal/Vertical Filter to Signal after Passing Former-Stage Horizontal/Vertical Filter HVSEL_MIX_Y controls the mixing ratio of the signal after passing a horizontal/vertical filter to the signal after passing the former-stage horizontal/vertical filter. For details, refer to section 30.5.5 (5), Horizontal and Vertical Signal Mixing Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1823 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.59 Y/C Separation Control Register 11 (YCSCR11) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1        Initial value: 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W V_Y_LEVEL[8:0] Bit Bit Name Initial Value R/W Description 15, 14  All 1 R Reserved These bits are always read as 1. The write value should always be 1.  13 0 R Reserved This bit is always read as 0. The write value should always be 0. 12, 11  All 1 R Reserved These bits are always read as 1. The write value should always be 1.  10, 9 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 to 0 V_Y_LEVEL 000000011 R/W [8:0] Vertical Luminance Detection Level for Correlation Detection Filter The luminance is detected when lower than the set value. (1) Vertical Luminance Detection Level for Correlation Detection Filter V_Y_LEVEL[8:0] select the vertical luminance detection level for correlation detection filter. Be sure to set 0 to all the bits in this field when this module is in use. Page 1824 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.60 Y/C Separation Control Register 12 (YCSCR12) During two-dimensional Y/C separation, the horizontal bandwidth can be further narrowed using the cascade horizontal BPF after horizontal BPF, vertical BPF, and horizontal/vertical BPF are switched. Bit: 14 15 13 12 11 DET2_MIX_C[3:0] Initial value: 0 R/W: R/W Bit 10 9 8 DET2_MIX_Y[3:0] 7 6 5 4     3 2 FIL2_MODE_2D [1:0] 1 0  FIL2_NAR ROW_2D 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R R/W Bit Name 15 to 12 DET2_MIX_C[3:0] Initial Value R/W Description 0000 R/W Mixing Ratio of C Signal after Passing Horizontal/Vertical Adaptive Filter to Signal after Passing Correlation Detection Filter (set 0 when DET2_ON = 0) 0: Horizontal/vertical adaptive filter 100.0% 1: Horizontal/vertical adaptive filter 87.5% to correlation detection filter 12.5% 2: Horizontal/vertical adaptive filter 75.0% to correlation detection filter 25.0% 3: Horizontal/vertical adaptive filter 62.5% to correlation detection filter 37.5% 4: Horizontal/vertical adaptive filter 50.0% to correlation detection filter 50.0% 5: Horizontal/vertical adaptive filter 37.5% to correlation detection filter 62.5% 6: Horizontal/vertical adaptive filter 25.0% to correlation detection filter 75.0% 7: Horizontal/vertical adaptive filter 12.5% to correlation detection filter 87.5% 8: Correlation detection filter 100% 9 to 15: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1825 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Bit Bit Name Initial Value R/W Description 11 to 8 DET2_MIX_Y[3:0] 0110 R/W Mixing Ratio of C Signal for Y Generation after Passing Horizontal/Vertical Adaptive Filter to Signal after Passing Correlation Detection Filter (set 0 when DET2_ON = 0) 0: Horizontal/vertical adaptive filter 100.0% 1: Horizontal/vertical adaptive filter 87.5% to correlation detection filter 12.5% 2: Horizontal/vertical adaptive filter 75.0% to correlation detection filter 25.0% 3: Horizontal/vertical adaptive filter 62.5% to correlation detection filter 37.5% 4: Horizontal/vertical adaptive filter 50.0% to correlation detection filter 50.0% 5: Horizontal/vertical adaptive filter 37.5% to correlation detection filter 62.5% 6: Horizontal/vertical adaptive filter 25.0% to correlation detection filter 75.0% 7: Horizontal/vertical adaptive filter 12.5% to correlation detection filter 87.5% 8: Correlation detection filter 100% 9 to 15: Setting prohibited 7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3, 2 FIL2_MODE_2D[1:0] 01 R/W Two-Dimensional Cascade/TAKE-OFF Filter Mode Select 0: Bypass 1: Cascade filter 2: TAKE-OFF filter 3: Setting prohibited 1  0 R Reserved This bit is always read as 0. The write value should always be 0. 0 FIL2_NARROW_2D 1 R/W Two-Dimensional Cascade Filter Select 0: Bypass 1: 17 TAP Page 1826 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Mixing Ratio of C Signal after Passing Horizontal/Vertical Adaptive Filter to Signal after Passing Correlation Detection Filter DET2_MIX_C controls the mixing ratio of the chroma signal (after adaptation) to the signal after passing the correlation detection filter. For details, refer to section 30.5.5 (6), Correlation Detection Value Mixing Block. (2) Mixing Ratio of C Signal for Y Generation after Passing Horizontal/Vertical Adaptive Filter to Signal after Passing Correlation Detection Filter For details, refer to section 30.5.5 (6), Correlation Detection Value Mixing Block. (3) Two-Dimensional Cascade/TAKE-OFF Filter Mode Select FIL2_MODE_2D selects the two-dimensional cascade/TAKE-OFF filter mode. For details, refer to section 30.5.5 (8), Cascade Filter Block. (4) Two-Dimensional Cascade Filter Select FIL2_NARROW_2D selects the two-dimensional cascade filter. For details, refer to section 30.5.5 (8), Cascade Filter Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1827 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.61 Digital Clamp Control Register 9 (DCPCR9) Bit: 15 14 13 12 11 10 CLP_HOL CLP_HOL CLP_HOL D_ON_Y D_ON_CB D_ON_CR 9 8 7 6 5 4 3 2 1 0              Initial value: 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 13  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 12 CLP_HOLD 1 _ON_Y R/W CLP_HOLD 1 _ON_CB R/W Clamp Data Hold Processing ON/OFF (Y) 0: Hold processing ON 1: Hold processing OFF 11 Clamp Data Hold Processing ON/OFF (Cb) 0: Hold processing ON 1: Hold processing OFF 10 CLP_HOLD 1 _ON_CR R/W Clamp Data Hold Processing ON/OFF (Cr) 0: Hold processing ON 1: Hold processing OFF 9 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (1) Clamp Data Hold Processing ON/OFF Control (Y) CLP_HOLD_ON_Y selects ON/OFF of hold processing for Y signal clamp data. Be sure to set 0 to this bit when this module is in use. (2) Clamp Data Hold Processing ON/OFF Control (Cb) CLP_HOLD_ON_CB selects ON/OFF of hold processing for Cb signal clamp data. Be sure to set 0 to this bit when this module is in use. Page 1828 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 30 Digital Video Decoder Clamp Data Hold Processing ON/OFF Control (Cr) CLP_HOLD_ON_CR selects ON/OFF of hold processing for Cr signal clamp data. Be sure to set 0 to this bit when this module is in use. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1829 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.62 Chroma Filter TAP Coefficient (WA_F0 to WA_F8) Registers for Y/C Separation (YCTWA_F0 to YCTWA_F8) Bit: 15 14 13    12 11 10 9 8 7 6 5 4 3 2 1 0 FIL2_2D_WA_F0 to FIL2_2D_WA_F8[12:0] Initial value: 0 0 0 * * * * * * * * * * * * * R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 to 0 FIL2_2D_WA_F0 * to FIL2_2D_WA_F8 [12:0] R/W Two-Dimensional Cascade Broadband (3.58/4.43/SECAM-DR)/TAKE-OFF Filter TAP Coefficient 0 to 8 [12]: Sign [11:0]: Absolute value Note: * Initial values: FIL2_2D_WA_F0: H'0018 FIL2_2D_WA_F1: H'002C FIL2_2D_WA_F2: H'0014 FIL2_2D_WA_F3: H'1034 FIL2_2D_WA_F4: H'1080 FIL2_2D_WA_F5: H'1080 FIL2_2D_WA_F6: H'100C FIL2_2D_WA_F7: H'0084 FIL2_2D_WA_F8: H'00C8 Page 1830 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Two-Dimensional Cascade Broadband (3.58/4.43/SECAM-DR)/TAKE-OFF Filter TAP Coefficient 0 to 8 Control FIL2_2D_WA_F0 to FIL2_2D_WA_F8[12:0] control two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient 0 to 8. The transfer function is defined as follows: H(z) = {F0(z8 + z+8) + F1(z7 + z+7) + F2(z6 + z+6) + F3(z5 + z+5) + F4(z4 + z+4) + F5(z3 + z+3) + F6(z2 + z+2) + F0(z1 + z+1) + F8(z0)} /1024 The coefficient value is represented using the MSB for a sign and the other bits for the effective value in the absolute value. Table 30.31 TAP Coefficient Settings Most Significant Bit Other Than MSB Setting Value 0 0 to 4095 +0 to +4095 1 0 to 4095 0 to 4095 For the recommended setting value for each filter, see section 30.5.5 (8), Cascade Filter Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1831 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.63 Chroma Filter TAP Coefficient (WB_F0 to WB_F8) Registers for Y/C Separation (YCTWB_F0 to YCTWB_F8) Bit: 15 14 13    12 11 10 9 8 7 6 5 4 3 2 1 0 FIL2_2D_WB_F0 to FIL2_2D_WB_F8[12:0] Initial value: 0 0 0 * * * * * * * * * * * * * R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 to 0 FIL2_2D_W * B_F0 to FIL2_2D_W B_F8[12:0] R/W Two-Dimensional Cascade Broadband (SECAM-DB) Filter TAP Coefficient 0 to 8 [12]: Sign [11:0]: Absolute value Note: * Initial values: FIL2_2D_WB_F0: H'100C FIL2_2D_WB_F1: H'0028 FIL2_2D_WB_F2: H'003C FIL2_2D_WB_F3: H'000C FIL2_2D_WB_F4: H'1068 FIL2_2D_WB_F5: H'109C FIL2_2D_WB_F6: H'1040 FIL2_2D_WB_F7: H'0078 FIL2_2D_WB_F8: H'00D0 Page 1832 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Two-Dimensional Cascade Broadband (SECAM-DB) Filter TAP Coefficient 0 to 8 Control FIL2_2D_WB_F0 to FIL2_2D_WB_F8[12:0] control two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient 0 to 8. The transfer function is defined as follows: H(z) = {F0(z8 + z+8) + F1(z7 + z+7) + F2(z6 + z+6) + F3(z5 + z+5) + F4(z4 + z+4) + F5(z3 + z+3) + F6(z2 + z+2) + F0(z1 + z+1) + F8(z0)} /1024 The coefficient value is represented using the MSB for a sign and the other bits for the effective value in the absolute value. Table 30.32 TAP Coefficient Settings Most Significant Bit Other Than MSB Setting Value 0 0 to 4095 +0 to +4095 1 0 to 4095 0 to 4095 For the recommended setting value for each filter, see section 30.5.5 (8), Cascade Filter Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1833 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.64 Chroma Filter TAP Coefficient (NA_F0 to NA_F8) Registers for Y/C Separation (YCTNA_F0 to YCTNA_F8) Bit: 15 14 13    12 10 11 9 7 8 6 5 4 3 2 0 1 FIL2_2D_NA_F0 to FIL2_2D_NA_F8[12:0] Initial value: 0 0 0 * * * * * * * * * * * * * R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 to 0 FIL2_2D_N * A_F0 to FIL2_2D_N A_F8[12:0] R/W Two-Dimensional Cascade Narrowband (3.58/4.43/SECAM-DR) Filter TAP Coefficient 0 to 8 [12]: Sign [11:0]: Absolute value Note: * Initial values: FIL2_2D_NA_F0: H'0018 FIL2_2D_NA_F1: H'002C FIL2_2D_NA_F2: H'0014 FIL2_2D_NA_F3: H'1034 FIL2_2D_NA_F4: H'1080 FIL2_2D_NA_F5: H'1080 FIL2_2D_NA_F6: H'100C FIL2_2D_NA_F7: H'0084 FIL2_2D_NA_F8: H'00C8 Page 1834 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Two-Dimensional Cascade Narrowband (3.58/4.43/SECAM-DR) Filter TAP Coefficient 0 to 8 Control FIL2_2D_NA_F0 to FIL2_2D_NA_F8[12:0] control two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient 0 to 8. The transfer function is defined as follows: H(z) = {F0(z8 + z+8) + F1(z7 + z+7) + F2(z6 + z+6) + F3(z5 + z+5) + F4(z4 + z+4) + F5(z3 + z+3) + F6(z2 + z+2) + F0(z1 + z+1) + F8(z0)} /1024 The coefficient value is represented using the MSB for a sign and the other bits for the effective value in the absolute value. Table 30.33 TAP Coefficient Settings Most Significant Bit Other Than MSB Setting Value 0 0 to 4095 +0 to +4095 1 0 to 4095 0 to 4095 For the recommended setting value for each filter, see section 30.5.5 (8), Cascade Filter Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1835 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.65 Chroma Filter TAP Coefficient (NB_F0 to NB_F8) Registers for Y/C Separation (YCTNB_F0 to YCTNB_F8) Bit: 15 14 13    Initial value: 0 0 0 * * * * * * * * * * * * * R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 12 11 10 9 8 7 6 5 4 3 2 1 0 FIL2_2D_NB_F0 to FIL2_2D_NB_F8[12:0] Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 to 0 FIL2_2D_ * NB_F0 to FIL2_2D_N B_F8[12:0] R/W Two-Dimensional Cascade Narrowband (SECAMDB) Filter TAP Coefficient 0 to 8 [12]: Sign [11:0]: Absolute value Note: * Initial values: FIL2_2D_NB_F0: H'1438 FIL2_2D_NB_F1: H'0AF0 FIL2_2D_NB_F2: H'1CEC FIL2_2D_NB_F3: H'065C FIL2_2D_NB_F4: H'05A4 FIL2_2D_NB_F5: H'1CEC FIL2_2D_NB_F6: H'085C FIL2_2D_NB_F7: H'0178 FIL2_2D_NB_F8: H'1568 Page 1836 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 30 Digital Video Decoder Two-Dimensional Cascade Narrowband (SECAM-DB) Filter TAP Coefficient 0 to 8 Control FIL2_2D_NB_F0 to FIL2_2D_NB_F8[12:0] control two-dimensional cascade narrowband (SECAM-DB) filter TAP coefficient 0 to 8. The transfer function is defined as follows: H(z) = {F0(z8 + z+8) + F1(z7 + z+7) + F2(z6 + z+6) + F3(z5 + z+5) + F4(z4 + z+4) + F5(z3 + z+3) + F6(z2 + z+2) + F0(z1 + z+1) + F8(z0)} /1024 The coefficient value is represented using the MSB for a sign and the other bits for the effective value in the absolute value. Table 30.34 TAP Coefficient Settings Most Significant Bit Other Than MSB Setting Value 0 0 to 4095 +0 to +4095 1 0 to 4095 0 to 4095 For the recommended setting value for each filter, see section 30.5.5 (8), Cascade Filter Block. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1837 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.66 Luminance (Y) Signal Gain Control Register (YGAINCR) Bit: 15 14 13 12 11 10       9 8 7 6 5 4 3 2 1 0 Y_GAIN2[9:0] Initial value: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) Y_GAIN2 [9:0] 10000000 R/W 00 Y Signal Gain Coefficient (0 = 0 times, 512 = 1.0 times, 1023  2.0 times) Y Signal Output Gain Control Y_GAIN2 controls the Y signal output gain. Y signal output = Y signal after decoding  (Y_GAIN/512) Page 1838 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.67 Color Difference (Cb) Signal Gain Control Register (CBGAINCR) Bit: 15 14 13 12 11 10       Initial value: 0 0 0 0 0 R/W: R R R R R 9 8 7 6 0 1 0 0 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 CB_GAIN2[9:0] Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 CB_GAIN2 [9:0] (1) 10000000 R/W 00 Cb Signal Gain Coefficient (0 = 0 times, 512 = 1.0 times, 1023  2.0 times) Cb Signal Output Gain Control CB_GAIN2 controls the Cb signal output gain. Cb signal output = Cb signal after decoding  (CB_GAIN/512) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1839 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.68 Color Difference (Cr) Signal Gain Control Register (CRGAINCR) Bit: 15 14 13 12 11 10       9 8 7 6 5 4 3 2 1 0 CR_GAIN2[9:0] Initial value: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 (1) CR_GAIN2 10000000 R/W [9:0] 00 Cr Signal Gain Coefficient (0 = 0 times, 512 = 1.0 times, 1023  2.0 times) Cr Signal Output Gain Control CR_GAIN2 controls the Cr signal output gain. Cr signal output = Cr signal after decoding  (CR_GAIN/512) Page 1840 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.69 PGA Register Update (PGA_UPDATE) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1                Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGA_ VEN 1 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PGA_VEN 1 R/W PGACR Register V Update Enable 1: Enable 0: Disable (1) PGACR Register V Update Enable PGA_VEN enables or disables V update of PGACR register. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1841 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.70 PGA Control Register (PGACR) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    PGA_GAIN _SEL        Initial value: 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W R R R R R R R R PGA_GAIN[4:0] Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 PGA_GAIN 0 _SEL R/W PGA Switch 0: Automatic (AGC) 1: Manual (refer to the PGA_GAIN description below.) 12 to 8 PGA_GAIN 01000 [4:0] R/W PGA Gain 7 to 4  R Reserved All 0 0 (0.8 Vpp) to 31 (1.6 Vpp) These bits are always read as 0. The write value should always be 0.  3 1 R Reserved This bit is always read as 1. The write value should always be 1. 2 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: All the bits in this register are updated when the vertical sync signal is asserted with PGA_VEN in PGA_UPDATE being 1. (1) PGA Switch When PGA_GAIN_SEL is 0 and ADCCR1.AGCMODE is 1, the AGC-controlled value is reflected on the PGA gain. When PGA_GAIN_SEL is 1, the PGA_GAIN value is directly reflected on the PGA gain. In this case, the ADCCR1.AGCMODE setting is invalid. Setting ADCCR1.AGCMODE to 0 and PGA_GAIN_SEL to 0 simultaneously is prohibited. Page 1842 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 30 Digital Video Decoder PGA Gain When PGA_GAIN_SEL is 1, the PGA_GAIN value is reflected on the PGA gain. One of 32 levels of gain values can be set for the PGA of this LSI. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1843 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.4.71 ADC Control Register 2 (ADCCR2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0  ADC_ VINSEL               Initial value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0.  8 1 R Reserved This bit is always read as 1. The write value should always be 1. 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ADC_VINSEL 0 R/W Input Pin Control 0: VIN1 input 1: VIN2 input (1) Input Pin Control ADC_VINSEL selects the pin for inputting composite video signals. Page 1844 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.5 Operation 30.5.1 Overview Section 30 Digital Video Decoder This module decodes composite video signals (CVBS) and separates them into horizontal/vertical sync signals, luminance signals (Y), and color difference signals (Cb/Cr). Supported color systems are NTSC, PAL, and SECAM. This module consists of an A/D converter for video signal input, sync separator circuit, burst controlled oscillator (BCO), a Y/C separator circuit, a chroma decoding circuit, a digital clamp circuit, and an output gain adjustment circuit. Figure 30.25 shows an overall block diagram. This LSI A/D converter for video signal input BIAS VRT VRB Digital control Gain control Clamp VIN1 PGA Noise reduction LPF, Sync slicer, Horizontal AFC, Vertical count-down, AGC/peak limiter, Signal detection A/D VIN2 VDAVcc VDAVss HS, VS VE, HE Sync separation circuit VIDEO_X1 Crystal oscillator 27 MHz Color sub-carrier reproduction, Color system detection VIDEO_X2 BCO ACC gain, Color killer Color sub-carrier signal Color killer, Pedestal clamp, Color system ACC, Center clamp, TINT Noise detection correction, NTSC 2D C R-Y axis PAL 2D YCbCr correction YCbCr SECAM 1D Y Y/C separation circuit Chroma decoding circuit Digital clamp circuit Capturing position, Contrast adjustment, Color adjustment YCbCr (30 bits) Output adjustment circuit Figure 30.25 Overall Block Diagram (1) A/D Converter for Video Signal Input The A/D converter processes the composite video signal (CVBS) using the sync tip clamp block and the programmable gain amplifier (PGA) and A/D-converts the signal. The composite video signals from either VIN1 or VIN2 pin are selected. (2) Sync Separator Circuit The sync separator circuit extracts the horizontal and vertical sync signals from the composite video signal. This circuit also detects the amplitude of the sync signals and automatically adjusts the PGA gain (automatic gain control = AGC). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1845 of 3092 Section 30 Digital Video Decoder (3) SH7268 Group, SH7269 Group Burst Controlled Oscillator (BCO) The BCO extracts the color burst signal from the composite video signal and reproduces the color sub-carrier signal required for color demodulation. The BCO also acquires phase and frequency information from the color burst signal and detects the color system used. (4) Y/C Separator Circuit The Y/C separator circuit separates the composite video signal of the NTSC, PAL, or SECAM format into the Y and C signals. Two-dimensional adaptive separation is used for NTSC and PAL and one-dimensional separation for SECAM. (5) Chroma Decoding Circuit The chroma decoding circuit demodulates the C signal extracted by the Y/C separator circuit into the Cb/Cr signal. This circuit has the automatic color control function (ACC), in which the amplitude of the color burst signal is detected to adjust the color gain automatically and also has the TINT/R-Y axis correction function, in which hue is adjusted at demodulation. (6) Digital Clamp Circuit The digital clamp circuit provides pedestal clamp for the Y signals and center clamp for the Cb/Cr signals at any position. This circuit also detects the amount of noise using the autocorrelation function. (7) Output Adjustment Circuit The output adjustment circuit sets the capturing position and adjusts the contrast and color. Page 1846 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.5.2 Section 30 Digital Video Decoder A/D Converter for Video Signal Input The A/D converter processes the composite video signal (CVBS) using the sync tip clamp block and the programmable gain amplifier (PGA) and A/D-converts the signal. Figure 30.26 shows the block diagram of the A/D converter for video signal input. (2) Sync tip clamp Gain control (4) VIN1 10-bit precision A/D converter VIN2 (1) Input pin selection A/D converted value (10 bits) (3) PGA Figure 30.26 Block Diagram of A/D Converter for Video Signal Input Figure 30.27 shows the waveforms when a video signal is A/D-converted. Single  Differential PGA (VRT-VRB) 10-bit precision A/D converter 1023 [LSB] Sync tip clamp VRB voltage 0 [LSB] - (VRT-VRB) Figure 30.27 A/D Conversion Image (1) Input Pin Selection Block The input pin selection block selects either the VIN1 or VIN2 pin for inputting the signal according to the ADCCR2.ADC_VINSEL setting. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1847 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (2) Sync Tip Clamp Block The sync tip clamp block clamps the sync tip level to the VRB voltage ( 1.0 V). (3) Programmable Gain Amplifier (PGA) The PGA adjusts the gain so that the input video signal voltage ( 0.8 Vpp to 1.6 Vpp) should be the level to be input to the A/D converter ( 2.0 Vpp). One of 32 levels of gain values can be set. One level corresponds to gain of 0.2 dB (typ.). The minimum gain is 1.835 dB (typ.) and maximum gain is 8.023 dB (typ.). Table 30.35 shows the PGA gain setting and gain values. Table 30.35 PGA Gain Setting and Gain Values (dB) PGA Gain Setting Input Range (Vpp) Gain Value (dB) 0 1.619 1.835 1 1.585 2.021 2 1.551 2.206 3 1.519 2.392 4 1.486 2.579 5 1.455 2.766 6 1.423 2.954 7 1.393 3.142 8 1.363 3.322 9 1.333 3.522 : : : 27 0.879 7.143 28 0.857 7.360 29 0.836 7.578 30 0.815 7.799 31 0.794 8.023 The PGA gain can be set using PGACR.PGA_GAIN[4:0] with PGACR.PGA_GAIN_SEL = 1. When the AGC function is on (ADCCR1.AGCMODE = 1), the gain is automatically set. Page 1848 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 30 Digital Video Decoder 10-Bit Precision A/D Converter The 10-bit precision A/D converter receives the gain-adjusted video signal from the PGA and A/D-converts the signal. The converter has 10-bit resolution and performs sampling at 27 MHz, which is the frequency of the clock signal input via VIDEO_X1 or VIDEO_X2. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1849 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder 30.5.3 Sync Separator Circuit The sync separator circuit extracts the horizontal and vertical sync signals from the composite video signal. This circuit also detects the amplitude of the sync signals and automatically adjusts the PGA gain (automatic gain control = AGC). Figure 30.28 shows the block diagram of the sync separator circuit. (9) AGC with peak limiter Sync signal mplitude (1) Video signal (2) Noise reduction LPF for horizontal sync Clipping block (4) Composite sync separator for horizontal sync (10) (7) Horizontal AFC H VBI period (3) (5) Noise reduction LPF for vertical sync Composite sync separator for vertical sync (6) Vertical sync separator PGA gain control Horizontal sync (HS) Vertical sync (VS) (8) Vertical countdown block Timing adjustment and signal detection block V Figure 30.28 Block Diagram of Sync Separator Circuit (1) Clipping Block The clipping block clips the high tone component of the video signal to reduce amplitudedependency of the video signal. The specific clipping level can be set using SYNSCR3.SSCLIPSEL[3:0]. The clipping level should be within the range so that the composite sync signal component should not be deteriorated (should be detectable). (2) Noise Reduction Low-Pass Filter (LPF) for Horizontal Sync The noise reduction LPF reduces the superimposed noise on the video signals before composite sync signal separation. The LPFs can be separately set for the horizontal sync and vertical sync. The cutoff frequency of the horizontal sync LPF can be set using SYNSCR1.LPFHSYNC[2:0]. The cutoff frequency should be within a range that assures that the composite sync signal components are not degraded (are detectable). (3) Noise Reduction Low-Pass Filter (LPF) for Vertical Sync The noise reduction LPF reduces the superimposed noise on the video signals before composite sync signal separation. The LPFs can be separately set for the horizontal sync and vertical sync. The cutoff frequency of the vertical sync LPF can be set using SYNCSCR1.LPFVSYNC[2:0]. The Page 1850 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder cutoff frequency should be within a range that assures that the composite sync signal components are not degraded (are detectable). (4) Composite Sync Separator for Horizontal Sync The composite sync separator separates the composite sync signal from the video signal according to the slice level. The composite sync slice levels can be separately set for the vertical and vertical sync signals. The slice level can be set either automatically or manually according to the SYNSCR1.SLICERMODE_H[1:0] setting. When automatic setting is used, the slice level is automatically set according to the SYNSCR1.SLICERMODE_H[1:0], SYNSCR2.SYNCMAXDUTY_H[5:0], and SYNSCR2.SYNCMINDUTY_H[5:0] setting. The slice level detection speed can be set using SYNSCR1.VELOCITYSHIFT_H[3:0]. When manual setting is used, the slice level is determined by SYNSCR3.CSYNCSLICE_H[9:0]. (5) Composite Sync Separator for Vertical Sync The composite sync separator separates the composite sync signal from the video signal according to the slice level. The composite sync slice levels can be separately set for the vertical and vertical sync signals. The slice level can be set either automatically or manually according to the SYNSCR1.SLICERMODE_V[1:0] setting. When automatic setting is used, the slice level is automatically set according to the SYNSCR1.SLICERMODE_V[1:0], SYNSCR4.SYNCMAXDUTY_H[5:0], and SYNSCR4.SYNCMINDUTY_H[5:0] setting. When manual setting is used, the slice level is determined by SYNSCR5.CSYNCSLICE_V[9:0]. (6) Vertical Sync Separator The vertical sync separator extracts the vertical sync signal from the composite video signal separated using (5) above. The threshold value for separating the vertical sync signal can be set using SYNSCR5.VSYNCSLICE[4:0]. The value should be set depending on the serration pulse width of each video signal format. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1851 of 3092 Section 30 Digital Video Decoder (7) SH7268 Group, SH7269 Group Horizontal Automatic Frequency Control (AFC) Block The horizontal AFC, which is a digital PLL, extracts the horizontal sync signal from the composite video signal separated using (4) above. The AFC removes the pseudo horizontal sync signal and interpolates the incomplete horizontal sync signal to generate a stable horizontal sync signal. The center frequency and lock range of the horizontal AFC can be set using HAFCCR1.HAFCTYP[9:0], HAFCCR2.HAFCMAX[9:0], and HAFCCR3.HAFCMIN[9:0]. If the horizontal AFC is locked, VSYNCSR.FHLOCK becomes 1; and if the horizontal AFC is unlocked, VSYNCSR.FHLOCK becomes 0. The horizontal AFC oscillation cycle can be checked by reading HSYNCSR.FHCOUNT[16:1] and VSYNCSR.FHCOUNT[0]. The loop gain (response speed) of the horizontal AFC can be set using HAFCCR1.HAFCCGAIN[3:0]. As the speed is increased, the lockup time becomes shorter. However, the horizontal oscillation frequency will be more susceptible to noise. With HAFCCR3.HAFCMODE[1], AFCPFCR.PHDET_FIX, and AFCPFCR.PHDET_DIV[2:0], the loop gain can be reduced when S/N is low to prevent malfunction attributed to noise. Whether S/N is low or not can be checked with VSYNCSR.ISNOISY. The loop gain during the vertical blanking period (VBI) can be set using HAFCCR2.HAFCSTART[3:0], HAFCCR3.HAFCEND[3:0], and HAFCCR3.HAFCMODE[0]. This is usually used to avoid malfunction in the VCR head switch. (8) Vertical Countdown Block The vertical countdown block removes the pseudo vertical sync signal from the vertical sync signal separated using (6) above and interpolates the incomplete vertical sync signal to generate a stable vertical sync signal. The oscillation cycle of the vertical countdown block can be set using VCDWCR1.VCDDEFAULT[1:0]. When set to 0, the input vertical sync signal is detected and the oscillation cycle is automatically set appropriately. The detection result of the input vertical sync signal is indicated by VSYNCSR.FVMODE. When set to 1, 50.00-Hz oscillation mode is set. Here, it is recommended to set VCDWCR1.NOVCD60 to 1 (60-Hz oscillation off) to avoid unexpected malfunction. When set to 2 or 3, 59.94-/60.00-Hz oscillation mode is set. Here, it is recommended to set VCDWCR1.NOVCD50 to 1 (50-Hz oscillation off) to avoid unexpected malfunction. The lock range of the vertical countdown block can be set using VCDWCR1.VCDWINDOW[5:0] and VCDWCR1.VCDOFFSET[4:0]. If the vertical countdown block is locked, VSYNCSR.FVLOCK becomes 1; and if the vertical countdown block is unlocked, VSYNCSR.FVLOCK becomes 0. Page 1852 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder The cycle of the input vertical sync signal can be checked by reading VSYNCSR.FVCOUNT[7:0]. When the vertical sync signal input cannot be detected, VSYNCSR.NOSIGNAL is set to 1. (9) Automatic Gain Control (AGC) Block with Peak Limiter The AGC block detects the amplitude of the sync signal and automatically controls the PGA gain to the target value. The AGC function is activated with ADCCR1.AGCMODE = 1.  Gain Control according to Sync Amplitude The target sync signal amplitude can be set using AGCCR1.AGCLEVEL[8:0] and AGCCR2.AGCPRECIS[5:0]. For example, when NTSC signals are quantized by the 10-bit A/D converter, the sync signal amplitude for the full range of the A/D converter can be provided by: 1023[LSB]  (40[IRE]  173[IRE]) = 236.53179[LSB] Therefore, 236[LSB] should be set to AGCCR1.AGCLEVEL[8:0]. The gain is fixed when it falls within the following range. Target value (= AGCCR1.AGCLEVEL[8:0])  AGCCR2.AGCPRECISE[5:0] Whether the gain is fixed or not can be checked by reading AGCCR2.AGCCONVERGE. The detected sync signal amplitude can be checked using SYNCSSR.SYNCDEPTH[9:0]. The AGC response speed can be set using AGCCR1.AGCRESOPONSE[2:0]. As the speed is increased, the input signal is tracked more quickly; however, it will result in more susceptibleness to noise. The currently set gain value can be checked using AGCCSR2.AGCGAIN[7:0]. The actual PGA gain setting can be roughly calculated as follows: 0.585776  (AGCCSR2.AGCGAIN[7:0]  49) For example, when AGCCSR2.AGCGAIN[7:0] is 64 (corresponding to 1), PGA gain setting = 0.585776  (64  49)  8.78 As a result, the PGA gain setting is 8 or 9. One of 0 to 31 can be set as the PGA gain value. The gain during vertical blanking period (VBI) can be set using AGCCR1.DOREDUCE and AGCCR1.NOREDUCE. The sync amplitude detection result during VBI can be read from SYNCSSR.ISREDUCED. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1853 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder  Peak Limiter The peak limiter works when the ratio of the video signal amplitude to the sync signal amplitude is inappropriate. If the ratio is smaller than expected, the PGA gain becomes smaller, and the video signal after gain adjustment becomes smaller than the full range of the A/D converter. Contrarily, if the ratio is larger than expected, the PGA gain becomes larger, and the video signal after gain adjustment becomes larger than the full range of the A/D converter. 1023 [LSB] Smaller than the full range Video signal Ratio of video signal amplitude amplitude to sync signal amplitude is small 236 [LSB] Sync signal Gain adjustment amplitude 0 [LSB] Input video Output signal Overflow 1023 [LSB] Video signal amplitude Ratio of video signal amplitude to sync signal amplitude is large 236 [LSB] Sync signal Gain adjustment amplitude 0 [LSB] Input video Output signal Figure 30.29 Cases in which Ratio of Video Signal Amplitude to Sync Signal Amplitude is Inappropriate To deal with this problem, the peak limiter adjusts the PGA gain based on the sampled video signal peak value. The peak value used to control the gain can be set using PKLIMITCR.PEAKLEVEL[1:0]. When the peak value of the sampled video signal is smaller than the value set using PKLIMITCR.PEAKLEVEL[1:0], the gain is increased. Contrarily, when the peak value of the sampled video signal is larger than the value set using PKLIMITCR.PEAKLEVEL[1:0] exceeding the maximum allowable value set using PKLIMITCR.MAXPEAKSAMPLES[7:0], the gain is decreased. Page 1854 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder The gain increase/decrease response speed and maximum compression ratio can be set using PKLIMITCR.PEAKATTACK[1:0], PKLIMITCR.PEAKRELEASE[1:0], and PKLIMITCR.PEAKRATIO[1:0]. The number of pixels with the peak value larger than the value set using PKLIMITCR.PEAKLEVEL[1:0] can be checked with AGCCSR1.HIGHSAMPLES[7:0]; and the number of overflowing pixels (exceeding 1023[LSB]) can be checked with AGCCSR1.PEAKSAMPLES[7:0].  Manual Setting Manual setting of the PGA gain can be enabled by setting PGACR.PGA_GAIN_SEL to 1. Here, the value set using PGACR.PGA_GAIN[4:0] is actually set as the PGA gain. When PGACR.PGA_GAIN_SEL is 1, ADCCR1.AGCMODE setting is invalid. Setting PGACR.PGA_GAIN_SEL to 0 (automatic setting) and ADCCR1.AGCMODE to 0 (AGC off) simultaneously is prohibited. (10) Timing Adjustment and Signal Detection Block The timing adjustment and signal detection block adjusts the output timing of the horizontal and vertical sync signals generated using (7) and (8) above. This block also detects the field; whether the interlaced or progressive system is used can be checked with VSYNCSR.INTERLACED. If the field detection function is unstable, setting SYNSCR5.VSYNCDELAY to 1 may improve the function. The phases of the Hsync and Vsync signals are adjusted according to the result of detecting the field, and output of the Vsync signal from the sync separator circuit is delayed by one horizontal period. When having video display controller 4 capture the output signal from this module, take the above delay into consideration and set SCL0_DS2.RES_VS (vertical position setting for video signal capturing) as follows. VSYNC + (V backporch - 2) lines 30.5.4 Burst Controlled Oscillator (BCO) The BCO extracts the color burst signal from the composite video signal and reproduces the color sub-carrier signal required for color demodulation. It also acquires the phase and frequency information from the color burst signal and detects the color system used. Figure 30.30 shows the block diagram of the BCO. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1855 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder (1) Video signal Color burst extraction (2) Color burst adjustment ACC gain, color killer (3) Burst lock PLL Color sub-carrier (4) Color system detection Color system Figure 30.30 Block Diagram of Burst Controlled Oscillator (1) Color Burst Extraction Block The color burst extraction block extracts the color burst signal. The position of the color burst signal to be extracted can be adjusted using BTGPCR.BGPWIDTH[6:0] and BTGPCR.BGPSTART[7:0]. The extraction result of the color burst signal can be checked by reading CROMASR1.NOBURST. (2) Color Burst Adjustment Block The color burst adjustment block adjusts the amplitude of the extracted color burst signal. For details, refer to section 30.5.6 (1), Automatic Color Control (ACC) Block. This block also outputs the signal to turn on or off the color killer according to the amplitude of the input color burst signal. For details, refer to section 30.5.6 (2), Color Killer. (3) Burst Lock PLL The burst lock PLL is a digital PLL which reproduces the color sub-carrier signal from the adjusted color signal. The lock range of the burst lock PLL can be set using BTLCR.LOCKRANGE[1:0]. If the burst lock PLL is locked, CROMASR1.FSCLOCK becomes 1; and if unlocked, CROMASR1.FSCLOCK becomes 0. The loop gain of the burst lock PLL can be set using BTLCR.LOOPGAIN[1:0] and BTLCR.LOCKLIMIT[1:0]. As the response speed is increased and the frequency search is started earlier, the lockup time becomes shorter. However, the PLL becomes unstable and unlocked more easily due to noise. The S/N of the color burst signal can be checked using CROMASR2.LOCKLEVEL[7:0]. Page 1856 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 30 Digital Video Decoder Color System Detection Block The color system detection block detects the color system of the input video signal based on the oscillation frequency of the burst lock PLL and phase information of the color burst signal. The color system can be detected using BTLCR.NONTSC358, BTLCR.NONTSC443, BTLCR.NOPALM, BTLCR.NOPALN, BTLCR.NOPAL443, and BTLCR.NOSECAM. Color system detection can be set to fully automatic, manual, or semi-automatic (detecting the specified color system only). If the detection result does not apply to any color system type, the color system selected with BTLCR.DEFAULTSYS[1:0] is assumed. When an NTSC, PAL, or SECAM signal is detected, 1 is read from CROMASR2.ISNTSC, CROMASR2.ISPAL, or CROMASR2.ISSEAM, respectively. The currently used color system can be checked by reading CROMASR1.COLORSYS[1:0]. The color sub-carrier frequency can be checked by reading CROMASR1.FSCMODE. 30.5.5 Y/C Separator Circuit The Y/C separator circuit separates the composite video signal of the NTSC, PAL, or SECAM format into the Y and C signals. Two-dimensional adaptive separation is used for NTSC and PAL and one-dimensional separation for SECAM. Figure 30.31 shows a block diagram of the Y/C separator circuit. (1) Video signal (2) Horizontal and vertical filter Line delay (3) (4) 3 lines Horizontal (5) /vertical Horizontal value and vertical signal mixing Horizontal and vertical correlation detection Correlation value Correlation detection filter Correlation detection value (7) Horizontal (6) /vertical value Correlation detection value mixing C signal Y generation for Y generation Y (9) Over-range processing Y C signal for Y generation (8) C Cascade filter C Figure 30.31 Block Diagram of Y/C Separator Circuit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1857 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.36 shows the operation of the Y/C separator circuit for each color format. Table 30.36 Y/C Separation Operation for Each Color Format Color Format YC Separation Operation NTSC-3.58 Two dimensional NTSC-4.43 Two dimensional PAL-M Two dimensional PAL-N Two dimensional PAL-4.43 Two dimensional SECAM One dimensional (1) Line Delay Block In two-dimensional Y/C separation, three lines of data is required (directly adjacent three lines for NTSC and adjacent three lines on every second line for PAL). This block delays video signals to hold three lines of data. (2) Horizontal and Vertical Filter Block In two-dimensional adaptive Y/C separation, the horizontal band pass filter (BPF), vertical band pass filter (BPF), and horizontal/vertical band pass filter (BPF) are adaptively switched according to the correlation between the horizontally-/vertically-adjacent pixels. This block processes the input signals using the horizontal BPF, vertical BPF, or horizontal/vertical BPF. In onedimensional Y/C separation, only the horizontal BPF is used. Figure 30.32 shows the filter configuration. Page 1858 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Horizontal BPF HBPF1_9TAP_ON 17TAP BPF HBPF_NARROW 0 0 Output from HBPF filter 9TAP BPF 1 17TAP BPF 1 Output from H17TAP filter Output from H9TAP filter Horizontal/ vertical BPF Upper line Middle line Lower line Vertical BPF Output from VBPF filter HVBPF1_9TAP_ON HVBPF_NARROW 17TAP BPF 0 9TAP BPF 1 0 Output from HVBPF filter 17TAP BPF 1 Output from HV17TAP filter Output from HV9TAP filter Figure 30.32 Horizontal and Vertical Filter Configuration The horizontal BPF is composed of two stages. Either the 9-TAP or 17-TAP BPF is selected at the former stage. When YCSCR8.HBPF1_9TAP_ON/HVBPF1_9TAP_ON is 0, the 17-TAP BPF is selected; and when 1, the 9-TAP BPF is selected. Either bypass operation or the 9-TAP BPF is selected at the latter stage. When YCSCR8.HBPF_NARROW/HVBPF_ NARROW is 0, bypass operation is selected; and when 1, the 17-TAP BPF is selected. (3) Horizontal and Vertical Correlation Detection Block The horizontal and vertical correlation detection block detects the correlation value between the horizontal pixels, vertical pixels, and horizontal/vertical pixels. The value obtained by mixing the detected correlation value and the two-dimensional Y/C separation filter select coefficient is used for selecting the appropriate horizontal, vertical, or horizontal/vertical filter. Table 30.37 shows the two-dimensional Y/C separation filter select coefficients. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1859 of 3092 Section 30 Digital Video Decoder SH7268 Group, SH7269 Group Table 30.37 Two-Dimensional Y/C Separation Filter Select Coefficients Category Bit Name Description Bit Correlation Vertical Y/C separation select coefficients YCSCR5. K21A[5:0] As the value becomes larger, the vertical BPF is applied to the narrower range. YCSCR5. K22A[7:0] As the value becomes larger, the vertical BPF is applied to the narrower range. YCSCR7. K23A[3:0] As the value becomes larger, the vertical BPF is applied to the narrower range. YCSCR7. K24[4:0] As the value becomes larger, the vertical BPF is applied to the wider range. There is correlation between these bits. When horizontal dot crawl is conspicuous, make the bit field value smaller (make the K24 value larger). However, when the value is too small (K24 is too large), vertical dot crawl is produced. YCSCR6. K21B[5:0] As the value becomes larger, the vertical BPF is applied to the narrower range. YCSCR6. K22B[7:0] As the value becomes larger, the vertical BPF is applied to the narrower range. YCSCR7. K23B[3:0] As the value becomes larger, the vertical BPF is applied to the narrower range. YCSCR3. K11[5:0] As the value becomes larger, the horizontal There is correlation BPF is applied to the narrower range. between these bits. When vertical dot crawl is As the value becomes larger, the horizontal conspicuous, make the bit BPF is applied to the narrower range. field value smaller. As the value becomes larger, the horizontal However, when the value is BPF is applied to the narrower range. too small, horizontal dot crawl is produced. Horizontal Y/C separation select coefficients YCSCR3. K13[5:0] YCSCR3. K15[5:0] YCSCR4. K12[5:0] YCSCR4. K14[5:0] YCSCR4. K16[5:0] Page 1860 of 3092 There is correlation between these bits. When horizontal dot crawl is conspicuous, make the bit field value smaller. However, when the value is too small, vertical dot crawl is produced. As the value becomes larger, the horizontal There is correlation BPF is applied to the narrower range. between these bits. When vertical dot crawl is As the value becomes larger, the horizontal conspicuous, make the bit BPF is applied to the narrower range. field value smaller. As the value becomes larger, the horizontal However, when the value is BPF is applied to the narrower range. too small, horizontal dot crawl is produced. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 30 Digital Video Decoder Correlation Detection Filter Block The correlation detection filter block, specific to this module, attaches greater importance to the correlation between lines to reduce dot crawl, especially at the intersection of a cross. By mixing the signals after correlation detection filter block, dot crawl can be reduced when dot crawl is not fully removed by the horizontal and vertical filter block. (5) Horizontal and Vertical Signal Mixing Block The horizontal and vertical signal mixing block mixes the signals output from the horizontal, vertical, and horizontal/vertical filter blocks with the signals output from the horizontal and horizontal/vertical filters of the former stage. After that, the appropriate signal is selected from among the signals output from the horizontal, vertical, and horizontal/vertical filters according to the correlation value obtained using (3). Figure 30.33 shows the configuration of the horizontal and vertical signal mixing block. HSEL_MIX_Y Output from HBPF filter Output from H17TAP filter Output from H9TAP filter 0 1 HFIL_TAP_SEL Output from HV9TAP filter VSEL_MIX_Y Output from VBPF filter C HVSEL_MIX_Y Output from HVBPF filter Output from HV17TAP filter Output from HV9TAP filter 0 1 Detected value HFIL_TAP_SEL Figure 30.33 Configuration of Horizontal and Vertical Signal Mixing Block The signal to be mixed, which is output from either the horizontal or horizontal/vertical filter of the former stage, can be selected with YCSCR8.HFIL_TAP_SEL. When YCSCR8. HFIL_TAP_SEL is 0, the signal output from the 17-TAP filter is selected; and when 1, the signal output from the 9-TAP filter is selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1861 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder This block mixes the signals output from the horizontal filter with the signals output from the above described horizontal filter of the former stage. The mixing ratio can be set with YCSCR9.HSEL_MIX_Y[3:0]. Similarly, this block mixes the signals output from the vertical or horizontal/vertical filter with the signals output from the above described horizontal/vertical filter of the former stage. The mixing ratio can be set with YCSCR9.VSEL_MIX_Y[3:0] and YCSCR9.HVSEL_MIX_Y[3:0]. This block selects the appropriate signal from among the signals output from the horizontal, vertical, and horizontal/vertical filters according to the correlation value obtained using (3). (6) Correlation Detection Value Mixing Block The correlation detection value mixing block mixes the C signal for Y generation, and the C signal generated using (5) with the signals after correlation detection filter block (4). Figure 30.34 shows the configuration of the correlation detection value mixing block. DET2_MIX_Y C signal for Y generation C signal for Y generation DET2_MIX_C C C Correlation detection value Figure 30.34 Configuration of Correlation Detection Value Mixing Block When YCSCR9.DET2_ON is 1, this block mixes the signal after the correlation detection filter block. The mixing ratio of the C signal for Y generation to the signal after the correlation detection filter block can be set with YCSCR12.DET2_MIX_Y[3:0]. Similarly, the mixing ratio of the C signal to the signal after the correlation detection filter block can be set with YCSCR12.DET2_MIX_C[3:0]. When YCSCR9.DET2_ON is 0, this block outputs the signal after the horizontal and vertical filter block without mixing. Page 1862 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (7) Section 30 Digital Video Decoder Y Generation Block The Y generation block generates the Y signal by subtracting the C signal for Y generation from the video signal. (8) Cascade Filter Block The cascade filter block allows the C signal to pass through the cascade filter or TAKE-OFF filter to further narrow the bandwidth. Figure 30.35 shows the configuration of the cascade filter block. FIL2_MODE_2D FIL_NARROW_2D 0 C C 17TAP BPF FIL2_2D_WA/WB 17TAP BPF 1 FIL2_2D_NA/NB Figure 30.35 Configuration of Cascade Filter Block The cascade filter block is composed of two stages. Either bypass operation or 17-TAP filter is selected at the former stage. Bypass operation, cascade, or TAKE-OFF filter can be selected at the former stage with YCSCR12.FIL2_MODE_2D[1:0]. Similarly, either bypass operation or 17-TAP filter can be selected at the latter stage with YCSCR12.FIL2_NARROW_2D. Both of the former- and latter-stage filters are universal and can be set with YCTWA_F0 to YCTWA_F8, YCTWB_F0 to YCTWB_F8, YCTNA_F0 to YCTNA_F8, and YCTNB_F0 to YCTNB_F8. Tables 30.38 to 30.40 show the recommended setting for each filter. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1863 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.38 Recommended Settings for Two-Dimensional Y/C Filters (NTSC) NTSC NTSC TAKE-OFF Cascade Filter Bypass 1 TAKE-OFF Filter 2 Broad- Narrow- Stages band Bit Name Operation Stage FIL2_MODE_2D 0 1 FIL2_NARROW_2D  0 1  FIL2_2D_WA_F0  24 24 FIL2_2D_WA_F1  44 FIL2_2D_WA_F2  FIL2_2D_WA_F3  FIL2_2D_WA_F4 FIL2_2D_WA_F5 Cascade Filter Bypass 1 2 Filter Broad- Narrow- Bit Name Operation Stage FIL2_MODE_2D 0 1  FIL2_NARROW_2D  0 1   0 0 FIL2_2D_NA_F0   24   44 0 -48 FIL2_2D_NA_F1   44   20 20 0 -20 FIL2_2D_NA_F2   20   -52 -52 -28 160 FIL2_2D_NA_F3   -52    -128 -128 96 232 FIL2_2D_NA_F4   -128    -128 -128 228 -116 FIL2_2D_NA_F5   -128   FIL2_2D_WA_F6  -12 -12 -916 -900 FIL2_2D_NA_F6   -12   FIL2_2D_WA_F7  132 132 -204 -4 FIL2_2D_NA_F7   132   FIL2_2D_WA_F8  200 200 1648 1392 FIL2_2D_NA_F8   200   FIL2_2D_WB_F0      FIL2_2D_NB_F0      FIL2_2D_WB_F1      FIL2_2D_NB_F1      FIL2_2D_WB_F2      FIL2_2D_NB_F2      FIL2_2D_WB_F3      FIL2_2D_NB_F3      FIL2_2D_WB_F4      FIL2_2D_NB_F4      FIL2_2D_WB_F5      FIL2_2D_NB_F5      FIL2_2D_WB_F6      FIL2_2D_NB_F6      FIL2_2D_WB_F7      FIL2_2D_NB_F7      FIL2_2D_WB_F8      FIL2_2D_NB_F8      Page 1864 of 3092 band 2 Stages band band 2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.39 Recommended Settings for Two-Dimensional Y/C Filters (PAL) PAL PAL Cascade TAKE-OFF Cascade TAKE-OFF Filter Filter Filter Filter Bypass 1 2 Broad- Narrow Bit Name Operation Stage Stages band Bypass 1 2 Bit Name Operation Stage Stages band FIL2_MODE_2D 0 1 FIL2_MODE_2D 0 1 FIL2_NARROW_2D  0 1   FIL2_NARROW_2D  0 1   FIL2_2D_WA_F0  -20 -20 0 0 FIL2_2D_NA_F0   -20   FIL2_2D_WA_F1  24 24 0 0 FIL2_2D_NA_F1   24   FIL2_2D_WA_F2  64 64 0 -23 FIL2_2D_NA_F2   64   FIL2_2D_WA_F3  40 40 16 -46 FIL2_2D_NA_F3   40   FIL2_2D_WA_F4  -76 -76 59 145 FIL2_2D_NA_F4   -76   FIL2_2D_WA_F5  -164 -164 85 409 FIL2_2D_NA_F5   -164   FIL2_2D_WA_F6  -84 -84 -498 -918 FIL2_2D_NA_F6   -84   FIL2_2D_WA_F7  108 108 -101 -363 FIL2_2D_NA_F7   108   FIL2_2D_WA_F8  216 216 878 1592 FIL2_2D_NA_F8   216   FIL2_2D_WB_F0      FIL2_2D_NB_F0      FIL2_2D_WB_F1      FIL2_2D_NB_F1      FIL2_2D_WB_F2      FIL2_2D_NB_F2      FIL2_2D_WB_F3      FIL2_2D_NB_F3      FIL2_2D_WB_F4      FIL2_2D_NB_F4      FIL2_2D_WB_F5      FIL2_2D_NB_F5      FIL2_2D_WB_F6      FIL2_2D_NB_F6      FIL2_2D_WB_F7      FIL2_2D_NB_F7      FIL2_2D_WB_F8      FIL2_2D_NB_F8      R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 -band 2 Broad- Narrow -band 2 Page 1865 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.40 Recommended Settings for Two-Dimensional Y/C Filters (SECAM) SECAM SECAM Cascade Cascade Filter Filter Bypass 1 2 Bit Name Operation Stage Stages FIL2_MODE_2D 0 1 FIL2_NARROW_2D  0 FIL2_2D_WA_F0  FIL2_2D_WA_F1 Bypass 1 2 Bit Name Operation Stage Stages 2 FIL2_MODE_2D 0 1 1  FIL2_NARROW_2D  0 1  -20 -20 0 FIL2_2D_NA_F0   -1008   24 24 -12 FIL2_2D_NA_F1   1976  FIL2_2D_WA_F2  64 64 -18 FIL2_2D_NA_F2   -2024  FIL2_2D_WA_F3  40 40 38 FIL2_2D_NA_F3   444  FIL2_2D_WA_F4  -76 -76 100 FIL2_2D_NA_F4   1868  FIL2_2D_WA_F5  -164 -164 88 FIL2_2D_NA_F5   -2864  FIL2_2D_WA_F6  -84 -84 -508 FIL2_2D_NA_F6   1352  FIL2_2D_WA_F7  108 108 -114 FIL2_2D_NA_F7   1376  FIL2_2D_WA_F8  216 216 852 FIL2_2D_NA_F8   -2240  FIL2_2D_WB_F0  -12 -12  FIL2_2D_NB_F0   -1080  FIL2_2D_WB_F1  40 40  FIL2_2D_NB_F1   2800  FIL2_2D_WB_F2  60 60  FIL2_2D_NB_F2   -3308  FIL2_2D_WB_F3  12 12  FIL2_2D_NB_F3   1628  FIL2_2D_WB_F4  -104 -104  FIL2_2D_NB_F4   1444  FIL2_2D_WB_F5  -156 -156  FIL2_2D_NB_F5   -3308  FIL2_2D_WB_F6  -64 -64  FIL2_2D_NB_F6   2140  FIL2_2D_WB_F7  120 120  FIL2_2D_NB_F7   376  FIL2_2D_WB_F8  208 208  FIL2_2D_NB_F8   -1384  (9) TAKE-OFF Filter TAKE-OFF Filter 2 Over-Range Control Block If overflow or underflow occurs at the top or bottom of the color amplitude of video signals, Y/C separation may not be correctly performed thus causing vertical lines to appear as dot crawl. To reduce this phenomenon, the over-range control block automatically inserts the low-pass filter for Y signals (cuts off the frequency components of the vertical lines) Page 1866 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Setting RGORCR7.UCMP_SW to 1 enables over-range control, and setting RGORCR7.DCMP_SW to 1 enables under-range control. One of four over-range levels can be set with RGORCR1.RADJ_O_LEVEL0[9:0], RGORCR3.RADJ_O_LEVEL1[9:0], and RGORCR5.RADJ_O_LEVEL2[9:0]. Similarly, one of four under-range levels can be set with RGORCR2.RADJ_U_LEVEL0[9:0], RGORCR4.RADJ_U_LEVEL1[9:0], and RGORCR6.RADJ_U_LEVEL2[9:0]. The filter to be inserted is appropriately selected according to the over-range and under-range levels. Setting HWIDE_SW to 1 enables detection of the maximum (minimum) level of five pixels in the horizontal direction in addition to the currently processed pixel to detect over-range or underrange occurrence. 30.5.6 Chroma Decoding Circuit The chroma decoding circuit demodulates the C signal extracted by the Y/C separator circuit into the Cb/Cr signal. This circuit has the automatic color control function (ACC), in which the amplitude of the color burst signal is detected to adjust the color gain automatically and also has the TINT/R-Y axis correction function, in which hue is adjusted at demodulation. Figure 30.36 shows the block diagram of the chroma decoding circuit. (1) ACC gain C ACC C (2) Color killer (4) C (6) Color killer Color system Color sub-carrier signal Cb (3) Hue adjustment correction Chroma decoding Cr Frequency band inhibition LPF Cb Cr (5) Y Delay adjustment Y Figure 30.36 Block Diagram of Chroma Decoding Circuit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1867 of 3092 Section 30 Digital Video Decoder (1) SH7268 Group, SH7269 Group Automatic Color Control (ACC) Block The ACC block detects the amplitude of the color burst signal and automatically controls the C signal gain so that the amplitude should be controlled to the target value. The ACC function is activated with ACCCR1.ACCMODE = 0. The target amplitude of the color burst signal can be set with ACCCR1.ACCLEVEL[8:0]. The gain is fixed when the amplitude falls within ACCCR1.ACCLEVEL[8:0] ± ACCCR3.ACCPRECIS[5:0]. The maximum ACC gain can be set with ACCCR1.ACCMAXGAIN[1:0]. The currently set gain value can be checked by reading CROMASR1.ACCMAINGAIN[8:0] (main) and CROMASR1.ACCSUBGAIN[1:0] (sub). The C signal gain can also be set manually by setting ACCCR1.ACCMODE to 1. The specific gain value can be set with ACCCR2.CHROMAMAINGAIN[8:0] (main) and ACCCR2.CHROMASUBGAIN[1:0] (sub). (2) Color Killer The color killer deletes color information when the color bust signal amplitude is small in a weak electric field. The color killer is turned on or off based on the hysteresis; specifically, it is turned on when the amplitude reaches the value set with ACCCR3.KILLERLEVEL[5:0] and turned off when the amplitude reaches the value determined by ACCCR3.KILLERLEVEL[5:0] + ACCCR1.KILLEROFFSET[3:0]. The color killer can also be turned off forcibly by so setting ACCCR3.KILLERMODE. (3) Hue Adjustment Correction Block The hue adjustment correction block adjusts the color sub-carrier signal phase to adjust the Cb/Cr hue after chroma decoding. This function can be used only for the NTSC and PAL systems. The phase of the demodulation axis is controlled with TINTCR.TINTMAIN[9:0] and the phase of the R-Y axis is controlled with TINTCR.TINTSUB[5:0]. (4) Chroma Decoding Block The chroma decoding block demodulates the Cb/Cr signal from the C signal. Line averaging can be carried out before demodulation according to YCDCR.DEMODMODE[1:0] setting. YCDCR.DEMODMODE[1:0] should usually be set to 2 (two-line demodulation for PAL only; one-line demodulation for NTSC). Page 1868 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 30 Digital Video Decoder Delay Adjustment Block The delay adjustment block delays the Y signal to adjust the Y/C signal delay. The Y signal can be delayed by -16 to 15 clock pulses with YCDCR.LUMADELAY[4:0]. (6) Frequency Band Inhibition LPF The frequency band inhibition LPF inhibits the frequency band of the Cb/Cr signal after chroma decoding. This LPF is turned on or off according to YCDCR.CHROMALPF setting. 30.5.7 Digital Clamp Circuit The digital clamp circuit provides pedestal clamp for the Y signals and center clamp for the Cb/Cr signals at any position. This circuit also detects the amount of noise using the autocorrelation function. Figure 30.37 shows the block diagram of the digital clamp circuit. (1) Vertical sync Horizontal sync Vertical clamp position Vertical clamp position (6) (2) Y signal horizontal clamp position (3) Cb/Cr signal horizontal clamp position Y signal horizontal clamp position Noise detection Cb/Cr signal horizontal clamp position (4) Pedestal clamp Y (10 bits) Y (10 bits) (5) Center clamp Cb (10bits) Cb (10 bits) Cr (10 bits) Cr (10bits) Figure 30.37 Block Diagram of Digital Clamp Circuit (1) Vertical Clamp Position Control Block The vertical clamp position can be set with DCPCR4.DCPSTART[5:0] and DCPCR5.DCPEND[5:0]. The setting is used in common to Y, Cb, and Cr signals. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1869 of 3092 Section 30 Digital Video Decoder (2) SH7268 Group, SH7269 Group Y Signal Horizontal Clamp Position Control Block The horizontal clamp start position of the Y signal can be set with DCPCR7.DCPPOS_Y[7:0]. The horizontal clamp width can be set with DCPCR6.DCPWIDTH[6:0]. The horizontal clamp width setting is used in common to Y, Cb, and Cr signals. (3) Cb/Cr Signal Horizontal Clamp Position Control Block The horizontal clamp start position of the Cb/Cr signal can be set with DCPCR8.DCPPOS_C[7:0]. The horizontal clamp width can be set with DCPCR6.DCPWIDTH[6:0]. The horizontal clamp width setting is used in common to Y, Cb, and Cr signals. (4) Pedestal Clamp Control Block The pedestal clamp control block stabilizes the Y signal pedestal level. When DCPCR1.DCPMODE_Y is 0, the value set with DCPCR1.BLANKLEVEL_Y[9:0] is subtracted from the Y signal, which is expressed as: Y signal output = Y signal input  DCPCR1.BLANKLEVEL_Y[9:0] When DCPCR1.DCPMODE_Y is 1, the Y signal level detected at the set clamp position and DCPCR1.BLANKLEVEL_Y[9:0] are added together and the resulting value is subtracted from the Y signal, which is expressed as: Y signal output = Y signal input  (detected value + DCPCR1.BLANKLEVEL_Y[9:0]) The detected value can be used from DSPCR1.CLAMPLEVEL_Y[9:0]. The clamp response speed can be set with DCPCR3.DCPRESPONSE[2:0]. The setting is used in common to Y, Cb, and Cr signals. (5) Center Clamp Control Block The center clamp control block stabilizes the Cb/Cr signal center level. When DCPCR2.DCPMODE_C is 0, the value set with DCPCR2.BLANKLEVEL_CB/DCPCR2.BLANKLEVEL_CR[5:0] is subtracted from the Cb/Cr signal, which is expressed as: Cb signal output = Cb signal input  DCPCR2.BLANKLEVEL_CB[5:0] Cr signal output = Cr signal input  DCPCR2.BLANKLEVEL_CR[5:0] Page 1870 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder When DCPCR2.DCPMODE_C is 1, the Cb/Cr signal level detected at the set clamp position and DCPCR2.BLANKLEVEL_CB/DCPCR2.BLANKLEVEL_CR[5:0] are added together and the resulting value is subtracted from the Cb/Cr signal, which is expressed as: Cb signal output = Cb signal input  (detected value + DCPCR2.BLANKLEVEL_CB[5:0]) Cr signal output = Cr signal input  (detected value + DCPCR2.BLANKLEVEL_CR[5:0]) The detected value can be used from DSPCR1.CLAMPLEVEL_CB[5:0] and DSPCR2.CLAMPLEVEL_CR[5:0]. The clamp response speed can be set with DCPCR3.DCPRESPONSE[2:0]). The setting is used in common to Y, Cb, and Cr signals. (6) Noise Detection Block Using the autocorrelation function, the noise amount at the set clamp position can be detected. With NSDCR.ACFINPUT[1:0], either Y, Cb, or Cr signal can be selected for which to calculate the autocorrelation function. The delay time for autocorrelation function calculation can be set with NSDCR.ACFLAGTIME[4:0] and accumulated field amount of autocorrelation function can be set with NSDCR.ACFFILTER[1:0]. The autocorrelation function (correlation coefficient) can be read from NSDSR.ACFSTRENGTH[15:0]. 30.5.8 Output Control Circuit The output control circuit sets the signal capturing position and adjusts the contrast and color. Figure 30.38 shows the block diagram of the output control circuit (1) Capturing position setting Vertical sync Vertical enable signal Horizontal enable signal Horizontal sync (2) Contrast and color adjustment Y (10 bits) Cb (10 bits) Y (10 bits) Cb (10 bits) Cr (10 bits) Cr (10 bits) Figure 30.38 Block Diagram of Output Control Circuit R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1871 of 3092 Section 30 Digital Video Decoder (1) SH7268 Group, SH7269 Group Capturing Position Setting Block The capturing position setting block sets the position to capture the input video signals. The position can be set with TGCR1.SRCLEFT[8:0], TGCR2.SRCTOP[5:0], TGCR2.SRCHEIGHT[9:0], and TGCR3.SRCWIDTH[10:0]. These settings are applied only to this module. To set the display size of the input video signals, the vertical capture size register (SCL0_DS2) and horizontal capture size register (SCL0_DS3) of the scaler of video display controller 4 should be used. (2) Contrast and Color Adjustment Block The contrast and color adjustment block adjusts the gain of the output Y/Cb/Cr signals. The contrast (Y signal gain) can be adjusted with YGAINCR.Y_GAIN2[9:0] and the color (Cb/Cr signal gain) can be adjusted with CBGAINCR.CB_GAIN2[9:0] and CRGAINCR.CR_GAIN2[9:0]. Page 1872 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.6 Section 30 Digital Video Decoder Recommended Setting Tables 30.41 and 30.42 show the recommended setting for this module. Table 30.41 Recommended Setting Common to Various Color Formats Register Bit Initial Value (Decimal) Recommended Value (Decimal) Remarks ADCCR1 AGCMODE 0 1 AGC on SYNSCR1 LPFVSYNC 3 3 LPFHSYNC 3 5 VELOCITYSHIFT_H 0 2 SLICERMODE_H 2 2 Automatic slicing SLICERMODE_V 2 2 Automatic slicing SYNCMAXDUTY_H 15 15 SYNCMINDUTY_H 10 10 SSCLIPSEL 15 15 CSYNCSLICE_H 146 146 SYNCMAXDUTY_V 15 15 SYNCMINDUTY_V 10 9 VSYNCDELAY 0 0 VSYNCSLICE 11 10 CSYNCSLICE_V 146 146 HAFCGAIN 6 12 HAFCFREERUN 0 0 HAFCSTART 0 0 NOX2HOSC 0 1 DOX2HOSC 0 0 HAFCEND 8 8 HAFCMODE 2 2 VCDFREERUN 0 0 SYNSCR2 SYNSCR3 SYNSCR4 SYNSCR5 HAFCCR1 HAFCCR2 HAFCCR3 VCDWCR1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Comparison disabled during VBI period Page 1873 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Bit Initial Value (Decimal) Recommended Value (Decimal) DCPCR1 DCPMODE_Y 1 1 DCPCHECK 0 0 BLANKLEVEL_Y 0 -40 (984) DCPMODE_C 0 0 BLANKLEVEL_CB 0 0 BLANKLEVEL_CR 0 0 DCPCR3 DCPRESPONSE 5 0 DCPCR4 DCPSTART 16 16 DCPCR5 DCPEND 16 2 DCPCR6 DCPWIDTH 54 27 DCPCR7 DCPPOS_Y 162 162 DCPCR8 DCPPOS_C 27 54 NSDCR ACFINPUT 0 0 ACFLAGTIME 0 0 ACFFILTER 0 3 LOCKRANGE 1 1 LOOPGAIN 1 3 LOCKLIMIT 2 1 BCOFREERUN 0 0 BGPCHECK 0 0 BGPWIDTH 36 54 DCPCR2 BTLCR BTGPCR ACCCR1 ACCCR2 Page 1874 of 3092 BGPSTART 130 110 KILLEROFFSET 8 5 ACCMODE 0 0 ACCMAXGAIN 0 0 CHROMASUBGAIN 0 0 CHROMAMAINGAIN 256 210 Remarks Automatic clamp setting ACC on R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Bit Initial Value (Decimal) Recommended Value (Decimal) ACCCR3 ACCRESPONSE 1 1 ACCPRECIS 20 8 KILLERMODE 0 0 KILLERLEVEL 9 4 TINTSUB 0 0 TINTMAIN 0 0 LUMADELAY 0 0 CHROMALPF 0 0 DEMODMODE 2 2 DOREDUCE 0 0 NOREDUCE 0 0 AGCRESPONSE 5 4 AGCCR2 AGCPRECIS 10 10 PKLIMITCR PEAKLEVEL 0 2 PEAKATTACK 2 2 PEAKRELEASE 0 3 PEAKRATIO 0 0 MAXPEAKSAMPLES 0 20 RGORCR1 RADJ_O_LEVEL0 1023 928 RGORCR2 RADJ_U_LEVEL0 0 32 RGORCR3 RADJ_O_LEVEL1 1023 960 RGORCR4 RADJ_U_LEVEL1 0 48 RGORCR5 RADJ_O_LEVEL2 1023 992 RGORCR6 RADJ_U_LEVEL2 0 64 RGORCR7 TEST_MONI 0 0 RADJ_MIX_K_FIX 0 0 UCMP_SW 0 1 Over-range detection enabled DCMP_SW 0 1 Under-range detection enabled HWIDE_SW 1 1 TINTCR YCDCR AGCCR1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Remarks Peak limiter on Page 1875 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Register Bit Initial Value (Decimal) Recommended Value (Decimal) AFCPFCR PHDET_FIX 0 0 PHDET_DIV 5 5 RUPDCR NEWSETTING 0 1 YCSCR8 HBPF_NARROW 1 0 HVBPF_NARROW 1 0 HBPF1_9TAP_ON 0 0 HVBPF1_9TAP_ON 0 0 HFIL_TAP_SEL 0 0 YCSCR11 V_Y_LEVEL 3 0 DCPCR9 CLP_HOLD_ON_Y 1 0 CLP_HOLD_ON_CB 1 0 CLP_HOLD_ON_CR 1 Remarks 0 YCTWA_F0 to YCTWA_F8 FIL2_2D_WA_F0 to FIL2_2D_WA_F8 Refer to 30.5.5 (8), Cascade Filter Block. YCTWB_F0 to YCTWA_F8 FIL2_2D_WB_F0 to FIL2_2D_WB_F8 Refer to 30.5.5 (8), Cascade Filter Block. YCTNA_F0 to YCTNA_F8 FIL2_2D_NA_F0 to FIL2_2D_NA_F8 Refer to 30.5.5 (8), Cascade Filter Block. YCTNB_F0 to YCTNB_F8 FIL2_2D_NB_F0 to FIL2_2D_NB_F8 Refer to 30.5.5 (8), Cascade Filter Block. YGAINCR Y_GAIN2 512 816 CBGAINCR CB_GAIN2 512 663 CRGAINCR CR_GAIN2 512 663 PGA_UPDATE PGA_VEN 1 1 PGACR PGA_GAIN_SEL 0 0 PGA_GAIN 0 0 ADC_VINSEL 0 0 ADCCR2 Page 1876 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder Table 30.42 Recommended Setting for Each Color Format NTSC-443 Register Bit NTSC-3.58 NTSC-4.43 PAL-4.43 PAL-M PAL-N SECAM (60 Hz) PAL-60 Capturing position setting TGCR1 SRCLEFT 256 256 256 256 256 256 256 256 TGCR2 SRCTOP 16 19 19 16 19 19 16 16 SRCHEIGHT 241 288 288 241 288 288 241 241 SRCWIDTH 1428 1412 1412 1428 1412 1412 1428 1428 HAFCCR1 HAFCTYP 692 704 704 692 704 704 692 692 HAFCCR2 HAFCMAX 792 785 785 792 785 785 792 792 HAFCCR3 HAFCMIN 592 630 630 592 630 630 592 592 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 VCDDEFAULT 2 1 1 2 1 1 2 2 VCDWINDOW 30 30 30 30 30 30 30 30 VCDOFFSET 15 15 15 15 15 15 15 15 DEFAULTSYS 0 0 1 1 1 2 0 1 NONTSC358 0 1 1 1 1 1 1 1 NONTSC443 1 0 1 1 1 1 0 1 NOPALM 1 1 1 0 1 1 1 1 NOPALN 1 1 1 1 0 1 1 1 NOPAL443 1 1 0 1 1 1 1 0 NOSECAM 1 1 1 1 1 0 1 1 220 220 230 230 230 220 220 230 230 230 242 242 242 242 230 242 TGCR3 Horizontal AFC setting Vertical countdown setting VCDWCR NOVCD50 1 NOVCD60 BCO setting BTLCR ACC level setting ACCCR1 ACCLEVEL AGC level setting AGCCR1 AGCLEVEL R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1877 of 3092 SH7268 Group, SH7269 Group Section 30 Digital Video Decoder NTSC-443 Register Bit NTSC-3.58 NTSC-4.43 PAL-4.43 PAL-M PAL-N SECAM (60 Hz) PAL-60 K15 2 2 2 2 2 2 2 2 K13 8 8 8 8 8 8 8 8 K11 4 4 3 3 3 4 4 3 K16 3 3 4 4 4 3 3 4 K14 16 16 63 63 63 16 16 63 K12 8 8 2 2 2 1 8 2 K22A 32 32 32 32 32 32 32 32 K21A 6 6 10 10 10 10 6 10 K22B 8 8 15 15 15 15 8 15 K21B 6 6 10 10 10 6 6 10 K23B 6 6 3 3 3 3 6 3 K23A 3 3 3 3 3 3 3 3 K24 5 5 8 8 8 8 5 8 DET2_ON 1 1 0 0 0 1 1 0 HSEL_MIX_Y 6 6 0 0 0 6 6 0 VSEL_MIX_Y 6 6 0 0 0 6 6 0 HVSEL_MIX_Y 0 0 0 0 0 0 0 0 YCSCR12 DET2_MIX_C 0 0 0 0 0 0 0 0 DET2_MIX_Y 2 2 0 0 0 0 2 0 FIL2_MODE_2D 1 1 0 0 0 1 1 0 FIL2_NARROW_2D 1 1 1 1 1 1 1 1 Y/C separation setting YCSCR3 YCSCR4 YCSCR5 YCSCR6 YCSCR7 YCSCR9 Page 1878 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 30.7 Section 30 Digital Video Decoder Connection Example Figure 30.39 shows a pin connection example of this module. This LSI Anti-alias filter*1 Input RVIN1 1 F CVIN2 1 F VIN1 VDAVDD 3.3 0.3 V (Analog power supply) 75 Anti-alias filter*1 Input RVIN2 CVIN1 VDAVSS VIN2 0V (Analog ground) VRT (TOP reference voltage) 75 BIAS RBIAS 24 k 1 VRB (BOTTOM reference voltage) CVRT 0.1 F CVRB 0.1 F CL1 VIDEO_X1 CL2 Crystal oscillator 27 MHz 100 ppm*2 ROF VIDEO_X2 ROD Notes: 1. Insert it if necessary. 2. Reference value The output video quality depends on the clock precision. Input as precise clock as possible. Figure 30.39 Pin Connection Example R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1879 of 3092 Section 30 Digital Video Decoder Page 1880 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 31 Video Display Controller 4 (1): Overview Section 31 Video Display Controller 4 (1): Overview 31.1 Features The video display controller 4 consists of the following six blocks. For the image synthesis, two graphics planes + video image or three graphics planes can be selected. 1. Input controller: Input video image selection, sync signal adjustment, horizontal noise reduction, and brightness adjustment, gain adjustment, and YCbCrGBR conversion using a color matrix 2. Scaler: Scale up, scale down, and rotation of input video images using the frame buffer, and repeated recording of the specified number of fields in the frame buffer 3. Image quality improver: Black stretch, LTI/sharpness, and YCbCrGBR conversion using a color matrix 4. Image synthesizer: Synthesis of two graphics planes + video image or three graphics planes 5. Output controller: Brightness/contrast adjustment, gamma correction, dither processing, output format conversion, control signal output for TFT-LCD panel 6. System controller: Interrupt control, panel clock control, CLUT table select signal status flag output The functions of video display controller 4 are listed in table 31.1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1881 of 3092 Section 31 Video Display Controller 4 (1): Overview SH7268 Group, SH7269 Group Table 31.1 Features of Video Display Controller 4 Item Function Operating frequency Video input clock: 27/54 MHz (for video image), 66.67 MHz or less (for RGB video image) Panel clock: 66.67 MHz or less (depends on the panel specifications) Input video image specification   8-bit input conforming to ITU-R BT.656 standard (27 MHz) 8-bit input conforming to ITU-R BT.601 standard (27 MHz, interlace signal)  8-bit input conforming to ITU-R BT.601 standard (54 MHz, progressive signal)  Digital pin input: YCbCr444, RGB888, RGB666, and RGB565 video image  Digital pin input size: Maximum input video image size to be set*: 1024 pixels  1024 lines (horizontal  vertical) Note: * Depends on the AC characteristics of the connected device.  Video image recording function   Examples of input video image size: SVGA (800  600), WVGA (800  480), VGA (640  480), WAVGA (480  240), QVGA in landscape (320  240), QVGA in portrait (240  320) Storing the video image in the YCbCr422/RGB565/RGB888 format at a rate of 1/1, 1/2, 1/4, or 1/8 field. Maximum video image size to be stored: 1 size of input video image Video image quality Contrast adjustment, brightness adjustment, horizontal noise reduction, adjustment function black stretch, LTI/sharpness Video image scaling Vertical: 1/8 to 8, linear/hold interpolation processing Horizontal: 1/8 to 8, linear/hold interpolation IP conversion can be performed by adjusting the initial phase. Video image rotation function Page 1882 of 3092 0/90/180/270 degree rotation and horizontal mirroring (with image renderer, exclusive access control) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 31 Video Display Controller 4 (1): Overview Item Function Graphics    Graphics function Number of graphic planes: Three planes (graphics 1, graphics 2, and graphics 3) Supported pixel formats:  RGB565 progressive format (: none, R: 5 bits, G: 6 bits, B: 5 bits; 16 bits in total)  RGB888 progressive format (: none, R: 8 bits, G: 8 bits, B: 8 bits; 24 bits in total)   RGB1555 progressive format (: 1 bit, R: 5 bits, G: 5 bits, B: 5 bits; 16 bits in total)   RGB4444 progressive format (: 4 bits, R: 4 bits, G: 4 bits, B: 4 bits; 16 bits in total)   RGB8888 progressive format (: 8 bits, R: 8 bits, G: 8 bits, B: 8 bits; 32 bits in total)  CLUT8 progressive format (CLUT: 8 bits)  CLUT4 progressive format (CLUT: 4 bits)  CLUT1 progressive format (CLUT: 1 bits)  YCbCr422 progressive format (Y: 8 bits, Cb/Cr: 8 bits; 16 bits in total) (only for graphics 1) Maximum image size to be read: 1024 pixels  1024 lines (horizontal  vertical) Alpha blending in rectangular area: Mixes images according to transparency rate  in the specified area (fade-in and fade-out functions are available.) Chroma-key: Mixes images using the specified RGB color and CLUT value according to transparency rate . Alpha blending in one pixel units: Mixes images according to transparency rate  when the target graphics image is in the RGB1555, RGB4444, RGB8888, or CLUT8/4/1 format. For each dot, the priority among the  values of the above functions is as follows: Alpha blending in rectangular area > Chroma-key > Alpha blending in one pixel units Output video image Maximum output video image size to be set*: 1999 pixels  2035 lines size (horizontal  vertical) Note: * Depends on the AC characteristics of the display panel. Examples of output video image size:     R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SVGA (800  600), WVGA (800  480), VGA (640  480), WQVGA (480  240), QVGA size in landscape (320  240) QVGA size in portrait (240  320) Page 1883 of 3092 Section 31 Video Display Controller 4 (1): Overview Item SH7268 Group, SH7269 Group Function Output video image  format    RGB888 progressive video output (24-bit parallel output) RGB666 progressive video output (18-bit parallel output) RGB565 progressive video output (16-bit parallel output) RGB888 progressive video output (8-bit serial output) Panel output adjustment Panel brightness/contrast adjustment, RGB gamma correction, dither processing, output format conversion Sync signal output Control signal output for the TFT-LCD panel Interrupt output      Page 1884 of 3092 Vsync signal for video image input/output Line interrupt output (can be output on a desired line.) Erroneous Vsync cycle detection signal for video input Field write completion signal Overflow/underflow signal for the internal buffer R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 31.2 Section 31 Video Display Controller 4 (1): Overview Block Diagram Figures 31.1 and 31.2 show the entire block diagram of this module. For details, see the description of each block. This LSI Internal graphics bus (IV2-BUS) DV_DATA 23 to DV_DATA 0 DV_HSYNC DV_VSYNC DV_CLK Internal bus write control or distortion correction Color matrix Video decoder Horizontal noise reduction External input block Sync signal adjustment block Internal graphics bus (IV1-BUS) Internal bus read control (1) Bit reduction Data expansion (1) Vertical scale down Vertical scale up Horizontal scale down Horizontal scale up Scaling-down control block Scaling-up control block Image quality improver block Output selection Graphics block (1) Synchronization control block Input control block Next stage Scaler block Figure 31.1 Video Display Controller 4 Former Stage Block Diagram This LSI Internal graphics bus (IV2-BUS) Interrupt control Clock control LCD_CLK Internal graphics bus (IV3-BUS) Image quality improver block Alpha blending (2) Alpha blending (3) Graphics block (2) Graphics block (3) Image synthesizer Output I/F Data expansion (3) Dither processing Data expansion (2) LCD_DATA 23 to LCD_DATA 0 LCD TCON Internal bus read control (3) Gamma correction Internal bus read control (2) Brightness/contrast adjustment Color matrix Black stretch Previous stage LTI/Sharpness System control block LCD_TCON 6 to LCD_TCON0 Output control block Figure 31.2 Video Display Controller 4 Latter Stage Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1885 of 3092 SH7268 Group, SH7269 Group Section 31 Video Display Controller 4 (1): Overview 31.3 Input/Output Pins Table 31.2 shows the pin configuration. Table 31.2 Pin Configuration Symbol I/O Pin Name Function DV_CLK Input External input clock External input clock pin DV_VSYNC Input External input Vsync External input Vsync signal pin DV_HSYNC Input External input Hsync External input Hsync signal pin DV_DATA 23 to Input DV_DATA 0 External input video image data External input video image data pin LCD_CLK Panel clock Panel output clock pin LCD_DATA 23 Output to LCD_DATA 0 Video image data for panel Panel output video image data pin LCD_TCON 6 to Output LCD_TCON 0 Control signal for panel Panel output timing control pin LCD_EXTCLK Panel clock source Panel clock source input pin Page 1886 of 3092 Output Input R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 31.4 Section 31 Video Display Controller 4 (1): Overview Clocks There are two clocks to be mainly used by the video display controller 4: the video image clock and pixel clock. The video image clock is used while the video image is processed in the input controller, passed to the scale-down control block in the scaler, and then written to the buffer (internal bus write control). When the INP_SEL bit is 0 (video decoder output selected) in INP_SEL_CNT of the input controller, the VIDEO_X1 clock (27 MHz) is used as the video image clock. When INP_SEL is 1 (external input pin selected), the DV_CLK clock is used as the video image clock. The pixel clock is used in graphics read-out processing by the scaler (internal bus read controller) through output controller processing. When the parallel RGB output is selected in the output controller, the frequencies of the pixel clock and panel clock (LCD_CLK) are the same. The panel clock can be selected from the video image clock, LCD_EXTCLK, and peripheral bus clock 1 (P1) with the PANEL_ICKSEL[1:0] bits in SYSCNT_PANEL_CLK of the system controller. When the serial RGB output (3/4 speed mode) is selected in the output controller, the pixel clock frequency is 1/3 or 1/4 the panel clock (LCD_CLK) frequency. Note: Points to be aware of when using LCD_EXTCLK The LCD_EXTCLK signal is multiplexed in three locations: pins PE0, PH5, and PG27. However, it is recommended that pins PE0 and PG27 be used when the digital video decoder is employed. Using pin PH5 can result in the generation of noise on the analog input screen. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1887 of 3092 Section 31 Video Display Controller 4 (1): Overview 31.5 SH7268 Group, SH7269 Group Hsync and Vsync Signals Hsync and Vsync signals to be used in the logic stage following the scale-up control block of the scaler are generated by the synchronization control block of the scaler. Since the Hsync and Vsync signals are used as the reference signals for the LCD TCON, which generates various LCD panel driving timings, they are also the reference signals for the control signals (LCD_TCON6 to LCD_TCON0 pins) passed to the LCD panel. The output Hsync signal always operates at a free-running frequency, and the horizontal period is set with SCL0_FRC4.RES_FH[10:0]. On the other hand, the output Vsync signal is selected from the external input (video decoder or digital pin input) and free-running Vsync signals with SCL0_FRC3.RES_VS_SEL of the scaler. (1) External Input Vsync In this mode, the output Vsync signal is generated according to an external input Vsync signal. For displaying video image input from the video decoder or a digital pin on the panel, always use this mode. However, the output Hsync signal is free running even in this mode. Figure 31.3 shows the timing of external input Vsync signal. Input Vsync signal (DV_VSYNC or Video Decoder VS output) SCL0_FRC5. RES_VSDLY[7:0] setting Vsync signal (Scaler output) Hsync signal (Scaler output) Free-running period SCL0_FRC4.RES_FH[10:0] setting Figure 31.3 External Input Vsync Timing Page 1888 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 31 Video Display Controller 4 (1): Overview Free-Running Vsync In this mode, the Vsync signal is generated according to the pixel clock (free running). The vertical period is selected with SCL0_FRC4.RES_FV[10:0]. The output Hsync signal is also free running. Figure 31.4 shows the timing. SCL0_FRC4.RES_FV[10:0] setting Free-running period Free-running Vsync signal Vsync signal (Scaler output) Hsync signal (Scaler output) Free-running period SCL0_FRC4.RES_FH[10:0] setting Figure 31.4 Free Running Vsync Timing (3) Sync Signal Selection Table 31.3 shows examples of sync signal selection. Table 31.3 Sync Signal Selection External Video Input Graphics Vsync Signal Selected Not displayed Not displayed Not used Not displayed Displayed Free-running Vsync Displayed Not displayed External input Vsync Displayed Displayed External input Vsync Recorded Not displayed Not used Recorded Displayed Free-running Vsync (4) Usage Note on Changing Vsync Signal Selections When the Vsync signal selection is changed, the output Vsync signal is discontinuous, resulting in disordered panel display. In this case, perform the mute processing according to the panel specification as necessary and change the Vsync signal selection. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1889 of 3092 Section 31 Video Display Controller 4 (1): Overview Page 1890 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Section 32 Video Display Controller 4 (2): Input Controller 32.1 32.1.1 Input Controller Functions Overview of Functions The input controller selects either video decoder output signals or signals supplied via the external input pins, and subjects the signals to synchronization adjustment, horizontal noise reduction, and brightness adjustment, gain adjustment, and YCbCr  GBR conversion using a color matrix. The functional block diagram of the input controller is shown below. INP_SEL Sync signal adjustment block INP_FORMAT External input block Color matrix (TINT) HS,VS,HE, VE,FLD, YCbCr/RGB888 (24 bits) Horizontal NR (1, 2, 3, 4 adjacent pixels) HS,VS, YCbCr/ RGB888 (24 bits) Sync delay adjustment HS,VS, YCbCr/ RGB888 (24 bits) HS,VS, YCbCr/RGB888 (24 bits) Sync signal phase compensation HS,VS, YCbCr (24 bits) Vertical sync line delay RGB888/666/565, YCbCr444 interface BT656/601 interface DV_DATA23 to DV_DATA0, DV_HSYNC, DV_VSYNC, DV_CLK, HS,VS, YCbCr (24 bits) Input selection HS,VS, YCbCr(30 bits) Output selection Video decoder Video decoder interface This LSI HS,VS,HE, VE,FLD, YCbCr/RGB888 (24 bits) Scaler Image quality adjustment block Register control Register control Input controller Figure 32.1 Functional Block Diagram of Input Controller R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1891 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.2 Updating Registers of External Signal Input Block and Sync Signal Adjustment Block The control registers of the external input block and sync signal adjustment block are updated by setting the relevant update control bit to 1. For the control registers of the image quality adjustment block, the update timing is controlled using the Vsync signal. After 1 is set to the bits in the update control register, the contents of the relevant registers are actually modified at the rising edge of the Vsync signal, when the update control register is automatically cleared to 0. Table 32.1 Register Update Control Initial Value Register Name Bit Name INP_UPDATE INP_EXT_UPDATE 0 Description External Input Block Register Update 0: Registers are not updated. 1: Registers are updated. INP_UPDATE INP_IMG_UPDATE 0 Sync Signal Adjustment Block Register Update 0: Registers are not updated. 1: Registers are updated. IMGCNT_UPDATE IMGCNT_VEN 0 Image Quality Adjustment Block Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync signal. Page 1892 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.1.3 Section 32 Video Display Controller 4 (2): Input Controller Selecting Input Signals The input controller selects either video decoder output signals or signals supplied via the external input pins. Table 32.2 Input Signal Selection Register Name Bit Name Initial Value Description INP_SEL_CNT INP_SEL 0 Input Select 0: Video decoder output signals 1: Signals supplied via the external input pins R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1893 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.4 Controlling Externally Input Video Signals The externally input video image signals in the YCbCr444, RGB888, RGB666, RGB565, BT656, and BT601 formats can be handled. The BT656 signals can be used for the 525-line and 59.94 Hz (27.0-MHz) and the 625-line and 50.00-Hz (27.0-MHz) interlace signals. The BT601 signals can be used for the 8-bit data line 525-line and 59.94 Hz (27.0-MHz) and the 625-line and 50.00-Hz (27.0-MHz) interlace signals and the 525-line and 59.94 Hz (54.0-MHz) and the 625-line and 50.00-Hz (54.0-MHz) progressive signals. The above signals can be selected by the INP_FORMAT[2:0] bits. Bit endian change and B/R signal swap are controlled by setting the INP_ENDIAN_ON and INP_SWAP_ON bits. Table 32.3 Externally Input Video Signal Control Register Name Bit Name Initial Value Description INP_SEL_CNT INP_FORMAT[2:0] 000 External Input Format Select 0: YCbCr444, RGB888 1: RGB666 2: RGB565 3: BT656 4: BT601 5 to 7: Setting prohibited INP_EXT_ SYNC_CNT INP_ENDIAN_ON 0 External Input Bit Endian Change On/Off Control 0: Off 1: On INP_EXT_ SYNC_CNT INP_SWAP_ON 0 External Input B/R Signal Swap On/Off Control 0: Off 1: On Page 1894 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.1.5 Section 32 Video Display Controller 4 (2): Input Controller Selecting Clock Edge for Externally Input Signals The clock edge for receiving the video image signals, Vsync signals, and Hsync signals is individually selected with the INP_PXD_EDGE, INP_VS_EDGE, INP_HS_EDGE bits. Table 32.4 Externally Input Clock Edge Selection Register Name Bit Name Initial Value Description INP_SEL_CNT INP_PXD_EDGE 0 Clock Edge Select for Capturing External Input Video Image Signals DV_DATA23 to DV_DATA0 0: Rising edge 1: Falling edge INP_SEL_CNT INP_VS_EDGE 0 Clock Edge Select for Capturing External Input Vsync Signal DV_VSYNC 0: Rising edge 1: Falling edge INP_SEL_CNT INP_HS_EDGE 0 Clock Edge Select for Capturing External Input Hsync Signal DV_HSYNC 0: Rising edge 1: Falling edge Figure 32.2 shows the typical input timing of externally input signals. The input signals can be received at the rising edge of the clock signal DV_CLK when the INP_PXD_EDGE, INP_VS_EDGE, and INP_ES_EDGE bits are 0. DV_CLK DV_DATA23 to DV_DATA0 DV_HSYNC DV_VSYNC Figure 32.2 Typical Input Timing of Externally Input Signals (Clock Phase) 32.1.6 Externally Input Sync Signal Inversion Control Inversion of polarity of the Vsync and Hsync signals can be controlled by the INP_VS_INV and INP_HS_INV bits. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1895 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.5 Sync Signal Inversion Control Register Name Bit Name Initial Value Description INP_EXT_ SYNC_CNT INP_VS_INV 0 External Input Vsync Signal DV_VSYNC Inversion Control 0: Not inverted (positive polarity) 1: Inverted (negative polarity) INP_EXT_ SYNC_CNT INP_HS_INV 0 External Input Hsync Signal DV_HSYNC Inversion Control 0: Not inverted (positive polarity) 1: Inverted (negative polarity) 32.1.7 Bit Allocation of Externally Input Video Image Signals Allocation of the externally input video image signal pins DV_DATA to the signals in each format is described below. (1) YCbCr444/RGB888 Input When the external input is of YCbCr444/RGB888 format, the video image signal pins DV_DATA are allocated to the internal signals Y/GOUT, Cb/BOUT, Cr/ROUT, as shown in table 32.6. Page 1896 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.6 Bit Allocation of DV_DATA Pin Inputs when the External Input is of YCbCr444/RGB888 INP_FORMAT[2:0] 0 0 0 0 INP_ENDIAN_ON 0 0 1 1 INP_SWAP_ON 0 1 0 1 DV_DATA23 Cr/ROUT[7] Cb/BOUT[7] Cr/ROUT[0] Cb/BOUT[0] DV_DATA22 Cr/ROUT[6] Cb/BOUT[6] Cr/ROUT[1] Cb/BOUT[1] DV_DATA21 Cr/ROUT[5] Cb/BOUT[5] Cr/ROUT[2] Cb/BOUT[2] DV_DATA20 Cr/ROUT[4] Cb/BOUT[4] Cr/ROUT[3] Cb/BOUT[3] DV_DATA19 Cr/ROUT[3] Cb/BOUT[3] Cr/ROUT[4] Cb/BOUT[4] DV_DATA18 Cr/ROUT[2] Cb/BOUT[2] Cr/ROUT[5] Cb/BOUT[5] DV_DATA17 Cr/ROUT[1] Cb/BOUT[1] Cr/ROUT[6] Cb/BOUT[6] DV_DATA16 Cr/ROUT[0] Cb/BOUT[0] Cr/ROUT[7] Cb/BOUT[7] DV_DATA15 Y/GOUT[7] Y/GOUT[7] Y/GOUT[0] Y/GOUT[0] DV_DATA14 Y/GOUT[6] Y/GOUT[6] Y/GOUT[1] Y/GOUT[1] DV_DATA13 Y/GOUT[5] Y/GOUT[5] Y/GOUT[2] Y/GOUT[2] DV_DATA12 Y/GOUT[4] Y/GOUT[4] Y/GOUT[3] Y/GOUT[3] DV_DATA11 Y/GOUT[3] Y/GOUT[3] Y/GOUT[4] Y/GOUT[4] DV_DATA10 Y/GOUT[2] Y/GOUT[2] Y/GOUT[5] Y/GOUT[5] DV_DATA9 Y/GOUT[1] Y/GOUT[1] Y/GOUT[6] Y/GOUT[6] DV_DATA8 Y/GOUT[0] Y/GOUT[0] Y/GOUT[7] Y/GOUT[7] DV_DATA7 Cb/BOUT[7] Cr/ROUT[7] Cb/BOUT[0] Cr/ROUT[0] DV_DATA6 Cb/BOUT[6] Cr/ROUT[6] Cb/BOUT[1] Cr/ROUT[1] DV_DATA5 Cb/BOUT[5] Cr/ROUT[5] Cb/BOUT[2] Cr/ROUT[2] DV_DATA4 Cb/BOUT[4] Cr/ROUT[4] Cb/BOUT[3] Cr/ROUT[3] DV_DATA3 Cb/BOUT[3] Cr/ROUT[3] Cb/BOUT[4] Cr/ROUT[4] DV_DATA2 Cb/BOUT[2] Cr/ROUT[2] Cb/BOUT[5] Cr/ROUT[5] DV_DATA1 Cb/BOUT[1] Cr/ROUT[1] Cb/BOUT[6] Cr/ROUT[6] DV_DATA0 Cb/BOUT[0] Cr/ROUT[0] Cb/BOUT[7] Cr/ROUT[7] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1897 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller (2) RGB666 Input When the external input is of RGB666 format, the video image signal pins DV_DATA are allocated to the internal signals GOUT, BOUT, ROUT as shown in table 32.7. The internal signals GOUT, BOUT, ROUT to which the video image signal pins DV_DATA are allocated are output as a 24-bit video image from the RGB666 interface with the following formulae. G[7:0] = GOUT[7:2]  255  63 B[7:0] = BOUT[7:2]  255  63 R[7:0] = ROUT[7:2]  255  63 Table 32.7 Bit Allocation of DV_DATA Pin Inputs When the External Input is of RGB666 INP_FORMAT[2:0] 1 1 1 1 INP_ENDIAN_ON 0 0 1 1 INP_SWAP_ON 0 1 0 1 DV_DATA17 ROUT[7] BOUT[7] ROUT[2] BOUT[2] DV_DATA16 ROUT[6] BOUT[6] ROUT[3] BOUT[3] DV_DATA15 ROUT[5] BOUT[5] ROUT[4] BOUT[4] DV_DATA14 ROUT[4] BOUT[4] ROUT[5] BOUT[5] DV_DATA13 ROUT[3] BOUT[3] ROUT[6] BOUT[6] DV_DATA12 ROUT[2] BOUT[2] ROUT[7] BOUT[7] DV_DATA11 GOUT[7] GOUT[7] GOUT[2] GOUT[2] DV_DATA10 GOUT[6] GOUT[6] GOUT[3] GOUT[3] DV_DATA9 GOUT[5] GOUT[5] GOUT[4] GOUT[4] DV_DATA8 GOUT[4] GOUT[4] GOUT[5] GOUT[5] DV_DATA7 GOUT[3] GOUT[3] GOUT[6] GOUT[6] DV_DATA6 GOUT[2] GOUT[2] GOUT[7] GOUT[7] DV_DATA5 BOUT[7] ROUT[7] BOUT[2] ROUT[2] DV_DATA4 BOUT[6] ROUT[6] BOUT[3] ROUT[3] DV_DATA3 BOUT[5] ROUT[5] BOUT[4] ROUT[4] DV_DATA2 BOUT[4] ROUT[4] BOUT[5] ROUT[5] DV_DATA1 BOUT[3] ROUT[3] BOUT[6] ROUT[6] DV_DATA0 BOUT[2] ROUT[2] BOUT[7] ROUT[7] Page 1898 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 32 Video Display Controller 4 (2): Input Controller RGB565 Input When the external input is of RGB565 format, the video image signal pins DV_DATA are allocated to the internal signals GOUT, BOUT, ROUT as shown in table 32.8. The internal signals GOUT, BOUT, ROUT to which the video image signal pins DV_DATA are allocated are output as a 24-bit video image from the RGB565 interface with the following formulae. G[7:0] = GOUT[7:2]  255  63 B[7:0] = BOUT[7:3]  255  31 R[7:0] = ROUT[7:3]  255  31 Table 32.8 Bit Allocation of DV_DATA Pin Inputs When the External Input is of RGB565 INP_FORMAT[2:0] 2 2 2 2 INP_ENDIAN_ON 0 0 1 1 INP_SWAP_ON 0 1 0 1 DV_DATA15 ROUT[7] BOUT[7] ROUT[3] BOUT[3] DV_DATA14 ROUT[6] BOUT[6] ROUT[4] BOUT[4] DV_DATA13 ROUT[5] BOUT[5] ROUT[5] BOUT[5] DV_DATA12 ROUT[4] BOUT[4] ROUT[6] BOUT[6] DV_DATA11 ROUT[3] BOUT[3] ROUT[7] BOUT[7] DV_DATA10 GOUT[7] GOUT[7] GOUT[2] GOUT[2] DV_DATA9 GOUT[6] GOUT[6] GOUT[3] GOUT[3] DV_DATA8 GOUT[5] GOUT[5] GOUT[4] GOUT[4] DV_DATA7 GOUT[4] GOUT[4] GOUT[5] GOUT[5] DV_DATA6 GOUT[3] GOUT[3] GOUT[6] GOUT[6] DV_DATA5 GOUT[2] GOUT[2] GOUT[7] GOUT[7] DV_DATA4 BOUT[7] ROUT[7] BOUT[3] ROUT[3] DV_DATA3 BOUT[6] ROUT[6] BOUT[4] ROUT[4] DV_DATA2 BOUT[5] ROUT[5] BOUT[5] ROUT[5] DV_DATA1 BOUT[4] ROUT[4] BOUT[6] ROUT[6] DV_DATA0 BOUT[3] ROUT[3] BOUT[7] ROUT[7] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1899 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller (4) BT656/BT601 Input When the external input is of BT656 or BT601 format, the video image signal pins DV_DATA are allocated to the internal signal BTOUT, as shown in table 32.9. The internal signal BTOUT to which the video image signal pins DV_DATA are allocated is expanded to the YCbCr signal. For expansion to the YCbCr signal, see section 32.1.11, BT656/BT601 Format Setting. Table 32.9 Bit Allocation of DV_DATA Pin Inputs When the External Input is of BT656 or BT601 INP_FORMAT[2:0] 3 to 4 3 to 4 INP_ENDIAN_ON 0 1 INP_SWAP_ON 0 0 DV_DATA7 BTOUT[7] BTOUT[0] DV_DATA6 BTOUT[6] BTOUT[1] DV_DATA5 BTOUT[5] BTOUT[2] DV_DATA4 BTOUT[4] BTOUT[3] DV_DATA3 BTOUT[3] BTOUT[4] DV_DATA2 BTOUT[2] BTOUT[5] DV_DATA1 BTOUT[1] BTOUT[6] DV_DATA0 BTOUT[0] BTOUT[7] Page 1900 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.1.8 Section 32 Video Display Controller 4 (2): Input Controller Typical Signal Timing of BT601 Format Figures 32.3 and 32.4 show the horizontal timings and figures 32.5 and 32.6 show the vertical timings of the BT601 format. 16:9 or 4:3 at 13.5 MHz 625 0H Analog line n-1 Analog line n Digital line n-1 Digital line n Digital blanking 12T Luminance samples 717 718 719 720 721 132T 730 731 732 733 862 863 0 1 2 4:2:2,chroma CR samples 359 360 365 366 491 0 1 359 360 365 366 491 0 1 4:2:2,chroma C B samples T: Luminance sampling period Quoted from ITU-R BT.601-5 Figure 32.3 BT601 Horizontal Timing (625 Lines/50.00 Hz) 16:9 or 4:3 at 13.5 MHz 525 0H Analog line n-1 Analog line n Digital line n-1 Digital line n Digital blanking Luminance samples 717 16T 718 719 720 721 122T 734 735 736 737 856 857 0 1 2 4:2:2,chroma C R samples 359 360 367 368 428 0 1 359 360 367 368 428 0 1 4:2:2,chroma C B samples T: Luminance sampling period Quoted from ITU-R BT.601-5 Figure 32.4 BT601 Horizontal Timing (525 Lines/59.94 Hz) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1901 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller TOP (First) field Quoted from ITU-R BT.470-6 25H +  2.5H 622 623 624 2.5H 625 BOTTOM field 1 2.5H 2 0V 3 4 5 6 7 23 24 TOP field HS VS FLD BOTTOM (Second) field 25H +  2.5H 309 310 311 TOP field 312 2.5H 313 0V 314 2.5H 315 316 317 318 319 320 336 337 BOTTOM field HS VS FLD Figure 32.5 BT601 Vertical Timing (625 Lines/50.00 Hz) Page 1902 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller TOP (First) field Quoted from ITU-R BT.470-6 19 to 21H +  3.0H 525 BOTTOM field 1 2 0V 3.0H 3 4 3.0H 5 6 7 8 9 10 21 22 TOP field HS VS FLD BOTTOM (Second) field 19 to 21H +  3.0H 262 TOP field 263 264 0V 3.0H 265 266 267 3.0H 268 269 270 271 272 273 283 284 BOTTOM field HS VS FLD Figure 32.6 BT601 Vertical Timing (525 Lines/59.94 Hz) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1903 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.9 Typical Signal Timing of BT656 Format Figures 32.7 and 32.8 show the horizontal timings of the BT601 format. 16:9 or 4:3 at 13.5 MHz 525 0H Analog line n-1 Analog line n Digital line n-1 Digital line n Digital blanking Luminance samples 12T 717 718 719 720 721 132T 730 731 732 733 862 863 0 1 2 4:2:2,chroma CR samples 359 360 365 366 491 0 1 359 360 365 366 491 0 1 Y861 CB419 Y862 CR419 Y863 CB0 Y0 CR0 Y1 Replaced by timing reference signal CB0 Y0 CR0 Y1 DV_DATA7 to DV_DATA0 Replaced by digital blanking data CB359 Y718 CR359 Y719 Replaced by timing reference signal CB366 Y732 CR366 Y733 CB359 Y718 CR359 Y719 CB360 Y720 CR360 Y721 4:2:2,chroma CB samples End of active video T: Luminance sampling period Start of active video Timing reference signal Quoted from ITU-R BT.656-4, ITU-R BT.601-5 DV_HSYNC Figure 32.7 BT656 Horizontal Timing (625 Lines/50.00 Hz) Page 1904 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 16:9 or 4:3 at 13.5 MHz 525 0H Analog line n-1 Analog line n Digital line n-1 Digital line n Digital blanking Luminance samples 16T 717 718 719 720 721 122T 734 735 736 737 856 857 0 1 2 4:2:2,chroma CR samples 359 360 367 368 428 0 1 359 360 367 368 428 0 1 Y855 CB428 Y856 CR428 Y857 CB0 Y0 CR0 Y1 Replaced by timing reference signal CB0 Y0 CR0 Y1 DV_DATA7 to DV_DATA0 Replaced by digital blanking data CB359 Y718 CR359 Y719 Replaced by timing reference signal CB368 Y736 CR368 Y737 CB359 Y718 CR359 Y719 CB360 Y720 CR360 Y721 4:2:2,chroma CB samples End of active video T: Luminance sampling period Start of active video Timing reference signal Quoted from ITU-R BT.656-4, ITU-R BT.601-5 DV_HSYNC Figure 32.8 BT656 Horizontal Timing (525 Lines/59.94 Hz) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1905 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.10 SAV/EAV Code in BT656 Format Table 32.10 shows the timing of inserting the SAV/EAV code in the BT656 format. Bit information is shown in tables 32.11 and 32.12. This module does not refer to the parity bits P3 to P0 shown in table 32.12. Table 32.10 SAV/EAV Code Insertion Timing (Line) 625 525 Line 624 Line 1 Line 23 Line 20 Line 311 Line 264 Line 336 Line 283 V-digital field blanking Field 1 Start (V = 1) Finish (V = 0) Field 2 Start (V = 1) Finish (V = 0) V-digital field blanking Field 1 F=0 Line 1 Line 4 Field 2 F=1 Line 313 Line 266 Page 1906 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.11 SAV/EAV Code Bit Information (1) Data Bit Number 1st Word (FF) 2nd Word (00) 3rd Word (00) 4th Word (XY) 7 (MSB) 1 0 0 1 6 1 0 0 F 5 1 0 0 V 4 1 0 0 H 3 1 0 0 P3 2 1 0 0 P2 1 1 0 0 P1 0 1 0 0 P0 [Legend] F = 0 during field 1 F = 1 during field 2 V = 0 elsewhere V = 1 during field blanking H = 0 is SAV H = 1 is EAV Table 32.12 SAV/EAV Code Bit Information (2) F V H P3 P2 P1 P0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1907 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Figures 32.9 and 32.10 show the SAV/EAV code tables. One Horizontal Period EAV H blank SAV Valid area 1 2 3 4 285 286 287 288 289 290 291 292 … 1725 1726 1727 1728 1 FF 00 00 B6 FF 00 00 AB : FF 00 00 B6 FF 00 00 AB 22 FF 00 00 B6 FF 00 00 AB 23 FF 00 00 9D FF 00 00 80 Cb0 : FF 00 00 9D FF 00 00 80 : : Field1 : FF 00 00 9D FF 00 00 80 : : (top) : FF 00 00 9D FF 00 00 80 : : FF 00 00 9D FF 00 00 80 : : : FF 00 00 9D FF 00 00 80 : : 310 FF 00 00 9D FF 00 00 80 Cb0 311 FF 00 00 B6 FF 00 00 AB 312 FF 00 00 B6 FF 00 00 AB 313 FF 00 00 F1 FF 00 00 EC FF 00 00 F1 FF 00 00 EC 335 FF 00 00 F1 FF 00 00 EC 336 FF 00 00 DA FF 00 00 C7 Cb0 Digital Blanking Data Y0 Cr0 Y1 … Cb718 Y718 Cr718 Y719 Valid pixel data area Y0 Cr0 Y1 … : Cb718 Y718 Cr718 Y719 Digital Blanking Data Field2 (bottom) : Digital Blanking Data Y0 Cr0 Y1 … Cb718 Y718 Cr718 Y719 : FF 00 00 DA FF 00 00 C7 : : : FF 00 00 DA FF 00 00 C7 : : : FF 00 00 DA FF 00 00 C7 : : FF 00 00 DA FF 00 00 C7 : : : FF 00 00 DA FF 00 00 C7 : : 623 FF 00 00 DA FF 00 00 C7 Cb0 624 FF 00 00 F1 FF 00 00 EC 625 FF 00 00 F1 FF 00 00 EC Valid pixel data area Y0 Cr0 Y1 … : Cb718 Y718 Cr718 Y719 Digital Blanking Data Figure 32.9 SAV/EAV Code in BT656 Format (625 Lines/50.00 Hz) Page 1908 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller One Horizontal Period EAV 1 2 3 H blank 4 SAV Valid area 273 274 275 276 277 278 279 280 … 1713 1714 1715 1716 1 FF 00 00 F1 FF 00 00 EC 2 FF 00 00 F1 FF 00 00 EC 3 FF 00 00 F1 FF 00 00 EC 4 FF 00 00 B6 FF 00 00 AB : FF 00 00 B6 FF 00 00 AB 19 FF 00 00 B6 FF 00 00 AB 20 FF 00 00 9D FF 00 00 80 Cb0 : FF 00 00 9D FF 00 00 80 : Field1 : FF 00 00 9D FF 00 00 80 : (top) : FF 00 00 9D FF 00 00 80 : : FF 00 00 9D FF 00 00 80 : : : FF 00 00 9D FF 00 00 80 : : 263 FF 00 00 9D FF 00 00 80 Cb0 264 FF 00 00 B6 FF 00 00 AB 265 FF 00 00 B6 FF 00 00 AB 266 FF 00 00 F1 FF 00 00 EC Field2 Digital Blanking Data Digital Blanking Data Y0 Cr0 Y1 … Cb718 Y718 Cr718 Y719 : : : Valid pixel data area Y0 Cr0 Y1 … Cb718 Y718 Cr718 Y719 Digital Blanking Data Field2 (bottom) FF 00 00 F1 FF 00 00 EC 282 FF : 00 00 F1 FF 00 00 EC Digital Blanking Data 283 FF 00 00 DA FF 00 00 C7 Cb0 Y0 Cr0 Y1 … Cb718 Y718 Cr718 Y719 : FF 00 00 DA FF 00 00 C7 : : : FF 00 00 DA FF 00 00 C7 : : : FF 00 00 DA FF 00 00 C7 : : FF 00 00 DA FF 00 00 C7 : : : FF 00 00 DA FF 00 00 C7 : : 525 FF 00 00 DA FF 00 00 C7 Cb0 : Valid pixel data area Y0 Cr0 Y1 … Cb718 Y718 Cr718 Y719 Figure 32.10 SAV/EAV Code in BT656 Format (525 Lines/59.94 Hz) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1909 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.11 BT656/BT601 Format Setting The BT656 format can be used for the 525-line and 59.94-Hz and the 625-line and 50.00-Hz interlace signal format. The BT601 format can be used for the 525-line and 59.94 Hz and the 625-line and 50.00-Hz interlace signal format and progressive signal format. The Vsync signal timing for the 525-line BT656 format and 625-line BT656 format are different. The operating mode is set by the INP_F525_625 bit. Table 32.13 Operating Mode Setting for BT656 Format Register Name Bit Name Initial Value INP_EXT_SYNC_CNT INP_F525_625 0 Description Number of Lines for BT656 Input of External Input System 0: 525 lines 1: 625 lines When the interlace signals are to be input in BT656/BT601 format, half of 2fH phase timings of the Vsync signal and the Hsync signal are set with the INP_FH50[9:0] bits. The INP_FH50[9:0] bits are also used for the vertical synchronous phase adjustment block. Therefore, for bit description, see table 32.17. When the external input is of BT656 format, the reference point of the Hsync signal is set with the INP_H_EDGE_SEL bit. Table 32.14 Hsync Signal Reference Selection for BT656 Format Initial Value Register Name Bit Name INP_EXT_SYNC_CNT INP_H_EDGE_ 0 SEL Description Hsync Signal Reference Select for BT656 Format of External Input System 0: EAV 1: SAV Page 1910 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller When the external input is of BT656/BT601 format, the internal signal BTOUT[7:0], which is input from the DV_DATA pins and allocated, is expanded to the 24-bit YCbCr signal. Expansion timing with respect to the Hsync signal reference is set with the INP_H_POS[1:0] bits. [INP_H_POS[1:0] = 0] [INP_H_POS[1:0] = 2] DV_HSYNC DV_HSYNC BTOUT[7:0] ... Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 ... YOUT[7:0] XX XX Y0 Y1 Y2 Y3 ... Y4 ... ... Y5 ... ... ... ... BTOUT[7:0] ... ... ... YOUT[7:0] XX ... Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 ... XX XX Y0 Y1 Y2 Y3 ... Y4 ... ... Y5 ... ... CBOUT[7:0] XX Cb0 Cb2 Cb4 ... CBOUT[7:0] XX XX Cb0 Cb2 Cb4 ... CROUT[7:0] XX Cr0 Cr2 Cr4 ... CROUT[7:0] XX XX Cr0 Cr2 Cr4 ... [INP_H_POS[1:0] = 1] [INP_H_POS[1:0] = 3] DV_HSYNC DV_HSYNC BTOUT[7:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 ... YOUT[7:0] XX XX Y0 Y1 Y2 Y3 ... Y4 ... Y5 ... ... ... BTOUT[7:0] ... ... ... ... YOUT[7:0] XX ... Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 ... XX XX Y0 Y1 Y2 Y3 ... Y4 ... Y5 ... ... ... ... ... CBOUT[7:0] XX Cb0 Cb2 Cb4 ... ... CBOUT[7:0] XX XX Cb0 Cb2 Cb4 ... CROUT[7:0] XX Cr0 Cr2 Cr4 ... ... CROUT[7:0] XX XX Cr0 Cr2 Cr4 ... Figure 32.11 YCbCr Data Expansion for BT656/BT601 Input Table 32.15 Data String Start Timing Selection Register Name Bit Name Initial Value Description INP_EXT_SYNC_CNT INP_H_POS[1:0] 0 Y/Cb/Y/Cr Data String Start Timing with respect to Hsync Reference 0: Cb/Y/Cr/Y 1: Y/Cr/Y/Cb 2: Cr/Y/Cb/Y 3: Y/Cb/Y/Cr R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1911 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.12 YCbCr444/RBG888/666/565 Input Timing The YCbCr444/RGB888/666/565 format can be used for the progressive YCbCr/RGB signal. The sync signal width (H_SYNC, V_SYNC), sync signal polarity (H_POL, V_POL), valid period start position (H_BP, V_BP), valid period end position (H_FP, V_FP), and valid period video width (H_ACTIVE, V_ACTIVE) are shown in table 32.16. Table 32.16 YCbCr/RGB Signal Reception Timing Item Description External input clock Maximum external input clock frequency: 66.67 MHz Vsync signal width (V_SYNC) Minimum Vsync signal width: 1 CLK Vsync signal polarity (V_POL) Positive or negative polarity is selected by the relevant registers. Vertical valid period start position (V_BP) From Vsync reference to the head of the video image: 5 lines or more Vertical valid period video width (V_ACTIVE) Maximum vertical valid period: 1024 lines Vertical valid period end position (V_FP) From the end of the video image to the Vsync reference: 4 lines or more*1 Hsync signal width (H_SYNC) Minimum Hsync signal width: 1 CLK Hsync signal polarity (H_POL) Positive or negative polarity is selected by the relevant registers. Horizontal valid period start position (H_BP) From Hsync reference to the head of the video image: 16 CLK or more Horizontal valid period video width (H_ACTIVE) Maximum horizontal valid period: 1024 pixels Horizontal valid period end position (H_FP) From the end of the video image to the Hsync reference: 16 CLK or more*2 Number of vertical lines (V_BP+V_ACTIVE+V_FP) Between vertical synchronization signals: 2047 lines or less Number of horizontal pixels (H_BP+H_ACTIVE+H_FP) Between horizontal synchronization signals: 2047 CLK or less Notes: 1. When V_FP is below 4 lines, the setting of INP_DLY_ADJ.INP_VS_DLY_L[2:0] should be adjusted so that V_FP is at least 4 lines. 2. When H_FP is below 16 CLK, the settings of INP_DLY_ADJ.INP_VS_DLY[7:0], INP_HS_DLY[7:0], and INP_FLD_DLY[7:0] should be adjusted so that H_FP is at least 16 CLK. Page 1912 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller H_SYNC H_BP H_ACTIVE H_FP DV_HSYNC V_SYNC V_BP V_ACTIVE Valid image area DV_VSYNC V_FP Figure 32.12 YCbCr/RGB Signal Reception Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1913 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.13 Field Differentiation and Vsync Signal Phase Adjustment The phase of the input Vsync signal and Hsync signal is detected and the field of the interlace signal is determined. When the reference point of the Vsync signal is detected within 0.5 horizontal period with respect to the Hsync signal, it is determined as the interlace top field. When the reference point of the Vsync signal is detected outside 0.5 horizontal period with respect to the Hsync signal, it is determined as the interlace bottom field. [Interlace (TOP), progressive] →Top HSIN VSIN 1/4fH 1/4fH Not affected by the falling timing 1/2fH 1fH VSOUT 1fH FLDOUT [Interlace (BOTTOM)] →Bottom HSIN VSIN 1/4fH 1/4fH Not affected by the falling timing 1/2fH VSOUT FLDOUT 1fH 1fH Figure 32.13 Vsync Signal Phase Adjustment The timings of 1/2fH Vsync signal phase and 1/4fH Vsync signal phase are set with INP_FH50[9:0] and INP_FH25[9:0], respectively. Page 1914 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.17 Vsync Signal Phase Timing Setting Register Name Bit Name Initial Value Description INP_VSYNC_PH_ADJ INP_HF50[9:0] 858 Vsync Signal 1/2fH Phase Timing Should be 1/2 the horizontal cycle. INP_VSYNC_PH_ADJ INP_FH25[9:0] 429 Vsync Signal 1/4fH Phase Timing Should be 1/4 the horizontal cycle. 32.1.14 Vsync Signal Delay Adjustment in Line Units The Vsync signal line delay adjust block can delay the Vsync signal and the field differentiation signal in line units. When a video signal with a short vertical front porch is input, the vertical front porch is adjusted. VSIN FLDIN HSIN VSOUT INP_VS_DLY_L[2:0] = 4 4 lines INP_VS_DLY_L[2:0] = 4 4 lines FLDOUT HSOUT Figure 32.14 Timing of Vsync Signal Delay in Line Units Table 32.18 Adjustment of Vsync Signal Delay in Line Units Register Name Bit Name INP_DLY_ADJ INP_VS_DLY_ L[2:0] Initial Value 0 Description Number of Lines for Delaying Vsync Signal and Field Differentiation Signal Delay amount: 0 to 7 (lines) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1915 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.1.15 Sync Signal Delay Adjustment Delay can be adjusted independently for the Vsync signal, Hsync signal, and field differentiation signal in the units of clock. Lacking margin of the horizontal front porch is adjusted according to the input synchronization disturbance. Table 32.19 Sync Signal Delay Adjustment Register Name Bit Name Initial Value Description INP_DLY_ADJ INP_VS_DLY[7:0] 0 Vsync Signal Delay Amount Delay amount: 0 to 254 (clock cycles) INP_DLY_ADJ INP_HS_DLY[7:0] 0 Hsync Signal Delay Amount Delay amount: 0 to 254 (clock cycles) INP_DLY_ADJ INP_FLD_DLY[7:0] 0 Field Differentiation Signal Delay Amount Delay amount: 0 to 254 (clock cycles) 32.1.16 Horizontal Noise Reduction Noise can be reduced according to horizontal pixel reference. Noise reduction is controlled through noise component frequency band (TAP), noise level (threshold), and noise reduction intensity (gain). (1) Frequency Band (TAP) Setting for Noise Component The noise frequency band can be selected independently from the following four types by using the NR1D_Y_TAP[1:0], NR1D_CB_TAP[1:0], and NR1D_CR_TAP[1:0] bits. When the number of adjacent pixels is one (noise reduction NR1D_Y/CB/CR_TAP is 0): BPF(1)   1  1  Z ( 1) , 2  Z (0 ) ,  1  Z ( 1) 4  When the number of adjacent pixels is two (noise reduction NR1D_Y/CB/CR_TAP is 1): BPF( 2)  Page 1916 of 3092  1  1  Z (  2 ) , 2  Z ( 0 ) ,  1  Z ( 2 ) 4  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller When the number of adjacent pixels is three (noise reduction NR1D_Y/CB/CR_TAP is 2): BPF(3 )   1  1  Z ( 3 ) , 2  Z (0 ) ,  1  Z ( 3 ) 4  When the number of adjacent pixels is four (noise reduction NR1D_Y/CB/CR_TAP is 3): BPF( 4)   1  1  Z ( 4 ) , 2  Z (0 ) ,  1  Z ( 4 ) 4  Note: Z(0) indicates the target pixel for noise reduction and Z(N) indicates the pixel that is n pixels off from Z(0) In the horizontal direction. (2) Setting Noise Level (Threshold) The absolute value of the detected noise amount (BPF output value) is compared with the values of the NR1D_Y_TH[6:0], NR1D_CB_TH[6:0], and NR1D_CR_TH[6:0] bits. When the detected noise amount is greater than NR1D_Y/CB/CR_TH, the absolute value of the detected noise amount is considered as NR1D_Y/CB/CR_TH (fixed value). ABS(BPF(n))  absolute value of detected noise amount when ABS(BPF(n))  NR1D_Y/CB/CR_TH: NOISE_ABS = ABS(BPF(n)) ABS(BPF(n)) > absolute value of detected noise amount when ABS(BPF(n)) > NR1D_Y/CB/CR_TH: NOISE_ABS = NR1D_Y/CB/CR_TH (3) Setting Noise Reduction Intensity (Gain) The absolute value of the detected noise amount is multiplied by the value of gain specified by the NR1D_Y_GAIN[1:0], NR1D_CB_GAIN[1:0], and NR1D_CR_GAIN[1:0] bits, and the feedback is calculated for the original signal. Computation when the amount of detected noise (BPF(n)) is negative (): DOUT = DIN + NOISE_ABS  2(NR1D_Y/CB/CR_GAIN+1) Computation when the amount of detected noise (BPF(n) is positive (+): DOUT = DIN – (NR1D_Y/CB/CR_GAIN+1) NOISE_ABS  2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1917 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.20 Horizontal Noise Reduction Register Name Bit Name Initial Value IMGCNT_NR_CNT0 NR1D_MD 1 Description Horizontal Noise Reduction Operating Mode 0: R/G/B mode 1: Y/Cb/Cr mode IMGCNT_NR_CNT0 NR1D_ON 0 Noise Reduction On/Off Control 0: Noise Reduction Off 1: Noise Reduction On IMGCNT_NR_CNT0 NR1D_Y_TAP[1:0] 0 Y/G Signal TAP Select 0: Adjacent pixel 1: 2 adjacent pixels 2: 3 adjacent pixels 3: 4 adjacent pixels IMGCNT_NR_CNT0 NR1D_Y_TH[6:0] 8 Maximum Value (Absolute Value) of Y/G Signal Coring Coring is implemented when detected noise amount value  NR1D_Y_TH. Unsigned: 0 to 127 [LSB] IMGCNT_NR_CNT0 NR1D_Y_GAIN[1:0] 3 Noise Reduction Gain Adjustment of Y/G Signal 0: 1/2 1: 1/4 2: 1/8 3: 1/16 IMGCNT_NR_CNT1 NR1D_CB_TAP[1:0] 0 Cb/B Signal TAP Select 0: Adjacent pixel 1: 2 adjacent pixels 2: 3 adjacent pixels 3: 4 adjacent pixels IMGCNT_NR_CNT1 NR1D_CB_TH[6:0] 8 Maximum Value (Absolute Value) of Cb/B Signal Coring Coring is implemented when detected noise amount value  NR1D_C_TH. Unsigned: 0 to 127 [LSB] Page 1918 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Bit Name Bit Name Initial Value IMGCNT_NR_CNT1 NR1D_CB_GAIN[1:0] 3 Description Noise Reduction Gain Adjustment of Cb/B Signal 0: 1/2 1: 1/4 2: 1/8 3: 1/16 IMGCNT_NR_CNT1 NR1D_CR_TAP[1:0] 0 Cr/R Signal TAP Select 0: Adjacent pixel 1: 2 adjacent pixels 2: 3 adjacent pixels 3: 4 adjacent pixels IMGCNT_NR_CNT1 NR1D_CR_TH[6:0] 8 Maximum Value (Absolute Value) of Cr/R Signal Coring Coring is implemented when detected noise amount value  NR1D_C_TH. Unsigned: 0 to 127 [LSB] IMGCNT_NR_CNT1 NR1D_CR_GAIN[1:0] 3 Noise Reduction Gain Adjustment of Cr/R Signal 0: 1/2 1: 1/4 2: 1/8 3: 1/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1919 of 3092 Section 32 Video Display Controller 4 (2): Input Controller SH7268 Group, SH7269 Group 32.1.17 Color Matrix By using a color matrix, input signal offsets and nine-axis gain can be adjusted. This enables brightness adjustment, gain adjustment, and YCbCr and GBR mutual conversion. (1) GBR to GBR Conversion YGIN_A = YGIN + IMGCNT_MTX_YG – 128 CBBIN_A = CBBIN + IMGCNT_MTX_B – 128 CRRIN_A = CRRIN + IMGCNT_MTX_R – 128 YGOUT = (IMGCNT_MTX_GG×YGIN_A + IMGCNT_MTX_GB×CBBIN_A + IMGCNT_MTX_GR×CRRIN_A)  256 CBBOUT = (IMGCNT_MTX_BG×YGIN_A + IMGCNT_MTX_BB×CBBIN_A + IMGCNT_MTX_BR×CRRIN_A)  256 CRROUT = (IMGCNT_MTX_RG×YGIN_A + IMGCNT_MTX_RB×CBBIN_A + IMGCNT_MTX_RR×CRRIN_A)  256 (2) GBR to YCbCr Conversion YGIN_A = YGIN + IMGCNT_MTX_YG – 128 CBBIN_A = CBBIN + IMGCNT_MTX_B – 128 CRRIN_A = CRRIN + IMGCNT_MTX_R – 128 YGOUT = (IMGCNT_MTX_GG×YGIN_A + IMGCNT_MTX_GB×CBBIN_A + IMGCNT_MTX_GR×CRRIN_A)  256 CBBOUT = (IMGCNT_MTX_BG×YGIN_A + IMGCNT_MTX_BB×CBBIN_A + IMGCNT_MTX_BR×CRRIN_A)  256 + 128 CRROUT = (IMGCNT_MTX_RG×YGIN_A + IMGCNT_MTX_RB×CBBIN_A + IMGCNT_MTX_RR×CRRIN_A)  256 + 128 Page 1920 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.21 Matrix Coefficient (Typical Value) for SMPTE 293M YGIN CBBIN CRRIN Coefficient Set Value Coefficient Set Value 0.587 IMGCNT_ MTX_GG = 150 0.114 IMGCNT_MTX 0.299 _GB = 29 IMGCNT_MTX _GR = 77 CBBOUT –0.331 IMGCNT_ MTX_BG = 1963 0.500 IMGCNT_MTX –0.169 _BB = 128 IMGCNT_MTX _BR = 2005 CRROUT –0.419 IMGCNT_ MTX_RG = 1941 –0.081 IMGCNT_MTX 0.500 _RB = 2027 IMGCNT_MTX _RR = 128 YGOUT (3) Coefficient Set Value YCbCr to GBR Conversion YGIN_A = YGIN + IMGCNT_MTX_YG – 128 CBBIN_A = CBBIN – 128 CRRIN_A = CRRIN – 128 YGOUT = (IMGCNT_MTX_GG×YGIN_A + IMGCNT_MTX_GB×CBBIN_A + IMGCNT_MTX_GR×CRRIN_A)  256 CBBOUT = (IMGCNT_MTX_BG×YGIN_A + IMGCNT_MTX_BB×CBBIN_A + IMGCNT_MTX_BR×CRRIN_A)  256 CRROUT = (IMGCNT_MTX_RG×YGIN_A + IMGCNT_MTX_RB×CBBIN_A + IMGCNT_MTX_RR×CRRIN_A)  256 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1921 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.22 Matrix Coefficient (Typical Value) for SMPTE 293M YGIN CBBIN CRRIN Coefficient Set Value Coefficient Set Value 1.000 IMGCNT_ MTX_GG = 256 –0.344 IMGCNT_MTX –0.714 _GB = 1960 IMGCNT_MTX _GR = 1865 CBBOUT 1.000 IMGCNT_ MTX_BG = 256 1.772 IMGCNT_MTX 0.000 _BB = 454 IMGCNT_MTX _BR = 0 CRROUT 1.000 IMGCNT_ MTX_RG = 256 0.000 IMGCNT_MTX 1.402 _RB = 0 IMGCNT_MTX _RR = 359 YGOUT (4) Coefficient Set Value YCbCr to YCbCr Conversion YGIN_A = YGIN + IMGCNT_MTX_YG – 128 CBBIN_A = CBBIN – 128 CRRIN_A = CRRIN – 128 YGOUT = (IMGCNT_MTX_GG×YGIN_A + IMGCNT_MTX_GB×CBBIN_A + IMGCNT_MTX_GR×CRRIN_A)  256 CBBOUT = (IMGCNT_MTX_BG×YGIN_A + IMGCNT_MTX_BB×CBBIN_A + IMGCNT_MTX_BR×CRRIN_A)  256 + 128 CRROUT = (IMGCNT_MTX_RG×YGIN_A + IMGCNT_MTX_RB×CBBIN_A + IMGCNT_MTX_RR×CRRIN_A)  256 + 128 Page 1922 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.23 YCbCr to GBR Conversion Register Name Bit Name IMGCNT_MTX_MODE IMGCNT_MTX_MD [1:0] Initial Value Description 3 Operating Mode 0: GBR  GBR 1: GBR  YCbCr 2: YCbCr  GBR 3: YCbCr  YCbCr IMGCNT_MTX_YG_ ADJ0 IMGCNT_MTX_YG [7:0] 128 IMGCNT_MTX_CBB_ ADJ0 IMGCNT_MTX_B [7:0] 128 IMGCNT_MTX_CRR_ ADJ0 IMGCNT_MTX_R [7:0] 128 IMGCNT_MTX_YG_ ADJ0 IMGCNT_MTX_GG [10:0] 256 Offset (DC) Adjustment of Y/G Signal Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB], 512 [LSB]) Offset (DC) Adjustment of B Signal Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) Offset (DC) Adjustment of R Signal Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) Y/G Signal Gain Adjustment for Y/G Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_YG_ ADJ1 IMGCNT_MTX_GB [10:0] 0 Cb/B Signal Gain Adjustment for Y/G Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_YG_ ADJ1 IMGCNT_MTX_GR [10:0] 0 Cr/R Signal Gain Adjustment for Y/G Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_CBB_ ADJ0 IMGCNT_MTX_BG [10:0] 0 Y/G Signal Gain Adjustment for Cb/B Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_CBB_ ADJ1 IMGCNT_MTX_BB [10:0] 256 Cb/B Signal Gain Adjustment for Cb/B Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1923 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Bit Name Bit Name IMGCNT_MTX_CBB_ ADJ1 IMGCNT_MTX_BR [10:0] Initial Value 0 Description Cr/R Signal Gain Adjustment for Cb/B Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_CRR_ ADJ0 IMGCNT_MTX_RG [10:0] 0 Y/G Signal Gain Adjustment for Cr/R Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_CRR_ ADJ1 IMGCNT_MTX_RB [10:0] 0 Cb/B Signal Gain Adjustment for Cr/R Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) IMGCNT_MTX_CRR_ ADJ1 IMGCNT_MTX_RR [10:0] 256 Cr/R Signal Gain Adjustment for Cr/R Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Page 1924 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.2 Section 32 Video Display Controller 4 (2): Input Controller Register Descriptions Tables 32.24 and 32.25 show register Configuration.  Symbols used in Register Description: Initial value: Register value after a power-on reset : Undefined value R/W: Readable/writable. The written value can be read. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored. R/WC1: Readable/writable. Writing 1 initializes the bit. Writing 0 is ignored. R: Read-only. The write value should always be 0. /W: Write-only. The read value is undefined. Table 32.24 Register Configuration of Input Controller Address Access Size R/WC1 H'0000 0000 H'FFFF 7400 32/16 R/W H'0000 0000 H'FFFF 7404 32/16 External input sync signal control register INP_EXT_SYNC_CNT R/W H'0000 0000 H'FFFF 7408 32/16 Vsync signal phase adjustment register INP_VSYNC_PH_ADJ R/W H'035A 01AD H'FFFF 740C 32/16 Sync signal delay adjustment register INP_DLY_ADJ H'0000 0000 H'FFFF 7410 32/16 Name Abbreviation R/W External input block register update control register INP_UPDATE Input select control register INP_SEL_CNT R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R/W Initial Value Page 1925 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.25 Register Configuration of Image Quality Adjustment Block Address Access Size R/WC1 H'0000 0000 H'FFFF 7480 32/16 IMGCNT_NR_CNT0 R/W H'0010 0803 H'FFFF 7484 32/16 IMGCNT_NR_CNT1 R/W H'0803 0803 H'FFFF 7488 32/16 Image quality IMGCNT_MTX_MODE R/W adjustment block matrix mode register H'0000 0003 H'FFFF 74A0 32/16 Image quality IMGCNT_MTX_YG_ adjustment block matrix ADJ0 YG adjustment register 0 R/W H'0080 0100 H'FFFF 74A4 32/16 Image quality IMGCNT_MTX_YG_ adjustment block matrix ADJ1 YG adjustment register 1 R/W H'0000 0000 H'FFFF 74A8 32/16 Image quality IMGCNT_MTX_CBB_ adjustment block matrix ADJ0 CBB adjustment register 0 R/W H'0080 0000 H'FFFF 74AC 32/16 Image quality IMGCNT_MTX_CBB_ adjustment block matrix ADJ1 CBB adjustment register 1 R/W H'0100 0000 H'FFFF 74B0 32/16 Image quality IMGCNT_MTX_CRR_ adjustment block matrix ADJ0 CRR adjustment register 0 R/W H'0080 0000 H'FFFF 74B4 32/16 Image quality IMGCNT_MTX_CRR_ adjustment block matrix ADJ1 CRR adjustment register 1 R/W H'0000 0100 H'FFFF 74B8 32/16 Name Abbreviation R/W Image quality adjustment block register update control register IMGCNT_UPDATE NR control register 0 NR control register 1 Page 1926 of 3092 Initial Value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.2.1 Section 32 Video Display Controller 4 (2): Input Controller External Input Block Register Update Control Register (INP_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            INP_EXT_ UPDATE    INP_IMG_ UPDATE Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/WC1 R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 INP_EXT_ UPDATE 0 R/WC1 External Input Block Register Update  All 0 0: Registers are not updated. 1: Registers are updated. 3 to 1 R Reserved These bits are always read as 0. The write value should always be 0. 0 INP_IMG_ UPDATE 0 R/WC1 Sync Signal Adjustment Block Register Update 0: Registers are not updated. 1: Registers are updated. 32.2.2 Input Select Control Register (INP_SEL_CNT) Bit: 31 30 29 28 27 26 25 24 23 22 21            Initial Value: 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    INP_ PXD_ EDGE    INP_ VS_ EDGE    INP_ HS_ EDGE  INP_FORMAT[2:0] 19 18 17 16     0 20 INP_ SEL 0 0 0 0 0 R R/W R R R R Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R R R/W R R R R/W R R R R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1927 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 INP_SEL 0 R/W Input Select 0: Video decoder output signals 1: Signals supplied via the external input pins 19 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14 to 12 INP_ FORMAT [2:0] 0 R/W External Input Format Select 0: YcbCr444, RGB888 1: RGB666 2: RGB565 3: BT656 4: BT601 5 to 7: Setting prohibited 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 INP_PXD_ EDGE 0 R/W Clock Edge Select for Capturing External Input Video Image Signals DV_DATA23 to DV_DATA0 0: Rising edge 1: Falling edge 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 INP_VS_ EDGE 0 R/W Clock Edge Select for Capturing External Input Vsync Signals DV_VSYNC 0: Rising edge 1: Falling edge 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1928 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 0 INP_HS_ EDGE Section 32 Video Display Controller 4 (2): Input Controller Initial Value R/W Description 0 R/W Clock Edge Select for Capturing External Input Hsync Signals DV_HSYNC 0: Rising edge 1: Falling edge Note: INP_FORMAT, INP_PXD_EDGE, INP_VS_EDGE, and INP_HS_EDGE are updated when the INP_EXT_UPDATE bit in INP_UPDATE is 1. INP_SEL is updated when set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1929 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.3 External Input Sync Signal Control Register (INP_EXT_SYNC_CNT) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16    INP_ ENDIAN_ ON    INP_ SWAP_ ON    INP_ VS_INV    INP_ HS_INV Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        INP_ H_EDGE_ SEL    INP_ F525_625   - INP_H_POS[1:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R R R R/W R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 29  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 28 27 to 25 INP_ ENDIAN_ ON 0  All 0 R/W External Input Bit Endian Change On/Off Control 0: Off 1: On R Reserved These bits are always read as 0. The write value should always be 0. 24 INP_ 0 SWAP_ON R/W External Input B/R Signal Swap On/Off Control 0: Off 1: On 23 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 INP_VS_ INV 0 R/W External Input Vsync Signal DV_VSYNC Inversion Control 0: Not inverted (positive polarity) 1: Inverted (negative polarity) 19 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 1930 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 16 INP_HS_ INV Section 32 Video Display Controller 4 (2): Input Controller Initial Value R/W Description 0 R/W External Input Hsync Signal DV_HSYNC Inversion Control 0: Not inverted (positive polarity) 1: Inverted (negative polarity) 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 INP_H_ 0 EDGE_SEL R/W Reference Select for External Input BT656 Hsync Signal 0: EAV 1: SAV 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 INP_F525_ 0 625 R/W  R Number of Lines for BT656 External Input 0: 525 lines 1: 625 lines 3, 2 All 0 Reserved These bits are always read as 0. The write value should always be 0. 1, 0 INP_H_ POS[1:0] 0 R/W Y/Cb/Y/Cr Data String Start Timing to Hsync Reference for BT656/601 External Input 0: Cb/Y/Cr/Y 1: Y/Cr/Y/Cb 2: Cr/Y/Cb/Y 3: Y/Cb/Y/Cr Note: This register is updated when the INP_EXT_UPDATE bit in INP_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1931 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.4 Vsync Signal Phase Adjustment Register (INP_VSYNC_PH_ADJ) Bit: 31 30 29 28 27 26 25 24       - - 23 22 - 21 20 INP_FH50[9:0] - 19 18 17 16 - - - - Initial Value: 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 5 4       - - 6 - INP_FH25[9:0] - 3 2 1 0 - - - - Initial Value: 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 INP_FH50 [9:0] 858  All 0 R/W Vsync Signal 1/2fH Phase Timing 1/2 clock cycle of the horizontal cycle should be set. R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 INP_FH25 [9:0] 429 R/W Vsync Signal 1/4fH Phase Timing 1/4 clock cycle of the horizontal cycle should be set. Note: The INP_FH50[9:0] bits are updated when the INP_EXT_UPDATE and INP_IMG_UPDATE bits in INP_UPDATE are 1. The IMP_FH25[9:0] bits are updated when the INP_IMG_UPDATE bit is 1. 32.2.5 Sync Signal Delay Adjustment Register (INP_DLY_ADJ) Bit: 31 30 29 28 27      Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 - - Initial Value: 0 R/W: R/W Page 1932 of 3092 26 25 24 INP_VS_DLY_L[2:0] - SCL0_ SCL0_ VEN_DINP_VS_DLY[7:0] VEN_C - 23 22 21 - - - INP_FLD_DLY[7:0] - 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 4 3 2 1 0 7 6 5 - - - 20 19 18 SCL0_ INP_HS_DLY[7:0] VEN_B 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 24 INP_VS_ 0 DLY_L[2:0] R/W Number of lines for Delaying Vsync signal and Field Differentiation Signal Delay amount: 0 to 7 (lines) 23 to 16 15 to 8 7 to 0 INP_FLD_ DLY[7:0] 0 INP_VS_ DLY[7:0] 0 INP_HS_ DLY[7:0] 0 R/W Field Differentiation Signal Delay Amount Delay amount: 0 to 254 (clock cycles) R/W Vsync Signal Delay Amount Delay amount: 0 to 254 (clock cycles) R/W Hsync Signal Delay Amount Delay amount: 0 to 254 (clock cycles) Note: This register is updated when the INP_IMG_UPDATE bit in INP_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1933 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.6 Image Quality Adjustment Block Register Update Control Register (IMGCNT_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                IMGCNT _VEN Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 IMGCNT_ VEN 0 R/WC1 Image Quality Adjustment Block Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync signal. Page 1934 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.2.7 Section 32 Video Display Controller 4 (2): Input Controller NR Control Register 0 (IMGCNT_NR_CNT0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16            NR1D_ MD    NR1D_ ON Initial Value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R R R R R R R/W R R R R/W Bit: 15 14 13 12 11 10 9 8 5 4 1 0  - - Initial Value: 0 0 0 R/W: R R/W R/W Bit: GR1_ NR1D_Y_TH[6:0] ARC_ON - - - 0 1 0 0 R/W R/W R/W R/W 7 6   0 0 0 0 R/W R R R/W Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved 3 2   0 0 0 1 1 R/W R R R/W R/W NR1D_Y_TAP[1:0] - NR1D_Y_GAIN[1:0] - These bits are always read as 0. The write value should always be 0. 20 NR1D_MD 1 R/W Horizontal Noise Reduction Operating Mode 0: G/B/R mode 1: Y/Cb/Cr mode 19 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 NR1D_ON 0 R/W Noise Reduction On/Off Control 0: Noise reduction Off 1: Noise reduction On 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 8 NR1D_Y_ TH[6:0] 8 R/W Maximum Value (Absolute Value) of Y/G Signal Coring Coring is implemented when detected noise amount value  NR1D_Y_TH. Unsigned: 0 to 127 [LSB] 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1935 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Bit Bit Name 5, 4 NR1D_Y_ TAP[1:0] Initial Value R/W Description 0 R/W Y/G Signal TAP Select 0: Adjacent pixel 1: 2 adjacent pixels 2: 3 adjacent pixels 3: 4 adjacent pixels 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 NR1D_Y_ GAIN[1:0] 3 R/W Noise Reduction Gain Adjustment of Y/G Signal 0: 1/2 1: 1/4 2: 1/8 3: 1/16 Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. Page 1936 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.2.8 Section 32 Video Display Controller 4 (2): Input Controller NR Control Register 1 (IMGCNT_NR_CNT1) Bit: 31 30  - 29 28 - 27 26 NR1D_CB_TH[6:0] - 25 24 - 23 22   21 20 NR1D_CB_TAP[1:0] - 19 18   17 16 NR1D_CB_ GAIN[1:0] Initial Value: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 R/W: R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W Bit: 15 14 13 12 11 10 9 8 5 4 0  - - GR1_ NR1D_CR_TH[6:0] ARC_ON - - - 7 6   NR1D_CR_TAP[1:0] - 3 2 1   -NR1D_CR_ GAIN[1:0] Initial Value: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 R/W: R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W Bit Bit Name Initial Value R/W Description 31  0 R Reserved This bit is always read as 0. The write value should always be 0. 30 to 24 NR1D_CB_ 8 TH[6:0] R/W Maximum Value (Absolute Value) of Cb/B Signal Coring Coring is implemented when detected noise amount value  NR1D_CB_TH. Unsigned: 0 to 127 [LSB] 23, 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 NR1D_CB_ 0 TAP[1:0] R/W Cb/B Signal TAP Select 0: Adjacent pixel 1: 2 adjacent pixels 2: 3 adjacent pixels 3: 4 adjacent pixels 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 NR1D_CB_ 3 GAIN[1:0] R/W Noise Reduction Gain Adjustment of Cb/B Signal 0: 1/2 1: 1/4 2: 1/8 3: 1/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1937 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Bit Bit Name Initial Value R/W Description 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 8 NR1D_CR_ 8 TH[6:0] R/W Maximum Value (Absolute Value) of Cr/R Signal Coring Coring is implemented when detected noise amount value  NR1D_CR_TH. Unsigned: 0 to 127 [LSB] 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 NR1D_CR_ 0 TAP[1:0] R/W Cr/R Signal TAP Select 0: Adjacent pixel 1: 2 adjacent pixels 2: 3 adjacent pixels 3: 4 adjacent pixels 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 NR1D_CR_ 3 GAIN[1:0] R/W Noise Reduction Gain Adjustment of Cr/R Signal 0: 1/2 1: 1/4 2: 1/8 3: 1/16 Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. Page 1938 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 32.2.9 Section 32 Video Display Controller 4 (2): Input Controller Image Quality Adjustment Block Matrix Mode Register (IMGCNT_MTX_MODE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0               IMGCNT_ MTX_MD[1:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 R/W: R R R R R R R R R R R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 IMGCNT_ MTX_MD [1:0] 3 R/W Operating Mode 0: GBR  GBR 1: GBR  YCbCr 2: YCbCr  GBR 3: YCbCr  YCbCr Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1939 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.10 Image Quality Adjustment Block Matrix YG Adjustment Register 0 (IMGCNT_MTX_YG_ADJ0) 31 30 29 28 27 26 25 24         Initial Value: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3      - - - Bit: 23 22 21 - IMGCNT_MTX_YG[7:0] - 20 19 18 IMGCNT_MTX_GG[10:0] - 17 16 - - 2 1 0 - - - Initial Value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 11 IMGCNT_ MTX_YG [7:0] 128  All 0 R/W Offset (DC) Adjustment of Y/G Signal Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 IMGCNT_ MTX_GG [10:0] 256 R/W Y/G Signal Gain Adjustment for Y/G Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. Page 1940 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.11 Image Quality Adjustment Block Matrix YG Adjustment Register 1 (IMGCNT_MTX_YG_ADJ1) Bit: 31 30 29 28 27 26 25 24      - - - 22 23 21 20 19 IMGCNT_MTX_GB[10:0] - 18 17 16 - - - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3      - - - IMGCNT_MTX_GR[10:0] - 2 1 0 - - - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 IMGCNT_ MTX_GB [10:0] 0  All 0 R/W Cb/B Signal Gain Adjustment for Y/G Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 IMGCNT_ MTX_GR [10:0] 0 R/W Cr/R Signal Gain Adjustment for Y/G Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1941 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.12 Image Quality Adjustment Block Matrix CBB Adjustment Register 0 (IMGCNT_MTX_CBB_ADJ0) 22 21 17 16 - -IMGCNT_MTX_B[7:0] - - - 1 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W R/W 9 8 7 6 5 4 3 - - 23 20 31 30 29 28 27 26 25 24         Initial Value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R Bit: 15 14 13 12 11 10      - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W Bit: 19 2 1 0 - - - 0 0 0 0 R/W R/W R/W R/W IMGCNT_MTX_BG[10:0] - Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved 18 These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 11 IMGCNT_ 128 MTX_B[7:0] R/W  R All 0 Offset (DC) Adjustment of Cb/B Signal Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 IMGCNT_ MTX_BG [10:0] 0 R/W Y/G Signal Gain Adjustment for Cb/B Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. Page 1942 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.13 Image Quality Adjustment Block Matrix CBB Adjustment Register 1 (IMGCNT_MTX_CBB_ADJ1) 31 30 29 28 27 26 25 24      - - - Initial Value: 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5      - - - Bit: 23 22 21 18 17 16 - - - 0 0 0 0 R/W R/W R/W R/W R/W 4 3 20 19 IMGCNT_MTX_BB[10:0] - IMGCNT_MTX_BR[10:0] - 2 1 0 - - - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 IMGCNT_ MTX_BB [10:0] 256  All 0 R/W Cb/B Signal Gain Adjustment for Cb/B Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 IMGCNT_ MTX_BR [10:0] 0 R/W Cr/R Signal Gain Adjustment for Cb/B Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1943 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.14 Image Quality Adjustment Block Matrix CRR Adjustment Register 0 (IMGCNT_MTX_CRR_ADJ0) Bit: 31 30 29 28 27 26 25 24         23 22 21 - -IMGCNT_MTX_R[7:0] - 20 19 18 17 16 - - Initial Value: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3      - - - IMGCNT_MTX_RG[10:0] - 2 1 0 - - - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 11 IMGCNT_ MTX_R [7:0] 128  All 0 R/W Offset (DC) Adjustment of Cr/R Signal Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 IMGCNT_ MTX_RG [10:0] 0 R/W Y/G Signal Gain Adjustment for Cr/R Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. Page 1944 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.2.15 Image Quality Adjustment Block Matrix CRR Adjustment Register 1 (IMGCNT_MTX_CRR_ADJ1) 31 30 29 28 27 26 25 24      - - - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5      - - - Bit: 22 23 21 20 19 18 17 16 - - - 0 0 0 0 R/W R/W R/W R/W R/W 4 3 IMGCNT_MTX_RB[10:0] - IMGCNT_MTX_RR[10:0] - 2 1 0 - - - Initial Value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 IMGCNT_ MTX_RB [10:0] 0  All 0 R/W Cb/B Signal Gain Adjustment for Cr/R Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 IMGCNT_ MTX_RR [10:0] 256 R/W Cr/R Signal Gain Adjustment for Cr/R Signal Output Signed (two's complement) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when the IMGCNT_VEN bit in IMGCNT_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1945 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.3 32.3.1 Usage Methods Input Format Adjustment Method Setting examples of each input format are shown below. Table 32.26 Video Decoder (NTSC) Input Setting Example Register Name Bit Name Description Setting Value INP_SEL_CNT INP_SEL Selects the input signal. 0 INP_SEL_CNT INP_FORMAT[2:0] Selects the externally input format. Control not necessary INP_SEL_CNT INP_PXD_EDGE Selects the clock edge for capturing Control not the externally input video signals. necessary INP_SEL_CNT INP_VS_EDGE Selects the clock edge for capturing Control not the externally input Vsync signals. necessary INP_SEL_CNT INP_HS_EDGE Selects the clock edge for capturing Control not the externally input Hsync signals. necessary INP_EXT_SYNC_CNT INP_ENDIAN_ON Changes the bit endian of the external input. Control not necessary INP_EXT_SYNC_CNT INP_SWAP_ON Enables or disables the B/R signal swap of the external input. Control not necessary INP_EXT_SYNC_CNT INP_HS_INV Enables or disables the Hsync Control not signal inversion of the external input. necessary INP_EXT_SYNC_CNT INP_VS_INV Enables or disables the Hsync Control not signal inversion of the external input. necessary INP_EXT_SYNC_CNT INP_H_EDGE_SEL Selects the Hsync reference for BT656 input. Control not necessary INP_EXT_SYNC_CNT INP_F525_625 Sets the number of lines for BT656 input. Control not necessary INP_EXT_SYNC_CNT INP_H_POS[1:0] Sets the data start timing with respect to the Hsync in the BT656/601 format. Control not necessary INP_VSYNC_PH_ADJ INP_FH50[9:0] Sets the 1/2fH phase in clock cycle units. 858 INP_VSYNC_PH_ADJ INP_FH25[9:0] Sets the 1/4fH phase in clock cycle units. 429 Page 1946 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Description Setting Value Register Name Bit Name INP_DLY_ADJ INP_VS_DLY_L[2:0] Sets the number of lines for delaying 0 the Vsync signal and field differentiation signal. INP_DLY_ADJ INP_VS_DLY[7:0] Sets the amount of delay of the Vsync signal in clock cycle units. 0 INP_DLY_ADJ INP_HS_DLY[7:0] Sets the amount of delay of the Hsync signal in clock cycle units. 0 INP_DLY_ADJ INP_FLD_DLY[7:0] Sets the amount of delay of the field 0 differentiation signal in clock units. Note: Some registers require, after they are set, that the INP_EXT_UPDATE and INP_IMG_UPDATE bits in INP_UPDATE should be set to 1. Table 32.27 External Input (BT656, 525i) Setting Example Register Name Bit Name Description Setting Value INP_SEL_CNT INP_SEL Selects the input signal. 1 INP_SEL_CNT INP_FORMAT[2:0] Selects the externally input format. 3 INP_SEL_CNT INP_PXD_EDGE Selects the clock edge for capturing the externally input video signals. 0 INP_SEL_CNT INP_VS_EDGE Selects the clock edge for capturing the externally input Vsync signals. 0 INP_SEL_CNT INP_HS_EDGE Selects the clock edge for capturing the externally input Hsync signals. 0 INP_EXT_SYNC_CNT INP_ENDIAN_ON Changes the bit endian of the external input. 0 INP_EXT_SYNC_CNT INP_SWAP_ON Enables or disables the B/R signal swap of the external input. 0 INP_EXT_SYNC_CNT INP_HS_INV Enables or disables the Hsync signal inversion of the external input. 1 INP_EXT_SYNC_CNT INP_VS_INV Enables or disables the Hsync signal inversion of the external input. 1 INP_EXT_SYNC_CNT INP_H_EDGE_SEL Selects the Hsync reference for BT656 input. 0 INP_EXT_SYNC_CNT INP_F525_625 Sets the number of lines for BT656 input. 0 INP_EXT_SYNC_CNT INP_H_POS[1:0] Sets the data start timing with respect to the Hsync in the BT656/601 format. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 Page 1947 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Register Name Bit Name Setting Value Description INP_VSYNC_PH_ADJ INP_FH50[9:0] Sets the 1/2fH phase in clock cycle units. 858 INP_VSYNC_PH_ADJ INP_FH25[9:0] Sets the 1/4fH phase in clock cycle units. 429 INP_DLY_ADJ INP_VS_DLY_L[2:0] Sets the number of lines for delaying the 0 Vsync signal and field differentiation signal. INP_DLY_ADJ INP_VS_DLY[7:0] Sets the amount of delay of the Vsync signal in clock cycle units. 0 INP_DLY_ADJ INP_HS_DLY[7:0] Sets the amount of delay of the Hsync signal in clock cycle units. 0 INP_DLY_ADJ INP_FLD_DLY[7:0] Sets the amount of delay of the field differentiation signal in clock units. 0 Note: Some registers require, after they are set, that the INP_EXT_UPDATE and INP_IMG_UPDATE bits in IMP_UPDATE should be set to 1. Page 1948 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller Table 32.28 External Input (BT601, 525i) Setting Example Register Name Bit Name Description Setting Value INP_SEL_CNT INP_SEL Selects the input signal. 1 INP_SEL_CNT INP_FORMAT[2:0] Selects the externally input format. 4 INP_SEL_CNT INP_PXD_EDGE Selects the clock edge for capturing the externally input video signals. 0 INP_SEL_CNT INP_VS_EDGE Selects the clock edge for capturing the externally input Vsync signals. 0 INP_SEL_CNT INP_HS_EDGE Selects the clock edge for capturing the externally input Hsync signals. 0 INP_EXT_SYNC_CNT INP_ENDIAN_ON Changes the bit endian of the external input. 0 INP_EXT_SYNC_CNT INP_SWAP_ON Enables or disables the B/R signal swap of 0 the external input. INP_EXT_SYNC_CNT INP_HS_INV Enables or disables the Hsync signal inversion of the external input. 1 INP_EXT_SYNC_CNT INP_VS_INV Enables or disables the Hsync signal inversion of the external input. 1 INP_EXT_SYNC_CNT INP_H_EDGE_SEL Selects the Hsync reference for BT656 input. 0 INP_EXT_SYNC_CNT INP_F525_625 Sets the number of lines for BT656 input. 0 INP_EXT_SYNC_CNT INP_H_POS[1:0] Sets the data start timing with respect to the 0 Hsync in the BT656/601 format. INP_VSYNC_PH_ADJ INP_FH50[9:0] Sets the 1/2fH phase in clock cycle units. 858 INP_VSYNC_PH_ADJ INP_FH25[9:0] Sets the 1/4fH phase in clock cycle units. 429 INP_DLY_ADJ INP_VS_DLY_L[2:0] Sets the number of lines for delaying the 0 Vsync signal and field differentiation signal. INP_DLY_ADJ INP_VS_DLY[7:0] Sets the amount of delay of the Vsync signal in clock cycle units. 0 INP_DLY_ADJ INP_HS_DLY[7:0] Sets the amount of delay of the Hsync signal in clock cycle units. 0 INP_DLY_ADJ INP_FLD_DLY[7:0] Sets the amount of delay of the field differentiation signal in clock units. 0 Note: Some registers require, after they are set, that the INP_EXT_UPDATE and INP_IMG_UPDATE bits in INT_UPDATE should be set to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1949 of 3092 SH7268 Group, SH7269 Group Section 32 Video Display Controller 4 (2): Input Controller 32.3.2 Usage Method of Conversion Color Matrix Typical data conversion setting examples are shown below. Table 32.29 Conversion Color Matrix Register Name Bit Name GBR to GBR GBR to YCbCr YCbCr to YCbCr to GBR YCbCr IMGCNT_MTX_MODE IMGCNT_MTX_MD[1:0] 0 1 2 3 IMGCNT_MTX_YG_ADJ0 IMGCNT_MTX_YG[7:0] 128 128 128 128 IMGCNT_MTX_YG_ADJ0 IMGCNT_MTX_GG[10:0] 256 150 256 256 IMGCNT_MTX_YG_ADJ1 IMGCNT_MTX_GB[10:0] 29 1960 0 IMGCNT_MTX_YG_ADJ1 IMGCNT_MTX_GR[10:0] 0 0 77 1865 0 IMGCNT_MTX_CBB_ADJ0 IMGCNT_MTX_B[7:0] 128 128 128 128 IMGCNT_MTX_CBB_ADJ0 IMGCNT_MTX_BG[10:0] 0 1963 256 0 IMGCNT_MTX_CBB_ADJ1 IMGCNT_MTX_BB[10:0] 256 128 454 256 IMGCNT_MTX_CBB_ADJ1 IMGCNT_MTX_BR[10:0] 0 2005 0 0 IMGCNT_MTX_CRR_ADJ0 IMGCNT_MTX_R[7:0] 128 128 128 128 IMGCNT_MTX_CRR_ADJ0 IMGCNT_MTX_RG[10:0] 0 1941 256 0 IMGCNT_MTX_CRR_ADJ1 IMGCNT_MTX_RB[10:0] 0 2027 0 0 IMGCNT_MTX_CRR_ADJ1 IMGCNT_MTX_RR[10:0] 256 128 359 256 Note: The registers require, after they are set, that the IMGCNT_VEN bit in IMGCNT_UPDATE should be set to 1. Page 1950 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Section 33 Video Display Controller 4 (3): Scaler 33.1 Scaler 33.1.1 Overview of Functions The scaler subjects the YCbCr and RGB signals output from the input controller, to sync signal generation; and reduction, enlargement, and rotation of the images. The scaler also records video image in the frame buffer. In the scaler, either enlargement process or graphics 1 process can be used at a time. The functional block diagram of the scaler is shown below. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1951 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler IV2-BUS (read) YCbCr422 = 16 bits RGB565 = 16 bits RGB888 = 24(32) bits Internal bus read control YCbCr422 = 16 bits Line buffer Switching Buffer write control Buffer write control Buffer read control YCbCr422 to YCbCr444 conversion HS, VS, HE, VE Internal bus write control HS,VS,HE,VE, YCbCr422/RGB888/RGB565 YCbCr444 to YCbCr422 conversion Bit extension CLUT control Frame sub-sampling Output image enable signal generation Enable adjustment Vertical scale up (two-TAP linear) Horizontal scale up (two-TAP linear) Trimming Synthesis of moving picture and background Scaling-up control block Moving picture synthesizing block Horizontal prefilter (three-TAP) Specification of video image area to be captured HS, VS, FLD, YCbCr/RGB888 (24 bits) [Moving picture, scale up] YCbCr/RGB888 (24 bits) Vertical scale down (two-TAP linear) Horizontal scale down (two-TAP linear) Switching Line buffer Data expansion 1 Switching [Graphics] ARGB8888 Output selection Bit reduction HS, VS, HE, VE, YCbCr444/RGB888 CLUT table HS,VS,HE,VE, YCbCr422 (16 bits) Bit reduction Input controller Internal bus read control 1 Enable signal generation Rotation control Buffer read control Image renderer Rotation control Internal bus write control Line buffer Switching IV1-BUS (write/read) [Graphics] [Moving picture] RGB565 = 16 bits RGB565 = 16 bits RGB888 = 32 bits RGB888 = 32 bits YCbCr422 = 16 bits ARGB1555 = 16 bits ARGB4444 = 16 bits ARGB8888 = 32 bits CLUT8 = 8 bits CLUT4 = 4 bits CLUT1 = 1 bit YCbCr422 = 16 bits HS, VS, HE, VE, YCbCr/RGB888 (24 bits) Image quality improver Scaling-down control block Vsync signal generation Repeated Vsync signal masking Hsync signal generation Vsync signal correction Sync signal generation Full-image enable signal generation Free-running Vsync signal generation Missing-sync compensation Field determination signal delay control Repeated Vsync signal masking Switching Vsync signal delay control Graphics 1 Register control Synchronization control block Scaler Figure 33.1 Functional Block Diagram of Scaler 33.1.2 (1) Register Control Updating Registers The Vsync signal is used to control the update timing of all the registers of the scaling and graphics blocks except some registers of the sync control block. After 1 is set to the bits in the update control register, the contents of the relevant registers are modified at the rising edge of the Vsync signal. The update control register is automatically cleared to 0 after the modification. Page 1952 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.1 Register Update Control Register Name Bit Name Initial Value Description SCL0_UPDATE SCL0_UPDATE 0 SYNC Control Register Update 0: Registers are not updated. 1: Registers are updated. SCL0_UPDATE SCL0_VEN_D 0 Scaling-Up Control and Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. SCL0_UPDATE SCL0_VEN_C 0 Scaling-Down Control and Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. SCL0_UPDATE SCL0_VEN_B 0 Synchronization Control and Scaling-up Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. SCL0_UPDATE SCL0_VEN_A 0 Scaling-Down Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. SCL1_UPDATE SCL1_VEN_B 0 Frame Buffer Write Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. SCL1_UPDATE SCL1_VEN_A 0 Frame Buffer Write Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. GR1_UPDATE GR1_P_VEN 0 Graphics Display Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1953 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Register Name Bit Name Initial Value Description GR1_UPDATE GR1_IBUS_VEN 0 Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. The registers controlled by SCL0_VEN_A, SCL_0_VEN_C, SCL1_VEN_A, and SCL1_VEN_B are modified at the rising edge of the input Vsync signal. The registers controlled by SCL0_VEN_B, SCL0_VEN_D, GR1_P_VEN, and GR1_IBUS_VEN are modified at the rising edge of the output Vsync signal. 33.1.3 (1) Synchronization Control Selecting Vsync Signal The Vsync signal to be output from the scaler can be selected. When an external input signal is to be displayed, an external input Vsync signal should be selected to be output. When an external input signal is not provided, a free-running Vsync signal should be selected to be output. Table 33.2 Vsync Signal Selection Control Register Name Bit Name Initial Value Description SCL0_FRC3 RES_VS_SEL 1 Vsync Signal Output Select 0: External input Vsync signal 1: Internally generated free-running Vsync signal Page 1954 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 33 Video Display Controller 4 (3): Scaler Masking Repeated Vsync Signals It is possible to prevent receiving the Vsync signal with a period shorter than the standard period. This is achieved by setting the start timing to receive the next Vsync signal after receiving an input Vsync signal. The Vsync signal reception masking period is set with the RES_VMASK[15:0] bits. Masking period [usec] = RES_VMASK  128 ÷ pixel clock frequency [MHz] This function is enabled or disabled by the RES_VMASK_ON bit. Repeated Vsync signals VSIN Masking period RES_VMASK[15:0]×128 Vsync signal is masked during masking period. Repeated Vsync signal masking VSOUT Figure 33.2 Timing for Masking Repeated Vsync Signals Table 33.3 Repeated Vsync Signal Mask Control Register Name Bit Name Initial Value SCL0_FRC1 1 RES_VMASK_ON Description Repeated Vsync Signal Masking Control 0: Repeated Vsync signal masking control is disabled. 1: Repeated Vsync signal masking control is enabled. SCL0_FRC1 RES_VMASK[15:0] 2800 Repeated Vsync Signal Masking Period Sets the repeated Vsync signal masking period beginning at a Vsync signal in terms of 128 pixel-clock periods. Masking period [usec] = RES_VMASK  128 ÷ pixel clock frequency [MHz] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1955 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (3) Compensating for Missing Vsync Signals It is possible to prevent output of the Vsync signal with a period longer than the standard period. This is achieved by setting the wait time after reception of an input Vsync signal until reception of the next Vsync signal. If no Vsync signals are received during the wait time, an internally generated sync signal is inserted. The wait time can be set using the RES_VLACK[15:0] bits. Wait time [usec] = RES_VLACK  128 ÷ pixel clock frequency [MHz] This function is enabled or disabled by the RES_VLACK_ON bit. If no Vsync signals are input during the Vsync signal reception time, the RES_QVLACK bit is set to the high level. If Vsync signals are continuously detected four or more times during the Vsync signal reception time, the RES_QVLOCK bit is set to the high level. The RES_QVLOCK bit is valid even when both the RES_VMASK_ON and RES_VLACK_ON bits are set to turn off the corresponding functions. Note that, however, the RES_VMASK and RES_VLACK bits must be set correctly. Missing Vsync signal VSIN Wait time VSOUT RES_VLACK[15:0]×128 If no Vsync signal is input during the wait time, a missing-sync compensating pulse is output. After a missing-sync compensation, the wait time measurement is started from the missing-sync pulse. RES_VLACK[15:0]×128 Missing-sync compensating pulse Figure 33.3 Compensation of Missing Vsync Signals Page 1956 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.4 Missing Vsync Compensation Control Register Name Bit Name Initial Value Description SCL0_FRC2 RES_VLACK_ON 1 Missing Vsync Signal Compensation 0: Compensation of missing Vsync signals is disabled. 1: Compensation of missing Vsync signals is enabled. SCL0_FRC2 RES_VLACK[15:0] 3600 Missing-Sync Compensating Pulse Output Wait Time Sets the wait time before outputting a missingsync compensating pulse after a Vsync signal. Wait time [usec] = RES_VLACK × 128 ÷ pixel clock frequency [MHz] SCL0_FRC9 RES_QVLACK  Missing Vsync Signal Detection Flag 1: Missing Vsync signal input has been detected. 0: No missing Vsync signal input has been detected. SCL0_FRC9 RES_QVLOCK  Locked Vsync Signal Detection Flag 1: No repeated or missing Vsync signal input has been detected for four or more vertical periods. 0: Repeated or missing Vsync signal input has been detected. For the Vsync signal, repeated-signal masking is first carried out and then missing-signal compensation is carried out, followed by another repeated-signal masking. Repetition masking is inserted after missing-Vsync compensation to prevent output of the Vsync signal even in cases such as the input of a Vsync signal immediately after the input of a pulse to compensate for a missing Vsync signal. On/off control of the missing-Vsync compensation also applies to the second repeated-Vsync masking; and masking period setting of the first repeated-Vsync masking also applies to the second repeated-Vsync masking. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1957 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler VSIN Repeated-Vsync masking VS RES_VMASK_ON RES_VMASK[15:0] Missing-Vsync compensation RES_VLACK_ON RES_VLACK[15:0] VS Repeated-Vsync masking VSOUT RES_VLACK_ON RES_VMASK[15:0] Figure 33.4 Repeated-Vsync Masking and Missing-Vsync Compensation Missing Vsync signal Vsync signal is input after a missing detected. VSIN First masking period RES_VMASK[15:0]×128 Wait time First masking period RES_VLACK[15:0]×128 Wait time Not masked during the first repeatedVsync masking period Wait time VSOUT after missingVsync compensation Missing-Vsync compensating pulse Second masking period Second masking period Second masking period Second masking period VSOUT Masked during the second repeated-Vsync masking period The closer to the end of second masking period the Vsync signal input is, the longer the Vsync signal output cycle is. Figure 33.5 Timing for Masking Repeated Vsync Signals and Missing Vsync Signal Compensation Page 1958 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 33 Video Display Controller 4 (3): Scaler Free-Running Period Free-running Vsync and Hsync periods can be set. Hsync period [usec] = (RES_FH  1) ÷ pixel clock frequency [MHz] Vsync period [usec] = horizontal period [usec] × (RES_FV  1) Table 33.5 Free-Running Period Control Register Name Bit Name Initial Value Description SCL0_FRC4 RES_FV[10:0] 524 Free-Running Vsync Period Setting Free-running Vsync period = (RES_FV + 1) × horizontal period [usec] SCL0_FRC4 RES_FH[10:0] 799 Hsync Period Setting Hsync period [usec] = (RES_FH +1) ÷ pixel clock frequency [MHz] When selecting an external input Vsync signal, set the RES_VS_SEL bit to 0. At this time, the internally generated free-running Vsync signal is not output. In the meantime, the Hsync signal is always generated according to the free-running signal setting and output from the scaler. (5) Vsync Signal Delay Control Delay of Vsync signal output from the scaler can be controlled. The delay is used to adjust the frame buffer read timing. Table 33.6 Vsync Output Delay Control Register Name Bit Name Initial Value Description SCL0_FRC5 RES_VSDLY[7:0] 1 Vsync Signal Delay Control Adjusts the Vsync signal delay in the output Hsync period units. Vsync signal delay [usec]: RES_VSDLY × output Hsync period [usec] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1959 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Vsync (internal) Vsync (scaler output) Moving picture A (input) Moving picture A (write) Moving picture B (input) Moving picture B (write) Moving picture C (input) Moving picture C (write) RES_VSDLY Vsync (input) Moving picture A (read) Moving picture B (read) After 100% scale-up/down, scale down, or rotation processing is performed, data is written to the frame buffer. Moving picture C (read) After data is read from the frame buffer, 100% scale-up/ down or scale-up processing is performed. Figure 33.6 Vsync Signal Phases (Two Frame-Buffer Planes Used) Moving picture A (input) Vsync (internal) Moving picture A (write) Vsync (scaler output) Image to be written before frame buffer reading Reading does not get ahead of writing. Moving picture B (input) Moving picture B (write) Moving picture C (input) Moving picture C (write) After 100% scale-up/down, scale down, or rotation processing is performed, data is written to the frame buffer. RES_VSDLY Vsync (input) Moving picture A (read) Moving picture B (read) Moving picture C (read) After data is read from the frame buffer, 100% scale-up/ down or scale-up processing is performed. Figure 33.7 Vsync Signal Phases (One Frame-Buffer Plane Used) Page 1960 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.1.4 (1) Section 33 Video Display Controller 4 (3): Scaler Setting Angle of View Setting Image Area to be Captured The image area to be captured can be set for reduction or enlargement. The area is defined by specifying its start position and width based on the input Hsync and Vsync signals. Table 33.7 Control of Image Area to be Captured Register Name Bit Name Initial Value SCL0_DS2 RES_VS[10:0] 18 Description Vertical Position Setting for Video Signal Capturing (VSYNC + (V backporch - 1) lines) Note: The set value should be four or more (lines). RES_VS + RES_VW should be equal to or less than 2039 (lines). SCL0_DS2 RES_VW[10:0] 240 Vertical Width of Video Signal to be Captured (lines) Note: RES_VS + RES_VW should be equal to or less than 2039 (lines). SCL0_DS3 RES_HS[10:0] 244 Horizontal Position Setting for Video Signal Capturing (HSYNC + H backporch video-image clock cycles) Note: The set value should be 16 or more (clock cycles). RES_HS + RES_HW should be equal to or less than 2015 (clock cycles). SCL0_DS3 RES_HW[10:0] 1440 Horizontal Width of Video Signal to be Captured (video-image clock cycles) Note: RES_HS + RES_HW should be equal to or less than 2015 (clock cycles). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1961 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (2) Generating a Full-Screen Enable Signal The valid period of the full screen to be output from the scaler can be set. The valid period is defined by specifying its start position and width based on the Hsync and Vsync signals output from the scaler. The vertical front porch should be set to four or more lines, and the horizontal front porch should be 16 or more clock cycles. Table 33.8 Full-Screen Enable Control Register Name Bit Name Initial Value SCL0_FRC6 RES_F_VS[10:0] 35 Description Vertical Enable Signal Start Position for Full Screen. (VSYNC + V backporch lines) Note: The set value should be four or more (lines). RES_F_VS + RES_F_VW should be equal to or less than 2039 (lines). SCL0_FRC6 RES_F_VW[10:0] 480 Vertical Enable Signal Width for Full Screen (lines) Note: RES_F_VS + RES_F_VW should be equal to or less than 2039 (lines). SCL0_FRC7 RES_F_HS[10:0] 144 Horizontal Enable Signal Start Position for Full Screen. (HSYNC + H backporch pixel-clock cycles) Note: The set value should be 16 or more (clock cycles). RES_F_HS + RES_F_HW should be equal to or less than 2015 (clock cycles). SCL0_FRC7 RES_F_HW[10:0] 640 Horizontal Enable Signal Width for Full Screen (pixel-clock cycles) Notes: 1. RES_F_HS + RES_F_HW should be equal to or less than 2015 (clock cycles). 2. The set value should be equal to (horizontal signal width for full screen + 2) when serial RGB output is selected as an LCD output signal. Page 1962 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 33 Video Display Controller 4 (3): Scaler Generating an Image Output Enable Signal The valid period of the image to be output can be set. The valid period is defined by specifying its start position and width based on the Hsync and Vsync signals output from the scaler. Table 33.9 Image Output Enable Control Register Name Bit Name Initial Value SCL0_US2 RES_P_VS[10:0] 35 Description Vertical Enable Signal Start Position for Output Image. (VSYNC + V backporch lines) Note: The set value should be four or more (lines). RES_P_VS + RES_P_VW should be equal to or less than 2039 (lines). SCL0_US2 RES_P_VW[10:0] 480 Vertical Enable Signal Width for Output Image (lines) Note: RES_P_VS + RES_P_VW should be equal to or less than 2039 (lines). SCL0_US3 RES_P_HS[10:0] 144 Horizontal Enable Signal Start Position for Output Image. (HSYNC + H backporch pixel-clock cycles) Note: The set value should be 16 or more (clock cycles). RES_P_HS + RES_P_HW should be equal to or less than 2015 (clock cycles). SCL0_US3 RES_P_HW[10:0] 640 Horizontal Enable Signal Width for Output Image (pixel-clock cycles) Note: RES_P_HS + RES_P_HW should be equal to or less than 2015 (clock cycles). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1963 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Setting the area of input image to be captured Input Vsync signal Input Hsync signal RES_HS RES_HW RES_VS +1 Image area to be captured RES_VW RES_FH+1 RES_F_HW RES_P_VS RES_F_HS RES_F_VS Output Vsync signal Setting output enable Output Hsync signal Output full-image area RES_P_HS RES_P_VW RES_F_VW Output image area In free-running mode RES_FV + 1 RES_P_HW Figure 33.8 Enable Settings Page 1964 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.1.5 (1) Section 33 Video Display Controller 4 (3): Scaler Scaling Settings Scaling Processing Block The scaling-down control block scales down the input image from the input controller. When rotation is required, the scaling-down control block first scales down the image and then rotates it before writing it into the frame buffer. The scaling-up control block reads the rotated image from the frame buffer and scales it up. Table 33.10 Rotation and Scaling Process Rotation Normal Horizontal mirroring Horizontal Scaling Vertical Scaling Scaling-Down Control Block Scaling-Up Control Block Horizontal scale down Vertical scale down Horizontal scale down/ vertical scale down Horizontal 100% scale up/ vertical 100% scale up Horizontal scale down Vertical scale up Horizontal scale down/ vertical 100% scale up Horizontal 100% scale up/ vertical scale up Horizontal scale up Vertical scale down Horizontal 100% scale up/ vertical scale down Horizontal scale up/ vertical 100% scale up Horizontal scale up Vertical scale up Horizontal 100% scale up/ vertical 100% scale up Horizontal scale up/ vertical scale up Horizontal scale down Vertical scale down Horizontal scale down/ vertical scale down Horizontal 100% scale up/ vertical 100% scale up Horizontal scale down Vertical scale up Horizontal scale down/ vertical 100% scale up Horizontal 100% scale up/ vertical scale-up Horizontal scale up Vertical scale down Horizontal 100% scale up/ vertical scale down Horizontal scale up/ vertical 100% scale up Horizontal scale up Vertical scale up Horizontal 100% scale up/ vertical 100% scale up Horizontal scale up/ vertical scale up R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1965 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Rotation 90 rotation 180 rotation 270 rotation Page 1966 of 3092 Horizontal Scaling Vertical Scaling Scaling-Down Control Block Scaling-Up Control Block (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale down Horizontal scale down/ vertical scale down Horizontal 100% scale up/ vertical 100% scale up (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale up Horizontal scale down/ vertical 100% scale up Horizontal scale up/ vertical 100% scale up (Horizontal input  vertical output) scale up (Vertical input  horizontal output) scale up Horizontal 100% scale up/ vertical 100% scale up Horizontal scale up/ vertical scale up Horizontal scale down Vertical scale down Horizontal scale down/ vertical scale down Horizontal 100% scale up/ vertical 100% scale up Horizontal scale down Vertical scale up Horizontal scale down/ vertical 100% scale up Horizontal 100% scale up/ vertical scale up Horizontal scale up Vertical scale down Horizontal 100% scale up/ vertical scale down Horizontal scale up/ vertical 100% scale up Horizontal scale up Vertical scale up Horizontal 100% scale up/ vertical 100% scale up Horizontal scale up/ vertical scale up (Horizontal (Vertical Horizontal scale inputvertical inputhorizontal down/ vertical output) scale down output) scale down scale down Horizontal 100% scale up/ vertical 100% scale up (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale up Horizontal scale down/ vertical 100% scale up Horizontal scale up/ vertical 100% scale up (Horizontal input  vertical output) scale up (Vertical input  horizontal output) scale up Horizontal 100% scale up/ vertical 100% scale up Horizontal scale up/ vertical scale up R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Horizontal scale up Vertical scale up Vertical scale down Horizontal scale down Rotating the image data and writing the data to the frame buffer Scaling down the input image Reading the rotated image data from the frame buffer Scaling up the rotated image Figure 33.9 Rotation and Scaling Process It is impossible to use vertical reduction by the scaling-down control block and vertical enlargement by the scaling-up control block simultaneously because they are mutually exclusive. Thus, the following scaling processes cannot be performed with 90 rotation or 270 rotation. Table 33.11 Impossible Scaling Process Rotation 90 rotation 270 rotation Horizontal Scaling Vertical Scaling Scaling-Down Control Block Scaling-Up Control Block (Horizontal input  vertical output) scale up (Vertical input  horizontal output) scale down Horizontal 100% scale up/ vertical scale down Horizontal 100% scale up/ vertical scale up Scale up Scale down Input image Output image Figure 33.10 Impossible Scaling Process R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1967 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.6 Horizontal Prefilter The horizontal prefilter can be turned on or off for brightness (Y) and RGB signals to suppress the frequency band of the signals during horizontal size reduction. The input format depends on the RES_MD[1:0] bit setting in the writing mode register (SCL1_WR1). When the horizontal reduction ratio is high and there is too much folding frequency component to ignore, the horizontal prefilter should be turned on. Table 33.12 Horizontal Prefilter Settings Input Format RES_PFIL_SEL Operation YCbCr input 1 Turns on the horizontal prefilter for Y signal and turns off the horizontal prefilter for Cb/Cr signal. 0 Turns off the horizontal prefilter. 1 Turns on the horizontal prefilter for RGB signal. 0 Turns off the horizontal prefilter. RGB input Table 33.13 Horizontal Prefilter Control Register Name Bit Name Initial Value Description SCL0_DS4 RES_PFIL_SEL 0 Prefilter Mode Select for Brightness Signals 0: The prefilter is turned off. 1: The prefilter is turned on. (1/4  1/2  1/4) 33.1.7 Horizontal Scale-Down The number of horizontally arranged pixels can be decreased at a desired ratio in the range of 1/1 to 1/8 using pixel conversion. For the scaling filter, either hold or linear interpolation mode can be selected. (1) One-TAP Hold Interpolation When the interpolation position is between input pixels Xn and Xn+1, the Xinterpo interpolation value is defined as follows. Xinterpo = Xn Page 1968 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 33 Video Display Controller 4 (3): Scaler Two-TAP Linear Interpolation When the interpolation position is between input pixels Xn and Xn+1, the Xinterpo interpolation value is defined as follows based on the interpolation position "phase". Xinterpo = (Xn × (4096  phase) + Xn+1 × phase) / 4096 (3) Calculation of Horizontal Scale Down Ratio The value to be set to the horizontal scale-down ratio RES_DS_H_RATIO can be obtained using the following equation based on the number of input pixels RES_HW and number of output pixels RES_OUT_HW, where the decimals are rounded off. RES_DS_H_RATIO = round (RES_HW ÷ RES_OUT_HW × 4096) Note that, for 100% horizontal scale-up, the RES_HW and RES_OUT_HW values should be identical and the RES_DS_H_RATIO bits should be set to 4096. (4) Handling for Lack of Last-Input Pixel Interpolation is carried out between the second-last-input and last-input pixels to produce the lastoutput pixel at the right end of a screen. The interpolation position of the last-output pixel may be close to the second-last-input pixel depending on the horizontal scale-down ratio; in this case, it may appear that the last-input pixel is lacking. The undesirable influence by lack of last-input pixel can be decreased by appropriately adjusting the horizontal scale-down ratio using the following equations. Pre-adjustment horizontal scale-down ratio RATIO_org should be calculated first to find adjustment value , and then scale-down ratio RES_DS_H_RATIO should be determined. RATIO_org = round (RES_HW ÷ RES_OUT_HW × 4096)  = (RATIO_org × (RES_OUT_HW  1)  (RES_HW  1) × 4096) ÷ (RES_OUT_HW  1) RES_DS_H_RATIO = roundup (RATIO_org  ) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1969 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.14 Horizontal Scale Down Control Register Name Bit Name Initial Value Description SCL0_DS1 RES_DS_H_ON 1 Horizontal Scale Down On/Off 0: Off 1: On SCL0_DS7 RES_OUT_HW [10:0] 640 Number of Valid Horizontal Pixels Output by Scaling-down Control Block (Video-image clock cycles) SCL0_DS4 RES_DS_H_ INTERPOTYP 1 Horizontal Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation SCL0_DS4 RES_DS_H_RATIO 9224 [15:0] Horizontal Scale Down Ratio ([15:12]: Integer part, [11:0]: Decimal part) round(RES_HW ÷ RES_OUT_HW × 4096) RES_DS_H_RATIO < 4096: Setting prohibited RES_DS_H_RATIO = 4096: 100% scale up RES_DS_H_RATIO  4096: Scale down Note: The RES_OUT_HW value should be aligned in 4-pixel units and equal to or smaller than the RES_HW value. 33.1.8 Vertical Scale-Down The number of lines can be decreased in the vertical direction at a desired ratio in the range of 1/1 to 1/8 using pixel conversion. For the scaling filter, either hold or linear interpolation mode can be selected. (1) One-TAP Hold Interpolation When the interpolation position is between input lines Xn and Xn+1, the Xinterpo interpolation value is defined as follows. Xinterpo = Xn Page 1970 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 33 Video Display Controller 4 (3): Scaler Two-TAP Linear Interpolation When the interpolation position is between input lines Xn and Xn+1, the Xinterpo interpolation value is defined as follows based on the interpolation position "phase". Xinterpo = (Xn × (4096  phase) + Xn+1 × phase) / 4096 (3) Calculation of Vertical Scale Down Ratio The value to be set to the vertical scale-down ratio RES_V_RATIO can be obtained using the following equation based on the number of input lines RES_VW and number of output lines RES_OUT_VW, where the decimals are rounded off. RES_V_RATIO = round (RES_VW ÷ RES_OUT_VW × 4096) Note that the RES_VW and RES_OUT_VW values should be identical for vertical enlargement or 100% vertical enlargement. For 100% vertical enlargement, reduction is carried out assuming RES_V_RATIO as 4096. (4) Handling for Lack of Last-Input Line Interpolation is carried out between the second-last-input and last-input lines to produce the lastoutput line at the lower end of a screen. The interpolation position of the last-output line may be close to the second-last-input line depending on the vertical scale-down ratio; in this case, it may appear that the last-input line is lacking. The undesirable influence by the lack of last-input line can be decreased by appropriately adjusting the vertical scale-down ratio using the following equations. Pre-adjustment vertical scale-down ratio RATIO_org should be calculated first to find adjustment value , and then scale-down ratio RES_V_RATIO should be determined. RATIO_org = round (RES_VW ÷ RES_OUT_VW × 4096)  = (RATIO_org × (RES_OUT_VW  1)  (RES_VW  1) × 4096) ÷ (RES_OUT_VW  1) RES_V_RATIO = round (RATIO_org  ) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1971 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.15 Vertical Scale Down Control Register Name Bit Name Initial Value Description SCL0_DS1 RES_DS_V_ON 1 Vertical Scale Down On/Off 0: Off 1: On SCL0_DS7 RES_OUT_VW[10:0] 240 Number of Valid Lines in Vertical Direction Output by Scaling-Down Control Block (lines) This bit setting is used for the number of lines to be written to the frame buffer. When SCL1_WR1.RES_LOOP is 0 (frame write mode), these bits specify the number of lines for one frame. When SCL1_WR1.RES_LOOP is 1 (line write mode), these bits specify the number of lines for writing in a ring configuration. SCL0_DS5 RES_V_INTERPOTYP 1 Vertical Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation SCL0_DS6 RES_V_RATIO[15:0] 2044 Vertical Scale UP/Down Ratio ([15:12]: Integer part, [11:0]: Decimal part) For scale down: round(RES_VW ÷ RES_OUT_VW × 4096) For scale up: round(RES_IN_VW ÷ RES_P_VW × 4096) RES_V_RATIO < 4096: Scale up RES_V_RATIO = 4096: 100% scale up RES_V_RATIO  4096: Scale down Note: RES_V_RATIO and RES_V_INTERPOTYP are both shared by vertical reduction and vertical enlargement. It is impossible to use vertical reduction and vertical enlargement simultaneously because they are mutually exclusive. The RES_OUT_VW value should be aligned in 4-line units and equal to or smaller than the RES_VW value. Page 1972 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.1.9 Section 33 Video Display Controller 4 (3): Scaler Horizontal Scale Up The number of horizontally arranged pixels can be increased at a desired ratio in the range of 1/1 to 8/1 using pixel conversion. For the scaling filter, either hold or linear interpolation mode can be selected. (1) One-TAP Hold Interpolation When the interpolation position is between input pixels Xn and Xn+1, the Xinterpo interpolation value is defined as follows. Xinterpo = Xn (2) Two-TAP Linear Interpolation When the interpolation position is between input pixels Xn and Xn+1, the Xinterpo interpolation value is defined as follows based on the interpolation position "phase". Xinterpo = (Xn × (4096  phase) + Xn+1 × phase) / 4096 (3) Calculation of Horizontal Scale Up Ratio The value to be set to the horizontal scale-up ratio RES_US_H_RATIO can be obtained using the following equation based on the number of input pixels RES_IN_HW and number of output pixels RES_P_HW, where the decimals are rounded off. RES_US_H_RATIO = round (RES_IN_HW ÷ RES_P_HW × 4096) Note that, for 100% horizontal scale-up, the RES_IN_HW and RES_P_HW values should be identical and the RES_US_H_RATIO bits should be set to 4096. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1973 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (4) Folding Handling Since interpolation is carried out between the last-input pixel and second-last-input folding pixel to produce the last-output pixel at the right end of a screen, folding may undesirably stand out depending on the horizontal scale up ratio. The undesirable influence by folding pixels can be decreased by appropriately adjusting the horizontal scale-up ratio using the following equations. Pre-adjustment horizontal scale-up ratio RATIO_org should be calculated first to find adjustment value , and then scale-up ratio RES_US_H_RATIO should be determined. RATIO_org = round (RES_IN_HW ÷ RES_P_HW × 4096)  = (RATIO_org × (RES_P_HW  1)  (RES_IN_HW  1) × 4096 ÷ (RES_P_HW  1) RES_US_H_RATIO = round (RATIO_org  ) Table 33.16 Horizontal Scale Up Control Register Name Bit Name Initial Value Description SCL0_US1 1 Horizontal Scale Up On/Off RES_US_H_ON 0: Off 1: On SCL0_US4 RES_IN_HW[10:0] 640 Number of Valid Horizontal Pixels Input to Scaling-down Control Block (Pixel-clock cycles) SCL0_US6 RES_US_H_ INTERPOTYP 1 Horizontal Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation SCL0_US5 RES_US_H_RATIO [15:0] 9224 Horizontal Scale Up Ratio ([15:12]: Integer part, [11:0]: Decimal part) round(RES_IN_HW ÷ RES_P_HW × 4096) RES_US_H_RATIO < 4096: Scale up RES_US_H_RATIO = 4096: 100% scale-up RES_US_H_RATIO  4096: Setting prohibited Page 1974 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.10 Vertical Scale-Up The number of lines can be increased in the vertical direction at a desired ratio in the range of 1/1 to 8/1 using pixel conversion. For the scaling filter, either hold or linear interpolation mode can be selected. (1) One-TAP Hold Interpolation When the interpolation position is between input lines Xn and Xn+1, the Xinterpo interpolation value is defined as follows. Xinterpo = Xn (2) Two-TAP Linear Interpolation When the interpolation position is between input lines Xn and Xn+1, the Xinterpo interpolation value is defined as follows based on the interpolation position "phase". Xinterpo = (Xn × (4096  phase) + Xn+1 × phase) / 4096 (3) Calculation of Vertical Scale Up Ratio The value to be set to the vertical scale-up ratio RES_V_RATIO can be obtained using the following equation based on the number of input lines RES_IN_VW and number of output lines RES_P_VW, where the decimals are rounded off. RES_V_RATIO = round (RES_IN_VW ÷ RES_P_VW × 4096) Note that, for 100% vertical enlargement or vertical reduction, the RES_IN_VW and RES_P_VW values should be identical. (4) Folding Handling The last line to be output at the bottom of the screen is produced by interpolation between the last line and line for folding (second-last line to be input). According to the vertical scale-up rate, this may cause folding to stand out. The undesirable influence by folding lines can be decreased by appropriately adjusting the vertical scale-up ratio using the following equations. Pre-adjustment vertical scale-up ratio RATIO_org should be calculated first to find adjustment value , and then scale-up ratio RES_V_RATIO should be determined. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1975 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler RATIO_org = round (RES_IN_VW ÷ RES_P_VW × 4096)  = (RATIO_org × (RES_P_VW  1)  (RES_IN_VW  1) × 4096) ÷ (RES_P_VW  1) RES_V_RATIO = round (RATIO_org  ) Table 33.17 Vertical Scale Up Control Register Name Bit Name Initial Value Description SCL0_US1 RES_US_V_ON 1 Vertical Scale Up On/Off 0: Off 1: On SCL0_US4 RES_IN_VW[10:0] 240 Number of Valid Lines in Vertical Direction Input to Scaling-down Control Block (Lines) SCL0_DS5 RES_V_INTERPOTYP 1 Vertical Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation SCL0_DS6 RES_V_RATIO[15:0] 2044 Vertical Scale Up Ratio ([15:12]: Integer part, [11:0]: Decimal part) For scale down: round(RES_VW ÷ RES_OUT_VW × 4096) For scale up: round(RES_IN_VW ÷ RES_P_VW × 4096) RES_V_RATIO < 4096: Scale up RES_V_RATIO = 4096: 100% scale up RES_V_RATIO  4096: Scale down Note: RES_V_RATIO and RES_V_INTERPOTYP are both shared by vertical reduction and vertical enlargement. It is impossible to use vertical reduction and vertical enlargement simultaneously because they are mutually exclusive. Page 1976 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.11 IP Conversion (1) Initial Phase Control When interlace signals are input, line flickering caused by the line offset between the top and bottom fields can be decreased before being displayed by independently adjusting the initial scaling phases of the fields. For various operations, appropriate settings should be made referring to the relevant registers as listed in table 33.18. Table 33.18 Initial Scaling Phase Settings (Standard Values) for IP Conversion Rotation Horizontal Scaling Vertical Scaling Reference Bit (Setting) Normal Horizontal scale down Vertical scale down RES_TOP_INIPHASE = 2048 Horizontal scale down Vertical scale up RES_TOP_INIPHASE = 2048 Horizontal scale up Vertical scale down RES_TOP_INIPHASE = 2048 Horizontal scale up Vertical scale up RES_TOP_INIPHASE = 2048 Horizontal scale down Vertical scale down RES_TOP_INIPHASE = 2048 Horizontal scale down Vertical scale up RES_TOP_INIPHASE = 2048 Horizontal scale up Vertical scale down RES_TOP_INIPHASE = 2048 Horizontal scale up Vertical scale up RES_TOP_INIPHASE = 2048 (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale down RES_TOP_INIPHASE = 2048 (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale up RES_TOP_INIPHASE = 2048 (Horizontal input  vertical output) scale up (Vertical input  horizontal output) scale up RES_US_HB_INIPHASE = 2048 Horizontal mirroring 90 rotation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1977 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Rotation Horizontal Scaling Vertical Scaling Reference Bit (Setting) 180 rotation Horizontal scale down Vertical scale down RES_TOP_INIPHASE = 2048 Horizontal scale down Vertical scale up RES_BTM_INIPHASE = 2048 Horizontal scale up Vertical scale down RES_TOP_INIPHASE = 2048 Horizontal scale up Vertical scale up RES_BTM_INIPHASE = 2048 (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale down RES_TOP_INIPHASE = 2048 (Horizontal input  vertical output) scale down (Vertical input  horizontal output) scale up RES_TOP_INIPHASE = 2048 (Horizontal input  vertical output) scale up (Vertical input  horizontal output) scale up RES_US_HT_INIPHASE = 2048 270 rotation Note: Set 0 to the initial phase control registers where the specific value is not shown in the table. Set 0 to all the initial phase control registers when progressive signals are input. Table 33.19 Initial Scaling Phase Control Register Name Bit Name SCL0_DS5 RES_BTM_INIPHASE [11:0] Initial Value 0 Description Vertical Interpolation Start Phase for Bottom Field 0 to 4095 (0 to approx.1.0) SCL0_DS5 RES_TOP_INIPHASE [11:0] 2048 Vertical Interpolation Start Phase for Top Field 0 to 4095 (0 to approx.1.0) SCL0_US6 RES_US_HB_INIPHASE 0 [11:0] Horizontal Interpolation Start Phase for Bottom Field 0 to 4095 (0 to approx.1.0) SCL0_US6 RES_US_HT_INIPHASE [11:0] 0 Horizontal Interpolation Start Phase for Top Field 0 to 4095 (0 to approx.1.0) Page 1978 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Progressive image (1) (2) (3) (4) (5) (6) P-I conversion Interlaced image (TOP) (1) Interlaced image (BOTTOM) Initial phase = 2048 (3) (5) … 0.5 × (1) + 0.5 × (3) (2) (3) 0.5 × (2) + 0.5 × (4) 0.5 × (3) + 0.5 × (5) (4) (5) 0.5 × (4) + 0.5 × (6) … (6) … … (2) (4) (6) … I-P conversion Progressive image after IP conversion I-P conversion Figure 33.11 IP Conversion Processing Schematic Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1979 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (2) Field Determination Signal Control When interlace signals are input, the field determination signal can be controlled, which is output to the scaling-up control block during vertical scaling. When progressive signals are input or vertical scaling is carried out by the scaling-down control block, the field determination signal output to the scaling-up control block is fixed to the specific level, and thus either 0 or 1 can be set to the RES_FLD_DLY_SEL bit. Table 33.20 Settings for Field Determination Signal Control Input Signal Rotation Vertical Processing Frame Buffer RES_FLD_DLY_SEL Progressive     Interlace Normal Vertical scale down   Vertical scale up One plane or less 0 Horizontal mirroring 180 rotation 90 rotation 270 rotation Two planes or more 1 (Horizontal input   vertical output) scale down  (Horizontal input Two planes or  vertical output) more scale up 1 Table 33.21 Field Determination Signal Control Register Name Bit Name Initial Value Description SCL0_FRC5 RES_FLD_DLY_SEL 1 Field Determination Signal Delay Control 0: No delay 1: Delay of one vertical cycle Page 1980 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 33 Video Display Controller 4 (3): Scaler Switching of the Field Determination Signal (R version only) The source of the field determination signal to be output to the scaling-up control block can be switched. Table 33.22 Switching the Field Determination Signal Register Name Bit Name Initial Value Description SCL0_FRC8 RES_US_FLD 0 Field Determination Signal Switching 0: The field determination signal is generated by the synchronization control block. 1: Frame number to be read (0: top field, 1: bottom field) Note: When RES_FLM_MD is 0, set this bit to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1981 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.12 Trimming The upper, lower, right, and left parts of a post-scaling image can be trimmed off as specified by the RES_VCUT and RES_HCUT bits before being output. The frame lines of the post-scaling image can also be displayed by setting the RES_DISP_ON bit to 1. Vsync Hsync Vertical enable signal start position [line] = RES_P_VS 1[clk] Output image area 1[line] 1[clk] Vertical trimming width [line] = RES_VCUT Horizontal trimming width [clk] = RES_HCUT Output area after trimming Vertical width [line] =RES_P_VW 1[line] White data output Horizontal width [clk] =RES_P_HW Horizontal enable signal start position [clk] =RES_P_HS Figure 33.12 Area Relationship for Trimming (Frame Lines Displayed) Page 1982 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.23 Trimming Control Register Name Bit Name Initial Value SCL0_US7 RES_HCUT[7:0] 0 SCL0_US7 RES_VCUT[7:0] 0 Description Horizontal Amount of Cut-off Post-Scaling Image (Right and Left Parts) Sets the number of pixel-clock cycles. Vertical Amount of Cut-off Post-Scaling Image (Upper and Lower Parts) Sets the number of lines. SCL0_US8 RES_DISP_ON 0 Post-Scaling Image Frame Display On/Off 0: Frame display on 1: Frame display off 33.1.13 Screen Synthesis During the valid full-screen period, the image area can be overlayed before being output. If the image area to be output is smaller than a full-screen, the background color specified by the RES_BK_COL_R, RES_BK_COL_G, and RES_BK_COL_B bits are displayed to fill the background. Table 33.24 Screen Synthesis Control Register Name Bit Name SCL0_OVR1 SCL0_OVR1 SCL0_OVR1 Initial Value RES_BK_COL_R[7:0] 128 RES_BK_COL_B[7:0] 128 RES_BK_COL_G[7:0] 0 Description Background Color Setting R/Cr Signal R: 8 bits; unsigned (0 to 255 [LSB]) Cr: 8 bits; 128 offset binary; unsigned (0 to 255 [LSB]) Background Color Setting B/Cb Signal B: 8 bits; unsigned (0 to 255 [LSB]) Cb: 8 bits; 128 offset binary; unsigned (0 to 255 [LSB]) Background Color Setting G/Y Signal G/Y: 8 bits; unsigned (0 to 255 [LSB]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1983 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler RES_P_VS Vsync Hsync RES_F_VS Output full-image area RES_P_HS RES_P_VW Output image area RES_F_VW RES_P_HW Specifying the color with RES_BK_COL_R, RES_BK_COL_G, and RES_BK_COL_B RES_F_HS RES_F_HW Figure 33.13 Area Relationship with Output Image Size Smaller than a Full Screen Page 1984 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.14 Selecting Format for Writing Video Image Signals to Frame Buffer A format can be selected for writing video image signals to the frame buffer. Although 24-bit YCbCr signals or 24-bit RGB signals are input to the scaling control block, they are converted into 16-bit YCbCr422 signals, 16-bit RGB565 signals, or 32-bit RGB888 signals before being written to the frame buffer. As bit reduction processing of RGB565, rounding off or 2  2 pattern dither can be selected with the RES_DTH_ON bit. For details on pattern dither, see section 36.1.7, Dither Process in section 36, Video Display Controller 4 (6): Output Controller. Input YCbCr signals are converted into YCbCr422 signals and output to the image renderer. For distortion correction, refer to section 38, Image Renderer (IMR-LS). Table 33.25 Frame Buffer Writing Mode Setting RES_BITDEC_ON RES_MD[1:0] Writing Mode 0 2 RGB888 (normal, horizontal mirroring) 1 1 RGB565 (normal, horizontal mirroring, rotation) 0 0 YCbCr422 (normal, horizontal mirroring, rotation) 1 0 YCbCr422 (distortion correction) Table 33.26 Video Signal Writing Format Selection Control Register Name Bit Name Initial Value Description SCL1_WR1 RES_MD[1:0] 0 Frame Buffer Video-Signal Writing Format 0: YCbCr422 (16 bits) 1: RGB565 (16 bits) 2: RGB888 (24 (32) bits) 3: Setting prohibited SCL1_WR6 RES_BITDEC_ON 0 Bit Reduction On/Off 0: Off 1: On SCL1_WR6 RES_DTH_ON 0 Dither Correction On/Off 0: Off (rounded off) 1: On (2  2 pattern dither) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1985 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.15 Horizontal Mirroring and Rotation Horizontal mirroring and rotation can be carried out for scaled-down images before being written to the frame buffer. Tables 33.27 and 33.28 show the relationship between various writing modes for image processing and video signals. Table 33.27 Relationship between Writing Modes and Video Signals RES_DS_WR_MD[2:0] Writing Modes YCbCr422 RGB565 RGB888 0 Normal writing Enabled Enabled Enabled 1 Horizontal mirroring Enabled Enabled Enabled 2 90 rotation Enabled Enabled Disabled 3 180 rotation Enabled Enabled Disabled 4 270 rotation Enabled Enabled Disabled 5 to 7 Setting prohibited    Table 33.28 Horizontal Mirroring and Rotation Control Register Name Bit Name Initial Value SCL1_WR1 RES_DS_WR_MD[2:0] 0 Description Frame Buffer Writing Mode for Image Processing 0: Normal 1: Horizontal mirroring 2: 90 rotation 3: 180 rotation 4: 270 rotation 5 to 7: Setting prohibited Page 1986 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.1.16 Writing to Frame Buffer (1) Frame Buffer Transfer Mode Either 32-byte or 128-byte transfer mode can be selected for accessing the frame buffer in which video image data and graphics data are stored. Table 33.29 Frame Buffer Transfer Mode Register Name Bit Name Initial Value Description SCL1_WR1 0 Transfer Burst Length for Frame Buffer Writing RES_BST_MD 0: 32-byte 1: 128-byte (2) Frame Buffer Write Control Frame buffer writing is enabled or disabled. Table 33.30 Frame Buffer Writing Control Register Name Bit Name Initial Value Description SCL1_WR5 0 Frame Buffer Write Enable RES_WENB After making the setting to enable writing, writing starts from the second frame. 0: Frame buffer writing is disabled. 1: Frame buffer writing is enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1987 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (3) Frame Buffer Writing Rate Selection A frame buffer writing rate can be selected from among 1/1, 1/2, 1/4, and 1/8 the vertical frequency of the input signal. When 1/2, 1/4, or 1/8 is selected, either the top or bottom field can be selected for writing. Table 33.31 Frame Buffer Write Control Initial Value Register Name Bit Name SCL1_WR5 RES_FS_RATE[1:0] 0 Description Writing Rate Sets the frame buffer writing rate to the vertical frequency of the input signal. 0: 1/1 an input signal (The RES_FLD_SEL setting is invalid.) 1: 1/2 an input signal 2: 1/4 an input signal 3: 1/8 an input signal SCL1_WR5 RES_FLD_SEL 0 Write Field Select 0: Top field 1: Bottom field SCL1_WR5 RES_INTER 1 Field Operating Mode Select 0: Progressive 1: Interlace (4) Frame Buffer Write Addresses Frame buffer addresses are specified using the base address, line offset address, frame offset address, data size of a line, and the number of lines in a frame. The frame buffer address generation mode is selectable (R version only). The RES_BASE[31:0], RES_LN_OFF[14:0], and RES_FLM_OFF[22:0] bits should be set in 32byte units (the lower five bits should be fixed to 0). For 128-byte transfer, bits [6:5] in the address control registers should be fixed to 0 since addresses should be specified in 128-byte units. For the data size of a line and the number of lines in a frame, the relevant register values set for the scaling-down control block are used. Page 1988 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.32 Frame Buffer Write Address Control Register Name Bit Name Initial Value SCL1_WR1 RES_FLM_MD 0 Description Frame Buffer Address Generation Mode Select 0: RES_BASE  RES_FLM_OFF × frame number 1: RES_BASE  RES_FLM_OFF × field information (top field: 0; bottom field: 1) Note: This bit should be set to 0 when a progressive signal is being input. When the setting of this bit is 1, the setting for frame buffers should be for the use of two. This bit is only provided in the R version. In products other than the R version, this bit is always read as 0, and when writing, the value written should always be 0. SCL1_WR2 RES_BASE[31:0] 0 Frame Buffer Base Address Sets the start address of the frame buffer where frame data is to be stored. For 32-byte transfer: The lower five bits should be fixed to 0_0000. For 128-byte transfer: The lower seven bits should be fixed to 000_0000. SCL1_WR3 RES_LN_OFF[14:0] 2048 Frame Buffer Line Offset Address Sets the line offset address for calculating the start address of each line. Line 0: RES_BASE Line 1: RES_BASE  RES_LN_OFF × 1 : Line n: RES_BASE  RES_LN_OFF × n For 32-byte transfer: The lower five bits should be fixed to 0_0000. For 128-byte transfer: The lower seven bits should be fixed to 000_0000. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1989 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Register Name Bit Name Initial Value Description SCL1_WR4 RES_FLM_OFF[22:0] 524288 Frame Buffer Frame Offset Address Sets the frame offset address for calculating the start address of each frame. Buffer 0: RES_BASE Buffer 1: RES_BASE  RES_FLM_OFF × 1 : Buffer n: RES_BASE  RES_FLM_OFF × n For 32-byte transfer: The lower five bits should be fixed to 0_0000. For 128-byte transfer: The lower seven bits should be fixed to 000_0000. RES_BASE RES_OUT_VW RES_HW RES_FLM_OFF RES_HS RES_VS +1 Frame offset Input Vsync signal RES_OUT_HW Number of pixels in horizontal direction Number of lines in vertical direction Start address Input Hsync signal Image area to be captured RES_VW RES_OUT_VW for 90° or 270° rotation RES_LN_OFF Line offset After 100% scale-up/down or scale-down processing is performed, data is written to the frame buffer. RES_OUT_HW for 90° or 270° rotation RES_OUT_HW RES_OUT_VW Number of lines in vertical direction Number of pixels in horizontal direction Figure 33.14 Data Arrangement in Frame Buffer Page 1990 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Write start address Normal Horizontal mirroring 90° rotation 180° rotation 270° rotation Figure 33.15 Data Arrangement in Frame Buffer in Various Writing Modes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1991 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (5) Frame Buffer Management The scaling control block can handle multiple frames as the frame buffer. Data is written to the buffer in cyclic mode according to the number of frames specified by the RES_FLM_NUM bits. For rotation, the RES_FLM_NUM bits should be set to 1 (2 frames). To use the frame buffer as the ring buffer in line mode, the RES_FLM_NUM bits should be set to 0 (1 frame) and the RES_LOOP bit to 1. Table 33.33 Frame Buffer Write Control Register Name Bit Name SCL1_WR3 RES_FLM_NUM [9:0] Initial Value 1 Description Number of Frames of Buffer to be Written to Number of frames defined by RES_FLM_NUM  1 are used. For normal image display: 0 or 1(one or two planes) For horizontal mirror image display: 0 or 1 (one or two planes) For rotated image display: 1 (2 planes) For video recording: the number of frames to be stored  1 SCL1_WR1 RES_LOOP 0 Frame Buffer Write Mode Select 0: Frame mode 1: Line mode (read as ring buffer) SCL1_WR7 Page 1992 of 3092 RES_FLM_CNT [9:0]  Frame Number of Frame Immediately Before That Currently Being Accessed R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 33 Video Display Controller 4 (3): Scaler Buffer Overflow Handling If writing to the frame buffer cannot be completed due to bus-traffic related problems, an overflow interrupt can be output to the interrupt controller. Table 33.34 Buffer Overflow Detection Register Name Bit Name Initial Value Description SCL1_WR7 RES_OVERFLOW  Line Buffer Overflow Detect 1: Line buffer has overflowed. 0: Line buffer has not overflowed. (7) Frame Buffer Write End Flag When writing one frame of data to the frame buffer is completed, a frame buffer write end interrupt can be output to the interrupt controller. 33.1.17 Selecting a Scaling-up Process or Graphics 1 Process Scaling-up process and graphics 1 process are mutually exclusive and thus frame buffer cannot be read out simultaneously for the processes. When displaying input video image signals or displaying enlarged graphics, data is read from the frame buffer via the scaling-up control block. However, graphics can be enlarged and displayed by the scaling-up control block only when the RGB565, RGB888, or YCbCr422 format is used. When displaying graphics without enlargement, the data is read from the frame buffer via the graphics 1 processing block. With the RES_IBUS_SYNC_SEL bit, sync signals for reading out the frame buffer and read size setting bits are selected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1993 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Table 33.35 Selection of Scaling-Up Process and Graphics 1 Process Type of Output Scaling Display RES_IBUS_ Sync Signals for Frame Buffer Read Display Enabling SYNC_SEL Frame Buffer Read Size Setting Bits Bits Input video signal display 0 Output from scaling- RES_IN_VW up control block RES_IN_HW Enlarged graphics display Graphics display RES_P_VS RES_P_VW RES_P_HS RES_P_HW 1 Output from graphics 1 processing block GR1_FLM_LNUM* GR1_GRC_VS GR1_HW* GR1_GRC_VW GR1_GRC_HS GR1_GRC_HW Note: * The value set to the register + 1 is the actual read size. GR1_BASE Start address Output Hsync signal RES_F_HW RES_P_VS RES_F_HS RES_F_VS RES_IN_VW Number of lines in vertical direction Frame offset GR1_FLM_OFF Number of pixels in horizontal direction Output Vsync signal RES_IN_HW Output full-image area RES_P_HS RES_P_HW RES_IN_VW Number of lines in vertical direction RES_IN_HW Number of pixels in horizontal direction RES_P_VW Read from the frame buffer and scaled up Line offset RES_F_VW Output image area GR1_LN_OFF Figure 33.16 Area Setting for Input Video Image Signal Display and Enlarged Graphics Display Page 1994 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler GR1_BASE Start address Output Hsync signal RES_F_HW GR1_GRC_ VS Output Vsync signal RES_F_HS RES_F_VS Number of lines in vertical direction GR1_FLM_OFF Frame offset Number of pixels in horizontal direction GR1_FLM_LNUM+1 GR1_HW+1 Output full-image area GR1_GRC_ HS GR1_GRC_HW Number of lines in vertical direction GR1_FLM_LNUM+1 GR1_HW+1 Number of pixels in horizontal direction GR1_GRC_VW Read from the frame buffer RES_F_VW Output image area GR1_LN_OFF Line offset Figure 33.17 Area Setting for Graphics Display Table 33.36 Scaling-Up Process or Graphics 1 Process Selection Register Name Bit Name Initial Value SCL0_US8 RES_IBUS_SYNC_SEL 0 Description Sync Signal Select for Frame Buffer Read Block 0: Sync signals from the scaling-up control block 1: Sync signals from the graphics processing block The GR1_DISP_SEL bits are used to select a display by the scaling-up control block (video image display or enlarged graphics display) or graphics display. For details on the graphics processing, refer to the section "Image Synthesizer" described below. 33.1.18 Reading from Frame Buffer For frame buffer read operation and graphics processing, refer to the section "Image Synthesizer" to be described. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1995 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2 Register Descriptions Table 33.37 shows the register configuration.  Symbols used in Register Description: Initial value: Register value after a reset : Undefined value R/W: Readable/writable. The written value can be read. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored. R/WC1: Readable/writable. Writing 1 initializes the bit. Writing 0 is ignored. R: Read-only. The write value should always be 0. /W: Write-only. The read value is undefined. Table 33.37 Register Configuration of the Scaler Initial Value Address Access Size SCL0_UPDATE R/WC1 H'0000 0000 H'FFFF 7500 32/16 Mask control register SCL0_FRC1 R/W H'0AF0 0001 H'FFFF 7504 32/16 Missing Vsync compensation control register SCL0_FRC2 R/W H'0E10 0001 H'FFFF 7508 32/16 Output sync select register SCL0_FRC3 R/W H'0000 0001 H'FFFF 750C 32/16 Free-running period control register SCL0_FRC4 R/W H'020C 031F H'FFFF 7510 32/16 Output delay control register SCL0_FRC5 R/W H'0000 0101 H'FFFF 7514 32/16 Full-screen vertical size register SCL0_FRC6 R/W H'0023 01E0 H'FFFF 7518 32/16 Full-screen horizontal size register SCL0_FRC7 R/W H'0090 0280 H'FFFF 751C 32/16 Field determination signal switching SCL0_FRC8 register (R version only) R/W H'0000 0011 H'FFFF 7520 32/16 Vsync detection register SCL0_FRC9 R H'0000 0000 H'FFFF 7524 32/16 Scaling-down control register SCL0_DS1 R/W H'0000 0011 H'FFFF 752C 32/16 Vertical capture size register SCL0_DS2 R/W H'0012 00F0 H'FFFF 7530 32/16 Horizontal capture size register SCL0_DS3 R/W H'00F4 05A0 H'FFFF 7534 32/16 Horizontal scale down register SCL0_DS4 R/W H'1000 2408 H'FFFF 7538 32/16 Initial vertical phase register SCL0_DS5 R/W H'1800 0000 H'FFFF 753C 32/16 Vertical scaling register SCL0_DS6 R/W H'0000 07FC H'FFFF 7540 Name Abbreviation SCL0 register update control register Page 1996 of 3092 R/W 32/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Name Abbreviation R/W Initial Value Address Access Size Scaling-down control block output size register SCL0_DS7 R/W H'00F0 0280 H'FFFF 7544 32/16 Scaling-up control register SCL0_US1 R/W H'0000 0011 H'FFFF 7548 32/16 Output image vertical size register SCL0_US2 R/W H'0023 01E0 H'FFFF 754C 32/16 Output image horizontal size register SCL0_US3 R/W H'0090 0280 H'FFFF 7550 32/16 Scaling-up control block input size register SCL0_US4 R/W H'00F0 0280 H'FFFF 7554 32/16 Horizontal scale up register SCL0_US5 R/W H'0000 2408 H'FFFF 7558 32/16 Horizontal scale up initial phase register SCL0_US6 R/W H'1000 0000 H'FFFF 755C 32/16 Trimming register SCL0_US7 R/W H'0000 0000 H'FFFF 7560 32/16 Frame buffer read select register SCL0_US8 R/W H'0000 0000 H'FFFF 7564 32/16 Background color register SCL0_OVR1 R/W H'0080 0080 H'FFFF 756C 32/16 SCL1 register update control register SCL1_UPDATE R/WC1 H'0000 0000 H'FFFF 7580 32/16 Writing mode register SCL1_WR1 R/W H'0000 0000 H'FFFF 7588 32/16 Write address register 1 SCL1_WR2 R/W H'0000 0000 H'FFFF 758C 32/16 Write address register 2 SCL1_WR3 R/W H'0800 0001 H'FFFF 7590 32/16 Write address register 3 SCL1_WR4 R/W H'0008 0000 H'FFFF 7594 32/16 Frame sub-sampling register SCL1_WR5 R/W H'0000 1000 H'FFFF 759C 32/16 Bit reduction register SCL1_WR6 R/W H'0000 0000 H'FFFF 75A0 32/16 Write detection register SCL1_WR7 R H'0000 0000 H'FFFF 75A4 32/16 Graphics 1 register update control register GR1_UPDATE R/WC1 H'0000 0000 H'FFFF 7600 32/16 Frame buffer read control register (Graphics 1) GR1_FLM_RD R/W H'0000 0000 H'FFFF 7604 32/16 Frame buffer control register 1 (Graphics 1) GR1_FLM1 R/W H'0000 0000 H'FFFF 7608 32/16 Frame buffer control register 2 (Graphics 1) GR1_FLM2 R/W H'0000 0000 H'FFFF 760C 32/16 Frame buffer control register 3 (Graphics 1) GR1_FLM3 R/W H'0800 0001 H'FFFF 7610 32/16 Frame buffer control register 4 (Graphics 1) GR1_FLM4 R/W H'0008 0000 H'FFFF 7614 32/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1997 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Name Abbreviation R/W Initial Value Address Access Size Frame buffer control register 5 (Graphics 1) GR1_FLM5 R/W H'0000 03FF H'FFFF 7618 32/16 Frame buffer control register 6 (Graphics 1) GR1_FLM6 R/W H'8000 0000 H'FFFF 761C 32/16 Alpha blending control register 1 (Graphics 1) GR1_AB1 R/W H'0000 0000 H'FFFF 7620 32/16 Alpha blending control register 2 (Graphics 1) GR1_AB2 R/W H'0000 0000 H'FFFF 7624 32/16 Alpha blending control register 3 (Graphics 1) GR1_AB3 R/W H'0000 0000 H'FFFF 7628 32/16 Alpha blending control register 7 (Graphics 1) GR1_AB7 R/W H'00FF 0000 H'FFFF 7638 32/16 Alpha blending control register 8 (Graphics 1) GR1_AB8 R/W H'0000 0000 H'FFFF 763C 32/16 Alpha blending control register 9 (Graphics 1) GR1_AB9 R/W H'0000 0000 H'FFFF 7640 32/16 Alpha blending control register 10 (Graphics 1) GR1_AB10 R/W H'0000 0000 H'FFFF 7644 32/16 Alpha blending control register 11 (Graphics 1) GR1_AB11 R/W H'0000 0000 H'FFFF 7648 32/16 Background color control register (Graphics 1) GR1_BASE R/W H'0000 8080 H'FFFF 764C 32/16 CLUT table control register (Graphics 1) GR1_CLUT R/W H'0000 0000 H'FFFF 7650 32/16 Page 1998 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.2.1 Section 33 Video Display Controller 4 (3): Scaler SCL0 Register Update Control Register (SCL0_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      SCL0_U PDATE    SCL0_ VEN_B    SCL0_ VEN_A Initial value: 0 0 R/W: R R SCL0_ SCL0_ VEN_D VEN_C 0 0 R/WC1 R/WC1 0 0 0 0 0 0 0 0 0 0 0 0 R R R R/WC1 R R R R/WC1 R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 SCL0_ VEN_D 0 R/WC1 Scaling-Up Control and Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 12 SCL0_ VEN_C 0 R/WC1 Scaling-Down Control and Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 SCL0_ UPDATE 0 R/WC1 SYNC Control Register Update 0: Registers are not updated. 1: Registers are updated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 1999 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 SCL0_ VEN_B 0 R/WC1 Synchronization Control and Scaling-up Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 SCL0_ VEN_A 0 R/WC1 Scaling-Down Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2000 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.2.2 Section 33 Video Display Controller 4 (3): Scaler Mask Control Register (SCL0_FRC1) Bit: Initial value: 31 30 29 28 27 26 25 - - - - - - - 23 22 21 20 19 18 17 - - - - - - - - 16 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                RES_ VMASK_ ON 0 R/W: R/W Bit: 24 RES_VMASK[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R R R R R R R R R R/W Initial Value Bit Bit Name 31 to 16 RES_VMASK 2800 [15:0] R/W Description R/W Repeated Vsync Signal Masking Period Sets the repeated Vsync signal masking period beginning at a Vsync signal in terms of 128 pixelclock periods. Masking period [usec] = RES_VMASK  128 ÷ pixel clock frequency [MHz] 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_ VMASK_ON 1 R/W Repeated Vsync Signal Masking Control 0: Repeated Vsync signal masking control is disabled. 1: Repeated Vsync signal masking control is enabled. Note: This register is updated when the SCL0_UPDATE bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2001 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.3 Missing Vsync Compensation Control Register (SCL0_FRC2) Bit: Initial value: 31 30 29 28 27 26 25 - - - - - - - 23 22 21 20 19 18 17 - - - - - - - - RES_VLACK[15:0] 16 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                RES_ VLACK_ ON 0 R/W: R/W Bit: 24 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name 31 to 16 RES_ VLACK [15:0] Initial Value R/W Description 3600 R/W Missing-Sync Compensating Pulse Output Wait Time Sets the wait time before outputting a missing-sync compensating pulse after a Vsync signal. Wait time [usec] = RES_VLACK × 128 ÷ pixel clock frequency[MHz] 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_ 1 VLACK_ON R/W Missing Vsync Signal Compensation 0: Compensation of missing Vsync signals is disabled. 1: Compensation of missing Vsync signals is enabled. Note: This register is updated when the SCL0_UPDATE bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2002 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.2.4 Section 33 Video Display Controller 4 (3): Scaler Output Sync Select Register (SCL0_FRC3) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                RES_ VS_SEL Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 Reserved R These bits are always read as 0. The write value should always be 0. 0 RES_VS_ SEL 1 R/W Vsync Signal Output Select 0: Externally input Vsync signal 1: Internally generated free-running Vsync signal Note: This register is updated when the SCL0_UPDATE bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2003 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.5 Free-Running Period Control Register (SCL0_FRC4) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_FV[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - -RES_FH[10:0] - - - - - Initial value: 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 RES_FV [10:0] 524  All 0 R/W Free-Running Vsync Period Setting Free-running Vsync period = (RES_FV + 1) × horizontal period [usec] R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_FH [10:0] 799 R/W Hsync Period Setting Hsync period [usec] = (RES_FH +1) ÷ pixel clock frequency [MHz] Note: This register is updated when the SCL0_UPDATE bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2004 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.2.6 Section 33 Video Display Controller 4 (3): Scaler Output Delay Control Register (SCL0_FRC5) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        RES_ FLD_ DLY_SEL - - - - - - - Initial value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 9  All 0 R Reserved RES_VSDLY[7:0] These bits are always read as 0. The write value should always be 0. 8 RES_FLD_ 1 DLY_SEL R/W Field Determination Signal Delay Control 0: No delay 1: Delay of one vertical cycle 7 to 0 RES_ 1 VSDLY[7:0] R/W Vsync Signal Delay Control Adjusts the Vsync signal delay in the output Hsync period units. Vsync signal delay [usec]: RES_VSDLY × output Hsync period [usec] Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2005 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.7 Full-Screen Vertical Size Register (SCL0_FRC6) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 23 22 21 20 19 18 17 - - - - 0 0 0 1 1 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 RES_F_VW[10:0] - - - - - RES_F_VS[10:0] - 16 Initial value: 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_F_VS 35 [10:0] R/W Vertical Enable Signal Start Position for Full Screen. (VSYNC + V backporch lines) Note: The set value should be four or more (lines). RES_F_VS + RES_F_VW should be equal to or less than 2039 (lines). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_F_VW 480 [10:0] R/W Vertical Enable Signal Width for Full Screen (lines) Note: RES_F_VS + RES_F_VW should be equal to or less than 2039 (lines). Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2006 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.2.8 Section 33 Video Display Controller 4 (3): Scaler Full-Screen Horizontal Size Register (SCL0_FRC7) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_F_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - RES_F_HW[10:0] - - - - - Initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_F_HS 144 [10:0] R/W Horizontal Enable Signal Start Position for Full Screen. (HSYNC+H backporch pixel-clock cycles) Note: The set value should be 16 or more (clock cycles). RES_F_HS + RES_F_HW should be equal to or less than 2015 (clock cycles). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_F_HW 640 [10:0] R/W Horizontal Enable Signal Width for Full Screen (pixelclock cycles) Notes: 1. RES_F_HS + RES_F_HW should be equal to or less than 2015 (clock cycles). 2. The set value should be equal to (horizontal signal width for full screen + 2) when serial RGB output is selected as an LCD output signal. Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2007 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.9 Field Determination Signal Switching Register (SCL0_FRC8) (R version only) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      RES_ US_FLD           Bit: Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 R/W: R R R R R R/W R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 RES_US_ FLD 0 R/W Field Determination Signal Switching 0: The field determination signal is generated by the synchronization control block. 1: Frame number to be read (0: top field, 1: bottom field) Note: When RES_FLM_MD is 0, set this bit to 0. 9 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4  1 R Reserved This bit is always read as 1. The write value should always be 1. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0  1 R Reserved This bit is always read as 1. The write value should always be 1. Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2008 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.10 Vsync Detection Register (SCL0_FRC9) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            RES_ QVLOCK    RES_ QVLACK Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RES_ QVLOCK 0 R Locked Vsync Signal Detection Flag 1: No repeated or missing Vsync signal input has been detected for four or more vertical periods. 0: Repeated or missing Vsync signal input has been detected. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_ QVLACK 0 R Missing Vsync Signal Detection Flag 1: Missing Vsync signal input has been detected. 0: No missing Vsync signal input has been detected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2009 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.11 Scaling-Down Control Register (SCL0_DS1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            RES_DS_ V_ON    RES_DS_ H_ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 R/W: R R R R R R R R R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RES_DS_ V_ON 1 R/W Vertical Scale Down On/Off 0: Off 1: On 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_DS_ H_ON 1 R/W Horizontal Scale Down On/Off 0: Off 1: On Note: This register is updated when the SCL0_VEN_A bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2010 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.12 Vertical Capture Size Register (SCL0_DS2) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - RES_VW[10:0] - - - - - Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_VS [10:0] 18 R/W Vertical Position Setting for Video Signal Capturing (VSYNC + (V backporch - 1) lines) Note: The set value should be four or more (lines). RES_VS + RES_VW should be equal to or less than 2039 (lines). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_VW [10:0] 240 R/W Vertical Width of Video Signal to be Captured (Lines) Note: RES_VS + RES_VW should be equal to or less than 2039 (lines). Note: This register is updated when the SCL0_VEN_A bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2011 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.13 Horizontal Capture Size Register (SCL0_DS3) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - RES_HW[10:0] - - - - - Initial value: 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_HS [10:0] 244 R/W Horizontal Position Setting for Video Signal Capturing (HSYNC + H backporch video-image clock cycles) Note: The set value should be 16 or more (clock cycles). RES_HS + RES_HW should be equal to or less than 2015 (clock cycles). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_HW [10:0] 1440 R/W Horizontal Width of Video Signal to be Captured (Video-image clock cycles) Note: RES_HS + RES_HW should be equal to or less than 2015 (clock cycles). Note: This register is updated when the SCL0_VEN_A bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2012 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.14 Horizontal Scale Down Register (SCL0_DS4) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16   RES_PFIL_ SEL RES_DS_H_ INTERPO TYP             Initial value: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - Initial value: 0 R/W: R/W - RES_DS_H_RATIO[15:0] 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31, 30  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 29 RES_ PFIL_SEL 0 R/W Prefilter Mode Select for Brightness Signals 0: The prefilter is turned off. 1: The prefilter is turned on. (1/4  1/2  1/4) 28 RES_DS_H_ 1 INTERPOTYP R/W Horizontal Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation 27 to 16  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 RES_DS_H_ RATIO [15:0] 9224 R/W Horizontal Scale Down Ratio ([15:12]: Integer part, [11:0]: Decimal part) round(RES_HW ÷ RES_OUT_HW × 4096) RES_DS_H_RATIO  4096: Setting prohibited RES_DS_H_RATIO = 4096: 100% scale up RES_DS_H_RATIO  4096: Scale down Note: This register is updated when the SCL0_VEN_A bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2013 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.15 Initial Vertical Phase Register (SCL0_DS5) Bit: 31 30 29 28 27 26 25 24    RES_V_ INTERPOT YP - - - - 23 22 21 20 19 18 17 16 - - - - - - - RES_TOP_INIPHASE[11:0] Initial value: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0     - - - - - - - - - - - RES_BTM_INIPHASE[11:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 29  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 28 RES_V_ 1 INTERPOTYP R/W RES_TOP_ INIPHASE [11:0] 2048 R/W  All 0 Vertical Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation 27 to 16 15 to 12 Vertical Interpolation Start Phase for Top Field 0 to 4095 (0 to approx.1.0) R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 RES_BTM_ INIPHASE [11:0] 0 R/W Vertical Interpolation Start Phase for Bottom Field 0 to 4095 (0 to approx.1.0) Note: This register is updated when the SCL0_VEN_A and SCL0_VEN_B bits in the SCL0 register update control register (SCL0_UPDATE) are 1. Page 2014 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.16 Vertical Scaling Register (SCL0_DS6) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - SCL0_U - RES_V_RATIO[15:0] PDATE - SCL0_ VEN_B - - - Initial value: R/W: SCL0_ SCL0_ VEN_D VEN_C 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 16  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 RES_V_ 2044 RATIO[15:0] R/W Vertical Scale Up/Down Ratio ([15:12]: Integer part, [11:0]: Decimal part) For scale down: round (RES_VW ÷ RES_OUT_VW × 4096) For scale up: round (RES_IN_VW ÷ RES_P_VW × 4096) RES_V_RATIO < 4096: Scale up RES_V_RATIO = 4096: 100% scale up RES_V_RATIO  4096: Scale down Note: These bits updated when the SCL0_VEN_A and SCL0_VEN_B bits in the SCL0 register update control register (SCL0_UPDATE) are 1. Accordingly, even a scaled-up graphics display requires both an input Vsync signal and output Vsync signal. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2015 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.17 Scaling-Down Control Block Output Size Register (SCL0_DS7) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_OUT_VW[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - RES_OUT_HW[10:0] - Initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_OUT_ 240 VW[10:0] R/W Number of Valid Lines in Vertical Direction Output by Scaling-down Control Block (lines) This bit setting is used for the number of lines to be written to the frame buffer. When SCL1_WR1.RES_LOOP is 0 (frame write mode), specify the number of lines for one frame. When SCL1_WR1.RES_LOOP is 1 (line write mode), specify the number of lines for repeated write. Note: The RES_OUT_VW value should be aligned in 4-line units and equal to or smaller than the RES_VW value. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_OUT_ 640 HW[10:0] R/W Number of Valid Horizontal Pixels Output by ScalingDown Control Block (video-image clock cycles) Note: The RES_OUT_HW value should be aligned in 4-pixel units and equal to or smaller than the RES_HW value. Note: This register is updated when the SCL0_VEN_A and SCL0_VEN_C bits in the SCL0 register update control register (SCL0_UPDATE) are 1. Page 2016 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.18 Scaling-Up Control Register (SCL0_US1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            RES_US _V_ON    RES_US _H_ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 R/W: R R R R R R R R R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RES_US_ V_ON 1 R/W Vertical Scale Up On/Off 0: Off 1: On 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_US_ H_ON 1 R/W Horizontal Scale Up On/Off 0: Off 1: On Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2017 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.19 Output Image Vertical Size Register (SCL0_US2) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_P_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - RES_P_VW[10:0] - - - - - Initial value: 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_P_VS 35 [10:0] R/W Vertical Enable Signal Start Position for Output Image (VSYNC + V backporch lines) Note: The set value should be four or more (lines). RES_P_VS  RES_P_VW should be equal to or less than 2039 (lines). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_P_VW 480 [10:0] R/W Vertical Enable Signal Width for Output Image (lines) Note: RES_P_VS  RES_P_VW should be equal to or less than 2039 (lines). Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2018 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.20 Output Image Horizontal Size Register (SCL0_US3) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_P_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - RES_P_HW[10:0] - - - - - Initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_P_HS 144 [10:0] R/W Horizontal Enable Signal Start Position for Output Image (HSYNC+H backporch pixel-clock cycles) Note: The set value should be 16 or more (clock cycles). RES_P_HS  RES_P_HW should be equal to or less than 2015 (clock cycles). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_P_HW 640 [10:0] R/W Horizontal Enable Signal Width for Output Image (pixel-clock cycles) Note: RES_P_HS  RES_P_HW should be equal to or less than 2015 (clock cycles). Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2019 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.21 Scaling-Up Control Block Input Size Register (SCL0_US4) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 RES_IN_VW[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - RES_IN_HW[10:0] - Initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 RES_IN_ VW[10:0] 240 R/W Number of Valid Lines in Vertical Direction Input to Scaling-down Control Block (lines) 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 RES_IN_ HW[10:0] 640 R/W Number of Valid Horizontal Pixels Input to Scalingdown Control Block (pixel-clock cycles) Note: This register is updated when the SCL0_VEN_B and SCL0_VEN_D bits in the SCL0 register update control register (SCL0_UPDATE) are 1. Page 2020 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.22 Horizontal Scale Up Register (L0_US5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - SCL0_ VEN_B - - - Bit: Initial value: 0 R/W: R/W SCL0_ SCL0_ VEN_D VEN_C RES_US_H_RATIO[15:0] - SCL0_U PDATE 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 16  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 RES_US_ H_RATIO [15:0] 9224 R/W Horizontal Scale Up Ratio ([15:12]: Integer part, [11:0]: Decimal part) round (RES_IN_HW ÷ RES_P_HW × 4096) RES_US_H_RATIO < 4096: Scale up RES_US_H_RATIO = 4096: 100% scale up RES_US_H_RATIO  4096: Setting prohibited Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2021 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.23 Horizontal Scale Up Initial Phase Register (SCL0_US6) Bit: 31 30 29 28 27 26 25 24    RES_US_ H_INTERP OTYP - - - - 23 22 21 20 19 18 17 16 - - - - - - - RES_US_HT_INIPHASE[11:0] Initial value: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0     - - - - - - - - - - - RES_US_HB_INIPHASE[11:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 29  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 28 RES_US_H_ 1 INTERPOTYP R/W Horizontal Interpolation Mode Select 0: Hold interpolation 1: Linear interpolation 27 to 16 15 to 12 RES_US_HT_ 0 INIPHASE [11:0] R/W  R All 0 Horizontal Interpolation Start Phase for Top Field 0 to 4095 (0 to approx.1.0) Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 RES_US_HB_ 0 INIPHASE [11:0] R/W Horizontal Interpolation Start Phase for Bottom Field 0 to 4095 (0 to approx.1.0) Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2022 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.24 Trimming Register (SCL0_US7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - SCL0_ RES_VCUT[7:0] VEN_B - Initial value: 0 R/W: R/W SCL0_ SCL0_ VEN_D RES_HCUT[7:0] VEN_C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 16  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 to 8 RES_HCUT 0 [7:0] R/W Horizontal Amount of Cut-off Post-Scaling Image (Right and Left Parts) Sets the number of pixel-clock cycles. 7 to 0 RES_VCUT 0 [7:0] R/W Vertical Amount of Cut-off Post-Scaling Image (Upper and Lower Parts) Sets the number of lines. Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2023 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.25 Frame Buffer Read Select Register (SCL0_US8) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            RES_IBUS _SYNC_ SEL    RES_DISP _ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RES_IBUS_ 0 SYNC_SEL R/W Sync Signal Select for Frame Buffer Read Block 0: Sync signals from the scaling-up control block 1: Sync signals from the graphics processing block 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_DISP_ 0 ON R/W Post-Scaling Image Frame Display On/Off 0: Frame display on 1: Frame display off Note: RES_IBUS_SYNC_SEL is updated when the values of the SCL0_VEN_B and SCL0_VEN_D bits in the SCL0 register update control register (SCL0_UPDATE) are both 1. RES_DISP_ON is updated when the value of the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. Page 2024 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.26 Background Color Register (SCL0_OVR1) Bit: 31 30 29 28 27 26 25 24 23 22         - - 21 20 19 18 -RES_BK_COL_R[7:0] - 17 16 - Initial value: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - SCL0_ - RES_BK_COL_B[7:0] VEN_B - Initial value: R/W: SCL0_ SCL0_ RES_BK_COL_G[7:0] VEN_D VEN_C - 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 RES_BK_ 128 CLO_R[7:0] R/W Background Color Setting R/Cr Signal R: 8 bits; unsigned (0 to 255 [LSB]) Cr: 8 bits; 128 offset binary; unsigned (0 to 255 [LSB]) 15 to 8 RES_BK_ 0 COL_G[7:0] R/W 7 to 0 RES_BK_ 128 COL_B[7:0] R/W Background Color Setting G/Y Signal G/Y: 8 bits; unsigned (0 to 255 [LSB]) Background Color Setting B/Cb Signal B: 8 bits; unsigned (0 to 255 [LSB]) Cb: 8 bits; 128 offset binary; unsigned (0 to 255 [LSB]) Note: This register is updated when the SCL0_VEN_B bit in the SCL0 register update control register (SCL0_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2025 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.27 SCL1 Register Update Control Register (SCL1_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            SCL1_ VEN_B    SCL1_ VEN_A Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/WC1 R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 SCL1_ VEN_B 0 R/WC1 Frame Buffer Write Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 SCL1_ VEN_A 0 R/WC1 Frame Buffer Write Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2026 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.28 Writing Mode Register (SCL1_WR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2        RES_FLM _MD  -RES_DS_WR_MD[2:0] - Bit: - RES_MD[1:0] 1 0 RES_ LOOP RES_ BST_MD Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 9  All 0 Reserved R These bits are always read as 0. The write value should always be 0. 8 RES_FLM_MD 0 R/W Frame Buffer Address Generation Mode Select 0: RES_BASE  RES_FLM_OFF × frame number 1: RES_BASE  RES_FLM_OFF × field information (top field: 0; bottom field: 1) Note: This bit should be set to 0 when a progressive signal is being input. When the setting of this bit is 1, the setting for frame buffers should be for the use of two. This bit is only provided in the R version. In products other than the R version, this bit is always read as 0, and when writing, the value written should always be 0. 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 RES_DS_ WR_MD [2:0] 0 R/W Frame Buffer Writing Mode for Image Processing 0: Normal 1: Horizontal mirroring 2: 90 rotation 3: 180 rotation 4: 270 rotation 5 to 7: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2027 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Bit Bit Name 3, 2 RES_MD [1:0] Initial Value R/W Description 0 Frame Buffer Video-Signal Writing Format R/W 0: YCbCr422 (16 bits) 1: RGB565 (16 bits) 2: RGB888 (24 (32) bits) 3: Setting prohibited 1 RES_LOOP 0 R/W Frame Buffer Write Mode Select 0: Frame mode 1: Line mode (read as ring buffer) 0 RES_BST_MD 0 R/W Transfer Burst Length for Frame Buffer Writing 0: 32-byte 1: 128-byte Note: RES_FLM_MD, RES_LOOP, and RES_BST_MD are updated when the SCL1_VEN_B bit in the SCL1 register update control register (SCL1_UPDATE) is 1. RES_DS_WR_MD and RES_MD are updated when the SCL1_VEN_A and SCL1_VEN_B bits in the SCL1 register update control register (SCL1_UPDATE) are 1. Page 2028 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.29 Write Address Register 1 (SCL1_WR2) Bit: Initial value: 31 30 29 28 27 26 25 - - - - - - - RES_BASE[31:16] - 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 - - - - - - RES_BASE[15:0] - R/W: R/W Bit: Initial value: 15 0 R/W: R/W 24 22 21 20 19 18 17 - - - - - 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 23 16 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 0 RES_BASE 0 [31:0] R/W Description R/W Frame Buffer Base Address Sets the start address of the frame buffer where frame data is to be stored. For 32-byte transfer: The lower five bits should be fixed to 0 0000. For 128-byte transfer: The lower seven bits should be fixed to 000 0000. Note: This register is updated when the SCL1_VEN_B bit in the SCL1 register update control register (SCL1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2029 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.30 Write Address Register 2 (SCL1_WR3) Bit: 31 30  29 28 27 26 25 - - - - - 24 23 22 RES_LN_OFF[14:0] - 21 20 19 18 17 16 - Initial value: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - RES_ FLD_ DLY_SEL - - RES_FLM_NUM[9:0] - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31  0 R Reserved This bit is always read as 0. The write value should always be 0. 30 to 16 RES_LN_ OFF[14:0] 2048 R/W Frame Buffer Line Offset Address Sets the line offset address for calculating the start address of each line. Line 0: RES_BASE Line 1: RES_BASE  RES_LN_OFF × 1 : Line n: RES_BASE  RES_LN_OFF × n For 32-byte transfer: The lower five bits should be fixed to 0 0000. For 128-byte transfer: The lower seven bits should be fixed to 000 0000. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 RES_FLM_ 1 NUM[9:0] R/W Number of Frames of Buffer to be Written to Number of frames defined by RES_FLM_NUM  1 are used. For normal image display: 0 or 1 (one or two planes) For horizontal mirror image display: 0 or 1 (one or two planes) For rotated image display: 1 (2 planes) For video recording: the number of frames to be stored  1 Page 2030 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Note: This register is updated when the SCL1_VEN_B bit in the SCL1 register update control register (SCL1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2031 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.31 Write Address Register 3 (SCL1_WR4) Bit: 31 30 29 28 27 26 25 24 23 22 21          - - 20 19 18 17 RES_FLM_OFF[22:16] - 16 - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - -RES_FLM_OFF[15:0] - - Initial value: 0 R/W: R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 23  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 22 to 0 RES_FLM_ 524288 OFF[22:0] R/W Frame Buffer Frame Offset Address Sets the frame offset address for calculating the start address of each frame. Buffer 0: RES_BASE Buffer 1: RES_BASE  RES_FLM_OFF × 1 : Buffer n: RES_BASE  RES_FLM_OFF × n For 32-byte transfer: The lower five bits should be fixed to 0 0000. For 128-byte transfer: The lower seven bits should be fixed to 000 0000. Note: This register is updated when the SCL1_VEN_B bit in the SCL1 register update control register (SCL1_UPDATE) is 1. Page 2032 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.32 Frame Sub-Sampling Register (SCL1_WR5) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8    RES_ INTER   RES_FS_ -RATE[1:0] 7 6 5 4 3 2 1 0    RES_ FLD_SEL    RES_ WENB Initial value: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R/W R/W R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 RES_ INTER 1 R/W Field Operating Mode Select 0: Progressive 1: Interlace 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 RES_FS_ RATE[1:0] 0 R/W Writing Rate Sets the frame buffer writing rate to the vertical frequency of the input signal. 0: 1/1 an input signal (The RES_FLD_SEL setting is invalid.) 1: 1/2 an input signal 2: 1/4 an input signal 3: 1/8 an input signal 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2033 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Initial Value Bit Bit Name 4 RES_FLD_ 0 SEL R/W Description R/W Write Field Select 0: Top field 1: Bottom field 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_ WENB 0 R/W Frame Buffer Write Enable After making the setting to enable writing, writing starts from the second frame. 0: Frame buffer writing is disabled. 1: Frame buffer writing is enabled. Note: This register is updated when the SCL1_VEN_A bit in the SCL1 register update control register (SCL1_UPDATE) is 1. Page 2034 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.33 Bit Reduction Register (SCL1_WR6) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            RES_ DTH_ON    RES_ BITDEC_ ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RES_DTH_ 0 ON R/W Dither Correction On/Off 0: Off (rounded off) 1: On (2  2 dither pattern) 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RES_ BITDEC_ ON 0 R/W Bit Reduction On/Off 0: Off 1: On Note: This register is updated when the SCL1_VEN_A bit in the SCL1 register update control register (SCL1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2035 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.34 Write Detection Register (SCL1_WR7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                RES_ OVER FLOW Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - SCL0_U PDATE - - - SCL0_ VEN_B - - - RES_FLM_CNT[9:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 RES_ OVERFLOW 0 R Line Buffer Overflow Detect 1: Line buffer has overflowed. 0: Line buffer has not overflowed. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 RES_FLM_ CNT[9:0] Page 2036 of 3092 0 R Frame Number of Frame Immediately Before That Currently Being Accessed R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.35 Graphics 1 Register Update Control Register (GR1_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            GR1_ P_VEN    GR1_ IBUS_ VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/WC1 R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR1_P_ VEN 0 R/WC1 Graphics Display Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR1_IBUS_ 0 VEN R/WC1 Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2037 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.36 Frame Buffer Read Control Register (Graphics 1) (GR1_FLM_RD) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR1_ R_ENB Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR1_R_ ENB 0 R/W Frame Buffer Read Enable 0: Frame buffer reading is disabled. 1: Frame buffer reading is enabled. Note: This register is updated when the GR1_IBUS_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2038 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.37 Frame Buffer Control Register 1 (Graphics 1) (GR1_FLM1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                GR1_LN_ OFF_DIR Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8       - GR1_FLM_SEL[1:0] 7 6 5 4 3 2 1 0    GR1_IMR_ FLM_INV    GR1_ BST_MD Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 GR1_LN_ OFF_DIR 0 R/W Selects the line offset address direction of the frame buffer. 0: Increments the address by the line offset address. 1: Decrements the address by the line offset address. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 GR1_FLM_ 0 SEL[1:0] R/W Selects a frame buffer address setting signal. 0: Links to scaling-down process. 1: Selects GR1_FLM_NUM. 2: Links to distortion correction. 3: Setting prohibited 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR1_IMR_ FLM_INV 0 R/W Sets the frame buffer number for distortion correction. 0: Does not replace the numbers of the frames to be read. 1: Replaces the numbers of the frames to be read. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2039 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Bit Bit Name Initial Value R/W Description 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR1_BST_ 0 MD R/W Frame Buffer Burst Transfer Mode 0: 32-byte transfer 1: 128- byte transfer Note: GR1_LN_OFF_DIR, GR1_FLM_SEL, and GR1_IMR_FLM_INV are updated when the GR1_IBUS_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. GR1_BST_MD is updated when the GR1_IBUS_VEN and GR1_P_VEN bits in the graphics 1 register update control register (GR1_UPDATE) are 1. Page 2040 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.38 Frame Buffer Control Register 2 (Graphics 1) (GR1_FLM2) Bit: Initial value: 31 30 29 28 27 26 25 - - - - - - - 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 24 23 22 GR1_BASE[31:16] - 21 20 19 18 17 - - - - - 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 2 1 0 - - - - - - GR1_BASE[15:0] - 5 4 3 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 0 GR1_BASE 0 [31:0] R/W Description R/W Frame Buffer Base Address Sets the start address of the frame buffer where frame data is to be stored. GR_BASE[4:3] and GR_BASE[6:3] are referred to during 32-byte burst transfer and 128-byte burst transfer, respectively, to skip the start line data. The lower three bits should be fixed to 000. Note: This register is updated when the GR1_IBUS_VEN and GR1_P_VEN bits in the graphics 1 register update control register (GR1_UPDATE) are 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2041 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.39 Frame Buffer Control Register 3 (Graphics 1) (GR1_FLM3) Bit: 31 30  29 28 27 26 25 - - - - - 24 23 22 GR1_LN_OFF[14:0] - 21 20 19 18 17 16 - Initial value: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - RES_ FLD_ DLY_SEL - - GR1_FLM_NUM[9:0] - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31  0 R Reserved This bit is always read as 0. The write value should always be 0. 30 to 16 GR1_LN_ OFF[14:0] 2048 R/W Frame Buffer Line Offset Address Sets the line offset address for calculating the start address of each line. Line 0:GR1_BASE Line 1:GR1_BASE  GR1_LN_OFF × 1 : Line n: GR1_BASE  GR1_LN_OFF × n For 32-byte transfer: The lower five bits should be fixed to 0 0000. For 128-byte transfer: The lower seven bits should be fixed to 000 0000. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GR1_FLM_ 1 NUM[9:0] R/W Frame Number of Frame Buffer Manually set the frame number when GR1_FLM_SEL = 1. Note: This register is updated when the GR1_IBUS_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2042 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.40 Frame Buffer Control Register 4 (Graphics 1) (GR1_FLM4) Bit: 31 30 29 28 27 26 25 24 23 22 21          - - 20 19 18 17 16 GR1_FLM_OFF[22:16] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - -GR1_FLM_OFF[15:0] - - Initial value: 0 R/W: R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 23  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 22 to 0 GR1_FLM_ 524288 OFF[22:0] R/W Frame Buffer Frame Offset Address Specifies the frame offset address used for calculating the start address of each frame buffer when more than one buffer is used. Buffer 0: GR1_BASE Buffer 1: GR1_BASE  GR1_FLM_OFF × 1 : Buffer n: GR1_BASE  GR1_FLM_OFF × n For 32-byte transfer: The lower five bits should be fixed to 0 0000. For 128-byte transfer: The lower seven bits should be fixed to 000 0000. Note: This register is updated when the GR1_IBUS_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2043 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.41 Frame Buffer Control Register 5 (Graphics 1) (GR1_FLM5) Bit: 31 30 29 28 27 26 25 24       - - 23 22 21 20 19 18 17 16 - - - GR1_FLM_LNUM[9:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - - GR1_FLM_LOOP[9:0] - - - - Initial value: 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GR1_FLM_ 0 LNUM[9:0] R/W  R All 0 Sets number of lines in a frame Number of lines is (GR1_FLM_LNUM  1). Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GR1_FLM_ 1023 LOOP[9:0] R/W Number of lines when reading the addresses repeatedly by returning to the start address after reaching the end address. (GR1_FLM_LOOP  1) lines are read. Note: This register is updated when the GR1_IBUS_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2044 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.42 Frame Buffer Control Register 6 (Graphics 1) (GR1_FLM6) Bit: 31 - Initial value: 1 R/W: R/W Bit: 15 30 29 - - 28 GR1_FORMAT[3:0] R/W: 26 25 24 23 22   - - - - 21 20 -GR1_HW[9:0] - 19 18 17 - - - 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - GR1_ ENDIAN_ ON    GR1_ CNV444_ MD   - - - - - GR1_YCC_SWAP[2:0] Initial value: 27 GR1_STA_POS[5:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R R R/W R R R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 28 GR1_ FORMAT [3:0] Initial Value R/W Description 8 R/W Sets the format of the frame buffer read signal. 0: RGB565 1: RGB888 2: RGB1555 3: RGB4444 4: RGB8888 5: CLUT8 6: CLUT4 7: CLUT1 8: YCbCr422 9 to 15: Setting prohibited 27, 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 GR1_HW [9:0] 0 R/W Sets the width of the horizontal valid period. The width is (GR1_HW  1) pixels. Note: The set value should be equal to or more than two. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2045 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Initial Value Bit Bit Name 15 to 13 GR1_YCC_ 0 SWAP[2:0] R/W Description R/W Controls swapping of data read from buffer in the YCbCr422 format. Valid only when GR1_ENDIAN_ON = 1. 0: Cb/Y0/Cr/Y1 1: Y0/Cb/Y1/Cr 2: Cr/Y0/Cb/Y1 3: Y0/Cr/Y1/Cb 4: Y1/Cr/Y0/Cb 5: Cr/Y1/Cb/Y0 6: Y1/Cb/Y0/Cr 7: Cb/Y1/Cr/Y0 12 GR1_ ENDIAN_ ON 0 R/W Turns on/off the endian control of data read from buffer. 0: Off 1: On 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 GR1_ CNV444_ MD 0 R/W Sets the interpolation mode for YCbCr422 to YCbCr444 conversion. 0: Hold interpolation 1: Average interpolation 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 GR1_STA_ 0 POS[5:0] R/W Sets the amount of data to be skipped through. Specifically data amount equal to the amount indicated by GR1_STA_POS is skipped from the start of the line. Note: GR1_YCC_SWAP, GR1_ENDIAN_ON, GR1_CNV444, and GR1_STA_POS are updated when GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. GR1_FORMAT and GR1_HW are updated when GR1_IBUS_VEN and GR1_P_VEN bits in the graphics 1 register update control register (GR1_UPDATE) are 1. Page 2046 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.43 Alpha Blending Control Register 1 (Graphics 1) (GR1_AB1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            GR1_ GRC_DISP _ON   - GR1_DISP_SEL[1:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/W R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR1_GRC_ 0 DISP_ON R/W Turns on/off frame-line display of the graphics image area. 0: Frame-line display off 1: Frame-line display on 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 GR1_DISP_ 0 SEL[1:0] R/W Selects the graphics display mode. 0: Background color display (GR1_BASE) 1: Lower-layer graphics display When displaying video image or enlarged graphics, select this setting. 2: Current graphics display When displaying graphics, select this setting. 3: Blended display of lower-layer graphics and current graphics* Note: * Select this setting whenever chroma-key processing is to proceed. Since only current graphics are to be displayed by chroma-key processing, set the  values for both pixels to be subject to chromakeying and pixels not to be subject to chroma-keying to 255. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2047 of 3092 Section 33 Video Display Controller 4 (3): Scaler SH7268 Group, SH7269 Group Note: This register is updated when GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2048 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.44 Alpha Blending Control Register 2 (Graphics 1) (GR1_AB2) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR1_GRC_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4      - - - GR1_GRC_VW[10:0] - 3 2 1 0 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 GR1_GRC_ 0 VS[10:0] R/W  R All 0 Vertical Start Position of Graphics Image Area. Note: The set value should be four or more (lines). GR1_GRC_VS + GR1_GRC_VW should be equal to or less than 2039 (lines). Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR1_GRC_ 0 VW[10:0] R/W Vertical Width of Graphics Image Area. Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2049 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.45 Alpha Blending Control Register 3 (Graphics 1) (GR1_AB3) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR1_GRC_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - GR1_GRC_HW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 GR1_GRC_ 0 HS[10:0] R/W  R All 0 Horizontal Start Position of Graphics Image Area. Note: The set value should be 16 or more (clock cycles). GR1_GRC_HS + GR1_GRC_HW should be equal to or less than 2015 (clock cycles). Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR1_GRC_ 0 HW[10:0] R/W Horizontal Width of Graphics Image Area. Note: For displaying an image with 1- or 2-pixel horizontal width, set GR1_HW to 2 and GR1_GRC_HW to 1 (1 pixel) or 2 (2 pixels). Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2050 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.46 Alpha Blending Control Register 7 (Graphics 1) (GR1_AB7) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR1_ CK_ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR1_CK_ ON 0 R/W CLUT-Index/RGB-Index Chroma-Key Processing On/Off 0: Off 1: On Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2051 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.47 Alpha Blending Control Register 8 (Graphics 1) (GR1_AB8) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - -GR1_CK_KCLUT[7:0] - 28 27 26 25 24 - - 23 22 21 - - GR1_CK_KG[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GR1_CK_KB[7:0] - - - - - GR1_CK_KR[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 24 GR1_CK_ 0 KCLUT[7:0] R/W Description R/W CLUT Signal for CLUT-Index Chroma-Key Processing CLUT: Unsigned 8 bits (0 to 255 [LSB]) 23 to 16 GR1_CK_ KG[7:0] 0 R/W 15 to 8 GR1_CK_ KB[7:0] 0 R/W 7 to 0 GR1_CK_ KR[7:0] 0 R/W G Signal for RGB-Index Chroma-Key Processing G: Unsigned 8 bits (0 to 255 [LSB]) B Signal for RGB-Index Chroma-Key Processing B: Unsigned 8 bits (0 to 255 [LSB]) R Signal for RGB-Index Chroma-Key Processing R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2052 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.48 Alpha Blending Control Register 9 (Graphics 1) (GR1_AB9) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - GR1_CK_A[7:0] - 28 27 26 25 24 - - - 23 22 21 - - 20 19 18 GR1_CK_G[7:0] - 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 2 - - - - GR1_CK_B[7:0] - 6 5 - - GR1_CK_R[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 24 GR1_CK_A 0 [7:0] R/W Description R/W Replaced Alpha Signal after RGB-Index Chroma-Key Processing : Unsigned 8 bits (0 to 255 [LSB]) Note: These bits should always be set to 255 to display the current graphics only. 23 to 16 GR1_CK_G 0 [7:0] R/W Replaced G Signal after RGB-Index Chroma-Key Processing G: Unsigned 8 bits (0 to 255 [LSB]) 15 to 8 GR1_CK_B 0 [7:0] R/W Replaced B Signal after RGB-Index Chroma-Key Processing B: Unsigned 8 bits (0 to 255 [LSB]) 7 to 0 GR1_CK_R 0 [7:0] R/W Replaced R Signal after RGB-Index Chroma-Key Processing R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2053 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.49 Alpha Blending Control Register 10 (Graphics 1) (GR1_AB10) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - 28 27 GR1_A0[7:0] - 26 25 24 - - - 23 22 21 - - 20 19 GR1_G0[7:0] - 18 17 16 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 - - - - - GR1_B0[7:0] - 6 5 - - GR1_R0[7:0] - 2 1 0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 GR1_A0 [7:0] Initial Value R/W Description 0 R/W CLUT1 0 Signal Replaced with  signal when in the CLUT1 format and CLUT1 = 0. Replaced with  signal when in the RGB1555 format and  = 0. Note: These bits should always be set to 255 to display the current graphics only. 23 to 16 15 to 8 7 to 0 GR1_G0 [7:0] 0 GR1_B0 [7:0] 0 GR1_R0 [7:0] 0 R/W CLUT1 G0 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 0. R/W CLUT1 B0 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 0. R/W CLUT1 R0 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 0. Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2054 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.50 Alpha Blending Control Register 11 (Graphics 1) (GR1_AB11) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - 28 27 GR1_A1[7:0] - 26 25 24 - - - 23 22 21 - - 20 19 GR1_G1[7:0] - 18 17 16 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 - - - - - GR1_B1[7:0] - 6 5 - - GR1_R1[7:0] - 2 1 0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 GR1_A1 [7:0] Initial Value R/W Description 0 R/W CLUT1 1 Signal Replaced with  signal when in the CLUT1 format and CLUT1 = 1. Replaced with  signal when in the RGB1555 format and  = 1. Note: These bits should always be set to 255 to display the current graphics only. 23 to 16 15 to 8 7 to 0 GR1_G1 [7:0] 0 GR1_B1 [7:0] 0 GR1_R1 [7:0] 0 R/W CLUT1 G1 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 1. R/W CLUT1 B1 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 1. R/W CLUT1 R1 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 1. Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2055 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.51 Background Color Control Register (Graphics 1) (GR1_BASE) Bit: 31 30 29 28 27 26 25 24 23 22         - - 21 20 19 18 - GR1_BASE_G[7:0] - 17 16 - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - SCL0_ - GR1_BASE_R[7:0] VEN_B - Initial value: R/W: SCL0_ SCL0_ GR1_BASE_B[7:0] VEN_D VEN_C - 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 8 7 to 0 GR1_BASE 0 _G[7:0] R/W GR1_BASE 128 _B[7:0] R/W GR1_BASE 128 _R[7:0] R/W Background Color G Signal G: Unsigned 8 bits (0 to 255 [LSB]) Background Color B Signal B: Unsigned 8 bits (0 to 255 [LSB]) Background Color R Signal R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. Page 2056 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.2.52 CLUT Table Control Register (Graphics 1) (GR1_CLUT) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                GR1_ CLT_SEL Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 GR1_CLT_ 0 SEL R/W CLUT Table Select Signal 0: Selects CLUT table 0. Referring to the CLUT table 0 value to expand to RGB8888 The CPU side can read-access or write-access to the CLUT table 1. 1: Selects CLUT table 1. Referring to the CLUT table 1 value to expand to RGB8888 The CPU side can read-access or write-access to the CLUT table 0. 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: This register is updated when the GR1_P_VEN bit in the graphics 1 register update control register (GR1_UPDATE) is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2057 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.3 Usage Method 33.3.1 Scaling Setting Example for 525i Video Input and VGA-Size (640  480) Video Output (1) Angles of View for Input and Output This section describes an example of setting the signals of the input and output angles of view shown in table 33.38. Here, the over-scan rate is assumed to be 100. Table 33.38 Input and Output Angles for 525i Video Input and VGA-Size (640  480) Video Output Input Signal Output Signal Signal Format Rotation Buffer Planes Scaling Filter 1440  240 640  480 Two planes YCbCr Normal 2-tap linear Frame buffer Internal bus write control block Internal bus read control block Bit reduction block Data expansion block Scale-down control block Input controller Sync control block Scale-up control block Moving picture synthesizing block Enable signal generation Image quality improver Video image signal Sync signal Figure 33.18 Signal Paths for Displaying Input Video Image (2) Horizontal Scaling (Horizontal Scale Down, Scaling Filter: 2-Tap Linear) The scaling rate for folding can be calculated as shown below. RATIO_org = round (1440 ÷ 640 × 4096) = 9216  = (9216 × (640  1)  (1440  1) × 4096) ÷ (640  1) = 8.01 Horizontal scaling ratio = round (9216  (8.01)) = 9225 Page 2058 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 33 Video Display Controller 4 (3): Scaler Vertical Scaling (Vertical Scale Up, Scaling Filter: 2-Tap Linear) The scaling rate for folding can be calculated as shown below. RATIO_org = round (240 ÷ 480 × 4096) = 2048  = (2048 × (480 − 1) − (240 − 1) × 4096) ÷ (480 − 1) = 4.27 Vertical scaling ratio = round (2048 − (4.07)) = 2044 (4) Setting Frame Buffer Access Area Since video data is written to the frame buffer after scaled down, the write size is 640 × 240 pixels. The frame buffer area required is 640 pixels or more for line offset and line offset × 240 pixels or more for frame offset. 240 Number of lines in vertical direction 640 Number of pixels in horizontal direction At least 640 pixels are necessary for the buffer area. Frame offset address Image area At least 240 lines are necessary for the buffer area. Here, the frame buffer work area is assumed to be 1024  256 pixels. Line offset address Frame buffer work area Figure 33.19 Frame Buffer Access Area Setting R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2059 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Since the frame buffer is accessed in 64-bit units, YCbCr422 (16 bits) is accessed in 4-pixel units. The line offset address values to be set are: RES_LN_OFF[14:0] = 1024 × 2 = 2048 GR1_LN_OFF[14:0] = 1024 × 2 = 2048 The frame offset address values to be set are: RES_FLM_OFF[22:0] = RES_LN_OFF[14:0] × 256 = 524288 GR1_FLM_OFF[22:0] = GR1_LN_OFF[14:0] × 256 = 524288 (5) Register Setting Example Table 33.39 Register Setting Example for 525i Video Input and VGA-Size Video Output Register Name Bit Name Settings Remarks Synchronization Control SCL0_FRC3 RES_VS_SEL 0 External Vsync selected SCL0_FRC4 RES_FH[10:0] 799 Horizontal period width of output signal (period width = set value + 1) Size of Angle of View SCL0_DS2 RES_VS[10:0] 15 Vertical capture start position of input signal SCL0_DS2 RES_VW[10:0] 240 Vertical capture width of input signal SCL0_DS3 RES_HS[10:0] 244 Horizontal capture start position of input signal SCL0_DS3 RES_HW[10:0] 1440 Horizontal capture width of input signal SCL0_FRC6 RES_F_VS[10:0] 35 Vertical valid start position of full screen SCL0_FRC6 RES_F_VW[10:0] 480 Vertical valid width of full screen SCL0_FRC7 RES_F_HS[10:0] 144 Horizontal valid start position of full screen SCL0_FRC7 RES_F_HW[10:0] 640 Horizontal valid width of full screen SCL0_US2 RES_P_VS[10:0] 35 Vertical valid start position of output image SCL0_US2 RES_P_VW[10:0] 480 Vertical valid width of output image SCL0_US3 RES_P_HS[10:0] 144 Horizontal valid start position of output image SCL0_US3 RES_P_HW[10:0] 640 Horizontal valid width of output image Page 2060 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Register Name Bit Name Settings Remarks Scaling Setting SCL0_DS4 RES_DS_H_RATIO [15:0] 9224 Horizontal scaling-down because RES_DS_H_RATIO is equal to or larger than 4096 SCL0_DS1 RES_DS_H_ON 1 Horizontal scaling-down on SCL0_US1 RES_US_H_ON 0 Horizontal scaling-up off SCL0_US5 RES_US_H_RATIO [15:0] 4096 Horizontal scaling-up off because RES_US_H_RATIO is equal to or larger than 4096 SCL0_DS1 RES_DS_V_ON 0 Vertical scaling-down off SCL0_US1 RES_US_V_ON 1 Vertical scaling-up on SCL0_DS6 RES_V_RATIO[15:0] 2044 Vertical scaling-up because RES_V_RATIO is smaller than 4096 SCL0_DS7 RES_OUT_VW[10:0] 240 Vertical valid input width because the vertical scaling-down function is off SCL0_DS7 RES_OUT_HW[10:0] 640 Horizontal image size after horizontal scalingdown SCL0_US4 RES_IN_VW[10:0] 240 Vertical width of frame buffer read SCL0_US4 RES_IN_HW[10:0] 640 Horizontal width of frame buffer read IP Conversion Setting SCL0_DS5 RES_TOP_INIPHASE 2048 [11:0] Top field adjusted by 0.5-line phase SCL0_DS5 RES_BTM_INIPHASE 0 [11:0] No phase adjustment for bottom field SCL0_FRC5 RES_FLD_DLY_SEL IP conversion with two planes of frame buffer used for vertical scaling-up 1 Frame Buffer Write Setting SCL1_WR1 RES_DS_WR_MD[2:0] 0 Normal write mode for rotation control SCL1_WR1 RES_MD[1:0] 0 Frame buffer write format YCbCr422 (16 bits) SCL1_WR2 RES_BASE[31:0] 0 Frame buffer write start address (0 in setting example) SCL1_WR3 RES_LN_OFF[14:0] 2048 Frame buffer write line offset SCL1_WR3 RES_FLM_NUM[9:0] 1 Two planes of frame buffer used SCL1_WR4 RES_FLN_OFF[22:0] 524288 Frame buffer write frame offset SCL1_WR5 RES_WENB 1 Frame buffer write enabled R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2061 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler Register Name Bit Name Settings Remarks Frame Buffer Read Setting GR1_FLM1 GR1_FLM_SEL[1:0] 0 Frame number for frame buffer write output GR1_FLM2 GR1_BASE[31:0] 0 Conforming to frame buffer write setting GR1_FLM3 GR1_LN_OFF[14:0] 2048 Conforming to frame buffer write setting GR1_FLM4 GR1_FLM_OFF[22:0] 524288 Conforming to frame buffer write setting GR1_FLM6 GR1_FORMAT[3:0] 8 Frame buffer read format YCbCr422 GR1_FLM_RD GR1_R_ENB 1 Frame buffer read enabled GR1_FLM6 GR1_CNV444_MD 1 Mean value interpolation in YCbCr422  YCbCr444 conversion Scaling-up Selection SCL0_US8 RES_IBUS_SYNC_ SEL 0 Scaled-up video signal displayed GR1_AB1 GR1_DISP_SEL[1:0] 1 Scaling display selected Page 2062 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 33.3.2 (1) Section 33 Video Display Controller 4 (3): Scaler Scaling Setting Example for Graphics Display Angle of View for Graphics Display This section describes an example of setting the signals of the input and output angles of view shown in table 33.40. Table 33.40 Input and Output Angles of View for Graphics Display Graphics Size Output Signal Graphics Signal Format 640  480 640  480 RGB888 Frame buffer Internal bus read control block Data expansion block Sync control block Scale-up control block Moving picture synthesizing block Enable signal generation Image quality improver Video image signal Sync signal Figure 33.20 Signal Paths for Graphics Display (2) Setting Frame Buffer Access Area In the frame buffer in which graphics data is stored, graphics data needs to be expanded in the area of 640  480 pixels or larger. Here, the frame buffer area in which graphics data is expanded is assumed to be 640  480 pixels. Since the frame buffer is accessed in 64-bit units, RGB888 (32 bits) is accessed in 2-pixel units. The line offset address values to be set are: GR1_LN_OFF[14:0] = 640 × 4 = 2560 The frame offset address values to be set are: GR1_FLM_OFF[22:0] = GR1_LN_OFF[14:0] × 480 = 1228800 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2063 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (3) Register Setting Example Table 33.41 Register Setting Example for Graphics Display Register Name Bit Name Settings Remarks Synchronization Control SCL0_FRC3 RES_VS_SEL 1 Free-running Vsync selected (when the appropriate input signal is available, an external sync can also be selected) SCL0_FRC4 RES_FV[10:0] 524 Vertical period width of output signal (period width = set value + 1) SCL0_FRC4 RES_FH[10:0] 799 Horizontal period width of output signal (period width = set value + 1) Size of Angle of View SCL0_FRC6 RES_F_VS[10:0] 35 Vertical valid start position of full screen SCL0_FRC6 RES_F_VW[10:0] 480 Vertical valid width of full screen SCL0_FRC7 RES_F_HS[10:0] 144 Horizontal valid start position of full screen SCL0_FRC7 RES_F_HW[10:0] 640 Horizontal valid width of full screen GR1_AB2 GR1_GRC_VS[10:0] 35 Vertical valid start position of graphics output GR1_AB2 GR1_GRC_VW[10:0] 480 Vertical valid width of graphics output GR1_AB3 GR1_GRC_HS[10:0] 144 Horizontal valid start position of graphics output GR1_AB3 GR1_GRC_HW[10:0] 640 Horizontal valid width of graphics output Frame Buffer Read Setting GR1_FLM1 GR1_FLM_SEL[1:0] 1 Frame number setting with register GR1_FLM3 GR1_FLM_NUM[9:0] 0 Frame number of frame buffer (0 in setting example) GR1_FLM5 GR1_FLM_LNUM[9:0] 479 Number of graphics lines (number of lines = set value + 1) GR1_FLM6 GR1_HW[9:0] 639 Horizontal valid width of graphics (valid width = set value + 1) GR1_FLM2 GR1_BASE[31:0] 0 Conforming to graphics expansion setting (0 in setting example) GR1_FLM3 GR1_LN_OFF[14:0] 2560 Conforming to graphics expansion setting Page 2064 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Register Name Section 33 Video Display Controller 4 (3): Scaler Bit Name Settings Remarks Frame Buffer Read Setting GR1_FLM4 GR1_FLM_OFF[22:0] 1228800 Conforming to graphics expansion setting GR1_FLM6 GR1_FORMAT[3:0] 1 Frame buffer read format RGB888 GR1_FLM_RD GR1_R_ENB 1 Frame buffer read enabled Scaling-up Selection SCL0_US8 RES_IBUS_SYNC_SEL 1 Graphics output displayed GR1_AB1 GR1_DISP_SEL[1:0] Graphics display selected R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 2 Page 2065 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler 33.3.3 (1) Scaling Setting Example for Scaled-up Graphics Display Angles of View for Input and Output This section describes an example of setting the signals of the input and output angles of view shown in table 33.42. Table 33.42 Input and Output Angles of View for Scaled-up Graphics Display Graphics Size Output Signal Graphics Signal Format 640  480 800  600 RGB565 Frame buffer Internal bus read control block Data expansion block Sync control block Scale-up control block Moving picture synthesizing block Enable signal generation Image quality improver Video image signal Sync signal Figure 33.21 Signal Paths for Scaled-up Graphics Display Page 2066 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 33 Video Display Controller 4 (3): Scaler Horizontal Scaling (Horizontal Scale Up, Scaling Filter: 2-Tap Linear) The scaling rate for folding can be calculated as shown below. RATIO_org = round (640 ÷ 800 × 4096) = 3277  = (3277 × (800  1)  (640  1) × 4096) ÷ (800  1) = 1.23 Horizontal scaling ratio = round (3277  (1.23)) = 3276 (3) Vertical Scaling (Vertical Scale Up, Scaling Filter: 2-Tap Linear) The scaling rate for folding can be calculated as shown below. RATIO_org = round (480 ÷ 600 × 4096) = 3277  = (3277 × (600  1)  (480  1) × 4096) ÷ (600  1) = 1.57 Vertical scaling ratio = round (3277  (1.57)) = 3275 (4) Setting Frame Buffer Access Area In the frame buffer in which graphics data is stored, graphics data needs to be expanded in the area of 640  480 pixels or larger. Here, the frame buffer area in which graphics data is expanded is assumed to be 640  480 pixels. Since the frame buffer is accessed in 64-bit units, RGB565 (16 bits) is accessed in 4-pixel units. The line offset address values to be set are: GR1_LN_OFF[14:0] = 640 × 2 = 1280 The frame offset address values to be set are: GR1_FLM_OFF[22:0] = GR1_LN_OFF[14:0] × 480 = 614400 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2067 of 3092 SH7268 Group, SH7269 Group Section 33 Video Display Controller 4 (3): Scaler (5) Register Setting Example Table 33.43 Register Setting Example for Scaled-up Graphics Display Register Name Bit Name Settings Remarks Synchronization Control SCL0_FRC3 RES_VS_SEL 1 Free-running Vsync selected (when the appropriate input signal is available, an external sync can also be selected) SCL0_FRC4 RES_FV[10:0] 668 Vertical period width of output signal (period width = set value + 1) SCL0_FRC4 RES_FH[10:0] 1040 Horizontal period width of output signal (period width = set value + 1) Size of Angle of View SCL0_FRC6 RES_F_VS[10:0] 27 Vertical valid start position of full screen SCL0_FRC6 RES_F_VW[10:0] 600 Vertical valid width of full screen SCL0_FRC7 RES_F_HS[10:0] 216 Horizontal valid start position of full screen SCL0_FRC7 RES_F_HW[10:0] 800 Horizontal valid width of full screen SCL0_US2 RES_P_VS[10:0] 27 Vertical valid start position of image output SCL0_US2 RES_P_VW[10:0] 600 Vertical valid width of image output SCL0_US3 RES_P_HS[10:0] 216 Horizontal valid start position of image output SCL0_US3 RES_P_HW[10:0] 800 Horizontal valid width of image output Scaling Setting SCL0_US5 RES_US_H_RATIO[15:0] 3276 Horizontal scaling-up because the size is smaller than 4096 SCL0_DS6 RES_V_RATIO[15:0] 3275 Vertical scaling-up because the size is smaller than 4096 SCL0_US1 RES_US_H_ON 1 Horizontal scaling-up on SCL0_US1 RES_US_V_ON 1 Vertical scaling-up on SCL0_US4 RES_IN_VW[10:0] 480 Vertical width of frame buffer read SCL0_US4 RES_IN_HW[10:0] 640 Horizontal width of frame buffer read Page 2068 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Register Name Section 33 Video Display Controller 4 (3): Scaler Bit Name Settings Remarks Frame Buffer Read Setting GR1_FLM1 GR1_FLM_SEL[1:0] 1 Frame number setting with register GR1_FLM3 GR1_FLM_NUM[9:0] 0 Frame number of frame buffer (0 in setting example) GR1_FLM2 GR1_BASE[31:0] 0 Conforming to graphics expansion setting (0 in setting example) GR1_FLM3 GR1_LN_OFF[14:0] 1280 Conforming to graphics expansion setting GR1_FLM4 GR1_FLM_OFF[22:0] 614400 Conforming to graphics expansion setting GR1_FLM6 GR1_FORMAT[3:0] 0 Frame buffer read format RGB565 GR1_FLM_RD GR1_R_ENB 1 Frame buffer read enabled Scaling-up Selection SCL0_US8 RES_IBUS_SYNC_SEL 0 Scaled-up video signal displayed GR1_AB1 GR1_DISP_SEL[1:0] 1 Scaling display selected R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2069 of 3092 Section 33 Video Display Controller 4 (3): Scaler Page 2070 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Section 34 Video Display Controller 4 (4): Image Quality Improver 34.1 Image Quality Improver 34.1.1 Overview of Functions The image quality improver subjects scaled YCbCr signals to black stretching, LTI/sharpness processing, and GBR conversion by using a color matrix. The image quality improver does not act on RGB signals. Color matrix (TINT) HS,VS HE,VE YCbCr/R GB888 (24bit) LTI(H2,4) Sharpness (H1,2,3) Scaler Black stretch Figure 34.1 is a functional block diagram of the image quality improver. HS,VS HE,VE RGB888 (24bit) Image synthesizer Register control Image quality improver Figure 34.1 Functional Block Diagram of Image Quality Improver 34.1.2 Register Update Control The control register for image quality improver controls the update timing entirely by vertical synchronous signals. The vertical synchronous signal launched after the update control register is set to 1 is reflected in various registers, following which the update control register is automatically cleared to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2071 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Table 34.1 Register Update Control Register Name Bit Name Initial Value ADJ_UPDATE 0 ADJ_VEN Description Image Quality Improver Register Update 0: Register is not updated. 1: Register is updated by launch of vertical synchronous signal. 34.1.3 Black Stretch Black stretch refers to the black stretch correction of the Y signal of the input video signal of YCbCr format. Correction of the Y signal is done by adjusting the time constant, depth (gain), and start point. Figure 34.2 is a drawing illustrating black stretch correction. Time constant adjustment Depth (gain) adjustment Start point adjustment Setting 1Setting 2Setting 3 Setting 1Setting 2Setting 3 BKSTR_T1[4:0] 8 9 10 BKSTR_T1[4:0] 8 8 8 BKSTR_T1[4:0] 8 8 BKSTR_T2[4:0] 8 7 5 BKSTR_T2[4:0] 8 8 8 BKSTR_T2[4:0] 8 8 8 BKSTR_D[3:0] 5 5 5 BKSTR_D[3:0] 3 6 9 BKSTR_D[3:0] 5 5 5 BKSTR_ST[3:0] 3 3 3 BKSTR_ST[3:0] 3 3 3 BKSTR_ST[3:0] 3 9 15 255 255 64 64 64 48 32 Output signal 255 Output signal Output signal Setting 1Setting 2Setting 3 48 32 Setting 1 16 16 16 Setting 3 0 32 48 Input signal 64 Setting 2 Setting 3 0 16 32 Setting 1 Setting 2 Setting 3 0 48 Setting 1 Setting 2 255 8 0 0 16 32 48 Input signal 64 255 0 16 32 48 64 255 Input signal Figure 34.2 Black Stretch Correction (With Sample Settings) Page 2072 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Table 34.2 Black Stretch Control Register Name Bit Name ADJ_BKSTR_SET BKSTR_ON Initial Value Description 0 Black Stretch On/Off Control 0: Black Stretch Off 1: Black Stretch On ADJ_BKSTR_SET BKSTR_ST[3:0] 0 Black Stretch Start Point 0 (low) to 15 (high) ADJ_BKSTR_SET BKSTR_T1[4:0] 0 Black Stretch Time Constant (T1) 0 (small) to 31 (large) ADJ_BKSTR_SET BKSTR_T2[4:0] 0 Black Stretch Time Constant (T2) 0 (small) to 30 (large), 31: Setting prohibited ADJ_BKSTR_SET BKSTR_D[3:0] 0 Black Stretch Depth 0 (shallow) to 15 (deep) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2073 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.1.4 Enhancer The enhancer subjects the scaled Y signal input to transient improvement (LTI) and sharpness processing in the horizontal direction. (1) Enhancer Area Specification The operating area of the enhancer is specified with reference to the rising edges of the Hsync signal and Vsync signal. ENH_HS should be set to four or greater clocks, and ENH_VS should be set to two or greater lines. Figure 34.3 shows enhancer area setting. Clock Internal V counter Vsync signal output Hsync signal output X 1 2 ENH_HS[10:0] 3 4 1 2 3 4 5 6 7 8 9 Internal H counter ENH_HW[10:0] 1 2 ENH_VS[10:0] X 3 1 3 ENH_VW[10:0] 2 4 5 6 m-1 Enhancer is enabled in the period defined by ENH_HS [10:0] = 4, ENH_HW [10:0] = 9, ENH_VS [10:0] = 3, and ENH_VW [10:0] = 6 m Figure 34.3 Period when Enhancer is Enabled Setting ENH_DISP_ON to 1 displays the enhancer-enabled area with frame lines. Page 2074 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Table 34.3 Enhancer Area Control Register Name Bit Name ADJ_ENH_TIM1 ENH_MD Initial Value Description 1 Operating Mode 0: RGB mode 1: YCbCr mode ADJ_ENH_TIM2 ENH_VS[10:0] 0 Start Position of Vertical Valid Image Area in Enhancer-Enabled Area Note: Set to 2 or greater lines. ADJ_ENH_TIM2 ENH_VW[10:0] 0 Width of Vertical Valid Image Area in EnhancerEnabled Area ADJ_ENH_TIM3 ENH_HS[10:0] 0 Start Position of Horizontal Valid Image Area in Enhancer-Enabled Area Note: Set to 4 or greater clocks. ADJ_ENH_TIM3 ENH_HW[10:0] 0 Width of Horizontal Valid Image Area in Enhancer-Enabled Area ADJ_ENH_TIM1 ENH_DISP_ON 0 Frame Line Display in Enhancer-Enabled Area 0: Off 1: On (2) LTI (Luminance Transient Improvement) The enhancer subjects the Y signal input to transient improvement in the horizontal direction. Transient improvement of the blanking signal is turned off. Input signal Output signal after correction Figure 34.4 LTI Correction After edge detection of the image, the LTI can be independently controlled in the two horizontal bands. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2075 of 3092 Section 34 Video Display Controller 4 (4): Image Quality Improver SH7268 Group, SH7269 Group In LTI, the median filter is inserted after edge detection of the image. In LTI (H4), the reference pixels of the median filter can be selected. However, under normal operations, half the tap data (second adjacent pixel) at edge detection is used as reference. Table 34.4 Reference Pixel Table for LTI Reference Pixel for Edge Detection LPF Application Horizontal LTI (H2) Second adjacent pixel used as reference LPF not applied or LPF Adjacent pixel used as (1,2,1) reference Horizontal LTI (H4) Fourth adjacent pixel used as reference LPF (1,2,1) LTI Band Median Filter Reference Pixels Adjacent pixel or second adjacent pixel used as reference In LTI, the detection result can be subjected to a coring process. The core value set in the register is subtracted from the edge detection result, and LTI correction is performed on the coring output after subtraction. Set by coring Set by coring Edge detection result output Coring output Figure 34.5 LTI Coring Page 2076 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Table 34.5 LTI Control Register Name Bit Name Initial Value Description ADJ_ENH_LTI1 LTI_H_ON 0 LTI On/Off Control 0: LTI off 1: LTI on ADJ_ENH_LTI1 LTI_H2_INC_ZERO 10 [7:0] Median Filter LTI Correction Threshold LTI correction is disabled when: right TAP value – center TAP value < LTI1_H2_INC_ZERO or left TAP value – center TAP value < LTI1_H2_INC_ZERO. ADJ_ENH_LTI1 LTI_H2_LPF_SEL 0 LPF Selection for Folding Prevention Before H2 Edge Detection 0: LPF not selected 1: LPF selected ADJ_ENH_LTI1 LTI_H2_GAIN[7:0] 0 LTI Edge Amplitude Value Gain 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) ADJ_ENH_LTI1 LTI_H2_CORE[7:0] 0 LTI Coring (Maximum core value of 255) Amplitude smaller than or equal to the value of LTI_H2_CORE is cored from the edge amplitude value. (A core value setting of 128 remains unchanged.) ADJ_ENH_LTI2 LTI_H4_INC_ZERO 10 [7:0] Median Filter LTI Correction Threshold LTI correction is disabled when: right TAP value – center TAP value < LTI1_H4_INC_ZERO or left TAP value – center TAP value < LTI1_H4_INC_ZERO. ADJ_ENH_LTI2 LTI_H4_MEDIAN_T 0 AP_SEL Median Filter Reference Pixel Select 0: Second adjacent pixel selected as reference 1: Adjacent pixel selected as reference ADJ_ENH_LTI2 LTI_H4_GAIN[7:0] 0 LTI Edge Amplitude Value Gain 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2077 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Initial Value Register Name Bit Name ADJ_ENH_LTI2 LTI_H4_CORE[7:0] 0 Description LTI Coring (Maximum core value of 255) Amplitude less than or equal to the value of LTI_H4_CORE is cored from the edge amplitude value. (A core value setting of 128 remains unchanged.) (3) Sharpness Process The enhancer performs edge enhancement on the Y signal input by adding overshoot and undershoot to the original signal. Edge enhancement of the blanking signal is turned off. Input signal Output signal after correction Figure 34.6 Sharpness Correction After edge detection of the image, the sharpness can be independently controlled in the three horizontal bands. In horizontal sharpness, a 3-tap low-pass filter (LPF) is inserted before edge detection to prevent folding. The LPF can be turned on or off by register setting. Page 2078 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Table 34.6 Reference Pixel Table for Sharpness Sharpness Band Reference Pixel for Edge Detection LPF Application Horizontal sharpness (H1) Adjacent pixel used as reference LPF not applied Horizontal sharpness (H2) Second adjacent pixel used as reference LPF not applied or LPF (1,2,1) Horizontal sharpness (H3) Third adjacent pixel used as reference LPF (1,2,1) The edge amplitude of the edge to be enhanced is adjusted according to the value of SHP_CORE. Edge enhancement is accomplished when the edge detection result of the image is greater than the value of SHP_CORE. In edge enhancement, a correction value is output by multiplying (edge amplitude value SHP_CORE) by sharpness gain. Sharpness is turned off when the edge detection result of the image is smaller than the value of SHP_CORE. When edge amplitude value = SHP_CORE Sharpness turned on using (edge amplitude value-SHP_CORE) When edge amplitude value < SHP_CORE Sharpness turned off SHP_CORE Correction value output Edge detection result Figure 34.7 Sharpness Characteristics R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2079 of 3092 Section 34 Video Display Controller 4 (4): Image Quality Improver SH7268 Group, SH7269 Group Table 34.7 Sharpness Control Register Name Bit Name Initial Value Description ADJ_ENH_SHP1 SHP_H_ON 0 Sharpness On/Off Control 0: Horizontal sharpness off 1: Horizontal sharpness on ADJ_ENH_SHP3 SHP_H2_LPF_ SEL 0 LPF Selection for Folding Prevention Before H2 Edge Detection 0: LPF not selected 1: LPF selected ADJ_ENH_SHP2 SHP_H1_CLIP_O [7:0] 0 Sharpness Correction Value Clipping (on the Overshoot Side) Correction value clipped according to SHP_H1_CLIP_O ADJ_ENH_SHP2 SHP_H1_CLIP_U [7:0] 0 Sharpness Correction Value Clipping (on the Undershoot Side) Correction value clipped according to SHP_H1_CLIP_U ADJ_ENH_SHP2 SHP_H1_GAIN_O 0 [7:0] Sharpness Edge Amplitude Value Gain (on the Overshoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H1_GAIN_O  (edge amplitude value – SHP_H1_CORE) ADJ_ENH_SHP2 SHP_H1_GAIN_U 0 [7:0] Sharpness Edge Amplitude Value Gain (on the Undershoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H1_GAIN_U  (edge amplitude value – SHP_H1_CORE) ADJ_ENH_SHP1 SHP_H1_CORE [6:0] 0 Active Sharpness Range Edge amplitude value  SHP_H1_CORE: Sharpness processing on Edge amplitude value < SHP_H1_CORE: Sharpness processing off Sharpness processing is always on when the edge detection value is 128 or greater. Page 2080 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Register Name Bit Name ADJ_ENH_SHP4 SHP_H2_CLIP_O [7:0] Section 34 Video Display Controller 4 (4): Image Quality Improver Initial Value 0 Description Sharpness Correction Value Clipping (on the Overshoot Side) Correction value clipped according to SHP_H2_CLIP_O ADJ_ENH_SHP4 SHP_H2_CLIP_U [7:0] 0 Sharpness Correction Value Clipping (on the Undershoot Side) Correction value clipped according to SHP_H2_CLIP_U ADJ_ENH_SHP4 SHP_H2_GAIN_O 0 [7:0] Sharpness Edge Amplitude Value Gain (on the Overshoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H2_GAIN_O  (edge amplitude value – SHP_H2_CORE) ADJ_ENH_SHP4 SHP_H2_GAIN_U 0 [7:0] Sharpness Edge Amplitude Value Gain (on the Undershoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H2_GAIN_U  (edge amplitude value – SHP_H2_CORE) ADJ_ENH_SHP3 SHP_H2_CORE [6:0] 0 Active Sharpness Range Edge amplitude value  SHP_H2_CORE: Sharpness processing on Edge amplitude value < SHP_H2_CORE: Sharpness processing off Sharpness processing is always on when the edge detection value is 128 or greater. ADJ_ENH_SHP6 SHP_H3_CLIP_O [7:0] 0 Sharpness Correction Value Clipping (on the Overshoot Side) Correction value clipped according to SHP_H3_CLIP_O ADJ_ENH_SHP6 SHP_H3_CLIP_U [7:0] 0 Sharpness Correction Value Clipping (on the Undershoot Side) Correction value clipped according to SHP_H3_CLIP_U R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2081 of 3092 Section 34 Video Display Controller 4 (4): Image Quality Improver Initial Value Register Name Bit Name ADJ_ENH_SHP6 SHP_H3_GAIN_O 0 [7:0] SH7268 Group, SH7269 Group Description Sharpness Edge Amplitude Value Gain (on the Overshoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H3_GAIN_O  (edge amplitude value – SHP_H3_CORE) ADJ_ENH_SHP6 SHP_H3_GAIN_U 0 [7:0] Sharpness Edge Amplitude Value Gain (on the Undershoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H3_GAIN_U  (edge amplitude value – SHP_H3_CORE) ADJ_ENH_SHP5 SHP_H3_CORE [6:0] 0 Active Sharpness Range Edge amplitude value  SHP_H3_CORE: Sharpness processing on Edge amplitude value < SHP_H3_CORE: Sharpness processing off Sharpness processing is always on when the edge detection value is 128 or greater. 34.1.5 Color Matrix Color matrix is performed by adjusting the offset of each input signal and nine-axis gain. This allows YCbCr to GBR conversion. (1) GBR to GBR Conversion YGIN_A = YGIN + ADJ_MTX_YG  128 CBBIN_A = CBBIN + ADJ_MTX_B  128 CRRIN_A = CRRIN + ADJ_MTX_R  128 YGOUT = (ADJ_MTX_GG  YGIN_A + ADJ_MTX_GB  CBBIN_A + ADJ_MTX_GR  CRRIN_A)  256 CBBOUT = (ADJ_MTX_BG  YGIN_A + ADJ_MTX_BB  CBBIN_A + ADJ_MTX_BR  CRRIN_A)  256 Page 2082 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver CRROUT = (ADJ_MTX_RG  YGIN_A + ADJ_MTX_RB  CBBIN_A + ADJ_MTX_RR  CRRIN_A)  256 (2) YCbCr to GBR Conversion YGIN_A = YGIN + ADJ_MTX_YG  128 CBBIN_A = CBBIN  128 CRRIN_A = CRRIN  128 YGOUT = (ADJ_MTX_GG  YGIN_A + ADJ_MTX_GB  CBBIN_A + ADJ_MTX_GR  CRRIN_A)  256 CBBOUT = (ADJ_MTX_BG  YGIN_A + ADJ_MTX_BB  CBBIN_A + ADJ_MTX_BR  CRRIN_A)  256 CRROUT = (ADJ_MTX_RG  YGIN_A + ADJ_MTX_RB  CBBIN_A + ADJ_MTX_RR  CRRIN_A)  256 Table 34.8 Matrix Coefficients (Standard Values) of SMPTE 293M YGIN Coefficient Bit Setting YGOUT 1.000 CBBIN Coefficient Bit Setting CRRIN Coefficient Bit Setting ADJ_MTX_GG –0.344 = 256 ADJ_MTX_GB –0.714 = 1960 ADJ_MTX_GR = 1865 CBBOUT 1.000 ADJ_MTX_BG 1.772 = 256 ADJ_MTX_BB 0.000 = 454 ADJ_MTX_BR =0 CRROUT 1.000 ADJ_MTX_RG 0.000 = 256 ADJ_MTX_RB 1.402 =0 ADJ_MTX_RR = 359 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2083 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Table 34.9 Color Matrix Control Register Name Bit Name ADJ_MTX_MODE ADJ_MTX_MD [1:0] Initial Value Description 2 Operating Mode 0: GBR  GBR 1: Setting prohibited 2: YCbCr  GBR 3: Setting prohibited ADJ_MTX_YG_ADJ0 ADJ_MTX_YG [7:0] 128 Unsigned (0 (-128) to 128(0) to 255 (+127) [LSB]) ADJ_MTX_CBB_ADJ0 ADJ_MTX_B [7:0] 128 ADJ_MTX_CRR_ADJ0 ADJ_MTX_R [7:0] 128 ADJ_MTX_YG_ADJ0 256 ADJ_MTX_GG [10:0] Y/G Signal Offset (DC) Adjustment B Signal Offset (DC) Adjustment Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) R Signal Offset (DC) Adjustment Unsigned (0 (-128) to 128 (0) to 255 (+127) [LSB]) Gain Adjustment of Y/G Signal of G Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_YG_ADJ1 ADJ_MTX_GB [10:0] 1960 Gain Adjustment of Cb/B Signal of G Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_YG_ADJ1 ADJ_MTX_GR [10:0] 1865 Gain Adjustment of Cr/R Signal of G Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_CBB_ADJ0 ADJ_MTX_BG [10:0] 256 Gain Adjustment of Y/G Signal of B Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Page 2084 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Register Name Bit Name ADJ_MTX_CBB_ADJ1 ADJ_MTX_BB [10:0] Initial Value 454 Description Gain adjustment of Cb/B signal of B Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_CBB_ADJ1 ADJ_MTX_BR [10:0] 0 Gain Adjustment of Cr/R Signal of B Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_CRR_ADJ0 ADJ_MTX_RG 256 [10:0] Gain Adjustment of Y/G Signal of R Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_CRR_ADJ1 ADJ_MTX_RB [10:0] 0 Gain Adjustment of Cb/B Signal of R Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) ADJ_MTX_CRR_ADJ1 ADJ_MTX_RR 359 [10:0] Gain Adjustment of Cr/R Signal of R Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2085 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2 Register Description Table 34.10 shows the register configuration. [Symbols used in Register Description] Initial value : Register value after a reset  : Undefined value R/W : Readable/writable. The written value can be read. R/WC0 : Read and write. Bit is initialized if 0 is written, and ignored if 1 is written. R/WC1 : Read and write. Bit is initialized if 1 is written, and ignored if 0 is written. R : Read-only. The write value should always be 0. /W : Write-only. Read value is undefined. Table 34.10 Image Quality Improver Register Configuration Address Access Size H'FFFF 7680 32/16 H'0000 0000 H'FFFF 7684 32/16 Name Abbreviation R/W Initial Value Register update control register in image quality improver ADJ_UPDATE R/WC1 H'0000 0000 Black stretch register ADJ_BKSTR_SET R/W Enhancer timing adjustment ADJ_ENH_TIM1 register 1 R/W H'0000 0010 H'FFFF 7688 32/16 Enhancer timing adjustment ADJ_ENH_TIM2 register 2 R/W H'0023 01E0 H'FFFF 768C 32/16 Enhancer timing adjustment ADJ_ENH_TIM3 register 3 R/W H'0091 0280 H'FFFF 7690 32/16 Enhancer sharpness register 1 ADJ_ENH_SHP1 R/W H'0000 0000 H'FFFF 7694 32/16 Enhancer sharpness register 2 ADJ_ENH_SHP2 R/W H'0000 0000 H'FFFF 7698 32/16 Enhancer sharpness register 3 ADJ_ENH_SHP3 R/W H'0000 0000 H'FFFF 769C 32/16 Page 2086 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver Name Abbreviation R/W Initial Value Address Access Size Enhancer sharpness register 4 ADJ_ENH_SHP4 R/W H'0000 0000 H'FFFF 76A0 32/16 Enhancer sharpness register 5 ADJ_ENH_SHP5 R/W H'0000 0000 H'FFFF 76A4 32/16 Enhancer sharpness register 6 ADJ_ENH_SHP6 R/W H'0000 0000 H'FFFF 76A8 32/16 Enhancer LTI register 1 ADJ_ENH_LTI1 R/W H'000A 0000 H'FFFF 76AC 32/16 Enhancer LTI register 2 ADJ_ENH_LTI2 R/W H'000A 0000 H'FFFF 76B0 32/16 Matrix mode register in image quality improver ADJ_MTX_MODE R/W H'0000 0002 H'FFFF 76B4 32/16 32/16 Matrix YG control register 0 ADJ_MTX_YG_ in image quality improver ADJ0 R/W H'0080 0100 H'FFFF 76B8 Matrix YG control register 1 ADJ_MTX_YG_ in image quality improver ADJ1 R/W H'07A8 0749 H'FFFF 76BC 32/16 Matrix CBB control register 0 in image quality improver ADJ_MTX_CBB_ ADJ0 R/W H'0080 0100 H'FFFF 76C0 32/16 Matrix CBB control register 1 in image quality improver ADJ_MTX_CBB_ ADJ1 R/W H'01C6 0000 H'FFFF 76C4 32/16 Matrix CRR control register ADJ_MTX_CRR_ 0 in image quality improver ADJ0 R/W H'0080 0100 H'FFFF 76C8 32/16 Matrix CRR control register ADJ_MTX_CRR_ 1 in image quality improver ADJ1 R/W H'0000 0167 H'FFFF 76CC 32/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2087 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.1 Register Update Control Register in Image Quality Improver (ADJ_UPDATE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                ADJ_ VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit: Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ADJ_VEN 0 R/WC1 Image Quality Improver Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2088 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 34.2.2 Section 34 Video Display Controller 4 (4): Image Quality Improver Black Stretch Register (ADJ_BKSTR_SET) Bit: 31 30 29 28 27 26 25 24        BKSTR_ ON 23 22 21 20 - 19 - BKSTR_ST[3:0] 18 17 16 - - - BKSTR_D[3:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 4 3 2 1 0    - - BKSTR_T1[4:0] - BKSTR_T2[4:0] - - - 7 6 5    Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 BKSTR_ON 0 R/W Black Stretch On/Off Control 0: Black stretch off 1: Black stretch on 23 to 20 19 to 16 15 to 13 BKSTR_ST 0 [3:0] R/W BKSTR_D [3:0] 0 R/W  All 0 Black Stretch Start Point Setting values: 0 (low) to 15 (high) Depth of Black Stretch Setting Values: 0 (shallow) to 15 (deep) R Reserved These bits are always read as 0. The write value should always be 0. 12 to 8 BKSTR_T1 0 [4:0] R/W Black Stretch Time Constant (T1) 7 to 5  R Reserved All 0 Setting Values: 0 (small) to 31 (large) These bits are always read as 0. The write value should always be 0. 4 to 0 BKSTR_T2 0 [4:0] R/W Black Stretch Time Constant (T2) Setting Values: 0 (small) to 31 (large) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2089 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.3 Enhancer Timing Adjustment Register 1 (ADJ_ENH_TIM1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            ENH_MD    ENH_ DISP_ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R R R R R R R/W R R R R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 ENH_MD 1 R/W Operating Mode 0: RGB mode 1: YCbCr mode 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ENH_DISP_ 0 ON R/W Frame Line Display On/Off of Enhancer-Enabled Area 0: Display off 1: Display on Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2090 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 34.2.4 Section 34 Video Display Controller 4 (4): Image Quality Improver Enhancer Timing Adjustment Register 2 (ADJ_ENH_TIM2) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 ENH_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - ENH_VW[10:0] - - - - - Initial value: 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 ENH_VS [10:0] 35 R/W Start Position of Vertical Valid Image Area in Enhancer-Enabled Area Note: Set to 2 or greater lines. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ENH_VW [10:0] 480 R/W Width of Vertical Valid Image Area in EnhancerEnabled Area Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2091 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.5 Enhancer Timing Adjustment Register 3 (ADJ_ENH_TIM3) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 ENH_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - ENH_HW[10:0] - - - - - Initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 ENH_HS [10:0] 145 R/W Start Position of Horizontal Valid Image Area in Enhancer-Enabled Image Area Note: Set to 4 or greater clocks. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ENH_HW [10:0] 640 R/W Width of Horizontal Image Area in Enhancer-Enabled Area Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2092 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 34.2.6 Section 34 Video Display Controller 4 (4): Image Quality Improver Enhancer Sharpness Register 1 (ADJ_ENH_SHP1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                SHP_H _ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0          - - SHP_H1_CORE[6:0] - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 SHP_H_ON 0 R/W Sharpness On/Off Control 0: Horizontal sharpness off 1: Horizontal sharpness on 15 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 to 0 SHP_H1_ CORE[6:0] 0 R/W Active Sharpness Range Edge amplitude value  SHP_H1_CORE: Sharpness processing on Edge amplitude value < SHP_H1_CORE: Sharpness processing off Sharpness processing is always on when the edge detection value is 128 or greater. Note: This register is updated when ADJ_VEN is in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2093 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.7 Enhancer Sharpness Register 2 (ADJ_ENH_SHP2) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - SHP_H1_CLIP_O[7:0] - 28 27 26 25 24 - - 23 22 21 - -SHP_H1_CLIP_U[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - -SHP_H1_GAIN_O[7:0] - - - - -SHP_H1_GAIN_U[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 24 SHP_H1_ 0 CLIP_O[7:0] R/W Description R/W Sharpness Correction Value Clipping (on the Overshoot Side) Correction value clipped according to SHP_H1_CLIP_O 23 to 16 SHP_H1_ 0 CLIP_U[7:0] R/W Sharpness Correction Value Clipping (on the Undershoot Side) Correction value clipped according to SHP_H1_CLIP_U 15 to 8 SHP_H1_ GAIN_O [7:0] 0 R/W Sharpness Edge Amplitude Value Gain (on the Overshoot Side) 0 (0 times) to 64 (+1 times) to 255 (+approx. 4 times) Sharpness correction value = SHP_H1_GAIN_O × (edge amplitude value – SHP_H1_CORE) 7 to 0 SHP_H1_ GAIN_U [7:0] 0 R/W Sharpness Edge Amplitude Value Gain (on the Undershoot Side) 0 (0 times) to 64 (+1 times) to 255 (+approx. 4 times) Sharpness correction value = SHP_H1_GAIN_U × (Edge amplitude value – SHP_H1_CORE) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2094 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 34.2.8 Section 34 Video Display Controller 4 (4): Image Quality Improver Enhancer Sharpness Register 3 (ADJ_ENH_SHP3) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                SHP_H2_ LPF_SEL Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0          - - - SHP_H2_CORE[6:0] - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 SHP_H2_ LPF_SEL 0 R/W LPF Selection for Folding Prevention Before H2 Edge Detection 0: LPF not selected 1: LPF selected 15 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 to 0 SHP_H2_ CORE[6:0] 0 R/W Active Sharpness Range Edge amplitude value  SHP_H2_CORE: Sharpness processing on Edge amplitude value < SHP_H2_CORE: Sharpness processing off Sharpness processing is unchanged when the edge detection value is 128 or higher Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2095 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.9 Enhancer Sharpness Register 4 (ADJ_ENH_SHP4) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - SHP_H2_CLIP_O[7:0] - 28 27 26 25 24 - - 23 22 21 - -SHP_H2_CLIP_U[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - -SHP_H2_GAIN_O[7:0] - - - - -SHP_H2_GAIN_U[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 24 SHP_H2_ 0 CLIP_O[7:0] R/W Description R/W Sharpness Correction Value Clipping (on the Overshoot Side) Correction value clipped according to SHP_H2_CLIP_O 23 to 16 SHP_H2_ 0 CLIP_U[7:0] R/W Sharpness Correction Value Clipping (on the Undershoot Side) Correction value clipped according to SHP_H2_CLIP_U 15 to 8 SHP_H2_ GAIN_O [7:0] 0 R/W Sharpness Edge Amplitude Value Gain (on the Overshoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H2_GAIN_O × (edge amplitude value – SHP_H2_CORE) 7 to 0 SHP_H2_ GAIN_U [7:0] 0 R/W Sharpness Edge Amplitude Value Gain (on the Undershoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H2_GAIN_U × (edge amplitude value – SHP_H2_CORE) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2096 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.10 Enhancer Sharpness Register 5 (ADJ_ENH_SHP5) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0          - - SHP_H3_CORE[6:0] - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 to 0 SHP_H3_ CORE[6:0] 0 R/W Active Sharpness Range Edge amplitude value  SHP_H3_CORE: Sharpness processing on Edge amplitude value < SHP_H3_CORE: Sharpness processing off Sharpness processing is unchanged when the edge detection value is 128 or higher Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2097 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.11 Enhancer Sharpness Register 6 (ADJ_ENH_SHP6) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 25 24 - SHP_H3_CLIP_O[7:0] - 28 27 26 - - 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 14 13 12 11 10 - -SHP_H3_GAIN_O[7:0] - 23 22 21 17 16 - -SHP_H3_CLIP_U[7:0] - 20 19 18 - - 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 9 8 7 6 5 4 3 2 - - - -SHP_H3_GAIN_U[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 24 SHP_H3_ 0 CLIP_O[7:0] R/W Description R/W Sharpness Correction Value Clipping (on the Overshoot Side) Correction value clipped according to SHP_H3_CLIP_O 23 to 16 SHP_H3_ 0 CLIP_U[7:0] R/W Sharpness Correction Value Clipping (on the Undershoot Side) Correction value clipped according to SHP_H3_CLIP_U 15 to 8 SHP_H3_ GAIN_O [7:0] 0 R/W Sharpness Edge Amplitude Value Gain (on the Overshoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H3_GAIN_O  (Edge amplitude value – SHP_H3_CORE) 7 to 0 SHP_H3_ GAIN_U [7:0] 0 R/W Sharpness Edge Amplitude Value Gain (on the Undershoot Side) 0 (0 times) to 64 (+1 times) to 255 (+ approx. 4 times) Sharpness correction value = SHP_H3_GAIN_U  (Edge amplitude value – SHP_H3_CORE) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2098 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.12 Enhancer LTI Register 1 (ADJ_ENH_LTI1) Bit: Initial value: 31 30 29 28 27 26 25 24 LTI_H_ ON       LTI_H2_ LPF_SEL 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 23 22 21 - - 20 19 18 17 16 - - - LTI_H2_INC_ZERO[7:0] - 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - LTI_H2_GAIN[7:0] - LTI_H2_CORE[7:0] - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 LTI_H_ON 0 R/W LTI On/Off Control 0: LTI off 1: LTI on 30 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 LTI_H2_ LPF_SEL 0 R/W LPF Selection for Folding Prevention Before H2 Edge Detection 0: LPF not selected 1: LPF selected 23 to 16 LTI_H2_INC 10 _ZERO[7:0] R/W Median Filter LTI Correction Threshold LTI correction is disabled when | right TAP value – center TAP value | < LTI_H2_INC_ZERO or | left TAP value – center TAP value | < LTI_H2_INC_ZERO 15 to 8 7 to 0 LTI_H2_ GAIN[7:0] 0 LTI_H2_ CORE[7:0] 0 R/W LTI Edge Amplitude Value Gain 0 (0 times) to 64 (+ 1 times) to 255 (+ approx. 4 times) R/W LTI Coring (Maximum Core value of 255) Amplitude less than or equal to the value of LTI_H2_CORE is cored from the edge amplitude value. (A core value setting of 128 remains unchanged) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2099 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.13 Enhancer LTI Register 2 (ADJ_ENH_LTI2) Bit: 31 30 29 28 27 26 25 24        LTI_H4_ MEDIAN_ TAP_SEL 23 22 21 - - 20 19 18 17 16 - - - - - LTI_H4_INC_ZERO[7:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - Initial value: 0 R/W: R/W LTI_H4_GAIN[7:0] LTI_H4_CORE[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 23 to 16 LTI_H4_ MEDIAN_ TAP_SEL 0 R/W Median Filter Reference Pixel Select 0: Second adjacent pixel selected as reference 1: Adjacent pixel selected as reference LTI_H4_INC 10 _ZERO[7:0] R/W Median Filter LTI Correction Threshold LTI correction is disabled when | right TAP value – center TAP value | < LTI_H4_INC_ZERO or | left TAP value – center TAP value | < LTI_H4_INC_ZERO 15 to 8 7 to 0 LTI_H4_ GAIN[7:0] 0 LTI_H4_ CORE[7:0] 0 R/W LTI Edge Amplitude Value Gain 0 (0 times) to 64 (+ 1 times) to 255 (+ approx. 4 times) R/W LTI Coring (Maximum Core value of 255) Amplitude less than or equal to the value of LTI_H4_CORE is cored from the edge amplitude value (A core value setting of 128 remains unchanged) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2100 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.14 Matrix Mode Register in Image Quality Improver (ADJ_MTX_MODE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0               ADJ_MTX_ -MD[1:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 R/W: R R R R R R R R R R R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 ADJ_MTX_ 2 MD[1:0] R/W Operating Mode 0: GBR  GBR 1: Setting prohibited 2: YCbCr  GBR 3: Setting prohibited Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2101 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.15 Matrix YG Control Register 0 in Image Quality Improver (ADJ_MTX_YG_ADJ0) 23 22 21 20 19 31 30 29 28 27 26 25 24         Initial value: 0 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4      - Initial value: 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: - - Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved 18 ADJ_MTX_YG[7:0] - 17 16 - - 0 0 0 R/W R/W R/W R/W 3 2 1 0 - - - 0 0 0 0 0 R/W R/W R/W R/W R/W ADJ_MTX_GG[10:0] These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 11 ADJ_MTX_ 128 YG[7:0] R/W  R All 0 Y/G Signal Offset (DC) Adjustment Unsigned (0 (-128) to (128 (0) to 255 (+127) [LSB]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ADJ_MTX_ 256 GG[10:0] R/W Gain Adjustment of Y/G Signal of G Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2102 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.16 Matrix YG Control Register 1 in Image Quality Improver (ADJ_MTX_YG_ADJ1) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 ADJ_MTX_GB[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - ADJ_MTX_GR[10:0] - Initial value: 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 ADJ_MTX_ 1960 GB[10:0] R/W  R All 0 Gain Adjustment of Cb/B Signal of G Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ADJ_MTX_ 1865 GR[10:0] R/W Gain Adjustment of Cr/R Signal of G Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2103 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.17 Matrix CBB Control Register 0 in Image Quality Improver (ADJ_MTX_CBB_ADJ0) 23 22 21 20 19 31 30 29 28 27 26 25 24         Initial value: 0 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4      - Initial value: 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: - - Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved 18 ADJ_MTX_B[7:0] - 17 16 - - 0 0 0 R/W R/W R/W R/W 3 2 1 0 - - - 0 0 0 0 0 R/W R/W R/W R/W R/W ADJ_MTX_BG[10:0] These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 11 ADJ_MTX_ 128 B[7:0] R/W  R All 0 B Signal Offset (DC) Adjustment Unsigned (0 (-128) to (128 (0) to 255 (+127) [LSB]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ADJ_MTX_ 256 BG[10:0] R/W Gain Adjustment of Y/G Signal of B Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2104 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.18 Matrix CBB Control Register 1 in Image Quality Improver (ADJ_MTX_CBB_ADJ1) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 1 1 1 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 - - - - 0 0 1 1 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W ADJ_MTX_BB[10:0] - ADJ_MTX_BR[10:0] - Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved 16 These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 ADJ_MTX_ 454 BB[10:0] R/W  R All 0 Gain Adjustment of Cb/B Signal of B Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ADJ_MTX_ 0 BR[10:0] R/W Gain Adjustment of Cr/R Signal of B Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2105 of 3092 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.19 Matrix CRR Control Register 0 in Image Quality Improver (ADJ_MTX_CRR_ADJ0) 23 31 30 29 28 27 26 25 24         Initial value: 0 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R R R R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5      - Bit: 22 - 19 20 21 - 18 16 17 ADJ_MTX_R[7:0] - - - 0 0 0 0 R/W R/W R/W R/W R/W 4 3 2 1 0 - - - ADJ_MTX_RG[10:0] Initial value: 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 50. The write value should always be 50. 23 to 16 15 to 11 ADJ_MTX_ 128 R[7:0] R/W  R All 0 R Signal Offset (DC) Adjustment Unsigned (0 (-128) to (128 (0) to 255 (+127) [LSB]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ADJ_MTX_ 256 RG[10:0] R/W Gain Adjustment of Y/G Signal of R Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. Page 2106 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 34 Video Display Controller 4 (4): Image Quality Improver 34.2.20 Matrix CRR Control Register 1 in Image Quality Improver (ADJ_MTX_CRR_ADJ1) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Initial value: 0 0 0 0 0 0 0 1 0 1 1 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - 0 0 1 1 1 R/W R/W R/W R/W R/W ADJ_MTX_RB[10:0] - ADJ_MTX_RR[10:0] - Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved 16 These bits are always read as 0. The write value should always be 0. 26 to 16 15 to 11 ADJ_MTX_ 0 RB[10:0] R/W  R All 0 Gain Adjustment of Cb/B Signal of R Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 ADJ_MTX_ 359 RR[10:0] R Gain Adjustment of Cr/R Signal of R Signal Output Signed (complement of 2) (-1024 to +1023 [LSB], 256 [LSB] = 1.0 [times]) Note: This register is updated when ADJ_VEN in ADJ_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2107 of 3092 Section 34 Video Display Controller 4 (4): Image Quality Improver 34.3 Usage Method 34.3.1 Black Stretch Usage Method SH7268 Group, SH7269 Group The degree of black stretch can be adjusted by setting the depth (BKSTR_D[3:0]) and the start point (BKSTR_ST[3:0]) of the black stretch. The variation in the black stretch time axis can be adjusted by setting the time constant (BKSTR_T1[4:0] and BKSTR_T2[4:0]). By setting the time constant, changes that occur abruptly due to swapping of the scene can be controlled. Table 34.11 Black Stretch Setting Register Register Name Bit Name Set Value ADJ_BKSTR_SET BKSTR_ON When black stretch is on: 1 ADJ_BKSTR_SET BKSTR_D[3:0] Set the depth of black stretch. The depth increases as the value becomes larger. ADJ_BKSTR_SET BKSTR_ST[3:0] Set the start point of black stretch. The stretching area becomes larger as the value becomes larger. ADJ_BKSTR_SET BKSTR_T1[4:0] Set the time constant of black stretch in the positive direction. The changes are more delayed as the value becomes larger. ADJ_BKSTR_SET BKSTR_T2[4:0] Set the time constant of black stretch in the negative direction. The changes are more delayed as the value becomes larger. Note: ADJ_VEN in ADJ_UPDATE should be set to 1 after setting the registers. Page 2108 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 34.3.2 Section 34 Video Display Controller 4 (4): Image Quality Improver LTI Processing of Enhancer Figure 34.8 shows an example of LTI adjustment. LTI_H2_GAIN adjustment LTI_H4_GAIN adjustment Enhancer output Y signal Enhancer output Y signal LTI gain is adjusted with the LTI_H2_GAIN and LTI_H4_GAIN bits. The center frequency of LTI differs in the LTI _H2_GAIN and LTI_H4_GAIN bits. Figure 34.8 Example of LTI Adjustment R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2109 of 3092 Section 34 Video Display Controller 4 (4): Image Quality Improver 34.3.3 SH7268 Group, SH7269 Group Sharpness Processing of Enhancer Figure 34.9 shows an example of sharpness adjustment. Enhancer output Y signal Enhancer output Y signal Sharpness gain is adjusted on the undershoot side with the SHP_H1_GAIN_U, SHP_H2_GAIN_U, and SHP_H3_GAIN_U bits. Sharpness gain is adjusted on the overshoot side with the SHP_H1_GAIN_O, SHP_H2_GAIN_O, and SHP_H3_GAIN_O bits. Enhancer output Y signal Enhancer output Y signal Sharpness clipping is adjusted on the undershoot side with the SHP_H1_CLIP_U, SHP_H2_CLIP_U, and SHP_H3_CLIP_U bits. Sharpness clipping is adjusted on the overshoot side with the SHP_H1_CLIP_O, SHP_H2_CLIP_O, and SHP_H3_CLIP_O bits. SHP_H1_GAIN_O adjustment SHP_H2_GAIN_O adjustment SHP_H3_GAIN_O adjustment Enhancer output Y signal SHP_H1_GAIN_U adjustment SHP_H2_GAIN_U adjustment Enhancer output Y signal SHP_H3_GAIN_U adjustment Sharpness center frequency differs in the SHP _H1_GAIN_U, SHP_H2_GAIN_U, and SHP_H3_GAIN_U bits. Sharpness center frequency differs in the SHP_H1_GAIN_O, SHP_H2_GAIN_O, and SHP_H3_GAIN_O bits. Figure 34.9 Example of Sharpness Adjustment Page 2110 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 34.3.4 Section 34 Video Display Controller 4 (4): Image Quality Improver Setting Method for Color Matrix Data Conversion GBR signals are assumed to be input to the circuit subsequent to the image quality improver; therefore, the output from the color matrix circuit should be in the GBR format. Table 34.12 shows an example of GBR conversion setting. Table 34.12 Recommended Setting Values for Matrix Conversion GBR to GBR Conversion YCBCR to GBR Conversion Register Name Bit Name Recommended Recommended Values Values ADJ_MTX_MODE ADJ_MTX_MD[1:0] 0 2 ADJ_MTX_YG_ADJ0 ADJ_MTX_YG[7:0] 128 128 ADJ_MTX_CBB_ADJ0 ADJ_MTX_B[7:0] 128 128 ADJ_MTX_CRR_ADJ0 ADJ_MTX_R[7:0] 128 128 ADJ_MTX_YG_ADJ0 ADJ_MTX_GG[10:0] 256 256 ADJ_MTX_YG_ADJ1 ADJ_MTX_GB[10:0] 0 1960 ADJ_MTX_YG_ADJ1 ADJ_MTX_GR[10:0] 0 1865 ADJ_MTX_CBB_ADJ0 ADJ_MTX_BG[10:0] 0 256 ADJ_MTX_CBB_ADJ1 ADJ_MTX_BB[10:0] 256 454 ADJ_MTX_CBB_ADJ1 ADJ_MTX_BR[10:0] 0 0 ADJ_MTX_CRR_ADJ0 ADJ_MTX_RG[10:0] 0 256 ADJ_MTX_CRR_ADJ1 ADJ_MTX_RB[10:0] 0 0 ADJ_MTX_CRR_ADJ1 ADJ_MTX_RR[10:0] 256 359 Note: ADJ_VEN in ADJ_UPDATE should be set to 1 after setting the registers. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2111 of 3092 Section 34 Video Display Controller 4 (4): Image Quality Improver Page 2112 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Section 35 Video Display Controller 4 (5): Image Synthesizer 35.1 Image Synthesizer 35.1.1 Overview of Functions The image synthesizer reads graphics data from the frame buffer and displays the synthesized image on the screen. Two graphics planes + video or three graphics planes can be selected for synthesis. RGB565, RGB888, RGB1555, RGB4444, RGB8888, CLUT8, CLUT4, CLUT1, and YCbCr422 (for the graphics 1 process) formats can be used for graphics data, and RGB565, RGB888, and YCbCr422 formats for video data. On each of the graphics planes, background color, lower-layer graphics, current graphics, or blended image (graphics 2 and 3 processes) of lower-layer graphics and current graphics can be displayed. The large-capacity on-chip RAM and external SDRAM can be used as the frame buffer. However, display may not be possible if the bus bandwidth is insufficient when using external SDRAM. Therefore, it is recommended that the frame buffer be allocated in the large-capacity on-chip RAM. The functional block diagram of the image synthesizer is shown below. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2113 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer IV4-BUS(read) IV3-BUS(read) IV2-BUS(read) [Graphics] RGB565 = 16 bits RGB888 = 32 bits RGB1555 = 16 bits RGB4444 = 16 bits RGB8888 = 32 bits CLUT8 = 8 bits CLUT4 = 4 bits CLUT1 = 1 bit [Graphics] RGB565 = 16 bits RGB888 = 32 bits RGB1555 = 16 bits RGB4444 = 16 bits RGB8888 = 32 bits CLUT8 = 8 bits CLUT4 = 4 bits CLUT1 = 1 bit Internal bus read control Buffer write control Buffer write control Buffer read control Buffer read control Line buffer Internal bus read control Buffer write control Line buffer Internal bus read control Buffer read control Line buffer [Moving picture] [Graphics] RGB565 = 16 bits RGB565 = 16 bits RGB888 = 32 bits RGB888 = 32 bits YCbCr422 = 16 bits RGB1555 = 16 bits RGB4444 = 16 bits RGB8888 = 32 bits CLUT8 = 8 bits CLUT4 = 4 bits CLUT1 = 1 bit YCbCr422 = 16 bits 422 to 444 conversion Internal bus read control 2 Data expansion 1 Enable adjustment Data expansion 2 Bit extension CLUT control Data expansion 3 [Graphics] Switching Vertical scale up (two TAP linear) CLUT control CLUT table Output image enable signal generation Bit extension CLUT table Bit extension CLUT control Internal bus read control 3 CLUT table Internal bus read control 1 HS,VS,HE,VE [Current graphics] [Current graphics] [Current graphics] Register control Scaler (synchronization, scale up) Register control Scaler (graphics 1) [Lower-layer Graphics] HS,VS HE,VE RGB888 (24 bits) Alpha blending 2 [Lower-layer Graphics] HS,VS HE,VE RGB888 (24 bits) Register control Image synthesizer (graphics 2) HS,VS HE,VE RGB888 (24 bits) Enable signal generation Image quality improver Alpha blending HS,VS HE,VE YCbCr/RGB888 (24 bits) Enable signal generation Scale-up control block HS,VS HE,VE YCbCr/RGB888 (24 bits) Alpha blending Synthesis of moving picture and background Moving picture synthesizing block Output select Trimming Enable signal generation [Moving picture, scale up] Horizontal scale up (two TAP linear) Alpha blending 3 HS,VS HE,VE RGB888 (24 bits) Output controller Register control Image synthesizer (graphics 3) Figure 35.1 Functional Block Diagram of Image Synthesizer Page 2114 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.1.2 Section 35 Video Display Controller 4 (5): Image Synthesizer Graphics Data Read Control Graphics data read can be controlled for the three processes: the graphics 1 process in the scaler and the graphics 2 and 3 processes in the image synthesizer. The register bits of each process can be identified by the number in the register name like GR1_xxxx, GR2_xxxx, and GR3_xxxx, respectively. In the sections except for Register Descriptions, however, the number is omitted like GR_xxxx for convenience sake. (1) Updating Registers The Vsync signal is used to control the update timing of all the registers for graphics display and frame buffer read control. After 1 is set to the bits in the update control register, the contents of the relevant registers are actually modified at the rising edge of the Vsync signal, when the update control register is automatically cleared to 0. Table 35.1 Register Update Control Register Name Bit Name Initial Value Description GR_UPDATE GR_P_VEN 0 Graphics Display Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. GR_UPDATE GR_IBUS_VEN 0 Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2115 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer (2) Frame Buffer Burst Transfer Mode Either 32-byte or 128-byte transfer mode can be selected for accessing the frame buffer in which video data and graphics data are stored. Table 35.2 Frame Buffer Burst Transfer Mode Initial Value Register Name Bit Name GR_FLM1 GR_BST_M 0 D Description Frame Buffer Burst Transfer Mode 0: 32-byte transfer 1: 128- byte transfer (3) Frame Buffer Control Mode More than one frame of data is read from the frame buffer. For graphics data, set the GR_FLM_SEL[1:0] bits to 1, and set the specific display frame number with the GR_FLM_NUM[9:0] bits. For video data, select a mode with the GR_FLM_SEL[1:0] bits depending on the writing process used; the quantity of the frames used for video data is set in the writing process block. Table 35.3 Frame Buffer Control Mode Register Name Bit Name GR_FLM1 Initial Value Description GR_FLM_SEL[1:0] 0 Frame Buffer Address Setting Signal Select 0: Control linked to scaling-down process, or frame 0 selected. *1 1: Register GR_FLM_NUM selected. 2: Control linked to distortion correction, or frame 0 selected. *2 3: Setting prohibited GR_FLM3 GR_FLM_NUM[9:0] 0 Frame Number of Frame Buffer Manually set the frame number when GR_FLM_SEL = 1. Notes: 1. For graphics 1 process, frame buffer control links to the scaling-down process. For the graphics 2 and 3 processes, frame 0 is selected. 2. For graphics 1 process, frame buffer control links to distortion correction. For the graphics 2 and 3 processes, frame 0 is selected. Page 2116 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (4) Section 35 Video Display Controller 4 (5): Image Synthesizer Frame Buffer Read Control The following bit enables or disables read access to the frame buffer. Table 35.4 Frame Buffer Read Control Register Name Bit Name Initial Value Description GR_FLM_RD GR_R_ENB 0 Frame Buffer Read Enable 0: Disables read access to the frame buffer. 1: Enables read access to the frame buffer. (5) Distortion Correction Frame Buffer Control Two frames (frames 0 and 1) are used for distortion correction, and the frame numbers to be read by the image renderer are set. The frame numbers to be read (frames 0 and 1) can be switched by setting the GR_IMR_FLM_INV bit. This bit is enabled only when the GR_FLM_SEL bits are set to 2. Table 35.5 Distortion Correction Frame Buffer Control Initial Value Register Name Bit Name GR1_FLM1 GR1_IMR_FLM_INV 0 Description Sets the frame buffer number for distortion correction.* 0: Does not switch the frame numbers to be read. 1: Switches the frame numbers to be read. Note: * This function is supported for the graphics 1 process only. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2117 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer (6) Frame Buffer Size The following bits set the size of the frame buffer to be read. The numbers of horizontal pixels and of lines in the vertical direction are set with the GR_HW[9:0] and GR_FLM_LNUM[9:0] bits, respectively. Table 35.6 Frame Buffer Size Register Name Bit Name Initial Value GR_FLM6 GR_HW[9:0] 0 Description Sets the width of the horizontal valid period. The width is (GR_HW  1) pixels. Note: Set to 2 or greater. GR_FLM5 GR_FLM_LNUM[9:0] 0 Sets the number of lines in a frame The number of lines is (GR_FLM_LNUM  1). (7) Calculating Addresses in Frame Buffer The data area in the frame buffer is defined using the addresses specified by GR_BASE[31:0], GR_LN_OFF[14:0], and GR_FLM_OFF[22:0] bits and the display frame number. The GR_LN_OFF[14:0] and GR_FLM_OFF[22:0] bits should be set in units of 32/128 bytes (the lower 5/7 bits should be fixed to 0). The GR_BASE[31:0] bits should be set in units of 64 bits to set the display data start position (the lower three bits should be fixed). Page 2118 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer GR_BASE Start address GR_FLM_OFF Frame offset Frame 0 GR_FLM_LNUM+1 Number of lines in vertical direction GR_HW+1 Number of pixels in horizontal direction GR_LN_OFF Line offset Frame 1 GR_FLM_LNUM+1 Number of lines in vertical direction GR_HW+1 Number of pixels in horizontal direction Figure 35.2 Data Arrangement in Frame Buffer R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2119 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.7 Calculation of Addresses in Frame Buffer Register Name Bit Name Initial Value Description GR_FLM2 0 Frame Buffer Base Address GR_BASE[31:0] Sets the start address of the frame buffer where frame data is to be stored. GR_BASE[4:3] and GR_BASE[6:3] are referred to during 32-byte burst transfer and 128-byte burst transfer, respectively, to skip the start line data. The lower 3 bits should be set to 000. GR_FLM3 GR_LN_OFF[14:0] 0 Frame Buffer Line Offset Address Sets the line offset address for calculating the start address of each line. Line 0:GR_BASE Line 1:GR_BASE  GR_LN_OFF × 1 : Line n: GR_BASE  GR_LN_OFF × n For 32-byte transfer, the lower 5 bits should be fixed to 0_0000. For 128-byte transfer, the lower 7 bits should be fixed to 000_0000. GR_FLM4 GR_FLM_OFF[22:0] 0 Frame Buffer Frame Offset Address (lower) Specifies the frame offset address used for calculating the start address of each frame buffer when more than one buffer is used. Buffer 0: GR_BASE Buffer 1: GR_BASE  GR_FLM_OFF × 1 : Buffer n: GR_BASE  GR_FLM_OFF × n For 32-byte transfer, the lower 5 bits should be fixed to 0_0000. For 128-byte transfer, the lower 7 bits should be fixed to 000_0000. Page 2120 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (8) Section 35 Video Display Controller 4 (5): Image Synthesizer Setting Frame Buffer Size Smaller than One Frame Frame buffer size can be set in one-line units. When the number of lines set with the GR_FLM_LOOP[9:0] bits is smaller than the value of the GR_FLM_LNUM[9:0] bits, data is again read from the start address of the frame buffer after the number of lines set with the (GR_FLM_LOOP[9:0] + 1) bits have been read. Table 35.8 Setting of Frame Buffer Size Smaller than One Frame Register Name Bit Name GR_FLM5 Initial Value GR_FLM_LOOP[9:0] 1023 Description Number of lines when reading the addresses repeatedly by returning to the start address after reaching the end address. The number of lines is (GR_FLM_LOOP  1). (9) Line Offset Control for Frame Buffer The following bit sets the line offset address direction of the frame buffer. Table 35.9 Line Offset Address Direction Control for Frame Buffer Register Name Bit Name Initial Value GR_FLM1 0 GR_LN_OFF_DIR Description Selects the line offset address direction of the frame buffer. 0: Increments the address by the line offset address. 1: Decrements the address by the line offset address. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2121 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer GR_LN_OFF Line offset GR_FLM_LNUM+1 Number of lines in vertical direction Number of lines in vertical direction Frame 0 Data is read in a vertically-reversed order starting at the address specified by GR_BASE. GR_FLM_LNUM+1 GR_HW+1 Number of pixels in horizontal direction GR_BASE GR_FLM_OFF Frame offset Start address GR_HW+1 Number of pixels in horizontal direction Frame 1 Figure 35.3 Data Arrangement with Line Offset and Decrement Control Page 2122 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer (10) Selecting Format of Frame Buffer Read Signal Signal formats RGB565, RGB888, RGB1555, RGB4444, RGB8888, CLUT8, CLUT4 and CLUT1 are supported for the graphics 1, 2 and 3 processes. The YCbCr422 format is also supported for the graphics 1 process. The GR_FORMAT[3:0] bits select a signal format. Table 35.10 Format Selection for Frame Buffer Read Signal Register Name Bit Name Initial Value Description GR_FLM6 GR_FORMAT[3:0] 0 Sets the format of the frame buffer read signal. 0: RGB565 1: RGB888 2: RGB1555 3: RGB4444 4: RGB8888 5: CLUT8 6: CLUT4 7: CLUT1 8: YCbCr422 or setting prohibited * 9 to 15: Setting prohibited Note: * Setting this value selects YCbCr422 for the graphics 1 process, and is prohibited for the graphics 2 and 3 processes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2123 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer (11) Endian Control In the frame buffer, data is handled in 64-bit units, and endian of the data to be read can be controlled by setting the GR_ENDIAN_ON bit. When the GR_ENDIAN_ON bit is set to 1 with YCbCr422 selected, data arrangement is controlled with the GR_YCC_SWAP[2:0] bits. [63] [56] R0[7:3] RGB565 RGB888 ARGB1555 ARGB4444 G0[7:3] A0[7:4] R0[7:4] [40] R1[7:3] G0[7:4] A1 B0[7:4] CLUT2[7:4] G1[7:3] A1[7:4] R1[7:4] G1[7:4] CLUT4[7:4] [24] B1[7:4] CLUT6[7:4] [16] G2[7:3] A2[7:4] R2[7:4] G2[7:4] A3 B2[7:4] CLUT10[7:4] [0] B3[7:3] B1[7:0] G3[7:3] A3[7:4] R3[7:4] B3[7:3] G3[7:4] G1[7:0] CLUT5[7:0] CLUT9[7:4] [7] G3[7:2] R3[7:3] R1[7:0] CLUT4[7:0] CLUT8[7:4] [8] R3[7:3] G1[7:0] B2[7:3] A1[7:0] CLUT7[7:4] [15] B2[7:3] R1[7:0] R2[7:3] CLUT3[7:0] CLUT5[7:4] [23] G2[7:2] 8'h00 A2 B0[7:0] CLUT2[7:0] CLUT3[7:4] [31] R2[7:3] B1[7:3] G0[7:0] CLUT1[7:0] CLUT1[7:4] [32] B1[7:3] B0[7:0] R1[7:3] R0[7:0] CLUT0[7:0] [39] G1[7:2] G0[7:0] B0[7:3] A0[7:0] CLUT0[7:4] [47] R0[7:0] R0[7:3] CLUT8 CLUT1 [48] B0[7:3] 8'h00 A0 ARGB8888 CLUT4 [55] G0[7:2] CLUT6[7:0] CLUT11[7:4] CLUT12[7:4] B3[7:4] B1[7:0] CLUT7[7:0] CLUT13[7:4] CLUT14[7:4] CLUT15[7:4] CLUT0, 1, . . . , 6, 7 CLUT8, 9, . . . , 14, 15 CLUT16, 17, . . . , 22, 23 CLUT24, 25, . . . , 30, 31 CLUT32, 33, . . . , 38, 39 CLUT40, 41, . . . , 46, 47 CLUT48, 49, . . . , 54, 55 CLUT56, 57, . . . , 62, 63 CB0[7:0] Y0[7:0] CR0[7:0] Y1[7:0] CB2[7:0] Y2[7:0] CR2[7:0] Y3[7:0] YCbCr422 Figure 35.4 Data Arrangement with Endian Control Disabled [63] RGB565 [56] G0[4:2] RGB888 ARGB1555 ARGB4444 G0[7:5] [47] [40] G1[4:2] A0 B0[7:4] [32] R1[7:3] R0[7:0] R0[7:3] G0[7:6] G1[5:3] A0[7:4] [39] B1[7:3] G0[7:0] B0[7:3] G0[7:4] CLUT8 CLUT1 [48] R0[7:3] B0[7:0] G0[5:3] ARGB8888 CLUT4 [55] B0[7:3] R0[7:4] [31] [24] G2[4:2] A1 B1[7:4] [16] R2[7:3] B1[7:0] R1[7:3] G1[7:6] G2[5:3] A1[7:4] [23] B2[7:3] 8'h00 B1[7:3] G1[7:4] G1[7:5] R1[7:4] [15] [8] G3[4:2] A2 B2[7:4] [0] R3[7:3] R1[7:0] R2[7:3] A2[7:4] [7] B3[7:3] G1[7:0] B2[7:3] G2[7:4] G2[7:5] G2[7:6] G3[5:3] R2[7:4] 8'h00 B3[7:3] G3[7:4] G3[7:5] A3 B3[7:4] R3[7:3] A3[7:4] G3[7:6] R3[7:4] B0[7:0] G0[7:0] R0[7:0] A0[7:0] B1[7:0] G1[7:0] R1[7:0] A1[7:0] CLUT0[7:0] CLUT1[7:0] CLUT2[7:0] CLUT3[7:0] CLUT4[7:0] CLUT5[7:0] CLUT6[7:0] CLUT7[7:0] CLUT0[7:4] CLUT1[7:4] CLUT0, 1, . . . , 6, 7 CLUT2[7:4] CLUT3[7:4] CLUT8, 9, . . . , 14, 15 CLUT4[7:4] CLUT5[7:4] CLUT16, 17, . . . , 22, 23 CLUT6[7:4] CLUT7[7:4] CLUT24, 25, . . . , 30, 31 CLUT8[7:4] CLUT9[7:4] CLUT32, 33, . . . , 38, 39 CLUT10[7:4] CLUT11[7:4] CLUT40, 41, . . . , 46, 47 CLUT12[7:4] CLUT13[7:4] CLUT14[7:4] CLUT48, 49, . . . , 54, 55 CLUT15[7:4] CLUT56, 57, . . . , 62, 63 Figure 35.5 Data Arrangement with Endian Control Enabled [63] [56] YCC_SWAP=0 [55] [48] CB0[7:0] Y0[7:0] YCC_SWAP=1 Y0[7:0] YCC_SWAP=2 CR0[7:0] YCC_SWAP=3 [47] [40] [39] [32] CR0[7:0] Y1[7:0] CB0[7:0] Y1[7:0] Y0[7:0] CB0[7:0] Y0[7:0] CR0[7:0] YCC_SWAP=4 Y1[7:0] YCC_SWAP=5 CR0[7:0] YCC_SWAP=6 YCC_SWAP=7 [31] [24] [23] [16] CB2[7:0] Y2[7:0] CR0[7:0] Y2[7:0] Y1[7:0] CR2[7:0] Y1[7:0] CB0[7:0] CR0[7:0] Y0[7:0] Y1[7:0] CB0[7:0] Y1[7:0] CB0[7:0] CB0[7:0] Y1[7:0] [15] [8] [7] [0] CR2[7:0] Y3[7:0] CB2[7:0] Y3[7:0] CR2[7:0] Y2[7:0] CB2[7:0] Y3[7:0] Y2[7:0] CR2[7:0] Y3[7:0] CB2[7:0] CB0[7:0] Y3[7:0] CR2[7:0] Y2[7:0] CB2[7:0] Y0[7:0] CR2[7:0] Y3[7:0] CB2[7:0] Y2[7:0] Y0[7:0] CR0[7:0] Y3[7:0] CB2[7:0] Y2[7:0] CR2[7:0] CR0[7:0] Y0[7:0] CB2[7:0] Y3[7:0] CR2[7:0] Y2[7:0] Figure 35.6 YCbCr422 Data Arrangement with Swapping Enabled Page 2124 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.11 Endian Control Register Name Bit Name Initial Value GR_FLM6 0 GR_ENDIAN_ON Description Turns on/off the endian control of data read from buffer. 0: Off 1: On GR1_FLM6 GR1_YCC_SWAP [2:0] 0 Controls swapping of data read from buffer in the YCbCr422 format. Valid only when GR1_ENDIAN_ON = 1. * 0: Cb/Y0/Cr/Y1 1: Y0/Cb/Y1/Cr 2: Cr/Y0/Cb/Y1 3: Y0/Cr/Y1/Cb 4: Y1/Cr/Y0/Cb 5: Cr/Y1/Cb/Y0 6: Y1/Cb/Y0/Cr 7: Cb/Y1/Cr/Y0 Note: * These bits are supported for the graphics 1 process only. (12) Display Start Pixel Setting for Read Data When a horizontal offset is applied to display the image data in the frame buffer, the display start pixel is set with the GR_BASE[31:0] and GR_STA_POS[5:0] bits. Calculation of the values for the GR_BASE[31:0] and GR_STA_POS[5:0] bits depends on the signal format. The display start pixel can be calculated with the formulas in the table below, where H_OFF is a horizontal offset from the display start pixel. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2125 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.12 Calculation of Display Start Position for Various Signal Formats Signal Format of Video/Graphics Number of Bits per Pixel Calculation Formula * RGB888 32 GR_BASE[31:3] = t (H_OFF ÷ 2) 1 RGB8888 GR_STA_POS[5:0] = mod (H_OFF ÷ 2) YCbCr422*2 RGB565 16 GR_BASE[31:3] = int (H_OFF ÷ 4) RGB1555 GR_STA_POS[5:0] = mod (H_OFF ÷ 4) RGB4444 CLUT8 8 CLUT4 4 GR_BASE[31:3] = int (H_OFF ÷ 8) GR_STA_POS[5:0] = mod (H_OFF ÷ 8) GR_BASE[31:3] = int (H_OFF ÷ 16) GR_STA_POS[5:0] = mod (H_OFF ÷ 16) CLUT1 1 GR_BASE[31:3] = int (H_OFF ÷ 64) GR_STA_POS[5:0] = mod (H_OFF ÷ 64) Notes: 1. The functions int() and mod() output a quotient and a remainder, respectively. 2. The YCbCr422 format is not supported for the graphics 2 and 3 processes. In the YCbCr422 format, 32 bits are used for two pixels (Cb, Y0, Cr, and Y1 components). Therefore, the start position is controlled in units of 32 bits. Table 35.13 Setting of Display Start Pixel of Read Data Register Name Bit Name Initial Value GR_FLM6 GR_STA_POS[5:0] 0 Description Sets the amount of data to be skipped through. Specifically data amount equal to the amount indicated by GR_STA_POS is skipped from the start of the line. GR_FLM2 GR_BASE[31:0] 0 Frame Buffer Base Address Sets the start address of the frame buffer where frame data is to be stored. GR_BASE[4:3] and GR_BASE[6:3] are referred to during 32-byte burst transfer and 128-byte burst transfer, respectively, to skip the start line data. The lower 3 bits should be fixed to 000. Page 2126 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer (13) YCbCr422 to YCbCr444 Conversion Data format for the graphics 1 process is converted from YCbCr422 to YCbCr444. This function is not supported for the graphics 2 and 3 processes. Table 35.14 YCbCr422 to YCbCr444 Conversion Register Name Bit Name Initial Value GR1_FLM6 0 GR1_CNV444_MD Description Sets the interpolation mode for YCbCr422 to YCbCr444 conversion. * 0: Hold interpolation 1: Average interpolation Note: * This register is not provided for the graphics 2 and 3 processes, for which the YCbCr422 format is not supported. (14) Bit Extension Converts RGB565, RGB888, RGB1555, and RGB4444 formats to RGB8888.  RGB565 to RGB8888 Format Conversion After conversion, [7:0] is fixed to 255. After conversion, R[7:0] = R[4:0]  263  32 (round off to an integer), approximation of R[4:0]  255  31 After conversion G[7:0] = G[5:0]  259  64 (round off to an integer), approximation of G[5:0]  255  63 After conversion, B[7:0] = B[4:0]  263  32 (round off to an integer), approximation of B[4:0]  255  31  RGB888 to RGB8888 Format Conversion After conversion, [7:0] is fixed to 255. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2127 of 3092 Section 35 Video Display Controller 4 (5): Image Synthesizer SH7268 Group, SH7269 Group  RGB1555 to RGB8888 Format Conversion After conversion, [7:0] is GR_A1 when  input is 1, and GR_A0 when 0. After conversion, R[7:0] = R[4:0]  263  32 (round off to an integer), approximation of R[4:0]  255  31 After conversion, G[7:0] = G[4:0]  263  32 (round off to an integer), approximation of G[4:0]  255  31 After conversion, B[7:0] = B[4:0]  263  32 (round off to an integer), approximation of B[4:0]  255  31  RGB4444 to RGB8888 Format Conversion After conversion, [7:0] = [3:0]  17 After conversion, R[7:0] = R[3:0]  17 After conversion, G[7:0] = G[3:0]  17 After conversion, B[7:0] = B[3:0]  17 (15) Buffer Underflow Processing When data read from the frame buffer cannot be completed due to bus-traffic related problems, an underflow interrupt signal is output. Page 2128 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.1.3 Section 35 Video Display Controller 4 (5): Image Synthesizer Setting Graphics Display Area The graphics display area is set with the GR_GRC_HS[10:0], GR_GRC_HW[10:0], GR_GRC_VS[10:0], and GR_GRC_VW[10:0] bits based on the rising edges of the Hsync and Vsync signals. Figure 35.7 shows the graphics display area. Clock Hsync signal 0 1 2 3 4 5 6 7 8 9 n-1 n HCNT[10:0] 0 1 2 3 4 5 Valid graphics area when GR_GRC_HS[10:0] = 2, GR_GRC_HW[10:0] = 6, GR_GRC_VS[10:0] = 1, and GR_GRC_VW[10:0] = 4 m-1 m VCNT[10:0] Vsync signal Figure 35.7 Graphics Display Area The frame line of the graphics area can be displayed by setting the GR_GRC_DISP_ON bit to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2129 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.15 Graphics Image Area Setting Register Name Bit Name Initial Value GR_AB3 GR_GRC_HS[10:0] 0 Description Sets the horizontal start position of the graphics image area. Note: Set to 16 or greater clocks and the result of GR_GRC_HS + GR_GRC_HW should be smaller than or equal to 2015 clocks. GR_AB3 GR_GRC_HW[10:0] 0 Sets the horizontal width of the graphics image area. Note: For displaying an image with 1- or 2pixel horizontal width, set GR_HW to 2 and GR_GRC_HW to 1 (1-pixel) or 2 (2-pixel). GR_AB2 GR_GRC_VS[10:0] 0 Sets the vertical start position of the graphics image area. Note: Set to 4 or greater lines and the result of GR_GRC_VS + GR_GRC_VW should be smaller than or equal to 2039 lines. GR_AB2 GR_GRC_VW[10:0] 0 Sets the vertical width of the graphics image area. GR_AB1 GR_GRC_DISP_ON 0 Turns on/off frame-line display of the graphics image area. 0: Frame-line display off 1: Frame-line display on Page 2130 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.1.4 Section 35 Video Display Controller 4 (5): Image Synthesizer Interrupt Generation at Specified Line An interrupt signal can be generated at the line specified with the GR3_LINE[10:0] bits. Table 35.16 Interrupt Generation at Specified Line Register Name Bit Name Initial Value Description GR3_CLUT_INT GR3_LINE[10:0] 0 Line Interrupt Set * When the number of lines matches the value of the GR3_LINE bits, an interrupt signal is output. This function is enabled even when the graphics 3 process is not used. Note: 35.1.5 * This function is supported for the graphics 3 process only; these bits are not supported for the graphics 1 and 2 processes. Formats of Frame Buffer Read Signals and Corresponding Alpha Blending Types Setting the GR_FORMAT[3:0] bits selects the format of the signal read from the frame buffer. Table 35.17 shows the signal formats and the corresponding alpha blending types. The blending functions are only available to the graphics 2 and 3 processes. The priority of the alpha value is: alpha blending in rectangular area > chroma-key processing > alpha blending in pixel units. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2131 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.17 Formats of Frame Buffer Read Signal and Corresponding Alpha Blending Types GR_FORMAT [3:0] Alpha Blending in Rectangular Signal Format Area RGB-Index Chroma-Key Processing CLUT-Index Chroma-Key Processing Alpha Blending in Pixel Units 0 RGB565 Supported Supported *1 Not supported Not supported *2 1 RGB888 Supported Supported Not supported Not supported 2 * 2 RGB1555 Supported Supported *1*3 Not supported Supported *3 3 RGB4444 Supported Supported *1 Not supported Supported 4 RGB8888 Supported Supported Not supported Supported 5 CLUT8 Supported Not supported Supported Supported 5 CLUT4 Supported Not supported Supported 7 CLUT1 Supported * Not supported Supported * Supported *4 8 YCbCr422 Not supported *5 Not supported *5 Not supported *5 Not supported *5 4 Supported 4 Notes: 1. When each color component of the RGB signal read from the frame buffer is not 8 bits, it is converted to 8 bits by calculation in RGB-index chroma-key processing. (See section 35.1.2 (14) Bit Extension.) 2. Since  value is 255, the current graphics is always displayed. 3.  value for data read from the frame buffer is specified with one bit. This one-bit signal selects one of the two registers, each of which holds an 8-bit  value. 4. CLUT value for the frame buffer signal is specified with one bit. This one-bit signal selects one of the two registers, each of which holds the , G, B, and R values (8 bits for each value). The CLUT table is not referenced. 5. YCbCr422 is supported for the graphics 1 process, but any type of blending and chroma key processing cannot be used. Page 2132 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.1.6 Section 35 Video Display Controller 4 (5): Image Synthesizer Display Selection The GR_DISP_SEL[1:0] bits select the graphics to be displayed from the background color, the lower-layer graphics, the current graphics, and the blended image of the lower-layer graphics and the current graphics. For blending, alpha blending in a rectangular area, RGB-index chroma-key processing, CLUT-index chroma-key processing, or alpha blending in one-pixel units can be selected. Table 35.18 shows the settings for various display types. Table 35.18 Settings for Various Display Types GR_DISP_SEL [1:0] Processing for GR_ARC_ON GR_CK_ON Graphics Area Processing for the Area Outside the Graphics Area 0   Background color Background color 1   Lower-layer graphics Lower-layer graphics 2   Current graphics Background color 3 1  Alpha blending in a rectangular area* Lower-layer graphics 3 0 1 RGB-index or CLUTindex chroma-key processing Lower-layer graphics 3 0 0 Alpha-blending in one- Lower-layer graphics pixel units* Note: * The blending function is supported for the graphics 2 and 3 processes only. Vsync signal Rectangular area setting by the scaler Hsync signal GR_ARC_VS GR_GRC_VS Display area Graphics area [GR_DISP_SEL = 0] Displays the background color set by GR_BASE_G, GR_BASE_B, GR_BASE_R [GR_DISP_SEL = 1] Displays the lower-layer graphics. [GR_DISP_SEL = 2] Displays the current graphics. [GR_DISP_SEL = 3] Displays the alpha-blended image of the lower-layer graphics and current graphics. GR_ARC_VW GR_ARC_HS GR_ARC_HW GR_GRC_HS GR_GRC_HW Rectangular area setting by the scaler GR_GRC_VW Alpha blending image of the rectangular area [GR_DISP_SEL = 0] Displays the background color set by GR_BASE_G, GR_BASE_B, GR_BASE_R [GR_DISP_SEL = 1] Displays the lower-layer graphics [GR_DISP_SEL = 2] Displays the background color set by GR_BASE_G, GR_BASE_B, GR_BASE_R [GR_DISP_SEL = 3] Displays the lower-layer graphics [GR_DISP_SEL = 3,GR_ARC_ON = 1] Displays the alpha-blended image of the rectangular area Figure 35.8 Graphic Display Types R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2133 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Figure 35.9 shows the graphics planes displayed when the GR_DISP_SEL bits are set to 3. For correspondence between the lower-layer graphics and the current graphics, see figure 35.1. Current graphics Lower-layer graphics Current graphics and lower-layer graphics are blended and Displayed using the following formula ( × = 0 to 255): (Current graphics ×  + lower graphics × (255 - ))/255 Figure 35.9 Graphics Planes with GR_DISP_SEL Set to 3 Table 35.19 Alpha Blending Setting Register Name Bit Name Initial Value Description GR_AB1 0 Selects the graphics display mode. GR_DISP_SEL[1:0] 0: Background color display 1: Lower-layer graphics display 2: Current graphics display 3: Blended display of lower-layer graphics and current graphics*1 GR_AB1 GR_ARC_ON 0 Turns on/off alpha blending in a rectangular 2 area.* 0: Off 1: On GR_AB7 GR_CK_ON 0 Turns on/off CLUT-index/RGB-index chromakey processing. 0: Off 1: On Notes: 1. The graphics 1 process supports the chroma key process only. When performing chroma key processing, set the  value for converting the pixels to be subjected to chroma key processing, and the  value of the pixels not to be subjected to the chroma key processing to 255 to display the current graphics only. 2. This function is supported only for the graphics 2 and 3 processes. This bit is not provided for the graphics 1 process. Page 2134 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.1.7 Section 35 Video Display Controller 4 (5): Image Synthesizer Background Color Display Processing The color set with the GR_BASE_G[7:0], GR_BASE_B[7:0], and GR_BASE_R[7:0] bits is displayed. G output = GR_BASE_G B output = GR_BASE_B R output = GR_BASE_R Table 35.20 Background Color Setting Register Name Bit Name Initial Value Description GR_BASE 0 Background color G signal GR_BASE_G[7:0] G: 8 bits; unsigned (0 to 255 [LSB]) GR_BASE GR_BASE_B[7:0] 0 Background color B signal B: 8 bits; unsigned (0 to 255 [LSB]) GR_BASE GR_BASE_R[7:0] 0 Background color R signal R: 8 bits; unsigned (0 to 255 [LSB]) 35.1.8 Lower-Layer Graphics Display Processing The lower-layer graphics are displayed as follows: G output = G input of lower-layer graphics B output = B input of lower-layer graphics R output = R input of lower-layer graphics 35.1.9 Current Graphics Display Processing The current graphics are displayed as follows: G output = G input of current graphics B output = B input of current graphics R output = R input of current graphics R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2135 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.1.10 Display with Alpha Blending in a Rectangular Area The rectangular area subjected to alpha blending is set with the GR_ARC_HS[10:0], GR_ARC_HW[10:0], GR_ARC_VS[10:0], and GR_ARC_VW[10:0] bits based on the rising edges of the Hsync and Vsync signals. This function is not supported for the graphics 1 process. Figure 35.10 shows the rectangular area setting for alpha blending. Clock Hsync signal 0 1 2 3 4 5 6 7 8 9 n-1 n HCNT[10:0] 0 1 2 3 4 5 Valid graphics area when GR_ARC_HS[10:0] = 2, GR_ARC_HW[10:0] = 6, GR_ARC_VS[10:0] = 1, and GR_ARC_VW[10:0] = 4 m-1 m VCNT[10:0] Vsync signal Figure 35.10 Rectangular Area Setting for Alpha Blending The frame line of graphics area can be displayed by setting the GR_ARC_DISP_ON bit to 1. Page 2136 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.21 Setting of Rectangular Area for Alpha Blending Register Name Bit Name Initial Value GR_AB5 GR_ARC_HS[10:0] 0 Sets the horizontal start position of the valid image area for alpha blending in a rectangular area. GR_AB5 GR_ARC_HW[10:0] 0 Sets the horizontal width of the valid image area for alpha blending in a rectangular area. GR_AB4 GR_ARC_VS[10:0] 0 Sets the vertical start position of the valid image area for alpha blending in a rectangular area. GR_AB4 GR_ARC_VW[10:0] 0 Sets the vertical width of the valid image area for alpha blending in a rectangular area. GR_AB1 GR_ARC_DISP_ON 0 Turns on/off frame-line display of the image area for alpha blending in a rectangular area. Description 0: Frame-line display off 1: Frame-line display on In alpha blending in a rectangular area, the current graphics are faded in or out by setting the fadein or fade-out coefficients with the GR_ARC_DEF[7:0], GR_ARC_MODE, GR_ARC_COEF[7:0], and GR_ARC_RATE[7:0] bits. First, the value of the GR_ARC_DEF[7:0] bits is assigned to the  value. [Alpha value] Then, each time the Vsync signal rises for the number of times set with the GR_ARC_RATE[7:0] bits + 1, the value of the GR_ARC_COEF[7:0] bit is added to or subtracted from the  value. Displays lower-layer graphics Fade-in Displays current graphics Fade-out Displays lower-layer graphics 255 GR_ARC_COEF GR_ARC_RATE 0 GR_ARC_COEF = 0 GR_ARC_COEF > 0 GR_ARC_COEF = 0 GR_ARC_COEF < 0 GR_ARC_COEF = 0 [Time] Figure 35.11 Fade In and Fade Out R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2137 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.22 Setting for Alpha Blending in a Rectangular Area Register Name Bit Name Initial Value GR_AB7 0 GR_ARC_DEF[7:0] Description Sets the initial alpha value for alpha blending in a rectangular area. Note: The initial  value cannot be changed during addition or subtraction (GR_ARC_ST = 1). To change the value during the above condition, the alpha blending in a rectangular area should be off (GR_ARC_ON = 0). GR_AB6 GR_ARC_MODE 0 Alpha Blending Mode in Rectangular Area 0: Addition 1: Subtraction GR_AB6 GR_ARC_COEF[7:0] 0 Sets the alpha coefficient for alpha blending in a rectangular area. (0 to 255) [7:0]: Variation (absolute value) GR_AB6 GR_ARC_RATE[7:0] 0 Sets the frame rate for alpha blending in a rectangular area. GR_MON GR_ARC_ST  Status Flag for Alpha Blending in Rectangular Area 0: Addition or subtraction has been completed. ( value is 0 or 255) 1: Addition or subtraction is in progress. The values specified with the following expressions are used in the alpha blending calculation described in section 35.1.14, Alpha Blending Calculation.  value = Fade-in/out coefficient G value = G input of the current graphics B value = B input of the current graphics R value = R input of the current graphics Page 2138 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.1.11 RGB-Index Chroma-Key Processing The pixels that satisfy all the expressions below are subjected to RGB-index chroma-key processing. G input of the current graphics = GR_CK_KG B input of the current graphics = GR_CK_KB R input of the current graphics = GR_CK_KR In RGB-index chroma-key processing, the values specified with the following expressions are used in the alpha blending calculation described in section 35.1.14, Alpha Blending Calculation.  In RGB1555 format (when GR_FORMAT[3:0] = 2)  value = (GR_A1 or GR_A0 when  input of the current graphics is 1 or 0, respectively) G value = GR_CK_G B value = GR_CK_B R value = GR_CK_R  In other formats (when GR_FORMAT[3:0] = 0, 1, 3, or 4)  value = GR_CK_A G value = GR_CK_G B value = GR_CK_B R value = GR_CK_R For the pixels that are not subjected to RGB-index chroma-key processing, the values specified with the following expressions are used in the alpha blending calculation described in section 35.1.14, Alpha Blending Calculation.  value =  input of the current graphics G value = G input of the current graphics B value = B input of the current graphics R value = R input of the current graphics R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2139 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.23 Setting for RGB-Index Chroma-Key Processing Register Name Bit Name Initial Value GR_AB8 GR_CK_KG[7:0] 0 GR_AB8 GR_CK_KB[7:0] 0 Description G Signal for RGB-Index Chroma-Key Processing G: 8 bits; unsigned (0 to 255 [LSB]) B Signal for RGB-Index Chroma-Key Processing B: 8 bits; unsigned (0 to 255 [LSB]) GR_AB8 GR_CK_KR[7:0] 0 R Signal for RGB-Index Chroma-Key Processing R: 8 bits; unsigned (0 to 255 [LSB]) GR_AB9 GR_CK_A[7:0] 0 Replaced Alpha Signal after RGB-Index Chroma-Key Processing* : 8 bits; unsigned (0 to 255 [LSB]) GR_AB9 GR_CK_G[7:0] 0 Replaced G Signal after RGB-Index ChromaKey Processing G: 8 bits; unsigned (0 to 255 [LSB]) GR_AB9 GR_CK_B[7:0] 0 Replaced B Signal after RGB-Index ChromaKey Processing B: 8 bits; unsigned (0 to 255 [LSB]) GR_AB9 GR_CK_R[7:0] 0 Replaced R Signal after RGB-Index ChromaKey Processing R: 8 bits; unsigned (0 to 255 [LSB]) Note: * To use this function for the graphics 1 process, the alpha value should be set to 255. Page 2140 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.1.12 CLUT-Index Chroma-Key Processing The pixels that satisfy the expression below are subjected to CLUT-index chroma-key processing. CLUT input of the current graphics = GR_CK_KCLUT In CLUT-index chroma-key processing, the values specified with the following expressions are used in the alpha blending calculation described in section 35.1.14, Alpha Blending Calculation.  In CLUT1 format (when GR_FORMAT[3:0] = 7)  value = (GR_A1 or GR_A0 when CLUT input of the current graphics is 1 or 0, respectively) G value = (GR_G1 or GR_G0 when CLUT input of the current graphics is 1 or 0, respectively) B value = (GR_B1 or GR_B0 when CLUT input of the current graphics is 1 or 0, respectively) R value = (GR_R1 or GR_R0 when CLUT input of the current graphics is 1 or 0, respectively)  In other formats (when GR_FORMAT[3:0] = 5 or 6)  value = GR_CK_A G value = GR_CK_G B value = GR_CK_B R value = GR_CK_R For the pixels that are not subjected to CLUT-index chroma-key processing, the values specified with the following expressions are used in the alpha blending calculation described in section 35.1.14, Alpha Blending Calculation.  value =  input of the current graphics G value = G input of the current graphics B value = B input of the current graphics R value = R input of the current graphics R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2141 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.24 Setting for CLUT-Index Chroma-Key Processing Initial Value Register Name Bit Name Description GR_AB8 GR_CK_ 0 KCLUT[7:0] CLUT Signal for CLUT-Index Chroma-Key Processing GR_AB10 GR_A0[7:0] 0 CLUT1 0 Signal* CLUT: 8 bits; unsigned (0 to 255 [LSB]) Replaced with  signal when in the CLUT1 format and CLUT1= 0. Replaced with  signal when in the RGB1555 format and  = 0. GR_AB10 GR_G0[7:0] 0 CLUT1 G0 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 0. GR_AB10 GR_B0[7:0] 0 CLUT1 B0 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 0. GR_AB10 GR_R0[7:0] 0 CLUT1 R0 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 0. GR_AB11 GR_A1[7:0] 0 CLUT1 1 Signal* Replaced with  signal when in the CLUT1 format and CLUT1 = 1. Replaced with  signal when in the RGB1555 format and  = 1. GR_AB11 GR_G1[7:0] 0 CLUT1 G1 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 1. GR_AB11 GR_B1[7:0] 0 CLUT1 B1 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 1. GR_AB11 GR_R1[7:0] 0 CLUT1 R1 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 1. Note: * To use this function for the graphics 1 process, the alpha value should be set to 255. Page 2142 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.1.13 Display with Alpha Blending in One-Pixel Units In the alpha blending in one-pixel units, the values specified with the following expressions are used in the alpha blending calculation described in section 35.1.14, Alpha Blending Calculation.  value =  input of the current graphics G value = G input of the current graphics B value = B input of the current graphics R value = R input of the current graphics 35.1.14 Alpha Blending Calculation Alpha blending of two input signals is performed using the  value as described below (rounded up if the result includes a decimal fraction). G output = (G value   value + G input of the lower-layer graphics  (255   value)) ÷ 256 B output = (B value   value + B input of the lower-layer graphics  (255   value)) ÷ 256 R output = (R value   value + R input of the lower-layer graphics  (255   value)) ÷ 256 35.1.15 CLUT Table When the signal format is CLUT8 or CLUT4, the format is converted to RGB8888 based on the CLUT table. When the format is CLUT1, it is converted to RGB8888 based on the register value. Figure 35.12 shows data arrangement in the CLUT table. 31 24  value 23 16 R value 15 8 G value 7 0 B value Figure 35.12 Data Arrangement in CLUT Table R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2143 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer The CLUT tables are arranged in the following addresses. Graphics 1 CLUT table: H'FFFF6000 to H'FFFF63FF (For CLUT4, addresses H'FFFF6000 to H'FFFF603F are valid.) Graphics 2 CLUT table: H'FFFF6400 to H'FFFF67FF (For CLUT4, addresses H'FFFF6400 to H'FFFF643F are valid.) Graphics 3 CLUT table: H'FFFF6800 to H'FFFF6BFF (For CLUT4, addresses H'FFFF6800 to H'FFFF683F are valid.) Two CLUT tables (CLUT table 0, CLUT table 1) on the different planes are allocated to the same address and one of the tables is selected with the GR_CLT_SEL bit. This allows rewriting one CLUT table when this module refers to the other CLUT table. Table 35.25 CLUT Table Selection Register Name Bit Name Initial Value GR_CLUT 0 GR_CLT_SEL Description CLUT Table Select Signal 0: Selects CLUT table 0. The format is converted to RGB8888 based on the CLUT table 0. CLUT table 1 can be read from or written to by the CPU. 1: Selects CLUT table 1. The format is converted to RGB8888 based on the CLUT table 1. CLUT table 0 can be read from or written to by the CPU. Page 2144 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.2 Section 35 Video Display Controller 4 (5): Image Synthesizer Register Descriptions Tables 35.26 to 35.28 show the register configuration.  Symbols used in Register Description: Initial value: Register value after a reset : Undefined value R/W: Readable/writable. The written value can be read. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored. R/WC1: Readable/writable. Writing 1 initializes the bit. Writing 0 is ignored. R: Read-only. The write value should always be 0. /W: Write-only. The read value is undefined. Table 35.26 shows the register configuration for the graphics 2 process. Table 35.27 shows the register configuration for the graphics 3 process. Table 35.28 shows the CLUT table configuration. The register configuration for the graphics 1 process is described in section 33, Video Display Controller 4 (3): Scaler. Table 35.26 Register Configuration of the Image Synthesizer (Graphics 2 Process) Address Access Size R/WC1 H'0000 0000 H'FFFF 7700 32/16 GR2_FLM_RD R/W H'0000 0000 H'FFFF 7704 32/16 Frame buffer control register 1 (Graphics 2) GR2_FLM1 R/W H'0000 0000 H'FFFF 7708 32/16 Frame buffer control register 2 (Graphics 2) GR2_FLM2 R/W H'0000 0000 H'FFFF 770C 32/16 Frame buffer control register 3 (Graphics 2) GR2_FLM3 R/W H'0000 0000 H'FFFF 7710 32/16 Frame buffer control register 4 (Graphics 2) GR2_FLM4 R/W H'0000 0000 H'FFFF 7714 32/16 Name Abbreviation R/W Graphics 2 register update control register GR2_UPDATE Frame buffer read control register (Graphics 2) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Initial Value Page 2145 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Name Abbreviation R/W Initial Value Address Access Size Frame buffer control register 5 (Graphics 2) GR2_FLM5 R/W H'0000 03FF H'FFFF 7718 32/16 Frame buffer control register 6 (Graphics 2) GR2_FLM6 R/W H'0000 0000 H'FFFF 771C 32/16 Alpha blending control register 1 (Graphics 2) GR2_AB1 R/W H'0000 0000 H'FFFF 7720 32/16 Alpha blending control register 2 (Graphics 2) GR2_AB2 R/W H'0000 0000 H'FFFF 7724 32/16 Alpha blending control register 3 (Graphics 2) GR2_AB3 R/W H'0000 0000 H'FFFF 7728 32/16 Alpha blending control register 4 (Graphics 2) GR2_AB4 R/W H'0000 0000 H'FFFF 772C 32/16 Alpha blending control register 5 (Graphics 2) GR2_AB5 R/W H'0000 0000 H'FFFF 7730 32/16 Alpha blending control register 6 (Graphics 2) GR2_AB6 R/W H'0000 0000 H'FFFF 7734 32/16 Alpha blending control register 7 (Graphics 2) GR2_AB7 R/W H'00FF 0000 H'FFFF 7738 32/16 Alpha blending control register 8 (Graphics 2) GR2_AB8 R/W H'0000 0000 H'FFFF 773C 32/16 Alpha blending control register 9 (Graphics 2) GR2_AB9 R/W H'0000 0000 H'FFFF 7740 32/16 Alpha blending control GR2_AB10 register 10 (Graphics 2) R/W H'0000 0000 H'FFFF 7744 32/16 Alpha blending control GR2_AB11 register 11 (Graphics 2) R/W H'0000 0000 H'FFFF 7748 32/16 Background color control register (Graphics 2) GR2_BASE R/W H'0000 0000 H'FFFF 774C 32/16 CLUT table control register (Graphics 2) GR2_CLUT R/W H'0000 0000 H'FFFF 7750 32/16 R H'0000 0000 H'FFFF 7754 32/16 Status monitor register GR2_MON (Graphics 2) Page 2146 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Table 35.27 Register Configuration of the Image Synthesizer (Graphics 3 Process) Address Access Size R/WC1 H'0000 0000 H'FFFF 7780 32/16 GR3_FLM_RD R/W H'0000 0000 H'FFFF 7784 32/16 Frame buffer control register 1 (Graphics 3) GR3_FLM1 R/W H'0000 0000 H'FFFF 7788 32/16 Frame buffer control register 2 (Graphics 3) GR3_FLM2 R/W H'0000 0000 H'FFFF 778C 32/16 Frame buffer control register 3 (Graphics 3) GR3_FLM3 R/W H'0000 0000 H'FFFF 7790 32/16 Frame buffer control register 4 (Graphics 3) GR3_FLM4 R/W H'0000 0000 H'FFFF 7794 32/16 Frame buffer control register 5 (Graphics 3) GR3_FLM5 R/W H'0000 03FF H'FFFF 7798 32/16 Frame buffer control register 6 (Graphics 3) GR3_FLM6 R/W H'0000 0000 H'FFFF 779C 32/16 Alpha blending control register 1 (Graphics 3) GR3_AB1 R/W H'0000 0000 H'FFFF 77A0 32/16 Alpha blending control register 2 (Graphics 3) GR3_AB2 R/W H'0000 0000 H'FFFF 77A4 32/16 Alpha blending control register 3 (Graphics 3) GR3_AB3 R/W H'0000 0000 H'FFFF 77A8 32/16 Alpha blending control register 4 (Graphics 3) GR3_AB4 R/W H'0000 0000 H'FFFF 77AC 32/16 Alpha blending control register 5 (Graphics 3) GR3_AB5 R/W H'0000 0000 H'FFFF 77B0 32/16 Alpha blending control register 6 (Graphics 3) GR3_AB6 R/W H'0000 0000 H'FFFF 77B4 32/16 Alpha blending control register 7 (Graphics 3) GR3_AB7 R/W H'00FF 0000 H'FFFF 77B8 32/16 Alpha blending control register 8 (Graphics 3) GR3_AB8 R/W H'0000 0000 H'FFFF 77BC 32/16 Alpha blending control register 9 (Graphics 3) GR3_AB9 R/W H'0000 0000 H'FFFF 77C0 Name Abbreviation R/W Graphics 3 register update control register GR3_UPDATE Frame buffer read control register (Graphics 3) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Initial Value 32/16 Page 2147 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer R/W Initial Value Address Access Size Alpha blending control GR3_AB10 register 10 (Graphics 3) R/W H'0000 0000 H'FFFF 77C4 32/16 Alpha blending control GR3_AB11 register 11 (Graphics 3) R/W H'0000 0000 H'FFFF 77C8 32/16 Background color control register (Graphics 3) R/W H'0000 0000 H'FFFF 77CC 32/16 CLUT table and GR3_CLUT_INT interrupt control register (Graphics 3) R/W H'0000 0000 H'FFFF 77D0 32/16 Status monitor register GR3_MON (Graphics 3) R H'0000 0000 H'FFFF 77D4 32/16 Initial Value Address Name Abbreviation GR3_BASE Table 35.28 CLUT Table Configuration Name Abbreviation R/W Access Size Graphics 1 CLUT table GR1_CLUTT R/W  H'FFFF 6000 to H'FFFF 63FF 32 Graphics 2 CLUT table GR2_CLUTT R/W  H'FFFF 6400 to H'FFFF 67FF 32 Graphics 3 CLUT table GR3_CLUTT R/W  H'FFFF 6800 to H'FFFF 6BFF 32 Page 2148 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.2.1 Section 35 Video Display Controller 4 (5): Image Synthesizer Graphics 2 Register Update Control Register (GR2_UPDATE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            GR2_ P_VEN    GR2_ IBUS_ VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/WC1 R R R R/WC1 Bit: Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR2_P_ VEN 0 R/WC1 Graphics Display Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR2_IBUS_ 0 VEN R/WC1 Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2149 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.2 Frame Buffer Read Control Register (Graphics 2) (GR2_FLM_RD) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR2_ R_ENB Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR2_R_ENB 0 R/W Frame Buffer Read Enable 0: Frame buffer reading is disabled. 1: Frame buffer reading is enabled. Note: This register is updated when GR2_IBUS_VEN in GR2_UPDATE is 1. Page 2150 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.2.3 Section 35 Video Display Controller 4 (5): Image Synthesizer Frame Buffer Control Register 1 (Graphics 2) (GR2_FLM1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                GR2_ LN_OFF_ DIR Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8       Initial value: 0 0 0 0 0 0 0 R/W: R R R R R R R/W Bit: 7 6 5 4 3 2 1 0        GR2_ BST_MD 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R/W - GR2_FLM_SEL[1:0] Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 GR2_LN_ OFF_DIR 0 R/W Selects the line offset address direction of the frame buffer. 0: Increments the address by the line offset address. 1: Decrements the address by the line offset address. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 GR2_FLM_ 0 SEL[1:0] R/W Selects a frame buffer address setting signal. 0: Selects frame 0. 1: Selects register GR2_FLM_NUM. 2: Selects frame 0. 3: Setting prohibited 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR2_BST_ 0 MD R/W Frame Buffer Burst Transfer Mode 0: 32-byte transfer 1: 128- byte transfer Note: GR2_LN_OFF_DIR and GR2_FLM_SEL are updated when GR2_IBUS_VEN in GR2_UPDATE is 1. GR2_BST_MD is updated when GR2_IBUS_VEN and GR2_P_VEN in GR2_UPDATE are 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2151 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.4 Frame Buffer Control Register 2 (Graphics 2) (GR2_FLM2) Bit: Initial value: 31 30 29 28 27 26 25 - - - - - - - 0 Initial value: 23 22 21 20 19 18 17 - - - - - 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 2 1 0 - - - - - - - GR2_BASE[15:0] - R/W: R/W Bit: 24 GR2_BASE[31:16] - 0 R/W: R/W 5 4 3 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 0 GR2_BASE 0 [31:0] R/W Description R/W Frame Buffer Base Address (upper) Sets the start address of the frame buffer where frame data is to be stored. GR_BASE[4:3] and GR_BASE[6:3] are referred to during 32-byte burst transfer and 128-byte burst transfer, respectively, to skip the start line data. The lower 3 bits should be fixed to 000. Note: This register is updated when GR2_IBUS_VEN and GR2_P_VEN in GR2_UPDATE are 1. Page 2152 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.2.5 Section 35 Video Display Controller 4 (5): Image Synthesizer Frame Buffer Control Register 3 (Graphics 2) (GR2_FLM3) 31 30 29 28 27 26 25  - - - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8       - Initial value: 0 0 0 0 0 0 0 R/W: R R R R R R R/W Bit: 24 23 22 20 19 18 17 16 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 - - GR2_FLM_NUM[9:0] - - - - 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W GR2_LN_OFF[14:0] - Bit Bit Name Initial Value R/W Description 31  0 R Reserved 21 - This bit is always read as 0. The write value should always be 0. 30 to 16 GR2_LN_ OFF[14:0] 0 R/W Frame Buffer Line Offset Address Sets the line offset address for calculating the start address of each line. Line 0:GR2_BASE Line 1:GR2_BASE  GR2_LN_OFF × 1 : Line n: GR2_BASE  GR2_LN_OFF × n For 32 byte transfer, the lower 5 bits should be fixed to 0_0000. For 128 byte transfer, the lower 7 bits should be fixed to 000_0000. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GR2_FLM_ 0 NUM[9:0] R/W Frame Number of Frame Buffer Manually set the frame number when GR2_FLM_SEL = 1. Note: This register is updated when GR2_IBUS_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2153 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.6 Frame Buffer Control Register 4 (Graphics 2) (GR2_FLM4) Bit: 31 30 29 28 27 26 25 24 23 22 21          - - 20 19 18 17 GR2_FLM_OFF[22:16] - 16 - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - -GR2_FLM_OFF[15:0] - - Initial value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 23  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 22 to 0 GR2_FLM_ 0 OFF[22:0] R/W Frame Buffer Frame Offset Address (upper) Specifies the frame offset address used for calculating the start address of each frame buffer when more than one buffer is used. Buffer 0: GR2_BASE Buffer 1: GR2_BASE  GR2_FLM_OFF × 1 : Buffer n: GR2_BASE  GR2_FLM_OFF × n For 32 byte transfer, the lower 5 bits should be fixed to 0_0000. For 128 byte transfer, the lower 7 bits should be fixed to 000_0000. Note: This register is updated when GR2_IBUS_VEN in GR2_UPDATE is 1. Page 2154 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.2.7 Section 35 Video Display Controller 4 (5): Image Synthesizer Frame Buffer Control Register 5 (Graphics 2) (GR2_FLM5) Bit: 31 30 29 28 27 26 25 24       - - 23 22 21 20 19 GR2_FLM_LNUM[9:0] - 18 17 16 - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - - GR2_FLM_LOOP[9:0] - - - - Initial value: 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GR2_FLM_ 0 LNUM[9:0] R/W  R All 0 Sets number of lines in a frame The number of lines is (GR2_FLM_LNUM  1). Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GR2_FLM_ 1023 LOOP[9:0] R/W Number of lines when reading the addresses repeatedly by returning to the start address after reaching the end address. The number of lines is (GR2_FLM_LOOP  1). Note: This register is updated when GR2_IBUS_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2155 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.8 Frame Buffer Control Register 6 (Graphics 2) (GR2_FLM6) 30 29 28 27 26 25 24 23 22 19 18 17 - - -   - - - - -GR2_HW[9:0] - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    GR2_ ENDIAN_ ON       - - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R R R R/W R/W R/W R/W R/W R/W Bit: 31 GR2_FORMAT[3:0] Initial value: 0 R/W: R/W Bit: Bit Bit Name 31 to 28 GR2_ FORMAT [3:0] 21 20 GR2_STA_POS[5:0] Initial Value R/W Description 0 R/W Sets the format of the frame buffer read signal. 16 0: RGB565 1: RGB888 2: RGB1555 3: RGB4444 4: RGB8888 5: CLUT8 6: CLUT4 7: CLUT1 8 to 15: Setting prohibited 27, 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 GR2_HW [9:0] 0  All 0 R/W Sets the width of the horizontal valid period. The width is (GR2_HW  1) pixels. Note: Set to 2 or greater. 15 to 13 R Reserved These bits are always read as 0. The write value should always be 0. Page 2156 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 12 GR2_ ENDIAN_ ON Section 35 Video Display Controller 4 (5): Image Synthesizer Initial Value R/W Description 0 R/W Turns on/off the endian control of data read from buffer. 0: Off 1: On 11 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 GR2_ STA_POS [5:0] 0 R/W Sets the amount of data to be skipped through. Specifically data amount equal to the amount indicated by GR2_STA_POS is skipped from the start of the line. Note: GR2_ENDIAN_ON and GR2_STA_POS are updated when GR2_P_VEN in GR2_UPDATE is 1. GR2_FORMAT and GR2_HW are updated when GR2_IBUS_VEN and GR2_P_VEN in GR2_UPDATE are 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2157 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.9 Alpha Blending Control Register 1 (Graphics 2) (GR2_AB1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    GR2_ ARC_ON    GR2_ ARC_ DISP_ON    GR2_ GRC_ DISP_ON   Bit: - GR2_DISP_SEL[1:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 GR2_ARC_ 0 ON R/W Turns on/off alpha blending in a rectangular area. 0: Off 1: On 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 GR2_ARC_ 0 DISP_ON R/W Turns on/off frame-line display of the image area for alpha blending in a rectangular area. 0: Frame-line display off 1: Frame-line display on 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR2_GRC_ 0 DISP_ON R/W Turns on/off frame-line display of the graphics image area. 0: Frame-line display off 1: Frame-line display on 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2158 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Initial Value Bit Bit Name 1, 0 GR2_DISP_ 0 SEL[1:0] R/W Description R/W Selects the graphics display mode. 0: Background color display 1: Lower-layer graphics display 2: Current graphics display 3: Blended display of lower-layer graphics and current graphics Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. 35.2.10 Alpha Blending Control Register 2 (Graphics 2) (GR2_AB2) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR2_GRC_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - GR2_GRC_VW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR2_GRC_ 0 VS[10:0] R/W Sets the vertical start position of the graphics image area. Note: Set to 4 or greater lines and the result of GR2_GRC_VS  GR2_GRC_VW should be smaller than or equal to 2039 lines. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR2_GRC_ 0 VW[10:0] R/W Sets the vertical width of the graphics image area. Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2159 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.11 Alpha Blending Control Register 3 (Graphics 2) (GR2_AB3) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR2_GRC_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - GR2_GRC_HW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR2_GRC_ 0 HS[10:0] R/W Sets the horizontal start position of the graphics image area. Note: Set to 16 or greater clocks and the result of GR2_GRC_HS  GR2_GRC_HW should be smaller than or equal to 2015 clocks. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR2_GRC_ 0 HW[10:0] R/W Sets the horizontal width of the graphics image area. Note: For displaying an image with 1- or 2-pixel horizontal width, set GR2_HW to 2 and GR2_GRC_HW to 1 (1-pixel) or 2 (2-pixel). Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. Page 2160 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.12 Alpha Blending Control Register 4 (Graphics 2) (GR2_AB4) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR2_ARC_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - GR2_ARC_VW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR2_ARC_ 0 VS[10:0] R/W Sets the vertical start position of the valid image area for alpha blending in a rectangular area. 15 to 11  R Reserved All 0 These bits are always read as 0. The write value should always be 0. 10 to 0 GR2_ARC_ 0 VW[10:0] R/W Sets the vertical width of the valid image area for alpha blending in a rectangular area. Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2161 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.13 Alpha Blending Control Register 5 (Graphics 2) (GR2_AB5) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR2_ARC_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - GR2_ARC_HW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR2_ARC_ 0 HS[10:0] R/W Sets the horizontal start position of the valid image area for alpha blending in a rectangular area. 15 to 11  R Reserved All 0 These bits are always read as 0. The write value should always be 0. 10 to 0 GR2_ARC_ 0 HW[10:0] R/W Sets the horizontal width of the valid image area for alpha blending in a rectangular area. Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. Page 2162 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.14 Alpha Blending Control Register 6 (Graphics 2) (GR2_AB6) Bit: 31 30 29 28 27 26 25 24        GR2_ARC _MODE 23 22 - 21 20 19 18 GR2_ARC_COEF[7:0] - 17 16 - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0         - GR2_ARC_RATE[7:0] - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 GR2_ARC_ 0 MODE R/W Alpha Blending Mode in Rectangular Area 0: Addition 1: Subtraction 23 to 16 GR2_ARC_ 0 COEF[7:0] R/W Sets the alpha coefficient for alpha blending in a rectangular area. (0 to 255) 15 to 8  R Reserved [7:0]: Variation (absolute value) All 0 These bits are always read as 0. The write value should always be 0. 7 to 0 GR2_ARC_ 0 RATE[7:0] R/W Sets the frame rate for alpha blending in a rectangular area. Note: This bit is updated when GR2_P_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2163 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.15 Alpha Blending Control Register 7 (Graphics 2) (GR2_AB7) Bit: 31 30 29 28 27 26 25 24 23 22 21         - - - 20 19 GR2_ARC_DEF[7:0] - 18 17 - - 16 Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR2_ CK_ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 GR2_ARC_ 255 DEF[7:0] R/W Sets the initial alpha value for alpha blending in a rectangular area. Note: The initial  value cannot be changed during addition or subtraction (GR2_ARC_ST = 1). To change the value during the above condition, the alpha blending in a rectangular area should be off (GR_ARC2_ON = 0). 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR2_CK_ ON 0 R/W Turns on/off CLUT-index/RGB-index chroma-key processing. 0: Off 1: On Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. Page 2164 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.16 Alpha Blending Control Register 8 (Graphics 2) (GR2_AB8) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - -GR2_CK_KCLUT[7:0] - 28 27 26 25 24 - - 23 22 21 - - GR2_CK_KG[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GR2_CK_KB[7:0] - - - - - GR2_CK_KR[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 23 to 16 Initial Value R/W Description GR2_CK_ 0 KCLUT[7:0] R/W CLUT Signal for CLUT-Index Chroma-Key Processing GR2_CK_ KG[7:0] 0 R/W G Signal for RGB-Index Chroma-Key Processing GR2_CK_ KB[7:0] 0 GR2_CK_ KR[7:0] 0 CLUT: Unsigned 8 bits (0 to 255 [LSB]) 15 to 8 7 to 0 G: Unsigned 8 bits (0 to 255 [LSB]) R/W B Signal for RGB-Index Chroma-Key Processing B: Unsigned 8 bits (0 to 255 [LSB]) R/W R Signal for RGB-Index Chroma-Key Processing R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2165 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.17 Alpha Blending Control Register 9 (Graphics 2) (GR2_AB9) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - GR2_CK_A[7:0] - 28 27 26 25 24 - - - 23 22 21 - - 20 19 18 GR2_CK_G[7:0] - 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 2 - - - - GR2_CK_B[7:0] - 6 5 - - GR2_CK_R[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 23 to 16 Initial Value R/W Description GR2_CK_A 0 [7:0] R/W Replaced Alpha Signal after RGB/CLUT-Index Chroma-Key Processing GR2_CK_G 0 [7:0] R/W Replaced G Signal after RGB/CLUT-Index ChromaKey Processing : Unsigned 8 bits (0 to 255 [LSB]) G: Unsigned 8 bits (0 to 255 [LSB]) 15 to 8 GR2_CK_B 0 [7:0] R/W Replaced B Signal after RGB/CLUT-Index ChromaKey Processing B: Unsigned 8 bits (0 to 255 [LSB]) 7 to 0 GR2_CK_R 0 [7:0] R/W Replaced R Signal after RGB/CLUT-Index ChromaKey Processing R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. Page 2166 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.18 Alpha Blending Control Register 10 (Graphics 2) (GR2_AB10) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - 28 0 0 0 R/W R/W 14 13 - - 27 26 25 24 - - - 0 0 0 0 R/W R/W R/W R/W 12 11 10 - GR2_A0[7:0] - GR2_B0[7:0] - 23 22 21 - - 0 0 0 0 R/W R/W R/W R/W 9 8 7 - - 6 5 - - 20 19 18 17 16 - - - 0 0 0 0 R/W R/W R/W R/W R/W 4 3 GR2_G0[7:0] - GR2_R0[7:0] - 2 1 0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 GR2_A0 [7:0] Initial Value R/W Description 0 R/W CLUT1 0 Signal Replaced with  signal when in the CLUT1 format and CLUT1= 0. Replaced with  signal when in the RGB1555 format and  = 0. 23 to 16 15 to 8 7 to 0 GR2_G0 [7:0] 0 GR2_B0 [7:0] 0 GR2_R0 [7:0] 0 R/W CLUT1 G0 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 0. R/W CLUT1 B0 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 0. R/W CLUT1 R0 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 0. Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2167 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.19 Alpha Blending Control Register 11 (Graphics 2) (GR2_AB11) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - 28 27 GR2_A1[7:0] - 26 25 24 - - - 23 22 21 - - 20 19 GR2_G1[7:0] - 18 17 16 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 - - - - - GR2_B1[7:0] - 6 5 - - GR2_R1[7:0] - 2 1 0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 GR2_A1 [7:0] Initial Value R/W Description 0 R/W CLUT1 1 Signal Replaced with  signal when in the CLUT1 format and CLUT1 = 1. Replaced with  signal when in the RGB1555 format and  = 1. 23 to 16 15 to 8 7 to 0 GR2_G1 [7:0] 0 GR2_B1 [7:0] 0 GR2_R1 [7:0] 0 R/W CLUT1 G1 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 1. R/W CLUT1 B1 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 1. R/W CLUT1 R1 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 1. Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. Page 2168 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.20 Background Color Control Register (Graphics 2) (GR2_BASE) Bit: 31 30 29 28 27 26 25 24         23 22 - 21 20 19 18 - GR2_BASE_G[7:0] - 17 16 - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - GR2_BASE_R[7:0] - - - Initial value: 0 R/W: R/W - GR2_BASE_B[7:0] - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 8 7 to 0 GR2_ BASE_G [7:0] 0 GR2_ BASE_B [7:0] 0 GR2_ BASE_R [7:0] 0 R/W Background Color G Signal G: Unsigned 8 bits (0 to 255 [LSB]) R/W Background Color B Signal B: Unsigned 8 bits (0 to 255 [LSB]) R/W Background Color R Signal R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2169 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.21 CLUT Table Control Register (Graphics 2) (GR2_CLUT) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                GR2_ CLT_SEL Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 GR2_CLT_ 0 SEL R/W CLUT Table Select Signal 0: Selects CLUT table 0. The format is converted to RGB8888 based on the CLUT table 0. CLUT table 1 can be read from or written to by the CPU. 1: Selects CLUT table 1. The format is converted to RGB8888 based on the CLUT table 1. CLUT table 0 can be read from or written to by the CPU. 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: This register is updated when GR2_P_VEN in GR2_UPDATE is 1. Page 2170 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.22 Status Monitor Register (Graphics 2) (GR2_MON) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR2_ ARC_ST Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR2_ARC_ 0 ST R Status Flag for Alpha Blending in Rectangular Area 0: Addition or subtraction has been completed. ( value is 0 or 255) 1: Addition or subtraction is in progress. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2171 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.23 Graphics 3 Register Update Control Register (GR3_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            GR3_ P_VEN    GR3_ IBUS_ VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R/WC1 R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR3_P_ VEN 0 R/WC1 Graphics Display Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR3_IBUS_ 0 VEN R/WC1 Frame Buffer Read Control Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2172 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.24 Frame Buffer Read Control Register (Graphics 3) (GR3_FLM_RD) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR3_ R_ENB Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR3_R_ ENB 0 R/W Frame Buffer Read Enable 0: Frame buffer reading is disabled. 1: Frame buffer reading is enabled. Note: This register is updated when GR3_IBUS_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2173 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.25 Frame Buffer Control Register 1 (Graphics 3) (GR3_FLM1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                GR3_ LN_OFF_ DIR Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8       - GR3_FLM_SEL[1:0] 7 6 5 4 3 2 1 0        GR3_ BST_ MD Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 GR3_LN_ OFF_DIR 0 R/W Selects the line offset address direction of the frame buffer. 0: Increments the address by the line offset address. 1: Decrements the address by the line offset address. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 GR3_FLM_ 0 SEL[1:0] R/W Selects a frame buffer address setting signal. 0: Selects frame 0. 1: Selects register GR3_FLM_NUM. 2: Selects frame 0. 3: Setting prohibited 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR3_BST_ 0 MD R/W Frame Buffer Burst Transfer Mode 0: 32-byte transfer 1: 128- byte transfer Note: GR3_LN_OFF_DIR and GR3_FLM_SEL are updated when GR3_IBUS_VEN in GR3_UPDATE is 1. GR3_BST_MD is updated when GR3_IBUS_VEN and GR3_P_VEN in GR3_UPDATE are 1. Page 2174 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.26 Frame Buffer Control Register 2 (Graphics 3) (GR3_FLM2) Bit: Initial value: 31 30 29 28 27 26 - - - - - - 0 Initial value: 24 23 22 - GR3_BASE[31:16] - 21 20 19 18 17 - - - - - 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - GR3_BASE[15:0] - - - - R/W: R/W Bit: 25 0 R/W: R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Bit Bit Name 31 to 0 GR3_BASE 0 [31:0] R/W Description R/W Frame Buffer Base Address (upper) Sets the start address of the frame buffer where frame data is to be stored. GR_BASE[4:3] and GR_BASE[6:3] are referred to during 32-byte burst transfer and 128-byte burst transfer, respectively, to skip the start line data. The lower 3 bits should be fixed to 000. Note: This register is updated when GR3_IBUS_VEN and GR3_P_VEN in GR3_UPDATE are 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2175 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.27 Frame Buffer Control Register 3 (Graphics 3) (GR3_FLM3) 31 30 29 28 27 26 25  - - - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8       - Initial value: 0 0 0 0 0 0 0 R/W: R R R R R R R/W Bit: 24 23 22 20 19 18 17 16 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 - - GR3_FLM_NUM[9:0] - - - - 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W GR3_LN_OFF[14:0] - Bit Bit Name Initial Value R/W Description 31  0 R Reserved 21 - This bit is always read as 0. The write value should always be 0. 30 to 16 GR3_LN_ OFF[14:0] 0 R/W Frame Buffer Line Offset Address Sets the line offset address for calculating the start address of each line. Line 0:GR3_BASE Line 1:GR3_BASE  GR3_LN_OFF × 1 : Line n: GR3_BASE  GR3_LN_OFF × n For 32 byte transfer, the lower 5 bits should be fixed to 0_0000. For 128 byte transfer, the lower 7 bits should be fixed to 000_0000. 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GR3_FLM_ 0 NUM[9:0] R/W Frame Number of Frame Buffer Manually set the frame number when GR3_FLM_SEL = 1. Note: This register is updated when GR3_IBUS_VEN in GR3_UPDATE is 1. Page 2176 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.28 Frame Buffer Control Register 4 (Graphics 3) (GR3_FLM4) Bit: 31 30 29 28 27 26 25 24 23 22 21          - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - -GR3_FLM_OFF[15:0] - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: R/W Bit Bit Name Initial Value R/W Description 31 to 23  All 0 R Reserved 20 19 18 16 17 GR3_FLM_OFF[22:16] - - These bits are always read as 0. The write value should always be 0. 22 to 0 GR3_FLM_ 0 OFF[22:0] R/W Frame Buffer Frame Offset Address (upper) Specifies the frame offset address used for calculating the start address of each frame buffer when more than one buffer is used. Buffer 0: GR3_BASE Buffer 1: GR3_BASE  GR3_FLM_OFF × 1 : Buffer n: GR3_BASE  GR3_FLM_OFF × n For 32 byte transfer, the lower 5 bits should be fixed to 0_0000. For 128 byte transfer, the lower 7 bits should be fixed to 000_0000. Note: This register is updated when GR3_IBUS_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2177 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.29 Frame Buffer Control Register 5 (Graphics 3) (GR3_FLM5) Bit: 31 30 29 28 27 26 25 24       - - 23 22 21 20 19 GR3_FLM_LNUM[9:0] - 18 17 16 - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - - GR3_FLM_LOOP[9:0] - - - - Initial value: 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 15 to 10 GR3_FLM_ 0 LNUM[9:0] R/W  R Sets number of lines in a frame The number of lines is (GR3_FLM_LNUM  1). All 0 Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 GR3_FLM_ 1023 LOOP[9:0] R/W Number of lines when reading the addresses repeatedly by returning to the start address after reaching the end address. The number of lines is (GR3_FLM_LOOP  1). Note: This register is updated when GR3_IBUS_VEN in GR3_UPDATE is 1. 35.2.30 Frame Buffer Control Register 6 (Graphics 3) (GR3_FLM6) Bit: 31 30 29 28 27 26 25 24 23 22 - - -   - - - - GR3_FORMAT[3:0] Initial value: 20 -GR3_HW[9:0] - 19 18 17 - - - 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    GR3_ ENDIAN_ ON       - - - - - 0 R/W: R/W Bit: 21 GR3_STA_POS[5:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R R R R/W R/W R/W R/W R/W R/W Page 2178 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 31 to 28 GR3_ FORMAT [3:0] Section 35 Video Display Controller 4 (5): Image Synthesizer Initial Value R/W Description 0 R/W Sets the format of the frame buffer read signal. 0: RGB565 1: RGB888 2: RGB1555 3: RGB4444 4: RGB8888 5: CLUT8 6: CLUT4 7: CLUT1 8 to 15: Setting prohibited 27, 26  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 GR3_HW [9:0] 0  All 0 R/W Sets the width of the horizontal valid period. The width is (GR3_HW  1) pixels. Note: Set to 2 or greater. 15 to 13 R Reserved These bits are always read as 0. The write value should always be 0. 12 GR3_ ENDIAN_ ON 0 R/W Turns on/off the endian control of data read from buffer. 0: Off 1: On 11 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 GR3_STA_ 0 POS[5:0] R/W Sets the amount of data to be skipped through. Specifically data amount equal to the amount indicated by GR3_STA_POS is skipped from the start of the line. Note: GR3_ENDIAN_ON and GR3_STA_POS are updated when GR3_P_VEN in GR3_UPDATE is 1. GR3_FORMAT and GR3_HW are updated when GR3_IBUS_VEN and GR3_P_VEN in GR3_UPDATE are 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2179 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.31 Alpha Blending Control Register 1 (Graphics 3) (GR3_AB1) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    GR3_ ARC_ON    GR3_ ARC_ DISP_ON    GR3_ GRC_ DISP_ON   - GR3_DISP_SEL[1:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 GR3_ARC_ 0 ON R/W Turns on/off alpha blending in a rectangular area. 0: Off 1: On 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 GR3_ARC_ 0 DISP_ON R/W Turns on/off frame-line display of the image area for alpha blending in a rectangular area. 0: Frame-line display off 1: Frame-line display on 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR3_GRC_ 0 DISP_ON R/W Turns on/off frame-line display of the graphics image area. 0: Frame-line display off 1: Frame-line display on 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2180 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer Initial Value Bit Bit Name 1, 0 GR3_DISP_ 0 SEL[1:0] R/W Description R/W Selects the graphics display mode. 0: Background color display 1: Lower-layer graphics display 2: Current graphics display 3: Blended display of lower-layer graphics and current graphics Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2181 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.32 Alpha Blending Control Register 2 (Graphics 3) (GR3_AB2) Bit: 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - 23 22 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - GR3_GRC_VS[10:0] - GR3_GRC_VW[10:0] - 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR3_GRC_ 0 VS[10:0] R/W Sets the vertical start position of the graphics image area. Note: Set to 4 or greater lines and the result of GR3_GRC_VS  GR3_GRC_VW should be smaller than or equal to 2039 lines. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR3_GRC_ 0 VW[10:0] R/W Sets the vertical width of the graphics image area. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. Page 2182 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.33 Alpha Blending Control Register 3 (Graphics 3) (GR3_AB3) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 23 22 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - GR3_GRC_HS[10:0] - GR3_GRC_HW[10:0] - 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR3_GRC_ 0 HS[10:0] R/W Sets the horizontal start position of the graphics image area. Note: Set to 16 or greater clocks and the result of GR3_GRC_HS  GR3_GRC_HW should be smaller than or equal to 2015 clocks. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR3_GRC_ 0 HW[10:0] R/W Sets the horizontal width of the graphics image area. Note: For displaying an image with 1- or 2-pixel horizontal width, set GR3_HW to 2 and GR3_GRC_HW to 1 (1-pixel) or 2 (2-pixel). Note: All the bits assigned to this address are updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2183 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.34 Alpha Blending Control Register 4 (Graphics 3) (GR3_AB4) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 23 22 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - GR3_ARC_VS[10:0] - GR3_ARC_VW[10:0] - 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR3_ARC_ 0 VS[10:0] R/W Sets the vertical start position of the valid image area for alpha blending in a rectangular area. 15 to 11  R Reserved All 0 These bits are always read as 0. The write value should always be 0. 10 to 0 GR3_ARC_ 0 VW[10:0] R/W Sets the vertical width of the valid image area for alpha blending in a rectangular area. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. Page 2184 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.35 Alpha Blending Control Register 5 (Graphics 3) (GR3_AB5) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 GR3_ARC_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - GR3_ARC_HW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 GR3_ARC_ 0 HS[10:0] R/W Sets the horizontal start position of the valid image area for alpha blending in a rectangular area. 15 to 11  R Reserved All 0 These bits are always read as 0. The write value should always be 0. 10 to 0 GR3_ARC_ 0 HW[10:0] R/W Sets the horizontal width of the valid image area for alpha blending in a rectangular area. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2185 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.36 Alpha Blending Control Register 6 (Graphics 3) (GR3_AB6) Bit: 31 30 29 28 27 26 25 24        GR3_ARC _MODE 23 22 - 21 20 19 18 GR3_ARC_COEF[7:0] - 17 16 - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0         - GR3_ARC_RATE[7:0] - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 GR3_ARC_ 0 MODE R/W Alpha Blending Mode in Rectangular Area 0: Addition 1: Subtraction 23 to 16 GR3_ARC_ 0 COEF[7:0] R/W Sets the alpha coefficient for alpha blending in a rectangular area. (0 to 255) 15 to 8  R Reserved [7:0]: Variation (absolute value) All 0 These bits are always read as 0. The write value should always be 0. 7 to 0 GR3_ARC_ 0 RATE[7:0] R/W Sets the frame rate for alpha blending in a rectangular area. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. Page 2186 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.37 Alpha Blending Control Register 7 (Graphics 3) (GR3_AB7) Bit: 31 30 29 28 27 26 25 24 23 22 21         - - - 20 19 GR3_ARC_DEF[7:0] - 18 17 - - 16 Initial value: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR3_ CK_ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 GR3_ARC_ 255 DEF[7:0] R/W Sets the initial alpha value for alpha blending in a rectangular area. Note: The initial  value cannot be changed during addition or subtraction (GR3_ARC_ST = 1). To change the value during the above condition, the alpha blending in a rectangular area should be off (GR3_ARC_ON = 0). 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR3_CK_ ON 0 R/W Turns on/off CLUT-index/RGB-index chroma-key processing. 0: Off 1: On Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2187 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.38 Alpha Blending Control Register 8 (Graphics 3) (GR3_AB8) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - -GR3_CK_KCLUT[7:0] - 28 27 26 25 24 - - 23 22 21 - - GR3_CK_KG[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GR3_CK_KB[7:0] - - - - - GR3_CK_KR[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 23 to 16 Initial Value R/W Description GR3_CK_ 0 KCLUT[7:0] R/W CLUT Signal for CLUT-Index Chroma-Key Processing GR3_CK_ KG[7:0] 0 R/W G Signal for RGB-Index Chroma-Key Processing GR3_CK_ KB[7:0] 0 GR3_CK_ KR[7:0] 0 CLUT: Unsigned 8 bits (0 to 255 [LSB]) 15 to 8 7 to 0 G: Unsigned 8 bits (0 to 255 [LSB]) R/W B Signal for RGB-Index Chroma-Key Processing B: Unsigned 8 bits (0 to 255 [LSB]) R/W R Signal for RGB-Index Chroma-Key Processing R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. Page 2188 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.39 Alpha Blending Control Register 9 (Graphics 3) (GR3_AB9) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - GR3_CK_A[7:0] - 28 27 26 25 24 - - - 23 22 21 - - 20 19 18 GR3_CK_G[7:0] - 17 16 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 2 - - - - GR3_CK_B[7:0] - 6 5 - - GR3_CK_R[7:0] - 1 0 - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 23 to 16 Initial Value R/W Description GR3_CK_A 0 [7:0] R/W Replaced Alpha Signal after RGB/CLUT-Index Chroma-Key Processing GR3_CK_G 0 [7:0] R/W Replaced G Signal after RGB/CLUT-Index ChromaKey Processing : Unsigned 8 bits (0 to 255 [LSB]) G: Unsigned 8 bits (0 to 255 [LSB]) 15 to 8 GR3_CK_B 0 [7:0] R/W Replaced B Signal after RGB/CLUT-Index ChromaKey Processing B: Unsigned 8 bits (0 to 255 [LSB]) 7 to 0 GR3_CK_R 0 [7:0] R/W Replaced R Signal after RGB/CLUT-Index ChromaKey Processing R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2189 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.40 Alpha Blending Control Register 10 (Graphics 3) (GR3_AB10) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - 0 0 0 R/W R/W 14 13 - - 28 27 22 21 - - 0 0 0 0 R/W R/W R/W R/W 9 8 7 - - 26 25 24 - - - 0 0 0 0 R/W R/W R/W R/W 12 11 10 - GR3_A0[7:0] - GR3_B0[7:0] - 23 6 5 - - 20 19 18 17 16 - - - 0 0 0 0 R/W R/W R/W R/W R/W 4 3 GR3_G0[7:0] - GR3_R0[7:0] - 2 1 0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 GR3_A0 [7:0] Initial Value R/W Description 0 R/W CLUT1 0 Signal Replaced with  signal when in the CLUT1 format and CLUT1= 0. Replaced with  signal when in the RGB1555 format and  = 0. 23 to 16 15 to 8 7 to 0 GR3_G0 [7:0] 0 GR3_B0 [7:0] 0 GR3_R0 [7:0] 0 R/W CLUT1 G0 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 0. R/W CLUT1 B0 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 0. R/W CLUT1 R0 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 0. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. Page 2190 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.41 Alpha Blending Control Register 11 (Graphics 3) (GR3_AB11) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W 30 29 - - 28 27 GR3_A1[7:0] - 26 25 24 - - - 23 22 21 - - 20 19 GR3_G1[7:0] - 18 17 16 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 4 3 - - - - - GR3_B1[7:0] - 6 5 - - GR3_R1[7:0] - 2 1 0 - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 24 GR3_A1 [7:0] Initial Value R/W Description 0 R/W CLUT1 1 Signal Replaced with  signal when in the CLUT1 format and CLUT1 = 1. Replaced with  signal when in the RGB1555 format and  = 1. 23 to 16 15 to 8 7 to 0 GR3_G1 [7:0] 0 GR3_B1 [7:0] 0 GR3_R1 [7:0] 0 R/W CLUT1 G1 Signal Replaced with G signal when in the CLUT1 format and CLUT1 = 1. R/W CLUT1 B1 Signal Replaced with B signal when in the CLUT1 format and CLUT1 = 1. R/W CLUT1 R1 Signal Replaced with R signal when in the CLUT1 format and CLUT1 = 1. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2191 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.42 Background Color Control Register (Graphics 3) (GR3_BASE) Bit: 31 30 29 28 27 26 25 24         23 22 - 21 20 19 18 - GR3_BASE_G[7:0] - 17 16 - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - GR3_BASE_R[7:0] - - - Initial value: 0 R/W: R/W - GR3_BASE_B[7:0] - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 15 to 8 7 to 0 GR3_BASE_G 0 [7:0] R/W GR3_BASE_B 0 [7:0] R/W GR3_BASE_R 0 [7:0] R/W Background Color G Signal G: Unsigned 8 bits (0 to 255 [LSB]) Background Color B Signal B: Unsigned 8 bits (0 to 255 [LSB]) Background Color R Signal R: Unsigned 8 bits (0 to 255 [LSB]) Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. Page 2192 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.43 CLUT Table and Interrupt Control Register (Graphics 3) (GR3_CLUT_INT) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                GR3_ CLT_SEL Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - GR3_LINE[10:0] - - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 GR3_CLT_ 0 SEL R/W CLUT Table Select Signal 0: Selects CLUT table 0. The format is converted to RGB8888 based on the CLUT table 0. CLUT table 1 can be read from or written to by the CPU. 1: Selects CLUT table 1. The format is converted to RGB8888 based on the CLUT table 1. CLUT table 0 can be read from or written to by the CPU. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 GR3_LINE [10:0] 0 R/W Line Interrupt Set When number of lines matches the value of the GR3_LINE bits, an interrupt signal is output. This function is enabled even when the graphics 3 process is not used. Note: This register is updated when GR3_P_VEN in GR3_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2193 of 3092 SH7268 Group, SH7269 Group Section 35 Video Display Controller 4 (5): Image Synthesizer 35.2.44 Status Monitor Register (Graphics 3) (GR3_MON) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GR3_ ARC_ST Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR3_ARC_ 0 ST R Status Flag for Alpha Blending in Rectangular Area 0: Addition or subtraction has been completed. ( value is 0 or 255) 1: Addition or subtraction is in progress. Page 2194 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 35.3 Usage Method 35.3.1 Mute Image Section 35 Video Display Controller 4 (5): Image Synthesizer The initial values of the GR1_DISP_SEL[1:0], GR2_DISP_SEL[1:0], and GR3_DISP_SEL[1:0] bits are all 0. Accordingly, in the initial setting, a background color is displayed both inside and outside the graphics area for graphics 1, 2, and 3 processes. Since the default background color is black, the black mute image is displayed in the initial state. 35.3.2 Alpha Blending in Rectangular Area The alpha coefficient and the frame rate can be changed during fade in and fade out by modifying the GR_ARC_MODE, GR_ARC_COEF[7:0] and GR_ARC_RATE[7:0] bits, respectively. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2195 of 3092 Section 35 Video Display Controller 4 (5): Image Synthesizer Page 2196 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Section 36 Video Display Controller 4 (6): Output Controller 36.1 Output Controller 36.1.1 Overview of Functions The output controller subjects RGB signals output from the image synthesizer to brightness adjustment, contrast adjustment, gamma correction of individual RGB, dither process, and output format conversion. The output controller also generates various timing signals for LCD panel drive. Figure 36.1 shows the function block diagram of the output controller. Output interface LCD TCON Dither process Gamma correction HS,VS, HE,VE, RGB888 (24 bits) Brightness/contrast adjustment Image synthesizer This LSI RGB888 (24 bits) Panel control signal LCD_DATA23 to LCD_DATA0 LCD_TCON6 to LCD_TCON0 Register control Output controller Figure 36.1 Functional Block Diagram of Output Controller R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2197 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.1.2 Register Update Control The Vsync signal is used to control the update timing of all the registers of the output controller. After 1 is set to the bits in the update control register, the contents of the relevant registers are actually modified at the rising edge of the Vsync signal, when the update control register is automatically cleared to 0. Table 36.1 Register Update Control Initial Value Register Name Bit Name OUT_UPDATE OUTCNT_VEN 0 Description Brightness/Contrast Control, Dither Process, Output Interface Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. GAM_G_UPDATE GAM_G_VEN 0 Gamma Correction (G) Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. GAM_B_UPDATE GAM_B_VEN 0 Gamma Correction (B) Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. GAM_R_UPDATE GAM_R_VEN 0 Gamma Correction (R) Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. TCON_UPDATE TCON_VEN 0 LCD TCON Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2198 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.1.3 Section 36 Video Display Controller 4 (6): Output Controller Route Selection The processing sequence of the brightness/contrast control and gamma correction control can be swapped according to the settings of the register. Table 36.2 Route Selection Initial Value Register Name Bit Name OUT_CLK_PHASE OUTCNT_FR 0 ONT_GAM Description Correction Circuit Sequence Control 0: Brightness  contrast  gamma correction 1: Gamma correction  contrast  brightness 36.1.4 Panel Brightness Adjustment Brightness (DC) adjustment is individually performed for RGB signals from image synthesizer. (BRT_R/G/BOUT after brightness adjustment has many bits to prevent overflow or underflow. The overflow or underflow process is performed at contrast calculation.) (1) Calculation formulas for brightness (DC) adjustment BRT_GOUT = GIN + PBRT_G  512 BRT_BOUT = BIN + PBRT_B  512 BRT_ROUT = RIN + PBRT_R  512 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2199 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.3 Brightness (DC) Adjustment Register Name Bit Name Initial Value Description OUT_BRIGHT1 PBRT_G[9:0] 512 Brightness (DC) Adjustment of G Signal Unsigned (0 (-512) to 512 (0) to 1023 (+511) [LSB], 512 [LSB] with offset) OUT_BRIGHT2 PBRT_B[9:0] 512 Brightness (DC) Adjustment of B Signal Unsigned (0 (-512) to 512 (0) to 1023 (+511) [LSB], 512 [LSB] with offset) OUT_BRIGHT2 PBRT_R[9:0] 512 Brightness (DC) Adjustment of R Signal Unsigned (0 (-512) to 512 (0) to 1023 (+511) [LSB], 512 [LSB] with offset) 36.1.5 Contrast Adjustment Contrast is calculated for RGB signals obtained after brightness calculation. (If an overflow or underflow occurs, contrast is clipped to the maximum or minimum value.) (1) Calculation formulas for contrast (gain) adjustment GOUT = BRT_GOUT  CONT_G/128 BOUT = BRT_BOUT  CONT_B/128 ROUT = BRT_ROUT  CONT_R/128 Table 36.4 Contrast (Gain) Adjustment Register Name Bit Name Initial Value Description OUT_CONTRAST CONT_G [7:0] 128 Contrast (Gain) Adjustment of G Signal 0/128 to 255/128 (approx.2 times) OUT_CONTRAST CONT_B [7:0] 128 Contrast (Gain) Adjustment of B Signal 0/128 to 255/128 (approx.2 times) OUT_CONTRAST CONT_R [7:0] 128 Contrast (Gain) Adjustment of R Signal 0/128 to 255/128 (approx.2 times) Page 2200 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.1.6 Section 36 Video Display Controller 4 (6): Output Controller Gamma Correction Gamma correction is carried out by dividing an input signal having 256 gradation levels into 32 and controlling the gain of each area. Gain coefficient of each area can be set as 0 to approx. 2.0 [times] (1) Gamma correction formula for each area DOUT = ((DIN  TH(n))  GAIN(n) + OFFSET(n))/256 DIN: Input signal (8-bit) DOUT: Output signal (10-bit) TH(n): Threshold (8-bit) OFFSET(n): Offset value (19-bit) GAIN(n): Gain coefficient (11-bit) (2) Offset calculation formulas for each area OFFSET(n) = OFFSET(n1) + DEF_O(n) (When n = 0, OFFSET(0) = 0.) DEF_O(n) = (TH(n)  TH(n1))  GAIN(n1 (When n = 0, OFFSET(0) = 0.) OFFSET(n): Offset value of current area (19-bit) OFFSET(n-1): Offset value of previous area (19-bit) DEF_O(n): Difference in offset value of Current and previous area (19-bit) TH(n): Threshold of current area (8-bit) TH(n-1): Threshold of previous area (8-bit) GAIN(n-1): Gain coefficient of previous area (11-bit) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2201 of 3092 SH7268 Group, SH7269 Group DEF_O(3) Section 36 Video Display Controller 4 (6): Output Controller 0 TH(1) OFFSET(3) OFFSET(2) DEF_O(2) OFFSET(1) G AI N( 0) DEF_O(1) GA IN (1 ) Output [LSB] (2) IN A G TH(2) TH(3) Input [LSB] Figure 36.2 Corresponding Chart of Offset Calculation Formulas Page 2202 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 TH_1[7:0]= 8 TH_2[7:0]= 16 TH_3[7:0]= 24 TH_4[7:0]= 32 TH_5[7:0]= 40 TH_6[7:0]= 48 TH_7[7:0]= 56 TH_8[7:0]= 64 TH_9[7:0]= 72 TH_10[7:0]= 80 TH_11[7:0]= 88 TH_12[7:0]= 96 TH_13[7:0]=104 TH_14[7:0]=112 TH_15[7:0]=120 TH_16[7:0]=128 TH_17[7:0]=136 TH_18[7:0]=144 TH_19[7:0]=152 TH_20[7:0]=160 TH_21[7:0]=168 TH_22[7:0]=176 TH_23[7:0]=184 TH_24[7:0]=192 TH_25[7:0]=200 TH_26[7:0]=208 TH_27[7:0]=216 TH_28[7:0]=224 TH_29[7:0]=232 TH_30[7:0]=240 TH_31[7:0]=248 255 Output [LSB] SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Section 36 Video Display Controller 4 (6): Output Controller 1023 Output signal Input signal 0 Input [LSB] Figure 36.3 Example of Input-Output Characteristics of Gamma Correction Page 2203 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.5 Gamma Correction Register Name Bit Name Initial Value Description GAM_SW GAM_ON 0 Gamma Correction On/Off Control 0: Off 1: On GAM_G_AREA1 to GAM_G_TH_01 to * GAM_G_AREA8 GAM_G_TH_31 [7:0] Start Threshold of Area 1 to 31 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area*1 < Threshold of 2 current area < Threshold of next area* *1: GAM_G_TH_01 is 0 *2: GAM_G_TH_31 is  255 *Initial Value GAM_G_TH_01:8, GAM_G_TH_02:16, GAM_G_TH_03:24, GAM_G_TH_04:32, GAM_G_TH_05:40, GAM_G_TH_06:48, GAM_G_TH_07:56, GAM_G_TH_08:64, GAM_G_TH_09:72, GAM_G_TH_10:80 GAM_G_TH_11:88, GAM_G_TH_12:96, GAM_G_TH_13:104, GAM_G_TH_14:112, GAM_G_TH_15:120, GAM_G_TH_16:128, GAM_G_TH_17:136, GAM_G_TH_18:144, GAM_G_TH_19:152, GAM_G_TH_20:160, GAM_G_TH_21:168, GAM_G_TH_22:176, GAM_G_TH_23:184, GAM_G_TH_24:192, GAM_G_TH_25:200, GAM_G_TH_26:208, GAM_G_TH_27:216, GAM_G_TH_28:224, GAM_G_TH_29:232, GAM_G_TH_30:240, GAM_G_TH_31:248 Page 2204 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Initial Value Register Name Bit Name GAM_G_LUT1 to GAM_G_LUT16 GAM_G_GAIN_00 1024 to GAM_G_GAIN_31 [10:0] GAM_B_AREA1 to GAM_B_TH_01 to * GAM_B_AREA8 GAM_B_TH_31 [7:0] Description Gain Adjustment of Area 0 to 31 of G Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) Start Threshold of Area 1 to 31 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area*1 < Threshold of 2 current area < Threshold of next area* *1: GAM_B_TH_01 is 0 *2: GAM_B_TH_31 is  255 *Initial Value GAM_B_TH_01:8, GAM_B_TH_02:16, GAM_B_TH_03:24, GAM_B_TH_04:32, GAM_B_TH_05:40, GAM_B_TH_06:48, GAM_B_TH_07:56, GAM_B_TH_08:64, GAM_B_TH_09:72, GAM_B_TH_10:80 GAM_B_TH_11:88, GAM_B_TH_12:96, GAM_B_TH_13:104, GAM_B_TH_14:112, GAM_B_TH_15:120, GAM_B_TH_16:128, GAM_B_TH_17:136, GAM_B_TH_18:144, GAM_B_TH_19:152, GAM_B_TH_20:160, GAM_B_TH_21:168, GAM_B_TH_22:176, GAM_B_TH_23:184, GAM_B_TH_24:192, GAM_B_TH_25:200, GAM_B_TH_26:208, GAM_B_TH_27:216, GAM_B_TH_28:224, GAM_B_TH_29:232, GAM_B_TH_30:240, GAM_B_TH_31:248 GAM_B_LUT1 to GAM_B_LUT16 GAM_B_GAIN_00 1024 to GAM_B_GAIN_31 [10:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Gain Adjustment of Area 0 to 31 of B Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) Page 2205 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Register Name Bit Name Initial Value GAM_R_AREA1 to GAM_R_TH_01 to * GAM_R_AREA8 GAM_R_TH_31 [7:0] Description Start Threshold of Area 1 to 31 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area*1 < Threshold of 2 current area < Threshold of next area* *1: GAM_R_TH_01 is 0 *2: GAM_R_TH_31 is  255 *Initial Value GAM_R_TH_01:8, GAM_R_TH_02:16, GAM_R_TH_03:24, GAM_R_TH_04:32, GAM_R_TH_05:40, GAM_R_TH_06:48, GAM_R_TH_07:56, GAM_R_TH_08:64, GAM_R_TH_09:72, GAM_R_TH_10:80 GAM_R_TH_11:88, GAM_R_TH_12:96, GAM_R_TH_13:104, GAM_R_TH_14:112, GAM_R_TH_15:120, GAM_R_TH_16:128, GAM_R_TH_17:136, GAM_R_TH_18:144, GAM_R_TH_19:152, GAM_R_TH_20:160, GAM_R_TH_21:168, GAM_R_TH_22:176, GAM_R_TH_23:184, GAM_R_TH_24:192, GAM_R_TH_25:200, GAM_R_TH_26:208, GAM_R_TH_27:216, GAM_R_TH_28:224, GAM_R_TH_29:232, GAM_R_TH_30:240, GAM_R_TH_31:248 GAM_R_LUT1 to GAM_R_LUT16 Page 2206 of 3092 GAM_R_GAIN_00 1024 to GAM_R_GAIN_31 [10:0] Gain Adjustment of Area 0 to 31 of R Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.1.7 Section 36 Video Display Controller 4 (6): Output Controller Dither Process Dither process is carried out by adjusting brightness/contrast or reducing 10-bit RGB signals output from the gamma correction block to 8-bit, 6-bit, or 5-bit RGB signals. The operation mode of dither process can be selected from truncate mode, round-off mode, 2  2 pattern dither mode and random pattern dither mode. Frame (4n) Frame (4n + 2) Clock Clock Hsync signal Hsync signal B C D A B C D A B C D C D A B C D A B C D A B D A B C D A B C D A B A B C D A B C D A B C D A B C D A B C D A B C D C D A B C D A B C D A B C D A B C D A B C D A B A B C D A B C D A B C D A B C D A B C D A B C D C D A B C D A B C D A B C D A B C D A B C D A B A B C D A B C D A B C D Vsync signal Vsync signal A C Frame (4n + 1) Frame (4n + 3) Clock Clock Hsync signal Hsync signal B C D A B C D A B C D A D A B C D A B C D A B D A B C D A B C D A B C B C D A B C D A B C D A B C D A B C D A B C D A D A B C D A B C D A B C A B C D A B C D A B C B C D A B C D A B C D A D A B C D A B C D A B C A : PDTH_PA[1:0] Vsync signal Vsync signal D B C B C D A B C D A B C D A D A B C D A B C D A B C B C D A B C D A B C D A : PDTH_PB[1:0] C : PDTH_PC[1:0] D : PDTH_PD[1:0] Figure 36.4 Operation Specification of 2  2 Pattern Dither R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2207 of 3092 Section 36 Video Display Controller 4 (6): Output Controller SH7268 Group, SH7269 Group The conversion equations are as follows. [Truncate mode] (a) 10 bits to 8 bits Output RGB data[7:0] = Input RGB data[9:0]  4 (truncate the number below the decimal point) (b) 10 bits to 6 bits Output RGB data[7:2] = Input RGB data[9:0]  16 (truncate the number below the decimal point) (c) 10 bits to 5 bits Output RGB data[7:3] = Input RGB data[9:0]  32 (truncate the number below the decimal point) [Round-off mode] (a) 10 bits to 8 bits Output RGB data[7:0] = Input RGB data[9:0]  4 (round off to an integer) (b) 10 bits to 6 bits Output RGB data[7:2] = Input RGB data[9:0]  16 (round off to an integer) (c) 10 bits to 5 bits Output RGB data[7:3] = Input RGB data[9:0]  32 (round off to an integer) [2  2 pattern dither mode, random pattern dither mode] (a) 10 bits to 8 bits Output RGB data[7:0] = Input RGB data[9:0]  4  pattern value at the first decimal place (truncate the number below the decimal point after addition) (b) 10 bits to 6 bits Output RGB data[7:2] = Input RGB data[9:0]  16  pattern value at the first decimal place (truncate the number below the decimal point after addition) Page 2208 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller (c) 10 bits to 5 bits Output RGB data[7:3] = Input RGB data[9:0]  32  pattern value at the first decimal place (truncate the number below the decimal point after addition) Table 36.6 Panel Dither Correction Register Name Bit Name Initial Value Description OUT_PDTHA PDTH_SEL[1:0] 0 Panel Dither Operation Mode 0: Truncate 1: Round-off 2: 2  2 pattern dither 3: Random pattern dither OUT_PDTHA PDTH_FORMAT[1:0] 0 Panel Dither Output Format Select 0: RGB888 1: RGB666 2: RGB565 3: Setting prohibited OUT_PDTHA PDTH_PA[1:0] 3 Pattern Value (A) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) OUT_PDTHA PDTH_PB[1:0] 0 Pattern Value (B) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) OUT_PDTHA PDTH_PC[1:0] 2 Pattern Value (C) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) OUT_PDTHA PDTH_PD[1:0] 1 Pattern Value (D) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2209 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.1.8 Output Format Conversion In output format conversion, the RGB signal after dither process is converted to LCD output signal having any of the following formats, namely, parallel RGB888, parallel RGB666, parallel RGB565, and serial RGB. Further, converted data can be allocated to LCD output pins as selected. (1) Bit Allocation of LCD Signals for RGB888 Output Table 36.7 shows the RGB signal input allocated to the LCD signal output for RGB888 output. R/G/BIN[7:0] are the RGB internal signals after dither process. Table 36.7 Bit Allocation of RGB Signal Input for RGB888 Output OUT_FORMAT 0 0 0 0 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 LCD_DATA23 RIN[7] BIN[7] RIN[0] BIN[0] LCD_DATA22 RIN[6] BIN[6] RIN[1] BIN[1] LCD_DATA21 RIN[5] BIN[5] RIN[2] BIN[2] LCD_DATA20 RIN[4] BIN[4] RIN[3] BIN[3] LCD_DATA19 RIN[3] BIN[3] RIN[4] BIN[4] LCD_DATA18 RIN[2] BIN[2] RIN[5] BIN[5] LCD_DATA17 RIN[1] BIN[1] RIN[6] BIN[6] LCD_DATA16 RIN[0] BIN[0] RIN[7] BIN[7] LCD_DATA15 GIN[7] GIN[7] GIN[0] GIN[0] LCD_DATA14 GIN[6] GIN[6] GIN[1] GIN[1] LCD_DATA13 GIN[5] GIN[5] GIN[2] GIN[2] LCD_DATA12 GIN[4] GIN[4] GIN[3] GIN[3] LCD_DATA11 GIN[3] GIN[3] GIN[4] GIN[4] LCD_DATA10 GIN[2] GIN[2] GIN[5] GIN[5] Page 2210 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller OUT_FORMAT 0 0 0 0 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 LCD_DATA9 GIN[1] GIN[1] GIN[6] GIN[6] LCD_DATA8 GIN[0] GIN[0] GIN[7] GIN[7] LCD_DATA7 BIN[7] RIN[7] BIN[0] RIN[0] LCD_DATA6 BIN[6] RIN[6] BIN[1] RIN[1] LCD_DATA5 BIN[5] RIN[5] BIN[2] RIN[2] LCD_DATA4 BIN[4] RIN[4] BIN[3] RIN[3] LCD_DATA3 BIN[3] RIN[3] BIN[4] RIN[4] LCD_DATA2 BIN[2] RIN[2] BIN[5] RIN[5] LCD_DATA1 BIN[1] RIN[1] BIN[6] RIN[6] LCD_DATA0 BIN[0] RIN[0] BIN[7] RIN[7] (2) Bit Allocation of LCD Signal for RGB666 Output Table 36.8 shows the RGB signal input allocated to the LCD signal output for RGB666 output. R/G/BIN[7:0] are the RGB internal signals after dither process. Table 36.8 Bit Allocation of RGB Signal Input for RGB666 Output OUT_FORMAT 1 1 1 1 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 LCD_DATA23 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA22 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA21 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA20 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA19 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA18 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA17 RIN[7] BIN[7] RIN[2] BIN[2] LCD_DATA16 RIN[6] BIN[6] RIN[3] BIN[3] LCD_DATA15 RIN[5] BIN[5] RIN[4] BIN[4] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2211 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller OUT_FORMAT 1 1 1 1 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 LCD_DATA14 RIN[4] BIN[4] RIN[5] BIN[5] LCD_DATA13 RIN[3] BIN[3] RIN[6] BIN[6] LCD_DATA12 RIN[2] BIN[2] RIN[7] BIN[7] LCD_DATA11 GIN[7] GIN[7] GIN[2] GIN[2] LCD_DATA10 GIN[6] GIN[6] GIN[3] GIN[3] LCD_DATA9 GIN[5] GIN[5] GIN[4] GIN[4] LCD_DATA8 GIN[4] GIN[4] GIN[5] GIN[5] LCD_DATA7 GIN[3] GIN[3] GIN[6] GIN[6] LCD_DATA6 GIN[2] GIN[2] GIN[7] GIN[7] LCD_DATA5 BIN[7] RIN[7] BIN[2] RIN[2] LCD_DATA4 BIN[6] RIN[6] BIN[3] RIN[3] LCD_DATA3 BIN[5] RIN[5] BIN[4] RIN[4] LCD_DATA2 BIN[4] RIN[4] BIN[5] RIN[5] LCD_DATA1 BIN[3] RIN[3] BIN[6] RIN[6] LCD_DATA0 BIN[2] RIN[2] BIN[7] RIN[7] Page 2212 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 36 Video Display Controller 4 (6): Output Controller Bit Allocation of LCD Signal for RGB565 Output Table 36.9 shows the RGB signal input allocated to the LCD signal output for RGB565 output. R/G/BIN[7:0] are the RGB internal signals after dither process. Table 36.9 Bit Allocation of RGB Signal Input for RGB565 Output OUT_FORMAT 2 2 2 2 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 LCD_DATA23 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA22 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA21 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA20 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA19 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA18 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA17 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA16 Fixed to 0 Fixed to 0 Fixed to 0 Fixed to 0 LCD_DATA15 RIN[7] BIN[7] RIN[3] BIN[3] LCD_DATA14 RIN[6] BIN[6] RIN[4] BIN[4] LCD_DATA13 RIN[5] BIN[5] RIN[5] BIN[5] LCD_DATA12 RIN[4] BIN[4] RIN[6] BIN[6] LCD_DATA11 RIN[3] BIN[3] RIN[7] BIN[7] LCD_DATA10 GIN[7] GIN[7] GIN[2] GIN[2] LCD_DATA9 GIN[6] GIN[6] GIN[3] GIN[3] LCD_DATA8 GIN[5] GIN[5] GIN[4] GIN[4] LCD_DATA7 GIN[4] GIN[4] GIN[5] GIN[5] LCD_DATA6 GIN[3] GIN[3] GIN[6] GIN[6] LCD_DATA5 GIN[2] GIN[2] GIN[7] GIN[7] LCD_DATA4 BIN[7] RIN[7] BIN[3] RIN[3] LCD_DATA3 BIN[6] RIN[6] BIN[4] RIN[4] LCD_DATA2 BIN[5] RIN[5] BIN[5] RIN[5] LCD_DATA1 BIN[4] RIN[4] BIN[6] RIN[6] LCD_DATA0 BIN[3] RIN[3] BIN[7] RIN[7] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2213 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller (4) Bit Allocation of LCD Signal for Serial RGB Output For serial RGB output, RGB signal input shown table 36.10 is allocated to rgb internal signals and the signals are converted from parallel to serial format and output as LCD signals. R/G/BIN[7:0] are the RGB internal signals after dither process. The internal signals r[7:0], g[7:0], and b[7:0] are serially output to LCD_DATA7 to LCD_DATA0. Table 36.10 Bit Allocation of RGB Signal Input for Serial RGB Output OUT_FORMAT 3 3 3 3 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 r[7] RIN[7] BIN[7] RIN[0] BIN[0] r[6] RIN[6] BIN[6] RIN[1] BIN[1] r[5] RIN[5] BIN[5] RIN[2] BIN[2] r[4] RIN[4] BIN[4] RIN[3] BIN[3] r[3] RIN[3] BIN[3] RIN[4] BIN[4] r[2] RIN[2] BIN[2] RIN[5] BIN[5] r[1] RIN[1] BIN[1] RIN[6] BIN[6] r[0] RIN[0] BIN[0] RIN[7] BIN[7] g[7] GIN[7] GIN[7] GIN[0] GIN[0] g[6] GIN[6] GIN[6] GIN[1] GIN[1] g[5] GIN[5] GIN[5] GIN[2] GIN[2] g[4] GIN[4] GIN[4] GIN[3] GIN[3] g[3] GIN[3] GIN[3] GIN[4] GIN[4] g[2] GIN[2] GIN[2] GIN[5] GIN[5] g[1] GIN[1] GIN[1] GIN[6] GIN[6] g[0] GIN[0] GIN[0] GIN[7] GIN[7] b[7] BIN[7] RIN[7] BIN[0] RIN[0] b[6] BIN[6] RIN[6] BIN[1] RIN[1] Page 2214 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller OUT_FORMAT 3 3 3 3 OUT_ENDIAN_ON 0 0 1 1 OUT_SWAP_ON 0 1 0 1 b[5] BIN[5] RIN[5] BIN[2] RIN[2] b[4] BIN[4] RIN[4] BIN[3] RIN[3] b[3] BIN[3] RIN[3] BIN[4] RIN[4] b[2] BIN[2] RIN[2] BIN[5] RIN[5] b[1] BIN[1] RIN[1] BIN[6] RIN[6] b[0] BIN[0] RIN[0] BIN[7] RIN[7] (5) Parallel to Serial Conversion As shown in table 36.11, four types of parallel to serial conversions are possible by controlling clock speed mode and selecting the scan direction (‘n’ in the table are natural numbers). Table 36.11 Specifications of Serial RGB Output OUT_FRQ_SEL 1 1 2 2 OUT_DIR_SEL 0 1 0 1 Line (2n-1) Repeated (r  g  b) Repeated (b  g  r) Repeated Repeated (r  g  b  X) (X  b  g  r) Line 2n Repeated (g  b  r) Repeated (r  b  g) Repeated Repeated (r  g  b  X) (X  b  g  r) Figures 36.5 and 36.6 show the timing of parallel to serial conversion in triple speed and quadruple speed modes, respectively. LCD_CLK Line 1 Line 2 Line (2n-1) Line 2n OUT_FRQ_SEL[1:0] = 1 OUT_DIR_SEL = 0 X X X X X X X X r g b r g b r g ... ... ... X X X X X X X X g b r g b r g b ... ...... X X X X X X X X r g b r g b r g ... ...... X X X X X X X X g b r g b r g b ... ... ... X X X X OUT_FRQ_SEL[1:0] = 1 OUT_DIR_SEL= 1 X X X X X X X X b g r b g r b g ... ... ... X X X X X X X X r b g r b g r b ... ...... X X X X X X X X b g r b g r b g ... ...... X X X X X X X X r b g r b g r b ... ... ... X X X X Figure 36.5 Timing of Parallel to Serial Conversion in Triple Speed Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2215 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller LCD_CLK Line 1 Line 2 Line (2n-1) Line 2n OUT_FRQ_SEL[1:0] = 2 OUT_DIR_SEL = 0 X X X X X X X X r g b X r g b X ... ... ... X X X X X X X X r g b X r g b X ... ... ... X X X X X X X X r g b X r g b X ... ... ... X X X X X X X X r g b X r g b X ... ... ... X X X X OUT_FRQ_SEL[1:0] = 2 OUT_DIR_SEL = 1 X X X X X X X X X b g r X b g r ... ... ... X X X X X X X X X b g r X b g r ... ... ... X X X X X X X X X b g r X b g r ... ... ... X X X X X X X X X b g r X b g r ... ... ... X X X X Figure 36.6 Timing of Parallel to Serial Conversion in Quadruple Speed Mode During serial output, the phase timing with the HE signal can be adjusted by OUT_PHASE[0:1]. Figure 36.7 shows the timing of the clock phases of the serial RGB output (triple speed mode). Pixel clock LCD_CLK HE OUT_PHASE[1:0] = 0 LCD_DATA7 to LCD_DATA0 OUT_PHASE[1:0] = 1 LCD_DATA7 to LCD_DATA0 OUT_PHASE[1:0] = 2 LCD_DATA7 to LCD_DATA0 ... ... ... ... ... ... r g b r g b r g b r g b ... ... ... ... ... ... ... r g b r g b r g b r g ... ... ... ... ... ... ... ... r g b r g b r g b r Figure 36.7 Timing of Clock Phases of Serial RGB Output (Triple Speed Mode) Figure 36.8 shows the timing of the clock phases of the serial RGB output (quadruple speed mode). Pixel clock LCD_CLK HE OUT_PHASE[1:0] = 0 LCD_DATA7 to LCD_DATA0 OUT_PHASE[1:0] = 1 LCD_DATA7 to LCD_DATA0 OUT_PHASE[1:0] = 2 LCD_DATA7 to LCD_DATA0 OUT_PHASE[1:0] = 3 LCD_DATA7 to LCD_DATA0 ... ... ... ... ... ... ... ... r g b X r g b X r g b X r g b X ... ... ... ... ... ... ... ... ... r g b X r g b X r g b X r g b ... ... ... ... ... ... ... ... ... ... r g b X r g b X r g b X r g ... ... ... ... ... ... ... ... ... ... ... r g b X r g b X r g b X r Figure 36.8 Timing of Clock Phases of Serial RGB Output (Quadruple Speed Mode) Page 2216 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.12 Output Format Conversion Register Name Bit Name Initial Value Description OUT_SET OUT_FORMAT[1:0] 0 Output Format Select 0: RBG888 1: RGB666 2: RGB565 3: Serial RGB OUT_SET OUT_ENDIAN_ON 0 Bit Endian Change On/Off Control 0: Off 1: On OUT_SET OUT_SWAP_ON 0 B/R Signal Swap On/Off Control 0: Off 1: On OUT_SET OUT_FRQ_SEL[1:0] 0 Clock Frequency Control 0: 100% speed  (parallel RGB) 1: Triple speed  (serial RGB) 2: Quadruple speed  (serial RGB) 3: Setting prohibited OUT_SET OUT_DIR_SEL 0 Scan Direction Select 0: Forward scan 1: Reverse scan OUT_SET OUT_PHASE[1:0] 0 Clock Phase Adjustment for Serial RGB Output Triple speed mode 0: 0 (clk) 1: 1 (clk) 2: 2 (clk) 3: Setting prohibited Quadruple speed mode 0: 0 (clk) 1: 1 (clk) 2: 2 (clk) 3: 3 (clk) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2217 of 3092 Section 36 Video Display Controller 4 (6): Output Controller 36.1.9 SH7268 Group, SH7269 Group LCD TCON The LCD TCON generates various timing signals for driving the LCD panel. Specifically, the timing include two vertical panel driver signals, five horizontal panel driver signals, and one composite signal of the vertical and horizontal panel driver signals. Table 36.13 lists the timing signals that are generated by LCD TCON Table 36.13 Signals Generated by LCD TCON Signal Name Type Description STVA/VS Vertical  Gate start signal The pulse width, pulse position, and pulse polarity of the signal can be controlled.  Vsync signal The width, position, and polarity of the sync signal can be controlled.  Gate start signal The pulse width, pulse position, and pulse polarity of the signal can be controlled.  Vertical enable signal The width, position, and polarity of the sync signal can be controlled.  Source start signal The pulse width, pulse position, and pulse polarity of the signal can be controlled.  Hsync signal The width, position, and polarity of the sync signal can be controlled.  Source strobe signal The pulse width, pulse position, and pulse polarity of the signal can be controlled.  Horizontal enable signal The width, position, and polarity of the enable signal can be controlled. STVB/VE STH/SP/HS STB/LP/HE Page 2218 of 3092 Vertical Horizontal Horizontal R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Signal Name Type Description CPV/GCK Horizontal  Gate clock signal The pulse width, pulse position, and pulse polarity of the signal can be controlled. POLA Horizontal  VCOM voltage polarity control signal The polarity inversion position, and polarity inversion operation (1x1, 1x2, 2x2) can be controlled. POLB Horizontal  VCOM voltage polarity control signal The polarity inversion position, and polarity inversion operation (1x1, 1x2, 2x2) can be controlled. DE Horizontal/Ver  tical (1) Horizontal Reference Offset Control Data enable signal The width, position, and polarity of the enable signal can be controlled. The horizontal reference offset control enables generation of a reference signal with a clock delay equivalent to the value of TCON_OFFSET[10:0] from the rising edge of the Hsync signal. If a signal that spans across the Hsync signal needs to be generated, such a signal is generated with reference to the offset reference signal. Pixel clock Hsync signal H_INT (internal signal) CNT_HOFF (internal signal) TCON_OFFSET + 1 Figure 36.9 Generation of Offset Horizontal Reference (H_OFF) Signal R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2219 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.14 Horizontal Reference Signal Selection Initial Value Description TCON_OFFSET [10:0] 0 Offset Hsync Signal Timing TCON_STH_HS_ SEL 0 Signal Name Bit Name TCON_TIM TCON_TIM_STH2 Sets the clock cycle count from the rising edge of the Hsync signal. STH Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference TCON_TIM_STB2 TCON_STB_HS_ SEL 0 STB Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference TCON_TIM_CPV2 TCON_CPV_HS_ SEL 0 CPV Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference TCON_TIM_POLA2 TCON_POLA_HS_ SEL 0 POLA Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference TCON_TIM_POLB2 TCON_POLB_HS_ SEL 0 POLB Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference Note: When generating the POLA and POLB signals in reverse mode, the bits TCON_POLA_HS_SEL and TCON_POLB_HS_SEL should be set to 0. Page 2220 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 36 Video Display Controller 4 (6): Output Controller Horizontal Panel Driver Signal Generation (A) Horizontal synchronous panel driver signal generation (A) involves generation of a timing signal that changes twice in a horizontal period according to the values of TCON_xxxx_HS[10:0] and TCON_xxxx_HW[10:0] bits, which set the first changing timing and the second changing timing, respectively. The internal counter performs the following operations. 1. Resets the counter value at the rising edge of the Hsync signal as the reference. 2. Increments the counter value at the rising edge of the panel clock. A fixed output value of 0 can be obtained by setting 0 in TCON_xxxx_HW[10:0], which set the second changing timing. Pixel clock Hsync signal Normal mode TCON_xxxx_HS TCON_xxxx_HW Figure 36.10 Horizontal Panel Driver Signal (in Normal Mode) Pixel clock Hsync signal Timing signal not generated Normal mode TCON_xxxx_HS TCON_xxxx_HW = 0 Figure 36.11 Horizontal Panel Driver Signal (in Normal Mode and When TCON_xxxx_HW_ = 0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2221 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Pixel clock Hsync signal Timing signal generated beyond Hsync signal CNT_HOFF TCON_OFFSET + 1 Normal mode TCON_xxxx_HS TCON_xxxx_HW Figure 36.12 Horizontal Panel Driver Signal (in Normal Mode and When Offset Horizontal Reference is Used) Table 36.15 Settings for Horizontal Panel Driver Signal Generation (A) Register Name Bit Name TCON_TIM_STH1 TCON_STH_HS [10:0] Initial Value 0 Description STH Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STH_HS from the rising edge of the Hsync signal (clock cycles) TCON_TIM_STH1 TCON_TIM_STB1 TCON_STH_HW 96 [10:0] TCON_STB_HS [10:0] 144 STH Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STH_HW (clock cycles) STB Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STB_HS from the rising edge of the Hsync signal (clock cycles) TCON_TIM_STB1 TCON_TIM_CPV1 TCON_STB_HW [10:0] 640 TCON_CPV_HS [10:0] 0 STB Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STB_HW (clock cycles) CPV Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_CPV_HS from the rising edge of the Hsync signal (clock cycles) TCON_TIM_CPV1 Page 2222 of 3092 TCON_CPV_HW 0 [10:0] CPV Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_CPV_HW (clock cycles) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 36 Video Display Controller 4 (6): Output Controller Horizontal Panel Driver Signal Generation (B) In addition to the normal mode operation described in (2), reverse mode operation, that is, horizontal panel driver signal generation (B) is provided. In reverse mode, operation starts at the rising edge of the Vsync signal as the reference and a signal is generated such that its polarity is inverted every horizontal period in the timing set by the TCON_xxxx_HS[10:0] bits, which set the first changing timing. In reverse mode, regardless of whether the number of lines in the vertical direction is odd or even, the polarity of the signals generated is inverted every horizontal period. The following three reverse modes are selectable for polarity inversion operation. Table 36.16 Horizontal Panel Driver Signal Generation Modes Register Name Bit Name TCON_TIM_POLA2 TCON_POLA_MD [1:0] Initial Value 1 Description POLA Signal Generation Mode Select 0: Normal mode Generates the signal that changes twice a horizontal period. 1: 1 x 1 reverse mode Generates the signal whose polarity is inverted every horizontal period. 2: 1 x 2 reverse mode Generates the signal whose polarity is inverted in the first horizontal period and is subsequently inverted every two horizontal periods. 3: 2 x 2 reverse mode Generates the signal whose polarity is inverted every two horizontal periods. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2223 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Register Name Bit Name TCON_TIM_POLB2 TCON_POLB_MD [1:0] Initial Value Description 1 POLB Signal Generation Mode Select 0: Normal mode Generates the signal that changes twice a horizontal period. 1: 1 x 1 reverse mode Generates the signal whose polarity is inverted every horizontal period. 2: 1 x 2 reverse mode Generates the signal whose polarity is inverted in the first horizontal period and is subsequently inverted every two horizontal periods. 3: 2 x 2 reverse mode Generates the signal whose polarity is inverted every two horizontal periods. Vsync signal Hsync signal Reverse mode (1 X 1) (1) xxxx_HS (2) (3) (1) xxxx_HS xxxx_HS (2) (3) xxxx_HS Polarity inverted every vertical period Figure 36.13 Horizontal Panel Driver Signal (in 1  1 Reverse Mode) Vsync signal Hsync signal Reverse mode (1 X 2) (1) xxxx_HS (2) (3) xxxx_HS (1) xxxx_HS (2) (3) xxxx_HS Polarity inverted every vertical period Figure 36.14 Horizontal Panel Driver Signal (in 1  2 Reverse Mode) Page 2224 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Vsync signal Hsync signal Reverse mode (2 X 2) (1) xxxx_HS (2) xxxx_HS (3) (1) (2) xxxx_HS xxxx_HS Polarity inverted every vertical period Figure 36.15 Horizontal Panel Driver Signal (in 2  2 Reverse Mode) Table 36.17 Settings of Horizontal Panel Driver Signal Generation (B) Register Name Bit Name TCON_TIM_POLA1 TCON_POLA_HS [10:0] Initial Value 0 Description POLA Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_POLA_HS + 1 from the rising edge of the Hsync signal (clock cycles) Note: When 1 x 1, 1 x 2, or 2 x 2 reverse mode is selected, these bits should be set to 1 or greater. TCON_TIM_POLA1 TCON_POLA_HW [10:0] 0 POLA Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_POLA_HW (clock cycles) TCON_TIM_POLB1 TCON_POLB_HS [10:0] 0 POLBA Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_POLB_HS + 1 from the rising edge of the Hsync signal (clock cycles) Note: When 1 x 1, 1 x 2, or 2 x 2 reverse mode is selected, these bits should be set to1 or greater. TCON_TIM_POLB1 TCON_POLB_HW [10:0] 0 POLB Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_POLB_HW (clock cycles) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2225 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller (4) Vertical Panel Driver Signal Generation The vertical synchronous panel driver signal generation involves the following operations. 1. Initialization at the rising edge of the Vsync signal 2. Generation of a timing signal that changes twice in a vertical period according to the values of the internal counter, and TCON_xxxx_VS[10:0] and TCON_xxxx_VW[10:0] bits, which set the first changing timing and the second changing timing, respectively. The internal counter increments the counter value in the following two cases. 1. At the rising edge of the Hsync signal 2. At the point reached after a clock delay specified by the value of TCON_HALF[10:0] from the rising edge of the Hsync signal (normally, 1/2fH is set). fH = 858 Pixel clock Hsync signal H_INT (internal signal) H_HALF (internal signal) TCON_HALF = 429 When 1/2 horizontal period is set Figure 36.16 1/2 Pulse (H_HALF) Signal Generation Table 36.18 Settings of 1/2 Pulse (H_HALF) Signal Generation Register Name Bit Name Initial Value Description TCON_TIM 400 1/2fH Timing TCON_HALF[10:0] Specifies the clock count from the rising edge of the Hsync signal as the counting timing of horizontal counter Page 2226 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Vsync signal H_INT H_HALF STVA, STVB VS VW Figure 36.17 Vertical Panel Driver Signal (H_INT Reference Operation) Vsync signal H_INT H_HALF STVA, STVB VS VW Figure 36.18 Vertical Panel Driver Signal (H_HALF Reference Operation) Vsync signal H_INT H_HALF STVA, STVB VS VW = 1 Figure 36.19 Vertical Panel Driver Signal (H_INT and H_HALF Reference Operation) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2227 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.19 Vertical Panel Driver Signal Generation Register Name Bit Name TCON_TIM_STVA1 TCON_STVA_VS [10:0] Initial Value 0 Description STVA Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STVA_HS from the rising edge of the Vsync signal (1/2fH cycles) TCON_TIM_STVA1 TCON_STVA_VW [10:0] 4 STVA Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STVA_HW (1/2fH cycles) TCON_TIM_STVB1 TCON_STVB_VS 70 [10:0] STVB Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STVB_HS from the rising edge of the Vsync signal (1/2fH cycles) TCON_TIM_STVB1 TCON_STVB_VW [10:0] 960 STVB Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STVB_HW (1/2fH cycles) (5) DE Timing Signal Generation DE timing signal generation involves generation of data enable signal (DE) that indicates the valid period of the video signal by synthesizing the horizontal panel driver (HE) signal and the vertical panel driver (VE) signal (AND). Vsync signal Hsync signal VE HE DE Figure 36.20 Data Enable Signal Generation Page 2228 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 36 Video Display Controller 4 (6): Output Controller Polarity Inversion Polarity inversion enables inversion of polarity of each signal generated by the signal generating circuit. Table 36.20 Panel Driver Signal Polarity Inversion Control Register Name Bit Name Initial Value Description TCON_TIM_STVA2 TCON_STVA_INV 1 Polarity Inversion Control of STVA Signal 0: Not inverted 1: Inverted TCON_TIM_STVB2 TCON_STVB_INV 0 Polarity Inversion Control of STVB Signal 0: Not inverted 1: Inverted TCON_TIM_STH2 TCON_STH_INV 1 Polarity Inversion Control of STH Signal 0: Not inverted 1: Inverted TCON_TIM_STB2 TCON_STB_INV 0 Polarity Inversion Control of STB Signal 0: Not inverted 1: Inverted TCON_TIM_CPV2 TCON_CPV_INV 0 Polarity Inversion Control of CPV Signal 0: Not inverted 1: Inverted TCON_TIM_POLA2 TCON_POLA_INV 0 Polarity Inversion Control of POLA Signal 0: Not inverted 1: Inverted TCON_TIM_POLB2 TCON_POLB_INV 0 Polarity Inversion Control of POLB Signal 0: Not inverted 1: Inverted TCON_TIM_DE TCON_DE_INV 0 Polarity Inversion Control of DE Signal 0: Not inverted 1: Inverted R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2229 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller (7) Output Selection An output pin is selected for every signal subjected to polarity inversion control. Table 36.21 Panel Driver Signal Output Selection Register Name Bit Name TCON_TIM_STVA2 TCON_STVA_SEL [2:0] Initial Value Description 0 Output Signal Select for LCD_TCON0 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE TCON_TIM_STVB2 TCON_STVB_SEL [2:0] 1 Output Signal Select for LCD_TCON1 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE TCON_TIM_STH2 TCON_STH_SEL [2:0] 2 Output Signal Select for LCD_TCON2 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Page 2230 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Register Name Bit Name TCON_TIM_STB2 TCON_STB_SEL [2:0] Section 36 Video Display Controller 4 (6): Output Controller Initial Value Description 7 Output Signal Select for LCD_TCON3 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE TCON_TIM_CPV2 TCON_CPV_SEL [2:0] 4 Output Signal Select for LCD_TCON4 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE TCON_TIM_POLA2 TCON_POLA_SEL [2:0] 5 Output Signal Select for LCD_TCON5 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2231 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Register Name Bit Name TCON_TIM_POLB2 TCON_POLB_SEL [2:0] Initial Value Description 6 Output Signal Select for LCD_TCON6 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE (8) Output Phase Selection The output phase can be individually selected for the video output signal and the various timing output signals based on the LCD_CLK (panel clock). Table 36.22 Panel Output Signal Phase Selection Register Name Bit Name OUT_CLK_PHASE OUTCNT_LCD_ EDGE Initial Value 0 Description Output Phase Control of LCD_DATA23 to LCD_DATA0 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin OUT_CLK_PHASE OUTCNT_STVA_ EDGE 0 Output Phase Control of LCD_TCON0 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin OUT_CLK_PHASE OUTCNT_STVB_ EDGE 0 Output Phase Control of LCD_TCON1 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin OUT_CLK_PHASE OUTCNT_STH_ EDGE 0 Output Phase Control of LCD_TCON2 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin OUT_CLK_PHASE OUTCNT_STB_ EDGE 0 Output Phase Control of LCD_TCON3 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin Page 2232 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Register Name Bit Name OUT_CLK_PHASE OUTCNT_CPV_ EDGE Section 36 Video Display Controller 4 (6): Output Controller Initial Value Description 0 Output Phase Control of LCD_TCON4 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin OUT_CLK_PHASE OUTCNT_POLA_ EDGE 0 Output Phase Control of LCD_TCON5 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin OUT_CLK_PHASE OUTCNT_POLB_ EDGE 0 Output Phase Control of LCD_TCON6 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2233 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2 Register Descriptions Table 36.23 shows the register configuration.  Symbols used in Register Description: Initial value: Register value after a reset : Undefined value R/W: Readable/writable. The written value can be read. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored. R/WC1: Readable/writable. Writing 1 initializes the bit. Writing 0 is ignored. R: Read-only. The write value should always be 0. /W: Write-only. The read value is undefined. Table 36.23 Gamma Correction Block Register Configuration Initial Value Address Access Size GAM_G_UPDATE R/WC1 H'0000 0000 H'FFFF 7800 32/16 GAM_SW R/W H'0000 0000 H'FFFF 7804 32/16 Table setting register G1 in GAM_G_LUT1 gamma correction block R/W H'0400 0400 H'FFFF 7808 32/16 Table setting register G2 in GAM_G_LUT2 gamma correction block R/W H'0400 0400 H'FFFF 780C 32/16 Table setting register G3 in GAM_G_LUT3 gamma correction block R/W H’0400 0400 H'FFFF 7810 32/16 Table setting register G4 in GAM_G_LUT4 gamma correction block R/W H'0400 0400 H'FFFF 7814 32/16 Table setting register G5 in GAM_G_LUT5 gamma correction block R/W H'0400 0400 H'FFFF 7818 32/16 Table setting register G6 in GAM_G_LUT6 gamma correction block R/W H’0400 0400 H'FFFF 781C 32/16 Table setting register G7 in GAM_G_LUT7 gamma correction block R/W H'0400 0400 H'FFFF 7820 32/16 Table setting register G8 in GAM_G_LUT8 gamma correction block R/W H'0400 0400 H'FFFF 7824 32/16 Register Name Abbreviation Register update control register G in gamma correction block Function switch register in gamma correction block Page 2234 of 3092 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller R/W Initial Value Address Access Size Table setting register G9 in GAM_G_LUT9 gamma correction block R/W H'0400 0400 H'FFFF 7828 32/16 Table setting register G10 GAM_G_LUT10 in gamma correction block R/W H'0400 0400 H'FFFF 782C 32/16 Table setting register G11 GAM_G_LUT11 in gamma correction block R/W H'0400 0400 H'FFFF 7830 32/16 Table setting register G12 GAM_G_LUT12 in gamma correction block R/W H'0400 0400 H'FFFF 7834 32/16 Table setting register G13 GAM_G_LUT13 in gamma correction block R/W H’0400 0400 H'FFFF 7838 32/16 Table setting register G14 GAM_G_LUT14 in gamma correction block R/W H'0400 0400 H'FFFF 783C 32/16 Table setting register G15 GAM_G_LUT15 in gamma correction block R/W H'0400 0400 H'FFFF 7840 32/16 Table setting register G16 GAM_G_LUT16 in gamma correction block R/W H'0400 0400 H'FFFF 7844 32/16 Area setting register G1 in GAM_G_AREA1 gamma correction block R/W H'0008 1018 H'FFFF 7848 32/16 Area setting register G2 in GAM_G_AREA2 gamma correction block R/W H'2028 3038 H'FFFF 784C 32/16 Area setting register G3 in GAM_G_AREA3 gamma correction block R/W H'4048 5058 H'FFFF 7850 32/16 Area setting register G4 in GAM_G_AREA4 gamma correction block R/W H'6068 7078 H'FFFF 7854 32/16 Area setting register G5 in GAM_G_AREA5 gamma correction block R/W H'8088 9098 H'FFFF 7858 32/16 Area setting register G6 in GAM_G_AREA6 gamma correction block R/W H'A0A8 B0B8 H'FFFF 785C 32/16 Area setting register G7 in GAM_G_AREA7 gamma correction block R/W H'C0C8 D0D8 H'FFFF 7860 32/16 Area setting register G8 in GAM_G_AREA8 gamma correction block R/W H'E0E8 F0F8 H'FFFF 7864 32/16 H'0000 0000 H'FFFF 7880 32/16 H'0400 0400 H'FFFF 7888 32/16 Register Name Register update control register B in gamma correction block Abbreviation GAM_B_UPDATE R/WC1 Table setting register B1 in GAM_B_LUT1 gamma correction block R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R/W Page 2235 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Register Name Access Size R/W Initial Value Address Table setting register B2 in GAM_B_LUT2 gamma correction block R/W H'0400 0400 H'FFFF 788C 32/16 Table setting register B3 in GAM_B_LUT3 gamma correction block R/W H'0400 0400 H'FFFF 7890 32/16 Table setting register B4 in GAM_B_LUT4 gamma correction block R/W H'0400 0400 H'FFFF 7894 32/16 Table setting register B5 in GAM_B_LUT5 gamma correction block R/W H'0400 0400 H'FFFF 7898 32/16 Table setting register B6 in GAM_B_LUT6 gamma correction block R/W H'0400 0400 H'FFFF 789C 32/16 Table setting register B7 in GAM_B_LUT7 gamma correction block R/W H'0400 0400 H'FFFF 78A0 32/16 Table setting register B8 in GAM_B_LUT8 gamma correction block R/W H'0400 0400 H'FFFF 78A4 32/16 Table setting register B9 in GAM_B_LUT9 gamma correction block R/W H'0400 0400 H'FFFF 78A8 32/16 Table setting register B10 GAM_B_LUT10 in gamma correction block R/W H'0400 0400 H'FFFF 78AC 32/16 Table setting register B11 GAM_B_LUT11 in gamma correction block R/W H'0400 0400 H'FFFF 78B0 32/16 Table setting register B12 GAM_B_LUT12 in gamma correction block R/W H'0400 0400 H'FFFF 78B4 32/16 Table setting register B13 GAM_B_LUT13 in gamma correction block R/W H'0400 0400 H'FFFF 78B8 32/16 Table setting register B14 GAM_B_LUT14 in gamma correction block R/W H'0400 0400 H'FFFF 78BC 32/16 Table setting register B15 GAM_B_LUT15 in gamma correction block R/W H'0400 0400 H'FFFF 78C0 32/16 Table setting register B16 GAM_B_LUT16 in gamma correction block R/W H'0400 0400 H'FFFF 78C4 32/16 Area setting register B1 in gamma correction block GAM_B_AREA1 R/W H'0008 1018 H'FFFF 78C8 32/16 Area setting register B2 in gamma correction block GAM_B_AREA2 R/W H'2028 3038 H'FFFF 78CC 32/16 Area setting register B3 in gamma correction block GAM_B_AREA3 R/W H'4048 5058 H'FFFF 78D0 32/16 Page 2236 of 3092 Abbreviation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Access Size Register Name Abbreviation R/W Initial Value Address Area setting register B4 in gamma correction block GAM_B_AREA4 R/W H'6068 7078 H'FFFF 78D4 32/16 Area setting register B5 in gamma correction block GAM_B_AREA5 R/W H'8088 9098 H'FFFF 78D8 32/16 Area setting register B6 in gamma correction block GAM_B_AREA6 R/W H'A0A8 B0B8 H'FFFF 78DC 32/16 Area setting register B7 in gamma correction block GAM_B_AREA7 R/W H'C0C8 D0D8 H'FFFF 78E0 32/16 Area setting register B8 in gamma correction block GAM_B_AREA8 R/W H'E0E8 F0F8 H'FFFF 78E4 32/16 Register update control register R in gamma correction block GAM_R_UPDATE R/WC1 H'0000 0000 H'FFFF 7900 32/16 32/16 Table setting register R1 in GAM_R_LUT1 gamma correction block R/W H'0400 0400 H'FFFF 7908 Table setting register R2 in GAM_R_LUT2 gamma correction block R/W H'0400 0400 H'FFFF 790C 32/16 Table setting register R3 in GAM_R_LUT3 gamma correction block R/W H'0400 0400 H'FFFF 7910 32/16 Table setting register R4 in GAM_R_LUT4 gamma correction block R/W H'0400 0400 H'FFFF 7914 32/16 Table setting register R5 in GAM_R_LUT5 gamma correction block R/W H'0400 0400 H'FFFF 7918 32/16 Table setting register R6 in GAM_R_LUT6 gamma correction block R/W H'0400 0400 H'FFFF 791C 32/16 Table setting register R7 in GAM_R_LUT7 gamma correction block R/W H'0400 0400 H'FFFF 7920 32/16 Table setting register R8 in GAM_R_LUT8 gamma correction block R/W H'0400 0400 H'FFFF 7924 32/16 Table setting register R9 in GAM_R_LUT9 gamma correction block R/W H'0400 0400 H'FFFF 7928 32/16 Table setting register R10 GAM_R_LUT10 in gamma correction block R/W H'0400 0400 H'FFFF 792C 32/16 Table setting register R11 GAM_R_LUT11 in gamma correction block R/W H'0400 0400 H'FFFF 7930 32/16 Table setting register R12 GAM_R_LUT12 in gamma correction block R/W H'0400 0400 H'FFFF 7934 32/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2237 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller R/W Initial Value Address Access Size Table setting register R13 GAM_R_LUT13 in gamma correction block R/W H'0400 0400 H'FFFF 7938 32/16 Table setting register R14 GAM_R_LUT14 in gamma correction block R/W H'0400 0400 H'FFFF 793C 32/16 Table setting register R15 GAM_R_LUT15 in gamma correction block R/W H'0400 0400 H'FFFF 7940 32/16 Table setting register R16 GAM_R_LUT16 in gamma correction block R/W H'0400 0400 H'FFFF 7944 32/16 Area setting register R1 in gamma correction block GAM_R_AREA1 R/W H'0008 1018 H'FFFF 7948 32/16 Area setting register R2 in gamma correction block GAM_R_AREA2 R/W H'2028 3038 H'FFFF 794C 32/16 Area setting register R3 in gamma correction block GAM_R_AREA3 R/W H'4048 5058 H'FFFF 7950 32/16 Area setting register R4 in gamma correction block GAM_R_AREA4 R/W H'6068 7078 H'FFFF 7954 32/16 Area setting register R5 in gamma correction block GAM_R_AREA5 R/W H'8088 9098 H'FFFF 7958 32/16 Area setting register R6 in gamma correction block GAM_R_AREA6 R/W H'A0A8 B0B8 H'FFFF 795C 32/16 Area setting register R7 in gamma correction block GAM_R_AREA7 R/W H'C0C8 D0D8 H'FFFF 7960 32/16 Area setting register R8 in gamma correction block GAM_R_AREA8 R/W H'E0E8 F0F8 H'FFFF 7964 32/16 Register Name Page 2238 of 3092 Abbreviation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.24 TCON Block Register Configuration R/W Initial Value Address Access Size TCON register update TCON_UPDATE control register R/WC1 H'0000 0000 H'FFFF 7980 32/16 TCON reference timing setting register TCON_TIM R/W H'0190 0000 H'FFFF 7984 32/16 TCON vertical timing setting register A1 TCON_TIM_STVA1 R/W H'0000 0004 H'FFFF 7988 32/16 TCON vertical timing setting register A2 TCON_TIM_STVA2 R/W H'0000 0010 H'FFFF 798C 32/16 TCON vertical timing setting register B1 TCON_TIM_STVB1 R/W H'0046 03C0 H'FFFF 7990 32/16 TCON vertical timing setting register B2 TCON_TIM_STVB2 R/W H’0000 0001 H'FFFF 7994 32/16 TCON horizontal timing setting register STH1 TCON_TIM_STH1 R/W H'0000 0060 H'FFFF 7998 32/16 TCON horizontal timing setting register STH2 TCON_TIM_STH2 R/W H'0000 0012 H'FFFF 799C 32/16 TCON horizontal timing setting register STB1 TCON_TIM_STB1 R/W H'0090 0280 H'FFFF 79A0 32/16 TCON horizontal timing setting register STB2 TCON_TIM_STB2 R/W H'0000 0007 H'FFFF 79A4 32/16 TCON horizontal timing setting register CPV1 TCON_TIM_CPV1 R/W H’0000 0000 H'FFFF 79A8 32/16 TCON horizontal timing setting register CPV2 TCON_TIM_CPV2 R/W H’0000 0004 H'FFFF 79AC 32/16 TCON horizontal timing setting register POLA1 TCON_TIM_POLA1 R/W H’0000 0000 H'FFFF 79B0 32/16 TCON horizontal timing setting register POLA2 TCON_TIM_POLA2 R/W H’0000 1005 H'FFFF 79B4 32/16 Register Name Abbreviation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2239 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Register Name Abbreviation R/W Initial Value Address Access Size TCON horizontal timing setting register POLB1 TCON_TIM_POLB1 R/W H’0000 0000 H'FFFF 79B8 32/16 TCON horizontal timing setting register POLB2 TCON_TIM_POLB2 R/W H’0000 1006 H'FFFF 79BC 32/16 R/W H’0000 0000 H'FFFF 79C0 32/16 TCON data enable TCON_TIM_DE polarity setting register Table 36.25 Output Controller Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Register update control register in output controller OUT_UPDATE R/WC1 H'0000 0000 H'FFFF 7A00 32/16 Output interface register OUT_SET R/W H'001F 0000 H'FFFF 7A04 32/16 Brightness (DC) correction register 1 OUT_BRIGHT1 R/W H’0000 0200 H'FFFF 7A08 32/16 Brightness (DC) correction register 2 OUT_BRIGHT2 R/W H’0200 0200 H'FFFF 7A0C 32/16 Contrast (gain) correction register OUT_CONTRAST R/W H’0080 8080 H'FFFF 7A10 32/16 Panel dither register OUT_PDTHA R/W H’0000 3021 H'FFFF 7A14 32/16 Output phase control register OUT_CLK_PHASE R/W H’0000 0000 H'FFFF 7A24 32/16 Page 2240 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.2.1 Section 36 Video Display Controller 4 (6): Output Controller Register Update Control Register G in Gamma Correction Block (GAM_G_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GAM_ G_VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GAM_G_VEN 0 R/WC1 Gamma Correction (G) Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2241 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.2 Function Switch Register in Gamma Correction Block (GAM_SW) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GAM_ ON Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GAM_ON 0 R/W Gamma Correction On/Off Control 0: Off 1: On Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. Page 2242 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.2.3 Section 36 Video Display Controller 4 (6): Output Controller Table Setting Register G1 to G16 in Gamma Correction Block (GAM_G_LUT1 to GAM_G_LUT16) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 23 22 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - GAM_G_GAIN_xx[10:0] - GAM_G_GAIN_yy[10:0] - 16 Initial value: 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 * 1024 R/W GAM_G_LUT1: Gain Adjustment of Area 0 of G Signal GAM_G_LUT2: Gain Adjustment of Area 2 of G Signal GAM_G_LUT3: Gain Adjustment of Area 4 of G Signal GAM_G_LUT4: Gain Adjustment of Area 6 of G Signal GAM_G_LUT5: Gain Adjustment of Area 8 of G Signal GAM_G_LUT6: Gain Adjustment of Area 10 of G Signal GAM_G_LUT7: Gain Adjustment of Area 12 of G Signal GAM_G_LUT8: Gain Adjustment of Area 14 of G Signal GAM_G_LUT9: Gain Adjustment of Area 16 of G Signal GAM_G_LUT10: Gain Adjustment of Area 18 of G Signal GAM_G_LUT11: Gain Adjustment of Area 20 of G Signal GAM_G_LUT12: Gain Adjustment of Area 22 of G Signal GAM_G_LUT13: Gain Adjustment of Area 24 of G Signal GAM_G_LUT14: Gain Adjustment of Area 26 of G Signal GAM_G_LUT15: Gain Adjustment of Area 28 of G Signal GAM_G_LUT16: Gain Adjustment of Area 30 of G Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2243 of 3092 Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name 26 to 16 * Initial Value R/W Description 1024 R/W *: Bit Name SH7268 Group, SH7269 Group GAM_G_LUT1: GAM_G_GAIN_00[10:0] GAM_G_LUT2: GAM_G_GAIN_02[10:0] GAM_G_LUT3: GAM_G_GAIN_04[10:0] GAM_G_LUT4: GAM_G_GAIN_06[10:0] GAM_G_LUT5: GAM_G_GAIN_08[10:0] GAM_G_LUT6: GAM_G_GAIN_10[10:0] GAM_G_LUT7: GAM_G_GAIN_12[10:0] GAM_G_LUT8: GAM_G_GAIN_14[10:0] GAM_G_LUT9: GAM_G_GAIN_16[10:0] GAM_G_LUT10: GAM_G_GAIN_18[10:0] GAM_G_LUT11: GAM_G_GAIN_20[10:0] GAM_G_LUT12: GAM_G_GAIN_22[10:0] GAM_G_LUT13: GAM_G_GAIN_24[10:0] GAM_G_LUT14: GAM_G_GAIN_26[10:0] GAM_G_LUT15: GAM_G_GAIN_28[10:0] GAM_G_LUT16: GAM_G_GAIN_30[10:0] 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 * 1024 R/W GAM_G_LUT1: Gain Adjustment of Area 1 of G Signal GAM_G_LUT2: Gain Adjustment of Area 3 of G Signal GAM_G_LUT3: Gain Adjustment of Area 5 of G Signal GAM_G_LUT4: Gain Adjustment of Area 7 of G Signal GAM_G_LUT5: Gain Adjustment of Area 9 of G Signal GAM_G_LUT6: Gain Adjustment of Area 11 of G Signal GAM_G_LUT7: Gain Adjustment of Area 13 of G Signal GAM_G_LUT8: Gain Adjustment of Area 15 of G Signal GAM_G_LUT9: Gain Adjustment of Area 17 of G Signal GAM_G_LUT10: Gain Adjustment of Area 19 of G Signal Page 2244 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name Initial Value R/W Description 10 to 0 * 1024 R/W GAM_G_LUT11: Gain Adjustment of Area 21 of G Signal GAM_G_LUT12: Gain Adjustment of Area 23 of G Signal GAM_G_LUT13: Gain Adjustment of Area 25 of G Signal GAM_G_LUT14: Gain Adjustment of Area 27 of G Signal GAM_G_LUT15: Gain Adjustment of Area 29 of G Signal GAM_G_LUT16: Gain Adjustment of Area 31 of G Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) *: Bit Name GAM_G_LUT1: GAM_G_GAIN_01[10:0] GAM_G_LUT2: GAM_G_GAIN_03[10:0] GAM_G_LUT3: GAM_G_GAIN_05[10:0] GAM_G_LUT4: GAM_G_GAIN_07[10:0] GAM_G_LUT5: GAM_G_GAIN_09[10:0] GAM_G_LUT6: GAM_G_GAIN_11[10:0] GAM_G_LUT7: GAM_G_GAIN_13[10:0] GAM_G_LUT8: GAM_G_GAIN_15[10:0] GAM_G_LUT9: GAM_G_GAIN_17[10:0] GAM_G_LUT10: GAM_G_GAIN_19[10:0] GAM_G_LUT11: GAM_G_GAIN_21[10:0] GAM_G_LUT12: GAM_G_GAIN_23[10:0] GAM_G_LUT13: GAM_G_GAIN_25[10:0] GAM_G_LUT14: GAM_G_GAIN_27[10:0] GAM_G_LUT15: GAM_G_GAIN_29[10:0] GAM_G_LUT16: GAM_G_GAIN_31[10:0] Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2245 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.4 Area Setting Register G1 in Gamma Correction Block (GAM_G_AREA1) 31 30 29 28 27 26 25 24         Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R Bit: 15 14 13 12 11 10 Bit: Initial value: 0 R/W: R/W Bit 22 21 20 19 18 17 16 - - GAM_G_TH_01[7:0] - - - 0 0 0 0 1 0 0 0 R R/W R/W R/W R/W R/W R/W R/W R/W 9 8 7 6 5 4 3 2 1 0 - - - -GAM_G_TH_03[7:0] - - - 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 24  -GAM_G_TH_02[7:0] - 23 Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 GAM_G_TH_01 8 [7:0] R/W Start Threshold of Area 1 of G Signal Unsigned (0 to 255 [LSB]) 0 < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_02 16 [7:0] R/W Start Threshold of Area 2 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_03 24 [7:0] R/W Start Threshold of Area 3 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. Page 2246 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.2.5 Section 36 Video Display Controller 4 (6): Output Controller Area Setting Register G2 in Gamma Correction Block (GAM_G_AREA2) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 25 24 - -GAM_G_TH_04[7:0] - - - 0 1 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 14 13 12 11 10 - - GAM_G_TH_06[7:0] - 28 27 26 22 21 17 16 - - GAM_G_TH_05[7:0] - - - 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 9 8 7 6 5 4 3 2 - - - - GAM_G_TH_07[7:0] - 23 20 19 18 1 0 - - 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 32 04[7:0] R/W Description R/W Start Threshold of Area 4 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 40 05[7:0] R/W Start Threshold of Area 5 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 48 06[7:0] R/W Start Threshold of Area 6 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 56 07[7:0] R/W Start Threshold of Area 7 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2247 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.6 Area Setting Register G3 in Gamma Correction Block (GAM_G_AREA3) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - -GAM_G_TH_08[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_G_TH_09[7:0] - 20 19 18 17 16 - - 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_G_TH_10[7:0] - - - - - GAM_G_TH_11[7:0] - 1 0 - - 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 64 08[7:0] R/W R/W Description Start Threshold of Area 8 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 72 09[7:0] R/W Start Threshold of Area 9 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 80 10[7:0] R/W Start Threshold of Area 10 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 88 11[7:0] R/W Start Threshold of Area 11 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. Page 2248 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.2.7 Section 36 Video Display Controller 4 (6): Output Controller Area Setting Register G4 in Gamma Correction Block (GAM_G_AREA4) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - -GAM_G_TH_12[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_G_TH_13[7:0] - 20 19 18 17 16 - - 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_G_TH_14[7:0] - - - - - GAM_G_TH_15[7:0] - 1 0 - - 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 96 12[7:0] R/W Description R/W Start Threshold of Area 12 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 104 13[7:0] R/W Start Threshold of Area 13 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 112 14[7:0] R/W Start Threshold of Area 14 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 120 15[7:0] R/W Start Threshold of Area 15 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2249 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.8 Area Setting Register G5 in Gamma Correction Block (GAM_G_AREA5) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - -GAM_G_TH_16[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_G_TH_17[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_G_TH_18[7:0] - - - - - GAM_G_TH_19[7:0] - 1 0 - - 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 128 16[7:0] R/W Description R/W Start Threshold of Area 16 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 136 17[7:0] R/W Start Threshold of Area 17 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 144 18[7:0] R/W Start Threshold of Area 18 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 152 19[7:0] R/W Start Threshold of Area 19 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. Page 2250 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 36.2.9 Section 36 Video Display Controller 4 (6): Output Controller Area Setting Register G6 in Gamma Correction Block (GAM_G_AREA6) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - -GAM_G_TH_20[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_G_TH_21[7:0] - 20 19 18 17 16 - - 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_G_TH_22[7:0] - - - - - GAM_G_TH_23[7:0] - 1 0 - - 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 160 20[7:0] R/W Description R/W Start Threshold of Area 20 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 168 21[7:0] R/W Start Threshold of Area 21 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 176 22[7:0] R/W Start Threshold of Area 22 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 184 23[7:0] R/W Start Threshold of Area 23 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2251 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.10 Area Setting Register G7 in Gamma Correction Block (GAM_G_AREA7) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - -GAM_G_TH_24[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_G_TH_25[7:0] - 20 19 18 17 16 - - 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_G_TH_26[7:0] - - - - - GAM_G_TH_27[7:0] - 1 0 - - 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 192 24[7:0] R/W Description R/W Start Threshold of Area 24 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 200 25[7:0] R/W Start Threshold of Area 25 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 208 26[7:0] R/W Start Threshold of Area 26 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 216 27[7:0] R/W Start Threshold of Area 27 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. Page 2252 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.11 Area Setting Register G8 in Gamma Correction Block (GAM_G_AREA8) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - -GAM_G_TH_28[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_G_TH_29[7:0] - 20 19 18 17 16 - - 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_G_TH_30[7:0] - - - - - GAM_G_TH_31[7:0] - 1 0 - - 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_G_TH_ 224 28[7:0] R/W Description R/W Start Threshold of Area 28 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_G_TH_ 232 29[7:0] R/W Start Threshold of Area 29 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_G_TH_ 240 30[7:0] R/W Start Threshold of Area 30 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_G_TH_ 248 31[7:0] R/W Start Threshold of Area 31 of G Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area  255 Note: This register is updated when GAM_G_VEN in GAM_G_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2253 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.12 Register Update Control Register B in Gamma Correction Block (GAM_B_UPDATE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GAM_B _VEN Bit: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GAM_B_VEN 0 R/WC1 Gamma Correction (B) Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2254 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.13 Table Setting Register B1 to B16 in Gamma Correction Block (GAM_B_LUT1 to GAM_B_LUT16) Bit: 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Initial value: 0 0 0 0 0 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit Initial Bit Name Value 31 to 27  All 0 R/W Description R Reserved 23 22 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W 21 20 GAM_B_GAIN_xx[10:0] - GAM_B_GAIN_yy[10:0] - 16 These bits are always read as 0. The write value should always be 0. 26 to 16 * 1024 R/W GAM_B_LUT1: Gain Adjustment of Area 0 of B Signal GAM_B_LUT2: Gain Adjustment of Area 2 of B Signal GAM_B_LUT3: Gain Adjustment of Area 4 of B Signal GAM_B_LUT4: Gain Adjustment of Area 6 of B Signal GAM_B_LUT5: Gain Adjustment of Area 8 of B Signal GAM_B_LUT6: Gain Adjustment of Area 10 of B Signal GAM_B_LUT7: Gain Adjustment of Area 12 of B Signal GAM_B_LUT8: Gain Adjustment of Area 14 of B Signal GAM_B_LUT9: Gain Adjustment of Area 16 of B Signal GAM_B_LUT10: Gain Adjustment of Area 18 of B Signal GAM_B_LUT11: Gain Adjustment of Area 20 of B Signal GAM_B_LUT12: Gain Adjustment of Area 22 of B Signal GAM_B_LUT13: Gain Adjustment of Area 24 of B Signal GAM_B_LUT14: Gain Adjustment of Area 26 of B Signal GAM_B_LUT15: Gain Adjustment of Area 28 of B Signal GAM_B_LUT16: Gain Adjustment of Area 30 of B Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2255 of 3092 Section 36 Video Display Controller 4 (6): Output Controller Bit Initial Bit Name Value 26 to 16 * 1024 R/W Description R/W *: Bit Name SH7268 Group, SH7269 Group GAM_B_LUT1: GAM_B_GAIN_00[10:0] GAM_B_LUT2: GAM_B_GAIN_02[10:0] GAM_B_LUT3: GAM_B_GAIN_04[10:0] GAM_B_LUT4: GAM_B_GAIN_06[10:0] GAM_B_LUT5: GAM_B_GAIN_08[10:0] GAM_B_LUT6: GAM_B_GAIN_10[10:0] GAM_B_LUT7: GAM_B_GAIN_12[10:0] GAM_B_LUT8: GAM_B_GAIN_14[10:0] GAM_B_LUT9: GAM_B_GAIN_16[10:0] GAM_B_LUT10: GAM_B_GAIN_18[10:0] GAM_B_LUT11: GAM_B_GAIN_20[10:0] GAM_B_LUT12: GAM_B_GAIN_22[10:0] GAM_B_LUT13: GAM_B_GAIN_24[10:0] GAM_B_LUT14: GAM_B_GAIN_26[10:0] GAM_B_LUT15: GAM_B_GAIN_28[10:0] GAM_B_LUT16: GAM_B_GAIN_30[10:0] 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 * 1024 R/W GAM_B_LUT1: Gain Adjustment of Area 1 of B Signal GAM_B_LUT2: Gain Adjustment of Area 3 of B Signal GAM_B_LUT3: Gain Adjustment of Area 5 of B Signal GAM_B_LUT4: Gain Adjustment of Area 7 of B Signal GAM_B_LUT5: Gain Adjustment of Area 9 of B Signal GAM_B_LUT6: Gain Adjustment of Area 11 of B Signal GAM_B_LUT7: Gain Adjustment of Area 13 of B Signal GAM_B_LUT8: Gain Adjustment of Area 15 of B Signal GAM_B_LUT9: Gain Adjustment of Area 17 of B Signal GAM_B_LUT10: Gain Adjustment of Area 19 of B Signal Page 2256 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Initial Bit Name Value R/W Description 10 to 0 * R/W GAM_B_LUT11: Gain Adjustment of Area 21 of B Signal 1024 GAM_B_LUT12: Gain Adjustment of Area 23 of B Signal GAM_B_LUT13: Gain Adjustment of Area 25 of B Signal GAM_B_LUT14: Gain Adjustment of Area 27 of B Signal GAM_B_LUT15: Gain Adjustment of Area 29 of B Signal GAM_B_LUT16: Gain Adjustment of Area 31 of B Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) *: Bit Name GAM_B_LUT1: GAM_B_GAIN_01[10:0] GAM_B_LUT2: GAM_B_GAIN_03[10:0] GAM_B_LUT3: GAM_B_GAIN_05[10:0] GAM_B_LUT4: GAM_B_GAIN_07[10:0] GAM_B_LUT5: GAM_B_GAIN_09[10:0] GAM_B_LUT6: GAM_B_GAIN_11[10:0] GAM_B_LUT7: GAM_B_GAIN_13[10:0] GAM_B_LUT8: GAM_B_GAIN_15[10:0] GAM_B_LUT9: GAM_B_GAIN_17[10:0] GAM_B_LUT10: GAM_B_GAIN_19[10:0] GAM_B_LUT11: GAM_B_GAIN_21[10:0] GAM_B_LUT12: GAM_B_GAIN_23[10:0] GAM_B_LUT13: GAM_B_GAIN_25[10:0] GAM_B_LUT14: GAM_B_GAIN_27[10:0] GAM_B_LUT15: GAM_B_GAIN_29[10:0] GAM_B_LUT16: GAM_B_GAIN_31[10:0] Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2257 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.14 Area Setting Register B1 in Gamma Correction Block (GAM_B_AREA1) Bit: 31 30 29 28 27 26 25 24         23 22 - 21 20 19 18 - GAM_B_TH_01[7:0] - 17 16 - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - GAM_B_TH_03[7:0] - - - Initial value: 0 R/W: R/W Bit 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 24  - GAM_B_TH_02[7:0] - Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 GAM_B_TH_01 8 [7:0] R/W Start Threshold of Area 1 of B Signal Unsigned (0 to 255 [LSB]) 0 < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_02 16 [7:0] R/W Start Threshold of Area 2 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_03 24 [7:0] R/W Start Threshold of Area 3 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. Page 2258 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.15 Area Setting Register B2 in Gamma Correction Block (GAM_B_AREA2) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - - GAM_B_TH_04[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_B_TH_05[7:0] - 20 19 18 17 16 - - 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_06[7:0] - - - - - GAM_B_TH_07[7:0] - 1 0 - - 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_04 32 [7:0] R/W Description R/W Start Threshold of Area 4 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_05 40 [7:0] R/W Start Threshold of Area 5 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_06 48 [7:0] R/W Start Threshold of Area 6 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_07 56 [7:0] R/W Start Threshold of Area 7 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2259 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.16 Area Setting Register B3 in Gamma Correction Block (GAM_B_AREA3) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - - GAM_B_TH_08[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_B_TH_09[7:0] - 20 19 18 17 16 - - 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_10[7:0] - - - - - GAM_B_TH_11[7:0] - 1 0 - - 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_08 64 [7:0] R/W R/W Description Start Threshold of Area 8 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_09 72 [7:0] R/W Start Threshold of Area 9 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_10 80 [7:0] R/W Start Threshold of Area 10 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_11 88 [7:0] R/W Start Threshold of Area 11 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. Page 2260 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.17 Area Setting Register B4 in Gamma Correction Block (GAM_B_AREA4) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - - GAM_B_TH_12[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_B_TH_13[7:0] - 20 19 18 17 16 - - 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_14[7:0] - - - - - GAM_B_TH_15[7:0] - 1 0 - - 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_12 96 [7:0] R/W Description R/W Start Threshold of Area 12 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_13 104 [7:0] R/W Start Threshold of Area 13 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_14 112 [7:0] R/W Start Threshold of Area 14 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_15 120 [7:0] R/W Start Threshold of Area 15 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2261 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.18 Area Setting Register B5 in Gamma Correction Block (GAM_B_AREA5) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - - GAM_B_TH_16[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_B_TH_17[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_18[7:0] - - - - - GAM_B_TH_19[7:0] - 1 0 - - 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_16 128 [7:0] R/W R/W Description Start Threshold of Area 16 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_17 136 [7:0] R/W Start Threshold of Area 17 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_18 144 [7:0] R/W Start Threshold of Area 18 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_19 152 [7:0] R/W Start Threshold of Area 19 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. Page 2262 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.19 Area Setting Register B6 in Gamma Correction Block (GAM_B_AREA6) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - - GAM_B_TH_20[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_B_TH_21[7:0] - 20 19 18 17 16 - - 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_22[7:0] - - - - - GAM_B_TH_23[7:0] - 1 0 - - 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_20 160 [7:0] R/W R/W Description Start Threshold of Area 20 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_21 168 [7:0] R/W Start Threshold of Area 21 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_22 176 [7:0] R/W Start Threshold of Area 22 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_23 184 [7:0] R/W Start Threshold of Area 23 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2263 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.20 Area Setting Register B7 in Gamma Correction Block (GAM_B_AREA7) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 27 28 26 30 29 - - GAM_B_TH_24[7:0] - 25 24 - - 23 19 20 18 22 21 - - GAM_B_TH_25[7:0] - 17 16 - - 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_26[7:0] - - - - - GAM_B_TH_27[7:0] - 1 0 - - 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_24 192 [7:0] R/W R/W Description Start Threshold of Area 24 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_25 200 [7:0] R/W Start Threshold of Area 25 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_26 208 [7:0] R/W Start Threshold of Area 26 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_27 216 [7:0] R/W Start Threshold of Area 27 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. Page 2264 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.21 Area Setting Register B8 in Gamma Correction Block (GAM_B_AREA8) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - - GAM_B_TH_28[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_B_TH_29[7:0] - 20 19 18 17 16 - - 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_B_TH_30[7:0] - - - - - GAM_B_TH_31[7:0] - 1 0 - - 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_B_TH_28 224 [7:0] R/W R/W Description Start Threshold of Area 28 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_B_TH_29 232 [7:0] R/W Start Threshold of Area 29 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_B_TH_30 240 [7:0] R/W Start Threshold of Area 30 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_B_TH_31 248 [7:0] R/W Start Threshold of Area 31 of B Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area  255 Note: This register is updated when GAM_B_VEN in GAM_B_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2265 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.22 Register Update Control Register R in Gamma Correction Block (GAM_R_UPDATE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                GAM_R _VEN Bit: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GAM_R_VEN 0 R/WC1 Gamma Correction (R) Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2266 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.23 Table Setting Register R1 to R16 in Gamma Correction Block (GAM_R_LUT1 to GAM_R_LUT16) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Initial value: 0 0 0 0 0 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W Bit: Bit Bit Name 31 to 27  Initial Value R/W Description All 0 Reserved R 22 23 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W GAM_R_GAIN_xx[10:0] - GAM_R_GAIN_yy[10:0] - 16 These bits are always read as 0. The write value should always be 0. 26 to 16 * 1024 R/W GAM_R_LUT1: Gain Adjustment of Area 0 of R Signal GAM_R_LUT2: Gain Adjustment of Area 2 of R Signal GAM_R_LUT3: Gain Adjustment of Area 4 of R Signal GAM_R_LUT4: Gain Adjustment of Area 6 of R Signal GAM_R_LUT5: Gain Adjustment of Area 8 of R Signal GAM_R_LUT6: Gain Adjustment of Area 10 of R Signal GAM_R_LUT7: Gain Adjustment of Area 12 of R Signal GAM_R_LUT8: Gain Adjustment of Area 14 of R Signal GAM_R_LUT9: Gain Adjustment of Area 16 of R Signal GAM_R_LUT10: Gain Adjustment of Area 18 of R Signal GAM_R_LUT11: Gain Adjustment of Area 20 of R Signal GAM_R_LUT12: Gain Adjustment of Area 22 of R Signal GAM_R_LUT13: Gain Adjustment of Area 24 of R Signal GAM_R_LUT14: Gain Adjustment of Area 26 of R Signal GAM_R_LUT15: Gain Adjustment of Area 28 of R Signal GAM_R_LUT16: Gain Adjustment of Area 30 of R Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2267 of 3092 Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name 26 to 16 * Initial Value R/W Description 1024 *: Bit Name R/W SH7268 Group, SH7269 Group GAM_R_LUT1: GAM_R_GAIN_00[10:0] GAM_R_LUT2: GAM_R_GAIN_02[10:0] GAM_R_LUT3: GAM_R_GAIN_04[10:0] GAM_R_LUT4: GAM_R_GAIN_06[10:0] GAM_R_LUT5: GAM_R_GAIN_08[10:0] GAM_R_LUT6: GAM_R_GAIN_10[10:0] GAM_R_LUT7: GAM_R_GAIN_12[10:0] GAM_R_LUT8: GAM_R_GAIN_14[10:0] GAM_R_LUT9: GAM_R_GAIN_16[10:0] GAM_R_LUT10: GAM_R_GAIN_18[10:0] GAM_R_LUT11: GAM_R_GAIN_20[10:0] GAM_R_LUT12: GAM_R_GAIN_22[10:0] GAM_R_LUT13: GAM_R_GAIN_24[10:0] GAM_R_LUT14: GAM_R_GAIN_26[10:0] GAM_R_LUT15: GAM_R_GAIN_28[10:0] GAM_R_LUT16: GAM_R_GAIN_30[10:0] 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 * 1024 R/W GAM_R_LUT1: Gain Adjustment of Area 1 of R Signal GAM_R_LUT2: Gain Adjustment of Area 3 of R Signal GAM_R_LUT3: Gain Adjustment of Area 5 of R Signal GAM_R_LUT4: Gain Adjustment of Area 7 of R Signal GAM_R_LUT5: Gain Adjustment of Area 9 of R Signal GAM_R_LUT6: Gain Adjustment of Area 11 of R Signal GAM_R_LUT7: Gain Adjustment of Area 13 of R Signal GAM_R_LUT8: Gain Adjustment of Area 15 of R Signal GAM_R_LUT9: Gain Adjustment of Area 17 of R Signal GAM_R_LUT10: Gain Adjustment of Area 19 of R Signal Page 2268 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name Initial Value R/W Description 10 to 0 * 1024 GAM_R_LUT11: Gain Adjustment of Area 21 of R Signal R/W GAM_R_LUT12: Gain Adjustment of Area 23 of R Signal GAM_R_LUT13: Gain Adjustment of Area 25 of R Signal GAM_R_LUT14: Gain Adjustment of Area 27 of R Signal GAM_R_LUT15: Gain Adjustment of Area 29 of R Signal GAM_R_LUT16: Gain Adjustment of Area 31 of R Signal Unsigned (0 to 2047 [LSB], 1024 [LSB] = 1.0 [times]) *: Bit Name GAM_R_LUT1: GAM_R_GAIN_01[10:0] GAM_R_LUT2: GAM_R_GAIN_03[10:0] GAM_R_LUT3: GAM_R_GAIN_05[10:0] GAM_R_LUT4: GAM_R_GAIN_07[10:0] GAM_R_LUT5: GAM_R_GAIN_09[10:0] GAM_R_LUT6: GAM_R_GAIN_11[10:0] GAM_R_LUT7: GAM_R_GAIN_13[10:0] GAM_R_LUT8: GAM_R_GAIN_15[10:0] GAM_R_LUT9: GAM_R_GAIN_17[10:0] GAM_R_LUT10: GAM_R_GAIN_19[10:0] GAM_R_LUT11: GAM_R_GAIN_21[10:0] GAM_R_LUT12: GAM_R_GAIN_23[10:0] GAM_R_LUT13: GAM_R_GAIN_25[10:0] GAM_R_LUT14: GAM_R_GAIN_27[10:0] GAM_R_LUT15: GAM_R_GAIN_29[10:0] GAM_R_LUT16: GAM_R_GAIN_31[10:0] Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2269 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.24 Area Setting Register R1 in Gamma Correction Block (GAM_R_AREA1) Bit: 31 30 29 28 27 26 25 24         23 22 - 21 20 19 18 - GAM_R_TH_01[7:0] - 17 16 - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - GAM_R_TH_03[7:0] - - - Initial value: 0 R/W: R/W Bit 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 24  -GAM_R_TH_02[7:0] - Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 GAM_R_TH_ 8 01[7:0] R/W Start Threshold of Area 1 of R Signal Unsigned (0 to 255 [LSB]) 0 < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 16 02[7:0] R/W Start Threshold of Area 2 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 24 03[7:0] R/W Start Threshold of Area 3 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. Page 2270 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.25 Area Setting Register R2 in Gamma Correction Block (GAM_R_AREA2) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - - GAM_R_TH_04[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_05[7:0] - 20 19 18 17 16 - - 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_R_TH_06[7:0] - - - - - GAM_R_TH_07[7:0] - 1 0 - - 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 32 04[7:0] R/W Description R/W Start Threshold of Area 4 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 40 05[7:0] R/W Start Threshold of Area 5 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 48 06[7:0] R/W Start Threshold of Area 6 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 56 07[7:0] R/W Start Threshold of Area 7 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2271 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.26 Area Setting Register R3 in Gamma Correction Block (GAM_R_AREA3) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - - GAM_R_TH_08[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_09[7:0] - 20 19 18 17 16 - - 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_R_TH_10[7:0] - - - - - GAM_R_TH_11[7:0] - 1 0 - - 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 64 08[7:0] R/W Description R/W Start Threshold of Area 8 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 72 09[7:0] R/W Start Threshold of Area 9 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 80 10[7:0] R/W Start Threshold of Area 10 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 88 11[7:0] R/W Start Threshold of Area 11 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. Page 2272 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.27 Area Setting Register R4 in Gamma Correction Block (GAM_R_AREA4) Bit: Initial value: 31 0 R/W: R/W Bit: Initial value: 15 0 R/W: R/W Bit 30 29 - - GAM_R_TH_12[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_13[7:0] - 20 19 18 17 16 - - 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_R_TH_14[7:0] - - - - - GAM_R_TH_15[7:0] - 1 0 - - 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 96 12[7:0] R/W Description R/W Start Threshold of Area 12 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 104 13[7:0] R/W Start Threshold of Area 13 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 112 14[7:0] R/W Start Threshold of Area 14 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 120 15[7:0] R/W Start Threshold of Area 15 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2273 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.28 Area Setting Register R5 in Gamma Correction Block (GAM_R_AREA5) Bit: Initial value: 31 1 R/W: R/W Bit: 15 Initial value: 1 R/W: R/W Bit 30 29 - - GAM_R_TH_16[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_17[7:0] - 20 19 18 17 16 - - 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - GAM_R_TH_18[7:0] - - - - - GAM_R_TH_19[7:0] - - - 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 128 16[7:0] R/W Description R/W Start Threshold of Area 16 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 136 17[7:0] R/W Start Threshold of Area 17 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 144 18[7:0] R/W Start Threshold of Area 18 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 152 19[7:0] R/W Start Threshold of Area 19 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. Page 2274 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.29 Area Setting Register R6 in Gamma Correction Block (GAM_R_AREA6) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - - GAM_R_TH_20[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_21[7:0] - 20 19 18 17 16 - - 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_R_TH_22[7:0] - - - - - GAM_R_TH_23[7:0] - 1 0 - - 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 160 20[7:0] R/W Description R/W Start Threshold of Area 20 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 168 21[7:0] R/W Start Threshold of Area 21 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 176 22[7:0] R/W Start Threshold of Area 22 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 184 23[7:0] R/W Start Threshold of Area 23 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2275 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.30 Area Setting Register R7 in Gamma Correction Block (GAM_R_AREA7) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - - GAM_R_TH_24[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_25[7:0] - 20 19 18 17 16 - - 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_R_TH_26[7:0] - - - - - GAM_R_TH_27[7:0] - 1 0 - - 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 192 24[7:0] R/W Description R/W Start Threshold of Area 24 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 200 25[7:0] R/W Start Threshold of Area 25 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 208 26[7:0] R/W Start Threshold of Area 26 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 216 27[7:0] R/W Start Threshold of Area 27 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. Page 2276 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.31 Area Setting Register R8 in Gamma Correction Block (GAM_R_AREA8) Bit: Initial value: 31 1 R/W: R/W Bit: Initial value: 15 1 R/W: R/W Bit 30 29 - - GAM_R_TH_28[7:0] - 28 27 26 25 24 - - 23 22 21 - - GAM_R_TH_29[7:0] - 20 19 18 17 16 - - 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 - - GAM_R_TH_30[7:0] - - - - - GAM_R_TH_31[7:0] - 1 0 - - 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value 31 to 24 GAM_R_TH_ 224 28[7:0] R/W Description R/W Start Threshold of Area 28 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 23 to 16 GAM_R_TH_ 232 29[7:0] R/W Start Threshold of Area 29 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 15 to 8 GAM_R_TH_ 240 30[7:0] R/W Start Threshold of Area 30 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area < Threshold of next area 7 to 0 GAM_R_TH_ 248 31[7:0] R/W Start Threshold of Area 31 of R Signal Unsigned (0 to 255 [LSB]) Threshold of previous area < Threshold of current area  255 Note: This register is updated when GAM_R_VEN in GAM_R_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2277 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.32 TCON Register Update Control Register (TCON_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                TCON_ VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 TCON_VEN 0 R/WC1 LCD TCON Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. Page 2278 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.33 TCON Reference Timing Setting Register (TCON_TIM) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 1 1 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 23 22 21 20 19 18 17 - - - - 1 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - TCON_HALF[10:0] - TCON_OFFSET[10:0] - 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_HALF 400 [10:0] R/W 15 to 11  R All 0 1/2fH Timing Specifies the clock count from the rising edge of the Hsync signal as the counting timing of horizontal counter. Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_OFFS 0 ET[10:0] R/W Offset Hsync Signal Timing Sets the clock cycle count from the rising edge of the Hsync signal. Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2279 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.34 TCON Vertical Timing Setting Register A1 (TCON_TIM_STVA1) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 TCON_STVA_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  TCON_STVA_VW[10:0] - Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_ STVA_VS [10:0] 0 15 to 11  All 0 R/W STVA Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STVA_VS from the rising edge of the Vsync signal (1/2fH cycles). R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_ STVA_VW [10:0] 4 R/W STVA Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STVA_VW (1/2fH cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2280 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.35 TCON Vertical Timing Setting Register A2 (TCON_TIM_STVA2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            TCON_ STVA_ INV  TCON_STVA_SEL[2:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R R R R R R R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_ STVA_INV 1 R/W Polarity Inversion Control of STVA Signal 0: Not inverted 1: Inverted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_ STVA_SEL [2:0] 0 R/W Output Signal Select for LCD_TCON0 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2281 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.36 TCON Vertical Timing Setting Register B1 (TCON_TIM_STVB1) Bit: 31 30 29 28 27 26 25 24      - - - 23 22 21 20 TCON_STVB_VS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - TCON_STVB_VW[10:0] - Initial value: 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_ STVB_VS [10:0] 70 15 to 11  All 0 R/W STVB Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STVB_VS from the rising edge of the Vsync signal (1/2fH cycles). R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_ STVB_VW [10:0] 960 R/W STVB Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STVB_VW (1/2fH cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2282 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.37 TCON Vertical Timing Setting Register B2 (TCON_TIM_STVB2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0            TCON_ STVB_ INV  TCON_STVB_SEL[2:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R R R R R R R R R R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_ STVB_INV 0 R/W Polarity Inversion Control of STVB Signal 0: Not inverted 1: Inverted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_ STVB_SEL [2:0] 1 R/W Output Signal Select for LCD_TCON1 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2283 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.38 TCON Horizontal Timing Setting Register STH1 (TCON_TIM_STH1) Bit: 31 30 29 28 27 26 25 24      - - - 22 23 21 20 TCON_STH_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - TCON_STH_HW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_STH_ 0 HS[10:0] R/W STH Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STH_HS + 1 from the rising edge of the Hsync signal (clock cycles). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_STH_ 96 HW[10:0] R/W STH Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STH_HW (clock cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2284 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.39 TCON Horizontal Timing Setting Register STH2 (TCON_TIM_STH2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        TCON_ STH_HS_ SEL    TCON_ STH_INV  - TCON_STH_SEL[2:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 R/W: R R R R R R R R/W R R R R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 TCON_STH_ 0 HS_SEL R/W  R STH Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference 7 to 5 All 0 Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_STH_ 1 INV R/W  R Polarity Inversion Control of STH Signal 0: Not inverted 1: Inverted 3 0 Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_STH_ 2 SEL[2:0] R/W Output Signal Select for LCD_TCON2 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2285 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.40 TCON Horizontal Timing Setting Register STB1 (TCON_TIM_STB1) Bit: 31 30 29 28 27 26 25 24      - - - 22 23 21 20 TCON_STB_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - TCON_STB_HW[10:0] - Initial value: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_STB_ HS[10:0] 144 R/W STB Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_STB_HS + 1 from the rising edge of the Hsync signal (clock cycles). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_STB_ HW[10:0] 640 R/W STB Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_STB_HW (clock cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2286 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.41 TCON Horizontal Timing Setting Register STB2 (TCON_TIM_STB2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        TCON_ STB_HS_ SEL    TCON_ STB_INV  - TCON_STB_SEL[2:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 R/W: R R R R R R R R/W R R R R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 TCON_STB_ HS_SEL 0 R/W STB Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_STB_ INV 0 R/W Polarity Inversion Control of STB Signal 0: Not inverted 1: Inverted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_STB_ SEL[2:0] 7 R/W Output Signal Select for LCD_TCON3 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2287 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.42 TCON Horizontal Timing Setting Register CPV1 (TCON_TIM_CPV1) Bit: 31 30 29 28 27 26 25 24      - - - 22 23 21 20 TCON_CPV_HS[10:0] - 19 18 17 16 - - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0      - - - - - - - TCON_CPV_HW[10:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_CPV_ 0 HS[10:0] R/W CPV Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_CPV_HS + 1 from the rising edge of the Hsync signal (clock cycles). 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_CPV_ 0 HW[10:0] R/W CPV Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_CPV_HW (clock cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2288 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.43 TCON Horizontal Timing Setting Register CPV2 (TCON_TIM_CPV2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        TCON_ CPV_HS_ SEL    TCON_ CPV_INV  - TCON_CPV_SEL[2:0] - Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R/W: R R R R R R R R/W R R R R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 31 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 TCON_CPV_ 0 HS_SEL R/W CPV Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_CPV_ 0 INV R/W Polarity Inversion Control of CPV Signal 0: Not inverted 1: Inverted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_CPV_ 4 SEL[2:0] R/W Output Signal Select for LCD_TCON4 Pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2289 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.44 TCON Horizontal Timing Setting Register POLA1 (TCON_TIM_POLA1) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 23 22 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - TCON_POLA_HS[10:0] - TCON_POLA_HW[10:0] - 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_ POLA_HS [10:0] 0 R/W POLA Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_POLA_HS from the rising edge of the Hsync signal (clock cycles). Note: When 1 x 1, 1 x 2, or 2 x 2 reverse mode is selected, these bits should be set to1 or greater. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_ POLA_HW [10:0] 0 R/W POLA Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_POLA_HW (clock cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2290 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.45 TCON Horizontal Timing Setting Register POLA2 (TCON_TIM_POLA2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   - TCON_ POLA_MD[1:0]    TCON_ POLA_HS _SEL    TCON_ POLA_ INV  -TCON_POLA_SEL[2:0] - Initial value: 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 R/W: R R R/W R/W R R R R/W R R R R/W R R/W R/W R/W Bit Bit Name 31 to 14  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 TCON_ POLA_MD [1:0] 1 R/W POLA Signal Generation Mode Select 0: Normal mode Generates the signal that changes twice a horizontal period. 1: 1 x 1 reverse mode Generates the signal whose polarity is inverted every horizontal period. 2: 1 x 2 reverse mode Generates the signal whose polarity is inverted in the first horizontal period and is subsequently inverted every two horizontal periods. 3: 2 x 2 reverse mode Generates the signal whose polarity is inverted every two horizontal periods. 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2291 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Initial Value R/W Description TCON_ POLA_HS_ SEL 0 R/W POLA Signal Operating Reference Select  All 0 Bit Bit Name 8 7 to 5 0: Hsync signal reference 1: Offset Hsync signal reference R Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_ POLA_INV 0 R/W Polarity Inversion Control of POLA Signal 0: Not inverted 1: Inverted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_ POLA_SEL [2:0] 5 R/W Output Signal Select for LCD_TCON5 pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2292 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.46 TCON Horizontal Timing Setting Register POLB1 (TCON_TIM_POLB1) 31 30 29 28 27 26 25 24      - - - Initial value: 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6      - - - Bit: 22 23 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - TCON_POLB_HS[10:0] - TCON_POLB_HW[10:0] - 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 27  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 to 16 TCON_ POLB_HS [10:0] 0 R/W POLB Signal Pulse Start Position (First Changing Timing) Starts pulse output after the time specified by the value of TCON_POLB_HS from the rising edge of the Hsync signal (clock cycles). Note: When 1 x 1, 1 x 2, or 2 x 2 reverse mode is selected, these bits should be set to1 or greater. 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 0 TCON_ POLB_HW [10:0] 0 R/W POLB Pulse Width (Second Changing Timing) Outputs a pulse of the duration of the value of TCON_POLB_HW (clock cycles). Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2293 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.47 TCON Horizontal Timing Setting Register POLB2 (TCON_TIM_POLB2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   - TCON_ POLB_MD[1:0]    TCON_ POLB_HS _SEL    TCON_ POLB_ INV  -TCON_POLB_SEL[2:0] - Initial value: 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 R/W: R R R/W R/W R R R R/W R R R R/W R R/W R/W R/W Bit Bit Name 31 to 14  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 TCON_ POLB_MD [1:0] 1 R/W POLB Signal Generation Mode Select 0: Normal mode Generates the signal that changes twice a horizontal period. 1: 1 x 1 reverse mode Generates the signal whose polarity is inverted every horizontal period. 2: 1 x 2 reverse mode Generates the signal whose polarity is inverted in the first horizontal period and is subsequently inverted every two horizontal periods. 3: 2 x 2 reverse mode Generates the signal whose polarity is inverted every two horizontal periods. 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 TCON_ POLB_HS_ SEL Page 2294 of 3092 0 R/W POLB Signal Operating Reference Select 0: Hsync signal reference 1: Offset Hsync signal reference R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 TCON_ POLB_INV 0 R/W Polarity Inversion Control of POLB Signal 0: Not inverted 1: Inverted 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 TCON_ POLB_SEL [2:0] 6 R/W Output Signal Select for LCD_TCON6 pin 0: STVA/VS 1: STVB/VE 2: STH/SP/HS 3: STB/LP/HE 4: CPV/GCK 5: POLA 6: POLB 7: DE Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2295 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.48 TCON Data Enable Polarity Setting Register (TCON_TIM_DE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                TCON_ DE_INV Bit: Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 TCON_DE_INV 0 R/W Polarity Inversion Control of DE Signal 0: Not inverted 1: Inverted Note: This register is updated when TCON_VEN in TCON_UPDATE is 1. Page 2296 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.49 Register Update Control Register in Output Controller (OUT_UPDATE) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                OUTCNT _VEN Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/WC1 Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 OUTCNT_ VEN 0 R/WC1 Brightness/Contrast, Dither Process, Output Interface Register Update 0: Registers are not updated. 1: Registers are updated at the rising edge of the Vsync. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2297 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.50 Output Interface Register (OUT_SET) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16    OUT_ ENDIAN_ ON    OUT_ SWAP_ ON         - Initial value: 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 R/W: R R R R/W R R R R/W R R R R R R R R Bit: 15 14 13 12 11 10 9 8 1 0   OUT_ FORMAT[1:0] - -   Initial value: 0 0 0 0 0 0 0 R/W: R R R/W R/W R R R/W Bit Bit Name 31 to 29  7 6 5 4 3 2    OUT_ DIR_ SEL   0 0 0 0 0 0 0 0 0 R/W R R R R/W R R R/W R/W OUT_FRQ_SEL[1:0] Initial Value R/W Description All 0 R Reserved - OUT_PHASE[1:0] These bits are always read as 0. The write value should always be 0. 28 OUT_ ENDIAN_ON 0 R/W Bit Endian Change On/Off Control 0: Off 1: On 27 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 OUT_SWAP_ ON 0 R/W B/R Signal Swap On/Off Control 0: Off 1: On 23 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 to 16  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2298 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Initial Value Bit Bit Name 13, 12 OUT_FORMAT 0 [1:0] R/W Description R/W Output Format Select 0: RBG888 1: RGB666 2: RGB565 3: Serial RGB 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 OUT_FRQ_ SEL[1:0] 0 R/W Clock Frequency Control 0: 100% speed  (parallel RGB) 1: Triple speed  (serial RGB) 2: Quadruple speed  (serial RGB) 3: Setting prohibited 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 OUT_DIR_SEL 0 R/W Scan Direction Select 0: Forward scan 1: Reverse scan 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2299 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name 1, 0 OUT_PHASE [1:0] Initial Value R/W Description 0 R/W Clock Phase Adjustment During Serial RGB Output Triple speed mode 0: 0 (clk) 1: 1 (clk) 2: 2 (clk) 3: Setting prohibited Quadruple speed mode 0: 0 (clk) 1: 1 (clk) 2: 2 (clk) 3: 3 (clk) Note: This register is updated when OUTCNT_VEN in OUT_UPDATE is 1. 36.2.51 Brightness (DC) Correction Register 1 (OUT_BRIGHT1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0       - - - - - - - Bit: PBRT_G[9:0] - Initial value: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 10  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 PBRT_G[9:0] 512 R/W Brightness (DC) Adjustment of G Signal Unsigned (0 (-512) to 512 (0) to 1023 (+511) [LSB], 512 [LSB] with offset) Note: This register is updated when OUTCNT_VEN in OUT_UPDATE is 1. Page 2300 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.52 Brightness (DC) Correction Register 2 (OUT_BRIGHT2) 31 30 29 28 27 26 25 24       - - Initial value: 0 0 0 0 0 0 1 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6       - - Bit: 23 22 - - 21 20 19 18 17 - - - - 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 5 4 3 2 1 0 - - - - PBRT_B[9:0] - PBRT_R[9:0] - 16 Initial value: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 26  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 16 PBRT_B[9:0] 512 R/W Brightness (DC) Adjustment of B Signal Unsigned (0 (-512) to 512 (0) to 1023 (+511) [LSB], 512 [LSB] with offset) 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 to 0 PBRT_R[9:0] 512 R/W Brightness (DC) Adjustment of R Signal Unsigned (0 (-512) to 512 (0) to 1023 (+511) [LSB], 512 [LSB] with offset) Note: This register is updated when OUTCNT_VEN in OUT_UPDATE is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2301 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.53 Contrast (Gain) Correction Register (OUT_CONTRAST) Bit: 31 30 29 28 27 26 25 24         23 22 21 - - 20 19 CONT_G[7:0] - 18 17 16 - - - Initial value: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - Initial value: 1 R/W: R/W Bit CONT_R[7:0] - 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 31 to 24  CONT_B[7:0] - Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 to 16 CONT_G[7:0] 128 R/W Contrast (Gain) Adjustment of G Signal 0/128 to 255/128 (approx.2 times) 15 to 8 CONT_B[7:0] 128 R/W Contrast (Gain) Adjustment of B Signal 0/128 to 255/128 (approx.2 times) 7 to 0 CONT_R[7:0] 128 R/W Contrast (Gain) Adjustment of R Signal 0/128 to 255/128 (approx.2 times) Note: This register is updated when OUTCNT_VEN in OUT_UPDATE is 1. Page 2302 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.54 Panel Dither Register (OUT_PDTHA) 31 30 29 28 27 26 25 24 23 22 21 20 19 18           PDTH_SEL[1:0]   Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R/W R/W R R R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0   PDTH_PA[1:0] - -   PDTH_PB[1:0]   PDTH_PC[1:0]   PDTH_PD[1:0] Initial value: 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 R/W: R R R/W R/W R R R/W R/W R R R/W R/W R R R/W R/W Bit: Bit Bit Name 31 to 22  - Initial Value R/W Description All 0 R Reserved - - 17 16 - PDTH_FORMAT[1:0] - These bits are always read as 0. The write value should always be 0. 21, 20 PDTH_SEL [1:0] 0 R/W Panel Dither Operation Mode 0: Truncate 1: Round-off 2: 2  2 pattern dither 3: Random pattern dither 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 PDTH_ 0 FORMAT[1:0] R/W Panel Dither Output Format Select 0: RGB888 1: RGB666 2: RGB565 3: Setting prohibited 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PDTH_PA [1:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 3 R/W Pattern Value (A) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) Page 2303 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name Initial Value R/W Description 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 7, 6 PDTH_PB [1:0] 0  All 0 R/W Pattern Value (B) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 3, 2 PDTH_PC [1:0] 2  All 0 R/W Pattern Value (C) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PDTH_PD [1:0] 1 R/W Pattern Value (D) of 2  2 Pattern Dither Unsigned (0 to 3 [LSB]) Note: This register is updated when OUTCNT_VEN in OUT_UPDATE is 1. Page 2304 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.2.55 Output Phase Control Register (OUT_CLK_PHASE) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    OUTCNT_ FRONT_ GAM    OUTCNT_ LCD_ EDGE  Bit: OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ POLB_ STVA_ STVB_ STH_ STB_ CPV_ POLA_ EDGE EDGE EDGE EDGE EDGE EDGE EDGE Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 31 to 13  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 OUTCNT_ 0 FRONT_GAM R/W Correction Circuit Sequence Control 0: Brightness  contrast  gamma correction 1: Gamma correction  contrast  brightness 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 OUTCNT_ LCD_EDGE 0 R/W Output Phase Control of LCD_DATA23 to LCD_DATA0 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 OUTCNT_ 0 STVA_EDGE R/W Output Phase Control of LCD_TCON0 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin 5 OUTCNT_ 0 STVB_EDGE R/W Output Phase Control of LCD_TCON1 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2305 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Bit Bit Name 4 OUTCNT_ STH_EDGE Initial Value R/W Description 0 R/W Output Phase Control of LCD_TCON2 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin 3 OUTCNT_ STB_EDGE 0 R/W Output Phase Control of LCD_TCON3 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin 2 OUTCNT_ CPV_EDGE 0 R/W Output Phase Control of LCD_TCON4 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin 1 OUTCNT_ 0 POLA_EDGE R/W Output Phase Control of LCD_TCON5 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin 0 OUTCNT_ 0 POLB_EDGE R/W Output Phase Control of LCD_TCON6 Pin 0: Output at the rising edge of LCD_CLK pin 1: Output at the falling edge of LCD_CLK pin Note: This register is updated when OUTCNT_VEN in OUT_UPDATE is 1. Page 2306 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.3 Usage Methods 36.3.1 Gamma Correction Adjustment Method The characteristics of G, B, R of each panel to be connected should be measured and gamma correction should be made to suit the panel. Since the gamma correction adjustment depends on to the characteristics of the panel, there are no recommended setting values. 36.3.2 Dither Usage Method Dither is used when pseudo contour is appeared on the display screen. Table 36.26 Dither Settings Bit Name Setting Value PDTH_FORMAT[1:0] Selects the format. For RGB888: 0 For RGB666: 1 For RGB565: 2 PDTH_SEL[1:0] When 2x2 pattern dither is to be used: 2 PDTH_PA[1:0] Normally 3 (initial value) PDTH_PB[1:0] Normally 0 (initial value) PDTH_PC[1:0] Normally 2 (initial value) PDTH_PD[1:0] Normally 1 (initial value) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2307 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller 36.3.3 Output Format Adjustment Method The setting example of the typical output format is shown in tables 36.27 and 36.28. It is necessary to carry out the setting of synchronization system signals of each output format similarly as the setting of output after scaling. Table 36.27 Setting Example of Synchronizing Signal Register Name Bit Name VGA SVGA Description TCON_TIM TCON_HALF[10:0] 400 528 Sets the half value of 1H time period in clock units. 0 0 Sets the pulse generation start position from the rising edge of the internal Vsync signal. Vsync signal TCON_TIM_STVA1 TCON_STVA_VS[10:0] A 1/2H time period is set as 1. TCON_TIM_STVA1 TCON_STVA_VW[10:0] 4 8 Sets the changing point from the above pulse generation start position. A 1/2H time period is set as 1. TCON_TIM_STVA2 TCON_STVA_INV 0 0 Sets the output polarity of the above pulse. For inverted output: 1 TCON_TIM_STVA2 TCON_STVA_SEL[2:0] 0 0 For STVA output selection: 0 68 44 Sets the pulse generation start position from the rising edge of the internal Vsync signal. Vertical enable signal TCON_TIM_STVB1 TCON_STVB_VS[10:0] A 1/2H time period is set as 1. TCON_TIM_STVB1 TCON_STVB_VW[10:0] 960 1200 Sets the changing point from the above pulse generation start position. A 1/2H time period is set as 1. TCON_TIM_STVB2 TCON_STVB_INV 0 0 Sets the output polarity of the above pulse. For inverted output: 1 TCON_TIM_STVB2 TCON_STVB_SEL[2:0] 1 1 For STVB output selection: 1 Page 2308 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Register Name Section 36 Video Display Controller 4 (6): Output Controller Bit Name VGA SVGA Description TCON_TIM_STH1 TCON_STH_HS[10:0] 0 0 Sets the pulse generation start position from the rising edge of the internal Hsync signal. TCON_TIM_STH1 TCON_STH_HW[10:0] 96 128 Sets the changing point from the above pulse generation start position. TCON_TIM_STH2 TCON_STH_INV 0 0 Sets the output polarity of the above pulse. For inverted output: 1 TCON_TIM_STH2 TCON_STH_SEL[2:0] 2 2 For STH output selection: 2 Hsync signal Horizontal enable signal TCON_TIM_STB1 TCON_STB_HS[10:0] 128 192 Sets the pulse generation start position from the rising edge of the internal Hsync signal. TCON_TIM_STB1 TCON_STB_HW[10:0] 640 800 Sets the changing point from the above pulse generation start position. TCON_TIM_STB2 TCON_STB_INV 0 0 Sets the output polarity of the above pulse. For inverted output: 1 TCON_TIM_STB2 TCON_STB_SEL[2:0] 3 3 For STB output selection: 3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2309 of 3092 SH7268 Group, SH7269 Group Section 36 Video Display Controller 4 (6): Output Controller Table 36.28 Setting Example of Data System Register Name Bit Name RGB RGB888 () Description OUT_SET OUT_ENDIAN_ON 0 0 When bit endian is changed: 1 OUT_SET OUT_SWAP_ON 0 0 When B/R is to be swapped: 1 OUT_SET OUT_PIXEL_INV_ON 0 0 When the function of reducing number of simultaneous changes is to be used: 1 OUT_SET OUT_SUM_MOVE[4:0] 31 31 When OUT_PIXEL_INV_ON = 1, this register becomes valid. Sets the simultaneous changing threshold. OUT_SET OUT_FORMAT[1:0] 3 Sets the output format. 0 For RGB888: 0 For RGB666: 1 For RGB565: 2 For serial RGB: 3 OUT_SET OUT_FRQ_SEL[1:0] 0 1 Sets the output clock. For RGB888, RGB666, RGB565: 0 For triple speed serial RGB output: 1 For quadruple serial RGB output: 2 OUT_SET OUT_DIR_SEL 0 0 When data arrangement of the serial RGB output is to be reversed: 1 OUT_SET OUT_PHASE[1:0] 0 0 Sets when output phase of the serial RGB is shifted. Not delayed Delayed by one clock cycle: 1 Delayed by two clock cycles: 2 Delayed by three clock cycles: 3 (applicable only for quadruple speed mode) Page 2310 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Section 37 Video Display Controller 4 (7): System Controller 37.1 System Controller 37.1.1 Overview of Functions The system controller provides interrupt control, panel clock control, CLUT table read select signal status flag output functions. 37.1.2 Interrupt Control Nine interrupt signals are output from the scaler and image synthesizer. The system controller controls whether to output these interrupt signals. One is written to the corresponding INT_STA* bit when an interrupt signal is to be accepted. After 1 has been written to the bit, however, its value is still read out as 0 until the interrupt signal is accepted. Once the interrupt signal has been accepted, the INT_STA* bit is read out as 1. The bit for an accepted interrupt signal is cleared by writing 0 to the INT_STA* bit. If further interrupt signals are to be accepted after the INT_STA* bit has been cleared, 1 is again written to the bit. Table 37.1 Interrupt Signals Signal Name Function VI_VSYNC Vsync signal before scaling LO_VSYNC Vsync signal after scaling VSYNCERR Missing Vsync signal for scaling VLINE Specified line signal for panel output VFIELD Field end signal for recording function VBUFERR1 Frame buffer write overflow signal VBUFERR2 Graphics 1 frame buffer read underflow signal VBUFERR3 Graphics 2 frame buffer read underflow signal VBUFERR4 Graphics 3 frame buffer read underflow signal R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2311 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Table 37.2 Interrupt Clear/Hold Settings Register Name Bit Name Initial Value SYSCNT_INT2 INT_STA0 0 Description VI_VSYNC Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. INT_STA1 0 LO_VSYNC Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. INT_STA2 0 VSYNCERR Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. INT_STA3 0 VLINE Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. INT_STA4 0 VFIELD Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. INT_STA5 0 VBUFERR1 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. Page 2312 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Register Name Bit Name Initial Value Description SYSCNT_INT2 INT_STA6 0 VBUFERR2 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. INT_STA7 0 VBUFERR3 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. SYSCNT_INT1 INT_STA8 0 VBUFERR4 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2313 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Table 37.3 Interrupt Output On/Off Settings Register Name Bit Name Initial Value Description SYSCNT_INT4 INT_OUT0_ON 0 VI_VSYNC Interrupt Output On/Off 0: Off 1: On INT_OUT1_ON 0 LO_VSYNC Interrupt Output On/Off 0: Off 1: On INT_OUT2_ON 0 VSYNCERR Interrupt Output On/Off 0: Off 1: On INT_OUT3_ON 0 VLINE Interrupt Output On/Off 0: Off 1: On INT_OUT4_ON 0 VFIELD Interrupt Output On/Off 0: Off 1: On INT_OUT5_ON 0 VBUFERR1 Interrupt Output On/Off 0: Off 1: On INT_OUT6_ON 0 VBUFERR2 Interrupt Output On/Off 0: Off 1: On INT_OUT7_ON 0 VBUFERR3 Interrupt Output On/Off 0: Off 1: On SYSCNT_INT3 INT_OUT8_ON 0 VBUFERR4 Interrupt Output On/Off 0: Off 1: On Page 2314 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 37.1.3 Section 37 Video Display Controller 4 (7): System Controller Panel Clock Control The video image clock, external clock, or peripheral clock 1 is selectable as the source of the panel clock for supply to this module. The module is also equipped with a divider for scaling the frequency by factors from 1/1 to 1/32. The bits listed in table 37.4 control the panel clock. Table 37.4 Panel Clock Control Register Name Bit Name Initial Value SYSCNT_PANEL_CLK PANEL_ICKSEL 0 [1:0] Description Panel Clock Source Select 0: Video image clock (this is VIDEO_X1 if INP_SEL = 0 and DV_CLK if INP_SEL = 0) 1: External clock (LCD_EXTCLK) 2: Peripheral clock 1 (P1) 3: Setting prohibited SYSCNT_PANEL_CLK PANEL_ICKEN 0 Panel Clock Operation Enable 0: Disables operation of the panel clock operation block. 1: Enables operation of the panel clock operation block. Note: Set this bit to 0 before changing the value of the PANEL_ICKSEL or PANEL_DCDR bits. SYSCNT_PANEL_CLK PANEL_DCDR [5:0] 1 Clock Frequency Division Ratio Refer to table 37.5 for details on the settings. Note: Settings other than those in table 37.5 are prohibited. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2315 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Table 37.5 I/O Clock Frequency and Divisors I/O Clock Frequency (MHz) DCDR[5:0] Clock Ratio 27.00 54.00 66.67*2 000001*1 1/1 27.00 54.00 66.67 000010 1/2 13.50 27.00 33.33 000011 1/3 9.00 18.00 22.22 000100 1/4 6.75 13.50 16.67 000101 1/5 5.40 10.80 13.33 000110 1/6 4.50 9.00 11.11 000111 1/7 3.86 7.71 9.52 001000 1/8 3.38 6.75 8.33 001001 1/9 3.00 6.00 7.41 001100 1/12 2.25 4.50 5.56 010000 1/16 1.69 3.38 4.17 011000 1/24 1.13 2.25 2.78 100000 1/32 0.84 1.69 2.08 Notes: 1. This setting is prohibited when peripheral clock 1 (P1) has been selected as the source for supply of the panel clock. 2. This is applicable whether the external clock (LCD_EXTCLK) or peripheral clock 1 (P1) has been selected as the source for supply of the panel clock. Page 2316 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller The panel clock setting procedure is described below. (1) Specifying 1/7 frequency division In the initial settings after a power-on reset or after returning from deep-standby, and when changing the input source of the panel clock by means of the INP_SEL bit in the INP_SEL_CNT register of the input control block and the PANEL_ICKSEL[1:0] bits, do not fail to perform the steps below to confirm that the 1/7 clock ratio output is selected for the panel clock. (a) After specifying the panel clock input source by means of the INP_SEL bit in the INP_SEL_CNT register of the input control block and the PANEL_ICKSEL[1:0] bits, set the PANEL_DCDR[5:0] bits to specify 1/7 as the clock ratio. (b) Set PANEL_ICKEN to 1. (c) In the scaling block, set the period of the vertical sync signal. (d) Set to 1 the TCON_VEN bit in the TCON_UPDATE register of the output control block. (e) After the vertical sync signal period set in (d) has elapsed, read the TCON_VEN bit. If the read value is 0, the panel clock is being output correctly and the setting procedure is complete. If the read value is 1, the panel clock output is fixed at low or high level. (f) If the output is fixed, initialize video display controller 4 by means of the VDC4SRST bit in the SWRSTCR2 register of the power-down modes, then redo the setting procedure from (a). (2) Specifying 1/3, 1/4, 1/6, 1/8, 1/12, 1/16, 1/24, or 1/32 frequency division In the initial settings after a power-on reset or after returning from deep-standby, and when changing the input source of the panel clock by means of the INP_SEL bit in the INP_SEL_CNT register of the input control block and the PANEL_ICKSEL[1:0] bits, do not fail to perform the steps below to confirm that the 1/12 clock ratio output is selected for the panel clock, then specify the desired clock ratio. If the 1/12 clock ratio output is abnormal, output at the desired clock ratio will also be abnormal. (a) After specifying the panel clock input source by means of the INP_SEL bit in the INP_SEL_CNT register of the input control block and the PANEL_ICKSEL[1:0] bits, set the PANEL_DCDR[5:0] bits to specify 1/12 as the clock ratio. (b) Set PANEL_ICKEN to 1. (c) In the scaling block, set the period of the vertical sync signal. (d) Set to 1 the TCON_VEN bit in the TCON_UPDATE register of the output control block. (e) After the vertical sync signal period set in (d) has elapsed, read the TCON_VEN bit. If the read value is 0, set the PANEL_DCDR[5:0] bits to specify the desired clock ratio and complete the setting procedure. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2317 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller If the read value is 1, the panel clock output is fixed at low or high level. (f) If the output is fixed, initialize video display controller 4 by means of the VDC4SRST bit in the SWRSTCR2 register of the power-down modes, then redo the setting procedure from (a). (3) Specifying a frequency division ratio other than the above There is no need to confirm the division ratio of the panel clock output. (a) After specifying the panel clock input source by means of the INP_SEL bit in the INP_SEL_CNT register of the input control block and the PANEL_ICKSEL[1:0] bits, set the PANEL_DCDR[5:0] bits to specify the desired clock ratio. (b) Set PANEL_ICKEN to 1. 37.1.4 CLUT Table Read Select Signal Status Flag The CLUT read select signal status can be read using the flags shown in table 37.6. Table 37.6 CLUT Table Read Select Signal Status Flags Register Name Bit Name Initial Value SYSCNT_CLUT GR1_CLT_SEL_ST  Description Graphics 1 CLUT Table Read Select Signal Status Flag 0: CLUT table 0 is read out. 1: CLUT table 1 is read out. SYSCNT_CLUT GR2_CLT_SEL_ST  Graphics 2 CLUT Table Read Select Signal Status Flag 0: CLUT table 0 is read out. 1: CLUT table 1 is read out. SYSCNT_CLUT GR3_CLT_SEL_ST  Graphics 3 CLUT Table Read Select Signal Status Flag 0: CLUT table 0 is read out. 1: CLUT table 1 is read out. Page 2318 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 37.2 Section 37 Video Display Controller 4 (7): System Controller Register Descriptions The following register sets are allocated in the SH register map area.  Symbols used in Register Descriptions Initial value: Register value after a reset : Undefined value R/W: Readable/writable. The written value can be read. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored. R/WC1: Readable/writable. Writing 1 initializes the bit. Writing 0 is ignored. R: Read-only. The write value should always be 0. /W: Write-only. The read value is undefined. Table 37.7 Register Configuration of System Controller Register Name Abbreviation R/W Initial Value Address Access Size Interrupt control register 1 SYSCNT_INT1 R/W H'0000 0000 H'FFFF 7A80 32/16 Interrupt control register 2 SYSCNT_INT2 R/W H'0000 0000 H'FFFF 7A84 32/16 Interrupt control register 3 SYSCNT_INT3 R/W H'0000 0000 H'FFFF 7A88 32/16 Interrupt control register 4 SYSCNT_INT4 R/W H'0000 0000 H'FFFF 7A8C 32/16 Panel clock control register SYSCNT_PANEL_C R/W LK H'0001 H'FFFF 7A90 16 CLUT table read select signal status register SYSCNT_CLUT H'0000 H'FFFF 7A92 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R Page 2319 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller 37.2.1 Interrupt Control Register 1 (SYSCNT_INT1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                INT_ STA8 Bit: Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 INT_STA8 0 R/W VBUFERR4 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. Page 2320 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 37.2.2 Section 37 Video Display Controller 4 (7): System Controller Interrupt Control Register 2 (SYSCNT_INT2) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16    INT_ STA7    INT_ STA6    INT_ STA5    INT_ STA4 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    INT_ STA3    INT_ STA2    INT_ STA1    INT_ STA0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R R/W Bit Bit Name 31 to 29  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 28 INT_STA7 0 R/W VBUFERR3 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. 27 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 INT_STA6 0 R/W VBUFERR2 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. 23 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 INT_STA5 0 R/W VBUFERR1 Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2321 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Bit Bit Name 19 to 17  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 INT_STA4 0 R/W VFIELD Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 INT_STA3 0 R/W VLINE Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 INT_STA2 0 R/W VSYNCERR Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 INT_STA1 0 R/W LO_VSYNC Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. Page 2322 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Bit Bit Name Initial Value R/W Description 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 INT_STA0 0 R/W VI_VSYNC Interrupt Clear/Hold 0(W): Clears the interrupt status. 1(W): Starts interrupt acceptance. 0(R): No interrupt has occurred. 1(R): An interrupt has occurred. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2323 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller 37.2.3 Interrupt Control Register 3 (SYSCNT_INT3) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16                 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0                INT_ OUT8_ON Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 INT_OUT8_ ON 0 R/W VBUFERR4 Interrupt Output On/Off 0: Off 1: On Page 2324 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 37.2.4 Section 37 Video Display Controller 4 (7): System Controller Interrupt Control Register 4 (SYSCNT_INT4) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16    INT_ OUT7_ ON    INT_ OUT6_ ON    INT_ OUT5_ ON    INT_ OUT4_ ON Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0    INT_ OUT3_ ON    INT_ OUT2_ ON    INT_ OUT1_ ON    INT_ OUT0_ ON Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R/W R R R R/W R R R R/W R R R R/W Bit Bit Name 31 to 29  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 28 INT_OUT7_ ON 0 R/W VBUFERR3 Interrupt Output On/Off 0: Off 1: On 27 to 25  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 24 INT_OUT6_ ON 0 R/W VBUFERR2 Interrupt Output On/Off 0: Off 1: On 23 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 INT_OUT5_ ON 0 R/W VBUFERR1 Interrupt Output On/Off 0: Off 1: On R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2325 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller Bit Bit Name 19 to 17  Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 INT_OUT4_ ON 0 R/W VFIELD Interrupt Output On/Off 0: Off 1: On 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 INT_OUT3_ ON 0 R/W VLINE Interrupt Output On/Off 0: Off 1: On 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 INT_OUT2_ ON 0 R/W VSYNCERR Interrupt Output On/Off 0: Off 1: On 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 INT_OUT1_ ON 0 R/W LO_VSYNC Interrupt Output On/Off 0: Off 1: On 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 INT_OUT0_ ON 0 R/W VI_VSYNC Interrupt Output On/Off 0: Off 1: On Page 2326 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 37.2.5 Section 37 Video Display Controller 4 (7): System Controller Panel Clock Control Register (SYSCNT_PANEL_CLK) Bit: 15 14   12 13 PANEL_ICKSEL[1:0] - 11 10 9 8 7 6 5 4    PANEL_ ICKEN   - - 3 2 PANEL_DCDR[5:0] - 0 1 - Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W: R R R/W R/W R R R R/W R R R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PANEL_ICKS All 0 EL[1:0] R/W Panel Clock Source Select 0: Video image clock (this is VIDEO_X1 if INP_SEL = 0 and DV_CLK if INP_SEL = 0) 1: External clock (LCD_EXTCLK) 2: Peripheral clock 1 (P1) 3: Setting prohibited 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PANEL_ ICKEN 0 R/W Panel Clock Operation Enable 0: Disables operation of the panel clock operation block. 1: Enables operation of the panel clock operation block. Note: Set this bit to 0 before changing the value of the PANEL_ICKSEL or PANEL_DCDR bits. 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 PANEL_ DCDR[5:0] 1 R/W Clock Frequency Division Ratio Refer to table 37.5 for details on the settings. Note: Settings other than those in table 37.5 are prohibited. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2327 of 3092 SH7268 Group, SH7269 Group Section 37 Video Display Controller 4 (7): System Controller 37.2.6 CLUT Table Read Select Signal Status Register (SYSCNT_CLUT) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0        GR3_CLT _SEL_ST    GR2_CLT _SEL_ST    GR1_CLT _SEL_ST Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 GR3_CLT_ SEL_ST  R Graphics 3 CLUT Table Read Select Signal Status Flag 0: CLUT table 0 is read out. 1: CLUT table 1 is read out. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 GR2_CLT_ SEL_ST  R Graphics 2 CLUT Table Read Select Signal Status Flag 0: CLUT table 0 is read out. 1: CLUT table 1 is read out. 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GR1_CLT_ SEL_ST  R Graphics 1 CLUT Table Read Select Signal Status Flag 0: CLUT table 0 is read out. 1: CLUT table 1 is read out. Page 2328 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 38 Image Renderer (IMR-LS) Section 38 Image Renderer (IMR-LS) Renesas Electronics Corporation is only able to provide information contained in this section to parties with which we have concluded a nondisclosure agreement. Please contact one of our sales representatives for details. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2329 of 3092 Section 38 Image Renderer (IMR-LS) Page 2330 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit Section 39 Display Out Comparison Unit The display out comparison unit checks whether the data output from the graphics display module* agrees with the expected graphics data. This checking is accomplished by comparing the CRC code of the data output from the graphics display module with the pre-calculated CRC code of the expected graphics data. Note: * This indicates video display controller 4 in this LSI. 39.1 Features This module has the following features.  Comparison of Graphics Planes of Graphics Display Module One of the graphics planes of the graphics display module can be selected and its CRC code can be compared with the expected CRC code.  Comparison of Data after  Blending The CRC code of the graphics data obtained after  blending in the graphics display module can be compared with the expected CRC code.  Rectangular Area Specification The rectangular area can be specified based on the graphics data output from the graphics display module (graphics plane or graphics data obtained after  blending) and its CRC code can be compared with the expected CRC code.  Pixel Format A pixel format for 32 bits/pixel or 16 bits/pixel can be selected. ARGB8888/RGB888 are available for 32 bits/pixel, and only RGB565 is available for 16 bits/pixel. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2331 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.2 Block Diagram An overall block diagram of this module is shown in figure 39.1. Peripheral bus Bus interface Module data bus Register block Graphics data of graphics plane 1 Graphics data of graphics plane 2 Graphics data of graphics plane 3 CRC code calculation/comparison Graphics data after  blending Figure 39.1 Block Diagram Page 2332 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.3 Section 39 Display Out Comparison Unit Register Descriptions Table 39.1 shows the register configuration. Table 39.1 Register Configuration Register Name Abbreviation R/W Address Control register DOCMCR R/W H'FFFFA800 32 Status register DOCMSTR R H'FFFFA804 32 Status clear register DOCMCLSTR R/W H'FFFFA808 32 Interrupt enable register DOCMIENR R/W H'FFFFA80C 32 Operation parameter setting register DOCMPMR R/W H'FFFFA814 32 Expected CRC code register DOCMECRCR R/W H'FFFFA818 32 Calculated CRC code value register DOCMCCRCR R H'FFFFA81C 32 Horizontal start position setting register DOCMSPXR R/W H'FFFFA820 32 Vertical start position setting register DOCMSPYR R/W H'FFFFA824 32 Horizontal size setting register DOCMSZXR R/W H'FFFFA828 32 Vertical size setting register DOCMSZYR R/W H'FFFFA82C 32 CRC code initialization register DOCMCRCIR R/W H'FFFFA830 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Access Size Page 2333 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.1 Control Register (DOCMCR) DOCMCR turns CRC code comparison on or off. Bit: 31 - 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - CMPRU Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - CMPR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 CMPRU 0 R Display Out Comparison Update Value Reflects the internal update of the CMPR bit. It should be checked that this bit is 0 before updating the registers other than the CMPR bit in DOCMCR, DOCMCLSTR, and DOCMIENR. For details, see section 39.4.8, Register Update Timing. 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 CMPR 0 R/W Display Out Comparison Execution Executes display out comparison. This bit is loaded inside when the start of the valid period of the graphics data is detected. For details, see section 39.4.8, Register Update Timing. 0: Stops display out comparison. 1: Executes display out comparison. Page 2334 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.3.2 Section 39 Display Out Comparison Unit Status Register (DOCMSTR) DOCMSTR returns the comparison result of the CRC code. The result is reflected in this register when the end of the valid period of the graphics data is detected. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - CMPST Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31, 30  All 0 R Reserved Values read from these bits are undefined. The write value should always be 0. 29 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 CMPST 0 R/W Display Out Comparison Status 0: Compared CRC codes match. 1: Compared CRC codes do not match. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2335 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.3 Status Clear Register (DOCMCLSTR) Writing 1 to the CMPCLST bit causes clearing of the CMPST bit in DOCMSTR to 0. However, clearing of the CMPST bit in DOCMSTR after 1 is written to the CMPCLST bit takes a fixed amount of time. Confirm that the CMPST bit in DOCMSTR is actually clear after writing 1 to the CMPCLST bit. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - CMP CLST Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 CMPCLST 0 R/W Display Out Comparison Status Clear Setting this bit to 1 clears the CMPST bit in DOCMSTR to 0. This bit is always read as 0. Page 2336 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.3.4 Section 39 Display Out Comparison Unit Interrupt Enable Register (DOCMIENR) DOCMIENR enables interrupt of the corresponding status bits in DOCMSTR. Bit: 31 - 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - CMPIEN Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 CMPIEN 0 R/W Display Out Comparison Mismatch Detection Interrupt Enable Enables/disables the display out comparison mismatch detection interrupt (CMPI) when the CMPST bit in DOCMSTR is set to 1. 0: Disables the display out comparison mismatch detection interrupt (CMPI). 1: Enables the display out comparison mismatch detection interrupt (CMPI). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2337 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.5 Operation Parameter Setting Register (DOCMPMR) DOCMPMR selects the graphics data and sets the pixel format. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - CMPBT Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 3 2 1 0 - CMPDFA[7:0] Initial value: 0 R/W: R/W Bit 0 R/W 0 R/W Bit Name 31 to 17  0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 CMP DAUF - - - 0 R/W 0 R 0 R 0 R Initial Value R/W Description All 0 R Reserved CMPSELP[3:0] 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 16 CMPBT 0 R/W Pixel Format Data Width Specifies the data width of the pixel format. 0: 32 bits/pixel (ARGB8888/RGB888 format) 1: 16 bits/pixel (RGB565 format) 15 to 8 7 CMPDFA [7:0] H'00 CMPDAUF 0 R/W Display Out Comparison Default  Value Sets the default  value. This bit is enabled when the CMPDAUF bit is 1. R/W Display Out Comparison Default  Value Use Enables the use of default  value. 0: Disables use of default  value. 1: Enables use of default  value. Note: This bit is enabled only if RGB888 format is selected. For ARGB8888/RGB565 format, this bit should always be set to 0. When this bit is set to 0 when RGB888/RGB666 pixel format is selected, the data output from the graphics display module is used as the  value. Page 2338 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit Bit Bit Name Initial Value R/W Description 6 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 CMPSELP [3:0] 0000 R/W Display Out Comparison Selection Plane Selects the graphics data for CRC code comparison. 0: Selects no data. 1 to 3: Selects graphics data of graphics plane 1 to graphics plane 3. 9: Selects graphics data after  blending. Other than above: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2339 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.6 Expected CRC Code Register (DOCMECRCR) DOCMECRCR specifies the CRC code of the expected graphics data. Bit: 31 30 29 28 27 26 25 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 24 23 22 21 20 19 18 17 16 CMPECRC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W CMPECRC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W Bit Bit Name 31 to 0 CMPECRC [31:0] 39.3.7 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description H'00000000 R/W Expected Display Out Comparison CRC Code The expected CRC code value of the selected graphics data or rectangular area Calculated CRC Code Value Register (DOCMCCRCR) The CRC code calculation result of the selected graphics plane or rectangular area can be read from this register. The calculation result is reflected in this register when the end of the valid period of the graphics data is detected. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMPCCRC[31:16] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R CMPCCRC[15:0] Initial value: 0 R/W: R 0 R Bit Bit Name 31 to 0 CMPCCRC [31:0] Page 2340 of 3092 0 R 0 R 0 R Initial Value R/W H'00000000 R 0 R 0 R 0 R 0 R Description Calculated Display Out Comparison CRC Code Value The calculated CRC code value of the selected graphics data or rectangular area R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.3.8 Section 39 Display Out Comparison Unit Horizontal Start Position Setting Register (DOCMSPXR) DOCMSPXR specifies the horizontal start position of the rectangular area for which the CRC code is calculated. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W - 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 16 CMPSPX[10:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 0 CMPSPX [10:0] H'000 R/W Display Out Comparison Horizontal Start Position Specifies the horizontal start position of the rectangular area for which the CRC code is calculated. The set value should be smaller than or equal to the horizontal size of the graphics data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2341 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.9 Vertical Start Position Setting Register (DOCMSPYR) DOCMSPYR specifies the vertical start position of the rectangular area for which the CRC code is calculated. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W - 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 16 CMPSPY[10:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 0 CMPSPY [10:0] H'000 R/W Display Out Comparison Vertical Start Position Specifies the vertical start position of the rectangular area for which the CRC code is calculated. The set value should be smaller than or equal to the vertical size of the graphics data. Page 2342 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.10 Horizontal Size Setting Register (DOCMSZXR) DOCMSZXR specifies the horizontal size of the rectangular area for which the CRC code is calculated. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W - 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 16 CMPSZX[10:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 0 CMPSZX [10:0] H'000 R/W Display Out Comparison Horizontal Size Specifies the horizontal size of the rectangular area for which the CRC code is calculated. The value should be set as follows: Horizontal size of the graphics data  Horizontal start position (CMPSPX) + Horizontal size (CMPSZX). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2343 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.11 Vertical Size Setting Register (DOCMSZYR) DOCMSZYR specifies the vertical size of the rectangular area for which the CRC code is calculated. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W - 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 16 CMPSZY[10:0] 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 0 CMPSZY [10:0] H'000 R/W Display Out Comparison Vertical Size Specifies the vertical size of the rectangular area for which the CRC code is calculated. The value should be set as follows: Vertical size of the graphics data  Vertical start position (CMPSPY) + Vertical size (CMPSZY). Page 2344 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.3.12 CRC Code Initialization Register (DOCMCRCIR) DOCMCRCIR is used to specify the initial value of the CRC code. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRCINI[31:16] Initial value: 1 R/W: R/W Bit: 15 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 14 13 12 11 10 9 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W CRCINI[15:0] Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 31 to 0 CRCINI [31:0] H'FFFFFFFF R/W Display Output CRC Comparison Initial Value R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 These bits specify the initial value of the CRC for the rectangular region of the selected graphics data. Page 2345 of 3092 Section 39 Display Out Comparison Unit 39.4 Operation 39.4.1 Overview of Operations SH7268 Group, SH7269 Group This module is capable of calculating the CRC code of the arbitrary rectangular area of graphics data. By comparing the CRC code with the pre-calculated expected CRC code value, this module can detect whether the display output is obtained as expected. Main features of this module are as follows.     Graphics data can be selected from graphics plane 1 to graphics plane 3 Graphics data after  blending can be selected Arbitrary rectangular area of the selected graphics data can be specified Pixel format can be selected from ARGB88888 and RGB888 for 32 bits/pixel or RGB565 for 16 bits/pixel  Interrupt is generated when the compared CRC codes do not match. 39.4.2 System Configuration This module is configured as shown in figure 39.2. The CRC code is calculated after receiving the graphics data output from the graphics display module. The calculated CRC code is then compared with the pre-calculated expected CRC code value. The graphics data can be selected from graphics plane 1 to graphics plane 3, and the data after  blending. Page 2346 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit Graphics display module Graphics plane 1 Graphics data display Superimposition Display timing control Graphics plane 3 This module Display out compare CRC32 calculation Interrupt signal Comparator Select register Expected CRC code register Figure 39.2 System Configuration 39.4.3 CRC Calculation Method The display out comparison unit generates a 32-bit CRC code by using the following CRC polynomial (IEEE802.3). x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x+1 CRC is sequentially calculated beginning with LSB in pixel units. In other words, for 32 bits/pixel, it is calculated in units of 32 bits and for 16 bits/pixel, it is calculated in units of 16 bits. During CRC calculation of data, pixel data is input when the graphics data is output (top left to bottom right). 39.4.4 Graphics Data Selection for CRC Code Generation The graphics data for which the CRC code is calculated can be selected from the graphics plane 1 to graphics plane 3 or the graphics data after  blending by setting the CMPSELP[3:0] bits in DOCMPMR. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2347 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.4.5 (1) Pixel Format Pixel Format Specification DOCMPMR specifies the pixel format. The pixel formats are given in table 39.2. Table 39.2 Pixel Format Bits in DOCMPMR 32 bits/pixel ARGB8888 CMPBT CMPDFA[7:0] CMPDAUF 0   Arbitrary Arbitrary   RGB888 16 bits/pixel (2) RGB565 1 Data Arrangement for Available Pixel Formats Data arrangement for each pixel format is given below.  ARGB8888 (32 bits/pixel) b31 b24 b23  8 bits b16 b15 Red 8 bits b8 b7 Green 8 bits b0 Blue 8 bits  RGB888 (32 bits/pixel) b31 b24 b23 * Note: b16 b15 Red 8 bits * b8 b7 Green 8 bits b0 Blue 8 bits When CMPDAUF = 0,  value is the value output from the graphics display module. When CMPDAUF = 1,  value is the value specified by CMPDFA[7:0].  RGB565 (16 bits/pixel) b15 Red 5 bits Page 2348 of 3092 b11 b10 Green 6 bits b5 b4 b0 Blue 5 bits R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.4.6 Section 39 Display Out Comparison Unit Rectangular Area Settings Based on the selected graphics data, the start position and size of the rectangular area for which the CRC code is calculated can be set with the register. Figure 39.3 shows such a rectangular area and table 39.3 shows the register settings for the area. (1) Horizontal size of the graphics data (4) CMPSPY (3) CMPSPX Area for which the CRC code is calculated (6) CMPSZY (2) Vertical size of the graphics data (5) CMPSZX Figure 39.3 Rectangular Area for which the CRC Code is Calculated R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2349 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit Table 39.3 Register Settings for the Rectangular Area for which the CRC Code is Calculated Symbol in the No. Figure (1) Register Used for Setting Horizontal size of the graphics data Description Horizontal size of the graphics data. Set the size using the graphics display module. (2) Vertical size of the graphics data Vertical size of the graphics data. Set the size using the graphics display module. (3) CMPSPX (horizontal start position) DOCMSPXR Set the horizontal distance from the upper left origin of the graphics data to the rectangular area for which the CRC code is calculated in pixel units. (4) CMPSPY (vertical start position) DOCMSPYR Set the vertical distance from the upper left origin of the graphics data to the rectangular area for which the CRC code is calculated in line units. (5) CMPSZX (horizontal size) DOCMSZXR Set the horizontal size of the rectangular area for which the CRC code is calculated in pixel units. The value should be set as follows: Horizontal size of the graphics data  CMPSPX + CMPSZX. (6) CMPSZY (vertical size) DOCMSZYR Set the vertical size of the rectangular area for which the CRC code is calculated in line units. The value should be set as follows: Vertical size of the graphics data  CMPSPY + CMPSZY. Page 2350 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.4.7 Section 39 Display Out Comparison Unit CRC Calculation Time Period and Comparison Timing Figure 39.4 shows the CRC calculation time period and timing of comparing the calculated result with the expected value. (1) The CMPR bit is set to 1. 1 frame Vertical valid period VE (internal signal)*1 Blanking Blanking 1 line 1 line 1 line Horizontal valid period HE (internal signal)*2 Rectangular area valid period (internal signal) (2) CRC code calculation period Internal CRC code (3) Comparison Expected CRC code Expected CRC code Comparison timing (internal signal) CMPST bit (4) Mismatch Notes: 1. Enabled for the time period equivalent to vertical size of graphics data. 2. Enabled for the time period equivalent to horizontal size of graphics data. Figure 39.4 CRC Calculation Time Period and Timing of Comparing the Calculated Result with the Expected Value [Operation] (1) The operation starts at the next frame after the CMPR bit in DOCMCR is set to 1. For the register update timing, see section 39.4.8, Register Update Timing. (2) CRC code is calculated in the set rectangular area. (3) The CRC code calculation result is compared with the expected CRC code value (DOCMECRCR) at the end of the valid period of the graphics data. (4) If the compared CRC codes do not match, the CMPST bit in DOCMSTR is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2351 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit 39.4.8 (1) Register Update Timing Timing when Register Values are Loaded Inside All the register bits except the CMPR bit in DOCMCR are loaded inside immediately after the registers are written to. Thus, if the register is updated with the CMPRU bit in DOCMCR as 1, an unexpected result is likely to be obtained in the CRC code calculation. The registers that affect the CRC code calculation (i.e., registers other than DOCMCLSTR and DOCMIENR) should be updated after confirming that the CMPRU bit in DOCMCR is 0. The CMPR bit in DOCMCR is loaded inside upon detection of the start of the valid period of the graphics data. Thus, even if the register is rewritten to in the middle of a frame, the CRC code calculation of the frame does not get affected. (2) Timing when Internal State is Reflected in Registers The internal state is reflected in DOCMSTR and DOCMCCRCR at the end of the valid period of the graphics data. The internal state of the CMPR bit is reflected in the CMPRU bit in DOCMCR at the start of the valid period of the graphics data. Figure 39.5 shows the register update timing. The CMPR bit is set to 1. (1) The CMPR bit is set to 0. (3) Frame 1 Vertical valid period VE (internal signal)* Blanking Frame 2 Blanking Frame 3 Blanking CMPR bit Update (2) Update (4) CMPRU bit CMPR update (internal signal) Calculated CRC code (internal signal) DOCMSTR DOCMCCRCR CRC code 1 CRC code 2 Update (5) CRC code 1 Update (5) CRC code 2 Register update (internal signal) CRC calculation period Note: Enabled for the time period equivalent to vertical size of graphics data. Figure 39.5 Register Update Timing Page 2352 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit [Operation] (1) The CMPR bit is set to 1. This bit is not immediately loaded inside. (2) CRC calculation is carried out after the CMPR bit value is loaded inside upon detection of the start of the valid period of the graphics data. (3) To suspend the CRC comparison, the CMPR bit is set to 0. Similarly to (1), this bit is not immediately loaded inside. (4) The CRC calculation is suspended after the CMPR bit value is loaded inside upon detection of the start of the valid period of the graphics data. (5) The internal state is reflected in the register at the end of the valid period of the graphics data. 39.4.9 (1) Operation Flow Procedure for Starting Display Out Comparison Figure 39.6 shows a sample procedure for starting the display out comparison. Start setting. Set all the bits except the CMPR bit in DOCMCR. • The values are immediately loaded inside. Set the CMPR bit in DOCMCR to 1. No Has the start of valid period of the graphics data been detected? • Hardware process Yes Start display out comparison. Figure 39.6 Sample Procedure for Starting the Display Out Comparison R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2353 of 3092 SH7268 Group, SH7269 Group Section 39 Display Out Comparison Unit (2) Procedure for Changing Register Setting Figure 39.7 shows a sample procedure for changing the register setting during display out comparison. Start setting. Set the CMPR bit in DOCMCR to 0. No Is the CMPRU bit in DOCMCR 0? • Check that the CMPRU is set to 0 before modifying the register value. Yes Set all the bits except the CMPR bit in DOCMCR. • The values are immediately loaded inside. Set the CMPR bit in DOCMCR to 1. Has the start of valid period of the graphics data been detected? No • Hardware process Yes Start display out comparison. Figure 39.7 Sample Procedure for Changing the Register Setting during Display Out Comparison Page 2354 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 39.5 Section 39 Display Out Comparison Unit Interrupt The display out comparison mismatch detection interrupt is provided as an interrupt source. The interrupt request is generated when the CMPIEN bit in DOCMIENR and the CMPST bit in DOCMSTR are both set to 1. The CMPST bit should be cleared from within the interrupt service routine. However, withdrawing the interrupt request from the CPU after clearing of the CMPST bit takes a fixed amount of time. Thus, avoid erroneous acceptance of the interrupt for which the source bit should have been cleared by checking twice to ensure that the CMPST bit is actually clear, and only then issue the RTE instruction. 39.6 Usage Note 39.6.1 Expected CRC Value When graphics plane 1 to graphics plane 3 are selected, the expected CRC code value (DOCMECRCR) should be calculated from the graphics data to be used by using the software. When the graphics data after  blending is selected, the graphics data after  blending should be selected at the time of debugging and the calculated CRC code value read from DOCMCCRCR should be used as the expected CRC code value. This is because there is a possibility of mismatching of the result of superimposition of the graphics data by the software and the result of superimposition by the graphics display module due to an error in calculation when the graphics data after  blending is selected. 39.6.2 Expansion Control Functionality When scaling settings are applied for expansion processing by video display controller 4, this module becomes incapable of generating CRC codes. Stop this module while expansion processing is being applied. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2355 of 3092 Section 39 Display Out Comparison Unit Page 2356 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 40 OpenVG-Compliant Renesas Graphics Processor Section 40 OpenVG-Compliant Renesas Graphics Processor 40.1 Specification This processor supports OpenVG1.1, an open source 2D vector graphics API. Dedicated hardware and a programmable shader are used to accelerate OpenVG Stage 2 to Stage 8 processing. Please refer to the Khronos Group Web site for the specifications of OpenVG1.1. 40.2 Usage Note When using the OpenVG graphics processor and JPEG codec unit at the same time, it is necessary to implement exclusive bus access control in software to ensure that they do not access the bus simultaneously. Operation cannot be guaranteed if the OpenVG graphics processor and JPEG codec unit access the bus simultaneously. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2357 of 3092 Section 40 OpenVG-Compliant Renesas Graphics Processor Page 2358 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Section 41 JPEG Codec Unit The JPEG codec unit incorporates a JPEG codec conforming to the JPEG baseline compression and decompression standard to provide high-speed compression of image data and high-speed decoding of JPEG data. 41.1 Features The JPEG codec unit has the following features:  Conforms to the JPEG baseline standard within the range described in this document. This module does not support the following basic features: Scanning with two elements Non-interleave scanning with multiple elements  Operational precision: Conforming to JPEG Part 2, ISO-IEC10918-2  Image input/output system: Block interleave method  Pixel format: Compression: YCbCr422 (H = 2:1:1, V = 1:1:1) Decompression: YCbCr444 (H = 1:1:1, V = 1:1:1), YCbCr422 (H = 2:1:1, V = 1:1:1), YCbCr411 (H = 4:1:1, V = 1:1:1), YCbCr420 (H = 2:1:1, V = 2:1:1) Output pixel format to the buffer: YCbCr422, ARGB8888, RGB565  Four quantization tables provided  Four Huffman tables provided (two tables for AC coefficients and two tables for DC coefficients)  Markers supported: SOI (start of image), SOF0 (start of frame type 0), SOS (start of scan), DQT (define quantization tables), DHT (define Huffman tables), DRI (define restart interval), RSTm (restart marks), and EOI (end of image)  Image data rate: Max. 133.34 Mbytes/s (at 66.67-MHz operation)  The buffer size can be reduced by using the mode in which data transfer is temporarily stopped each time the specified number of lines or the specified amount of data is transferred during image data input/output or coded data input.  Processing unit: 8-byte address boundary units can be set  Image sizes that can be processed: Sizes divisible by the minimum coded unit (MCU): 8 lines by 8 pixels in YCbCr444; 8 lines by 16 pixels in YCbCr422; 8 lines by 32 pixels in YCbCr411; 16 lines by 16 pixels in YCbCr420 Note: Compression and decompression processing of images in unsupported pixel formats or unsupported image sizes should be avoided. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2359 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Figure 41.1 shows a block diagram. Internal graphics bus (RGP1-BUS) Internal graphics bus (RGP2-BUS) JPEG codec unit JPEG core DCT, quantizer Huffman coder marker processing Quantization table Huffman table Data input bus interface Data output bus interface Control circuit, JPEG core registers Output bus control register Input bus control register Module data bus Bus interface Peripheral bus 1 Figure 41.1 Block Diagram Page 2360 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.2 Section 41 JPEG Codec Unit Register Descriptions Table 41.1 shows the register configuration. Table 41.1 Register Configuration Register Name Abbreviation R/W Address Access Size JPEG code mode register JCMOD R/W H'E801 7000 8 JPEG code command register JCCMD R/W H'E801 7001 8 JPEG code quantization table number register JCQTN R/W H'E801 7003 8 JPEG code Huffman table number register JCHTN R/W H'E801 7004 8 JPEG code DRI upper register JCDRIU R/W H'E801 7005 8 JPEG code DRI lower register JCDRID R/W H'E801 7006 8 JPEG code vertical size upper register JCVSZU R/W H'E801 7007 8 JPEG code vertical size lower register JCVSZD R/W H'E801 7008 8 JPEG code horizontal size upper register JCHSZU R/W H'E801 7009 8 JPEG code horizontal size lower register JCHSZD R/W H'E801 700A 8 JPEG code data count upper register JCDTCU R H'E801 700B 8 JPEG code data count middle register JCDTCM R H'E801 700C 8 JPEG code data count lower register JCDTCD R H'E801 700D 8 JPEG interrupt enable register 0 JINTE0 R/W H'E801 700E 8 JPEG interrupt status register 0 JINTS0 R/W H'E801 700F 8 JPEG code decode error register JCDERR R/W H'E801 7010 8 JPEG code reset register JCRST R H'E801 7011 8 JPEG interface compression control register JIFECNT R/W H'E801 7040 32 JPEG interface compression source address register JIFESA R/W H'E801 7044 32 JPEG interface compression line offset register JIFESOFST R/W H'E801 7048 32 JPEG interface compression destination address register JIFEDA R/W H'E801 704C 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2361 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Register Name Abbreviation R/W Address Access Size JPEG interface compression source line count register JIFESLC R/W H'E801 7050 32 JPEG interface decompression control register JIFDCNT R/W H'E801 7058 32 JPEG interface decompression source address register JIFDSA R/W H'E801 705C 32 JPEG interface decompression destination offset register JIFDDOFST R/W H'E801 7060 32 JPEG interface decompression destination address register JIFDDA R/W H'E801 7064 32 JPEG interface decompression source count register JIFDSDC R/W H'E801 7068 32 JPEG interface decompression destination line count register JIFDDLC R/W H'E801 706C 32 JPEG interface decompression  setting register JIFDADT R/W H'E801 7070 32 JPEG interrupt enable register 1 JINTE1 R/W H'E801 708C 32 JPEG interrupt status register 1 JINTS1 R/W H'E801 7090 32 JPEG code quantization table 0 register JCQTBL0 R/W H'E801 7100 to H'E801 713F 8 JPEG code quantization table 1 register JCQTBL1 R/W H'E801 7140 to H'E801 717F 8 JPEG code quantization table 2 register JCQTBL2 R/W H'E801 7180 to H'E801 71BF 8 JPEG code quantization table 3 register JCQTBL3 R/W H'E801 71C0 to H'E801 71FF 8 JPEG code Huffman table DC0 register JCHTBD0 W H'E801 7200 to H'E801 721B 8 JPEG code Huffman table AC0 register JCHTBA0 W H'E801 7220 to H'E801 72D1 8 JPEG code Huffman table DC1 register JCHTBD1 W H'E801 7300 to H'E801 731B 8 JPEG code Huffman table AC1 register JCHTBA1 W H'E801 7320 to H'E801 73D1 8 Note: For the settings of the JPEG code quantization table and JPEG code Huffman table, see section 41.3.1 (4), Table Setting. Page 2362 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.2.1 Section 41 JPEG Codec Unit JPEG Code Mode Register (JCMOD) JCMOD sets the operating mode before this module starts operation. Bit: 7 6 5 4 3 — — — — DSP 0 R R 0 R R 0 R R 0 R R 0 R/W R/W Initial value: R/W(compress): R/W(decompress): 2 1 0 REDU[2:0] 0 R/W R 0 R/W R 0 R/W R R/W Bit Bit Name Initial Value 7 to 4  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 3 DSP 0 R/W Compression/Decompression Set 0: Compression process 1: Decompression process Note: When changing between processing for compression and for decompression, be sure to reset this module in advance by setting the JCUSRST bit in the software reset control register 2 (SWRSTCR2) of the power-down modes. 2 to 0 REDU[2:0] 000 R/W R Pixel Format [Compression] 001: YCbCr422 Other than above: Setting prohibited. [Decompression] 000: YCbCr444 001: YCbCr422 110: YCbCr411 010: YCbCr420 Other than above: Error (this module cannot process normally.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2363 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.2 JPEG Code Command Register (JCCMD) JCCMD sets commands. Bits of this register need not be cleared to 0 after setting a command. Multiple commands must not be set simultaneously. Bit: 7 6 5 4 3 BRST — — — — JEND JRST JSRT 2 1 0 Initial value: 0 R/W(compres): R*/W R/W(decompress): R*/W 0 R R 0 R R 0 R R 0 R R 0 0 0 R*/W Undefined R*/W R*/W R*/W R*/W Note: * Values read from these bits are undefined. R/W Bit Bit Name Initial Value 7 BRST 0 DeCompression compression R*/W Description Bus Reset Setting this bit to 1 resets the internal circuits. While this module is in operation (from setting the JPEG core process start command to writing the last output coded/image data), do not set this bit to 1. For the bus reset processing, see section 41.5, Bus Reset Processing. 6 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 JEND 0 R*/W Interrupt Request Clear Command This bit is valid only for the interrupt sources corresponding to bits INS6, INS5, and INS3 in JINTS0. To clear an interrupt request, set this bit to 1. Page 2364 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 1 JRST 0 Invalid JPEG Core Process Stop Clear Command De- R*/W To clear the process-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0), set this bit to 1. 0 JSRT 0 R*/W JPEG Core Process Start Command To start JPEG core processing, set this bit to 1. Do not write this bit to 1 again while this module is in operation. Note: * Values read from these bits are undefined. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2365 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.3 JPEG Code Quantization Table Number Register (JCQTN) JCQTN sets the quantization table number before compression process is started.     To use quantization table No. 0 (JCQTBL0) as the first color component, set QT1 to B'00 To use quantization table No. 1 (JCQTBL1) as the first color component, set QT1 to B'01 To use quantization table No. 2 (JCQTBL2) as the first color component, set QT1 to B'10 To use quantization table No. 3 (JCQTBL3) as the first color component, set QT1 to B'11 Bit: Initial value: R/W(compress): R/W(decompress): 7 6 5 — — QT3[1:0] 0 R R 0 R R 0 R/W R 4 0 R/W R 3 2 1 QT2[1:0] 0 R/W R 0 R/W R 0 QT1[1:0] 0 R/W R 0 R/W R R/W Bit Bit Name Initial Value 7, 6  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 5, 4 QT3[1:0] 00 R/W R Quantization table number for the third color component 3, 2 QT2[1:0] 00 R/W R 1, 0 QT1[1:0] 00 R/W R Quantization table number for the second color component Quantization table number for the first color component Page 2366 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.2.4 Section 41 JPEG Codec Unit JPEG Code Huffman Table Number Register (JCHTN) JCHTN sets the Huffman table number (AC/DC) before compression process is started.  To use DC/AC Huffman table No. 0 (JCHTBD0 and JCHTBA0) as the first color component, set bits HTA1 and HTD1 to B'0  To use DC/AC Huffman table No. 1 (JCHTBD1 and JCHTBA1) as the first color component, set bits HTA1 and HTD1 to B'1 Bit: Initial value: R/W(compress): R/W(decompress): 7 6 — — HTA3 HTD3 HTA2 HTD2 HTA1 HTD1 5 4 0 R R 0 R R 0 R/W R 0 R/W R 3 0 R/W R 2 0 R/W R 1 0 R/W R 0 0 R/W R R/W Bit Bit Name Initial Value 7, 6  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 5 HTA3 0 R/W R Huffman table number (AC) for the third color component 4 HTD3 0 R/W R Huffman table number (DC) for the third color component 3 HTA2 0 R/W R Huffman table number (AC) for the second color component 2 HTD2 0 R/W R Huffman table number (DC) for the second color component 1 HTA1 0 R/W R Huffman table number (AC) for the first color component 0 HTD1 0 R/W R Huffman table number (DC) for the first color component R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2367 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.5 JPEG Code DRI Upper Register (JCDRIU) JCDRIU sets the upper bytes of the minimum coded units (MCUs) preceding an RST marker. Bit: 7 6 5 4 3 2 1 0 DRIU[7:0] Initial value: 0 0 0 0 0 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value Compression compression Description 7 to 0 DRIU[7:0] H'00 R/W Upper Bytes of MCUs Preceding RST Marker De- Invalid When both upper and lower bytes are set to H'00, neither a DRI nor an RST marker is placed. Page 2368 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.2.6 Section 41 JPEG Codec Unit JPEG Code DRI Lower Register (JCDRID) JCDRID sets the lower bytes of MCUs preceding an RST marker. Bit: 7 6 5 4 3 2 1 0 DRID[7:0] Initial value: 0 0 0 0 0 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value Compression compression Description 7 to 0 DRID[7:0] H'00 R/W Lower Bytes of MCUs Preceding RST Marker De- Invalid When both upper and lower bytes are set to H'00, neither a DRI nor an RST marker is placed. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2369 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.7 JPEG Code Vertical Size Upper Register (JCVSZU) JCVSZU sets the upper bytes of the vertical image size. Bit: 7 6 5 4 3 2 1 0 0 R/W R 0 R/W R 0 R/W R VSZU[7:0] Initial value: 0 R/W(compress): R/W R/W(decompress): R 0 R/W R 0 R/W R 0 R/W R 0 R/W R R/W Initial Value Bit Bit Name 7 to 0 VSZU[7:0] H'00 DeCompression compression Description R/W Upper Bytes of Vertical Image Size R In decompression process, a downloaded value from the JPEG coded data is set. Page 2370 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.2.8 Section 41 JPEG Codec Unit JPEG Code Vertical Size Lower Register (JCVSZD) JCVSZD sets the lower bytes of the vertical image size. Bit: 7 6 5 4 3 2 1 0 0 R/W R 0 R/W R 0 R/W R VSZD[7:0] Initial value: 0 R/W(compress): R/W R/W(decompress): R 0 R/W R 0 R/W R 0 R/W R 0 R/W R R/W Initial Value Bit Bit Name 7 to 0 VSZD[7:0] H'00 DeCompression compression Description R/W Lower Bytes of Vertical Image Size R In decompression process, a downloaded value from the JPEG coded data is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2371 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.9 JPEG Code Horizontal Size Upper Register (JCHSZU) JCHSZU sets the upper bytes of the horizontal image size. Bit: 7 6 5 4 3 2 1 0 0 R/W R 0 R/W R 0 R/W R HSZU[7:0] Initial value: 0 R/W(compress): R/W R/W(decompress): R 0 R/W R 0 R/W R 0 R/W R 0 R/W R R/W Initial Value Bit Bit Name 7 to 0 HSZU[7:0] H'00 DeCompression compression Description R/W Upper Bytes of Horizontal Image Size R In decompression process, a downloaded value from the JPEG coded data is set. Page 2372 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.10 JPEG Coded Horizontal Size Lower Register (JCHSZD) JCHSZD sets the lower bytes of the horizontal image size. Bit: 7 6 5 4 3 2 1 0 0 R/W R 0 R/W R 0 R/W R HSZD[7:0] Initial value: 0 R/W(compress): R/W R/W(decompress): R 0 R/W R 0 R/W R 0 R/W R 0 R/W R R/W Initial Value Bit Bit Name 7 to 0 HSZD[7:0] H'00 DeCompression compression Description R/W Lower Bytes of Horizontal Image Size R In decompression process, a downloaded value from the JPEG coded data is set. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2373 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.11 JPEG Code Data Count Upper Register (JCDTCU) The upper bytes for the counted amount of data to be compressed are set to JCDTCU. The values of this register are reset before compression starts. Bit: 7 6 5 4 3 2 1 0 DCU[7:0] Initial value: 0 0 0 0 0 0 0 0 R/W(compress): R R R R R R R R R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value Compression compression Description 7 to 0 DCU[7:0] H'00 R Upper bytes of the counted amount of data to be compressed Page 2374 of 3092 De- Invalid R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.12 JPEG Code Data Count Middle Register (JCDTCM) The middle bytes for the counted amount of data to be compressed are set to JCDTCM. The values of this register are reset before compression starts. Bit: 7 6 5 4 3 2 1 0 DCM[7:0] Initial value: 0 0 0 0 0 0 0 0 R/W(compress): R R R R R R R R R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value Compression compression Description 7 to 0 DCM[7:0] H'00 R Middle bytes of the counted amount of data to be compressed R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 De- Invalid Page 2375 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.13 JPEG Code Data Count Lower Register (JCDTCD) The lower bytes for the counted amount of data to be compressed are set to JCDTCD. The values of this register are reset before compression starts. Bit: 7 6 5 4 3 2 1 0 DCD[7:0] Initial value: 0 0 0 0 0 0 0 0 R/W(compress): R R R R R R R R R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name Initial Value Compression compression Description 7 to 0 DCD[7:0] H'00 R Lower bytes of the counted amount of data to be compressed Page 2376 of 3092 De- Invalid R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.14 JPEG Interrupt Enable Register 0 (JINTE0) JINTE0 enables interrupts. When any of bits INT7 to INT5 is set to B'1, the INS5 bit in JINTS0 indicates B'1 as the error status upon occurrence of the compression data error, and the ERR bit in JCDERR indicates the particular error code. Bit: 7 INT7 6 5 INT6 INT5 Initial value: 0 0 0 R/W(compress): Undefined Undefined Undefined R/W(decompress): R/W R/W R/W 4 3 2 1 0 — INT3 — — — 0 R R 0 Undefined 0 R R 0 R R 0 R R R/W R/W Bit Bit Name Initial Value Compression compression Description 7 INT7 0 Invalid This bit enables an interrupt to be generated when the number of data in the restart interval of the Huffman-coding segment is not correct in decompression. De- R/W When this bit is not set to enable interrupt generation, an error code is not returned. 6 INT6 0 Invalid R/W This bit enables an interrupt to be generated when the total number of data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. 5 INT5 0 Invalid R/W This bit enables an interrupt to be generated when the final number of MCU data in the Huffman-coding segment is not correct in decompression. When this bit is not set to enable interrupt generation, an error code is not returned. 4  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2377 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 3 INT3 0 Invalid This bit enables an interrupt to be generated when it has been determined that the image size and the subsampling setting of the compressed data can be read through analyzing the data. 2 to 0  All 0 De- R/W R Reserved These bits are always read as 0. The write value should always be 0. Page 2378 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.15 JPEG Interrupt Status Register 0 (JINTS0) JINTS0 identifies the interrupt sources. The interrupt sources of this register should be cleared by clearing the corresponding interrupt status bits to 0 and setting the relevant bit in JCCMD appropriately. Bit: Initial value: R/W(compress): R/W(decompress): 4 3 2 1 0 — 7 INS6 INS5 6 5 — INS3 — — — 0 R R 0 0 R/W* Undefined R/W* R/W* 0 R R 0 Undefined 0 R R 0 R R 0 R R R/W* Note: * Clear this bit by writing 0 to it. Do not write 1 to this bit. R/W Bit Bit Name Initial Value 7  0 DeCompression compression R Description Reserved This bit is always read as 0. The write value should always be 0. 6 INS6 0 5 INS5 0 4  0 R/W* Invalid R/W* R This bit is set to 1 when this module completes compression process normally. This bit is set to 1 when a compressed data error occurs. Reserved This bit is always read as 0. The write value should always be 0. 3 INS3 0 2 to 0  All 0 Invalid R/W* R This bit is set to 1 when the image size and pixel format can be read. When an interrupt occurs, this module stops processing and the state is indicated by the JCRST register. To make this module resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. Reserved These bits are always read as 0. The write value should always be 0. Note: * Clear this bit by writing 0 to it. Do not write 1 to this bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2379 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.16 JPEG Code Decode Error Register (JCDERR) JCDERR indicates the error code to identify the type of the error which has occurred in the compressed data analysis for decompression. The values of this register are reset before this module starts decompression. Bit: Initial value: R/W(compress): R/W(decompress): 7 6 5 4 — — — — 3 ERR[3:0] 0 R R 0 R R 0 R R 0 R R Undefined Undefined Undefined Undefined 1 R/W 2 1 0 R/W 1 R/W 0 0 R/W R/W Bit Bit Name Initial Value 7 to 4  All 0 DeCompression compression R Description Reserved These bits are always read as 0. 3 to 0 ERR[3:0] 1010 Invalid R/W Error Code (See tables 41.3 and 41.4.) Page 2380 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.17 JPEG Code Reset Register (JCRST) JCRST indicates a processing-stopped state caused by requests to read the image size and pixel format (enabled by the INT3 bit in JINTE0). To resume processing, set the JPEG core process stop clear command bit (JRST) in JCCMD. Bit: Initial value: R/W(compress): R/W(decompress): 7 6 5 4 3 2 1 0 — — — — — — — RST 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Undefined 0 R R/W Bit Bit Name Initial Value 7 to 1  All 0 DeCompression compression R Description Reserved These bits are always read as 0. 0 RST 0 Invalid R Operating State 0: State other than below 1: Suspended state caused by interrupt sources of JINTE0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2381 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.18 JPEG Interface Compression Control Register (JIFECNT) JIFECNT controls the compression process. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 2 1 0 — — — — — JOUTSWAP[2:0] 0 R R 0 R R 0 R R 0 R R 0 R R Initial value: R/W(compress): R/W(decompress): Initial value: R/W(compress): R/W(decompress): 0 R/W 0 R/W 0 R/W Undefined Undefined Undefined 7 6 5 4 3 — DIN RINI DIN RCMD DIN LC — 0 R/W 0 R/W 0 R/W 0 R R Undefined Undefined Undefined 0 R R DINSWAP[2:0] 0 R/W 0 R/W 0 R/W Undefined Undefined Undefined R/W Bit Bit Name 31 to 11  Initial Value DeCompression compression All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 JOUTSWA 000 P[2:0] R/W Invalid Byte/Word/Longword Swap Output coded data in compression is swapped. 000: (1) (2) (3) (4) (5) (6) (7) (8) 001: (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 010: (3) (4) (1) (2) (7) (8) (5) (6) [Word swap] 011: (4) (3) (2) (1) (8) (7) (6) (5) [Word - byte swap] 100: (5) (6) (7) (8) (1) (2) (3) (4) [Longword swap] 101: (6) (5) (8) (7) (2) (1) (4) (3) [Longword - byte swap] 110: (7) (8) (5) (6) (3) (4) (1) (2) [Longword - word swap] 111: (8) (7) (6) (5) (4) (3) (2) (1) [Longword - word - byte swap] 7  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 2382 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 6 DINRINI 0 R/W Address Initialization when Resuming Input of Image Data Lines De- Invalid This bit is only valid when the count mode for stopping the input of image data lines is on. Set this bit before writing 1 to the dataline resume command bit. 0: The transfer address is not initialized when the input of image data lines is restarted. 1: The transfer address is initialized when the input of image data lines is restarted. 5 DINRCMD 0 R/W Invalid Input Image Data Lines Resume Command This bit is valid only when the count mode for stopping the input of image data lines is on. Setting this bit to 1 resumes reading input image data. This bit is always read as 0. 4 DINLC 0 R/W Invalid Count Mode Setting for Stopping Input Image Data Lines 0: Count mode for stopping the input of image data lines is off. 1: Count mode for stopping the input of image data lines is on. 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2383 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Initial Value Bit Bit Name 2 to 0 DINSWAP 000 [2:0] DeCompression compression Description R/W Byte/Word Swap Invalid Input image data in compression is swapped. 000: (1) (2) (3) (4) (5) (6) (7) (8) 001: (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 010: (3) (4) (1) (2) (7) (8) (5) (6) [Word swap] 011: (4) (3) (2) (1) (8) (7) (6) (5) [Word - byte swap] 100: (5) (6) (7) (8) (1) (2) (3) (4) [Longword swap] 101: (6) (5) (8) (7) (2) (1) (4) (3) [Longword - byte swap] 110: (7) (8) (5) (6) (3) (4) (1) (2) [Longword - word swap] 111: (8) (7) (6) (5) (4) (3) (2) (1) [Longword - word - byte swap] Page 2384 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.19 JPEG Interface Compression Source Address Register (JIFESA) JIFESA sets the source address of the input image data. This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ESA[31:16] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ESA[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name 31 to 3 ESA[31:3] 2 to 0 ESA[2:0] Initial Value H'0000 0000 DeCompression compression Description R/W Input Image Data Source Address (in 8byte units) R Invalid The lower three bits should be set to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2385 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.20 JPEG Interface Compression Line Offset Register (JIFESOFST) JIFESOFST sets the line offset of the input image data (refer to section 41.3.4, Storing Image Data). This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R Initial value: R/W(compress): R/W(decompress): — Initial value: R/W(compress): R/W(decompress): 0 R R ESMW[14:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name 31 to 15  Initial Value DeCompression compression All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 14 to 3 ESMW [14:3] 2 to 0 ESMW[2:0] Page 2386 of 3092 H'0000 R/W R Invalid Input Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.21 JPEG Interface Compression Destination Address Register (JIFEDA) JIFEDA sets the destination address of the output coded data. This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EDA[31:16] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EDA[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name 31 to 3 EDA[31:3] 2 to 0 EDA[2:0] Initial Value H'0000 0000 DeCompression compression Description R/W Output Coded Data Destination Address (in 8-byte units) R Invalid The lower three bits should be set to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2387 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.22 JPEG Interface Compression Source Line Count Register (JIFESLC) JIFESLC sets the number of input image data lines when the count mode for stopping the input of image data lines is on (the DINLC bit in JIFECNT is set to 1). This register should be set in 8-line units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W(compress): R/W(decompress): LINES[15:0] Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 R/W(compress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W(decompress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W Bit Bit Name 31 to 16  Initial Value DeCompression compression H'FFF8 R Description Reserved Values read from these bits are undefined. The write value should always be 0. 15 to 3 LINES[15:3] H'FFF8 R/W 2 to 0 LINES[2:0] R Invalid Number of Input Image Data Lines to be Read (in 8-line units) The lower three bits should be set to 0. Page 2388 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.23 JPEG Interface Decompression Control Register (JIFDCNT) JIFDCNT controls the decompression process. Bit: 31 30 — — 0 R R 0 R R Initial value: R/W(compress): R/W(decompress): Bit: 15 — Initial value: R/W(compress): R/W(decompress): 0 R R 29 28 27 26 25 VINTER[1:0] HINTER[1:0] 0 0 0 24 23 22 21 20 19 18 17 16 OPF[1:0] — — — — — — — — 0 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 1 0 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W 14 13 12 JINR JINR JINC INI CMD 0 0 0 Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W 11 10 9 8 7 — JINSWAP[2:0] — 0 R R 0 Undefined Undefined Undefined 0 R R 0 R/W R/W 0 R/W 6 5 4 DOUT DOUT DOUT RINI RCMD LD 0 0 0 Undefined Undefined Undefined R/W R/W R/W 3 2 — DOUTSWAP[2:0] 0 R R Undefined Undefined Undefined 0 R/W 0 R/W 0 R/W R/W Bit Bit Name Initial Value 31, 30  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 29, 28 VINTER [1:0] 00 Invalid R/W Vertical Subsampling Subsamples vertical output image data. 00: No subsampling 01: Subsamples output data into 1/2. 10: Subsamples output data into 1/4. 11: Subsamples output data into 1/8. 27, 26 HINTER [1:0] 00 Invalid R/W Horizontal Subsampling Subsamples horizontal output image data. 00: No subsampling 01: Subsamples output data into 1/2. 10: Subsamples output data into 1/4. 11: Subsamples output data into 1/8. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2389 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 25, 24 OPF[1:0] 00 Invalid Specifies output image data pixel format. De- R/W 00: YCbCr422 01: ARGB8888 10: RGB565 11: Setting prohibited 23 to 15  14 JINRINI All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 Invalid R/W Address Initialization when Input Coded Data is Resumed This bit is only valid when the count mode for stopping the input of coded data is on. Set this bit before writing 1 to the data resume command bit. 0: The transfer address is not initialized when the input of coded data is restarted. 1: The transfer address is initialized when the input of coded data is restarted. 13 JINRCMD 0 Invalid R/W Input Coded Data Resume Command This bit is valid only when the count mode for stopping the input of coded data is on. Setting this bit to 1 resumes reading input coded data. This bit is always read as 0. 12 JINC 0 Invalid R/W Count Mode Setting for Stopping Input Coded Data 0: Count mode for stopping the input of coded data is off. 1: Count mode for stopping the input of coded data is on. Page 2390 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value 11  0 DeCompression compression R Description Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 JINSWAP [2:0] 000 Invalid R/W Byte/Word/Longword Swap Input coded data in decompression is swapped. 000: (1) (2) (3) (4) (5) (6) (7) (8) 001: (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 010: (3) (4) (1) (2) (7) (8) (5) (6) [Word swap] 011: (4) (3) (2) (1) (8) (7) (6) (5) [Word - byte swap] 100: (5) (6) (7) (8) (1) (2) (3) (4) [Longword swap] 101: (6) (5) (8) (7) (2) (1) (4) (3) [Longword - byte swap] 110: (7) (8) (5) (6) (3) (4) (1) (2) [Longword - word swap] 111: (8) (7) (6) (5) (4) (3) (2) (1) [Longword - word - byte swap] 7  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2391 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 6 DOUTRINI 0 Invalid Address Initialization when Resuming Output of Image Data Lines De- R/W This bit is only valid when the count mode for stopping the output of image data lines is on. Set this bit before writing 1 to the dataline resume command bit. 0: The transfer address is not initialized when the output of lines of image data is restarted. 1: The transfer address is initialized when the output of lines of image data is restarted. 5 DOUTRCMD 0 Invalid R/W Output Image Data Lines Resume Command This bit is valid only when the count mode for stopping the output of image data lines is on. Setting this bit to 1 resumes writing image data. This bit is always read as 0. 4 DOUTLC 0 Invalid R/W Count Mode for Stopping Output Image Data Lines 0: Count mode for stopping the output of image data lines is off. 1: Count mode for stopping the output of image data lines is on. 3  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 2392 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Initial Value Bit Bit Name 2 to 0 DOUTSWAP 000 [2:0] DeCompression compression Description Invalid Byte/Word Swap R/W Output image data in decompression is swapped. 000: (1) (2) (3) (4) (5) (6) (7) (8) 001: (2) (1) (4) (3) (6) (5) (8) (7) [Byte swap] 010: (3) (4) (1) (2) (7) (8) (5) (6) [Word swap] 011: (4) (3) (2) (1) (8) (7) (6) (5) [Word - byte swap] 100: (5) (6) (7) (8) (1) (2) (3) (4) [Longword swap] 101: (6) (5) (8) (7) (2) (1) (4) (3) [Longword - byte swap] 110: (7) (8) (5) (6) (3) (4) (1) (2) [Longword - word swap] 111: (8) (7) (6) (5) (4) (3) (2) (1) [Longword - word - byte swap] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2393 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.24 JPEG Interface Decompression Source Address Register (JIFDSA) JIFDSA sets the source address of the input coded data. This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DSA[31:16] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W(decompress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSA[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W(decompress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W Bit Bit Name 31 to 3 DSA[31:3] 2 to 0 DSA[2:0] Initial Value H'0000 0000 DeCompression compression Description Invalid Input Coded Data Source Address (in 8byte units) R/W R The lower three bits should be set to 0. Page 2394 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.25 JPEG Interface Decompression Line Offset Register (JIFDDOFST) JIFDDOFST sets the line offset of the output image data to be transferred to the external buffer (refer to section 41.3.4, Storing Image Data). This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value: R/W(compress): R/W(decompress): DDMW[14:0] — Initial value: R/W(compress): R/W(decompress): 0 R R 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W Bit Bit Name 31 to 15  Initial Value DeCompression All 0 compression R Description Reserved These bits are always read as 0. The write value should always be 0. 14 to 3 DDMW[14:3] 2 to 0 DDMW[2:0] H'0000 Invalid R/W R Output Image Data Lines Offset (in 8-byte units) The lower three bits should be set to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2395 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.26 JPEG Interface Decompression Destination Address Register (JIFDDA) JIFDDA sets the destination address of the output image data. This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DDA[31:16] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress):Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W(decompress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDA[15:0] Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W(compress):Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W(decompress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W Initial Value Bit Bit Name 31 to 3 DDA[31:3] H'0000 0000 DDA[2:0] 2 to 0 DeCompression compression Description Invalid Output Image Data Destination Address (in 8-byte units) R/W R The lower three bits should be set to 0. Page 2396 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.27 JPEG Interface Decompression Source Data Count Register (JIFDSDC) JIFDSDC sets the amount of input coded data when the count mode for stopping the input of coded data is on (the JINC bit in JIFDCNT is set to 1). This register should be set in 8-byte units. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W(compress): R/W(decompress): JDATAS[15:0] Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 R/W(compress):Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W(decompress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W Bit Bit Name 31 to 16  Initial Value DeCompression compression H'FFF8 R Description Reserved Values read from these bits are undefined. The write value should always be 0. 15 to 3 JDATAS[15:3] H'FFF8 2 to 0 JDATAS[2:0] Invalid R/W R Amount of Input Coded Data to be Read (in 8-byte units) The lower three bits should be set to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2397 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.28 JPEG Interface Decompression Destination Line Count Register (JIFDDLC) JIFDDLC sets the number of output image data lines when the count mode for stopping the output of image data lines is on (the DOUTLC bit in JIFECNT is set to 1). This register should be set such that that the output image data line count matches the MCU unit. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 1 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W(compress): R/W(decompress): LINES[15:0] Initial value: 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 R/W(compress): Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W(decompress): R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W Bit Bit Name 31 to 16  Initial Value DeCompression compression H'FFF8 R Description Reserved Values read from these bits are undefined. The write value should always be 0. 15 to 3 LINES[15:3] H'FFF8 Invalid R/W 2 to 0 LINES[2:0] R Set these bits to specify the number of lines of output image data to be written. Use a setting value such that that the output image data line count matches the MCU unit. For YCbCr444, YCbCr422, and YCbCr411 output, the setting value × 1 is equal to the output image data line count. For YCbCr420 output, the setting value × 2 is equal to the output image data line count. The lower three bits should be set to 0. Page 2398 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.29 JPEG Interface Decompression  Set Register (JIFDADT) JIFDADT is used to set the  value when output is in ARGB8888 format. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — ALPHA[7:0] 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial value: R/W(compress): R/W(decompress): Initial value: R/W(compress): R/W(decompress): 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W R/W R/W R/W Bit Bit Name Initial Value 31 to 8  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 ALPHA [7:0] H'00 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Invalid R/W Setting of the  value for output in ARGB8888 format. Page 2399 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.30 JPEG Interrupt Enable Register 1 (JINTE1) JINTE1 enables interrupts. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — CBTEN DIN LEN — — DOU DBTEN JINEN TLEN 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R/W 0 R/W 0 R R 0 R R Undefined Undefined Undefined Initial value: R/W(compress): R/W(decompress): Initial value: R/W(compress): R/W(decompress): Undefined Undefined 0 R/W 0 R/W 0 R/W R/W Bit Bit Name Initial Value 31 to 7  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 6 CBTEN 0 R/W Invalid Enables or disables a data transfer processing interrupt request (JDTI) when the CBTF bit in JINTS1 is set to 1. 0: Disables an interrupt request. 1: Enables an interrupt request. 5 DINLEN 0 R/W Invalid Enables or disables a data transfer processing interrupt request (JDTI) when the DINLF bit in JINTS1 is set to 1. 0: Disables an interrupt request. 1: Enables an interrupt request. 4, 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 DBTEN 0 Invalid R/W Enables or disables a data transfer processing interrupt request (JDTI) when the DBTF bit in JINTS1 is set to 1. 0: Disables an interrupt request. 1: Enables an interrupt request. Page 2400 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 1 JINEN 0 Invalid Enables or disables a data transfer processing interrupt request (JDTI) when the JINF bit in JINTS1 is set to 1. De- R/W 0: Disables an interrupt request. 1: Enables an interrupt request. 0 DOUTLEN 0 Invalid R/W Enables or disables a data transfer processing interrupt request (JDTI) when the DOUTLF bit in JINTS1 is set to 1. 0: Disables an interrupt request. 1: Enables an interrupt request. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2401 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.2.31 JPEG Interrupt Status Register 1 (JINTS1) JINTS1 indicates the interrupt sources. The interrupt sources of this register should be cleared by writing 0 to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — Initial value: R/W(compress): R/W(decompress): 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — CBTF DINLF — — DBTF JINF DOU TLF 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 R R 0 0 R/W* R/W* 0 R R 0 R R 0 0 0 Bit: Initial value: R/W(compress): R/W(decompress): Undefined Undefined Undefined Undefined Undefined R/W* R/W* R/W* Note: * When the bit is read as 1, write 0 to clear it. When the bit is read as 0, write 1 to it. R/W Bit Bit Name Initial Value 31 to 7  All 0 DeCompression compression R Description Reserved These bits are always read as 0. The write value should always be 0. 6 CBTF 0 R/W* Invalid This bit is set to 1 when the last output coded data is written in compression. 5 DINLF 0 R/W* Invalid This bit is set to 1 when the number of input image data lines indicated by JIFESLC is read in compression. This bit is valid only when the DINLC bit in JIFECNT is set to 1. 4, 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 DBTF Page 2402 of 3092 0 Invalid R/W* This bit is set to 1 when the last output image data is written in decompression. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit R/W Bit Bit Name Initial Value Compression compression Description 1 JINF 0 Invalid This bit is set to 1 when the amount of input coded data indicated by JIFDSDC is read in decompression. De- R/W* This bit is valid only when the JINC bit in JIFDCNT is set to 1. 0 DOUTLF 0 Invalid R/W* In decompression, this bit is set to 1 when the number of lines of output image data indicated by JIFDDLC have been written. This bit is only valid when the DOUTLC bit in JIFDCNT is set to 1. Note: * When the bit is read as 1, write 0 to clear it. When the bit is read as 0, write 1 to it. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2403 of 3092 Section 41 JPEG Codec Unit 41.3 Operation 41.3.1 Compression (1) SH7268 Group, SH7269 Group Overview of Processing The compression process flows are described below. 1. The JPEG core is activated. A marker is output. (After a marker is output, image data can be input.) Approximately 30,000 cycles (necessary for making SOI to SOS markers) 2. Image data is transferred in MCUs from the external buffer to this module. If the count mode for stopping the input of image data lines is on, reading is stopped each time the number of lines set in JIFESLC is read. Reading is resumed by setting the DINRCMD bit in JIFECNT to 1. When the DINRINI bit in JIFECNT is zero, the addresses for reading on resumption are continued from the addresses in the previous round of transfer. When the DINRINI bit is one, the address set in JIFESA is used on resumption. Reading is also stopped when one frame of image data is completely transferred. If the count mode for stopping the input of image data lines is off, reading is continued until one frame of image data is completely transferred. 3. Image data is input to the JPEG core. The input data is processed in MCUs at any time in the JPEG core. 4. Coded data is transferred from this module to the external buffer. 5. Compression is completed after one frame of data is processed completely. Page 2404 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit (2) Flowchart (Compression) (a) Initial Settings After completing the JPEG core settings and input/output buffer settings and transferring image data to the external buffer, activate this module by setting the JSRT bit in JCCMD to 1. After this module has been activated, the JPEG markers (SOI to SOS) are generated and output. It takes approximately 30,000 cycles to generate the markers. Start initial setting Software reset Set the JPEG core. Set the I/O buffer. Software reset Reset this module in advance by setting the JCURST bit in SWRSTCR2 of the power-down modes. JPEG core settings Pixel format setting: Compression setting: Quantization table number setting: Huffman table number setting: DRI setting: Vertical image size setting: Horizontal image size setting: Quantization table setting: Huffman table setting: REDU bits in JCMOD DSP bit in JCMOD JCQTN JCHTN JCDRIU, JCDRID JCVSZU, JCVSZD JCHSZU, JCHSZD JCQTBL0 to JCQTBL3 JCHTBD0, JCHTBD1, JCHTBA0, JCHTBA1 I/O buffer settings Byte/word/longword swap setting: Input data line stop count mode setting: Address initialization setting for resumption of input image data: Source address setting: Line offset setting: Destination address setting: Source line count setting: Interrupt settings: JOUTSWAP, DINSWAP bits in JIFECNT DINLC bit in JIFECNT DINRINI bit in JIFECNT JIFESA JIFESOFST JIFEDA JIFESLC CBTEN, DINLEN bits in JINTE1 Set the JSRT bit in JCCMD to 1. Initial setting completed Figure 41.2 Compression Initial Setting Flow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2405 of 3092 Section 41 JPEG Codec Unit (b) SH7268 Group, SH7269 Group Compression Process The compression process flows are described below.  When JPEG compression process has been completed, the INS6 bit in JINTS0 is set to 1. However, this module continues processing since the coded data remains to be transferred. The CBTF bit in JINTS1 is set to 1 when the last coded data is transferred. The interrupt source is cleared by writing 0 to the INS6 bit. However, the interrupt request asserted by this interrupt source cannot be cleared by writing 0 to the INS6 bit. Set an interrupt request clear command (by setting the JEND bit in JCCMD to 1) to clear the interrupt request.  When this module has completed compression and all coded data has been transferred, the CBTF flag in JINTS1 is set to 1. When the CBTEN bit in JINTE1 is 1 here, an interrupt is generated. The interrupt source is cleared by writing 0 to the CBTF flag.  If the count mode for stopping image data lines is on, when the specified number of image data lines set in JIFESLC has been read, the DINLF flag in JINTS1 is set to 1, and reading is stopped. When the DINLEN bit in JINTE1 is 1 here, an interrupt is generated. An interrupt source is cleared by writing 0 to the DINLEN bit. Setting the DINRCMD bit in JIFECNT to 1 resumes reading. When the DINRINI bit in JIFECNT is zero, the addresses for reading on resumption are continued from the addresses in the previous round of transfer. When the DINRINI bit is one, the address set in JIFESA is used on resumption. (c) Data Correction When after dividing the output coded data by 8 the remainder is 1 to 6 bytes, transfer of bytes 1 to 6 of the remainder may not complete successfully. If the transfer is unsuccessful, bytes 1 to 6 of the remainder are written to the address specified in the JPEG interface compression destination address register (JIFEDA), overwriting the existing data.* For this reason it is necessary to check whether the output coded data was transferred successfully and, if not, to perform data correction. Note: * This module handles the output of coded data in 16-bit units. For this reason, if the coded data has an odd code length, the final code output will be H'D9FF. (H'FF is appended.) When the remainder is 1, 3, or 5 bytes, the remainder data (1, 3, or 5 bytes) + H'FF is written to the address specified in JIFEDA, overwriting the existing data. Page 2406 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Output coded data Address specified in JIFEDA XX XX FF D9 The data that should have been written to the end address is instead written to the address specified in JIFEDA, overwriting the existing data. XX XX FF D9 Figure 41.3 Conceptual Diagram of Abnormal Transfer of Output Coded Data Start compression Is interrupt source generated? No Yes Is the INS6 flag in JINTS0 to 1? (JEDI) Set interrupt request clear command. Set the JEND bit in JCCMD to 1. Set input image data resume command. Set the DINRCMD bit in JIFECNT to 1. Clear the INS6 flag in JINTS0. Clear the DINLF flag in JINTS1. Yes No Yes Is the CBTF flag in JINTS1 to 1? (JDTI) Data Correction No DINLF = 1 (JDTI) Clear all the flags in JINTS1. Compression completed Figure 41.4 Compression Process Flow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2407 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Data correction start No Read JCDTCU, JCDTCM, and JCDTCD *1 [1] Read the compressed data volume from JCDTCU, JCDTCM, and JCDTCD. Remainder 1 to 6 bytes when compressed data volume / 8? *2 [2] Determine if after dividing the compressed data volume by 8 the remainder is 1 to 6 bytes. *3 [3] Based on the compressed data volume read in [1], read the data from the address to which the final coded data (0xFFD9) was written. *4 [4] Determine if the final coded data EOI (0xFFD9) was written. Read data from the address specified in JIFEDA *5 [5] Read from the address specified in JIFEDA the number of remainder data bytes calculated in [2]. Data from the address specified in JIFEDA matches expected value? *6 [6] Determine if the data read from the address specified in JIFEDA matches the expected value. This will be the beginning of the JPEG data, so the expected value will be 0xFFD8 (SIO), 0xFFDB (DQT), 0x00XX (XX: 0x84 for quantization table 2, 0xC5 for quantization table 3) Yes Read final coded data from storage RAM No Final coded data = 0xFFD9 (EOI)? Yes Yes No Correct final 1 to 6 bytes of data Correct data at address specified in JIFEDA *7 *8 [7] If transfer did not complete successfully, write the 1 to 6 bytes read in [6] to the end address. [8] Some data has been overwritten, so correct the data at the address specified in JIFEDA. Data correction end Note: If the coded data has an odd code length, the final code output will be H'D9FF. (H'FF is appended.) Therefore, when the remainder is 1, 3, or 5 bytes, is should be corrected to 2, 4, or 6 bytes of data, respectively. Figure 41.5 Data Correction Flowchart Page 2408 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 41 JPEG Codec Unit JPEG Coded Data Format Figure 41.6 shows the data output stream in compression. The amount of coded data from SOI to EOI is indicated by JCDTCU, JCDTCM, and JCDTCD. When both JCDRIU and JCDRID are set to H'0000 0000, the following markers are not output.  DRI marker  RST marker (in compressed image data) SOI DQT DRI SOF0 DHT SOS Encoded image EOI Figure 41.6 JPEG Coded Data Format DQT: DHT: SOF0: SOS: Not output for unused table. Output in order DC0, AC0, DC1, and AC1. Not output for unused table. Component identifiers are C1 = first color component, C2 = second color component, and C3 = third color component. Scan component selectors are CS1 = first color component, CS2 = second color component, and CS3 = third color component. Header Volume (Reference):  SOI: 2 bytes (FFD8)  DQT: 134 bytes when two quantization tables are used, 199 bytes when three quantization tables are used (65 bytes/table increase or decrease)  DRI: 6 bytes  SOF0: 19 bytes (4:2:2)  DHT: 420 bytes (two tables are used)  SOS: 14 bytes (4:2:2)  EOI: 2 bytes (FFD9) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2409 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit (4) Table Setting (a) Quantization Table Specification The order of addresses shown in 8  8 blocks corresponds to that of the register addresses. Do not access this table while this module is in processing. Table 41.2 Quantization Table 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F JCQTBL0 (H'E801 7100) = H'00 JCQTBL0 (H'E801 7101) = H'01 JCQTBL0 (H'E801 7102) = H'02 JCQTBL0 (H'E801 7103) = H'03 : JCQTBL0 (H'E801 713F) = H'3F (b) Huffman Table Specification Examples of the Huffman table specification given in the ITU-T T81 Annex K.3.3 recommended by JPEG are shown below. In compression, the following settings must be specified for all the codes so that Huffman codes can be generated for all the group numbers.  DC Huffman table: The number of codes for each code length is 12. The group numbers in order of frequency of occurrence are 12.  AC Huffman table: The number of codes for each code length is 162. The zero run length/the group numbers in order of frequency of occurrence are 162. Do not access the following tables while this module is in processing. In particular, read access is prohibited. Page 2410 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit  Table K.3/T81 JCHTBD0 (H'E801 7200) = H'00 JCHTBD0 (H'E801 7201) = H'01 JCHTBD0 (H'E801 7202) = H'05 JCHTBD0 (H'E801 7203) = H'01 : JCHTBD0 (H'E801 721B) = H'0B  Table K.4/T81 JCHTBD1 (H'E801 7300) = H'00 JCHTBD1 (H'E801 7301) = H'03 JCHTBD1 (H'E801 7302) = H'01 JCHTBD1 (H'E801 7303) = H'01 : JCHTBD1 (H'E801 731B) = H'0B  Table K.5/T81 JCHTBA0 (H'E801 7220) = H'00 JCHTBA0 (H'E801 7221) = H'02 JCHTBA0 (H'E801 7222) = H'01 JCHTBA0 (H'E801 7223) = H'03 : JCHTBA0 (H'E801 72D1) = H'FA  Table K.6/T81 JCHTBA1 (H'E801 7320) = H'00 JCHTBA1 (H'E801 7321) = H'02 JCHTBA1 (H'E801 7322) = H'01 JCHTBA1 (H'E801 7323) = H'02 : JCHTBA1 (H'E801 73D1) = H'FA R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2411 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit (5) Input Pixel Format Image data in the YCbCr422 format can be input to this module. Allocation of data in the YCbCr422 format can be changed by the DINSWAP bits in JIFECNT as shown below.  When the DINSWAP bits = 000 b63 b56 Y0 8 bits b55 b48 Cb0 8 bits b47 b40 Y1 8 bits b39 b32 b31 b24 b23 b16 b15 b8 b7 b0 Cr0 8 bits Y2 8 bits Cb1 8 bits Y3 8 bits Cr1 8 bits b39 b31 b23 b15 b7  When the DINSWAP bits = 001 b63 b56 Cb0 8 bits b55 b48 Y0 8 bits b47 b40 Cr0 8 bits b32 b24 b16 b8 b0 Y1 8 bits Cb1 8 bits Y2 8 bits Cr1 8 bits Y3 8 bits b39 b31 b23 b15 b7  When the DINSWAP bits = 010 b63 b56 Y1 8 bits b55 b48 Cr0 8 bits b47 b40 Y0 8 bits b32 b24 Cb0 8 bits Y3 8 bits b39 b31 b16 b8 Cr1 8 bits Y2 8 bits b23 b15 b0 Cb1 8 bits  When the DINSWAP bits = 100 b63 b56 Y2 8 bits b55 b48 Cb1 8 bits b47 b40 Y3 8 bits b32 b24 b16 b8 b7 b0 Cr1 8 bits Y0 8 bits Cb0 8 bits Y1 8 bits Cr0 8 bits b39 b31 b23 b15 b7  When the DINSWAP bits = 101 b63 b56 Cb1 8 bits b55 b48 Y2 8 bits b47 b40 Cr1 8 bits b32 b24 b16 b8 b0 Y3 8 bits Cb0 8 bits Y0 8 bits Cr0 8 bits Y1 8 bits b39 b31 b23 b15 b7  When the DINSWAP bits = 110 b63 b56 Y3 8 bits b55 b48 Cr1 8 bits b47 b40 Y2 8 bits b32 b24 b16 b8 b0 Cb1 8 bits Y1 8 bits Cr0 8 bits Y0 8 bits Cb0 8 bits b39 b31 b23 b15 b7  When the DINSWAP bits = 111 b63 b56 Cr1 8 bits b55 b48 Y3 8 bits Page 2412 of 3092 b47 b40 Cb1 8 bits b32 Y2 8 bits b24 Cr0 8 bits b16 Y1 8 bits b8 Cb0 8 bits b0 Y0 8 bits R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 41 JPEG Codec Unit Output Coded Data In the case of compression, coded data are output. This module handles the output of coded data in 16-bit units. For this reason, if the coded data have an odd code length (are fractional), the final code for output will be H'D9FF. The JOUTSWAP bits in JIFECNT can be used to alter the arrangement of coded data in the output. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2413 of 3092 Section 41 JPEG Codec Unit 41.3.2 (1) SH7268 Group, SH7269 Group Decompression Overview of Processing The decompression process flows are described below. 1. The JPEG core is activated. 2. Coded data is transferred from the external buffer to this module. If the count mode for stopping the input of coded data is on, reading is stopped each time the amount of coded data set in JIFDSLC is read. Reading is resumed by setting the JINRCMD bit in JIFDCNT to 1. When the JINRINI bit in JIFDCNT is zero, the addresses for reading on resumption are continued from the addresses in the previous round of transfer. When the JINRINI bit is one, the address set in JIFDSA is used on resumption. Reading is stopped when the end of the coded data is detected. If the count mode for stopping the input of coded data is off, reading is continued until the end of code is detected. With this module, more coded data may be read than the coded data size since coded data reading is continued until the end of code is detected. 3. Coded data is input to the JPEG core. The input data is processed in MCUs at any time in the JPEG core. 4. Image data is transferred in MCUs from this module to the external buffer. When the count mode for stopping the output of image data lines is on, writing is stopped each time the number of image data lines set in JIFDDLC is written. Writing is resumed by setting the DOUTRCMD bit in JIFECNT to 1. When the DOUTRINI bit in JIFDCNT is zero, the addresses for writing on resumption are continued from the addresses in the previous round of transfer. When the DOUTRINI bit is one, the address set in JIFDDA is used on resumption. Writing is stopped when one frame of image data is completely transferred. If the count mode for stopping the output of image data lines is off, writing is continued until one frame of image data is completely transferred. 5. Decompression is completed after one frame of data is processed completely. Page 2414 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (a) Section 41 JPEG Codec Unit Initial Settings  When the INT3 bit in JINTE0 is set to 0: After completing the JPEG core settings and input/output buffer settings and transferring coded data to the external buffer, activate this module by setting the JSRT bit in JCCMD to 1.  When the INT3 bit in JINTE0 is set to 1: After completing the JPEG core settings and input buffer settings and transferring coded data to the external buffer, activate this module by setting the JSRT bit in JCCMD to 1. When the image size and pixel format become readable after the coded data has been decompressed, the INS3 bit in JINTS0 is set. At this time, decompression is temporarily stopped. After the image size and pixel format have been read, set the output buffer. Setting the JRST bit in JCCMD to 1 after interrupt handling resumes decompression. Start initial setting Software reset Reset this module in advance by setting the JCUSRST bit in SWRSTCR2 of the power-down modes. Software reset Set the JPEG core. Set the input buffer. No Is the INT3 flag in JINTE0 1? Yes Set output buffer. Image information acquisition Set the JSRT bit in JCCMD to 1. Initial setting completed JPEG core settings Decompression setting: Interrupt setting: DSP bit in JCMOD INT7 to INT5 and INT3 flags in JINTE0 Input buffer settings Byte/word/longword swap setting: Input coded data stop count setting: Address initialization setting for resumption of input coded data: Source address setting: Source count setting: Interrupt setting: JINSWAP bit in JIFDCNT JINC bit in JIFDCNT JINRINI bit in JIFDCNT JIFDSA JIFDSDC JINEN bit in JINTE0 Output buffer settings Byte/word/longword swap setting Vertical/horizontal subsampling setting: Output image pixel format setting: Output data line stop count setting: Address initialization setting for resumption of output image data: Line offset setting: Destination address setting: Destination line count setting: Interrupt setting: DOUTSWAP bit in JIFDCNT VINTER and HINTER bits in JIFDCNT OPF bits in JIFDCNT DOUTLC bit in JIFDCNT DOUTRINI bit in JIFDCNT JIFDDOFST JIFDDA JIFDDLC DBTEN, DOUTLEN bits in JINTE1 Figure 41.7 Decompression Initial Setting Flow R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2415 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Start of image information acquisition Set the JSRT bit in JCCMD to 1. Is an interrupt source generated? No Set input coded data resume command. Set the JINRCMD bit in JIFDCNT to 1. Yes Yes Is the INS5 flag in JINTS0 1? (JEDI) Clear the JINF flag in JINTS1. No Error handling Is the JINF flag in JINTS1 1? (JDTI) Yes JINF = 1 No INS3 = 1 (JEDI) Clear the INS3 flag in JINTS0. Set interrupt request clear command. Set the JEND bit in JCCMD to 1. Set output buffer. Output buffer settings Byte/word/longword swap setting: Vertical/horizontal subsampling setting: Output image pixel format setting: Output data line stop count setting: Address initialization setting for resumption of output image data: Line offset setting: Destination address setting: Destination line count setting: Interrupt settings: DOUTSWAP bit in JIFDCNT VINTER and HINTER bits in JIFDCNT OPF bits in JIFDCNT DOUTLC bit in JIFDCNT DOUTRINI bit in JIFDCNT JIFDDOST JIFDDA JIFDDLC DBTEN, DOUTLEN bits in JINTE1 Set the JRST bit in JCCMD to 1. End of image information acquisition Figure 41.8 Image Information Acquisition Flow Page 2416 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 41 JPEG Codec Unit Decompression Process The decompression process flows are described below.  When JPEG decompression process has been completed, the INS6 bit in JINTS0 is set to 1. However, this module continues processing since the image data remains to be transferred. The DBTF bit in JINTS1 is set to 1 when the last image data is transferred. The interrupt source is cleared by writing 0 to the INS6 bit. However, the interrupt request asserted by this interrupt source cannot be cleared by writing 0 to the INS6 bit. Set an interrupt request clear command (by setting the JEND bit in JCCMD to 1) to clear the interrupt request.  When this module has completed decompression process and all image data has been transferred, the DBTF flag in JINTS1 is set to 1. When the DBTEN bit in JINTE1 is 1 here, an interrupt is generated. The interrupt source is cleared by writing 0 to the DBTF flag.  If the count mode for stopping input coded data is on, when the specified amount of coded data set in JIFDSDC have been read, the JINF flag in JINTS1 is set to 1, and reading is stopped. When the JINEN bit in JINTE1 is 1 here, an interrupt is generated. An interrupt source is cleared by writing 0 to the JINF bit. Setting the JINRCMD bit in JIFDCNT to 1 resumes reading. When the JINRINI bit in JIFDCNT is zero, the addresses for reading on resumption are continued from the addresses in the previous round of transfer. When the JINRINI bit is one, the address set in JIFDSA is used on resumption.  If the count mode for stopping the output image data is on, when the specified number of image data lines set in JIFDDLC have been written, the DOUTLF flag in JINT1 is set to 1, and writing is stopped. When the DOUTLEN bit in JINTE1 is 1 here, an interrupt is generated. An interrupt source is cleared by writing 0 to the DOUTLF bit. Setting the DOUTRCMD bit in JIFDCNT to 1 resumes writing. When the DOUTRINI bit in JIFDCNT is zero, the addresses for writing on resumption are continued from the addresses in the previous round of transfer. When the DOUTRINI bit is one, the address set in JIFDDA is used on resumption. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2417 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Start decompression Is interrupt source generated? No Yes Yes Set interrupt request clear command. Set the JEND bit in JCCMD to 1. Set input coded data resume command. Set the JINRCMD bit in JIFDCNT to 1. Clear the INS6 flag in JINTS0. Clear the JINF flag in JINTS1. Is the INS5 flag in JINTS0 to 1? (JEDI) No Is the INS6 flag in JINTS0 to 1? (JEDI) Error handling Yes No Yes Is the DBTF flag in JINTS1 to 1? (JDTI) No Clear all the flags in JINTS1. Is the JINF flag in JINTS1 to 1? (JDTI) No Yes DOUTLF = 1 (JDTI) Clear the DOUTLF flag in JINTS1. Set output image data resume command. Set the DOUTRCMD bit in JIFDCNT to 1. Decompression completed Figure 41.9 Decompression Process Flow Page 2418 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (c) Section 41 JPEG Codec Unit Error Handling If the INS5 bit in JINTS0 is 1, it indicates that there is an error in the input JPEG coded data and that the decompression process by this module has been ended. Read the ERR bits in JCDERR to determine the cause of the error. The interrupt signal asserted due to the interrupt source indicated by the INS5 bit cannot be negated by clearing the interrupt status through 0-writing. To clear the interrupt request, set the interrupt request clear command (by setting the JEND bit in JCCMD to 1). When performing decompression/compression processing after error handling finishes, start the processing from the initial settings. Start error handling Clear all the flags in JINTS0. Set interrupt request clear command. Set the JEND bit in JCCMD to 1. Read error code value. Error handling Error handling Handle the error appropriately according to the error coded value. Error handling completed Figure 41.10 Error Handling Flow (2) Input JPEG Coded Data Markers to be processed in decompression are SOI, SOF0, SOS, DQT, DHT, DRI, RSTm, and EOI. Other markers except for the error markers shown below are ignored even if they are read. The JINSWAP bits in JIFDCNT can be used to alter the arrangement for the input of coded data. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2419 of 3092 Section 41 JPEG Codec Unit (3) JPEG Decompression Errors (a) Error Marker SH7268 Group, SH7269 Group If a marker error is found while analyzing compressed data for decompression, the code to identify the error type (shown in table 41.3) is set to ERR bits in JCDERR. When an error is detected, this module generates an interrupt signal and terminates decoding. The stored code value will be set to B'1010 (default value) at the start of processing of the next frame or after a bus reset. Table 41.3 Decompression Error Codes Code Description B'0000 Normal B'0001 SOI not detected: SOI not detected until EOI detected B'0010 SOF1 to SOFF detected B'0011 Unprovided pixel format detected B'0100 SOF accuracy error: Other than 8 detected B'0101 DQT accuracy error: Other than 0 detected B'0110 Component error 1: The number of SOF0 header components detected is other than 1, 3, or 4 B'0111 Component error 2: The number of components differs between SOF0 header and SOS B'1000 SOF0, DQT, and DHT not detected when SOS detected B'1001 SOS not detected: SOS not detected until EOI detected B'1010 EOI not detected (default) B'1011 Restart interval data number error detected B'1100 Image size error detected B'1101 Last MCU data number error detected B'1110 Block data number error detected Page 2420 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (b) Section 41 JPEG Codec Unit Huffman Coded Segment Error During the compressed data analysis in decompression operation, if there is an increase or decrease in the decoded data count due to an error resulting from bit reversal or missing data in the Huffman-coded segment, determine the error type, and set the error code in the ERR bit in JCDERR. Table 41.4 lists the segment error codes. The error code is set, interrupt signal is issued, and the process is ended only if the bits INT7 to INT5 in JINTE0 corresponding to the detected error is set to 1. The set code value will turn to the default value (B'1010) at the start of processing of the next frame or after a bus reset. However, in this error detection, if an error in the Huffman-coded segment does not result in an alteration in the decoded data count, the error will go undetected. [Example] The number of data in a Huffman coded segment with pixel format setting YCbCr422, DRI = 2, X = 80 pixels, and Y = 8 pixels Restart interval 1 SOS Restart interval 2 RST Coded segment Coded segment Restart interval 3 RST Coded segment EOI Number of data in the last MCU: Pixel format setting is YCbCr422, the number of data to be decoded in each MCU is 256. Number of data in the restart interval: In restart intervals 1 and 2, there are data of two MCUs; the number of data to be decoded is 512. Image size: The total number of data to be decoded is 1280. Figure 41.11 Huffman Coded Segment R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2421 of 3092 Section 41 JPEG Codec Unit SH7268 Group, SH7269 Group Table 41.4 Segment Error Codes Code Description B'0000 Normal B'1011 Restart interval data number error: The number of data in each interval is compared with the number of data specified by the DRI marker. If an interval has more or less data that is specified by the DRI marker, the decompression error code (1011) is set. The last interval which is shorter than the restart interval is not compared. If the DRI marker segment is not placed or the specified number is 00, an error is not detected even if the RSTm marker is placed. Also an m which indicates the order of RSTm marker modulo 8 (m = 0 to 7) is exempt from the error detection analysis. When the INT7 bit in JINTE0 is set to 0, this error is not detected. B'1100 Image size error: The data number of an image which is calculated from the number of lines specified by the frame parameter and the number of samples per line is compared with the total number of data from SOS to EOI (in pixel units). If the numbers of data do not match, the decompression error code (1100) is set. When the INT6 bit in JINTE0 is set to 0, this error is not detected. The data number of an image is shown in MCU units. Thus the number of lines and the number of samples per line for calculation need to be shown in MCU units. B'1101 Last MCU data number error: Whether the number of data in the MCUs at the EOI detection is shown in MCU units is checked and fractions are detected. If error (1100) occurs simultaneously, error (1100) has priority. When the INT5 bit in JINTE0 is set to 0, this error is not detected. B'1110 Block data number error: Whether a block is an 8  8 array is checked; the check is performed for fractions. When bits INT7 to INT5 in JINTE0 are all set to 0, this error is not detected. Page 2422 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.3.3 Section 41 JPEG Codec Unit Output Pixel Format in Decompression This module is capable of decompressing JPEG encoded data created in the YCbCr444, YCbCr422, YCbCr411, and YCbCr420 formats. The pixel format of the output image will be YCbCr422, ARGB8888, or RGB565. The flow of conversion of decompressed data to the given output pixel format is shown below. Internal bus This module YCbCr422 On-chip RAM Color matrix Y0 to Y3 JPEG core Cb YCbCr conversion YCbCr→RGB conversion Vertical/horizontal subsampling RGB 888 Cr Bit reduction Swap RGB 565 OPF bits YCbCr444 Figure 41.12 Block Diagram of Output Pixel Format Conversion in Decompression (1) On-chip RAM Data decoded by the JPEG core are stored in MCUs on RAM in this module. (2) YCbCr Conversion When data are to be output in the ARGB8888 or RGB565 format, data in the YCbCr422, YCbCr411, or YCbCr420 format are first converted to the YCbCr444 format. When data are to be output in the YCbCr422 format, data in the YCbCr444, YCbCr411, or YCbCr420 format are converted to the YCbCr422 format. Conversion is performed using simple interpolation. (3) YCbCr  RGB Conversion Data in the YCbCr444 format are converted to the RGB888 format. The following formulae are used. R = 1.000Y + 1.402Cr G = 1.000Y - 0.344Cb - 0.714Cr B = 1.000Y + 1.772Cb R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2423 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit (4) Bit Reduction RGB888 data is reduced to RGB565 data. The lower three bits of red and blue, and lower two bits of green are removed. (5) Output Pixel Format Selection The pixel format to be output is selected by the OPF bit in JIFDCNT. Allocation of data (while the DOUTSWAP bits in JIFDCNT  000) in the pixel format is shown below.  YCbCr422 (32 bits/pixel) b31 b24 b23 Y0 8 bits b16 b15 Cb 8 bits b8 b7 Y1 8 bits b0 Cr 8 bits  ARGB8888 (32 bits/pixel) b31 b24 b23 * Note: * b16 b15 Red 8 bits b8 b7 Green 8 bits b0 Blue 8 bits This value is determined by the ALPHA[7:0] bits in JIFDADT.  RGB565 (16 bits/pixel) b15 b11 b10 Red 5 bits (6) b5 b4 Green 6 bits b0 Blue 5 bits Vertical/Horizontal Subsampling The output data can be horizontally and vertically subsampled according to the VINTER and HINTER bit setting in JIFDCNT. Figures 41.13 to 41.15 show line subsampling modes. For the output formats ARGB8888 and RGB565, one cell represents one pixel in the figures. For the output format YCbCr422, one cell represents one set of Y0Cb0Y1Cr0 in the figures. As subsampling is carried out by minimum coded units (MCU), the numbers of the horizontal and vertical block units will vary according to the decompressed pixel format. Page 2424 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit Tables 41.5 and 41.6 show the values of n and m in the figures. Horizontal: Table 41.5 Number of Horizontal Blocks Compression Format Output Format n YCbCr444 YCbCr422 1/2 YCbCr444 ARGB8888, RGB565 1 YCbCr422 YCbCr422 1 YCbCr422 ARGB8888, RGB565 2 YCbCr411 YCbCr422 2 YCbCr411 ARGB8888, RGB565 4 YCbCr420 YCbCr422 1 YCbCr420 ARGB8888, RGB565 2 Vertical: Table 41.6 Number of Vertical Blocks Compression Format Output Format m YCbCr444 YCbCr422 1 YCbCr444 ARGB8888, RGB565 1 YCbCr422 YCbCr422 1 YCbCr422 ARGB8888, RGB565 1 YCbCr411 YCbCr422 1 YCbCr411 ARGB8888, RGB565 1 YCbCr420 YCbCr422 2 YCbCr420 ARGB8888, RGB565 2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2425 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit  Subsampling into 1/2 Even lines are skipped by subsampling. 8 × n blocks 2 3 4 5 6 7 8 : : 1 6 7 8 2 3 4 5 6 7 8 × m blocks 8 : : 6 7 :Lines to be skipped by subsampling 8 Figure 41.13 MCU when subsampling into 1/2 is selected  Subsampling into 1/4 The second, third, and fourth lines are skipped by subsampling. 8 × n blocks 2 3 4 5 6 7 8 : : 1 6 7 8 2 3 4 5 6 7 : : 8 × m blocks 8 6 7 8 : Lines to be skipped by subsampling Figure 41.14 MCU when subsampling into 1/4 is selected Page 2426 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit  Subsampling into 1/8 The second, third, fourth, fifth, sixth, seventh, and eighth lines are skipped by subsampling. 8 × n blocks 2 3 4 5 6 7 8 : : 1 6 7 8 2 3 4 5 6 7 : : 8 × m blocks 8 6 7 : Lines to be skipped by subsampling 8 Figure 41.15 MCU when subsampling into 1/8 is selected (7) Swap Allocation of data can be changed by the DOUTSWAP bits in JIFECNT. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2427 of 3092 SH7268 Group, SH7269 Group Section 41 JPEG Codec Unit 41.3.4 Storing Image Data Figure 41.16 shows the buffer area for storing the image data.  Start address Compression: JIFESA Decompression: JIFDDA  Horizontal size Compression, decompression: JCHSZU, JCHSZD  Vertical size Compression, decompression: JCVSAU, JCVSZD  Offset Compression: JIFESOFST Decompression: JIFDDOFST JIFESOFST/JIFDDOFST JIFESA/JIFDDA JCHSZU, JCHSZD Area for storing image data JCVSZU JCVSZD Figure 41.16 Image of Storing Image Data Page 2428 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.4 Section 41 JPEG Codec Unit Interrupts Two types of interrupt requests, namely compression/decompression process interrupt request (JEDI) and data transfer interrupt request (JDTI), are available in this module. The two types of interrupt requests are each related to multiple sources. The interrupt request cancellation methods differ depending on the source of the interrupt request. 41.4.1 Compression/Decompression Process Interrupt Request (JEDI) The flags in JINTS0 indicate compression/decompression-related sources. The interrupt requests asserted by these interrupt sources cannot be negated by clearing the corresponding interrupt status bits to 0. Issue an interrupt request clear command (by setting the JEND bit in JCCMD to 1) to clear the interrupt request. When a flag in JINTS0 is set to 1, a compression/decompression process interrupt request is sent to the interrupt controller. (1) Compression  JPEG compression process end When the INS6 bit in JINTS0 is 1, the JPEG compression process has been successfully completed. After all of the coded data is transferred, this module completes compression. (2) Decompression  JPEG decompression process end When the INS6 bit in JINTS0 is 1, the JPEG decompression process has been successfully completed. After all of the image data is transferred, this module completes decompression.  JPEG decompression error occurrence When the INS5 bit in JINTS0 is 1, the input JPEG coded data has an error and this module has stopped the decompression process. Read the error code (ERR bits in JCDERR) and identify the error source. This interrupt occurs when any of the INT7 to INT5 bits in JINTE0 is 1.  Request for reading the image size and pixel format When the INS3 bit in JINTS0 is 1, JPEG coded data has been input and information regarding the image size and pixel format can be read. Since the JPEG decompression process is suspended, resume the JPEG decompression process by setting the process stop clear command after accessing the necessary registers. This interrupt occurs when the INT3 bit in JINTE0 is 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2429 of 3092 Section 41 JPEG Codec Unit 41.4.2 SH7268 Group, SH7269 Group Data Transfer Interrupt Request (JDTI) The flags in JINTS1 are the interrupt sources for transferring the image data and coded data. The interrupt requests asserted by these interrupt sources can be negated by clearing the corresponding interrupt status bits to 0. (1) Compression  Interrupt request generated after the specified number of input image data lines has been read When the DINLF bit in JINTS1 is 1, the number of image data lines specified by JIFESLC has been transferred; transfer the rest of the image data to the external buffer and resume transferring the data from the external buffer. A data transfer interrupt request is sent when the DINLEN bit in JINTE1 is 1.  Interrupt request generated after all processes are completed When the CBTF bit in JINTS1 is 1, this module has completed compression and transferred all of the coded data. The data transfer interrupt request is sent when the CBTEN bit in JINTE1 is set to 1. Page 2430 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 41 JPEG Codec Unit Decompression  Interrupt request generated after the specified number of output image data lines has been written to When the DOUTLF bit in the JINTS1 is 1, the number of image data lines specified by JIFDDLC has been transferred. Secure a space for the next coded data in the external buffer, and resume transfer process. A data transfer interrupt request is sent when the DOUTLEN bit in JINTE1 is 1.  Interrupt request generated after the specified amount of input coded data has been read The JINF bit in JINTS1 becomes 1 when the amount of coded data specified by JIFDSDC has been transferred. Secure the next coded data in the external buffer, and resume transfer process. A data transfer interrupt is also sent at this time if the JINEN bit in JINTE1 is 1.  Interrupt request generated after all processes are completed The DBTF bit in JINTS1 becomes 1 when this module has completed decompression and transferred all of the coded data. A data transfer interrupt request is also sent at this time if the DBTEN bit in JINTE1 is set to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2431 of 3092 Section 41 JPEG Codec Unit 41.5 SH7268 Group, SH7269 Group Bus Reset Processing Issuing the bus reset command (setting the BRST bit in JCCMD to 1) causes a bus reset. When this module is in operation, the bus reset command should not be issued. Registers below are initialized by a bus reset.       JPEG code data count upper register (JCDTCU) JPEG code data count middle register (JCDTCM) JPEG code data count lower register (JCDTCD) JPEG interrupt status register 0 (JINTS0) JPEG code decode error register (JCDERR) JPEG code reset register (JCRST) Page 2432 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 41.6 Usage Notes 41.6.1 Pixel Format YCbCr Section 41 JPEG Codec Unit This module treats the range from -128 to 127 as input/output values for YCbCr values in the YCbCr444, YCbCr422, YCbCr411, or YCbCr420 pixel format. On the other hand, video display controller 4 treats the range from 0 to 255 as input/output values for YCbCr. Therefore, when bidirectionally transferring data in YCbCr pixel formats between this module and video display controller 4, correct YCbCr values by adding or subtracting 128. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2433 of 3092 Section 41 JPEG Codec Unit Page 2434 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Section 42 Sampling Rate Converter The sampling rate converter converts the sampling rate for data produced by decoders such as WMA, MP3, or AAC. 42.1 Features  Data size: 16 bits (stereo/monaural)  Sampling rates Input: Either 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz is selectable. Output: Either 8 kHz*, 16 kHz*, 32 kHz, 44.1 kHz, or 48 kHz is selectable. Note: * When 44.1 kHz is selected as the input sampling rate.  Processing capacity: A sample output interval is a maximum of 14 s. (P0  33 MHz)  SNR: 80 db or higher  Five interrupt sources: Input data FIFO empty, output data FIFO full, output data FIFO overwrite, output data FIFO underflow, and conversion end  Two DMA transfer sources: Input data FIFO empty and output data FIFO full  Module standby mode Power consumption can be reduced by stopping clock supply to this module when not used. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2435 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Figure 42.1 shows a block diagram. SRCID Input data FIFO 32 bits x 8 stages FIR filter Peripheral bus SRCOD Output data FIFO 32 bits x 16 stages SRCIDCTRL SRCODCTRL SRCCTRL Interrupt/DMA transfer request SRCSTAT I/O controller [Legend] SRCID: Input data register SRCOD: Output data register SRCIDCTRL: Input data control register SRCODCTRL: Output data control register Control register SRCCTRL: Status register SRCSTAT: Figure 42.1 Block Diagram Page 2436 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 42.2 Section 42 Sampling Rate Converter Register Descriptions Table 42.1 shows the register configuration. Table 42.1 Register Configuration Access Size Channel Register Name Abbreviation R/W Initial Value Address 0 SRCID_0 R/W H'00000000 H'FFFE7000 16, 32 Output data register_0 SRCOD_0 R H'00000000 H'FFFE7004 16, 32 Input data control register_0 SRCIDCTRL_0 R/W H'0000 H'FFFE7008 16 Output data control register_0 SRCODCTRL_0 R/W H'0000 H'FFFE700A 16 Control register_0 SRCCTRL_0 R/W H'0000 H'FFFE700C 16 Status register_0 SRCSTAT_0 R/(W)* H'0002 H'FFFE700E 16 Input data register_1 SRCID_1 R/W H'00000000 H'FFFE7800 16, 32 Output data register_1 SRCOD_1 R H'00000000 H'FFFE7804 16, 32 Input data control register_1 SRCIDCTRL_1 R/W H'0000 H'FFFE7808 16 Output data control register_1 SRCODCTRL_1 R/W H'0000 H'FFFE780A 16 Control register_1 SRCCTRL_1 R/W H'0000 H'FFFE780C 16 Status register_1 SRCSTAT_1 R/(W)* H'0002 H'FFFE780E 16 Input data register_2 SRCID_2 R/W H'00000000 H'FFFE8000 16, 32 Output data register_2 SRCOD_2 R H'00000000 H'FFFE8004 16, 32 Input data control register_2 SRCIDCTRL_2 R/W H'0000 H'FFFE8008 16 Output data control register_2 SRCODCTRL_2 R/W H'0000 H'FFFE800A 16 Control register_2 SRCCTRL_2 R/W H'0000 H'FFFE800C 16 Status register_2 SRCSTAT_2 R/(W)* H'0002 H'FFFE800E 16 Input data register_0 1 2 Note: * Bits 15 to 6 and 4 are read-only. Only 0 can be written to bits 5 and 3 after having read as 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2437 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.2.1 Input Data Register (SRCID) SRCID is a 32-bit readable/writable register that is used to input the data before sampling rate conversion. All the bits are read as 0. The data input to SRCID is stored in the 8-stage input data FIFO. When the number of data units in the input data FIFO is 8, writing to SRCID has no effect. For stereo data, bits 31 to 16 are for Lch data, and bits 15 to 0 are for Rch data. For monaural data, data in bits 31 to 16 is valid, and data in bits 15 to 0 is invalid. Bit: 31 Initial value: 0 R/W: R/W Bit: 15 Initial value: 0 R/W: R/W 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The data subject to sampling rate conversion is aligned differently depending on the IED bit setting in SRCIDCTRL. Table 42.2 shows the relationship between the IED bit setting and data alignment. Table 42.2 Alignment of Data before Sampling Rate Conversion IED Lch[15:8] Lch[7:0] Rch[15:8] Lch[7:0] 0 SRCID[31:24] SRCID[23:16] SRCID[15:8] SRCID[7:0] 1 SRCID[23:16] SRCID[31:24] SRCID[7:0] SRCID[15:8] Page 2438 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 42.2.2 Section 42 Sampling Rate Converter Output Data Register (SRCOD) SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The data in the 16-stage output data FIFO is read through SRCOD. When the number of data in the output data FIFO is zero after the start of conversion, the value previously read is read again. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: Initial value: R/W: 0 R The data in SRCOD is aligned differently depending on the OCH and OED bit setting in SRCODCTRL. Table 42.3 shows the correspondence between the OCH and OED bit setting and data alignment in SRCOD. Table 42.3 Alignment of Data in SRCOD OCH 0 1*1 OED SRCOD[31:24] SRCOD[23:16] SRCOD[15:8] 2 SRCOD[7:0] Rch[7:0]*2 0 Lch[15:8] Lch[7:0] Rch[15:8]* 1 Lch[7:0] Lch[15:8] Rch[7:0]*2 Rch[15:8]*2 0 Rch[15:8] Rch[7:0] Lch[15:8] Lch[7:0] 1 Rch[7:0] Rch[15:8] Lch[7:0] Lch[15:8] Notes: 1. When processing monaural data, do not set the bit to 1. 2. When processing monaural data, the data in these bits is invalid. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2439 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.2.3 Input Data Control Register (SRCIDCTRL) SRCIDCTRL is a 16-bit readable/writable register that specifies the endian format of input data, enables/disables the interrupt requests, and specifies the triggering number of data units. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IED IEN ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ IFTRG[1:0] Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 10  All 0 R Reserved 0 R/W 0 0 R/W These bits are always read as 0. The write value should always be 0. 9 IED 0 R/W Input Data Endian Specifies the endian format of the input data. 0: Big endian 1: Little endian 8 IEN 0 R/W Input Data FIFO Empty Interrupt Enable Enables/disables the input data FIFO empty interrupt request to be issued when the number of data units in the input FIFO becomes equal to or smaller than the triggering number specified by the IFTRG1 and IFTRG0 bits, thus resulting in the IINT bit in the status register (SRCSTAT) being set to 1. 0: Input data FIFO empty interrupt is disabled. 1: Input data FIFO empty interrupt is enabled. 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2440 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W Description 1, 0 IFTRG[1:0] 00 R/W Input FIFO Data Triggering Number Specifies the condition in terms of the number on which the IINT bit in the status register (SRCSTAT) is set to 1. When the number of data units in the input FIFO becomes equal to or smaller than the triggering number listed below, the IINT bit is set to 1. 00: 0 01: 2 10: 4 11: 6 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2441 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.2.4 Output Data Control Register (SRCODCTRL) SRCODCTRL is a 16-bit readable/writable register that specifies whether to exchange the channels for the output data, specifies the endian format of output data, enables/disables the interrupt requests, and specifies the triggering number of data units. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ⎯ ⎯ ⎯ ⎯ ⎯ OCH OED OEN ⎯ ⎯ -⎯ ⎯ ⎯ ⎯ Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved 1 0 OFTRG[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 OCH 0 R/W Output Data Channel Exchange Specifies whether to exchange the channels for the output data register (SRCOD). When processing monaural data, do not set this bit to 1. 0: Does not exchange the channels (the same order as data input) 1: Exchanges the channels (the opposite order from data input) 9 OED 0 R/W Output Data Endian Specifies the endian format of the output data. 0: Big endian 1: Little endian 8 OEN 0 R/W Output Data FIFO Full Interrupt Enable Enables/disables the output data FIFO full interrupt request to be issued when the number of data units in the output FIFO becomes equal to or greater than the number specified by the OFTRG1 and OFTRG0 bits, thus resulting in the OINT bit in the status register (SRCSTAT) being set to 1. 0: Output data FIFO full interrupt is disabled. 1: Output data FIFO full interrupt is enabled. Page 2442 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 OFTRG[1:0] 00 R/W Output FIFO Data Trigger Number Specifies the condition in terms of the number on which the OINT bit in the status register (SRCSTAT) is set to 1. When the number of data units in the output FIFO becomes equal to or greater than the number listed below, the OINT bit is set to 1. 00: 1 01: 4 10: 8 11: 12 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2443 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.2.5 Control Register (SRCCTRL) SRCCTRL is a 16-bit readable/writable register that enables/disables the module operation, enables/disables the interrupt requests, and specifies flush processing, clear processing of the internal work memory, and the input and output sampling rates. Bit: 15 14 10 9 8 ⎯ ⎯ CEEN SRCEN UDEN OVEN FL CL Initial value: 0 R/W: R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 13 12 0 R/W 11 0 R/W 7 6 5 4 3 0 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 0 R/W 0 R/W 2 ⎯ IFS[3:0] 0 R/W 0 R 1 0 OFS[2:0] 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 13 CEEN 0 R/W Conversion End Interrupt Enable Enables/disables the conversion end interrupt to be generated when the CEF bit in SRCSTAT is set to 1 after flush processing is completed and all the output data is read. 0: Disables conversion end interrupt requests. 1: Enables conversion end interrupt requests. 12 SRCEN 0 R/W Module Enable Enables/disables this module operation. Writing 1 while SRCEN  0 clears the internal work memory. 0: Disables this module operation. 1: Enables this module operation. Note: When SRCEN  1, do not change the settings of the following bits. Page 2444 of 3092 Register Bit Bit Name SRCIDCTRL 9 IED SRCODCTRL 10, 9 OCH, OED SRCCTRL 7 to 4, 2 to 0 IFS[3:0], OFS[2:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W Description 11 UDEN 0 R/W Output Data FIFO Underflow Interrupt Enable Enables/disables the output data FIFO underflow interrupt to be generated when output data FIFO is read and the UDF bit in SRCSTAT is set to 1 while the number of data units in the output data FIFO is zero. 0: Disables output data FIFO underflow interrupt requests. 1: Enables output data FIFO underflow interrupt requests. 10 OVEN 0 R/W Output Data FIFO Overwrite Interrupt Enable Enables/disables the output data FIFO overwrite interrupt request to be issued when the conversion for the next data has been completed while the number of data units in the output FIFO is eight, thus setting the OVF bit in the status register (SRCSTAT) to 1. When OVEN = 1: Conversion processing is stopped until the OVF bit is cleared by the CPU accessing to SRCSTAT when the output data FIFO overwrite interrupt is generated. At this time, conversion result writing to the output data FIFO is also stopped. OVEN = 0: The OVF bit is automatically cleared when the output data FIFO has space, and conversion processing can be continued. 0: Output data FIFO overwrite interrupt is disabled. 1: Output data FIFO overwrite interrupt is enabled. 9 FL 0 R/W Internal Work Memory Flush Writing 1 to this bit starts converting the sampling rate of all the data in the input FIFO, input buffer memory, and intermediate memory (i.e., flush processing). This bit is always read as 0. When SRCEN = 0, writing 1 to this bit does not trigger flush processing. In addition, when 1 is written to the FL bit while the number of data units in the input buffer memory is less than the values shown in table 42.6, valid output data cannot be received. Thus the internal work memory is cleared without triggering the flush processing. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2445 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W Description 8 CL 0 R/W Internal Work Memory Clear Writing 1 to this bit clears the input FIFO, output FIFO, input buffer memory, intermediate memory, and accumulator. This bit is always read as 0. Even when SRCEN = 0, writing 1 to this bit clears the processing. 7 to 4 IFS[3:0] All 0 R/W Input Sampling Rate Specifies the input sampling rate. 0000: 8.0 kHz 0001: 11.025 kHz 0010: 12.0 kHz 0011: Setting prohibited 0100: 16.0 kHz 0101: 22.05 kHz 0110: 24.0 kHz 0111: Setting prohibited 1000: 32.0 kHz 1001: 44.1 kHz 1010: 48.0 kHz 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 2446 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W Description 2 to 0 OFS[2:0] All 0 R/W Output Sampling Rate These bits specify the output sampling rate. 000: 44.1 kHz 001: 48.0 kHz 010: 32.0 kHz 011: Setting prohibited 100: 8.0 kHz* 101: 16.0 kHz* 110: Setting prohibited 111: Setting prohibited Note: * Setting the OFS[2:0] bits to 100 or 101 is valid only when the IFS[3:0] bits are 1001. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2447 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter After flush processing has been completed, the number of output data units obtained as a result of conversion can be calculated by using the following formula. Output sampling rate Number of output data units = (Number of input data units × n - 1) × Input sampling rate × n +1 Table 42.4 Value of n in the Formula OFS Setting (Output 0000 Sampling (8.0) Rate [kHz]) IFS Setting (Input Sampling Rate [kHz]) 0001 0010 (11.025) (12.0) 0100 (16.0) 0101 (22.05) 0110 (24.0) 1000 (32.0) 1001 (44.1) 1010 (48.0) 000 (44.1) 6 4 4 3 2 2 3  1 001 (48.0) 6 4 4 3 2 2 3 1  010 (32.0) 4 8 4 2 4 2  2 1 100 (8.0)        1  101 (16.0)        1  Conversion processing is not started and thus output data is not obtained until the specified number of data units are input. The minimum number of input data units necessary for obtaining the first output data depends on the IFS and OFS bit settings. Tables 42.5 and 42.6 show the relation between the settings of the IFS and OFS bits and the number of input data required. Table 42.5 Relation between Sampling Rate Settings and Number of Initial Input Data Units Required OFS Setting (Output Sampling 0000 Rate [kHz]) (8.0) 0001 0010 (11.025) (12.0) 0100 (16.0) 0101 (22.05) 0110 (24.0) 1000 (32.0) 1001 (44.1) 1010 (48.0) 000 (44.1) 38 40 40 43 48 48 43  63 001 (48.0) 38 40 40 43 48 48 43 32  010 (32.0) 40 37 40 48 40 48  48 63 100 (8.0)        63  101 (16.0)        63  Page 2448 of 3092 IFS Setting (Input Sampling Rate [kHz]) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Table 42.6 Relation between Sampling Rate Settings and Number of Input Data Units Required for Flush Processing OFS Setting (Output Sampling 0000 Rate [kHz]) (8.0) 0001 0010 (11.025) (12.0) 0100 (16.0) 0101 (22.05) 0110 (24.0) 1000 (32.0) 1001 (44.1) 1010 (48.0) 000 (44.1) 27 24 24 22 16 16 22  1 001 (48.0) 27 24 24 22 16 16 22 32  010 (32.0) 24 29 24 16 24 16  16 1 100 (8.0)        1  101 (16.0)        1  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 IFS Setting (Input Sampling Rate [kHz]) Page 2449 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.2.6 Status Register (SRCSTAT) SRCSTAT is a 16-bit readable/writable register that indicates the number of data units in the input and output data FIFOs, whether the various interrupt sources have been generated or not, and the flush processing status. Bit: 15 14 13 12 11 10 OFDN[4:0] Initial value: 0 R/W: R 0 R 0 R 9 8 7 IFDN[3:0] 0 R 0 R 0 R 0 R 0 R 0 R 6 5 4 3 2 1 0 ⎯ CEF FLF UDF OVF IINT OINT 0 R 0 R(W)*1 0 R 0 0 1 0 R(W)*1R/(W)*1R/(W)*1R/(W)*1 Note: *1 Only 0 can be written after having read as 1. Bit Bit Name Initial Value R/W 15 to 11 OFDN[4:0] All 0 R Description Output FIFO Data Count Indicates the number of data units in the output FIFO. 10 to 7 IFDN[3:0] All 0 R 6  0 R Input FIFO Data Count Indicates the number of data units in the input FIFO. Reserved This bit is always read as 0. The write value should always be 0. 5 CEF 0 R/(W)* Conversion End Flag Indicates that all the output data is read after flush processing is completed. [Clearing conditions]  When 0 has been written to the CEF bit after reading CEF = 1.  When 1 has been written to the CL bit in SRCCTRL.  When 1 has been written to the SRCEN bit in SRCCTRL while SRCEN is 0. [Setting condition]  Page 2450 of 3092 When the number of data units in the output data FIFO is zero on completion of flush processing. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W Description 4 FLF 0 R Flush Processing Status Flag Indicates whether flush processing is in progress or not. [Clearing conditions]  When flush processing has been completed.  When 1 has been written to the CL bit in SRCCTRL.  When 1 has been written to the SRCEN bit in SRCCTRL while SRCEN is 0. [Setting condition]  3 UDF 0 When 1 has been written to the FL bit in SRCCTRL. R/(W)* Output FIFO Underflow Interrupt Request Flag Indicates that the output data FIFO is read when the number of data units in the output data FIFO is zero. [Clearing conditions]  When 0 has been written to the UDF bit after reading UVF = 1.  When 1 has been written to the CL bit in SRCCTRL.  When 1 has been written to the SRCEN bit in SRCCTRL while SRCEN is 0. [Setting condition]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 When the output data FIFO is read while the number of data units in the output FIFO is zero. Page 2451 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W 2 OVF 0 R/(W)* Output Data FIFO Overwrite Interrupt Request Flag Description Indicates that the sampling rate conversion for the next data has been completed when the output data FIFO is full. The conversion is stopped until the OVF flag is cleared. [Clearing conditions]  When 0 has been written to the OVF bit after reading OVF = 1 while the OVEN bit in SRCCTRL is 1.  When the number of data units in the output FIFO decreases after reading SRCOD while the OVEN bit in SRCCTRL is 0.  When 1 has been written to the CL bit in SRCCTRL.  When 1 has been written to the SRCEN bit in SRCCTRL while SRCEN is 0. [Setting condition]  Page 2452 of 3092 When the sampling rate conversion for the next data has been completed when the output FIFO is full. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W 1 IINT 1 R/(W)* Input Data FIFO Empty Interrupt Request Flag Description Indicates that the number of data units in the input FIFO has become equal to or smaller than the triggering number specified by the IFTRG1 and IFTRG0 bits in the input data control register (SRCIDCTRL). [Clearing conditions]  When 0 has been written to the IINT bit after reading IINT = 1.  When the number of data units in the input FIFO has exceeded the specified triggering number due to DMA transfer to the input FIFO. [Setting conditions] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016  When the number of data units in the input FIFO has become equal to or smaller than the specified triggering number.  When 1 has been written to the CL bit in SRCCTRL.  When 1 has been written to the SRCEN bit in SRCCTRL while SRCEN is 0. Page 2453 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter Bit Bit Name Initial Value R/W 0 OINT 0 R/(W)* Output Data FIFO Full Interrupt Request Flag Description Indicates that the number of data units in the output FIFO has become equal to or greater than the triggering number specified by the OFTRG[1:0] bits in the output data control register (SRCODCTRL). [Clearing conditions]  When 0 has been written to the OINT bit after reading OINT = 1.  When the number of data units in the FIFO has become less than the specified triggering number due to DMA transfer to the output FIFO.  When 1 has been written to the CL bit in SRCCTRL.  When 1 has been written to the SRCEN bit in SRCCTRL while SRCEN is 0. [Setting condition]  Note: * When the number of data units in the output FIFO has become equal to or greater than the specified triggering number. Only 0 can be written after having read as 1. Page 2454 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 42.3 Operation 42.3.1 Initial Setting Section 42 Sampling Rate Converter Figure 42.2 shows a sample flowchart for initial setting. Register Bit Items to be Set Start initial setting SRCCTRL Set necessary parameters. Set the SRCEN bit in SRCCTRL to 1 SRCIDCTRL Initial setting completed SRCODCTRL CEEN Enabling/disabling of the CEF interrupt UDEN Enabling/disabling of the UDF interrupt OVEN Enabling/disabling of the OVF interrupt IFS[3:0] Input sampling rate OFS[2:0] Output sampling rate IED Input data endian IEN Enabling/disabling of the IDE interrupt IFTRG[1:0] Input data FIFO triggering number OCH Exchanging of output data channels OED Output data endian OEN Enabling/disabling of the ODF interrupt OFTRG[1:0] Output data FIFO triggering number Figure 42.2 Sample Flowchart for Initial Setting R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2455 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.3.2 Data Input Figure 42.3 is a sample flowchart for data input. Start data input Read the IINT bit in SRCSTAT. IINT = 1? No Yes Write the data to be converted to SRCID and clear the IINT bit to 0. Has all the data been input? No Yes Set the FL bit in SRCCTRL to 1. Data input completed Figure 42.3 Sample Flowchart for Data Input (1) When Interrupts are Issued to CPU 1. Set the IEN bit in SRCIDCTRL to 1. 2. When the IINT bit in SRCSTAT is set to 1, the IDE interrupt request is issued. In the interrupt processing routine, read the IINT bit and confirm that it is 1, write data to SRCID, and write 0 to the IINT bit. Then return from the interrupt processing routine. 3. Repeat step 2 until all the data has been input, and write 1 to the FL bit in SRCCTRL. Page 2456 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 42 Sampling Rate Converter When Interrupts are Used to Activate Direct Memory Access Controller 1. Assign IDEI of this module to one channel of the direct memory access controller. 2. Set the IEN bit in SRCIDCTRL to 1. 3. When the IINT bit in SRCSTAT is set to 1, the IDE interrupt request is issued thus activating the direct memory access controller. When the direct memory access controller has written data to the SRCID thus resulting in the number of data units in the input data FIFO exceeding that of the triggering number specified by the IFTRG1 and IFTRG 0 bits in SRCIDCTRL, the IINT bit is cleared to 0. 4. Repeat step 3 until all the data has been input, and write 1 to the FL bit in SRCCTRL. (3) When Serial Sound Interface Interrupts are Used for Activating Direct Memory Access Controller to Transfer Input Data from Serial Sound Interface 1. Assign the serial sound interface to one channel of the direct memory access controller as a DMA transfer request source. Set SSIFRDR of the serial sound interface as a transfer source and SRCID of the sampling rate converter as a transfer destination, and set the serial source interface to enable reception operation. 2. When the RDF bit in SSIFSR is set to 1, the serial sound interface interrupt request is issued thus activating the direct memory access controller. The direct memory access controller then reads data from SSIFRDR and writes the data to SRCID. 3. Repeat step 2 until all the data has been input, and write 1 to the FL bit in SRCCTRL. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2457 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.3.3 Data Output Figure 42.4 is a sample flowchart for data output. Start data output Read the OINT bit in SRCSTAT. OINT = 1? No Yes Read the data after conversion from SRCOD and clear the OINT bit to 0. Flush processing started? No Yes Read the FLF bit in SRCSTAT. FLF = 0? No Yes Data output completed Figure 42.4 Sample Flowchart for Data Output Page 2458 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 42 Sampling Rate Converter When Interrupts are Issued to CPU 1. Set the OEN bit in SRCODCTRL to 1. 2. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued. In the interrupt processing routine, read the OINT bit and confirm that it is 1, read data from SRCOD, and write 0 to the OINT bit. Then return from the interrupt processing routine. 3. After flush processing starts, repeat step 2 until the CEF bit in SRCSTAT is read as 1. (2) When Interrupts are Used to Activate Direct Memory Access Controller 1. Assign ODFI of this module to one channel of the direct memory access controller. 2. Set the OEN bit in SRCODCTRL to 1. 3. When the OINT bit in SRCSTAT is set to 1, the ODF interrupt request is issued thus activating the direct memory access controller. When the direct memory access controller has read data from SRCOD thus resulting in the number of data units in the output data FIFO being less than the triggering number specified by the OFTRG1 and OFTRG0 bits in SRCODCTRL, the OINT bit is cleared to 0. 4. After flush processing starts, repeat step 3 until the FLF bit in SRCSTAT is read as 0. (3) When Serial Sound Interface Interrupts are Used for Activating Direct Memory Access Controller to Transfer Output Data to Serial Sound Interface 1. Set the OVEN bit in SRCCTRL to 0 to disable the OVF interrupt request generation. 2. Assign the serial sound interface to one channel of the direct memory access controller as a DMA transfer request source. Set SRCID of the sampling rate converter as a transfer source and SSIFTDR of the serial sound interface as a transfer destination, and set the serial source interface to enable transmission operation. 3. When the TDE bit in SSIFSR is set to 1, the serial sound interface issues an interrupt request thus activating the direct memory access controller. The direct memory access controller then reads data from SRCOD and writes the data to SSIFTDR. 4. After flush processing starts, repeat step 3 until the CEF bit in SRCSTAT is read as 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2459 of 3092 SH7268 Group, SH7269 Group Section 42 Sampling Rate Converter 42.4 Interrupts This module has five interrupt sources: input data FIFO empty (IDEI), output data FIFO full (ODFI), output data FIFO overwrite (OVF), output data FIFO underflow (UDF), and conversion end (CEF). Table 42.7 summarizes the interrupts. Table 42.7 Interrupt Requests and Generation Conditions Direct Memory Access Controller Activation Interrupt Request Abbreviation Interrupt Condition Input data FIFO empty IDEI IINT = 1, IEN = 1, and SRCEN = 1 Possible Output data FIFO full ODFI OINT = 1, OEN = 1, and SRCEN = 1 Possible Output data FIFO overwrite OVF OVF = 1, OVEN = 1, and Not possible SRCEN = 1 Output data FIFO underflow UDF UDF = 1, UDEN = 1, and Not possible SRCEN = 1 Conversion end CEF CEF = 1, CEEN = 1, and Not possible SRCEN = 1 When the interrupt condition is satisfied, the CPU executes the interrupt exception handling routine. The interrupt source flags should be cleared in the routine. The IDEI and ODFI interrupts can activate the direct memory access controller when the direct memory access controller is set to allow this. If the direct memory access controller is activated, the interrupts from this module are not sent to the CPU. When the direct memory access controller has written data to SRCID resulting in the number of data units in the input data FIFO exceeding that of the specified triggering number, the IINT bit is cleared to 0. Similarly, when the direct memory access controller has read data from SRCOD resulting in the number of data units in the output data FIFO being less than the specified triggering number, the OINT bit is cleared to 0. Page 2460 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 42.5 Usage Notes 42.5.1 Notes on Accessing Registers Section 42 Sampling Rate Converter After the following write access to SRCCTRL, three cycles of the peripheral clock 0 (P0) elapse before the corresponding bit in SRCSTAT is updated.  Before the FLF bit in SRCSTAT is set after 1 is written to the FL bit in SRCCTRL  Before each bit in SRCSTAT is initialized after 1 is written to the CL bit in SRCCTRL  Before each bit in SRCSTAT is initialized after 1 is written to the SRCEN bit in SRCCTRL while the SRCEN bit is 0 On the other hand, as the CPU executes any subsequent instruction without waiting for the completion of the register writing, an instruction that immediately follows that used to write to SRCCTRL cannot accurately detect the updated state of SRCSTAT. To check the updated SRCSTAT state, dummy-read SRCCTRL or SRCSTAT after the instruction used to write to SRCCTRL. 42.5.2 Notes on Flush Processing When 1 is written to the FL bit in SRCCTRL, this module continues conversion processing by adding 0-data to the input data end point. Flush processing, therefore, should be performed when the audio data end point is input and there is no subsequent data. To perform conversion again after flush processing, clear the internal work memory in either of the following ways.  Write 1 to the CL bit in SRCCTRL.  Write 0 and then 1 to the SRCEN bit in SRCCTRL. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2461 of 3092 Section 42 Sampling Rate Converter Page 2462 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 43 Sound Generator Section 43 Sound Generator This LSI has an on-chip sound generator with four channels. 43.1 Features Module data bus SGCR1/2 SGCSR SGLR SGTFR SGSFR Bus interface  Capable of adjusting sound volume using 8-bit PWM output  Selection of operating clocks Four types of operating clocks (P0/2, P0/4, P0/8, and P0/16) can be selected.  Frequency settings in the 31-Hz to 20-kHz range with precision of 1% or less  Output stop procedures can be selected  Automatic attenuator function can be selected  Interrupt source: one type Attenuation end interrupt can be requested  Module stop mode can be set Internal data bus Attenuation control circuit Control circuit Waveform generation circuit P0φ/2 P0φ/4 P0φ/8 P0φ/16 Clock selection citcuit SGOUT SGCLK SGI Legend: SGCR1: SGCSR: SGCR2: SGLR: SGTFR: SGSFR: Sound generator control register 1 Sound generator control status register Sound generator control register 2 Sound generator loudness register Sound generator tone frequency register Sound generator reference frequency register Figure 43.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2463 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator 43.2 Input/Output Pins Table 43.1 shows the pin configuration. Table 43.1 Pin Configuration Name Abbr. I/O Function Sound generator output pin 0 SGOUT_0 Output Channel 0 sound generator output Sound generator output pin 1 SGOUT_1 Output Channel 1 sound generator output Sound generator output pin 2 SGOUT_2 Output Channel 2 sound generator output Sound generator output pin 3 SGOUT_3 Output Channel 3 sound generator output 43.3 Register Descriptions Table 43.2 shows the register configuration. Separate explanations for each channel are not given in this section. Page 2464 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 43 Sound Generator Table 43.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address 0 SGCR1_0 R/W H'00 H'FFFEC800 8,16 Sound generator control status SGCSR_0 register_0 R/W H'00 H'FFFEC801 8,16 Sound generator control register 2_0 SGCR2_0 R/W H'00 H'FFFEC802 8,16 Sound generator loudness register_0 SGLR_0 R/W H'00 H'FFFEC803 8,16 Sound generator tone frequency register_0 SGTFR_0 R/W H'00 H'FFFEC804 8,16 Sound generator reference frequency register_0 SGSFR_0 R/W H'00 H'FFFEC805 8,16 Sound generator control register 1_1 SGCR1_1 R/W H'00 H'FFFECA00 8,16 Sound generator control status SGCSR_1 register_1 R/W H'00 H'FFFECA01 8,16 Sound generator control register 2_1 SGCR2_1 R/W H'00 H'FFFECA02 8,16 Sound generator loudness register_1 SGLR_1 R/W H'00 H'FFFECA03 8,16 Sound generator tone frequency register_1 SGTFR_1 R/W H'00 H'FFFECA04 8,16 Sound generator reference frequency register_1 SGSFR_1 R/W H'00 H'FFFECA05 8,16 Sound generator control register 1_2 SGCR1_2 R/W H'00 H'FFFECC00 8,16 Sound generator control status SGCSR_2 register_2 R/W H'00 H'FFFECC01 8,16 Sound generator control register 2_2 SGCR2_2 R/W H'00 H'FFFECC02 8,16 Sound generator loudness register_2 SGLR_2 R/W H'00 H'FFFECC03 8,16 Sound generator tone frequency register_2 SGTFR_2 R/W H'00 H'FFFECC04 8,16 1 2 Sound generator control register 1_0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Access Size Page 2465 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator Channel Register Name Abbreviation R/W Initial Value Address 2 Sound generator reference frequency register_2 SGSFR_2 R/W H'00 H'FFFECC05 8,16 3 Sound generator control register 1_3 SGCR1_3 R/W H'00 H'FFFECE00 8,16 Sound generator control status SGCSR_3 register_3 R/W H'00 H'FFFECE01 8,16 Sound generator control register 2_3 SGCR2_3 R/W H'00 H'FFFECE02 8,16 Sound generator loudness register_3 SGLR_3 R/W H'00 H'FFFECE03 8,16 Sound generator tone frequency register_3 SGTFR_3 R/W H'00 H'FFFECE04 8,16 Sound generator reference frequency register_3 SGSFR_3 R/W H'00 H'FFFECE05 8,16 Page 2466 of 3092 Access Size R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 43.3.1 Section 43 Sound Generator Sound Generator Control Register 1 (SGCR1) SGCR1 controls the operation of this module. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 SGST STPM ⎯ SGCK[1] SGCK[0] DPF[2] DPF[1] DPF[0] 0 0 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 7 SGST 0 R/W Description Operation Start Starts/stops the operation. 0: Stops the operation 1: Starts the operation. The stop procedures differ depending on the STPM bit setting even when SGST = 1 6 STPM 0 R/W Stop Procedure Select Selects the operation stop procedure. 0: Stops when SGST = 0 1: When the attenuator function is on, operation stops if SGST = 0 and SGDEF = 1 When the attenuator function is off, operation stops if SGST = 0 and SGEND = 1 5  0 R Reserved This bit is always read as 0. The write value should always be 0. 4, 3 SGCK[1:0] H'0 R/W Clock Select Selects the operating clock (SGCLK). 00: P0/2 01: P0/4 10: P0/8 11: P0/16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2467 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator Bit Bit Name Initial Value R/W Description 2 to 0 DPF[2:0] H'0 R/W Attenuator Function Select These bits turn the attenuator function on and off, and select the attenuation cycle. 000: Attenuator function is off. 001: Attenuates at the TONE frequency 010: Attenuates at the TONE frequency/2 011: Attenuates at the TONE frequency/4 100: Attenuates at the TONE frequency/8 101: Attenuates at the TONE frequency/16 110: Attenuates at the TONE frequency/32 111: Setting prohibited Page 2468 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 43.3.2 Section 43 Sound Generator Sound Generator Control Status Register (SGCSR) SGCSR is a status register. Bit: Bit name: Initial value: R/W: 7 6 5 4 3 2 1 0 SGIE SGDEF — — — — — — 0 0 0 0 0 0 0 0 R/W R/(W)* R R R R R R Bit Bit Name Initial Value R/W Description 7 SGIE 0 R/W Interrupt Enable Enables/disables the attenuation end interrupt requests. 0: Disables interrupt requests 1: Enables interrupt requests 6 SGDEF 0 R/(W)* Attenuation End Flag [Setting condition]  When attenuation operation ends [Clearing conditions]  5 to 0 All 0 R  When 0 is written after SGDEF = 1 is read  When SGLR is written Reserved These bits are always read as 0. The write value should always be 0. Note: * Only 0 can be written to clear the flag. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2469 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator 43.3.3 Sound Generator Control Register 2 (SGCR2) SGCR2 is used for the termination of this module. Bit: Bit name: 7 6 5 4 3 2 1 0 SGEND TCHG — — — — — — 0 0 0 0 0 0 0 0 R/W R/W R R R R R R Initial value: R/W: Bit Bit Name Initial Value R/W Description 7 SGEND 0 R/W Stop Controls the operation of this module when the attenuator function is off and STPM = 1. 0: Continues operation 1: Stops operation When STPM = 0, the SGST bit controls operation regardless of this bit setting. 6 TCHG 0 R/W TONE Change Protect Enables/disables writing to the TONE or SFS bit. Bits TONE and SFS can be modified when TCHG = 1. 0: Disables writing to the TONE and SFS bit 1: Enables writing to the TONE and SFS bit 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2470 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 43.3.4 Section 43 Sound Generator Sound Generator Loudness Register (SGLR) SGLR sets the SGOUT duty. Bit: 7 6 5 4 3 2 1 0 LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 to 0 LD[7:0] H'00 R/W Loudness Data Bit name: Initial value: R/W: These bits store the duty data for pulse output. 43.3.5 Sound Generator Tone Frequency Register (SGTFR) SGTFR sets the tone frequency. Bit: 7 6 5 4 3 2 1 0 Bit name: — TONE[6] TONE[5] TONE[4] TONE[3] TONE[2] TONE[1] TONE[0] Initial value: 0 0 0 0 0 0 0 0 R/W: R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * These bits can be written to only when TCHG = 1. Bit Bit Name Initial Value R/W 7  0 R Description Reserved This bit is always read as 0. The write value should always be 0. 6 to 0 TONE[6:0] H'00 R/(W)* Tone Frequency Setting These bits set the tone frequency based on the reference frequency specified by the SFS bit. Setting H'00 is prohibited. Note: * These bits can be written to when TCHG = 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2471 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator 43.3.6 Sound Generator Reference Frequency Register (SGSFR) SGSFR sets the reference frequency. Bit: Bit name: 7 6 5 4 3 2 1 0 SFS[7] SFS[6] SFS[5] SFS[4] SFS[3] SFS[2] SFS[1] SFS[0] 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * These bits can be written to only when TCHG = 1. Bit Bit Name Initial Value R/W 7 to 0 SFS[7:0] H'00 R/(W)* Reference Frequency Setting Description These bits set the reference frequency based on the operating clock (SGCLK) specified by the SGCK bit in SGCR1. Setting H'00 is prohibited. Note: * These bits can be written to when TCHG = 1. Page 2472 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 43.4 Operation 43.4.1 Base Operation (1) Section 43 Sound Generator Initial Settings Make sure that this module has stopped before setting registers. The operation stop procedure, operating clock and attenuator function on/off settings are specified by the SGCR1 setting. When the attenuator function is on, the attenuation cycle is selected. The interrupt request is set by the SGIE bit in SGCSR. (2) Activation The operation of this module is enabled by setting the SGST bit in SGCR1 to 1 and clearing the SGEND bit in SGCR2 to 0. Set the TCHG bit in SGCR2 to 1 to cancel the write protect for SGSFR and SGTFR. Use bits SFS7 to SFS0 in SGSFR to select the reference frequency and bits TONE6 to TONE0 in SGTFR to select the tone frequency. SGLR specifies the output pulse duty. This module starts operation after writing to SGCR2, SGLR, SGTFR, and SGSFR is completed. (3) Stopping The operation stop procedure of this module is specified by the STPM bit in SGCR1. When the attenuator function is off and STPM is 0, the operation is stopped by the SGST bit regardless of the SGEND bit setting. When the attenuator function is off and STPM is 1, the operation is stopped by clearing the SGST bit to 0 and setting the SGEND bit to 1. When the attenuator function is on and STPM is 0, clearing the SGST bit to 0 stops operation even though the automatic attenuation does not end and the SGDEF bit is not set to 1. When the attenuator function is on and STPM is 1, clearing the SGST bit to 0 does not stop operation until the automatic attenuation ends and the SGDEF bit is set to 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2473 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator The conditions for stopping this module are listed in table 43.3 and examples of stopping operation are shown in figure 43.2. Table 43.3 Stop Conditions Attenuator Function Off STPM SGST SGEND SGDEF Attenuator Function On Operation STPM SGST SGEND SGDEF Operation 0 0 x x Stopped 0 0 x x Stopped 0 1 x x Output 0 1 x x Output 1 0 0 x Retained* 1 0 x 0 Retained* 1 0 1 x Stopped 1 0 x 1 Stopped 1 1 0 x Output 1 1 x 0 Output 1 1 1 x Output 1 1 x 1 Output Legend: x: Don't care Note: * Previous state is held. Page 2474 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 43 Sound Generator Attenuator function Off • STPM = 0 SGST SGEND SGOUT 0 is written to SGST Operation is stopped • STPM = 1 SGST SGEND SGOUT 0 is written to SGST Operation is stopped Attenuator function On • STPM = 0 SGST SGDEF (Attenuation end flag) SGOUT 0 is written to SGST Operation is stopped • STPM = 1 SGST SGDEF (Attenuation end flag) SGOUT Flag set (Attenuation end) 0 is written to SGST Operation is stopped Flag set Flag clear (Attenuation end) Figure 43.2 Examples of Stopping Operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2475 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator Start Initial settings Set SGST in SGCR1 to 1 Set SGCR2, SGLR, SGTFR, and SGSFR Start output Attenuator function Off? No (Attenuator function On) Yes No SGDEF = 0? SGST = 0? No Yes Clear SGDEF Yes No No SGST = 0? STPM = 0? Yes No Yes No SGEND = 1? STPM = 0? Yes Yes No SGDEF = 1? Yes End Figure 43.3 Operation Flow Page 2476 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 43.4.2 Section 43 Sound Generator Tone Frequency Setting This module provides tone frequency output in the range of 31 Hz to 20 kHz, with precision of 1% or less. The tone frequency is calculated by: Reference frequency (Hz) = SGCLK (Hz)/SFS Tone frequency (Hz) = Reference frequency (Hz)/(2  TONE) = SGCLK (Hz)/(2  SFS  TONE) Setting values of the TONE bit in SGTFR and SFS bit in SGFSR are calculated by: SFS = SGCLK (Hz)/reference frequency (Hz) (0 < SFS  255) TONE = Reference frequency (Hz)/(2  TONE frequency (Hz)) (0 < TONE  127) An example of relationship between the tone frequency and output error is shown in table 43.4. Table 43.4 Relationship between Tone Frequency and Output Error Tone Frequency SFS[7:0] TONE[6:0] Error (%) 220.00 F7 2E 0.01 329.63 ED 20 0.003 440.00 F7 17 0.01 659.26 ED 10 0.003 880.00 8E 14 0.03 1318.50 ED 8 0.005 1760.00 8E A 0.03 2637.00 ED 4 0.005 3520.00 8E 5 0.03 5274.00 ED 2 0.005 7040.00 47 5 0.03 Note: SGCLK = 5 MHz Since changing P0 frequency affects the tone frequency, care should be taken when changing it. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2477 of 3092 SH7268 Group, SH7269 Group Section 43 Sound Generator 43.4.3 Auto Attenuator Function When the auto attenuator function is on, the loudness data (LD) determines the initial duty cycle for SGOUT. The SGOUT duty cycle is attenuated by a factor of 1/32 using the attenuation cycle set by the DPF bit in SGCR1. The attenuation characteristics are calculated by the equation: LDn = int (LD0  (1  1/32)n) LD: n: SGOUT duty cycle (The initial data is SGLR.) Attenuation cycle number Figure 43.4 is a graph of attenuation characteristics. LD (Loudness data) 256 192 128 64 0 0 32 64 96 128 160 192 Attenuation cycle Figure 43.4 Attenuation Characteristics Page 2478 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 43.4.4 Section 43 Sound Generator Output Waveform As shown in figure 43.5, the output waveform this module is obtained by synthesis of the on-chip 8-bit PWM pulse output and the tone frequency output. The duty cycle for the on-chip 8-bit PWM pulse output is set by SGLR. Loudness data PWM output Reference frequency × 256 + Tone frequency SGOUT Figure 43.5 Output Waveforms 43.5 Interrupt Source When the attenuator function is on and an automatic attenuation operation is completed, the SGDEF bit in SGCSR is set. An interrupt request is issued if the SGIE bit in SGCSR is set to 1. When STPM = 0, the SGDEF bit is set only when the first attenuation operation is completed. If the SGDEF bit is cleared during automatic attenuation, the SGDEF bit is set when the next attenuation operation is completed. Table 43.5 Interrupt Source Name Interrupt Source Interrupt Flag SGDEI Attenuation end SGDEF 256 Loudness data 0 t [Time] SGST SGDEF Figure 43.6 Attenuation End Flag Setting Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2479 of 3092 Section 43 Sound Generator 43.6 Usage Note 43.6.1 Module Stop Mode Settings SH7268 Group, SH7269 Group The module stop control register enables or disables the operation of this module. With the initial setting, the operation of this module is stopped. Register access is enabled by canceling module stop mode. For details, see section 49, Power-Down Modes. Page 2480 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 44 SD Host Interface Section 44 SD Host Interface Renesas Electronics Corporation is only able to provide information contained in this section to parties with which we have concluded a nondisclosure agreement. Please contact one of our sales representatives for details. For the features and electrical characteristics of the SD host interface, consult section 1, Overview and section 52, Electrical Characteristics, respectively. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2481 of 3092 Section 44 SD Host Interface Page 2482 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Section 45 MMC Host Interface The MMC host interface is a host controller conforming to the JEDEC Standard JESD84-A44 that allows connection with devices with the MMC interface. 45.1        Features Supports 1/4/8-bit MMC bus Supports the Single Data Rate only MMC clock frequency = P1 frequency/2n (n = 1 to 10). Data buffer: 512 bytes  2 Three types of interrupt requests: normal operation, error/timeout, card detection. DMA transfer requests: buffer write and buffer read Card detection function R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2483 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Figure 45.1 shows a block diagram of this module. MMC host interface Module clock Host I/F Peripheral bus 1 Registers Sequence generation Card socket Card I/F MMC_CLK MMC_CMD DMA (buffer write/read) Direct memory access controller Interrupt controller MMC_D[7:0] DMA control MMC_CD Interrupt (normal operation, error/timeout, card detection) Buffer I/F Interrupt control Card detection . . . Buffer A 512 bytes Buffer B 512 bytes Figure 45.1 Block Diagram of MMC Host Interface 45.2 Input/Output Pins Table 45.1 shows the pin configuration of this module. Table 45.1 Pin Configuration Pin Name I/O Function MMC_CLK Output MMC clock MMC_CMD Input/output Command/response MMC_D[7:0] Input/output Transmit/receive data MMC_CD Input Card detection* Note: * Check the specifications of the card socket to be used before connection. Page 2484 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.3 Section 45 MMC Host Interface Register Descriptions Table 45.2 shows the register configuration of this module. Table 45.2 Register Configuration Register Name Abbreviation R/W Address Access Size Command setting register CE_CMD_SET R/W H'E8030800 16, 32 Argument register CE_ARG R/W H'E8030808 16, 32 Argument register for automatically-issued CMD12 CE_ARG_CMD12 R/W H'E803080C 16, 32 Command control register CE_CMD_CTRL R/W H'E8030810 16, 32 Transfer block setting register CE_BLOCK_SET R/W H'E8030814 16, 32 Clock control register CE_CLK_CTRL R/W H'E8030818 16, 32 Buffer access configuration register CE_BUF_ACC R/W H'E803081C 16, 32 Response register 3 CE_RESP3 R H'E8030820 16, 32 Response register 2 CE_RESP2 R H'E8030824 16, 32 Response register 1 CE_RESP1 R H'E8030828 16, 32 Response register 0 CE_RESP0 R H'E803082C 16, 32 Response register for automatically-issued CMD12 CE_RESP_CMD12 R H'E8030830 16, 32 Data register CE_DATA R/W H'E8030834 16*, 32 Interrupt flag register CE_INT R/W H'E8030840 16, 32 Interrupt enable register CE_INT_EN R/W H'E8030844 16, 32 Status register 1 CE_HOST_STS1 R H'E8030848 16, 32 Status register 2 CE_HOST_STS2 R H'E803084C 16, 32 DMA mode setting register CE_DMA_MODE R/W H'E803085C 16, 32 Card detection/port control register CE_DETECT R/W H'E8030870 16, 32 Special mode setting register CE_ADD_MODE R/W H'E8030874 16, 32 Version register CE_VERSION R/W H'E803087C 16, 32 Note: Do not access registers other than those shown above. Note: * For 16-bit access, H'E8030834 is the only address for access. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2485 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.1 Command Setting Register (CE_CMD_SET) CE_CMD_SET sets a command sequence. The command sequence starts when the settings have been made in bits 31 to 16. Note that writing to CE_CMD_SET is disabled while a command sequence is proceeding (i.e., the value of CMDSEQ in CE_HOST_STS1 is 1). CE_CMD_SET should be set according to the description in section 45.7.12, Setting Values of CE_CMD_SET. Bit: Initial value: R/W: Bit: 31 30 — — 0 R 0 R 15 14 RIDXC[1:0] Initial value: 0 R/W: R/W 0 R/W 29 28 27 26 25 24 23 CMD[5:0] 0 R/W 0 R/W 0 R/W 13 12 0 R/W 22 RTYP[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 21 20 RBSY — WDAT DWEN CMLTE 19 18 0 R/W 0 R 0 R/W 0 R/W 17 16 CMD12 EN 0 R/W 0 R/W 0 11 10 9 8 7 6 5 4 3 2 1 RCRC7C[1:0] — CRC 16C — CRC STE TBIT OPDM — — SBIT — DATW[1:0] 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R 0 R/W Bit Bit Name Initial Value R/W 31, 30  00 R 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 29 to 24 CMD[5:0] All 0 R/W Command Index These bits set a command index ([45:40]). Note: Setting a command index in these bits initiates the command sequence. 23, 22 RTYP[1:0] 00 R/W Response Type 00: No response 01: 6-byte response (R1, R1b, R3, R4, R5) 10: 17-byte response (R2) 11: Setting prohibited 21 RBSY 0 R/W Response Busy Select Selects whether “busy” is involved in response reception. 0: No response busy 1: Response busy involved (R1b) Page 2486 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W Description 20  0 R Reserved This bit is always read as 0. The write value should always be 0. 19 WDAT 0 R/W Presence/Absence of Data 0: No data 1: With data 18 DWEN 0 R/W Read/Write (valid when “with data” is selected) 0: Read from the card 1: Write to the card 17 CMLTE 0 R/W Single/Multi Block Transfer Select (valid when “with data” is selected) 0: Single-block transfer 1: Multi-block transfer 16 CMD12EN 0 R/W Automatic CMD12 Issuance (valid when multi-block transfer is selected) 0: Does not issue CMD12 automatically. 1: Issues CMD12 automatically (= automatic CMD12) For details of automatic CMD12 issuance, see section 45.6.4, Automatic CMD12 Issuance. Note: Set the transfer block size to 512 bytes. Set RBSY to 0. 15, 14 RIDXC[1:0] 00 R/W Response Index Check Specify the items to be checked for [45:40] of a 6-byte response or [133:128] of a 17-byte response. 00: Checks the response index (ensure that the response index matches the command index.) 01: Checks the check bits (ensure that the bits are all 1.) 10: No checking 11: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2487 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name 13, 12 RCRC7C [1:0] Initial Value R/W Description 00 R/W Response CRC7 Check Specify the items to be checked for [7:1] of a 6-byte response or a 17-byte response. 00: Checks CRC7 (set the response type to 01) 01: Checks the check bits (set the response type to 01) 10: Checks internal CRC7 (R2 only) (set the response type to 10) 11: No checking 11  0 R Reserved The write value should always be 0. 10 CRC16C 0 R/W CRC16 Check in Reception (valid when “with data” and “read” are selected) 0: Checks CRC16 1: Does not check CRC16 (use when CMD14) 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8 CRCSTE 0 R/W CRC Status Reception (valid when “with data” and “write” are selected) 0: Receives CRC status 1: Does not receive CRC status (use when CMD19) 7 TBIT 0 R/W Transmission Bit Setting 0: Sets the transmission bit ([46]) to 1. 1: Sets the transmission bit ([46]) to 0. 6 OPDM 0 R/W Open-Drain Output Mode 0: Normal output 1: Open-drain output Note: This setting is only applied to the MMC_CMD line. 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2488 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W Description 3 SBIT 0 R/W Read Data Start Bit Detection (valid when "with data" and "read" are selected) 0: Detects the start bit when the MMC_D signals set by DATW are all 0. 1: Detects the start bit when MMC_D[0] is 0. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 DATW[1:0] 00 R/W Data Bus Width Setting (valid when "with data" is selected) 00: 1 bit 01: 4 bits 10: 8 bits 11: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2489 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.2 Argument Register (CE_ARG) CE_ARG sets the argument for the command to be transmitted. Set CE_ARG before starting the command sequence. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ARG[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ARG[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 0 ARG[31:0] H'00000000 R/W These bits set [39:8] of a command. Note: Set the argument of automaticallyissued CMD12 by CE_ARG_CMD12. 45.3.3 Argument Register for Automatically-Issued CMD12 (CE_ARG_CMD12) CE_ARG_CMD12 is used to set the argument for the automatically-issued CMD12 in multi-block transfer. For the automatically-issued CMD12, see section 45.6.4, Automatic CMD12 Issuance. Set CE_ARG_CMD12 before starting the command sequence. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C12ARG[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W C12ARG[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 0 C12ARG[31:0] H'00000000 R/W These bits set [39:8] of a command. Page 2490 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.3.4 Section 45 MMC Host Interface Command Control Register (CE_CMD_CTRL) CE_CMD_CTRL is used to terminate a command sequence forcibly. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — — — — — — — BREAK 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 BREAK 0 R/W Forcible Termination of Command Sequence To discontinue the current command sequence, write 1 to this bit while the bit is 0 and then write 0. After the above procedure, check if the value of the CMDSEQ bit in CE_HOST_STS1 has become 0 and then perform a software reset. Note: Since a software reset returns the register value to the initial value, the register needs be set again. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2491 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.5 Transfer Block Setting Register (CE_BLOCK_SET) CE_BLOCK_SET specifies the size of the block and the number of blocks for the data to be transferred. Set CE_BLOCK_SET before starting the command sequence. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BLKCNT[15:0] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W BLKSIZ[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W Initial Value R/W Description BLKCNT [15:0] H'0000 R/W Number of Blocks for Transfer BLKSIZ [15:0] H'0200 Bit Bit Name 31 to 16 15 to 0 0 R/W Page 2492 of 3092 Note: This setting is valid for multi-block transfer. R/W Transfer Block Size Note: Transfer block size should be set as follows.  Single-block transfer: 1 to 512 bytes  Multi-block transfer: 512 bytes R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.3.6 Section 45 MMC Host Interface Clock Control Register (CE_CLK_CTRL) CE_CLK_CTRL controls the MMC clock and sets timeout values. Do not change the setting of this register while a command sequence is in progress. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 — — — — — — — CLKEN — — — — Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 — — 0 R 0 R Initial value: R/W: SRSPTO[1:0] 0 R/W 0 R/W SRBSYTO[3:0] 0 R/W 0 R/W 0 R/W SRWDTO[3:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 25  All 0 R Reserved 0 R/W 0 R/W 0 R/W 19 18 17 16 CLKDIV[3:0] 0 R/W 0 R/W 0 R/W 0 R/W 3 2 1 0 — — — — 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 24 CLKEN 0 R/W MMC Clock Output Control 0: Does not output the MMC clock (tied to low level) 1: Outputs the MMC clock 23 to 20  00 R Reserved These bits are always read as 0. The write value should always be 0. 19 to 16 CLKDIV[3:0] 0000 R/W MMC Clock Frequency Setting 0000: P1/2 0001: P1/22 0111: P1/28 9 1000: P1/2 1001: P1/210 1010 to 1111: Setting prohibited 15, 14  0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2493 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name 13, 12 SRSPTO [1:0] Initial Value R/W Description 00 R/W Response Timeout Setting Specifies the timeout period for the RSPTO bit of CE_INT. 00: 64 MMC clock cycles 01: 128 MMC clock cycles 10: 256 MMC clock cycles 11: Setting prohibited 11 to 8 SRBSYTO [3:0] 0000 R/W Response Busy Timeout Setting Specifies the timeout period for the RBSYTO bit of CE_INT. 0000: 214 MMC clock cycles 0001: 215 MMC clock cycles : 1110: 228 MMC clock cycles 1111: 229 MMC clock cycles 7 to 4 SRWDTO [3:0] 0000 R/W Write Data/Read Data Timeout Setting Specifies the timeout period for the WDATTO and RDATTO bits of CE_INT. 0000: 214 MMC clock cycles 0001: 215 MMC clock cycles : 1110: 228 MMC clock cycles 1111: 229 MMC clock cycles 3 to 0  0000 R Reserved These bits are always read as 0. The write value should always be 0. Page 2494 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.3.7 Section 45 MMC Host Interface Buffer Access Configuration Register (CE_BUF_ACC) CE_BUF_ACC configures the method of accessing data registers and mode of DMA transfer. Do not change the setting of this register while a command sequence is in progress. For explanation of the buffers, see section 45.6.3, Buffer Structure and Buffer Accesses. Bit: 31 30 29 28 27 26 — — — — — — Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — — — — — — — — 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: 25 24 DMAW DMAR EN EN 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 26  All 0 R Reserved 23 22 21 20 19 18 — — — — — — 0 R 0 R 0 R 0 R 0 R 0 R 17 16 BUSW ATYP 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 25 DMAWEN 0 R/W Buffer Write DMA Transfer Request Enable 0: Disables DMA transfer request for buffer writing 1: Enables DMA transfer request for buffer writing 24 DMAREN 0 R/W Buffer Read DMA Transfer Request Enable 0: Disables DMA transfer request for buffer reading 1: Enables DMA transfer request for buffer reading 23 to 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 BUSW 0 R/W Data register access size selection 0: When access to CE_DATA in 32-bit. 1: When access to CE_DATA in 16-bit. 16 ATYP 0 R/W 0: When not swapped byte-wise. 1: When swapped byte-wise. Note: For explanation of the buffers, see section 45.6.3, Buffer Structure and Buffer Accesses. 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2495 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.8 Response Registers 3 to 0 (CE_RESP3 to CE_RESP0) CE_RESP3 to CE_RESP0 are the registers for storing the response that has been received. For the formats of response values, see section 45.6.1, Command/Response Formats.  CE_RESP3 Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSP[127:112] Initial value: 0 R/W: R Bit: 15 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 9 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R RSP[111:96] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 0 RSP[127:96] H'00000000 R [127:96] of a 17-byte response are stored.  CE_RESP2 Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSP[95:80] Initial value: 0 R/W: R Bit: 15 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 9 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R RSP[79:64] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 0 RSP[95:64] H'00000000 R [95:64] of 17-byte response are stored. Page 2496 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface  CE_RESP1 Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSP[63:48] Initial value: 0 R/W: R Bit: 15 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 9 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R RSP[47:32] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 0 RSP[63:32] H'00000000 R [63:32] of a 17-byte response are stored.  CE_RESP0 Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSP[31:16] Initial value: 0 R/W: R Bit: 15 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 9 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R RSP[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 0 RSP[31:0] H'00000000 R [39:8] of a 6-byte response or [17:0] of a 17-byte response are stored. Note: The response to the automaticallyissued CMD12 is stored in CE_RESP_CMD12. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2497 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.9 Response Register for Automatically-Issued CMD12 (CE_RESP_CMD12) CE_RESP_CMD12 is the register for storing the response to the automatically-issued CMD12. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSP12[31:16] Initial value: 0 R/W: R Bit: 15 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 9 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R RSP12[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 0 RSP12[31:0] H'00000000 R [39:8] of a response to the automaticallyissued CMD12 are stored. 45.3.10 Data Register (CE_DATA) CE_DATA is used to access the buffers of this module. In 16-bit access, only DATA[31:16] is accessible. For the write/read data formats, see section 45.6.2, Data Block Format. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DATA[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 0 DATA[31:0] H'00000000 R/W Buffer write/read data [31:0] Page 2498 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.11 Interrupt Flag Register (CE_INT) CE_INT indicates various statuses during execution of a command sequence. Each bit is set when its setting condition has been met. To clear flag(s), write 0 only to the bit(s) to be cleared and write 1 to the other bits. For the operation in the case of an error or timeout, see section 45.6.5, Operation in the Case of Error/Timeout. Bit: Initial value: R/W: Bit: 31 30 29 28 27 — — — — — 26 0 R 0 R 0 R 0 R 0 R 0 R/W 11 10 25 24 23 22 21 20 19 18 — — RBSY CRSP E E 0 R/W 0 R 0 R 0 R/W 4 3 2 CMD12 CMD12 CMD12 DTRAN BUFR BUFW BUFR DRE RBE CRE E E EN EN 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17 16 0 R/W 15 14 13 12 9 8 7 6 5 1 0 CMD VIO BUF VIO — — WDAT RDAT ERR ERR RIDX ERR RSP ERR — — — CRCS WDAT RDAT TO TO TO RBSY TO RSP TO Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W 31 to 27  00 26 CMD12DRE 0 R 0 R/W 0 R/W 0 R/W Description Reserved These bets are always read as 0. The writing value should always be 0. R/W* Automatic CMD12 Issuance & Buffer Read Complete [Setting condition] Response busy for automatically-issued CMD12 and buffer reading have been completed. [Clearing condition] Writing a 0 to this bit Note: When CMD12DRE has been set, CMD12RBE, CMD12CRE, and BUFRE have also been set. So, these bits should be cleared as well. 25 CMD12RBE 0 R/W* Automatic CMD12 Issuance Response Busy Complete [Setting condition] Reception of the response and response busy for an automaticallyissued CMD12 have been completed. [Clearing condition] Writing a 0 to this bit Note: When CMD12RBE is set, CMD12CRE is also set. So, clear the bit as well. When CMD12RBE is set during a multi-block write, DTRANE is also set. So clear the bit as well. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2499 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Initial Value R/W Bit Bit Name 24 CMD12CRE 0 Description R/W* Automatic CMD12 Response Complete [Setting conditions] The response to an automatically-issued CMD12 has been received. [Clearing condition] Writing a 0 to this bit 23 DTRANE 0 R/W* Data Transmission Complete [Setting conditions] Transmission of all blocks of data has been completed.  When configured to receive CRC status: Completion of busy (data busy) after reception of CRC status  When configured not to receive CRC status: Completion of data transmission [Clearing condition] Writing a 0 to this bit 22 BUFRE 0 R/W* Buffer Read Complete [Setting conditions] All blocks of data have been received and the data have been read from the buffer [Clearing condition] Writing a 0 to this bit 21 BUFWEN 0 R/W* Buffer Write Ready [Setting conditions] The buffer has become empty and ready for writing. [Clearing condition] Writing a 0 to this bit Note: This bit is not set when DMA transfer request for buffer writing is enabled. 20 BUFREN 0 R/W* Buffer Read Ready [Setting conditions] Transfer block size of data have been stored in the buffer and it has become ready for reading [Clearing condition] Writing a 0 to this bit Note: This bit is not set when DMA transfer request for buffer reading is enabled. 19, 18  0 R Reserved These bits are always read as 0.The write value should always be 0. Page 2500 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W 17 RBSYE 0 Description R/W* Response Busy Complete [Setting condition] Reception of a response and response busy have been completed. [Clearing condition] Writing a 0 to this bit Note: When RBSYE has been set, CRSPE has also been set. So, this bit should be cleared as well. Completion of reception of the response and response busy for automatically-issued CMD12 is reflected in CMD12RBE. 16 CRSPE 0 R/W* Command/Response Complete [Setting conditions] A command has been transmitted or a response has been received  When configured not to receive response: A command has been transmitted  When configured to receive 6- or 17-byte response: A response has been received [Clearing condition] Writing a 0 to this bit Note: Completion of reception of the response to automaticallyissued CMD12 is reflected in CMD12CRE. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2501 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W 15 CMDVIO 0 Description R/W* Command Issuance Error [Setting conditions] Illegal setting has been made in CE_CMD_SET or CE_BLOCK_SET.  During execution of a command sequence: Writing to CMD[5:0] in CE_CMD_SET (The command sequence is not stopped automatically.)  At the start of command sequence: Writing to CMD[5:0] in CE_CMD_SET when the registers have been set for one of the following combinations of selection  No response + response busy  No response + with data  No data + automatic CMD12 issuance  With data + single-block transfer + automatic CMD12 issuance  With data + response busy + automatic CMD12 issuance  With data + transfer block size = 0  With data + transfer block size  513  With data + multi-block transfer + number of blocks for transfer = 0 [Clearing condition] Writing a 0 to this bit Page 2502 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W 14 BUFVIO 0 Description R/W* Buffer Access Error [Setting conditions] Illegal buffer access has been attempted.  CE_ DATA has been accessed exceeding the block size set in BLKSIZ[15:0] in CE_BLOCK_SET  While data is being read from the card: CE_DATA has been accessed with BUFREN not set (when DMA is used, with no DMA transfer request asserted for buffer reading)  While data is being written to the card: CE_DATA has been accessed with BUFWEN not set (when DMA is used, with no DMA transfer request asserted for buffer writing) [Clearing condition] Writing a 0 to this bit Note: When BUFVIO has been set, the command sequence is not stopped automatically. 13, 12  00 R Reserved These bits are always read as 0. The write value should always be 0. 11 WDATERR 0 R/W* Write Data Error [Setting conditions] Error is found in the data that has been written.  Error is in the status of the CRC status  Error is in the end bits of the CRC status [Clearing condition] Writing a 0 to this bit Note: When WDATERR has been set, the command sequence is stopped automatically. 10 RDATERR 0 R/W* Read Data Error [Setting conditions] Error is found in the read data.  Error is in CRC16 of the read data  Error is in the end bits of the read data [Clearing condition] Writing a 0 to this bit Note: When RDATERR has been set, the command sequence is stopped automatically. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2503 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W 9 RIDXERR 0 Description R/W* Response Index Error [Setting conditions] Error has been found in the index value of the response.  When an error has been found in [45:40] of a 6-byte response (including automatically-issued CMD12) or [133:128] of a 17-byte response (The items to be checked are set by RIDXC in CE_CMD_SET.) [Clearing condition] Writing a 0 to this bit Note: When RIDXERR has been set, the command sequence is stopped automatically. 8 RSPERR 0 R/W* Response Error [Setting conditions] Error has been found in the response values of the response.  Transmission bit in the response is high  Error is in the end bits of the response  When an error has been found in [7:1] of a 6-byte response (including automatically-issued CMD12) or a 17-byte response (The items to be checked are set by RCRC7C in CE_CMD_SET.) [Clearing condition] Writing a 0 to this bit Note: When RSPERR has been set, the command sequence is stopped automatically. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 CRCSTO 0 R/W* CRC Status Timeout [Setting conditions] CRC status could not be received [Clearing condition] Writing a 0 to this bit Note: The command sequence is not stopped even if CRCSTO is set. Page 2504 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W 3 WDATTO 0 Description R/W* Write Data Timeout [Setting conditions] The busy status remains unchanged after the period set by SRWDTO in CE_CLK_CTRL after the CRC status was received. [Clearing condition] Writing a 0 to this bit Note: The command sequence is not stopped even if WDATTO is set. 2 RDATTO 0 R/W* Read Data Timeout [Setting conditions]  Read data could not be received within the period set by SRWDTO in CE_CLK_CTRL after the read command was transmitted  Read data could not be received within the period set by SRWDTO in CE_CLK_CTRL after the read data was received. [Clearing condition] Writing a 0 to this bit Note: The command sequence is not stopped even if RDATTO is set. 1 RBSYTO 0 R/W* Response Busy Timeout [Setting conditions] The busy status remains unchanged after the period set by SRBSYTO in CE_CLK_CTRL after the command (including automatically-issued CMD12) was transmitted. [Clearing condition] Writing a 0 to this bit Note: The command sequence is not stopped even if RBSYTO is set. 0 RSPTO 0 R/W* Response Timeout [Setting conditions] Response could not be received within the period set by SRSPTO in CE_CLK_CTRL after the command (including automatically-issued CMD12) was transmitted. [Clearing condition] Writing a 0 to this bit Note: The command sequence is not stopped even if RSPTO is set. Note: * A 0 is the only value that can be written to these bits. Writing a 1 is ignored. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2505 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.12 Interrupt Enable Register (CE_INT_EN) CE_INT_EN controls output of the CE_INT-related interrupt signals. If a flag in CE_INT is set to 1 while its corresponding bit in CE_INT_EN is set to 1, an interrupt request is output. For details on interrupt requests, see section 45.4, Interrupt Requests. Bit: Initial value: R/W: Bit: 31 30 29 28 27 — — — — — 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 — — 0 R 0 R MCMD MBUF VIO VIO Initial value: 0 R/W: R/W 0 R/W 26 25 24 23 22 21 20 19 18 — — 0 R/W 0 R 0 R 0 R/W 0 R/W 4 3 2 1 0 MCMD MCMD MCMD MDT MBUF MBUF MBUF 12DRE 12RBE 12CRE RANE RE WEN REN MWDAT MRDAT MRIDX MRSP ERR ERR ERR ERR 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 27  All 0 R Reserved 0 R/W 0 R/W 0 R/W 7 6 5 — — — 0 R 0 R 0 R 17 16 MRBSY MCRSP E E MCRC MWDA MRDA MRBS MRSP STO TTO TTO YTO TO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 26 MCMD12DRE 0 R/W CMD12DRE Interrupt Enable 0: Disables interrupt output by the CMD12DRE flag 1: Enables interrupt output by the CMD12DRE flag 25 MCMD12RBE 0 R/W CMD12RBE Interrupt Enable 0: Disables interrupt output by the CMD12RBE flag 1: Enables interrupt output by the CMD12RBE flag 24 MCMD12CRE 0 R/W CMD12CRE Interrupt Enable 0: Disables interrupt output by the CMD12CRE flag 1: Enables interrupt output by the CMD12CRE flag 23 MDTRANE 0 R/W DTRANE Interrupt Enable 0: Disables interrupt output by the DTRANE flag 1: Enables interrupt output by the DTRANE flag 22 MBUFRE 0 R/W BUFRE Interrupt Enable 0: Disables interrupt output by the BUFRE flag 1: Enables interrupt output by the BUFRE flag 21 MBUFWEN 0 R/W BUFWEN Interrupt Enable 0: Disables interrupt output by the BUFWEN flag 1: Enables interrupt output by the BUFWEN flag Page 2506 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W Description 20 MBUFREN 0 R/W BUFREN Interrupt Enable 0: Disables interrupt output by the BUFREN flag 1: Enables interrupt output by the BUFREN flag 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 MRBSYE 0 R/W RBSYE Interrupt Enable 0: Disables interrupt output by the RBSYE flag 1: Enables interrupt output by the RBSYE flag 16 MCRSPE 0 R/W CRSPE Interrupt Enable 0: Disables interrupt output by the CRSPE flag 1: Enables interrupt output by the CRSPE flag 15 MCMDVIO 0 R/W CMDVIO Interrupt Enable 0: Disables interrupt output by the CMDVIO flag 1: Enables interrupt output by the CMDVIO flag 14 MBUFVIO 0 R/W BUFVIO Interrupt Enable 0: Disables interrupt output by the BUFVIO flag 1: Enables interrupt output by the BUFVIO flag 13, 12  00 R Reserved These bits are always read as 0. The write value should always be 0. 11 MWDATER R 0 R/W WDATERR Interrupt Enable 0: Disables interrupt output by the WDATERR flag 1: Enables interrupt output by the WDATERR flag 10 MRDATERR 0 R/W RDATERR Interrupt Enable 0: Disables interrupt output by the RDATERR flag 1: Enables interrupt output by the RDATERR flag 9 MRIDXERR 0 R/W RIDXERR Interrupt Enable 0: Disables interrupt output by the RIDXERR flag 1: Enables interrupt output by the RIDXERR flag 8 MRSPERR 0 R/W RSPERR Interrupt Enable 0: Disables interrupt output by the RSPERR flag 1: Enables interrupt output by the RSPERR flag R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2507 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 MCRCSTO 0 R/W CRCSTO Interrupt Enable 0: Disables interrupt output by the CRCSTO flag 1: Enables interrupt output by the CRCSTO flag 3 MWDATTO 0 R/W WDATTO Interrupt Enable 0: Disables interrupt output by the WDATTO flag 1: Enables interrupt output by the WDATTO flag 2 MRDATTO 0 R/W RDATTO Interrupt Enable 0: Disables interrupt output by the RDATTO flag 1: Enables interrupt output by the RDATTO flag 1 MRBSYTO 0 R/W RBSYTO Interrupt Enable 0: Disables interrupt output by the RBSYTO flag 1: Enables interrupt output by the RBSYTO flag 0 MRSPTO 0 R/W RSPTO Interrupt Enable 0: Disables interrupt output by the RSPTO flag 1: Enables interrupt output by the RSPTO flag Page 2508 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.13 Status Register 1 (CE_HOST _STS1) CE_HOST STS1 indicates the number of blocks that have been transferred, states of the MMC_CMD and MMC_D lines, index of the received response, and command sequence status. Bit: 31 30 CMD CMD SEQ SIG Initial value: 0 R R/W: R Bit: 15 14 29 28 27 26 25 24 23 22 21 0 R R R R R 8 7 6 5 0 R 0 R RSPIDX[5:0] 0 R 0 R 0 R 0 R 0 R 13 12 11 10 9 20 19 DATSIG[7:0] 18 17 16 R R R R 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R RCVBLK[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 CMDSEQ 0 R Command Sequence Status 0: Command sequence is in the initial state 1: Command sequence is being executed 30 CMDSIG Undefined R MMC_CMD Line Status Indicates the state on the command line. 29 to 24 23 to 16 RSPIDX [5:0] H'00 R DATSIG [7:0] Undefined R Response Index Indicate [45:40] of a 6-byte response or [133:128] of a 17-byte response. MMC_D Status Indicate the states on the MMC_D[7:0] lines. Note: When a communication error or a timeout error occurs, MMC_D[0] may remain 0. 15 to 0 RCVBLK [15:0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H'0000 R Number of Transferred Blocks Indicate the number blocks that have been transferred.  When the DWEN bit in CE_CMD_SET is 0 Number of blocks read from the card  When the DWEN bit in CE_CMD_SET is 1 Number of blocks written to the card Page 2509 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.14 Status Register 2 (CE_HOST _STS2) CE_HOST _STS2 indicates timeout and error statuses. Bit: Initial value: R/W: Bit: 31 30 CRC STE CRC 16E 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 15 — Initial value: R/W: 0 R 29 28 27 26 25 24 23 22 21 20 19 RSP EBE AC12 IDXE RSP IDXE — — — 0 R 0 R 0 R 0 R 0 R 0 R 0 R 9 8 AC12 RSP CRC RDAT AC12R CRCE CRC7E STEBE EBE EBE STRD DATBS CRCST AC12 RSPBS AC12 STRS ATTO YTO TO BSYTO YTO RSPTO PTO 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 CRCSTE 0 R 0 R 18 17 16 CRCST[2:0] 0 R 0 R 0 R 7 6 5 4 3 2 1 0 — — — — — — — — 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R CRC Status Error This bit is set to 1 when an error is found in the CRC status value. 30 CRC16E 0 R Read Data CRC16 Error This bit is set to 1 when an error is found in CRC16 in the read data. 29 AC12CRCE 0 R Automatic CMD12 Response CRC7 Error This bit is set to 1 when an error is found in [7:1] of the response to the automatically-issued CMD12. Note: The items to be checked are set by RCRC7C in CE_CMD_SET. 28 RSPCRC7E 0 R Command Response CRC7 Error (other than automaticallyissued CMD12) This bit is set to 1 when an error is found in [7:1] of a 6-byte response or a 17-byte response. Note: The items to be checked are set by RCRC7C in CE_CMD_SET. 27 CRCSTEBE 0 R CRC Status End Bit Error This bit is set to 1 when an error is found in the end bits in CRC status. 26 RDATEBE 0 R Read Data End Bit Error This bit is set to 1 when an error is found in the end bits in the read data. 25 AC12REBE 0 R Automatic CMD12 Response End Bit Error This bit is set to 1 when an error is found in the end bits of the response to the automatically-issued CMD12. Page 2510 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Bit Bit Name Initial Value R/W Description 24 RSPEBE 0 R 23 AC12IDXE 0 R Command Response End Bit Error (other than automatically-issued CMD12) This bit is set to 1 when an error is found in the end bits of the response. Automatic CMD12 Response Index Error This bit is set to 1 when an error is found in [45:40] of the response to the automatically-issued CMD12. Note: The items to be checked are set by RIDXC in CE_CMD_SET. 22 RSPIDXE 0 R Command Response Index Error This bit is set to 1 when an error is found in [45:40] of a 6byte response or [133:128] of a 17-byte response. Note: The items to be checked are set by RIDXC in CE_CMD_SET. 21 to 19  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 18 to 16 CRCST [2:0] 15  000 R CRC Status Indicate the value of the CRC status that has been received. 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 STRDATTO 0 R Read Data Timeout   13 DATBSYTO 0 R This bit is set to 1 if read data is not received within the period set by the SRWDTO bits in CE_CLK_CTRL after a read command was transmitted. This bit is set to 1 if read data is not received within the period set by the SRWDTO bits in CE_CLK_CTRL after a read data was received. Data Busy Timeout This bit is set to 1 if busy status remains unchanged after the period set by the SRWDTO bits in CE_CLK_CTRL after the CRC status was received. 12 CRCSTTO 0 R CRC Status Timeout This bit is set to 1 if CRC status could not be received. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2511 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface Initial Value R/W Description Bit Bit Name 11 AC12BSYTO 0 R Automatic CMD12 Response Busy Timeout This bit is set to 1 if busy state remains unchanged after the period set by the SRBSYTO bits in CE_CLK_CTRL after the automatically-issued CMD12 was transmitted. 10 RSPBSYTO 0 R Response Busy Timeout This bit is set to 1 if busy state remains unchanged after the period set by the SRBSYTO bits in CE_CLK_CTRL after a command (other than automatically-issued CMD12) was transmitted. 9 AC12RSPTO 0 R Automatic CMD12 Response Timeout This bit is set to 1 if the response is not received within the period set by the SRSPTO bits in CE_CLK_CTRL after the automatically-issued CMD12 was transmitted. 8 STRSPTO 0 R Response Timeout This bit is set to 1 if the response is not received within the period set by the SRSPTO bits in CE_CLK_CTRL after a command (other than automatically-issued CMD12) was transmitted. 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2512 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.15 DMA Mode Setting Register (CE_DMA_MODE) CE_DMA_MODE sets the transfer unit for DMA transfer. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — — — — — — — DMA SEL 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 DMASEL 0 R/W DMA Transfer Size Select Selects the transfer unit for CE_DATA read/write DMA transfer. Set this bit in combination with the transfer size (TS[1:0]) set in the DMA channel control register. 0: 2-byte (word) or 4-byte (longword) unit 1: 16-byte (longword  4) unit Note: When a transfer error or timeout occurs during DMA transfer in 16-byte units, leading to the forced termination of transfer, write 0 to this bit and then set it to 1 again. Also do this whenever a software reset is used. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2513 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.16 Card Detection/Port Control Register (CE_DETECT) CE_DETECT controls the card detection. For details on interrupt requests by the card detection, see section 45.4, Interrupt Requests. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — — — — — Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — CD SIG CD RISE CD FALL — — — — — — MCD RISE MCD FALL — — — — 0 R — R 0 0 R/W* R/W* 0 R — R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14 CDSIG Undefined R MMC_CD Pin Status Indication Indicates the MMC_CD pin status. 13 CDRISE 0 R/W* MMC_CD Pin Rise Detection Flag [Setting condition] The MMC_CD pin level changes from low to high. [Clearing condition] 0 is written to. 12 CDFALL 0 R/W* MMC_CD Pin Fall Detection Flag [Setting condition] The MMC_CD pin level changes from high to low. [Clearing condition] 0 is written to. 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10  Undefined R Reserved The write value should always be 0. 9 to 6  All 0 Reserved These bits are always read as 0. The write value should always be 0. Page 2514 of 3092 R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Bit Bit Name 5 Initial Value Section 45 MMC Host Interface R/W Description MCDRISE 0 R/W CDRISE Interrupt Enable 0: Disables interrupt output by the CDRISE flag. 1: Enables interrupt output by the CDRISE flag. 4 MCDFALL 0 R/W CDFALL Interrupt Enable 0: Disables interrupt output by the CDFALL flag. 1: Enables interrupt output by the CDFALL flag. 3 to 0  R Reserved These bits are always read as 0. The write value should always be 0. All 0 Note: * A 0 is the only value that can be written to these bits. Writing a 1 is ignored. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2515 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.17 Special Mode Setting Register (CE_ADD_MODE) CE_ADD_MODE controls the internal clock. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 — — — — — — — — — — — — CLK MAIN — — — Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 — — — — — — — — — — — — — — — — 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 20  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 19 CLKMAIN 0 R/W Internal Clock Control 0: Normal mode 1: Low power consumption mode (only the card detection is enabled) 18 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2516 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.3.18 Version Register (CE_VERSION) CE_VERSION indicates the version number and controls software reset of this module. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SW RST — — — — — — — — — — — — — — — Initial value: 0 R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 1 R 1 R Bit: 15 VERSION[15:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 SWRST 0 R/W Software Reset 0: Software reset cleared (normal operation) 1: Executes software reset. When SWRST is set to 1, all the register values are reset to the initial values. (SWRST is not reset to the initial value) 30 to 16  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 VERSION [15:0] H'0003 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 R Version Information Indicates the version number of this module. Page 2517 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.4 Interrupt Requests Table 45.3 shows the interrupt request specifications of this module. This module generates three types of interrupt requests: normal operation, error/timeout, and card detection. When an interrupt flag is set to 1and also the corresponding interrupt is enabled, an interrupt request is asserted. Table 45.3 Specifications of Interrupt Requests Flag Register Bit Mask Register Bit Interrupt Request CE_INT CMD12DRE CE_INT_EN MCMD12DRE Normal operation interrupt (MMC2) CE_DETECT CMD12RBE MCMD12RBE CMD12CRE MCMD12CRE DTRANE MDTRANE BUFRE MBUFRE BUFWEN MBUFWEN BUFREN MBUFREN RBSYE MRBSYE CRSPE MCRSPE CMDVIO MCMDVIO BUFVIO MBUFVIO WDATERR MWDATERR RDATERR MRDATERR RIDXERR MRIDXERR RSPERR MRSPERR CRCSTO MCRCSTO WDATTO MWDATTO RDATTO MRDATTO RBSYTO MRBSYTO RSPTO MRSPTO CDRISE CEFALL Page 2518 of 3092 CE_DETECT MCDRISE MCDFALL Error/timeout interrupt (MMC1) Card detection interrupt (MMC0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.5 Section 45 MMC Host Interface DMA Specifications This module provides two channels for DMA transfer requests: one for buffer reading and the other for buffer writing. 45.5.1 DMA for Buffer Writing The DMA transfer request is asserted for buffer writing when the buffer has become empty while the DMAWEN bit in CE_BUF_ACC is set to 1. The DMA transfer request stays asserted for the amount of data specified by BLKSIZ (the block size set in CE_BLOCK_SET)  BLKCNT (the number of blocks for transfer set in CE_BLOCK_SET), and negated after the last block has been transferred. Note that the BUFWEN bit in CE_INT will not be asserted during DMA transfer. If an error has occurred during DMA transfer or DMA transfer is forcibly terminated, the command sequence is stopped automatically, which causes the DMA transfer request to be negated. 45.5.2 DMA for Buffer Reading The DMA transfer request is asserted for buffer reading when the buffer stores data of the block size specified in CE_BLOCK_SET while the DMAREN bit in CE_BUF_ACC is set to 1. The DMA transfer request stays asserted for the amount of data specified by BLKSIZ (the block size set in CE_BLOCK_SET)  BLKCNT (the number of blocks for transfer set in CE_BLOCK_SET), and negated after the last block has been transferred. Note that the BUFREN bit in CE_INT will not be asserted during DMA transfer. If an error has occurred during DMA transfer or DMA transfer is forcibly terminated, the command sequence is stopped automatically, which causes the DMA transfer request to be negated. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2519 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.6 Operation 45.6.1 Command/Response Formats Figure 45.2 shows the format of the command to be transferred. The command index that is set in CMD[5:0] of CE_CMD_SET and the argument set in ARG[31:0] of CE_ARG are reflected in the command. S: Start bit, T: Transmission bit, E: End bit Bit: MMC_CMD 47 46 45:40 39:8 7:1 0 S T Index Argument CRC7 E Transmit the value of CMD[5:0] in CE_CMD_SET Transmit the value of ARG[31:0] in CE_ARG Figure 45.2 Command Format Figures 45.3 and 45.4 show the formats when a 6-byte response and 17-byte response are received, respectively. The response index is stored in RSPIDX[5:0] of CE_HOST_STS1, and the status value of the response is stored to CE_RESP0 or CE_RESP3 to CE_RESP0. S: Start bit, T: Transmission bit, E: End bit Bit: MMC_CMD 47 46 S T 45:40 Set the items to be checked by RIDXC in CE_CMD_SET. 39:8 7:1 0 E Store receive data to RSP[31:0] in CE_RESP0. Set the items to be checked by RCRC7C in CE_CMD_SET. Figure 45.3 Format of 6-Byte Response S: Start bit, T: Transmission bit, E: End bit Bit: MMC_CMD 135 S 134 133:128 127:8 T 7:1 0 E Set the items to be checked by RIDXC in CE_CMD_SET. Store receive data to RSP[127:0] in CE_RESP3 to CE_RESP0. Set the items to be checked by RCRC7C in CE_CMD_SET Figure 45.4 Format of 17-Byte Response (R2) Page 2520 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.6.2 Section 45 MMC Host Interface Data Block Format Figure 45.5 shows the format of data. For details on D0 to D3 in figure 45.5, see section 45.6.3, Buffer Structure and Buffer Accesses. When data is written to a card, data stored in the buffer is transmitted. When data is read from a card, receive data is stored to the buffer. MMC_CLK D0 MMC_D[0] S b7 b6 b0 ... ... b0 crc Data ... crc crc E CRC (a) 1-bit mode MMC_CLK D0 D1 MMC_D[3] S b7 b3 b7 b3 ... b3 crc ... crc crc E MMC_D[2] S b6 b2 b6 b2 ... b2 crc ... crc crc E MMC_D[1] S b5 b1 b5 b1 ... b1 crc ... crc crc E MMC_D[0] S b4 b0 b4 b0 ... b0 crc ... crc crc E Data CRC (b) 4-bit mode MMC_CLK D0 D1 D2 D3 MMC_D[7] S b7 b7 b7 b7 ... b7 crc ... crc crc E MMC_D[6] S b6 b6 b6 b6 ... b6 crc ... crc crc E MMC_D[5] S b5 b5 b5 b5 ... b5 crc ... crc crc E MMC_D[4] S b4 b4 b4 b4 ... b4 crc ... crc crc E MMC_D[3] S b3 b3 b3 b3 ... b3 crc ... crc crc E MMC_D[2] S b2 b2 b2 b2 ... b2 crc ... crc crc E MMC_D[1] S b1 b1 b1 b1 ... b1 crc ... crc crc E MMC_D[0] S b0 b0 b0 b0 ... b0 crc ... crc crc E Data CRC (c) 8-bit mode Figure 45.5 Data Block Format R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2521 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.6.3 Buffer Structure and Buffer Accesses This module has two units of 512-byte RAM as shown in figure 45.6. Therefore, for multi-block writing, if one block of data (512 bytes) stored in one buffer has been transmitted but the other buffer is full, the next block of data can be continuously transmitted. For multi-block reading, if one block of receive data has been stored in one buffer but the other buffer is empty, the next block of receive data can be continuously stored in the buffer. If neither of the buffers is empty for multi-block reading, the MMC clock is stopped and reception is suspended. When one of the buffers becomes empty, the MMC clock supply is started to start reception. The buffer is accessed with CE_DATA. If the transfer block size is set to 4  n + 1 or 4  n + 3, CE_DATA should be accessed for 4  n + 2 bytes or 4  (n + 1) bytes in 16-bit access, and for 4  (n + 1) bytes in 32-bit access. (n = 0, 1, 2, …, 127) 16-bit access 32-bit access 24 23 D0 31 128 words Buffer 16 15 D1 24 23 8 7 D2 16 15 0 8 7 D0 h'34:CE_DATA 31 0 D0 D4 D1 D5 D2 D6 D3 D7 D4 D8 D5 D9 D6 D10 D7 D11 Buffer D8 D12 D12 D16 D16 D24 D9 D13 D13 D17 D17 D21 D10 D14 D14 D18 D18 D22 D11 D15 D15 D19 D19 D23 D20 D24 D24 D104 D104 D108 D21 D25 D25 D105 D489 D109 D22 D26 D26 D106 D106 D110 D23 D27 D27 D107 D491 D111 16 15 24 23 31 D3 128 words 31 h'34:CE_DATA 8 7 0 D1 24 23 16 15 8 7 0 D0 D4 D1 D5 D2 D6 D3 D7 D4 D8 D5 D9 D6 D10 D7 D11 D8 D12 D12 D16 D16 D24 D9 D13 D13 D17 D17 D21 D10 D14 D14 D18 D18 D22 D11 D15 D15 D19 D19 D23 D20 D24 D24 D104 D104 D108 D21 D25 D25 D105 D489D109 D22 D26 D26 D106 D106 D110 D23 D27 D27 D107 D491D111 D492 D112 D493 D113 D494 D114 D495 D115 D492D112 D493D113 D494D114 D495D115 D496 D116 D500 D120 D497 D117 D501 D121 D498 D118 D502 D122 D499 D119 D503 D123 D497D117 D501D121 D505D125 D498D118 D502D122 D506D126 D499D119 D503D123 D507D127 D509 D510 D511 D504 D124 D505 D125 D506 D126 D507 D127 D496D116 D500D120 D504D124 D508 D509 D510 D511 D508 Buffer B Buffer A Buffer B Buffer A Figure 45.6 Double Buffer Structure Page 2522 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface The buffer access select function allows byte-wise swapping of data when the buffer is accessed by writing to or reading from CE_DATA. This function is enabled by the setting of CE_BUFF_ACC. Figure 45.7 shows the specification of 32-bit and 16-bit accesses. 32-bit access [With the default setting] Read from CE_DATA: 31 [Swap in byte units] 24 23 D0 h'34:CE_DATA 31 24 23 D0 Buffer Write to CE_DATA: 31 16 15 24 23 31 8 7 16 15 24 23 0 8 7 D2 31 16 15 24 23 7 8 16 15 0 D3 7 D1 D1 0 D0 8 16 15 24 23 7 D2 D2 D0 Buffer 8 D1 D1 D3 31 0 D3 24 23 Write to CE_DATA: 31 h'34:CE_DATA 16 15 D2 D0 Buffer D3 24 23 D3 0 8 7 16 15 Read from CE_DATA: 31 h'34:CE_DATA D3 D2 D1 0 D3 D2 D1 D0 Buffer 8 7 D2 D1 D0 h'34:CE_DATA 16 15 D1 0 D0 8 D2 D3 16-bit access [With the default setting] [Swap in byte units] Read from CE_DATA: 31 Read from CE_DATA: 31 24 23 D0 h'34:CE_DATA 16 15 8 7 0 D1 31 24 23 D0 Buffer 31 16 15 D1 24 23 D2 h'34:CE_DATA 8 7 D2 16 15 0 D3 8 7 31 16 15 8 D0 0 D3 24 23 D0 Buffer 31 16 15 D1 24 23 D3 h'34:CE_DATA 8 7 D2 16 15 0 D3 8 7 0 D2 31 24 23 D0 Buffer 16 15 D1 8 7 D2 0 D3 24 23 D0 16 15 8 7 0 D1 31 24 23 31 24 23 D1 h'34:CE_DATA 31 16 15 D1 D0 24 23 D2 h'34:CE_DATA 16 15 D1 8 7 D2 0 D3 16 15 8 7 0 D0 Buffer 24 23 D0 Write to CE_DATA: 31 h'34:CE_DATA 31 Buffer Write to CE_DATA: 8 7 D2 16 15 31 0 D3 8 7 0 D3 24 23 D0 Buffer 31 24 23 D3 h'34:CE_DATA 16 15 D1 8 7 D2 16 15 0 D3 8 7 0 D2 31 Buffer 24 23 D1 h'34:CE_DATA 24 23 D0 16 15 D1 8 7 D2 31 0 D3 Buffer 24 23 D0 16 15 D1 8 7 D2 0 D3 n = 0, 1, 2, ... , 255 Figure 45.7 Specification of Byte-Swapping in 32/16-Bit Accesses (n = 1, 2, 3 … 255) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2523 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.6.4 Automatic CMD12 Issuance This module automatically issues CMD12 when multi-block transfer is performed with the CMD12EN in CE_CMD_SET set to 1. Figure 45.8 shows the timing of automatic CMD12 issuance in multi-block read. CMD12 is issued such that the end bit of the command is sent two bits before the end bit of the data during reception of the last block. Automatically issued CMD12 Response to CMD12 MMC_CLK MMC_CMD S T INDEX 5 4 ARG 8 7 6 5 4 3 14 13 12 CRC 1 0 E 3 2 1 S T 2 bits before MMC_D[0] 35 34 32 33 31 30 29 1 0 CRC 15 0 E Last block of the read data Figure 45.8 Timing of Automatically-Issued CMD12 in Multi-Block Read (1-Bit Mode) Figure 45.9 shows the timing of automatic CMD12 issuance in multi-block write. CMD12 is issued after the data busy after transmission of the last block has ended. Automatically issued CMD12 MMC_CLK MMC_CMD MMC_D[0] S 0 CRC 15 14 1 0 E CRCstatus S 0 1 0 E T INDEX 5 4 Data busy Last block of the write data Figure 45.9 Timing of Automatically-Issued CMD12 in Multi-Block Write (1-Bit Mode) The argument of the automatically-issued CMD12 is set by CE_ARG_CMD12. The value of [39:8] of the response to CMD12 is stored to CE_RESP_CMD12. The busy status on response reception is received. Page 2524 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.6.5 Section 45 MMC Host Interface Operation in the Case of Error/Timeout This module may not be stopped in case of error occurrence. If the command sequence is in progress when an error occurs (check the CMDSEQ bit in CE_HOST_STS1), terminate the sequence forcibly and perform a software reset. The data for transmission or received data that had been stored in the buffers at the time of error occurrence are not guaranteed. This module is not stopped when a timeout has occurred. To execute the next command after a timeout error has occurred, terminate the sequence forcibly, perform a software reset. For forcible termination, refer to section 45.7.11, Forcible Termination. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2525 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7 Examples of Setting This section shows the procedures for executing typical command sequences. 45.7.1 Legends Figure 45.10 shows the legends for the symbols used in the figures in the following subsections. State of MMC_CMD and MMC_D lines Interrupt and buffer states Flowchart and register setting INT CPU BUF HOST CARD HOST (MMC_ CMD) : Initial state INT : Interrupt CARD (MMC _D) BUF:W : Buffer write CMD:S : Transmit command BUF:R : Buffer read RSP:R : Receive response DAT:S : Transmit data : Register access CRCST:R : Waiting for certain processing to end : Conditional branch : Receive CRC status BUSY:R : Receive busy DAT:R : Receive data Figure 45.10 Legends for the Symbols Used in the Figures Page 2526 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.7.2 Section 45 MMC Host Interface Command Transmission INT CPU BUF Settings for command transmission CARD (MMC_ CMD) Start Settings prior to command transmission HOST Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_INT_EN , H'0001_CF3F); Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'0000_0000); Waiting for command response complete flag HOST CARD (MMC _D) CMD:S INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Idle Figure 45.11 Command Transmission (CMD0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2527 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7.3 Command Transmission  Response Reception INT Write(CE_INT Settings for command transmission BUF HOST CARD HOST CARD (MMC _CMD) Start Settings prior to command transmission CPU (MMC _D) , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_INT_EN , H'0001_CF3F); Write(CE_ARG , H****_****); Write(CE_CMD_SET , H'0D40_0000); CMD:S Waiting for command response complete flag RSP:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Error/timeout processing Idle Figure 45.12 Command Transmission  Response Reception (CMD3) Page 2528 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.7.4 (1) Section 45 MMC Host Interface Command Transmission  Response Reception (with Response Busy) When the busy time period is less than the period set by SRBSYTO in CE_CLK_CTRL INT Write(CE_INT Settings for command transmission BUF HOST CARD HOST CARD (MMC _CMD) Start Settings prior to command transmission CPU (MMC _D) , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0*00); Write(CE_INT_EN , H'0001_CF3F); Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'0660_0000); CMD:S Waiting for command response complete flag RSP:R BUSY:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Error check Response check Enable setting Read(CE_RESP0); Write(CE_INT_EN , H'0002_CF3F); Waiting for response busy complete flag INT Flag check Read(CE_INT); Write(CE_INT , H'FFFD_FFFF); Error check Error/timeout processing Idle Figure 45.13 Command Transmission  Response Reception (with Response Busy) (CMD6) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2529 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface (2) When the busy time period may be equal to or beyond the period set by SRBSYTO in CE_CLK_CTRL INT CPU BUF HOST CARD HOST CARD (MMC_ CMD) Start Write(CE_INT Settings prior to command transmission Settings for command transmission (MMC _D) , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0F00); Write(CE_INT_EN , H'0001_CF3F); Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'2660_0000); Set and start a timer in other modules (because the timer in this module cannot be used for check the busy time). CMD:S Waiting for command response complete flag RSP:R BUSY:R INT Read(CE_INT); Flag check Write(CE_INT , H'FFFE_FFFF); Error check Read(CE_RESP0); Response check Write(CE_INT_EN Enable setting , H'0002_CF3F); Waiting for response busy complete flag INT Read(CE_INT); Flag check Error Determination Write(CE_INT Response busy timeout flag only Response busy complete flag only Error/timeout processing Idle , H'FFFD_FFFF); Forcible termination Checking the end of busy state by CMD13. Check is performed until the specified timer value is exceeded. Figure 45.14 Command Transmission  Response Reception (with Response Busy) (CMD38) Page 2530 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.7.5 Section 45 MMC Host Interface Single-Block Read INT CPU BUF Start Settings prior to command transmission Settings for command transmission Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_BUF_ACC , H'0000_0000); Write(CE_INT_EN , H'0001_CF3F); Write(CE_BLOCK_SET , H'0000_0***); Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'1148_0002); HOST CARD HOST CARD (MMC _CMD) (MMC _D) CMD:S Waiting for command response complete flag RSP:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Enable setting Write(CE_INT_EN , H'0050_CF3F); Waiting for buffer read enable flag DAT:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFEF_FFFF); Error check Buffer read (for the block size) Read(CE_DATA); BUF:R Waiting for buffer read complete flag INT Read(CE_INT); Flag check Write(CE_INT , H'FFBF_FFFF); Error check Error/timeout processing Idle Figure 45.15 Single-Block Read (CMD17) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2531 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7.6 Multi-Block Read INT Start Settings prior to command transmission Settings for command transmission Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_BUF_ACC , H'0000_0000); Write(CE_INT_EN , H'0001_CF3F); Write(CE_BLOCK_SET , H'****_0200); Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'124A_0002); CPU BUF HOST CARD HOST CARD (MMC _CMD) (MMC _D) CMD:S Waiting for command response complete flag RSP:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Enable setting Write(CE_INT_EN , H'0050_CF3F); Waiting for buffer read enable flag DAT:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFEF_FFFF); Error check Buffer read (for the block size) Read(CE_DATA); BUF:R Final block read complete Waiting for buffer read complete flag INT Flag check Read(CE_INT); Write(CE_INT , H'FFBF_FFFF); Error check Error/timeout processing Idle Figure 45.16 Multi-Block Read (CMD18 Pre-Defined) Page 2532 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.7.7 Section 45 MMC Host Interface Multi-Block Read (with Automatic CMD12 Issuance) INT Start Settings prior to command transmission Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_BUF_ACC Write(CE_INT_EN CPU BUF HOST CARD HOST CARD (MMC _CMD) (MMC _D) , H'0000_0000); , H'0001_CF3F); Write(CE_BLOCK_SET , H'****_0200); Settings for command transmission Write(CE_ARG , H'****_****); Write(CE_ARG_CMD12 , H'****_****); Write(CE_CMD_SET , H'124B_0002); CMD:S Waiting for command response complete flag RSP:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Enable setting Write(CE_INT_EN , H'0410_CF3F); CMD12 is automatically issued when the final block is transferred. Waiting for buffer read enable flag CMD:S DAT:R INT Flag check Read(CE_INT); Write(CE_INT RSP:R , H'FFEF_FFFF); Error check Buffer read (for the block size) BUF:R Read(CE_DATA); Final block read complete Waiting for complete flags for automatically-issued CMD12 and buffer read INT Flag check Read(CE_INT); Write(CE_INT , H'F8BF_FFFF); Error check Response check Error/timeout processing Read(CE_RESP_CMD12); Idle Figure 45.17 Multi-Block Read (with Automatic CMD12 Issuance) (CMD18 Open-Ended) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2533 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7.8 Single-Block Write Start INT Settings prior to command transmission Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_BUF_ACC , H'0000_0000); Write(CE_INT_EN , H'0001_CF3F); CPU BUF HOST CARD HOST CARD (MMC _CMD) (MMC _D) Write(CE_BLOCK_SET , H'0000_0***); Settings for command transmission Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'184C_0002); CMD:S Waiting for command response complete flag RSP:R INT Read(CE_INT); Flag check Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Enable setting Write(CE_INT_EN , H'00A0_CF3F); INT Waiting for buffer write enable flag Read(CE_INT); Flag check Buffer write (for the block size) Write(CE_INT , H'FFDF_FFFF); Write(CE_DATA , H'****_****); BUF:W DAT:S CRCST:R Waiting for data transmission complete flag BUSY:R INT Read(CE_INT); Flag check Write(CE_INT , H'FF7F_FFFF); Error check Error/timeout processing Idle Figure 45.18 Single-Block Write (CMD24) Page 2534 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 45.7.9 Section 45 MMC Host Interface Multi-Block Write INT Start Settings prior to command transmission Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Write(CE_BUF_ACC , H'0000_0000); Write(CE_INT_EN , H''h0001_CF3F); CPU BUF HOST CARD HOST CARD (MMC _CMD) (MMC _D) Write(CE_BLOCK_SET , H'****_0200); Settings for command transmission Write(CE_ARG , H'****_****); Write(CE_CMD_SET , H'194E_0002); CMD:S Waiting for command response complete flag RSP:R INT Read(CE_INT); Flag check Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Enable setting Write(CE_INT_EN , H'00A0_CF3F); Waiting for buffer write enable flag INT Flag check Read(CE_INT); Write(CE_INT , H'FFDF_FFFF); Write(CE_DATA , H'****_****); Error check Buffer write (for the block size) BUF:W DAT:S CRCST:R Final block write complete BUSY:R Waiting for data transmission complete flag INT Flag check Read(CE_INT); Write(CE_INT , H'FF7F_FFFF); Error check Error/timeout processing Idle Figure 45.19 Multi-Block Write (CMD25 Pre-Defined) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2535 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7.10 Multi-Block Write (with Automatic CMD12 Issuance) Write(CE_INT , H'0000_0000); Write(CE_CLK_CTRL , H'0100_0000); Settings prior to command transmission Write(CE_BUF_ACC , H'0000_0000); Write(CE_INT_EN , H'0001_CF3F); Settings for command transmission Write(CE_ARG Start INT CPU BUF HOST CARD HOST CARD (MMC _CMD) (MMC _D) Write(CE_BLOCK_SET , H'****_0200); , H'****_****); Write(CE_ARG_CMD12 , H'****_****); Write(CE_CMD_SET , H'194F_0002); CMD:S Waiting for command response complete flag RSP:R INT Flag check Read(CE_INT); Write(CE_INT , H'FFFE_FFFF); Error check Response check Read(CE_RESP0); Enable setting Write(CE_INT_EN , H'0220_CF3F); Waiting for buffer write enable flag INT Flag check Read(CE_INT); Write(CE_INT , H'FFDF_FFFF); Write(CE_DATA , H'****_****); Error check Buffer write (for the block size) BUF:W DAT:S CRCST:R Final block write complete CMD12 is automatically issued when the final block is transferred. BUSY:R CMD:S Waiting for automatically-issued CMD12 response busy complete flag RSP:R BUSY:R INT Read(CE_INT); Flag check Write(CE_INT , H'FC7F_FFFF); Error check Response check Error/timeout processing Read(CE_RESP_CMD12); Idle Figure 45.20 Multi-Block Write (with Automatic CMD12 Issuance) (CMD25 Open-Ended) Page 2536 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7.11 Forcible Termination INT CPU BUF Command sequence in progress Enable setting Settings for forcible termination of command sequence Check of command sequence status HOST CARD (MMC _CMD) Write(CE_INT_EN , H'0000_0000); Write(CE_CMD_CTRL , H'0000_0001); Write(CE_CMD_CTRL , H'0000_0000); HOST CARD (MMC _D) Read(CE_HOST_STS1); Termination check Software reset execution Write(CE_VERSION , H'8000_0000); Write(CE_VERSION , H'0000_0000); Idle Figure 45.21 Forcible Termination R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2537 of 3092 SH7268 Group, SH7269 Group Section 45 MMC Host Interface 45.7.12 Setting Values of CE_CMD_SET Table 45.4 lists the setting values required to issue commands. Table 45.4 Setting Values of CE_CMD_SET RIDXC[1:0] RCRC7C[1:0] TBIT OPDM 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 01 01 0 0 0 0 0 0 0 0 0 0 00 CMD2 R2 0 0 000010 10 0 0 0 0 0 0 01 10 0 0 0 0 0 0 0 0 0 0 00 CMD3 R1 0 0 000011 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD4 - 0 0 000100 00 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD5 R1b 0 0 000101 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD6 R1b 0 0 000110 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD7 R1 0 0 000111 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 R1b 0 0 000111 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD8 R1 0 0 001000 01 0 0 1 0 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** CMD9 R2 0 0 001001 10 0 0 0 0 0 0 01 10 0 0 0 0 0 0 0 0 0 0 00 CMD10 R2 0 0 001010 10 0 0 0 0 0 0 01 10 0 0 0 0 0 0 0 0 0 0 00 CMD12 R1 0 0 001100 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 00 R1b 0 0 001100 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 CMD13 R1 0 0 001101 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD14 R1 0 0 001110 01 0 0 1 0 0 0 00 00 0 1 0 0 0 0 0 0 1 0 ** CMD15 - 0 0 001111 00 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD16 R1 0 0 010000 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD17 R1 0 0 010001 01 0 0 1 0 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** CMD18 R1 0 0 010010 01 0 0 1 0 1 0 00 00 0 0 0 0 0 0 0 0 0 * ** R1 0 0 010010 01 0 0 1 0 1 1 00 00 0 0 0 0 0 0 0 0 0 * ** CMD19 R1 0 0 010011 01 0 0 1 1 0 0 00 00 0 0 0 1 0 0 0 0 0 0 ** CMD23 R1 0 0 010111 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD24 R1 0 0 011000 01 0 0 1 1 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** CMD25 R1 0 0 011001 01 0 0 1 1 1 0 00 00 0 0 0 0 0 0 0 0 0 * ** R1 0 0 011001 01 0 0 1 1 1 1 00 00 0 0 0 0 0 0 0 0 0 * ** CMD26 R1 0 0 011010 01 0 0 1 1 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** CMD27 R1 0 0 011011 01 0 0 1 1 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** CMD28 R1b 0 0 011100 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD29 R1b 0 0 011101 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 Page 2538 of 3092 Remarks CMD12EN 0 0 DATW[1:0] CMLTE 0 0 - DWEN 0 01 SBIT - WDAT 00 000001 - - 000000 0 CRCSTE RBSY 0 0 - CMD[5:0] 0 R3 CRC16C - - - CMD1 RTYP[1:0] - CMD0 Command Response CE_CMD_SET Predefined Openended Predefined Openended R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 45 MMC Host Interface TBIT OPDM 0 0 00 00 0 0 0 0 0 0 0 0 0 * 0 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** CMD35 R1 0 0 100011 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD36 R1 0 0 100100 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD38 R1b 0 0 100110 01 1 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD39 R4 0 0 100111 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD40 R5 0 0 101000 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 R5 0 0 101000 01 0 0 0 0 0 0 00 00 0 0 0 0 1 1 0 0 0 0 00 CMD42 R1 0 0 101010 01 0 0 1 1 0 0 00 00 0 0 0 0 0 0 0 0 0 0 ** CMD55 R1 0 0 110111 01 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 00 CMD56 R1 0 0 111000 01 0 0 1 0 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** Read R1 0 0 111000 01 0 0 1 1 0 0 00 00 0 0 0 0 0 0 0 0 0 * ** Read Remarks RIDXC[1:0] RCRC7C[1:0] 0 1 DATW[1:0] CMD12EN 1 0 - CMLTE 0 0 SBIT - DWEN 0 01 - WDAT 01 011111 CRCSTE - 011110 0 - RBSY 0 0 CRC16C - CMD[5:0] 0 R1 RTYP[1:0] - R1 CMD31 Response CMD30 Command - CE_CMD_SET ** Send CMD Send RSP Note: This module does not support CMD11 and CMD20. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2539 of 3092 Section 45 MMC Host Interface 45.8 Usage Note 45.8.1 Card Detection SH7268 Group, SH7269 Group The CDRISE and CDFALL bits in CE_DETECT which are used for the card detection function do not have a chattering elimination function. The chattering elimination processing should be implemented by software. Page 2540 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer Section 46 Motor Control PWM Timer This LSI has two channels of on-chip motor control PWM (pulse width modulator) timer with a maximum capability of eight pulse outputs for each channel. 46.1 Features  Maximum of 16 pulse outputs  Two 10-bit PWM channels, each with eight outputs.  10-bit counter (PWCNT) and cycle register (PWCYR).  Duty and output polarity can be set for each output.  Automatic data transfer in every cycle  Each of four duty registers (PWDTR) is provided with buffer registers (PWBFR), with data transferred automatically every cycle.  Duty settings selectable  A duty cycle of 0% to 100% can be selected by means of a duty register setting.  Counting clock selectable  There is a choice of five counting clocks (P0, P0/2, P0/4, P0/8, P0/16).  High-speed access via internal 16-bit bus  Two interrupt sources  An interrupt can be requested independently for each channel by a cycle register compare match.  Automatic transfer of register data  Block transfer and one-word data transfer are available by activating the direct memory access controller.  Module stop mode can be set R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2541 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer Figure 46.1 shows a block diagram of the motor control PWM timer. P0φ, P0φ/2, P0φ/4, P0φ/8, P0φ/16 Interrupt request PWCR PWCNT Compare match 0 12 9 PWDTRA PWBFRC PWDTRC PWBFRE PWBFRG PWPR 0 PWBFRA PWBTCR Bus interface 12 9 Internal data bus PWCYR PWDTRE PWDTRG P/N PWMA P/N PWMB P/N PWMC P/N PWMD P/N PWME P/N PWMF P/N PWMG P/N PWMH Legend: PWCR: PWM control register PWPR: PWM polarity register PWCNT: PWM counter PWCYR: PWM cycle register PWDTRA, PWDTRC, PWDTRE, PWDTRG: PWM duty registers A, C, E, G PWBFRA, PWBFRC, PWBFRE, PWBFRG: PWM buffer registers A, C, E, G PWBTCR: PWM buffer transfer control register Figure 46.1 Block Diagram of Motor Control PWM Timer Page 2542 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 46.2 Section 46 Motor Control PWM Timer Input/Output Pins Table 46.1 shows the pin configuration of this module. Table 46.1 Pin Configuration Channel 1 2 Name Abbrev. I/O Function PWM output pin 1A PWM1A Output Channel 1A PWM output PWM output pin 1B PWM1B Output Channel 1B PWM output PWM output pin 1C PWM1C Output Channel 1C PWM output PWM output pin 1D PWM1D Output Channel 1D PWM output PWM output pin 1E PWM1E Output Channel 1E PWM output PWM output pin 1F PWM1F Output Channel 1F PWM output PWM output pin 1G PWM1G Output Channel 1G PWM output PWM output pin 1H PWM1H Output Channel 1H PWM output PWM output pin 2A PWM2A Output Channel 2A PWM output PWM output pin 2B PWM2B Output Channel 2B PWM output PWM output pin 2C PWM2C Output Channel 2C PWM output PWM output pin 2D PWM2D Output Channel 2D PWM output PWM output pin 2E PWM2E Output Channel 2E PWM output PWM output pin 2F PWM2F Output Channel 2F PWM output PWM output pin 2G PWM2G Output Channel 2G PWM output PWM output pin 2H PWM2H Output Channel 2H PWM output R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2543 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer 46.3 Register Descriptions This module has the following registers for each channel as listed in table 46.2. Table 46.2 Register Description Register Name Abbreviation R/W Initial Value Address Access Size PWM control register_1 PWCR_1 R/W H'C0 H'FFFEF4E0 8, 16 PWM polarity register_1 PWPR_1 R/W H'00 H'FFFEF4E4 8, 16 PWM cycle register_1 PWCYR_1 R/W H'FFFF H'FFFEF4E6 16 PWM buffer register_1A PWBFR_1A R/W H'EC00 H'FFFEF4E8 16 PWM buffer register_1C PWBFR_1C R/W H'EC00 H'FFFEF4EA 16 PWM buffer register_1E PWBFR_1E R/W H'EC00 H'FFFEF4EC 16 PWM buffer register_1G PWBFR_1G R/W H'EC00 H'FFFEF4EE 16 PWM control register_2 PWCR_2 R/W H'C0 H'FFFEF4F0 8, 16 PWM polarity register_2 PWPR_2 R/W H'00 H'FFFEF4F4 8, 16 PWM cycle register_2 PWCYR_2 R/W H'FFFF H'FFFEF4F6 16 PWM buffer register_2A PWBFR_2A R/W H'EC00 H'FFFEF4F8 16 PWM buffer register_2C PWBFR_2C R/W H'EC00 H'FFFEF4FA 16 PWM buffer register_2E PWBFR_2E R/W H'EC00 H'FFFEF4FC 16 PWM buffer register_2G PWBFR_2G R/W H'EC00 H'FFFEF4FE 16 PWM buffer transfer control register PWBTCR R/W H'00 H'FFFEF406 8, 16 Page 2544 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 46.3.1 Section 46 Motor Control PWM Timer PWM Control Register_n (PWCR_n) (n = 1, 2) PWCR_n performs interrupt control, starting/stopping of the counter, and counter clock selection. It also contains a flag that indicates a compare match with the cycle register. Bit 7 6 5 4 3 2 1 0 Bit Name — — IE CMF CST CKS2 CKS1 CKS0 Initial Value 1 1 0 0 0 0 0 0 R/W — — R/W R/(W)* R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1  Reserved These bits are always read as 1 and cannot be modified. 5 IE 0 R/W Interrupt Enable Enables or disables an interrupt request in the event of a compare match with PWCYR_n of the corresponding channel. 0: Interrupt disabled 1: Interrupt enabled 4 CMF 0 R/(W)* Compare Match Flag Indicates the occurrence of a compare match with PWCYR_n of the corresponding channel. [Setting condition] When PWCNT_n = PWCYR_n  1 [Clearing conditions]  When 0 is written to CMF after reading CMF = 1  When the direct memory access controller is activated by a compare match interrupt, and the DTA bit in DMDR of the direct memory access controller is 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2545 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer Bit Bit Name Initial Value R/W Description 3 CST 0 R/W Counter Start Selects starting or stopping of PWCNT_n of the corresponding channel. 0: PWCNT_n is stopped 1: PWCNT_n is started 2 CKS2 0 R/W Clock Select 1 CKS1 0 R/W 0 CKS0 0 R/W These bits select the operating clock for PWCNT_n of the corresponding channel. 000: Counts on P0/1 001: Counts on P0/2 010: Counts on P0/4 011: Counts on P0/8 1XX: Counts on P0/16 [Legend] X: Don't care Note: * Only 0 can be written, to clear the flag. Page 2546 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 46.3.2 Section 46 Motor Control PWM Timer PWM Polarity Register_n (PWPR_n) (n = 1, 2) PWPR_n selects the PWM output polarity. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 OPSnH OPSnG OPSnF OPSnE OPSnD OPSnC OPSnB OPSnA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 7 OPSnH 0 R/W Output Polarity Select Description 6 OPSnG 0 R/W Each of these bits selects the PWM output polarity. 5 OPSnF 0 R/W 0: PWM direct output 4 OPSnE 0 R/W 3 OPSnD 0 R/W 2 OPSnC 0 R/W 1 OPSnB 0 R/W 0 OPSnA 0 R/W 1: PWM inverse output (n = 1, 2) 46.3.3 PWM Counter_n (PWCNT_n) (n = 1, 2) PWCNT_n is a 10-bit up-counter incremented by the input clock. The input clock is selected by clock select bits CKS2 to CKS0 in PWCR_n. PWCNT_n can not be directly accessed by the CPU. PWCNT_n is initialized to H'FC00, when the CST bit in PWCRn is cleared to 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2547 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer 46.3.4 PWM Cycle Register_n (PWCYR_n) (n = 1, 2) PWCYR_n is a 16-bit readable/writable register that sets the PWM conversion cycle. Bit: 15 14 13 12 11 10 9 8 PWC Y15 PWC Y14 PWC Y13 PWC Y12 PWC Y11 PWC Y10 PWC Y9 PWC Y8 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit: 7 6 5 4 3 2 1 0 PWC Y7 PWC Y6 PWC Y5 PWC Y4 PWC Y3 PWC Y2 PWC Y1 PWC Y0 Initial value: 1 R/W: R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W When a PWCYR_n compare match occurs, PWCNT_n is cleared and data is transferred from the buffer register (PWBFR_n) to the duty register (PWDTR_n). PWCYR_n should be written to only while PWCNT_n is stopped. A value of H'FC00 must not be set to PWCYR_n. Compare match PWCNT (lower 10 bits) PWCYR (lower 10 bits) Compare match 0 1 N–2 N–1 0 1 N Figure 46.2 Cycle Register Compare Match Page 2548 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 46.3.5 Section 46 Motor Control PWM Timer PWM Duty Registers_nA, nC, nE, nG (PWDTR_nA, PWDTR_nC, PWDTR_nE, PWDTR_nG) (n = 1, 2) There are four PWDTR_n registers (PWDTR_nA, PWDTR_nC, PWDTR_nE, and PWDTR_nG). The PWDTR_nA is used for outputs PWMnA and PWMnB, PWDTR_nC for outputs PWMnC and PWMnD, PWDTR_nE for outputs PWMnE and PWMnF, and PWDTR_nG for outputs PWMnG and PWMnH. PWDTR_n can not be directly accessed by the CPU. When a PWCYR_n compare match occurs, data is transferred from the buffer register (PWBFR_n) to the duty register (PWDTR_n). PWDTR_n is initialized to H'00 when the CST bit is cleared to 0. Bit 15 14 13 12 11 10 9 8 Bit Name — — — OTS — — DT9 DT8 Initial Value — — — 0 — — 0 0 R/W — — — — — — — — Bit Bit Name 7 6 5 4 3 2 1 0 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial Value 0 0 0 0 0 0 0 0 R/W — — — — — — — — R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2549 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer Bit Bit Name Initial Value R/W Description 15 to 13    Reserved 12 OTS 0  Output Terminal Select Selects the pin used for PWM output. Unselected pins output a low level (or a high level when the corresponding bit in PWPR_n is set to 1). For details, see table 46.3. 11, 10    Reserved 9 DT9 0  Duty 8 DT8 0  7 DT7 0  6 DT6 0  5 DT5 0  4 DT4 0  These bits specify the PWM output duty. A high level (or a low level when the corresponding bit in PWPR_n is set to 1) is output from the time PWCNT_n is cleared by a PWCYR_n compare match until a PWDTR_n compare match occurs. When all of the bits are 0, there is no high-level (or low-level when the corresponding bit in PWPR_n is set to 1) output period. 3 DT3 0  2 DT2 0  1 DT1 0  0 DT0 0  Table 46.3 Output Selection by OTS Bit Bit 12 Register OTS Description PWDTR_1A/ 0 PWMnA output selected PWDTR_2A 1 PWMnB output selected PWDTR_1C/ 0 PWMnC output selected PWDTR_2C 1 PWMnD output selected PWDTR_1E/ 0 PWMnE output selected PWDTR_2E 1 PWMnF output selected PWDTR_1G/ 0 PWMnG output selected PWDTR_2G 1 PWMnH output selected Page 2550 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer Compare match PWCNT_1/2 (lower 10 bits) 0 M–2 1 PWCYR_1/2 (lower 10 bits) N PWDTR_1/2 (lower 10 bits) M M–1 M N–1 0 N–1 0 PWM output on selected pin PWM output on unselected pin Figure 46.3 Duty Register Compare Match (OPS = 0 in PWPR_n) PWCNT_1/2 (lower 10 bits) 0 1 N–2 PWCYR_1/2 (lower 10 bits) N PWDTR_1/2 (lower 10 bits) M PWM output (M = 0) PWM output (0 < M < N) PWM output (N ≤ M) Figure 46.4 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_n) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2551 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer 46.3.6 PWM Buffer Registers_nA, nC, nE, nG (PWBFR_nA, PWBFR_nC, PWBFR_nE, PWBFR_nG) (n = 1, 2) There are four PWBFR_n registers (PWBFR_nA, PWBFR_nC, PWBFR_nE, and PWBFR_nG). When a PWCYR_n compare match occurs, data is transferred from the buffer register (PWBFR_n) to the duty register (PWDTR_n). Bit: 15 14 13 12 11 10 9 8 — — — OTS — — DT9 DT8 Initial Value: 1 1 1 0 1 1 0 0 R/W: R R R R/W R R R/W R/W Bit: 7 6 5 4 3 2 1 0 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial Value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 15 to 13  All 1 R R/W: Description Reserved These bits are always read as 1 and cannot be modified. 12 OTS 0 R/W Output Terminal Select Holds the data to be sent to bit 12 in PWDTR_n. 11, 10  All 1 R Reserved These bits are always read as 1 and cannot be modified. 9 DT9 0 R/W Duty 8 DT8 0 R/W 7 DT7 0 R/W These bits hold the data to be sent to bits 9 to 0 in PWDTR_n. 6 DT6 0 R/W 5 DT5 0 R/W 4 DT4 0 R/W 3 DT3 0 R/W 2 DT2 0 R/W 1 DT1 0 R/W 0 DT0 0 R/W Page 2552 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 46.3.7 Section 46 Motor Control PWM Timer PWM Buffer Transfer Control Register (PWBTCR) PWBTCR enables or disables the data transfer from buffer register to duty register with the compare match of PWM counter and PWM cycle register. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 BTC2G BTC2E BTC2C BTC2A BTC1G BTC1E BTC1C BTC1A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 BTC2G 0 R/W 6 BTC2E 0 R/W 0: Data transfer from PWBFR_n to PWDTR_n is enabled with PWCNT_n and PWCYR_n compare match 5 BTC2C 0 R/W 4 BTC2A 0 R/W 3 BTC1G 0 R/W 2 BTC1E 0 R/W 1 BTC1C 0 R/W 0 BTC1A 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 1: Data transfer from PWBFR_n to PWDTR_n is disabled with PWCNT_n and PWCYR_n compare match Page 2553 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer 46.4 Bus Master Interface 46.4.1 16-Bit Data Registers PWCYR_n and PWBFR_n are 16-bit registers. These registers are linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. They cannot be read or written by 8-bit access; 16-bit access must always be used. Internal data bus H Bus master L Bus interface Module data bus PWCYR Figure 46.5 16-Bit Register Access Operation (Bus Master  PWCYR_n (16 Bits)) 46.4.2 8-Bit Data Registers PWCR_n, PWPR_n, and PWBTCR are 8-bit registers that can be read and written to in 8-bit units. These registers are linked to the bus master by a 16-bit data bus, and can be read or written by 16bit access; in this case, the lower eight bits are read as H'FF. Internal data bus H Bus master L Bus interface Module data bus PWCR Figure 46.6 8-Bit Register Access Operation (Bus Master  PWCR_n (Upper Eight Bits)) Page 2554 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 46.5 Operation 46.5.1 PWM Operation Section 46 Motor Control PWM Timer PWM waveforms are output from pins PWM1A to PWM1H and PWM2A to PWM2H as shown in figure 46.7. (1) Initial Settings Set the PWM output polarity in PWPR_n; select the clock to be input to PWCNT_n with the CKS2 to CKS0 bits in PWCRn; set the PWM conversion cycle in PWCYR_n; and set the first frame of data in PWBFR_nA, PWBFR_nC, PWBFR_nE, and PWBFR_nG. (2) Activation When the CST bit in PWCR_n is set to 1, PWCNT_n starts counting up. On compare match between PWCNT_n and PWCYR_n, data is transferred from the buffer register to the duty register and the CMF bit in PWCR_n is set to 1. At the same time, if the IE bit in PWCR_n has been set to 1, an interrupt can be requested or the direct memory access controller can be activated. (3) Waveform Output The PWM outputs selected by the OTS bits in PWDTR_nA, PWDTR_nC, PWDTR_nE, and PWDTR_nG go high when a compare match occurs between PWCNT_n and PWCYR_n. The PWM outputs not selected by the OTS bit are low. When a compare match occurs between PWCNT_n and PWDTR_nA, PWDTR_nC, PWDTR_nE, or PWDTR_nG, the corresponding PWM output goes low. If the corresponding bit in PWPR_n is set to 1, the output is inverted. PWCYR PWBFRA PWDTRA OTS (PWDTRA) = 0 OTS (PWDTRA) = 1 OTS (PWDTRA) = 0 OTS (PWDTRA) = 1 PWMA PWMB Figure 46.7 PWM Operation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2555 of 3092 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer (4) Next Frame When a compare match occurs between PWCNT_n and PWCYR_n, data is transferred from the buffer register to the duty register. PWCNT_n is reset and starts counting up from H'000. The CMF bit in PWCR_n is set, and if the IE bit in PWCR_n has been set, an interrupt can be requested or the direct memory access controller can be activated. (5) Stopping When the CST bit in PWCR_n is cleared to 0, PWCNT_n is reset and stops. All PWM outputs go low (or high if the corresponding bit in PWPR_n is set to 1). 46.5.2 Buffer Transfer Control Setting a corresponding bit in the PWM buffer transfer control register disables a buffer transfer on compare match. This prevents the output from changing when compare match occurs while the buffer register is being changed. A buffer transfer on compare match is resumed after cleaning the bit. PWCYR PWBFR_1A PWDTR_1A PWBFR_1C PWDTR_1C PWCNT Write PWMBTCR Buffer updated (PWBFR_1C) Buffer updated (PWBFR_1A) Disabled: 1 Enabled: 0 Buffer updated (PWBFR_1A) Disabled Buffer updated (PWBFR_1C) Enabled Figure 46.8 Disabling Buffer Transfer Page 2556 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 46 Motor Control PWM Timer 46.6 Usage Note 46.6.1 Conflict between Buffer Register Write and Compare Match If a PWBFR_n write is performed in the state immediately after a cycle register compare match, the buffer register and duty register are both modified. PWM output changed by the cycle register compare match is not changed by modification of the duty register due to conflict. This may result in unanticipated duty output. Buffer register modification must be completed before automatic transfer by the direct memory access controller, exception handling due to a compare match interrupt, or the occurrence of a cycle register compare match on detection of the rise of CMF (compare match flag) in PWCR_n. T1 Tw Tw T2 P0φ Address Buffer register address Write signal Compare match PWCNT (lower 10 bits) PWBFR PWDTR 0 N M N M PWM output CMF Figure 46.9 Conflict between Buffer Register Write and Compare Match R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2557 of 3092 Section 46 Motor Control PWM Timer Page 2558 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 47 On-Chip RAM Section 47 On-Chip RAM This LSI has an on-chip high-speed RAM, which achieves fast access, an on-chip large-capacity RAM for display area and work area (128 Kbytes of this RAM are shared with the on-chip data retention RAM), and an on-chip data retention RAM, which can retain data in deep standby mode. These memory units can be used to store instructions or data. The operation and write access to the on-chip high-speed RAM and large-capacity RAM (including on-chip data retention RAM) can be enabled or disabled through the RAM enable bits and RAM write enable bits. The on-chip data retention RAM is assigned to page 0 of the on-chip large-capacity RAM. Retention or non-retention of data by the on-chip data retention RAM in deep standby mode is selectable on a per-page basis. 47.1 Features  Page  The on-chip high-speed RAM consists of four pages. The size of one page is 16 Kbytes.  The on-chip large-capacity RAM consists of six pages.  The on-chip data retention RAM consists of four pages. Page 0 has 16-Kbytes, page 1 has 16-Kbytes, page 2 has 32-Kbytes, and page 3 has 64-Kbytes.  Memory map The on-chip RAM is located in the address spaces shown in tables 47.1 to 47.3. Table 47.1 Address Spaces of On-Chip High-Speed RAM Page Address Page 0 H'FFF80000 to H'FFF83FFF Page 1 H'FFF84000 to H'FFF87FFF Page 2 H'FFF88000 to H'FFF8BFFF Page 3 H'FFF8C000 to H'FFF8FFFF R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2559 of 3092 SH7268 Group, SH7269 Group Section 47 On-Chip RAM Table 47.2 Address Spaces of On-Chip Large-Capacity RAM Page Cache-enabled Address Cache-disabled Address Page 0 (256KB) H'1C000000 to H'1C03FFFF H'3C000000 to H'3C03FFFF Page 1 (256KB) H'1C040000 to H'1C07FFFF H'3C040000 to H'3C07FFFF Page 2 (512KB) H'1C080000 to H'1C0FFFFF H'3C080000 to H'3C0FFFFF Page 3 (512KB) H'1C100000 to H'1C17FFFF H'3C100000 to H'3C17FFFF Page 4 (512KB) H'1C180000 to H'1C1FFFFF H'3C180000 to H'3C1FFFFF Page 5 (512KB) H'1C200000 to H'1C27FFFF H'3C200000 to H'3C27FFFF Table 47.3 Address Spaces of On-Chip Data Retention RAM Page Cache-enabled Address Cache-disabled Address Page 0 (16KB) H'1C000000 to H'1C003FFF H'3C000000 to H'3C003FFF Page 1 (16KB) H'1C004000 to H'1C007FFF H'3C004000 to H'3C007FFF Page 2 (32KB) H'1C008000 to H'1C00FFFF H'3C008000 to H'3C00FFFF Page 3 (64KB) H'1C010000 to H'1C01FFFF H'3C010000 to H'3C01FFFF  Ports Each page of the on-chip high-speed RAM has two independent read and write ports and is connected to the internal DMA bus (ID bus), CPU instruction fetch bus (F bus), and CPU memory access bus (M bus). (Note that the F bus is connected only to the read ports.) The F bus and M bus are used for access by the CPU, and the ID bus is used for access by the direct memory access controller. Each page of the on-chip large-capacity RAM has one read and write port and is connected to the internal CPU bus (IC bus), internal DMA bus (ID bus) and internal graphics buses (IV1 to IV4, RGP1 to RGP4). The on-chip RAM for data retention is included in page 0 of the on-chip large-capacity RAM. Accordingly, the on-chip RAM for data retention is shared with the read and write port of page 0 of the on-chip large-capacity RAM. Page 2560 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 47 On-Chip RAM  Priority When the same page of the on-chip high-speed RAM is accessed from different buses simultaneously, the access is processed according to the priority. The priority is ID bus  M bus  F bus. When the same page of the on-chip large-capacity RAM is accessed from different buses simultaneously, the access is processed according to the priority. The priority is (A) > RGP1 bus > RGP2 bus> RGP3 bus > RGP4 bus. (A) operates in round robin mode, and the priority order is switched among the IV1 bus (read), IV1 bus (write), IV2 bus, IV3 bus, IV4 bus, IC bus, and ID bus.  Number of access cycles On-chip high-speed RAM: the number of cycles for access to read or write from buses F and I is one cycle of I. Number of cycles for access from the ID bus depend on the ratio of the CPU clock (I) to the internal bus clock (B). Table 47.4 indicates number of cycles for access from the ID bus. Table 47.4 Number of Cycles for Access to On-Chip High-Speed RAM from the ID Bus Read/Write Ratio of I and B Number of Access (B) Cycles Read 1:1 3 2:1 2 3:1 2 4:1 2 6:1 1 8:1 1 1:1 2 2:1 2 3:1 2 4:1 2 6:1 1 8:1 1 Write Note: For the settable ratios of I to B, see section 5, Clock Pulse Generator. On-chip large-capacity RAM: the number of cycles for access to read or write from any bus is one cycle of B. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2561 of 3092 SH7268 Group, SH7269 Group Section 47 On-Chip RAM 47.2 Usage Notes 47.2.1 Page Conflict When the same page of the on-chip high-speed RAM or the on-chip large-capacity RAM is accessed from different buses simultaneously, a conflict on the page occurs. Although each access is completed correctly, this kind of conflict degrades the memory access speed. Therefore, it is advisable to provide software measures to prevent such conflicts as far as possible. For example, no conflict will arise if different pages are accessed by each bus. 47.2.2 RAME and RAMWE Bits Before disabling memory operation or write access to the on-chip high-speed RAM through the RAME or RAMWE bit, be sure to read from any address and then write to the same address in each page; otherwise, the last written data in each page may not be actually written to the RAM. // For page 0 MOV.L #H'FFF80000,R0 MOV.L @R0,R1 MOV.L R1,@R0 // For page 1 MOV.L #H'FFF84000,R0 MOV.L @R0,R1 MOV.L R1,@R0 // For page 2 MOV.L #H'FFF88000,R0 MOV.L @R0,R1 MOV.L R1,@R0 // For page 3 MOV.L #H'FFF8C000,R0 MOV.L @R0,R1 MOV.L R1,@R0 Figure 47.1 Examples of Read/Write Page 2562 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 47.2.3 Section 47 On-Chip RAM Data Retention Data in the on-chip high-speed RAM and the large-capacity RAM (including on-chip data retention RAM) are retained in the states other than power-on reset and deep standby mode. In power-on reset and deep standby mode, these RAMs operate as described below. (1) Power-on Reset (a) On-Chip High-Speed RAM Data are retained on a power-on reset by disabling the setting of either the RAME or RAMWE bit. Data are not retained when the setting of the RAME and RAMWE bits are both enabled. (b) On-Chip Large-Capacity RAM (Excluding On-Chip Data Retention RAM) Data are retained on a power-on reset by disabling the setting of either the VRAME or VRAMWE bit. Data are not retained when the setting of the VRAME and VRAMWE bits are both enabled. (c) On-Chip Data Retention RAM Data are retained on a power-on reset by disabling the setting of any of the VRAME, VRAMWE, or RRAMWE, excluding the case that deep standby mode is canceled by power-on reset. Data are not retained when the setting of the VRAME, VRAMWE and RRAMWE bits are all enabled. (2) Deep Standby Mode (a) On-Chip High-Speed RAM and On-Chip Large-Capacity RAM (Excluding On-Chip Data Retention RAM) Data are not retained. (b) On-Chip Data Retention RAM Data are retained in deep standby mode by enabling the setting of the RRAMKP bit, excluding the case that deep standby mode is canceled by power-on reset. In the case that deep standby mode is canceled by interrupt or pins for cancelling, power-on reset exception handling is executed, but the data are retained. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2563 of 3092 Section 47 On-Chip RAM Page 2564 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Section 48 General Purpose I/O Ports This LSI has 9 general purpose I/O ports: A, B, C, D, E, F, G, H, and J. All port pins are multiplexed with other peripheral module pin functions. Each port is provided with registers for selecting the pin functions and those I/O directions of multiplex pins, data registers for storing the pin data and port registers for reading the states of the pins. 48.1 Features  By setting the control registers, multiplexed pin functions can be selectable.  When the general I/O function or TIOC I/O function of multi-function timer pulse unit 2 is specified, the I/O direction can be selected by I/O register settings. Table 48.1 Number of General Purpose I/O Pins Port SH7268 SH7269 A 2 I/O pins B 22 I/O pins C 9 I/O pins D 16 I/O pins E 4 input pins with open-drain outputs 8 input pins with open-drain outputs F 23 I/O pins G 28 I/O pins H 6 input pins 8 input pins J  32 I/O pins 111 pins (101 I/O pins, 4 input pins with open-drain outputs, and 6 input pins) 149 pins (133 I/O pins, 8 input pins with open-drain outputs, and 8 input pins) Total R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2565 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Tables 48.2 to 48.10 show the multiplex pins of this LSI. The registers and pin functions in the shaded cells are available only in the SH7269 Group. Table 48.2 Multiplexed Pins (Port A) RES Pin input H L Port Function 1 Function 2 A PA1 MD_BOOT1 PA0 MD_BOOT0 Note: The function 2 of port A is enabled in the state of RES = L and always general I/O functions in the state of RES = H. Table 48.3 Multiplexed Pins (Port B) Setting Mode Bits (PBnMD[2:0]) Setting Register PBCR5 PBCR4 PBCR3 PBCR2 000 001 010 011 100 110 Function 1 Function 2 Function 3 Function 4 Function 5 Function 7 PB22 A22 CTx2 IETxD CS4  PB21 A21 CRx2 IERxD   PB20 A20 QMI_0/QIO1_0 MISO0  SPBMI_0/SPBIO1_0 PB19 A19 QMO_0/QIO0_0 MOSI0  SPBMO_0/SPBIO0_0 PB18 A18 QSSL_0 SSL00  SPBSSL PB17 A17 QSPCLK_0 RSPCK0  SPBCLK PB16 A16 QIO3_0   SPBIO3_0 PB15 A15 QIO2_0   SPBIO2_0 PB14 A14 QIO3_1   SPBIO3_1 PB13 A13 QIO2_1   SPBIO2_1 PB12 A12 TIOC3D    PB11 A11 TIOC3C    PB10 A10 TIOC3B    PB9 A9 TIOC3A    PB8 A8 TIOC2B    Page 2566 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Setting Mode Bits (PBnMD[2:0]) Setting Register PBCR1 PBCR0 000 001 010 011 100 110 Function 1 Function 2 Function 3 Function 4 Function 5 Function 7 PB7 A7 TIOC2A    PB6 A6 TIOC1B    PB5 A5 TIOC1A    PB4 A4 TIOC0D    PB3 A3 TIOC0C    PB2 A2 TIOC0B    PB1 A1 TIOC0A    R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2567 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.4 Multiplexed Pins (Port C) Setting Mode Bits (PCnMD[2:0]) 000 001 010 011 100 101 Setting Register Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 PCCR2 PC8 CS3 TxD7 CTx1 CTx0&CTx1  PCCR1 PC7 CKE RxD7 CRx1 CRx0/CRx1 PC6 CAS SCK7 CTx0 CTx0&CTx1  &CTx2 PC5 RAS  CRx0 CRx0/CRx1/ IRQ0 CRx2 PC4 WE1/ DQMLU/ WE TxD6    PC3 WE0/ DQMLL RxD6    PC2 RD/WR SCK6    PC1 RD     PC0 CS0 MD_BOOT2    PCCR0 IRQ1 Note: The function 3 of PC0 is enabled in the state of RES = L and the function 1 or 2 in the state of RES = H. Page 2568 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.5 Multiplexed Pins (Port D) Setting Mode Bits (PDnMD[1:0]) Setting Register PDCR3 PDCR2 PDCR1 PDCR0 00 01 10 Function 1 Function 2 Function 3 PD15 D15/NAF7 PWM2H PD14 D14/NAF6 PWM2G PD13 D13/NAF5 PWM2F PD12 D12/NAF4 PWM2E PD11 D11/NAF3 PWM2D PD10 D10/NAF2 PWM2C PD9 D9/NAF1 PWM2B PD8 D8/NAF0 PWM2A PD7 D7/FWE PWM1H PD6 D6/FALE PWM1G PD5 D5/FCLE PWM1F PD4 D4/FRE PWM1E PD3 D3 PWM1D PD2 D2 PWM1C PD1 D1 PWM1B PD0 D0 PWM1A Note: The function 2 of bus state controller and /or the function of NAND flash memory controller change automatically. (See section 10, Bus State Controller.). R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2569 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.6 Multiplexed Pins (Port E) Setting Mode Bits (PEnMD[2:0]) Setting Register PECR1 PECR0 000 001 010 011 100 Function 1 Function 2 Function 3 Function 4 Function 5 PE7 SDA3 RxD7   PE6 SCL3 RxD6   PE5 SDA2 RxD5 DV_HSYNC  PE4 SCL2 RxD4 DV_VSYNC  PE3 SDA1 TCLKD ADTRG DV_HSYNC PE2 SCL1 TCLKC IOIS16 DV_VSYNC PE1 SDA0 TCLKB AUDIO_CLK DV_CLK PE0 SCL0 TCLKA LCD_EXTCLK  Table 48.7 Multiplexed Pins (Port F) Setting Mode Bits (PFnMD[2:0]) Setting Register PFCR6 PFCR5 PFCR4 PFCR3 000 001 010 011 100 101 110 Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 PF23 SD_D2_0   TxD3 MMC_D2  PF22 SD_D3_0   RxD3 MMC_D3  PF21 SD_CMD_0   SCK3 MMC_CMD  PF20 SD_CLK_0 SSIDATA3   MMC_CLK  PF19 SD_D0_0 SSIWS3  IRQ7 MMC_D0  PF18 SD_D1_0 SSISCK3  IRQ6 MMC_D1  PF17 SD_WP_0  FRB IRQ5   PF16 SD_CD_0  FCE IRQ4 MMC_CD  PF15 A0 SSIDATA2 WDTOVF TxD2 UBCTRG  PF14 A25 SSIWS2  RxD2   PF13 A24 SSISCK2  SCK2   PF12  SSIDATA1 DV_DATA3 TxD1 MMC_D7  Page 2570 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Setting Mode Bits (PFnMD[2:0]) Setting Register PFCR2 PFCR1 PFCR0 000 001 010 011 100 101 110 Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 PF11  SSIWS1 DV_DATA2 RxD1 MMC_D6  PF10 CS1 SSISCK1 DV_DATA1 SCK1 MMC_D5  PF9 BS  DV_DATA0 SCK0 MMC_D4 RTS1 PF8 A23   TxD0   PF7  SSIRxD0  RxD0 SGOUT_3 CTS1 PF6 CE2A SSITxD0   SGOUT_2  PF5  SSIWS0   SGOUT_1  PF4 CS5/CE1A SSISCK0   SGOUT_0  PF3 CS2 QMI_1/ QIO1_1 MISO1 TIOC4D AUDIO_ XOUT SPBMI_1/ SPBIO1_1 PF2 WAIT QMO_1/ QIO0_1 MOSI1 TIOC4C TEND0 SPBMO_1/ SPBIO0_1 PF1 BACK QSSL_1 SSL10 TIOC4B DACK0  PF0 BREQ QSPCLK_1 RSPCK1 TIOC4A DREQ0  Table 48.8 Multiplexed Pins (Port G) Setting Mode Bits (PGnMD[2:0]) Setting Register PGCR6 PGCR5 000 001 010 011 100 Function 1 Function 2 Function 3 Function 4 Function 5 PG27  LCD_TCON2 LCD_EXTCLK  PG26  LCD_TCON1   PG25  LCD_TCON0   PG24  LCD_CLK   PG23  LCD_DATA23 LCD_TCON6 TxD5 PG22  LCD_DATA22 LCD_TCON5 RxD5 PG21 DV_DATA7 LCD_DATA21 LCD_TCON4 TxD4 PG20 DV_DATA6 LCD_DATA20 LCD_TCON3 RxD4 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2571 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Setting Mode Bits (PGnMD[2:0]) Setting Register PGCR4 PGCR3 PGCR2 PGCR1 PGCR0 000 001 010 011 100 Function 1 Function 2 Function 3 Function 4 Function 5 PG19 DV_DATA5 LCD_DATA19 SPDIF_OUT SCK5 PG18 DV_DATA4 LCD_DATA18 SPDIF_IN SCK4 PG17 WE3/ICIOWR/ AH/DQMUU LCD_DATA17   PG16 WE2/ICIORD/ DQMUL LCD_DATA16   PG15 D31 LCD_DATA15 PINT7  PG14 D30 LCD_DATA14 PINT6  PG13 D29 LCD_DATA13 PINT5  PG12 D28 LCD_DATA12 PINT4  PG11 D27 LCD_DATA11 PINT3 TIOC3D PG10 D26 LCD_DATA10 PINT2 TIOC3C PG9 D25 LCD_DATA9 PINT1 TIOC3B PG8 D24 LCD_DATA8 PINT0 TIOC3A PG7 D23 LCD_DATA7 IRQ7 TIOC2B PG6 D22 LCD_DATA6 IRQ6 TIOC2A PG5 D21 LCD_DATA5 IRQ5 TIOC1B PG4 D20 LCD_DATA4 IRQ4 TIOC1A PG3 D19 LCD_DATA3 IRQ3 TIOC0D PG2 D18 LCD_DATA2 IRQ2 TIOC0C PG1 D17 LCD_DATA1 IRQ1 TIOC0B PG0 D16 LCD_DATA0 IRQ0 TIOC0A Page 2572 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.9 Multiplexed Pins (Port H) Setting Mode Bits (PHnMD[1:0]) 00 01 10 11 Setting Register Function 1 Function 2 Function 3 Function 4 PHCR1 PH7 AN7 PINT7  PH6 AN6 PINT6  PH5 AN5 PINT5 LCD_EXTCLK PH4 AN4 PINT4  PH3 AN3 PINT3  PH2 AN2 PINT2  PH1 AN1 PINT1  PH0 AN0 PINT0  PHCR0 Table 48.10 Multiplexed Pins (Port J: Available Only in the SH7269 Group) Setting Mode Bits (PJnMD[2:0]) Setting Register PJCR7 PJCR6 PJCR5 000 001 010 011 100 101 110 Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 PJ31 DV_CLK      PJ30  SSIDATA5  TIOC2B IETxD  PJ29  SSIWS5  TIOC2A IERxD  PJ28  SSISCK5  TIOC1B RTS7  PJ27 SGOUT_3   TIOC1A CTS7  PJ26 SGOUT_2 SSIDATA4 LCD_TCON5  TxD7  PJ25 SGOUT_1 SSIWS4 LCD_TCON4 SPDIF_OUT RxD7  PJ24 SGOUT_0 SSISCK4 LCD_TCON3 SPDIF_IN SCK7  PJ23 DV_DATA23 LCD_DATA23 LCD_TCON6 IRQ3 CTx1 CTx0&CTx1 PJ22 DV_DATA22 LCD_DATA22 LCD_TCON5 IRQ2 CRx1 CRx0/CRx1 PJ21 DV_DATA21 LCD_DATA21 LCD_TCON4 IRQ1 CTx2 CTx0&CTx1& CTx2 PJ20 DV_DATA20 LCD_DATA20 LCD_TCON3 IRQ0 CRx2 CRx0/CRx1/ CRx2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2573 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Setting Mode Bits (PJnMD[2:0]) Setting Register PJCR4 PJCR3 PJCR2 PJCR1 PJCR0 000 001 010 011 100 101 110 Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 PJ19 DV_DATA19 LCD_DATA19 MISO0 TIOC0D SIOFRxD AUDIO_ XOUT PJ18 DV_DATA18 LCD_DATA18 MOSI0 TIOC0C SIOFTxD  PJ17 DV_DATA17 LCD_DATA17 SSL00 TIOC0B SIOFSYNC  PJ16 DV_DATA16 LCD_DATA16 RSPCK0 TIOC0A SIOFSCK  PJ15 DV_DATA15 LCD_DATA15 PINT7 PWM2H TxD7  PJ14 DV_DATA14 LCD_DATA14 PINT6 PWM2G TxD6  PJ13 DV_DATA13 LCD_DATA13 PINT5 PWM2F TxD5  PJ12 DV_DATA12 LCD_DATA12 PINT4 PWM2E SCK7  PJ11 DV_DATA11 LCD_DATA11 PINT3 PWM2D SCK6  PJ10 DV_DATA10 LCD_DATA10 PINT2 PWM2C SCK5  PJ9 DV_DATA9 LCD_DATA9 PINT1 PWM2B RTS5  PJ8 DV_DATA8 LCD_DATA8 PINT0 PWM2A CTS5  PJ7 DV_DATA7 LCD_DATA7 SD_D2_1 PWM1H   PJ6 DV_DATA6 LCD_DATA6 SD_D3_1 PWM1G   PJ5 DV_DATA5 LCD_DATA5 SD_CMD_1 PWM1F   PJ4 DV_DATA4 LCD_DATA4 SD_CLK_1 PWM1E   PJ3 DV_DATA3 LCD_DATA3 SD_D0_1 PWM1D   PJ2 DV_DATA2 LCD_DATA2 SD_D1_1 PWM1C   PJ1 DV_DATA1 LCD_DATA1 SD_WP_1 PWM1B   PJ0 DV_DATA0 LCD_DATA0 SD_CD_1 PWM1A   Page 2574 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 48.2 Section 48 General Purpose I/O Ports Register Descriptions Table 48.11 lists the register configuration. Table 48.11 Register Configuration Port Register Name Abbreviation R/W Intial Value Address A Port A I/O register 0 PAIOR0 R/W H'0000 H'FFFE3812 8, 16*2 Port A data register 0 PADR0 R/W H'0000 H'FFFE3816 8, 16*2 Port A port register 0 PAPR0 R H'xxxx B C Access Size H'FFFE381A 8, 16 1 Port B control register 5 PBCR5 R/W H'0000/H'0001* H'FFFE3824 8, 16, 32 Port B control register 4 PBCR4 R/W H'0000/H'1111*1 H'FFFE3826 8, 16 Port B control register 3 PBCR3 R/W H'0000/H'1111*1 H'FFFE3828 8, 16, 32 Port B control register 2 PBCR2 R/W H'0000/H'1111*1 H'FFFE382A 8, 16 Port B control register 1 PBCR1 R/W H'0000/H'1111*1 H'FFFE382C 8, 16, 32 Port B control register 0 PBCR0 R/W H'0000/H'1110/ H'1100*1 H'FFFE382E 8, 16 Port B I/O register 1 PBIOR1 R/W H'0000 H'FFFE3830 8, 16, 32 Port B I/O register 0 PBIOR0 R/W H'0000 H'FFFE3832 8, 16 Port B data register 1 PBDR1 R/W H'0000 H'FFFE3834 8, 16, 32 Port B data register 0 PBDR0 R/W H'0000 H'FFFE3836 8, 16 Port B port register 1 PBPR1 R H'xxxx H'FFFE3838 8, 16, 32 Port B port register 0 PBPR0 R H'xxxx H'FFFE383A 8, 16 Port C control register 2 PCCR2 R/W H'0000 H'FFFE384A 8, 16 Port C control register 1 PCCR1 R/W H'0000 H'FFFE384C 8, 16, 32 1 Port C control register 0 PCCR0 R/W H'0000/H'0011* H'FFFE384E 8, 16 Port C I/O register 0 PCIOR0 R/W H'0000 H'FFFE3852 8, 16 Port C data register 0 PCDR0 R/W H'0000 H'FFFE3856 8, 16 Port C port register 0 PCPR0 R H'xxxx H'FFFE385A 8, 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2575 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Port D Register Name Abbreviation R/W Port D control register 3 PDCR3 Port D control register 2 PDCR2 Port D control register 1 PDCR1 E F G R/W R/W R/W Intial Value Address Access Size 1 H'FFFE3868 8, 16, 32 H'0000/H'1111* 1 H'FFFE386A 8, 16 H'0000/H'1111* 1 H'FFFE386C 8, 16, 32 1 H'FFFE386E 8, 16 H'0000/H'1111* Port D control register 0 PDCR0 R/W H'0000/H'1111* Port D I/O register 0 PDIOR0 R/W H'0000 H'FFFE3872 8, 16 Port D data register 0 PDDR0 R/W H'0000 H'FFFE3876 8, 16 Port D port register 0 PDPR0 R H'xxxx H'FFFE387A 8, 16 Port E control register 1 PECR1 R/W H'0000 H'FFFE388C 8, 16, 32 Port E control register 0 PECR0 R/W H'0000 H'FFFE388E 8, 16 Port E I/O register 0 PEIOR0 R/W H'0000 H'FFFE3892 8, 16 Port E data register 0 PEDR0 R/W H'0000 H'FFFE3896 8, 16 Port E port register 0 PEPR0 R H'xxxx H'FFFE389A 8, 16 Port F control register 6 PFCR6 R/W H'0000 H'FFFE38A2 8, 16 Port F control register 5 PFCR5 R/W H'0000 H'FFFE38A4 8, 16, 32 Port F control register 4 PFCR4 R/W H'0000 H'FFFE38A6 8*3, 16 Port F control register 3 PFCR3 R/W H'0000 H'FFFE38A8 8, 16, 32 Port F control register 2 PFCR2 R/W H'0000 H'FFFE38AA 8, 16 Port F control register 1 PFCR1 R/W H'0000 H'FFFE38AC 8, 16, 32 Port F control register 0 PFCR0 R/W H'0000 H'FFFE38AE 8, 16 Port F I/O register 1 PFIOR1 R/W H'0000 H'FFFE38B0 8, 16, 32 Port F I/O register 0 PFIOR0 R/W H'0000 H'FFFE38B2 8, 16 Port F data register 1 PFDR1 R/W H'0000 H'FFFE38B4 8, 16, 32 Port F data register 0 PFDR0 R/W H'0000 H'FFFE38B6 8, 16 Port F port register 1 PFPR1 R H'xxxx H'FFFE38B8 8, 16, 32 Port F port register 0 PFPR0 R H'xxxx H'FFFE38BA 8, 16 Port G control register 6 PGCR6 R/W H'0000 H'FFFE38C2 8, 16 Port G control register 5 PGCR5 R/W H'0000 H'FFFE38C4 8, 16, 32 Port G control register 4 PGCR4 R/W H'0000 Port G control register 3 PGCR3 Port G control register 2 PGCR2 R/W R/W H'FFFE38C6 8, 16 1 H'FFFE38C8 8, 16, 32 1 H'FFFE38CA 8, 16 1 H'FFFE38CC 8, 16, 32 H'0000/H'1111* H'0000/H'1111* Port G control register 1 PGCR1 R/W H'0000/H'1111* Port G control register 0 PGCR0 R/W H'0000/H'1111*1 H'FFFE38CE 8, 16 Page 2576 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Port Register Name Abbreviation R/W Intial Value Address G Port G I/O register 1 PGIOR1 R/W H'0000 H'FFFE38D0 8, 16, 32 Port G I/O register 0 PGIOR0 R/W H'0000 H'FFFE38D2 8, 16 Port G data register 1 PGDR1 R/W H'0000 H'FFFE38D4 8, 16, 32 Port G data register 0 PGDR0 R/W H'0000 H'FFFE38D6 8, 16 Port G port register 1 PGPR1 R H'xxxx H'FFFE38D8 8, 16, 32 Port G port register 0 PGPR0 R H'xxxx H'FFFE38DA 8, 16 H J  Access Size Port H control register 1 PHCR1 R/W H'0000 H'FFFE38EC 8, 16, 32 Port H control register 0 PHCR0 R/W H'0000 H'FFFE38EE 8, 16 Port H port register 0 PHPR0 R H'xxxx H'FFFE38FA 8, 16 Port J control register 7 PJCR7 R/W H'0000 H'FFFE3900 8, 16, 32 Port J control register 6 PJCR6 R/W H'0000 H'FFFE3902 8, 16 Port J control register 5 PJCR5 R/W H'0000 H'FFFE3904 8, 16, 32 Port J control register 4 PJCR4 R/W H'0000 H'FFFE3906 8, 16 Port J control register 3 PJCR3 R/W H'0000 H'FFFE3908 8, 16, 32 Port J control register 2 PJCR2 R/W H'0000 H'FFFE390A 8, 16 Port J control register 1 PJCR1 R/W H'0000 H'FFFE390C 8, 16, 32 Port J control register 0 PJCR0 R/W H'0000 H'FFFE390E 8, 16 Port J I/O register 1 PJIOR1 R/W H'0000 H'FFFE3910 8, 16, 32 Port J I/O register 0 PJIOR0 R/W H'0000 H'FFFE3912 8, 16 Port J data register 1 PJDR1 R/W H'0000 H'FFFE3914 8, 16, 32 Port J data register 0 PJDR0 R/W H'0000 H'FFFE3916 8, 16 Port J port register 1 PJPR1 R H'xxxx H'FFFE3918 8, 16, 32 Port J port register 0 PJPR0 R H'xxxx H'FFFE391A 8, 16 Serial sound interface noise canceler control register SNCR R/W H'0000 H'FFFE393E 8, 16 Notes: 1. The initial value depends on the boot mode of the LSI. 2. In 16-bit access, the register can be read but cannot be written to. 3. In 8-bit access, the register can be read but cannot be written to. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2577 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.1 Port A I/O Register 0 (PAIOR0) PAIOR0 is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. The PA1IOR and PA0IOR bits correspond to the PA1 and PA0 pins, respectively. If a bit in PAIOR0 is set to 1, the corresponding pin on port A functions as output. If it is cleared to 0, the corresponding pin function as input. Bits 15 to 9, and 7 to 1 in PAIOR0 are reserved. These bits are always read as 0. The write value should always be 0. Bit: Initial value: R/W: 48.2.2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PA1 IOR - - - - - - - PA0 IOR 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Port A Data Register 0 (PADR0) PADR0 is a 16-bit readable/writable register that stores port A data. The PA1DR and PA0DR bits correspond to the PA1 and PA0 pins, respectively. When a pin function is general output, if a value is written to PADR0, that value is output from the pin, and if PADR0 is read, the register value is returned regardless of the pin state. When a pin function is general input, if PADR0 is read, the pin state, not the register value, is returned directly. If a value is written to PADR0, although that value is written into PADR0, it does not affect the pin state. Table 48.12 summarizes PADR0 read/write operation. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PA1 DR - - - - - - - PA0 DR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PA1DR 0 R/W See table 48.12. 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PA0DR Page 2578 of 3092 0 R/W See table 48.12. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.12 Port A Data Register 0 (PADR0) Read/Write Operation  Bits 8 and 0 of PADR0 PAIOR0 Pin Function Read Operation Write Operation 0 General input Pin state Can write to PADR0, but does not affect the pin state 1 General output PADR0 value Value written is output from the pin 48.2.3 Port A Port Register 0 (PAPR0) PAPR0 is a 16-bit read-only register, in which the PA1PR and PA0PR bits correspond to the PA1 and PA0 pins, respectively. PAPR0 always returns the states of the pins. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - PA1 PR PA0 PR 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PA1 R PA0 R Bit Bit Name Initial Value R/W Description 15 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 PA1PR Pin state R 0 PA0PR Pin state R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 The pin state is returned. These bits cannot be modified. Page 2579 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5) PBCR0 to PBCR5 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port B. (1) Port B Control Register 5 (PBCR5) Bit: 15 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 11  10 9 8 7 6 - - PB21MD[1:0] - 0 R 0 R 0 R/W 0 R PB22MD[2:0] 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 Reserved R 5 4 3 0 R/W 2 1 0 PB20MD[2:0] 0 R/W 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 10 to 8 PB22MD[2:0] 000 R/W PB22 Mode Select the function of the PB22. 7, 6  All 0 R 000: PB22 100: CS4 001: A22 101: Setting prohibited 010: CTx2 110: Setting prohibited 011: IETxD 111: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PB21MD[1:0] 00 R/W PB21 Mode Select the function of the PB21. 3  0 R 00: PB21 10: CRx2 01: A21 11: IERxD Reserved This bit is always read as 0. The write value should always be 0. Page 2580 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W 2 to 0 PB20MD[2:0] 000/001 R/W Description PB20 Mode Select the function of the PB20. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB20 (initial value) 001: A20 (initial value) 001: A20 010: Setting prohibited 010: QMISO0/QIO10 011: Setting prohibited 011: MISO0 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBMI_0/SPBIO1_0 111: Setting prohibited 111: Setting prohibited Page 2581 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (2) Port B Control Register 4 (PBCR4) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PB19MD[2:0] 0 R/W 0 R/W 0/1 R/W 11 - 0 R 10 9 8 PB18MD[2:0] 0 R/W 0 R/W 0/1 R/W 7 6 - 0 R Bit Bit Name Initial Value R/W Description 15  0 R 5 4 0 R/W 0 R/W 3 2 - PB17MD[2:0] 0/1 R/W 0 R 1 0 PB16MD[2:0] 0 R/W 0 R/W 0/1 R/W Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PB19MD[2:0] 000/001 R/W PB19 Mode Select the function of the PB19. 11  0 R Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB19 (initial value) 001: A19 (initial value) 001: A19 010: Setting prohibited 010: QMO_0/QIO0_0 011: Setting prohibited 011: MOSI0 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBMO_0/SPBIO0_0 111: Setting prohibited 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PB18MD[2:0] 000/001 R/W PB18 Mode Select the function of the PB18. Page 2582 of 3092 Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB18 (initial value) 001: A18 (initial value) 001: A18 010: Setting prohibited 010: QSSL_0 011: Setting prohibited 011: SSL00 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBSSL 111: Setting prohibited 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PB17MD[2:0] 000/001 R/W PB17 Mode Select the function of the PB17. 3  0 R Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB17 (initial value) 001: A17 (initial value) 001: A17 010: Setting prohibited 010: QSPCLK_0 011: Setting prohibited 011: RSPCK0 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBCLK 111: Setting prohibited 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PB16MD[2:0] 000/001 R/W PB16 Mode Select the function of the PB16. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Boot mode 1, 0 Boot mode 2 to 5 000: Setting prohibited 000: PB16 (initial value) 001: A16 (initial value) 001: A16 010: Setting prohibited 010: QIO3_0 011: Setting prohibited 011: Setting prohibited 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBIO3_0 111: Setting prohibited 111: Setting prohibited Page 2583 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (3) Port B Control Register 3 (PBCR3) Bit: 15 - Initial value: R/W: 0 R 14 13 12 PB15MD[2:0] 0 R/W 0 R/W 0/1 R/W 11 10 9 0 R 8 PB14MD[2:0] 0 R/W 0 R/W 0/1 R/W 7 6 0 R 5 4 PB13MD[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 0/1 R/W 3 2 - - PB12MD[1:0] 1 0 0 R 0 R 0 R/W 0/1 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PB15MD[2:0] 000/001 R/W PB15 Mode Select the function of the PB15. Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB15 (initial value) 001: A15 (initial value) 001: A15 010: Setting prohibited 010: QIO2_0 011: Setting prohibited 011: Setting prohibited 11  0 R 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBIO2_0 111: Setting prohibited 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PB14MD[2:0] 000/001 R/W PB14 Mode Select the function of the PB14. Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB14 (initial value) 001: A14 (initial value) 001: A14 010: Setting prohibited 010: QIO3_1 011: Setting prohibited. 011: Setting prohibited Page 2584 of 3092 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBIO3_1 111: Setting prohibited 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PB13MD[2:0] 000/001 R/W PB13 Mode Select the function of the PB13. Boot modes 0, 1 Boot modes 2 to 5 000: Setting prohibited 000: PB13 (initial value) 001: A13 (initial value) 001: A13 010: Setting prohibited 010: QIO2_1 011: Setting prohibited 011: Setting prohibited 3, 2  All 0 R 100: Setting prohibited 100: Setting prohibited 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: SPBIO2_1 111: Setting prohibited 111: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PB12MD[1:0] 00/01 R/W PB12 Mode Select the function of the PB12. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB12 (initial value) 01: A12 (initial value) 01: A12 10: Setting prohibited 10: TIOC3D 11: Setting prohibited 11: Setting prohibited Page 2585 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (4) Port B Control Register 2 (PBCR2) Bit: Initial value: R/W: 15 14 11 10 7 6 - - PB11MD[1:0] 13 12 - - PB10MD[1:0] - - 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0/1 R/W 9 8 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 Reserved R 5 4 PB9MD[1:0] 0 R/W 0/1 R/W 3 2 - - 0 R 0 R 1 0 PB8MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PB11MD[1:0] 00/01 R/W PB11 Mode Select the function of the PB11. 11, 10  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB11 (initial value) 01: A11 (initial value) 01: A11 10: Setting prohibited 10: TIOC3C 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PB10MD[1:0] 00/01 R/W PB10 Mode Select the function of the PB10. 7, 6  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB10 (initial value) 01: A10 (initial value) 01: A10 10: Setting prohibited 10: TIOC3B 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Page 2586 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 5, 4 PB9MD[1:0] 00/01 PB9 Mode R/W Select the function of the PB9. 3, 2  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB9 (initial value) 01: A9 (initial value) 01: A9 10: Setting prohibited 10: TIOC3A 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PB8MD[1:0] 00/01 R/W PB8 Mode Select the function of the PB8. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB8 (initial value) 01: A8 (initial value) 01: A8 10: Setting prohibited 10: TIOC2B 11: Setting prohibited 11: Setting prohibited Page 2587 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (5) Port B Control Register 1 (PBCR1) Bit: Initial value: R/W: 15 14 - - 0 R 0 R 13 12 PB7MD[1:0] 0 R/W 0/1 R/W 11 10 7 6 3 2 - - PB6MD[1:0] 9 8 - - PB5MD[1:0] - - 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 0/1 R/W 1 0 PB4MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PB7MD[1:0] 00/01 R/W PB7 Mode Select the function of the PB7. 11, 10  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB7 (initial mode) 01: A7 (initial value) 01: A7 10: Setting prohibited 10: TIOC2A 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PB6MD[1:0] 00/01 R/W PB6 Mode Select the function of the PB6. 7, 6  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB6 (initial value) 01: A6 (initial value) 01: A6 10: Setting prohibited 10: TIOC1B 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Page 2588 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 5, 4 PB5MD[1:0] 00/01 R/W PB5 Mode Select the function of the PB5. 3, 2  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB5 (initial value) 01: A5 (initial value) 01: A5 10: Setting prohibited 10: TIOC1A 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PB4MD[1:0] 00/01 R/W PB4 Mode Select the function of the PB4. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB4 (initial value) 01: A4 (initial value) 01: A4 10: Setting prohibited 10: TIOC0D 11: Setting prohibited 11: Setting prohibited Page 2589 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (6) Port B Control Register 0 (PBCR0) Bit: Initial value: R/W: 15 14 - - 0 R 0 R 13 12 PB3MD[1:0] 0 R/W 0/1 R/W 11 10 - - 0 R 0 R 9 8 PB2MD[1:0] 0 R/W 0/1 R/W 7 6 - - 0 R 0 R Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 PB1MD[1:0] 0 R/W 0/1 R/W 3 2 1 - - - 0 - 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 13, 12 PB3MD[1:0] 00/01 R/W PB3 Mode Select the function of the PB3. 11, 10  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB3 (initial value) 01: A3 (initial value) 01: A3 10: Setting prohibited 10: TIOC0C 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PB2MD[1:0] 00/01 R/W PB2 Mode Select the function of the PB2. 7, 6  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB2 (initial value) 01: A2 (initial value) 01: A2 10: Setting prohibited 10: TIOC0B 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Page 2590 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 5, 4 PB1MD[1:0] 00/01 R/W PB1 Mode Select the function of the PB1. 3 to 0  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PB1 (initial value) 01: A1 (initial value) 01: A1 10: Setting prohibited 10: TIOC0A 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2591 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.5 Port B I/O Registers 0, 1 (PBIOR0, PBIOR1) PBIOR0 and PBIOR1 are 16-bit readable/writable registers that are used to set the pins on port B as inputs or outputs. The PB22IOR to PB1IOR bits correspond to the PB22 to PB1 pins, respectively. PBIOR1 and PBIOR0 are enabled when the port B pins are functioning as generalpurpose I/O (PB22 to PB1) or TIOC I/O of multi-function timer pulse unit 2. In other states, they are disabled. If a bit in PBIOR1 or PBIOR0 is set to 1, the corresponding pin on port B functions as output pin. If it is cleared to 0, the corresponding pin functions as an input pin. Bits 15 to 7 in PBIOR1 and bit 0 in PBIOR0 are reserved. These bits are always read as 0. The write value should always be 0. (1) Port B I/O Register 1 (PBIOR1) Bit: Initial value: R/W: (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - PB22 IOR PB21 IOR PB20 IOR PB19 IOR PB18 IOR PB17 IOR PB16 IOR 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port B I/O Register 0 (PBIOR0) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Page 2592 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 48.2.6 Section 48 General Purpose I/O Ports Port B Data Registers 0, 1 (PBDR0, PBDR1) PBDR0 and PBDR1 are 16-bit readable/writable registers that store port B data. The PB22DR to PB1DR bits correspond to the PB22 to PB1 pins, respectively. When a pin function is general output, if a value is written to PBDR1 or PBDR0, the value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PBDR1 or PBDR0 is read, the pin state, not the register value, is returned directly. If a value is written to PBDR1 or PBDR0, although that value is written into PBDR1 or PBDR0, it does not affect the pin state. Table 48.13 summarizes PBDR1/PBDR0 read/write operation. (1) Port B Data Register 1 (PBDR1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - PB22 DR PB21 DR PB20 DR PB19 DR PB18 DR PB17 DR PB16 DR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 7  All 0 R Reserved Bit: These bits are always read as 0. The write value should always be 0. 6 PB22DR 0 R/W 5 PB21DR 0 R/W 4 PB20DR 0 R/W 3 PB19DR 0 R/W 2 PB18DR 0 R/W 1 PB17DR 0 R/W 0 PB16DR 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 See table 48.13 Page 2593 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (2) Port B Data Register 0 (PBDR0) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PB15 DR PB14 DR PB13 DR PB12 DR PB11 DR PB10 DR PB9 DR PB8 DR PB7 DR PB6 DR PB5 DR PB4 DR PB3 DR PB2 DR PB1 DR - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 PB15DR 0 R/W See table 48.13 14 PB14DR 0 R/W 13 PB13DR 0 R/W 12 PB12DR 0 R/W 11 PB11DR 0 R/W 10 PB10DR 0 R/W 9 PB9DR 0 R/W 8 PB8DR 0 R/W 7 PB7DR 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0  0 R 0 Reserved This bit is always read as 0. The write value should always be 0. Page 2594 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.13 Port B Data Registers 1, 0 (PBDR1, PBDR0) Read/Write Operation  Bits 6 to 0 of PBDR1 and Bits 15 to 1 of PBDR0 PBIOR1, 0 Pin Function Read Operation 0 General input Pin state Can write to PBDR0/PBDR1, but it has no effect on the pin state. Other than general input Pin state Can write to PBDR0/PBDR1, but it has no effect on the pin state. General output PBDR0/PBDR1 Value written is output to the pin value Other than general output PBDR0/PBDR1 Can write to PBDR0/PBDR1, but it has no effect value on the pin state. 1 48.2.7 Write Operation Port B Port Registers 0, 1 (PBPR0, PBPR1) PBPR (PBPR0, PBPR1) is 16-bit read-only register, in which the PB22PR to PB1PR bits correspond to the PB22 to PB1 pins, respectively. PBPR always returns the states of the pins regardless of the PBCR5 to PBCR0 settings. (1) Port B Port Register 1 (PBPR1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - PB22 PR PB21 PR PB20 PR PB19 PR PB18 PR PB17 PR PB16 PR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PB22 PB21 PB20 PB19 PB18 PB17 PB16 R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 7  All 0 R Reserved Bit: These bits are always read as 0. The write value should always be 0. 6 PB22PR Pin state R 5 PB21PR Pin state R 4 PB20PR Pin state R 3 PB19PR Pin state R 2 PB18PR Pin state R 1 PB17PR Pin state R 0 PB16PR Pin state R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 The pin state is returned. These bits cannot be modified. Page 2595 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (2) Port B Port Register 0 (PBPR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PB15 PR PB14 PR PB13 PR PB12 PR PB11 PR PB10 PR PB9 PR PB8 PR PB7 PR PB6 PR PB5 PR PB4 PR PB3 PR PB2 PR PB1 PR 0 - Initial value: PB15 PB14 PB13 PB12 PB11 PB10 R/W: R R R R R R PB9 R PB8 R PB7 R PB6 R PB5 R PB4 R PB3 R PB2 R PB1 R 0 R Bit Bit Name Initial Value R/W Description 15 PB15PR Pin state R 14 PB14PR Pin state R The pin state is returned. These bits cannot be modified. 13 PB13PR Pin state R 12 PB12PR Pin state R 11 PB11PR Pin state R 10 PB10PR Pin state R 9 PB9PR Pin state R 8 PB8PR Pin state R 7 PB7PR Pin state R 6 PB6PR Pin state R 5 PB5PR Pin state R 4 PB4PR Pin state R 3 PB3PR Pin state R 2 PB2PR Pin state R 1 PB1PR Pin state R 0  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 2596 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 48.2.8 Section 48 General Purpose I/O Ports Port C Control Registers 0 to 2 (PCCR0 to PCCR2) PCCR0 to PCCR2 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port C. (1) Port C Control Register 2 (PCCR2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 3  All 0 R Reserved 2 1 0 PC8MD[2:0] 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 2 to 0 PC8MD[2:0] 000 R/W PC8 Mode Select the function of the PC8. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 000: PC8 100:CTx0&CTx1 001: CS3 101: Setting prohibited 010: TxD7 110: Setting prohibited 011: CTx1 111: Setting prohibited Page 2597 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (2) Port C Control Register 1 (PCCR1) Bit: 15 - Initial value: 0 R/W: R 14 13 12 0 R/W 0 R/W 11 10 9 - PC7MD[2:0] 0 R/W 0 R 8 7 PC6MD[2:0] - 0 R/W 0 R 0 R/W 0 R/W 6 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 3 2 PC5MD[2:0] 5 4 - - 0 R/W 0 R 0 R 0 R/W 1 0 PC4MD[1:0] 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PC7MD[2:0] 000 R/W PC7 Mode Select the function of the PC7. 11  0 R 000: PC7 100: CRx0/CRx1 001: CKE 101: IRQ1 010: RxD7 110: Setting prohibited 011: CRx1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PC6MD[2:0] 000 R/W PC6 Mode Select the function of the PC6. 001: CAS 100: CTx0&CTx1& CTx2 010: SCK7 101: Setting prohibited 011: CTx0 110: Setting prohibited 000: PC6 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PC5MD[2:0] 000 R/W PC5 Mode Select the function of the PC5. 000: PC5 100: CTx0/CTx1/CTx2 001: RAS 101: IRQ0 010: Setting prohibited 110: Setting prohibited 011: CRx0 Page 2598 of 3092 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PC4MD[1:0] 00 R/W PC4 Mode Select the function of the PC4. (3) 0: PC4 10: TxD6 1: WE1/DQMLU/WE 11: Setting prohibited Port C Control Register 0 (PCCR0) Bit: 15 14 - - Initial value: 0 R/W: R 0 R 13 12 PC3MD[1:0] 0 R/W 0 R/W 11 10 - - 0 R 0 R 9 8 PC2MD[1:0] 0 R/W 0 R/W 7 6 5 4 3 2 1 0 - - - PC1MD - - - PC0MD 0 R 0 R 0 R 0/1 R/W 0 R 0 R 0 R 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 PC3MD[1:0] 00 R/W PC3 Mode Select the function of the PC3. 11, 10  All 0 R 00: PC3 10: RxD6 01: WE0/DQMLL 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PC2MD[1:0] 00 R/W PC2 Mode Select the function of the PC2. 7 to 5  All 0 R 00: PC2 10: SCK6 01: RD/WR 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2599 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 4 PC1MD 0/1 R/W PC1 Mode Selects the function of the PC1.  3 to 1 All 0 R Boot modes 0, 1 Boot modes 2 to 5 0: Setting prohibited 0: PC1 (initial value) 1: RD (initial value) 01: RD Reserved These bits are always read as 0. The write value should always be 0. 0 PC0MD 0/1 R/W PC0 Mode Selects the function of the PC0. 48.2.9 Boot modes 0, 1 Boot modes 2 to 5 0: Setting prohibited 0: PC0 (initial value) 1: CS0 (initial value) 1: CS0 Port C I/O Register 0 (PCIOR0) PCIOR0 is a 16-bit readable/writable register that is used to set the pins on port C as inputs or outputs. The PC8IOR to PC0IOR bits correspond to the PC8 to PC0 pins, respectively. PCIOR0 is enabled when the port C pins are functioning as general-purpose I/O (PC8 to PC0). In other states, PCIOR0 is disabled. If a bit in PCIOR0 is set to 1, the corresponding pin on port C functions as an output pin. If it is cleared to 0, the corresponding pin functions as an input pin. Bits 15 to 9 in PCIOR0 are reserved. These bits are always read as 0. The write value should always be 0. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PC8 IOR PC7 IOR PC6 IOR PC5 IOR PC4 IOR PC3 IOR PC2 IOR PC1 IOR PC0 IOR 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 2600 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.10 Port C Data Register 0 (PCDR0) PCDR0 is a 16-bit readable/writable register that stores port C data. The PC8DR to PC0DR bits correspond to the PC8 to PC0 pins, respectively. When a pin function is general output, if a value is written to PCDR0, that value is output directly from the pin, and if PCDR0 is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PCDR0 is read, the pin state, not the register value, is returned directly. If a value is written to PCDR0, although that value is written into PCDR0, it does not affect the pin state. Table 48.14 summarizes PCDR0 read/write operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PC8 DR PC7 DR PC6 DR PC5 DR PC4 DR PC3 DR PC2 DR PC1 DR PC0 DR Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved Bit: These bits are always read as 0. The write value should always be 0. 8 PC8DR 0 R/W 7 PC7DR 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 See table 48.14 Page 2601 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.14 Port C Data Register 0 (PCDR0) Read/Write Operation  Bits 8 to 0 of PCDR0 PCIOR0 Pin Function Read Operation Write Operation 0 General input Pin state Can write to PCDR0, but it has no effect on the pin state. Other than general input Pin state Can write to PCDR0, but it has no effect on the pin state. 1 General output PCDR0 value Value written is output from pin Other than PCDR0 value general output Can write to PCDR0, but it has no effect on the pin state 48.2.11 Port C Port Register 0 (PCPR0) PCPR0 is a 16-bit read-only register, in which the PC8PR to PC0PR bits correspond to the PC8 to PC0 pins, respectively. PCPR0 always returns the states of the pins regardless of the PCCR0 to PCCR2 settings. Bit: 15 Initial value: R/W: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - PC8 PR PC7 PR PC6 PR PC5 PR PC4 PR PC3 PR PC2 PR PC1 PR PC0 PR 0 R 0 R 0 R 0 R 0 R 0 R 0 R PC8 R PC7 R PC6 R PC5 R PC4 R PC3 R PC2 R PC1 R PC0 R Bit Bit Name Initial Value R/W Description 15 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 PC8PR Pin state R 7 PC7PR Pin state R 6 PC6PR Pin state R 5 PC5PR Pin state R 4 PC4PR Pin state R 3 PC3PR Pin state R 2 PC2PR Pin state R 1 PC1PR Pin state R 0 PC0PR Pin state R Page 2602 of 3092 The pin state is returned. These bits cannot be modified. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.12 Port D Control Register 0 to 3 (PDCR0 to PDCR3) PDCR0 to PDCR3 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port D. (1) Port D Control Register 3 (PDCR3) Bit: Initial value: R/W: 15 14 11 10 7 6 - - PD15MD[1:0] 13 12 - - PD14MD[1:0] - - PD13MD[1:0] 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0/1 R/W 9 8 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 0/1 R/W 3 2 - - 0 R 0 R 1 0 PD12MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PD15MD[1:0] 00/01 R/W PD15 Mode Select the function of the PD15. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD15 (initial value) 01: D15/NAF7 (initial value) 01: D15/NAF7 10: Setting prohibited 11: Setting prohibited 10: PWM2H 11: Setting prohibited 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PD14MD[1:0] 00/01 R/W PD14 Mode Select the function of the PD14. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD14 (initial value) 01: D14/NAF6 (initial value) 01: D14/NAF6 10: Setting prohibited 11: Setting prohibited 10: PWM2G 11: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2603 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PD13MD[1:0] 00/01 R/W PD13 Mode Select the function of the PD13. Boot mode 2 to 5 Boot mode 2 to 5 00: PD13 (initial value) 00: PD15 (initial value)  3, 2 All 0 R 01: D13/NAF5 01: D15/NAF7 10: PWM2F 10: PWM2H 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PD12MD[1:0] 00/01 R/W PD12 Mode Select the function of the PD12. Boot mode 2 to 5 Boot mode 2 to 5 00: PD12 (initial value) 00: PD14 (initial value) (2) 01: D12/NAF4 01: D14/NAF6 10: PWM2E 10: PWM2G 11: Setting prohibited 11: Setting prohibited Port D Control Register 2 (PDCR2) Bit: Initial value: R/W: 15 14 11 10 7 6 - - PD11MD[1:0] 13 12 - - PD10MD[1:0] - - 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0/1 R/W 9 8 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 PD9MD[1:0] 0 R/W 0/1 R/W 3 2 - - 0 R 0 R 1 0 PD8MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. Page 2604 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value 13, 12 PD11MD[1:0] 00/01 R/W Description R/W PD11 Mode Select the function of the PD11. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD11 (initial value) 01: D11/NAF3 (initial value) 01: D11/NAF3 10: Setting prohibited 11: Setting prohibited 10: PWM2D 11: Setting prohibited 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PD10MD[1:0] 00/01 R/W PD10 Mode Select the function of the PD10. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD10 (initial value) 01: D10/NAF2 (initial value) 01: D10/NAF2 10: Setting prohibited 11: Setting prohibited 10: PWM2C 11: Setting prohibited 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PD9MD[1:0] 00/01 R/W PD9 Mode Select the function of the PD9. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD9 (initial value) 01: D9/NAF1 (initial value) 01: D10/NAF1 10: Setting prohibited 11: Setting prohibited 10: PWM2B 11: Setting prohibited 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2605 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 1, 0 PD8MD[1:0] 00/01 R/W PD8 Mode Select the function of the PD8. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD8 (initial value) 01: D8/NAF0 (initial value) 01: D8/NAF0 10: Setting prohibited 11: Setting prohibited 10: PWM2A 11: Setting prohibited (3) Port D Control Register 1 (PDCR1) Bit: Initial value: R/W: 15 14 - - 0 R 0 R 13 12 PD7MD[1:0] 0 R/W 0/1 R/W 11 10 7 6 - - PD6MD[1:0] 9 8 - - 0 R 0 R 0 R/W 0 R 0 R 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 PD5MD[1:0] 0 R/W 0/1 R/W 3 2 - - 0 R 0 R 1 0 PD4MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PD7MD[1:0] 00/01 R/W PD7 Mode Select the function of the PD7. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD7 (initial value) 01: D7/FWE (initial value) 01: D7/FWE 11, 10  All 0 R 10: Setting prohibited 10: PWM1H 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Page 2606 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 9, 8 PD6MD[1:0] 00/01 R/W PD6 Mode Select the function of the PD6. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD6 (initial value) 01: D6/FALE (initial value) 01: D6/FALE 10: Setting prohibited 11: Setting prohibited 10: PWM1G 11: Setting prohibited 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PD5MD[1:0] 00/01 R/W PD5 Mode Select the function of the PD5. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD5 (initial value) 01: D5/FCLE (initial value) 01: D5/FCLE 10: Setting prohibited 11: Setting prohibited 10: PWM1F 11: Setting prohibited 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PD4MD[1:0] 00/01 R/W PD4 Mode Select the function of the PD4. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD4 (initial value) 01: D4/FRE (initial value) 01: D4/FRE 10: Setting prohibited 11: Setting prohibited 10: PWM1E 11: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2607 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (4) Port D Control Register 0 (PDCR0) Bit: Initial value: R/W: 15 14 - - 0 R 0 R 13 12 PD3MD[1:0] 0 R/W 0/1 R/W 11 10 7 6 - - PD2MD[1:0] 9 8 - - 0 R 0 R 0 R/W 0 R 0 R 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 PD1MD[1:0] 0 R/W 0/1 R/W 3 2 - - 0 R 0 R 1 0 PD0MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PD3MD[1:0] 00/01 R/W PD3 Mode Select the function of the PD3. 11, 10  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD3 (initial value) 01: D3 (initial value) 01: D3 10: Setting prohibited 10: PWM1D 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PD2MD[1:0] 00/01 R/W PD2 Mode Select the function of the PD2. 7, 6  All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD2 (initial value) 01: D2 (initial value) 01: D2 10: Setting prohibited 10: PWM1C 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Page 2608 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 5, 4 PD1MD[1:0] 00/01 R/W PD1 Mode Select the function of the PD1.  3, 2 All 0 R Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD1 (initial value) 01: D1 (initial value) 01: D1 10: Setting prohibited 10: PWM1B 11: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PD0MD[1:0] 00/01 R/W PD0 Mode Select the function of the PD0. Boot modes 0, 1 Boot modes 2 to 5 00: Setting prohibited 00: PD0 (initial value) 01: D0 (initial value) 01: D0 10: Setting prohibited 10: PWM1A 11: Setting prohibited 11: Setting prohibited 48.2.13 Port D I/O Register 0 (PDIOR0) PDIOR0 is a 16-bit readable/writable register that is used to set the pins on port D as inputs or outputs. The PD15IOR to PD0IOR bits correspond to the PD15 to PD0 pins, respectively. The setting of PDIOR0 is valid for the pins for which general I/O function is selected and has no effect on the pins for which other function is selected. If a bit in PDIOR0 is set to 1, the corresponding pin on port D functions as an output. If it is cleared to 0, the corresponding pin functions as an input. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 IOR PD14 IOR PD13 IOR PD12 IOR PD11 IOR PD10 IOR PD9 IOR PD8 IOR PD7 IOR PD6 IOR PD5 IOR PD4 IOR PD3 IOR PD2 IOR PD1 IOR PD0 IOR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2609 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.14 Port D Port Register 0 (PDDR0) PDDR0 is a 16-bit readable/writable register that stores port D data. The PD15DR to PD0DR bits correspond to the PD15 to PD0 pins, respectively. When a pin function is general output, if a value is written to PDDR0, that value is output directly from the pin, and if PDDR0 is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PDDR0 is read, the pin state, not the register value, is returned directly. If a value is written to PDDR0, although that value is written into PDDR0, it does not affect the pin state. Table 48.15 summarizes PDDR0 read/write operation. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 DR PD14 DR PD13 DR PD12 DR PD11 DR PD10 DR PD9 DR PD8 DR PD7 DR PD6 DR PD5 DR PD4 DR PD3 DR PD2 DR PD1 DR PD0 DR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 PD15DR 0 R/W See table 48.15 14 PD14DR 0 R/W 13 PD13DR 0 R/W 12 PD12DR 0 R/W 11 PD11DR 0 R/W 10 PD10DR 0 R/W 9 PD9DR 0 R/W 8 PD8DR 0 R/W 7 PD7DR 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W Page 2610 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.15 Port D Data Register 0 (PDDR0) Read/Write Operation  Bits 15 to 0 of PDDR0 PCIOR0 Pin Function Read Operation Write Operation 0 General input Pin state Can write to PDDR0, but it has no effect on the pin state. Other than general input Pin state Can write to PDDR0, but it has no effect on the pin state. 1 General output PDDR0 value Value written is output from pin Other than PDDR0 value general output Can write to PDDR0, but it has no effect on the pin state R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2611 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.15 Port D Port Register 0 (PDPR0) PDPR0 is a 16-bit read-only register, in which the PD15PR to PD0PR bits correspond to the PD15 to PD0 pins, respectively. PDPR0 always returns the states of the pins regardless of the PDCR0 to PDCR3 settings. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD15 PR PD14 PR PD13 PR PD12 PR PD11 PR PD10 PR PD9 PR PD8 PR PD7 PR PD6 PR PD5 PR PD4 PR PD3 PR PD2 PR PD1 PR PD0 PR Initial value: PD15 PD14 PD13 PD12 PD11 PD10 R/W: R R R R R R PD9 R PD8 R PD7 R PD6 R PD5 R PD4 R PD3 R PD2 R PD1 R PD0 R Bit Bit Name Initial Value R/W Description The pin state is returned. These bits cannot be modified. 15 PD15PR Pin state R 14 PD14PR Pin state R 13 PD13PR Pin state R 12 PD12PR Pin state R 11 PD11PR Pin state R 10 PD10PR Pin state R 9 PD9PR Pin state R 8 PD8PR Pin state R 7 PD7PR Pin state R 6 PD6PR Pin state R 5 PD5PR Pin state R 4 PD4PR Pin state R 3 PD3PR Pin state R 2 PD2PR Pin state R 1 PD1PR Pin state R 0 PD0PR Pin state R Page 2612 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.16 Port E Control Registers 0, 1 (PECR0, PECR1) PECR1 and PECR0 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port E. (1) Port E Control Register 1 (PECR1: Available Only in the SH7269 Group) Bit: 15 14 - - Initial value: 0 R/W: R 0 R 13 12 PE7MD[1:0] 0 R/W 0 R/W 11 10 - - 0 R 0 R 9 8 PE6MD[1:0] 0 R/W 0 R/W 7 6 - - 0 R 0 R Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 PE5MD[1:0] 0 R/W 0 R/W 3 2 - - 0 R 0 R 1 0 PE4MD[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PE7MD[1:0] 00 R/W PE7 Mode Select the function of the PE7. 11, 10  All 0 R 00: PE7 10: RxD7 01: SDA3 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PE6MD[1:0] 00 R/W PE6 Mode Select the function of the PE6. 7, 6  All 0 R 00: PE6 10: RxD6 01: SCL3 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PE5MD[1:0] 00 R/W PE5 Mode Select the function of the PE5. 3, 2  All 0 R 00: PE5 10: RxD5 01: SDA2 11: DV_HSYNC Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2613 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 1, 0 PE4MD[1:0] 00 R/W PE4 Mode Select the function of the PE4. (2) 00: PE4 10: RxD4 01: SCL2 11: DV_VSYNC Port E Control Register 0 (PECR0) Bit: 15 - Initial value: 0 R/W: R 14 13 12 0 R/W 0 R/W 11 10 - PE3MD[2:0] 0 R/W 0 R 9 8 7 PE2MD[2:0] - 0 R/W 0 R 0 R/W Bit Bit Name Initial Value R/W 15  0 R 0 R/W 6 3 2 PE1MD[2:0] 5 - - 0 R/W 0 R 0 R 0 R/W 4 0 R/W 1 0 PE0MD[1:0] 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PE3MD[2:0] 000 R/W PE3 Mode Select the function of the PE3. 11  0 R 000: PE3 100: DV_HSYNC 001: SDA1 101: Setting prohibited 010: TCLKD 110: Setting prohibited 011: ADTRG 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PE2MD[2:0] 000 R/W PE2 Mode Select the function of the PE2. 7  0 R 000: PE2 100: DV_VSYNC 001: SCL1 101: Setting prohibited 010: TCLKD 110: Setting prohibited 011: IOIS16 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. Page 2614 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 6 to 4 PE1MD[2:0] 000 R/W PE1 Mode Select the function of the PE1. 3, 2  All 0 R 000: PE1 100: DV_CLK 001: SDA0 101: Setting prohibited 010: TCLKB 110: Setting prohibited 011: AUDIO_CLK 111: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PE0MD[1:0] 00 R/W PE0 Mode Select the function of the PE0. 00: PE0 10: TCLKA 01: SCL0 11: LCD_EXTCLK 48.2.17 Port E I/O Register 0 (PEIOR0) PEIOR0 is a 16-bit readable/writable register that is used to set the pins on port F as inputs or outputs. The PE7IOR to PE0IOR bits correspond to the PE7 to PE0 pins respectively. PEIOR0 is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE7 to PE0). In other states, it is disabled. If a bit in PEIOR0 is set to 1, the corresponding pin on port E functions as an output pin. If it is cleared to 0, the corresponding pin functions as an input pin. Bits 15 to 8 of PEIOR0 and bits 7 to 4 of PEIOR0 in the SH7268 Group are reserved. This bit is always read as 0. The write value should always be 0. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2615 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.18 Port E Data Register 0 (PEDR0) PEDR0 is a 16-bit readable/writable register that stores port E data. The PE7DR to PE0DR bits correspond to the PE7 to PE0 pins, respectively. 8 pins on Port E are open-drain outputs. When a pin function is general output, if 0 is written to PEDR0, 0 is output from the pin and if 1 is written to, the pin will be in the high-impedance state. If PEDR0 is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PEDR0 is read, the pin state, not the register value, is returned directly. If a value is written to PEDR0, although that value is written into PEDR0, it does not affect the pin state. Table 48.16 summarizes PEDR0 read/write operation. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PE7 DR PE6 DR PE5 DR PE4 DR PE3 DR PE2 DR PE1 DR PE0 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 PE7DR 0 R/W See table 48.16. 6 PE6DR 0 R/W 5 PE5DR 0 R/W Bits 7 to 4 are reserved in the SH7268 Group. These bits are always read as 1. The write value should always be 1. 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W Page 2616 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.16 Port E Data Register 0 (PEDR0) Read/Write Operation  Bits 7 to 0 of PEDR0 PEIOR0 Pin Operation Read Operation Write Operation 0 1 General input Pin state Can write to PEDR0, but it has no effect on the pin state. Other than general input Pin state Can write to PEDR0, but it has no effect on the pin state General output PEDR0 value When PExDR = 0, 0 outputs from the pin. When PExDR = 1, the pin is in the high-impedance state. Other than PEDR0 value general output Can write to PEDR0, but it has no effect on the pin state 48.2.19 Port E Port Register 0 (PEPR0) PEPR0 is a 16-bit read-only register, in which the PE7PR to PE0PR bits correspond to the PE7 to PE0 pins, respectively. PEPR0 always returns the states of the pins regardless of the PECR0 and PECR1 settings. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PE7 PR PE6 PR PE5 PR PE4 PR PE3 PR PE2 PR PE1 PR PE0 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PE7 R PE6 R PE5 R PE4 R PE3 R PE2 R PE1 R PE0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 PE7PR Pin state R 6 PE6PR Pin state R 5 PE5PR Pin state R 4 PE4PR Pin state R 3 PE3PR Pin state R 2 PE2PR Pin state R 1 PE1PR Pin state R 0 PE0PR Pin state R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 The pin state is returned. These bits cannot be modified. Bits 7 to 4 are reserved in the SH7268 Group. These bits are always read as 1. Page 2617 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.20 Port F Control Registers 0 to 6 (PFCR0 to PFCR6) PFCR0 to PFCR6 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port F. (1) Port F Control Register 6 (PFCR6) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PF23MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 7 0 R/W 0 R/W 6 - PF22MD[2:0] 0 R/W 0 R 5 4 PF21MD[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 0 R/W 3 - 0 R 2 1 0 PF20MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PF23MD[2:0] 000 R/W PF23 Mode Select the function of the PF23. 000: PF23 100: TxD3 001: SD_D2_0 101: MMC_D2 010: Setting prohibited 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PF22MD[2:0] 000 R/W PF22 Mode Select the function of the PF22. 000: PF22 100: RxD3 001: SD_D3_0 101: MMC_D3 010: Setting prohibited 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 2618 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 6 to 4 PF21MD[2:0] 000 R/W PF21 Mode Select the function of the PF21. 000: PF21 100: SCK3 001: SD_CMD_0 101: MMC_CMD 010: Setting prohibited 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited  3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF20MD[2:0] 000 R/W PF20 Mode Select the function of the PF20. 000: PF20 100: Setting prohibited 001: SD_CLK_0 101: MMC_CLK 010: SSIDATA3 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited (2) Port F Control Register 5 (PFCR5) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PF19MD[2:0] 0 R/W 0 R/W 0 R/W 11 - 0 R 10 9 8 PF18MD[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 0 R/W 7 - 0 R 6 5 4 PF17MD[2:0] 0 R/W 0 R/W 0 R/W 3 - 0 R 2 1 0 PF16MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2619 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name 14 to 12 PF19MD[2:0] Initial Value R/W Description 000 R/W PF19 Mode Select the function of the PF19. 000: PF19 100: IRQ7 001: SD_D0_0 101: MMC_D0 010: SSIWS3 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PF18MD[2:0] 000 R/W PF18 Mode Select the function of the PF18. 000: PF18 100: IRQ6 001: SD_D1_0 101: MMC_D1 010: SSISCK3 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PF17MD[2:0] 000 R/W PF17 Mode Select the function of the PF17. 000: PF17 100: IRQ5 001: SD_WP_0 101: Setting prohibited 010: Setting prohibited 110: Setting prohibited 011: FRB 3  0 R 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF16MD[2:0] 000 R/W PF16 Mode Select the function of the PF16. 000: PF16 100: IRQ4 001: SD_CD_0 101: MMC_CD 010: Setting prohibited 110: Setting prohibited 011: FCE Page 2620 of 3092 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 48 General Purpose I/O Ports Port F Control Register 4 (PFCR4) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 - - - - - - - - - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 2 1 0 PF15MD[2:0] 0 R/W 0 R/W 0 R/W Note: Access PFCR4 in 16 bits with H'5A in bits 15 to 8; PFCR4 cannot be accessed in 8 bits. Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. When writing a value to PF15MD[2:0], write H'5A to these bits.  7 to 3 All 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF15MD[2:0] 000* R/W PF15 Mode Select the function of the PF15. Note: * 000: PF15 100: TxD2 001: A0 101: UBCTRG 010: SSIDATA2 110: Setting prohibited 011: WDTOVF 111: Setting prohibited Not initialized by a reset triggered by WDT overflow. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2621 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (4) Port F Control Register 3 (PFCR3) Bit: 15 14 13 12 11 - - - - - Initial value: 0 R/W: R 0 R 0 R 0 R 0 R Bit Bit Name 15 to 11  10 9 8 7 0 R/W 0 R/W 6 - PF14MD[2:0] 0 R/W 0 R 5 4 PF13MD[2:0] 0 R/W Initial Value R/W Description All 0 R Reserved 0 R/W 0 R/W 3 - 0 R 2 1 0 PF12MD[2:0] 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 8 PF14MD[2:0] 000 R/W PF14 Mode Select the function of the PF14. 000: PF14 100: RxD2 001: A25 101: Setting prohibited 010: SSIWS2 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PF13MD[2:0] 000 R/W PF13 Mode Select the function of the PF13. 000: PF13 100: SCK2 001: A24 101: Setting prohibited 010: SSISCK2 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF12MD[2:0] 000 R/W PF12 Mode Select the function of the PF12. 000: PF12 100: TxD1 001: Setting prohibited 101: MMC_D7 Page 2622 of 3092 010: SSIDATA1 110: Setting prohibited 011: DV_DATA3 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (5) Section 48 General Purpose I/O Ports Port F Control Register 2 (PFCR2) Bit: 15 - Initial value: R/W: 0 R 14 13 12 PF11MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 0 R 9 8 0 R/W 0 R/W 7 6 - PF10MD[2:0] 0 R/W 0 R 5 4 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 3 2 - PF9MD[2:0] 0 R/W 0 R 1 0 PF8MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PF11MD[2:0] 000 R/W PF11 Mode Select the function of the PF11. 000: PF11 100: RxD1 001: Setting prohibited 101: MMC_D6 11  0 R 010: SSIWS1 110: Setting prohibited 011: DV_DATA2 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PF10MD[2:0] 000 R/W PF10 Mode Select the function of the PF10. 7  0 R 000: PF10 100: SCK1 001: CS1 101: MMC_D5 010: SSISCK1 110: Setting prohibited 011: DV_DATA1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PF9MD[2:0] 000 R/W PF9 Mode Select the function of the PF9. 000: PF9 100: SCK0 001: BS 101: MMC_D4 010: Setting prohibited 110: RTS1 011: DV_DATA0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 111: Setting prohibited Page 2623 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF8MD[2:0] 000 R/W PF8 Mode Select the function of the PF8. 000: PF8 100: TxD0 001: A23 101: Setting prohibited 010: Setting prohibited 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited (6) Port F Control Register 1 (PFCR1) Bit: 15 - Initial value: R/W: 0 R 14 13 12 0 R/W 0 R/W 11 - PF7MD[2:0] 0 R/W 0 R 10 9 8 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 7 6 - PF6MD[2:0] 0 R/W 0 R 5 4 3 0 R/W 0 R/W 2 - PF5MD[2:0] 0 R/W 0 R 1 0 PF4MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PF7MD[2:0] 000 R/W PF7 Mode Select the function of the PF7. 11  0 R 000: PF7 100: RxD0 001: Setting prohibited 101: SGOUT_3 010: SSIRxD0 110: CTS1 011: Setting prohibited 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. Page 2624 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 10 to 8 PF6MD[2:0] 000 R/W PF6 Mode Select the function of the PF6. 7  0 R 000: PF6 100: Setting prohibited 001: CE2A 101: SGOUT_2 010: SSITxD0 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PF5MD[2:0] 000 R/W PF5 Mode Select the function of the PF5. 3  0 R 000: PF5 100: Setting prohibited 001: Setting prohibited 101: SGOUT_1 010: SSIWS0 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF4MD[2:0] 000 R/W PF4 Mode Select the function of the PF4. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 000: PF4 100: Setting prohibited 001: CS5/CE1A 101: SGOUT_0 010: SSISCK0 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited Page 2625 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (7) Port F Control Register 0 (PFCR0) Bit: 15 - Initial value: R/W: 0 R 14 13 12 0 R/W 0 R/W 11 - PF3MD[2:0] 0 R/W 0 R 10 9 8 0 R/W 0 R/W 7 6 - PF2MD[2:0] 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15  0 R Reserved 5 4 3 0 R/W 0 R/W 2 - PF1MD[2:0] 0 R/W 0 R 1 0 PF0MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PF3MD[2:0] 000 R/W PF3 Mode Select the function of the PF3. 11  0 R 000: PF3 100: TIOC4D 001: CS2 101: AUDIO_XOUT 010: QMI_1/QIO1_1 110: SPBMI_1/SPBIO1_1 011: MISO1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PF2MD[2:0] 000 R/W PF2 Mode Select the function of the PF2. 000: PF2 001: WAIT 010: QMO_1/QIO0_1 011: MOSI1 100: TIOC4C 101: TEND0 110: SPBMO_1/SPBIO0_1 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PF1MD[2:0] 000 R/W PF1 Mode Select the function of the PF1. 000: PF1 001: BACK 010: QSSL_1 011: SSL10 Page 2626 of 3092 100: TIOC4B 101: DACK0 110: Setting prohibited 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PF0MD[2:0] 000 R/W PF0 Mode Select the function of the PF0. 000: PF0 001: BREQ 010: QSPCLK_1 011: RSPCK1 100: TIOC4A 101: DREQ0 110: Setting prohibited 111: Setting prohibited 48.2.21 Port F I/O Registers 0, 1 (PFIOR0, PFIOR1) PFIOR0 and PFIOR1 are 16-bit readable/writable registers that are used to set the pins on port F as inputs or outputs. The PF23IOR to PF0IOR bits correspond to the PF23 to PF0 pins, respectively. PFIOR0 or PFIOR1 is enabled when the port F pins are functioning as generalpurpose I/O (PF23 to PF0) or TIOC I/O of multi-function timer pulse unit 2. In other states, they are disabled. If a bit in PFIOR0 or PFIOR1 is set to 1, the corresponding pin on port F functions as an output. If it is cleared to 0, the corresponding pin functions as an input. Bits 15 to 8 in PFIOR1 are reserved. These bits are always read as 0. The write value should always be 0. (1) Port F IO Register 1 (PFIOR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PF23 IOR PF22 IOR PF21 IOR PF20 IOR PF19 IOR PF18 IOR PF17 IOR PF16 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W (2) Port F IO Register 0 (PFIOR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF15 IOR PF14 IOR PF13 IOR PF12 IOR PF11 IOR PF10 IOR PF9 IOR PF8 IOR PF7 IOR PF6 IOR PF5 IOR PF4 IOR PF3 IOR PF2 IOR PF1 IOR PF0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2627 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.22 Port F Data Registers 0, 1 (PFDR0, PFDR1) PFDR0 and PFDR1 are 16-bit readable/writable registers that store port F data. The PF23DR to PF0DR bits correspond to the PF23 to PF pins respectively. When a pin function is general output, if a value is written to PFDR0 or PFDR1, that value is output directly from the pin, and if PFDR0 or PFDR1 is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PFDR0 or PFDR1 is read, the pin state, not the register value, is returned directly. If a value is written to PFDR0 or PFDR1, although that value is written into PFDR0 or PFDR1, it does not affect the pin state. Table 48.17 summarizes PFDR0/PDFR1 read/write operation. (1) Port F Data Register 1 (PFDR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PF23 DR PF22 DR PF21 DR PF20 DR PF19 DR PF18 DR PF17 DR PF16 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 PF23DR 0 R/W 6 PF22DR 0 R/W 5 PF21DR 0 R/W 4 PF20DR 0 R/W 3 PF19DR 0 R/W 2 PF18DR 0 R/W 1 PF17DR 0 R/W 0 PF16DR 0 R/W Page 2628 of 3092 See table 48.17 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 48 General Purpose I/O Ports Port F Data Register 0 (PFDR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF15 DR PF14 DR PF13 DR PF12 DR PF11 DR PF10 DR PF9 DR PF8 DR PF7 DR PF6 DR PF5 DR PF4 DR PF3 DR PF2 DR PF1 DR PF0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 PF15DR 0 R/W See table 48.17 14 PF14DR 0 R/W 13 PF13DR 0 R/W 12 PF12DR 0 R/W 11 PF11DR 0 R/W 10 PF10DR 0 R/W 9 PF9DR 0 R/W 8 PF8DR 0 R/W 7 PF7DR 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2629 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.17 Port F Data Registers 0, 1 (PFDR0, PFDR1) Read/Write Operation  Bits 23 to 0 of PFDR1 and bits 15 to 0 of PFDR0 PFIOR0 Pin Operation Read Operation Write Operation 0 1 General input Pin state Can write to PFDR0/PFDR1, but it has no effect on the pin state Other than general input Pin state Can write to PFDR0/PFDR1, but it has no effect on the pin state General output PFDR0 value Value written is output from pin Other than PFDR0 value general output Can write to PFDR0/PFDR1, but it has no effect on the pin state 48.2.23 Port F Port Registers 0, 1 (PFPR0, PFPR1) PFPR0 and PFPR1 are 16-bit read-only registers, in which PF23PR to PF0PR bits correspond to the PF23 to PF0 pins, respectively. PFPR0 or PFPR1 always returns the states of the pins regardless of the PFCR0 to PFCR5 settings. (1) Port F Port Register 1 (PFPR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PF23 PR P226 PR PF21 PR PF20 PR PF19 PR PF18 PR PF17 PR PF16 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PF23 PF22 PF21 PF20 PF19 PF18 PF17 PF16 R R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2630 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 7 PF23PR Pin state R 6 PF22PR Pin state R The pin state is returned. These bits cannot be modified. 5 PF21PR Pin state R 4 PF20PR Pin state R 3 PF19PR Pin state R 2 PF18PR Pin state R 1 PF17PR Pin state R 0 PF16PR Pin state R (2) Port F Port Register 0 (PFPR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PF14 PR PF13 PR PF12 PR PF11 PR PF10 PR PF9 PR PF8 PR PF7 PR PF6 PR PF5 PR PF4 PR PF3 PR PF2 PR PF1 PR PF0 PR Initial value: PF15 PF14 PF13 PF12 PF11 PF10 R/W: R R R R R R PF9 R PF8 R PF7 R PF6 R PF5 R PF4 R PF3 R PF2 R PF1 R PF0 R PF15 PR Bit Bit Name Initial Value R/W Description 15 PF15PR Pin state R 14 PF14PR Pin state R The pin state is returned. These bits cannot be modified. 13 PF13PR Pin state R 12 PF12PR Pin state R 11 PF11PR Pin state R 10 PF10PR Pin state R 9 PF9PR Pin state R 8 PF6PR Pin state R 7 PF7PR Pin state R 6 PF6PR Pin state R 5 PF5PR Pin state R 4 PF4PR Pin state R 3 PF3PR Pin state R 2 PF2PR Pin state R 1 PF1PR Pin state R 0 PF0PR Pin state R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2631 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.24 Port G Control Registers 0 to 6 (PGCR0 to PGCR6) PGCR0 to PGCR6 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port G. (1) Port G Control Register 6 (PGCR6) Bit: 15 11 10 7 6 - 14 - PG27MD[1:0] 13 12 - - PG26MD[1:0] - - PG25MD[1:0] Initial value: 0 R/W: R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R/W 9 8 0 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 0 R/W 3 2 - - 0 R 0 R 1 0 PG24MD[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PG27MD[1:0] 00 R/W PG27 Mode Select the function of the PG27. 11, 10  All 0 R 00: PG27 10: LCD_TCON2 01: Setting prohibited 11: LCD_EXTCLK Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PG26MD[1:0] 00 R/W PG26 Mode Select the function of the PG26. 7, 6  All 0 R 00: PG26 10: LCD_TCON1 01: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PG25MD[1:0] 00 R/W PG25 Mode Select the function of the PG25. 3, 2  All 0 R 00: PG25 10: LCD_TCON0 01: Setting prohibited 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. Page 2632 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 1, 0 PG24MD[1:0] 00 R/W PG24 Mode Select the function of the PG24. (2) 00: PG24 10: LCD_CLK 01: Setting prohibited 11: Setting prohibited Port G Control Register 5 (PGCR5) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PG23MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 7 6 - PG22MD[2:0] 0 R/W 0 R 5 4 PG21MD[2:0] 0 R/W 0 R/W 0 R/W 3 - 0 R 2 1 0 PG20MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PG23MD[2:0] 000 R/W PG23 Mode Select the function of the PG23. 000: PG23 100: TxD5 001: Setting prohibited 101: Setting prohibited 11  0 R 010: LCD_DATA23 110: Setting prohibited 011: LCD_TCON6 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PG22MD[2:0] 000 R/W PG22 Mode Select the function of the PG22. 000: PG22 100: RxD5 001: Setting prohibited 101: Setting prohibited 7  0 R 010: LCD_DATA22 110: Setting prohibited 011: LCD_TCON5 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2633 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value 6 to 4 PG21MD[2:0] 00 R/W Description R/W PG21 Mode Select the function of the PG21.  3 0 R 000: PG21 100: TxD4 001: DV_DATA7 101: Setting prohibited 010: LCD_DATA21 110: Setting prohibited 011: LCD_TCON4 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PG20MD[2:0] 000 R/W PG20 Mode Select the function of the PG20. (3) 000: PG20 100: RxD4 001: DV_DATA6 101: Setting prohibited 010: LCD_DATA20 110: Setting prohibited 011: LCD_TCON3 111: Setting prohibited Port G Control Register 4 (PGCR4) Bit: 15 - Initial value: R/W: 0 R 14 13 12 PG19MD[2:0] 0 R/W 0 R/W 0 R/W 11 0 R 10 9 8 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 7 6 - PG18MD[2:0] 0 R/W 0 R 5 4 3 - PG17MD[2:0] 0 R/W 0 R/W 0 R/W 0 R 2 1 0 PG16MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PG19MD[2:0] 000 R/W PG19 Mode Select the function of the PG19. Page 2634 of 3092 000: PG19 100: SCK5 001: DV_DATA5 101: Setting prohibited 010: LCD_DATA19 110: Setting prohibited 011: SPDIF_OUT 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 11  0 Reserved R This bit is always read as 0. The write value should always be 0. 10 to 8 PG18MD[2:0] 000 R/W PG18 Mode Select the function of the PG18. 7, 6  All 0 R 000: PG18 100: SCK4 001: DV_DATA4 101: Setting prohibited 010: LCD_DATA18 110: Setting prohibited 011: SPDIF_IN 111: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PG17MD[1:0] 00 R/W PG17 Mode Select the function of the PG17. 00: PG17 10: LCD_DATA17 01: WE3/ICIOWR/AH/ 11: Setting prohibited DQMUU 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PG16MD[1:0] 00 R/W PG16 Mode Select the function of the PG16. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00: PG16 10: LCD_DATA16 01: WE2/ICIORD/ DQMUL 11: Setting prohibited Page 2635 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (4) Port G Control Register 3 (PGCR3) Bit: 15 11 10 - 14 - PG15MD[1:0] 13 12 - - Initial value: 0 R/W: R 0 R 0 R/W 0 R 0 R/W 0/1 R/W 7 6 PG14MD[1:0] 9 8 - - PG13MD[1:0] 0 R/W 0 R 0 R 0 R/W 0/1 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 0/1 R/W 3 2 - - 0 R 0 R 1 0 PG12MD[1:0] 0 R/W 0/1 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PG15MD[1:0] 00/01 R/W PG15 Mode Select the function of the PG15. 11, 10  All 0 R Boot mode 1 Boot mode 0, 2 to 5 00: Setting prohibited 00: PG15 (initial value) 01: D31 (initial value) 01: D31 10: Setting prohibited 10: LCD_DATA15 11: Setting prohibited 11: PINT7 Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PG14MD[1:0] 00/01 R/W PG14 Mode Select the function of the PG14. 7, 6  All 0 R Boot mode 1 Boot mode 0, 2 to 5 00: Setting prohibited 00: PG14 (initial value) 01: D30 (initial value) 01: D30 10: Setting prohibited 10: LCD_DATA14 11: Setting prohibited 11: PINT6 Reserved This bit is always read as 0. The write value should always be 0. Page 2636 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value 5, 4 PG13MD[1:0] 00/01 R/W Description R/W PG13 Mode Select the function of the PG13. 3, 2  All 0 R Boot mode 1 Boot mode 0, 2 to 5 00: Setting prohibited 00: PG13 (initial value) 01: D29 (initial value) 01: D29 10: Setting prohibited 10: LCD_DATA13 11: Setting prohibited 11: PINT5 Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PG12MD[1:0] 00/01 R/W PG12 Mode Select the function of the PG12. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Boot mode 1 Boot mode 0, 2 to 5 00: Setting prohibited 00: PG12 (initial value) 01: D28 (initial value) 01: D28 10: Setting prohibited 10: LCD_DATA12 11: Setting prohibited 11: PINT4 Page 2637 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (5) Port G Control Register 2 (PGCR2) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PG11MD[2:0] 0 R/W 0 R/W 0/1 R/W 11 10 - 0 R 9 8 7 0 R/W 0 R/W 6 - PG10MD[2:0] 0/1 R/W 0 R 5 4 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 3 2 - PG9MD[2:0] 0/1 R/W 0 R 1 0 PG8MD[2:0] 0 R/W 0 R/W 0/1 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PG11MD[2:0] 000/001 R/W PG11 Mode Select the function of the PG11. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG11 (initial value) 001: D27 (initial value) 010: Setting prohibited 001: D27 011: Setting prohibited 010: LCD_DATA11 100: Setting prohibited 011: PINT3 101: Setting prohibited 100: TIOC3D 110: Setting prohibited 101: Setting prohibited 111: Setting prohibited 110: Setting prohibited 111: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 2638 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value 10 to 8 PG10MD[2:0] 000/001 R/W Description R/W PG10 Mode Select the function of the PG10. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG10 (initial value) 001: D26 (initial value) 010: Setting prohibited 001: D26 011: Setting prohibited 010: LCD_DATA10 100: Setting prohibited 011: PINT2 101: Setting prohibited 100: TIOC3C 110: Setting prohibited 101: Setting prohibited 111: Setting prohibited 110: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PG9MD[2:0] 000/001 R/W PG9 Mode Select the function of the PG9. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG9 (initial value) 001: D25 (initial value) 001: D25 010: Setting prohibited 010: LCD_DATA9 011: Setting prohibited 011: PINT1 100: Setting prohibited 100: TIOC3B 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2639 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 2 to 0 PG8MD[2:0] 000/001 R/W PG8 Mode Select the function of the PG8. Boot mode 0, 2 to 5 Boot mode 1 000: Setting prohibited 000: PG8 (initial value) 001: D24 (initial value) 001: D24 010: Setting prohibited 010: LCD_DATA8 011: Setting prohibited 011: PINT0 100: Setting prohibited 100: TIOC3A 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited (6) Port G Control Register 1 (PGCR1) Bit: 15 - Initial value: 0 R/W: R 14 13 12 11 0 R/W 0 R/W 0/1 R/W 10 - PG7MD[2:0] 0 R 9 8 0 R/W 0 R/W 7 6 - PG6MD[2:0] 0/1 R/W 0 R 5 4 3 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 2 - PG5MD[2:0] 0/1 R/W 0 R 1 0 PG4MD[2:0] 0 R/W 0 R/W 0/1 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PG7MD[2:0] 000/001 R/W PG7 Mode Select the function of the PG7. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG7 (initial value) 001: D23 (initial value) 001: D23 010: Setting prohibited 010: LCD_DATA7 011: Setting prohibited 011: IRQ7 100: Setting prohibited 100: TIOC2B 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited Page 2640 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PG6MD[2:0] 000/001 R/W PG6 Mode Select the function of the PG6. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG6 (initial value) 001: D22 (initial value) 001: D22 010: Setting prohibited 010: LCD_DATA6 011: Setting prohibited 011: IRQ6 100: Setting prohibited 100: TIOC2A 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PG5MD[2:0] 000/001 R/W PG5 Mode Select the function of the PG5. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG5 (initial value) 001: D21 (initial value) 001: D21 010: Setting prohibited 010: LCD_DATA5 011: Setting prohibited 011: IRQ5 100: Setting prohibited 100: TIOC1B 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2641 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 2 to 0 PG4MD[2:0] 000/001 R/W PG4 Mode Select the function of the PG4. Boot mode 0, 2 to 5 Boot mode 1 000: Setting prohibited 000: PG4 (initial value) 001: D20 (initial value) 001: D20 010: Setting prohibited 010: LCD_DATA4 011: Setting prohibited 011: IRQ4 100: Setting prohibited 100: TIOC1A 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited (7) Port G Control Register 0 (PGCR0) Bit: 15 - Initial value: 0 R/W: R 14 13 12 11 - PG3MD[2:0] 0 R/W 0 R/W 0/1 R/W 0 R 10 9 8 0 R/W 0 R/W 7 6 - PG2MD[2:0] 0/1 R/W 0 R 5 4 3 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 2 - PG1MD[2:0] 0/1 R/W 0 R 1 0 PG0MD[2:0] 0 R/W 0 R/W 0/1 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PG3MD[2:0] 000/001 R/W PG3 Mode Select the function of the PG3. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG3 (initial value) 001: D19 (initial value) 001: D19 010: Setting prohibited 010: LCD_DATA3 011: Setting prohibited 011: IRQ3 100: Setting prohibited 100: TIOC0D 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited Page 2642 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PG2MD[2:0] 000/001 R/W PG2 Mode Select the function of the PG2. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG2 (initial value) 001: D18 (initial value) 001: D18 010: Setting prohibited 010: LCD_DATA2 011: Setting prohibited 011: IRQ2 100: Setting prohibited 100: TIOC0C 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PG1MD[2:0] 000/001 R/W PG1 Mode Select the function of the PG1. Boot mode 1 Boot mode 0, 2 to 5 000: Setting prohibited 000: PG1 (initial value) 001: D17 (initial value) 001: D17 010: Setting prohibited 010: LCD_DATA1 011: Setting prohibited 011: IRQ1 100: Setting prohibited 100: TIOC0B 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2643 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value 2 to 0 PG0MD[2:0] 000/001 R/W Description R/W PG0 Mode Select the function of the PG0. Boot mode 0, 2 to 5 Boot mode 1 000: Setting prohibited 000: PG0 (initial value) 001: D16 (initial value) 001: D16 010: Setting prohibited 010: LCD_DATA0 011: Setting prohibited 011: IRQ0 100: Setting prohibited 100: TIOC0A 101: Setting prohibited 101: Setting prohibited 110: Setting prohibited 110: Setting prohibited 111: Setting prohibited 111: Setting prohibited 48.2.25 Port G I/O Registers 0, 1 (PGIOR0, PGIOR1) PGIOR1 and PGIOR0 are 16-bit readable/writable registers that are used to set the pins on port G as inputs or outputs. The PG27IOR to PG0IOR bits correspond to the PG27 to PG0, respectively. PGIOR1 and PGIOR0 are enabled when the port G pins are functioning as general-purpose I/O (PG27 to PG0) or TIOC I/O of multi-function timer pulse unit 2. In other states, they are disabled. If bits in PGIOR1 and PGIOR0 are set to 1, corresponding pins on port G functions as outputs. If they are cleared to 0, the corresponding pins function as inputs. Bits 15 to 12 in PGIOR1 are reserved. These bits are always read as 0. The write values should always be 0. (1) Port G IO Register 1 (PGIOR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - PG27 IOR PG26 IOR PG25 IOR PG24 IOR PG23 IOR PG22 IOR PG21 IOR PG20 IOR PG19 IOR PG18 IOR PG17 IOR PG16 IOR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W (2) Port G IO Register 0 (PGIOR0) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG15 IOR PG14 IOR PG13 IOR PG12 IOR PG11 IOR PG10 IOR PG9 IOR PG8 IOR PG7 IOR PG6 IOR PG5 IOR PG4 IOR PG3 IOR PG2 IOR PG1 IOR PG0 IOR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 2644 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.26 Port G Data Registers 0, 1 (PGDR0, PGDR1) PGDR1 and PGDR0 are 16-bit readable/writable registers that store port G data. The PG27DR to PG0DR bits correspond to the PG27 to PGDR0 pins, respectively. When a pin function is general output, if a value is written to PGDR1 or PGDR0, that value is output from the pin, and if PGDR1 or PGDR0 is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PGDR1 or PGDR0 is read, the pin state, not the register value, is returned directly. If a value is written to PGDR1 or PGDR0, although that value is written into PGDR1 or PGDR0, it does not affect the pin state. Table 48.18 summarizes PGDR1/PGDR0 read/write operation. (1) Port G Data Register 1 (PGDR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - PG27 DR PG26 DR PG25 DR PG24 DR PG23 DR PG22 DR PG21 DR PG20 DR PG19 DR PG18 DR PG17 DR PG16 DR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 PG27DR 0 R/W 10 PG26DR 0 R/W 9 PG25DR 0 R/W 8 PG24DR 0 R/W 7 PG23DR 0 R/W 6 PG22DR 0 R/W 5 PG21DR 0 R/W 4 PG20DR 0 R/W 3 PG19DR 0 R/W 2 PG18DR 0 R/W 1 PG17DR 0 R/W 0 PG16DR 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 See table 48.18 Page 2645 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (2) Port G Data Register 0 (PGDR0) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG15 DR PG14 DR PG13 DR PG12 DR PG11 DR PG10 DR PG9 DR PG8 DR PG7 DR PG6 DR PG5 DR PG4 DR PG3 DR PG2 DR PG1 DR PG0 DR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 PG15DR 0 R/W See table 48.18 14 PG14DR 0 R/W 13 PG13DR 0 R/W 12 PG12DR 0 R/W 11 PG11DR 0 R/W 10 PG10DR 0 R/W 9 PG9DR 0 R/W 8 PG8DR 0 R/W 7 PG7DR 0 R/W 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W Page 2646 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.18 Port G Data Registers 1, 0 (PGDR1, PGDR0) Read/Write Operation  Bits 11 to 0 of PGDR1 and Bits 15 to 0 of PGDR0 PGIOR1, 0 Pin Function Read Operation Write Operation 0 General input Pin state Can write to PGDR0/PGDR1, but it has no effect on the pin state Other than general input Pin state Can write to PGDR0/PGDR1, but it has no effect on the pin state General output PGDR0/PGDR1 value Value written is output to pin Other than general output PGDR0/PGDR1 value Can write to PGDR0/PGDR1, but it has no effect on the pin state 1 48.2.27 Port G Port Registers 0, 1 (PGPR0, PGPR1) PGPR1 and PGPR0 are 16-bit read-only registers, in which the PG27PR to PG0PR bits correspond to the PG27 to PG0 pins, respectively. PGPR1 and PGPR0 always return the states of the pins regardless of the PGCR6 to PGCR0 settings. (1) Port G Port Register 1 (PGPR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - PG27 PR PG26 PR PG25 PR PG24 PR PG23 PR PG22 PR PG21 PR PG20 PR PG19 PR PG18 PR PG17 PR PG16 PR Initial value: 0 R/W: R 0 R 0 R 0 R PG27 PG26 PG25 PG24 PG23 PG22 PG21 PG20 PG19 PG18 PG17 PG16 R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2647 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 11 PG27PR Pin state R 10 PG26PR Pin state R The pin state is returned. These bits cannot be modified. 9 PG25PR Pin state R 8 PG24PR Pin state R 7 PG23PR Pin state R 6 PG22PR Pin state R 5 PG21PR Pin state R 4 PG20PR Pin state R 3 PG19PR Pin state R 2 PG18PR Pin state R 1 PG17PR Pin state R 0 PG16PR Pin state R Page 2648 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 48 General Purpose I/O Ports Port G Port Register 0 (PGPR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG15 PR PG14 PR PG13 PR PG12 PR PG11 PR PG10 PR PG9 PR PG8 PR PG7 PR PG6 PR PG5 PR PG4 PR PG3 PR PG2 PR PG1 PR PG0 PR Initial value: PG15 PG14 PG13 PG12 PG11 PG10 R/W: R R R R R R PG9 R PG8 R PG7 R PG6 R PG5 R PG4 R PG3 R PG2 R PG1 R PG0 R Bit Bit Name Initial Value R/W Description 15 PG15PR Pin state R 14 PG14PR Pin state R The pin state is returned. These bits cannot be modified. 13 PG13PR Pin state R 12 PG12PR Pin state R 11 PG11PR Pin state R 10 PG10PR Pin state R 9 PG9PR Pin state R 8 PG8PR Pin state R 7 PG7PR Pin state R 6 PG6PR Pin state R 5 PG5PR Pin state R 4 PG4PR Pin state R 3 PG3PR Pin state R 2 PG2PR Pin state R 1 PG1PR Pin state R 0 PG0PR Pin state R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2649 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.28 Port H Control Registers 0, 1 (PHCR0, PHCR1) PHCR1 and PHCR0 are 16-bit readable/writable registers that are used to select the function of the multiplexed pins on port H. (1) Port H Control Register 1 (PHCR1) Bit: 15 11 10 - 14 - PH7MD[1:0] 13 12 - - Initial value: 0 R/W: R 0 R 0 R/W 0 R 0 R 0 R/W 9 8 7 6 - - PH5MD[1:0] 0 R 0 R 0 R/W PH6MD[1:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 0 R/W 3 2 - - 0 R 0 R 1 0 PH4MD[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PH7MD[1:0] 00 R/W PH7 Mode Select the function of the PH7. 00: PH7 10: PINT7 01: AN7 11: Setting prohibited Note: 11, 10  All 0 R Bits 13 and 12 are reserved in the SH7268 Group. These bits are always read as 0. The write value should always be 0. Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PH6MD[1:0] 00 R/W PH6 Mode Select the function of the PH6. 00: PH6 10: PINT6 01: AN6 11: Setting prohibited Note: 7, 6  All 0 R Bits 9 and 8 are reserved in the SH7268 Group. These bits are always read as 0. The write value should always be 0. Reserved These bits are always read as 0. The write value should always be 0. Page 2650 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 5, 4 PH5MD[1:0] 00 R/W PH5 Mode Select the function of the PH5.  3, 2 All 0 R 00: PH5 10: PINT5 01: AN5 11: LCD_EXTCLK Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PH4MD[1:0] 00 R/W PH4 Mode Select the function of the PH4. (2) 00: PH4 10: PINT4 01: AN4 11: Setting prohibited Port H Control Register 0 (PHCR0) Bit: 15 11 10 - 14 - PH3MD[1:0] 13 12 - - Initial value: 0 R/W: R 0 R 0 R/W 0 R 0 R 0 R/W 9 8 PH2MD[1:0] 0 R/W 0 R/W 7 6 - - 0 R 0 R Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 5 4 PH1MD[1:0] 0 R/W 0 R/W 3 2 - - 0 R 0 R 1 0 PH0MD[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 13, 12 PH3MD[1:0] 00 R/W PH3 Mode Select the function of the PH3. 11, 10  All 0 R 00: PH3 10: PINT3 01: AN3 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 9, 8 PH2MD[1:0] 00 R/W PH2 Mode Select the function of the PH2. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 00: PH2 10: PINT2 01: AN2 11: Setting prohibited Page 2651 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 PH1MD[1:0] 00 R/W PH1 Mode Select the function of the PH1.  3, 2 All 0 R 00: PH1 10: PINT1 01: AN1 11: Setting prohibited Reserved These bits are always read as 0. The write value should always be 0. 1, 0 PH0MD[1:0] 00 R/W PH3 Mode Select the function of the PH0. 00: PH0 10: PINT0 01: AN0 11: Setting prohibited 48.2.29 Port H Port Register 0 (PHPR0) PHPR0 is a 16-bit read-only register, in which the PH7PR to PH0PR bits correspond to the PH7 to PH0 pins, respectively. PHPR0 always returns the states of the pins when the general input function is selected. This register is read as 1 during operation of the A/D converter. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - PH7 PR PH6 PR PH5 PR PH4 PR PH3 PR PH2 PR PH1 PR PH0 PR Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R PH7 R PH6 R PH5 R PH4 R PH3 R PH2 R PH1 R PH0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2652 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 7 PH7PR Pin state R 6 PH6PR Pin state R The pin state is returned. These bits cannot be modified. 5 PH5PR Pin state R 4 PH4PR Pin state R 3 PH3PR Pin state R 2 PH2PR Pin state R 1 PH1PR Pin state R 0 PH0PR Pin state R Note: Bits 7 and 6 are reserved in the SH7268 Group. These bits are always read as 0. The write value should always be 0. 48.2.30 Port J Control Registers 0 to 7 (PJCR0 to PJCR7: Available Only in the SH7269 Group) PJCR7 to PJCR0 are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port J. (1) Port J Control Register 7 (PJCR7) Bit: 15 14 13 12 11 - - - PJ31 MD - Initial value: 0 R/W: R 0 R 0 R 0 R/W 0 R Bit Bit Name 15 to 13  10 9 8 PJ30MD[2:0] 0 R/W 0 R/W 7 6 - 0 R/W 0 R 5 4 PJ29MD[2:0] 0 R/W Initial Value R/W Description All 0 R Reserved 0 R/W 0 R/W 3 - 0 R 2 1 0 PJ28MD[2:0] 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 12 PJ31MD 0 R/W PJ31 Mode Select the function of the PJ31. 0: PJ31 1: DV_CLK 11  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2653 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 10 to 8 PJ30MD[2:0] 000 R/W PJ30 Mode Select the function of the PJ30. 000: PJ30 100: TIOC2B 001: Setting prohibited 101: IETxD 010: SSIDATA5 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ29MD[2:0] 000 R/W PJ29 Mode Select the function of the PJ29. 000: PJ29 100: TIOC2A 001: Setting prohibited 101: IERxD 010: SSIWS5 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ28MD[2:0] 000 R/W PJ28 Mode Select the function of the PJ28. 000: PJ28 100: TIOC1B 001: Setting prohibited 101: RTS7 010: SSISCK5 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited Page 2654 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 48 General Purpose I/O Ports Port J Control Register 6 (PJCR6) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PJ27MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 PJ26MD[2:0] 0 R/W 0 R/W 7 6 - 0 R/W 0 R 5 4 3 PJ25MD[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 2 - 0 R/W 0 R 1 0 PJ24MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PJ27MD[2:0] 000 R/W PJ27 Mode Select the function of the PJ27. 000: PJ27 100: TIOC1A 001: SGOUT_3 101: CTS7 010: Setting prohibited 110: Setting prohibited 011: Setting prohibited 111: Setting prohibited 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PJ26MD[2:0] 000 R/W PJ26 Mode Select the function of the PJ26. 7  0 R 000: PJ26 100: Setting prohibited 001: SGOUT_2 101: TxD7 010: SSIDATA4 110: Setting prohibited 011: LCD_TCON5 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ25MD[2:0] 000 R/W PJ25 Mode Select the function of the PJ25. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 000: PJ25 100: SPDIF_OUT 001: SGOUT_1 101: RxD7 010: SSIWS4 110: Setting prohibited 011: LCD_TCON4 111: Setting prohibited Page 2655 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ24MD[2:0] 000 R/W PJ24 Mode Select the function of the PJ24. (3) 000: PJ24 100: SPDIF_IN 001: SGOUT_0 101: SCK7 010: SSISCK4 110: Setting prohibited 011: LCD_TCON3 111: Setting prohibited Port J Control Register 5 (PJCR5) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PJ23MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 PJ22MD[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 7 6 - 0 R/W 0 R 5 4 3 PJ21MD[2:0] 0 R/W 0 R/W 2 - 0 R/W 0 R 1 0 PJ20MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PJ23MD[2:0] 000 R/W PJ23 Mode Select the function of the PJ23. 11  0 R 000: PJ23 100: IRQ3 001: DV_DATA23 101: CTx1 010: LCD_DATA23 110: CTx0&CTx1 011: LCD_TCON6 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. Page 2656 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 10 to 8 PJ22MD[2:0] 000 R/W PJ22 Mode Select the function of the PJ22. 7  0 R 000: PJ22 100: IRQ2 001: DV_DATA22 101: CRx1 010: LCD_DATA22 110: CRx0/CRx1 011: LCD_TCON5 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ21MD[2:0] 000 R/W PJ21 Mode Select the function of the PJ21. 000: PJ21 100: IRQ1 001: DV_DATA21 101: CTx2 010: LCD_DATA21 110: CTx0&CTx1& CTx2 011: LCD_TCON4 111: Setting prohibited 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ20MD[2:0] 000 R/W PJ20 Mode Select the function of the PJ20. 000: PJ20 100: IRQ0 001: DV_DATA20 101: CRx2 010: LCD_DATA20 110: CRx0/CRx1/ CRx2 011: LCD_TCON3 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2657 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (4) Port J Control Register 4 (PJCR4) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PJ19MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 PJ18MD[2:0] 0 R/W 0 R/W 7 6 - 0 R/W 0 R 5 4 3 PJ17MD[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W - 0 R/W 0 R 2 1 0 PJ16MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PJ19MD[2:0] 000 R/W PJ19 Mode Select the function of the PJ19. 11  0 R 000: PJ19 100: TIOC0D 001: DV_DATA19 101: SIOFRxD 010: LCD_DATA19 110: AUDIO_XOUT 011: MISO0 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PJ18MD[2:0] 000 R/W PJ18 Mode Select the function of the PJ18. 7  0 R 000: PJ18 100: TIOC0C 001: DV_DATA18 101: SIOFTxD 010: LCD_DATA18 110: Setting prohibited 011: MOSI0 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ17MD[2:0] 000 R/W PJ17 Mode Select the function of the PJ17. Page 2658 of 3092 000: PJ17 100: TIOC0B 001: DV_DATA17 101: SIOFSYNC 010: LCD_DATA17 110: Setting prohibited 011: SSL00 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ16MD[2:0] 000 R/W PJ16 Mode Select the function of the PJ16. (5) 000: PJ16 100: TIOC0A 001: DV_DATA16 101: SIOFSCK 010: LCD_DATA16 110: Setting prohibited 011: RSPCK0 111: Setting prohibited Port J Control Register 3 (PJCR3) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PJ15MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 PJ14MD[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 7 6 - 0 R/W 0 R 5 4 3 PJ13MD[2:0] 0 R/W 0 R/W 2 - 0 R/W 0 R 1 0 PJ12MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PJ15MD[2:0] 000 R/W PJ15 Mode Select the function of the PJ15. 11  0 R 000: PJ15 100: PWM2H 001: DV_DATA15 101: TxD7 010: LCD_DATA15 110: Setting prohibited 011: PINT7 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2659 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 10 to 8 PJ14MD[2:0] 000 R/W PJ14 Mode Select the function of the PJ14. 7  0 R 000: PJ14 100: PWM2G 001: DV_DATA14 101: TxD6 010: LCD_DATA14 110: Setting prohibited 011: PINT6 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ13MD[2:0] 000 R/W PJ13 Mode Select the function of the PJ13. 3  0 R 000: PJ13 100: PWM2F 001: DV_DATA13 101: TxD5 010: LCD_DATA13 110: Setting prohibited 011: PINT5 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ12MD[2:0] 000 R/W PJ12 Mode Select the function of the PJ12. Page 2660 of 3092 000: PJ12 100: PWM2E 001: DV_DATA12 101: SCK7 010: LCD_DATA12 110: Setting prohibited 011: PINT4 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (6) Section 48 General Purpose I/O Ports Port J Control Register 2 (PJCR2) Bit: 15 - Initial value: 0 R/W: R 14 13 12 PJ11MD[2:0] 0 R/W 0 R/W 0 R/W 11 10 - 0 R 9 8 PJ10MD[2:0] 0 R/W 0 R/W 7 6 - 0 R/W 0 R 5 4 3 PJ9MD[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 2 - 0 R/W 0 R 1 0 PJ8MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PJ11MD[2:0] 000 R/W PJ11 Mode Select the function of the PJ11. 11  0 R 000: PJ11 100: PWM2D 001: DV_DATA11 101: SCK6 010: LCD_DATA11 110: Setting prohibited 011: PINT3 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PJ10MD[2:0] 000 R/W PJ10 Mode Select the function of the PJ10. 7  0 R 000: PJ10 100: PWM2C 001: DV_DATA10 101: SCK5 010: LCD_DATA10 110: Setting prohibited 011: PINT2 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ9MD[2:0] 000 R/W PJ9Mode Select the function of the PJ9. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 000: PJ9 100: PWM2B 001: DV_DATA9 101: RTS5 010: LCD_DATA9 110: Setting prohibited 011: PINT1 111: Setting prohibited Page 2661 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ8MD[2:0] 000 R/W PJ8 Mode Select the function of the PJ8. (7) 000: PJ8 100: PWM2A 001: DV_DATA8 101: CTS5 010: LCD_DATA8 110: Setting prohibited 011: PINT0 111: Setting prohibited Port J Control Register 1 (PJCR1) Bit: 15 14 - Initial value: 0 R/W: R 13 12 PJ7MD[2:0] 0 R/W 0 R/W 11 10 9 - 0 R/W 0 R 8 PJ6MD[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W 15  0 R 7 6 - 0 R/W 0 R 5 4 3 PJ5MD[2:0] 0 R/W 0 R/W 2 - 0 R/W 0 R 1 0 PJ4MD[2:0] 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 PJ7MD[2:0] 000 R/W PJ7 Mode Select the function of the PJ7. 11  0 R 000: PJ7 100: PWM1H 001: DV_DATA7 101: Setting prohibited 010: LCD_DATA7 110: Setting prohibited 011: SD_D2_1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. Page 2662 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 10 to 8 PJ6MD[2:0] 000 R/W PJ6 Mode Select the function of the PJ6. 7  0 R 000: PJ6 100: PWM1G 001: DV_DATA6 101: Setting prohibited 010: LCD_DATA6 110: Setting prohibited 011: SD_D3_1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ5MD[2:0] 000 R/W PJ5 Mode Select the function of the PJ5. 3  0 R 000: PJ5 100: PWM1F 001: DV_DATA5 101: Setting prohibited 010: LCD_DATA5 110: Setting prohibited 011: SD_CMD_1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ4MD[2:0] 000 R/W PJ4 Mode Select the function of the PJ4. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 000: PJ4 100: PWM1E 001: DV_DATA4 101: Setting prohibited 010: LCD_DATA4 110: Setting prohibited 011: SD_CLK_1 111: Setting prohibited Page 2663 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (8) Port J Control Register 0 (PJCR0) Bit: 15 14 - Initial value: 0 R/W: R 13 12 PJ3MD[2:0] 0 R/W 0 R/W 11 10 9 - 0 R/W 0 R 8 PJ2MD[2:0] 0 R/W 0 R/W 7 6 - 0 R/W 0 R 5 4 3 PJ1MD[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 15  0 R Reserved 0 R/W 2 - 0 R/W 0 R 1 0 PJ0MD[2:0] 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 to 12 PJ3MD[2:0] 000 R/W PJ3 Mode Select the function of the PJ3. 11  0 R 000: PJ3 100: PWM1D 001: DV_DATA3 101: Setting prohibited 010: LCD_DATA3 110: Setting prohibited 011: SD_D0_1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 PJ2MD[2:0] 000 R/W PJ2 Mode Select the function of the PJ2. 7  0 R 000: PJ2 100: PWM1C 001: DV_DATA2 101: Setting prohibited 010: LCD_DATA2 110: Setting prohibited 011: SD_D1_1 111: Setting prohibited Reserved This bit is always read as 0. The write value should always be 0. 6 to 4 PJ1MD[2:0] 000 R/W PJ1 Mode Select the function of the PJ1. Page 2664 of 3092 000: PJ1 100: PWM1B 001: DV_DATA1 101: Setting prohibited 010: LCD_DATA1 110: Setting prohibited 011: SD_WP_1 111: Setting prohibited R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PJ0MD[2:0] 000 R/W PJ0 Mode Select the function of the PJ0. 000: PJ0 100: PWM1A 001: DV_DATA0 101: Setting prohibited 010: LCD_DATA0 110: Setting prohibited 011: SD_CD_1 111: Setting prohibited 48.2.31 Port J I/O registers 0, 1 (PJIOR0, PJIOR1: Available Only in the SH7269 Group) PJIOR0 and PJIOR1 are 16-bit readable/writable registers that are used to set the pins on port J as inputs or outputs. The PJ31IOR to PJ0IOR bits correspond to the PJ31 to PJ0 pins respectively. The setting of PJIOR0 or PJIOR1 is valid for the pins for which general I/O (PJ31 to PJ0) function and has no effect on the pins for which other function is selected. If a bit in PJIOR0 or PJIOR1 is set to 1, the corresponding pin on port J functions as an output pin. If it is cleared to 0, the corresponding pin functions as an input pin. (1) Port J IO Register 1 (PJIOR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ31 IOR PJ30 IOR PJ29 IOR PJ28 IOR PJ27 IOR PJ26 IOR PJ25 IOR PJ24 IOR PJ23 IOR PJ22 IOR PJ21 IOR PJ20 IOR PJ19 IOR PJ18 IOR PJ17 IOR PJ16 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W (2) Port J IO Register 0 (PJIOR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ15 IOR PJ14 IOR PJ13 IOR PJ12 IOR PJ11 IOR PJ10 IOR PJ9 IOR PJ8 IOR PJ7 IOR PJ6 IOR PJ5 IOR PJ4 IOR PJ3 IOR PJ2 IOR PJ1 IOR PJ0 IOR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2665 of 3092 Section 48 General Purpose I/O Ports SH7268 Group, SH7269 Group 48.2.32 Port J Data Registers 0, 1 (PJDR0, PJDR1: Available Only in the SH7269 Group) PJDR0 and PJDR1 are 16-bit readable/writable registers that store port J data. The PJ31DR to PJ0DR bits correspond to the PJ31 to PJ0 pins, respectively. When a pin function is general output, if a value is written to PJDR0 or PJDR1, that value is output from the pin, and if PJDR0 or PJDR1 is read, the register value is returned directly regardless of the pin state. When a pin function is general input, if PJDR0 or PJDR1 is read, the pin state, not the register value, is returned directly. If a value is written to PJDR0 or PJDR1, although that value is written into PJDR0 or PJDR1, it does not affect the pin state. Table 48.19 summarizes PJDR0/PJDR1 read/write operation. Page 2666 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (1) Section 48 General Purpose I/O Ports Port J Data Register 1 (PJDR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ31 DR PJ30 DR PJ29 DR PJ28 DR PJ27 DR PJ26 DR PJ25 DR PJ24 DR PJ23 DR PJ22 DR PJ21 DR PJ20 DR PJ19 DR PJ18 DR PJ17 DR PJ16 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 PJ31DR 0 R/W See table 48.19 14 PJ30DR 0 R/W 13 PJ29DR 0 R/W 12 PJ28DR 0 R/W 11 PJ27DR 0 R/W 10 PJ26DR 0 R/W 9 PJ25DR 0 R/W 8 PJ24DR 0 R/W 7 PJ23DR 0 R/W 6 PJ22DR 0 R/W 5 PJ21DR 0 R/W 4 PJ20DR 0 R/W 3 PJ19DR 0 R/W 2 PJ18DR 0 R/W 1 PJ17DR 0 R/W 0 PJ16DR 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2667 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports (2) Port J Data Register 0 (PJDR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ15 DR PJ14 DR PJ13 DR PJ12 DR PJ11 DR PJ10 DR PJ9 DR PJ8 DR PJ7 DR PJ6 DR PJ5 DR PJ4 DR PJ3 DR PJ2 DR PJ1 DR PJ0 DR Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 PJ15DR 0 R/W See table 48.19 14 PJ14DR 0 R/W 13 PJ13DR 0 R/W 12 PJ12DR 0 R/W 11 PJ11DR 0 R/W 10 PJ10DR 0 R/W 9 PJ9DR 0 R/W 8 PJ8DR 0 R/W 7 PJ7DR 0 R/W 6 PJ6DR 0 R/W 5 PJ5DR 0 R/W 4 PJ4DR 0 R/W 3 PJ3DR 0 R/W 2 PJ2DR 0 R/W 1 PJ1DR 0 R/W 0 PJ0DR 0 R/W Page 2668 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Table 48.19 Port J Data Registers 1, 0 (PJDR1, PJDR0) Read/Write Operation  Bits 15 to 0 of PJDR1 and bits 15 to 0 of PJDR0 PJIOR0, 1 Pin Function Read Operation Write Operation 0 General input Pin state Can write to PJDR0/PJDR1, but it has no effect on the pin state. Other than general input Pin state Can write to PJDR0/PJDR1, but it has no effect on the pin state. 1 General output PJDR0/PJDR1 value Value written is output from pin Other than PJDR0/PJDR1 general output value Can write to PJDR0/PJDR1, but it has no effect on the pin state 48.2.33 Port J Port Registers 0, 1 (PJPR0, PJPR1: Available Only in the SH7269 Group) PJPR0 and PJPR1 are 16-bit read-only registers, in which the PJ31PR to PJ0PR bits correspond to the PJ31 to PJ0 pins, respectively. PJPR0 and PJPR1 always return the states of the pins regardless of the PJCR0 and PJCR1 settings. (1) Port J Port Register 1 (PJPR1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ31 PR PJ30 PR PJ29 PR PJ28 PR PJ27 PR PJ26 PR PJ25 PR PJ24 PR PJ23 PR PJ22 PR PJ21 PR PJ20 PR PJ19 PR PJ18 PR PJ17 PR PJ16 PR Initial value: PJ31 R/W: R PJ30 R PJ29 R PJ28 R PJ27 R PJ26 R PJ25 R PJ24 R PJ23 R PJ22 R PJ21 R PJ20 R PJ19 R PJ18 R PJ17 R PJ16 R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2669 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 15 PJ31PR Pin state R 14 PJ30PR Pin state R The pin state is returned. These bits cannot be modified. 13 PJ29PR Pin state R 12 PJ28PR Pin state R 11 PJ27PR Pin state R 10 PJ26PR Pin state R 9 PJ25PR Pin state R 8 PJ24PR Pin state R 7 PJ23PR Pin state R 6 PJ22PR Pin state R 5 PJ21PR Pin state R 4 PJ20PR Pin state R 3 PJ19PR Pin state R 2 PJ18PR Pin state R 1 PJ17PR Pin state R 0 PJ16PR Pin state R Page 2670 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 48 General Purpose I/O Ports Port J Port Register 0 (PJPR0) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PJ15 PR PJ14 PR PJ13 PR PJ12 PR PJ11 PR PJ10 PR PJ9 PR PJ8 PR PJ7 PR PJ6 PR PJ5 PR PJ4 PR PJ3 PR PJ2 PR PJ1 PR PJ0 PR Initial value: PJ15 R/W: R PJ14 R PJ13 R PJ12 R PJ11 R PJ10 R PJ9 R PJ8 R PJ7 R PJ6 R PJ5 R PJ4 R PJ3 R PJ2 R PJ1 R PJ0 R Bit Bit Name Initial Value R/W Description 15 PJ15PR Pin state R 14 PJ14PR Pin state R The pin state is returned. These bits cannot be modified. 13 PJ13PR Pin state R 12 PJ12PR Pin state R 11 PJ11PR Pin state R 10 PJ10PR Pin state R 9 PJ9PR Pin state R 8 PJ8PR Pin state R 7 PJ7PR Pin state R 6 PJ6PR Pin state R 5 PJ5PR Pin state R 4 PJ4PR Pin state R 3 PJ3PR Pin state R 2 PJ2PR Pin state R 1 PJ1PR Pin state R 0 PJ0PR Pin state R R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2671 of 3092 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports 48.2.34 Serial Sound Interface Noise Canceler Control Register (SNCR) SNCR is 16-bit readable/writable register that controls the noise canceler in the input route from the LSI pin to a serial sound interface. Each bit can be set only when slave mode is selected for the corresponding channel of the serial sound interface. The bit should be used as it is the initial value when master mode is selected for the corresponding channel of the serial sound interface. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - SSI5 NCE SSI4 NCE SSI3 NCE SSI2 NCE SSI1 NCE SSI0 NCE Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 SSI5NCE 0 R/W Serial Sound Interface Channel 5 Noise Canceler Enable Enables or disables the noise canceler of SSISCK5, SSIWS5, and SSIDATA5. 0: Noise canceler is disabled. 1: Noise canceler is enabled. 4 SSI4NCE 0 R/W Serial Sound Interface Channel 4 Noise Canceler Enable Enables or disables the noise canceler of SSISCK4, SSIWS4, and SSIDATA4. 0: Noise canceler is disabled. 1: Noise canceler is enabled. 3 SSI3NCE 0 R/W Serial Sound Interface Channel 3 Noise Canceler Enable Enables or disables the noise canceler of SSISCK3, SSIWS3, and SSIDATA3. 0: Noise canceler is disabled. 1: Noise canceler is enabled. Page 2672 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 48 General Purpose I/O Ports Bit Bit Name Initial Value R/W Description 2 SSI2NCE 0 R/W Serial Sound Interface Channel 2 Noise Canceler Enable Enables or disables the noise canceler of SSISCK2, SSIWS2, and SSIDATA2. 0: Noise canceler is disabled. 1: Noise canceler is enabled. 1 SSI1NCE 0 R/W Serial Sound Interface Channel 1 Noise Canceler Enable Enables or disables the noise canceler of SSISCK1, SSIWS1, and SSIDATA1. 0: Noise canceler is disabled. 1: Noise canceler is enabled. 0 SSI0NCE 0 R/W Serial Sound Interface Channel 0 Noise Canceler Enable Enables or disables the noise canceler of SSISCK0, SSIWS0, and SSIRxD0. 0: Noise canceler is disabled. 1: Noise canceler is enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2673 of 3092 Section 48 General Purpose I/O Ports Page 2674 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Section 49 Power-Down Modes This LSI supports sleep mode, software standby mode, deep standby mode, and module standby mode. In power-down modes, functions of CPU, clocks, on-chip memory, or part of on-chip peripheral modules are halted or the power-supply is turned off, through which low power consumption is achieved. These modes are canceled by a reset or interrupt. 49.1 Features 49.1.1 Power-Down Modes This LSI has the following power-down modes and function: 1. 2. 3. 4. Sleep mode Software standby mode Deep standby mode Module standby function Table 49.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2675 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Table 49.1 States of Power-Down Modes State*1 HighSpeed On-Chip RAM Cache Memory PowerDown Mode Transition Conditions CPG Sleep Execute Running Halted mode SLEEP instruction with STBY bit CPU CPU Register Held Running LargeCapacity On-Chip RAM (including on-chip dataOn-Chip retention Peripheral Realtime RAM) Modules Clock Running Running Power Supply External Canceling Memory Procedure Running*2 Running Autorefresh in STBCR1 cleared to 0  Interrupt  Manual reset  Power-on reset  DMA address error Software Execute standby mode Halted Halted Held SLEEP instruction Execute standby mode SLEEP instruction with STBY and DEEP bits in STBCR1 set to 1 Halted Halted (contents (contents are are held*5*6) held*5*7) with STBY bit in STBCR1 set to 1 and DEEP bit to 0 Deep Halted 2 Running* Running Selfrefresh  NMI interrupt  IRQ interrupt  Power-on reset Halted Halted Halted Halted Halted (contents (contents are not in on-chip held) dataretention RAM are held*3) Halted Running*2 Halted Self-  NMI interrupt*4  Power-on refresh reset*4  Realtime clock alarm interrupt*4  Change on the pins for canceling* Page 2676 of 3092 4 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes State*1 HighSpeed On-Chip RAM Cache Memory PowerDown Mode Transition Conditions Module Set the MSTP Running Running Held CPG standby bits in mode STBCR2 to STBCR10 to 1 CPU CPU Register Running LargeCapacity On-Chip RAM (including on-chip dataOn-Chip retention Peripheral Realtime RAM) Modules Clock Running Specified module halted Halted Power Supply External Canceling Memory Procedure Running Autorefresh  Clear MSTP bit to 0  Power-on reset (only for the user debugging interface and direct memory access controller) Notes: 1. The pin state is retained or set to high impedance. For details, see section 53.1, Pin States in section 53, States and Handling of Pins. 2. The realtime clock operates when the START bit in the RCR2 register is set to 1. For details, see section 15, Realtime Clock. When deep standby mode is canceled by a power-on reset, the running state cannot be retained. Make the initial setting for the realtime clock again. 3. Setting the bits RRAMKP3 to RRAMKP0 in the RRAMKP register to 1 enables to retain the data in the corresponding area on the on-chip data-retention RAM during the transition to deep standby. When the deep standby is canceled by a power-on reset, the retained contents are initialized. 4. Deep standby mode can be canceled by an interrupt (NMI or realtime clock alarm interrupt), a power-on reset, or change on the pins for canceling (PJ23 to PJ20, PG3, PG2, PF19 to PF16, PC7, and PC5). Even when deep standby mode is canceled by a source other than a reset, power-on reset exception handling is executed instead of interrupt exception handling. PJ23 to PJ20 can be used only in the SH7269 Group. 5. When software standby mode is canceled by a power-on reset, the retained contents are initialized. 6. By setting the RAME bit in SYSCR1 or RAMWE bit in SYSCR2 to disable accesses, contents in the high-speed on-chip RAM can be retained even when software standby mode is canceled by a power-on reset. 7. By setting the VRAME bit in SYSCR3 or VRAMWE bit in SYSCR4 to disable accesses, contents in the large-capacity on-chip RAM (including on-chip data-retention RAM) can be retained even when software standby mode is canceled by a power-on reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2677 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2 Register Descriptions Table 49.2 shows the register configuration. Table 49.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Standby control register 1 STBCR1 R/W H'00 H'FFFE0014 8 Standby control register 2 STBCR2 R/W H'00 H'FFFE0018 8 Standby control register 3 STBCR3 R/W H'7E H'FFFE0408 8 Standby control register 4 STBCR4 R/W H'FF H'FFFE040C 8 Standby control register 5 STBCR5 R/W H'FF H'FFFE0410 8 Standby control register 6 STBCR6 R/W H'FF H'FFFE0414 8 Standby control register 7 STBCR7 R/W H'FF H'FFFE0418 8 Standby control register 8 STBCR8 R/W H'FF H'FFFE041C 8 Standby control register 9 STBCR9 R/W H'FF H'FFFE0440 8 Standby control register 10 STBCR10 R/W H'7F H'FFFE0444 8 Software reset control register 1 SWRSTCR1 R/W H'00 H'FFFE0430 8 Software reset control register 2 SWRSTCR2 R/W H'00 H'FFFE0434 8 System control register 1 SYSCR1 R/W H'FF H'FFFE0400 8 System control register 2 SYSCR2 R/W H'FF H'FFFE0404 8 System control register 3 SYSCR3 R/W H'FF H'FFFE0420 8 System control register 4 SYSCR4 R/W H'FF H'FFFE0424 8 System control register 5 SYSCR5 R/W H'00 H'FFFE0428 8 On-chip data-retention RAM area setting register RRAMKP R/W H'00 H'FFFE6800 8 Deep standby control register DSCTR R/W H'00 H'FFFE6802 8 Deep standby cancel source select register DSSSR R/W H'0000 H'FFFE6804 16 Deep standby cancel edge select register DSESR R/W H'0000 H'FFFE6806 16 Deep standby cancel source flag DSFR register R/W H'0000 H'FFFE6808 16 XTAL crystal oscillator gain control register R/W H'00 H'FFFE6810 8 Page 2678 of 3092 XTALCTR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 49.2.1 Section 49 Power-Down Modes Standby Control Register 1 (STBCR1) STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 5 4 3 2 1 STBY DEEP - - - - - 0 - Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 STBY 0 R/W Software Standby, Deep Standby 6 DEEP 0 R/W Specifies transition to software standby mode or deep standby mode. 0x: Executing SLEEP instruction puts chip into sleep mode. 10: Executing SLEEP instruction puts chip into software standby mode. 11: Executing SLEEP instruction puts chip into deep standby mode. 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. [Legend] x: Don't care R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2679 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 5 4 3 2 1 MSTP 10 MSTP 9 MSTP 8 MSTP 7 - - - - Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 MSTP10 0 R/W Module Stop 10 0 When the MSTP10 bit is set to 1, the clock supply to the user debugging interface is halted. 0: The user debugging interface runs. 1: Clock supply to the user debugging interface halted. 6 MSTP9 0 R/W Module Stop 9 When the MSTP9 bit is set to 1, the clock supply to the user break controller is halted. 0: The user break controller runs. 1: Clock supply to the user break controller halted. 5 MSTP8 0 R/W Module Stop 8 When the MSTP8 bit is set to 1, the clock supply to the direct memory access controller is halted. 0: The direct memory access controller runs. 1: Clock supply to the direct memory access controller halted. Note: Do not set this bit to 1 when using multifunction timer pulse unit 2, the compare-match timer, the serial communication interface with FIFO, the controller area network, the IEBus™ controller, the sound generator, or the motor control PWM timer. Page 2680 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 4 MSTP7 0 R/W Module Stop 7 When the MSTP7 bit is set to 1, the clock supply to the FPU is halted. After setting the MSTP7 bit to 1, the MSTP7 bit cannot be cleared by writing 0. This means that, after the clock supply to the FPU is halted by setting the MSTP7 bit to 1, the supply cannot be restarted by clearing the MSTP7 bit to 0. To restart the clock supply to the FPU after it was halted, reset the LSI by a power-on reset. 0: The FPU runs. 1: Clock supply to the FPU is halted. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 49.2.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 5 4 3 2 1 0 HIZ MSTP 36 MSTP 35 - - MSTP 32 - MSTP 30 1 R/W 1 R/W 1 R 1 R 1 R/W 1 R 0 R/W Initial value: 0 R/W: R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2681 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 7 HIZ 0 R/W Port High Impedance Selects whether the state of specific output pin is retained or high impedance in software standby mode or deep standby mode. As to which pins are controlled, see section 53.1, Pin States in section 53, States and Handling of Pins. This bit must not be set while the TME bit in WTSCR of the watchdog timer is 1. To set the output pin to high-impedance, set the HIZ bit to 1 only while the TME bit is 0. 0: The pin state is retained in software standby mode or deep standby mode. 1: The pin is set to high-impedance in software standby mode or deep standby mode. 6 MSTP36 1 R/W Module Stop 36 When the MSTP36 bit is set to 1, the clock supply to the IEBusTM controller is halted. 0: The IEBusTM controller runs. TM 1: Clock supply to the IEBus controller is halted. 5 MSTP35 1 R/W Module Stop 35 When the MSTP35 bit is set to 1, the clock supply to the multi-function timer pulse unit 2 is halted. 0: The multi-function timer pulse unit 2 runs. 1: Clock supply to the multi-function timer pulse unit 2 is halted. 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1. Page 2682 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 2 MSTP32 1 R/W Module Stop 32 When the MSTP32 bit is set to 1, the clock supply to the AD converter is halted. 0: The AD converter runs. 1: Clock supply to the AD converter is halted. 1  1 R Reserved This bit is always read as 1. The write value should always be 1. 0 MSTP30 0 R/W Module Stop 30 When the MSTP30 bit is set to 1, the clock supply to the realtime clock is halted. 0: The realtime clock runs. 1: Clock supply to the realtime clock is halted. Note: When the realtime clock is halted, set the bits in registers shown below.  Set bit RTCEN in the control register 2 (RCR2) to 0.  Set bits RCKSEL[1:0] in the control register 5 (RCR5) to 00. After the settings above, set bit MSTP30 to 1. 49.2.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 5 MSTP 47 MSTP 46 MSTP 45 MSTP MSTP 44 43 MSTP MSTP 42 41 MSTP 40 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Initial value: 1 R/W: R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 4 3 1 R/W 2 1 1 R/W 0 Page 2683 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 7 MSTP47 1 R/W Module Stop 47 When the MSTP47 bit is set to 1, the clock supply to channel 0 of the serial communication unit with FIFO is halted. 0: Channel 0 of the serial communication unit with FIFO runs. 1: Clock supply to channel 0 of the serial communication unit with FIFO is halted. 6 MSTP46 1 R/W Module Stop 46 When the MSTP46 bit is set to 1, the clock supply to channel 1 of the serial communication unit with FIFO is halted. 0: Channel 1 of the serial communication unit with FIFO runs. 1: Clock supply to channel 1 of the serial communication unit with FIFO is halted. 5 MSTP45 1 R/W Module Stop 45 When the MSTP45 bit is set to 1, the clock supply to channel 2 of the serial communication unit with FIFO is halted. 0: Channel 2 of the serial communication unit with FIFO runs. 1: Clock supply to channel 2 of the serial communication unit with FIFO is halted. 4 MSTP44 1 R/W Module Stop 44 When the MSTP44 bit is set to 1, the clock supply to channel 3 of the serial communication unit with FIFO is halted. 0: Channel 3 of the serial communication unit with FIFO runs. 1: Clock supply to channel 3 of the serial communication unit with FIFO is halted. Page 2684 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 MSTP43 1 R/W Module Stop 43 When the MSTP43 bit is set to 1, the clock supply to channel 4 of the serial communication unit with FIFO is halted. 0: Channel 4 of the serial communication unit with FIFO runs. 1: Clock supply to channel 4 of the serial communication unit with FIFO is halted. 2 MSTP42 1 R/W Module Stop 42 When the MSTP42 bit is set to 1, the clock supply to channel 5 of the serial communication unit with FIFO is halted. 0: Channel 5 of the serial communication unit with FIFO runs. 1: Clock supply to channel 5 of the serial communication unit with FIFO is halted. 1 MSTP41 1 R/W Module Stop 41 When the MSTP41 bit is set to 1, the clock supply to channel 6 of the serial communication unit with FIFO is halted. 0: Channel 6 of the serial communication unit with FIFO runs. 1: Clock supply to channel 6 of the serial communication unit with FIFO is halted. 0 MSTP40 1 R/W Module Stop 40 When the MSTP40 bit is set to 1, the clock supply to channel 7 of the serial communication unit with FIFO is halted. 0: Channel 7 of the serial communication unit with FIFO runs. 1: Clock supply to channel 7 of the serial communication unit with FIFO is halted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2685 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.5 Standby Control Register 5 (STBCR5) STBCR5 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 MSTP MSTP 57 56 Initial value: 1 R/W: R/W 1 R/W 5 4 3 2 MSTP 55 MSTP 54 MSTP 53 MSTP 52 MSTP MSTP 51 50 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 MSTP57 1 R/W Module Stop 57 1 0 1 R/W When the MSTP57 bit is set to 1, the clock supply to channel 0 of the I2C bus interface 3 is halted. 0: Channel 0 of the I2C bus interface 3 runs. 1: Clock supply to channel 0 of the I2C bus interface 3 is halted. 6 MSTP56 1 R/W Module Stop 56 When the MSTP56 bit is set to 1, the clock supply to channel 1 of the I2C bus interface 3 is halted. 2 0: Channel 1 of the I C bus interface 3 runs. 1: Clock supply to channel 1 of the I2C bus interface 3 is halted. 5 MSTP55 1 R/W Module Stop 55 When the MSTP55 bit is set to 1, the clock supply to channel 2 of the I2C bus interface 3 is halted. 2 0: Channel 2 of the I C bus interface 3 runs. 1: Clock supply to channel 2 of the I2C bus interface 3 is halted. 4 MSTP54 1 R/W Module Stop 54 When the MSTP54 bit is set to 1, the clock supply to channel 3 of the I2C bus interface 3 is halted. 2 0: Channel 3 of the I C bus interface 3 runs. 1: Clock supply to channel 3 of the I2C bus interface 3 is halted. Page 2686 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 MSTP53 1 R/W Module Stop 53 When the MSTP53 bit is set to 1, the clock supply to channel 0 of the controller area network is halted. 0: Channel 0 of the controller area network runs. 1: Clock supply to channel 0 of the controller area network is halted. 2 MSTP52 1 R/W Module Stop 52 When the MSTP52 bit is set to 1, the clock supply to channel 1 of the controller area network is halted. 0: Channel 1 of the controller area network runs. 1: Clock supply to channel 1 of the controller area network is halted. 1 MSTP51 1 R/W Module Stop 51 When the MSTP51 bit is set to 1, the clock supply to channel 0 of the Renesas serial peripheral interface is halted. 0: Channel 0 of the Renesas serial peripheral interface runs. 1: Clock supply to channel 0 of the Renesas serial peripheral interface is halted. 0 MSTP50 1 R/W Module Stop 50 When the MSTP50 bit is set to 1, the clock supply to channel 1 of the Renesas serial peripheral interface is halted. 0: Channel 1 of the Renesas serial peripheral interface runs. 1: Clock supply to channel 1 of the Renesas serial peripheral interface is halted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2687 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.6 Standby Control Register 6 (STBCR6) STBCR6 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 MSTP MSTP 67 66 Initial value: 1 R/W: R/W 1 R/W 5 4 3 2 MSTP 65 MSTP 64 MSTP 63 MSTP 62 MSTP MSTP 61 60 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 MSTP67 1 R/W Module Stop 67 1 0 1 R/W When the MSTP67 bit is set to 1, the clock supply to channel 0 of the serial sound interface is halted. 0: Channel 0 of the serial sound interface runs. 1: Clock supply to channel 0 of the serial sound interface is halted. 6 MSTP66 1 R/W Module Stop 66 When the MSTP66 bit is set to 1, the clock supply to channel 1 of the serial sound interface is halted. 0: Channel 1 of the serial sound interface runs. 1: Clock supply to channel 1 of the serial sound interface is halted. 5 MSTP65 1 R/W Module Stop 65 When the MSTP65 bit is set to 1, the clock supply to channel 2 of the serial sound interface is halted. 0: Channel 2 of the serial sound interface runs. 1: Clock supply to channel 2 of the serial sound interface is halted. 4 MSTP64 1 R/W Module Stop 64 When the MSTP64 bit is set to 1, the clock supply to channel 3 of the serial sound interface is halted. 0: Channel 3 of the serial sound interface runs. 1: Clock supply to channel 3 of the serial sound interface is halted. Page 2688 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 MSTP63 1 R/W Module Stop 63 When the MSTP63 bit is set to 1, the clock supply to the CD-ROM decoder is halted. 0: The CD-ROM decoder runs. 1: Clock supply to the CD-ROM decoder is halted. 2 MSTP62 1 R/W Module Stop 62 When the MSTP62 bit is set to 1, the clock supply to channel 0 of the sampling rate converter is halted. 0: Channel 0 of the sampling rate converter runs. 1: Clock supply to channel 0 of the sampling rate converter is halted. 1 MSTP61 1 R/W Module Stop 61 When the MSTP61 bit is set to 1, the clock supply to channel 1 of the sampling rate converter is halted. 0: Channel 1 of the sampling rate converter runs. 1: Clock supply to channel 1 of the sampling rate converter C is halted. 0 MSTP60 1 R/W Module Stop 60 When the MSTP60 bit is set to 1, the clock supply to the USB 2.0 host/function module is halted. 0: The USB 2.0 host/function module runs. 1: Clock supply to the USB 2.0 host/function module is halted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2689 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.7 Standby Control Register 7 (STBCR7) STBCR7 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 MSTP MSTP 77 76 Initial value: 1 R/W: R/W 1 R/W 5 4 3 2 1 0 MSTP 75 - MSTP 73 MSTP 72 - MSTP 70 1 R/W 1 R 1 R/W 1 R/W 1 R 1 R/W Bit Bit Name Initial Value R/W Description 7 MSTP77 1 R/W Module Stop 77 When the MSTP77 bit is set to 1, the clock supply to the clocked synchronous serial I/O with FIFO is halted. 0: The clocked synchronous serial I/O with FIFO runs. 1: Clock supply to the clocked synchronous serial I/O with FIFO is halted. 6 MSTP76 1 R/W Module Stop 76 When the MSTP76 bit is set to 1, the clock supply to the Renesas SPDIF interface is halted. 0: The Renesas SPDIF interface runs. 1: Clock supply to the Renesas SPDIF interface is halted. 5 MSTP75 1 R/W Module Stop 75 When the MSTP75 bit is set to 1, the clock supply to the SPI multi I/O bus controller is halted. 0: The SPI multi I/O bus controller runs. 1: Clock supply to the SPI multi I/O bus controller is halted. 4  1 R Reserved This bit is always read as 1. The write value should always be 1. Page 2690 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 MSTP73 1 R/W Module Stop 73 When the MSTP73 bit is set to 1, the clock supply to the video display controller 4 is halted. 0: The video display controller 4 runs. 1: Clock supply to the video display controller 4 is halted. 2 MSTP72 1 R/W Module Stop 72 When the MSTP72 bit is set to 1, the clock supply to the compare match timer is halted. 0: The compare match timer runs. 1: Clock supply to the compare match timer is halted. 1  1 R Reserved This bit is always read as 1. The write value should always be 1. 0 MSTP70 1 R/W Module Stop 70 When the MSTP70 bit is set to 1, the clock supply to the NAND flash memory controller is halted. 0: The NAND flash memory controller runs. 1: Clock supply to the NAND flash memory controller is halted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2691 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.8 Standby Control Register 8 (STBCR8) STBCR8 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 MSTP MSTP 87 86 Initial value: 1 R/W: R/W 1 R/W 5 4 3 2 1 MSTP 85 MSTP 84 - MSTP 82 MSTP 81 - 1 R/W 1 R/W 1 R 1 R/W 1 R/W 1 R Bit Bit Name Initial Value R/W Description 7 MSTP87 1 R/W Module Stop 87 0 When the MSTP87 bit is set to 1, the clock supply to the motor control PWM timer is halted. 0: The motor control PWM timer runs. 1: Clock supply to the motor control PWM timer is halted. 6 MSTP86 1 R/W Module Stop 86 When the MSTP86 bit is set to 1, the clock supply to the MMC host interface is halted. 0: The MMC host interface runs. 1: Clock supply to the MMC host interface is halted. 5 MSTP85 1 R/W Module Stop 85 When the MSTP85 bit is set to 1, the clock supply to the image renderer is halted. 0: The image renderer runs. 1: Clock supply to the image renderer is halted. 4 MSTP84 1 R/W Module Stop 84 When the MSTP84 bit is set to 1, the clock supply to the OpenVG-compliant Renesas graphics processor is halted. 0: The OpenVG-compliant Renesas graphics processor runs. 1: Clock supply to the OpenVG-compliant Renesas graphics processor is halted. Page 2692 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3  1 R Reserved This bit is always read as 1. The write value should always be 1. 2 MSTP82 1 R/W Module Stop 82 When the MSTP82 bit is set to 1, the clock supply to channel 0 of the Renesas quad serial peripheral interface is halted. 0: Channel 0 of the Renesas quad serial peripheral interface runs. 1: Clock supply to channel 0 of the Renesas quad serial peripheral interface is halted. 1 MSTP81 1 R/W Module Stop 81 When the MSTP81 bit is set to 1, the clock supply to channel 1 of the Renesas quad serial peripheral interface is halted. 0: Channel 1 of the Renesas quad serial peripheral interface runs. 1: Clock supply to channel 1 of the Renesas quad serial peripheral interface is halted. 0  1 R Reserved This bit is always read as 1. The write value should always be 1. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2693 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.9 Standby Control Register 9 (STBCR9) STBCR9 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 MSTP MSTP 97 96 Initial value: 1 R/W: R/W 1 R/W 5 4 1 0 MSTP 95 MSTP 94 MSTP MSTP 93 92 3 MSTP 91 MSTP 90 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 MSTP97 1 R/W Module Stop 97 2 1 R/W When the MSTP97 bit is set to 1, the clock supply to the SD host interface 00 is halted. 0: The SD host interface 00 runs. 1: Clock supply to the SD host interface 00 is halted. 6 MSTP96 1 R/W Module Stop 96 When the MSTP96 bit is set to 1, the clock supply to the SD host interface 01 is halted. 0: The SD host interface 01 runs. 1: Clock supply to the SD host interface 01 is halted. 5 MSTP95 1 R/W Module Stop 95 When the MSTP95 bit is set to 1, the clock supply to the SD host interface 10 is halted. 0: The SD host interface 10 runs. 1: Clock supply to the SD host interface 10 is halted. 4 MSTP94 1 R/W Module Stop 94 When the MSTP94 bit is set to 1, the clock supply to the SD host interface 11 is halted. 0: The SD host interface 11 runs. 1: Clock supply to the SD host interface 11 is halted. Page 2694 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 MSTP93 1 R/W Module Stop 93 When the MSTP93 bit is set to 1, the clock supply to channel 4 of the serial sound interface is halted. 0: Channel 4 of the serial sound interface runs. 1: Clock supply to channel 4 of the serial sound interface is halted. 2 MSTP92 1 R/W Module Stop 92 When the MSTP92 bit is set to 1, the clock supply to channel 5 of the serial sound interface is halted. 0: Channel 5 of the serial sound interface runs. 1: Clock supply to channel 5 of the serial sound interface is halted. 1 MSTP91 1 R/W Module Stop 91 When the MSTP91 bit is set to 1, the clock supply to channel 2 of the sampling rate converter is halted. 0: Channel 2 of the sampling rate converter runs. 1: Clock supply to channel 2 of the sampling rate converter is halted. 0 MSTP90 1 R/W Module Stop 90 When the MSTP90 bit is set to 1, the clock supply to channel 2 of the controller area network is halted. 0: Channel 2 of the controller area network runs. 1: Clock supply to channel 2 of the controller area network is halted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2695 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.10 Standby Control Register 10 (STBCR10) STBCR10 is an 8-bit readable/writable register that controls the operation of each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 MSTP MSTP 107 106 Initial value: 0 R/W: R/W 1 R/W 5 4 MSTP 105 - MSTP MSTP 103 102 3 2 MSTP MSTP 101 100 1 R/W 1 R 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7 MSTP107 0 R/W Module Stop 107 1 0 1 R/W When the MSTP107 bit is set to 1, the clock supply to the digital video decoder is halted. 0: The digital video decoder runs. 1: Clock supply to the digital video decoder is halted. 6 MSTP106 1 R/W Module Stop 106 When the MSTP106 bit is set to 1, the clock supply to the JPEG codec unit is halted. 0: The JPEG codec unit runs. 1: Clock supply to the JPEG codec unit is halted. 5 MSTP105 1 R/W Module Stop 105 When the MSTP105 bit is set to 1, the clock supply to the display out comparison unit is halted. 0: The display out comparison unit runs. 1: Clock supply to the display out comparison unit is halted. 4  1 R Reserved This bit is always read as 1. The write value should always be 1. Page 2696 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 3 MSTP103 1 R/W Module Stop 103 When the MSTP103 bit is set to 1, the clock supply to channel 0 of the sound generator is halted. 0: Channel 0 of the sound generator runs. 1: Clock supply to channel 0 of the sound generator is halted. 2 MSTP102 1 R/W Module Stop 102 When the MSTP102 bit is set to 1, the clock supply to channel 1 of the sound generator is halted. 0: Channel 1 of the sound generator runs. 1: Clock supply to channel 1 of the sound generator is halted. 1 MSTP101 1 R/W Module Stop 101 When the MSTP101 bit is set to 1, the clock supply to channel 2 of the sound generator is halted. 0: Channel 2 of the sound generator runs. 1: Clock supply to channel 2 of the sound generator is halted. 0 MSTP100 1 R/W Module Stop 100 When the MSTP100 bit is set to 1, the clock supply to channel 3 of the sound generator is halted. 0: Channel 3 of the sound generator runs. 1: Clock supply to channel 3 of the sound generator is halted. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2697 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.11 Software Reset Control Register 1 (SWRSTCR1) SWRSTCR1 is an 8-bit readable/writable register that controls a software reset for the serial sound interface and IEBusTM controller and the operation of the crystal resonator for audio. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 AXT ALE Initial value: 0 R/W: R/W 4 3 2 SSIF5 SSIF4 SRST SRST 6 5 IEB SRST SSIF3 SRST SSIF2 SRST SSIF1 SSIF0 SRST SRST 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 Bit Bit Name Initial Value R/W Description 7 AXTALE 0 R/W AUDIO_X1 Clock Control 0 0 R/W Controls the function of AUDIO_X1 pin. 0: Runs the on-chip crystal oscillator/enables the external clock input. 1: Halts the on-chip crystal oscillator/disables the external clock input. 6 SSIF5SRST 0 R/W Serial Sound Interface Channel 5 Software Reset Controls the serial sound interface channel 5 reset with software. 0: The serial sound interface channel 5 reset is canceled. 1: The serial sound interface channel 5 is reset. 5 SSIF4SRST 0 R/W Serial Sound Interface Channel 4 Software Reset Controls the serial sound interface channel 4 reset with software. 0: The serial sound interface channel 4 reset is canceled. 1: The serial sound interface channel 4 is reset. 4 IEBSRST 0 R/W IEBusTM Controller Software Reset Controls the IEBusTM controller reset with software. 0: The IEBusTM controller reset is canceled. 1: The IEBusTM controller is reset. Page 2698 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Initial Value Bit Bit Name 3 SSIF3SRST 0 R/W Description R/W Serial Sound Interface Channel 3 Software Reset Controls the serial sound interface channel 3 reset with software. 0: The serial sound interface channel 3 reset is canceled. 1: The serial sound interface channel 3 is reset. 2 SSIF2SRST 0 R/W Serial Sound Interface Channel 2 Software Reset Controls the serial sound interface channel 2 reset with software. 0: The serial sound interface channel 2 reset is canceled. 1: The serial sound interface channel 2 is reset. 1 SSIF1SRST 0 R/W Serial Sound Interface Channel 1 Software Reset Controls the serial sound interface channel 1 reset with software. 0: The serial sound interface channel 1 reset is canceled. 1: The serial sound interface channel 1 is reset. 0 SSIF0SRST 0 R/W Serial Sound Interface Channel 0 Software Reset Controls the serial sound interface channel 0 reset with software. 0: The serial sound interface channel 0 reset is canceled. 1: The serial sound interface channel 0 is reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2699 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.12 Software Reset Control Register 2 (SWRSTCR2) SWRSTCR2 is an 8-bit readable/writable register that controls a software reset for each module. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - JCU SRST RGPV GSRST - - VDC4 SRST 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 JCUSRST 0 R/W JPEG Codec Unit Software Reset Controls the JPEG codec unit reset with software. 0: The JPEG codec unit reset is canceled. 1: The JPEG codec unit is reset. 3 RGPVGSRST 0 R/W OpenVG-Compliant Renesas Graphics Processor Software Reset Controls the OpenVG-compliant Renesas graphics processor reset with software. 0: The OpenVG-compliant Renesas graphics processor reset is canceled. 1: The OpenVG-compliant Renesas graphics processor is reset. 2, 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 VDC4SRST 0 R/W Video Display Controller 4 Software Reset Controls the Video display controller 4 reset with software. 0: The Video display controller 4 reset is canceled. 1: The Video display controller 4 is reset. Page 2700 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.13 System Control Register 1 (SYSCR1) SYSCR1 is an 8-bit readable/writable register that enables or disables access (read and write) to a specified page in the high-speed on-chip RAM. When an RAMEn (n = 0 to 3) bit is set to 1, access to page n is enabled. When an RAMEn bit is cleared to 0, page n cannot be accessed. In this case, an undefined value is returned when reading data or fetching an instruction from page n, and writing to page n is ignored. The initial value of an RAMEn bit is 1. Note that when clearing the RAMEn bit to 0, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAMEn bit. If such an instruction is not executed, the data last written to page n may not be written to the high-speed onchip RAM. SYSCR1 should be set with a program located in an area other than the high-speed on-chip RAM. Furthermore, an instruction to read SYSCR1 should be located immediately after the instruction to write to SYSCR1. If not, normal access is not guaranteed. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: 7 6 5 4 - - - - 1 R 1 R 1 R 1 R 3 2 1 0 RAME3 RAME2 RAME1 RAME0 1 R/W Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved 1 R/W 1 R/W 1 R/W These bits are always read as 1. The write value should always be 1. 3 RAME3 1 R/W RAM Enable 3 (corresponding area: page 3* in highspeed on-chip RAM) 0: Access to page 3 is disabled. 1: Access to page 3 is enabled. 2 RAME2 1 R/W RAM Enable 2 (corresponding area: page 2* in highspeed on-chip RAM) 0: Access to page 2 is disabled. 1: Access to page 2 is enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2701 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 1 RAME1 1 R/W RAM Enable 1 (corresponding area: page 1* in highspeed on-chip RAM) 0: Access to page 1 is disabled. 1: Access to page 1 is enabled. 0 RAME0 1 R/W RAM Enable 0 (corresponding area: page 0* in highspeed on-chip RAM) 0: Access to page 0 is disabled. 1: Access to page 0 is enabled. Note: * For addresses in each page, see section 47, On-Chip RAM. 49.2.14 System Control Register 2 (SYSCR2) SYSCR2 is an 8-bit readable/writable register that enables or disables writing to a specified page in the high-speed on-chip RAM. When an RAMWEn (n = 0 to 3) bit is set to 1, writing to page n is enabled. When an RAMWEn bit is cleared to 0,writing to page n is ignored. The initial value of an RAMWEn bit is 1. Note that when clearing the RAMWEn bit to 0, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAMWEn bit. If such an instruction is not executed, the data last written to page n may not be written to the high-speed onchip RAM. SYSCR2 should be set with a program located in an area other than the high-speed on-chip RAM. Furthermore, an instruction to read SYSCR2 should be located immediately after the instruction to write to SYSCR2. If not, normal access is not guaranteed. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: Page 2702 of 3092 7 6 5 4 3 2 1 0 - - - - RAM WE3 RAM WE2 RAM WE1 RAM WE0 1 R 1 R 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 7 to 4  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 3 RAMWE3 1 R/W RAM Write Enable 3 (corresponding area: page 3* in high-speed on-chip RAM) 0: Writing to page 3 is disabled. 1 Writing to page 3 is enabled. 2 RAMWE2 1 R/W RAM Write Enable 2 (corresponding area: page 2* in high-speed on-chip RAM) 0: Writing to page 2 is disabled. 1: Writing to page 2 is enabled. 1 RAMWE1 1 R/W RAM Write Enable 1 (corresponding area: page 1* in high-speed on-chip RAM) 0: Writing to page 1 is disabled. 1: Writing to page 1 is enabled. 0 RAMWE0 1 R/W RAM Write Enable 0 (corresponding area: page 0* in high-speed on-chip RAM) 0: Writing to page 0 is disabled. 1: Writing to page 0 is enabled. Note: * For addresses in each page, see section 47, On-Chip RAM. 49.2.15 System Control Register 3 (SYSCR3) SYSCR3 is an 8-bit readable/writable register that enables or disables access (read and write) to a specified page in the large-capacity on-chip RAM. When a VRAMEn (n = 0 to 5) bit is set to 1, access to page n is enabled. When a VRAMEn bit is cleared to 0, page n cannot be accessed. In this case, an undefined value is returned when reading data or fetching an instruction from page n, and writing to page n is ignored. The initial value of a VRAMEn bit is 1. SYSCR3 should be set with a program located in an area other than the large-capacity on-chip RAM. Furthermore, an instruction to read SYSCR3 should be located immediately after the instruction to write to SYSCR3. If not, normal access is not guaranteed. Note: When writing to this register, see section 49.4, Usage Notes. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2703 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - VRA ME5 VRA ME4 VRA ME3 VRA ME2 VRA ME1 VRA ME0 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 VRAME5 1 R/W RAM Enable 5 (corresponding area: page 5* in largecapacity on-chip RAM) 0: Access to page 5 is disabled. 1: Access to page 5 is enabled. 4 VRAME4 1 R/W RAM Enable 4 (corresponding area: page 4* in largecapacity on-chip RAM) 0: Access to page 4 is disabled. 1: Access to page 4 is enabled. 3 VRAME3 1 R/W RAM Enable 3 (corresponding area: page 3* in largecapacity on-chip RAM) 0: Access to page 3 is disabled. 1: Access to page 3 is enabled. 2 VRAME2 1 R/W RAM Enable 2 (corresponding area: page 2* in largecapacity on-chip RAM 0: Access to page 2 is disabled. 1: Access to page 2 is enabled. 1 VRAME1 1 R/W RAM Enable 1 (corresponding area: page 1* in largecapacity on-chip RAM 0: Access to page 1 is disabled. 1: Access to page 1 is enabled. 0 VRAME0 1 R/W RAM Enable 0 (corresponding area: page 0* in largecapacity on-chip RAM) 0: Access to page 0 is disabled. 1: Access to page 0 is enabled. Note: * For addresses in each page, see section 47, On-Chip RAM. Page 2704 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.16 System Control Register 4 (SYSCR4) SYSCR4 is an 8-bit readable/writable register that enables or disables writing to a specified page in the large-capacity on-chip RAM. When a VRAMWEn (n = 0 to 5) bit is set to 1, writing to page n is enabled. When a VRAMWEn bit is cleared to 0, writing to page n is ignored. The initial value of a VRAMWEn bit is 1. SYSCR4 should be set with a program located in an area other than the large-capacity on-chip RAM. Furthermore, an instruction to read SYSCR4 should be located immediately after the instruction to write to SYSCR4. If not, normal access is not guaranteed. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: 7 6 - - 1 R 1 R 5 4 3 2 1 0 VRAM VRAM VRAM VRAM VRAM VRAM WE5 WE4 WE3 WE2 WE1 WE0 1 R/W 1 R/W 1 R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved 1 R/W 1 R/W 1 R/W These bits are always read as 1. The write value should always be 1. 5 VRAMWE5 1 R/W RAM Write Enable 5 (corresponding area: page 5* in large-capacity on-chip RAM) 0: Writing to page 5 is disabled. 1: Writing to page 5 is enabled. 4 VRAMWE4 1 R/W RAM Write Enable 4 (corresponding area: page 4* in large-capacity on-chip RAM) 0: Writing to page 4 is disabled. 1: Writing to page 4 is enabled. 3 VRAMWE3 1 R/W RAM Write Enable 3 (corresponding area: page 3* in large-capacity on-chip RAM) 0: Writing to page 3 is disabled. 1: Writing to page 3 is enabled. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2705 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 2 VRAMWE2 1 R/W RAM Write Enable 2 (corresponding area: page 2* in large-capacity on-chip RAM 0: Writing to page 2 is disabled. 1: Writing to page 2 is enabled. 1 VRAMWE1 1 R/W RAM Write Enable 1 (corresponding area: page 1* in large-capacity on-chip RAM 0: Writing to page 1 is disabled. 1: Writing to page 1 is enabled. 0 VRAMWE0 1 R/W RAM Write Enable 0 (corresponding area: page 0* in large-capacity on-chip RAM) 0: Writing to page 0 is disabled. 1: Writing to page 0 is enabled. Note: * For addresses in each page, see section 47, On-Chip RAM. 49.2.17 System Control Register 5 (SYSCR5) SYSCR5 is an 8-bit readable/writable register that enables or disables writing to a specified page in the on-chip data-retention RAM. When a RRAMWEn (n = 0 to 3) bit in SYSCR5 is set to 1, writing to page n is enabled. When a RRAMWEn bit is cleared to 0, writing to page n is ignored. The initial value of a RRAMWEn bit is 0. SYSCR5 should be set with a program located in an area other than the on-chip data-retention RAM. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: Page 2706 of 3092 7 6 5 4 - - - - 0 R 0 R 0 R 0 R 3 2 1 0 RRAM RRAM RRAM RRAM WE3 WE2 WE1 WE0 0 R/W 0 R/W 0 R/W 0 R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 RRAMWE3 0 R/W RAM Write Enable 3 (corresponding area: page 3*2 in on-chip data-retention RAM) 0: Writing to page 3 is disabled. 1: Writing to page 3 is enabled. 2 RRAMWE2 0 R/W RAM Write Enable 2 (corresponding area: page 2*2 in on-chip data-retention RAM 0: Writing to page 2 is disabled. 1: Writing to page 2 is enabled. 1 RRAMWE1 0 R/W RAM Write Enable 1 (corresponding area: page 1*2 in on-chip data-retention RAM 0: Writing to page 1 is disabled. 1: Writing to page 1 is enabled. 0 RRAMWE0 0 R/W RAM Write Enable 0 (corresponding area: page 0*2 in on-chip data-retention RAM) 0: Writing to page 0 is disabled. 1: Writing to page 0 is enabled. Notes: 1. For addresses in each page, see section 47, On-Chip RAM. 2. When the VRAME0 bit in SYSCR3 is cleared to 0 (access to page 0 in large-capacity on-chip RAM is invalid), the on-chip data-retention RAM cannot be accessed (read and written), regardless of the setting of this bit. When the VRAMWE0 bit in SYSCR4 is cleared to 0 (writing to page 0 in large-capacity on-chip RAM is invalid), the on-chip data-retention RAM cannot be written, regardless of the setting of this bit. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2707 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.18 On-Chip Data-Retention RAM Area Setting Register (RRAMKP) RRAMKP is an 8-bit readable/writable register that selects whether the contents of the corresponding area of the on-chip data-retention RAM are retained or not in deep standby mode. When the RRAMKP3 to RRAMKP0 bits are set to 1, the contents of the corresponding area of the on-chip data-retention RAM are retained in deep standby mode. When these bits are cleared to 0, the contents of the corresponding area of the on-chip data-retention RAM are not retained in deep standby mode. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: 7 6 5 4 - - - - 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W 7 to 4  All 0 R 3 2 1 0 RRAM RRAM RRAM RRAM KP3 KP2 KP1 KP0 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved These bits are always read as 0. The write value should always be 0. 3 RRAMKP3 0 R/W On-Chip Data-Retention RAM Storage Area 3 (corresponding area: page 3* in on-chip dataretention RAM) 0: The contents of the on-chip data-retention RAM are not retained in deep standby mode. 1: The contents of the on-chip data-retention RAM are retained in deep standby mode. 2 RRAMKP2 0 R/W On-Chip Data-Retention RAM Storage Area 2 (corresponding area: page 2* in on-chip dataretention RAM) 0: The contents of the on-chip data-retention RAM are not retained in deep standby mode. 1: The contents of the on-chip data-retention RAM are retained in deep standby mode. Page 2708 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 1 RRAMKP1 0 R/W On-Chip Data-Retention RAM Storage Area 1 (corresponding area: page 1* in on-chip dataretention RAM) 0: The contents of the on-chip data-retention RAM are not retained in deep standby mode. 1: The contents of the on-chip data-retention RAM are retained in deep standby mode. 0 RRAMKP0 0 R/W On-Chip Data-Retention RAM Storage Area 0 (corresponding area: page 0* in on-chip dataretention RAM) 0: The contents of the on-chip data-retention RAM are not retained in deep standby mode. 1: The contents of the on-chip data-retention RAM are retained in deep standby mode. Note: * For addresses in each page, see section 47, On-Chip RAM. 49.2.19 Deep Standby Control Register (DSCTR) DSCTR is an 8-bit readable/writable register that selects whether the states of the external memory control pins are retained or not when returning from deep standby mode and specifies the method to start the LSI. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 7 6 EBUS RAM KEEPE BOOT Initial value: 0 R/W: R/W R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0 R/W 5 4 3 2 1 - - - - - 0 - 0 R 0 R 0 R 0 R 0 R 0 R Page 2709 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Initial Value Bit Bit Name 7 EBUSKEEPE 0 R/W Description R/W Retention of External Memory Control Pin State 0: The state of the external memory control pins is not retained when returning from deep standby mode. 1: The state of the external memory control pins is retained when returning from deep standby mode. 6 RAMBOOT 0 R/W Selection of Method after Returning from Deep Standby Mode Selects an activation method after returning from deep standby mode. 0: Activated according to the boot mode specified for a reset. 1: The program is read from the on-chip dataretention RAM. Program counter (PC): H'1C000000 Stack pointer (SP): H'1C000004 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 2710 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.20 Deep Standby Cancel Source Select Register (DSSSR) DSSSR is a 16-bit readable/writable register that consists of the bits for selecting a source to cancel deep standby mode. The realtime clock alarm interrupt or change on the pins for canceling (PJ23 to PJ20, PG3, PG2, PF19 to PF16, PC7, and PC5) can be selected as a cancel source. The pins for canceling can be used for canceling deep standby, regardless of pin function settings in the general I/O port. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 15 14 13 12 11 10 9 8 7 - PJ23 PJ22 PJ21 PJ20 PG3 PG2 NMI - Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W 15  0 R 6 5 RTCAR PF19 0 R/W 0 R/W 4 3 2 1 0 PF18 PF17 PF16 PC7 PC5 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description Reserved This bit is always read as 0. The write value should always be 0. 14 PJ23 0 R/W Cancel by Change on PJ23 0: Deep standby mode is not canceled by change on the PJ23 pin. 1: Deep standby mode is canceled by change on the PJ23 pin. Note: This bit can be used only in the SH7269 Group. 13 PJ22 0 R/W Cancel by Change on PJ22 0: Deep standby mode is not canceled by change on the PJ22 pin. 1: Deep standby mode is canceled by change on the PJ22 pin. Note: This bit can be used only in the SH7269 Group. 12 PJ21 0 R/W Cancel by Change on PJ21 0: Deep standby mode is not canceled by change on the PJ21 pin. 1: Deep standby mode is canceled by change on the PJ21 pin. Note: This bit can be used only in the SH7269 Group. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2711 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 11 PJ20 0 R/W Cancel by Change on PJ20 0: Deep standby mode is not canceled by change on the PJ20 pin. 1: Deep standby mode is canceled by change on the PJ20 pin. Note: This bit can be used only in the SH7269 Group. 10 PG3 0 R/W Cancel by Change on PG3 0: Deep standby mode is not canceled by change on the PG3 pin. 1: Deep standby mode is canceled by change on the PG3 pin. 9 PG2 0 R/W Cancel by Change on PG2 0: Deep standby mode is not canceled by change on the PG2 pin. 1: Deep standby mode is canceled by change on the PG2 pin. 8 NMI 0 R/W Cancel by Change on NMI 0: Deep standby mode is not canceled by change on the NMI pin. 1: Deep standby mode is canceled by change on the NMI pin. 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 RTCAR 0 R/W Cancel by Realtime Clock Alarm Interrupt 0: Deep standby mode is not canceled by a realtime clock alarm interrupt. 1: Deep standby mode is canceled by a realtime clock alarm interrupt. 5 PF19 0 R/W Cancel by Change on PF19 0: Deep standby mode is not canceled by change on the PF19 pin. 1: Deep standby mode is canceled by change on the PF19 pin. Page 2712 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 4 PF18 0 R/W Cancel by Change on PF18 0: Deep standby mode is not canceled by change on the PF18 pin. 1: Deep standby mode is canceled by change on the PF18 pin. 3 PF17 0 R/W Cancel by Change on PF17 0: Deep standby mode is not canceled by change on the PF17 pin. 1: Deep standby mode is canceled by change on the PF17 pin. 2 PF16 0 R/W Cancel by Change on PF16 0: Deep standby mode is not canceled by change on the PF16 pin. 1: Deep standby mode is canceled by change on the PF16 pin. 1 PC7 0 R/W Cancel by Change on PC7 0: Deep standby mode is not canceled by change on the PC7 pin. 1: Deep standby mode is canceled by change on the PC7 pin. 0 PC5 0 R/W Cancel by Change on PC5 0: Deep standby mode is not canceled by change on the PC5 pin. 1: Deep standby mode is canceled by change on the PC5 pin. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2713 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.21 Deep Standby Cancel Edge Select Register (DSESR) DSESR is a 16-bit readable/writable register that consists of the bits for selecting an edge to be detected for the pin specified as a deep standby cancel source with DSSSR. This register setting is always valid for canceling deep standby, regardless of the interrupt controller setting. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 15 - 14 13 12 11 PJ23E PJ22E PJ21E PJ20E Initial value: 0 R/W: R 0 R/W 0 R/W 0 R/W 0 R/W 10 9 8 7 6 PG3E PG2E NMIE - - 0 R/W 0 R/W 0 R/W 0 R 0 R Bit Bit Name Initial Value R/W Description 15  0 R Reserved 5 4 3 2 PF19E PF18E PF17E PF16E 0 R/W 0 R/W 0 R/W 0 R/W 1 0 PC7E PC5E 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 PJ23E 0 R/W PJ23 Edge Detection 0: Falling edge of PJ23 is detected. 1: Rising edge of PJ23 is detected. Note: This bit can be used only in the SH7269 Group. 13 PJ22E 0 R/W PJ22 Edge Detection 0: Falling edge of PJ22 is detected. 1: Rising edge of PJ22 is detected. Note: This bit can be used only in the SH7269 Group. 12 PJ21E 0 R/W PJ21 Edge Detection 0: Falling edge of PJ21 is detected. 1: Rising edge of PJ21 is detected. Note: This bit can be used only in the SH7269 Group. 11 PJ20E 0 R/W PJ20 Edge Detection 0: Falling edge of PJ20 is detected. 1: Rising edge of PJ20 is detected. Note: This bit can be used only in the SH7269 Group. Page 2714 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W Description 10 PG3E 0 R/W PG3 Edge Detection 0: Falling edge of PG3 is detected. 1: Rising edge of PG3 is detected. 9 PG2E 0 R/W PG2 Edge Detection 0: Falling edge of PG2 is detected. 1: Rising edge of PG2 is detected. 8 NMIE 0 R/W NMI Edge Detection 0: Falling edge of NMI is detected. 1: Rising edge of NMI is detected. 7, 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 PF19E 0 R/W PF19 Edge Detection 0: Falling edge of PF19 is detected. 1: Rising edge of PF19 is detected. 4 PF18E 0 R/W PF18 Edge Detection 0: Falling edge of PF18 is detected. 1: Rising edge of PF18 is detected. 3 PF17E 0 R/W PF17 Edge Detection 0: Falling edge of PF17 is detected. 1: Rising edge of PF17 is detected. 2 PF16E 0 R/W PF16 Edge Detection 0: Falling edge of PF16 is detected. 1: Rising edge of PF16 is detected. 1 PC7E 0 R/W PC7 Edge Detection 0: Falling edge of PC7 is detected. 1: Rising edge of PC7 is detected. 0 PC5E 0 R/W PC5 Edge Detection 0: Falling edge of PC5 is detected. 1: Rising edge of PC5 is detected. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2715 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.22 Deep Standby Cancel Source Flag Register (DSFR) DSFR is a 16-bit readable/writable register composed of two types of bits. One is the flag that confirms which source canceled deep standby mode. The other is the bit that releases the state of pins after canceling deep standby mode. When deep standby mode is canceled by an interrupt (NMI, realtime clock alarm interrupt, or change on the pins for canceling) and changes on the pins for canceling, this register retains the previous data although power-on reset exception handling is executed. When deep standby mode is canceled by a power-on reset, this register is initialized to H'0000. All flags must be cleared immediately before transition to deep standby mode. Note: When writing to this register, see section 49.4, Usage Notes. Bit: 15 IO KEEP 14 13 12 11 PJ23F PJ22F PJ21F PJ20F 10 9 8 7 6 PG3F PG2F NMIF - RTC ARF Initial value: 0 0 0 0 0 0 0 0 R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 0 R 5 4 3 2 PF19F PF18F PF17F PF16F 1 0 PC7F PC5F 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written after reading 1 to clear the flag. Bit Bit Name Initial Value R/W 15 IOKEEP 0 R/(W)* Release of Pin State Retention Description Releases the retention of the pin state after canceling deep standby mode 0: Pin state not retained [Clearing condition]  Writing 0 after reading 1 1: Pin state retained [Setting condition]  14 PJ23F 0 When deep standby mode is entered R/(W)* PJ23 Flag 0: No change on the PJ23 pin 1: Change on the PJ23 pin Note: This bit can be used only in the SH7269 Group. Page 2716 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W 13 PJ22F 0 R/(W)* PJ22 Flag Description 0: No change on the PJ22 pin 1: Change on the PJ22 pin Note: This bit can be used only in the SH7269 Group. 12 PJ21F 0 R/(W)* PJ21 Flag 0: No change on the PJ21 pin 1: Change on the PJ21 pin Note: This bit can be used only in the SH7269 Group. 11 PJ20F 0 R/(W)* PJ20 Flag 0: No change on the PJ20 pin 1: Change on the PJ20 pin Note: This bit can be used only in the SH7269 Group. 10 PG3F 0 R/(W)* PG3 Flag 0: No change on the PG3 pin 1: Change on the PG3 pin 9 PG2F 0 R/(W)* PG2 Flag 0: No change on the PG2 pin 1: Change on the PG2 pin 8 NMIF 0 R/(W)* NMI Flag 0: No interrupt on NMI pin 1: Interrupt on NMI pin 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 RTCARF 0 R/(W)* RTCAR Flag 0: No realtime clock alarm interrupt generated 1: Realtime clock alarm Interrupt generated 5 PF19F 0 R/(W)* PF19 Flag 0: No change on the PF19 pin 1: Change on the PF19 pin R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2717 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Bit Bit Name Initial Value R/W 4 PF18F 0 R/(W)* PF18 Flag Description 0: No change on the PF18 pin 1: Change on the PF18 pin 3 PF17F 0 R/(W)* PF17 Flag 0: No change on the PF17 pin 1: Change on the PF17 pin 2 PF16F 0 R/(W)* PF16 Flag 0: No change on the PF16 pin 1: Change on the PF16 pin 1 PC7F 0 R/(W)* PC7 Flag 0: No change on the PC7 pin 1: Change on the PC7 pin 0 PC5F 0 R/(W)* PC5 Flag 0: No change on the PC5 pin 1: Change on the PC5 pin Note: * Only 0 can be written after reading 1 to clear the flag. Page 2718 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.2.23 XTAL Crystal Oscillator Gain Control Register (XTALCTR) XTALCTR is an 8-bit readable/writable register that controls the gain of the crystal oscillator for XTAL. If the realtime clock uses the XTAL input, XTALCTR retains the previous value when software standby mode or deep standby mode is canceled by a source other than a power-on reset. If the realtime clock does not use the XTAL input, XTALCTR is initialized to H'00 when software standby or deep standby mode is entered. XTALCTR is also initialized to H'00 when software standby or deep standby mode is canceled by a power-on reset. Note: When writing to this register, see section 49.4, Usage Notes. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - GAIN 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 GAIN 0 R/W XTAL Crystal Oscillator Gain Select 0: Large gain 1: Small gain R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2719 of 3092 Section 49 Power-Down Modes 49.3 Operation 49.3.1 Sleep Mode (1) SH7268 Group, SH7269 Group Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run in sleep mode. The clock output from the CKIO pin is continued. (2) Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), a DMA address error, or a reset (manual reset or power-on reset).  Canceling by an interrupt When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the priority level of the generated interrupt is equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU, or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt request is not accepted and sleep mode is not canceled.  Canceling by a DMA address error When a DMA address error occurs, sleep mode is canceled and DMA address error exception handling is executed.  Canceling by a reset Sleep mode is canceled by a power-on reset or a manual reset. Page 2720 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 49.3.2 (1) Section 49 Power-Down Modes Software Standby Mode Transition to Software Standby Mode The LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit and DEEP bit in STBCR1 are 1 and 0 respectively. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also stops. The contents of the CPU and cache registers remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. As for the states of on-chip peripheral module registers in software standby mode, see section 51.3, Register States in Each Operating Mode. The CPU takes one cycle to finish writing to STBCR1, and then executes processing for the next instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP instruction after reading STBCR1 to have the values written to STBCR1 by the CPU to be definitely reflected in the SLEEP instruction. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the timer control register of the watchdog timer (WTCSR) to 0 to stop the watchdog timer. 2. Set the timer counter (WTCNT) of the watchdog timer to 0 and the CKS[2:0] bits in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY and DEEP bits in STBCR1 to 1 and 0 respectively, read STBCR1. Then, execute a SLEEP instruction. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2721 of 3092 Section 49 Power-Down Modes (2) SH7268 Group, SH7269 Group Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (power-on reset). Clock signal starts to be output from the CKIO pin.  Canceling by an interrupt When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) of the interrupt controller) or the falling edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller) is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation settling counter (watchdog timer) used to count the oscillation settling time. After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer control/status register (WTCSR) of the watchdog timer before the transition to software standby mode, the watchdog timer overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in case of IRQ) is started. If the priority level of the generated interrupt is equal to or lower than the interrupt mask level specified in the status register (SR) of the CPU, the interrupt request is not accepted and software standby mode is not canceled. When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0] bits so that the watchdog timer overflow period will be equal to or longer than the oscillation settling time. The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until software standby mode is canceled.  Canceling by a reset When the RES pin is driven low, software standby mode is canceled and the LSI enters the power-on reset state. After that, if the RES pin is driven high, the power-on reset exception handling is started. Keep the RES pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin. Page 2722 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 49 Power-Down Modes Note on Release from Software Standby Mode Release from software standby mode is triggered by interrupts (NMI and IRQ) or resets (manual reset and power-on reset). If, however, a SLEEP instruction and an interrupt other than NMI and IRQ are generated at the same time, software standby mode may be canceled due to acceptance of the interrupt. When initiating a transition to software standby mode, make settings so that interrupts are not generated before execution of the SLEEP instruction. (4) Note on Canceling Software Standby Mode After software standby mode is canceled, unstable clock pulses are output from the CKIO pin during oscillation settling time. To prevent malfunction due to the unstable pulses, bits 13 and 12 in FRQCR should be modified. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2723 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes 49.3.3 Software Standby Mode Application Example This example describes a transition to software standby mode on the falling edge of the NMI signal, and cancellation on the rising edge of the NMI signal. The timing is shown in figure 49.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine, the STBY and DEEP bits in STBCR1 are set to 1 and 0 respectively, and a SLEEP instruction is executed, software standby mode is entered. Thereafter, software standby mode is canceled when the NMI pin is changed from low to high level. Oscillator CK NMI pin NMIE bit STBY bit LSI state Program execution NMI exception handling Exception service routine Software standby mode Oscillation settling time NMI exception handling Figure 49.1 NMI Timing in Software Standby Mode (Application Example) Page 2724 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 49.3.4 (1) Section 49 Power-Down Modes Deep Standby Mode Transition to Deep Standby Mode The LSI switches from a program execution state to deep standby mode by executing the SLEEP instruction when the STBY bit and DEEP bit in STBCR1 are set to 1. In deep standby mode, not only the CPU, clocks, and on-chip peripheral modules but also power supply is turned off excluding the on-chip data-retention RAM area specified by the RRAMKP3 to RRAMKP0 bits in RRAMKP and realtime clock. This can significantly reduce power consumption. Therefore, data in the registers of the CPU, cache, and on-chip peripheral modules are not retained. Pin state values immediately before the transition to deep standby mode are retained. The CPU takes one cycle to finish writing to DSFR, and then executes processing for the next instruction. However, it actually takes one or more cycles to write. Therefore, execute a SLEEP instruction after reading DSFR to reflect the values written to DSFR by the CPU in the SLEEP instruction without fail. The procedure for switching to deep standby mode is as follows. Figure 49.2 also shows its flowchart. 1. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip dataretention RAM area that must be retained. Transfer the programs to be retained to the specified areas of the on-chip data-retention RAM. 2. Set the RAMBOOT and EBUSKEEPE bits in DSCTR to specify the activation method for returning from deep standby mode and to select whether the external memory control pin status is retained or not. 3. When canceling deep standby mode by an interrupt, set the corresponding bit in DSSSR to select the pin or source to cancel deep standby mode. In this case, specify the input signal detection mode for the selected pin with the corresponding bit in DSESR. 4. Execute read and write of an arbitrary but the same address for each page in the on-chip dataretention RAM area. When this is not executed, data last written may not be written to the onchip data-retention RAM. If there is a write to the on-chip data-retention RAM after this time, execute this processing after the last write to the on-chip data-retention RAM. 5. Set the STBY and DEEP bits in STBCR1 to 1. 6. Read out the DSFR register after clearing the flag in the DSFR register. Then execute the SLEEP instruction. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2725 of 3092 SH7268 Group, SH7269 Group Section 49 Power-Down Modes Set the RRAMKP bit in RRAMKP as needed Transfer data that needs to be retained to the corresponding area Set the corresponding bit in DSCTR as needed Set the corresponding bit in DSSSR as needed Set the corresponding bit in DSESR as needed Set the realtime clock registers as needed Perform read/write to the same arbitrary address in each retention page of the on-chip data-retention RAM Set the STBY and DEEP bits in STBCR1 to 1 Read STBCR1 Read DSFR and clear the flags of DSFR Execute the SLEEP instruction Transition to deep standby mode Figure 49.2 Flowchart of Transition to Deep Standby Mode Page 2726 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (2) Section 49 Power-Down Modes Canceling Deep Standby Mode Deep standby mode is canceled by interrupts (NMI or realtime clock alarm interrupt), change on the pins for canceling, or a reset (power-on reset). The realtime clock alarm interrupt can always cancel deep standby mode regardless of the interrupt priority level or the settings of the status register (SR) in the CPU and of the alarm interrupt enable flag (RCR1.AIE). When canceling the mode by a source other than a reset, a power-on reset exception handling is executed instead of an interrupt exception handling. Figure 49.3 shows the flowchart of canceling deep standby mode. Deep standby mode Detect an interrupt (NMI or realtime clock alarm). Detect change on the pins for canceling. Detect RES The RES pin is held low during oscillation settling time Count oscillation settling time Power-on reset exception handling according to the boot mode specified for the reset No RAMBOOT=1? Yes Power-on reset exception handling Read PC from H'1C000000 Read SP from H'1C000004 Power-on reset exception handling according to the boot mode specified for the reset To the initialization routine Check the flags in DSFR Processing according to deep standby mode cancel source Reconfiguration of peripheral functions* Clear the IOKEEP bit in DSFR (Release the pin state retention) To the state before the transition to deep standby mode Note: * Peripheral functions include all functions such as the clock pulse generator, interrupt controller, bus state controller, general I/O ports, and peripheral modules. Figure 49.3 Flowchart of Canceling Deep Standby Mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2727 of 3092 Section 49 Power-Down Modes SH7268 Group, SH7269 Group  Canceling by a source other than a reset When the falling or rising edge of the NMI pin (selected by a corresponding bit in DSESR) or falling or rising edge of the pins for canceling (selected by a corresponding bit in DSESR) is detected or the realtime clock alarm interrupt (see section 15.4.4, Alarm Function) is generated, clock oscillation is started after the wait time for the oscillation settling time. After the oscillation settling time has elapsed, deep standby mode is cancelled and the power-on reset exception handling is executed. The clock output phase of the CKIO pin may be unstable immediately after detecting a cancel source and until deep standby mode is canceled. The detecting of the NMI pin, the pins for canceling, and the realtime clock alarm interrupt becomes enable when the corresponding bits in DSSSR are set. The detected cancel sources are kept, but they are reflected to DSFR after canceling the deep standby mode. When the CPU accepts any interrupts, all of the cancel sources that are kept are cleared. When the CPU enters the deep standby mode as the detected cancel sources are kept, the deep standby mode is canceled immediately after the CPU enters the deep standby mode.  Canceling with a reset Driving the RES pin low cancels deep standby mode and causes a transition to the power-on reset state. After this, driving the RES pin high initiates power-on reset exception handling. Output of the internal clock from the CKIO pin also starts by driving the RES pin low. Keep the RES pin low until the clock oscillation has settled. Page 2728 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 49 Power-Down Modes Operation after Canceling Deep Standby Mode After canceling deep standby mode, the LSI can be activated through the external memory or from the on-chip data-retention RAM, which can be selected by setting the RAMBOOT bit in DSCTR. By setting the EBUSKEEPE bit, the states of the external memory control pins can be retained even after cancellation of deep standby mode. Table 49.3 shows the pin states after cancellation of deep standby mode according to the setting of each bit. Table 49.4 lists the external memory control pins. Table 49.3 Pin States after Cancellation of Deep Standby Mode and System Activation Method by the DSCTR Settings EBUSKEEPE RAMBOOT Bit Bit Activation Method Pin States After Cancellation of Deep Standby Mode 0 External memory The states of the external memory control pins are not retained. 0 For other pins, the retention of their states is cancelled when the IOKEEP bit is cleared. 0 1 On-chip data- The states of the external memory control pins are not retention retained. RAM After cancellation of deep standby mode, the retention of the external memory control pin states is cancelled. For other pins, the retention of their states is cancelled when the IOKEEP bit is cleared. 1 0  1 1 On-chip data- The states of the external memory control pin are retention retained. RAM The retention of the states of the external memory control pins and other pins is cancelled when the IOKEEP bit is cleared. Setting prohibited. Table 49.4 External Memory Control Pins in Different Modes Boot Mode 0 (CS0 Area: Bus Width: 16 Bits) Boot Mode 0 (CS0 Area: Boot Mode 2 Boot Mode 3 Bus Width: 32 (NAND Flash (Serial Flash Bits) Memory) Memory) A[20:1] D[15:0] CS0, RD, CKIO A[20:2] D[31:0] CS0, RD, CKIO R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 NAF[7:0] FRE, FCLE, FALE, FWE, FCE, FRB Boot Mode 4 Boot Mode 5 (SD Host (MMC Host Interface) Interface) RSPCK0, SSL00, SD_CLK0, MOSI0, MISO0 SD_CMD0, (PB17 to PB20 SD_D[3:0]0 only) MMC_CLK, MMC_CMD, MMC_D[3:0] Page 2729 of 3092 Section 49 Power-Down Modes SH7268 Group, SH7269 Group When deep standby mode is canceled by interrupts (NMI or realtime clock alarm) or changes on the pins for canceling, the deep standby cancel source flag register (DSFR) can be used to confirm which source has canceled the mode. Pins retain the state immediately before the transition to deep standby mode. However, in system activation through the external memory, the retention of the states of the external memory control pins is cancelled so that programs can be fetched after cancellation of deep standby mode. Other pins, after cancellation of deep standby mode, continue to retain the pin states until writing 0 to the IOKEEP bit in DSFR after reading 1 from the same bit. In system activation from the on-chip data-retention RAM, after cancellation of deep standby mode, both the external memory control pins and other pins continues to retain the pin states until writing 0 to the IOKEEP bit in DSFR after reading 1 from the same bit. Reconfiguration of peripheral functions is required to return to the previous state of deep standby mode. Peripheral functions include all functions such as the clock pulse generator, interrupt controller, general I/O ports, and peripheral modules. After the reconfiguration, the retention of the pin state can be canceled and the LSI returns to the state prior to the transition to deep standby mode by reading 1 from the IOKEEP bit in DSFR and then writing 0 to it. (4) Notes on Transition to Deep Standby Mode If multiple canceling sources have been specified and multiple canceling sources are input, multiple cancel source flags will be set. Page 2730 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 49.3.5 (1) Section 49 Power-Down Modes Module Standby Function Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in the program execution state and sleep mode. Disable a module before placing it in the module standby mode. In addition, do not access the module's registers while it is in the module standby state. For details on the states of registers, see section 51.3, Register States in Each Operating Mode. (2) Canceling Module Standby Function The module standby function can be canceled by clearing each MSTP bit to 0, or by a power-on reset (only possible for the realtime clock, user debugging interface, and direct memory access controller). When taking a module out of the module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to confirm that it has been cleared to 0. 49.3.6 Adjustment of XTAL Crystal Oscillator Gain The gain of the crystal oscillator can be adjusted using the GAIN bit in XTALCTR. To modify the gain, PLL settling time is needed. The settling time is counted using the on-chip watchdog timer. 1. The large gain is selected in the initial state. 2. Set the watchdog timer so that the specified settling time should be obtained and stop the watchdog timer. Specifically, the following settings are necessary: TME in WTCSR = 0: Stop the watchdog timer. CKS[2:0] in WTCSR: Division ratio for watchdog timer count clock WTCNT: Initial counter value (The watchdog timer starts counting on the set clock.) 3. Set the GAIN bit to the desired value. 4. The LSI is internally stopped and the watchdog timer starts counting. The clock is supplied only to the watchdog timer and other internal clocks are stopped. In this state, the CKIO pin continues to output an unstable clock. To avoid malfunction due to the unstable clock, modify the CKOEN2 bit in FRQCR appropriately. Since this state is equivalent to the software standby mode state, some registers of on-chip peripheral modules are initialized. For details, see section 51.3, Register States in Each Operating Mode. 5. When an overflow occurs on the watchdog timer, the specified clock supply is started and the LSI starts operation. The watchdog timer stops after an overflow. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2731 of 3092 Section 49 Power-Down Modes 49.4 Usage Notes 49.4.1 Usage Notes on Setting Registers SH7268 Group, SH7269 Group When writing to the registers related to power-down modes, note the following. When writing to the register related to power-down modes, the CPU, after executing a write instruction, executes the next instruction without waiting for the write operation to complete. Therefore, to reflect the change specified by writing to the register while the next instruction is executed, insert a dummy read of the same register between the register write instruction and the next instruction. 49.4.2 Usage Notes when the Realtime Clock is not Used When the realtime clock is not used, set the MSTP30 bit in STBCR3 to 1 after setting the bits in registers of the realtime clock. For details, see section 49.2.3, Standby Control Register 3 (STBCR3). Page 2732 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 50 User Debugging Interface Section 50 User Debugging Interface This LSI incorporates a user debugging interface for the boundary scan function and emulator support. 50.1 Features The user debugging interface is a serial input/output interface that supports JTAG (Joint Test Action Group, IEEE Std.1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture). This module incorporates a boundary scan TAP controller and an emulation TAP controller for controlling the user debugging interface interrupt function. When the TRST pin is asserted, including the case of power-on, the boundary scan TAP controller is selected. By inputting the emulation TAP controller switching command, the emulation TAP controller is selected. To switch from the emulation TAP controller to the boundary scan TAP controller, assert the TRST pin. In ASE mode, the emulation TAP controller is selected. For connection with the emulator, see the manual for the emulator. Figure 50.1 shows a block diagram. Pin switching logic TDI TAP controller for boundary scanning BSBPR BSIR SDBSR BSID TDO TCK TMS TAP controller for emulation SDBPR SDIR TRST Figure 50.1 Block Diagram R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2733 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface 50.2 Input/Output Pins Table 50.1 Pin Configuration Pin Name Symbol I/O Function Serial data input/output clock pin TCK Input Data is serially supplied to this module from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. Mode select input pin TMS Input The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol complies with the JTAG standard (IEEE Std.1149.1). Reset input pin TRST Input Input is accepted asynchronously with respect to TCK, and when low, this module is reset. TRST must be low for a period when power is turned on regardless of using the function. See section 50.5.2, Reset Configuration, for more information. Serial data input pin TDI Input Data is transferred to this module by changing this signal in synchronization with TCK. Serial data output pin TDO Output Data is read from this module by reading this pin in synchronization with TCK. The initial value of the data output timing is the TCK falling edge, but this initial value can be changed to the TCK rising edge by inputting the TDO transition timing switching command to SDIR. See section 50.5.3, TDO Output Timing, for more information. ASE mode select pin ASEMD* Input Note: * If a low level is input at the ASEMD pin while the RES pin is asserted, ASE mode is entered; if a high level is input, product chip mode is entered. In ASE mode, dedicated emulator function can be used. The input level at the ASEMD pin should be held for at least one cycle after RES negation. When the emulator is not in use, fix this pin to the high level. Page 2734 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 50.3 Section 50 User Debugging Interface Description of the Boundary Scan TAP Controller The boundary scan TAP controller has the following registers. Table 50.2 Register Configuration of the Boundary Scan TAP Controller Register Name Abbreviation R/W Initial Value Address Access Size Bypass register BSBPR     Instruction register BSIR  H'4   Boundary scan register SDBSR     ID register BSID  H'080C6447   50.3.1 Bypass Register (BSBPR) BSBPR is a 1-bit register that cannot be accessed by the CPU. When BSIR is set to BYPASS mode, BSBPR is connected between TDI and TDO pins. The initial value is undefined. 50.3.2 Instruction Register (BSIR) BSIR is a 4-bit register and initialized by TRST assertion or in the TAP test-logic-reset state. This register cannot be accessed by the CPU. Bit Bit Name Initial Value R/W Description 3 to 0 TI[3:0] 0100  Test Instruction The instruction of this module is transferred to BSIR as a serial input from TDI. For commands, see table 50.3. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2735 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface Table 50.3 Supported Commands for Boundary Scan TAP Controller Bits 3 to 0 TI3 TI2 TI1 TI0 Description 0 0 0 0 EXTEST 0 0 0 1 SAMPLE/PRELOAD 0 0 1 1 Emulation TAP controller switching command 0 1 0 0 IDCODE (initial value) 0 1 1 0 CLAMP 0 1 1 1 HIGHZ Other than the above 50.3.3 Reserved Boundary Scan Register (SDBSR) SDBSR is a shift register located on the PAD to control input/output pins of this LSI. This register cannot be accessed by the CPU. The initial value is undefined. The EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands can be used to perform the boundary scan test that conforms to the JTAG standard. Table 50.4 shows the correspondence between the LSI pins and the bits of the boundary scan register. Page 2736 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 50 User Debugging Interface Table 50.4 Correspondence between the LSI Pins and the Bits of the Boundary Scan Register SH7268 SH7269 Pin SH7268 SH7269 Pin SH7268 Bit Number Bit Number Name*1 Type Bit Number Bit Number Name*1 Type From TDI SH7269 Pin Bit Number Bit Number Name*1 Type  399 PJ1 OUTPUT 371 371 PG13 CONTROL 426 426 PG0 OUTPUT  398 PJ1 CONTROL 370 370 PG13 INPUT 425 425 PG0 CONTROL  397 PJ1 INPUT 369 369 PG14 OUTPUT 424 424 PG0 INPUT 396 396 PG8 OUTPUT 368 368 PG14 CONTROL 423 423 PG1 OUTPUT 395 395 PG8 CONTROL 367 367 PG14 INPUT 422 422 PG1 CONTROL 394 394 PG8 INPUT 366 366 PG15 OUTPUT 421 421 PG1 INPUT  393 PJ2 OUTPUT 365 365 PG15 CONTROL 420 420 PG2 OUTPUT  392 PJ2 CONTROL 364 364 PG15 INPUT 419 419 PG2 CONTROL  391 PJ2 INPUT 363 363 PG16 OUTPUT 418 418 PG2 INPUT  390 PJ3 OUTPUT 362 362 PG16 CONTROL 417 417 PG3 OUTPUT  389 PJ3 CONTROL 361 361 PG16 INPUT 416 416 PG3 CONTROL  388 PJ3 INPUT  360 PJ5 OUTPUT 415 415 PG3 INPUT  387 PJ4 OUTPUT  359 PJ5 CONTROL 414 414 PG4 OUTPUT  386 PJ4 CONTROL  358 PJ5 INPUT 413 413 PG4 CONTROL  385 PJ4 INPUT  357 PJ6 OUTPUT 412 412 PG4 INPUT 384 384 PG9 OUTPUT  356 PJ6 CONTROL 411 411 PG5 OUTPUT 383 383 PG9 CONTROL  355 PJ6 INPUT 410 410 PG5 CONTROL 382 382 PG9 INPUT 354 354 PG17 OUTPUT 409 409 PG5 INPUT 381 381 PG10 OUTPUT 353 353 PG17 CONTROL 408 408 PG6 OUTPUT 380 380 PG10 CONTROL 352 352 PG17 INPUT 407 407 PG6 CONTROL 379 379 PG10 INPUT  351 PJ7 OUTPUT 406 406 PG6 INPUT 378 378 PG11 OUTPUT  350 PJ7 CONTROL 405 405 PG7 OUTPUT 377 377 PG11 CONTROL  349 PJ7 INPUT 404 404 PG7 CONTROL 376 376 PG11 INPUT  348 PJ8 OUTPUT 403 403 PG7 INPUT 375 375 PG12 OUTPUT  347 PJ8 CONTROL  402 PJ0 OUTPUT 374 374 PG12 CONTROL  346 PJ8 INPUT  401 PJ0 CONTROL 373 373 PG12 INPUT  345 PJ9 OUTPUT  400 PJ0 INPUT 372 372 PG13 OUTPUT  344 PJ9 CONTROL R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2737 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface SH7268 SH7269 SH7268 Pin SH7269 Pin SH7268 SH7269 Pin 1 Bit Number Bit Number Name* Type Bit Number Bit Number Name*1 Type Bit Number Bit Number Name*1 Type  343 PJ9 INPUT 311 311 PF0 CONTROL 279 279 PF11 OUTPUT 342 342 PG18 OUTPUT 310 310 PF0 INPUT 278 278 PF11 CONTROL 341 341 PG18 CONTROL 309 309 PF1 OUTPUT 277 277 PF11 INPUT 340 340 PG18 INPUT 308 308 PF1 CONTROL 276 276 PF12 OUTPUT 339 339 PG19 OUTPUT 307 307 PF1 INPUT 275 275 PF12 CONTROL 338 338 PG19 CONTROL 306 306 PF2 OUTPUT 274 274 PF12 INPUT 337 337 PG19 INPUT 305 305 PF2 CONTROL 273 273 PF13 OUTPUT 336 336 PG20 OUTPUT 304 304 PF2 INPUT 272 272 PF13 CONTROL 335 335 PG20 CONTROL 303 303 PF3 OUTPUT 271 271 PF13 INPUT 334 334 PG20 INPUT 302 302 PF3 CONTROL 270 270 PF14 OUTPUT 333 333 PG21 OUTPUT 301 301 PF3 INPUT 269 269 PF14 CONTROL 332 332 PG21 CONTROL 300 300 PF4 OUTPUT 268 268 PF14 INPUT 331 331 PG21 INPUT 299 299 PF4 CONTROL 267 267 PF15 OUTPUT 330 330 PG22 OUTPUT 298 298 PF4 INPUT 266 266 PF15 CONTROL 329 329 PG22 CONTROL 297 297 PF5 OUTPUT 265 265 PF15 INPUT 328 328 PG22 INPUT 296 296 PF5 CONTROL  264 PJ10 OUTPUT 327 327 PG23 OUTPUT 295 295 PF5 INPUT  263 PJ10 CONTROL 326 326 PG23 CONTROL 294 294 PF6 OUTPUT  262 PJ10 INPUT 325 325 PG23 INPUT 293 293 PF6 CONTROL 261 261 PF16 OUTPUT 324 324 PG24 OUTPUT 292 292 PF6 INPUT 260 260 PF16 CONTROL 323 323 PG24 CONTROL 291 291 PF7 OUTPUT 259 259 PF16 INPUT 322 322 PG24 INPUT 290 290 PF7 CONTROL 258 258 PF17 OUTPUT 321 321 PG25 OUTPUT 289 289 PF7 INPUT 257 257 PF17 CONTROL 320 320 PG25 CONTROL 288 288 PF8 OUTPUT 256 256 PF17 INPUT 319 319 PG25 INPUT 287 287 PF8 CONTROL 255 255 PF18 OUTPUT 318 318 PG26 OUTPUT 286 286 PF8 INPUT 254 254 PF18 CONTROL 317 317 PG26 CONTROL 285 285 PF9 OUTPUT 253 253 PF18 INPUT 316 316 PG26 INPUT 284 284 PF9 CONTROL  252 PJ11 OUTPUT 315 315 PG27 OUTPUT 283 283 PF9 INPUT  251 PJ11 CONTROL 314 314 PG27 CONTROL 282 282 PF10 OUTPUT  250 PJ11 INPUT 313 313 PG27 INPUT 281 281 PF10 CONTROL  249 PJ12 OUTPUT 312 312 PF0 OUTPUT 280 280 PF10 INPUT  248 PJ12 CONTROL Page 2738 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group SH7268 SH7269 Section 50 User Debugging Interface SH7268 Pin SH7269 Pin SH7268 SH7269 Pin 1 Bit Number Bit Number Name* Type Bit Number Bit Number Name*1 Type Bit Number Bit Number Name*1 Type  247 PJ12 INPUT 216 216 PD3 OUTPUT 185 185 PD10 CONTROL  246 PJ13 OUTPUT 215 215 PD3 CONTROL 184 184 PD10 INPUT  245 PJ13 CONTROL 214 214 PD3 INPUT 183 183 PD11 OUTPUT  244 PJ13 INPUT  213 PJ25 OUTPUT 182 182 PD11 CONTROL 243 243 PF19 OUTPUT  212 PJ25 CONTROL 181 181 PD11 INPUT 242 242 PF19 CONTROL  211 PJ25 INPUT 180 180 PD12 OUTPUT 241 241 PF19 INPUT  210 PJ26 OUTPUT 179 179 PD12 CONTROL 240 240 PF20 OUTPUT  209 PJ26 CONTROL 178 178 PD12 INPUT 239 239 PF20 CONTROL  208 PJ26 INPUT 177 177 PD13 OUTPUT 238 238 PF20 INPUT  207 PJ27 OUTPUT 176 176 PD13 CONTROL 237 237 PF21 OUTPUT  206 PJ27 CONTROL 175 175 PD13 INPUT 236 236 PF21 CONTROL  205 PJ27 INPUT 174 174 PD14 OUTPUT 235 235 PF21 INPUT 204 204 PD4 OUTPUT 173 173 PD14 CONTROL 234 234 PF22 OUTPUT 203 203 PD4 CONTROL 172 172 PD14 INPUT 233 233 PF22 CONTROL 202 202 PD4 INPUT 171 171 PD15 OUTPUT 232 232 PF22 INPUT 201 201 PD5 OUTPUT 170 170 PD15 CONTROL 231 231 PF23 OUTPUT 200 200 PD5 CONTROL 169 169 PD15 INPUT 230 230 PF23 CONTROL 199 199 PD5 INPUT 168 168 PC1 OUTPUT 229 229 PF23 INPUT 198 198 PD6 OUTPUT 167 167 PC1 CONTROL 228 228 PD0 OUTPUT 197 197 PD6 CONTROL 166 166 PC1 INPUT 227 227 PD0 CONTROL 196 196 PD6 INPUT 165 165 PC2 OUTPUT 226 226 PD0 INPUT 195 195 PD7 OUTPUT 164 164 PC2 CONTROL  225 PJ24 OUTPUT 194 194 PD7 CONTROL 163 163 PC2 INPUT  224 PJ24 CONTROL 193 193 PD7 INPUT 162 162 PC3 OUTPUT  223 PJ24 INPUT 192 192 PD8 OUTPUT 161 161 PC3 CONTROL 222 222 PD1 OUTPUT 191 191 PD8 CONTROL 160 160 PC3 INPUT 221 221 PD1 CONTROL 190 190 PD8 INPUT 159 159 PC4 OUTPUT 220 220 PD1 INPUT 189 189 PD9 OUTPUT 158 158 PC4 CONTROL 219 219 PD2 OUTPUT 188 188 PD9 CONTROL 157 157 PC4 INPUT 218 218 PD2 CONTROL 187 187 PD9 INPUT 156 156 PC5 OUTPUT 217 217 PD2 INPUT 186 186 PD10 OUTPUT 155 155 PC5 CONTROL R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2739 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface SH7268 SH7269 SH7268 Pin SH7269 Pin SH7268 SH7269 Pin 1 Bit Number Bit Number Name* Type Bit Number Bit Number Name*1 Type Bit Number Bit Number Name*1 Type 154 154 PC5 INPUT  122 PJ17 CONTROL  90 PJ20 OUTPUT 153 153 PC6 OUTPUT  121 PJ17 INPUT  89 PJ20 CONTROL 152 152 PC6 CONTROL  120 PJ18 OUTPUT  88 PJ20 INPUT 151 151 PC6 INPUT  119 PJ18 CONTROL 87 87 PB13 OUTPUT 150 150 PC7 OUTPUT  118 PJ18 INPUT 86 86 PB13 CONTROL 149 149 PC7 CONTROL 117 117 PB5 OUTPUT 85 85 PB13 INPUT 148 148 PC7 INPUT 116 116 PB5 CONTROL  84 PJ21 OUTPUT 147 147 PC8 OUTPUT 115 115 PB5 INPUT  83 PJ21 CONTROL 146 146 PC8 CONTROL 114 114 PB6 OUTPUT  82 PJ21 INPUT 145 145 PC8 INPUT 113 113 PB6 CONTROL  81 PJ22 OUTPUT 144 144 PB1 OUTPUT 112 112 PB6 INPUT  80 PJ22 CONTROL 143 143 PB1 CONTROL 111 111 PB7 OUTPUT  79 PJ22 INPUT 142 142 PB1 INPUT 110 110 PB7 CONTROL  78 PJ23 OUTPUT 141 141 PB2 OUTPUT 109 109 PB7 INPUT  77 PJ23 CONTROL 140 140 PB2 CONTROL 108 108 PB8 OUTPUT  76 PJ23 INPUT 139 139 PB2 INPUT 107 107 PB8 CONTROL 75 75 PB14 OUTPUT 138 138 PB3 OUTPUT 106 106 PB8 INPUT 74 74 PB14 CONTROL 137 137 PB3 CONTROL 105 105 PB9 OUTPUT 73 73 PB14 INPUT 136 136 PB3 INPUT 104 104 PB9 CONTROL 72 72 PB15 OUTPUT  135 PJ14 OUTPUT 103 103 PB9 INPUT 71 71 PB15 CONTROL  134 PJ14 CONTROL 102 102 PB10 OUTPUT 70 70 PB15 INPUT  133 PJ14 INPUT 101 101 PB10 CONTROL 69 69 PB16 OUTPUT  132 PJ15 OUTPUT 100 100 PB10 INPUT 68 68 PB16 CONTROL  131 PJ15 CONTROL 99 99 PB11 OUTPUT 67 67 PB16 INPUT  130 PJ15 INPUT 98 98 PB11 CONTROL 66 66 PB17 OUTPUT 129 129 PB4 OUTPUT 97 97 PB11 INPUT 65 65 PB17 CONTROL 128 128 PB4 CONTROL 96 96 PB12 OUTPUT 64 64 PB17 INPUT 127 127 PB4 INPUT 95 95 PB12 CONTROL 63 63 PB18 OUTPUT  126 PJ16 OUTPUT 94 94 PB12 INPUT 62 62 PB18 CONTROL  125 PJ16 CONTROL  93 PJ19 OUTPUT 61 61 PB18 INPUT  124 PJ16 INPUT  92 PJ19 CONTROL 60 60 PB19 OUTPUT  123 PJ17 OUTPUT  91 PJ19 INPUT 59 59 PB19 CONTROL Page 2740 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group SH7268 SH7269 Section 50 User Debugging Interface SH7268 Pin SH7269 Pin SH7268 SH7269 Pin 1 Bit Number Bit Number Name* Type Bit Number Bit Number Name*1 Type Bit Number Bit Number Name*1 Type 58 58 PB19 INPUT  38 PJ28 CONTROL  18 PE5 OUTPUT*2 57 57 PB20 OUTPUT  37 PJ28 INPUT  17 PE4 INPUT 56 56 PB20 CONTROL  36 PJ29 OUTPUT  16 PE5 INPUT 55 55 PB20 INPUT  35 PJ29 CONTROL  15 PE6 OUTPUT*2 54 54 PB21 OUTPUT  34 PJ29 INPUT  14 PE7 OUTPUT*2 53 53 PB21 CONTROL  33 PJ30 OUTPUT  13 PE6 INPUT 52 52 PB21 INPUT  32 PJ30 CONTROL  12 PE7 INPUT 51 51 PB22 OUTPUT  31 PJ30 INPUT 11 11 NMI INPUT 50 50 PB22 CONTROL  30 PJ31 OUTPUT 10 10 PH0 INPUT 49 49 PB22 INPUT  29 PJ31 CONTROL 9 9 PH1 INPUT 48 48 PC0 OUTPUT  28 PJ31 INPUT 8 8 PH2 INPUT 7 7 PH3 INPUT 47 47 PC0 CONTROL 27 27 PE0 2 OUTPUT* 2 46 46 PC0 INPUT 26 26 PE1 OUTPUT* 6 6 PH4 INPUT 45 45 PA0 OUTPUT 25 25 PE0 INPUT 5 5 PH5 INPUT 44 44 PA0 CONTROL 24 24 PE1 INPUT 43 42 43 42 PA0 PA1 INPUT OUTPUT 23 22 23 22 PE2 PE3  4 PH6 INPUT 2  3 PH7 INPUT 2 2 2 ASEBRKAKN OUTPUT OUTPUT* OUTPUT* /ASEBRK 41 41 PA1 CONTROL 21 21 PE2 INPUT 1 1 ASEBRKAKN CONTROL /ASEBRK 40 40 PA1 INPUT 20 OUTPUT  20 PE3 INPUT 0 0 ASEBRKAKN INPUT /ASEBRK  Notes: 39 1. PJ28 19 PE4 2 OUTPUT* To TDO The pin name used for function 1. 2. The pin is open-drain. The pin state is low when driven low, whereas high impedance (Hi-Z) when driven high. 3. The pin of CONTROL is active-low. When this pin is driven low, the state of the corresponding pin is output. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2741 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface 50.3.4 ID Register (BSID) BSID is a 32-bit register that cannot be accessed by the CPU. The register can be read from pins when the IDCODE command is set, but is not writable. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 8 7 6 5 4 3 2 1 0 0 - 1 - 0 - 0 - 0 - 1 - 1 - 1 - DID[31:16] Initial value: R/W: 0 - 0 - 0 - 0 - 1 - 0 - 0 - Bit: 15 14 13 12 11 10 9 DID[15:0] Initial value: R/W: 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - Bit Bit Name Initial Value R/W Description 31 to 0 DID[31:0] H'080C6447  Device This is an ID register defined by JTAG. The value in this LSI is H'080C6447. The upper four bits may be changed for different chip versions. Page 2742 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 50.4 Section 50 User Debugging Interface Description of the Emulation TAP Controller To use the emulation TAP controller, enter the emulation TAP controller switching command in the BSIR register of the boundary scan TAP controller. The emulation TAP controller has the following registers. Table 50.5 Register Configuration of the Emulation TAP Controller Register Name Abbreviation R/W Initial Value Access Size Address Bypass register SDBPR     Instruction register SDIR R H'EFFD H'FFFE2000 16 50.4.1 Bypass Register (SDBPR) SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS mode, SDBPR is connected between pins TDI and TDO pins. The initial value is undefined. 50.4.2 Instruction Register (SDIR) SDIR is a 16-bit read-only register and initialized by TRST assertion or in the TAP test-logic-reset state. This module can write to this register regardless of the CPU mode. When a reserved command is set in this register, the operation is not guaranteed. The initial value is H'EFFD. Bit: 15 14 13 12 11 10 9 8 TI[7:0] Initial value: 1* R/W: R 1* R 1* R 0* R 1* R 1* R 1* R 1* R 7 6 5 4 3 2 1 - - - - - - - 0 - 1 R 1 R 1 R 1 R 1 R 1 R 0 R 1 R Note: * The initial value of TI[7:0] is a reserved value, but replace it with a non-reserved value when setting a command. Bit Bit Name Initial Value 15 to 8 TI[7:0] 11101111* R R/W Description Test Instruction The instruction of this module is transferred to SDIR as a serial input from TDI. For commands, see table 50.6. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2743 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface Bit Bit Name Initial Value R/W Description 7 to 2  All 1 R Reserved 1  0 R These bits are always read as 1. Reserved These bits are always read as 0.  0 1 R Reserved These bits are always read as 1. Table 50.6 Supported Commands for Emulation TAP Controller Bits 15 to 8 TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description 0 1 1 0     User debugging interface reset negation 0 1 1 1     User debugging interface reset assertion 1 0 0 1 1 1 0 0 TDO transition timing switch 1 0 1 1     User debugging interface interrupt 1 1 1 1     BYPASS Other than the above Page 2744 of 3092 Reserved R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 50 User Debugging Interface 50.5 Operation 50.5.1 TAP Controller Figure 50.2 shows the internal states of the TAP controller. This state machine conforms to the state transitions defined by JTAG. 1 Test -logic-reset 0 1 0 1 Run-test/idle 1 Select-DR Select-IR 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 1 0 1 1 1 Exit1-DR Exit1-IR 0 0 Pause-DR 1 0 0 Pause-IR 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR Update-IR 1 1 0 0 Figure 50.2 TAP Controller State Transitions Note: The transition condition is the TMS value at the rising edge of TCK. The TDI value is sampled at the rising edge of TCK; shifting occurs at the falling edge of TCK. For details on transition timing of the TDO value, see section 50.5.3, TDO Output Timing. The TDO is at high impedance, except with shift-DR and shift-IR states. During the change to TRST = 0, there is a transition to test-logic-reset asynchronously with TCK. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2745 of 3092 SH7268 Group, SH7269 Group Section 50 User Debugging Interface 50.5.2 Reset Configuration Table 50.7 Reset Configuration ASEMD*1 RES TRST Chip State H L L Power-on reset and the reset of this module H Power-on reset H L L H L Reset this module only H Normal operation L Reset hold*2 H Power-on reset L Reset this module only H Normal operation Notes: 1. Performs product chip mode and ASE mode settings ASEMD = H, normal mode ASEMD = L, ASE mode 2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is negated. In this state, the CPU does not start up. When TRST is driven high, the operation of this module is enabled, but the CPU does not start up. The reset hold state is cancelled by a power-on reset. 50.5.3 TDO Output Timing When the emulation TAP controller is selected, a transition on the TDO pin is output on the falling edge of TCK with the initial value. However, setting a TDO transition timing switching command in SDIR via the pin and passing the Update-IR state synchronizes the TDO transition with the rising edge of TCK. This command does not affect the output timing of the boundary scan TAP controller. To synchronize the transition of TDO with the falling edge of TCK after setting the TDO transition timing switching command, the TRST pin must be asserted simultaneously with the power-on reset. In the case of power-on reset by the RES pin, the sync reset is still in operation for a certain period in the LSI even after the RES pin is negated. Thus, if the TRST pin is asserted immediately after the negation of the RES pin, the TDO transition timing switching command is cleared, resulting in TDO transitions synchronized with the falling edges of TCK. To prevent this, make sure to allow a period of 20 tcyc or longer between the signal transitions of the RES and TRST pins. Page 2746 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 50 User Debugging Interface TCK TDO (after execution of TDO transition timing switching command) tTDOD tTDOD TDO (initial value) Figure 50.3 User Debugging Interface Data Transfer Timing 50.5.4 User Debugging Interface Reset A user debugging interface reset occurs when a user debugging interface reset assert command is set in SDIR. A user debugging interface reset is of the same kind as a power-on reset. A user debugging interface reset is cleared by setting a user debugging interface reset negate command. The required time between the user debugging interface reset assert command and user debugging interface reset negate command is the same as time for keeping the RES pin low to apply a poweron reset. SDIR User debugging interface reset assert User debugging interface reset assert Chip internal reset Fetch the initial values of PC and SR from the exception handling vector table CPU state Figure 50.4 User debugging interface Reset 50.5.5 User Debugging Interface Interrupt The user debugging interface interrupt function generates an interrupt by setting a command from the user debugging interface into SDIR. A user debugging interface interrupt is a general exception/interrupt operation, resulting in fetching the exception service routine start address from the exception handling vector table, jumping to that address, and starting program execution from that address. This interrupt request has a fixed priority level of 15. User debugging interface interrupts are accepted in sleep mode, but not in software standby mode. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2747 of 3092 Section 50 User Debugging Interface 50.6 SH7268 Group, SH7269 Group Boundary Scan By setting the commands in BSIR by this module, pins can be configured for boundary scan mode defined by JTAG. 50.6.1 Supported Instructions This LSI supports three required instructions (BYPASS, SAMPLE/PRELOAD, and EXTEST) and three optional instructions (IDCODE, CLAMP, and HIGHZ) defined by JTAG. (1) BYPASS The BYPASS instruction is a required standard instruction to operate the bypass register. This instruction is used to increase the transfer speed of serial data of other LSIs on the printed circuit board by reducing the shift path. During execution of this instruction, the test circuit does not affect the system circuit. (2) SAMPLE/PRELOAD The SAMPLE/PRELOAD instruction inputs a value from the internal circuit of the LSI to the boundary scan register, and output the data from scan path or load the data to the scan path. During execution of the instruction, the value on the input pin of the LSI is transferred to the internal circuit and the value of the internal circuit is output externally from the output pin. Execution of the instruction does not affect the system circuit of the LSI. In SAMPLE operation, the snapshots of the value transferred from the input pin to the internal circuit and the value transferred from the internal circuit to the output pin are captured in the boundary scan register and then read from the scan path. Capturing of the snapshots is performed in synchronization with the rising edge of TCK in the capture-DR state. The capturing is performed without interfering with normal operation of the LSI. In PRELOAD operation, an initial value is set in the output latch of the boundary scan register from the scan path before execution of the EXTEST instruction. Without PRELOAD operation, an undefined value is output from the output pin until the first scan sequence is completed (transferred to the output latch) during execution of the EXTEST instruction (the parallel output latch is always output to the output pin with the EXTEST instruction). Page 2748 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group (3) Section 50 User Debugging Interface EXTEST The EXTEST instruction tests the external circuit when this LSI is mounted on the printed circuit board. During execution of this instruction, the output pin is used to output the test data (set in advance by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board and the input pin is used to capture the test result from the printed circuit board to the boundary scan register. When a test is performed using the EXTEST instruction N times, the N-th test data is scanned-in during (N-1)-th scan-out. The data loaded in the boundary scan register of the output pin in the capture-DR state of this instruction is not used in testing of the external circuit (an exchange is made in shift operation). (4) IDCODE Setting a command to SDIR can set pins to IDCODE mode that is defined by JTAG. When this module is initialized (TRST is asserted or TAP is placed in the test-logic-reset state), IDCODE mode is entered. (5) CLAMP and HIGHZ Setting a command to SDIR can set pins to CLAMP/HIGHZ mode that is defined by JTAG. When this module is initialized (TRST is asserted or TAP is placed in the test-logic-reset state), IDCODE mode is entered. 50.6.2 Notes 1. The clock related signals (EXTAL, XTAL, CKIO, AUDIO_X1, AUDIO_X2, USB_X1, USB_X2, RTC_X1, RTC_X2, and MD_CLK0) are inapplicable to the boundary scan. 2. The reset-related signal (RES) is inapplicable to the boundary scan. 3. Related signals (TCK, TDI, TDO, TMS, TRST, and ASEMD) of this module are inapplicable to the boundary scan. 4. The USB related signals (DP, DM, VBUS, and REFRIN) are inapplicable to the boundary scan. 5. Execute the boundary scan in product chip mode and input the ASEMD pin to high during the RES pin assertion period. And make sure to fix the ASEMD pin at high while executing the boundary scan. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2749 of 3092 Section 50 User Debugging Interface 50.7 SH7268 Group, SH7269 Group Usage Notes 1. Once a command of this module has been set, it will not be modified until another command is not set again. If the same command is to be set continuously, the command must be set after a command (BYPASS mode, etc.) that does not affect chip operations is once set. 2. In software standby mode and in this module's standby state, none of the functions of this module can be used. To retain the TAP status before and after standby mode, keep TCK high before entering standby mode. 3. Regardless of whether this module is used, make sure to keep the TRST pin low to initialize this module at power-on or in recovery from deep standby by the RES pin assertion. 4. If the TRST pin is asserted immediately after the setting of the TDO transition timing switching command and the negation of the RES pin, the TDO transition timing switching command is cleared. To avoid this case, make sure to put 20 tcyc or longer between the signal transition timing of the RES and TRST pins. For details, see section 50.5.3, TDO Output Timing. 5. When starting the TAP controller after the negation of the TRST pin, make sure to allow 200 ns or longer after the negation. 6. Please keep TMS pin high for 200 ns from TRST pin negation. Page 2750 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Section 51 List of Registers This section gives information on the on-chip I/O registers of this LSI in the following structures. 1.    Register Addresses (by functional module, in order of the corresponding section numbers) Registers are described by functional module, in order of the corresponding section numbers. Access to reserved addresses which are not described in this register address list is prohibited. When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big endian mode is selected.  An asterisk (*) in the column "Access Size" indicates that the unit of access in reading differs from that in writing for the given register. For details, see the register descriptions in the relevant section. 2. Register Bits  Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers).  Reserved bits are indicated by "—" in the bit name.  No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. 3. Register States in Each Operating Mode  Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers).  For the initial state of each bit, refer to the description of the register in the corresponding section.  The register states described are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2751 of 3092 Section 51 List of Registers SH7268 Group, SH7269 Group 4. Notes when Writing to the On-Chip Peripheral Modules  To access an on-chip module register, two or more peripheral module clock (P) cycles are required. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to the software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. Page 2752 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 51.1 Section 51 List of Registers Register Addresses (by functional module, in order of the corresponding section numbers) Number Access Module Name Register Name Abbreviation of Bits Address Size Clock pulse Frequency control register FRQCR 16 H'FFFE0010 16 Interrupt control register 0 ICR0 16 H'FFFE0800 16, 32 Interrupt control register 1 ICR1 16 H'FFFE0802 16, 32 Interrupt control register 2 ICR2 16 H'FFFE0804 16, 32 IRQ interrupt request register IRQRR 16 H'FFFE0806 16, 32 PINT interrupt enable register PINTER 16 H'FFFE0808 16, 32 PINT interrupt request register PIRR 16 H'FFFE080A 16, 32 Bank control register IBCR 16 H'FFFE080C 16, 32 Bank number register IBNR 16 H'FFFE080E 16, 32 Interrupt priority register 01 IPR01 16 H'FFFE0818 16, 32 Interrupt priority register 02 IPR02 16 H'FFFE081A 16, 32 Interrupt priority register 05 IPR05 16 H'FFFE0820 16, 32 Interrupt priority register 06 IPR06 16 H'FFFE0C00 16, 32 Interrupt priority register 07 IPR07 16 H'FFFE0C02 16, 32 Interrupt priority register 08 IPR08 16 H'FFFE0C04 16, 32 Interrupt priority register 09 IPR09 16 H'FFFE0C06 16, 32 Interrupt priority register 10 IPR10 16 H'FFFE0C08 16, 32 Interrupt priority register 11 IPR11 16 H'FFFE0C0A 16, 32 Interrupt priority register 12 IPR12 16 H'FFFE0C0C 16, 32 Interrupt priority register 13 IPR13 16 H'FFFE0C0E 16, 32 Interrupt priority register 14 IPR14 16 H'FFFE0C10 16, 32 Interrupt priority register 15 IPR15 16 H'FFFE0C12 16, 32 Interrupt priority register 16 IPR16 16 H'FFFE0C14 16, 32 Interrupt priority register 17 IPR17 16 H'FFFE0C16 16, 32 Interrupt priority register 18 IPR18 16 H'FFFE0C18 16, 32 Interrupt priority register 19 IPR19 16 H'FFFE0C1A 16, 32 Interrupt priority register 20 IPR20 16 H'FFFE0C1C 16, 32 generator Interrupt controller R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2753 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Interrupt controller Interrupt priority register 21 IPR21 16 H'FFFE0C1E 16, 32 Interrupt priority register 22 IPR22 16 H'FFFE0C20 16, 32 Interrupt priority register 23 IPR23 16 H'FFFE0C22 16, 32 Interrupt priority register 24 IPR24 16 H'FFFE0C24 16, 32 Interrupt priority register 25 IPR25 16 H'FFFE0C26 16, 32 Interrupt priority register 26 IPR26 16 H'FFFE0C28 16, 32 Break address register_0 BAR_0 32 H'FFFC0400 32 Break address mask register_0 BAMR_0 32 H'FFFC0404 32 Break data register_0 BDR_0 32 H'FFFC0408 32 Break data mask register_0 BDMR_0 32 H'FFFC040C 32 Break address register_1 BAR_1 32 H'FFFC0410 32 Break address mask register_1 BAMR_1 32 H'FFFC0414 32 Break data register_1 BDR_1 32 H'FFFC0418 32 Break data mask register_1 BDMR_1 32 H'FFFC041C 32 Break bus cycle register_0 BBR_0 16 H'FFFC04A0 16 Break bus cycle register_1 BBR_1 16 H'FFFC04B0 16 Break control register BRCR 32 H'FFFC04C0 32 Cache control register 1 CCR1 32 H'FFFC1000 32 Cache control register 2 CCR2 32 H'FFFC1004 32 Common control register CMNCR 32 H'FFFC 0000 32 CS0 space bus control register CS0BCR 32 H'FFFC 0004 32 CS1 space bus control register CS1BCR 32 H'FFFC 0008 32 CS2 space bus control register CS2BCR 32 H'FFFC 000C 32 CS3 space bus control register CS3BCR 32 H'FFFC 0010 32 CS4 space bus control register CS4BCR 32 H'FFFC 0014 32 CS5 space bus control register CS5BCR 32 H'FFFC 0018 32 CS0 space wait control register CS0WCR 32 H'FFFC 0028 32 CS1 space wait control register CS1WCR 32 H'FFFC 002C 32 CS2 space wait control register CS2WCR 32 H'FFFC 0030 32 CS3 space wait control register CS3WCR 32 H'FFFC 0034 32 CS4 space wait control register CS4WCR 32 H'FFFC 0038 32 User break controller Cache Bus state controller Page 2754 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Bus state controller CS5 space wait control register CS5WCR 32 H'FFFC 003C 32 SDRAM control register SDCR 32 H'FFFC 004C 32 Refresh timer control/status register RTCSR 16 H'FFFC 0050 32 Refresh timer counter RTCNT 16 H'FFFC 0054 32 Direct memory access controller Refresh time constant register RTCOR 16 H'FFFC 0058 32 DMA source address register_0 SAR0 32 H'FFFE1000 16, 32 DMA destination address register_0 DAR0 32 H'FFFE1004 16, 32 DMA transfer count register_0 DMATCR0 32 H'FFFE1008 16, 32 DMA channel control register_0 RSAR0 32 H'FFFE1100 16, 32 DMA reload source address register_0 RDAR0 32 H'FFFE1104 16, 32 DMA reload destination address RDMATCR0 32 H'FFFE1108 16, 32 DMA reload transfer count register_0 CHCR0 32 H'FFFE100C 8, 16, 32 DMA source address register_1 SAR1 32 H'FFFE1010 16, 32 DMA destination address register_1 DAR1 32 H'FFFE1014 16, 32 DMA transfer count register_1 DMATCR1 32 H'FFFE1018 16, 32 DMA channel control register_1 CHCR1 32 H'FFFE101C 8, 16, 32 DMA reload source address register_1 RSAR1 32 H'FFFE1110 16, 32 DMA reload destination address RDAR1 32 H'FFFE1114 16, 32 DMA reload transfer count register_1 RDMATCR1 32 H'FFFE1118 16, 32 DMA source address register_2 SAR2 32 H'FFFE1020 16, 32 DMA destination address register_2 DAR2 32 H'FFFE1024 16, 32 DMA transfer count register_2 DMATCR2 32 H'FFFE1028 16, 32 DMA channel control register_2 CHCR2 32 H'FFFE102C 8, 16, 32 DMA reload source address register_2 RSAR2 32 H'FFFE1120 16, 32 DMA reload destination address RDAR2 32 H'FFFE1124 16, 32 DMA reload transfer count register_2 RDMATCR2 32 H'FFFE1128 16, 32 DMA source address register_3 SAR3 32 H'FFFE1030 16, 32 DMA destination address register_3 DAR3 32 H'FFFE1034 16, 32 DMA transfer count register_3 DMATCR3 32 H'FFFE1038 16, 32 DMA channel control register_3 CHCR3 32 H'FFFE103C 8, 16, 32 register_0 register_1 register_2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2755 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Direct memory DMA reload source address register_3 RSAR3 32 H'FFFE1130 16, 32 DMA reload destination address RDAR3 32 H'FFFE1134 16, 32 access controller register_3 DMA reload transfer count register_3 RDMATCR3 32 H'FFFE1138 16, 32 DMA source address register_4 SAR4 32 H'FFFE1040 16, 32 DMA destination address register_4 DAR4 32 H'FFFE1044 16, 32 DMA transfer count register_4 DMATCR4 32 H'FFFE1048 16, 32 DMA channel control register_4 CHCR4 32 H'FFFE104C 8, 16, 32 DMA reload source address register_4 RSAR4 32 H'FFFE1140 16, 32 DMA reload destination address RDAR4 32 H'FFFE1144 16, 32 DMA reload transfer count register_4 RDMATCR4 32 H'FFFE1148 16, 32 DMA source address register_5 SAR5 32 H'FFFE1050 16, 32 DMA destination address register_5 DAR5 32 H'FFFE1054 16, 32 DMA transfer count register_5 DMATCR5 32 H'FFFE1058 16, 32 DMA channel control register_5 CHCR5 32 H'FFFE105C 8, 16, 32 DMA reload source address register_5 RSAR5 32 H'FFFE1150 16, 32 DMA reload destination address RDAR5 32 H'FFFE1154 16, 32 DMA reload transfer count register_5 RDMATCR5 32 H'FFFE1158 16, 32 DMA source address register_6 SAR6 32 H'FFFE1060 16, 32 DMA destination address register_6 DAR6 32 H'FFFE1064 16, 32 DMA transfer count register_6 DMATCR6 32 H'FFFE1068 16, 32 DMA channel control register_6 CHCR6 32 H'FFFE106C 8, 16, 32 DMA reload source address register_6 RSAR6 32 H'FFFE1160 16, 32 DMA reload destination address RDAR6 32 H'FFFE1164 16, 32 DMA reload transfer count register_6 RDMATCR6 32 H'FFFE1168 16, 32 DMA source address register_7 SAR7 32 H'FFFE1070 16, 32 DMA destination address register_7 DAR7 32 H'FFFE1074 16, 32 DMA transfer count register_7 DMATCR7 32 H'FFFE1078 16, 32 DMA channel control register_7 CHCR7 32 H'FFFE107C 8, 16, 32 DMA reload source address register_7 RSAR7 32 H'FFFE1170 16, 32 register_4 register_5 register_6 Page 2756 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Direct memory DMA reload destination address RDAR7 32 H'FFFE1174 16, 32 access controller register_7 RDMATCR7 32 H'FFFE1178 16, 32 DMA source address register_8 SAR8 32 H'FFFE1080 16, 32 DMA destination address register_8 DAR8 32 H'FFFE1084 16, 32 DMA transfer count register_8 DMATCR8 32 H'FFFE1088 16, 32 DMA channel control register_8 RSAR8 32 H'FFFE1180 16, 32 DMA reload source address register_8 RDAR8 32 H'FFFE1184 16, 32 DMA reload destination address RDMATCR8 32 H'FFFE1188 16, 32 DMA reload transfer count register_8 CHCR8 32 H'FFFE108C 8, 16, 32 DMA source address register_9 SAR9 32 H'FFFE1090 16, 32 DMA destination address register_9 DAR9 32 H'FFFE1094 16, 32 DMA transfer count register_9 DMATCR9 32 H'FFFE1098 16, 32 DMA channel control register_9 CHCR9 32 H'FFFE109C 8, 16, 32 DMA reload source address register_9 RSAR9 32 H'FFFE1190 16, 32 DMA reload destination address RDAR9 32 H'FFFE1194 16, 32 DMA reload transfer count register_9 RDMATCR9 32 H'FFFE1198 16, 32 DMA source address register_10 SAR10 32 H'FFFE10A0 16, 32 DMA destination address register_10 DAR10 32 H'FFFE10A4 16, 32 DMA transfer count register_10 DMATCR10 32 H'FFFE10A8 16, 32 DMA channel control register_10 CHCR10 32 H'FFFE10AC 8, 16, 32 DMA reload source address register_10 RSAR10 32 H'FFFE11A0 16, 32 DMA reload destination address RDAR10 32 H'FFFE11A4 16, 32 DMA reload transfer count register_10 RDMATCR10 32 H'FFFE11A8 16, 32 DMA source address register_11 SAR11 32 H'FFFE10B0 16, 32 DMA destination address register_11 DAR11 32 H'FFFE10B4 16, 32 DMA transfer count register_11 DMATCR11 32 H'FFFE10B8 16, 32 DMA channel control register_11 CHCR11 32 H'FFFE10BC 8, 16, 32 DMA reload source address register_11 RSAR11 32 H'FFFE11B0 16, 32 DMA reload transfer count register_7 register_8 register_9 register_10 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2757 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Direct memory DMA reload destination address RDAR11 32 H'FFFE11B4 16, 32 access controller register_11 RDMATCR11 32 H'FFFE11B8 16, 32 DMA source address register_12 SAR12 32 H'FFFE10C0 16, 32 DMA destination address register_12 DAR12 32 H'FFFE10C4 16, 32 DMA transfer count register_12 DMATCR12 32 H'FFFE10C8 16, 32 DMA channel control register_12 CHCR12 32 H'FFFE10CC 8, 16, 32 DMA reload source address register_12 RSAR12 32 H'FFFE11C0 16, 32 DMA reload destination address RDAR12 32 H'FFFE11C4 16, 32 DMA reload transfer count register_12 RDMATCR12 32 H'FFFE11C8 16, 32 DMA source address register_13 SAR13 32 H'FFFE10D0 16, 32 DMA destination address register_13 DAR13 32 H'FFFE10D4 16, 32 DMA transfer count register_13 DMATCR13 32 H'FFFE10D8 16, 32 DMA channel control register_13 CHCR13 32 H'FFFE10DC 8, 16, 32 DMA reload source address register_13 RSAR13 32 H'FFFE11D0 16, 32 DMA reload destination address RDAR13 32 H'FFFE11D4 16, 32 RDMATCR13 32 H'FFFE11D8 16, 32 DMA source address register_14 SAR14 32 H'FFFE10E0 16, 32 DMA destination address register_14 DAR14 32 H'FFFE10E4 16, 32 DMA transfer count register_14 DMATCR14 32 H'FFFE10E8 16, 32 DMA channel control register_14 CHCR14 32 H'FFFE10EC 8, 16, 32 DMA reload source address register_14 RSAR14 32 H'FFFE11E0 16, 32 DMA reload destination address RDAR14 32 H'FFFE11E4 16, 32 RDMATCR14 32 H'FFFE11E8 16, 32 DMA source address register_15 SAR15 32 H'FFFE10F0 16, 32 DMA destination address register_15 DAR15 32 H'FFFE10F4 16, 32 DMA transfer count register_15 DMATCR15 32 H'FFFE10F8 16, 32 DMA channel control register_15 CHCR15 32 H'FFFE10FC 8, 16, 32 DMA reload source address register_15 RSAR15 32 H'FFFE11F0 16, 32 DMA reload destination address register_15 RDAR15 32 H'FFFE11F4 16, 32 DMA reload transfer count register_11 register_12 register_13 DMA reload transfer count register_13 register_14 DMA reload transfer count register_14 Page 2758 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Direct memory DMA reload transfer count register_15 RDMATCR15 32 H'FFFE11F8 16, 32 DMA operation register DMAOR 16 H'FFFE1200 8, 16 DMA extension resource selector 0 DMARS0 16 H'FFFE1300 16 DMA extension resource selector 1 DMARS1 16 H'FFFE1304 16 DMA extension resource selector 2 DMARS2 16 H'FFFE1308 16 DMA extension resource selector 3 DMARS3 16 H'FFFE130C 16 DMA extension resource selector 4 DMARS4 16 H'FFFE1310 16 DMA extension resource selector 5 DMARS5 16 H'FFFE1314 16 DMA extension resource selector 6 DMARS6 16 H'FFFE1318 16 access controller Multi-function timer pulse unit 2 DMA extension resource selector 7 DMARS7 16 H'FFFE131C 16 Timer control register_0 TCR_0 8 H'FFFE4300 8 Timer mode register_0 TMDR_0 8 H'FFFE4301 8 Timer I/O control register H_0 TIORH_0 8 H'FFFE4302 8 Timer I/O control register L_0 TIORL_0 8 H'FFFE4303 8 Timer interrupt enable register_0 TIER_0 8 H'FFFE4304 8 Timer status register_0 TSR_0 8 H'FFFE4305 8 Timer counter_0 TCNT_0 16 H'FFFE4306 16 Timer general register A_0 TGRA_0 16 H'FFFE4308 16 Timer general register B_0 TGRB_0 16 H'FFFE430A 16 Timer general register C_0 TGRC_0 16 H'FFFE430C 16 Timer general register D_0 TGRD_0 16 H'FFFE430E 16 Timer general register E_0 TGRE_0 16 H'FFFE4320 16 Timer general register F_0 TGRF_0 16 H'FFFE4322 16 Timer interrupt enable register 2_0 TIER2_0 8 H'FFFE4324 8 Timer status register 2_0 TSR2_0 8 H'FFFE4325 8 Timer buffer operation transfer mode TBTM_0 8 H'FFFE4326 8 Timer control register_1 TCR_1 8 H'FFFE4380 8 Timer mode register_1 TMDR_1 8 H'FFFE4381 8 register_0 Timer I/O control register_1 TIOR_1 8 H'FFFE4382 8 Timer interrupt enable register_1 TIER_1 8 H'FFFE4384 8 Timer status register_1 TSR_1 8 H'FFFE4385 8 Timer counter_1 TCNT_1 16 H'FFFE4386 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2759 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Multi-function timer Timer general register A_1 TGRA_1 16 H'FFFE4388 16 Timer general register B_1 TGRB_1 16 H'FFFE438A 16 Timer input capture control register TICCR 8 H'FFFE4390 8 Timer control register_2 TCR_2 8 H'FFFE4000 8 Timer mode register_2 TMDR_2 8 H'FFFE4001 8 pulse unit 2 Timer I/O control register_2 TIOR_2 8 H'FFFE4002 8 Timer interrupt enable register_2 TIER_2 8 H'FFFE4004 8 Timer status register_2 TSR_2 8 H'FFFE4005 8 Timer counter_2 TCNT_2 16 H'FFFE4006 16 Timer general register A_2 TGRA_2 16 H'FFFE4008 16 Timer general register B_2 TGRB_2 16 H'FFFE400A 16 Timer control register_3 TCR_3 8 H'FFFE4200 8 Timer mode register_3 TMDR_3 8 H'FFFE4202 8 Timer I/O control register H_3 TIORH_3 8 H'FFFE4204 8 Timer I/O control register L_3 TIORL_3 8 H'FFFE4205 8 Timer interrupt enable register_3 TIER_3 8 H'FFFE4208 8 Timer status register_3 TSR_3 8 H'FFFE422C 8 Timer counter_3 TCNT_3 16 H'FFFE4210 16 Timer general register A_3 TGRA_3 16 H'FFFE4218 16 Timer general register B_3 TGRB_3 16 H'FFFE421A 16 Timer general register C_3 TGRC_3 16 H'FFFE4224 16 Timer general register D_3 TGRD_3 16 H'FFFE4226 16 Timer buffer operation transfer mode TBTM_3 8 H'FFFE4238 8 TCR_4 8 H'FFFE4201 8 register_3 Timer control register_4 Page 2760 of 3092 Timer mode register_4 TMDR_4 8 H'FFFE4203 8 Timer I/O control register H_4 TIORH_4 8 H'FFFE4206 8 Timer I/O control register L_4 TIORL_4 8 H'FFFE4207 8 Timer interrupt enable register_4 TIER_4 8 H'FFFE4209 8 Timer status register_4 TSR_4 8 H'FFFE422D 8 Timer counter_4 TCNT_4 16 H'FFFE4212 16 Timer general register A_4 TGRA_4 16 H'FFFE421C 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Multi-function timer Timer general register B_4 TGRB_4 16 H'FFFE421E 16 Timer general register C_4 TGRC_4 16 H'FFFE4228 16 Timer general register D_4 TGRD_4 16 H'FFFE422A 16 Timer buffer operation transfer mode TBTM_4 8 H'FFFE4239 8 16 H'FFFE4240 16 TADCORA_4 16 H'FFFE4244 16 TADCORB_4 16 H'FFFE4246 16 TADCOBRA_4 16 H'FFFE4248 16 TADCOBRB_4 16 H'FFFE424A 16 Timer start register TSTR 8 H'FFFE4280 8 Timer synchronous register TSYR 8 H'FFFE4281 8 Timer read/write enable register TRWER 8 H'FFFE4284 8 Timer output master enable register TOER 8 H'FFFE420A 8 Timer output control register 1 TOCR1 8 H'FFFE420E 8 Timer output control register 2 TOCR2 8 H'FFFE420F 8 Timer gate control register TGCR 8 H'FFFE420D 8 pulse unit 2 register_4 Timer A/D converter start request control TADCR register Timer A/D converter start request cycle set register A_4 Timer A/D converter start request cycle set register B_4 Timer A/D converter start request cycle set buffer register A_4 Timer A/D converter start request cycle set buffer register B_4 Timer cycle data register TCDR 16 H'FFFE4214 16 Timer dead time data register TDDR 16 H'FFFE4216 16 Timer subcounter TCNTS 16 H'FFFE4220 16 Timer cycle buffer register TCBR 16 H'FFFE4222 16 Timer interrupt skipping set register TITCR 8 H'FFFE4230 8 Timer interrupt skipping counter TITCNT 8 H'FFFE4231 8 Timer buffer transfer set register TBTER 8 H'FFFE4232 8 Timer dead time enable register TDER 8 H'FFFE4234 8 Timer waveform control register TWCR 8 H'FFFE4260 8 Timer output level buffer register TOLBR 8 H'FFFE4236 8 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2761 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Compare match Compare match timer start register CMSTR 16 H'FFFEC000 16 Compare match timer control/status CMCSR_0 16 H'FFFEC002 16 Compare match counter_0 CMCNT_0 16 H'FFFEC004 8, 16 Compare match constant register_0 CMCOR_0 16 H'FFFEC006 8, 16 Compare match timer control/status CMCSR_1 16 H'FFFEC008 16 Compare match counter_1 CMCNT_1 16 H'FFFEC00A 8, 16 Compare match constant register_1 CMCOR_1 16 H'FFFEC00C 8, 16 Watchdog timer counter WTCNT 8 H'FFFE0002 8, 16 timer register_0 register_1 Watchdog timer Realtime clock Page 2762 of 3092 Watchdog timer control/status register WTCSR 8 H'FFFE0000 8, 16 Watchdog reset control/status register WRCSR 8 H'FFFE0004 8, 16 64-Hz counter R64CNT 8 H'FFFE6000 8 Second counter RSECCNT 8 H'FFFE6002 8 Minute counter RMINCNT 8 H'FFFE6004 8 Hour counter RHRCNT 8 H'FFFE6006 8 Day of week counter RWKCNT 8 H'FFFE6008 8 Date counter RDAYCNT 8 H'FFFE600A 8 Month counter RMONCNT 8 H'FFFE600C 8 Year counter RYRCNT 16 H'FFFE600E 16 Second alarm register RSECAR 8 H'FFFE6010 8 Minute alarm register RMINAR 8 H'FFFE6012 8 Hour alarm register RHRAR 8 H'FFFE6014 8 Day of week alarm register RWKAR 8 H'FFFE6016 8 Date alarm register RDAYAR 8 H'FFFE6018 8 Month alarm register RMONAR 8 H'FFFE601A 8 Year alarm register RYRAR 16 H'FFFE6020 16 Control register 1 RCR1 8 H'FFFE601C 8 Control register 2 RCR2 8 H'FFFE601E 8 Control register 3 RCR3 8 H'FFFE6024 8 Control register 5 RCR5 8 H'FFFE6026 8 Frequency register H RFRH 16 H'FFFE602A 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Realtime clock Frequency register L RFRL 16 H'FFFE602C 16 Serial Serial mode register_0 SCSMR_0 16 H'E8007000 16 Bit rate register_0 SCBRR_0 8 H'E8007004 8 Serial control register_0 SCSCR_0 16 H'E8007008 16 Transmit FIFO data register_0 SCFTDR_0 8 H'E800700C 8 Serial status register_0 SCFSR_0 16 H'E8007010 16 Receive FIFO data register_0 SCFRDR_0 8 H'E8007014 8 FIFO control register_0 SCFCR_0 16 H'E8007018 16 FIFO data count set register_0 SCFDR_0 16 H'E800701C 16 Serial port register_0 SCSPTR_0 16 H'E8007020 16 Line status register_0 SCLSR_0 16 H'E8007024 16 Serial extension mode register_0 SCEMR_0 16 H'E8007028 16 communication interface with FIFO Serial mode register_1 SCSMR_1 16 H'E8007800 16 Bit rate register_1 SCBRR_1 8 H'E8007804 8 Serial control register_1 SCSCR_1 16 H'E8007808 16 Transmit FIFO data register_1 SCFTDR_1 8 H'E800780C 8 Serial status register_1 SCFSR_1 16 H'E8007810 16 Receive FIFO data register_1 SCFRDR_1 8 H'E8007814 8 FIFO control register_1 SCFCR_1 16 H'E8007818 16 FIFO data count set register_1 SCFDR_1 16 H'E800781C 16 Serial port register_1 SCSPTR_1 16 H'E8007820 16 Line status register_1 SCLSR_1 16 H'E8007824 16 Serial extension mode register_1 SCEMR_1 16 H'E8007828 16 Serial mode register_2 SCSMR_2 16 H'E8008000 16 Bit rate register_2 SCBRR_2 8 H'E8008004 8 Serial control register_2 SCSCR_2 16 H'E8008008 16 Transmit FIFO data register_2 SCFTDR_2 8 H'E800800C 8 Serial status register_2 SCFSR_2 16 H'E8008010 16 Receive FIFO data register_2 SCFRDR_2 8 H'E8008014 8 FIFO control register_2 SCFCR_2 16 H'E8008018 16 FIFO data count set register_2 SCFDR_2 16 H'E800801C 16 Serial port register_2 SCSPTR_2 16 H'E8008020 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2763 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Serial Line status register_2 SCLSR_2 16 H'E8008024 16 Serial extension mode register_2 SCEMR_2 16 H'E8008028 16 Serial mode register_3 SCSMR_3 16 H'E8008800 16 Bit rate register_3 SCBRR_3 8 H'E8008804 8 Serial control register_3 SCSCR_3 16 H'E8008808 16 Transmit FIFO data register_3 SCFTDR_3 8 H'E800880C 8 Serial status register_3 SCFSR_3 16 H'E8008810 16 Receive FIFO data register_3 SCFRDR_3 8 H'E8008814 8 FIFO control register_3 SCFCR_3 16 H'E8008818 16 FIFO data count set register_3 SCFDR_3 16 H'E800881C 16 Serial port register_3 SCSPTR_3 16 H'E8008820 16 Line status register_3 SCLSR_3 16 H'E8008824 16 Serial extension mode register_3 SCEMR_3 16 H'E8008828 16 Serial mode register_4 SCSMR_4 16 H'E8009000 16 Bit rate register_4 SCBRR_4 8 H'E8009004 8 Serial control register_4 SCSCR_4 16 H'E8009008 16 Transmit FIFO data register_4 SCFTDR_4 8 H'E800900C 8 Serial status register_4 SCFSR_4 16 H'E8009010 16 Receive FIFO data register_4 SCFRDR_4 8 H'E8009014 8 FIFO control register_4 SCFCR_4 16 H'E8009018 16 communication interface with FIFO Page 2764 of 3092 FIFO data count set register_4 SCFDR_4 16 H'E800901C 16 Serial port register_4 SCSPTR_4 16 H'E8009020 16 Line status register_4 SCLSR_4 16 H'E8009024 16 Serial extension mode register_4 SCEMR_4 16 H'E8009028 16 Serial mode register_5 SCSMR_5 16 H'E8009800 16 Bit rate register_5 SCBRR_5 8 H'E8009804 8 Serial control register_5 SCSCR_5 16 H'E8009808 16 Transmit FIFO data register_5 SCFTDR_5 8 H'E800980C 8 Serial status register_5 SCFSR_5 16 H'E8009810 16 Receive FIFO data register_5 SCFRDR_5 8 H'E8009814 8 FIFO control register_5 SCFCR_5 16 H'E8009818 16 FIFO data count set register_5 SCFDR_5 16 H'E800981C 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Serial Serial port register_5 SCSPTR_5 16 H'E8009820 16 Line status register_5 SCLSR_5 16 H'E8009824 16 Serial extension mode register_5 SCEMR_5 16 H'E8009828 16 Serial mode register_6 SCSMR_6 16 H'E800A000 16 Bit rate register_6 SCBRR_6 8 H'E800A004 8 Serial control register_6 SCSCR_6 16 H'E800A008 16 Transmit FIFO data register_6 SCFTDR_6 8 H'E800A00C 8 Serial status register_6 SCFSR_6 16 H'E800A010 16 Receive FIFO data register_6 SCFRDR_6 8 H'E800A014 8 FIFO control register_6 SCFCR_6 16 H'E800A018 16 FIFO data count set register_6 SCFDR_6 16 H'E800A01C 16 Serial port register_6 SCSPTR_6 16 H'E800A020 16 Line status register_6 SCLSR_6 16 H'E800A024 16 Serial extension mode register_6 SCEMR_6 16 H'E800A028 16 Serial mode register_7 SCSMR_7 16 H'E800A800 16 Bit rate register_7 SCBRR_7 8 H'E800A804 8 Serial control register_7 SCSCR_7 16 H'E800A808 16 Transmit FIFO data register_7 SCFTDR_7 8 H'E800A80C 8 Serial status register_7 SCFSR_7 16 H'E800A810 16 Receive FIFO data register_7 SCFRDR_7 8 H'E800A814 8 FIFO control register_7 SCFCR_7 16 H'E800A818 16 FIFO data count set register_7 SCFDR_7 16 H'E800A81C 16 Serial port register_7 SCSPTR_7 16 H'E800A820 16 Line status register_7 SCLSR_7 16 H'E800A824 16 Serial extension mode register_7 SCEMR_7 16 H'E800A828 16 Control register_0 SPCR_0 8 H'E800E000 8, 16 Slave select polarity register_0 SSLP_0 8 H'E800E001 8, 16 Pin control register_0 SPPCR_0 8 H'E800E002 8, 16 communication interface with FIFO Renesas serial peripheral interface Status register_0 SPSR_0 8 H'E800E003 8, 16 Data register_0 SPDR_0 32 H'E800E004 8, 16, 32 Sequence control register_0 SPSCR_0 8 H'E800E008 8, 16 Sequence status register_0 SPSSR_0 8 H'E800E009 8, 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2765 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Renesas serial Bit rate register_0 SPBR_0 8 H'E800E00A 8, 16 Data control register_0 SPDCR_0 8 H'E800E00B 8, 16 Clock delay register_0 SPCKD_0 8 H'E800E00C 8, 16 Slave select negation delay register_0 SSLND_0 8 H'E800E00D 8, 16 Next-access delay register_0 SPND_0 8 H'E800E00E 8 Command register_00 SPCMD_00 16 H'E800E010 16 Command register_01 SPCMD_01 16 H'E800E012 16 Command register_02 SPCMD_02 16 H'E800E014 16 Command register_03 SPCMD_03 16 H'E800E016 16 Buffer control register_0 SPBFCR_0 8 H'E800E020 8, 16 Buffer data count setting register_0 SPBFDR_0 16 H'E800E022 16 Control register_1 SPCR_1 8 H'E800E800 8, 16 peripheral interface Page 2766 of 3092 Slave select polarity register_1 SSLP_1 8 H'E800E801 8, 16 Pin control register_1 SPPCR_1 8 H'E800E802 8, 16 Status register_1 SPSR_1 8 H'E800E803 8, 16 Data register_1 SPDR_1 32 H'E800E804 8, 16, 32 Sequence control register_1 SPSCR_1 8 H'E800E808 8, 16 Sequence status register_1 SPSSR_1 8 H'E800E809 8, 16 Bit rate register_1 SPBR_1 8 H'E800E80A 8, 16 Data control register_1 SPDCR_1 8 H'E800E80B 8, 16 Clock delay register_1 SPCKD_1 8 H'E800E80C 8, 16 Slave select negation delay register_1 SSLND_1 8 H'E800E80D 8, 16 Next-access delay register_1 SPND_1 8 H'E800E80E 8 Command register_10 SPCMD_10 16 H'E800E810 16 Command register_11 SPCMD_11 16 H'E800E812 16 Command register_12 SPCMD_12 16 H'E800E814 16 Command register_13 SPCMD_13 16 H'E800E816 16 Buffer control register_1 SPBFCR_1 8 H'E800E820 8, 16 Buffer data count setting register_1 SPBFDR_1 16 H'E800E822 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Renesas quad Control register_0 SPCR_0 8 H'E8033800 8, 16, 32 Slave select polarity register_0 SSLP_0 8 H'E8033801 8, 16, 32 Pin control register_0 SPPCR_0 8 H'E8033802 8, 16, 32 Status register_0 SPSR_0 8 H'E8033803 8, 16, 32 Data register_0 SPDR_0 32 H'E8033804 8, 16, 32 Sequence control register_0 SPSCR_0 8 H'E8033808 8, 16, 32 Sequence status register_0 SPSSR_0 8 H'E8033809 8, 16, 32 Bit rate register_0 SPBR_0 8 H'E803380A 8, 16, 32 Data control register_0 SPDCR_0 8 H'E803380B 8, 16, 32 Clock delay register_0 SPCKD_0 8 H'E803380C 8, 16, 32 Slave select negation delay register_0 SSLND_0 8 H'E803380D 8, 16, 32 Next-access delay register_0 SPND_0 8 H'E803380E 8, 16, 32 Command register 0_0 SPCMD0_0 16 H'E8033810 16, 32 Command register 1_0 SPCMD1_0 16 H'E8033812 16, 32 Command register 2_0 SPCMD2_0 16 H'E8033814 16, 32 Command register 3_0 SPCMD3_0 16 H'E8033816 16, 32 Buffer control register_0 SPBFCR_0 8 H'E8033818 8, 16, 32 Buffer data count setting register_0 SPBDCR_0 16 H'E803381A 16, 32 Transfer data length multiplier setting SPBMUL0_0 32 H'E803381C 32 SPBMUL1_0 32 H'E8033820 32 SPBMUL2_0 32 H'E8033824 32 SPBMUL3_0 32 H'E8033828 32 Control register_1 SPCR_1 8 H'E8034000 8, 16, 32 Slave select polarity register_1 SSLP_1 8 H'E8034001 8, 16, 32 Pin control register_1 SPPCR_1 8 H'E8034002 8, 16, 32 Status register_1 SPSR_1 8 H'E8034003 8, 16, 32 Data register_1 SPDR_1 32 H'E8034004 8, 16, 32 Sequence control register_1 SPSCR_1 8 H'E8034008 8, 16, 32 Sequence status register_1 SPSSR_1 8 H'E8034009 8, 16, 32 serial peripheral interface register 0_0 Transfer data length multiplier setting register 1_0 Transfer data length multiplier setting register 2_0 Transfer data length multiplier setting register 3_0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2767 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Renesas quad Bit rate register_1 SPBR_1 8 H'E803400A 8, 16, 32 Data control register_1 SPDCR_1 8 H'E803400B 8, 16, 32 Clock delay register_1 SPCKD_1 8 H'E803400C 8, 16, 32 Slave select negation delay register_1 SSLND_1 8 H'E803400D 8, 16, 32 Next-access delay register_1 SPND_1 8 H'E803400E 8, 16, 32 Command register 0_1 SPCMD0_1 16 H'E8034010 16, 32 Command register 1_1 SPCMD1_1 16 H'E8034012 16, 32 Command register 2_1 SPCMD2_1 16 H'E8034014 16, 32 Command register 3_1 SPCMD3_1 16 H'E8034016 16, 32 Buffer control register_1 SPBFCR_1 8 H'E8034018 8, 16, 32 Buffer data count setting register_1 SPBDCR_1 16 H'E803401A 16, 32 Transfer data length multiplier setting SPBMUL0_1 32 H'E803401C 32 SPBMUL1_1 32 H'E8034020 32 SPBMUL2_1 32 H'E8034024 32 SPBMUL3_1 32 H'E8034028 32 Common control register CMNCR 32 H'FFFC1C00 32 SSL delay register SSLDR 32 H'FFFC1C04 32 Bit rate register SPBCR 32 H'FFFC1C08 32 Data read control register DRCR 32 H'FFFC1C0C 32 Data read command setting register DRCMR 32 H'FFFC1C10 32 Data read extended address setting DREAR 32 H'FFFC1C14 32 Data read option setting register DROPR 32 H'FFFC1C18 32 Data read enable setting register DRENR 32 H'FFFC1C1C 32 SPI mode control register SMCR 32 H'FFFC1C20 32 SPI mode command setting register SMCMR 32 H'FFFC1C24 32 SPI mode address setting register SMADR 32 H'FFFC1C28 32 serial peripheral interface register 0_1 Transfer data length multiplier setting register 1_1 Transfer data length multiplier setting register 2_1 Transfer data length multiplier setting register 3_1 SPI Multi I/O Bus Controller register Page 2768 of 3092 SPI mode option setting register SMOPR 32 H'FFFC1C2C 32 SPI mode enable setting register SMENR 32 H'FFFC1C30 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size SPI Multi I/O Bus SPI mode read data register 0 SMRDR0 32 H'FFFC1C38 8, 16, 32 SPI mode read data register 1 SMRDR1 32 H'FFFC1C3C 8, 16, 32 SPI mode write data register 0 SMWDR0 32 H'FFFC1C40 8, 16, 32 SPI mode write data register 1 SMWDR1 32 H'FFFC1C44 8, 16, 32 Controller I2C bus interface 3 Common status register CMNSR 32 H'FFFC1C48 32 I2C bus control register 1_0 ICCR1_0 8 H'FFFEE000 8 I2C bus control register 2_0 ICCR2_0 8 H'FFFEE001 8 2 ICMR_0 8 H'FFFEE002 8 2 ICIER_0 8 H'FFFEE003 8 2 I C bus status register_0 ICSR_0 8 H'FFFEE004 8 Slave address register_0 SAR_0 8 H'FFFEE005 8 ICDRT_0 8 H'FFFEE006 8 I C bus mode register_0 I C bus interrupt enable register_0 2 I C bus transmit data register_0 2 I C bus receive data register_0 ICDRR_0 8 H'FFFEE007 8 NF2CYC register_0 NF2CYC_0 8 H'FFFEE008 8 I2C bus control register 1_1 ICCR1_1 8 H'FFFEE400 8 2 ICCR2_1 8 H'FFFEE401 8 2 ICMR_1 8 H'FFFEE402 8 2 ICIER_1 8 H'FFFEE403 8 2 I C bus status register_1 ICSR_1 8 H'FFFEE404 8 Slave address register_1 SAR_1 8 H'FFFEE405 8 I C bus transmit data register_1 ICDRT_1 8 H'FFFEE406 8 I2C bus receive data register_1 ICDRR_1 8 H'FFFEE407 8 NF2CYC register_1 I C bus control register 2_1 I C bus mode register_1 I C bus interrupt enable register_1 2 NF2CYC_1 8 H'FFFEE408 8 2 ICCR1_2 8 H'FFFEE800 8 2 ICCR2_2 8 H'FFFEE801 8 2 ICMR_2 8 H'FFFEE802 8 2 ICIER_2 8 H'FFFEE803 8 2 I C bus status register_2 ICSR_2 8 H'FFFEE804 8 Slave address register_2 SAR_2 8 H'FFFEE805 8 I2C bus transmit data register_2 ICDRT_2 8 H'FFFEE806 8 I C bus receive data register_2 ICDRR_2 8 H'FFFEE807 8 NF2CYC register_2 NF2CYC_2 8 H'FFFEE808 8 I C bus control register 1_2 I C bus control register 2_2 I C bus mode register_2 I C bus interrupt enable register_2 2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2769 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name 2 I C bus interface 3 Register Name of Bits Address Size 2 ICCR1_3 8 H'FFFEEC00 8 2 ICCR2_3 8 H'FFFEEC01 8 2 ICMR_3 8 H'FFFEEC02 8 2 ICIER_3 8 H'FFFEEC03 8 I C bus control register 1_3 I C bus control register 2_3 I C bus mode register_3 I C bus interrupt enable register_3 2 I C bus status register_3 ICSR_3 8 H'FFFEEC04 8 Slave address register_3 SAR_3 8 H'FFFEEC05 8 I2C bus transmit data register_3 ICDRT_3 8 H'FFFEEC06 8 I C bus receive data register_3 ICDRR_3 8 H'FFFEEC07 8 NF2CYC register_3 NF2CYC_3 8 H'FFFEEC08 8 Control register_0 SSICR_0 32 H'FFFF0000 8, 16, 32 Status register_0 SSISR_0 32 H'FFFF0004 8, 16, 32 FIFO control register_0 SSIFCR_0 32 H'FFFF0010 8, 16, 32 FIFO status register_0 SSIFSR_0 32 H'FFFF0014 8, 16, 32 Transmit FIFO data register_0 SSIFTDR_0 32 H'FFFF0018 32 Receive FIFO data register_0 SSIFRDR_0 32 H'FFFF001C 32 TDM mode register_0 SSITDMR_0 32 H'FFFF0020 8, 16, 32 Control register_1 SSICR_1 32 H'FFFF0800 8, 16, 32 Status register_1 SSISR_1 32 H'FFFF0804 8, 16, 32 FIFO control register_1 SSIFCR_1 32 H'FFFF0810 8, 16, 32 FIFO status register_1 SSIFSR_1 32 H'FFFF0814 8, 16, 32 2 Serial sound interface Page 2770 of 3092 Access Abbreviation Transmit FIFO data register_1 SSIFTDR_1 32 H'FFFF0818 32 Receive FIFO data register_1 SSIFRDR_1 32 H'FFFF081C 32 TDM mode register_1 SSITDMR_1 32 H'FFFF0820 8, 16, 32 Control register_2 SSICR_2 32 H'FFFF1000 8, 16, 32 Status register_2 SSISR_2 32 H'FFFF1004 8, 16, 32 FIFO control register_2 SSIFCR_2 32 H'FFFF1010 8, 16, 32 FIFO status register_2 SSIFSR_2 32 H'FFFF1014 8, 16, 32 Transmit FIFO data register_2 SSIFTDR_2 32 H'FFFF1018 32 Receive FIFO data register_2 SSIFRDR_2 32 H'FFFF101C 32 TDM mode register_2 SSITDMR_2 32 H'FFFF1020 8, 16, 32 Control register_3 SSICR_3 32 H'FFFF1800 8, 16, 32 Status register_3 SSISR_3 32 H'FFFF1804 8, 16, 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Serial sound FIFO control register_3 SSIFCR_3 32 H'FFFF1810 8, 16, 32 FIFO status register_3 SSIFSR_3 32 H'FFFF1814 8, 16, 32 Transmit FIFO data register_3 SSIFTDR_3 32 H'FFFF1818 32 Receive FIFO data register_3 SSIFRDR_3 32 H'FFFF181C 32 TDM mode register_3 SSITDMR_3 32 H'FFFF1820 8, 16, 32 Control register_4 SSICR_4 32 H'FFFF2000 8, 16, 32 Status register_4 SSISR_4 32 H'FFFF2004 8, 16, 32 FIFO control register_4 SSIFCR_4 32 H'FFFF2010 8, 16, 32 FIFO status register_4 SSIFSR_4 32 H'FFFF2014 8, 16, 32 Transmit FIFO data register_4 SSIFTDR_4 32 H'FFFF2018 32 Receive FIFO data register_4 SSIFRDR_4 32 H'FFFF201C 32 TDM mode register_4 SSITDMR_4 32 H'FFFF2020 8, 16, 32 Control register_5 SSICR_5 32 H'FFFF2800 8, 16, 32 Status register_5 SSISR_5 32 H'FFFF2804 8, 16, 32 FIFO control register_5 SSIFCR_5 32 H'FFFF2810 8, 16, 32 FIFO status register_5 SSIFSR_5 32 H'FFFF2814 8, 16, 32 Transmit FIFO data register_5 SSIFTDR_5 32 H'FFFF2818 32 Receive FIFO data register_5 SSIFRDR_5 32 H'FFFF281C 32 TDM mode register_5 SSITDMR_5 32 H'FFFF2820 8, 16, 32 SIMDR 16 H'FFFF4800 16 Clock select register SISCR 16 H'FFFF4802 16 Transmit data assign register SITDAR 16 H'FFFF4804 16 Receive data assign register SIRDAR 16 H'FFFF4806 16 Control register SICTR 16 H'FFFF480C 16 FIFO control register SIFCTR 16 H'FFFF4810 16 Status register SISTR 16 H'FFFF4814 16 Interrupt enable register SIIER 16 H'FFFF4816 16 Transmit data register SITDR 32 H'FFFF4820 8, 16, 32 interface Serial I/O with FIFO Mode register Controller area network Receive data register SIRDR 32 H'FFFF4824 8, 16, 32 Master Control Register_0 MCR_0 16 H'FFFE5000 16 General Status Register_0 GSR_0 16 H'FFFE5002 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2771 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Controller area Bit Configuration Register 1_0 BCR1_0 16 H'FFFE5004 16 Bit Configuration Register 0_0 BCR0_0 16 H'FFFE5006 16 Interrupt Request Register_0 IRR_0 16 H'FFFE5008 16 Interrupt Mask Register_0 IMR_0 16 H'FFFE500A 16 network Transmit/Receive Error Counter_0 TEC_REC_0 16 H'FFFE500C 8, 16 Transmit Pending Register 1_0 TXPR1_0 16 H'FFFE5020 32 Transmit Pending Register 0_0 TXPR0_0 16 H'FFFE5022 16 Transmit Cancel Register 1_0 TXCR1_0 16 H'FFFE5028 16 Transmit Cancel Register 0_0 TXCR0_0 16 H'FFFE502A 16 Transmit Acknowledge Register 1_0 TXACK1_0 16 H'FFFE5030 16 Transmit Acknowledge Register 0_0 TXACK0_0 16 H'FFFE5032 16 Abort Acknowledge Register 1_0 ABACK1_0 16 H'FFFE5038 16 Abort Acknowledge Register 0_0 ABACK0_0 16 H'FFFE503A 16 Data Frame Receive Pending Register RXPR1_0 16 H'FFFE5040 16 RXPR0_0 16 H'FFFE5042 16 RFPR1_0 16 H'FFFE5048 16 RFPR0_0 16 H'FFFE504A 16 Mailbox Interrupt Mask Register 1_0 MBIMR1_0 16 H'FFFE5050 16 Mailbox Interrupt Mask Register 0_0 MBIMR0_0 16 H'FFFE5052 16 Unread Message Status Register 1_0 UMSR1_0 16 H'FFFE5058 16 Unread Message Status Register 0_0 UMSR0_0 16 H'FFFE505A 16 Timer Trigger Control Register 0_0 TTCR0_0 16 H'FFFE5080 16 Cycle Maximum/Tx-Enable Window CMAX_TEW_0 16 H'FFFE5084 16 Reference Trigger Offset Register_0 RFTROFF_0 16 H'FFFE5086 16 Timer Status Register_0 TSR_0 16 H'FFFE5088 16 Cycle Counter Register_0 CCR_0 16 H'FFFE508A 16 Timer Counter Register_0 TCNTR_0 16 H'FFFE508C 16 Cycle Time Register_0 CYCTR_0 16 H'FFFE5090 16 1_0 Data Frame Receive Pending Register 0_0 Remote Frame Receive Pending Register 1_0 Remote Frame Receive Pending Register 0_0 Register_0 Page 2772 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Controller area Reference Mark Register_0 RFMK_0 16 H'FFFE5094 16 Timer Compare Match Register 0_0 TCMR0_0 16 H'FFFE5098 16 Timer Compare Match Register 1_0 TCMR1_0 16 H'FFFE509C 16 Timer Compare Match Register 2_0 TCMR2_0 16 H'FFFE50A0 16 Tx-Trigger Time Selection Register_0 TTTSEL_0 16 H'FFFE50A4 16 Mailbox n Control 0 H_0 MBn_CONTROL0_H_0 16 H'FFFE5100 16, 32 (n = 0 to 31) (n  0 to 31) n32 Mailbox n Control 0 L_0 MBn_CONTROL0_L_0 16 H'FFFE5102 (n = 0 to 31) (n  0 to 31) n32 Mailbox n Local Acceptance Filter Mask MBn_LAFM0_0 0_0 (n = 0 to 31) (n  0 to 31) Mailbox n Local Acceptance Filter Mask MBn_LAFM1_0 1_0 (n = 0 to 31) (n  0 to 31) network Mailbox n data 01_0 (n = 0 to 31) MBn_DATA_01_0 16 MBn_DATA_23_0 16 MBn_DATA_45_0 16 MBn_DATA_67_0 16 MBn_CONTROL1_0 16 MBn_TIMESTAMP_0 (n = 0 to 15, 30, 31) (n  0 to 15, 30, 31) Mailbox n Trigger Time_0 (n = 24 to 30) MBn_TTT_0 16 MBn_TTCONTROL_0 H'FFFE510A 8, 16 H'FFFE510C 8, 16, 32 H'FFFE510E 8, 16 n32 16 H'FFFE5110 8, 16 n32 16 H'FFFE5112 16 n32 16 H'FFFE5114 16 n32 (n  24 to 30) Mailbox n TTControl_0 (n = 24 to 29) 8, 16, 32 n32 (n  0 to 31) Mailbox n Timestamp_0 H'FFFE5108 n32 (n  0 to 31) Mailbox n Control 1_0 (n = 0 to 31) 16 n32 (n  0 to 31) Mailbox n data 67_0 (n = 0 to 31) H'FFFE5106 n32 (n  0 to 31) Mailbox n data 45_0 (n = 0 to 31) 16, 32 n32 (n  0 to 31) Mailbox n data 23_0 (n = 0 to 31) H'FFFE5104 16 16 H'FFFE5116 16 n32 (n  24 to 29) Master Control Register_1 MCR_1 16 H'FFFE5800 16 General Status Register_1 GSR_1 16 H'FFFE5802 16 Bit Configuration Register 1_1 BCR1_1 16 H'FFFE5804 16 Bit Configuration Register 0_1 BCR0_1 16 H'FFFE5806 16 Interrupt Request Register_1 IRR_1 16 H'FFFE5808 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2773 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Controller area Interrupt Mask Register_1 IMR_1 16 H'FFFE580A 16 Transmit/Receive Error Counter_1 TEC_REC_1 16 H'FFFE580C 8, 16 Transmit Pending Register 1_1 TXPR1_1 16 H'FFFE5820 32 Transmit Pending Register 0_1 TXPR0_1 16 H'FFFE5822 16 Transmit Cancel Register 1_1 TXCR1_1 16 H'FFFE5828 16 Transmit Cancel Register 0_1 TXCR0_1 16 H'FFFE582A 16 Transmit Acknowledge Register 1_1 TXACK1_1 16 H'FFFE5830 16 Transmit Acknowledge Register 0_1 TXACK0_1 16 H'FFFE5832 16 Abort Acknowledge Register 1_1 ABACK1_1 16 H'FFFE5838 16 Abort Acknowledge Register 0_1 ABACK0_1 16 H'FFFE583A 16 Data Frame Receive Pending Register RXPR1_1 16 H'FFFE5840 16 RXPR0_1 16 H'FFFE5842 16 RFPR1_1 16 H'FFFE5848 16 RFPR0_1 16 H'FFFE584A 16 Mailbox Interrupt Mask Register 1_1 MBIMR1_1 16 H'FFFE5850 16 Mailbox Interrupt Mask Register 0_1 MBIMR0_1 16 H'FFFE5852 16 Unread Message Status Register 1_1 UMSR1_1 16 H'FFFE5858 16 Unread Message Status Register 0_1 UMSR0_1 16 H'FFFE585A 16 Timer Trigger Control Register 0_1 TTCR0_1 16 H'FFFE5880 16 Cycle Maximum/Tx-Enable Window CMAX_TEW_1 16 H'FFFE5884 16 Reference Trigger Offset Register_1 RFTROFF_1 16 H'FFFE5886 16 Timer Status Register_1 TSR_1 16 H'FFFE5888 16 Cycle Counter Register_1 CCR_1 16 H'FFFE588A 16 Timer Counter Register_1 TCNTR_1 16 H'FFFE588C 16 Cycle Time Register_1 CYCTR_1 16 H'FFFE5890 16 Reference Mark Register_1 RFMK_1 16 H'FFFE5894 16 Timer Compare Match Register 0_1 TCMR0_1 16 H'FFFE5898 16 Timer Compare Match Register 1_1 TCMR1_1 16 H'FFFE589C 16 network 1_1 Data Frame Receive Pending Register 0_1 Remote Frame Receive Pending Register 1_1 Remote Frame Receive Pending Register 0_1 Register_1 Page 2774 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Controller area Timer Compare Match Register 2_1 TCMR2_1 16 H'FFFE58A0 16 Tx-Trigger Time Selection Register_1 TTTSEL_1 16 H'FFFE58A4 16 Mailbox n Control 0 H_1 (n = 0 to 31) MBn_CONTROL0_H_1 16 H'FFFE5900 16, 32 (n = 0 to 31) n32 MBn_CONTROL0_L_1 16 H'FFFE5902 (n = 0 to 31) n32 network Mailbox n Control 0 L_1 (n = 0 to 31) Mailbox n Local Acceptance Filter Mask MBn_LAFM0_1 0_1 (n = 0 to 31) (n = 0 to 31) Mailbox n Local Acceptance Filter Mask MBn_LAFM1_1 1_1 (n = 0 to 31) (n = 0 to 31) Mailbox n data 01_1 (n = 0 to 31) MBn_DATA_01_1 16 MBn_DATA_23_1 16 MBn_DATA_45_1 16 MBn_DATA_67_1 16 MBn_CONTROL 16 MBn_TIMESTAMP_1 (n = 0 to 15, 30, 31) (n = 0 to 15, 30, 31) Mailbox n Trigger Time_1 (n = 24 to 30) MBn_TTT_1 16 MBn_TTCONTROL_1 H'FFFE590A 8, 16 H'FFFE590C 8, 16, 32 H'FFFE590E 8, 16 n32 16 H'FFFE5910 8, 16 n32 16 H'FFFE5912 16 n32 16 H'FFFE5914 16 n32 (n = 24 to 30) Mailbox n TTControl_1 (n = 24 to 29) 8, 16, 32 n32 1_1 (n = 0 to 31) Mailbox n Timestamp_1 H'FFFE5908 n32 (n = 0 to 31) Mailbox n Control 1_1 (n = 0 to 31) 16 n32 (n = 0 to 31) Mailbox n data 67_1 (n = 0 to 31) H'FFFE5906 n32 (n = 0 to 31) Mailbox n data 45_1 (n = 0 to 31) 16, 32 n32 (n = 0 to 31) Mailbox n data 23_1 (n = 0 to 31) H'FFFE5904 16 16 H'FFFE5916 16 n32 (n = 24 to 29) Master Control Register_2 MCR_2 16 H'FFFED800 16 General Status Register_2 GSR_2 16 H'FFFED802 16 Bit Configuration Register 1_2 BCR1_2 16 H'FFFED804 16 Bit Configuration Register 0_2 BCR0_2 16 H'FFFED806 16 Interrupt Request Register_2 IRR_2 16 H'FFFED808 16 Interrupt Mask Register_2 IMR_2 16 H'FFFED80A 16 Transmit/Receive Error Counter_2 TEC_REC_2 16 H'FFFED80C 8, 16 Transmit Pending Register 1_2 TXPR1_2 16 H'FFFED820 32 Transmit Pending Register 0_2 TXPR0_2 16 H'FFFED822 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2775 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Controller area Transmit Cancel Register 1_2 TXCR1_2 16 H'FFFED828 16 Transmit Cancel Register 0_2 TXCR0_2 16 H'FFFED82A 16 Transmit Acknowledge Register 1_2 TXACK1_2 16 H'FFFED830 16 Transmit Acknowledge Register 0_2 TXACK0_2 16 H'FFFED832 16 Abort Acknowledge Register 1_2 ABACK1_2 16 H'FFFED838 16 Abort Acknowledge Register 0_2 ABACK0_2 16 H'FFFED83A 16 Data Frame Receive Pending Register RXPR1_2 16 H'FFFED840 16 RXPR0_2 16 H'FFFED842 16 RFPR1_2 16 H'FFFED848 16 RFPR0_2 16 H'FFFED84A 16 Mailbox Interrupt Mask Register 1_2 MBIMR1_2 16 H'FFFED850 16 Mailbox Interrupt Mask Register 0_2 MBIMR0_2 16 H'FFFED852 16 Unread Message Status Register 1_2 UMSR1_2 16 H'FFFED858 16 Unread Message Status Register 0_2 UMSR0_2 16 H'FFFED85A 16 Timer Trigger Control Register 0_2 TTCR0_2 16 H'FFFED880 16 Cycle Maximum/Tx-Enable Window CMAX_TEW_2 16 H'FFFED884 16 Reference Trigger Offset Register_2 RFTROFF_2 16 H'FFFED886 16 Timer Status Register_2 TSR_2 16 H'FFFED888 16 Cycle Counter Register_2 CCR_2 16 H'FFFED88A 16 Timer Counter Register_2 TCNTR_2 16 H'FFFED88C 16 Cycle Time Register_2 CYCTR_2 16 H'FFFED890 16 Reference Mark Register_2 RFMK_2 16 H'FFFED894 16 Timer Compare Match Register 0_2 TCMR0_2 16 H'FFFED898 16 Timer Compare Match Register 1_2 TCMR1_2 16 H'FFFED89C 16 Timer Compare Match Register 2_2 TCMR2_2 16 H'FFFED8A0 16 Tx-Trigger Time Selection Register_2 TTTSEL_2 16 H'FFFED8A4 16 Mailbox n Control 0 H_2 (n = 0 to 31) MBn_CONTROL0_H_2 16 H'FFFED900 16, 32 (n = 0 to 31) n32 network 1_2 Data Frame Receive Pending Register 0_2 Remote Frame Receive Pending Register 1_2 Remote Frame Receive Pending Register 0_2 Register_2 Page 2776 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name Register Name Controller area Mailbox n Control 0 L_2 (n = 0 to 31) network Abbreviation Access Address Size MBn_CONTROL0_L_2 16 H'FFFED902 16 (n = 0 to 31) n32 Mailbox n Local Acceptance Filter Mask MBn_LAFM0_2 0_2 (n = 0 to 31) of Bits 16 H'FFFED904 16, 32 n32 (n = 0 to 31) Mailbox n Local Acceptance Filter Mask MBn_LAFM1_2 1_2 (n = 0 to 31) (n = 0 to 31) Mailbox n data 01_2 (n = 0 to 31) MBn_DATA_01_2 16 MBn_DATA_23_2 16 MBn_DATA_45_2 16 MBn_DATA_67_2 16 MBn_CONTROL1_2 16 31) (n = 0 to 15, 30, 31) Mailbox n Trigger Time_2 (n = 24 to 30) MBn_TTT_2 16 MBn_TTCONTROL_2 16 IEBus control register IECTR 8, 16, 32 H'FFFED90E 8, 16 H'FFFED910 8, 16 H'FFFED912 16 n32 16 H'FFFED914 16 n32 16 H'FFFED916 16 n32 (n = 24 to 29) IEBusTM controller H'FFFED90C n32 (n = 24 to 30) Mailbox n TTControl_2 (n = 24 to 29) 8, 16 n32 (n = 0 to 31) Mailbox n Timestamp_2 (n = 0 to 15, 30, MBn_TIMESTAMP_2 H'FFFED90A n32 (n = 0 to 31) Mailbox n Control 1_2 (n = 0 to 31) 8, 16, 32 n32 (n = 0 to 31) Mailbox n data 67_2 (n = 0 to 31) H'FFFED908 n32 (n = 0 to 31) Mailbox n data 45_2 (n = 0 to 31) 16 n32 (n = 0 to 31) Mailbox n data 23_2 (n = 0 to 31) H'FFFED906 8 H'FFFEF000 8 IEBus command register IECMR 8 H'FFFEF001 8 IEBus master control register IEMCR 8 H'FFFEF002 8 IEBus master unit address register 1 IEAR1 8 H'FFFEF003 8 IEBus master unit address register 2 IEAR2 8 H'FFFEF004 8 IEBus slave address setting register 1 IESA1 8 H'FFFEF005 8 IEBus slave address setting register 2 IESA2 8 H'FFFEF006 8 IEBus transmit message length register IETBFL 8 H'FFFEF007 8 IEBus reception master address register IEMA1 8 H'FFFEF009 8 IEMA2 8 H'FFFEF00A 8 1 IEBus reception master address register 2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2777 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name TM IEBus controller Abbreviation of Bits Address Size IEBus receive control field register IERCTL 8 H'FFFEF00B 8 IEBus receive message length register IERBFL 8 H'FFFEF00C 8 IEBus lock address register 1 IELA1 8 H'FFFEF00E 8 IEBus lock address register 2 IELA2 8 H'FFFEF00F 8 IEBus general flag register IEFLG 8 H'FFFEF010 8 IEBus transmit status register IETSR 8 H'FFFEF011 8 IEBus transmit interrupt enable register IEIET 8 H'FFFEF012 8 IEBus receive status register IERSR 8 H'FFFEF014 8 IEBus receive interrupt enable register IEIER 8 H'FFFEF015 8 IEBus clock select register IECKSR 8 H'FFFEF018 8 IEBus transmit data buffer registers 001 IETB001 to IETB128 8 H'FFFEF100 to 8 IERB001 to IERB128 8 H'FFFEF200 to 8 to 128 IEBus receive data buffer registers 001 H'FFFEF17F to 128 Renesas SPDIF interface Page 2778 of 3092 Access Register Name H'FFFEF27F Transmitter channel 1 audio register TLCA 32 H'E8012000 32 Transmitter channel 2 audio register TRCA 32 H'E8012004 32 Transmitter channel 1 status register TLCS 32 H'E8012008 32 Transmitter channel 2 status register TRCS 32 H'E801200C 32 Transmitter user data register TUI 32 H'E8012010 32 Receiver channel 1 audio register RLCA 32 H'E8012014 32 Receiver channel 2 audio register RRCA 32 H'E8012018 32 Receiver channel 1 status register RLCS 32 H'E801201C 32 Receiver channel 2 status register RRCS 32 H'E8012020 32 Receiver user data register RUI 32 H'E8012024 32 Control register CTRL 32 H'E8012028 32 Status register STAT 32 H'E801202C 32 Transmitter DMA audio data register TDAD 32 H'E8012030 32 Receiver DMA audio data register RDAD 32 H'E8012034 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size CD-ROM decoder Enable control register CROMEN 8 H'E8005000 8 8 H'E8005001 8 Sync code-based synchronization control CROMSY0 register Decoding mode control register CROMCTL0 8 H'E8005002 8 EDC/ECC check control register CROMCTL1 8 H'E8005003 8 Automatic decoding stop control register CROMCTL3 8 H'E8005005 8 Decoding option setting control register CROMCTL4 8 H'E8005006 8 HEAD20 to HEAD22 representation CROMCTL5 8 H'E8005007 8 Sync code status register CROMST0 8 H'E8005008 8 Post-ECC header error status register CROMST1 8 H'E8005009 8 Post-ECC subheader error status CROMST3 8 H'E800500B 8 CROMST4 8 H'E800500C 8 CROMST5 8 H'E800500D 8 ECC/EDC error status register CROMST6 8 H'E800500E 8 Buffer status register CBUFST0 8 H'E8005014 8 Decoding stoppage source status CBUFST1 8 H'E8005015 8 Buffer overflow status register CBUFST2 8 H'E8005016 8 Pre-ECC correction header: minutes HEAD00 8 H'E8005018 8 HEAD01 8 H'E8005019 8 Pre-ECC correction header: frames (1/75 HEAD02 8 H'E800501A 8 HEAD03 8 H'E800501B 8 SHEAD00 8 H'E800501C 8 SHEAD01 8 H'E800501D 8 control register register Header/subheader validity check status register Mode determination and link sector detection status register register data register Pre-ECC correction header: seconds data register second) data register Pre-ECC correction header: mode data register Pre-ECC correction subheader: file number (byte 16) data register Pre-ECC correction subheader: channel number (byte 17) data register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2779 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name CD-ROM decoder Access Register Name Abbreviation of Bits Address Size Pre-ECC correction subheader: sub- SHEAD02 8 H'E800501E 8 SHEAD03 8 H'E800501F 8 SHEAD04 8 H'E8005020 8 SHEAD05 8 H'E8005021 8 SHEAD06 8 H'E8005022 8 SHEAD07 8 H'E8005023 8 HEAD20 8 H'E8005024 8 HEAD21 8 H'E8005025 8 HEAD22 8 H'E8005026 8 HEAD23 8 H'E8005027 8 SHEAD20 8 H'E8005028 8 Post-ECC correction subheader: channel SHEAD21 8 H'E8005029 8 SHEAD22 8 H'E800502A 8 SHEAD23 8 H'E800502B 8 SHEAD24 8 H'E800502C 8 Post-ECC correction subheader: channel SHEAD25 8 H'E800502D 8 SHEAD26 8 H'E800502E 8 SHEAD27 8 H'E800502F 8 mode (byte 18) data register Pre-ECC correction subheader: data type (byte 19) data register Pre-ECC correction subheader: file number (byte 20) data register Pre-ECC correction subheader: channel number (byte 21) data register Pre-ECC correction subheader: submode (byte 22) data register Pre-ECC correction subheader: data type (byte 23) data register Post-ECC correction header: minutes data register Post-ECC correction header: seconds data register Post-ECC correction header: frames (1/75 second) data register Post-ECC correction header: mode data register Post-ECC correction subheader: file number (byte 16) data register number (byte 17) data register Post-ECC correction subheader: submode (byte 18) data register Post-ECC correction subheader: data type (byte 19) data register Post-ECC correction subheader: file number (byte 20) data register number (byte 21) data register Post-ECC correction subheader: submode (byte 22) data register Post-ECC correction subheader: data type (byte 23) data register Page 2780 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name CD-ROM decoder Access Register Name Abbreviation of Bits Address Size Automatic buffering setting control CBUFCTL0 8 H'E8005040 8 CBUFCTL1 8 H'E8005041 8 CBUFCTL2 8 H'E8005042 8 CBUFCTL3 8 H'E8005043 8 CROMST0M 8 H'E8005045 8 CD-ROM decoder reset control register ROMDECRST 8 H'E8005100 8 CD-ROM decoder reset status register RSTSTAT 8 H'E8005101 8 Serial sound interface data control SSI 8 H'E8005102 8 Interrupt flag register INTHOLD 8 H'E8005108 8 Interrupt source mask control register INHINT 8 H'E8005109 8 CD-ROM decoder stream data input STRMDIN0 16 H'E8005200 16, 32* STRMDIN2 16 H'E8005202 16 STRMDOUT0 16 H'E8005204 16, 32 A/D data register A ADDRA 16 H'E8005800 16 A/D data register B ADDRB 16 H'E8005802 16 A/D data register C ADDRC 16 H'E8005804 16 A/D data register D ADDRD 16 H'E8005806 16 A/D data register E ADDRE 16 H'E8005808 16 register Automatic buffering start sector setting: minutes control register Automatic buffering start sector setting: seconds control register Automatic buffering start sector setting: frames control register ISY interrupt source mask control register register register CD-ROM decoder stream data input register CD-ROM decoder stream data output register A/D converter A/D data register F ADDRF 16 H'E800580A 16 A/D data register G ADDRG 16 H'E800580C 16 A/D data register H ADDRH 16 H'E800580E 16 A/D control/status register ADCSR 16 H'E8005820 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2781 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size NAND flash Common control register FLCMNCR 32 H'FFFF4000 32 Command control register FLCMDCR 32 H'FFFF4004 32 Command code register FLCMCDR 32 H'FFFF4008 32 Address register FLADR 32 H'FFFF400C 32 memory controller USB 2.0 host/function module Page 2782 of 3092 Address register 2 FLADR2 32 H'FFFF403C 32 Data register FLDATAR 32 H'FFFF4010 32 Data counter register FLDTCNTR 32 H'FFFF4014 32 Interrupt DMA control register FLINTDMACR 32 H'FFFF4018 32 Ready busy timeout setting register FLBSYTMR 32 H'FFFF401C 32 Ready busy timeout counter FLBSYCNT 32 H'FFFF4020 32 Data FIFO register FLDTFIFO 32 H'FFFF4050 32 Control code FIFO register FLECFIFO 32 H'FFFF4060 32 Transfer control register FLTRCR 8 H'FFFF402C 8 Bus hold time setting register FLHOLDCR 32 H'FFFF4038 32 System configuration control register SYSCFG 16 H'E8010000 16 CPU bus wait setting register BUSWAIT 16 H'E8010002 16 System configuration status register SYSSTS 16 H'E8010004 16 Device state control register DVSTCTR 16 H'E8010008 16 Test mode register TESTMODE 16 H'E801000C 16 DMA0-FIFO bus configuration register D0FBCFG 16 H'E8010010 16 DMA1-FIFO bus configuration register D1FBCFG 16 H'E8010012 16 CFIFO port register CFIFO 32 H'E8010014 8, 16, 32 D0FIFO port register D0FIFO 32 H'E8010018 8, 16, 32 D1FIFO port register D1FIFO 32 H'E801001C 8, 16, 32 CFIFO port select register CFIFOSEL 16 H'E8010020 16 CFIFO port control register CFIFOCTR 16 H'E8010022 16 D0FIFO port select register D0FIFOSEL 16 H'E8010028 16 D0FIFO port control register D0FIFOCTR 16 H'E801002A 16 D1FIFO port select register D1FIFOSEL 16 H'E801002C 16 D1FIFO port control register D1FIFOCTR 16 H'E801002E 16 Interrupt enable register 0 INTENB0 16 H'E8010030 16 Interrupt enable register 1 INTENB1 16 H'E8010032 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size USB 2.0 BRDY interrupt enable register BRDYENB 16 H'E8010036 16 NRDY interrupt enable register NRDYENB 16 H'E8010038 16 BEMP interrupt enable register BEMPENB 16 H'E801003A 16 SOF output configuration register SOFCFG 16 H'E801003C 16 Interrupt status register 0 INTSTS0 16 H'E8010040 16 Interrupt status register 1 INTSTS1 16 H'E8010042 16 BRDY interrupt status register BRDYSTS 16 H'E8010046 16 NRDY interrupt status register NRDYSTS 16 H'E8010048 16 BEMP interrupt status register BEMPSTS 16 H'E801004A 16 Frame number register FRMNUM 16 H'E801004C 16 Frame number register UFRMNUM 16 H'E801004E 16 USB address register USBADDR 16 H'E8010050 16 USB request type register USBREQ 16 H'E8010054 16 USB request value register USBVAL 16 H'E8010056 16 USB request index register USBINDX 16 H'E8010058 16 USB request length register USBLENG 16 H'E801005A 16 DCP configuration register DCPCFG 16 H'E801005C 16 DCP maximum packet size register DCPMAXP 16 H'E801005E 16 DCP control register DCPCTR 16 H'E8010060 16 Pipe window select register PIPESEL 16 H'E8010064 16 host/function module Pipe configuration register PIPECFG 16 H'E8010068 16 Pipe buffer setting register PIPEBUF 16 H'E801006A 16 Pipe maximum packet size register PIPEMAXP 16 H'E801006C 16 Pipe cycle control register PIPEPERI 16 H'E801006E 16 Pipe 1 control register PIPE1CTR 16 H'E8010070 16 Pipe 2 control register PIPE2CTR 16 H'E8010072 16 Pipe 3 control register PIPE3CTR 16 H'E8010074 16 Pipe 4 control register PIPE4CTR 16 H'E8010076 16 Pipe 5 control register PIPE5CTR 16 H'E8010078 16 Pipe 6 control register PIPE6CTR 16 H'E801007A 16 Pipe 7 control register PIPE7CTR 16 H'E801007C 16 Pipe 8 control register PIPE8CTR 16 H'E801007E 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2783 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size USB 2.0 Pipe 9 control register PIPE9CTR 16 H'E8010080 16 Pipe 1 transaction counter enable PIPE1TRE 16 H'E8010090 16 Pipe 1 transaction counter register PIPE1TRN 16 H'E8010092 16 Pipe 2 transaction counter enable PIPE2TRE 16 H'E8010094 16 Pipe 2 transaction counter register PIPE2TRN 16 H'E8010096 16 Pipe 3 transaction counter enable PIPE3TRE 16 H'E8010098 16 host/function module register register register Pipe 3 transaction counter register PIPE3TRN 16 H'E801009A 16 Pipe 4 transaction counter enable PIPE4TRE 16 H'E801009C 16 Pipe 4 transaction counter register PIPE4TRN 16 H'E801009E 16 Pipe 5 transaction counter enable PIPE5TRE 16 H'E80100A0 16 Pipe 5 transaction counter register PIPE5TRN 16 H'E80100A2 16 Device address 0 configuration register DEVADD0 16 H'E80100D0 16 Device address 1 configuration register DEVADD1 16 H'E80100D2 16 Device address 2 configuration register DEVADD2 16 H'E80100D4 16 Device address 3 configuration register DEVADD3 16 H'E80100D6 16 Device address 4 configuration register DEVADD4 16 H'E80100D8 16 Device address 5 configuration register DEVADD5 16 H'E80100DA 16 Device address 6 configuration register DEVADD6 16 H'E80100DC 16 Device address 7 configuration register DEVADD7 16 H'E80100DE 16 Device address 8 configuration register DEVADD8 16 H'E80100E0 16 Device address 9 configuration register DEVADD9 16 H'E80100E2 16 Device address A configuration register DEVADDA 16 H'E80100E4 16 ADC control register 1 ADCCR1 16 H'FFFFA008 16 Timing generation control register 1 TGCR1 16 H'FFFFA00E 16 Timing generation control register 2 TGCR2 16 H'FFFFA010 16 Timing generation control register 3 TGCR3 16 H'FFFFA012 16 register register Digital video decoder Page 2784 of 3092 Sync separation control register 1 SYNSCR1 16 H'FFFFA01A 16 Sync separation control register 2 SYNSCR2 16 H'FFFFA01C 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Digital video Sync separation control register 3 SYNSCR3 16 H'FFFFA01E 16 Sync separation control register 4 SYNSCR4 16 H'FFFFA020 16 Sync separation control register 5 SYNSCR5 16 H'FFFFA022 16 Horizontal AFC control register 1 HAFCCR1 16 H'FFFFA024 16 Horizontal AFC control register 2 HAFCCR2 16 H'FFFFA026 16 Horizontal AFC control register 3 HAFCCR3 16 H'FFFFA028 16 Vertical countdown control register 1 VCDWCR1 16 H'FFFFA02A 16 Digital clamp control register 1 DCPCR1 16 H'FFFFA030 16 Digital clamp control register 2 DCPCR2 16 H'FFFFA032 16 Digital clamp control register 3 DCPCR3 16 H'FFFFA034 16 Digital clamp control register 4 DCPCR4 16 H'FFFFA036 16 Digital clamp control register 5 DCPCR5 16 H'FFFFA038 16 Digital clamp control register 6 DCPCR6 16 H'FFFFA03A 16 Digital clamp control register 7 DCPCR7 16 H'FFFFA03C 16 Digital clamp control register 8 DCPCR8 16 H'FFFFA03E 16 Noise detection control register NSDCR 16 H'FFFFA040 16 Burst lock/chroma decoding control BTLCR 16 H'FFFFA042 16 Burst gate pulse control register BTGPCR 16 H'FFFFA044 16 ACC control register 1 ACCCR1 16 H'FFFFA046 16 ACC control register 2 ACCCR2 16 H'FFFFA048 16 ACC control register 3 ACCCR3 16 H'FFFFA04A 16 TINT control register TINTCR 16 H'FFFFA04C 16 Y/C delay/chroma decoding control YCDCR 16 H'FFFFA04E 16 AGC control register 1 AGCCR1 16 H'FFFFA050 16 AGC control register 2 AGCCR2 16 H'FFFFA052 16 Peak limiter control register PKLIMITCR 16 H'FFFFA054 16 Over-range control register 1 RGORCR1 16 H'FFFFA056 16 Over-range control register 2 RGORCR2 16 H'FFFFA058 16 Over-range control register 3 RGORCR3 16 H'FFFFA05A 16 Over-range control register 4 RGORCR4 16 H'FFFFA05C 16 decoder register register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2785 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Digital video Over-range control register 5 RGORCR5 16 H'FFFFA05E 16 Over-range control register 6 RGORCR6 16 H'FFFFA060 16 Over-range control register 7 RGORCR7 16 H'FFFFA062 16 Feedback control register for horizontal AFCPFCR 16 H'FFFFA07C 16 Register update enable register RUPDCR 16 H'FFFFA07E 16 Sync separation status/vertical cycle VSYNCSR 16 H'FFFFA080 16 Horizontal cycle read register HSYNCSR 16 H'FFFFA082 16 Digital clamp read register 1 DCPSR1 16 H'FFFFA084 16 Digital clamp read register 2 DCPSR2 16 H'FFFFA086 16 Noise detection read register NSDSR 16 H'FFFFA08C 16 Chroma decoding read register 1 CROMASR1 16 H'FFFFA08E 16 Chroma decoding read register 2 CROMASR2 16 H'FFFFA090 16 Sync separation read register SYNCSSR 16 H'FFFFA092 16 AGC control read register 1 AGCCSR1 16 H'FFFFA094 16 AGC control read register 2 AGCCSR2 16 H'FFFFA096 16 Y/C separation control register 3 YCSCR3 16 H'FFFFA104 16 Y/C separation control register 4 YCSCR4 16 H'FFFFA106 16 Y/C separation control register 5 YCSCR5 16 H'FFFFA108 16 Y/C separation control register 6 YCSCR6 16 H'FFFFA10A 16 Y/C separation control register 7 YCSCR7 16 H'FFFFA10C 16 Y/C separation control register 8 YCSCR8 16 H'FFFFA10E 16 Y/C separation control register 9 YCSCR9 16 H'FFFFA110 16 Y/C separation control register 11 YCSCR11 16 H'FFFFA114 16 Y/C separation control register 12 YCSCR12 16 H'FFFFA116 16 Digital clamp control register 9 DCPCR9 16 H'FFFFA180 16 Chroma filter TAP coefficient (WA_F0) YCTWA_F0 16 H'FFFFA192 16 YCTWA_F1 16 H'FFFFA194 16 YCTWA_F2 16 H'FFFFA196 16 decoder AFC phase comparator read register register for Y/C separation Chroma filter TAP coefficient (WA_F1) register for Y/C separation Chroma filter TAP coefficient (WA_F2) register for Y/C separation Page 2786 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Digital video Chroma filter TAP coefficient (WA_F3) YCTWA_F3 16 H'FFFFA198 16 decoder register for Y/C separation YCTWA_F4 16 H'FFFFA19A 16 YCTWA_F5 16 H'FFFFA19C 16 YCTWA_F6 16 H'FFFFA19E 16 YCTWA_F7 16 H'FFFFA1A0 16 YCTWA_F8 16 H'FFFFA1A2 16 YCTWB_F0 16 H'FFFFA1A4 16 YCTWB_F1 16 H'FFFFA1A6 16 YCTWB_F2 16 H'FFFFA1A8 16 YCTWB_F3 16 H'FFFFA1AA 16 YCTWB_F4 16 H'FFFFA1AC 16 YCTWB_F5 16 H'FFFFA1AE 16 YCTWB_F6 16 H'FFFFA1B0 16 YCTWB_F7 16 H'FFFFA1B2 16 YCTWB_F8 16 H'FFFFA1B4 16 YCTNA_F0 16 H'FFFFA1B6 16 YCTNA_F1 16 H'FFFFA1B8 16 YCTNA_F2 16 H'FFFFA1BA 16 Chroma filter TAP coefficient (WA_F4) register for Y/C separation Chroma filter TAP coefficient (WA_F5) register for Y/C separation Chroma filter TAP coefficient (WA_F6) register for Y/C separation Chroma filter TAP coefficient (WA_F7) register for Y/C separation Chroma filter TAP coefficient (WA_F8) register for Y/C separation Chroma filter TAP coefficient (WB_F0) register for Y/C separation Chroma filter TAP coefficient (WB_F1) register for Y/C separation Chroma filter TAP coefficient (WB_F2) register for Y/C separation Chroma filter TAP coefficient (WB_F3) register for Y/C separation Chroma filter TAP coefficient (WB_F4) register for Y/C separation Chroma filter TAP coefficient (WB_F5) register for Y/C separation Chroma filter TAP coefficient (WB_F6) register for Y/C separation Chroma filter TAP coefficient (WB_F7) register for Y/C separation Chroma filter TAP coefficient (WB_F8) register for Y/C separation Chroma filter TAP coefficient (NA_F0) register for Y/C separation Chroma filter TAP coefficient (NA_F1) register for Y/C separation Chroma filter TAP coefficient (NA_F2) register for Y/C separation R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2787 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Digital video Chroma filter TAP coefficient (NA_F3) YCTNA_F3 16 H'FFFFA1BC 16 decoder register for Y/C separation YCTNA_F4 16 H'FFFFA1BE 16 YCTNA_F5 16 H'FFFFA1C0 16 YCTNA_F6 16 H'FFFFA1C2 16 YCTNA_F7 16 H'FFFFA1C4 16 YCTNA_F8 16 H'FFFFA1C6 16 YCTNB_F0 16 H'FFFFA1C8 16 YCTNB_F1 16 H'FFFFA1CA 16 YCTNB_F2 16 H'FFFFA1CC 16 YCTNB_F3 16 H'FFFFA1CE 16 YCTNB_F4 16 H'FFFFA1D0 16 YCTNB_F5 16 H'FFFFA1D2 16 YCTNB_F6 16 H'FFFFA1D4 16 YCTNB_F7 16 H'FFFFA1D6 16 YCTNB_F8 16 H'FFFFA1D8 16 YGAINCR 16 H'FFFFA200 16 CBGAINCR 16 H'FFFFA202 16 CRGAINCR 16 H'FFFFA204 16 PGA_UPDATE 16 H'FFFFA280 16 Chroma filter TAP coefficient (NA_F4) register for Y/C separation Chroma filter TAP coefficient (NA_F5) register for Y/C separation Chroma filter TAP coefficient (NA_F6) register for Y/C separation Chroma filter TAP coefficient (NA_F7) register for Y/C separation Chroma filter TAP coefficient (NA_F8) register for Y/C separation Chroma filter TAP coefficient (NB_F0) register for Y/C separation Chroma filter TAP coefficient (NB_F1) register for Y/C separation Chroma filter TAP coefficient (NB_F2) register for Y/C separation Chroma filter TAP coefficient (NB_F3) register for Y/C separation Chroma filter TAP coefficient (NB_F4) register for Y/C separation Chroma filter TAP coefficient (NB_F5) register for Y/C separation Chroma filter TAP coefficient (NB_F6) register for Y/C separation Chroma filter TAP coefficient (NB_F7) register for Y/C separation Chroma filter TAP coefficient (NB_F8) register for Y/C separation Luminance (Y) signal gain control register Color difference (CB) signal gain control register Color difference (CR) signal gain control register PGA register update Page 2788 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Digital video PGA control register PGACR 16 H'FFFFA282 16 ADC control register 2 ADCCR2 16 H'FFFFA284 16 Video display External input block register update INP_UPDATE 32 H'FFFF7400 16, 32 controller 4 control register INP_SEL_CNT 32 H'FFFF7404 16, 32 External input sync signal control register INP_EXT_SYNC_CNT 32 H'FFFF7408 16, 32 Vsync signal phase adjustment register INP_VSYNC_PH_ADJ 32 H'FFFF740C 16, 32 Sync signal delay adjustment register INP_DLY_ADJ 32 H'FFFF7410 16, 32 Image quality adjustment block register IMGCNT_UPDATE 32 H'FFFF7480 16, 32 IMGCNT_NR_ 32 H'FFFF7484 16, 32 32 H'FFFF7488 16, 32 32 H'FFFF74A0 16, 32 32 H'FFFF74A4 16, 32 32 H'FFFF74A8 16, 32 32 H'FFFF74AC 16, 32 32 H'FFFF74B0 16, 32 32 H'FFFF74B4 16, 32 32 H'FFFF74B8 16, 32 decoder Input select control register update control register NR control register 0 CNT0 NR control register 1 IMGCNT_NR_ CNT1 Image quality adjustment block matrix IMGCNT_MTX_ mode register MODE Image quality adjustment block matrix IMGCNT_MTX_ YG adjustment register 0 YG_ADJ0 Image quality adjustment block matrix IMGCNT_MTX_ YG adjustment register 1 YG_ADJ1 Image quality adjustment block matrix IMGCNT_MTX_ CBB adjustment register 0 CBB_ADJ0 Image quality adjustment block matrix IMGCNT_MTX_ CBB adjustment register 1 CBB_ADJ1 Image quality adjustment block matrix IMGCNT_MTX_ CRR adjustment register 0 CRR_ADJ0 Image quality adjustment block matrix IMGCNT_MTX_ CRR adjustment register 1 CRR_ADJ1 SCL0 register update control register SCL0_UPDATE 32 H'FFFF7500 16, 32 Mask control register SCL0_FRC1 32 H'FFFF7504 16, 32 Missing Vsync compensation control SCL0_FRC2 32 H'FFFF7508 16, 32 register Output sync select register SCL0_FRC3 32 H'FFFF750C 16, 32 Free-running period control register SCL0_FRC4 32 H'FFFF7510 16, 32 Output delay control register SCL0_FRC5 32 H'FFFF7514 16, 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2789 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Full-screen vertical size register SCL0_FRC6 32 H'FFFF7518 16, 32 Full-screen horizontal size register SCL0_FRC7 32 H'FFFF751C 16, 32 Field determination signal switching SCL0_FRC8 32 H'FFFF7520 16, 32 Vsync detection register SCL0_FRC9 32 H'FFFF7524 16, 32 Scaling-down control register SCL0_DS1 32 H'FFFF752C 16, 32 Vertical capture size register SCL0_DS2 32 H'FFFF7530 16, 32 Horizontal capture size register SCL0_DS3 32 H'FFFF7534 16, 32 Horizontal scale down register SCL0_DS4 32 H'FFFF7538 16, 32 Initial vertical phase register SCL0_DS5 32 H'FFFF753C 16, 32 Vertical scaling register SCL0_DS6 32 H'FFFF7540 16, 32 Scaling-down control block output size SCL0_DS7 32 H'FFFF7544 16, 32 Scaling-up control register SCL0_US1 32 H'FFFF7548 16, 32 Output image vertical size register SCL0_US2 32 H'FFFF754C 16, 32 Output image horizontal size register SCL0_US3 32 H'FFFF7550 16, 32 Scaling-up control block input size SCL0_US4 32 H'FFFF7554 16, 32 Horizontal scale up register SCL0_US5 32 H'FFFF7558 16, 32 Horizontal scale up initial phase register SCL0_US6 32 H'FFFF755C 16, 32 Trimming register SCL0_US7 32 H'FFFF7560 16, 32 Frame buffer read select register SCL0_US8 32 H'FFFF7564 16, 32 Background color register SCL0_OVR1 32 H'FFFF756C 16, 32 SCL1 register update control register SCL1_UPDATE 32 H'FFFF7580 16, 32 Writing mode register SCL1_WR1 32 H'FFFF7588 16, 32 Write address register 1 SCL1_WR2 32 H'FFFF758C 16, 32 Write address register 2 SCL1_WR3 32 H'FFFF7590 16, 32 Write address register 3 SCL1_WR4 32 H'FFFF7594 16, 32 Frame sub-sampling register SCL1_WR5 32 H'FFFF759C 16, 32 Bit reduction register SCL1_WR6 32 H'FFFF75A0 16, 32 Write detection register SCL1_WR7 32 H'FFFF75A4 16, 32 Graphics 1 register update control GR1_UPDATE 32 H'FFFF7600 16, 32 controller 4 register (R version only) register register register Page 2790 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Frame buffer read control register GR1_FLM_RD 32 H'FFFF7604 16, 32 controller 4 (Graphics 1) GR1_FLM1 32 H'FFFF7608 16, 32 GR1_FLM2 32 H'FFFF760C 16, 32 GR1_FLM3 32 H'FFFF7610 16, 32 GR1_FLM4 32 H'FFFF7614 16, 32 GR1_FLM5 32 H'FFFF7618 16, 32 GR1_FLM6 32 H'FFFF761C 16, 32 GR1_AB1 32 H'FFFF7620 16, 32 GR1_AB2 32 H'FFFF7624 16, 32 GR1_AB3 32 H'FFFF7628 16, 32 GR1_AB7 32 H'FFFF7638 16, 32 GR1_AB8 32 H'FFFF763C 16, 32 GR1_AB9 32 H'FFFF7640 16, 32 GR1_AB10 32 H'FFFF7644 16, 32 GR1_AB11 32 H'FFFF7648 16, 32 GR1_BASE 32 H'FFFF764C 16, 32 GR1_CLUT 32 H'FFFF7650 16, 32 32 H'FFFF7680 16, 32 Frame buffer control register 1 (Graphics 1) Frame buffer control register 2 (Graphics 1) Frame buffer control register 3 (Graphics 1) Frame buffer control register 4 (Graphics 1) Frame buffer control register 5 (Graphics 1) Frame buffer control register 6 (Graphics 1) Alpha blending control register 1 (Graphics 1) Alpha blending control register 2 (Graphics 1) Alpha blending control register 3 (Graphics 1) Alpha blending control register 7 (Graphics 1) Alpha blending control register 8 (Graphics 1) Alpha blending control register 9 (Graphics 1) Alpha blending control register 10 (Graphics 1) Alpha blending control register 11 (Graphics 1) Background color control register (Graphics 1) CLUT table control register (Graphics 1) Register update control register in image ADJ_UPDATE quality improver Black stretch register ADJ_BKSTR_SET 32 H'FFFF7684 16, 32 Enhancer timing adjustment register 1 ADJ_ENH_TIM1 32 H'FFFF7688 16, 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2791 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Enhancer timing adjustment register 2 ADJ_ENH_TIM2 32 H'FFFF768C 16, 32 Enhancer timing adjustment register 3 ADJ_ENH_TIM3 32 H'FFFF7690 16, 32 Enhancer sharpness register 1 ADJ_ENH_SHP1 32 H'FFFF7694 16, 32 Enhancer sharpness register 2 ADJ_ENH_SHP2 32 H'FFFF7698 16, 32 Enhancer sharpness register 3 ADJ_ENH_SHP3 32 H'FFFF769C 16, 32 Enhancer sharpness register 4 ADJ_ENH_SHP4 32 H'FFFF76A0 16, 32 Enhancer sharpness register 5 ADJ_ENH_SHP5 32 H'FFFF76A4 16, 32 Enhancer sharpness register 6 ADJ_ENH_SHP6 32 H'FFFF76A8 16, 32 Enhancer LTI register 1 ADJ_ENH_LTI1 32 H'FFFF76AC 16, 32 Enhancer LTI register 2 ADJ_ENH_LTI2 32 H'FFFF76B0 16, 32 Matrix mode register in image quality ADJ_MTX_MODE 32 H'FFFF76B4 16, 32 ADJ_MTX_YG_ADJ0 32 H'FFFF76B8 16, 32 ADJ_MTX_YG_ADJ1 32 H'FFFF76BC 16, 32 ADJ_MTX_CBB_ADJ0 32 H'FFFF76C0 16, 32 ADJ_MTX_CBB_ADJ1 32 H'FFFF76C4 16, 32 ADJ_MTX_CRR_ADJ0 32 H'FFFF76C8 16, 32 ADJ_MTX_CRR_ADJ1 32 H'FFFF76CC 16, 32 GR2_UPDATE 32 H'FFFF7700 16, 32 GR2_FLM_RD 32 H'FFFF7704 16, 32 GR2_FLM1 32 H'FFFF7708 16, 32 GR2_FLM2 32 H'FFFF770C 16, 32 GR2_FLM3 32 H'FFFF7710 16, 32 controller 4 improver Matrix YG control register 0 in image quality improver Matrix YG control register 1 in image quality improver Matrix CBB control register 0 in image quality improver Matrix CBB control register 1 in image quality improver Matrix CRR control register 0 in image quality improver Matrix CRR control register 1 in image quality improver Graphics 2 register update control register Frame buffer read control register (Graphics 2) Frame buffer control register 1 (Graphics 2) Frame buffer control register 2 (Graphics 2) Frame buffer control register 3 (Graphics 2) Page 2792 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Frame buffer control register 4 GR2_FLM4 32 H'FFFF7714 16, 32 controller 4 (Graphics 2) GR2_FLM5 32 H'FFFF7718 16, 32 GR2_FLM6 32 H'FFFF771C 16, 32 GR2_AB1 32 H'FFFF7720 16, 32 GR2_AB2 32 H'FFFF7724 16, 32 GR2_AB3 32 H'FFFF7728 16, 32 GR2_AB4 32 H'FFFF772C 16, 32 GR2_AB5 32 H'FFFF7730 16, 32 GR2_AB6 32 H'FFFF7734 16, 32 GR2_AB7 32 H'FFFF7738 16, 32 GR2_AB8 32 H'FFFF773C 16, 32 GR2_AB9 32 H'FFFF7740 16, 32 GR2_AB10 32 H'FFFF7744 16, 32 GR2_AB11 32 H'FFFF7748 16, 32 GR2_BASE 32 H'FFFF774C 16, 32 CLUT table control register (Graphics 2) GR2_CLUT 32 H'FFFF7750 16, 32 Status monitor register (Graphics 2) GR2_MON 32 H'FFFF7754 16, 32 Graphics 3 register update control GR3_UPDATE 32 H'FFFF7780 16, 32 GR3_FLM_RD 32 H'FFFF7784 16, 32 Frame buffer control register 5 (Graphics 2) Frame buffer control register 6 (Graphics 2) Alpha blending control register 1 (Graphics 2) Alpha blending control register 2 (Graphics 2) Alpha blending control register 3 (Graphics 2) Alpha blending control register 4 (Graphics 2) Alpha blending control register 5 (Graphics 2) Alpha blending control register 6 (Graphics 2) Alpha blending control register 7 (Graphics 2) Alpha blending control register 8 (Graphics 2) Alpha blending control register 9 (Graphics 2) Alpha blending control register 10 (Graphics 2) Alpha blending control register 11 (Graphics 2) Background color control register (Graphics 2) register Frame buffer read control register (Graphics 3) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2793 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Frame buffer control register 1 GR3_FLM1 32 H'FFFF7788 16, 32 controller 4 (Graphics 3) GR3_FLM2 32 H'FFFF778C 16, 32 GR3_FLM3 32 H'FFFF7790 16, 32 GR3_FLM4 32 H'FFFF7794 16, 32 GR3_FLM5 32 H'FFFF7798 16, 32 GR3_FLM6 32 H'FFFF779C 16, 32 GR3_AB1 32 H'FFFF77A0 16, 32 GR3_AB2 32 H'FFFF77A4 16, 32 GR3_AB3 32 H'FFFF77A8 16, 32 GR3_AB4 32 H'FFFF77AC 16, 32 GR3_AB5 32 H'FFFF77B0 16, 32 GR3_AB6 32 H'FFFF77B4 16, 32 GR3_AB7 32 H'FFFF77B8 16, 32 GR3_AB8 32 H'FFFF77BC 16, 32 GR3_AB9 32 H'FFFF77C0 16, 32 GR3_AB10 32 H'FFFF77C4 16, 32 GR3_AB11 32 H'FFFF77C8 16, 32 GR3_BASE 32 H'FFFF77CC 16, 32 Frame buffer control register 2 (Graphics 3) Frame buffer control register 3 (Graphics 3) Frame buffer control register 4 (Graphics 3) Frame buffer control register 5 (Graphics 3) Frame buffer control register 6 (Graphics 3) Alpha blending control register 1 (Graphics 3) Alpha blending control register 2 (Graphics 3) Alpha blending control register 3 (Graphics 3) Alpha blending control register 4 (Graphics 3) Alpha blending control register 5 (Graphics 3) Alpha blending control register 6 (Graphics 3) Alpha blending control register 7 (Graphics 3) Alpha blending control register 8 (Graphics 3) Alpha blending control register 9 (Graphics 3) Alpha blending control register 10 (Graphics 3) Alpha blending control register 11 (Graphics 3) Background color control register (Graphics 3) Page 2794 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display CLUT table and interrupt control register GR3_CLUT_INT 32 H'FFFF77D0 16, 32 controller 4 (Graphics 3) Status monitor register (Graphics 3) GR3_MON 32 H'FFFF77D4 16, 32 Register update control register G in GAM_G_UPDATE 32 H'FFFF7800 16, 32 GAM_SW 32 H'FFFF7804 16, 32 GAM_G_LUT1 32 H'FFFF7808 16, 32 GAM_G_LUT2 32 H'FFFF780C 16, 32 GAM_G_LUT3 32 H'FFFF7810 16, 32 GAM_G_LUT4 32 H'FFFF7814 16, 32 GAM_G_LUT5 32 H'FFFF7818 16, 32 GAM_G_LUT6 32 H'FFFF781C 16, 32 GAM_G_LUT7 32 H'FFFF7820 16, 32 GAM_G_LUT8 32 H'FFFF7824 16, 32 GAM_G_LUT9 32 H'FFFF7828 16, 32 GAM_G_LUT10 32 H'FFFF782C 16, 32 GAM_G_LUT11 32 H'FFFF7830 16, 32 GAM_G_LUT12 32 H'FFFF7834 16, 32 GAM_G_LUT13 32 H'FFFF7838 16, 32 GAM_G_LUT14 32 H'FFFF783C 16, 32 GAM_G_LUT15 32 H'FFFF7840 16, 32 gamma correction block Function switch register in gamma correction block Table setting register G1 in gamma correction block Table setting register G2 in gamma correction block Table setting register G3 in gamma correction block Table setting register G4 in gamma correction block Table setting register G5 in gamma correction block Table setting register G6 in gamma correction block Table setting register G7 in gamma correction block Table setting register G8 in gamma correction block Table setting register G9 in gamma correction block Table setting register G10 in gamma correction block Table setting register G11 in gamma correction block Table setting register G12 in gamma correction block Table setting register G13 in gamma correction block Table setting register G14 in gamma correction block Table setting register G15 in gamma correction block R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2795 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Table setting register G16 in gamma GAM_G_LUT16 32 H'FFFF7844 16, 32 controller 4 correction block GAM_G_AREA1 32 H'FFFF7848 16, 32 GAM_G_AREA2 32 H'FFFF784C 16, 32 GAM_G_AREA3 32 H'FFFF7850 16, 32 GAM_G_AREA4 32 H'FFFF7854 16, 32 GAM_G_AREA5 32 H'FFFF7858 16, 32 GAM_G_AREA6 32 H'FFFF785C 16, 32 GAM_G_AREA7 32 H'FFFF7860 16, 32 GAM_G_AREA8 32 H'FFFF7864 16, 32 GAM_B_UPDATE 32 H'FFFF7880 16, 32 GAM_B_LUT1 32 H'FFFF7888 16, 32 GAM_B_LUT2 32 H'FFFF788C 16, 32 GAM_B_LUT3 32 H'FFFF7890 16, 32 GAM_B_LUT4 32 H'FFFF7894 16, 32 GAM_B_LUT5 32 H'FFFF7898 16, 32 GAM_B_LUT6 32 H'FFFF789C 16, 32 GAM_B_LUT7 32 H'FFFF78A0 16, 32 GAM_B_LUT8 32 H'FFFF78A4 16, 32 Area setting register G1 in gamma correction block Area setting register G2 in gamma correction block Area setting register G3 in gamma correction block Area setting register G4 in gamma correction block Area setting register G5 in gamma correction block Area setting register G6 in gamma correction block Area setting register G7 in gamma correction block Area setting register G8 in gamma correction block Register update control register B in gamma correction block Table setting register B1 in gamma correction block Table setting register B2 in gamma correction block Table setting register B3 in gamma correction block Table setting register B4 in gamma correction block Table setting register B5 in gamma correction block Table setting register B6 in gamma correction block Table setting register B7 in gamma correction block Table setting register B8 in gamma correction block Page 2796 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Table setting register B9 in gamma GAM_B_LUT9 32 H'FFFF78A8 16, 32 controller 4 correction block GAM_B_LUT10 32 H'FFFF78AC 16, 32 GAM_B_LUT11 32 H'FFFF78B0 16, 32 GAM_B_LUT12 32 H'FFFF78B4 16, 32 GAM_B_LUT13 32 H'FFFF78B8 16, 32 GAM_B_LUT14 32 H'FFFF78BC 16, 32 GAM_B_LUT15 32 H'FFFF78C0 16, 32 GAM_B_LUT16 32 H'FFFF78C4 16, 32 GAM_B_AREA1 32 H'FFFF78C8 16, 32 GAM_B_AREA2 32 H'FFFF78CC 16, 32 GAM_B_AREA3 32 H'FFFF78D0 16, 32 GAM_B_AREA4 32 H'FFFF78D4 16, 32 GAM_B_AREA5 32 H'FFFF78D8 16, 32 GAM_B_AREA6 32 H'FFFF78DC 16, 32 GAM_B_AREA7 32 H'FFFF78E0 16, 32 GAM_B_AREA8 32 H'FFFF78E4 16, 32 GAM_R_UPDATE 32 H'FFFF7900 16, 32 GAM_R_LUT1 32 H'FFFF7908 16, 32 Table setting register B10 in gamma correction block Table setting register B11 in gamma correction block Table setting register B12 in gamma correction block Table setting register B13 in gamma correction block Table setting register B14 in gamma correction block Table setting register B15 in gamma correction block Table setting register B16 in gamma correction block Area setting register B1 in gamma correction block Area setting register B2 in gamma correction block Area setting register B3 in gamma correction block Area setting register B4 in gamma correction block Area setting register B5 in gamma correction block Area setting register B6 in gamma correction block Area setting register B7 in gamma correction block Area setting register B8 in gamma correction block Register update control register R in gamma correction block Table setting register R1 in gamma correction block R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2797 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Table setting register R2 in gamma GAM_R_LUT2 32 H'FFFF790C 16, 32 controller 4 correction block GAM_R_LUT3 32 H'FFFF7910 16, 32 GAM_R_LUT4 32 H'FFFF7914 16, 32 GAM_R_LUT5 32 H'FFFF7918 16, 32 GAM_R_LUT6 32 H'FFFF791C 16, 32 GAM_R_LUT7 32 H'FFFF7920 16, 32 GAM_R_LUT8 32 H'FFFF7924 16, 32 GAM_R_LUT9 32 H'FFFF7928 16, 32 GAM_R_LUT10 32 H'FFFF792C 16, 32 GAM_R_LUT11 32 H'FFFF7930 16, 32 GAM_R_LUT12 32 H'FFFF7934 16, 32 GAM_R_LUT13 32 H'FFFF7938 16, 32 GAM_R_LUT14 32 H'FFFF793C 16, 32 GAM_R_LUT15 32 H'FFFF7940 16, 32 GAM_R_LUT16 32 H'FFFF7944 16, 32 GAM_R_AREA1 32 H'FFFF7948 16, 32 GAM_R_AREA2 32 H'FFFF794C 16, 32 GAM_R_AREA3 32 H'FFFF7950 16, 32 Table setting register R3 in gamma correction block Table setting register R4 in gamma correction block Table setting register R5 in gamma correction block Table setting register R6 in gamma correction block Table setting register R7 in gamma correction block Table setting register R8 in gamma correction block Table setting register R9 in gamma correction block Table setting register R10 in gamma correction block Table setting register R11 in gamma correction block Table setting register R12 in gamma correction block Table setting register R13 in gamma correction block Table setting register R14 in gamma correction block Table setting register R15 in gamma correction block Table setting register R16 in gamma correction block Area setting register R1 in gamma correction block Area setting register R2 in gamma correction block Area setting register R3 in gamma correction block Page 2798 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display Area setting register R4 in gamma GAM_R_AREA4 32 H'FFFF7954 16, 32 controller 4 correction block GAM_R_AREA5 32 H'FFFF7958 16, 32 GAM_R_AREA6 32 H'FFFF795C 16, 32 GAM_R_AREA7 32 H'FFFF7960 16, 32 GAM_R_AREA8 32 H'FFFF7964 16, 32 TCON register update control register TCON_UPDATE 32 H'FFFF7980 16, 32 TCON reference timing setting register TCON_TIM 32 H'FFFF7984 16, 32 TCON vertical timing setting register A1 TCON_TIM_STVA1 32 H'FFFF7988 16, 32 TCON vertical timing setting register A2 TCON_TIM_STVA2 32 H'FFFF798C 16, 32 TCON vertical timing setting register B1 TCON_TIM_STVB1 32 H'FFFF7990 16, 32 TCON vertical timing setting register B2 TCON_TIM_STVB2 32 H'FFFF7994 16, 32 TCON horizontal timing setting register TCON_TIM_STH1 32 H'FFFF7998 16, 32 TCON_TIM_STH2 32 H'FFFF799C 16, 32 TCON_TIM_STB1 32 H'FFFF79A0 16, 32 TCON_TIM_STB2 32 H'FFFF79A4 16, 32 TCON_TIM_CPV1 32 H'FFFF79A8 16, 32 TCON_TIM_CPV2 32 H'FFFF79AC 16, 32 TCON_TIM_POLA1 32 H'FFFF79B0 16, 32 TCON_TIM_POLA2 32 H'FFFF79B4 16, 32 TCON_TIM_POLB1 32 H'FFFF79B8 16, 32 TCON_TIM_POLB2 32 H'FFFF79BC 16, 32 Area setting register R5 in gamma correction block Area setting register R6 in gamma correction block Area setting register R7 in gamma correction block Area setting register R8 in gamma correction block STH1 TCON horizontal timing setting register STH2 TCON horizontal timing setting register STB1 TCON horizontal timing setting register STB2 TCON horizontal timing setting register CPV1 TCON horizontal timing setting register CPV2 TCON horizontal timing setting register POLA1 TCON horizontal timing setting register POLA2 TCON horizontal timing setting register POLB1 TCON horizontal timing setting register POLB2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2799 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Video display TCON data enable polarity setting TCON_TIM_DE 32 H'FFFF79C0 16, 32 controller 4 register 32 H'FFFF7A00 16, 32 Register update control register in output OUT_UPDATE controller Output interface register OUT_SET 32 H'FFFF7A04 16, 32 Brightness (DC) correction register 1 OUT_BRIGHT1 32 H'FFFF7A08 16, 32 Brightness (DC) correction register 2 OUT_BRIGHT2 32 H'FFFF7A0C 16, 32 Contrast (gain) correction register OUT_CONTRAST 32 H'FFFF7A10 16, 32 Panel dither register OUT_PDTHA 32 H'FFFF7A14 16, 32 Output phase control register OUT_CLK_PHASE 32 H'FFFF7A24 16, 32 Interrupt control register 1 SYSCNT_INT1 32 H'FFFF7A80 16, 32 Interrupt control register 2 SYSCNT_INT2 32 H'FFFF7A84 16, 32 Interrupt control register 3 SYSCNT_INT3 32 H'FFFF7A88 16, 32 Interrupt control register 4 SYSCNT_INT4 32 H'FFFF7A8C 16, 32 Panel clock control register SYSCNT_PANEL_CLK 16 H'FFFF7A90 16 CLUT table read select signal status SYSCNT_CLUT H'FFFF7A92 16 16 register Image renderer Page 2800 of 3092 Control register CR 32 H'FFFF3008 32 Status register SR 32 H'FFFF300C 32 Status clear register SRCR 32 H'FFFF3010 32 Interrupt control register ICR 32 H'FFFF3014 32 Interrupt mask register IMR 32 H'FFFF3018 32 DL status register DLPR 32 H'FFFF3020 32 DL start address register DLSAR 32 H'FFFF3030 32 Destination start address register DSAR 32 H'FFFF3034 32 Destination stride register DSTR 32 H'FFFF303C 32 Destination start address register 2 DSAR2 32 H'FFFF3048 32 DL start address register 2 DLSAR2 32 H'FFFF304C 32 Triangle mode register TRIMR 32 H'FFFF3060 32 Triangle set register TRIMSR 32 H'FFFF3064 32 Triangle clear register TRIMCR 32 H'FFFF3068 32 Triangle color register TRICR 32 H'FFFF306C 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name Image renderer Access Register Name Abbreviation of Bits Address Size Source and destination coordinate UVDPOR 32 H'FFFF3070 32 SUSR 32 H'FFFF3074 32 decimal point register Source width register Display out comparison unit JPEG codec unit Source height register SVSR 32 H'FFFF3078 32 MIN clipping X register XMINR 32 H'FFFF3080 32 MIN clipping Y register YMINR 32 H'FFFF3084 32 MAX clipping X register XMAXR 32 H'FFFF3088 32 MAX clipping Y register YMAXR 32 H'FFFF308C 32 Mesh generation X size register AMXSR 32 H'FFFF3090 32 Mesh generation Y size register AMYSR 32 H'FFFF3094 32 Mesh generation X start register AMXOR 32 H'FFFF3098 32 Mesh generation Y start register AMYOR 32 H'FFFF309C 32 Memory access control register 1 MACR1 32 H'FFFF30A0 32 Start line specification register LSPR 32 H'FFFF3A00 32 End line specification register LEPR 32 H'FFFF3A04 32 Mesh size register LMSR 32 H'FFFF3A08 32 Control register DOCMCR 32 H'FFFFA800 32 Status register DOCMSTR 32 H'FFFFA804 32 Status clear register DOCMCLSTR 32 H'FFFFA808 32 Interrupt enable register DOCMIENR 32 H'FFFFA80C 32 Operation parameter setting register DOCMPMR 32 H'FFFFA814 32 Expected CRC code register DOCMECRCR 32 H'FFFFA818 32 Calculated CRC code value register DOCMCCRCR 32 H'FFFFA81C 32 Horizontal start position setting register DOCMSPXR 32 H'FFFFA820 32 Vertical start position setting register DOCMSPYR 32 H'FFFFA824 32 Horizontal size setting register DOCMSZXR 32 H'FFFFA828 32 Vertical size setting register DOCMSZYR 32 H'FFFFA82C 32 CRC code initialization register DOCMCRCIR 32 H'FFFFA830 32 JPEG code mode register JCMOD 8 H'E8017000 8 JPEG code command register JCCMD 8 H'E8017001 8 JPEG code quantization table number JCQTN 8 H'E8017003 8 register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2801 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name JPEG codec unit Access Register Name Abbreviation of Bits Address Size JPEG code Huffman table number JCHTN 8 H'E8017004 8 JCDRIU 8 H'E8017005 8 register JPEG code DRI upper register JPEG code DRI lower register JCDRID 8 H'E8017006 8 JPEG code vertical size upper register JCVSZU 8 H'E8017007 8 JPEG code vertical size lower register JCVSZD 8 H'E8017008 8 JPEG code horizontal size upper register JCHSZU 8 H'E8017009 8 JPEG code horizontal size lower register JCHSZD 8 H'E801700A 8 JPEG code data count upper register JCDTCU 8 H'E801700B 8 JPEG code data count middle register JCDTCM 8 H'E801700C 8 JPEG code data count lower register JCDTCD 8 H'E801700D 8 JPEG interrupt enable register 0 JINTE0 8 H'E801700E 8 JPEG interrupt status register 0 JINTS0 8 H'E801700F 8 JPEG code decode error register JCDERR 8 H'E8017010 8 JPEG code reset register JCRST 8 H'E8017011 8 JPEG interface compression control JIFECNT 32 H'E8017040 32 JIFESA 32 H'E8017044 32 JIFESOFST 32 H'E8017048 32 JIFEDA 32 H'E801704C 32 JIFESLC 32 H'E8017050 32 JIFDCNT 32 H'E8017058 32 JIFDSA 32 H'E801705C 32 JIFDDOFST 32 H'E8017060 32 JIFDDA 32 H'E8017064 32 JIFDSDC 32 H'E8017068 32 register JPEG interface compression source address register JPEG interface compression line offset register JPEG interface compression destination address register JPEG interface compression source line count register JPEG interface decompression control register JPEG interface decompression source address register JPEG interface decompression destination offset register JPEG interface decompression destination address register JPEG interface decompression source count register Page 2802 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name JPEG codec unit Access Register Name Abbreviation of Bits Address Size JPEG interface decompression JIFDDLC 32 H'E801706C 32 JPEG interface decompression  setting JIFDADT 32 H'E8017070 32 destination line count register register JPEG interrupt enable register 1 JINTE1 32 H'E801708C 32 JPEG interrupt status register 1 JINTS1 32 H'E8017090 32 JPEG code quantization table 0 register JCQTBL0 512 H'E8017100 to 8 H'E801713F JPEG code quantization table 1 register JCQTBL1 512 H'E8017140 to 8 H'E801717F JPEG code quantization table 2 register JCQTBL2 512 H'E8017180 to 8 H'E80171BF JPEG code quantization table 3 register JCQTBL3 512 H'E80171C0 to 8 H'E80171FF JPEG code Huffman table DC0 register JCHTBD0 224 H'E8017200 to 8 H'E801721B JPEG code Huffman table AC0 register JCHTBA0 1416 H'E8017220 to 8 H'E80172D1 JPEG code Huffman table DC1 register JCHTBD1 224 H'E8017300 to 8 H'E801731B JPEG code Huffman table AC1 register JCHTBA1 1416 H'E8017320 to 8 H'E80173D1 Sampling rate converter Input data register_0 SRCID_0 32 H'FFFE7000 16, 32 Output data register_0 SRCOD_0 32 H'FFFE7004 16, 32 Input data control register_0 SRCIDCTRL_0 16 H'FFFE7008 16 Output data control register_0 SRCODCTRL_0 16 H'FFFE700A 16 Control register_0 SRCCTRL_0 16 H'FFFE700C 16 Status register_0 SRCSTAT_0 16 H'FFFE700E 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2803 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Sampling rate Input data register_1 SRCID_1 32 H'FFFE7800 16, 32 Output data register_1 SRCOD_1 32 H'FFFE7804 16, 32 Input data control register_1 SRCIDCTRL_1 16 H'FFFE7808 16 Output data control register_1 SRCODCTRL_1 16 H'FFFE780A 16 Control register_1 SRCCTRL_1 16 H'FFFE780C 16 Status register_1 SRCSTAT_1 16 H'FFFE780E 16 Input data register_2 SRCID_2 32 H'FFFE8000 16, 32 Output data register_2 SRCOD_2 32 H'FFFE8004 16, 32 Input data control register_2 SRCIDCTRL_2 16 H'FFFE8008 16 Output data control register_2 SRCODCTRL_2 16 H'FFFE800A 16 Control register_2 SRCCTRL_2 16 H'FFFE800C 16 Status register_2 SRCSTAT_2 16 H'FFFE800E 16 Sound generator control register 1_0 SGCR1_0 8 H'FFFEC800 8, 16 Sound generator control status SGCSR_0 8 H'FFFEC801 8, 16 Sound generator control register 2_0 SGCR2_0 8 H'FFFEC802 8, 16 Sound generator loudness register_0 SGLR_0 8 H'FFFEC803 8, 16 Sound generator tone frequency SGTFR_0 8 H'FFFEC804 8, 16 SGSFR_0 8 H'FFFEC805 8, 16 Sound generator control register 1_1 SGCR1_1 8 H'FFFECA00 8, 16 Sound generator control status SGCSR_1 8 H'FFFECA01 8, 16 Sound generator control register 2_1 SGCR2_1 8 H'FFFECA02 8, 16 Sound generator loudness register_1 SGLR_1 8 H'FFFECA03 8, 16 Sound generator tone frequency SGTFR_1 8 H'FFFECA04 8, 16 SGSFR_1 8 H'FFFECA05 8, 16 Sound generator control register 1_2 SGCR1_2 8 H'FFFECC00 8, 16 Sound generator control status SGCSR_2 8 H'FFFECC01 8, 16 SGCR2_2 8 H'FFFECC02 8, 16 converter Sound generator register_0 register_0 Sound generator reference frequency register_0 register_1 register_1 Sound generator reference frequency register_1 register_2 Sound generator control register 2_2 Page 2804 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size Sound generator Sound generator loudness register_2 SGLR_2 8 H'FFFECC03 8, 16 Sound generator tone frequency SGTFR_2 8 H'FFFECC04 8, 16 SGSFR_2 8 H'FFFECC05 8, 16 Sound generator control register 1_3 SGCR1_3 8 H'FFFECE00 8, 16 Sound generator control status SGCSR_3 8 H'FFFECE01 8, 16 Sound generator control register 2_3 SGCR2_3 8 H'FFFECE02 8, 16 Sound generator loudness register_3 SGLR_3 8 H'FFFECE03 8, 16 Sound generator tone frequency SGTFR_3 8 H'FFFECE04 8, 16 SGSFR_3 8 H'FFFECE05 8, 16 CE_CMD_SET 32 H'E8030800 16, 32 register_2 Sound generator reference frequency register_2 register_3 register_3 Sound generator reference frequency register_3 MMC host interface Command setting register Argument register CE_ARG 32 H'E8030808 16, 32 Argument register for automatically- CE_ARG_CMD12 32 H'E803080C 16, 32 Command control register CE_CMD_CTRL 32 H'E8030810 16, 32 Transfer block setting register CE_BLOCK_SET 32 H'E8030814 16, 32 Clock control register CE_CLK_CTRL 32 H'E8030818 16, 32 Buffer access configuration register CE_BUF_ACC 32 H'E803081C 16, 32 Response register 3 CE_RESP3 32 H'E8030820 16, 32 Response register 2 CE_RESP2 32 H'E8030824 16, 32 Response register 1 CE_RESP1 32 H'E8030828 16, 32 Response register 0 CE_RESP0 32 H'E803082C 16, 32 Response register for automatically- CE_RESP_CMD12 32 H'E8030830 16, 32 CE_DATA 32 H'E8030834 16, 32 Interrupt flag register CE_INT 32 H'E8030840 16, 32 Interrupt enable register CE_INT_EN 32 H'E8030844 16, 32 Status register 1 CE_HOST_STS1 32 H'E8030848 16, 32 Status register 2 CE_HOST_STS2 32 H'E803084C 16, 32 DMA mode setting register CE_DMA_MODE 32 H'E803085C 16, 32 issued CMD12 issued CMD12 Data register R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2805 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name Register Name of Bits Address Size CE_DETECT 32 H'E8030870 16, 32 Special mode setting register CE_ADD_MODE 32 H'E8030874 16, 32 Version register CE_VERSION 32 H'E803087C 16, 32 PWM control register_1 PWCR_1 8 H'FFFEF4E0 8, 16 PWM polarity register_1 PWPR_1 8 H'FFFEF4E4 8, 16 PWM cycle register_1 PWCYR_1 16 H'FFFEF4E6 16 PWM buffer register_1A PWBFR_1A 16 H'FFFEF4E8 16 PWM buffer register_1C PWBFR_1C 16 H'FFFEF4EA 16 PWM buffer register_1E PWBFR_1E 16 H'FFFEF4EC 16 PWM buffer register_1G PWBFR_1G 16 H'FFFEF4EE 16 PWM control register_2 PWCR_2 8 H'FFFEF4F0 8, 16 PWM polarity register_2 PWPR_2 8 H'FFFEF4F4 8, 16 PWM cycle register_2 PWCYR_2 16 H'FFFEF4F6 16 PWM buffer register_2A PWBFR_2A 16 H'FFFEF4F8 16 PWM buffer register_2C PWBFR_2C 16 H'FFFEF4FA 16 PWM buffer register_2E PWBFR_2E 16 H'FFFEF4FC 16 PWM buffer register_2G PWBFR_2G 16 H'FFFEF4FE 16 PWM buffer transfer control register PWBTCR 8 H'FFFEF406 8, 16 Port A I/O register 0 PAIOR0 16 H'FFFE3812 8, 16* Port A data register 0 PADR0 16 H'FFFE3816 8, 16* MMC host interface Card detection/port control register Motor control PWM timer General purpose I/O ports Page 2806 of 3092 Access Abbreviation Port A port register 0 PAPR0 16 H'FFFE381A 8, 16 Port B control register 5 PBCR5 16 H'FFFE3824 8, 16, 32 Port B control register 4 PBCR4 16 H'FFFE3826 8, 16 Port B control register 3 PBCR3 16 H'FFFE3828 8, 16, 32 Port B control register 2 PBCR2 16 H'FFFE382A 8, 16 Port B control register 1 PBCR1 16 H'FFFE382C 8, 16, 32 Port B control register 0 PBCR0 16 H'FFFE382E 8, 16 Port B I/O register 1 PBIOR1 16 H'FFFE3830 8, 16, 32 Port B I/O register 0 PBIOR0 16 H'FFFE3832 8, 16 Port B data register 1 PBDR1 16 H'FFFE3834 8, 16, 32 Port B data register 0 PBDR0 16 H'FFFE3836 8, 16 Port B port register 1 PBPR1 16 H'FFFE3838 8, 16, 32 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size General purpose Port B port register 0 PBPR0 16 H'FFFE383A 8, 16 Port C control register 2 PCCR2 16 H'FFFE384A 8, 16 Port C control register 1 PCCR1 16 H'FFFE384C 8, 16, 32 Port C control register 0 PCCR0 16 H'FFFE384E 8, 16 Port C I/O register 0 PCIOR0 16 H'FFFE3852 8, 16 Port C data register 0 PCDR0 16 H'FFFE3856 8, 16 Port C port register 0 PCPR0 16 H'FFFE385A 8, 16 Port D control register 3 PDCR3 16 H'FFFE3868 8, 16, 32 Port D control register 2 PDCR2 16 H'FFFE386A 8, 16 Port D control register 1 PDCR1 16 H'FFFE386C 8, 16, 32 Port D control register 0 PDCR0 16 H'FFFE386E 8, 16 Port D I/O register 0 PDIOR0 16 H'FFFE3872 8, 16 I/O ports Port D data register 0 PDDR0 16 H'FFFE3876 8, 16 Port D port register 0 PDPR0 16 H'FFFE387A 8, 16 Port E control register 1 PECR1 16 H'FFFE388C 8, 16, 32 Port E control register 0 PECR0 16 H'FFFE388E 8, 16 Port E I/O register 0 PEIOR0 16 H'FFFE3892 8, 16 Port E data register 0 PEDR0 16 H'FFFE3896 8, 16 Port E port register 0 PEPR0 16 H'FFFE389A 8, 16 Port F control register 6 PFCR6 16 H'FFFE38A2 8, 16 Port F control register 5 PFCR5 16 H'FFFE38A4 8, 16, 32 Port F control register 4 PFCR4 16 H'FFFE38A6 8, 16* Port F control register 3 PFCR3 16 H'FFFE38A8 8, 16, 32 Port F control register 2 PFCR2 16 H'FFFE38AA 8, 16 Port F control register 1 PFCR1 16 H'FFFE38AC 8, 16, 32 Port F control register 0 PFCR0 16 H'FFFE38AE 8, 16 Port F I/O register 1 PFIOR1 16 H'FFFE38B0 8, 16, 32 Port F I/O register 0 PFIOR0 16 H'FFFE38B2 8, 16 Port F data register 1 PFDR1 16 H'FFFE38B4 8, 16, 32 Port F data register 0 PFDR0 16 H'FFFE38B6 8, 16 Port F port register 1 PFPR1 16 H'FFFE38B8 8, 16, 32 Port F port register 0 PFPR0 16 H'FFFE38BA 8, 16 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2807 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Number Access Module Name Register Name Abbreviation of Bits Address Size General purpose Port G control register 6 PGCR6 16 H'FFFE38C2 8, 16 Port G control register 5 PGCR5 16 H'FFFE38C4 8, 16, 32 Port G control register 4 PGCR4 16 H'FFFE38C6 8, 16 Port G control register 3 PGCR3 16 H'FFFE38C8 8, 16, 32 I/O ports Port G control register 2 PGCR2 16 H'FFFE38CA 8, 16 Port G control register 1 PGCR1 16 H'FFFE38CC 8, 16, 32 Port G control register 0 PGCR0 16 H'FFFE38CE 8, 16 Port G I/O register 1 PGIOR1 16 H'FFFE38D0 8, 16, 32 Port G I/O register 0 PGIOR0 16 H'FFFE38D2 8, 16 Port G data register 1 PGDR1 16 H'FFFE38D4 8, 16, 32 Port G data register 0 PGDR0 16 H'FFFE38D6 8, 16 Port G port register 1 PGPR1 16 H'FFFE38D8 8, 16, 32 Port G port register 0 PGPR0 16 H'FFFE38DA 8, 16 Port H control register 1 PHCR1 16 H'FFFE38EC 8, 16, 32 Port H control register 0 PHCR0 16 H'FFFE38EE 8, 16 Port H port register 0 PHPR0 16 H'FFFE38FA 8, 16 Port J control register 7 PJCR7 16 H'FFFE3900 8, 16, 32 Port J control register 6 PJCR6 16 H'FFFE3902 8, 16 Port J control register 5 PJCR5 16 H'FFFE3904 8, 16, 32 Port J control register 4 PJCR4 16 H'FFFE3906 8, 16 Port J control register 3 PJCR3 16 H'FFFE3908 8, 16, 32 Port J control register 2 PJCR2 16 H'FFFE390A 8, 16 Port J control register 1 PJCR1 16 H'FFFE390C 8, 16, 32 Port J control register 0 PJCR0 16 H'FFFE390E 8, 16 Port J I/O register 1 PJIOR1 16 H'FFFE3910 8, 16, 32 Port J I/O register 0 PJIOR0 16 H'FFFE3912 8, 16 Port J data register 1 PJDR1 16 H'FFFE3914 8, 16, 32 Port J data register 0 PJDR0 16 H'FFFE3916 8, 16 Port J port register 1 PJPR1 16 H'FFFE3918 8, 16, 32 Port J port register 0 PJPR0 16 H'FFFE391A 8, 16 Serial sound interface noise canceler SNCR 16 H'FFFE393E 8, 16 control register Page 2808 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Number Module Name Register Name Access Abbreviation of Bits Address Size Power-down modes Standby control register 1 STBCR1 8 H'FFFE0014 8 Standby control register 2 STBCR2 8 H'FFFE0018 8 Standby control register 3 STBCR3 8 H'FFFE0408 8 Standby control register 4 STBCR4 8 H'FFFE040C 8 Standby control register 5 STBCR5 8 H'FFFE0410 8 Standby control register 6 STBCR6 8 H'FFFE0414 8 Standby control register 7 STBCR7 8 H'FFFE0418 8 Standby control register 8 STBCR8 8 H'FFFE041C 8 Standby control register 9 STBCR9 8 H'FFFE0440 8 Standby control register 10 STBCR10 8 H'FFFE0444 8 Software reset control register 1 SWRSTCR1 8 H'FFFE0430 8 Software reset control register 2 SWRSTCR2 8 H'FFFE0434 8 System control register 1 SYSCR1 8 H'FFFE0400 8 System control register 2 SYSCR2 8 H'FFFE0404 8 System control register 3 SYSCR3 8 H'FFFE0420 8 System control register 4 SYSCR4 8 H'FFFE0424 8 System control register 5 SYSCR5 8 H'FFFE0428 8 On-chip data-retention RAM area setting RRAMKP 8 H'FFFE6800 8 register Deep standby control register DSCTR 8 H'FFFE6802 8 Deep standby cancel source select DSSSR 16 H'FFFE6804 16 DSESR 16 H'FFFE6806 16 Deep standby cancel source flag register DSFR 16 H'FFFE6808 16 XTAL crystal oscillator gain control XTALCTR 8 H'FFFE6810 8 SDIR 16 H'FFFE2000 16 register Deep standby cancel edge select register register User debugging Instruction register interface R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2809 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers 51.2 Register Bits Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Clock pulse FRQCR  CKOEN2 CKOEN[1] CKOEN[0]   IFC[1] IFC[0]   BFC[1] BFC[0]     NMIL       NMIE         IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S generator Interrupt ICR0 controller ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR         PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S         IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F         PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E         PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1  BE[1] BE[0] BOVE          BN[3] BN[2] BN[1] BN[0] IPR01 IPR02 IPR05 IPR06 IPR07 IPR08 Page 2810 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Interrupt IPR09 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Section 51 List of Registers Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 controller IPR10 IPR11 IPR12 IPR13 IPR14 IPR15 IPR16 IPR17 IPR18 IPR19 IPR20 IPR21 IPR22 IPR23 IPR24 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2811 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Interrupt IPR25 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                     ICF   ICE     OCF  WT OCE                LE       W3LOAD W3LOCK       W2LOAD W2LOCK BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 controller IPR26 Cache CCR1 CCR2 User break BAR_0 controller BAMR_0 BBR_0 BDR_0 BDMR_0 Page 2812 of 3092 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0   UBID DBE   CP[1] CP[0] CD[1] CD[0] ID[1] ID[0] RW[1] RW[0] SZ[1] SZ[0] BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16 BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 User break BAR_1 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0   UBID DBE   CP[1] CP[0] CD[1] CD[0] ID[1] ID[0] RW[1] RW[0] SZ[1] SZ[0] BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 controller BAMR_1 BBR_1 BDR_1 BDMR_1 BRCR Bus state CMNCR controller CS0BCR BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16 BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0             UTOD1 UTOD0 CKS[1] CKS[0] SCMFC0 SCMFC1 SCMFD0 SCMFD1      PCB1 PCB0                          BLOCK DPRTY[1] DPRTY[0] DMAIW[2] DMAIW[1] DMAIW[0] DMAIWA    HIZMEM HIZCNT  IWW[2] IWW[1] IWW[0] IWRWD[2] IWRWD[1] IWRWD[0] IWRWS[2] IWRWS[1] IWRWS[0] IWRRD[2] IWRRD[1] IWRRD[0] IWRRS[2] IWRRS[1] IWRRS[0]  TYPE[2] TYPE[1] TYPE[0] ENDIAN BSZ[1] BSZ[0]          R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2813 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Bus state CS1BCR  IWW[2] IWW[1] IWW[0] IWRWD[2] IWRWD[1] IWRWD[0] IWRWS[2] IWRWS[1] IWRWS[0] IWRRD[2] IWRRD[1] IWRRD[0] IWRRS[2] IWRRS[1] IWRRS[0]  TYPE[2] TYPE[1] TYPE[0] ENDIAN BSZ[1] BSZ[0]           IWW[2] IWW[1] IWW[0] IWRWD[2] IWRWD[1] IWRWD[0] IWRWS[2] IWRWS[1] IWRWS[0] IWRRD[2] IWRRD[1] IWRRD[0] IWRRS[2] IWRRS[1] IWRRS[0]  TYPE[2] TYPE[1] TYPE[0] ENDIAN BSZ[1] BSZ[0]           IWW[2] IWW[1] IWW[0] IWRWD[2] IWRWD[1] IWRWD[0] IWRWS[2] IWRWS[1] IWRWS[0] IWRRD[2] IWRRD[1] IWRRD[0] IWRRS[2] IWRRS[1] IWRRS[0]  TYPE[2] TYPE[1] TYPE[0] ENDIAN BSZ[1] BSZ[0]           IWW[2] IWW[1] IWW[0] IWRWD[2] IWRWD[1] IWRWD[0] IWRWS[2] IWRWS[1] IWRWS[0] IWRRD[2] IWRRD[1] IWRRD[0] IWRRS[2] IWRRS[1] IWRRS[0]  TYPE[2] TYPE[1] TYPE[0] ENDIAN BSZ[1] BSZ[0]           IWW[2] IWW[1] IWW[0] IWRWD[2] IWRWD[1] IWRWD[0] IWRWS[2] IWRWS[1] IWRWS[0] IWRRD[2] IWRRD[1] IWRRD[0] IWRRS[2] IWRRS[1] IWRRS[0]  TYPE[2] TYPE[1] TYPE[0] ENDIAN BSZ[1] BSZ[0]                     BAS        SW[1] SW[0] WR[3] WR[2] WR[1] WR[0] WM     HW[1] HW[0]           BST[1] BST[0]   BW[1] BW[0]      W[3] W[2] W[1] W[0] WM                     BW[1] BW[0]      W[3] W[2] W[1] W[0] WM       controller CS2BCR CS3BCR CS4BCR CS5BCR CS0WCR CS0WCR CS0WCR Page 2814 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Bus state CS1WCR            BAS  WW[2] WW[1] WW[0]    SW[1] SW[0] WR[3] WR[2] WR[1] WR[0] WM     HW[1] HW[0]            BAS          WR[3] WR[2] WR[1] WR[0] WM                              A2CL1 A2CL0                   BAS          WR[3] WR[2] WR[1] WR[0] WM                        WTRP[1] WTRP[0]  WTRCD[1] WTRCD[0]  A3CL1 A3CL0   TRWL[1] TRWL[0]  WTRC[1] WTRC[0]            BAS  WW[2] WW[1] WW[0]    SW[1] SW[0] WR[3] WR[2] WR[1] WR[0] WM     HW[1] HW[0]           BST[1] BST[0]   BW[1] BW[0]    SW[1] SW[0] W[3] W[2] W[1] W[0] WM     HW[1] HW[0]           SZSEL MPXW/BAS  WW[2] WW[1] WW[0]    SW[1] SW[0] WR[3] WR[2] WR[1] WR[0] WM     HW[1] HW[0] controller CS2WCR CS2WCR CS3WCR CS3WCR CS4WCR CS4WCR CS5WCR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2815 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Bus state CS5WCR           SA[1] SA[0]      TED[3] TED[2] TED[1] TED[0] PCW[3] PCW[2] PCW[1] PCW[0] WM   TEH[3] TEH[2] TEH[1] TEH[0]            A2ROW[1] A2ROW[0]  A2COL[1] A2COL[0]   DEEP  RFSH RMODE PDOWN BACTV    A3ROW[1] A3ROW[0]  A3COL[1] A3COL[0]                         CMF CMIE CKS[2] CKS[1] CKS[0] RRC[2] RRC[1] RRC[0]                                                         controller SDCR RTCSR RTCNT RTCOR Direct SAR0 memory access controller DAR0 DMATCR0 Page 2816 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Direct CHCR0 TC  DO Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 RLDSAR RLDDAR  DAF SAF  TL  TEMASK HE HIE AM AL DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0] DL DS TB TS[1] TS[0] IE TE DE         DMATCR1         CHCR1 TC  RLDSAR RLDDAR  DAF SAF  DO TL  TEMASK HE HIE AM AL memory access controller RSAR0 RDAR0 RDMATCR0 SAR1 DAR1 DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0] DL DS TB TS[1] TS[0] IE TE DE R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2817 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Direct RSAR1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0         DMATCR2         CHCR2 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE memory access controller RDAR1 RDMATCR1 SAR2 DAR2 RSAR2 Page 2818 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Direct RDAR2 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0         DMATCR3         CHCR3 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE memory access controller RDMATCR2 SAR3 DAR3 RSAR3 RDAR3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2819 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Direct RDMATCR3                 memory access controller SAR4 DAR4 DMATCR4  CHCR4 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         RSAR4 RDAR4 RDMATCR4 Page 2820 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Direct SAR5 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0       memory access controller DAR5 DMATCR5    CHCR5 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         RSAR5 RDAR5 RDMATCR5 SAR6 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2821 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Direct DAR6 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 DMATCR6         CHCR6 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         memory access controller RSAR6 RDAR6 RDMATCR6 SAR7 DAR7 Page 2822 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Direct DMATCR7         CHCR7 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE                 memory access controller RSAR7 RDAR7 RDMATCR7 SAR8 DAR8 DMATCR8  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2823 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Direct CHCR8 TC   Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 RLDSAR RLDDAR  DAF SAF    TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         DMATCR9         CHCR9 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE memory access controller RSAR8 RDAR8 RDMATCR8 SAR9 DAR9 Page 2824 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Direct RSAR9 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                 memory access controller RDAR9 RDMATCR9 SAR10 DAR10 DMATCR10  CHCR10 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE RSAR10 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2825 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Direct RDAR10 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                 memory access controller RDMATCR10 SAR11 DAR11 DMATCR11  CHCR11 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE RSAR11 RDAR11 Page 2826 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Direct RDMATCR11                 memory access controller SAR12 DAR12 DMATCR12  CHCR12 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         RSAR12 RDAR12 RDMATCR12 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2827 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Direct SAR13 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0       memory access controller DAR13 DMATCR13    CHCR13 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         RSAR13 RDAR13 RDMATCR13 SAR14 Page 2828 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Direct DAR14 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0       memory access controller DMATCR14    CHCR14 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE         RSAR14 RDAR14 RDMATCR14 SAR15 DAR15 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2829 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Direct DMATCR15         CHCR15 TC  RLDSAR RLDDAR  DAF SAF     TEMASK HE HIE   DM[1] DM[0] SM[1] SM[0] RS[3] RS[2] RS[1] RS[0]   TB TS[1] TS[0] IE TE DE RDMATCR15         DMAOR   CMS[1] CMS[0]   PR[1] PR[0]      AE NMIF DME CH1MID[5] CH1MID[4] CH1MID[3] CH1MID[2] CH1MID[1] CH1MID[0] CH1RID[1] CH1RID[0] CH0MID[5] CH0MID[4] CH0MID[3] CH0MID[2] CH0MID[1] CH0MID[0] CH0RID[1] CH0RID[0] CH3MID[5] CH3MID[4] CH3MID[3] CH3MID[2] CH3MID[1] CH3MID[0] CH3RID[1] CH3RID[0] CH2MID[5] CH2MID[4] CH2MID[3] CH2MID[2] CH2MID[1] CH2MID[0] CH2RID[1] CH2RID[0] CH5MID[5] CH5MID[4] CH5MID[3] CH5MID[2] CH5MID[1] CH5MID[0] CH5RID[1] CH5RID[0] CH4MID[5] CH4MID[4] CH4MID[3] CH4MID[2] CH4MID[1] CH4MID[0] CH4RID[1] CH4RID[0] CH7MID[5] CH7MID[4] CH7MID[3] CH7MID[2] CH7MID[1] CH7MID[0] CH7RID[1] CH7RID[0] CH6MID[5] CH6MID[4] CH6MID[3] CH6MID[2] CH6MID[1] CH6MID[0] CH6RID[1] CH6RID[0] CH9MID[5] CH9MID[4] CH9MID[3] CH9MID[2] CH9MID[1] CH9MID[0] CH9RID[1] CH9RID[0] CH8MID[5] CH8MID[4] CH8MID[3] CH8MID[2] CH8MID[1] CH8MID[0] CH8RID[1] CH8RID[0] memory access controller RSAR15 RDAR15 DMARS0 DMARS1 DMARS2 DMARS3 DMARS4 Page 2830 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Direct DMARS5 CH11MID[5] CH11MID[4] CH11MID[3] CH11MID[2] CH11MID[1] CH11MID[0] CH11RID[1] CH11RID[0] CH10MID[5] CH10MID[4] CH10MID[3] CH10MID[2] CH10MID[1] CH10MID[0] CH10RID[1] CH10RID[0] CH13MID[5] CH13MID[4] CH13MID[3] CH13MID[2] CH13MID[1] CH13MID[0] CH13RID[1] CH13RID[0] CH12MID[5] CH12MID[4] CH12MID[3] CH12MID[2] CH12MID[1] CH12MID[0] CH12RID[1] CH12RID[0] CH15MID[5] CH15MID[4] CH15MID[3] CH15MID[2] CH15MID[1] CH15MID[0] CH15RID[1] CH15RID[0] CH14MID[5] CH14MID[4] CH14MID[3] CH14MID[2] CH14MID[1] CH14MID[0] CH14RID[1] CH14RID[0] TCR_0 CCLR[2] CCLR[1] CCLR[0] CKEG[1] CKEG[0] TPSC[2] TPSC[1] TPSC[0] TMDR_0  BFE BFB BFA MD[3] MD[2] MD[1] MD[0] TIORH_0 IOB[3] IOB[2] IOB[1] IOB[0] IOA[3] IOA[2] IOA[1] IOA[0] TIORL_0 IOD[3] IOD[2] IOD[1] IOD[0] IOC[3] IOC[2] IOC[1] IOC[0] TIER_0 TTGE   TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFD   TCFV TGFD TGFC TGFB TGFA TIER2_0 TTGE2      TGIEF TGIEE TSR2_0       TGFF TGFE TBTM_0      TTSE TTSB TTSA TCR_1  CCLR[1] CCLR[0] CKEG[1] CKEG[0] TPSC[2] TPSC[1] TPSC[0] TMDR_1     MD[3] MD[2] MD[1] MD[0] TIOR_1 IOB[3] IOB[2] IOB[1] IOB[0] IOA[3] IOA[2] IOA[1] IOA[0] memory access controller DMARS6 DMARS7 Multi-function timer pulse unit 2 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TGRE_0 TGRF_0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2831 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Multi-function TIER_1 TTGE  TSR_1 TCFD TICCR timer pulse Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 TCIEU TCIEV   TGIEB TGIEA  TCFU TCFV TGFD TGFC TGFB TGFA     I2BE I2AE I1BE I1AE TCR_2  CCLR[1] CCLR[0] CKEG[1] CKEG[0] TPSC[2] TPSC[1] TPSC[0] TMDR_2     MD[3] MD[2] MD[1] MD[0] TIOR_2 IOB[3] IOB[2] IOB[1] IOB[0] IOA[3] IOA[2] IOA[1] IOA[0] TIER_2 TTGE  TCIEU TCIEV   TGIEB TGIEA TSR_2 TCFD  TCFU TCFV TGFD TGFC TGFB TGFA TCR_3 CCLR[2] CCLR[1] CCLR[0] CKEG[1] CKEG[0] TPSC[2] TPSC[1] TPSC[0] TMDR_3   BFB BFA MD[3] MD[2] MD[1] MD[0] TIORH_3 IOB[3] IOB[2] IOB[1] IOB[0] IOA[3] IOA[2] IOA[1] IOA[0] TIORL_3 IOD[3] IOD[2] IOD[1] IOD[0] IOC[3] IOC[2] IOC[1] IOC[0] TIER_3 TTGE   TCIEV TGIED TGIEC TGIEB TGIEA TSR_3 TCFD   TCFV TGFD TGFC TGFB TGFA unit 2 TCNT_1 TGRA_1 TGRB_1 TCNT_2 TGRA_2 TGRB_2 TCNT_3 TGRA_3 TGRB_3 Page 2832 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Multi-function TGRC_3 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 TBTM_3       TTSB TTSA TCR_4 CCLR[2] CCLR[1] CCLR[0] CKEG[1] CKEG[0] TPSC[2] TPSC[1] TPSC[0] TMDR_4   BFB BFA MD[3] MD[2] MD[1] MD[0] TIORH_4 IOB[3] IOB[2] IOB[1] IOB[0] IOA[3] IOA[2] IOA[1] IOA[0] TIORL_4 IOD[3] IOD[2] IOD[1] IOD[0] IOC[3] IOC[2] IOC[1] IOC[0] TIER_4 TTGE TTGE2  TCIEV TGIED TGIEC TGIEB TGIEA TSR_4 TCFD   TCFV TGFD TGFC TGFB TGFA TBTM_4       TTSB TTSA TADCR BF[1] BF[0]       UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE timer pulse unit 2 TGRD_3 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TADCORA_4 TADCORB_4 TADCOBRA_4 TADCOBRB_4 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2833 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Multi-function TSTR CST4 CST3 TSYR SYNC4 TRWER timer pulse Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0    CST2 CST1 CST0 SYNC3    SYNC2 SYNC1 SYNC0        RWE TOER   OE4D OE4C OE3D OE4B OE4A OE3B TOCR1  PSYE   TOCL TOCS OLSN OLSP TOCR2 BF[1] BF[0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P TGCR  BDC N P FB WF VF UF TCDR  unit 2 TDDR TCNTS TCBR Compare TITCR T3AEN 3ACOR[2] 3ACOR[1] 3ACOR[0] T4VEN 4VCOR[2] 4VCOR[1] 4VCOR[0] TITCNT  3ACNT[2] 3ACNT[1] 3ACNT[0]  4VCNT[2] 4VCNT[1] 4VCNT[0] TBTER       BTE[1] BTE[0] TDER        TDER TWCR CCE       WRE TOLBR   OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P CMSTR               STR1 STR0         CMF CMIE     CKS[1] CKS[0]         CMF CMIE     CKS[1] CKS[0] match timer CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 Page 2834 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Compare CMCNT_1 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 IOVF   CKS[2] CKS[0] match timer CMCOR_1 Watchdog timer Realtime clock WTCNT WTCSR WT/IT TME CKS[1] WRCSR WOVF RSTE RSTS      R64CNT  1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz RSECCNT  10 seconds [2] 10 seconds [1] 10 seconds [0] 1 second [3] 1 second [2] 1 second [1] 1 second [0] RMINCNT  10 minutes [2] 10 minutes [1] 10 minutes [0] 1 minute [3] 1 minute [2] 1 minute [1] 1 minute [0] RHRCNT   10 hours [1] 10 hours [0] 1 hour [3] 1 hour [2] 1 hour [1] 1 hour [0] RWKCNT      Day [2] Day [1] Day [0] RDAYCNT   10 days [1] 10 days [0] 1 day [3] 1 day [2] 1 day [1] 1 day [0] RMONCNT    10 months 1 month [3] 1 month [2] 1 month [1] 1 month [0] RYRCNT 1000 years [3] 1000 years [2] 1000 years [1] 1000 years [0] 100 years [3] 100 years [2] 100 years [1] 100 years [0] 10 years [3] 10 years [2] 10 years [1] 10 years [0] 1 year [3] 1 year [2] 1 year [1] 1 year [0] RSECAR ENB 10 seconds [2] 10 seconds [1] 10 seconds [0] 1 second [3] 1 second [2] 1 second [1] 1 second [0] RMINAR ENB 10 minutes [2] 10 minutes [1] 10 minutes [0] 1 minute [3] 1 minute [2] 1 minute [1] 1 minute [0] RHRAR ENB  10 hours [1] 10 hours [0] 1 hour [3] 1 hour [2] 1 hour [1] 1 hour [0] RWKAR ENB     Day [2] Day [1] Day [0] RDAYAR ENB  10 days [1] 10 days [0] 1 day [3] 1 day [2] 1 day [1] 1 day [0] RMONAR ENB   10 months 1 month [3] 1 month [2] 1 month [1] 1 month [0] RYRAR 1000 years [3] 1000 years [2] 1000 years [1] 1000 years [0] 100 years [3] 100 years [2] 100 years [1] 100 years [0] 10 years [3] 10 years [2] 10 years [1] 10 years [0] 1 year [3] 1 year [2] 1 year [1] 1 year [0] RCR1 CF   CIE AIE   AF RCR2 PEF PES[2] PES[1] PES[0] RTCEN ADJ RESET START RCR3 ENB        RCR5        RCKSEL RFRH                RFC[16] RFC[15] RFC[14] RFC[13] RFC[12] RFC[11] RFC[10] RFC[9] RFC[8] RFC[7] RFC[6] RFC[5] RFC[4] RFC[3] RFC[2] RFC[1] RFC[0] RFRL R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2835 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial SCSMR_0         C/A CHR PE O/E STOP  CKS[1] CKS[0]         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0]             SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS         C/A CHR PE O/E STOP  CKS[1] CKS[0] communication interface with FIFO SCBRR_0 SCSCR_0 SCFTDR_0 SCFSR_0 SCFRDR_0 SCFCR_0 SCFDR_0 SCSPTR_0 SCLSR_0 SCEMR_0 SCSMR_1 SCBRR_1 SCSCR_1         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP SCFTDR_1 SCFSR_1 SCFRDR_1 SCFCR_1 SCFDR_1 Page 2836 of 3092    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial SCSPTR_1         RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS communication interface with FIFO SCLSR_1 SCEMR_1 SCSMR_2         C/A CHR PE O/E STOP  CKS[1] CKS[0]         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0]             SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS         C/A CHR PE O/E STOP  CKS[1] CKS[0]         TIE RIE TE RE REIE  CKE[1] CKE[0] SCBRR_2 SCSCR_2 SCFTDR_2 SCFSR_2 SCFRDR_2 SCFCR_2 SCFDR_2 SCSPTR_2 SCLSR_2 SCEMR_2 SCSMR_3 SCBRR_3 SCSCR_3 SCFTDR_3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2837 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial SCFSR_3 PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0]             SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS         C/A CHR PE O/E STOP  CKS[1] CKS[0]         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR communication interface with FIFO SCFRDR_3 SCFCR_3 SCFDR_3 SCSPTR_3 SCLSR_3 SCEMR_3 SCSMR_4 SCBRR_4 SCSCR_4 SCFTDR_4 SCFSR_4 SCFRDR_4 SCFCR_4 SCFDR_4 SCSPTR_4 SCLSR_4 SCEMR_4 Page 2838 of 3092      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0]             SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial SCSMR_5         C/A CHR PE O/E STOP  CKS[1] CKS[0]         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0]         RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS         C/A CHR PE O/E STOP  CKS[1] CKS[0] communication interface with FIFO SCBRR_5 SCSCR_5 SCFTDR_5 SCFSR_5 SCFRDR_5 SCFCR_5 SCFDR_5 SCSPTR_5 SCLSR_5 SCEMR_5 SCSMR_6 SCBRR_6 SCSCR_6         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP SCFTDR_6 SCFSR_6 SCFRDR_6 SCFCR_6 SCFDR_6    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2839 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial SCSPTR_6             SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS communication interface with FIFO SCLSR_6 SCEMR_6         C/A CHR PE O/E STOP  CKS[1] CKS[0]         TIE RIE TE RE REIE  CKE[1] CKE[0] PER[3] PER[2] PER[1] PER[0] FER[3] FER[2] FER[1] FER[0] ER TEND TDFE BRK FER PER RDF DR      RSTRG[2] RSTRG[1] RSTRG[0] RTRG[1] RTRG[0] TTRG[1] TTRG[0] MCE TFRST RFRST LOOP    T[4] T[3] T[2] T[1] T[0]    R[4] R[3] R[2] R[1] R[0]         RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IO SPB2DT                ORER         BGDM       ABCS SPCR_0 SPRIE SPE SPTIE SPEIE MSTR MODFEN   SSLP_0        SSL0P SPPCR_0   MOIFE MOIFV    SPLP SPSR_0 SPRF TEND SPTEF   MODF  OVRF SCSMR_7 SCBRR_7 SCSCR_7 SCFTDR_7 SCFSR_7 SCFRDR_7 SCFCR_7 SCFDR_7 SCSPTR_7 SCLSR_7 SCEMR_7 Renesas serial peripheral interface Page 2840 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Renesas SPDR_0 SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16 SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 SPSCR_0       SPSLN1 SPSLN0 SPSSR_0       SPCP1 SPCP0 serial peripheral interface SPBR_0 SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0 SPDCR_0 TXDMY SPLW1 SPLW0      SPCKD_0      SCKDL2 SCKDL1 SCKDL0 SSLND_0      SLNDL2 SLNDL1 SLNDL0 SPND_0      SPNDL2 SPNDL1 SPNDL0 SPCMD_00 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SPCMD_01 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SPCMD_02 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SPBFCR_0 TXRST RXRST TXTRG[1] TXTRG[0]  RXTRG[2] RXTRG[1] RXTRG[0] SPBFDR_0     T[3] T[2] T[1] T[0]   R[5] R[4] R[3] R[2] R[1] R[0] SPCMD_03 SPCR_1 SPRIE SPE SPTIE SPEIE MSTR MODFEN   SSLP_1        SSL0P SPPCR_1   MOIFE MOIFV    SPLP SPSR_1 SPRF TEND SPTEF   MODF  OVRF SPDR_1 SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16 SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 SPSCR_1       SPSLN1 SPSLN0 SPSSR_1       SPCP1 SPCP0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2841 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Renesas SPBR_1 SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0 SPDCR_1 TXDMY SPLW1 SPLW0      SPCKD_1      SCKDL2 SCKDL1 SCKDL0 SSLND_1      SLNDL2 SLNDL1 SLNDL0 SPND_1      SPNDL2 SPNDL1 SPNDL0 SPCMD_10 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SPCMD_11 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP    BRDV1 BRDV0 CPOL CPHA TXRST RXRST TXTRG[1] TXTRG[0]  RXTRG[2] RXTRG[1] RXTRG[0] serial peripheral interface SPCMD_12 SPCMD_13 SPBFCR_1     T[3] T[2] T[1] T[0]   R[5] R[4] R[3] R[2] R[1] R[0] SPCR_0 SPRIE SPE SPTIE      SSLP_0        SSLP SPPCR_0   MOIFE MOIFV  IO3FV IO2FV SPLP SPSR_0 SPRFF TEND SPTEF      SPDR_0 SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16 SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 SPSCR_0       SPSC1 SPSC0 SPSSR_0       SPSS1 SPSS0 SPBR_0 SPBR7 SPBR6 SPBR5 SPBR4 SPBR3 SPBR2 SPBR1 SPBR0 SPDCR_0 TXDMY        SPCKD_0      SCKDL2 SCKDL1 SCKDL0 SSLND_0      SLNDL2 SLNDL1 SLNDL0 SPND_0      SPNDL2 SPNDL1 SPNDL0 SPBFDR_1 Renesas quad serial peripheral interface Page 2842 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Renesas SPCMD0_0 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA quad serial peripheral interface SPCMD1_0 SPCMD2_0 SPCMD3_0 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SPBFCR_0 TXRST RXRST TXTRG1 TXTRG0  RXTRG2 RXTRG1 RXTRG0 SPBDCR_0   TXBC5 TXBC4 TXBC3 TXBC2 TXBC1 TXBC0   RXBC5 RXBC4 RXBC3 RXBC2 RXBC1 RXBC0 SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL0_0 SPBMUL1_0 SPBMUL2_0 SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] SPCR_1 SPRIE SPE SPTIE      SSLP_1        SSLP SPPCR_1   MOIFE MOIFV  IO3FV IO2FV SPLP SPSR_1 SPRFF TEND SPTEF      SPBMUL3_0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2843 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Renesas SPDR_1 SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16 SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 SPSCR_1       SPSC1 SPSC0 SPSSR_1       SPSS1 SPSS0 SPBR_1 SPBR7 SPBR6 SPBR5 SPBR4 SPBR3 SPBR2 SPBR1 SPBR0 SPDCR_1 TXDMY        SPCKD_1      SCKDL2 SCKDL1 SCKDL0 SSLND_1      SLNDL2 SLNDL1 SLNDL0 SPND_1      SPNDL2 SPNDL1 SPNDL0 SPCMD0_1 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SPCMD1_1 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SPCMD2_1 SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SCKDEN SLNDEN SPNDEN LSBF SPB3 SPB2 SPB1 SPB0 SSLKP SPIMOD1 SPIMOD0 SPRW BRDV1 BRDV0 CPOL CPHA SPBFCR_1 TXRST RXRST TXTRG1 TXTRG0  RXTRG2 RXTRG1 RXTRG0 SPBDCR_1   TXBC5 TXBC4 TXBC3 TXBC2 TXBC1 TXBC0   RXBC5 RXBC4 RXBC3 RXBC2 RXBC1 RXBC0 SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] quad serial peripheral interface SPCMD3_1 SPBMUL0_1 SPBMUL1_1 Page 2844 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Renesas SPBMUL2_1 SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] SPBMUL[31] SPBMUL[30] SPBMUL[29] SPBMUL[28] SPBMUL[27] SPBMUL[26] SPBMUL[25] SPBMUL[24] SPBMUL[23] SPBMUL[22] SPBMUL[21] SPBMUL[20] SPBMUL[19] SPBMUL[18] SPBMUL[17] SPBMUL[16] SPBMUL[15] SPBMUL[14] SPBMUL[13] SPBMUL[12] SPBMUL[11] SPBMUL[10] SPBMUL[9] SPBMUL[8] SPBMUL[7] SPBMUL[6] SPBMUL[5] SPBMUL[4] SPBMUL[3] SPBMUL[2] SPBMUL[1] SPBMUL[0] MD        MOIIO3[1] MOIIO3[0] MOIIO2[1] MOIIO2[0] MOIIO1[1] MOIIO1[0] MOIIO0[1] MOIIO0[0] IO3FV[1] IO3FV[0] IO2FV[1] IO2FV[0]   IO0FV[1] IO0FV[0]  CPHAT CPHAR SSLP CPOL  BSZ[1] BSZ[0]              SPNDL[2] SPNDL[1] SPNDL[0]      SLNDL[2] SLNDL[1] SLNDL[0]      SCKDL[2] SCKDL[1] SCKDL[0]                 SPBR[7] SPBR[6] SPBR[5] SPBR[4] SPBR[3] SPBR[2] SPBR[1] SPBR[0]       BRDV[1] BRDV[0]             RBURST[3] RBURST[2] RBURST[1] RBURST[0]       RCF RBE        SSLE         CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0]         OCMD[7] OCMD[6] OCMD[5] OCMD[4] OCMD[3] OCMD[2] OCMD[1] OCMD[0]         EAV[7] EAV[6] EAV[5] EAV[4] EAV[3] EAV[2] EAV[1] EAV[0]              EAC[2] EAC[1] EAC[0] quad serial peripheral interface SPBMUL3_1 SPI multi I/O CMNCR bus controller SSLDR SPBCR DRCR DRCMR DREAR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2845 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 SPI multi I/O DROPR OPD3[7] OPD3[6] OPD3[5] OPD3[4] OPD3[3] OPD3[2] OPD3[1] OPD3[0] OPD2[7] OPD2[6] OPD2[5] OPD2[4] OPD2[3] OPD2[2] OPD2[1] OPD2[0] OPD1[7] OPD1[6] OPD1[5] OPD1[4] OPD1[3] OPD1[2] OPD1[1] OPD1[0] OPD0[7] OPD0[6] OPD0[5] OPD0[4] OPD0[3] OPD0[2] OPD0[1] OPD0[0] CDB[1] CDB[0] OCDB[1] OCDB[0]   ADB[1] ADB[0]   OPDB[1] OPDB[0]   DRDB[1] DRDB[0] bus controller DRENR SMCR SMCMR SMADR SMOPR SMENR SMRDR0 Page 2846 of 3092  CDE  OCDE ADE[3] ADE[2] ADE[1] ADE[0] OPDE[3] OPDE[2] OPDE[1] OPDE[0]                            SSLKP      SPIRE SPIWE SPIE         CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0]         OCMD[7] OCMD[6] OCMD[5] OCMD[4] OCMD[3] OCMD[2] OCMD[1] OCMD[0] ADR[31] ADR[30] ADR[29] ADR[28] ADR[27] ADR[26] ADR[25] ADR[24] ADR[23] ADR[22] ADR[21] ADR[20] ADR[19] ADR[18] ADR[17] ADR[16] ADR[15] ADR[14] ADR[13] ADR[12] ADR[11] ADR[10] ADR[9] ADR[8] ADR[7] ADR[6] ADR[5] ADR[4] ADR[3] ADR[2] ADR[1] ADR[0] OPD3[7] OPD3[6] OPD3[5] OPD3[4] OPD3[3] OPD3[2] OPD3[1] OPD3[0] OPD2[7] OPD2[6] OPD2[5] OPD2[4] OPD2[3] OPD2[2] OPD2[1] OPD2[0] OPD1[7] OPD1[6] OPD1[5] OPD1[4] OPD1[3] OPD1[2] OPD1[1] OPD1[0] OPD0[7] OPD0[6] OPD0[5] OPD0[4] OPD0[3] OPD0[2] OPD0[1] OPD0[0] CDB[1] CDB[0] OCDB[1] OCDB[0]   ADB[1] ADB[0]   OPDB[1] OPDB[0]   SPIDB[1] SPIDB[0]  CDE  OCDE ADE[3] ADE[2] ADE[1] ADE[0] OPDE[3] OPDE[2] OPDE[1] OPDE[0] SPIDE[3] SPIDE[2] SPIDE[1] SPIDE[0] RDATA0[31] RDATA0[30] RDATA0[29] RDATA0[28] RDATA0[27] RDATA0[26] RDATA0[25] RDATA0[24] RDATA0[23] RDATA0[22] RDATA0[21] RDATA0[20] RDATA0[19] RDATA0[18] RDATA0[17] RDATA0[16] RDATA0[15] RDATA0[14] RDATA0[13] RDATA0[12] RDATA0[11] RDATA0[10] RDATA0[9] RDATA0[8] RDATA0[7] RDATA0[6] RDATA0[5] RDATA0[4] RDATA0[3] RDATA0[2] RDATA0[1] RDATA0[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 SPI multi I/O SMRDR1 RDATA1[31] RDATA1[30] RDATA1[29] RDATA1[28] RDATA1[27] RDATA1[26] RDATA1[25] RDATA1[24] RDATA1[23] RDATA1[22] RDATA1[21] RDATA1[20] RDATA1[19] RDATA1[18] RDATA1[17] RDATA1[16] RDATA1[15] RDATA1[14] RDATA1[13] RDATA1[12] RDATA1[11] RDATA1[10] RDATA1[9] RDATA1[8] RDATA1[7] RDATA1[6] RDATA1[5] RDATA1[4] RDATA1[3] RDATA1[2] RDATA1[1] RDATA1[0] WDATA0[31] WDATA0[30] WDATA0[29] WDATA0[28] WDATA0[27] WDATA0[26] WDATA0[25] WDATA0[24] WDATA0[23] WDATA0[22] WDATA0[21] WDATA0[20] WDATA0[19] WDATA0[18] WDATA0[17] WDATA0[16] bus controller SMWDR0 WDATA0[15] WDATA0[14] WDATA0[13] WDATA0[12] WDATA0[11] WDATA0[10] WDATA0[9] WDATA0[8] WDATA0[7] WDATA0[6] WDATA0[5] WDATA0[4] WDATA0[3] WDATA0[2] WDATA0[1] WDATA0[0] WDATA1[31] WDATA1[30] WDATA1[29] WDATA1[28] WDATA1[27] WDATA1[26] WDATA1[25] WDATA1[24] WDATA1[23] WDATA1[22] WDATA1[21] WDATA1[20] WDATA1[19] WDATA1[18] WDATA1[17] WDATA1[16] WDATA1[15] WDATA1[14] WDATA1[13] WDATA1[12] WDATA1[11] WDATA1[10] WDATA1[9] WDATA1[8] WDATA1[7] WDATA1[6] WDATA1[5] WDATA1[4] WDATA1[3] WDATA1[2] WDATA1[1] WDATA1[0]                               SSLF TEND ICCR1_0 ICE RCVD MST TRS CKS[3] CKS[2] CKS[1] CKS[0] ICCR2_0 BBSY SCP SDAO SDAOP SCLO  IICRST  ICMR_0 MLS    BCWP BC[2] BC[1] BC[0] ICIER_0 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_0 TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ SAR_0 SVA[6] SVA[5] SVA[4] SVA[3] SVA[2] SVA[1] SVA[0] FS NF2CYC_0       PRS NF2CYC ICCR1_1 ICE RCVD MST TRS CKS[3] CKS[2] CKS[1] CKS[0] ICCR2_1 BBSY SCP SDAO SDAOP SCLO  IICRST  ICMR_1 MLS    BCWP BC[2] BC[1] BC[0] ICIER_1 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_1 TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ SAR_1 SVA[6] SVA[5] SVA[4] SVA[3] SVA[2] SVA[1] SVA[0] FS SMWDR1 CMNSR 2 I C bus interface 3 ICDRT_0 ICDRR_0 ICDRT_1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2847 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation 2 I C bus interface 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 NF2CYC_1       PRS NF2CYC ICCR1_2 ICE RCVD MST TRS CKS[3] CKS[2] CKS[1] CKS[0] ICCR2_2 BBSY SCP SDAO SDAOP SCLO  IICRST  ICMR_2 MLS    BCWP BC[2] BC[1] BC[0] ICIER_2 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_2 TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ SAR_2 SVA[6] SVA[5] SVA[4] SVA[3] SVA[2] SVA[1] SVA[0] FS NF2CYC_2       PRS NF2CYC ICCR1_3 ICE RCVD MST TRS CKS[3] CKS[2] CKS[1] CKS[0] ICCR2_3 BBSY SCP SDAO SDAOP SCLO  IICRST  ICMR_3 MLS    BCWP BC[2] BC[1] BC[0] ICIER_3 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_3 TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ SAR_3 SVA[6] SVA[5] SVA[4] SVA[3] SVA[2] SVA[1] SVA[0] FS NF2CYC_3       PRS NF2CYC SSICR_0  CKS TUIEN TOIEN RUIEN ROIEN IIEN  CHNL[1] CHNL[0] DWL[2] DWL[1] DWL[0] SWL[2] SWL[1] SWL[0] ICDRR_1 ICDRT_2 ICDRR_2 ICDRT_3 ICDRR_3 Serial sound interface SSISR_0 SSIFCR_0 Page 2848 of 3092 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV[3] CKDV[2] CKDV[1] CKDV[0] MUEN  TEN REN   TUIRQ TOIRQ RUIRQ ROIRQ IIRQ                   TCHNO[1] TCHNO[0] TSWNO RCHNO[1] RCHNO[0] RSWNO IDST                         TTRG[1] TTRG[0] RTRG[1] RTRG[0] TIE RIE TFRST RFRST R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial sound SSIFSR_0     TDC[3] TDC[2] TDC[1] TDC[0]        TDE     RDC[3] RDC[2] RDC[1] RDC[0]        RDF                        CONT        TDM  CKS TUIEN TOIEN RUIEN ROIEN IIEN  CHNL[1] CHNL[0] DWL[2] DWL[1] DWL[0] SWL[2] SWL[1] SWL[0] SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV[3] CKDV[2] CKDV[1] CKDV[0] MUEN  TEN REN   TUIRQ TOIRQ RUIRQ ROIRQ IIRQ                   TCHNO[1] TCHNO[0] TSWNO RCHNO[1] RCHNO[0] RSWNO IDST                         TTRG[1] TTRG[0] RTRG[1] RTRG[0] TIE RIE TFRST RFRST     TDC[3] TDC[2] TDC[1] TDC[0]        TDE     RDC[3] RDC[2] RDC[1] RDC[0]        RDF interface SSIFTDR_0 SSIFRDR_0 SSITDMR_0 SSICR_1 SSISR_1 SSIFCR_1 SSIFSR_1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2849 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Serial sound SSIFTDR_1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                        CONT        TDM  CKS TUIEN TOIEN RUIEN ROIEN IIEN  CHNL[1] CHNL[0] DWL[2] DWL[1] DWL[0] SWL[2] SWL[1] SWL[0] interface SSIFRDR_1 SSITDMR_1 SSICR_2 SSISR_2 SSIFCR_2 SSIFSR_2 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV[3] CKDV[2] CKDV[1] CKDV[0] MUEN  TEN REN   TUIRQ TOIRQ RUIRQ ROIRQ IIRQ                   TCHNO[1] TCHNO[0] TSWNO RCHNO[1] RCHNO[0] RSWNO IDST                         TTRG[1] TTRG[0] RTRG[1] RTRG[0] TIE RIE TFRST RFRST     TDC[3] TDC[2] TDC[1] TDC[0]        TDE     RDC[3] RDC[2] RDC[1] RDC[0]        RDF SSIFTDR_2 Page 2850 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Serial sound SSIFRDR_2 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                        CONT        TDM  CKS TUIEN TOIEN RUIEN ROIEN IIEN  CHNL[1] CHNL[0] DWL[2] DWL[1] DWL[0] SWL[2] SWL[1] SWL[0] SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV[3] CKDV[2] CKDV[1] CKDV[0] MUEN  TEN REN   TUIRQ TOIRQ RUIRQ ROIRQ IIRQ                   TCHNO[1] TCHNO[0] TSWNO RCHNO[1] RCHNO[0] RSWNO IDST                         TTRG[1] TTRG[0] RTRG[1] RTRG[0] TIE RIE TFRST RFRST     TDC[3] TDC[2] TDC[1] TDC[0]        TDE     RDC[3] RDC[2] RDC[1] RDC[0]        RDF interface SSITDMR_2 SSICR_3 SSISR_3 SSIFCR_3 SSIFSR_3 SSIFTDR_3 SSIFRDR_3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2851 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial sound SSITDMR_3                        CONT        TDM  CKS TUIEN TOIEN RUIEN ROIEN IIEN  CHNL[1] CHNL[0] DWL[2] DWL[1] DWL[0] SWL[2] SWL[1] SWL[0] interface SSICR_4 SSISR_4 SSIFCR_4 SSIFSR_4 SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV[3] CKDV[2] CKDV[1] CKDV[0] MUEN  TEN REN   TUIRQ TOIRQ RUIRQ ROIRQ IIRQ                   TCHNO[1] TCHNO[0] TSWNO RCHNO[1] RCHNO[0] RSWNO IDST                         TTRG[1] TTRG[0] RTRG[1] RTRG[0] TIE RIE TFRST RFRST     TDC[3] TDC[2] TDC[1] TDC[0]        TDE     RDC[3] RDC[2] RDC[1] RDC[0]        RDF                        CONT        TDM SSIFTDR_4 SSIFRDR_4 SSITDMR_4 Page 2852 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Serial sound SSICR_5  CKS TUIEN TOIEN RUIEN ROIEN IIEN  CHNL[1] CHNL[0] DWL[2] DWL[1] DWL[0] SWL[2] SWL[1] SWL[0] SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL CKDV[3] CKDV[2] CKDV[1] CKDV[0] MUEN  TEN REN   TUIRQ TOIRQ RUIRQ ROIRQ IIRQ                   TCHNO[1] TCHNO[0] TSWNO RCHNO[1] RCHNO[0] RSWNO IDST                         TTRG[1] TTRG[0] RTRG[1] RTRG[0] TIE RIE TFRST RFRST     TDC[3] TDC[2] TDC[1] TDC[0]        TDE     RDC[3] RDC[2] RDC[1] RDC[0]        RDF                        CONT        TDM TRMD[1] TRMD[0] SYNCAT REDG FL[3] FL[2] FL[1] FL[0] TXDIZ  SYNCAC SYNCDL     interface SSISR_5 SSIFCR_5 SSIFSR_5 SSIFTDR_5 SSIFRDR_5 SSITDMR_5 Serial I/O with SIMDR FIFO SISCR MSSEL   BRPS[4] BRPS[3] BRPS[2] BRPS[1] BRPS[0]      BRDV[2] BRDV[1] BRDV[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2853 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Serial I/O with SITDAR FIFO SIRDAR SICTR SIFCTR SISTR SIIER SITDR SIRDR Controller MCR_0 area network GSR_0 BCR1_0 BCR0_0 IRR_0 IMR_0 Page 2854 of 3092 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 TDLE    TDLA[3] TDLA[2] TDLA[1] TDLA[0] TDRE TLREP   TDRA[3] TDRA[2] TDRA[1] TDRA[0] RDLE    RDLA[3] RDLA[2] RDLA[1] RDLA[0] RDRE    RDRA[3] RDRA[2] RDRA[1] RDRA[0] SCKE FSE     TXE RXE       TXRST RXRST TFWM[2] TFWM[1] TFWM[0] TFUA[4] TFUA[3] TFUA[2] TFUA[1] TFUA[0] RFWM[2] RFWM[1] RFWM[0] RFUA[4] RFUA[3] RFUA[2] RFUA[1] RFUA[0]   TFEMP TDREQ   RFFUL RDREQ    FSERR TFOVF TFUDF RFUDF RFOVF TDMAE  TFEMPE TDREQE RDMAE  RFFULE RDREQE    FSERRE TFOVFE TFUDFE RFUDFE RFOVFE SITDL[15] SITDL[14] SITDL[13] SITDL[12] SITDL[11] SITDL[10] SITDL[9] SITDL[8] SITDL[7] SITDL[6] SITDL[5] SITDL[4] SITDL[3] SITDL[2] SITDL[1] SITDL[0] SITDR[15] SITDR[14] SITDR[13] SITDR[12] SITDR[11] SITDR[10] SITDR[9] SITDR[8] SITDR[7] SITDR[6] SITDR[5] SITDR[4] SITDR[3] SITDR[2] SITDR[1] SITDR[0] SIRDL[15] SIRDL[14] SIRDL[13] SIRDL[12] SIRDL[11] SIRDL[10] SIRDL[9] SIRDL[8] SIRDL[7] SIRDL[6] SIRDL[5] SIRDL[4] SIRDL[3] SIRDL[2] SIRDL[1] SIRDL[0] SIRDR[15] SIRDR[14] SIRDR[13] SIRDR[12] SIRDR[11] SIRDR[10] SIRDR[9] SIRDR[8] SIRDR[7] SIRDR[6] SIRDR[5] SIRDR[4] SIRDR[3] SIRDR[2] SIRDR[1] SIRDR[0] MCR15 MCR14    TST[2] TST[1] TST[0] MCR7 MCR6 MCR5   MCR2 MCR1 MCR0           GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 TSG1[3] TSG1[2] TSG1[1] TSG1[0]  TSG2[2] TSG2[1] TSG2[0]   SJW[1] SJW[0]    BSP         BRP[7] BRP[6] BRP[5] BRP[4] BRP[3] BRP[2] BRP[1] BRP[0] IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller TEC_REC_0 TEC[7] TEC[6] TEC[5] TEC[4] TEC[3] TEC[2] TEC[1] TEC[0] REC[7] REC[6] REC[5] REC[4] REC[3] REC[2] REC[1] REC[0] TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[8] TXPR1[7] TXPR1[6] TXPR1[5] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[0] TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[8] TXPR0[7] TXPR0[6] TXPR0[5] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1]  TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[8] TXCR1[7] TXCR1[6] TXCR1[5] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[0] TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[8] TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1]  TXACK1[15] TXACK1[14] TXACK1[13] TXACK1[12] TXACK1[11] TXACK1[10] TXACK1[9] TXACK1[8] TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0[15] TXACK0[14] TXACK0[13] TXACK0[12] TXACK0[11] TXACK0[10] TXACK0[9] TXACK0[8] TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1]  area network TXPR1_0 TXPR0_0 TXCR1_0 TXCR0_0 TXACK1_0 TXACK0_0 ABACK1_0 ABACK0_0 RXPR1_0 RXPR0_0 RFPR1_0 RFPR0_0 MBIMR1_0 MBIMR0_0 UMSR1_0 ABACK1[15] ABACK1[14] ABACK1[13] ABACK1[12] ABACK1[11] ABACK1[10] ABACK1[9] ABACK1[8] ABACK1[7] ABACK1[6] ABACK1[5] ABACK1[4] ABACK1[3] ABACK1[2] ABACK1[1] ABACK1[0] ABACK0[15] ABACK0[14] ABACK0[13] ABACK0[12] ABACK0[11] ABACK0[10] ABACK0[9] ABACK0[8] ABACK0[7] ABACK0[6] ABACK0[5] ABACK0[4] ABACK0[3] ABACK0[2] ABACK0[1]  RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[8] RXPR1[7] RXPR1[6] RXPR1[5] RXPR1[4] RXPR1[3] RXPR1[2] RXPR1[1] RXPR1[0] RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0[9] RXPR0[8] RXPR0[7] RXPR0[6] RXPR0[5] RXPR0[4] RXPR0[3] RXPR0[2] RXPR0[1] RXPR0[0] RFPR1[15] RFPR1[14] RFPR1[13] RFPR1[12] RFPR1[11] RFPR1[10] RFPR1[9] RFPR1[8] RFPR1[7] RFPR1[6] RFPR1[5] RFPR1[4] RFPR1[3] RFPR1[2] RFPR1[1] RFPR1[0] RFPR0[15] RFPR0[14] RFPR0[13] RFPR0[12] RFPR0[11] RFPR0[10] RFPR0[9] RFPR0[8] RFPR0[7] RFPR0[6] RFPR0[5] RFPR0[4] RFPR0[3] RFPR0[2] RFPR0[1] RFPR0[0] MBIMR1[15] MBIMR1[14] MBIMR1[13] MBIMR1[12] MBIMR1[11] MBIMR1[10] MBIMR1[9] MBIMR1[8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] MBIMR0[15] MBIMR0[14] MBIMR0[13] MBIMR0[12] MBIMR0[11] MBIMR0[10] MBIMR0[9] MBIMR0[8] MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] UMSR1[15] UMSR1[14] UMSR1[13] UMSR1[12] UMSR1[11] UMSR1[10] UMSR1[9] UMSR1[8] UMSR1[7] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2855 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller UMSR0_0 UMSR0[15] UMSR0[14] UMSR0[13] UMSR0[12] UMSR0[11] UMSR0[10] UMSR0[9] UMSR0[8] UMSR0[7] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] TCR15 TCR14 TCR13 TCR12 TCR11 TCR10    TCR6 TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0      CMAX[2] CMAX[1] CMAX[0]     TEW[3] TEW[2] TEW[1] TEW[0] area network TTCR0_0 CMAX_TEW_0 RFTROFF_0 TSR_0 CCR_0 TCNTR_0 CYCTR_0 RFMK_0 TCMR0_0 TCMR1_0 TCMR2_0 TTTSEL_0 RFTROFF[7] RFTROFF[6] RFTROFF[5] RFTROFF[4] RFTROFF[3] RFTROFF[2] RFTROFF[1] RFTROFF[0]                    TSR4 TSR3 TSR2 TSR1 TSR0           CCR[5] CCR[4] CCR[3] CCR[2] CCR[1] CCR[0] TCNTR[15] TCNTR[14] TCNTR[13] TCNTR[12] TCNTR[11] TCNTR[10] TCNTR[9] TCNTR[8] TCNTR[7] TCNTR[6] TCNTR[5] TCNTR[4] TCNTR[3] TCNTR[2] TCNTR[1] TCNTR[0] CYCTR[15] CYCTR[14] CYCTR[13] CYCTR[12] CYCTR[11] CYCTR[10] CYCTR[9] CYCTR[8] CYCTR[7] CYCTR[6] CYCTR[5] CYCTR[4] CYCTR[3] CYCTR[2] CYCTR[1] CYCTR[0] RFMK[15] RFMK[14] RFMK[13] RFMK[12] RFMK[11] RFMK[10] RFMK[9] RFMK[8] RFMK[7] RFMK[6] RFMK[5] RFMK[4] RFMK[3] RFMK[2] RFMK[1] RFMK[0] TCMR0[15] TCMR0[14] TCMR0[13] TCMR0[12] TCMR0[11] TCMR0[10] TCMR0[9] TCMR0[8] TCMR0[7] TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1[15] TCMR1[14] TCMR1[13] TCMR1[12] TCMR1[11] TCMR1[10] TCMR1[9] TCMR1[8] TCMR1[7] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2[15] TCMR2[14] TCMR2[13] TCMR2[12] TCMR2[11] TCMR2[10] TCMR2[9] TCMR2[8] TCMR2[7] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0]  TTTSEL[14] TTTSEL[13] TTTSEL[12] TTTSEL[11] TTTSEL[10] TTTSEL[9] TTTSEL[8]         STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] RTR  STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] EXTID[17] EXTID[16] MBn_CONTRO  L0_H_0 STDID[3] 1 (n = 0 to 31)* MBn_CONTRO IDE L0_H_0 STDID[5] 2 (n = 0 to 31)* Page 2856 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Controller MBn_CONTRO EXTID[15] area network L0_L_0 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 EXTID[7] Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] (n = 0 to 31) MBn_LAFM0_0  STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ LAFM[10] LAFM[9] LAFM[8] LAFM[7] LAFM[6] LAFM[5] LAFM[4] STDID_ STDID_ STDID_ STDID_  IDE LAFM[3] LAFM[2] LAFM[1] LAFM[0]   STDID_ STDID_ LAFM[10] LAFM[9] 1 (n = 0 to 31)* MBn_LAFM0_0 IDE 2 (n = 0 to 31)* EXTID_ EXTID_ LAFM[17] LAFM[16] STDID_ STDID_ STDID_ LAFM[8] LAFM[7] LAFM[6] STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ EXTID_ EXTID_ LAFM[5] LAFM[4] LAFM[3] LAFM[2] LAFM[1] LAFM[0] LAFM[17] LAFM[16] MBn_LAFM1_0 EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ (n = 0 to 31) LAFM[15] LAFM[14] LAFM[13] LAFM[12] LAFM[11] LAFM[10] LAFM[9] LAFM[8] EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ LAFM[7] LAFM[6] LAFM[5] LAFM[4] LAFM[3] LAFM[2] LAFM[1] LAFM[0] MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MBn_DATA_ 01_0 (n = 0 to 31) MBn_DATA_ 23_0 (n = 0 to 31) MBn_DATA_ 45_0 (n = 0 to 31) MBn_DATA_ MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7  NMC   MBC[2] MBC[1] MBC[0]     DLC[3] DLC[2] DLC[1] DLC[0] MBn_CONTRO   NMC ATX DART MBC[2] MBC[1] MBC[0]    DLC[3] DLC[2] DLC[1] DLC[0] TS14 TS13 TS12 TS11 TS10 TS9 TS8 TS6 TS5 TS4 TS3 TS2 TS1 TS0 67_0 (n = 0 to 31) MBn_CONTRO  L1_0 (n = 0) L1_0  (n = 1 to 31) MBn_TIMESTA TS15 MP_0 TS7 (n = 0 to 15, 30, 31) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2857 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller MBn_TTT_0 TTT15 TTT14 TTT13 TTT12 TTT11 TTT10 TTT9 TTT8 area network (n = 24 to 30) TTT7 TTT6 TTT5 TTT4 TTT3 TTT2 TTT1 TTT0 TTW[1] TTW[0] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0]      REP_ REP_ REP_ FACTOR[2] FACTOR[1] FACTOR[0] MBn_TTCONT ROL_0 (n = 24 to 29) MCR_1 GSR_1 BCR1_1 BCR0_1 IRR_1 IMR_1 TEC_REC_1 TXPR1_1 TXPR0_1 TXCR1_1 TXCR0_1 TXACK1_1 TXACK0_1 Page 2858 of 3092 MCR15 MCR14    TST[2] TST[1] TST[0] MCR7 MCR6 MCR5   MCR2 MCR1 MCR0           GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 TSG1[3] TSG1[2] TSG1[1] TSG1[0]  TSG2[2] TSG2[1] TSG2[0]   SJW[1] SJW[0]    BSP         BRP[7] BRP[6] BRP[5] BRP[4] BRP[3] BRP[2] BRP[1] BRP[0] IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 TEC[7] TEC[6] TEC[5] TEC[4] TEC[3] TEC[2] TEC[1] TEC[0] REC[7] REC[6] REC[5] REC[4] REC[3] REC[2] REC[1] REC[0] TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[8] TXPR1[7] TXPR1[6] TXPR1[5] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[0] TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[8] TXPR0[7] TXPR0[6] TXPR0[5] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1]  TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[8] TXCR1[7] TXCR1[6] TXCR1[5] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[0] TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[8] TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1]  TXACK1[15] TXACK1[14] TXACK1[13] TXACK1[12] TXACK1[11] TXACK1[10] TXACK1[9] TXACK1[8] TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0[15] TXACK0[14] TXACK0[13] TXACK0[12] TXACK0[11] TXACK0[10] TXACK0[9] TXACK0[8] TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1]  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller ABACK1_1 ABACK1[15] ABACK1[14] ABACK1[13] ABACK1[12] ABACK1[11] ABACK1[10] ABACK1[9] ABACK1[8] ABACK1[7] ABACK1[6] ABACK1[5] ABACK1[4] ABACK1[3] ABACK1[2] ABACK1[1] ABACK1[0] ABACK0[15] ABACK0[14] ABACK0[13] ABACK0[12] ABACK0[11] ABACK0[10] ABACK0[9] ABACK0[8] ABACK0[7] ABACK0[6] ABACK0[5] ABACK0[4] ABACK0[3] ABACK0[2] ABACK0[1]  RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[8] RXPR1[7] RXPR1[6] RXPR1[5] RXPR1[4] RXPR1[3] RXPR1[2] RXPR1[1] RXPR1[0] RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0[9] RXPR0[8] RXPR0[7] RXPR0[6] RXPR0[5] RXPR0[4] RXPR0[3] RXPR0[2] RXPR0[1] RXPR0[0] RFPR1[15] RFPR1[14] RFPR1[13] RFPR1[12] RFPR1[11] RFPR1[10] RFPR1[9] RFPR1[8] RFPR1[7] RFPR1[6] RFPR1[5] RFPR1[4] RFPR1[3] RFPR1[2] RFPR1[1] RFPR1[0] RFPR0[15] RFPR0[14] RFPR0[13] RFPR0[12] RFPR0[11] RFPR0[10] RFPR0[9] RFPR0[8] RFPR0[7] RFPR0[6] RFPR0[5] RFPR0[4] RFPR0[3] RFPR0[2] RFPR0[1] RFPR0[0] MBIMR1[15] MBIMR1[14] MBIMR1[13] MBIMR1[12] MBIMR1[11] MBIMR1[10] MBIMR1[9] MBIMR1[8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] area network ABACK0_1 RXPR1_1 RXPR0_1 RFPR1_1 RFPR0_1 MBIMR1_1 MBIMR0_1 UMSR1_1 UMSR0_1 TTCR0_1 CMAX_TEW_1 RFTROFF_1 TSR_1 CCR_1 TCNTR_1 MBIMR0[15] MBIMR0[14] MBIMR0[13] MBIMR0[12] MBIMR0[11] MBIMR0[10] MBIMR0[9] MBIMR0[8] MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] UMSR1[15] UMSR1[14] UMSR1[13] UMSR1[12] UMSR1[11] UMSR1[10] UMSR1[9] UMSR1[8] UMSR1[7] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0] UMSR0[15] UMSR0[14] UMSR0[13] UMSR0[12] UMSR0[11] UMSR0[10] UMSR0[9] UMSR0[8] UMSR0[7] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] TCR15 TCR14 TCR13 TCR12 TCR11 TCR10    TCR6 TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0      CMAX[2] CMAX[1] CMAX[0]     TEW[3] TEW[2] TEW[1] TEW[0] RFTROFF[7] RFTROFF[6] RFTROFF[5] RFTROFF[4] RFTROFF[3] RFTROFF[2] RFTROFF[1] RFTROFF[0]                    TSR4 TSR3 TSR2 TSR1 TSR0           CCR[5] CCR[4] CCR[3] CCR[2] CCR[1] CCR[0] TCNTR[15] TCNTR[14] TCNTR[13] TCNTR[12] TCNTR[11] TCNTR[10] TCNTR[9] TCNTR[8] TCNTR[7] TCNTR[6] TCNTR[5] TCNTR[4] TCNTR[3] TCNTR[2] TCNTR[1] TCNTR[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2859 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller CYCTR_1 CYCTR[15] CYCTR[14] CYCTR[13] CYCTR[12] CYCTR[11] CYCTR[10] CYCTR[9] CYCTR[8] CYCTR[7] CYCTR[6] CYCTR[5] CYCTR[4] CYCTR[3] CYCTR[2] CYCTR[1] CYCTR[0] RFMK[15] RFMK[14] RFMK[13] RFMK[12] RFMK[11] RFMK[10] RFMK[9] RFMK[8] RFMK[7] RFMK[6] RFMK[5] RFMK[4] RFMK[3] RFMK[2] RFMK[1] RFMK[0] TCMR0[15] TCMR0[14] TCMR0[13] TCMR0[12] TCMR0[11] TCMR0[10] TCMR0[9] TCMR0[8] TCMR0[7] TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1[15] TCMR1[14] TCMR1[13] TCMR1[12] TCMR1[11] TCMR1[10] TCMR1[9] TCMR1[8] TCMR1[7] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2[15] TCMR2[14] TCMR2[13] TCMR2[12] TCMR2[11] TCMR2[10] TCMR2[9] TCMR2[8] TCMR2[7] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0]  TTTSEL[14] TTTSEL[13] TTTSEL[12] TTTSEL[11] TTTSEL[10] TTTSEL[9] TTTSEL[8]         STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] RTR  STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] EXTID[17] EXTID[16] area network RFMK_1 TCMR0_1 TCMR1_1 TCMR2_1 TTTSEL_1 MBn_CONTRO  L0_H_1 STDID[3] 1 (n = 0 to 31)* MBn_CONTRO IDE L0_H_1 STDID[5] 2 (n = 0 to 31)* MBn_CONTRO EXTID[15] L0_L_1 EXTID[7] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] (n = 0 to 31) MBn_LAFM0_1  STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ LAFM[10] LAFM[9] LAFM[8] LAFM[7] LAFM[6] LAFM[5] LAFM[4] STDID_ STDID_ STDID_ STDID_  IDE LAFM[3] LAFM[2] LAFM[1] LAFM[0]   STDID_ STDID_ LAFM[10] LAFM[9] 1 (n = 0 to 31)* MBn_LAFM0_1 IDE 2 (n = 0 to 31)* EXTID_ EXTID_ LAFM[17] LAFM[16] STDID_ STDID_ STDID_ LAFM[8] LAFM[7] LAFM[6] STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ EXTID_ EXTID_ LAFM[5] LAFM[4] LAFM[3] LAFM[2] LAFM[1] LAFM[0] LAFM[17] LAFM[16] MBn_LAFM1_1 EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ (n = 0 to 31) LAFM[15] LAFM[14] LAFM[13] LAFM[12] LAFM[11] LAFM[10] LAFM[9] LAFM[8] EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ LAFM[7] LAFM[6] LAFM[5] LAFM[4] LAFM[3] LAFM[2] LAFM[1] LAFM[0] MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MBn_DATA_ 01_1 (n = 0 to 31) Page 2860 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Controller MBn_DATA_ MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 area network 23_1 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7  NMC   MBC[2] MBC[1] MBC[0]     DLC[3] DLC[2] DLC[1] DLC[0] MBn_CONTRO   NMC ATX DART MBC[2] MBC[1] MBC[0]    DLC[3] DLC[2] DLC[1] DLC[0] TS14 TS13 TS12 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 TTT15 TTT14 TTT13 TTT12 TTT11 TTT10 TTT9 TTT8 TTT7 TTT6 TTT5 TTT4 TTT3 TTT2 TTT1 TTT0 TTW[1] TTW[0] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0]      REP_ REP_ REP_ FACTOR[2] FACTOR[1] FACTOR[0] Bit 24/16/8/0 (n = 0 to 31) MBn_DATA_ 45_1 (n = 0 to 31) MBn_DATA_ 67_1 (n = 0 to 31) MBn_CONTRO  L1_1 (n = 0) L1_1  (n = 1 to 31) MBn_TIMESTA TS15 MP_1 (n = 0 to 15, 30, 31) MBn_TTT_1 (n = 24 to 30) MBn_TTCONT ROL_1 (n = 24 to 29) MCR_2 GSR_2 BCR1_2 BCR0_2 IRR_2 IMR_2 MCR15 MCR14    TST[2] TST[1] TST[0] MCR7 MCR6 MCR5   MCR2 MCR1 MCR0           GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 TSG1[3] TSG1[2] TSG1[1] TSG1[0]  TSG2[2] TSG2[1] TSG2[0]   SJW[1] SJW[0]    BSP         BRP[7] BRP[6] BRP[5] BRP[4] BRP[3] BRP[2] BRP[1] BRP[0] IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2861 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller TEC_REC_2 TEC[7] TEC[6] TEC[5] TEC[4] TEC[3] TEC[2] TEC[1] TEC[0] REC[7] REC[6] REC[5] REC[4] REC[3] REC[2] REC[1] REC[0] TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[8] TXPR1[7] TXPR1[6] TXPR1[5] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[0] TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[8] TXPR0[7] TXPR0[6] TXPR0[5] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1]  area network TXPR1_2 TXPR0_2 TXCR1_2 TXCR0_2 TXACK1_2 TXACK0_2 ABACK1_2 ABACK0_2 RXPR1_2 RXPR0_2 RFPR1_2 RFPR0_2 MBIMR1_2 MBIMR0_2 UMSR1_2 Page 2862 of 3092 TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[8] TXCR1[7] TXCR1[6] TXCR1[5] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[0] TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[8] TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1]  TXACK1[15] TXACK1[14] TXACK1[13] TXACK1[12] TXACK1[11] TXACK1[10] TXACK1[9] TXACK1[8] TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0[15] TXACK0[14] TXACK0[13] TXACK0[12] TXACK0[11] TXACK0[10] TXACK0[9] TXACK0[8] TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1]  ABACK1[15] ABACK1[14] ABACK1[13] ABACK1[12] ABACK1[11] ABACK1[10] ABACK1[9] ABACK1[8] ABACK1[7] ABACK1[6] ABACK1[5] ABACK1[4] ABACK1[3] ABACK1[2] ABACK1[1] ABACK1[0] ABACK0[15] ABACK0[14] ABACK0[13] ABACK0[12] ABACK0[11] ABACK0[10] ABACK0[9] ABACK0[8] ABACK0[7] ABACK0[6] ABACK0[5] ABACK0[4] ABACK0[3] ABACK0[2] ABACK0[1]  RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[8] RXPR1[7] RXPR1[6] RXPR1[5] RXPR1[4] RXPR1[3] RXPR1[2] RXPR1[1] RXPR1[0] RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0[9] RXPR0[8] RXPR0[7] RXPR0[6] RXPR0[5] RXPR0[4] RXPR0[3] RXPR0[2] RXPR0[1] RXPR0[0] RFPR1[15] RFPR1[14] RFPR1[13] RFPR1[12] RFPR1[11] RFPR1[10] RFPR1[9] RFPR1[8] RFPR1[7] RFPR1[6] RFPR1[5] RFPR1[4] RFPR1[3] RFPR1[2] RFPR1[1] RFPR1[0] RFPR0[15] RFPR0[14] RFPR0[13] RFPR0[12] RFPR0[11] RFPR0[10] RFPR0[9] RFPR0[8] RFPR0[7] RFPR0[6] RFPR0[5] RFPR0[4] RFPR0[3] RFPR0[2] RFPR0[1] RFPR0[0] MBIMR1[15] MBIMR1[14] MBIMR1[13] MBIMR1[12] MBIMR1[11] MBIMR1[10] MBIMR1[9] MBIMR1[8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] MBIMR0[15] MBIMR0[14] MBIMR0[13] MBIMR0[12] MBIMR0[11] MBIMR0[10] MBIMR0[9] MBIMR0[8] MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] UMSR1[15] UMSR1[14] UMSR1[13] UMSR1[12] UMSR1[11] UMSR1[10] UMSR1[9] UMSR1[8] UMSR1[7] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller UMSR0_2 UMSR0[15] UMSR0[14] UMSR0[13] UMSR0[12] UMSR0[11] UMSR0[10] UMSR0[9] UMSR0[8] UMSR0[7] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] TCR15 TCR14 TCR13 TCR12 TCR11 TCR10    TCR6 TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0      CMAX[2] CMAX[1] CMAX[0]     TEW[3] TEW[2] TEW[1] TEW[0] area network TTCR0_2 CMAX_TEW_2 RFTROFF_2 TSR_2 CCR_2 TCNTR_2 CYCTR_2 RFMK_2 TCMR0_2 TCMR1_2 TCMR2_2 TTTSEL_2 RFTROFF[7] RFTROFF[6] RFTROFF[5] RFTROFF[4] RFTROFF[3] RFTROFF[2] RFTROFF[1] RFTROFF[0]                    TSR4 TSR3 TSR2 TSR1 TSR0           CCR[5] CCR[4] CCR[3] CCR[2] CCR[1] CCR[0] TCNTR[15] TCNTR[14] TCNTR[13] TCNTR[12] TCNTR[11] TCNTR[10] TCNTR[9] TCNTR[8] TCNTR[7] TCNTR[6] TCNTR[5] TCNTR[4] TCNTR[3] TCNTR[2] TCNTR[1] TCNTR[0] CYCTR[15] CYCTR[14] CYCTR[13] CYCTR[12] CYCTR[11] CYCTR[10] CYCTR[9] CYCTR[8] CYCTR[7] CYCTR[6] CYCTR[5] CYCTR[4] CYCTR[3] CYCTR[2] CYCTR[1] CYCTR[0] RFMK[15] RFMK[14] RFMK[13] RFMK[12] RFMK[11] RFMK[10] RFMK[9] RFMK[8] RFMK[7] RFMK[6] RFMK[5] RFMK[4] RFMK[3] RFMK[2] RFMK[1] RFMK[0] TCMR0[15] TCMR0[14] TCMR0[13] TCMR0[12] TCMR0[11] TCMR0[10] TCMR0[9] TCMR0[8] TCMR0[7] TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1[15] TCMR1[14] TCMR1[13] TCMR1[12] TCMR1[11] TCMR1[10] TCMR1[9] TCMR1[8] TCMR1[7] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2[15] TCMR2[14] TCMR2[13] TCMR2[12] TCMR2[11] TCMR2[10] TCMR2[9] TCMR2[8] TCMR2[7] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0]  TTTSEL[14] TTTSEL[13] TTTSEL[12] TTTSEL[11] TTTSEL[10] TTTSEL[9] TTTSEL[8]         STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] RTR  STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] EXTID[17] EXTID[16] MBn_CONTRO  L0_H_2 STDID[3] 1 (n = 0 to 31)* MBn_CONTRO IDE L0_H_2 STDID[5] 2 (n = 0 to 31)* R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2863 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Controller MBn_CONTRO EXTID[15] area network L0_L_2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 EXTID[7] Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] (n = 0 to 31) MBn_LAFM0_2  STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ LAFM[10] LAFM[9] LAFM[8] LAFM[7] LAFM[6] LAFM[5] LAFM[4] STDID_ STDID_ STDID_ STDID_  IDE LAFM[3] LAFM[2] LAFM[1] LAFM[0]   STDID_ STDID_ LAFM[10] LAFM[9] 1 (n = 0 to 31)* MBn_LAFM0_2 IDE 2 (n = 0 to 31)* EXTID_ EXTID_ LAFM[17] LAFM[16] STDID_ STDID_ STDID_ LAFM[8] LAFM[7] LAFM[6] STDID_ STDID_ STDID_ STDID_ STDID_ STDID_ EXTID_ EXTID_ LAFM[5] LAFM[4] LAFM[3] LAFM[2] LAFM[1] LAFM[0] LAFM[17] LAFM[16] MBn_LAFM1_2 EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ (n = 0 to 31) LAFM[15] LAFM[14] LAFM[13] LAFM[12] LAFM[11] LAFM[10] LAFM[9] LAFM[8] EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ EXTID_ LAFM[7] LAFM[6] LAFM[5] LAFM[4] LAFM[3] LAFM[2] LAFM[1] LAFM[0] MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA0 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MSG_DATA1 MBn_DATA_ 01_2 (n = 0 to 31) MBn_DATA_ MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA2 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA3 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA4 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA5 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA6 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7 MSG_DATA7  NMC   MBC[2] MBC[1] MBC[0]     DLC[3] DLC[2] DLC[1] DLC[0] MBn_CONTRO   NMC ATX DART MBC[2] MBC[1] MBC[0]     DLC[3] DLC[2] DLC[1] DLC[0] TS15 TS14 TS13 TS12 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 23_2 (n = 0 to 31) MBn_DATA_ 45_2 (n = 0 to 31) MBn_DATA_ 67_2 (n = 0 to 31) MBn_CONTRO  L1_2 (n = 0) L1_2 (n = 1 to 31) MBn_TIME STAMP_2 (n = 0 to 15, 30, 31) Page 2864 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Controller MBn_TTT_2 TTT15 TTT14 TTT13 TTT12 TTT11 TTT10 TTT9 TTT8 area network (n = 24 to 30) TTT7 TTT6 TTT5 TTT4 TTT3 TTT2 TTT1 TTT0 TTW[1] TTW[0] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0]      REP_FACTO REP_FACTO REP_FACTO R[2] R[1] R[0] MBn_TT CONTROL_2 (n = 24 to 29) TM IEBus controller IECTR  IOL DEE  RE    IECMR      CMD[2] CMD[1] CMD[0] IEMCR SS RN[2] RN[1] RN[0] CTL[3] CTL[2] CTL[1] CTL[0] IEAR1 IARL4[3] IARL4[2] IARL4[1] IARL4[0] IMD[1] IMD[0]  STE IEAR2 IARU8[7] IARU8[6] IARU8[5] IARU8[4] IARU8[3] IARU8[2] IARU8[1] IARU8[0] IESA1 ISAL4[3] ISAL4[2] ISAL4[1] ISAL4[0]     IESA2 ISAU8[7] ISAU8[6] ISAU8[5] ISAU8[4] ISAU8[3] ISAU8[2] ISAU8[1] ISAU8[0] IETBFL IBFL[7] IBFL[6] IBFL[5] IBFL[4] IBFL[3] IBFL[2] IBFL[1] IBFL[0] IEMA1 IMAL4[3] IMAL4[2] IMAL4[1] IMAL4[0]     IEMA2 IMAU8[7] IMAU8[6] IMAU8[5] IMAU8[4] IMAU8[3] IMAU8[2] IMAU8[1] IMAU8[0] IERCTL     RCTL[3] RCTL[2] RCTL[1] RCTL[0] IERBFL RBFL[7] RBFL[6] RBFL[5] RBFL[4] RBFL[3] RBFL[2] RBFL[1] RBFL[0] IELA1 ILAL8[7] ILAL8[6] ILAL8[5] ILAL8[4] ILAL8[3] ILAL8[2] ILAL8[1] ILAL8[0] IELA2     ILAU4[3] ILAU4[2] ILAU4[1] ILAU4[0] IEFLG CMX MRQ SRQ SRE LCK  RSS GG IETSR  TXS TXF  TXEAL TXETTME TXERO TXEACK IEIET  TXSE TXFE  TXEALE TXETTMEE TXEROE TXEACKE IERSR RXBSY RXS RXF RXEDE RXEOVE RXERTME RXEDLE RXEPE IEIER RXBSYE RXSE RXFE RXEDEE RXEOVEE RXERTMEE RXEDLEE RXEPEE IECKSR    CKS3  CKS[2] CKS[1] CKS[0]         IETB001 to IETB128 IERB001 to IERB128 Renesas TLCA SPDIF interface R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2865 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Renesas TRCA         TLCS   CLAC[1] CLAC[0] FS[3] FS[2] FS[1] FS[0] CHNO[3] CHNO[2] CHNO[1] CHNO[0] SRCNO[3] SRCNO[2] SRCNO[1] SRCNO[0] SPDIF interface CATCD[7] CATCD[6] CATCD[5] CATCD[4] CATCD[3] CATCD[2] CATCD[1] CATCD[0]   CTL[4] CTL[3] CTL[2] CTL[1] CTL[0]    CLAC[1] CLAC[0] FS[3] FS[2] FS[1] FS[0] CHNO[3] CHNO[2] CHNO[1] CHNO[0] SRCNO[3] SRCNO[2] SRCNO[1] SRCNO[0] CATCD[7] CATCD[6] CATCD[5] CATCD[4] CATCD[3] CATCD[2] CATCD[1] CATCD[0]   CTL[4] CTL[3] CTL[2] CTL[1] CTL[0]  RLCA         RRCA         RLCS   CLAC[1] CLAC[0] FS[3] FS[2] FS[1] FS[0] CHNO[3] CHNO[2] CHNO[1] CHNO[0] SRCNO[3] SRCNO[2] SRCNO[1] SRCNO[0] CATCD[7] CATCD[6] CATCD[5] CATCD[4] CATCD[3] CATCD[2] CATCD[1] CATCD[0] CTL[4] CTL[3] CTL[2] CTL[1] CTL[0] TRCS TUI RRCS Page 2866 of 3092   CLAC[1] CLAC[0] FS[3] FS[2] FS[1] FS[0] CHNO[3] CHNO[2] CHNO[1] CHNO[0] SRCNO[3] SRCNO[2] SRCNO[1] SRCNO[0] CATCD[7] CATCD[6] CATCD[5] CATCD[4] CATCD[3] CATCD[2] CATCD[1] CATCD[0] CTL[4] CTL[3] CTL[2] CTL[1] CTL[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Renesas RUI Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0    CKS  PB RASS[1] RASS[0] TASS[1] TASS[0] RDE TDE NCSI AOS RME TME REIE TEIE UBOI UBUI CREI PAEI PREI CSEI ABOI ABUI RUII TUII RCSI RCBI TCSI TCBI                CMD RIS TIS UBO UBU CE PARE PREE CSE ABO ABU RUIR TUIR CSRX CBRX CSTX CBTX TDAD         RDAD         CROMEN SUBC_EN CROM_EN CROM_STP      CROMSY0 SY_AUT SY_IEN SY_DEN      SPDIF interface CTRL STAT CD-ROM decoder CROMCTL0 MD_DESC  MD_AUTO MD_AUTOS1 MD_AUTOS2 MD_SEC[2] MD_SEC[1] MD_SEC[0] CROMCTL1 M2F2EDC MD_DEC[2] MD_DEC[1] MD_DEC[0]   MD_ MD_ PQREP[1] PQREP[0] CROMCTL3 STP_ECC STP_EDC  STP_MD STP_MIN    CROMCTL4  LINK2  EROSEL NO_ECC    CROMCTL5        MSF_LBA_ SEL CROMST0   ST_SYIL ST_SYNO ST_BLKS ST_BLKL ST_SECS ST_SECL CROMST1     ER2_HEAD0 ER2_HEAD1 ER2_HEAD2 ER2_HEAD3 CROMST3 ER2_SHEAD0 ER2_SHEAD1 ER2_SHEAD2 ER2_SHEAD3 ER2_SHEAD4 ER2_SHEAD5 ER2_SHEAD6 ER2_SHEAD7 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2867 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 CD-ROM CROMST4 NG_MD NG_MDCMP1 NG_MDCMP2 NG_MDCMP3 NG_MDCMP4 NG_MDDEF NG_MDTIM1 NG_MDTIM2 CROMST5 ST_AMD[2] ST_AMD[1] ST_AMD[0] ST_MDX LINK_ON LINK_DET LINK_SDET LINK_OUT1 CROMST6 ST_ERR  ST_ECCABT ST_ECCNG ST_ECCP ST_ECCQ ST_EDC1 ST_EDC2 CBUFST0 BUF_REF BUF_ACT       CBUFST1 BUF_ECC BUF_EDC  BUF_MD BUF_MIN    CBUFST2 BUF_NG        HEAD00 HEAD00[7] HEAD00[6] HEAD00[5] HEAD00[4] HEAD00[3] HEAD00[2] HEAD00[1] HEAD00[0] HEAD01 HEAD01[7] HEAD01[6] HEAD01[5] HEAD01[4] HEAD01[3] HEAD01[2] HEAD01[1] HEAD01[0] HEAD02 HEAD02[7] HEAD02[6] HEAD02[5] HEAD02[4] HEAD02[3] HEAD02[2] HEAD02[1] HEAD02[0] HEAD03 HEAD03[7] HEAD03[6] HEAD03[5] HEAD03[4] HEAD03[3] HEAD03[2] HEAD03[1] HEAD03[0] SHEAD00 SHEAD00[7] SHEAD00[6] SHEAD00[5] SHEAD00[4] SHEAD00[3] SHEAD00[2] SHEAD00[1] SHEAD00[0] SHEAD01 SHEAD01[7] SHEAD01[6] SHEAD01[5] SHEAD01[4] SHEAD01[3] SHEAD01[2] SHEAD01[1] SHEAD01[0] SHEAD02 SHEAD02[7] SHEAD02[6] SHEAD02[5] SHEAD02[4] SHEAD02[3] SHEAD02[2] SHEAD02[1] SHEAD02[0] SHEAD03 SHEAD03[7] SHEAD03[6] SHEAD03[5] SHEAD03[4] SHEAD03[3] SHEAD03[2] SHEAD03[1] SHEAD03[0] SHEAD04 SHEAD04[7] SHEAD04[6] SHEAD04[5] SHEAD04[4] SHEAD04[3] SHEAD04[2] SHEAD04[1] SHEAD04[0] SHEAD05 SHEAD05[7] SHEAD05[6] SHEAD05[5] SHEAD05[4] SHEAD05[3] SHEAD05[2] SHEAD05[1] SHEAD05[0] SHEAD06 SHEAD06[7] SHEAD06[6] SHEAD06[5] SHEAD06[4] SHEAD06[3] SHEAD06[2] SHEAD06[1] SHEAD06[0] SHEAD07 SHEAD07[7] SHEAD07[6] SHEAD07[5] SHEAD07[4] SHEAD07[3] SHEAD07[2] SHEAD07[1] SHEAD07[0] HEAD20 HEAD20[7] HEAD20[6] HEAD20[5] HEAD20[4] HEAD20[3] HEAD20[2] HEAD20[1] HEAD20[0] HEAD21 HEAD21[7] HEAD21[6] HEAD21[5] HEAD21[4] HEAD21[3] HEAD21[2] HEAD21[1] HEAD21[0] HEAD22 HEAD22[7] HEAD22[6] HEAD22[5] HEAD22[4] HEAD22[3] HEAD22[2] HEAD22[1] HEAD22[0] HEAD23 HEAD23[7] HEAD23[6] HEAD23[5] HEAD23[4] HEAD23[3] HEAD23[2] HEAD23[1] HEAD23[0] SHEAD20 SHEAD20[7] SHEAD20[6] SHEAD20[5] SHEAD20[4] SHEAD20[3] SHEAD20[2] SHEAD20[1] SHEAD20[0] SHEAD21 SHEAD21[7] SHEAD21[6] SHEAD21[5] SHEAD21[4] SHEAD21[3] SHEAD21[2] SHEAD21[1] SHEAD21[0] SHEAD22 SHEAD22[7] SHEAD22[6] SHEAD22[5] SHEAD22[4] SHEAD22[3] SHEAD22[2] SHEAD22[1] SHEAD22[0] SHEAD23 SHEAD23[7] SHEAD23[6] SHEAD23[5] SHEAD23[4] SHEAD23[3] SHEAD23[2] SHEAD23[1] SHEAD23[0] SHEAD24 SHEAD24[7] SHEAD24[6] SHEAD24[5] SHEAD24[4] SHEAD24[3] SHEAD24[2] SHEAD24[1] SHEAD24[0] SHEAD25 SHEAD25[7] SHEAD25[6] SHEAD25[5] SHEAD25[4] SHEAD25[3] SHEAD25[2] SHEAD25[1] SHEAD25[0] SHEAD26 SHEAD26[7] SHEAD26[6] SHEAD26[5] SHEAD26[4] SHEAD26[3] SHEAD26[2] SHEAD26[1] SHEAD26[0] SHEAD27 SHEAD27[7] SHEAD27[6] SHEAD27[5] SHEAD27[4] SHEAD27[3] SHEAD27[2] SHEAD27[1] SHEAD27[0] decoder CBUFCTL0 CBUF_AUT CBUF_EN  CBUF_MD[1] CBUF_MD[0] CBUF_TS CBUF_Q  CBUFCTL1 BS_MIN[7] BS_MIN[6] BS_MIN[5] BS_MIN[4] BS_MIN[3] BS_MIN[2] BS_MIN[1] BS_MIN[0] Page 2868 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 CD-ROM CBUFCTL2 BS_SEC[7] BS_SEC[6] BS_SEC[5] BS_SEC[4] BS_SEC[3] BS_SEC[2] BS_SEC[1] BS_SEC[0] CBUFCTL3 BS_FRM[7] BS_FRM[6] BS_FRM[5] BS_FRM[4] BS_FRM[3] BS_FRM[2] BS_FRM[1] BS_FRM[0] CROMST0M   ST_SYILM ST_SYNOM ST_BLKSM ST_BLKLM ST_SECSM ST_SECLM ROMDECRST LOGICRST RAMRST       RSTSTAT RAMCLRST        SSI BYTEND BITEND BUFEND0[1] BUFEND0[0] BUFEND1[1] BUFEND1[0]   decoder INTHOLD ISEC ITARG ISY IERR IBUF IREADY   INHINT INHISEC INHITARG INHISY INHIERR INHIBUF INHIREADY PRE PRE INHREQDM INHIREADY STRMDIN0 STRMDIN2 STRMDOUT0 STRMDIN[31] STRMDIN[30] STRMDIN[29] STRMDIN[28] STRMDIN[27] STRMDIN[26] STRMDIN[25] STRMDIN[24] STRMDIN[23] STRMDIN[22] STRMDIN[21] STRMDIN[20] STRMDIN[19] STRMDIN[18] STRMDIN[17] STRMDIN[16] STRMDIN[15] STRMDIN[14] STRMDIN[13] STRMDIN[12] STRMDIN[11] STRMDIN[10] STRMDIN[9] STRMDIN[8] STRMDIN[7] STRMDIN[6] STRMDIN[5] STRMDIN[4] STRMDIN[3] STRMDIN[2] STRMDIN[1] STRMDIN[0] STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT [15] [14] [13] [12] [11] [10] [9] [8] STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT STRMDOUT [7] [6] [5] [4] [3] [2] [1] [0]                                                 A/D converter ADDRA ADDRB ADDRC ADDRD ADDRE ADDRF ADDRG ADDRH R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2869 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation A/D converter ADCSR NAND flash FLCMNCR memory Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 ADF ADIE ADST TRGS[3] TRGS[2] TRGS[1] TRGS[0] CKS[2] CKS[1] CKS[0] MDS[2] MDS[1] MDS[0] CH[2] CH[1] CH[0]           BUSYON   SNAND QTSEL      ACM[1] ACM[0] NANDWF      CE    controller FLCMDCR FLCMCDR 3 FLADR* FLADR1* 4 FLADR2 FLDTCNTR Page 2870 of 3092 ADRCNT2 SCTCNT[19] SCTCNT[18] SCTCNT[17] SCTCNT[16] ADRMD CDSRC DOSR   SELRW DOADR ADRCNT[1] ADRCNT[0] DOCMD2 DOCMD1 SCTCNT[15] SCTCNT[14] SCTCNT[13] SCTCNT[12] SCTCNT[11] SCTCNT[10] SCTCNT[9] SCTCNT[8] SCTCNT[7] SCTCNT[6] SCTCNT[5] SCTCNT[4] SCTCNT[3] SCTCNT[2] SCTCNT[1] SCTCNT[0]                 CMD2[7] CMD2[6] CMD2[5] CMD2[4] CMD2[3] CMD2[2] CMD2[1] CMD2[0] CMD1[7] CMD1[6] CMD1[5] CMD1[4] CMD1[3] CMD1[2] CMD1[1] CMD1[0] ADR4[7] ADR4[6] ADR4[5] ADR4[4] ADR4[3] ADR4[2] ADR4[1] ADR4[0] ADR3[7] ADR3[6] ADR3[5] ADR3[4] ADR3[3] ADR3[2] ADR3[1] ADR3[0] ADR2[7] ADR2[6] ADR2[5] ADR2[4] ADR2[3] ADR2[2] ADR2[1] ADR2[0] ADR1[7] ADR1[6] ADR1[5] ADR1[4] ADR1[3] ADR1[2] ADR1[1] ADR1[0]       ADR[25] ADR[24] ADR[23] ADR[22] ADR[21] ADR[20] ADR[19] ADR[18] ADR[17] ADR[16] ADR[15] ADR[14] ADR[13] ADR[12] ADR[11] ADR[10] ADR[9] ADR[8] ADR[7] ADR[6] ADR[5] ADR[4] ADR[3] ADR[2] ADR[1] ADR[0]                         ADR5[7] ADR5[6] ADR5[5] ADR5[4] ADR5[3] ADR5[2] ADR5[1] ADR5[0] ECFLW[7] ECFLW[6] ECFLW[5] ECFLW[4] ECFLW[3] ECFLW[2] ECFLW[1] ECFLW[0] DTFLW[7] DTFLW[6] DTFLW[5] DTFLW[4] DTFLW[3] DTFLW[2] DTFLW[1] DTFLW[0]     DTCNT[11] DTCNT[10] DTCNT[9] DTCNT[8] DTCNT[7] DTCNT[6] DTCNT[5] DTCNT[4] DTCNT[3] DTCNT[2] DTCNT[1] DTCNT[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 NAND flash FLDATAR DT4[7] DT4[6] DT4[5] DT4[4] DT4[3] DT4[2] DT4[1] DT4[0] DT3[7] DT3[6] DT3[5] DT3[4] DT3[3] DT3[2] DT3[1] DT3[0] DT2[7] DT2[6] DT2[5] DT2[4] DT2[3] DT2[2] DT2[1] DT2[0] DT1[7] DT1[6] DT1[5] DT1[4] DT1[3] DT1[2] DT1[1] DT1[0]           FIFOTRG[1] FIFOTRG[0] AC1CLR AC0CLR DREQ1EN DREQ0EN        STERB BTOERB TRREQF1 TRREQF0 STERINTE RBERINTE TEINTE TRINTE1 TRINTE0             RBTMOUT[19] RBTMOUT[18] RBTMOUT[17] RBTMOUT[16] RBTMOUT[15] RBTMOUT[14] RBTMOUT[13] RBTMOUT[12] RBTMOUT[11] RBTMOUT[10] RBTMOUT[9] RBTMOUT[8] RBTMOUT[7] RBTMOUT[6] RBTMOUT[5] RBTMOUT[4] RBTMOUT[3] RBTMOUT[2] RBTMOUT[1] RBTMOUT[0] STAT[7] STAT[6] STAT[5] STAT[4] STAT[3] STAT[2] STAT[1] STAT[0]     memory controller FLINTDMACR FLBSYTMR FLBSYCNT FLDTFIFO RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT [19] [18] [17] [16] RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT [15] [14] [13] [12] [11] [10] [9] [8] RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT RBTIMCNT [7] [6] [5] [4] [3] [2] [1] [0] DTFO[31] DTFO[30] DTFO[29] DTFO[28] DTFO[27] DTFO[26] DTFO[25] DTFO[24] DTFO[23] DTFO[22] DTFO[21] DTFO[20] DTFO[19] DTFO[18] DTFO[17] DTFO[16] DTFO[15] DTFO[14] DTFO[13] DTFO[12] DTFO[11] DTFO[10] DTFO[9] DTFO[8] DTFO[7] DTFO[6] DTFO[5] DTFO[4] DTFO[3] DTFO[2] DTFO[1] DTFO[0] ECFO[31] ECFO[30] ECFO[29] ECFO[28] ECFO[27] ECFO[26] ECFO[25] ECFO[24] ECFO[23] ECFO[22] ECFO[21] ECFO[20] ECFO[19] ECFO[18] ECFO[17] ECFO[16] ECFO[15] ECFO[14] ECFO[13] ECFO[12] ECFO[11] ECFO[10] ECFO[9] ECFO[8] ECFO[7] ECFO[6] ECFO[5] ECFO[4] ECFO[3] ECFO[2] ECFO[1] ECFO[0] FLTRCR      TRSTAT TREND TRSTRT FLHOLDCR                                HOLDEN FLECFIFO R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2871 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 USB 2.0 SYSCFG      SCKE   HSE DCFM DRPD DPRPU UCKFSEL UCKPSEL UPLLE USBE             BWAIT[3] BWAIT[2] BWAIT[1] BWAIT[0]               LNST[1] LNST[0] host/function Bit 24/16/8/0 module BUSWAIT SYSSTS DVSTCTR TESTMODE D0FBCFG D1FBCFG CFIFO D0FIFO Page 2872 of 3092        WKUP RWUPE USBRST RESUME UACT  RHST[2] RHST[1] RHST[0]             UTST[3] UTST[2] UTST[1] UTST[0]            TENDE                TENDE     FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [31] [30] [29] [28] [27] [26] [25] [24] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [23] [22] [21] [20] [19] [18] [17] [16] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [15] [14] [13] [12] [11] [10] [9] [8] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [7] [6] [5] [4] [3] [2] [1] [0] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [31] [30] [29] [28] [27] [26] [25] [24] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [23] [22] [21] [20] [19] [18] [17] [16] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [15] [14] [13] [12] [11] [10] [9] [8] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [7] [6] [5] [4] [3] [2] [1] [0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation USB 2.0 D1FIFO host/function module CFIFOSEL CFIFOCTR D0FIFOSEL D0FIFOCTR D1FIFOSEL D1FIFOCTR INTENB0 INTENB1 BRDYENB Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [31] [30] [29] [28] [27] [26] [25] [24] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [23] [22] [21] [20] [19] [18] [17] [16] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [15] [14] [13] [12] [11] [10] [9] [8] FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT FIFOPORT [7] [6] [5] [4] [3] [2] [1] [0] RCNT REW   MBW[1] MBW[0]  BIGEND   ISEL  CURPIPE[3] CURPIPE[2] CURPIPE[1] CURPIPE[0] BVAL BCLR FRDY  DTLN[11] DTLN[10] DTLN[9] DTLN[8] DTLN[7] DTLN[6] DTLN[5] DTLN[4] DTLN[3] DTLN[2] DTLN[1] DTLN[0] RCNT REW DCLRM DREQE MBW[1] MBW[0]  BIGEND     CURPIPE[3] CURPIPE[2] CURPIPE[1] CURPIPE[0] BVAL BCLR FRDY  DTLN[11] DTLN[10] DTLN[9] DTLN[8] DTLN[7] DTLN[6] DTLN[5] DTLN[4] DTLN[3] DTLN[2] DTLN[1] DTLN[0] RCNT REW DCLRM DREQE MBW[1] MBW[0]  BIGEND     CURPIPE[3] CURPIPE[2] CURPIPE[1] CURPIPE[0] BVAL BCLR FRDY  DTLN[11] DTLN[10] DTLN[9] DTLN[8] DTLN[7] DTLN[6] DTLN[5] DTLN[4] DTLN[3] DTLN[2] DTLN[1] DTLN[0] VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE          BCHGE  DTCHE ATTCHE     EOFERRE SIGNE SACKE           PIPE9BRDYE PIPE8BRDYE PIPE4BRDYE PIPE3BRDYE PIPE2BRDYE PIPE1BRDYE PIPE0BRDYE PIPE7BRDYE PIPE6BRDYE PIPE5BRDYE NRDYENB BEMPENB SOFCFG    PIPE7NRDYE PIPE6NRDYE PIPE5NRDYE  PIPE4NRDYE PIPE3NRDYE PIPE2NRDYE PIPE1NRDYE PIPE0NRDYE     PIPE7BEMPE PIPE6BEMPE PIPE5BEMPE PIPE4BEMPE PIPE3BEMPE PIPE2BEMPE PIPE1BEMPE PIPE0BEMPE        TRNENSEL  BRDYM       R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016     PIPE9NRDYE PIPE8NRDYE PIPE9BEMPE PIPE8BEMPE Page 2873 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 USB 2.0 INTSTS0 VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS DVSQ[2] DVSQ[1] DVSQ[0] VALID CTSQ[2] CTSQ[1] CTSQ[0]  BCHG  DTCH ATTCH     EOFERR SIGN SACK           PIPE9BRDY PIPE8BRDY PIPE7BRDY PIPE6BRDY PIPE5BRDY PIPE4BRDY PIPE3BRDY PIPE2BRDY PIPE1BRDY PIPE0BRDY host/function module INTSTS1 BRDYSTS NRDYSTS BEMPSTS FRMNUM UFRMNUM USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR Page 2874 of 3092       PIPE9NRDY PIPE8NRDY PIPE7NRDY PIPE6NRDY PIPE5NRDY PIPE4NRDY PIPE3NRDY PIPE2NRDY PIPE1NRDY PIPE0NRDY       PIPE9BEMP PIPE8BEMP PIPE7BEMP PIPE6BEMP PIPE5BEMP PIPE4BEMP PIPE3BEMP PIPE2BEMP PIPE1BEMP PIPE0BEMP OVRN CRCE    FRNM[10] FRNM[9] FRNM[8] FRNM[7] FRNM[6] FRNM[5] FRNM[4] FRNM[3] FRNM[2] FRNM[1] FRNM[0]              UFRNM[2] UFRNM[1] UFRNM[0]          USBADDR[6] USBADDR[5] USBADDR[4] USBADDR[3] USBADDR[2] USBADDR[1] USBADDR[0] BREQUEST[7] BREQUEST[6] BREQUEST[5] BREQUEST[4] BREQUEST[3] BREQUEST[2] BREQUEST[1] BREQUEST[0] BMREQUEST BMREQUEST BMREQUEST BMREQUEST BMREQUEST BMREQUEST BMREQUEST BMREQUEST TYPE[7] TYPE[6] TYPE[5] TYPE[4] TYPE[3] TYPE[2] TYPE[1] TYPE[0] WVALUE[15] WVALUE[14] WVALUE[13] WVALUE[12] WVALUE[11] WVALUE[10] WVALUE[9] WVALUE[8] WVALUE[7] WVALUE[6] WVALUE[5] WVALUE[4] WVALUE[3] WVALUE[2] WVALUE[1] WVALUE[0] WINDEX[15] WINDEX[14] WINDEX[13] WINDEX[12] WINDEX[11] WINDEX[10] WINDEX[9] WINDEX[8] WINDEX[7] WINDEX[6] WINDEX[5] WINDEX[4] WINDEX[3] WINDEX[2] WINDEX[1] WINDEX[0] WLENGTH[15] WLENGTH[14] WLENGTH[13] WLENGTH[12] WLENGTH[11] WLENGTH[10] WLENGTH[9] WLENGTH[8] WLENGTH[7] WLENGTH[6] WLENGTH[5] WLENGTH[4] WLENGTH[3] WLENGTH[2] WLENGTH[1] WLENGTH[0]        CNTMD SHTNAK   DIR     DEVSEL[3] DEVSEL[2] DEVSEL[1] DEVSEL[0]      MXPS[6] MXPS[5] MXPS[4] MXPS[3] MXPS[2] MXPS[1] MXPS[0] BSTS SUREQ CSCLR CSSTS SUREQCLR   SQCLR SQSET SQMON PBUSY PINGE  CCPL PID[1] PID[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 USB 2.0 PIPESEL             PIPESEL[3] PIPESEL[2] PIPESEL[1] PIPESEL[0] TYPE[1] TYPE[0]    BFRE DBLB CNTMD SHTNAK   DIR EPNUM[3] EPNUM[2] EPNUM[1] EPNUM[0]  BUFSIZE[4] BUFSIZE[3] BUFSIZE[2] BUFSIZE[1] BUFSIZE[0]    BUFNMB[6] BUFNMB[5] BUFNMB[4] BUFNMB[3] BUFNMB[2] BUFNMB[1] BUFNMB[0] host/function module PIPECFG PIPEBUF PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR PIPE1TRE PIPE1TRN DEVSEL[3] DEVSEL[2] DEVSEL[1] DEVSEL[0]  MXPS[10] MXPS[9] MXPS[8] MXPS[7] MXPS[6] MXPS[5] MXPS[4] MXPS[3] MXPS[2] MXPS[1] MXPS[0]    IFIS          IITV[2] IITV[1] IITV[0] BSTS INBUFM CSCLR CSSTS  ATREPM ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS INBUFM CSCLR CSSTS  ATREPM ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS INBUFM CSCLR CSSTS  ATREPM ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS INBUFM CSCLR CSSTS  ATREPM ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS INBUFM CSCLR CSSTS  ATREPM ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS  CSCLR CSSTS   ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS  CSCLR CSSTS   ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS  CSCLR CSSTS   ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0] BSTS  CSCLR CSSTS   ACLRM SQCLR SQSET SQMON PBUSY    PID[1] PID[0]       TRENB TRCLR         TRNCNT[15] TRNCNT[14] TRNCNT[13] TRNCNT[12] TRNCNT[11] TRNCNT[10] TRNCNT[9] TRNCNT[8] TRNCNT[7] TRNCNT[6] TRNCNT[5] TRNCNT[4] TRNCNT[3] TRNCNT[2] TRNCNT[1] TRNCNT[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2875 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 USB 2.0 PIPE2TRE       TRENB TRCLR         TRNCNT[15] TRNCNT[14] TRNCNT[13] TRNCNT[12] TRNCNT[11] TRNCNT[10] TRNCNT[9] TRNCNT[8] TRNCNT[7] TRNCNT[6] TRNCNT[5] TRNCNT[4] TRNCNT[3] TRNCNT[2] TRNCNT[1] TRNCNT[0]       TRENB TRCLR         host/function module PIPE2TRN PIPE3TRE PIPE3TRN PIPE4TRE PIPE4TRN PIPE5TRE PIPE5TRN DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD5 DEVADD6 DEVADD7 Page 2876 of 3092 TRNCNT[15] TRNCNT[14] TRNCNT[13] TRNCNT[12] TRNCNT[11] TRNCNT[10] TRNCNT[9] TRNCNT[8] TRNCNT[7] TRNCNT[6] TRNCNT[5] TRNCNT[4] TRNCNT[3] TRNCNT[2] TRNCNT[1] TRNCNT[0]       TRENB TRCLR         TRNCNT[15] TRNCNT[14] TRNCNT[13] TRNCNT[12] TRNCNT[11] TRNCNT[10] TRNCNT[9] TRNCNT[8] TRNCNT[7] TRNCNT[6] TRNCNT[5] TRNCNT[4] TRNCNT[3] TRNCNT[2] TRNCNT[1] TRNCNT[0]       TRENB TRCLR         TRNCNT[15] TRNCNT[14] TRNCNT[13] TRNCNT[12] TRNCNT[11] TRNCNT[10] TRNCNT[9] TRNCNT[8] TRNCNT[7] TRNCNT[6] TRNCNT[5] TRNCNT[4] TRNCNT[3] TRNCNT[2] TRNCNT[1] TRNCNT[0]  UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]          UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       HPPHUB[3] HPPHUB[2] HPPHUB[1] HPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0]        HPPHUB[3] HPPHUB[2] HPPHUB[1] HPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 USB 2.0 DEVADD8  UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]       UPPHUB[3] UPPHUB[2] UPPHUB[1] UPPHUB[0] HUBPORT[2] HUBPORT[1] HUBPORT[0] USBSPD[1] USBSPD[0]             AGCMODE                SRCLEFT[8] SRCLEFT[7] SRCLEFT[6] SRCLEFT[5] SRCLEFT[4] SRCLEFT[3] SRCLEFT[2] SRCLEFT[1] SRCLEFT[0] SRCTOP[5] SRCTOP[4] SRCTOP[3] SRCTOP[2] SRCTOP[1] SRCTOP[0] SRCHEIGHT SRCHEIGHT [9] [8] host/function Bit 24/16/8/0  module DEVADD9 DEVADDA Digital video ADCCR1 decoder TGCR1 TGCR2 TGCR3 SYNSCR1 SYNSCR2 SYNSCR3 SYNSCR4   SRCHEIGHT SRCHEIGHT SRCHEIGHT SRCHEIGHT SRCHEIGHT SRCHEIGHT SRCHEIGHT SRCHEIGHT [7] [6] [5] [4] [3] [2] [1] [0]      SRCWIDTH SRCWIDTH SRCWIDTH [10] [9] [8] SRCWIDTH SRCWIDTH SRCWIDTH SRCWIDTH SRCWIDTH SRCWIDTH SRCWIDTH SRCWIDTH [7] [6] [5] [4] [3] [2] [1] [0] LPFVSYNC[2] LPFVSYNC[1] LPFVSYNC[0] LPFHSYNC[2] LPFHSYNC[1] LPFHSYNC[0]   VELOCITY VELOCITY VELOCITY VELOCITY SLICER SLICER SLICER SLICER SHIFT_H[3] SHIFT_H[2] SHIFT_H[1] SHIFT_H[0] MODE_H[1] MODE_H[0] MODE_V[1] MODE_V[0]     SYNCMAX SYNCMAX SYNCMAX SYNCMAX DUTY_H[5] DUTY_H[4] DUTY_H[3] DUTY_H[2] SYNCMAX SYNCMAX SYNCMIN SYNCMIN SYNCMIN SYNCMIN SYNCMIN SYNCMIN DUTY_H[1] DUTY_H[0] DUTY_H[5] DUTY_H[4] DUTY_H[3] DUTY_H[2] DUTY_H[1] DUTY_H[0]   SSCLIP SSCLIP SSCLIP SSCLIP CSYNC CSYNC SEL[3] SEL[2] SEL[1] SEL[0] SLICE_H[9] SLICE_H[8] CSYNC CSYNC CSYNC CSYNC CSYNC CSYNC CSYNC CSYNC SLICE_H[7] SLICE_H[6] SLICE_H[5] SLICE_H[4] SLICE_H[3] SLICE_H[2] SLICE_H[1] SLICE_H[0]     SYNCMAX SYNCMAX SYNCMAX SYNCMAX DUTY_V[5] DUTY_V[4] DUTY_V[3] DUTY_V[2] SYNCMAX SYNCMAX SYNCMIN SYNCMIN SYNCMIN SYNCMIN SYNCMIN SYNCMIN DUTY_V[1] DUTY_V[0] DUTY_V[5] DUTY_V[4] DUTY_V[3] DUTY_V[2] DUTY_V[1] DUTY_V[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2877 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video SYNSCR5 VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC CSYNC CSYNC DELAY SLICE[4] SLICE[3] SLICE[2] SLICE[1] SLICE[0] SLICE_V[9] SLICE_V[8] CSYNC CSYNC CSYNC CSYNC CSYNC CSYNC CSYNC CSYNC SLICE_V[7] SLICE_V[6] SLICE_V[5] SLICE_V[4] SLICE_V[3] SLICE_V[2] SLICE_V[1] SLICE_V[0] HAFCGAIN HAFCGAIN HAFCGAIN HAFCGAIN  [3] [2] [1] [0] HAFCTYP[7] HAFCTYP[6] HAFCTYP[5] HAFCTYP[4] decoder HAFCCR1 HAFCCR2 HAFCCR3 DCPCR1 DCPCR2 DCPCR4 DCPCR5 Page 2878 of 3092 HAFCTYP [9] [8] HAFCTYP[3] HAFCTYP[2] HAFCTYP[1] HAFCTYP[0] NOX2HOSC DOX2HOSC HAFCMAX HAFCMAX [9] [8] HAFCSTART HAFCSTART HAFCSTART HAFCSTART [2] [1] [0] HAFCMAX HAFCMAX HAFCMAX HAFCMAX HAFCMAX HAFCMAX HAFCMAX HAFCMAX [7] [6] [5] [4] [3] [2] [1] [0] HAFCEND[3] HAFCEND[2] HAFCEND[1] HAFCEND[0] HAFCMODE HAFCMODE HAFCMIN[9] HAFCMIN[8] [1] [0] HAFCMIN[6] VCDFREERUN NOVCD50 HAFCMIN[5] HAFCMIN[4] HAFCMIN[3] HAFCMIN[2] HAFCMIN[1] HAFCMIN[0] NOVCD60 VCD VCD VCD VCD VCD DEFAULT[1] DEFAULT[0] WINDOW[5] WINDOW[4] WINDOW[3] VCD VCD VCD VCD VCD VCD VCD VCD WINDOW[2] WINDOW[1] WINDOW[0] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0]   DCPCHECK  BLANK BLANK LEVEL_Y[9] LEVEL_Y[8] DCPMODE_Y  BLANK BLANK BLANK BLANK BLANK BLANK BLANK BLANK LEVEL_Y[7] LEVEL_Y[6] LEVEL_Y[5] LEVEL_Y[4] LEVEL_Y[3] LEVEL_Y[2] LEVEL_Y[1] LEVEL_Y[0]   BLANK BLANK DCPMODE_C  BLANK DCPCR3 HAFCTYP [3] HAFCMIN[7] VCDWCR1 HAFCFREE RUN BLANK BLANK BLANK LEVEL_CB[5] LEVEL_CB[4] LEVEL_CB[3] LEVEL_CB[2] BLANK BLANK BLANK BLANK LEVEL_CB[1] LEVEL_CB[0] LEVEL_CR[5] LEVEL_CR[4] LEVEL_CR[3] LEVEL_CR[2] LEVEL_CR[1] LEVEL_CR[0]  DCP DCP DCP     RESPONSE[2] RESPONSE[1] RESPONSE[0]             DCPSTART DCPSTART DCPSTART DCPSTART DCPSTART DCPSTART [5] [4] [3] [2] [1] [0]       BLANK BLANK DCPEND[5] DCPEND[4] DCPEND[3] DCPEND[2] DCPEND[1] DCPEND[0]           R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video DCPCR6  DCPWIDTH DCPWIDTH DCPWIDTH DCPWIDTH DCPWIDTH DCPWIDTH DCPWIDTH [6] [5] [4] [3] [2] [1] [0]         DCPPOS_Y decoder DCPCR7 DCPCR8 NSDCR DCPPOS_Y DCPPOS_Y DCPPOS_Y DCPPOS_Y DCPPOS_Y DCPPOS_Y DCPPOS_Y [7] [6] [5] [4] [3] [2] [1] [0]         DCPPOS_C DCPPOS_C DCPPOS_C DCPPOS_C DCPPOS_C DCPPOS_C DCPPOS_C DCPPOS_C [7] [6] [5] [4] [3] [2] [1] [0]           ACFINPUT[1] ACFINPUT[0]    ACFLAG TIME[4] BTLCR BTGPCR ACCCR1  ACFLAG ACFLAG ACFLAG ACFLAG TIME[3] TIME[2] TIME[1] TIME[0] LOCK LOCK LOOP LOOP LOCK RANGE[1] RANGE[0] GAIN[1] GAIN[0] LIMIT[1] DEFAULT DEFAULT NONTSC358 NONTSC443 SYS[1] SYS[0] BGPCHECK  ACF ACF FILTER[1] FILTER[0] LOCK BCO  LIMIT[0] FREERUN NOPALM NOPALN NOPAL443 NOSECAM BGPWIDTH BGPWIDTH BGPWIDTH BGPWIDTH BGPWIDTH BGPWIDTH BGPWIDTH [6] [5] [4] [3] [2] [1] [0] BGPSTART BGPSTART BGPSTART BGPSTART BGPSTART BGPSTART BGPSTART BGPSTART [7] [6] [5] [4] [3] [2] [1] [0] KILLER KILLER KILLER KILLER ACCMODE ACC ACC ACC OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0] MAXGAIN[1] MAXGAIN[0] LEVEL[8] ACCLEVEL[7] ACCLEVEL[6] ACCLEVEL[5] ACCLEVEL[4] ACCLEVEL[3] ACCLEVEL[2] ACCLEVEL[1 ACCLEVEL[0] ] ACCCR2 ACCCR3 TINTCR      CHROMA CHROMA SUBGAIN[1] SUBGAIN[0] CHROMA MAINGAIN[8] CHROMA CHROMA CHROMA CHROMA CHROMA CHROMA CHROMA CHROMA MAINGAIN[7] MAINGAIN[6] MAINGAIN[5] MAINGAIN[4] MAINGAIN[3] MAINGAIN[2] MAINGAIN[1] MAINGAIN[0] ACC ACC ACC ACC ACC ACC ACC ACC RESPONSE RESPONSE PRECIS[5] PRECIS[4] PRECIS[3] PRECIS[2] PRECIS[1] PRECIS[0] [1] [0] KILLER KILLER KILLER KILLER KILLER KILLER KILLER  MODE LEVEL[5] LEVEL[4] LEVEL[3] LEVEL[2] LEVEL[1] LEVEL[0] TINTSUB[5] TINTSUB[4] TINTSUB[3] TINTSUB[2] TINTSUB[1] TINTSUB[0] TINTMAIN[9] TINTMAIN[8] TINTMAIN[7] TINTMAIN[6] TINTMAIN[5] TINTMAIN[4] TINTMAIN[3] TINTMAIN[2] TINTMAIN[1] TINTMAIN[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2879 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Digital video YCDCR        decoder Bit 24/16/8/0 LUMA DELAY[4] AGCCR1 AGCCR2 PKLIMITCR RGORCR1 LUMADELAY LUMADELAY LUMADELAY LUMADELAY [3] [2] [1] [0]   DOREDUCE NOREDUCE RGORCR4 RGORCR5 Page 2880 of 3092 DEMOD MODE[1] MODE[0] AGC AGC AGC AGC RESPONSE[2] RESPONSE[1] RESPONSE[0] LEVEL[8] AGC AGC AGC AGC AGC AGC AGC LEVEL[7] LEVEL[6] LEVEL[5] LEVEL[4] LEVEL[3] LEVEL[2] LEVEL[1] LEVEL[0]   AGC AGC AGC AGC AGC AGC PRECIS[5] PRECIS[4] PRECIS[3] PRECIS[2] PRECIS[1] PRECIS[0]         PEAK PEAK PEAK PEAK PEAK PEAK PEAK PEAK LEVEL[1] LEVEL[0] ATTACK[1] ATTACK[0] RELEASE[1] RELEASE[0] RATIO[1] RATIO[0] MAXPEAK MAXPEAK MAXPEAK MAXPEAK MAXPEAK MAXPEAK MAXPEAK MAXPEAK SAMPLES[7] SAMPLES[6] SAMPLES[5] SAMPLES[4] SAMPLES[3] SAMPLES[2] SAMPLES[1] SAMPLES[0]       RADJ_O_ RADJ_O_ LEVEL0[9] LEVEL0[8] LEVEL0[7] RGORCR3 CHROMALPF DEMOD AGC RADJ_O_ RGORCR2   RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ LEVEL0[6] LEVEL0[5] LEVEL0[4] LEVEL0[3] LEVEL0[2] LEVEL0[1] LEVEL0[0]      RADJ_U_ RADJ_U_ LEVEL0[9] LEVEL0[8] RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ LEVEL0[7] LEVEL0[6] LEVEL0[5] LEVEL0[4] LEVEL0[3] LEVEL0[2] LEVEL0[1] LEVEL0[0]       RADJ_O_ RADJ_O_ LEVEL1[9] LEVEL1[8] RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ LEVEL1[7] LEVEL1[6] LEVEL1[5] LEVEL1[4] LEVEL1[3] LEVEL1[2] LEVEL1[1] LEVEL1[0]       RADJ_U_ RADJ_U_ LEVEL1[9] LEVEL1[8] RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ LEVEL1[7] LEVEL1[6] LEVEL1[5] LEVEL1[4] LEVEL1[3] LEVEL1[2] LEVEL1[1] LEVEL1[0]       RADJ_O_ RADJ_O_ LEVEL2[9] LEVEL2[8] RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ RADJ_O_ LEVEL2[7] LEVEL2[6] LEVEL2[5] LEVEL2[4] LEVEL2[3] LEVEL2[2] LEVEL2[1] LEVEL2[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video RGORCR6     RADJ_U_ RADJ_U_ LEVEL2[9] LEVEL2[8]   decoder RGORCR7 AFCPFCR RUPDCR VSYNCSR HSYNCSR DCPSR1 DCPSR2 NSDSR CROMASR1 CROMASR2 RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ RADJ_U_ LEVEL2[7] LEVEL2[6] LEVEL2[5] LEVEL2[4] LEVEL2[3] LEVEL2[2] LEVEL2[1] LEVEL2[0]   TEST_MONI TEST_MON TEST_MONI RADJ_MIX_ RADJ_MIX_ RADJ_MIX_ [2] I[1] [0] K_FIX[2] K_FIX[1] K_FIX[0]      UCMP_SW DCMP_SW HWIDE_SW            PHDET_FIX  PHDET_ PHDET_ PHDET_ DIV[2] DIV[1] DIV[0] NEWSETTING                FHCOUNT_L FHLOCK ISNOISY FHMODE NOSIGNAL FVLOCK FVMODE INTERLACED FVCOUNT[7] FVCOUNT[6] FVCOUNT[5] FVCOUNT[4] FVCOUNT[3] FVCOUNT[2] FVCOUNT[1] FVCOUNT[0] FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ H[16] H[15] H[14] H[13] H[12] H[11] H[10] H[9] FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ FHCOUNT_ H[8] H[7] H[6] H[5] H[4] H[3] H[2] H[1] CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP LEVEL_CB[5] LEVEL_CB[4] LEVEL_CB[3] LEVEL_CB[2] LEVEL_CB[1] LEVEL_CB[0] LEVEL_Y[9] LEVEL_Y[8] CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP LEVEL_Y[7] LEVEL_Y[6] LEVEL_Y[5] LEVEL_Y[4] LEVEL_Y[3] LEVEL_Y[2] LEVEL_Y[1] LEVEL_Y[0] CLAMP CLAMP CLAMP     CLAMP CLAMP CLAMP LEVEL_CR[5] LEVEL_CR[4] LEVEL_CR[3] LEVEL_CR[2] LEVEL_CR[1] LEVEL_CR[0]       ACFSTRENG ACFSTRENG ACFSTRENGT ACFSTRENGT ACFSTRENG ACFSTRENG ACFSTRENG ACFSTRENG TH[15] H[13] TH[10] TH[14] H[12] TH[11] TH[9] TH[8] ACFSTRENG ACFSTRENG ACFSTRENGT ACFSTRENGT ACFSTRENG ACFSTRENG ACFSTRENG ACFSTRENG TH[7] TH[6] H[5] H[4] TH[3] TH[2] TH[1] TH[0] FSCMODE FSCLOCK NOBURST ACCSUB ACCSUB ACCMAIN GAIN[1] GAIN[0] GAIN[8] COLOR COLOR SYS[1] SYS[0] ACCMAIN ACCMAIN ACCMAIN ACCMAIN ACCMAIN ACCMAIN ACCMAIN ACCMAIN GAIN[7] GAIN[6] GAIN[5] GAIN[4] GAIN[3] GAIN[2] GAIN[1] GAIN[0]    ISSECAM ISPAL ISNTSC   LOCK LOCK LOCK LOCK LOCK LOCK LOCK LOCK LEVEL[7] LEVEL[6] LEVEL[5] LEVEL[4] LEVEL[3] LEVEL[2] LEVEL[1] LEVEL[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2881 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Digital video SYNCSSR  ISREDUCED     SYNCDEPTH SYNCDEPTH decoder [9] AGCCSR1 AGCCSR2 Bit 24/16/8/0 [8] SYNCDEPTH SYNCDEPTH SYNCDEPTH SYNCDEPTH SYNCDEPTH SYNCDEPTH SYNCDEPTH SYNCDEPTH [7] [6] [5] [4] [3] [2] [1] [0] HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH SAMPLES[7] SAMPLES[6] SAMPLES[5] SAMPLES[4] SAMPLES[3] SAMPLES[2] SAMPLES[1] SAMPLES[0] PEAK PEAK PEAK PEAK PEAK PEAK PEAK PEAK SAMPLES[7] SAMPLES[6] SAMPLES[5] SAMPLES[4] SAMPLES[3] SAMPLES[2] SAMPLES[1] SAMPLES[0]        AGC CONVERGE YCSCR3 YCSCR4 YCSCR5 YCSCR6 YCSCR7 YCSCR8 YCSCR9 YCSCR11 AGCGAIN[7] AGCGAIN[6] AGCGAIN[5] AGCGAIN[4] AGCGAIN[3] AGCGAIN[2] AGCGAIN[1] AGCGAIN[0] K15[3] K15[2] K15[1] K15[0] K13[5] K13[4] K13[3] K13[2] K13[1] K13[0] K11[5] K11[4] K11[3] K11[2] K11[1] K11[0] K16[3] K16[2] K16[1] K16[0] K14[5] K14[4] K14[3] K14[2] K14[1] K14[0] K12[5] K12[4] K12[3] K12[2] K12[1] K12[0] K22A[7] K22A[6] K22A[5] K22A[4] K22A[3] K22A[2] K22A[1] K22A[0]   K21A[5] K21A[4] K21A[3] K21A[2] K21A[1] K21A[0] K22B[7] K22B[6] K22B[5] K22B[4] K22B[3] K22B[2] K22B[1] K22B[0]   K21B[5] K21B[4] K21B[3] K21B[2] K21B[1] K21B[0] K23B[3] K23B[2] K23B[1] K23B[0] K23A[3] K23A[2] K23A[1] K23A[0]    K24[4] K24[3] K24[2] K24[1] K24[0]    HBPF_ HVBPF_ HBPF1_ HVBPF1_ HFIL_ NARROW NARROW 9TAP_ON 9TAP_ON TAP_SEL         DET2_ON    HSEL_MIX_ HSEL_MIX_ HSEL_MIX_ HSEL_MIX_ Y[3] Y[2] Y[1] Y[0] VSEL_MIX_ VSEL_MIX_ VSEL_MIX_ VSEL_MIX_ HVSEL_MIX_ HVSEL_MIX_ HVSEL_MIX_ HVSEL_MIX Y[3] Y[2] Y[1] Y[0] Y[3] Y[2] Y[1]        _Y[0] V_Y_ LEVEL[8] Page 2882 of 3092 V_Y_ V_Y_ V_Y_ V_Y_ V_Y_ V_Y_ V_Y_ V_Y_ LEVEL[7] LEVEL[6] LEVEL[5] LEVEL[4] LEVEL[3] LEVEL[2] LEVEL[1] LEVEL[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Digital video YCSCR12 decoder DCPCR9 YCTWA_F0 YCTWA_F1 YCTWA_F2 YCTWA_F3 YCTWA_F4 YCTWA_F5 YCTWA_F6 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 DET2_MIX_ DET2_MIX_ DET2_MIX_ DET2_MIX_ DET2_MIX_ DET2_MIX_ DET2_MIX_ DET2_MIX_ C[3] C[2] C[1] C[0] Y[3] Y[2] Y[1] Y[0]        FIL2_MODE_2 FIL2_MODE_  FIL2_ D[1] NARROW_2D 2D[0] CLP_HOLD_O CLP_HOLD_O CLP_HOLD_ N_Y N_CB ON_CR              FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F0[12] WA_F0[11] WA_F0[10] WA_F0[9] WA_F0[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F0[7] WA_F0[6] WA_F0[5] WA_F0[4] WA_F0[3] WA_F0[2] WA_F0[1] WA_F0[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F1[12] WA_F1[11] WA_F1[10] WA_F1[9] WA_F1[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F1[7] WA_F1[6] WA_F1[5] WA_F1[4] WA_F1[3] WA_F1[2] WA_F1[1] WA_F1[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F2[12] WA_F2[11] WA_F2[10] WA_F2[9] WA_F2[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F2[7] WA_F2[6] WA_F2[5] WA_F2[4] WA_F2[3] WA_F2[2] WA_F2[1] WA_F2[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F3[12] WA_F3[11] WA_F3[10] WA_F3[9] WA_F3[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F3[7] WA_F3[6] WA_F3[5] WA_F3[4] WA_F3[3] WA_F3[2] WA_F3[1] WA_F3[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F4[12] WA_F4[11] WA_F4[10] WA_F4[9] WA_F4[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F4[7] WA_F4[6] WA_F4[5] WA_F4[4] WA_F4[3] WA_F4[2] WA_F4[1] WA_F4[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F5[12] WA_F5[11] WA_F5[10] WA_F5[9] WA_F5[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F5[7] WA_F5[6] WA_F5[5] WA_F5[4] WA_F5[3] WA_F5[2] WA_F5[1] WA_F5[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F6[12] WA_F6[11] WA_F6[10] WA_F6[9] WA_F6[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F6[7] WA_F6[6] WA_F6[5] WA_F6[4] WA_F6[3] WA_F6[2] WA_F6[1] WA_F6[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2883 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video YCTWA_F7  FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F7[12] WA_F7[11] WA_F7[10] WA_F7[9] WA_F7[8]   decoder YCTWA_F8 YCTWB_F0 YCTWB_F1 YCTWB_F2 YCTWB_F3 YCTWB_F4 YCTWB_F5 YCTWB_F6 Page 2884 of 3092 FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F7[7] WA_F7[6] WA_F7[5] WA_F7[4] WA_F7[3] WA_F7[2] WA_F7[1] WA_F7[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F8[12] WA_F8[11] WA_F8[10] WA_F8[9] WA_F8[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WA_F8[7] WA_F8[6] WA_F8[5] WA_F8[4] WA_F8[3] WA_F8[2] WA_F8[1] WA_F8[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F0[12] WB_F0[11] WB_F0[10] WB_F0[9] WB_F0[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F0[7] WB_F0[6] WB_F0[5] WB_F0[4] WB_F0[3] WB_F0[2] WB_F0[1] WB_F0[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F1[12] WB_F1[11] WB_F1[10] WB_F1[9] WB_F1[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F1[1] WB_F1[0] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F1[7] WB_F1[6] WB_F1[5] WB_F1[4] WB_F1[3]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F2[12] WB_F2[11] WB_F2[10] WB_F2[9] WB_F2[8] WB_F1[2] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F2[7] WB_F2[6] WB_F2[5] WB_F2[4] WB_F2[3] WB_F2[2] WB_F2[1] WB_F2[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F3[12] WB_F3[11] WB_F3[10] WB_F3[9] WB_F3[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F3[7] WB_F3[6] WB_F3[5] WB_F3[4] WB_F3[3] WB_F3[2] WB_F3[1] WB_F3[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F4[12] WB_F4[11] WB_F4[10] WB_F4[9] WB_F4[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_W WB_F4[7] WB_F4[6] WB_F4[5] WB_F4[4] WB_F4[3] WB_F4[2] WB_F4[1] B_F4[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F5[12] WB_F5[11] WB_F5[10] WB_F5[9] WB_F5[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F5[7] WB_F5[6] WB_F5[5] WB_F5[4] WB_F5[3] WB_F5[2] WB_F5[1] WB_F5[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F6[12] WB_F6[11] WB_F6[10] WB_F6[9] WB_F6[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F6[7] WB_F6[6] WB_F6[5] WB_F6[4] WB_F6[3] WB_F6[2] WB_F6[1] WB_F6[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video YCTWB_F7  FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F7[12] WB_F7[11] WB_F7[10] WB_F7[9] WB_F7[8]   decoder YCTWB_F8 YCTNA_F0 YCTNA_F1 YCTNA_F2 YCTNA_F3 YCTNA_F4 YCTNA_F5 YCTNA_F6 FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F7[7] WB_F7[6] WB_F7[5] WB_F7[4] WB_F7[3] WB_F7[2] WB_F7[1] WB_F7[0]    FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F8[12] WB_F8[11] WB_F8[10] WB_F8[9] WB_F8[8] FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ FIL2_2D_ WB_F8[7] WB_F8[6] WB_F8[5] WB_F8[4] WB_F8[3] WB_F8[2] WB_F8[1] B_F8[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA F0[12] F0[11] F0[10] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F0[7] F0[6] F0[5] F0[4] F0[3] F0[2] F0[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F1[12] F1[11] F1[10] F1[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F1[7] F1[6] F1[5] F1[4] F1[3] F1[2] F1[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F2[12] F2[11] F2[10] F2[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F2[7] F2[6] F2[5] F2[4] F2[3] F2[2] F2[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F3[12] F3[11] F3[10] F3[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F3[7] F3[6] F3[5] F3[4] F3[3] F3[2] F3[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA F4[12] F4[11] F4[10] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F4[7] F4[6] F4[5] F4[4] F4[3] F4[2] F4[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F5[12] F5[11] F5[10] F5[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F5[7] F5[6] F5[5] F5[4] F5[3] F5[2] F5[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F6[12] F6[11] F6[10] F6[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F6[7] F6[4] F6[3] F6[2] F6[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 F6[6] F6[5] _F0[9] _F0[1] _F1[9] _F1[1] _F2[9] _F2[1] _F3[9] _F3[1] _F4[9] _F4[1] _F5[9] _F5[1] _F6[9] _F6[1] FIL2_2D_NA_ F0[8] FIL2_2D_NA_ F4[8] Page 2885 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video YCTNA_F7  FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F7[12] F7[11] F7[10] F7[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F7[7] F7[6] F7[5] F7[4] F7[3] F7[2] F7[0]    FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F8[12] F8[11] F8[10] F8[8] FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA_ FIL2_2D_NA FIL2_2D_NA_ F8[7] F8[6] F8[5] F8[4] F8[3] F8[2] F8[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB F0[12] F0[11] F0[10] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F0[7] F0[6] F0[5] F0[4] F0[3] F0[2] F0[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F1[12] F1[11] F1[10] F1[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F1[7] F1[6] F1[5] F1[4] F1[3] F1[2] F1[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F2[12] F2[11] F2[10] F2[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F2[7] F2[6] F2[5] F2[4] F2[3] F2[2] F2[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F3[12] F3[11] F3[10] F3[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F3[7] F3[6] F3[5] F3[4] F3[3] F3[2] F3[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB F4[12] F4[11] F4[10] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F4[7] F4[6] F4[5] F4[4] F4[3] F4[2] F4[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F5[12] F5[11] F5[10] F5[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F5[7] F5[6] F5[5] F5[4] F5[3] F5[2] F5[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F6[12] F6[11] F6[10] F6[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F6[7] F6[4] F6[3] F6[2] F6[0]   decoder YCTNA_F8 YCTNB_F0 YCTNB_F1 YCTNB_F2 YCTNB_F3 YCTNB_F4 YCTNB_F5 YCTNB_F6 Page 2886 of 3092 F6[6] F6[5] _F7[9] _F7[1] _F8[9] _F8[1] _F0[9] _F0[1] _F1[9] _F1[1] _F2[9] _F2[1] _F3[9] _F3[1] _F4[9] _F4[1] _F5[9] _F5[1] _F6[9] _F6[1] FIL2_2D_NB_ F0[8] FIL2_2D_NB_ F4[8] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Digital video YCTNB_F7  FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F7[12] F7[11] F7[10] F7[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F7[7] F7[6] F7[5] F7[4] F7[3] F7[2] F7[0]    FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F8[12] F8[11] F8[10] F8[8] FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB_ FIL2_2D_NB FIL2_2D_NB_ F8[7] F8[6] F8[5] F8[4] F8[3] F8[2] _F8[1] F8[0]       Y_GAIN2[9] Y_GAIN2[8] Y_GAIN2[7] Y_GAIN2[6] Y_GAIN2[5] Y_GAIN2[4] Y_GAIN2[3] Y_GAIN2[2] Y_GAIN2[1] Y_GAIN2[0]   decoder YCTNB_F8 YGAINCR CBGAINCR CRGAINCR PGA_UPDATE PGACR _F7[9] _F7[1] _F8[9]       CB_GAIN2[9] CB_GAIN2[8] CB_GAIN2[7] CB_GAIN2[6] CB_GAIN2[5] CB_GAIN2[4] CB_GAIN2[3] CB_GAIN2[2] CB_GAIN2[1] CB_GAIN2[0]       CR_GAIN2[9] CR_GAIN2[8] CR_GAIN2[7] CR_GAIN2[6] CR_GAIN2[5] CR_GAIN2[4] CR_GAIN2[3] CR_GAIN2[2] CR_GAIN2[1] CR_GAIN2[0]                PGA_VEN   PGA_GAIN_ PGA_GAIN[4] PGA_GAIN[3] PGA_GAIN[2] PGA_GAIN[1] PGA_GAIN[0] SEL ADCCR2 Video display INP_UPDATE controller 4                        ADC_VINSEL                            INP_EXT_    UPDATE INP_SEL_CNT INP_IMG_ UPDATE            INP_SEL          INP_ INP_ INP_ FORMAT[2] FORMAT[1] FORMAT[0]   INP_VS_ EDGE R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 INP_PXD_ EDGE    INP_HS_ EDGE Page 2887 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Video display INP_EXT_  INP_   controller 4 SYNC_CNT    ENDIAN_ON Bit 24/16/8/0 INP_SWAP_O N    INP_VS_INV           INP_HS_INV INP_H_ EDGE_SEL  INP_VSYNC_ PH_ADJ INP_DLY_   INP_F525_625  UPDATE IMGCNT_NR_ CNT0 INP_H_ POS[1] POS[0]      INP_FH50[9] INP_FH50[8] INP_FH50[7] INP_FH50[6] INP_FH50[5] INP_FH50[4] INP_FH50[3] INP_FH50[2] INP_FH50[1] INP_FH50[0]       INP_FH25[9] INP_FH25[8] INP_FH25[7] INP_FH25[6] INP_FH25[5] INP_FH25[4] INP_FH25[3] INP_FH25[2] INP_FH25[1] INP_FH25[0]      INP_VS_ INP_VS_ INP_VS_ DLY_L[2] DLY_L[1] DLY_L[0] INP_FLD_ INP_FLD_ INP_FLD_ INP_FLD_ INP_FLD_ INP_FLD_ INP_FLD_ INP_FLD_ DLY[7] DLY[6] DLY[5] DLY[4] DLY[3] DLY[2] DLY[1] DLY[0] INP_VS_ INP_VS_ INP_VS_ INP_VS_ INP_VS_ INP_VS_ INP_VS_ INP_VS_ DLY[7] DLY[6] DLY[5] DLY[4] DLY[3] DLY[2] DLY[1] DLY[0] INP_HS_ INP_HS_ INP_HS_ INP_HS_ INP_HS_ INP_HS_ INP_HS_ INP_HS_ DLY[7] DLY[6] DLY[5] DLY[4] DLY[3] DLY[2] DLY[1] DLY[0]                                IMGCNT_VEN            NR1D_MD    NR1D_ON   Page 2888 of 3092 INP_H_  ADJ IMGCNT_  NR1D_Y_ NR1D_Y_ NR1D_Y_ NR1D_Y_ NR1D_Y_ NR1D_Y_ NR1D_Y_ TH[6] TH[5] TH[4] TH[3] TH[2] TH[1] TH[0]  NR1D_Y_ NR1D_Y_   NR1D_Y_ NR1D_Y_ TAP[1] TAP[0] GAIN[1] GAIN[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display IMGCNT_NR_  controller 4 CNT1    IMGCNT_ MTX_MODE IMGCNT_ MTX_YG_ADJ0 IMGCNT_ NR1D_CB_ NR1D_CB_ NR1D_CB NR1D_CB_ NR1D_CB_ NR1D_CB_ NR1D_CB_ TH[6] TH[5] _TH[4] TH[3] TH[2] TH[1] TH[0]  NR1D_CB_ NR1D_CB_   NR1D_CB_ NR1D_CB_ TAP[1] TAP[0] GAIN[1] GAIN[0] NR1D_CR_ NR1D_CR_ NR1D_CR_ NR1D_CR_ NR1D_CR_ NR1D_CR_ NR1D_CR_ TH[6] TH[5] TH[4] TH[3] TH[2] TH[1] TH[0]  NR1D_CR_ NR1D_CR_   NR1D_CR_ NR1D_CR_ TAP[1] TAP[0] GAIN[1] GAIN[0]                               IMGCNT_ IMGCNT_ MTX_MD[1] MTX_MD[0]         IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_YG[7] MTX_YG[6] MTX_YG[5] MTX_YG[4] MTX_YG[3] MTX_YG[2] MTX_YG[1] MTX_YG[0]      _CBB_ADJ0 IMGCNT_ IMGCNT_ MTX_GG[9] MTX_GG[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_GG[7] MTX_GG[6] MTX_GG[5] MTX_GG[4] MTX_GG[3] MTX_GG[2] MTX_GG[1] MTX_GG[0]      IMGCNT_ MTX_YG_ADJ1 IMGCNT_MTX IMGCNT_ MTX_GG[10] IMGCNT_ IMGCNT_ MTX_GB[10] MTX_GB[9] MTX_GB[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_GB[7] MTX_GB[6] MTX_GB[5] MTX_GB[4] MTX_GB[3] MTX_GB[2] MTX_GB[1] MTX_GB[0]      IMGCNT_ IMGCNT_ IMGCNT_ MTX_GR[10] MTX_GR[9] MTX_GR[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_GR[7] MTX_GR[6] MTX_GR[5] MTX_GR[4] MTX_GR[3] MTX_GR[2] MTX_GR[1] MTX_GR[0]         IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_B[7] MTX_B[6] MTX_B[5] MTX_B[4] MTX_B[3] MTX_B[2] MTX_B[1] MTX_B[0]      IMGCNT_ IMGCNT_ IMGCNT_ MTX_BG[10] MTX_BG[9] MTX_BG[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_BG[7] MTX_BG[6] MTX_BG[5] MTX_BG[4] MTX_BG[3] MTX_BG[2] MTX_BG[1] MTX_BG[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2889 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display IMGCNT_MTX    controller 4 _CBB_ADJ1 IMGCNT_ MTX_CRR_ ADJ0 IMGCNT_   SCL0_ UPDATE Bit 24/16/8/0 IMGCNT_ IMGCNT_ IMGCNT_ MTX_BB[10] MTX_BB[9] MTX_BB[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_BB[7] MTX_BB[6] MTX_BB[5] MTX_BB[4] MTX_BB[3] MTX_BB[2] MTX_BB[1] MTX_BB[0]      IMGCNT_ IMGCNT_ IMGCNT_ MTX_BR[10] MTX_BR[9] MTX_BR[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_BR[7] MTX_BR[6] MTX_BR[5] MTX_BR[4] MTX_BR[3] MTX_BR[2] MTX_BR[1] MTX_BR[0]         IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_R[7] MTX_R[6] MTX_R[5] MTX_R[4] MTX_R[3] MTX_R[2] MTX_R[1] MTX_R[0]      IMGCNT_ IMGCNT_ IMGCNT_ MTX_RG[10] MTX_RG[9] MTX_RG[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_RG[7] MTX_RG[6] MTX_RG[5] MTX_RG[4] MTX_RG[3] MTX_RG[2] MTX_RG[1] MTX_RG[0]      MTX_CRR_ ADJ1 Bit 26/18/10/2 Bit 25/17/9/1 IMGCNT_ IMGCNT_ IMGCNT_ MTX_RB[10] MTX_RB[9] MTX_RB[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_RB[7] MTX_RB[6] MTX_RB[5] MTX_RB[4] MTX_RB[3] MTX_RB[2] MTX_RB[1] MTX_RB[0]      IMGCNT_ IMGCNT_ IMGCNT_ MTX_RR[10] MTX_RR[9] MTX_RR[8] IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ IMGCNT_ MTX_RR[7] MTX_RR[6] MTX_RR[5] MTX_RR[4] MTX_RR[3] MTX_RR[2] MTX_RR[1] MTX_RR[0]                   SCL0_VEN_D SCL0_VEN_C    SCL0_UPDAT E SCL0_FRC1    SCL0_VEN_B    RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK [15] [14] [13] [12] [11] [10] [9] RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK RES_VMASK [7] [6] [5] [4] [3] [2] [1] [0]                SCL0_VEN_A [8] RES_ VMASK_ON Page 2890 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display SCL0_FRC2 RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ VLACK[15] VLACK[14] VLACK[13] VLACK[12] VLACK[11] VLACK[10] VLACK[9] VLACK[8] RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ VLACK[7] VLACK[6] VLACK[5] VLACK[4] VLACK[3] VLACK[2] VLACK[1] VLACK[0]                controller 4 RES_VLACK_ ON SCL0_FRC3                                RES_VS_ SEL SCL0_FRC4 SCL0_FRC5      RES_FV[10] RES_FV[9] RES_FV[8] RES_FV[7] RES_FV[6] RES_FV[5] RES_FV[4] RES_FV[3] RES_FV[2] RES_FV[1] RES_FV[0]      RES_FH[10] RES_FH[9] RES_FH[8] RES_FH[7] RES_FH[6] RES_FH[5] RES_FH[4] RES_FH[3] RES_FH[2] RES_FH[1] RES_FH[0]                        RES_FLD_ DLY_SEL SCL0_FRC6 RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ VSDLY[7] VSDLY[6] VSDLY[5] VSDLY[4] VSDLY[3] VSDLY[2] VSDLY[1] VSDLY[0]      RES_ RES_ RES_ F_VS[10] F_VS[9] F_VS[8] RES_F_VS[7] RES_F_VS[6] RES_F_VS[5] RES_F_VS[4] RES_F_VS[3]      RES_F_VS[2] RES_F_VS[1] RES_F_VS[0] RES_ RES_ RES_ F_VW[10] F_VW[9] F_VW[8] RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ F_VW[7] F_VW[6] F_VW[5] F_VW[4] F_VW[3] F_VW[2] F_VW[1] F_VW[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2891 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display SCL0_FRC7      controller 4 SCL0_FRC8 (R version only) Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 RES_ RES_ RES_ F_HS[10] F_HS[9] F_HS[8] RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ F_HS[7] F_HS[6] F_HS[5] F_HS[4] F_HS[3] F_HS[2] F_HS[1] F_HS[0]      RES_ RES_ RES_ F_HW[10] F_HW[9] F_HW[8] RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ F_HW[7] F_HW[6] F_HW[5] F_HW[4] F_HW[3] F_HW[2] F_HW[1] F_HW[0]                              RES_   US_FLD SCL0_FRC9                            RES_    QVLOCK SCL0_DS1                            RES_DS_V_    ON SCL0_DS2 SCL0_DS3 Page 2892 of 3092 RES_ QVLACK RES_DS_H_O N      RES_VS[10] RES_VS[9] RES_VS[8] RES_VS[7] RES_VS[6] RES_VS[5] RES_VS[4] RES_VS[3] RES_VS[2] RES_VS[1] RES_VS[0]      RES_VW[10] RES_VW[9] RES_VW[8] RES_VW[7] RES_VW[6] RES_VW[5] RES_VW[4] RES_VW[3] RES_VW[2] RES_VW[1] RES_VW[0]      RES_HS[10] RES_HS[9] RES_HS[8] RES_HS[7] RES_HS[6] RES_HS[5] RES_HS[4] RES_HS[3] RES_HS[2] RES_HS[1] RES_HS[0]      RES_HW[10] RES_HW[9] RES_HW[8] RES_HW[7] RES_HW[6] RES_HW[5] RES_HW[4] RES_HW[3] RES_HW[2] RES_HW[1] RES_HW[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display SCL0_DS4  RES_PFIL_ RES_DS_H_     SEL INTERPOTYP       controller 4 SCL0_DS5 SCL0_DS6 SCL0_DS7 SCL0_US1    RES_DS_H_ RES_DS_H_ RES_DS_H_R RES_DS_H_R RES_DS_H_R RES_DS_H_ RES_DS_H_ RES_DS_H_R RATIO[15] RATIO[14] ATIO[13] ATIO[11] RATIO[9] ATIO[8] ATIO[12] RATIO[10] RES_DS_H_ RES_DS_H_ RES_DS_H_R RES_DS_H_R RES_DS_H_R RES_DS_H_ RES_DS_H_ RES_DS_H_R RATIO[7] RATIO[6] ATIO[5] ATIO[4] ATIO[3] RATIO[2] RATIO[1] ATIO[0]    RES_V_ RES_TOP_ RES_TOP_ RES_TOP_ RES_TOP_ INTERPOTYP INIPHASE[11] INIPHASE[10] INIPHASE[9] INIPHASE[8] RES_TOP_ RES_TOP_ RES_TOP_ RES_TOP_ RES_TOP_ RES_TOP_ RES_TOP_ RES_TOP_ INIPHASE[7] INIPHASE[6] INIPHASE[5] INIPHASE[4] INIPHASE[3] INIPHASE[2] INIPHASE[1] INIPHASE[0]     RES_BTM_ RES_BTM_ RES_BTM_ RES_BTM_ INIPHASE[11] INIPHASE[10] INIPHASE[9] INIPHASE[8] RES_BTM_ RES_BTM_ RES_BTM_ RES_BTM_ RES_BTM_ RES_BTM_ RES_BTM_ RES_BTM_ INIPHASE[7] INIPHASE[6] INIPHASE[5] INIPHASE[4] INIPHASE[3] INIPHASE[2] INIPHASE[1] INIPHASE[0]                 RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RATIO[15] RATIO[14] RATIO[13] RATIO[12] RATIO[11] RATIO[10] RATIO[9] RATIO[8] RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RES_V_ RATIO[7] RATIO[6] RATIO[5] RATIO[4] RATIO[3] RATIO[2] RATIO[1] RATIO[0]      RES_OUT_ RES_OUT_ RES_OUT_ VW[10] VW[9] VW[8] RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      RES_OUT_ RES_OUT_ RES_OUT_ HW[10] HW[9] HW[8] RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ RES_OUT_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]                            RES_US_V_    ON R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 RES_US_H_ ON Page 2893 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Video display SCL0_US2    RES_P_VS[10] RES_P_VS[7] RES_P_VS[6] RES_P_VS[5] RES_P_VS[4] RES_P_VS[3] RES_P_VS[2] RES_P_VS[1] RES_P_VS[0]    controller 4 SCL0_US3     Bit 24/16/8/0 RES_P_VS[9] RES_P_VS[8] RES_P_ RES_P_ RES_P_ VW[10] VW[9] VW[8] RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      RES_P_ RES_P_ RES_P_ HS[10] HS[9] HS[8] RES_P_HS[7] RES_P_HS[6] RES_P_HS[5] RES_P_HS[4] RES_P_HS[3] RES_P_HS[2] RES_P_HS[1 RES_P_HS[0] ]  SCL0_US4 SCL0_US5 SCL0_US6 Page 2894 of 3092     RES_P_ RES_P_ RES_P_ HW[10] HW[9] HW[8] RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ RES_P_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]      RES_IN_ RES_IN_ RES_IN_ VW[10] VW[9] VW[8] RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      RES_IN_ RES_IN_ RES_IN_ HW[10] HW[9] HW[8] RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ RES_IN_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]                 RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RATIO[15] RATIO[14] RATIO[13] RATIO[12] RATIO[11] RATIO[10] RATIO[9] RATIO[8] RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RES_US_H_ RATIO[7] RATIO[6] RATIO[5] RATIO[4] RATIO[3] RATIO[2] RATIO[1] RATIO[0]    RES_US_H_ RES_US_HT_ RES_US_HT_ RES_US_HT_ RES_US_HT INTERPOTYP INIPHASE[11] INIPHASE[10] INIPHASE[9] _INIPHASE[8] RES_US_HT_ RES_US_HT_ RES_US_HT_ RES_US_HT_ RES_US_HT_ RES_US_HT_ RES_US_HT_ RES_US_HT_I INIPHASE[7] INIPHASE[6] INIPHASE[5] INIPHASE[4] INIPHASE[3] INIPHASE[2] INIPHASE[1] NIPHASE[0]     RES_US_HB_ RES_US_HB_ RES_US_HB_ RES_US_HB_I INIPHASE[11] INIPHASE[10] INIPHASE[9] NIPHASE[8] RES_US_HB_ RES_US_HB_ RES_US_HB_ RES_US_HB_ RES_US_HB_ RES_US_HB_ RES_US_HB_ RES_US_HB_I INIPHASE[7] INIPHASE[6] INIPHASE[5] INIPHASE[4] INIPHASE[3] INIPHASE[2] INIPHASE[1] NIPHASE[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display SCL0_US7                 controller 4 SCL0_US8 RES_HCUT RES_HCUT RES_HCUT RES_HCUT RES_HCUT RES_HCUT RES_HCUT RES_HCUT [7] [6] [5] [4] [3] [2] [1] [0] RES_VCUT RES_VCUT RES_VCUT RES_VCUT RES_VCUT RES_VCUT RES_VCUT RES_VCUT [7] [6] [5] [4] [3] [2] [1] [0]                            RES_IBUS_    RES_DISP_ SYNC_SEL SCL0_OVR1 SCL1_ UPDATE SCL1_WR1 ON         RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ COL_R[7] COL_R[6] COL_R[5] COL_R[4] COL_R[3] COL_R[2] COL_R[1] COL_R[0] RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ COL_G[7] COL_G[6] COL_G[5] COL_G[4] COL_G[3] COL_G[2] COL_G[1] COL_G[0] RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ RES_BK_ COL_B[7] COL_B[6] COL_B[5] COL_B[4] COL_B[3] COL_B[2] COL_B[1] COL_B[0]                            SCL1_VEN_B    SCL1_VEN_A                        RES_FLM_ MD (R version only)  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 RES_DS_WR RES_DS_WR RES_DS_WR _MD[2] _MD[0] _MD[1] RES_MD[1] RES_MD[0] RES_LOOP RES_BST _MD Page 2895 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display SCL1_WR2 RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ BASE[31] BASE[30] BASE[29] BASE[28] BASE[27] BASE[26] BASE[25] BASE[24] controller 4 SCL1_WR3 SCL1_WR4 RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ BASE[23] BASE[22] BASE[21] BASE[20] BASE[19] BASE[18] BASE[17] BASE[16] RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ BASE[15] BASE[14] BASE[13] BASE[12] BASE[11] BASE[10] BASE[9] BASE[8] RES_ RES_ RES_ RES_ RES_ RES_ RES_ RES_ BASE[7] BASE[6] BASE[5] BASE[4] BASE[3] BASE[2] BASE[1] BASE[0]  RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ RES_LN_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       RES_FLM_ RES_FLM_ NUM[9] NUM[8] RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ NUM[7] NUM[6] NUM[5] NUM[4] NUM[3] NUM[2] NUM[1] NUM[0]          SCL1_WR5 RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ OFF[22] OFF[21] OFF[20] OFF[19] OFF[18] OFF[17] OFF[16] RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ OFF[15] OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]                    RES_INTER   RES_FS_ RES_FS_ RATE[1] RATE[0]    RES_FLD_    RES_WENB SEL SCL1_WR6                            RES_DTH_    ON Page 2896 of 3092 RES_ BITDEC_ON R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display SCL1_WR7                controller 4 RES_OVERFL OW  GR1_UPDATE      RES_FLM_ RES_FLM_ CNT[9] CNT[8] RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ RES_FLM_ CNT[7] CNT[6] CNT[5] CNT[4] CNT[3] CNT[2] CNT[1] CNT[0]                            GR1_P_VEN    GR1_IBUS_ VEN GR1_FLM_ RD GR1_FLM1                                GR1_R_ENB                GR1_LN_ OFF_DIR        GR1_IMR_     GR1_FLM_ GR1_FLM_ SEL[1] SEL[0]  GR1_BST FLM_INV GR1_FLM2 _MD GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ BASE[31] BASE[30] BASE[29] BASE[28] BASE[27] BASE[26] BASE[25] BASE[24] GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ BASE[23] BASE[22] BASE[21] BASE[20] BASE[19] BASE[18] BASE[17] BASE[16] GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ BASE[15] BASE[14] BASE[13] BASE[12] BASE[11] BASE[10] BASE[9] BASE[8] GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ GR1_ BASE[7] BASE[6] BASE[5] BASE[4] BASE[3] BASE[2] BASE[1] BASE[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2897 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR1_FLM3  controller 4 GR1_FLM4 GR1_FLM6 GR1_AB1 GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ GR1_LN_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       GR1_FLM_ GR1_FLM_ NUM[9] NUM[8] GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ NUM[7] NUM[6] NUM[5] NUM[4] NUM[3] NUM[2] NUM[1] NUM[0]          GR1_FLM5 GR1_LN_ OFF[14] GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ OFF[22] OFF[21] OFF[20] OFF[19] OFF[18] OFF[17] OFF[16] GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ OFF[15] OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       GR1_FLM_ GR1_FLM_ LNUM[9] LNUM[8] GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ LNUM[7] LNUM[6] LNUM[5] LNUM[4] LNUM[3] LNUM[2] LNUM[1] LNUM[0]       GR1_FLM_ GR1_FLM_ LOOP[9] LOOP[8] GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ GR1_FLM_ LOOP[7] LOOP[6] LOOP[5] LOOP[4] LOOP[3] LOOP[2] LOOP[1] LOOP[0] GR1_ GR1_ GR1_ GR1_   GR1_HW[9] GR1_HW[8] FORMAT[3] FORMAT[2] FORMAT[1] FORMAT[0] GR1_HW[7] GR1_HW[6] GR1_HW[5] GR1_HW[4] GR1_HW[3] GR1_HW[2] GR1_HW[1] GR1_HW[0]    GR1_YCC_ GR1_YCC_ GR1_YCC_ GR1_ SWAP[2] SWAP[1] SWAP[0] ENDIAN_ON   GR1_STA_ GR1_STA_ GR1_STA_ GR1_STA_ GR1_STA_ GR1_STA_ POS[5] POS[4] POS[3] POS[2] POS[1] POS[0]                            GR1_GRC_   GR1_DISP_ GR1_DISP_ SEL[1] SEL[0] DISP_ON Page 2898 of 3092 GR1_ CNV444_MD R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GR1_AB2      controller 4 GR1_AB3 GR1_AB7 GR1_AB8 GR1_AB9 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GR1_GRC_ GR1_GRC_ GR1_GRC_ VS[10] VS[9] VS[8] GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ VS[7] VS[6] VS[5] VS[4] VS[3] VS[2] VS[1] VS[0]      GR1_GRC_ GR1_GRC_ GR1_GRC_ VW[10] VW[9] VW[8] GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      GR1_GRC_ GR1_GRC_ GR1_GRC_ HS[10] HS[9] HS[8] GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] HS[0]      GR1_GRC_ GR1_GRC_ GR1_GRC_ HW[10] HW[9] HW[8] GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ GR1_GRC_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]                                GR1_CK_ON GR1_CK_ GR1_CK GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ KCLUT[7] _KCLUT[6] KCLUT[5] KCLUT[4] KCLUT[3] KCLUT[2] KCLUT[1] KCLUT[0] GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ KG[7] KG[6] KG[5] _KG[4] KG[3] KG[2] KG[1] KG[0] GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ KB[7] KB[6] KB[5] KB[4] KB[3] KB[2] KB[1] KB[0] GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ GR1_CK_ KR[7] KR[6] KR[5] KR[4] KR[3] KR[2] KR[1] KR[0] GR1_CK_A[4] GR1_CK_A[3] GR1_CK_A[2] GR1_CK_A[1 GR1_CK_A[0] GR1_CK_A[7] GR1_CK_A[6] GR1_CK_A[5] ] GR1_CK_G[7] GR1_CK_G[6] GR1_CK_G[5] GR1_CK_G[4] GR1_CK_G[3] GR1_CK_G[2] GR1_CK_G[1] GR1_CK_G[0] GR1_CK_B[7] GR1_CK_B[6] GR1_CK_B[5] GR1_CK_B[4] GR1_CK_B[3] GR1_CK_B[2] GR1_CK_B[1 GR1_CK_B[0] GR1_CK_R[7] GR1_CK_R[4] GR1_CK_R[3] GR1_CK_R[2] ] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 GR1_CK_R[6] GR1_CK_R[5] GR1_CK_R[1] GR1_CK_R[0] Page 2899 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR1_AB10 GR1_A0[7] GR1_A0[6] GR1_A0[5] GR1_A0[4] GR1_A0[3] GR1_A0[2] GR1_A0[1] GR1_A0[0] GR1_G0[7] GR1_G0[6] GR1_G0[5] GR1_G0[4] GR1_G0[3] GR1_G0[2] GR1_G0[1] GR1_G0[0] GR1_B0[7] GR1_B0[6] GR1_B0[5] GR1_B0[4] GR1_B0[3] GR1_B0[2] GR1_B0[1] GR1_B0[0] GR1_R0[7] GR1_R0[6] GR1_R0[5] GR1_R0[4] GR1_R0[3] GR1_R0[2] GR1_R0[1] GR1_R0[0] GR1_A1[7] GR1_A1[6] GR1_A1[5] GR1_A1[4] GR1_A1[3] GR1_A1[2] GR1_A1[1] GR1_A1[0] GR1_G1[7] GR1_G1[6] GR1_G1[5] GR1_G1[4] GR1_G1[3] GR1_G1[2] GR1_G1[1] GR1_G1[0] GR1_B1[7] GR1_B1[6] GR1_B1[5] GR1_B1[4] GR1_B1[3] GR1_B1[2] GR1_B1[1] GR1_B1[0] GR1_R1[7] GR1_R1[6] GR1_R1[5] GR1_R1[4] GR1_R1[3] GR1_R1[2] GR1_R1[1] GR1_R1[0]         controller 4 GR1_AB11 GR1_BASE GR1_CLUT GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ GR1_BASE_ R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0]                GR1_CLT_ SEL ADJ_UPDATE ADJ_BKSTR_ SET ADJ_ENH_ TIM1                                                ADJ_VEN        BKSTR_ON BKSTR_ST[3] BKSTR_ST[2] BKSTR_ST[1] BKSTR_ST[0] BKSTR_D[3] BKSTR_D[2] BKSTR_D[1] BKSTR_D[0]    BKSTR_T1[4] BKSTR_T1[3] BKSTR_T1[2] BKSTR_T1[1] BKSTR_T1[0]    BKSTR_T2[4] BKSTR_T2[3] BKSTR_T2[2] BKSTR_T2[1] BKSTR_T2[0]                            ENH_MD    ENH_DISP_ ON Page 2900 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display ADJ_ENH_      ENH_VS[10] ENH_VS[9] ENH_VS[8] controller 4 TIM2 ENH_VS[7] ENH_VS[6] ENH_VS[5] ENH_VS[4] ENH_VS[3] ENH_VS[2] ENH_VS[1] ENH_VS[0]      ENH_VW[10] ENH_VW[9] ENH_VW[8] ENH_VW[7] ENH_VW[6] ENH_VW[5] ENH_VW[4] ENH_VW[3] ENH_VW[2] ENH_VW[1] ENH_VW[0]      ENH_HS[10] ENH_HS[9] ENH_HS[8] ENH_HS[7] ENH_HS[6] ENH_HS[5] ENH_HS[4] ENH_HS[3] ENH_HS[2] ENH_HS[1] ENH_HS[0] ADJ_ENH_ TIM3 ADJ_ENH_ SHP1      ENH_HW[10] ENH_HW[9] ENH_HW[8] ENH_HW[7] ENH_HW[6] ENH_HW[5] ENH_HW[4] ENH_HW[3] ENH_HW[2] ENH_HW[1] ENH_HW[0]                SHP_H_ON          SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ CORE[6] CORE[5] CORE[4] CORE[3] CORE[2] CORE[1] CORE[0] ADJ_ENH_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP2 CLIP_O[7] CLIP_O[6] CLIP_O[5] CLIP_O[4] CLIP_O[3] CLIP_O[2] CLIP_O[1] CLIP_O[0] ADJ_ENH_ SHP3 SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ CLIP_U[7] CLIP_U[6] CLIP_U[5] CLIP_U[4] CLIP_U[3] CLIP_U[2] CLIP_U[1] CLIP_U[0] SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ GAIN_O[7] GAIN_O[6] GAIN_O[5] GAIN_O[4] GAIN_O[3] GAIN_O[2] GAIN_O[1] GAIN_O[0] SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ SHP_H1_ GAIN_U[7] GAIN_U[6] GAIN_U[5] GAIN_U[4] GAIN_U[3] GAIN_U[2] GAIN_U[1] GAIN_U[0]                SHP_H2_ LPF_SEL          SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ CORE[6] CORE[5] CORE[4] CORE[3] CORE[2] CORE[1] CORE[0] ADJ_ENH_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP4 CLIP_O[7] CLIP_O[6] CLIP_O[5] CLIP_O[4] CLIP_O[3] CLIP_O[2] CLIP_O[1] CLIP_O[0] SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ CLIP_U[7] CLIP_U[6] CLIP_U[5] CLIP_U[4] CLIP_U[3] CLIP_U[2] CLIP_U[1] CLIP_U[0] SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ GAIN_O[7] GAIN_O[6] GAIN_O[5] GAIN_O[4] GAIN_O[3] GAIN_O[2] GAIN_O[1] GAIN_O[0] SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ SHP_H2_ GAIN_U[7] GAIN_U[6] GAIN_U[5] GAIN_U[4] GAIN_U[3] GAIN_U[2] GAIN_U[1] GAIN_U[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2901 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display ADJ_ENH_         controller 4 SHP5                  SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ CORE[6] CORE[5] CORE[4] CORE[3] CORE[2] CORE[1] CORE[0] ADJ_ENH_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP6 CLIP_O[7] CLIP_O[6] CLIP_O[5] CLIP_O[4] CLIP_O[3] CLIP_O[2] CLIP_O[1] CLIP_O[0] ADJ_ENH_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ CLIP_U[7] CLIP_U[6] CLIP_U[5] CLIP_U[4] CLIP_U[3] CLIP_U[2] CLIP_U[1] CLIP_U[0] SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ GAIN_O[7] GAIN_O[6] GAIN_O[5] GAIN_O[4] GAIN_O[3] GAIN_O[2] GAIN_O[1] GAIN_O[0] SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ SHP_H3_ GAIN_U[7] GAIN_U[6] GAIN_U[5] GAIN_U[4] GAIN_U[3] GAIN_U[2] GAIN_U[1] GAIN_U[0] LTI_H_ON       LTI1 ADJ_ENH_ LTI_H2_INC_ LTI_H2_INC_ LTI_H2_INC_Z LTI_H2_INC_Z LTI_H2_INC_Z LTI_H2_INC_ LTI_H2_INC_ LTI_H2_INC_ ZERO[7] ZERO[6] ERO[5] ERO[4] ERO[3] ZERO[2] ZERO[1] ZERO[0] LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ GAIN[7] GAIN[6] GAIN[5] GAIN[4] GAIN[3] GAIN[2] GAIN[1] GAIN[0] LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ LTI_H2_ CORE[7] CORE[6] CORE[5] CORE[4] CORE[3] CORE[2] CORE[1] CORE[0]        LTI2 ADJ_MTX_ MODE Page 2902 of 3092 LTI_H2_ LPF_SEL LTI_H4_MEDI AN_TAP_SEL LTI_H4_INC_ LTI_H4_INC_ LTI_H4_INC_ LTI_H4_INC_ LTI_H4_INC_ LTI_H4_INC_ LTI_H4_INC_ LTI_H4_INC_ ZERO[7] ZERO[6] ZERO[5] ZERO[4] ZERO[3] ZERO[2] ZERO[1] ZERO[0] LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ GAIN[7] GAIN[6] GAIN[5] GAIN[4] GAIN[3] GAIN[2] GAIN[1] GAIN[0] LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ LTI_H4_ CORE[7] CORE[6] CORE[5] CORE[4] CORE[3] CORE[2] CORE[1] CORE[0]                               ADJ_MTX_ ADJ_MTX_ MD[1] MD[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display ADJ_MTX_         controller 4 YG_ADJ0 ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ YG[7] YG[6] YG[5] YG[4] YG[3] YG[2] YG[1] YG[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ GG[9] GG[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ GG[7] GG[6] GG[5] GG[4] GG[3] GG[2] GG[1] GG[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ GB[10] GB[9] GB[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ GB[7] GB[6] GB[5] GB[4] GB[3] GB[2] GB[1] GB[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ GR[10] GR[9] GR[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ GR[7] GR[6] GR[5] GR[4] GR[3] GR[2] GR[1] GR[0]         ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ BG[10] BG[9] BG[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ BG[7] BG[6] BG[5] BG[4] BG[3] BG[2] BG[1] BG[0]      CBB_ADJ1 CRR_ADJ0 ADJ_MTX_ ADJ_MTX_ YG_ADJ1 CBB_ADJ0 ADJ_MTX_ GG[10] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ BB[10] BB[9] BB[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ BB[7] BB[6] BB[5] BB[4] BB[3] BB[2] BB[1] BB[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ BR[10] BR[9] BR[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ BR[7] BR[6] BR[5] BR[4] BR[3] BR[2] BR[1] BR[0]         ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ RG[10] RG[9] RG[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ RG[7] RG[6] RG[5] RG[4] RG[3] RG[2] RG[1] RG[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2903 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display ADJ_MTX_    controller 4 CRR_ADJ1 GR2_UPDATE   Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ RB[10] RB[9] RB[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ RB[7] RB[6] RB[5] RB[4] RB[3] RB[2] RB[1] RB[0]      ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ RR[10] RR[9] RR[8] ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ ADJ_MTX_ RR[7] RR[6] RR[5] RR[4] RR[3] RR[2] RR[1] RR[0]                            GR2_P_VEN    GR2_IBUS_ VEN GR2_FLM_RD GR2_FLM1                                GR2_R_ENB                GR2_LN_ OFF_DIR             GR2_FLM_ GR2_FLM_ SEL[1] SEL[0]  GR2_BST_ MD GR2_FLM2 Page 2904 of 3092 GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ BASE[31] BASE[30] BASE[29] BASE[28] BASE[27] BASE[26] BASE[25] BASE[24] GR2_ GR2_ GR2 GR2_ GR2_ GR2_ GR2_ GR2_ BASE[23] BASE[22] _BASE[21] BASE[20] BASE[19] BASE[18] BASE[17] BASE[16] GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ BASE[15] BASE[14] BASE[13] BASE[12] BASE[11] BASE[10] BASE[9] BASE[8] GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ GR2_ BASE[7] BASE[6] BASE[5] BASE[4] BASE[3] BASE[2] BASE[1] BASE[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR2_FLM3  GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ GR2_LN_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       GR2_FLM_ GR2_FLM_ NUM[9] NUM[8] controller 4 GR2_FLM4 GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ NUM[7] NUM[6] NUM[5] NUM[4] NUM[3] NUM[2] NUM[1] NUM[0]          GR2_FLM5 GR2_FLM6 GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ OFF[22] OFF[21] OFF[20] OFF[19] OFF[18] OFF[17] OFF[16] GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ OFF[15] OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       GR2_FLM_ GR2_FLM_ LNUM[9] LNUM[8] GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ LNUM[7] LNUM[6] LNUM[5] LNUM[4] LNUM[3] LNUM[2] LNUM[1] LNUM[0]       GR2_FLM_ GR2_FLM_ LOOP[9] LOOP[8] GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ GR2_FLM_ LOOP[7] LOOP[6] LOOP[5] LOOP[4] LOOP[3] LOOP[2] LOOP[1] LOOP[0] GR2_ GR2_ GR2_ GR2_   GR2_HW[9] GR2_HW[8] FORMAT[3] FORMAT[2] FORMAT[1] FORMAT[0] GR2_HW[7] GR2_HW[6] GR2_HW[5] GR2_HW[4] GR2_HW[3] GR2_HW[2] GR2_HW[1] GR2_HW[0]    GR2_     ENDIAN_ON  GR2_AB1  GR2_STA_ GR2_STA_ GR2_STA_ GR2_STA_ GR2_STA_ GR2_STA_ POS[5] POS[4] POS[3] POS[2] POS[1] POS[0]                    GR2_ARC_    GR2_ARC_ ON    GR2_GRC_ DISP_ON R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 DISP_ON   GR2_DISP_ GR2_DISP_ SEL[1] SEL[0] Page 2905 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GR2_AB2      controller 4 GR2_AB3 GR2_AB4 GR2_AB5 Page 2906 of 3092 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GR2_GRC_ GR2_GRC_ GR2_GRC_ VS[10] VS[9] VS[8] GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ VS[7] VS[6] VS[5] VS[4] VS[3] VS[2] VS[1] VS[0]      GR2_GRC_ GR2_GRC_ GR2_GRC_ VW[10] VW[9] VW[8] GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      GR2_GRC_ GR2_GRC_ GR2_GRC_ HS[10] HS[9] HS[8] GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] HS[0]      GR2_GRC_ GR2_GRC_ GR2_GRC_ HW[10] HW[9] HW[8] GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ GR2_GRC_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]      GR2_ARC_ GR2_ARC_ GR2_ARC_ VS[10] VS[9] VS[8] GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ VS[7] VS[6] VS[5] VS[4] VS[3] VS[2] VS[1] VS[0]      GR2_ARC_ GR2_ARC_ GR2_ARC_ VW[10] VW[9] VW[8] GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      GR2_ARC_ GR2_ARC_ GR2_ARC_ HS[10] HS[9] HS[8] GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] HS[0]      GR2_ARC_ GR2_ARC_ GR2_ARC_ HW[10] HW[9] HW[8] GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Video display GR2_AB6        Bit 24/16/8/0 GR2_ARC_ controller 4 MODE GR2_AB7 GR2_AB8 GR2_AB9 GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ COEF[7] COEF[6] COEF[5] COEF[4] COEF[3] COEF[2] COEF[1] COEF[0]         GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ RATE[7] RATE[6] RATE[5] RATE[4] RATE[3] RATE[2] RATE[1] RATE[0]         GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ GR2_ARC_ DEF[7] DEF[6] DEF[5] DEF[4] DEF[3] EF[2] DEF[1] DEF[0]                GR2_CK_ON GR2_CK_ GR2_CK_ GR2_CK GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ KCLUT[7] KCLUT[6] _KCLUT[5] KCLUT[4] KCLUT[3] KCLUT[2] KCLUT[1] KCLUT[0] GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ KG[7] KG[6] KG[5] KG[4] KG[3] KG[2] KG[1] KG[0] GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ KB[7] KB[6] KB[5] KB[4] KB[3] KB[2] KB[1] KB[0] GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ GR2_CK_ KR[7] KR[6] KR[5] KR[4] KR[3] KR[2] KR[1] KR[0] GR2_CK_A[7] GR2_CK_A[6] GR2_CK_A[5] GR2_CK_A[4] GR2_CK_A[3] GR2_CK_A[2] GR2_CK_A[1 GR2_CK_A[0] GR2_CK_G[7] GR2_CK_G[4] GR2_CK_G[3] GR2_CK_G[2] GR2_CK_B[4] GR2_CK_B[3] GR2_CK_B[2] GR2_CK_B[1 GR2_CK_B[0] ] GR2_CK_G[6] GR2_CK_G[5] GR2_CK_B[7] GR2_CK_B[6] GR2_CK_B[5] GR2_CK_G[1] GR2_CK_G[0] ] GR2_AB10 GR2_AB11 GR2_CK_R[7] GR2_CK_R[6] GR2_CK_R[5] GR2_CK_R[4] GR2_CK_R[3] GR2_CK_R[2] GR2_CK_R[1] GR2_CK_R[0] GR2_A0[7] GR2_A0[6] GR2_A0[5] GR2_A0[4] GR2_A0[3] GR2_A0[2] GR2_A0[1] GR2_A0[0] GR2_G0[7] GR2_G0[6] GR2_G0[5] GR2_G0[4] GR2_G0[3] GR2_G0[2] GR2_G0[1] GR2_G0[0] GR2_B0[7] GR2_B0[6] GR2_B0[5] GR2_B0[4] GR2_B0[3] GR2_B0[2] GR2_B0[1] GR2_B0[0] GR2_R0[7] GR2_R0[6] GR2_R0[5] GR2_R0[4] GR2_R0[3] GR2_R0[2] GR2_R0[1] GR2_R0[0] GR2_A1[7] GR2_A1[6] GR2_A1[5] GR2_A1[4] GR2_A1[3] GR2_A1[2] GR2_A1[1] GR2_A1[0] GR2_G1[7] GR2_G1[6] GR2_G1[5] GR2_G1[4] GR2_G1[3] GR2_G1[2] GR2_G1[1] GR2_G1[0] GR2_B1[7] GR2_B1[6] GR2_B1[5] GR2_B1[4] GR2_B1[3] GR2_B1[2] GR2_B1[1] GR2_B1[0] GR2_R1[7] GR2_R1[6] GR2_R1[5] GR2_R1[4] GR2_R1[3] GR2_R1[2] GR2_R1[1] GR2_R1[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2907 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR2_BASE         GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ GR2_BASE_ R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0]                controller 4 GR2_CLUT GR2_CLT_ SEL GR2_MON                                                GR2_ARC_ ST GR3_UPDATE                            GR3_P_VEN    GR3_IBUS_ VEN GR3_FLM_RD GR3_FLM1                                GR3_R_ENB                GR3_LN_ OFF_DIR             GR3_FLM_ GR3_FLM_ SEL[1] SEL[0]  GR3_BST_ MD Page 2908 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR3_FLM2 GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ BASE[31] BASE[30] BASE[29] BASE[28] BASE[27] BASE[26] BASE[25] BASE[24] GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ BASE[23] BASE[22] BASE[21] BASE[20] BASE[19] BASE[18] BASE[17] BASE[16] GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ BASE[15] BASE[14] BASE[13] BASE[12] BASE[11] BASE[10] BASE[9] BASE[8] GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ GR3_ BASE[7] BASE[6] BASE[5] BASE[4] BASE[3] BASE[2] BASE[1] BASE[0] GR3_LN_ controller 4 GR3_FLM3 GR3_FLM4  GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ GR3_LN_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       GR3_FLM_ GR3_FLM_ NUM[9] NUM[8] GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ NUM[7] NUM[6] NUM[5] NUM[4] NUM[3] NUM[2] NUM[1] NUM[0]          GR3_FLM5 GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ OFF[22] OFF[21] OFF[20] OFF[19] OFF[18] OFF[17] OFF[16] GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ OFF[15] OFF[14] OFF[13] OFF[12] OFF[11] OFF[10] OFF[9] OFF[8] GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ OFF[7] OFF[6] OFF[5] OFF[4] OFF[3] OFF[2] OFF[1] OFF[0]       GR3_FLM_ GR3_FLM_ LNUM[9] LNUM[8] GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ LNUM[7] LNUM[6] LNUM[5] LNUM[4] LNUM[3] LNUM[2] LNUM[1] LNUM[0]       GR3_FLM_ GR3_FLM_ LOOP[9] LOOP[8] GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ GR3_FLM_ LOOP[7] LOOP[6] LOOP[5] LOOP[4] LOOP[3] LOOP[2] LOOP[1] LOOP[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2909 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR3_FLM6 GR3_ GR3_ GR3_ GR3_   GR3_HW[9] GR3_HW[8] FORMAT[3] FORMAT[2] FORMAT[1] FORMAT[0] GR3_HW[7] GR3_HW[6] GR3_HW[5] GR3_HW[4] GR3_HW[3] GR3_HW[2] GR3_HW[1] GR3_HW[0]    GR3_     controller 4 ENDIAN_ON  GR3_AB1  GR3_STA_ GR3_STA_ GR3_STA_ GR3_STA_ GR3_STA_ GR3_STA_ POS[5] POS[4] POS[3] POS[2] POS[1] POS[0]                    GR3_ARC_ON    GR3_ARC_ DISP_ON    GR3_GRC_   DISP_ON GR3_AB2 GR3_AB3 GR3_AB4 Page 2910 of 3092      GR3_DISP_ GR3_DISP_ SEL[1] SEL[0] GR3_GRC_ GR3_GRC_ GR3_GRC_ VS[10] VS[9] VS[8] GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ VS[7] VS[6] VS[5] VS[4] VS[3] VS[2] VS[1] VS[0]      GR3_GRC_ GR3_GRC_ GR3_GRC_ VW[10] VW[9] VW[8] GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0]      GR3_GRC_ GR3_GRC_ GR3_GRC_ HS[10] HS[9] HS[8] GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] HS[0]      GR3_GRC_ GR3_GRC_ GR3_GRC_ HW[10] HW[9] HW[8] GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ GR3_GRC_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]      GR3_ARC_ GR3_ARC_ GR3_ARC_ VS[10] VS[9] VS[8] GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ VS[7] VS[6] VS[5] VS[4] VS[3] VS[2] VS[1] VS[0]      GR3_ARC_ GR3_ARC_ GR3_ARC_ VW[10] VW[9] VW[8] GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ VW[7] VW[6] VW[5] VW[4] VW[3] VW[2] VW[1] VW[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GR3_AB5      controller 4 GR3_AB6 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GR3_ARC_ GR3_ARC_ GR3_ARC_ HS[10] HS[9] HS[8] GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] HS[0]      GR3_ARC_ GR3_ARC_ GR3_ARC_ HW[10] HW[9] HW[8] GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]        GR3_ARC_ MODE GR3_AB7 GR3_AB8 GR3_AB9 GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ COEF[7] COEF[6] COEF[5] COEF[4] COEF[3] COEF[2] COEF[1] COEF[0]         GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ RATE[7] RATE[6] RATE[5] RATE[4] RATE[3] RATE[2] RATE[1] RATE[0]         GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ GR3_ARC_ DEF[7] DEF[6] DEF[5] DEF[4] DEF[3] DEF[2] DEF[1] DEF[0]                GR3_CK_ON GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ KCLUT[7] KCLUT[6] KCLUT[5] KCLUT[4] KCLUT[3] KCLUT[2] KCLUT[1] KCLUT[0] GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ KG[7] KG[6] KG[5] KG[4] KG[3] KG[2] KG[1] KG[0] GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ KB[7] KB[6] KB[5] KB[4] KB[3] KB[2] KB[1] KB[0] GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ GR3_CK_ KR[7] KR[6] KR[5] KR[4] KR[3] KR[2] KR[1] KR[0] GR3_CK_A[4] GR3_CK_A[3] GR3_CK_A[2] GR3_CK_A[1 GR3_CK_A[0] GR3_CK_A[7] GR3_CK_A[6] GR3_CK_A[5] ] GR3_CK_G[7] GR3_CK_G[6] GR3_CK_G[5] GR3_CK_G[4] GR3_CK_G[3] GR3_CK_G[2] GR3_CK_G[1] GR3_CK_G[0] GR3_CK_B[7] GR3_CK_B[6] GR3_CK_B[5] GR3_CK_B[4] GR3_CK_B[3] GR3_CK_B[2] GR3_CK_B[1 GR3_CK_B[0] GR3_CK_R[7] GR3_CK_R[4] GR3_CK_R[3] GR3_CK_R[2] ] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 GR3_CK_R[6] GR3_CK_R[5] GR3_CK_R[1] GR3_CK_R[0] Page 2911 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GR3_AB10 GR3_A0[7] GR3_A0[6] GR3_A0[5] GR3_A0[4] GR3_A0[3] GR3_A0[2] GR3_A0[1] GR3_A0[0] GR3_G0[7] GR3_G0[6] GR3_G0[5] GR3_G0[4] GR3_G0[3] GR3_G0[2] GR3_G0[1] GR3_G0[0] GR3_B0[7] GR3_B0[6] GR3_B0[5] GR3_B0[4] GR3_B0[3] GR3_B0[2] GR3_B0[1] GR3_B0[0] GR3_R0[7] GR3_R0[6] GR3_R0[5] GR3_R0[4] GR3_R0[3] GR3_R0[2] GR3_R0[1] GR3_R0[0] GR3_A1[7] GR3_A1[6] GR3_A1[5] GR3_A1[4] GR3_A1[3] GR3_A1[2] GR3_A1[1] GR3_A1[0] GR3_G1[7] GR3_G1[6] GR3_G1[5] GR3_G1[4] GR3_G1[3] GR3_G1[2] GR3_G1[1] GR3_G1[0] controller 4 GR3_AB11 GR3_BASE GR3_CLUT_ INT GR3_B1[7] GR3_B1[6] GR3_B1[5] GR3_B1[4] GR3_B1[3] GR3_B1[2] GR3_B1[1] GR3_B1[0] GR3_R1[7] GR3_R1[6] GR3_R1[5] GR3_R1[4] GR3_R1[3] GR3_R1[2] GR3_R1[1] GR3_R1[0]         GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ G[7] G[6] G[5] G[4] G[3] G[2] G[1] G[0] GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ GR3_BASE_ R[7] R[6] R[5] R[4] R[3] R[2] R[1] R[0]                GR3_CLT_ SEL GR3_MON      GR3_LINE[10] GR3_LINE[9] GR3_LINE[8] GR3_LINE[7] GR3_LINE[6] GR3_LINE[5] GR3_LINE[4] GR3_LINE[3] GR3_LINE[2] GR3_LINE[1] GR3_LINE[0]                                GR3_ARC_ ST GAM_G_UPDA  TE Page 2912 of 3092                               GAM_G_VEN R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GAM_SW                                GAM_ON      GAM_G_ controller 4 GAM_G_LUT1 GAM_G_LUT2 GAM_G_LUT3 GAM_G_LUT4 GAM_G_ GAM_G_ GAIN_00[10] GAIN_00[9] GAIN_00[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_00[7] GAIN_00[6] GAIN_00[5] GAIN_00[4] GAIN_00[3] GAIN_00[2] GAIN_00[1] GAIN_00[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_01[10] GAIN_01[9] GAIN_01[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_01[7] GAIN_01[6] GAIN_01[5] GAIN_01[4] GAIN_01[3] GAIN_01[2] GAIN_01[1] GAIN_01[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_02[10] GAIN_02[9] GAIN_02[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_02[7] GAIN_02[6] GAIN_02[5] GAIN_02[4] GAIN_02[3] GAIN_02[2] GAIN_02[1] GAIN_02[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_03[10] GAIN_03[9] GAIN_03[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_03[7] GAIN_03[6] GAIN_03[5] GAIN_03[4] GAIN_03[3] GAIN_03[2] GAIN_03[1] GAIN_03[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_04[10] GAIN_04[9] GAIN_04[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_04[7] GAIN_04[6] GAIN_04[5] GAIN_04[4] GAIN_04[3] GAIN_04[2] GAIN_04[1] GAIN_04[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_05[10] GAIN_05[9] GAIN_05[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_05[7] GAIN_05[6] GAIN_05[5] GAIN_05[4] GAIN_05[3] GAIN_05[2] GAIN_05[1] GAIN_05[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_06[10] GAIN_06[9] GAIN_06[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_06[7] GAIN_06[6] GAIN_06[5] GAIN_06[4] GAIN_06[3] GAIN_06[2] GAIN_06[1] GAIN_06[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_07[10] GAIN_07[9] GAIN_07[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_07[7] GAIN_07[6] GAIN_07[5] GAIN_07[4] GAIN_07[3] GAIN_07[2] GAIN_07[1] GAIN_07[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2913 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_G_LUT5      controller 4 GAM_G_LUT6 GAM_G_LUT7 GAM_G_LUT8 Page 2914 of 3092 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GAM_G_ GAM_G_ GAM_G_ GAIN_08[10] GAIN_08[9] GAIN_08[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_08[7] GAIN_08[6] GAIN_08[5] GAIN_08[4] GAIN_08[3] GAIN_08[2] GAIN_08[1] GAIN_08[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_09[10] GAIN_09[9] GAIN_09[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_09[7] GAIN_09[6] GAIN_09[5] GAIN_09[4] GAIN_09[3] GAIN_09[2] GAIN_09[1] GAIN_09[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_10[10] GAIN_10[9] GAIN_10[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_10[7] GAIN_10[6] GAIN_10[5] GAIN_10[4] GAIN_10[3] GAIN_10[2] GAIN_10[1] GAIN_10[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_11[10] GAIN_11[9] GAIN_11[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_11[7] GAIN_11[6] GAIN_11[5] GAIN_11[4] GAIN_11[3] GAIN_11[2] GAIN_11[1] GAIN_11[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_12[10] GAIN_12[9] GAIN_12[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_12[7] GAIN_12[6] GAIN_12[5] GAIN_12[4] GAIN_12[3] GAIN_12[2] GAIN_12[1] GAIN_12[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_13[10] GAIN_13[9] GAIN_13[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_13[7] GAIN_13[6] GAIN_13[5] GAIN_13[4] GAIN_13[3] GAIN_13[2] GAIN_13[1] GAIN_13[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_14[10] GAIN_14[9] GAIN_14[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_14[7] GAIN_14[6] GAIN_14[5] GAIN_14[4] GAIN_14[3] GAIN_14[2] GAIN_14[1] GAIN_14[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_15[10] GAIN_15[9] GAIN_15[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_15[7] GAIN_15[6] GAIN_15[5] GAIN_15[4] GAIN_15[3] GAIN_15[2] GAIN_15[1] GAIN_15[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_G_LUT9      controller 4 GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_16[10] GAIN_16[9] GAIN_16[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_16[7] GAIN_16[6] GAIN_16[5] GAIN_16[4] GAIN_16[3] GAIN_16[2] GAIN_16[1] GAIN_16[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_17[10] GAIN_17[9] GAIN_17[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_17[7] GAIN_17[6] GAIN_17[5] GAIN_17[4] GAIN_17[3] GAIN_17[2] GAIN_17[1] GAIN_17[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_18[10] GAIN_18[9] GAIN_18[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_18[7] GAIN_18[6] GAIN_18[5] GAIN_18[4] GAIN_18[3] GAIN_18[2] GAIN_18[1] GAIN_18[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_19[10] GAIN_19[9] GAIN_19[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_19[7] GAIN_19[6] GAIN_19[5] GAIN_19[4] GAIN_19[3] GAIN_19[2] GAIN_19[1] GAIN_19[0]      LUT11 GAM_G_ Bit 24/16/8/0 GAM_G_ LUT10 GAM_G_ Bit 26/18/10/2 Bit 25/17/9/1 GAM_G_ GAM_G_ GAM_G_ GAIN_20[10] GAIN_20[9] GAIN_20[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_20[7] GAIN_20[6] GAIN_20[5] GAIN_20[4] GAIN_20[3] GAIN_20[2] GAIN_20[1] GAIN_20[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_21[10] GAIN_21[9] GAIN_21[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_21[7] GAIN_21[6] GAIN_21[5] GAIN_21[4] GAIN_21[3] GAIN_21[2] GAIN_21[1] GAIN_21[0]      GAM_G_ LUT12 GAM_G_ GAM_G_ GAIN_22[10] GAIN_22[9] GAIN_22[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_22[7] GAIN_22[6] GAIN_22[5] GAIN_22[4] GAIN_22[3] GAIN_22[2] GAIN_22[1] GAIN_22[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_23[10] GAIN_23[9] GAIN_23[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_23[7] GAIN_23[6] GAIN_23[5] GAIN_23[4] GAIN_23[3] GAIN_23[2] GAIN_23[1] GAIN_23[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2915 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_G_    controller 4 LUT13 GAM_G_   GAM_G_ GAM_G_ GAIN_24[9] GAIN_24[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_24[6] GAIN_24[5] GAIN_24[4] GAIN_24[3] GAIN_24[2] GAIN_24[1] GAIN_24[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_25[10] GAIN_25[9] GAIN_25[8] GAM_G_ GAM_G_ GAM_G_ GAM_G GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_25[7] GAIN_25[6] GAIN_25[5] _GAIN_25[4] GAIN_25[3] GAIN_25[2] GAIN_25[1] GAIN_25[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_26[10] GAIN_26[9] GAIN_26[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_26[7] GAIN_26[6] GAIN_26[5] GAIN_26[4] GAIN_26[3] GAIN_26[2] GAIN_26[1] GAIN_26[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_27[10] GAIN_27[9] GAIN_27[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_27[7] GAIN_27[6] GAIN_27[5] GAIN_27[4] GAIN_27[3] GAIN_27[2] GAIN_27[1] GAIN_27[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_28[10] GAIN_28[9] GAIN_28[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ AIN_28[7] GAIN_28[6] GAIN_28[5] GAIN_28[4] GAIN_28[3] GAIN_28[2] GAIN_28[1] GAIN_28[0]      GAM_G_ GAM_G_ GAM_G_G GAIN_29[10] GAIN_29[9] AIN_29[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_29[7] GAIN_29[6] GAIN_29[5] GAIN_29[4] GAIN_29[3] GAIN_29[2] GAIN_29[1] GAIN_29[0]      GAM_G_ LUT16 Page 2916 of 3092 GAM_G_ GAIN_24[10] GAIN_24[7] LUT15 GAM_G_ Bit 24/16/8/0 GAM_G_ LUT14 GAM_G_ Bit 26/18/10/2 Bit 25/17/9/1 GAM_G_ GAM_G_ GAIN_30[10] GAIN_30[9] GAIN_30[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_30[7] GAIN_30[6] GAIN_30[5] GAIN_30[4] GAIN_30[3] GAIN_30[2] GAIN_30[1] GAIN_30[0]      GAM_G_ GAM_G_ GAM_G_ GAIN_31[10] GAIN_31[9] GAIN_31[8] GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAM_G_ GAIN_31[7] GAIN_31[6] GAIN_31[5] GAIN_31[4] GAIN_31[3] GAIN_31[2] GAIN_31[1] GAIN_31[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GAM_G_         controller 4 AREA1 GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 01[7] 01[6] 01[5] 01[4] 01[3] 01[2] 01[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 02[7] 02[6] 02[5] 02[4] 02[3] 02[2] 02[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 03[7] 03[6] 03[5] 03[4] 03[3] 03[2] 03[1] GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ AREA2 04[7] 04[6] 04[5] 04[4] 04[3] 04[2] 04[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 05[7] 05[6] 05[5] 05[4] 05[3] 05[2] 05[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 06[7] 06[6] 06[5] 06[4] 06[3] 06[2] 06[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 07[7] 07[6] 07[5] 07[4] 07[3] 07[2] 07[1] GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ AREA3 08[7] 08[6] 08[5] 08[4] 08[3] 08[2] 08[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 09[7] 09[6] 09[5] 09[4] 09[3] 09[2] 09[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 10[7] 10[6] 10[5] 10[4] 10[3] 10[2] 10[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 11[7] 11[6] 11[5] 11[4] 11[3] 11[2] 11[1] GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ AREA4 12[7] 12[6] 12[5] 12[4] 12[3] 12[2] 12[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 13[7] 13[6] 13[5] 13[4] 13[3] 13[2] 13[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 14[7] 14[6] 14[5] 14[4] 14[3] 14[2] 14[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 15[7] 15[6] 15[5] 15[4] 15[3] 15[2] 15[1] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 01[0] 02[0] 03[0] 04[0] 05[0] 06[0] 07[0] 08[0] 09[0] 10[0] 11[0] 12[0] 13[0] 14[0] 15[0] Page 2917 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Video display GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ controller 4 AREA5 16[7] 16[6] 16[5] 16[4] 16[3] 16[2] 16[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 17[7] 17[6] 17[5] 17[4] 17[3] 17[2] 17[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ 18[7] 18[6] 18[5] 18[4] 18[3] 18[2] 18[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_1 19[7] 19[6] 19[5] 19[4] 19[3] 19[2] 19[1] GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 AREA6 20[7] 20[6] 20[5] 20[4] 20[3] 20[2] 20[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 21[7] 21[6] 21[5] 21[4] 21[3] 21[2] 21[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 22[7] 22[6] 22[5] 22[4] 22[3] 22[2] 22[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 23[7] 23[6] 23[5] 23[4] 23[3] 23[2] 23[1] GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 AREA7 24[7] 24[6] 24[5] 24[4] 24[3] 24[2] 24[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 25[7] 25[6] 25[5] 25[4] 25[3] 25[2] 25[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 26[7] 26[6] 26[5] 26[4] 26[3] 26[2] 26[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 27[7] 27[6] 27[5] 27[4] 27[3] 27[2] 27[1] GAM_G_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 AREA8 28[7] 28[6] 28[5] 28[4] 28[3] 28[2] 28[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_2 29[7] 29[6] 29[5] 29[4] 29[3] 29[2] 29[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_3 30[7] 30[6] 30[5] 30[4] 30[3] 30[2] 30[1] GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_ GAM_G_TH_3 31[7] 31[6] 31[5] 31[4] 31[3] 31[2] 31[1] Page 2918 of 3092 Bit 24/16/8/0 16[0] 17[0] 18[0] 9[0] 0[0] 1[0] 2[0] 3[0] 4[0] 5[0] 6[0] 7[0] 8[0] 9[0] 0[0] 1[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GAM_B_UPDA         controller 4 TE                        GAM_B_VEN      GAM_B_ GAM_B_LUT1 GAM_B_LUT2 GAM_B_LUT3 GAM_B_LUT4 GAM_B_ GAM_B_ GAIN_00[10] GAIN_00[9] GAIN_00[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_00[7] GAIN_00[6] GAIN_00[5] GAIN_00[4] GAIN_00[3] GAIN_00[2] GAIN_00[1] GAIN_00[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_01[10] GAIN_01[9] GAIN_01[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_01[7] GAIN_01[6] GAIN_01[5] GAIN_01[4] GAIN_01[3] GAIN_01[2] GAIN_01[1] GAIN_01[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_02[10] GAIN_02[9] GAIN_02[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_02[7] GAIN_02[6] GAIN_02[5] GAIN_02[4] GAIN_02[3] GAIN_02[2] GAIN_02[1] GAIN_02[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_03[10] GAIN_03[9] GAIN_03[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_03[7] GAIN_03[6] GAIN_03[5] GAIN_03[4] GAIN_03[3] GAIN_03[2] GAIN_03[1] GAIN_03[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_04[10] GAIN_04[9] GAIN_04[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_04[7] GAIN_04[6] GAIN_04[5] GAIN_04[4] GAIN_04[3] GAIN_04[2] GAIN_04[1] GAIN_04[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_05[10] GAIN_05[9] GAIN_05[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_05[7] GAIN_05[6] GAIN_05[5] GAIN_05[4] GAIN_05[3] GAIN_05[2] GAIN_05[1] GAIN_05[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_06[10] GAIN_06[9] GAIN_06[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_06[7] GAIN_06[6] GAIN_06[5] GAIN_06[4] GAIN_06[3] GAIN_06[2] GAIN_06[1] GAIN_06[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_07[10] GAIN_07[9] GAIN_07[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_07[7] GAIN_07[6] GAIN_07[5] GAIN_07[4] GAIN_07[3] GAIN_07[2] GAIN_07[1] GAIN_07[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2919 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_B_LUT5      controller 4 GAM_B_LUT6 GAM_B_LUT7 GAM_B_LUT8 Page 2920 of 3092 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GAM_B_ GAM_B_ GAM_B_ GAIN_08[10] GAIN_08[9] GAIN_08[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_08[7] GAIN_08[6] GAIN_08[5] GAIN_08[4] GAIN_08[3] GAIN_08[2] GAIN_08[1] GAIN_08[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_09[10] GAIN_09[9] GAIN_09[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_09[7] GAIN_09[6] GAIN_09[5] GAIN_09[4] GAIN_09[3] GAIN_09[2] GAIN_09[1] GAIN_09[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_10[10] GAIN_10[9] GAIN_10[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_10[7] GAIN_10[6] GAIN_10[5] GAIN_10[4] GAIN_10[3] GAIN_10[2] GAIN_10[1] GAIN_10[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_11[10] GAIN_11[9] GAIN_11[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_11[7] GAIN_11[6] GAIN_11[5] GAIN_11[4] GAIN_11[3] GAIN_11[2] GAIN_11[1] GAIN_11[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_12[10] GAIN_12[9] GAIN_12[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_12[7] GAIN_12[6] GAIN_12[5] GAIN_12[4] GAIN_12[3] GAIN_12[2] GAIN_12[1] GAIN_12[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_13[10] GAIN_13[9] GAIN_13[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_13[7] GAIN_13[6] GAIN_13[5] GAIN_13[4] GAIN_13[3] GAIN_13[2] GAIN_13[1] GAIN_13[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_14[10] GAIN_14[9] GAIN_14[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_14[7] GAIN_14[6] GAIN_14[5] GAIN_14[4] GAIN_14[3] GAIN_14[2] GAIN_14[1] GAIN_14[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_15[10] GAIN_15[9] GAIN_15[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_15[7] GAIN_15[6] GAIN_15[5] GAIN_15[4] GAIN_15[3] GAIN_15[2] GAIN_15[1] GAIN_15[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_B_LUT9      controller 4 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GAM_B_ GAM_B_ GAM_B_ GAIN_16[10] GAIN_16[9] GAIN_16[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_G GAM_B_ GAM_B_ GAIN_16[7] GAIN_16[6] GAIN_16[5] GAIN_16[4] GAIN_16[3] AIN_16[2] GAIN_16[1] GAIN_16[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_17[10] GAIN_17[9] GAIN_17[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_17[7] GAIN_17[6] GAIN_17[5] GAIN_17[4] GAIN_17[3] GAIN_17[2] GAIN_17[1] GAIN_17[0]     GAM_B_ GAM_B_ GAM_B_ GAIN_18[10] GAIN_18[9] GAIN_18[8] GAM_B_LUT10  GAM_B_GAI GAM_B_GAI GAM_B_GAIN GAM_B_GAIN GAM_B_GAIN GAM_B_ GAM_B_ GAM_B_ N_18[7] N_18[6] _18[5] _18[4] _18[3] GAIN_18[2] GAIN_18[1] GAIN_18[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_19[10] GAIN_19[9] GAIN_19[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_19[7] GAIN_19[6] GAIN_19[5] GAIN_19[4] GAIN_19[3] GAIN_19[2] GAIN_19[1] GAIN_19[0]     GAM_B_ GAM_B_ GAM_B_ GAIN_20[10] GAIN_20[9] GAIN_20[8] GAM_B_LUT11  GAM_B_ GAM_B_ GAM_B_GAIN GAM_B_GAIN GAM_B_GAIN GAM_B_ GAM_B_ GAM_B_ GAIN_20[7] GAIN_20[6] _20[5] _20[4] _20[3] GAIN_20[2] GAIN_20[1] GAIN_20[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_21[10] GAIN_21[9] GAIN_21[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_21[7] GAIN_21[6] GAIN_21[5] GAIN_21[4] GAIN_21[3] GAIN_21[2] GAIN_21[1] GAIN_21[0]     GAM_B_ GAM_B_LUT12  GAM_B_ GAM_B_ GAIN_22[10] GAIN_22[9] GAIN_22[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_22[7] GAIN_22[6] GAIN_22[5] GAIN_22[4] GAIN_22[3] GAIN_22[2] GAIN_22[1] GAIN_22[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_23[10] GAIN_23[9] GAIN_23[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_23[7] GAIN_23[6] GAIN_23[5] GAIN_23[4] GAIN_23[3] GAIN_23[2] GAIN_23[1] GAIN_23[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2921 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Video display GAM_B_LUT13  Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5   Bit 28/20/12/4 Bit 27/19/11/3   controller 4 Bit 24/16/8/0 GAM_B_ GAM_B_ GAM_B_ GAIN_24[10] GAIN_24[9] GAIN_24[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_24[7] GAIN_24[6] GAIN_24[5] GAIN_24[4] GAIN_24[3] GAIN_24[2] GAIN_24[1] GAIN_24[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_25[10] GAIN_25[9] GAIN_25[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_25[7] GAIN_25[6] GAIN_25[5] GAIN_25[4] GAIN_25[3] GAIN_25[2] GAIN_25[1] GAIN_25[0]     GAM_B_ GAM_B_LUT14  GAM_B_ GAM_B_ GAIN_26[10] GAIN_26[9] GAIN_26[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_26[7] GAIN_26[6] GAIN_26[5] GAIN_26[4] GAIN_26[3] GAIN_26[2] GAIN_26[1] GAIN_26[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_27[10] GAIN_27[9] GAIN_27[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_27[7] GAIN_27[6] GAIN_27[5] GAIN_27[4] GAIN_27[3] GAIN_27[2] GAIN_27[1] GAIN_27[0]     GAM_B_LUT15  GAM_B_ GAM_B_ GAM_B_ GAIN_28[10] GAIN_28[9] GAIN_28[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_28[7] GAIN_28[6] GAIN_28[5] GAIN_28[4] GAIN_28[3] GAIN_28[2] GAIN_28[1] GAIN_28[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_29[10] GAIN_29[9] GAIN_29[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_GAI GAM_B_ GAM_B_ GAIN_29[7] GAIN_29[6] GAIN_29[5] GAIN_29[4] GAIN_29[3] N_29[2] GAIN_29[1] GAIN_29[0]     GAM_B_ GAM_B_LUT16  Page 2922 of 3092 Bit 26/18/10/2 Bit 25/17/9/1 GAM_B_ GAM_B_ GAIN_30[10] GAIN_30[9] GAIN_30[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_30[7] GAIN_30[6] GAIN_30[5] GAIN_30[4] GAIN_30[3] GAIN_30[2] GAIN_30[1] GAIN_30[0]      GAM_B_ GAM_B_ GAM_B_ GAIN_31[10] GAIN_31[9] GAIN_31[8] GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAM_B_ GAIN_31[7] GAIN_31[6] GAIN_31[5] GAIN_31[4] GAIN_31[3] GAIN_31[2] GAIN_31[1] GAIN_31[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GAM_B_         controller 4 AREA1 GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 01[7] 01[6] 01[5] 01[4] 01[3] 01[2] 01[1] 01[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 02[7] 02[6] 02[5] 02[4] 02[3] 02[2] 02[1] 02[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 03[7] 03[6] 03[5] 03[4] 03[3] 03[2] 03[1] 03[0] GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ AREA2 04[7] 04[6] 04[5] 04[4] 04[3] 04[2] 04[1] 04[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 05[7] 05[6] 05[5] 05[4] 05[3] 05[2] 05[1] 05[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 06[7] 06[6] 06[5] 06[4] 06[3] 06[2] 06[1] 06[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 07[7] 07[6] 07[5] 07[4] 07[3] 07[2] 07[1] 07[0] GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ AREA3 08[7] 08[6] 08[5] 08[4] 08[3] 08[2] 08[1] 08[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 09[7] 09[6] 09[5] 09[4] 09[3] 09[2] 09[1] 09[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 10[7] 10[6] 10[5] 10[4] 10[3] 10[2] 10[1] 10[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 11[7] 11[6] 11[5] 11[4] 11[3] 11[2] 11[1] 11[0] GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ AREA4 12[7] 12[6] 12[5] 12[4] 12[3] 12[2] 12[1] 12[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 13[7] 13[6] 13[5] 13[4] 13[3] 13[2] 13[1] 13[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 14[7] 14[6] 14[5] 14[4] 14[3] 14[2] 14[1] 14[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 15[7] 15[6] 15[5] 15[4] 15[3] 15[2] 15[1] 15[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2923 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ controller 4 AREA5 16[7] 16[6] 16[5] 16[4] 16[3] 16[2] 16[1] 16[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 17[7] 17[6] 17[5] 17[4] 17[3] 17[2] 17[1] 17[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 18[7] 18[6] 18[5] 18[4] 18[3] 18[2] 18[1] 18[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 19[7] 19[6] 19[5] 19[4] 19[3] 19[2] 19[1] 19[0] GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ AREA6 20[7] 20[6] 20[5] 20[4] 20[3] 20[2] 20[1] 20[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 21[7] 21[6] 21[5] 21[4] 21[3] 21[2] 21[1] 21[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 22[7] 22[6] 22[5] 22[4] 22[3] 22[2] 22[1] 22[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 23[7] 23[6] 23[5] 23[4] 23[3] 23[2] 23[1] 23[0] GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ AREA7 24[7] 24[6] 24[5] 24[4] 24[3] 24[2] 24[1] 24[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 25[7] 25[6] 25[5] 25[4] 25[3] 25[2] 25[1] 25[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 26[7] 26[6] 26[5] 26[4] 26[3] 26[2] 26[1] 26[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 27[7] 27[6] 27[5] 27[4] 27[3] 27[2] 27[1] 27[0] GAM_B_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ AREA8 28[7] 28[6] 28[5] 28[4] 28[3] 28[2] 28[1] 28[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 29[7] 29[6] 29[5] 29[4] 29[3] 29[2] 29[1] 29[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 30[7] 30[6] 30[5] 30[4] 30[3] 30[2] 30[1] 30[0] GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ GAM_B_TH_ 31[7] 31[6] 31[5] 31[4] 31[3] 31[2] 31[1] 31[0]                               GAM_R_VEN GAM_R_UPDA  TE Page 2924 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_R_LUT1      controller 4 GAM_R_LUT2 GAM_R_LUT3 GAM_R_LUT4 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GAM_R_ GAM_R_ GAM_R_ GAIN_00[10] GAIN_00[9] GAIN_00[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_00[7] GAIN_00[6] GAIN_00[5] GAIN_00[4] GAIN_00[3] GAIN_00[2] GAIN_00[1] GAIN_00[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_01[7] GAIN_01[6] GAIN_01[5]    GAM_R_ GAIN_01[4]  GAM_R_ GAM_R_ GAM_R_ GAIN_01[10] GAIN_01[9] GAIN_01[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_01[3] GAIN_01[2] GAIN_01[1] GAIN_01[0]  GAM_R_ GAM_R_ GAM_R_ GAIN_02[10] GAIN_02[9] GAIN_02[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_02[7] GAIN_02[6] GAIN_02[5] GAIN_02[4] GAIN_02[3] GAIN_02[2] GAIN_02[1] GAIN_02[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_03[10] GAIN_03[9] GAIN_03[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_03[7] GAIN_03[6] GAIN_03[5] GAIN_03[4] GAIN_03[3] GAIN_03[2] GAIN_03[1] GAIN_03[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_04[10] GAIN_04[9] GAIN_04[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_04[7] GAIN_04[6] GAIN_04[5] GAIN_04[4] GAIN_04[3] GAIN_04[2] GAIN_04[1] GAIN_04[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_05[10] GAIN_05[9] GAIN_05[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_05[7] GAIN_05[6] GAIN_05[5] GAIN_05[4] GAIN_05[3] GAIN_05[2] GAIN_05[1] GAIN_05[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_06[10] GAIN_06[9] GAIN_06[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_06[7] GAIN_06[6] GAIN_06[5] GAIN_06[4] GAIN_06[3] GAIN_06[2] GAIN_06[1] GAIN_06[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_07[10] GAIN_07[9] GAIN_07[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_07[7] GAIN_07[6] GAIN_07[5] GAIN_07[4] GAIN_07[3] GAIN_07[2] GAIN_07[1] GAIN_07[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2925 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_R_LUT5      controller 4 GAM_R_LUT6 GAM_R_LUT7 GAM_R_LUT8 Page 2926 of 3092 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 GAM_R_ GAM_R_ GAM_R_ GAIN_08[10] GAIN_08[9] GAIN_08[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_08[7] GAIN_08[6] GAIN_08[5] GAIN_08[4] GAIN_08[3] GAIN_08[2] GAIN_08[1] GAIN_08[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_09[10] GAIN_09[9] GAIN_09[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_09[7] GAIN_09[6] GAIN_09[5] GAIN_09[4] GAIN_09[3] GAIN_09[2] GAIN_09[1] GAIN_09[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_10[10] GAIN_10[9] GAIN_10[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ AIN_10[7] GAIN_10[6] GAIN_10[5] GAIN_10[4] GAIN_10[3] GAIN_10[2] GAIN_10[1] GAIN_10[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_11[10] GAIN_11[9] GAIN_11[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_11[7] GAIN_11[6] GAIN_11[5] GAIN_11[4] GAIN_11[3] GAIN_11[2] GAIN_11[1] GAIN_11[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_12[10] GAIN_12[9] GAIN_12[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_12[7] GAIN_12[6] GAIN_12[5] GAIN_12[4] GAIN_12[3] GAIN_12[2] GAIN_12[1] GAIN_12[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_13[10] GAIN_13[9] GAIN_13[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_13[7] GAIN_13[6] GAIN_13[5] GAIN_13[4] GAIN_13[3] GAIN_13[2] GAIN_13[1] GAIN_13[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_14[10] GAIN_14[9] GAIN_14[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_14[7] GAIN_14[6] GAIN_14[5] GAIN_14[4] GAIN_14[3] GAIN_14[2] GAIN_14[1] GAIN_14[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_15[10] GAIN_15[9] GAIN_15[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_15[7] GAIN_15[6] GAIN_15[5] GAIN_15[4] GAIN_15[3] GAIN_15[2] GAIN_15[1] GAIN_15[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_R_LUT9      controller 4 GAM_R_ GAM_R_GAI GAM_R_GAI GAM_R_GAIN N_16[10] N_16[9] _16[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_16[7] GAIN_16[6] GAIN_16[5] GAIN_16[4] GAIN_16[3] GAIN_16[2] GAIN_16[1] GAIN_16[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_17[10] GAIN_17[9] GAIN_17[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_17[7] GAIN_17[6] GAIN_17[5] GAIN_17[4] GAIN_17[3] GAIN_17[2] GAIN_17[1] GAIN_17[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_18[10] GAIN_18[9] GAIN_18[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_18[7] GAIN_18[6] GAIN_18[5] GAIN_18[4] GAIN_18[3] GAIN_18[2] GAIN_18[1] GAIN_18[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_19[10] GAIN_19[9] GAIN_19[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_19[7] GAIN_19[6] GAIN_19[5] GAIN_19[4] GAIN_19[3] GAIN_19[2] GAIN_19[1] GAIN_19[0]      LUT11 GAM_R_ Bit 24/16/8/0 GAM_R_ LUT10 GAM_R_ Bit 26/18/10/2 Bit 25/17/9/1 GAM_R_ GAM_R_ GAM_R_ GAIN_20[10] GAIN_20[9] GAIN_20[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_20[7] GAIN_20[6] GAIN_20[5] GAIN_20[4] GAIN_20[3] GAIN_20[2] GAIN_20[1] GAIN_20[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_21[10] GAIN_21[9] GAIN_21[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_21[7] GAIN_21[6] GAIN_21[5] GAIN_21[4] GAIN_21[3] GAIN_21[2] GAIN_21[1] GAIN_21[0]      GAM_R_ LUT12 GAM_R_ GAM_R_ GAIN_22[10] GAIN_22[9] GAIN_22[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_22[7] GAIN_22[6] GAIN_22[5] GAIN_22[4] GAIN_22[3] GAIN_22[2] GAIN_22[1] GAIN_22[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_23[10] GAIN_23[9] GAIN_23[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_23[7] GAIN_23[6] GAIN_23[5] GAIN_23[4] GAIN_23[3] GAIN_23[2] GAIN_23[1] GAIN_23[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2927 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display GAM_R_    controller 4 LUT13 GAM_R_   GAM_R_ GAM_R_ GAIN_24[9] GAIN_24[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_24[6] GAIN_24[5] GAIN_24[4] GAIN_24[3] GAIN_24[2] GAIN_24[1] GAIN_24[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_25[10] GAIN_25[9] GAIN_25[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_25[7] GAIN_25[6] GAIN_25[5] GAIN_25[4] GAIN_25[3] GAIN_25[2] GAIN_25[1] GAIN_25[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_26[10] GAIN_26[9] GAIN_26[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_26[7] GAIN_26[6] GAIN_26[5] GAIN_26[4] GAIN_26[3] GAIN_26[2] GAIN_26[1] GAIN_26[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_27[10] GAIN_27[9] GAIN_27[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_27[7] GAIN_27[6] GAIN_27[5] GAIN_27[4] GAIN_27[3] GAIN_27[2] GAIN_27[1] GAIN_27[0]      GAM_R_GAI GAM_R_GAI GAM_R_GAIN N_28[10] N_28[9] _28[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_28[7] GAIN_28[6] GAIN_28[5] GAIN_28[4] GAIN_28[3] GAIN_28[2] GAIN_28[1] GAIN_28[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_29[10] GAIN_29[9] GAIN_29[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_29[7] GAIN_29[6] GAIN_29[5] GAIN_29[4] GAIN_29[3] GAIN_29[2] GAIN_29[1] GAIN_29[0]      GAM_R_ LUT16 Page 2928 of 3092 GAM_R_ GAIN_24[10] GAIN_24[7] LUT15 GAM_R_ Bit 24/16/8/0 GAM_R_ LUT14 GAM_R_ Bit 26/18/10/2 Bit 25/17/9/1 GAM_R_ GAM_R_ GAIN_30[10] GAIN_30[9] GAIN_30[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_30[7] GAIN_30[6] GAIN_30[5] GAIN_30[4] GAIN_30[3] GAIN_30[2] GAIN_30[1] GAIN_30[0]      GAM_R_ GAM_R_ GAM_R_ GAIN_31[10] GAIN_31[9] GAIN_31[8] GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAM_R_ GAIN_31[7] GAIN_31[6] GAIN_31[5] GAIN_31[4] GAIN_31[3] GAIN_31[2] GAIN_31[1] GAIN_31[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display GAM_R_         controller 4 AREA1 GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 01[7] 01[6] 01[5] 01[4] 01[3] 01[2] 01[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 02[7] 02[6] 02[5] 02[4] 02[3] 02[2] 02[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 03[7] 03[6] 03[5] 03[4] 03[3] 03[2] 03[1] GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ AREA2 04[7] 04[6] 04[5] 04[4] 04[3] 04[2] 04[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 05[7] 05[6] 05[5] 05[4] 05[3] 05[2] 05[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 06[7] 06[6] 06[5] 06[4] 06[3] 06[2] 06[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 07[7] 07[6] 07[5] 07[4] 07[3] 07[2] 07[1] GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ AREA3 08[7] 08[6] 08[5] 08[4] 08[3] 08[2] 08[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 09[7] 09[6] 09[5] 09[4] 09[3] 09[2] 09[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 10[7] 10[6] 10[5] 10[4] 10[3] 10[2] 10[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 11[7] 11[6] 11[5] 11[4] 11[3] 11[2] 11[1] GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ AREA4 12[7] 12[6] 12[5] 12[4] 12[3] 12[2] 12[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 13[7] 13[6] 13[5] 13[4] 13[3] 13[2] 13[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 14[7] 14[6] 14[5] 14[4] 14[3] 14[2] 14[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 15[7] 15[6] 15[5] 15[4] 15[3] 15[2] 15[1] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 01[0] 02[0] 03[0] 04[0] 05[0] 06[0] 07[0] 08[0] 09[0] 10[0] 11[0] 12[0] 13[0] 14[0] 15[0] Page 2929 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Video display GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ controller 4 AREA5 16[7] 16[6] 16[5] 16[4] 16[3] 16[2] 16[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 17[7] 17[6] 17[5] 17[4] 17[3] 17[2] 17[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 18[7] 18[6] 18[5] 18[4] 18[3] 18[2] 18[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 19[7] 19[6] 19[5] 19[4] 19[3] 19[2] 19[1] GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ AREA6 20[7] 20[6] 20[5] 20[4] 20[3] 20[2] 20[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 21[7] 21[6] 21[5] 21[4] 21[3] 21[2] 21[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 22[7] 22[6] 22[5] 22[4] 22[3] 22[2] 22[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 23[7] 23[6] 23[5] 23[4] 23[3] 23[2] 23[1] GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ AREA7 24[7] 24[6] 24[5] 24[4] 24[3] 24[2] 24[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 25[7] 25[6] 25[5] 25[4] 25[3] 25[2] 25[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 26[7] 26[6] 26[5] 26[4] 26[3] 26[2] 26[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 27[7] 27[6] 27[5] 27[4] 27[3] 27[2] 27[1] GAM_R_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ AREA8 28[7] 28[6] 28[5] 28[4] 28[3] 28[2] 28[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 29[7] 29[6] 29[5] 29[4] 29[3] 29[2] 29[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 30[7] 30[6] 30[5] 30[4] 30[3] 30[2] 30[1] GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ GAM_R_TH_ 31[7] 31[6] 31[5] 31[4] 31[3] 31[2] 31[1] 31[0]                                TCON_VEN TCON_UPDAT E Page 2930 of 3092 Bit 24/16/8/0 16[0] 17[0] 18[0] 19[0] 20[0] 21[0] 22[0] 23[0] 24[0] 25[0] 26[0] 27[0] 28[0] 29[0] 30[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Video display TCON_TIM      controller 4 TCON_ TCON_ TCON_ HALF[10] HALF[9] HALF[8] TCON_ TCON_ TCON_ TCON_ TCON_ TCON_ TCON_ HALF[7] HALF[6] HALF[5] HALF[4] HALF[3] HALF[2] HALF[1] HALF[0]      TCON_OFFS TCON_OFFS TCON_OFFS ET[10] ET[9] ET[8] TCON_ TCON_ TCON_ TCON_ TCON_ TCON_ TCON_ TCON_ OFFSET[7] OFFSET[6] OFFSET[5] OFFSET[4] OFFSET[3] OFFSET[2] OFFSET[1] OFFSET[0]     TCON_STVA TCON_STVA TCON_STVA VA1 _VS[10] _VS[9] _VS[8] TCON_STVA TCON_STVA TCON_STVA_ TCON_STVA_ TCON_STVA_ TCON_STVA TCON_STVA TCON_STVA _VS[7] _VS[6] VS[5] VS[4] VS[3] _VS[2] _VS[1]      TCON_STVA TCON_STVA TCON_STVA _VW[10] _VW[9] _VS[0] _VW[8] TCON_STVA TCON_STVA TCON_STVA_ TCON_STVA_ TCON_STVA_ TCON_STVA TCON_STVA TCON_STVA _VW[7] _VW[6] VW[5] VW[4] VW[3] _VW[2] _VW[1] _VW[0]                           TCON_STVA_I  TCON_STVA TCON_STVA TCON_STVA NV _SEL[2] _SEL[1] TCON_STVB TCON_STVB TCON_STVB _VS[10] _VS[9] TCON_TIM_ST  TCON_TIM_ST      VB1 _SEL[0] _VS[8] TCON_STVB TCON_STVB TCON_STVB_ TCON_STVB_ TCON_STVB_ TCON_STVB TCON_STVB TCON_STVB _VS[7] _VS[6] VS[5] VS[4] VS[3] _VS[2] _VS[1]      TCON_STVB TCON_STVB TCON_STVB _VW[10] _VW[9] _VS[0] _VW[8] TCON_STVB TCON_STVB TCON_STVB_ TCON_STVB_ TCON_STVB_ TCON_STVB TCON_STVB TCON_STVB _VW[7] _VW[6] VW[5] VW[4] VW[3] _VW[2] _VW[1] _VW[0]                           TCON_STVB_I  TCON_STVB TCON_STVB TCON_STVB NV _SEL[2] _SEL[1] TCON_TIM_ST  VB2 Bit 24/16/8/0 TCON_ TCON_TIM_ST  VA2 Bit 26/18/10/2 Bit 25/17/9/1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 _SEL[0] Page 2931 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Video display TCON_TIM_ST  controller 4 H1 TCON_TIM_ STH2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5   Bit 28/20/12/4 Bit 27/19/11/3   Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 TCON_STH_ TCON_STH_ TCON_STH_ HS[10] HS[9] HS[8] TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] HS[0]      TCON_STH_ TCON_STH_ TCON_STH_ HW[10] HW[9] HW[8] TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ TCON_STH_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0]                        TCON_STH_ HS_SEL    TCON_STH_  INV TCON_TIM_      STB1 TCON_TIM_ STB2 TCON_STH_ TCON_STH_ TCON_STH_S SEL[2] SEL[1] EL[0] TCON_STB_H TCON_STB_ TCON_STB_ HS[10] HS[9] S[8] TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_H HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1] S[0]      TCON_STB_ TCON_STB_ TCON_STB_H HW[10] HW[9] W[8] TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_ TCON_STB_H HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] W[0]                        TCON_STB_H S_SEL    TCON_STB_  INV TCON_TIM_CP      V1 Page 2932 of 3092 TCON_STB_ TCON_STB_ TCON_STB_S SEL[2] SEL[1] EL[0] TCON_CPV_ TCON_CPV_ TCON_CPV_ HS[10] HS[9] HS[8] TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ HS[7] HS[6] HS[5] HS[4] HS[3] HS[2] HS[1]      HS[0] TCON_CPV_ TCON_CPV_ TCON_CPV_ HW[10] HW[9] HW[8] TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ TCON_CPV_ HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Video display TCON_TIM_CP  controller 4 V2 Section 51 List of Registers Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                       TCON_CPV_ HS_SEL    TCON_CPV_  INV TCON_TIM_      POLA1 TCON_TIM_ POLA2 SEL[0] TCON_POLA TCON_POLA TCON_POLA _HS[10] _HS[9] _HS[8] TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA _HS[6] _HS[5] _HS[4] _HS[3] _HS[2] _HS[1]      _HS[0] TCON_POLA TCON_POLA TCON_POLA _HW[10] _HW[9] _HW[8] TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA TCON_POLA _HW[7] _HW[6] _HW[5] _HW[4] _HW[3] _HW[2] _HW[1] _HW[0]                   TCON_POLA TCON_POLA    _MD[1] _MD[0]  TCON_POLA_      TCON_POLA _HS_SEL   POLB1 POLB2 SEL[1] _HS[7] INV TCON_TIM_ TCON_CPV_ TCON_CPV_ TCON_POLA  TCON_TIM_ TCON_CPV_ SEL[2] TCON_POLA TCON_POLA TCON_POLA _SEL[2] _SEL[1] TCON_POLB TCON_POLB TCON_POLB _HS[10] _HS[9] _SEL[0] _HS[8] TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB _HS[7] _HS[6] _HS[5] _HS[4] _HS[3] _HS[2] _HS[1]      _HS[0] TCON_POLB TCON_POLB TCON_POLB _HW[10] _HW[9] _HW[8] TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB TCON_POLB _HW[7] _HW[6] _HW[5] _HW[4] _HW[3] _HW[2] _HW[1] _HW[0]                   TCON_POLB TCON_POLB    _MD[1] _MD[0]  TCON_POLB_   INV R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 TCON_POLB _HS_SEL  TCON_POLB TCON_POLB TCON_POLB _SEL[2] _SEL[1] _SEL[0] Page 2933 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Video display TCON_TIM_DE    controller 4 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0                             TCON_DE_ INV OUT_UPDATE                                OUTCNT_ VEN OUT_SET    OUT_    ENDIAN_ON OUT_ SWAP_ON           OUT_ OUT_   OUT_FRQ_ OUT_FRQ_S FORMAT[1] FORMAT[0] SEL[1] EL[0]  OUT_DIR_ OUT_ OUT_ PHASE[1] PHASE[0]     SEL OUT_BRIGHT1                       PBRT_G[9] PBRT_G[8] PBRT_G[7] PBRT_G[6] PBRT_G[5] PBRT_G[4] PBRT_G[3] PBRT_G[2] PBRT_G[1] PBRT_G[0]      PBRT_B[9] PBRT_B[8] PBRT_B[7] PBRT_B[6] PBRT_B[5] PBRT_B[4] PBRT_B[3] PBRT_B[2] PBRT_B[1] PBRT_B[0]       PBRT_R[9] PBRT_R[8] PBRT_R[7] PBRT_R[6] PBRT_R[5] PBRT_R[4] PBRT_R[3] PBRT_R[2] PBRT_R[1] PBRT_R[0] OUT_BRIGHT2  OUT_ CONTRAST Page 2934 of 3092         CONT_G[7] CONT_G[6] CONT_G[5] CONT_G[4] CONT_G[3] CONT_G[2] CONT_G[1] CONT_G[0] CONT_B[7] CONT_B[6] CONT_B[5] CONT_B[4] CONT_B[3] CONT_B[2] CONT_B[1] CONT_B[0] CONT_R[7] CONT_R[6] CONT_R[5] CONT_R[4] CONT_R[3] CONT_R[2] CONT_R[1] CONT_R[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Video display OUT_PDTHA           PDTH_SEL[1] PDTH_SEL[0]   PDTH_ PDTH_ FORMAT[1] FORMAT[0] controller 4 OUT_CLK_ PHASE   PDTH_PA[1] PDTH_PA[0]   PDTH_PB[1] PDTH_PB[0]   PDTH_PC[1] PDTH_PC[0]   PDTH_PD[1] PDTH_PD[0]                    OUTCNT_    OUTCNT_ FRONT_GAM  SYSCNT_INT1 SYSCNT_INT2 SYSCNT_INT3 LCD_EDGE OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ OUTCNT_ STVA_EDGE STVB_EDGE STH_EDGE STB_EDGE CPV_EDGE POLA_EDGE POLB_EDGE OUTCNT_                                INT_STA8    INT_STA7    INT_STA6    INT_STA5    INT_STA4    INT_STA3    INT_STA2    INT_STA1    INT_STA0                                INT_OUT8_ ON SYSCNT_INT4    INT_OUT7_    ON    INT_OUT5_    ON    INT_OUT3_   INT_OUT1_ ON R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 INT_OUT4_ ON    ON  INT_OUT6_ ON INT_OUT2_ ON    INT_OUT0_ ON Page 2935 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Video display SYSCNT_  PANEL_ PANEL_   controller 4 PANEL_CLK ICKSEL[1] ICKSEL[0] PANEL_ PANEL_ PANEL_ PANEL_ PANEL_ PANEL_ DCDR[5] DCDR[4] DCDR[3] DCDR[2] DCDR[1] DCDR[0]       SYSCNT_        GR2_CLT_    SEL_ST CR SR SRCR ICR IMR DLPR Page 2936 of 3092 GR3_CLT_ SEL_ST  renderer PANEL_ ICKEN CLUT Image Bit 24/16/8/0 GR1_CLT_ SEL_ST                 SWRST          RESUME STOP   ARS RS                          DSA  STP  INT IER TRA                            STPCLR  INTCLR IERCLR TRACLR                            STPENB  INTENB IERENB TRAENB                            STM  INM IEM TRAM DLP[31] DLP[30] DLP[29] DLP[28] DLP[27] DLP[26] DLP[25] DLP[24] DLP[23] DLP[22] DLP[21] DLP[20] DLP[19] DLP[18] DLP[17] DLP[16] DLP[15] DLP[14] DLP[13] DLP[12] DLP[11] DLP[10] DLP[9] DLP[8] DLP[7] DLP[6] DLP[5] DLP[4] DLP[3] DLP[2] DLP[1] DLP[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Image DLSAR DLSA[31] DLSA[30] DLSA[29] DLSA[28] DLSA[27] DLSA[26] DLSA[25] DLSA[24] DLSA[23] DLSA[22] DLSA[21] DLSA[20] DLSA[19] DLSA[18] DLSA[17] DLSA[16] DLSA[15] DLSA[14] DLSA[13] DLSA[12] DLSA[11] DLSA[10] DLSA[9] DLSA[8] DLSA[7] DLSA[6] DLSA[5] DLSA[4] DLSA[3] DLSA[2] DLSA[1] DLSA[0] DSAR[31] DSAR[30] DSAR[29] DSAR[28] DSAR[27] DSAR[26] DSAR[25] DSAR[24] DSAR[23] DSAR[22] DSAR[21] DSAR[20] DSAR[19] DSAR[18] DSAR[17] DSAR[16] renderer DSAR DSTR DSAR2 DLSAR2 TRIMR TRIMSR TRIMCR DSAR[15] DSAR[14] DSAR[13] DSAR[12] DSAR[11] DSAR[10] DSAR[9] DSAR[8] DSAR[7] DSAR[6] DSAR[5] DSAR[4] DSAR[3] DSAR[2] DSAR[1] DSAR[0]                    DSTR[12] DSTR[11] DSTR[10] DSTR[9] DSTR[8] DSTR[7] DSTR[6] DSTR[5] DSTR[4] DSTR[3] DSTR[2] DSTR[1] DSTR[0] DSAR2[31] DSAR2[30] DSAR2[29] DSAR2[28] DSAR2[27] DSAR2[26] DSAR2[25] DSAR2[24] DSAR2[23] DSAR2[22] DSAR2[21] DSAR2[20] DSAR2[19] DSAR2[18] DSAR2[17] DSAR2[16] DSAR2[15] DSAR2[14] DSAR2[13] DSAR2[12] DSAR2[11] DSAR2[10] DSAR2[9] DSAR2[8] DSAR2[7] DSAR2[6] DSAR2[5] DSAR2[4] DSAR2[3] DSAR2[2] DSAR2[1] DSAR2[0] DLSA[31] DLSA[30] DLSA[29] DLSA[28] DLSA[27] DLSA[26] DLSA[25] DLSA[24] DLSA[23] DLSA[22] DLSA[21] DLSA[20] DLSA[19] DLSA[18] DLSA[17] DLSA[16] DLSA[15] DLSA[14] DLSA[13] DLSA[12] DLSA[11] DLSA[10] DLSA[9] DLSA[8] DLSA[7] DLSA[6] DLSA[5] DLSA[4] DLSA[3] DLSA[2] DLSA[1] DLSA[0]                          TCM DUDVM DXDYM AUTOSG AUTODG BFE TME                          TCMS DUDVMS DXDYMS AUTOSGS AUTODGS BFES TMES                          TCMC DUDVMC DXDYMC AUTOSGC AUTODGC BFEC TMEC R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2937 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Image TRICR         TCV[7] TCV[6] TCV[5] TCV[4] TCV[3] TCV[2] TCV[1] TCV[0] TCU[7] TCU[6] TCU[5] TCU[4] TCU[3] TCU[2] TCU[1] TCU[0] TCY[7] TCY[6] TCY[5] TCY[4] TCY[3] TCY[2] TCY[1] TCY[0]                        DDP      UVDPO[2] UVDPO[1] UVDPO[0]       SUW[9] SUW[8] SUW[7] SUW[6] SUW[5] SUW[4] SUW[3] SUW[2] SUW[1] SUW[0]       SVW[9] SVW[8] SVW[7] SVW[6] SVW[5] SVW[4] SVW[3] SVW[2] SVW[1] SVW[0]                 renderer UVDPOR SUSR SVSR XMINR YMINR XMAXR YMAXR Page 2938 of 3092       SVSR[9] SVSR[8] SVSR[7] SVSR[6] SVSR[5] SVSR[4] SVSR[3] SVSR[2] SVSR[1] SVSR[0]                     XMIN[11] XMIN[10] XMIN[9] XMIN[8] XMIN[7] XMIN[6] XMIN[5] XMIN[4] XMIN[3] XMIN[2] XMIN[1] XMIN[0]                     YMIN[11] YMIN[10] YMIN[9] YMIN[8] YMIN[7] YMIN[6] YMIN[5] YMIN[4] YMIN[3] YMIN[2] YMIN[1] YMIN[0]                     XMAX[11] XMAX[10] XMAX[9] XMAX[8] XMAX[7] XMAX[6] XMAX[5] XMAX[4] XMAX[3] XMAX[2] XMAX[1] XMAX[0]                     YMAX[11] YMAX[10] YMAX[9] YMAX[8] YMAX[7] YMAX[6] YMAX[5] YMAX[4] YMAX[3] YMAX[2] YMAX[1] YMAX[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Image AMXSR                       AMXS[9] AMXS[8] AMXS[7] AMXS[6] AMXS[5] AMXS[4] AMXS[3] AMXS[2] AMXS[1] AMXS[0]                       AMYS[9] AMYS[8] AMYS[7] AMYS[6] AMYS[5] AMYS[4] AMYS[3] AMYS[2] AMYS[1] AMYS[0]                       AMXO[9] AMXO[8] AMXO[7] AMXO[6] AMXO[5] AMXO[4] AMXO[3] AMXO[2] AMXO[1] AMXO[0]                 renderer AMYSR AMXOR AMYOR MACR1 LSPR LEPR LMSR       AMYO[9] AMYO[8] AMYO[7] AMYO[6] AMYO[5] AMYO[4] AMYO[3] AMYO[2] AMYO[1] AMYO[0]                    EMAM   LWSWAP                                LSPR[9] LSPR[8] LSPR[7] LSPR[6] LSPR[5] LSPR[4] LSPR[3] LSPR[2] LSPR[1] LSPR[0]                       LEPR[9] LEPR[8] LEPR[7] LEPR[6] LEPR[5] LEPR[4] LEPR[3] LEPR[2] LEPR[1] LEPR[0]                              LMSR[2] LMSR[1] LMSR[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2939 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Display out DOCMCR                CMPRU                CMPR                                CMPST                                CMPCLST                                CMPIEN                CMPBT CMPDFA[7] CMPDFA[6] CMPDFA[5] CMPDFA[4] CMPDFA[3] CMPDFA[2] CMPDFA[1] CMPDFA[0] CMPDAUF    CMPSELP[3] CMPSELP[2] CMPSELP[1] CMPSELP[0] CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC [31] [30] [29] [28] [27] [26] [25] [24] CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC [23] [22] [21] [20] [19] [18] [17] [16] CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC CMPECRC [15] [14] [13] [12] [11] [10] [9] [8] CMPECRC[7] CMPECRC[6] CMPECRC[5] CMPECRC[4] CMPECRC[3] CMPECRC[2] CMPECRC[1] CMPECRC[0] comparison unit DOCMSTR DOCMCLSTR DOCMIENR DOCMPMR DOCMECRCR DOCMCCRCR CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCR CMPCCRC [31] [30] [29] [28] [27] C[26] [25] [24] CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC [23] [22] [21] [20] [19] [18] [17] [16] CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC CMPCCRC [15] [14] [13] [12] [11] [10] [9] [8] CMPCCRC[4] CMPCCRC[3] CMPCCRC[2] CMPCCRC[1] CMPCCRC[0] CMPCCRC[7] CMPCCRC[6] CMPCCRC[5] Page 2940 of 3092 CMPCCRC R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Display out DOCMSPXR                      CMPSPX[10] CMPSPX[9] CMPSPX[8] CMPSPX[7] CMPSPX[6] CMPSPX[5] CMPSPX[4] CMPSPX[3] CMPSPX[2] CMPSPX[1] CMPSPX[0]                      CMPSPY[10] CMPSPY[9] CMPSPY[8] CMPSPY[7] CMPSPY[6] CMPSPY[5] CMPSPY[4] CMPSPY[3] CMPSPY[2] CMPSPY[1] CMPSPY[0]                      CMPSZX[10] CMPSZX[9] CMPSZX[8] CMPSZX[7] CMPSZX[6] CMPSZX[5] CMPSZX[4] CMPSZX[3] CMPSZX[2] CMPSZX[1] CMPSZX[0]                 comparison unit DOCMSPYR DOCMSZXR DOCMSZYR      CMPSZY[10] CMPSZY[9] CMPSZY[8] CMPSZY[7] CMPSZY[6] CMPSZY[5] CMPSZY[4] CMPSZY[3] CMPSZY[2] CMPSZY[1] CMPSZY[0] CRCINI[31] CRCINI[30] CRCINI[29] CRCINI[28] CRCINI[27] CRCINI[26] CRCINI[25] CRCINI[24] CRCINI[23] CRCINI[22] CRCINI[21] CRCINI[20] CRCINI[19] CRCINI[18] CRCINI[17] CRCINI[16] CRCINI[15] CRCINI[14] CRCINI[13] CRCINI[12] CRCINI[11] CRCINI[10] CRCINI[9] CRCINI[8] CRCINI[7] CRCINI[6] CRCINI[5] CRCINI[4] CRCINI[3] CRCINI[2] CRCINI[1] CRCINI[0] JCMOD     DSP REDU[2] REDU[1] REDU[0] JCCMD BRST     JEND JRST JSRT JCQTN   QT3[1] QT3[0] QT2[1] QT2[0] QT1[1] QT1[0] JCHTN   HTA3 HTD3 HTA2 HTD2 HTA1 HTD1 JCDRIU DRIU[7] DRIU[6] DRIU[5] DRIU[4] DRIU[3] DRIU[2] DRIU[1] DRIU[0] JCDRID DRID[7] DRID[6] DRID[5] DRID[4] DRID[3] DRID[2] DRID[1] DRID[0] JCVSZU VSZU[7] VSZU[6] VSZU[5] VSZU[4] VSZU[3] VSZU[2] VSZU[1] VSZU[0] JCVSZD VSZD[7] VSZD[6] VSZD[5] VSZD[4] VSZD[3] VSZD[2] VSZD[1] VSZD[0] JCHSZU HSZU[7] HSZU[6] HSZU[5] HSZU[4] HSZU[3] HSZU[2] HSZU[1] HSZU[0] JCHSZD HSZD[7] HSZD[6] HSZD[5] HSZD[4] HSZD[3] HSZD[2] HSZD[1] HSZD[0] DOCMCRCIR JPEG codec unit JCDTCU DCU[7] DCU[6] DCU[5] DCU[4] DCU[3] DCU[2] DCU[1] DCU[0] JCDTCM DCM[7] DCM[6] DCM[5] DCM[4] DCM[3] DCM[2] DCM[1] DCM[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2941 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 JPEG codec JCDTCD DCD[7] DCD[6] DCD[5] DCD[4] DCD[3] DCD[2] DCD[1] DCD[0] JINTE0 INT7 INT6 INT5  INT3    JINTS0  INS6 INS5  INS3    JCDERR     ERR[3] ERR[2] ERR[1] ERR[0] JCRST        RST JIFECNT                      JOUTSWAP JOUTSWAP JOUTSWAP [2] [1] [0] unit JIFESA JIFESOFST JIFEDA JIFESLC Page 2942 of 3092  DINRINI DINRCMD DINLC  DINSWAP[2] DINSWAP[1] DINSWAP[0] ESA[31] ESA[30] ESA[29] ESA[28] ESA[27] ESA[26] ESA[25] ESA[24] ESA[23] ESA[22] ESA[21] ESA[20] ESA[19] ESA[18] ESA[17] ESA[16] ESA[15] ESA[14] ESA[13] ESA[12] ESA[11] ESA[10] ESA[9] ESA[8] ESA[7] ESA[6] ESA[5] ESA[4] ESA[3] ESA[2] ESA[1] ESA[0]                  ESMW[14] ESMW[13] ESMW[12] ESMW[11] ESMW[10] ESMW[9] ESMW[8] ESMW[7] ESMW[6] ESMW[5] ESMW[4] ESMW[3] ESMW[2] ESMW[1] ESMW[0] EDA[31] EDA[30] EDA[29] EDA[28] EDA[27] EDA[26] EDA[25] EDA[24] EDA[23] EDA[22] EDA[21] EDA[20] EDA[19] EDA[18] EDA[17] EDA[16] EDA[15] EDA[14] EDA[13] EDA[12] EDA[11] EDA[10] EDA[9] EDA[8] EDA[7] EDA[6] EDA[5] EDA[4] EDA[3] EDA[2] EDA[1] EDA[0]                 LINES[15] LINES[14] LINES[13] LINES[12] LINES[11] LINES[10] LINES[9] LINES[8] LINES[7] LINES[6] LINES[5] LINES[4] LINES[3] LINES[2] LINES[1] LINES[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 JPEG codec JIFDCNT   VINTER[1] VINTER[0] HINTER[1] HINTER[0] OPF[1] OPF[0]          JINRINI JINRCMD JINC  JINSWAP[2] JINSWAP[1] JINSWAP[0]  DOUTRINI DOUTRCMD DOUTLC  unit JIFDSA JIFDDOFST JIFDDA JIFDSDC JIFDDLC JIFDADT DOUTSWAP DOUTSWAP DOUTSWAP[0 [2] [1] ] DSA[31] DSA[30] DSA[29] DSA[28] DSA[27] DSA[26] DSA[25] DSA[24] DSA[23] DSA[22] DSA[21] DSA[20] DSA[19] DSA[18] DSA[17] DSA[16] DSA[15] DSA[14] DSA[13] DSA[12] DSA[11] DSA[10] DSA[9] DSA[8] DSA[7] DSA[6] DSA[5] DSA[4] DSA[3] DSA[2] DSA[1] DSA[0]                  DDMW[14] DDMW[13] DDMW[12] DDMW[11] DDMW[10] DDMW[9] DDMW[8] DDMW[7] DDMW[6] DDMW[5] DDMW[4] DDMW[3] DDMW[2] DDMW[1] DDMW[0] DDA[31] DDA[30] DDA[29] DDA[28] DDA[27] DDA[26] DDA[25] DDA[24] DDA[23] DDA[22] DDA[21] DDA[20] DDA[19] DDA[18] DDA[17] DDA[16] DDA[15] DDA[14] DDA[13] DDA[12] DDA[11] DDA[10] DDA[9] DDA[8] DDA[7] DDA[6] DDA[5] DDA[4] DDA[3] DDA[2] DDA[1] DDA[0]                 JDATAS[15] JDATAS[14] JDATAS[13] JDATAS[12] JDATAS[11] JDATAS[10] JDATAS[9] JDATAS[8] JDATAS[7] JDATAS[6] JDATAS[5] JDATAS[4] JDATAS[3] JDATAS[2] JDATAS[1] JDATAS[0]                 LINES[15] LINES[14] LINES[13] LINES[12] LINES[11] LINES[10] LINES[9] LINES[8] LINES[7] LINES[6] LINES[5] LINES[4] LINES[3] LINES[2] LINES[1] LINES[0]                         ALPHA[7] ALPHA[6] ALPHA[5] ALPHA[4] ALPHA[3] ALPHA[2] ALPHA[1] ALPHA[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2943 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 JPEG codec JINTE1                          CBTEN DINLEN   DBTEN JINEN DOUTLEN                          CBTF DINLF   DBTF JINF DOUTLF       IED IEN       IFTRG[1] IFTRG[0]      OCH OED OEN       OFTRG[1] OFTRG[0]   CEEN SRCEN UDEN OVEN FL CL IFS[3] IFS[2] IFS[1] IFS[0]  OFS[2] OFS[1] OFS[0] OFDN[4] OFDN[3] OFDN[2] OFDN[1] OFDN[0] IFDN[3] IFDN[2] IFDN[1] IFDN[0]  CEF FLF UDF OVF IINT OINT unit JINTS1 Sampling rate SRCID_0 converter SRCOD_0 SRCIDCTRL _0 SRCODCTRL_ 0 SRCCTRL_0 SRCSTAT_0 SRCID_1 SRCOD_1 Page 2944 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0       IED IEN       IFTRG[1] IFTRG[0]      OCH OED OEN       OFTRG[1] OFTRG[0]   CEEN SRCEN UDEN OVEN FL CL IFS[3] IFS[2] IFS[1] IFS[0]  OFS[2] OFS[1] OFS[0] OFDN[4] OFDN[3] OFDN[2] OFDN[1] OFDN[0] IFDN[3] IFDN[2] IFDN[1] IFDN[0]  CEF FLF UDF OVF IINT OINT       IED IEN       IFTRG[1] IFTRG[0]      OCH OED OEN       OFTRG[1] OFTRG[0]   CEEN SRCEN UDEN OVEN FL CL IFS[3] IFS[2] IFS[1] IFS[0]  OFS[2] OFS[1] OFS[0] OFDN[4] OFDN[3] OFDN[2] OFDN[1] OFDN[0] IFDN[3] IFDN[2] IFDN[1] IFDN[0]  CEF FLF UDF OVF IINT OINT SGCR1_0 SGST STPM  SGCK[1] SGCK[0] DPF[2] DPF[1] DPF[0] SGCSR_0 SGIE SGDEF       SGCR2_0 SGEND TCHG       SGLR_0 LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] SGTFR_0  TONE[6] TONE[5] TONE[4] TONE[3] TONE[2] TONE[1] TONE[0] SGSFR_0 SFS[7] SFS[6] SFS[5] SFS[4] SFS[3] SFS[2] SFS[1] SFS[0] SGCR1_1 SGST STPM  SGCK[1] SGCK[0] DPF[2] DPF[1] DPF[0] SGCSR_1 SGIE SGDEF       Sampling rate SRCIDCTRL converter Section 51 List of Registers _1 SRCODCTRL_ 1 SRCCTRL_1 SRCSTAT_1 SRCID_2 SRCOD_2 SRCIDCTRL _2 SRCODCTRL_ 2 SRCCTRL_2 SRCSTAT_2 Sound generator R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2945 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Sound SGCR2_1 SGEND TCHG SGLR_1 LD[7] SGTFR_1 generator MMC host Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0       LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0]  TONE[6] TONE[5] TONE[4] TONE[3] TONE[2] TONE[1] TONE[0] SGSFR_1 SFS[7] SFS[6] SFS[5] SFS[4] SFS[3] SFS[2] SFS[1] SFS[0] SGCR1_2 SGST STPM  SGCK[1] SGCK[0] DPF[2] DPF[1] DPF[0] SGCSR_2 SGIE SGDEF       SGCR2_2 SGEND TCHG       SGLR_2 LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] SGTFR_2  TONE[6] TONE[5] TONE[4] TONE[3] TONE[2] TONE[1] TONE[0] SGSFR_2 SFS[7] SFS[6] SFS[5] SFS[4] SFS[3] SFS[2] SFS[1] SFS[0] SGCR1_3 SGST STPM  SGCK[1] SGCK[0] DPF[2] DPF[1] DPF[0] SGCSR_3 SGIE SGDEF       SGCR2_3 SGEND TCHG       SGLR_3 LD[7] LD[6] LD[5] LD[4] LD[3] LD[2] LD[1] LD[0] SGTFR_3  TONE[6] TONE[5] TONE[4] TONE[3] TONE[2] TONE[1] TONE[0] SGSFR_3 SFS[7] SFS[6] SFS[5] SFS[4] SFS[3] SFS[2] SFS[1] SFS[0] CE_CMD_SET   CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0] RTYP[1] RTYP[0] RBSY  WDAT DWEN CMLTE CMD12EN RIDXC[1] RIDXC[0] RCRC7C[1] RCRC7C[0]  CRC16C  CRCSTE TBIT OPDM   SBIT  DATW[1] DATW[0] ARG[31] ARG[30] ARG[29] ARG[28] ARG[27] ARG[26] ARG[25] ARG[24] ARG[23] ARG[22] ARG[21] ARG[20] ARG[19] ARG[18] ARG[17] ARG[16] interface CE_ARG CE_ARG_ CMD12 CE_CMD_ CTRL Page 2946 of 3092 ARG[15] ARG[14] ARG[13] ARG[12] ARG[11] ARG[10] ARG[9] ARG[8] ARG[7] ARG[6] ARG[5] ARG[4] ARG[3] ARG[2] ARG[1] ARG[0] C12ARG[31] C12ARG[30] C12ARG[29] C12ARG[28] C12ARG[27] C12ARG[26] C12ARG[25] C12ARG[24] C12ARG[23] C12ARG[22] C12ARG[21] C12ARG[20] C12ARG[19] C12ARG[18] C12ARG[17] C12ARG[16] C12ARG[15] C12ARG[14] C12ARG[13] C12ARG[12] C12ARG[11] C12ARG[10] C12ARG[9] C12ARG[8] C12ARG[7] C12ARG[6] C12ARG[5] C12ARG[4] C12ARG[3] C12ARG[2] C12ARG[1] C12ARG[0]                                BREAK R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 MMC host CE_BLOCK_S BLKCNT[15] BLKCNT[14] BLKCNT[13] BLKCNT[12] BLKCNT[11] BLKCNT[10] BLKCNT[9] BLKCNT[8] interface ET BLKCNT[7] BLKCNT[6] BLKCNT[5] BLKCNT[4] BLKCNT[3] BLKCNT[2] BLKCNT[1] BLKCNT[0] BLKSIZ[15] BLKSIZ[14] BLKSIZ[13] BLKSIZ[12] BLKSIZ[11] BLKSIZ[10] BLKSIZ[9] BLKSIZ[8] BLKSIZ[7] BLKSIZ[6] BLKSIZ[5] BLKSIZ[4] BLKSIZ[3] BLKSIZ[2] BLKSIZ[1] BLKSIZ[0]        CLKEN     CLKDIV[3] CLKDIV[2] CLKDIV[1] CLKDIV[0] CE_CLK_ CTRL CE_BUF_ACC CE_RESP3 CE_RESP2 CE_RESP1 CE_RESP0 CE_RESP_ CMD12   SRSPTO[1] SRSPTO[0] SRBSYTO[3] SRBSYTO[2] SRBSYTO[1] SRBSYTO[0] SRWDTO[3] SRWDTO[2] SRWDTO[1] SRWDTO[0]           DMAWEN DMAREN       BUSW ATYP                 RSP[127] RSP[126] RSP[125] RSP[124] RSP[123] RSP[122] RSP[121] RSP[120] RSP[119] RSP[118] RSP[117] RSP[116] RSP[115] RSP[114] RSP[113] RSP[112] RSP[111] RSP[110] RSP[109] RSP[108] RSP[107] RSP[106] RSP[105] RSP[104] RSP[103] RSP[102] RSP[101] RSP[100] RSP[99] RSP[98] RSP[97] RSP[96] RSP[95] RSP[94] RSP[93] RSP[92] RSP[91] RSP[90] RSP[89] RSP[88] RSP[87] RSP[86] RSP[85] RSP[84] RSP[83] RSP[82] RSP[81] RSP[80] RSP[79] RSP[78] RSP[77] RSP[76] RSP[75] RSP[74] RSP[73] RSP[72] RSP[71] RSP[70] RSP[69] RSP[68] RSP[67] RSP[66] RSP[65] RSP[64] RSP[63] RSP[62] RSP[61] RSP[60] RSP[59] RSP[58] RSP[57] RSP[56] RSP[55] RSP[54] RSP[53] RSP[52] RSP[51] RSP[50] RSP[49] RSP[48] RSP[47] RSP[46] RSP[45] RSP[44] RSP[43] RSP[42] RSP[41] RSP[40] RSP[39] RSP[38] RSP[37] RSP[36] RSP[35] RSP[34] RSP[33] RSP[32] RSP[31] RSP[30] RSP[29] RSP[28] RSP[27] RSP[26] RSP[25] RSP[24] RSP[23] RSP[22] RSP[21] RSP[20] RSP[19] RSP[18] RSP[17] RSP[16] RSP[15] RSP[14] RSP[13] RSP[12] RSP[11] RSP[10] RSP[9] RSP[8] RSP[7] RSP[6] RSP[5] RSP[4] RSP[3] RSP[2] RSP[1] RSP[0] RSP12[31] RSP12[30] RSP12[29] RSP12[28] RSP12[27] RSP12[26] RSP12[25] RSP12[24] RSP12[23] RSP12[22] RSP12[21] RSP12[20] RSP12[19] RSP12[18] RSP12[17] RSP12[16] RSP12[15] RSP12[14] RSP12[13] RSP12[12] RSP12[11] RSP12[10] RSP12[9] RSP12[8] RSP12[7] RSP12[6] RSP12[5] RSP12[4] RSP12[3] RSP12[2] RSP12[1] RSP12[0] R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2947 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 MMC host CE_DATA DATA[31] DATA[30] DATA[29] DATA[28] DATA[27] DATA[26] DATA[25] DATA[24] DATA[23] DATA[22] DATA[21] DATA[20] DATA[19] DATA[18] DATA[17] DATA[16] DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]      CMD12DRE CMD12RBE CMD12CRE DTRANE BUFRE BUFWEN BUFREN   RBSYE CRSPE CMDVIO BUFVIO   WDATERR RDATERR RIDXERR RSPERR    CRCSTO WDATTO RDATTO RBSYTO RSPTO      MCMD12DRE MCMD12RBE MCMD12CRE MDTRANE MBUFRE MBUFWEN MBUFREN   MRBSYE MCRSPE MCMDVIO MBUFVIO   MWDATERR MRDATERR MRIDXERR MRSPERR    MCRCSTO MWDATTO MRDATTO MRBSYTO MRSPTO CMDSEQ CMDSIG RSPIDX[5] RSPIDX[4] RSPIDX[3] RSPIDX[2] RSPIDX[1] RSPIDX[0] DATSIG[7] DATSIG[6] DATSIG[5] DATSIG[4] DATSIG[3] DATSIG[2] DATSIG[1] DATSIG[0] RCVBLK[15] RCVBLK[14] RCVBLK[13] RCVBLK[12] RCVBLK[11] RCVBLK[10] RCVBLK[9] RCVBLK[8] RCVBLK[7] RCVBLK[6] RCVBLK[5] RCVBLK[4] RCVBLK[3] RCVBLK[2] RCVBLK[1] RCVBLK[0] CRCSTE CRC16E AC12CRCE RSPCRC7E CRCSTEBE RDATEBE AC12REBE RSPEBE AC12IDXE RSPIDXE    CRCST[2] CRCST[1] CRCST[0]  STRDATTO DATBSYTO CRCSTTO AC12BSYTO RSPBSYTO AC12RSPTO STRSPTO                                        DMASEL                  CDSIG CDRISE CDFALL       MCDRISE MCDFALL                 CLKMAIN                    interface CE_INT CE_INT_EN CE_HOST_ STS1 CE_HOST_ STS2 CE_DMA_ MODE CE_DETECT CE_ADD_ MODE Page 2948 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 MMC host CE_VERSION SWRST    Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0             VERSION[15] VERSION[14] VERSION[13] VERSION[12] VERSION[11] VERSION[10] VERSION[9] VERSION[8] VERSION[7] VERSION[6] VERSION[5] VERSION[4] VERSION[3] VERSION[2] VERSION[1] VERSION[0] PWCR_1   IE CMF CST CKS2 CKS1 CKS0 PWPR_1 OPS1H OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A interface Motor control PWM timer PWCYR_1 PWBFR_1A PWBFR_1C PWBFR_1E PWCY15 PWCY14 PWCY13 PWCY12 PWCY11 PWCY10 PWCY9 PWCY8 PWCY7 PWCY6 PWCY5 PWCY4 PWCY3 PWCY2 PWCY1 PWCY0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 PWCR_2   IE CMF CST CKS2 CKS1 CKS0 PWPR_2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A PWCYR_2 PWCY15 PWCY14 PWCY13 PWCY12 PWCY11 PWCY10 PWCY9 PWCY8 PWCY7 PWCY6 PWCY5 PWCY4 PWCY3 PWCY2 PWCY1 PWCY0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 PWBFR_1G PWBFR_2A PWBFR_2C PWBFR_2E PWBFR_2G PWBTCR    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0    OTS   DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 BTC2G BTC2E BTC2C BTC2A BTC1G BTC1E BTC1C BTC1A         R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2949 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 General PAIOR0        PA1IOR        PA0IOR        PA1DR        PA0DR               PA1PR PA0PR purpose I/O ports PADR0 PAPR0 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0 PBIOR1 PBIOR0 PBDR1 PBDR0 PBPR1 PBPR0 Page 2950 of 3092      PB22MD2 PB22MD1 PB22MD0   PB21MD1 PB21MD0  PB20MD2 PB20MD1 PB20MD0  PB19MD2 PB19MD1 PB19MD0  PB18MD2 PB18MD1 PB18MD0  PB17MD2 PB17MD1 PB17MD0  PB16MD2 PB16MD1 PB16MD0  PB15MD2 PB15MD1 PB15MD0  PB14MD2 PB14MD1 PB14MD0  PB13MD2 PB13MD1 PB13MD0   PB12MD1 PB12MD0   PB11MD1 PB11MD0   PB10MD1 PB10MD0   PB9MD1 PB9MD0   PB8MD1 PB8MD0   PB7MD1 PB7MD0   PB6MD1 PB6MD0   PB5MD1 PB5MD0   PB4MD1 PB4MD0   PB3MD1 PB3MD0   PB2MD1 PB2MD0   PB1MD1 PB1MD0              PB22IOR PB21IOR PB20IOR PB19IOR PB18IOR PB17IOR PB16IOR PB15IOR PB14IOR PB13IOR PB12IOR PB11IOR PB10IOR PB9IOR PB8IOR PB7IOR PB6IOR PB5IOR PB4IOR PB3IOR PB2IOR PB1IOR           PB22DR PB21DR PB20DR PB19DR PB18DR PB17DR PB16DR PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR           PB22PR PB21PR PB20PR PB19PR PB18PR PB17PR PB16PR PB15PR PB14PR PB13PR PB12PR PB11PR PB10PR PB9PR PB8PR PB7PR PB6PR PB5PR PB4PR PB3PR PB2PR PB1PR  R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 General PCCR2              PC8MD2 PC8MD1 PC8MD0  PC7MD2 PC7MD1 PC7MD0  PC6MD2 PC6MD1 PC6MD0  PC5MD2 PC5MD1 PC5MD0   PC4MD1 PC4MD0   PC3MD1 PC3MD0   PC2MD1 PC2MD0    PC1MD0    PC0MD0 purpose I/O ports PCCR1 PCCR0 PCIOR0 PCDR0 PCPR0 PDCR3 PDCR2 PDCR1 PDCR0 PDIOR0 PDDR0 PDPR0 PECR1 PECR0 PEIOR0        PC8IOR PC7IOR PC6IOR PC5IOR PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR        PC8DR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR        PC8PR PC7PR PC6PR PC5PR PC4PR PC3PR PC2PR PC1PR PC0PR   PD15MD1 PD15MD0   PD14MD1 PD14MD0   PD13MD1 PD13MD0   PD12MD1 PD12MD0   PD11MD1 PD11MD0   PD10MD1 PD10MD0   PD9MD1 PD9MD0   PD8MD1 PD8MD0   PD7MD1 PD7MD0   PD6MD1 PD6MD0   PD5MD1 PD5MD0   PD4MD1 PD4MD0   PD3MD1 PD3MD0   PD2MD1 PD2MD0   PD1MD1 PD1MD0   PD0MD1 PD0MD0 PD15IOR PD14IOR PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR PD15DR PD14DR PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PD15PR PD14PR PD13PR PD12PR PD11PR PD10PR PD9PR PD8PR PD7PR PD6PR PD5PR PD4PR PD3PR PD2PR PD1PR PD0PR   PE7MD1 PE7MD0   PE6MD1 PE6MD0   PE5MD1 PE5MD0   PE4MD1 PE4MD0  PE3MD2 PE3MD1 PE3MD0  PE2MD2 PE2MD1 PE2MD0  PE1MD2 PE1MD1 PE1MD0   PE0MD1 PE0MD0         PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2951 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 General PEDR0         PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR         PE7PR PE6PR PE5PR PE4PR PE3PR PE2PR PE1PR PE0PR  PF23MD2 PF23MD1 PF23MD0  PF22MD2 PF22MD1 PF22MD0  PF21MD2 PF21MD1 PF21MD0  PF20MD2 PF20MD1 PF20MD0 purpose I/O ports PEPR0 PFCR6 PFCR5 PFCR4 PFCR3 PFCR2 PFCR1 PFCR0 PFIOR1 PFIOR0 PFDR1 PFDR0 PFPR1 PFPR0 PGCR6 Page 2952 of 3092  PF19MD2 PF19MD1 PF19MD0  PF18MD2 PF18MD1 PF18MD0  PF17MD2 PF17MD1 PF17MD0  PF16MD2 PF16MD1 PF16MD0              PF15MD2 PF15MD1 PF15MD0      PF14MD2 PF14MD1 PF14MD0  PF13MD2 PF13MD1 PF13MD0  PF12MD2 PF12MD1 PF12MD0  PF11MD2 PF11MD1 PF11MD0  PF10MD2 PF10MD1 PF10MD0  PF9MD2 PF9MD1 PF9MD0  PF8MD2 PF8MD1 PF8MD0  PF7MD2 PF7MD1 PF7MD0  PF6MD2 PF6MD1 PF6MD0  PF5MD2 PF5MD1 PF5MD0  PF4MD2 PF4MD1 PF4MD0  PF3MD2 PF3MD1 PF3MD0  PF2MD2 PF2MD1 PF2MD0  PF1MD2 PF1MD1 PF1MD0  PF0MD2 PF0MD1 PF0MD0         PF23IOR PF22IOR PF21IOR PF20IOR PF19IOR PF18IOR PF17IOR PF16IOR PF15IOR PF14IOR PF13IOR PF12IOR PF11IOR PF10IOR PF9IOR PF8IOR PF7IOR PF6IOR PF5IOR PF4IOR PF3IOR PF2IOR PF1IOR PF0IOR         PF23DR PF22DR PF21DR PF20DR PF19DR PF18DR PF17DR PF16DR PF15DR PF14DR PF13DR PF12DR PF11DR PF10DR PF9DR PF8DR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR         PF23PR PF22PR PF21PR PF20PR PF19PR PF18PR PF17PR PF16PR PF15PR PF14PR PF13PR PF12PR PF11PR PF10PR PF9PR PF8PR PF7PR PF6PR PF5PR PF4PR PF3PR PF2PR PF1PR PF0PR   PG27MD1 PG27MD0   PG26MD1 PG26MD0   PG25MD1 PG25MD0   PG24MD1 PG24MD0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 General PGCR5  PG23MD2 PG23MD1 PG23MD0  PG22MD2 PG22MD1 PG22MD0  PG21MD2 PG21MD1 PG21MD0  PG20MD2 PG20MD1 PG20MD0  PG19MD2 PG19MD1 PG19MD0  PG18MD2 PG18MD1 PG18MD0   PG17MD1 PG17MD0   PG16MD1 PG16MD0   PG15MD1 PG15MD0   PG14MD1 PG14MD0   PG13MD1 PG13MD0   PG12MD1 PG12MD0 purpose I/O ports PGCR4 PGCR3 PGCR2 PGCR1 PGCR0 PGIOR1 PGIOR0 PGDR1 PGDR0 PGPR1 PGPR0 PHCR1 PHCR0 PHPR0 PJCR7  PG11MD2 PG11MD1 PG11MD0  PG10MD2 PG10MD1 PG10MD0  PG9MD2 PG9MD1 PG9MD0  PG8MD2 PG8MD1 PG8MD0  PG7MD2 PG7MD1 PG7MD0  PG6MD2 PG6MD1 PG6MD0  PG5MD2 PG5MD1 PG5MD0  PG4MD2 PG4MD1 PG4MD0  PG3MD2 PG3MD1 PG3MD0  PG2MD2 PG2MD1 PG2MD0  PG1MD2 PG1MD1 PG1MD0  PG0MD2 PG0MD1 PG0MD0     PG27IOR PG26IOR PG25IOR PG24IOR PG23IOR PG22IOR PG21IOR PG20IOR PG19IOR PG18IOR PG17IOR PG16IOR PG15IOR PG14IOR PG13IOR PG12IOR PG11IOR PG10IOR PG9IOR PG8IOR PG7IOR PG6IOR PG5IOR PG4IOR PG3IOR PG2IOR PG1IOR PG0IOR     PG27DR PG26DR PG25DR PG24DR PG23DR PG22DR PG21DR PG20DR PG19DR PG18DR PG17DR PG16DR PG15DR PG14DR PG13DR PG12DR PG11DR PG10DR PG9DR PG8DR PG7DR PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR     PG27PR PG26PR PG25PR PG24PR PG23PR PG22PR PG21PR PG20PR PG19PR PG18PR PG17PR PG16PR PG15PR PG14PR PG13PR PG12PR PG11PR PG10PR PG9PR PG8PR PG7PR PG6PR PG5PR PG4PR PG3PR PG2PR PG1PR PG0PR   PH7MD1 PH7MD0   PH6MD1 PH6MD0   PH5MD1 PH5MD0   PH4MD1 PH4MD0   PH3MD1 PH3MD0   PH2MD1 PH2MD0   PH1MD1 PH1MD0   PH0MD1 PH0MD0         PH7PR PH6PR PH5PR PH4PR PH3PR PH2PR PH1PR PH0PR    PJ31MD  PJ30MD2 PJ30MD1 PJ30MD0  PJ29MD2 PJ29MD1 PJ29MD0  PJ28MD2 PJ28MD1 PJ28MD0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2953 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 General PJCR6  PJ27MD2 PJ27MD1 PJ27MD0  PJ26MD2 PJ26MD1 PJ26MD0  PJ25MD2 PJ25MD1 PJ25MD0  PJ24MD2 PJ24MD1 PJ24MD0  PJ23MD2 PJ23MD1 PJ23MD0  PJ22MD2 PJ22MD1 PJ22MD0  PJ21MD2 PJ21MD1 PJ21MD0  PJ20MD2 PJ20MD1 PJ20MD0  PJ19MD2 PJ19MD1 PJ19MD0  PJ18MD2 PJ18MD1 PJ18MD0  PJ17MD2 PJ17MD1 PJ17MD0  PJ16MD2 PJ16MD1 PJ16MD0 purpose I/O ports PJCR5 PJCR4 PJCR3 PJCR2 PJCR1 PJCR0 PJIOR1 PJIOR0 PJDR1 PJDR0 PJPR1 PJ15MD1 PJ15MD0  PJ14MD2 PJ14MD1 PJ14MD0 PJ13MD1 PJ13MD0  PJ12MD2 PJ12MD1 PJ12MD0  PJ11MD2 PJ11MD1 PJ11MD0  PJ10MD2 PJ10MD1 PJ10MD0  PJ9MD2 PJ9MD1 PJ9MD0  PJ8MD2 PJ8MD1 PJ8MD0  PJ7MD2 PJ7MD1 PJ7MD0  PJ6MD2 PJ6MD1 PJ6MD0  PJ5MD2 PJ5MD1 PJ5MD0  PJ4MD2 PJ4MD1 PJ4MD0  PJ3MD2 PJ3MD1 PJ3MD0  PJ2MD2 PJ2MD1 PJ2MD0  PJ1MD2 PJ1MD1 PJ1MD0  PJ0MD2 PJ0MD1 PJ0MD0 PJ31IOR PJ30IOR PJ29IOR PJ28IOR PJ27IOR PJ26IOR PJ25IOR PJ24IOR PJ23IOR PJ22IOR PJ21IOR PJ20IOR PJ19IOR PJ18IOR PJ17IOR PJ16IOR PJ15IOR PJ14IOR PJ13IOR PJ12IOR PJ11IOR PJ10IOR PJ9IOR PJ8IOR PJ7IOR PJ6IOR PJ5IOR PJ4IOR PJ3IOR PJ2IOR PJ1IOR PJ0IOR PJ31DR PJ30DR PJ29DR PJ28DR PJ27DR PJ26DR PJ25DR PJ24DR PJ23DR PJ22DR PJ21DR PJ20DR PJ19DR PJ18DR PJ17DR PJ16DR PJ15DR PJ14DR PJ13DR PJ12DR PJ11DR PJ10DR PJ9DR PJ8DR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR PJ31PR PJ30PR PJ29PR PJ28PR PJ27PR PJ26PR PJ25PR PJ24PR PJ22PR PJ21PR PJ20PR PJ19PR PJ18PR PJ17PR PJ16PR PJ15PR PJ14PR PJ13PR PJ12PR PJ11PR PJ10PR PJ9PR PJ8PR PJ7PR PJ6PR PJ5PR PJ4PR PJ3PR PJ2PR PJ1PR PJ0PR           SSI5NCE SSI4NCE SSI3NCE SSI2NCE SSI1NCE SSI0NCE STBCR1 STBY DEEP       STBCR2 MSTP10  MSTP8 MSTP7     STBCR3 HIZ MSTP36 MSTP35   MSTP32  MSTP30 STBCR4 MSTP47 MSTP46 MSTP45 MSTP44 MSTP43 MSTP42 MSTP41 MSTP40 SNCR modes PJ15MD2 PJ13MD2 PJ23PR PJPR0 Power-down   Page 2954 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Module Register Name Abbreviation Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 Power-down STBCR5 MSTP57 MSTP56 MSTP55 MSTP54 MSTP53 MSTP52 MSTP51 MSTP50 STBCR6 MSTP67 MSTP66 MSTP65 MSTP64 MSTP63 MSTP62 MSTP61 MSTP60 STBCR7 MSTP77 MSTP76 MSTP75  MSTP73 MSTP72  MSTP70 STBCR8 MSTP87 MSTP86 MSTP85 MSTP84  MSTP82 MSTP81  STBCR9 MSTP97 MSTP96 MSTP95 MSTP94 MSTP93 MSTP92 MSTP91 MSTP90 STBCR10 MSTP107 MSTP106 MSTP105  MSTP103 MSTP102 MSTP101 MSTP100 SWRSTCR1 AXTALE SSIF5SRST SSIF4SRST IEBSRST SSIF3SRST SSIF2SRST SSIF1SRST SSIF0SRST SWRSTCR2    JCUSRST RGPVGSRST   VDC4SRST SYSCR1     RAME3 RAME2 RAME1 RAME0 SYSCR2     RAMWE3 RAMWE2 RAMWE1 RAMWE0 SYSCR3   VRAME5 VRAME4 VRAME3 VRAME2 VRAME1 VRAME0 SYSCR4   VRAMWE5 VRAMWE4 VRAMWE3 VRAMWE2 VRAMWE1 VRAMWE0 SYSCR5     RRAMWE3 RRAMWE2 RRAMWE1 RRAMWE0 RRAMKP     RRAMKP3 RRAMKP2 RRAMKP1 RRAMKP0 DSCTR EBUSKEEPE RAMBOOT       DSSSR  PJ23 PJ22 PJ21 PJ20 PG3 PG2 NMI  RTCAR PF19 PF18 PF17 PF16 PC7 PC5  PJ23E PJ22E PJ21E PJ20E PG3E PG2E NMIE   PF19E PF18E PF17E PF16E PC7E PC5E IOKEEP PJ23F PJ22F PJ21F PJ20F PG3F PG2F NMIF  RTCARF PF19F PF18F PF17F PF16F PC7F PC5F XTALCTR        GAIN SDIR T1[7] T1[6] T1[5] T1[4] T1[3] T1[2] T1[1] T1[0]         modes DSESR DSFR User debugging interface Notes: 1. 2. 3. 4. When MCR15=0 When MCR15=1 In command access mode In sector access mode R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2955 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers 51.3 Register States in Each Operating Mode Module Name Clock pulse Register Power-On Manual Deep Software Module Abbreviation Reset Reset Standby Standby Standby Sleep FRQCR Initialized* Retained Initialized Retained  Retained IBNR Initialized Retained*2 Initialized Retained  Retained 1 generator Interrupt controller User break Other than above Initialized Retained Initialized Retained  Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained controller Cache Bus state controller Direct memory Initialized Retained  Retained 3 RTCSR Initialized Retained* Initialized Retained  Retained*3 RTCNT Initialized Retained*4 Initialized Retained  Retained*4 Other than above Initialized Retained Initialized Retained  Retained All registers Initialized Retained Initialized Retained Retained Retained*7 All registers Initialized Retained Initialized Retained Initialized Retained All registers Initialized Retained Initialized Initialized Retained Retained WRCSR Initialized*1 Retained Initialized Retained  Retained access controller Multi-function timer pulse unit 2 Compare match timer Watchdog timer Other than above Initialized Realtime clock Initialized 4 Initialized 4  Retained 4 Retained 4 R64CNT Retained* Retained* Retained* Retained* Retained Retained*4 RSECCNT Retained*4 Retained*4 Retained*4 Retained*4 Retained Retained*4 RMINCNT Retained*4 Retained*4 Retained*4 Retained*4 Retained Retained*4 RHRCNT Retained*4 Retained*4 Retained*4 Retained*4 Retained Retained*4 RWKCNT Retained*4 Retained*4 Retained*4 Retained*4 Retained Retained*4 RDAYCNT Retained*4 Retained*4 Retained*4 Retained*4 Retained Retained*4 RMONCNT Retained*4 Retained*4 Retained*4 Retained*4 Retained Retained*4 4 4 4 4 RYRCNT Retained* Retained* Retained* Retained* Retained Retained*4 RSECAR Retained Retained Retained Retained Retained Retained RMINAR Retained Retained Retained Retained Retained Retained RHRAR Retained Retained Retained Retained Retained Retained RWKAR Retained Retained Retained Retained Retained Retained Page 2956 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers Register Power-On Manual Deep Software Module Module Name Abbreviation Reset Reset Standby Standby Standby Sleep Realtime clock RDAYAR Retained Retained Retained Retained Retained Retained RMONAR Retained Retained Retained Retained Retained Retained RYRAR Retained Retained Retained Retained Retained Retained RCR1 Initialized Initialized Initialized Retained Retained Retained 5 RCR2 Initialized Initialized* Initialized Retained Retained Retained RCR3 Retained Retained Retained Retained Retained Retained RCR5 Retained Retained Retained Retained Retained Retained RFRH Retained Retained Retained Retained Retained Retained RFRL Retained Retained Retained Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained SPI multi I/O bus All registers Initialized Retained Initialized Retained Retained Retained Initialized Retained Initialized Retained*6 Retained*6 Retained Other than above Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained IEBusTM controller All registers Initialized Retained Initialized Retained Retained Retained Renesas SPDIF All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Initialized Initialized Retained Serial communication interface with FIFO Renesas serial peripheral interface Renesas quad serial peripheral interface controller I2C bus interface 3 Serial sound ICMR_0, 1, 2, 3 interface Serial I/O with FIFO Controller area network interface CD-ROM decoder A/D converter R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2957 of 3092 SH7268 Group, SH7269 Group Section 51 List of Registers Register Power-On Manual Deep Software Module Module Name Abbreviation Reset Reset Standby Standby Standby Sleep NAND flash All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained Image renderer All registers Initialized Retained Initialized Retained Retained Retained Display out All registers Initialized Retained Initialized Retained Retained Retained JPEG codec unit All registers Initialized Retained Initialized Retained Retained Retained Sampling rate All registers Initialized Retained Initialized Retained Retained Retained Sound generator All registers Initialized Retained Initialized Retained Retained Retained MMC host All registers Initialized Retained Initialized Retained Retained Retained All registers Initialized Retained Initialized Retained Retained Retained General purpose All registers Initialized Retained Initialized Retained  Retained Retained Retained  Retained  Retained memory controller USB 2.0 host/function module Digital video decoder Video display controller 4 comparison unit converter interface Motor control PWM timer I/O ports Power-down modes User debugging DSFR XTALCTR Initialized 10 Initialized* Retained Retained 9 Retained* 9 Retained* Other than above Initialized Retained Initialized Retained  Retained SDIR Retained Initialized Retained Retained Retained Retained interface*8 Notes: 1. Retains the previous value after an internal power-on reset by means of the watchdog timer. 2. The BN3 to BN0 bits are initialized. 3. Flag handling continues. 4. Counting up continues. 5. Bits RTCEN and START are retained. 6. Bits BC2 to BC0 are initialized. 7. Transfer operations can be continued. 8. Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller. Page 2958 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 51 List of Registers 9. Initialized when realtime clock is not using EXTAL. 10. Retains the previous value after an internal power-on reset by means of the watchdog timer or the user debugging interface reset. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2959 of 3092 Section 51 List of Registers Page 2960 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Section 52 Electrical Characteristics 52.1 Absolute Maximum Ratings Table 52.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage (I/O) PVCC 0.3 to 4.6 V Power supply voltage (Internal) VCC 0.3 to 1.7 V PLL power supply voltage PLLVCC 0.3 to 4.6 V Analog power supply voltage AVCC 0.3 to 4.6 V Analog reference voltage AVref 0.3 to AVCC 0.3 V USB transceiver analog power supply voltage (I/O) USBAPVCC 0.3 to 4.6 V USB transceiver digital power supply voltage (I/O) USBDPVCC 0.3 to 4.6 V USB transceiver analog power supply voltage (internal) USBAVCC 0.3 to 1.7 V USB transceiver digital power supply voltage (internal) USBDVCC 0.3 to 1.7 V USBUVCC 0.3 to 1.7 V A/D converter power supply voltage for video signal input VDAVCC 0.3 to 4.6 V Input voltage VBUS Vin 0.3 to 5.5 V Other input pins Vin 0.3- to 3.3-V power V supply (PVCC, PLLVCC, AVCC, USBAPVCC, USBDPVCC, VDAVCC) 0.3 Regular specifications Topr 20 to 85 Note: SH7269 (BGA) Group products do not have this pin. Note: SH7269 (BGA) Group products do not have this pin. Power supply for USB 480 MHz (internal) Note: SH7269 (BGA) Group products do not have this pin. Operating temperature Caution: 40 to 85 Wide-range specifications Storage temperature °C Tstg 55 to 125 °C Permanent damage to the LSI may result if absolute maximum ratings are exceeded. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2961 of 3092 Section 52 Electrical Characteristics 52.2 SH7268 Group, SH7269 Group Power-On/Power-Off Sequence The 1.2-V power supply (VCC, USBAVCC, USBDVCC, and USBUVCC) and 3.3-V power supply (PVCC, PLLVCC, AVCC, USBAPVCC, USBDPVCC, and VDAVCC) can be turned on and off in any order. When turning on the power, be sure to drive both the TRST and RES pins low; otherwise, the output pins and input/output pins output undefined levels, resulting in system malfunction. When turning off the power, drive the TRST and RES pins low if the undefined output may cause a problem. Page 2962 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.3 Section 52 Electrical Characteristics DC Characteristics  Conditions used to obtain DC characteristics (2) and (3) in table 52.2 other than current consumption VCC = USBDVCC = USBUVCC = 1.15 to 1.35 V, PVCC = USBDPVCC = 3.0 to 3.6 V, PLLVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAVCC = 1.15 to 1.35 V, USBAPVCC = 3.0 to 3.6 V, VDAVcc = 3.0 to 3.6 V, VSS = PLLVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS = USBAPVSS = USBUVSS = VDAVss = 0 V, Ta = 20 to 85 C (regular specifications), 40 to 85 C (wide-range specifications)  Conditions used to obtain DC characteristics (2) and (3) in table 52.2 for current consumption VCC = USBDVCC = USBUVCC = 1.25 V, PVCC = USBDPVCC = 3.3 V, PLLVCC = 3.3 V, AVCC = 3.3 V, USBAVCC = 1.25 V, USBAPVCC = 3.3 V, VDAVCC = 3.3 V, VSS = PLLVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS = USBAPVSS = USBUVSS = VDAVss = 0 V, Avref = 3.3 V, VBUS = 5.0 V Ta = 20 to 85 C (regular specifications), 40 to 85 C (wide-range specifications) I = 266.67 MHz, B = 133.33 MHz, P1 = 66.67 MHz, P0 = 33.33 MHz Note: SH7269 (BGA) Group products do not have pins USBDVCC, USBUVCC, USBDPVCC, PLLVSS, USBDVSS, USBAVSS, USBUVSS, USBDPVSS, and USBAPVSS. Table 52.2 DC Characteristics (1) [Common Items] Item Symbol Min. Typ. Max. Unit Power supply voltage PVCC 3.0 3.3 3.6 V VCC 1.15 1.25 1.35 V PLL power supply voltage PLLVCC 3.0 3.3 3.6 V Analog power supply voltage AVCC 3.0 3.3 3.6 V USB power supply voltage USBAPVCC 3.0 3.3 3.6 V Note: SH7269 (BGA) Group products do not have pins USBDPVcc, USBDVcc, and USBUVcc. USBDPVCC 1.15 1.25 1.35 V USBAVCC Test Conditions USBDVCC USBUVCC A/D converter power supply voltage for video signal input VDAVCC 3.0 3.3 3.6 V Input leakage current |Iin|   1.0 A All input pins R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Vin = 0.5 to PVCC – 0.5 V Page 2963 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Three-state leakage current Symbol All input/output |ISTI| pins, all output pins (except PE7 to PE0) (off state) PE7 to PE0 Input capacitance USB 2.0 host/function module pins* Cin all input/output pins, all input pins Min. Typ. Max. Unit Test Conditions   1.0 A Vin = 0.5 to PVCC – 0.5 V   10 A   20 pF   10 pF Note: * DP, DM, VBUS pins Table 52.2 DC Characteristics (2) [Current Consumption] SH7268/SH7269 (QFP) Item Power Supply Symbol Typ. Current consumption in normal operation VCC ICC 220 285 mA PLLVCC PLLICC 11 13 mA PVCC PICC* 92  mA AVCC AICC 1 4 mA During A/D conversion 1 3 A Waiting for A/D conversion Current consumption in sleep mode Page 2964 of 3092 Max. Unit Test Conditions AVref AIref 1 4 mA During A/D conversion, waiting for A/D conversion USBAVCC  USBDVCC  USBUVCC UICC 19 22 mA In USB highspeed operation USBAPVCC  USBDPVCC UPICC 44 47 mA In USB highspeed operation VBUS VICC 8.5 10 A VDAVCC VDAICC 7.5 8 mA VCC Isleep 170 240 mA For the other power supply, the current consumption is the same as in normal operation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Power Supply Symbol Typ. Max. Unit Current Ta  50 C consumption in software standby mode VCC  USBAVCC  USBDVCC  USBUVCC Isstby 7 65 mA PVCC  PLLVCC  USBAPVCC  USBDPVCC  VDAVCC PIsstby 4.5 6.5 mA Test Conditions For the other power supply, the current consumption is the same as in normal operation. Ta  50 C Vcc  USBAVCC  USBDVCC  USBUVCC Isstby 4 35 mA PVCC  PLLVCC  USBAPVCC  USBDPVCC  VDAVCC PIsstby 4.5 6.5 mA For the other power supply, the current consumption is the same as in normal operation. Current Ta  50 C consumption in deep standby mode VCC  USBAVCC  USBDVCC  USBUVCC Idstby 6 27 A RAM 0 Kbytes retained, RTC_X1 selected 8 40 A RAM 16 Kbytes retained, RTC_X1 selected 10 53 A RAM 32 Kbytes retained, RTC_X1 selected 14 80 A RAM 64 Kbytes retained, RTC_X1 selected 22 132 A RAM 128 Kbytes retained, RTC_X1 selected When the 13-MHz signal from EXTAL is selected, 5 and 6 µA are added to the "Typ." and "Max." values above, respectively. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2965 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Power Supply Symbol Typ. Max. Unit Test Conditions Current Ta  50 C consumption in deep standby mode PVCC  PLLVCC  AVCC  AVref  USBAPVCC  USBDPVCC  VDAVCC PIdstby 5.5 20 A RTC is not operating 9.5 24 A RTC_X1 selected 1  mA 13-MHz frequency from EXTAL selected, small gain* VBUS VICC 8.5 10 A VCC  USBAVCC  USBDVCC  USBUVCC Idstby 4 19 A RAM 0 Kbytes retained, RTC_X1 selected 5.5 29 A RAM 16 Kbytes retained, RTC_X1 selected 7 39 A RAM 32 Kbytes retained, RTC_X1 selected 10 58 A RAM 64 Kbytes retained, RTC_X1 selected 16 97 A RAM 128 Kbytes retained, RTC_X1 selected Current Ta  50 C consumption in deep standby mode When the 13-MHz signal from EXTAL is selected, 5 and 6 µA are added to the "Typ." and "Max." values above, respectively. Note: * PVCC  PLLVCC  AVCC  AVref  USBAPVCC  USBDPVCC  VDAVCC PIdstby VBUS VICC 5 16 A RTC is not operating 9 20 A RTC_X1 selected 1  mA 13-MHz frequency from EXTAL selected, small gain* 8.5 10 A Reference value. The actual operating current greatly depends on the system (such as slow rising/falling edges caused by IO load and toggle frequency). Be sure to determine the value using the actual system. Page 2966 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.2 DC Characteristics (3) [Current Consumption] SH7269 (BGA) Item Power Supply Symbol Typ. Max. Unit Test Conditions Current consumption in normal operation VCC ICC 220 285 mA USB is not operating In USB high-speed operation, 12 and 14 mA are added to the "Typ." and "Max." values above, respectively. PLLVCC PLLICC 11 13 mA PVCC PICC* 92  mA USB is not operating In USB high-speed operation, 42 mA is added to the "Typ." value above. AVCC Current consumption in sleep mode AICC 1 4 mA During A/D conversion 1 3 A Waiting for A/D conversion AVref AIref 1 4 mA During A/D conversion, waiting for A/D conversion USBAVCC UICC 7 8 mA In USB highspeed operation USBAPVCC UPICC 2 2.5 mA In USB highspeed operation VBUS VICC 8.5 10 A VDAVCC VDAICC 7.5 8 mA VCC Isleep 170 240 mA In USB high-speed operation, 12 and 14 mA are added to the "Typ." and "Max." values above, respectively. For the other power supply, the current consumption is the same as in normal operation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2967 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Power Supply Symbol Typ. Max. Unit Current Ta  50 C consumption in software standby mode VCC  USBAVCC Isstby 7 65 mA PVCC  PLLVCC  USBAPVCC  VDAVCC PIsstby 4.5 6.5 mA Test Conditions For the other power supply, the current consumption is the same as in normal operation. Ta  50 C VCC  USBAVCC Isstby 4 35 mA PVCC  PLLVCC  USBAPVCC  VDAVCC PIsstby 4.5 6.5 mA For the other power supply, the current consumption is the same as in normal operation. Current Ta  50 C consumption in deep standby mode VCC  USBAVCC Idstby 6 27 A RAM 0 Kbytes retained, RTC_X1 selected 8 40 A RAM 16 Kbytes retained, RTC_X1 selected 10 53 A RAM 32 Kbytes retained, RTC_X1 selected 14 80 A RAM 64 Kbytes retained, RTC_X1 selected 22 132 A RAM 128 Kbytes retained, RTC_X1 selected When the 13-MHz signal from EXTAL is selected, 5 and 6 µA are added to the "Typ." and "Max." values above, respectively. Page 2968 of 3092 PVCC  PLLVCC  AVCC  AVref  USBAPVCC  VDAVCC PIdstby VBUS VIcc 5.5 20 A RTC is not operating 9.5 24 A RTC_X1 selected 1  mA 13-MHz frequency from EXTAL selected, small gain* 8.5 10 A R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Power Supply Symbol Typ. Max. Unit Test Conditions Current Ta  50 C consumption in deep standby mode VCC  USBAVCC Idstby 4 19 A RAM 0 Kbytes retained, RTC_X1 selected 5.5 29 A RAM 16 Kbytes retained, RTC_X1 selected 7 39 A RAM 32 Kbytes retained, RTC_X1 selected 10 58 A RAM 64 Kbytes retained, RTC_X1 selected 16 97 A RAM 128 Kbytes retained, RTC_X1 selected When the 13-MHz signal from EXTAL is selected, 5 and 6 µA are added to the "Typ." and "Max." values above, respectively. Note: * PVCC  PLLVCC  AVCC  AVref  USBAPVCC  VDAVCC PIdstby VBUS VIcc 5 16 A RTC is not operating 9 20 A RTC_X1 selected 1  mA 13-MHz frequency from EXTAL selected, small gain* 8.5 10 A Reference value. The actual operating current greatly depends on the system (such as slow rising/falling edges caused by IO load and toggle frequency). Be sure to determine the value using the actual system. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2969 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.2 DC Characteristics (4) [Except I2C Bus Interface 3, and USB 2.0 Host/Function Module-Related Pins] Item Symbol Min. Typ. Max. Unit Input high voltage (except Schmitt pins) VIH 2.2  PVCC + 0.3 V Input low voltage (except Schmitt pins) 0.3  0.8 V Schmitt trigger input characteristics VIL VT VT + PVCC  0.75   V    0.5 V 0.2   V VT  VT +  Test Conditions Output high voltage VOH PVCC  0.5   V IOH = 2.0 mA Output low voltage VOL   0.4 V IOL = 2.0 mA Software standby VRAMS mode (high-speed onchip RAM and largecapacity on-chip RAM) 0.85   V Measured with VCC (= PLLVCC) as parameter Deep standby mode VRAMD (only the on-chip RAM for data retention) 1.15   V RAM standby voltage Table 52.2 DC Characteristics (5) [I2C Bus Interface 3-Related Pins*] Item Symbol Min. Typ. Max. Input high voltage VIH PVCC  0.7  PVCC + 0.3 V Input low voltage VIL 0.3  PVCC  0.3 V Schmitt trigger input characteristics VIH  VIL PVCC  0.05   V Output low voltage VOL  0.4 V Note: *  Unit Test Conditions IOL = 3.0 mA The PE7/SDA3/RxD7 to PE0/SCL0/TCLKA/LCD_EXTCLK pins are open-drain pins. Page 2970 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.2 DC Characteristics (6) [USB 2.0 Host/Function Module-Related Pins*] Symbol Min. Reference resistance RREF 5.6 k  1% 5.6 k  1% 5.6 k  1% Input high voltage (VBUS) VIH 4.02  5.25 V Input low voltage (VBUS) VIL 0.3  0.5 V Input high voltage (USB_X1) VIH PVCC  0.5  PVCC + 0.3 V Input low voltage (USB_X1) VIL 0.3  0.5 V Note: * Typ. Test Unit Conditions Item Max. REFRIN, VBUS, USB_X1, and USB_X2 pins Table 52.2 DC Characteristics (7) [USB 2.0 Host/Function Module-Related Pins* (LowSpeed, Full-Speed, and High-Speed Common Items)] Item Symbol Min. Typ. Max. Unit Test Conditions DP pull-up resistance (when function is selected) Rpu 0.900  1.575 k In idle mode 1.425  3.090 k In transmit/ receive mode 14.25  24.80 k DP and DM pull-down resistance Rpd (when host is selected) Note: * DP and DM pins R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2971 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.2 DC Characteristics (8) [USB 2.0 Host/Function Module-Related Pins* (LowSpeed and Full-Speed)] Item Test Unit Conditions Symbol Min. Typ. Max. Input high voltage VIH 2.0   V Input low voltage VIL   0.8 V Differential input sensitivity VDI 0.2   V Differential common mode range VCM 0.8  2.5 V Output high voltage VOH 2.8  3.6 V IOH = –200 A Output low voltage VOL 0.0  0.3 V IOL = 2 mA Output signal crossover voltage VCRS 1.3  2.0 V CL = 50 pF (full-speed) CL = 200 to 600 pF (low-speed) Note: * | (DP)  (DM) | DP and DM pins Table 52.2 DC Characteristics (9) [USB 2.0 Host/Function Module-Related Pins* (HighSpeed)] Item Symbol Min. Typ. Max. Unit Squelch detection threshold voltage (differential voltage) VHSSQ 100  150 mV Common mode voltage range VHSCM 50  500 mV Idle state VHSOI 10.0  10.0 mV Output high voltage VHSOH 360  440 mV Output low voltage VHSOL 10.0  10.0 mV Chirp J output voltage (difference) VCHIRPJ 700  1100 mV Chirp K output voltage (difference) VCHIRPK 900  500 mV Note: * Test Conditions DP and DM pins Page 2972 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.3 Permissible Output Currents Item Permissible output low current (per pin) PE7 to PE0 Symbol Min. Typ. IOL   Output pins other than above Max. Unit 10 mA 2 mA Permissible output low current (total) IOL   150 mA Permissible output high current (per pin) IOH   2 mA Permissible output high current (total) IOH   150 mA Caution: To protect the LSI's reliability, do not exceed the output current values in table 52.3. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2973 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed.  Conditions for AC characteristics VCC = USBDVCC = USBUVCC = 1.15 to 1.35 V, PVCC = USBDPVCC = 3.0 to 3.6 V, PLLVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAVCC = 1.15 to 1.35 V, USBAPVCC = 3.0 to 3.6 V, VDAVCC = 3.0 to 3.6 V, VSS = PLLVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS = USBAPVSS = USBUVSS = VDAVSS = 0 V, Ta = 20 to 85 C (regular specifications), 40 to 85 C (wide-range specifications) Note: SH7269 (BGA) Group products do not have the USBDVCC, USBUVCC, USBDPVCC, PLLVSS, USBDVSS, USBAVSS, USBUVSS, USBDPVSS, and USBAPVSS pins. Table 52.4 Operating Frequency Item Operating frequency 52.4.1 Symbol Min. Max. Unit f 50.00 266.67 MHz Internal bus clock (B) 50.00 133.33 MHz Peripheral clock 1 (P1) 50.00 66.67 MHz Peripheral clock 0 (P0) 25.00 33.33 MHz CPU clock (I) Remarks Clock Timing Table 52.5 Clock Timing Item Symbol Min. Max. EXTAL clock input frequency (when the clock is supplied to USB 2.0 host/function module) fEX 12MHz  100ppm Unit Figure 52.1 EXTAL clock input frequency (when the clock isn't supplied to USB 2.0 host/function module) 10.00 13.33 MHz EXTAL clock input cycle time (when the clock isn't tEXcyc supplied to USB 2.0 host/function module) 75.00 100.00 ns AUDIO_X1 clock input frequency (crystal resonator connected) fEX 10.00 50.00 MHz AUDIO_X1 clock input cycle time (crystal resonator connected) tEXcyc 20.00 100.00 ns Page 2974 of 3092 Figure R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Symbol Min. Max. Unit Figure AUDIO_X1, AUDIO_CLK clock input frequency (external clock input) fEX 1.00 50.00 MHz Figure 52.1 AUDIO_X1, AUDIO_CLK clock input cycle time (external clock input) tEXcyc 20.00 1000.00 ns USB_X1 clock input frequency (when the 12-MHz fEX clock is supplied to USB 2.0 host/function module) 12 MHz 100 ppm USB_X1 clock input frequency (when the 48-MHz clock is supplied to USB 2.0 host/function module and high-speed transfer function is used) 48 MHz 100 ppm USB_X1 clock input frequency (when the 48-MHz clock is supplied to USB 2.0 host/function module, high-speed transfer function is not used, and host controller function is used) 48 MHz 500 ppm USB_X1 clock input frequency (when the 48-MHz clock is supplied to USB 2.0 host/function module, high-speed transfer function is not used, and host controller function is not used) 48 MHz 2500 ppm VIDEO_X1 clock input frequency fEX 27 MHz 100 ppm* EXTAL, AUDIO_X1, AUDIO_CLK, USB_X1 clock tEXL input low pulse width 0.4 0.6 VIDEO_X1 clock input low pulse width 0.45 0.55 EXTAL, AUDIO_X1, AUDIO_CLK, USB_X1 clock tEXH input high pulse width 0.4 0.6 VIDEO_X1 clock input high pulse width 0.45 0.55 EXTAL, AUDIO_X1, AUDIO_CLK, USB_ X1 clock tEXr input rise time  4 VIDEO_X1 clock input rise time  3 EXTAL, AUDIO_X1, AUDIO_CLK, USB_ X1 clock tEXf input fall time  4 VIDEO_X1 clock input fall time  3 tEXcyc tEXcyc ns ns CKIO clock output frequency fOP 50.00 66.67 MHz CKIO clock output cycle time tcyc 15.00 20.00 ns R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Figures 52.2 (1) and 52.2 (2) Page 2975 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Symbol Min. Max. Unit Figure CKIO clock output low pulse width 1 tCKOL1 tcyc/2 tCKOr1  ns Figure 52.2 (1) CKIO clock output high pulse width 1 tCKOH1 tcyc/2 tCKOr1  ns CKIO clock output rise time 1 tCKOr1  3 ns CKIO clock output fall time 1 tCKOf1  3 ns CKIO clock output low pulse width 2 tCKOL2 tcyc/2 tCKOr2  ns CKIO clock output high pulse width 2 tCKOH2 tcyc/2 tCKOr2  ns CKIO clock output rise time 2 tCKOr2  2 ns CKIO clock output fall time 2 tCKOf2  2 ns Power-on oscillation settling time tOSC1 10  ms Figure 52.3 Oscillation settling time 1 on return from standby tOSC2 10  ms Figure 52.4 Real time clock oscillation settling time tROSC  3 s Figure 52.6 Mode hold time tMDH 200  ns Figures 52.3 and 52.4 Note: * Figure 52.2 (2) Reference value. The accuracy of the clock signal affects the quality of images output by the digital video decoder. Input clock signals that are as accurate as is possible. tEXcyc EXTAL, AUDIO_X1, AUDIO_CLK, USB_X1, 1/2 PVcc VIDEO_X1* (input) tEXH VIH tEXL VIH VIL tEXf VIL VIH 1/2 PVcc tEXr Note: * When the clock is input on the EXTAL, AUDIO_X1, AUDIO_CLK, USB_X1, or VIDEO_X1 Figure 52.1 EXTAL, AUDIO_X1, AUDIO_CLK, USB_X1, and VIDEO_X1 Clock Input Timing Page 2976 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tcyc tCKOH1 1/2 PVcc VOH tCKOL1 VOH VOH VOL VOL 1/2 PVcc tCKOr1 tCKOf1 Figure 52.2 (1) CKIO Clock Output Timing 1 tcyc tCKOH2 2.0V tCKOL2 2.0V 1/2 PVcc 0.8V tCKOf2 2.0V 0.8V 1/2 PVcc tCKOr2 Figure 52.2 (2) CKIO Clock Output Timing 2 Oscillation settling time CKIO, Internal clock Power Supply* Power Supply Min. tOSC1 RES TRST tMDH MD_BOOT2, MD_BOOT1, MD_BOOT0 MD_CLK0 Note: * PVcc, Vcc, PLLVcc, AVcc, USBAPVcc, USBDPVcc, USBAVcc, USBPVcc, USBUVcc, VDAVcc Note that SH7269 products in BGA packages do not have USBDVcc, USBUVcc, and USBDPVcc pins. Figure 52.3 Power-On Oscillation Settling Time R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2977 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Oscillation settling time Standby period CKIO, Internal clock tOSC2 RES tMDH MD_BOOT2, MD_BOOT1, MD_BOOT0 MD_CLK0 Note: Oscillation settling time when the internal oscillator is used. Figure 52.4 Oscillation Settling Time on Return from Standby (Return by Reset) Standby period Oscillation settling time CKIO, Internal clock tNMIW, tIRQW NMI, IRQ tOSC2 Figure 52.5 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ) Oscillation settling time Clock (internal) PVCC PVCCmin tROSC Figure 52.6 Real Time Clock Oscillation Settling Time Page 2978 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.4.2 Section 52 Electrical Characteristics Control Signal Timing Table 52.6 Control Signal Timing Item Symbol Min. RES pulse width Exit from standby mode tRESW Other than above Max. Unit Figure 10  ms 20  tcyc Figure 52.7 (1) TRST pulse width tTRSW 20  tcyc NMI pulse width tNMIW 20  tcyc IRQ pulse width tIRQW 20  tcyc PINT pulse width tPINTW 20  tcyc Figure 52.7 (2) BREQ setup time tBREQS 1/2tcyc + 7  ns Figure 52.8 BREQ hold time tBREQH 1/2tcyc + 2  ns BACK delay time tBACKD  1/2tcyc + 13 ns Bus buffer off time 1 tBOFF1  15 ns Bus buffer off time 2 tBOFF2  15 ns Bus buffer on time 1 tBON1  15 ns Bus buffer on time 2 tBON2  15 ns 0  ns BACK setup time before the bus buffer off tBACKS timing Figures 52.7 (2) and 52.5 tRESW/tTRSW RES TRST Figure 52.7 (1) Reset Input Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2979 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tNMIW NMI tIRQW IRQ7 to IRQ0 tPINTW PINT7 to PINT0 Figure 52.7 (2) Interrupt Signal Input Timing tBOFF2 tBON2 CKIO (HIZCNT = 0) CKIO (HIZCNT = 1) tBREQH tBREQS tBREQH tBREQS BREQ tBACKD BACK tBACKD tBACKS tBOFF1 A25 to A0, D31 to D0 tBON1 tBOFF2 RD, RD/WR, RAS, CAS, CSn, WEn, BS, CKE ICIOWR, ICIORD, CE2A tBON2 When HZCNT = 0 When HZCNT = 1 Figure 52.8 Bus Release Timing Page 2980 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.4.3 Section 52 Electrical Characteristics Bus Timing Table 52.7 Bus Timing CKIO = 66.67 MHz*1 Item Symbol Min. 3 Max. Unit Figure Address delay time 1 tAD1 0/2* 12 ns Figures 52.9 to 52.33, 52.34 to 52.37 Address delay time 2 tAD2 1/2tcyc 1/2tcyc + 12 ns Figure 52.16 Address setup time tAS 0  ns Figures 52.9 to 52.12, 52.16 Chip enable setup time tCS 0  ns Figures 52.9 to 52.12, 52.16 Address hold time tAH 0  ns Figures 52.9 to 52.12 BS delay time tBSD  12 ns Figures 52.9 to 52.30, 52.34 to 52.37 CS delay time 1 tCSD1 0/2*3 12 ns Figures 52.9 to 52.33, 52.34 to 52.37 Read write delay time 1 tRWD1 0/2*3 12 ns Figures 52.9 to 52.33, 52.34 to 52.37 Read strobe delay time tRSD 1/2tcyc 1/2tcyc + 12 ns Figures 52.9 to 52.16, 52.34, 52.35 Read data setup time 1 tRDS1 1/2tcyc+ 5  ns Figures 52.9 to 52.15, 52.34 to 52.37 Read data setup time 2 tRDS2 7  ns Figures 52.17 to 52.20, 52.25 to 52.27 Read data setup time 3 tRDS3 1/2tcyc + 5  ns Figure 52.16 Read data hold time 1 tRDH1 0  ns Figures 52.9 to 52.15, 52.34 to 52.37 Read data hold time 2 tRDH2 2  ns Figures 52.17 to 52.20, 52.25 to 52.27 Read data hold time 3 tRDH3 0  ns Figure 52.16 Write enable delay time 1 tWED1 1/2tcyc 1/2tcyc + 12 ns Figures 52.9 to 52.14, 52.34, 52.35 Write enable delay time 2 tWED2  12 ns Figure 52.15 Write data delay time 1 tWDD1  12 ns Figures 52.9 to 52.15, 52.34 to 52.37 Write data delay time 2 tWDD2  12 ns Figures 52.21 to 52.24, 52.28 to 52.30 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2981 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics CKIO = 66.67 MHz*1 Item Symbol Min. Max. Unit Figure Write data hold time 1 tWDH1 1  ns Figures 52.9 to 52.15, 52.34 to 52.37 Write data hold time 2 tWDH2 2  ns Figures 52.21 to 52.24, 52.28 to 52.30 Write data hold time 4 tWDH4 0  ns Figures 52.9 to 52.13, 52.34, 52.36 WAIT setup time tWTS 1/2tcyc + 4.5  ns Figures 52.10 to 52.16, 52.35, 52.37 WAIT hold time tWTH 1/2tcyc + 3.5  ns Figures 52.10 to 52.16, 52.35, 52.37 IOIS16 setup time TIO16S 1/2tcyc + 4.5  ns Figure 52.37 IOIS16 hold time TIO16H 1/2tcyc + 3.5  ns Figure 52.37 RAS delay time 1 tRASD1 2 12 ns Figures 52.17 to 52.33 CAS delay time 1 tCASD1 2 12 ns Figures 52.17 to 52.33 DQM delay time 1 tDQMD1 2 12 ns Figures 52.17 to 52.30 CKE delay time 1 tCKED1 2 12 ns Figure 52.32 AH delay time tAHD 1/2tcyc 1/2tcyc + 12 ns Figure 52.13 Multiplexed address delay time tMAD  12 ns Figure 52.13 Multiplexed address hold time tMAH 1  ns Figure 52.13 Address setup time for AH tAVVH 1/2tcyc – 2  ns Figure 52.13 DACK, TEND delay time tDACD Refer to the direct ns memory access controller timing Figures 52.9 to 52.30, 52.34 to 52.37 ICIORD delay time tICRSD  1/2tcyc + 12 ns Figures 52.36 and 52.37 ICIOWR delay time tICWSD  1/2tcyc + 12 ns Figures 52.36 and 52.37 Notes: 1. The maximum value (fmax) of CKIO (external bus clock) depends on the number of wait cycles and the system configuration of your board. 2. 1/2 tcyc indicated in minimum and maximum values for the item of delay, setup, and hold times represents a half cycle from the rising edge with a clock. That is, 1/2 tcyc describes a reference of the falling edge with a clock. 3. Values when SDRAM is used. Page 2982 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics T1 T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH RD tRDH1 Read tRDS1 D31 to D0 tWED1 tWED1 WEn Write tAH tWDH4 tWDH1 tWDD1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.9 Basic Bus Timing for Normal Space (No Wait) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2983 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics T1 Tw T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH RD tRDH1 tRDS1 Read D31 to D0 tWED1 tWED1 WEn Write tAH tWDH4 tWDD1 tWDH1 D31 to D0 tBSD tBSD BS tDACD DACKn TENDn* tDACD tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.10 Basic Bus Timing for Normal Space (One Software Wait Cycle) Page 2984 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics T1 Tw Twx T2 CKIO tAD1 tAD1 A25 to A0 tAS tCSD1 tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD tAH RD tRDH1 tRDS1 Read D31 to D0 tWED1 tWED1 WEn tAH tWDH4 tWDD1 Write tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTS tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.11 Basic Bus Timing for Normal Space (One Software Wait Cycle, One External Wait Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2985 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics T1 Tw T2 Taw T1 Tw T2 Taw CKIO tAD1 tAD1 tAD1 tAD1 A25 to A0 tAS tCSD1 CSn tCSD1 tAS tCSD1 tRWD1 tCS tRWD1 tCS tRWD1 tCSD1 tRWD1 RD/WR tRSD tRSD RD tAH tRSD tRSD tAH Read tRDH1 tRDH1 tRDS1 tRDS1 D15 to D0 tWED1 tWED1 Write WEn tWED1 tAH tWED1 tWDH4 tWDD1 tWDH4 tWDH1 tWDD1 tWDH1 D15 to D0 tBSD tBSD tBSD tBSD BS tDACD DACKn TENDn* tDACD tWTH tWTS tDACD tDACD tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.12 Basic Bus Timing for Normal Space (One Software Wait Cycle, External Wait Cycle Valid (WM Bit = 0), No Idle Cycle) Page 2986 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Ta1 Ta2 Ta3 T1 Tw Twx T2 CKIO tAD1 tAD1 tCSD1 tCSD1 A25 to A0 CS5 tRWD1 tRWD1 RD/WR tAHD tAHD tAHD AH Read tRSD tRSD RD tRDH1 tMAD tMAH D15 to D0 tRDS1 Data Address tAVVH tWED1 WE1, WE0 tWDD1 Write tAVVH tMAD D15 to D0 tWED1 tWDH4 tWDH1 tMAH Address tBSD Data tBSD BS tWTH tWTS tWTH tWTS WAIT tDACD tDACD DACKn* tDACD tDACD TENDn* Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.13 MPX-I/O Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2987 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Th T1 Twx T2 Tf CKIO tAD1 tAD1 tCSD1 tCSD1 A25 to A0 CSn tWED1 tWED1 WEn tRWD1 tRWD1 RD/WR tRSD tRSD RD Read tRDH1 tRDS1 D31 to D0 tRWD1 tRWD1 tWDD1 tWDH1 RD/WR Write D31 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTH WAIT tWTS tWTS Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.14 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control)) Page 2988 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Th T1 Twx T2 Tf CKIO tAD1 tAD1 tCSD1 tCSD1 tWED2 tWED2 A25 to A0 CSn WEn tRWD1 RD/WR tRSD Read tRSD RD tRDH1 tRDS1 D31 to D0 tRWD1 tRWD1 tRWD1 RD/WR tWDD1 Write tWDH1 D31 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTH WAIT tWTS tWTS Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.15 Bus Cycle of SRAM with Byte Selection (SW = 1 Cycle, HW = 1 Cycle, One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control)) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2989 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics T1 Tw Twx T2B Twb T2B CKIO tAD1 tAD2 tAD2 tAD1 A25 to A0 tCSD1 tAS tCSD1 CSn tCS tRWD1 tRWD1 RD/WR tRSD tRSD RD tRDH3 tRDS3 tRDH3 tRDS3 D31 to D0 WEn tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTH WAIT tWTS tWTS Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.16 Burst ROM Read Cycle (One Software Wait Cycle, One Asynchronous External Burst Wait Cycle, Two Burst) Page 2990 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Tc1 Tcw Td1 Tde CKIO tAD1 A25 to A0 tAD1 Row address tAD1 A12/A11 *1 tAD1 Column address tAD1 tAD1 READA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.17 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2991 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Trw Tc1 Tcw Td1 Tde Tap CKIO tAD1 A25 to A0 tAD1 Row address tAD1 A12/A11* Column address tAD1 1 tAD1 tAD1 READA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.18 Synchronous DRAM Single Read Bus Cycle (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 1 Cycle) Page 2992 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Tc1 Tc2 Td1 Td2 Tc3 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 Column address A12/A11 tAD1 (1 to 4) tAD1 *1 tAD1 tAD1 tAD1 READA command READ command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.19 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2993 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Trw Tc1 Tc2 Td1 Td2 Tc3 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 Column address *1 tAD1 (1 to 4) tAD1 A12/A11 tAD1 tAD1 READ command tAD1 READA command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.20 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle) Page 2994 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Tc1 Trwl CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 Column address tAD1 *1 tAD1 WRITA command A12/A11 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tBSD tBSD D31 to D0 BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.21 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, TRWL = 1 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2995 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Trw Trw Tc1 Trwl CKIO tAD1 A25 to A0 tAD1 tAD1 Column address Row address tAD1 tAD1 *1 tAD1 WRITA command A12/A11 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tBSD tBSD D31 to D0 BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.22 Synchronous DRAM Single Write Bus Cycle (Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle) Page 2996 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 *1 WRIT command A12/A11 WRITA command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.23 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2997 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 *1 A12/A11 WRIT command WRITA command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 tCASD1 tCASD1 RD/WR tRASD1 tRASD1 RAS CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.24 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) Page 2998 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Tc1 Tc2 Td1 Td2 Tc3 Tc4 Td3 Td4 Tde CKIO tAD1 A25 to A0 tAD1 Row address tAD1 tAD1 tAD1 tAD1 tAD1 Column address tAD1 *1 A12/A11 tAD1 READ command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 2999 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tc1 Tc2 Td1 Td2 Tc3 Tc4 Td3 Td4 Tde CKIO tAD1 A25 to A0 tAD1 tAD1 tAD1 tAD1 Column address tAD1 *1 A12/A11 tAD1 READ command tCSD1 tCSD1 CSn tRWD1 tRWD1 RD/WR tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle) Page 3000 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tp Section 52 Electrical Characteristics Trw Tr Tc1 Tc2 Td1 Td2 Tc3 Tc4 Td3 Td4 Tde CKIO tAD1 tAD1 tAD1 tAD1 tAD1 tAD1 Column address Row address A25 to A0 tAD1 tAD1 tAD1 *1 A12/A11 tAD1 READ command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.27 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3001 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 tAD1 Row address A25 to A0 tAD1 tAD1 tAD1 tAD1 Column address tAD1 tAD1 *1 A12/A11 WRIT command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.28 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle, TRWL = 0 Cycle) Page 3002 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tnop Tc1 Tc2 Tc3 Tc4 CKIO tAD1 tAD1 tAD1 tAD1 tAD1 Column address A25 to A0 tAD1 tAD1 tAD1 *1 A12/A11 WRIT command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.29 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle, TRWL = 0 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3003 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tp Tpw Tr Tc1 Tc2 Tc3 Tc4 CKIO tAD1 A25 to A0 tAD1 tAD1 Row address tAD1 tAD1 tAD1 tAD1 Column address tAD1 tAD1 tAD1 *1 A12/A11 WRIT command tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS tDQMD1 tDQMD1 DQMxx tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 tBSD tBSD BS (High) CKE tDACD tDACD DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.30 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles) (Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle) Page 3004 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 *1 A12/A11 tCSD1 tCSD1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS DQMxx (Hi-Z) D31 to D0 BS (High) CKE DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.31 Synchronous DRAM Auto-Refreshing Timing (WTRP = 1 Cycle, WTRC = 3 Cycles) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3005 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tp Tpw Trr Trc Trc Trc CKIO tAD1 tAD1 A25 to A0 tAD1 tAD1 *1 A12/A11 tCSD1 tCSD1 tCSD1 tCSD1 CSn tRWD1 tRWD1 tRASD1 tRASD1 tRWD1 RD/WR tRASD1 tRASD1 RAS tCASD1 tCASD1 CAS DQMxx (Hi-Z) D31 to D0 BS tCKED1 tCKED1 CKE DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.32 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) Page 3006 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tp Section 52 Electrical Characteristics Tpw Trr Trc Trc Trr Trc Trc Tmw Tde CKIO PALL REF REF MRS tAD1 tAD1 tAD1 A25 to A0 tAD1 tAD1 *1 A12/A11 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 CSn tRWD1 RD/WR tRASD1 tRASD1 tRASD1 tRASD1 RAS tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 tCASD1 CAS DQMxx (Hi-Z) D31 to D0 BS CKE DACKn TENDn*2 Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Figure 52.33 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3007 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 CKIO tAD1 tAD1 tCSD1 tCSD1 tRWD1 tRWD1 A25 to A0 CExx RD/WR tRSD tRSD RD tRDH1 Read tRDS1 D15 to D0 tWED1 tWED1 WE tWDH4 tWDD1 Write tWDH1 D15 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.34 PCMCIA Memory Card Bus Cycle (TED = 0 Cycle, TEH = 0 Cycle, No Wait) Page 3008 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tpcm0 Section 52 Electrical Characteristics Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO tAD1 tAD1 tCSD1 tCSD1 tRWD1 tRWD1 A25 to A0 CExx RD/WR tRSD tRSD RD tRDH1 Read tRDS1 D15 to D0 tWED1 tWED1 WE tWDD1 Write tWDH1 D15 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTS tWTH tWTS WAIT Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.35 PCMCIA Memory Card Bus Cycle (TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3009 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 CKIO tAD1 tAD1 tCSD1 tCSD1 tRWD1 tRWD1 A25 to A0 CExx RD/WR tICRSD tICRSD ICIORD tRDH1 Read tRDS1 D15 to D0 tICWSD tICWSD ICIOWR tWDH4 tWDH1 tWDD1 Write D15 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.36 PCMCIA I/O Card Bus Cycle (TED = 0 Cycle, TEH = 0 Cycle, No Wait) Page 3010 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Tpci0 Section 52 Electrical Characteristics Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w CKIO tAD1 tAD1 tCSD1 tCSD1 tRWD1 tRWD1 A25 to A0 CExx RD/WR tICRSD tICRSD ICIORD tRDH1 Read tRDS1 D15 to D0 tICWSD tICWSD ICIOWR tWDD1 Write tWDH1 D15 to D0 tBSD tBSD BS tDACD tDACD DACKn TENDn* tWTH tWTS tWTH tWTS WAIT tIO16H IOIS16 tIO16S Note: * The waveform for DACKn and TENDn is when active low is specified. Figure 52.37 PCMCIA I/O Card Bus Cycle (TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3011 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.4 UBC Timing Table 52.8 UBC Timing Item Symbol Min. Max. Unit Figure UBCTRG delay time tUBCTGD — 14 ns Figure 52.38 CKIO tUBCTGD UBCTRG Figure 52.38 UBC Trigger Timing Page 3012 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.4.5 Section 52 Electrical Characteristics Direct Memory Access Controller Timing Table 52.9 Direct Memory Access Controller Timing Item Symbol Min. Max. Unit Figure DREQ setup time tDRQS 5.5  ns Figure 52.39 DREQ hold time tDRQH 2.5  DACK, TEND delay time tDACD 0 12 Figure 52.40 CKIO tDRQS tDRQH DREQ0 Figure 52.39 DREQ Input Timing CKIO t DACD t DACD TEND0 DACK0 Figure 52.40 DACK, TEND Output Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3013 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.6 Multi-Function Timer Pulse Unit 2 Timing Table 52.10 Multi-Function Timer Pulse Unit 2 Timing Item Symbol Min. Max. Unit Figure Timer clock pulse width (single edge) tTCKWH/L 1.5  tp0cyc Figure 52.41 Timer clock pulse width (both edges) tTCKWH/L 2.5  tp0cyc Timer clock pulse width tTCKWH/L 2.5  tp0cyc (phase counting mode) Note: tp0cyc indicates peripheral clock (P0) cycle. TCLKA to TCLKD tTCKWL tTCKWH Figure 52.41 Clock Input Timing Page 3014 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.4.7 Section 52 Electrical Characteristics Watchdog Timer Timing Table 52.11 Watchdog Timer Timing Item Symbol Min. Max. Unit Figure WDTOVF delay time tWOVD  100 ns Figure 52.42 CKIO tWOVD tWOVD WDTOVF Figure 52.42 WDTOVF Output Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3015 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.8 Serial Communication Interface with FIFO Timing Table 52.12 Serial Communication Interface with FIFO Timing Item Symbol Min. Input clock cycle (clocked synchronous) tScyc (asynchronous) Max. Unit Figure 12  tp1cyc Figure 52.43 4  tp1cyc Input clock rise time tSCKr  1.5 tp1cyc Input clock fall time tSCKf  1.5 tp1cyc Input clock width tSCKW 0.4 0.6 tScyc Transmit data delay time (clocked synchronous) tTXD  3 tp1cyc  15 ns Receive data setup time (clocked synchronous) tRXS 4 tp1cyc  15  ns Receive data hold time (clocked synchronous) tRXH 1 tp1cyc  15  ns Figure 52.44 Note: tp1cyc indicates the peripheral clock 1 (P1) cycle. tSCKW tSCKr tSCKf SCK tScyc Figure 52.43 SCK Input Clock Timing tScyc SCK (input/output) tTXD TxD (data transmit) tRXS tRXH RxD (data receive) Figure 52.44 Transmit/Receive Data Input/Output Timing in Clocked Synchronous Mode Page 3016 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.4.9 Section 52 Electrical Characteristics Renesas Serial Peripheral Interface Timing Table 52.13 Renesas Serial Peripheral Interface Timing Item RSPCK clock cycle Symbol Min. Master tSPcyc Slave RSPCK clock high pulse width Master tSPCKWH Slave RSPCK clock low pulse width Master tSPCKWL Slave Data input setup time Master tSU Slave Data input hold time Master tH Slave SSL setup time Master tLEAD Slave SSL hold time Master tLAG Slave Data output delay time Master tOD Slave Data output hold time Master tOH Slave Continuous transmission delay time Master tTD Max. Unit Figure tcyc Figure 52.45 2 4096 8 4096 0.4  0.4  0.4  0.4  tSPcyc tSPcyc 15  ns 0  tcyc 0  ns 4  tcyc 1 tSPcyc  20 8  tSPcyc ns 4  1 tSPcyc 8  tSPcyc ns  20 4  tcyc  21 ns  4 tcyc tcyc 5  ns 3  tcyc 1 tSPcyc  2 tcyc 8  tSPcyc ns  2  tcyc 4  tcyc  Slave Slave access time tSA  4 tcyc Slave out release time tREL  3 tcyc R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Figures 52.46 to 52.49 Figures 52.48 and 52.49 Page 3017 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tSPCKWH VOH VOH RSPCK1, RSPCK0 Master select output VOL VOL tSPCKWL tSPcyc tSPCKWH VIH VIH RSPCK1, RSPCK0 Slave select input VIL VIL tSPCKWL tSPcyc Figure 52.45 Clock Timing tTD SSL10, SSL00 Output tLEAD tLAG RSPCK1, RSPCK0 CP0L = 0 Output RSPCK1, RSPCK0 CP0L = 1 Output tSU MISO1, MISO0 Input tH MSB IN DATA tOH MOSI1, MOSI0 Output MSB OUT LSB IN MSB IN tOD DATA LSB OUT IDLE MSB OUT Figure 52.46 Transmission and Reception Timing (Master, CPHA = 0) Page 3018 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tTD SSL10, SSL00 Output tLEAD tLAG RSPCK1, RSPCK0 CP0L = 0 Output RSPCK1, RSPCK0 CP0L = 1 Output tSU MISO1, MISO0 Input tH MSB IN tOH DATA LSB IN DATA LSB OUT MSB IN tOD MOSI1, MOSI0 Output MSB OUT IDLE MSB OUT Figure 52.47 Transmission and Reception Timing (Master, CPHA = 1) tTD SSL10, SSL00 Input tLEAD tLAG RSPCK1, RSPCK0 CP0L = 0 Input RSPCK1, RSPCK0 CP0L = 1 Input tOH tSA MISO1, MISO0 Output MSB OUT tSU MOSI1, MOSI0 Input tOD DATA LSB OUT IDLE MSB OUT tH MSB IN DATA MSB IN LSB IN Figure 52.48 Transmission and Reception Timing (Slave, CPHA = 0) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3019 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tTD SSL10, SSL00 Input tLEAD tLAG RSPCK1, RSPCK0 CP0L = 0 Input RSPCK1, RSPCK0 CP0L = 1 Input tOD tOH tSA MISO1, MISO0 Output LSB OUT (Last data) MSB OUT tSU MOSI1, MOSI0 Input tREL DATA IDLE MSB OUT tDR, tDF tH MSB IN LSB OUT DATA MSB IN LSB IN Figure 52.49 Transmission and Reception Timing (Slave, CPHA = 1) Page 3020 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.10 Renesas Quad Serial Peripheral Interface Timing Table 52.14 Renesas Quad Serial Peripheral Interface Timing Item Symbol Min. Max. Unit Figure QSPCLK clock cycle tQScyc 1 4080 tcyc Figure 52.50 Data input setup time tSU 5.0  ns Data input hold time tH 0.0 ns SSL setup time tLEAD 1.5  tQScyc 8.5  tQScyc 4 Figures 52.51 and 52.52 ns SSL hold time tLAG 1  tQScyc 8  tQScyc + 4 ns Data output delay time tOD  10.0 ns Data output hold time tOH 5.0  ns Continuous transfer delay time tTD 1 8 tQScyc Note: tcyc indicates the peripheral clock 1 (P1) cycle. QSPCLK Output tQScyc Figure 52.50 Clock Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3021 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tTD QSSL Output tLEAD tLAG QSPCLK CPOL = 0 Output QSPCLK CPOL = 1 Output tSU QMI, QIO0 to QIO3 Input tH MSB IN DATA tOH QMO, QIO0 to QIO3 Output MSB OUT LSB IN tOD DATA LSB OUT IDLE Figure 52.51 Transmission and Reception Timing (CPHA = 0) tTD QSSL Output tLEAD tLAG QSPCLK CPOL = 0 Output QSPCLK CPOL = 1 Output tSU QMI, QIO0 to QIO3 Input QMO, QIO0 to QIO3 Output tH MSB IN tOH DATA LSB IN DATA LSB OUT tOD MSB OUT IDLE Figure 52.52 Transmission and Reception Timing (CPHA = 1) Page 3022 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.11 SPI Multi I/O Bus Controller Timing Table 52.15 SPI Multi I/O Bus Controller Timing Item Symbol Min. Max. Unit Figure SPBCLK clock cycle tSPBcyc 2 2 tbcyc Figure 52.53 Data input setup time tSU 5.0  ns Data input hold time tH 0.0  ns Figures 52.54 and 52.55 SSL setup time tLEAD 1  tSPBcyc  3 8  tSPBcyc ns SSL hold time tLAG 1.5  tSPBcyc 1.5  tSPBcyc +3 ns Continuous transfer delay time tTD 1 1 tSPBcyc Data output delay time tOD  4.0 ns Data output hold time tOH 2.0  ns Data output buffer on time tBON  4.0 ns Data output buffer off time tBOFF 9.0 2.0 ns Figures 52.56 and 52.57 Note: tbcyc indicates the bus clock (B) cycle. SPBCLK Output tSPBcyc Figure 52.53 Clock Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3023 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tTD SPBSSL Output tLEAD tLAG SPBCLK CPOL = 0 Output SPBCLK CPOL = 1 Output tSU SPBMI_0/ SPBMI_1, SPBIO[0:3]_0/ SPBIO[0:3]_1 Input tH MSB IN DATA tOD tOH SPBMO_0/ SPBMO_1, SPBIO[0:3]_0/ SPBIO[0:3]_1 Output MSB OUT LSB IN DATA LSB OUT IDLE Figure 52.54 Transmission and Reception Timing (CPHAT = 0, CPHAR = 0) tTD SPBSSL Output tLEAD tLAG SPBCLK CPOL = 0 Output SPBCLK CPOL = 1 Output SPBMI_0/ SPBMI_1, SPBIO[0:3]_0/ SPBIO[0:3]_1 Input SPBMO_0/ SPBMO_1, SPBIO[0:3]_0/ SPBIO[0:3]_1 Output tSU tH MSB IN tOH DATA LSB IN tOD MSB OUT DATA LSB OUT IDLE Figure 52.55 Transmission and Reception Timing (CPHAT = 1, CPHAR = 1) Page 3024 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics SPBCLK CPOL = 0 Output SPBCLK CPOL = 1 Output tBOFF tBON SPBMI_0/ SPBMI_1, SPBIO[0:3]_0/ SPBIO[0:3]_1 Output Figure 52.56 Timing for Switching the Buffers on and off (CPHAT  0, CPHAR  0) SPBCLK CPOL = 0 Output SPBCLK CPOL = 1 Output tBOFF tBON SPBMI_0/ SPBMI_1, SPBIO[0:3]_0/ SPBIO[0:3]_1 Output Figure 52.57 Timing for Switching the Buffers on and off (CPHAT  1, CPHAR  1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3025 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.12 I2C Bus Interface 3 Timing Table 52.16 (1) I2C Bus Interface 3 Timing I2C Bus Format Item Symbol Min. SCL input cycle time tSCL SCL input high pulse width tSCLH SCL input low pulse width tSCLL SCL, SDA input rise time tSr  300 ns SCL, SDA input fall time tSf  300 ns SCL, SDA input spike pulse removal time* tSP  1, 2 tp0cyc* SDA input bus free time tBUF 5  tp0cyc* Start condition input hold time tSTAH 3  tp0cyc* Retransmit start condition input setup time tSTAS 3  tp0cyc* Stop condition input setup time tSTOS 3  tp0cyc* Data input setup time tSDAS 1 tp0cyc* + 20  ns 2 Max. Unit Figure 12 tp0cyc* + 600  ns 3 tp0cyc* + 300 1  ns Figure 52.58(1) 5 tp0cyc* + 300  ns 1 1 1 1 1 1 1 1 Data input hold time tSDAH 0  ns SCL, SDA capacitive load Cb 0 400 pF tSf  250 ns 3 SCL, SDA output fall time* Notes: 1. tp0cyc indicates the peripheral clock 0 (P0) cycle. 2. Depends on the value of NF2CYC. 3. Indicates the I/O buffer characteristic. VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSCL P* tSDAS tSr tSDAH [Legend] S: Start condition P: Stop condition Sr: Start condition for retransmission Figure 52.58(1) Input/Output Timing Page 3026 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.16 (2) I2C Bus Interface 3 Timing Clock Synchronized Serial Format Item Symbol Min. SCL input cycle time tSCL 12 tpcyc* + 600 SCL input high pulse width tSCLH 3 tpcyc* + 300 1 SCL input low pulse width tSCLL 5 tpcyc* + 300  ns SCL, SDA input rise time tSr  300 ns tSf  300 ns SCL, SDA input spike pulse removal time* tSP  1, 2 tpcyc* Data output delay time tHD 0 900 ns tSDAS 1 tpcyc* + 20  ns SCL, SDA input fall time 2 Data input setup time Max. 1 1 1 Unit Figure  ns  ns Figure 52.58(2) 1 Data input hold time tSDAH 0  ns SCL, SDA capacitive load Cb 0 400 pF tSf  250 ns 3 SCL, SDA output fall time* Figure 52.58(3) Figures 52.58(2) and 52.58(3) Notes: 1. tpcyc indicates the peripheral clock 0 (P0) cycle. 2. Depends on the value of NF2CYC. 3. Indicates the I/O buffer characteristic. tSf tSr tSCLL tSCLH SCL tSCL Figure 52.58(2) Clock Input/Output Timing SCL tHD SDA tSDAS tSDAH Figure 52.58(3) Transmission/Reception Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3027 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.13 Serial Sound Interface Timing Table 52.17 Serial Sound Interface Timing Item Symbol Min. Max. Unit Remarks Figure Output clock cycle tO 80 64000 ns Output Input clock cycle tI 80 64000 ns Input Figure 52.59 Clock high tHC 32  ns Bidirectional Clock low tLC 32  ns Clock rise time tRC  25 ns Delay tDTR 5 25 ns 10 45 ns Noise canceler not in use Noise canceler in use Setup time tSR 25  ns Hold time tHTR 5  ns Figures 52.60 and 52.61 tRC tHC SSISCKn Output tLC tI ,tO Figure 52.59 Clock Input/Output Timing Page 3028 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics SSISCKn (Input or output) SSIWSn, SSIDATAn (Input) tSR tHTR SSIWSn, SSIDATAn (Output) tDTR Figure 52.60 Transmission and Reception Timing (Synchronization with Rising Edge of SSISCKn) SSISCKn (Input or output) SSIWSn, SSIDATAn (Input) tSR tHTR SSIWSn, SSIDATAn (Output) tDTR Figure 52.61 Transmission and Reception Timing (Synchronization with Falling Edge of SSISCKn) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3029 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.14 Serial I/O with FIFO Timing Table 52.18 Serial I/O with FIFO Timing Item Symbol Min. Max. Unit Figure SCK_SIO clock input/output cycle time tSIcyc 80  ns Figures 52.62 to 52.64 SCK_SIO output high width tSWHO 0.4  tSIcyc  SCK_SIO output low width tSWLO 0.4  tSIcyc  SIOFSYNC output delay time tFSD 5 20 SCK_SIO input high width tSWHI 0.4  tSIcyc  SCK_SIO input low width tSWLI 0.4  tSIcyc  SIOFSYNC input setup time tFSS 20  SIOFSYNC input hold time tFSH 20  TXD_SIO output delay time tSTDD 5 20 RXD_SIO input setup time tSRDS 20  RXD_SIO input hold time tSRDH 20  Figures 52.62 and 52.63 Figure 52.64 Figures 52.62 to 52.64 tSIcyc tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD tSTDD TXD_SIO tSRDS tSRDH RXD_SIO Figure 52.62 Transmission and Reception Timing (Master Mode 1, Sampled at Falling Edge) Page 3030 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tSIcyc tSWHO tSWLO SCK_SIO (output) tFSD tFSD SIOFSYNC (output) tSTDD tSTDD TXD_SIO tSRDS tSRDH RXD_SIO Figure 52.63 Transmission and Reception Timing (Master Mode 1, Sampled at Rising Edge) tSIcyc tSWHI tSWLI SCK_SIO (input) tFSS tFSH SIOFSYNC (input) tSTDD tSTDD TXD_SIO tSRDS tSRDH RXD_SIO Figure 52.64 Transmission and Reception Timing (Slave Mode 1) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3031 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.15 A/D Converter Timing Table 52.19 A/D Converter Timing Module Item Symbol Min. Max. Unit Figure A/D converter Trigger input setup time tTRGS 17  ns Figure 52.65 CKIO tTRGS ADTRG Figure 52.65 A/D Converter External Trigger Input Timing Page 3032 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.16 NAND Type Flash Memory Controller Timing Table 52.20 NAND Type Flash Memory Interface Timing Item Symbol Min. Max. Unit Figure Command output setup time tNCDS 2  tfcyc  10  ns tNCDH 1.5  tfcyc  5  ns Figures 52.66 and 52.70 Command output hold time Data output setup time tNDOS 0.5  twfcyc  5  ns Data output hold time tNDOH 0.5  twfcyc  10  ns Command to address transition time 1 tNCDAD1 1.5  tfcyc  10  ns Figures 52.66 and 52.67 Command to address transition time 2 tNCDAD2 2  tfcyc  10  ns Figure 52.67 FWE cycle time tNWC twfcyc  5  ns Figures 52.67 and 52.69 FWE low pulse width tNWP 0.5  twfcyc  5  ns Figures 52.66, 52.67, 52.69, and 52.70 FWE high pulse width tNWH 0.5  twfcyc  5  ns Figures 52.67 and 52.69 Address to ready/busy transition time tNADRB  32  tp0cyc ns Figures 52.67 and 52.68 Command to ready/busy transition time tNCDRB  10  tp0cyc ns Figures 52.67 and 52.68 Ready/busy to data read transition time 1 tNRBDR1 1.5  tfcyc  ns Figure 52.68 Ready/busy to data read transition time 2 tNRBDR2 32  tp0cyc  ns FRE cycle time tNSCC twfcyc  5  ns FRE low pulse width tNSP 0.5  twfcyc  5  ns R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Figures 52.66, 52.67, 52.69, and 52.70 Figures 52.68 and 52.70 Page 3033 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Item Symbol Min. FRE high pulse width tNSPH Read data setup time tNRDS Read data hold time Max. Unit Figure 0.5  twfcyc  5  ns Figure 52.68 16  ns Figures 52.68 and 52.70 tNRDH 5  ns Figures 52.68 and 52.70 Data write setup time tNDWS 32  tp0cyc  ns Figure 52.69 Command to status read transition time tNCDSR 4  tfcyc  ns Figure 52.70 Command output off to status read transition time tNCDFSR 3.5  tfcyc  ns Status read setup time tNSTS 2.5  tfcyc  ns FCE output setup time tNCES 8  tp0cyc  ns Figure 52.66 FCE output hold time tNCEH tp0cyc  ns Figure 52.69 FCE output access time tNCEA 6  tp0cyc  ns Figure 52.68 FCE output high-level hold time tNCEOH 2  tp0cyc  ns Note: tfcyc indicates the period of one cycle of the FLCTL clock. twfcyc indicates the period of one cycle of the FLCTL clock when the value of the NANDWF bit is 0. On the other hand, twfcyc indicates the period of two cycles of the FLCTL clock when the value of the NANDWF bit is 1. tp0cyc indicates the period of one cycle of the peripheral clock 0 (P0). Page 3034 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tNCES FCE FCLE tNCDAD1 FALE tNCDS tNWP tNCDH FWE (High) FRE tNDOS NAF7 to NAF0 tNDOH Command (High) FRB Figure 52.66 NAND Type Flash Memory Command Issuance Timing FCE (Low) FCLE tNWC FALE tNCDAD2 tNWP tNWH tNWP tNWH tNWP tNCDAD1 FWE (High) FRE tNDOS tNDOH tNDOS tNDOH tNDOS tNDOH NAF7 to NAF0 Address (High) Address Address tNADRB (tNCDRB) FRB Figure 52.67 NAND Type Flash Memory Address Issuance Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3035 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics * FCE FCLE (Low) FALE tNSCC (High) tNCEOH tNCEA FWE tNRBDR2 tNSP tNSPH tNSP tNSP FRE tNRDS tNRDH tNRDS tNRDH NAF7 to NAF0 Data tNADRB tNCDRB Data tNRDS tNRDH Data tNRBDR1 FRB Note: * Waveform when the HOLDEN bit is 1. Figure 52.68 NAND Type Flash Memory Data Read Timing Page 3036 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics * FCE FCLE (Low) tNWC tNCEH tNCES FALE tNDWS tNWP tNWP tNWH tNWP FWE (High) FRE tNDOS tNDOH tNDOS tNDOH Data NAF7 to NAF0 tNDOS tNDOH Data Data (High) FRB Note: * Waveform when the HOLDEN bit is 1. Figure 52.69 NAND Type Flash Memory Data Write Timing FCE (Low) FCLE FALE (Low) tNCDS tNWP tNCDH FWE tNSTS tNCDSR FRE tNSP tNCDFSR tNDOS NAF7 to NAF0 tNDOH Command tNRDS tNRDH Status (High) FRB Figure 52.70 NAND Type Flash Memory Status Read Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3037 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.17 USB 2.0 Host/Function Module Timing Table 52.21 USB Transceiver Timing (Low-Speed) Item Symbol Min. Typ. Max. Unit Figure Rise time tLR 75  300 ns Figure 52.71 Fall time tLF 75  300 ns Rise/fall time lag tLR/tLF 80  125 % 90% DP, DM 90% 10% 10% tLR tLF Figure 52.71 DP and DM Output Timing (Low-Speed) PVCC DP CL = 200 pF to 600 pF Measurement circuit PVCC RL = 1.5 kΩ DM CL = 200 pF to 600 pF VSS The electric capacitance (CL) includes the stray capacitance of connection and the input capacitance of probe. Figure 52.72 Measurement Circuit (Low-Speed) Page 3038 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.22 USB Transceiver Timing (Full-Speed) Item Symbol Min. Typ. Max. Unit Figure Figure 52.73 Rise time tFR 4  20 ns Fall time tFF 4  20 ns Rise/fall time lag tFR/tFF 90  111.11 % 90% DP, DM 90% 10% 10% tFR tFF Figure 52.73 DP and DM Output Timing (Full-Speed) USBDPVCC * 1 DP CL = 50 pF Measurement circuit DM CL = 50 pF *2 USBDPVSS The electric capacitance (CL) includes the stray capacitance of connection and the input capacitance of probe. Notes: 1. The PVcc pin is used in SH7269 (BGA) Group products. 2. The Vss pin is used in SH7269 (BGA) Group products. Figure 52.74 Measurement Circuit (Full-Speed) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3039 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.23 USB Transceiver Timing (High-Speed) Item Symbol Min. Typ. Max. Unit Figure Figure 52.75 Rise time tHSR 500   ps Fall time tHSF 500   ps Output driver resistance ZHSDRV 40.5  49.5  DP, DM 90% 90% 10% tHSR 10% tHSF Figure 52.75 DP and DM Output Timing (High-Speed) USBDPVCC * 1 DP RL = 45Ω Measurement circuit DM RL = 45Ω *2 USBDPVSS Notes: 1. The PVcc pin is used in SH7269 (BGA) Group products. 2. The Vss pin is used in SH7269 (BGA) Group products. Figure 52.76 Measurement Circuit (High-Speed) Page 3040 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.18 Video Display Controller 4 Timing Table 52.24 Video Display Controller 4 Timing Item Symbol Min. Typ. Max. Unit Figure DV_CLK input clock frequency tDcyc   66.67 MHz Figure 52.77 DV_CLK input clock low pulse width tWIL 0.4   tDcyc DV_CLK input clock high pulse width tWIH 0.4   LCD_EXTCLK input clock frequency tEcyc   66.67 MHz LCD_EXTCLK input clock low pulse width tWIL 0.4   tEcyc LCD_EXTCLK input clock high pulse width tWIH 0.4   LCD_CLK output clock frequency tLcyc   66.67 MHz Figure 52.78 Input data setup time tVS 4   ns Figure 52.79 Input data hold time tVH 4   ns Output data delay time tDD 5  3 ns R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Figure 52.80 Page 3041 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tDcyc, tEcyc tWH DV_CLK, LCD_EXTCLK 1/2 PVcc VIH tWL VIH VIL VIL Figure 52.77 DV_CLK and LCD_EXTCLK Clock Input Timing tLcyc LCD_CLK 1/2 PVcc Figure 52.78 LCD_CLK Clock Output Timing Page 3042 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics DV_CLK tVS tVH Latched at rising edge DV_DATA23 to DV_DATA0, DV_VSYNC, DV_HSYNC tVS tVH Latched at falling edge Figure 52.79 Video Input Timing LCD_CLK tDD Output at falling edge LCD_DATA23 to LCD_DATA0, LCD_TCON6 to LCD_TCON0 tDD Output at rising edge Figure 52.80 Display Output Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3043 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.19 SD Host Interface Timing Table 52.25 SD Host Interface Timing Item Symbol Min. Max. Unit Figure SD_CLK clock cycle tSDPP 2  tp1cyc  ns SD_CLK clock high width tSDWH 0.4  tSDPP  ns SD_CLK clock low width tSDWL 0.4  tSDPP  ns SD_CLK clock rise time tSDLH  3 ns SD_CLK clock fall time tSDHL  3 ns SD_CMD, SD_D3 to SD_D0 output data delay (data transfer mode) tSDODLY  4 ns SD_CMD, SD_D3 to SD_D0 input data setup tSDISU 5  ns SD_CMD, SD_D3 to SD_D0 input data hold tSDIH 2  ns Figure 52.81 Note: tp1cyc indicates peripheral clock 1 (P1) cycle. tSDPP tSDWL tSDWH SD_CLK tSDISU tSDIH SD_CMD, SD_D3 to SD_D0 input SD_CMD, SD_D3 to SD_D0 output tSDODLY (max) tSDODLY (min) Figure 52.81 SD Card Interface Page 3044 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.20 MMC Host Interface Timing Table 52.26 MMC Host Interface Timing Item Symbol Min. Max. Unit Figure MMC_CLK clock cycle tMMCPP 2  tp1cyc  ns Figure 52.82 MMC_CLK clock high level width tMMCWH 6.5  ns MMC_CLK clock low level width tMMCWL 6.5  ns MMC_CLK clock rise time tMMCLH  3 ns MMC_CLK clock fall time tMMCHL  3 ns MMC_CMD, MMC_D7 to MMC_D0 tMMCODLY output data delay time (data transfer mode) 6.5 6.5 ns MMC_CMD, MMC_D7 to MMC_D0 intput data setup time tMMCISU 4.5  ns MMC_CMD, MMC_D7 to MMC_D0 intput data hold time tMMCIH 2  ns Note: tp1cyc indicates peripheral clock 1 (P1) cycle. tMMCPP tMMCWL tMMCWH MMC_CLK tMMCHL tMMCLH tMMCISU tMMCIH MMC_CMD, MMC_D7 to MMC_D0 Input MMC_CMD, MMC_D7 to MMC_D0 Output tMMCODLY (max) tMMCODLY (min) Figure 52.82 MMC Interface R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3045 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.21 General Purpose I/O Ports Timing Table 52.27 General Purpose I/O Ports Timing Item Symbol Min. Max. Unit Figure Output data delay time tPORTD  100 ns Figure 52.83 Input data setup time tPORTS 100  Input data hold time tPORTH 100  CKIO tPORTS tPORTH Port (read) tPORTD Port (write) Figure 52.83 General I/O Ports Timing Page 3046 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.22 User Debugging Interface Timing Table 52.28 User Debugging Interface Timing Item Symbol Min. Max. Unit Figure TCK cycle time tTCKcyc 50*  ns Figure 52.84 TCK high pulse width tTCKH 0.4 0.6 tTCKcyc TCK low pulse width tTCKL 0.4 0.6 tTCKcyc TDI setup time tTDIS 10  ns TDI hold time tTDIH 10  ns TMS setup time tTMSS 10  ns TMS hold time tTMSH 10  ns TDO delay time tTDOD  16 ns Capture register setup time tCAPTS 10  ns Capture register hold time tCAPTH 10  ns Update register delay time tUPDATED  20 ns Note: * Figure 52.85 Figure 52.86 Should be greater than the peripheral clock 0 (P0) cycle time. tTCKcyc tTCKH tTCKL VIH VIH VIH 1/2 PVcc 1/2 PVcc VIL VIL Figure 52.84 TCK Input Timing R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3047 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics tTCKcyc TCK tTDIS tTDIH tTMSS tTMSH TDI TMS tTDOD TDO change timing after switch command setting tTDOD TDO Initial value Figure 52.85 Data Transfer Timing TCK tCAPTS tCAPTH Capture register tUPDATED Update register Figure 52.86 Data Transfer Timing Page 3048 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.4.23 AC Characteristics Measurement Conditions  I/O signal reference level: PVCC/2, the minimum values of VIH, VT+, and VOH, and the maximum values of VIL, VT-, and VOL (refer to the individual timing chart)  Input pulse level: PVCC  Input rise and fall times: 1 ns LSI output pin Measurement point CL CMOS output Note: CL is the total value that includes the capacitance of measurement tools. CL = 30 pF Figure 52.87 Output Load Circuit Page 3050 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics 52.5 A/D Converter Characteristics Conditions: VCC = PLLVCC = USBDVCC = USBUVCC = 1.15 to 1.35 V, PVCC = USBDPVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAVCC = 1.15 to 1.35 V, USBAPVCC = 3.0 to 3.6 V, VDAVCC = 3.0 to 3.6 V, VSS = PLLVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS = USBAPVSS = USBUVSS = VDAVSS = 0 V, Ta = 20 to 85 C (regular specifications), 40 to 85 C (wide-range specifications) Note: SH7269 (BGA) Group products do not have the USBDVCC, USBUVCC, USBDPVCC, PLLVSS, USBDVSS, USBAVSS, USBUVSS, USBDPVSS, and USBAPVSS pins. Table 52.29 A/D Converter Characteristics Item Min. Typ. Max. Resolution 10 10 10 bits Conversion time 6   s Analog input capacitance   20 pF Permissible signal-source impedance   5 k Nonlinearity error   3.0* LSB Offset error   2.0* LSB Full-scale error   2.0* LSB Quantization error   0.5* LSB Absolute accuracy   5.0 LSB Note: * Unit Reference values Page 3050 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group 52.6 Section 52 Electrical Characteristics Video Characteristics of A/D Converter for the Input of Video Signals Conditions: VCC = PLLVCC = USBDVCC = USBUVCC = 1.15 to 1.35 V, PVCC = USBDPVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAVCC = 1.15 to 1.35 V, USBAPVCC = 3.0 to 3.6 V, VDAVCC = 3.0 to 3.6 V, VSS = PLLVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS = USBAPVSS = USBUVSS = VDAVSS = 0 V, Ta = 20 to 85 C (regular specifications), 40 to 85 C (wide-range specifications) Note: SH7269 (BGA) Group products do not have the USBDVCC, USBUVCC, USBDPVCC, PLLVSS, USBDVSS, USBAVSS, USBUVSS, USBDPVSS, and USBAPVSS pins. Table 52.30 Characteristics of A/D Converter for the Input of Video Signals (Reference Voltage) Item Min. Typ. Max. Unit Reference voltage (top)  2.0  V Reference voltage (bottom)  1.0  V Test Conditions Table 52.31 Characteristics of A/D Converter for the Input of Video Signals (Clamping) Item Min. Typ. Max. Unit Test Conditions Clamping voltage level  1.0  V Clamping to the VRB voltage Sink current  10  A Source current  1.0  mA Table 52.32 Characteristics of A/D Converter for the Input of Video Signals (PGA-Related) Item Min. Typ. Max. Unit Number of gain steps  32  step Gain step width  0.2  dB Minimum gain  1.835  dB Maximum gain  8.023  dB R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Test Conditions Page 3051 of 3092 SH7268 Group, SH7269 Group Section 52 Electrical Characteristics Table 52.33 Characteristics of A/D Converter for the Input of Video Signals (ADC) Item Min. Typ. Max. Unit Resolution  10  bit A/D conversion range  0.2  Vpp (VRT  VRB)  2 Integral linearity error   ±5.0 LSB ADC  PGA fs  27 MHz Differential linearity error   ±2.0 LSB ADC  PGA fs  27 MHz S/N  54*  dB fin  1MHz, fs  27 MHz PGA_GAIN  01000 S/(N  D)  51*  dB fin  1MHz, fs  27 MHz PGA_GAIN  01000 Note: * Test Conditions Reference value. Page 3052 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Section 53 States and Handling of Pins This section describes pin states in each operating mode and how to handle pins. 53.1 Pin States Table 53.1 shows the pin states in each operating mode. As for the input/output functions, input buffers are listed on the upper column and output buffers on the lower column. In addition, table 53.2 shows the pin states while the bus mastership is released, which differ from the states in the normal state. Table 53.1 Pin States Pin Function Pin State 2 Power-Down State Pin State Retained* Normal State EBUSKEEPE*3(Other (Other than Type Clock Pin Name 6 EXTAL* Power-On Right) Reset*1 I 6 XTAL* CKIO Boot I 0 1 I Power-On Deep Standby Software Standby Reset*4 Mode Mode I/Z* 5 I O/L* 5 O/L*5 O/Z*7 O/Z*7 O O O O/Z*7 O O Other than O/Z*7 O O/Z*7 O/Z*7 O/Z*7   Z Z Z Z 0, 1 mode than States at Right) States at O/Z*7 above AUDIO_CLK 6 AUDIO_X1* 6 AUDIO_X2* System control I 8 I/Z* I I 8 O O 8 O/L* L L AUDIO_XOUT O/L*  O/Z* * O/Z* * L/Z*9 RES I I I I I WDTOVF O  H H H BREQ I   Z Z BACK O  Z Z Z R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 9 16 9 16 Page 3053 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at than States at Right) Power-On Power-On Deep Standby Software Standby Reset*4 Mode Mode    I    I I I I I I I I I I   I/Z* I I   Z I I   O  O/Z* O  O/Z*10 0, 1 O Z O 2 to 5 O  O/Z*10 0 O Z O 1 to 5 O  O/Z*10 0, 1 I/Z Z I/Z O/Z Z O/Z I/Z  O/Z 1 Type Pin Name Right) Reset* 0 Operation MD_BOOT2 to  I mode MD_BOOT0 MD_CLK0  ASEMD NMI control Interrupt Power-Down State 3 IRQ7 (PF19), IRQ6 1 I 12 (PF18), IRQ5 (PF17), IRQ4 (PF16), IRQ3, IRQ2, IRQ1 (PC7, PJ21), IRQ0 (PC5, PJ20) IRQ7 (PG7), IRQ6 (PG6), IRQ5 (PG5), IRQ4 (PG4), IRQ1 (PG1), IRQ0 (PG0) PINT7 to PINT0 User break UBCTRG Z 9 Z 9 O/Z* O/Z*9 O/Z*10 O/Z*10 O/Z*10 O/Z*10 O/Z*10 O/Z*10 O/Z*10 O/Z*10 O/Z*10 O/Z*10 Z Z Z Z  Z Z  Z Z Z I/Z Z I/Z Z Z O/Z Z O/Z Z Z I/Z   Z Z O/Z  Z Z Z controller Address bus A25 to A21, A0 A20 Boot to A2 mode A1 Boot mode Data bus D15 Boot to D0 mode 2 to 5 D31 Boot to mode 1 O/Z*10 O/Z*10 Z Z Z Z D16 0, 2 to 5 Page 3054 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Type Pin Name Bus CS0 than States at Right) Power-On 1 Reset* 0 1 10 Deep Standby Software Standby Reset*4 Mode Mode H/Z* 10 H/Z*10 O Z O 2 to 5 O  H/Z*10 H/Z*10 H/Z*10 O  H/Z*10 H/Z*10 H/Z*10 0, 1 O Z O H/Z*10 H/Z*10 2 to 5 O  H/Z*10 H/Z*10 H/Z*10 RD/WR O  H/Z*10 H/Z*10 H/Z*10 BS O  H/Z*10 H/Z*10 H/Z*10 WAIT I   Z Z O  RAS, CAS O CKE IOIS16 mode CS5 to CS1, CE1A, H/Z* Power-On 0, 1 control Boot Right) Power-Down State 3 CE2A RD Boot mod H/Z*10 e WE3/ICIOWR/AH/ 10 H/Z* H/Z* 10 H/Z*10  O/Z*11 O/Z*11 O/Z*11 O  O/Z*11 O/Z*11 O/Z**11 I   Z Z DQMUU, WE2/ICIORD/DQMUL, WE1/DQMLU/WE, WE0/DQMLL R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3055 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at than States at Right) Power-On 1 Type Pin Name Right) Reset* 0 Direct DREQ0 I   DACK0 O  O/Z* controller TEND0 O  Multi- TCLKA to TCLKD I TIOC0A, TIOC0B, memory access function timer pulse unit 2 TIOC0C (PB3, PJ18), Power-Down State 3 1 9 Power-On Deep Standby Software Standby Reset*4 Mode Mode Z Z O/Z* 9 O/Z*9 O/Z*9 O/Z*9 O/Z*9   Z Z I   O/Z  O/Z* I    O/Z*9 Z 9 Z 9 O/Z* O/Z*9 TIOC0D (PB4, P19), TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D TIOC0C (PG3), TIOC0D (PG4) Realtime clock Serial RTC_X1* 6 O/Z 13 interface with FIFO 13 I O/Z*9 O/Z*9 I/Z* I/Z*13 O/H*13 O/H*13 O/Z*9 O/Z*9  Z Z   I/Z*12 I I   Z Z O/Z  O/Z* I  O/Z I/Z* I I/Z* RTC_X2*6 O/H*13 O O/H*13 TxD7 to TxD0 O/Z  O/Z* RxD7 (PE7, PJ25), I  RxD7 (PC7) I SCK7 to SCK0 communication 12 I/Z* 9 13 RxD6 to RxD0 RTS7, RTS5, RTS1 CTS7, CTS5, CTS1 Page 3056 of 3092 9 9 O/Z* O/Z*9  Z Z  O/Z*9 O/Z*9 O/Z*9 I   Z Z O/Z  O/Z*9 O/Z*9 O/Z*9 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Power-Down State 3 than States at Right) Power-On 1 Deep Standby Software Standby Reset*4 Mode Mode Z Z Pin Name Right) Reset* 0 Renesas MISO1, MISO0 (PJ19) I   O/Z  O/Z* O/Z* O/Z*9 I   Z Z 2, 4, 5 O/Z  O/Z* 3 O/Z   I   O/Z  O/Z* O/Z* O/Z*9 I   Z Z 2, 4, 5 O/Z  O/Z* 3 O/Z   I   O/Z  O/Z* O/Z* O/Z*9 I   Z Z 2, 4, 5 O/Z  O/Z* 3 O/Z   I  O/Z serial peripheral interface MISO0 (PB20) Boot mode MOSI1 (MOSI0), PJ18 MOSI0 (PB19) Boot mode RSPCK1, RSPCK0 (PJ16) RSPCK0 (PB17) Boot 9 9 9 O/Z*9 9 O/Z* 9 O/Z*9 O/Z*9 O/Z*9 Z Z 9 9 O/Z*9 9 O/Z* 9 O/Z*9 O/Z*9 O/Z*9 Z Z 9 O/Z* 9 O/Z*9 O/Z*9 O/Z*9  Z Z  O/Z*9 O/Z*9 O/Z*9 I   Z Z 2, 4, 5 O/Z  O/Z*9 O/Z*9 O/Z*9 3 O/Z   O/Z*9 O/Z*9 I   Z Z O/Z  O/Z*9 O/Z*9 O/Z*9 QSPCLK_1, QSPCLK_0 O/Z  O/Z*9 O/Z*9 O/Z*9 QSSL_1, QSSL_0 O/Z  O/Z*9 O/Z*9 O/Z*9 mode SSL10, SSL00 (PJ17) SSL00 (PB18) Boot mode Renesas 1 Power-On Type QIO3_1, QIO3_0, quad serial QIO2_1,QIO2_0, peripheral QMI_1/QIO1_1, interface QMI_1/QIO0_0, 9 O/Z*9 O/Z*9 QMO_1/QIO0_1, QMO_0/QIO0_0 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3057 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Power-Down State 3 than States at Right) Power-On 1 Type Pin Name Right) Reset* 0 SPI multi SPBIO3_1, SPBIO3_0, I   I/O bus SPBIO2_1,SPBIO2_0, SPBMI_1/SPBIO1_1, O/Z  O/Z* controller SPBCLK, SPBSSL O/Z  SCL3 to SCL0 I 1 9 Power-On Deep Standby Software Standby Reset*4 Mode Mode Z Z O/Z* 9 O/Z*9 O/Z*9 O/Z*9 O/Z*9   Z Z O/Z  Z Z Z I   Z Z O/Z  Z SSITxD0 O  O/Z* SSIRxD0 I  SSIDATA5 to SSIDATA1 I SPBMI_0/SPBIO1_0, SPBMO_1/SPBIO0_1, SPBMO_0/SPBIO0_0 I2C bus interface 3 SDA3 to SDA0 Serial sound Z 9 Z 9 O/Z* O/Z*9  Z Z   Z Z O/Z  O/Z*9 O/Z*9 O/Z*9 I   Z Z O/Z  O/Z*9 O/Z*9 O/Z*9 I   O/Z*12 Z O/Z  O/Z*9 O/Z*9 O/Z*9 I   Z Z O/Z  O/Z* I   O/Z  O/Z* I   O/Z  O/Z* I   O/Z  O/Z* SIOFTxD O/Z  SIOFRxD I  interface SSISCK5, SSISCK4, SSISCK2 to SSISCK0 SSISCK3 SSIWS5, SSIWS4, SSIWS2 to SSIWS0 SSIWS3 Serial I/O SIOFSCK with FIFO SIOFSYNC Page 3058 of 3092 9 9 9 9 9 O/Z* O/Z*9 O/Z*12 Z 9 O/Z* O/Z*9 Z Z 9 O/Z* O/Z*9 Z Z O/Z* 9 O/Z*9 O/Z*9 O/Z*9 O/Z*9  Z Z R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Type Pin Name Controller area network IEBus controller Renesas SPDIF than States at Right) Power-On 1 0 1 Power-On Deep Standby Software Standby Reset*4 Mode Mode Right) Reset* CTx2 to CTx0 O  O/Z* O/Z* O/Z*9 CRx2 (PJ20), CRx1, I   I/Z*12 I I   Z Z IETxD O  O/Z* O/Z* O/Z*9 IERxD I   Z Z SPDIF_OUT O  O/Z* O/Z* O/Z*9 SPDIF_IN I   Z Z AN7 to AN0 I   Z Z ADTRG I   Z I   O  O/Z* O  O/Z*9 2 O   0, 1, 3 to O  O/Z*9 2 O   0, 1, 3 to O  O/Z*9 2 O   0, 1, 3 to O  O/Z*9 O   I  O/Z O/Z 9 9 CRx0 CRx2 (PB21) TM Power-Down State 3 9 9 9 9 interface A/D converter NAND flash FRB FCE Z 12 I/Z* 9 I O/Z* 9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9  Z Z  O/Z*9 O/Z*9 O/Z*9   O/Z*9 O/Z*9 memory controller FALE Boot 0, 1, 3 to mode 5 FRE Boot O/Z*9 mode 5 FCLE Boot O/Z*9 mode 5 FWE Boot O/Z*9 mode 5 2 NAF7 to NAF0 Boot 0, 1, 3 to O/Z*9 mode 5 2 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 O/Z*9 Page 3059 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Power-Down State 3 than States at Right) Power-On Power-On Deep Standby Software Standby Reset*4 Mode Mode I/Z Z I/Z Z O/Z Z O/Z I I I I I REFRIN I I I I I USB_X1*6 I I I Z Z USB_X2*6 O O O L L Video LCD_DATA23 to O  O/Z*9 O/Z*9 O/Z*9 display LCD_DATA0 O  O/Z*9 O/Z*9 O/Z*9 LCD_CLK O  O/Z*9 O/Z*9 O/Z*9 LCD_EXTCLK I   Z Z DV_CLK I   Z Z DV_DATA23 to I   I/Z*12 I I   Z Z I   Z Z 1 Type Pin Name Right) Reset* 0 USB 2.0 DP, DM I/Z Z O/Z VBUS host/ 1 function module controller 4 LCD_TCON6 to LCD_TCON0 DV_DATA20 DV_DATA19 to DV_DATA0 DV_VSYNC, DV_HSYNC Page 3060 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Type Pin Name Power-Down State 3 than States at Right) Power-On 1 Deep Standby Software Standby Mode Mode 0 to 3 O  O/Z* 4 O   SD_CLK_1 O  SD_CLD_0 I  0 to 3 O/Z  O/Z* 4 O/Z   I   O/Z  O/Z* O/Z* O/Z*9 I   Z Z 0 to 3 O/Z  O/Z* 4 O/Z   I   0 to 3 O/Z  O/Z* 4 O/Z   I  O/Z SD_CD_0 SD_ Boot interface CLK_ mode 1 Reset*4 Reset* S/D host 0 Power-On Right) 9 O/Z* 9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 O/Z*9  Z Z O/Z*9 0 Boot mode SD_CLD_1 SD_D3_0, SD_D2_0 Boot mode SD_D1_0, SD_D0_0 9 O/Z*9 9 O/Z* 9 O/Z*9 O/Z*9 O/Z*9 Z Z 9 9 O/Z*9 O/Z*9 O/Z*9 O/Z*9 I/Z*12 I O/Z* 9 O/Z*9 O/Z*9 O/Z*9  Z Z  O/Z*9 O/Z*9 O/Z*9 I   I/Z*12 I SD_CD_1 I   Z Z SD_WP_0 I   I/Z*12 I SD_WP_1 I   Z Z Boot mode SD_D3_1 to SD_D0_1 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 9 O/Z* 9 O/Z*9 Page 3061 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Type Pin Name than States at Right) Power-On 1 Right) Reset* 0 0 to 3 O  O/Z* 5 O   I  0 to 3 O/Z 5 1 Deep Standby Software Standby Reset*4 Mode Mode O/Z* O/Z*9 O/Z*9 O/Z*9  Z Z  O/Z*9 O/Z*9 O/Z*9 O/Z   O/Z*9 O/Z*9 I   Z Z 0 to 3 O/Z  O/Z*9 O/Z*9 O/Z*9 5 O/Z   O/Z*9 O/Z*9 I   I/Z*12 I 0 to 3 O/Z  O/Z* 5 O/Z   I   O/Z  O/Z* I   SGOUT_3 to SGOUT_0 O  O/Z* VIDEO_X1*6 I I VIDEO_X2* O VIN1, VIN2 I MMC_ Boot interface CLK mode MMC_CMD Boot mode MMC_D3, MMC_D2 Boot mode MMC_D1, MMC_D0 Boot mode MMC_D7 to MMC_D4 MMC_CD 9 Power-On 9 MMC host Sound Power-Down State 3 O/Z*9 O/Z*9 O/Z*9 9 9 O/Z*9 9 9 9 O/Z* O/Z* O/Z*9 O/Z*9 Z Z 9 O/Z* O/Z*9 I/Z*12 I 9 O/Z* O/Z*9 I Z Z O O L L Z I Z I generator Video decoder 6 Page 3062 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at than States at Right) Power-On 1 Type Pin Name Right) Reset* 0 General PA1, PA0 I  I O/Z  O/Z* I Z I O/Z Z O/Z*9 I Z I 3 O/Z Z O/Z 2, 4, 5 O/Z Z O/Z*9 I Z I O/Z Z O/Z*9 I Z I purpose Power-Down State 3 1 Power-On Deep Standby Software Standby Reset*4 Mode Mode Z Z I 9 9 O/Z* O/Z*9 Z Z O/Z*9 O/Z*9 Z Z O/Z*9 O/Z*9 O/Z*9 O/Z*9 Z Z O/Z*9 O/Z*9 I/O ports PB22, PB21, PB16 to PB1 PB20 to PB17 Boot mode PC8, PC6, PC4 to PC1 PC7, PC5 PC0 PD15 to PD4 Boot mode O/Z*9 Z I/Z* 9 O/Z Z O/Z* I  I O/Z  O/Z* I Z I Z Z O/Z 3 to 5 O/Z Z O/Z*9 I Z I PF23 to PF20 Z Z O/Z* I Z I O/Z Z O/Z I Z Z O/Z Z O/Z* 4, 5 O/Z Z O/Z O/Z*9 Z I O/Z* O/Z*9 Z Z 9 O/Z*9 O/Z*9 O/Z*9 Z Z 9 O/Z* O/Z*9 Z Z Z Z Z Z Z 9 O/Z*9 I O/Z* O/Z* 9 0 to 3 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 O/Z* O/Z 12 I/Z* 9 9 Z 12 9 9 O/Z PE7 to PE0 mode Z 2 PD3 to PD0 Boot Z Z O/Z* 9 O/Z*9 O/Z*9 O/Z*9 Page 3063 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Type General Pin Name Right) PF19, PF18 purpose Boot I/O ports mode I Boot mode than States at Right) Power-On 1 Reset* Z 0 I 4, 5 O/Z Z O/Z I Z I 0 to 3, 5 O/Z Z O/Z*9 4 O/Z Z O/Z I Z I O/Z Z O/Z*9 Z I PG3, PG2 Z O/Z* I Z I O/Z Z O/Z* PH7 to PH0 I Z I PJ31 to PJ24, PJ19 to I Z I PJ23 to PJ20 O/Z Z O/Z* I Z I O/Z Page 3064 of 3092 Z O/Z* Software Standby Mode Mode I/Z* O/Z* O/Z Deep Standby Reset*4 9 Z PG27 to PG4, PG1, PG0 I Power-On 12 O/Z PF15 to PF0 PJ0 1 0 to 3 PF17, PF16 Power-Down State 3 O/Z*9 I/Z*12 O/Z*9 Z Z 9 I/Z* 9 I O/Z* 9 O/Z*9 O/Z*9 O/Z*9 I/Z*12 I O/Z*9 O/Z*9 O/Z*9 O/Z*9 Z Z O/Z*9 O/Z*9 Z Z 9 I/Z*12 O/Z* O/Z* I/Z*12 I 9 9 O/Z* O/Z*9 Z Z I Z Z 9 Z 9 I/Z*12 9 12 O/Z* O/Z*9 I/Z*12 I 9 O/Z* O/Z*9 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Function Pin State Pin State Retained*2 Normal State EBUSKEEPE* (Other (Other than States at Type Pin Name Power-Down State 3 than States at Right) Power-On 1 Deep Standby Software Standby Mode Mode O  O/Z* O/Z* O/Z*9 TRST I I I Z I TCK I I I Z I TDI I PWM1A, PWM1B, control PWM1C, PWM1D, 1 Reset*4 Reset* Motor 0 Power-On Right) 9 9 PWM timer PWM1E, PWM1F, PWM1G, PWM1H, PWM2A, PWM2B, PWM2C, PWM2D, PWM2E, PWM2F, PWM2G, PWM2H User debugging interface* 15 Emulator *15 I 14 I 14 Z I O/Z* O/Z*14 I Z I          AUDATA3 to AUDATA0      ASEBRKAK/ASEBRK Z Z Z Z Z TDO O/Z* O/Z* O/Z* TMS I I AUDSYNC  AUDCK R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 14 14 Page 3065 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Table 53.2 Pin States while the Bus Mastership is Released Pin Function Pin State Type Pin Name Bus Mastership Release Clock CKIO O/Z*7 System control BREQ I BACK L Address bus A25 to A0 Z Data bus D31 to D0 Z Bus control CS5 to CS0, CE1A, CE2A Z RD Z RD/WR Z BS Z WAIT Z WE3/ICIOWR/AH/DQMUU, WE2/ICIORD/DQMUL, WE1/DQMLU/WE, WE0/DQMLL Z RAS, CAS O/Z*11 CKE O/Z*11 FALE Z FRE Z FCLE Z FWE Z NAF7 to NAF0 Z NAND flash memory controller [Legend] I: Input O: Output H: High-level output L: Low-level output Z: High-impedance : Condition under which the pin function is not selectable Notes: 1. Indicates the power-on reset by low-level input to the RES pin. The pin states after a power-on reset by the user debugging interface reset assert command or the watchdog timer overflow is the same as the initial pin states at normal operation (see section 48, General Purpose I/O Ports). Page 3066 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins 2. After the chip has shifted to the power-on reset state from deep standby mode by the input on the NMI pin and so on, or by the realtime clock alarm interrupt, the pins retain the state until the IOKEEP bit in the deep standby cancel source flag register (DSFR) is cleared (see section 49, Power-Down Modes). 3. The EBUSKEEPE bit in deep standby control register (DSTCR) (see section 49, PowerDown Modes). 4. This LSI enters the power-on reset state for a certain period after recovery from deep standby control mode (see section 49, Power-Down Modes). 5. Depends on the setting of the RCKSEL bit in the realtime clock control register 5 (RCR5) (see section 15, Realtime Clock). 6. When pins for the connection with a crystal resonator are not used, the input pins (EXTAL, RTC_X1, AUDIO_X1, USB_X1, and VIDEO_X1) must be fixed (pull-up/down resistor, power supply, or ground.) and the output pins (XTAL, RTC_X2, AUDIO_X2, USB_X2, and VIDEO_X2) must be open. 7. Depends on the setting of the CKOEN bit in the frequency control register (FRQCR) of the clock pulse generator (see section 5, Clock Pulse Generator). 8. Depends on the setting of the AXTALE bit in the software reset control register (SWRSTCR) (see section 49, Power-Down Modes). 9. Depends on the setting of the HIZ bit in the standby control register 3 (STBCR3) (see section 49, Power-Down Modes). 10. Depends on the setting of the HIZMEM bit in the common control register (CMNCR) of the bus state controller (see section 10, Bus State Controller). 11. Depends on the setting of the HIZCNT bit in the common control register (CMNCR) of the bus state controller (see section 10, Bus State Controller). 12. Depends on the setting of the corresponding bit in the deep standby cancel source select register (DSSSR) (see section 49, Power-Down Modes). 13. Depends on the setting of the RTCEN bit in the realtime clock control register 2 (RCR2) (see section 15, Realtime Clock). 14. Z when the TAP controller of the user debugging interface is neither the Shift-DR nor Shift-IR state. 15. These are the pin states in product chip mode (ASEMD  H). See the Emulation Manual for the pin states in ASE mode (ASEMD  L). 16. When this is an output, the output is fixed to either the High or Low level. There is no oscillation. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3067 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins 53.2 Treatment of Unused Pins How unused pins are to be handled is indicated below. Table 53.3 Handling of Unused Pins (Except for User Debugging Interface and Emulator Interface Pins) Pin Name Handling NMI Fix this pin at a high level (pull up or connect to a power supply). DP, DM, VBUS  Connect these pins to USBDPVss (SH7268/SH7269 (QFP)).  Connect them to Vss (SH7269 (BGA)). REFRIN Connect this pin, via a 5.6 k20 resistor, to USBAPVcc. 1.2-V power dedicated to the USB (USBAVcc, USBDVcc, USBUVcc) Supply power at 1.2 V. 3.3-V power dedicated to the USB (USBAPVcc, USBDPVcc) Supply power at 3.3 V. Dedicated USB ground (USBAPVss, USBDPVss, USBAVss, USBDVss, USBUVss) Connect to ground. AVref Connect this pin to AVcc. Dedicated A/D power (AVcc) Supply power at 3.3 V. Dedicated A/D ground (AVss) Connect to ground. Dedicated A/D power for input of video signals (VDAVcc) Supply power at 3.3 V. Note: SH7269 (BGA) Group products do not have pins USBDVcc and USBUVcc. Note: SH7269 (BGA) Group products do not have the USBDPVcc pin. Note: SH7269 (BGA) Group products do not have the dedicated USB ground pins. Dedicated A/D ground for input Connect to ground. of video signals (VDAVss) BIAS Connect this pin, via a 24 k ± 10 resistor, to VDAVss. VIN1, VIN2, VRT, VRB Open-circuit Dedicated input pins other than Fix the level on the pins (pull them up or down, or connect them to the power supply or ground level). those listed above Page 3068 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Name Handling Input/output pins other than those listed above Make the input-pin settings and then fix the level (pull them up or down); alternatively, make the output-pin settings and leave the pins open-circuit. Dedicated output pins Open-circuit Note: We recommend that the values of pull-up or pull-down resistors are in the range from 4.7 k to 100 k. Table 53.4 Handling of Pins (when User Debugging Interface is not Used in Product Chip Mode) Pin Handling ASEMD Fix this pin at a high level (pull up or connect to the power supply). TRST Fix this pin at a low level (pull down or connect to the ground level). TCK, TMS, TDI Fix the level on the pins (pull them up or down, or connect them to the power supply or ground level). TDO, ASEBRKAK/ASEBRK Open-circuit Notes: 1. When using the user debugging interface, handle these pins as described in the manual for the emulator. 2. We recommend that the values of pull-up or pull-down resistors are in the range from 4.7 k to 100 k. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3069 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins 53.3 Handling of Pins in Deep Standby Mode How pins are to be handled in deep standby mode is indicated below. For the states of pins in deep standby mode, refer to the corresponding items under section, 53.1, Pin States. Handling of unused pins as described under section 53.2, Treatment of Unused Pins, also applies in deep standby mode. Table 53.5 Handling of Pins in Deep Standby Mode Pin Handling 1.2-V power (Vcc, USBDVcc, USBUVcc, USBAVcc) Supply power at 1.2 V. 3.3-V power (PVcc, AVcc, USBDPVcc, USBAPVcc, PLLVcc, VDAVcc) Supply power at 3.3 V. Ground (Vss, PLLVss, USBDVss, USBUVss, USBAVss, AVss USBDPVss, USBAPVss, VDAVss) Connect to ground. VBUS Fix the level on this pin (pull it up or down, or connect it to the power supply or ground level) or open circuit. However, note that current as indicated in table 52.2, DC Characteristics (2) [Current Consumption] SH7268/SH7269 (QFP) will be drawn by the pin fixed to the high level. REFRIN Connect this pin to USBAPVss via 5.6 k ± 1 resistor (SH7268 and SH7269 products in QFP packages). Note: SH7269 (BGA) Group products do not have pins USBDVcc and USBUVcc. Note: SH7269 (BGA) Group products do not have the USBDPVcc pin. Note: SH7269 (BGA) Group products do not have the PLLVss, USBDVss, USBAVss, USBUVss, USBDPVss, and USBAPVss pins. Connect this pin to Vss via 5.6 kΩ ± 1% resistor (SH7269 products in BGA packages). DP, DM Fix the level on the pins (pull them up or down, or connect them to the power supply or ground level) or open circuit. AVref Fix the level on this pin (from 3.0 V to AVcc) BIAS Connect this pin to VDAVss via 24 k ± 1 resistor. VRT, VRB Connect these pins to VDAVss via 0.1-F capacitor. VIN1, VIN2 Fix the level on the pins (pull them up or down, or connect them to the power supply or ground level) or open circuit. Page 3070 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Pin Handling EXTAL, RTC_X1, AUDIO_X1, USB_X1, VIDEOX1 Connect the pins to the crystal oscillator or the clock-input signal, or to a fixed level (pull them up or down, or connect them to the power supply or ground level) XTAL, RTC_X2, AUDIO_X2, USB_X2, VIDEO_X2 Connect the pins to the crystal oscillator or open circuit. Dedicated input pins other than those Fix the level on the pins (pull them up or down, or connect listed above them to the power supply or ground level). Input/output pins (other than those listed above) in the input state Fix the level on the pins (pull them up or down). Input/output pins (other than those listed above) in the high-impedance state Fix the level on the pins (pull them up or down) or open circuit. Input/output pins (other than those listed above) in the output state Open-circuit Dedicated output pins other than those listed above Open-circuit Note: We recommend that the values of pull-up or pull-down resistors are in the range from 4.7 k to 100 k. R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3071 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins 53.4 Recommended Combination of Bypass Capacitor Mount a multilayer ceramic capacitor between a pair of the power supply pins as a bypass capacitor. These capacitors must be placed as close as the power supply pins of the LSI. The capacitance of the capacitors should be used 0.1 F to 0.33 F (recommended values). For details of the capacitor related to the crystal resonator, see section 5, Clock Pulse Generator. PLQP0208KB-A Top view 1 PC1 2 PVcc 3 PC2 4 PC3 5 PC4 6 PC5 7 PVcc 8 PC6 9 Vss 10 PC7 11 Vcc 12 PC8 13 PB1 14 PB2 15 PB3 16 Vss 17 PB4 18 Vcc 19 PB5 20 PB6 21 PVcc 22 PB7 23 Vss 24 PB8 25 Vcc 26 PB9 27 PB10 28 PB11 29 PB12 30 Vss 31 PB13 32 Vcc 33 PB14 34 PB15 35 PVcc 36 PB16 37 Vss 38 PB17 39 Vcc 40 PB18 41 PB19 42 PB20 43 Vss 44 PB21 45 Vcc 46 PB22 47 PC0 48 PVcc 49 CKIO 50 Vss 51 PA0 52 Vcc 157 PF0 158 PVcc 159 PF1 160 Vss 161 PF2 162 PF3 163 PF4 164 PF5 165 PF6 166 PF7 167 PF8 168 PF9 169 PVcc 170 PF10 171 Vss 172 PF11 173 PF12 174 PF13 175 PF14 176 PF15 177 PF16 178 PF17 179 PF18 180 PVcc 181 PF19 182 Vss 183 PF20 184 Vcc 185 PF21 186 PF22 187 PF23 188 PD0 189 PD1 190 PD2 191 PD3 192 PVcc 193 Vss 194 PD4 195 PD5 196 PD6 197 PD7 198 PD8 199 PD9 200 PD10 201 PD11 202 PVcc 203 PD12 204 Vss 205 PD13 206 PD14 207 PD15 208 MD_CLK0 PG27 156 PG26 155 PG25 154 PG24 153 PG23 152 PG22 151 Vcc 150 PG21 149 Vss 148 PG20 147 PVcc 146 PG19 145 PG18 144 Vcc 143 PG17 142 Vss 141 PG16 140 PG15 139 PG14 138 PG13 137 Vcc 136 PG12 135 Vss 134 PG11 133 PVcc 132 PG10 131 PG9 130 Vcc 129 PG8 128 Vss 127 PG7 126 PG6 125 PG5 124 PG4 123 Vcc 122 PG3 121 Vss 120 AUDIO_X1 119 AUDIO_X2 118 PVcc 117 PG2 116 Vss 115 PG1 114 Vcc 113 PG0 112 Vss 111 TCK 110 TMS 109 TDI 108 TDO 107 ASEBRKAK/ASEBRK 106 TRST 105 Figures 53.1 and 53.2 are examples of externally allocated capacitors in the SH7268 Group and SH7269 (QFP) Group, respectively. Table 53.6 lists the correspondences between power-supply and ground pins for the connection of external capacitors in the case of SH7269 Group products (in BGA). AVref 104 AVcc 103 AVss 102 PH5 101 PH4 100 PH3 99 PH2 98 PH1 97 PH0 96 BIAS 95 VRB 94 VRT 93 VIN2 92 VIN1 91 VDAVss 90 VDAVcc 89 Vss 88 VIDEO_X2 87 VIDEO_X1 86 PVcc 85 USB_X2 84 USB_X1 83 USBUVss 82 USBUVcc 81 USBAVss 80 USBAVcc 79 USBAPVcc 78 USBAPVss 77 REFRIN 76 USBDVss 75 USBDVcc 74 VBUS 73 DP 72 DM 71 USBDPVss 70 USBDPVcc 69 RES 68 PLLVss 67 PLLVss 66 XTAL 65 EXTAL 64 PLLVcc 63 Vcc 62 ASEMD 61 Vss 60 NMI 59 PVcc 58 PE3 57 PE2 56 PE1 55 PE0 54 PA1 53 Figure 53.1 Example of Externally Allocated Capacitors in the SH7268 Group Page 3072 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group PG27 192 PG26 191 PG25 190 PG24 189 PG23 188 PG22 187 Vcc 186 PG21 185 Vss 184 PG20 183 PVcc 182 PG19 181 PG18 180 PJ9 179 PJ8 178 PJ7 177 Vcc 176 PG17 175 Vss 174 PJ6 173 PVcc 172 PJ5 171 PG16 170 PG15 169 PG14 168 PG13 167 Vcc 166 PG12 165 Vss 164 PG11 163 PVcc 162 PG10 161 PG9 160 PJ4 159 PJ3 158 PJ2 157 Vcc 156 PG8 155 Vss 154 PJ1 153 PVcc 152 PJ0 151 PG7 150 PG6 149 PG5 148 PG4 147 Vcc 146 PG3 145 Vss 144 AUDIO_X1 143 AUDIO_X2 142 PVcc 141 PG2 140 Vss 139 PG1 138 Vcc 137 PG0 136 Vss 135 TCK 134 TMS 133 TDI 132 TDO 131 ASEBRKAK/ASEBRK 130 TRST 129 Section 53 States and Handling of Pins PLQP0256LB-A Top view AVref 128 PH7 127 AVcc 126 PH6 125 AVss 124 PH5 123 PH4 122 PH3 121 PH2 120 PH1 119 PH0 118 BIAS 117 VRB 116 VRT 115 VIN2 114 VIN1 113 VDAVss 112 VDAVcc 111 Vss 110 VIDEO_X2 109 VIDEO_X1 108 PVcc 107 USB_X2 106 USB_X1 105 USBUVss 104 USBUVcc 103 USBAVss 102 USBAVcc 101 USBAPVcc 100 USBAPVss 99 REFRIN 98 USBDVss 97 USBDVcc 96 VBUS 95 DP 94 DM 93 USBDPVss 92 USBDPVcc 91 RTC_X2 90 RTC_X1 89 RES 88 PLLVss 87 PLLVss 86 XTAL 85 EXTAL 84 PLLVcc 83 Vcc 82 ASEMD 81 Vss 80 NMI 79 PVcc 78 PE7 77 PE6 76 PE5 75 PE4 74 PE3 73 PE2 72 PE1 71 PE0 70 PJ31 69 PJ30 68 PJ29 67 PJ28 66 PA1 65 1 PC1 2 PVcc 3 PC2 4 PC3 5 PC4 6 PC5 7 PVcc 8 PC6 9 Vss 10 PC7 11 Vcc 12 PC8 13 PB1 14 PB2 15 PB3 16 PJ14 17 PVcc 18 PJ15 19 Vss 20 PB4 21 Vcc 22 PJ16 23 PJ17 24 PJ18 25 PB5 26 PB6 27 PVcc 28 PB7 29 Vss 30 PB8 31 Vcc 32 PB9 33 PB10 34 PB11 35 PB12 36 PJ19 37 PVcc 38 PJ20 39 Vss 40 PB13 41 Vcc 42 PJ21 43 PJ22 44 PJ23 45 PB14 46 PB15 47 PVcc 48 PB16 49 Vss 50 PB17 51 Vcc 52 PB18 53 PB19 54 PB20 55 Vss 56 PB21 57 Vcc 58 PB22 59 PC0 60 PVcc 61 CKIO 62 Vss 63 PA0 64 Vcc 193 PF0 194 PVcc 195 PF1 196 Vss 197 PF2 198 PF3 199 PF4 200 PF5 201 PF6 202 PF7 203 PF8 204 PF9 205 PVcc 206 PF10 207 Vss 208 PF11 209 PF12 210 PF13 211 PF14 212 PF15 213 PVcc 214 PJ10 215 Vss 216 PF16 217 PF17 218 PF18 219 PJ11 220 PJ12 221 PJ13 222 PVcc 223 PF19 224 Vss 225 PF20 226 Vcc 227 PF21 228 PF22 229 PF23 230 PD0 231 PVcc 232 PJ24 233 Vss 234 PD1 235 PD2 236 PD3 237 PJ25 238 PJ26 239 PJ27 240 PVcc 241 Vss 242 PD4 243 PD5 244 PD6 245 PD7 246 PD8 247 PD9 248 PD10 249 PD11 250 PVcc 251 PD12 252 Vss 253 PD13 254 PD14 255 PD15 256 MD_CLK0 Figure 53.2 Example of Externally Allocated Capacitors in the SH7269 (QFP) Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3073 of 3092 SH7268 Group, SH7269 Group Section 53 States and Handling of Pins Table 53.6 Correspondences between Power-Supply and Ground Pins for the Connection of External Capacitors: SH7269 Group in BGA Power Supply Ground Pin No. Pin Name Pin No. Pin Name A2, B20, C19, D5, D6, D18, E17, H4, J4, M17, N17, T4, U3, U10, V2, V10, W1 Vcc Vss A19, B1, B18, C2, D2, D3, D11, D12, D15, D16, E4, J17, J18, N3, N4, T17, U18, V19, W20, Y11 PVcc U6 PLLVcc A1, A20, B2, B19, C3, C10, C18, D4, D10, D17, J9, J10, J11, J12, K4, K9, K10, K11, K12, K17, L4, L9, L10, L11, L12, L17, M4, M9, M10, M11, M12, U1, U4, U8, U9, U12, U17, V3, V9, V13, V18, W2, W11, W19, Y1, Y7, Y13, Y20 V11 USBAPVcc V12 USBAVcc U13 VDAVcc U15 VDAVss Y18 AVcc W18 AVss Y19 AVref Page 3074 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group Appendix Appendix A. Package Dimensions 30.0±0.2 28.0±0.1 156 105 104 0.5 28.0±0.1 30.0±0.2 157 208 53 1 0.50±0.15 * 1.25 0.10±0.05 1.00 *0.145±0.05 0.125 0.08 M 1.70 MAX 0.20 1.40 *0.22±0.05 52 0.08 Dimension including the plating thickness Base material dimension 0 to 8° UNIT: mm Package code JEITA code JEDEC code Mass (g) PLQP0208KB-A Conforms to EDR-7311 — 2.7 Figure A.1 SH7268 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3075 of 3092 SH7268 Group, SH7269 Group Appendix 30.0 ± 0.2 28 192 129 128 1.40 30.0 ± 0.2 193 256 65 0.08 0.10 ± 0.05 0.4 5 *0.145 ± 0.0 4 0.125 ± 0.0 0.07 M 1.40 *0.18 ± 0.05 0.16 ± 0.04 64 1.70Max 1 1.0 0.5 ± 0.1 0 to 8° UNIT: mm * Dimension including the plating thickness Base material dimension Package code JEITA code JEDEC code Mass (g) PLQP0256LB-A Conforms to EDR-7311 — 2.7 Figure A.2 SH7269 (QFP Version) Page 3076 of 3092 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 0.20 C B SH7268 Group, SH7269 Group Appendix 17.0 20 0.20 C A 18 16 17 14 15 12 13 10 11 8 9 6 4 7 5 2 3 1 A 0.8 19 B C D E F G H B 17.0 J K L M N P R T 0.9 U V W Y 0.8 A 0.9 4× 0.15 272 × φ0.50±0.05 0.20 C φ0.08 0.4±0.05 0.10 C M C AB 1.90 Max C UNIT: mm Package Code PRBG0272GA-A JEDEC ⎯ JEITA ⎯ Mass (reference value) 0.90g Figure A.3 SH7269 (BGA Version) R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Page 3077 of 3092 Appendix Page 3078 of 3092 SH7268 Group, SH7269 Group R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Index Numeries (Potential) time master .......................... 1241 16-bit/32-bit displacement ........................ 67 A A/D conversion time (multi mode and scan mode)................. 1456 A/D conversion timing ......................... 1455 A/D converter ....................................... 1437 A/D converter activation......................... 629 A/D converter characteristics................ 3050 A/D converter start request delaying function .................................... 622 A/D converter timing ............................ 3032 Absolute address ....................................... 67 Absolute address accessing....................... 67 Absolute maximum ratings ................... 2961 AC characteristics ................................. 2974 AC characteristics measurement conditions ............................................. 3049 Access size and data alignment .............. 323 Access wait control ................................. 335 Address array .................................. 248, 262 Address array read .................................. 262 Address errors ......................................... 152 Address map ........................................... 272 Address multiplexing .............................. 346 Address spaces of on-chip data retention RAM ...................................... 2560 Address spaces of on-chip high-speed RAM................................... 2559 Address spaces of on-chip large-capacity RAM.............................. 2560 Address-array write (associative operation) ............................ 263 Addressing modes..................................... 68 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Analog input pin ratings........................ 1462 Arithmetic operation instructions.............. 87 Auto attenuator function ....................... 2478 Automatic decoding stop function ........ 1427 Auto-refreshing ....................................... 373 Auto-request mode .................................. 453 B Bank active ............................................. 366 Banked register and input/output of banks ................................................... 217 Baud rate generator ............................... 1139 Bit manipulation instructions .................... 98 Bit synchronous circuit ......................... 1059 Block diagram of this LSI ......................... 17 Boot mode ............................................... 115 Boundary scan....................................... 2748 Branch instructions ................................... 92 Break detection and processing............... 816 Break on data access cycle ...................... 241 Break on instruction fetch cycle.............. 240 Buffering format ................................... 1428 Burst mode .............................................. 467 Burst read ................................................ 358 Burst ROM (clocked asynchronous) interface ............ 385 Burst ROM (clocked synchronous) interface ............. 398 Burst write............................................... 363 Bus arbitration......................................... 407 Bus state controller ................................. 267 Bus timing ............................................. 2981 Bus-released state.................................... 100 Page 3079 of 3092 C Cache ...................................................... 247 Cache operations .................................... 260 Calculating exception handling vector table addresses ............................. 146 CAN bus interface ................................ 1255 CAN interface ....................................... 1161 Canceling software standby mode (watchdog timer) .................................... 714 Cascaded operation ................................. 563 Caution on period setting ........................ 643 CD-ROM decoder ................................ 1369 Changing the division ratio..................... 135 Changing the frequency .......................... 135 Clock frequency control circuit .............. 127 Clock operating modes ........................... 130 Clock pulse generator ............................. 125 Clock timing ......................................... 2974 Clocked synchronous serial format ...... 1049 CMCNT count timing ............................. 699 Coherency of cache and external memory or large-capacity on-chip RAM .............. 261 Command access mode ........................ 1495 Communications protocol..................... 1267 Compare match timer ............................. 693 Complementary PWM mode .................. 583 Conditions for determining number of idle cycles ............................................... 400 Configuration mode .............................. 1105 Configuration of controller area network ................................................. 1230 Conflict between byte-write and count-up processes of CMCNT .............. 704 Conflict between word-write and count-up processes of CMCNT .............. 703 Conflict between write and compare-match processes of CMCNT .... 702 Control signal timing ............................ 2979 Controller area network ........................ 1157 Page 3080 of 3092 Controller area network control registers..................................... 1180 Controller area network interrupt sources .................................... 1253 Controller area network mailbox registers ................................... 1201 Controller area network memory map ......................................... 1163 Controller area network timer registers ................................................. 1215 CPU .......................................................... 57 Crystal oscillator ..................................... 127 CSn assert period expansion ................... 337 Cycle steal mode ..................................... 466 D Data array........................................ 248, 263 Data array read ........................................ 263 Data array write ...................................... 264 Data format ............................................. 858 Data format in registers............................. 62 Data formats in memory ........................... 62 Data transfer instructions .......................... 83 Data transfer with interrupt request signals ......................................... 221 DC characteristics ................................. 2963 Deep power-down mode ......................... 384 Deep standby mode ............................... 2725 Definitions of A/D conversion accuracy ................................................ 1459 Delayed branch instructions ...................... 65 Denormalized numbers ........................... 106 Direct memory access controller............. 413 Direct memory access controller interface ................................................ 1254 Direct memory access controller timing .................................................... 3013 Displacement accessing ............................ 67 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Display out comparison unit (DISCOM) ..................................... 2331 Divider 2 ................................................. 127 DMA transfer flowchart ......................... 452 DREQ pin sampling timing .................... 470 Dual address mode.................................. 462 Dual-SPI/Quad-SPI mode ....................... 946 Format of double-precision floating-point number ............................. 102 Format of single-precision foating-point number .............................. 102 FPU exception sources ............................ 112 FPU-related CPU instructions ................... 97 Full-scale error ...................................... 1459 E G ECC correction ..................................... 1426 EDC checking ....................................... 1427 Effective address calculation .................... 68 Electrical characteristics ....................... 2961 Encoding ............................................... 2404 Endian ..................................................... 323 Endian conversion for data in the input stream ................................ 1420 Equation for getting SCBRR value ......... 776 Error detection function .......................... 870 Error marker ......................................... 2420 Example of time triggered system ........ 1245 Exception handling ................................. 141 Exception handling state ......................... 100 Exception handling vector table ............. 144 Exception source generation immediately after delayed branch instruction .............. 161 Exceptions triggered by instructions....... 157 External request mode ............................ 453 External trigger input timing ................ 1457 General illegal instructions ..................... 159 General purpose I/O ports timing.......... 3046 General registers ....................................... 57 Global base register (GBR) ....................... 59 F Features of this LSI..................................... 1 Floating point operation instructions ...... 160 Floating-point operation instructions ........ 95 Floating-point ranges .............................. 104 Floating-point registers ........................... 107 Floating-point unit (FPU) ....................... 101 Flow of the user break operation ............ 239 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 H Halt mode .............................................. 1231 Huffman coded segment error............... 2421 Huffman table specification .................. 2410 I I2C bus format ...................................... 1040 I2C bus interface 3 ................................. 1021 I2C bus interface 3 timing ..................... 3026 IBUF interrupt....................................... 1433 ID reorder .............................................. 1181 IEBus bit format.................................... 1278 IEBus communications protocol ........... 1263 IEBus controller ................................ 1261 IERR interrupt....................................... 1433 Image renderer (IMR-LS) ..................... 2329 Immediate data .......................................... 66 Immediate data accessing.......................... 66 Immediate data format .............................. 63 Influences on absolute precision ........... 1463 Initial values of control registers ............... 61 Initial values of general registers .............. 61 Initial values of system registers ............... 61 Page 3081 of 3092 Input JPEG coded data ......................... 2419 Instruction features ................................... 64 Instruction format ..................................... 73 Instruction set ........................................... 77 Integer division instructions ................... 159 Internal arbitration for transmission ..... 1235 Interrupt controller.................................. 167 Interrupt exception handling ................... 156 Interrupt priority level ............................ 155 Interrupt response time ........................... 209 Interrupt sources ..................................... 814 Interrupts for encoding and decoding ... 2429 Interrupts for transferring data .............. 2430 IREADY interrupt ................................ 1433 IRQ interrupts ......................................... 185 ISEC interrupt ....................................... 1432 ISY interrupt ......................................... 1433 ITARG interrupt ................................... 1432 J JPEG codec unit (JCU) ......................... 2359 JPEG coded data format ....................... 2409 JPEG decoding errors ........................... 2420 Jump table base register (TBR) ................ 59 L List of pins of this LSI .............................. 34 Load-store architecture ............................. 64 Local acceptance filter mask (LAFM) ................................................ 1173 Logic operation instructions ..................... 90 Loopback mode .............................. 890, 954 Low-power SDRAM .............................. 382 LRU ........................................................ 249 Page 3082 of 3092 M Mailbox ....................................... 1160, 1164 Mailbox configuration .......................... 1172 Mailbox control..................................... 1160 Manual reset............................................ 150 Master receive operation ....................... 1043 Master transmit operation ..................... 1041 Memory-mapped cache........................... 262 Message control field ............................ 1169 Message data fields ............................... 1174 Message receive sequence .................... 1249 Message transmission request ..... 1234, 1244 Micro processor interface (MPI) ........... 1160 Module enabled mode ........................... 1105 Module standby function ...................... 2731 Module stop mode settings ................... 2480 MOSI signal value determination during SSL negate period........................ 852 Motor control PWM timer .................... 2541 MPX-I/O interface .................................. 338 Multi mode............................................ 1449 Multi-function timer pulse unit 2 ............ 475 Multi-master mode operation .................. 876 Multiply and accumulate register high (MACH) .................................................... 60 Multiply and accumulate register low (MACL) .................................................... 60 Multiply/multiply-and-accumulate operations .................................................. 65 N NAND flash memory controller ........... 1465 NAND flash memory controller interrupt requests................................... 1505 NAND type flash memory controller timing ................................... 3033 Noise filter ............................................ 1053 Non-compressed modes ........................ 1093 Nonlinearity error ................................. 1459 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Non-numbers (NaN) ............................... 105 Normal space interface ........................... 330 Note on using a PLL oscillation circuit .. 139 O Offset error ........................................... 1459 On-chip peripheral module interrupts ..... 187 On-chip peripheral module request......... 455 On-chip RAM ....................................... 2559 OpenVG-compliant renesas graphics processor ................................ 2357 Operation in asynchronous mode ........... 794 Operation in clocked synchronous mode .................................. 805 Output load circuit ................................ 3049 Output pin initialization for multi-function timer pulse unit 2 ............ 660 Output waveform .................................. 2479 Overview of processing ........................ 2414 P Package dimensions of this LSI .. 3075, 3076 Page conflict ......................................... 2562 PCMCIA interface .................................. 393 Permissible signal source impedance ... 1462 Phase counting mode .............................. 573 Pin assignment of this LSI ............ 18, 19, 20 Pin functions of this LSI ........................... 21 Pin states of this LSI ............................. 3053 PINT interrupts ....................................... 186 PLL circuit .............................................. 127 Power-down mode .................................. 378 Power-down modes .............................. 2675 Power-down state ................................... 100 Power-on reset ........................................ 149 Power-on sequence ................................. 379 Power-on/power-off sequence .............. 2962 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Prefetch operation (only for operand cache) ......................... 258 Procedure register (PR) ............................. 60 Processing of analog input pins ............ 1461 Product lineup of this LSI ......................... 16 Program counter (PC) ............................... 60 Program execution state .......................... 100 PWM Modes ........................................... 568 PWM operation ..................................... 2555 Q Quantization error ................................. 1459 Quantization table specification ............ 2410 R Realtime clock ........................................ 719 Receive data sampling timing and receive margin (asynchronous mode) ..... 816 Reconfiguration of mailbox .................. 1251 Register addresses (by functional module, in order of the corresponding section numbers) ............................................... 2753 Register bank error exception handling .......................................... 153, 220 Register bank errors ................................ 153 Register bank exception .......................... 220 Register banks ................................... 61, 216 Register bits .......................................... 2810 Register states in each operating mode . 2957 Registers ABACK0 .......................................... 1209 ABACK1 .......................................... 1209 ACCCR1 ........................................... 1770 ACCCR2 ........................................... 1774 ACCCR3 ........................................... 1775 ADCCR1 ........................................... 1722 ADCSR ............................................. 1442 ADDRA to ADDRH ......................... 1441 Page 3083 of 3092 AFCPFCR......................................... 1796 AGCCR1 .......................................... 1781 AGCCR2 .......................................... 1784 AGCCSR1 ........................................ 1810 AGCCSR2 ........................................ 1811 BAMR ................................................ 230 BAR .................................................... 229 BBR .................................................... 233 BCR0 ................................................ 1190 BCR1 ................................................ 1188 BDMR ................................................ 232 BDR .................................................... 231 BEMPENB ....................................... 1554 BEMPSTS ........................................ 1572 BRCR ................................................. 235 BRDYENB ....................................... 1551 BRDYSTS ........................................ 1568 BSBPR.............................................. 2735 BSID ................................................. 2742 BSIR ................................................. 2735 BTGPCR........................................... 1768 BTLCR ............................................. 1763 BUSWAIT ........................................ 1521 CBGAINCR ..................................... 1839 CBUFCTL0 ...................................... 1408 CBUFCTL1 ...................................... 1410 CBUFCTL2 ...................................... 1410 CBUFCTL3 ...................................... 1411 CBUFST0 ......................................... 1394 CBUFST1 ......................................... 1395 CBUFST2 ......................................... 1396 CCR .................................................. 1223 CCR1 .................................................. 250 CCR2 .................................................. 252 CFIFO ............................................... 1533 CFIFOCTR ....................................... 1543 CFIFOSEL........................................ 1535 CHCR ................................................ 427 CHROMASR1 .................................. 1805 CHROMASR2 .................................. 1807 Page 3084 of 3092 CMAX_TEW .................................... 1218 CMCNT .............................................. 698 CMCOR .............................................. 698 CMCSR............................................... 696 CMNCR ....................................... 277,959 CMSTR ............................................... 695 CRGAINCR ...................................... 1840 CROMCTL0 ..................................... 1380 CROMCTL1 ..................................... 1382 CROMCTL3 ..................................... 1383 CROMCTL4 ..................................... 1384 CROMCTL5 ..................................... 1386 CROMEN ......................................... 1378 CROMST0 ........................................ 1387 CROMST0M .................................... 1411 CROMST1 ........................................ 1388 CROMST3 ........................................ 1389 CROMST4 ........................................ 1390 CROMST5 ........................................ 1391 CROMST6 ........................................ 1392 CROMSY0 ....................................... 1379 CS0WCR ............................ 286, 299, 313 CS1WCR ............................................ 288 CS2WCR .................................... 291, 304 CS3WCR .................................... 291, 305 CS4WCR .................................... 293, 302 CS5WCR .................................... 296, 309 CSnBCR (n = 0 to 5)........................... 281 CTRL ................................................ 1334 CYCTR ............................................. 1224 D0FBCFG ......................................... 1532 D0FIFO ............................................. 1533 D0FIFOCTR ..................................... 1543 D0FIFOSEL ...................................... 1535 D1FBCFG ......................................... 1532 D1FIFO ............................................. 1533 D1FIFOCTR ..................................... 1543 D1FIFOSEL ...................................... 1535 DAR.................................................... 426 DCPCFG ........................................... 1582 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 DCPCR1 ........................................... 1751 DCPCR2 ........................................... 1753 DCPCR3 ........................................... 1755 DCPCR4 ........................................... 1756 DCPCR5 ........................................... 1757 DCPCR6 ........................................... 1758 DCPCR7 ........................................... 1759 DCPCR8 ........................................... 1760 DCPCR9 ........................................... 1828 DCPCTR........................................... 1585 DCPMAXP ....................................... 1584 DCPSR1 ........................................... 1802 DCPSR2 ........................................... 1803 DEVADDn ....................................... 1635 DMAOR ............................................. 441 DMARS0 to DMARS7 ....................... 445 DMATCR ........................................... 427 DOCMCLSTR .................................. 2336 DOCMCR ......................................... 2334 DOCMIENR ..................................... 2337 DOCMSTR ....................................... 2335 DSESR .............................................. 2714 DSFR ................................................ 2716 DSSSR .............................................. 2711 DVSTCTR ........................................ 1523 FLADR ............................................. 1477 FLADR2 ........................................... 1479 FLBSYCNT ...................................... 1488 FLBSYTMR ..................................... 1487 FLCMCDR ....................................... 1476 FLCMDCR ....................................... 1473 FLCMNCR ....................................... 1470 FLDATAR ........................................ 1481 FLDTCNTR...................................... 1480 FLDTFIFO........................................ 1489 FLECFIFO ........................................ 1490 FLHOLDCR ..................................... 1492 FLINTDMACR ................................ 1482 FLTRCR ........................................... 1491 FPSCR ................................................ 108 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 FPUL................................................... 110 FRMNUM ......................................... 1573 FRQCR ............................................... 132 GSR................................................... 1185 HAFCCR1 ........................................ 1743 HAFCCR2 ........................................ 1746 HAFCCR3 ........................................ 1748 HEAD00 ........................................... 1396 HEAD01 ........................................... 1397 HEAD02 ........................................... 1397 HEAD03 ........................................... 1398 HEAD20 ........................................... 1402 HEAD21 ........................................... 1403 HEAD22 ........................................... 1403 HEAD23 ........................................... 1404 HSYNCSR ........................................ 1801 IBCR ................................................... 182 IBNR ................................................... 183 ICCR1 .............................................. 1025 ICCR2 .............................................. 1028 ICDRR ............................................. 1038 ICDRS .............................................. 1038 ICDRT.............................................. 1037 ICIER ............................................... 1032 ICMR ............................................... 1030 ICR0 .................................................... 175 ICR1 .................................................... 177 ICR2 .................................................... 178 ICSR ................................................. 1034 IEAR1 ............................................... 1288 IEAR2 ............................................... 1289 IECKSR ............................................ 1310 IECMR .............................................. 1284 IECTR ............................................... 1283 IEFLG ............................................... 1296 IEIER ................................................ 1309 IEIET ................................................ 1303 IELA1 ............................................... 1294 IELA2 ............................................... 1295 IEMA1 .............................................. 1291 Page 3085 of 3092 IEMA2 .............................................. 1292 IEMCR ............................................. 1286 IERB ................................................. 1313 IERBFL ............................................ 1294 IERCTL ............................................ 1293 IERSR ............................................... 1305 IESA1 ............................................... 1289 IESA2 ............................................... 1290 IETB ................................................. 1312 IETBFL ............................................ 1290 IETSR ............................................... 1299 IMR .................................................. 1200 INHINT ............................................ 1417 INTENB0 ......................................... 1547 INTENB1 ......................................... 1549 INTHOLD ........................................ 1416 INTSTS0........................................... 1557 INTSTS1........................................... 1562 IPR01, IPR02, IPR05 to IPR26 .. 155, 172 IRQRR ................................................ 179 IRR ................................................... 1193 JCCMD ............................................. 2364 JCDERR ........................................... 2380 JCDRID ............................................ 2369 JCDRIU ............................................ 2368 JCDTCD ........................................... 2376 JCDTCM .......................................... 2375 JCDTCU ........................................... 2374 JCHSZD ........................................... 2373 JCHSZU ........................................... 2372 JCHTN.............................................. 2367 JCMOD ............................................ 2363 JCQTN.............................................. 2366 JCRST .............................................. 2381 JCVSZD ........................................... 2371 JCVSZU ........................................... 2370 JIFDCNT .......................................... 2389 JIFDDA ............................................ 2396 JIFDDLC .......................................... 2398 JIFDDOFST ..................................... 2395 Page 3086 of 3092 JIFDSA ............................................. 2394 JIFDSDC........................................... 2397 JIFECNT ........................................... 2382 JIFEDA ............................................. 2387 JIFESA .............................................. 2385 JIFESLC ........................................... 2388 JIFESOFST ....................................... 2386 JINTE0 .............................................. 2377 JINTE1 .............................................. 2400 JINTS0 .............................................. 2379 JINTS1 .............................................. 2402 MBIMR0........................................... 1213 MBIMR1........................................... 1213 MCR ................................................. 1180 NF2CYC ........................................... 1039 NRDYENB ....................................... 1552 NRDYSTS ........................................ 1570 NSDCR ............................................. 1761 NSDSR ............................................. 1804 PAIOR0 ............................................ 2578 PAPR0 .............................................. 2579 PBCR0 .............................................. 2590 PBCR1 .............................................. 2588 PBCR2 .............................................. 2586 PBCR3 .............................................. 2584 PBCR4 .............................................. 2582 PBCR5 .............................................. 2580 PBDR0 .............................................. 2594 PBDR1 .............................................. 2593 PBIOR0............................................. 2592 PBIOR1............................................. 2592 PBPR0............................................... 2596 PBPR1............................................... 2595 PCCR0 .............................................. 2599 PCCR1 .............................................. 2598 PCCR2 .............................................. 2597 PCDR0 .............................................. 2601 PCIOR0............................................. 2600 PCPR0............................................... 2602 PDCR0 .............................................. 2608 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 PDCR1 .............................................. 2606 PDCR2 .............................................. 2604 PDCR3 .............................................. 2603 PDDR0 ............................................. 2610 PDIOR0 ............................................ 2609 PDPR0 .............................................. 2612 PECR0 .............................................. 2614 PECR1 .............................................. 2613 PEDR0 .............................................. 2616 PEIOR0............................................. 2615 PEPR0............................................... 2617 PFCR0 .............................................. 2626 PFCR1 .............................................. 2624 PFCR2 .............................................. 2623 PFCR3 .............................................. 2622 PFCR4 .............................................. 2621 PFCR5 .............................................. 2619 PFCR6 .............................................. 2618 PFDR0 .............................................. 2628 PFIOR0 ............................................. 2627 PFPR0 ............................................... 2630 PGCR0 .............................................. 2642 PGCR1 .............................................. 2640 PGCR2 .............................................. 2638 PGCR3 .............................................. 2636 PGCR4 .............................................. 2634 PGCR5 .............................................. 2633 PGCR6 .............................................. 2632 PGDR0 ............................................. 2646 PGDR1 ............................................. 2645 PGIOR0 ............................................ 2644 PGIOR1 ............................................ 2644 PGPR0 .............................................. 2649 PGPR1 .............................................. 2647 PHCR0 .............................................. 2651 PHCR1 .............................................. 2650 PHPR0 .............................................. 2652 PINTER .............................................. 180 PIPEBUF .......................................... 1603 PIPECFG .......................................... 1596 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 PIPEMAXP ....................................... 1606 PIPEnCTR ........................................ 1610 PIPEnTRE ......................................... 1631 PIPEnTRN ........................................ 1633 PIPEPERI.......................................... 1608 PIPESEL ........................................... 1595 PIRR ................................................... 181 PJCR0 ............................................... 2664 PJCR1 ............................................... 2662 PJCR2 ............................................... 2661 PJCR3 ............................................... 2659 PJCR4 ............................................... 2658 PJCR5 ............................................... 2656 PJCR6 ............................................... 2655 PJCR7 ............................................... 2653 PJDR0 ............................................... 2668 PJDR1 ............................................... 2667 PJIOR0 .............................................. 2665 PJIOR1 .............................................. 2665 PJPR0 ................................................ 2671 PJPR1 ................................................ 2669 PKLIMITCR ..................................... 1785 PWBFR_n ......................................... 2552 PWBTCR .......................................... 2553 PWCNT_n ........................................ 2547 PWCR_n ........................................... 2545 PWCYR_n ........................................ 2548 PWDTR_n ........................................ 2549 PWPR_n............................................ 2547 R64CNT .............................................. 723 RCR1 .................................................. 738 RCR2 .................................................. 740 RCR3 .................................................. 742 RCR5 .................................................. 743 RDAD ............................................... 1353 RDAR ................................................. 439 RDAYAR............................................ 735 RDAYCNT ......................................... 728 RDMATCR ......................................... 440 REC................................................... 1200 Page 3087 of 3092 RFMK ............................................... 1225 RFPR0 .............................................. 1212 RFPR1 .............................................. 1211 RFRH/L .............................................. 744 RFTROFF ......................................... 1220 RGORCR1........................................ 1788 RGORCR2........................................ 1789 RGORCR3........................................ 1790 RGORCR4........................................ 1791 RGORCR5........................................ 1792 RGORCR6........................................ 1793 RGORCR7........................................ 1794 RHRAR .............................................. 733 RHRCNT ............................................ 726 RLCA ............................................... 1351 RLCS ................................................ 1355 RMINAR ............................................ 732 RMINCNT.......................................... 725 RMONAR........................................... 736 RMONCNT ........................................ 729 ROMDECRST .................................. 1412 RRCA ............................................... 1352 RRCS ................................................ 1357 RSAR.................................................. 438 RSECAR............................................. 731 RSECCNT .......................................... 724 RSTSTAT ......................................... 1413 RTCNT ............................................... 321 RTCSR ............................................... 319 RUI ................................................... 1354 RUPDCR .......................................... 1798 RWKAR ............................................. 734 RWKCNT ........................................... 727 RXPR0.............................................. 1211 RXPR1.............................................. 1210 RYRAR .............................................. 737 RYRCNT ............................................ 730 SAR (Direct memory access controller)...... 426 SAR (I2C bus interface 3) ................. 1037 Page 3088 of 3092 SCBRR ............................................... 776 SCEMR ............................................... 790 SCFCR ................................................ 782 SCFDR................................................ 785 SCFRDR ............................................. 759 SCFSR ................................................ 768 SCFTDR ............................................. 760 SCLSR ................................................ 789 SCRSR ................................................ 759 SCSCR ................................................ 764 SCSMR ............................................... 761 SCSPTR .............................................. 786 SCTSR ................................................ 760 SDBPR.............................................. 2743 SDBSR.............................................. 2736 SDCR .................................................. 315 SDIR ................................................. 2743 SGCR ................................................ 2467 SGCSR.............................................. 2469 SGLR ................................................ 2471 SGSFR .............................................. 2472 SGTFR .............................................. 2471 SHEAD00 ......................................... 1398 SHEAD01 ......................................... 1399 SHEAD02 ......................................... 1399 SHEAD03 ......................................... 1400 SHEAD04 ......................................... 1400 SHEAD05 ......................................... 1401 SHEAD06 ......................................... 1401 SHEAD07 ......................................... 1402 SHEAD20 ......................................... 1404 SHEAD21 ......................................... 1405 SHEAD22 ......................................... 1405 SHEAD23 ......................................... 1406 SHEAD24 ......................................... 1406 SHEAD25 ......................................... 1407 SHEAD26 ......................................... 1407 SHEAD27 ......................................... 1408 SICTR ............................................... 1121 SIFCTR ............................................. 1133 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SIIER ................................................ 1131 SIMDR ............................................. 1119 SIRDAR ........................................... 1138 SIRDR .............................................. 1125 SISCR ............................................... 1135 SISTR ............................................... 1126 SITDAR ............................................ 1136 SITDR............................................... 1124 SOFCFG ........................................... 1555 SPBCR ................................................ 966 SPBDCR ............................................. 923 SPBFCR ............................................. 921 SPBMULn .......................................... 924 SPBR .......................................... 837, 909 SPCKD ....................................... 840, 912 SPCMD............................................... 843 SPCMDn............................................. 915 SPCR .......................................... 825, 899 SPDCR ............................................... 911 SPDR .......................................... 833, 906 SPND .......................................... 842, 914 SPPCR ........................................ 828, 901 SPSCR ........................................ 834, 907 SPSR ........................................... 830, 903 SPSSR......................................... 836, 908 SRCCTRL ........................................ 2444 SRCID .............................................. 2438 SRCIDCTRL .................................... 2440 SRCOD ............................................. 2439 SRCODCTRL................................... 2442 SRCSTAT......................................... 2450 SSI .................................................... 1413 SSICR ............................................... 1069 SSIFCR ............................................. 1082 SSIFRDR .......................................... 1089 SSIFSR ............................................. 1085 SSIFTDR .......................................... 1088 SSIRDR ............................................ 1081 SSISR ............................................... 1077 SSITDMR ......................................... 1090 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SSITDR............................................. 1081 SSLND ........................................ 841, 913 SSLP ........................................... 827, 900 STAT ................................................ 1339 STBCR1 ............................................ 2679 STBCR10 .......................................... 2696 STBCR2 ............................................ 2680 STBCR3 ............................................ 2681 STBCR4 ............................................ 2683 STBCR5 ............................................ 2686 STBCR6 ............................................ 2688 STBCR7 ............................................ 2690 STBCR8 ............................................ 2692 STBCR9 ............................................ 2694 STRMDIN0 ...................................... 1418 STRMDIN2 ...................................... 1418 STRMDOUT0................................... 1419 SWRSTCR1 ...................................... 2698 SWRSTCR2 ...................................... 2700 SYNCSSR ......................................... 1809 SYNSCR1 ......................................... 1729 SYNSCR2 ......................................... 1735 SYNSCR3 ......................................... 1737 SYNSCR4 ......................................... 1739 SYNSCR5 ......................................... 1741 SYSCFG ........................................... 1516 SYSCR1 ............................................ 2701 SYSCR2 ............................................ 2702 SYSCR3 ............................................ 2703 SYSCR4 ............................................ 2705 SYSCR5 ............................................ 2706 SYSSTS ............................................ 1522 TADCOBRA_4................................... 524 TADCOBRB_4 ................................... 524 TADCORA_4 ..................................... 524 TADCORB_4 ..................................... 524 TADCR ............................................... 521 TBTER ................................................ 546 TBTM ................................................. 518 TCBR .................................................. 543 Page 3089 of 3092 TCDR ................................................. 542 TCMR0 to TCMR2 .......................... 1225 TCNT.................................................. 525 TCNTR ............................................. 1224 TCNTS ............................................... 541 TCR .................................................... 485 TDAD ............................................... 1345 TDDR ................................................. 542 TDER.................................................. 548 TEC .................................................. 1200 TESTMODE ..................................... 1529 TGCR ................................................. 539 TGCR1 ............................................. 1723 TGCR2 ............................................. 1724 TGCR3 ............................................. 1725 TGR .................................................... 525 TICCR ................................................ 519 TIER ................................................... 510 TINTCR............................................ 1777 TIOR ................................................... 492 TITCNT .............................................. 545 TITCR ................................................ 543 TLCA................................................ 1343 TLCS ................................................ 1347 TMDR ................................................ 489 TOCR1 ............................................... 532 TOCR2 ............................................... 535 TOER.................................................. 530 TOLBR ............................................... 538 TRCA ............................................... 1344 TRCS ................................................ 1349 TRWER .............................................. 529 TSR ........................................... 513, 1221 TSTR .................................................. 526 TSYR .................................................. 527 TTCR0 .............................................. 1216 TTTSEL............................................ 1227 TUI ................................................... 1346 TWCR ................................................ 549 TXACK0 .......................................... 1208 Page 3090 of 3092 TXACK1........................................... 1207 TXCR0 .............................................. 1207 TXCR1 .............................................. 1206 TXPR0 .............................................. 1205 TXPR1 .............................................. 1204 UFRMNUM ...................................... 1576 UMSR0 ............................................. 1214 UMSR1 ............................................. 1214 USBADDR ....................................... 1577 USBINDX......................................... 1580 USBLENG ........................................ 1581 USBREQ........................................... 1578 USBVAL .......................................... 1579 VCDWCR1 ....................................... 1749 VSYNCSR ........................................ 1799 WRCSR .............................................. 711 WTCNT .............................................. 707 WTCSR............................................... 708 XTALCTR ........................................ 2719 YCDCR............................................. 1779 YCSCR11 ......................................... 1824 YCSCR12 ......................................... 1825 YCSCR3 ........................................... 1812 YCSCR4 ........................................... 1813 YCSCR5 ........................................... 1814 YCSCR6 ........................................... 1815 YCSCR7 ........................................... 1816 YCSCR8 ........................................... 1818 YCSCR9 ........................................... 1820 YCTNA_F0 to YCTNA_F8 ............. 1834 YCTNB_F0 to YCTNB_F8 .............. 1836 YCTWA_F0 to YCTWA_F8 ............ 1830 YCTWB_F0 to YCTWB_F8 ............ 1832 YGAINCR ........................................ 1838 Relationship between access size and number of bursts............................... 358 Relationship between non-normal transfer operations................................... 938 Relationship between refresh requests and bus cycles ......................................... 377 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Renesas quad serial peripheral interface .................................................. 893 Renesas serial peripheral interface ......... 819 Renesas serial peripheral interface timing .................................................... 3017 Renesas SPDIF interface ...................... 1329 Reset sequence...................................... 1230 Reset state ............................................... 100 Reset-synchronized PWM mode ............ 580 Restoration from bank ............................ 218 Restoration from stack ............................ 219 Restriction on direct memory access controller usage....................................... 816 RISC-type instruction set .......................... 64 Roles of mailboxes ............................... 1166 Rounding ................................................ 111 S Sampling rate converter ........................ 2435 Saving to bank ........................................ 217 Saving to stack ........................................ 219 Scan mode ............................................ 1451 SD host interface .................................. 2481 SD host interface timing ....................... 3044 SDRAM interface ................................... 343 Searching cache ...................................... 256 Sector access mode ............................... 1499 Self-refreshing ........................................ 375 Sending a break signal ............................ 816 Serial bit clock control .......................... 1112 Serial communication interface with FIFO ............................................... 751 Serial communication interface with FIFO timing .................................. 3016 Serial I/O with FIFO ............................. 1115 Serial I/O with FIFO timing ................. 3030 Serial sound interface ........................... 1063 Serial sound interface timing ................ 3028 Setting analog input voltage ................. 1460 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 Setting I/O ports for controller area network .......................................... 1256 Shift instructions ....................................... 91 Sign extension of word data ...................... 64 Single address mode ............................... 464 Single mode .......................................... 1446 Single read .............................................. 362 Single write ............................................. 365 Single-SPI mode ..................................... 939 Slave mode operation .............................. 884 Slave receive operation ......................... 1048 Slave transmit operation........................ 1045 Sleep mode .................................. 1231, 2720 Slot illegal instructions ........................... 158 Software standby mode ......................... 2721 Sound generator .................................... 2463 SPI multi I/O bus controller .................... 955 SRAM interface with byte selection ....... 388 Stack after interrupt exception handling .................................................. 208 Stack status after exception handling ends .......................................... 161 Standby control circuit ............................ 127 Status register (SR) ................................... 58 Stopping and resuming CD-DSP operation ................................ 1435 Supported DMA transfers ....................... 461 Syndrome calculation............................ 1426 System configuration example ................ 853 System control instructions ....................... 93 System matrix ....................................... 1179 T T bit ........................................................... 65 Table setting .......................................... 2410 TAP controller ...................................... 2745 Target-sector buffering function ........... 1430 TDO output timing ................................ 2746 Test mode settings................................. 1228 Page 3091 of 3092 Time slave ............................................ 1242 Time trigger control (TT control) ......... 1176 Time triggered transmission ................. 1237 Timestamp ............................................ 1175 Timing to clear an interrupt source ......... 223 Tone frequency setting ......................... 2477 Transfer format ................856, 857, 930, 931 Transfer rate.......................................... 1027 Trap instructions ..................................... 158 TTW[1:0] (time trigger window).......... 1177 Tx-trigger control field ......................... 1176 Tx-trigger time (TTT) ........................... 1176 Types of exception handling and priority order .................................... 141 U UBC timing .......................................... 3012 Unconditional branch instructions with no delay slot...................................... 65 USB 2.0 host/function module ............. 1509 USB 2.0 host/function module timing .. 3038 Page 3092 of 3092 User break controller (UBC) ................... 225 User debugging interface ...................... 2733 User debugging interface interrupt ......... 185 User debugging interface interrupt ....... 2747 User debugging interface reset.............. 2747 User debugging interface timing ........... 3047 Using alarm function .............................. 748 Using interval timer mode ...................... 716 Using watchdog timer mode ................... 714 V Vector base register (VBR) ....................... 59 W Wait between access cycles .................... 399 Watchdog timer....................................... 705 Watchdog timer timing ......................... 3015 Write-back buffer (only for operand cache) ......................... 259 R01UH0048EJ0300 Rev. 3.00 Oct 21, 2016 SH7268 Group, SH7269 Group User’s Manual: Hardware Publication Date: Rev.3.00 Published by: Oct 21, 2016 Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3 Tel: +1-905-237-2004 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-6503-0, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333 Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949 Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL II Stage, Indiranagar, Bangalore, India Tel: +91-80-67208700, Fax: +91-80-67208777 Renesas Electronics Korea Co., Ltd. 12F., 234 Teheran-ro, Gangnam-Gu, Seoul, 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2016 Renesas Electronics Corporation. All rights reserved. Colophon 4.0 SH7268 Group, SH7269 Group R01UH0048EJ0300