R5S726A3P216FP#VZ

厂商：
RENESAS(瑞萨)
封装：
LQFP120
描述：
SH2A-FPU SuperH® SH7260 Microcontroller IC 32-Bit 216MHz ROMless 120-LQFP (14x14)

数据手册：

下载R5S726A3P216FP#VZ.pdf

立即购买

数据手册
价格&库存

R5S726A3P216FP#VZ 数据手册

User's Manual 32 SH726A Group, SH726B Group User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series SH726A SH726B www.renesas.com R5S726A R5S726B Rev.2.00 Sep 2015 Page ii of xxxiv Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. Page iii of xxxiv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Page iv of xxxiv Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. States and Handling of Pins 10. Appendix • Package Dimensions, etc. 11. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 12. Index Page v of xxxiv Preface This LSI is an RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users. Refer to the SH-2A, SH2A-FPU Software Manual for a detailed description of the instruction set. Notes on reading this manual:  In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.  In order to understand the details of the CPU's functions Read the SH-2A, SH2A-FPU Software Manual.  In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 34, List of Registers. Page vi of xxxiv  Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and do not refer to specific data in this manual. Page vii of xxxiv  Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: Initial value: R/W: 15 14 ⎯ ⎯ 13 12 11 ASID2 ASID1 ASID0 10 9 8 7 6 5 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Q 3 2 1 ACMP2 ACMP1 ACMP0 0 IFE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name − − Initial Value R/W Description 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function. 10 − 0 R Reserved This bit is always read as 0. 9 − 1 R Reserved This bit is always read as 1. − 0 15 14 Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. The bit or field is readable. R: "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. The bit or field is writable. W: (5) Description Describes the function of the bit or field and specifies the values for writing. All trademarks and registered trademarks are the property of their respective owners. Page viii of xxxiv Contents Section 1 Overview ..................................................................................................1 1.1 1.2 1.3 1.4 1.5 1.6 SH726A/726B Features ........................................................................................................ 1 Product Lineup .................................................................................................................... 11 Block Diagram .................................................................................................................... 12 Pin Assignment ................................................................................................................... 13 Pin Functions ...................................................................................................................... 15 List of Pins .......................................................................................................................... 23 Section 2 CPU ........................................................................................................37 2.1 2.2 2.3 2.4 2.5 Register Configuration ........................................................................................................ 37 2.1.1 General Registers ................................................................................................ 37 2.1.2 Control Registers ................................................................................................ 38 2.1.3 System Registers ................................................................................................. 40 2.1.4 Register Banks .................................................................................................... 41 2.1.5 Initial Values of Registers ................................................................................... 41 Data Formats ....................................................................................................................... 42 2.2.1 Data Format in Registers .................................................................................... 42 2.2.2 Data Formats in Memory .................................................................................... 42 2.2.3 Immediate Data Format ...................................................................................... 43 Instruction Features............................................................................................................. 44 2.3.1 RISC-Type Instruction Set .................................................................................. 44 2.3.2 Addressing Modes .............................................................................................. 48 2.3.3 Instruction Format............................................................................................... 53 Instruction Set ..................................................................................................................... 57 2.4.1 Instruction Set by Classification ......................................................................... 57 2.4.2 Data Transfer Instructions................................................................................... 63 2.4.3 Arithmetic Operation Instructions ...................................................................... 67 2.4.4 Logic Operation Instructions .............................................................................. 70 2.4.5 Shift Instructions ................................................................................................. 71 2.4.6 Branch Instructions ............................................................................................. 72 2.4.7 System Control Instructions ................................................................................ 73 2.4.8 Floating-Point Operation Instructions ................................................................. 75 2.4.9 FPU-Related CPU Instructions ........................................................................... 77 2.4.10 Bit Manipulation Instructions ............................................................................. 78 Processing States................................................................................................................. 79 Page ix of xxxiv Section 3 Floating-Point Unit (FPU) ..................................................................... 81 3.1 3.2 3.3 3.4 3.5 Features ............................................................................................................................... 81 Data Formats ....................................................................................................................... 82 3.2.1 Floating-Point Format ......................................................................................... 82 3.2.2 Non-Numbers (NaN) .......................................................................................... 85 3.2.3 Denormalized Numbers ...................................................................................... 86 Register Descriptions .......................................................................................................... 87 3.3.1 Floating-Point Registers ..................................................................................... 87 3.3.2 Floating-Point Status/Control Register (FPSCR)................................................ 88 3.3.3 Floating-Point Communication Register (FPUL) ............................................... 90 Rounding ............................................................................................................................ 91 FPU Exceptions .................................................................................................................. 92 3.5.1 FPU Exception Sources ...................................................................................... 92 3.5.2 FPU Exception Handling .................................................................................... 92 Section 4 Boot Mode ............................................................................................. 95 4.1 4.2 4.3 4.4 Features ............................................................................................................................... 95 Boot Mode and Pin Function Setting .................................................................................. 95 Operation ............................................................................................................................ 96 4.3.1 Boot Mode 0 ....................................................................................................... 96 4.3.2 Boot Mode 1 ....................................................................................................... 96 Notes ................................................................................................................................... 98 4.4.1 Boot Related Pins................................................................................................ 98 Section 5 Clock Pulse Generator ........................................................................... 99 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Features ............................................................................................................................... 99 Input/Output Pins .............................................................................................................. 102 Clock Operating Modes .................................................................................................... 103 Register Descriptions ........................................................................................................ 105 5.4.1 Frequency Control Register (FRQCR) ............................................................. 105 Changing the Frequency ................................................................................................... 108 5.5.1 Changing the Division Ratio ............................................................................. 108 Usage of the Clock Pins .................................................................................................... 109 5.6.1 In the Case of Inputting an External Clock ....................................................... 109 5.6.2 In the Case of Using a Crystal Resonator ......................................................... 110 5.6.3 In the Case of Not Using the Clock Pin ............................................................ 110 Oscillation Stabilizing Time ............................................................................................. 111 5.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator ........................ 111 5.7.2 Oscillation Stabilizing Time of the PLL circuit ................................................ 111 Notes on Board Design ..................................................................................................... 112 Page x of xxxiv 5.8.1 Note on Using a PLL Oscillation Circuit .......................................................... 112 Section 6 Exception Handling .............................................................................113 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Overview........................................................................................................................... 113 6.1.1 Types of Exception Handling and Priority........................................................ 113 6.1.2 Exception Handling Operations ........................................................................ 114 6.1.3 Exception Handling Vector Table..................................................................... 116 Resets ................................................................................................................................ 119 6.2.1 Input/Output Pins .............................................................................................. 119 6.2.2 Types of Reset .................................................................................................. 119 6.2.3 Power-On Reset ................................................................................................ 121 6.2.4 Manual Reset .................................................................................................... 122 Address Errors .................................................................................................................. 124 6.3.1 Address Error Sources ...................................................................................... 124 6.3.2 Address Error Exception Handling ................................................................... 125 Register Bank Errors ......................................................................................................... 125 6.4.1 Register Bank Error Sources ............................................................................. 125 6.4.2 Register Bank Error Exception Handling ......................................................... 126 Interrupts ........................................................................................................................... 126 6.5.1 Interrupt Sources ............................................................................................... 126 6.5.2 Interrupt Priority Level ..................................................................................... 127 6.5.3 Interrupt Exception Handling............................................................................ 128 Exceptions Triggered by Instructions ............................................................................... 129 6.6.1 Types of Exceptions Triggered by Instructions ................................................ 129 6.6.2 Trap Instructions ............................................................................................... 130 6.6.3 Slot Illegal Instructions ..................................................................................... 130 6.6.4 General Illegal Instructions ............................................................................... 131 6.6.5 Integer Division Exceptions .............................................................................. 131 6.6.6 FPU Exceptions ................................................................................................ 132 When Exception Sources Are Not Accepted .................................................................... 133 Stack Status after Exception Handling Ends ..................................................................... 133 Usage Notes ...................................................................................................................... 135 6.9.1 Value of Stack Pointer (SP) .............................................................................. 135 6.9.2 Value of Vector Base Register (VBR) .............................................................. 135 6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 135 6.9.4 Note before Exception Handling Begins Running ............................................ 136 Section 7 Interrupt Controller ..............................................................................139 7.1 7.2 Features ............................................................................................................................. 139 Input/Output Pins .............................................................................................................. 141 Page xi of xxxiv 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Register Descriptions ........................................................................................................ 142 7.3.1 Interrupt Priority Registers 01, 02, 05 to 22 (IPR01, IPR02, IPR05 to IPR22) ...................................................................... 144 7.3.2 Interrupt Control Register 0 (ICR0) .................................................................. 146 7.3.3 Interrupt Control Register 1 (ICR1) .................................................................. 148 7.3.4 Interrupt Control Register 2 (ICR2) .................................................................. 149 7.3.5 IRQ Interrupt Request Register (IRQRR) ......................................................... 150 7.3.6 PINT Interrupt Enable Register (PINTER) ....................................................... 151 7.3.7 PINT Interrupt Request Register (PIRR) .......................................................... 152 7.3.8 Bank Control Register (IBCR).......................................................................... 153 7.3.9 Bank Number Register (IBNR) ........................................................................ 154 Interrupt Sources ............................................................................................................... 155 7.4.1 NMI Interrupt.................................................................................................... 155 7.4.2 User Break Interrupt ......................................................................................... 156 7.4.3 User Debugging Interface Interrupt .................................................................. 156 7.4.4 IRQ Interrupts ................................................................................................... 156 7.4.5 PINT Interrupts ................................................................................................. 157 7.4.6 On-Chip Peripheral Module Interrupts ............................................................. 158 Interrupt Exception Handling Vector Table and Priority .................................................. 159 Operation .......................................................................................................................... 173 7.6.1 Interrupt Operation Sequence ........................................................................... 173 7.6.2 Stack after Interrupt Exception Handling ......................................................... 176 Interrupt Response Time ................................................................................................... 177 Register Banks .................................................................................................................. 183 7.8.1 Banked Register and Input/Output of Banks .................................................... 184 7.8.2 Bank Save and Restore Operations ................................................................... 184 7.8.3 Save and Restore Operations after Saving to All Banks ................................... 186 7.8.4 Register Bank Exception................................................................................... 187 7.8.5 Register Bank Error Exception Handling ......................................................... 187 Data Transfer with Interrupt Request Signals ................................................................... 188 7.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not Direct Memory Access Controller Activating................................................... 189 7.9.2 Handling Interrupt Request Signals as Sources for Activating Direct Memory Access Controller but Not CPU Interrupt........................................... 189 Usage Note........................................................................................................................ 190 7.10.1 Timing to Clear an Interrupt Source ................................................................. 190 Section 8 User Break Controller.......................................................................... 191 8.1 8.2 Features ............................................................................................................................. 191 Register Descriptions ........................................................................................................ 193 Page xii of xxxiv 8.3 8.4 8.2.1 Break Address Register (BAR) ......................................................................... 194 8.2.2 Break Address Mask Register (BAMR) ........................................................... 195 8.2.3 Break Data Register (BDR) .............................................................................. 196 8.2.4 Break Data Mask Register (BDMR) ................................................................. 197 8.2.5 Break Bus Cycle Register (BBR)...................................................................... 198 8.2.6 Break Control Register (BRCR) ....................................................................... 201 Operation .......................................................................................................................... 203 8.3.1 Flow of the User Break Operation .................................................................... 203 8.3.2 Break on Instruction Fetch Cycle...................................................................... 204 8.3.3 Break on Data Access Cycle ............................................................................. 205 8.3.4 Value of Saved Program Counter ..................................................................... 206 8.3.5 Usage Examples ................................................................................................ 207 Usage Notes ...................................................................................................................... 210 Section 9 Cache....................................................................................................211 9.1 9.2 9.3 9.4 Features ............................................................................................................................. 211 9.1.1 Cache Structure ................................................................................................. 211 Register Descriptions ........................................................................................................ 214 9.2.1 Cache Control Register 1 (CCR1) .................................................................... 214 9.2.2 Cache Control Register 2 (CCR2) .................................................................... 216 Operation .......................................................................................................................... 220 9.3.1 Searching Cache................................................................................................ 220 9.3.2 Read Access ...................................................................................................... 222 9.3.3 Prefetch Operation (Only for Operand Cache) ................................................. 222 9.3.4 Write Operation (Only for Operand Cache)...................................................... 223 9.3.5 Write-Back Buffer (Only for Operand Cache).................................................. 223 9.3.6 Coherency of Cache and External Memory or Large-Capacity On-Chip RAM ................................................................................................................. 225 Memory-Mapped Cache ................................................................................................... 226 9.4.1 Address Array ................................................................................................... 226 9.4.2 Data Array......................................................................................................... 228 9.4.3 Usage Examples ................................................................................................ 230 9.4.4 Usage Notes ...................................................................................................... 231 Section 10 Bus State Controller ...........................................................................233 10.1 10.2 10.3 Features ............................................................................................................................. 233 Input/Output Pins .............................................................................................................. 236 Area Overview .................................................................................................................. 237 10.3.1 Address Map ..................................................................................................... 237 Page xiii of xxxiv 10.3.2 10.4 10.5 Data Bus Width and Endian Specification for Each Area Depending on Boot Mode and Settings of Pins Related to This Module ................................. 239 Register Descriptions ........................................................................................................ 241 10.4.1 Common Control Register (CMNCR) .............................................................. 242 10.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 4) ................................. 245 10.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 4) .............................. 250 10.4.4 SDRAM Control Register (SDCR) ................................................................... 272 10.4.5 Refresh Timer Control/Status Register (RTCSR) ............................................. 276 10.4.6 Refresh Timer Counter (RTCNT) ..................................................................... 278 10.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 279 Operation .......................................................................................................................... 280 10.5.1 Endian/Access Size and Data Alignment.......................................................... 280 10.5.2 Normal Space Interface..................................................................................... 283 10.5.3 Access Wait Control ......................................................................................... 287 10.5.4 CSn Assert Period Expansion ........................................................................... 289 10.5.5 SDRAM Interface ............................................................................................. 290 10.5.6 Burst ROM (Clocked Asynchronous) Interface................................................ 325 10.5.7 SRAM Interface with Byte Selection................................................................ 327 10.5.8 Burst ROM (Clocked Synchronous) Interface .................................................. 332 10.5.9 Wait between Access Cycles ............................................................................ 333 10.5.10 Others................................................................................................................ 341 Section 11 Direct Memory Access Controller..................................................... 345 11.1 11.2 11.3 11.4 Features ............................................................................................................................. 345 Input/Output Pins .............................................................................................................. 348 Register Descriptions ........................................................................................................ 349 11.3.1 DMA Source Address Registers (SAR) ............................................................ 358 11.3.2 DMA Destination Address Registers (DAR) .................................................... 358 11.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 359 11.3.4 DMA Channel Control Registers (CHCR) ....................................................... 359 11.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 369 11.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 370 11.3.7 DMA Reload Transfer Count Registers (RDMATCR)..................................... 371 11.3.8 DMA Operation Register (DMAOR) ............................................................... 372 11.3.9 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7) .............. 375 Operation .......................................................................................................................... 380 11.4.1 Transfer Flow.................................................................................................... 380 11.4.2 DMA Transfer Requests ................................................................................... 382 11.4.3 Channel Priority ................................................................................................ 389 11.4.4 DMA Transfer Types ........................................................................................ 389 Page xiv of xxxiv 11.5 11.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 400 Usage Notes ...................................................................................................................... 404 11.5.1 Timing of DACK and TEND Outputs .............................................................. 404 Section 12 Multi-Function Timer Pulse Unit 2....................................................405 12.1 12.2 12.3 Features ............................................................................................................................. 405 Input/Output Pins .............................................................................................................. 410 Register Descriptions ........................................................................................................ 411 12.3.1 Timer Control Register (TCR) .......................................................................... 415 12.3.2 Timer Mode Register (TMDR) ......................................................................... 419 12.3.3 Timer I/O Control Register (TIOR) .................................................................. 422 12.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 440 12.3.5 Timer Status Register (TSR) ............................................................................. 443 12.3.6 Timer Buffer Operation Transfer Mode Register (TBTM) ............................... 448 12.3.7 Timer Input Capture Control Register (TICCR) ............................................... 449 12.3.8 Timer A/D Converter Start Request Control Register (TADCR) ..................... 451 12.3.9 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) .................................................................. 454 12.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) ............................................................. 454 12.3.11 Timer Counter (TCNT) ..................................................................................... 455 12.3.12 Timer General Register (TGR) ......................................................................... 455 12.3.13 Timer Start Register (TSTR)............................................................................. 456 12.3.14 Timer Synchronous Register (TSYR) ............................................................... 457 12.3.15 Timer Read/Write Enable Register (TRWER).................................................. 459 12.3.16 Timer Output Master Enable Register (TOER) ................................................ 460 12.3.17 Timer Output Control Register 1 (TOCR1) ...................................................... 462 12.3.18 Timer Output Control Register 2 (TOCR2) ...................................................... 466 12.3.19 Timer Output Level Buffer Register (TOLBR) ................................................ 469 12.3.20 Timer Gate Control Register (TGCR)............................................................... 470 12.3.21 Timer Subcounter (TCNTS) ............................................................................. 472 12.3.22 Timer Dead Time Data Register (TDDR) ......................................................... 473 12.3.23 Timer Cycle Data Register (TCDR) ................................................................. 473 12.3.24 Timer Cycle Buffer Register (TCBR) ............................................................... 474 12.3.25 Timer Interrupt Skipping Set Register (TITCR) ............................................... 474 12.3.26 Timer Interrupt Skipping Counter (TITCNT) ................................................... 476 12.3.27 Timer Buffer Transfer Set Register (TBTER) .................................................. 477 12.3.28 Timer Dead Time Enable Register (TDER) ...................................................... 479 12.3.29 Timer Waveform Control Register (TWCR) .................................................... 480 12.3.30 Bus Master Interface ......................................................................................... 481 Page xv of xxxiv 12.4 12.5 12.6 12.7 Operation .......................................................................................................................... 482 12.4.1 Basic Functions ................................................................................................. 482 12.4.2 Synchronous Operation..................................................................................... 488 12.4.3 Buffer Operation ............................................................................................... 490 12.4.4 Cascaded Operation .......................................................................................... 494 12.4.5 PWM Modes ..................................................................................................... 499 12.4.6 Phase Counting Mode ....................................................................................... 504 12.4.7 Reset-Synchronized PWM Mode...................................................................... 511 12.4.8 Complementary PWM Mode ............................................................................ 514 12.4.9 A/D Converter Start Request Delaying Function.............................................. 554 12.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation........................................................................................................... 558 Interrupt Sources ............................................................................................................... 559 12.5.1 Interrupt Sources and Priorities......................................................................... 559 12.5.2 Activation of Direct Memory Access Controller .............................................. 561 12.5.3 A/D Converter Activation ................................................................................. 561 Operation Timing.............................................................................................................. 563 12.6.1 Input/Output Timing ......................................................................................... 563 12.6.2 Interrupt Signal Timing .................................................................................... 570 Usage Notes ...................................................................................................................... 574 12.7.1 Module Standby Mode Setting ......................................................................... 574 12.7.2 Input Clock Restrictions ................................................................................... 574 12.7.3 Caution on Period Setting ................................................................................. 575 12.7.4 Contention between TCNT Write and Clear Operations .................................. 575 12.7.5 Contention between TCNT Write and Increment Operations ........................... 576 12.7.6 Contention between TGR Write and Compare Match ...................................... 577 12.7.7 Contention between Buffer Register Write and Compare Match ..................... 578 12.7.8 Contention between Buffer Register Write and TCNT Clear ........................... 579 12.7.9 Contention between TGR Read and Input Capture........................................... 580 12.7.10 Contention between TGR Write and Input Capture .......................................... 581 12.7.11 Contention between Buffer Register Write and Input Capture ......................... 582 12.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ........................................................................................................ 582 12.7.13 Counter Value during Complementary PWM Mode Stop ................................ 584 12.7.14 Buffer Operation Setting in Complementary PWM Mode ............................... 584 12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 585 12.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 586 12.7.17 Contention between Overflow/Underflow and Counter Clearing ..................... 587 12.7.18 Contention between TCNT Write and Overflow/Underflow ............................ 588 Page xvi of xxxiv 12.8 12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode ...................................................................... 588 12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode ....................................................................................................... 589 12.7.21 Interrupts in Module Standby Mode ................................................................. 589 12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection ........ 589 12.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode ........................................................................ 590 Output Pin Initialization for Multi-Function Timer Pulse Unit 2 ..................................... 592 12.8.1 Operating Modes............................................................................................... 592 12.8.2 Reset Start Operation ........................................................................................ 592 12.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc................ 593 12.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. .............................................................................. 594 Section 13 Compare Match Timer .......................................................................625 13.1 13.2 13.3 13.4 13.5 Features ............................................................................................................................. 625 Register Descriptions ........................................................................................................ 626 13.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 627 13.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 628 13.2.3 Compare Match Counter (CMCNT) ................................................................. 630 13.2.4 Compare Match Constant Register (CMCOR) ................................................. 630 Operation .......................................................................................................................... 631 13.3.1 Interval Count Operation .................................................................................. 631 13.3.2 CMCNT Count Timing ..................................................................................... 631 Interrupts ........................................................................................................................... 632 13.4.1 Interrupt Sources and DMA Transfer Requests ................................................ 632 13.4.2 Timing of Compare Match Flag Setting ........................................................... 632 13.4.3 Timing of Compare Match Flag Clearing ......................................................... 633 Usage Notes ...................................................................................................................... 634 13.5.1 Conflict between Write and Compare-Match Processes of CMCNT ............... 634 13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 635 13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT ................. 636 13.5.4 Compare Match between CMCNT and CMCOR ............................................. 636 Section 14 Watchdog Timer ................................................................................637 14.1 14.2 14.3 Features ............................................................................................................................. 637 Input/Output Pin ............................................................................................................... 638 Register Descriptions ........................................................................................................ 639 14.3.1 Watchdog Timer Counter (WTCNT) ................................................................ 639 Page xvii of xxxiv 14.4 14.5 14.3.2 Watchdog Timer Control/Status Register (WTCSR) ........................................ 640 14.3.3 Watchdog Reset Control/Status Register (WRCSR) ........................................ 643 14.3.4 Notes on Register Access.................................................................................. 644 Usage ................................................................................................................................ 646 14.4.1 Canceling Software Standby Mode................................................................... 646 14.4.2 Using Watchdog Timer Mode .......................................................................... 646 14.4.3 Using Interval Timer Mode .............................................................................. 648 Usage Notes ...................................................................................................................... 649 14.5.1 Timer Variation................................................................................................. 649 14.5.2 Prohibition against Setting H'FF to WTCNT .................................................... 649 14.5.3 Interval Timer Overflow Flag ........................................................................... 649 14.5.4 System Reset by WDTOVF Signal................................................................... 650 14.5.5 Manual Reset in Watchdog Timer Mode .......................................................... 650 14.5.6 Internal Reset in Watchdog Timer Mode .......................................................... 650 Section 15 Realtime Clock .................................................................................. 651 15.1 15.2 15.3 15.4 Features ............................................................................................................................. 651 Input/Output Pin ............................................................................................................... 653 Register Descriptions ........................................................................................................ 654 15.3.1 64-Hz Counter (R64CNT) ................................................................................ 655 15.3.2 Second Counter (RSECCNT) ........................................................................... 656 15.3.3 Minute Counter (RMINCNT) ........................................................................... 657 15.3.4 Hour Counter (RHRCNT)................................................................................. 658 15.3.5 Day of Week Counter (RWKCNT) .................................................................. 659 15.3.6 Date Counter (RDAYCNT) .............................................................................. 660 15.3.7 Month Counter (RMONCNT) .......................................................................... 661 15.3.8 Year Counter (RYRCNT) ................................................................................. 662 15.3.9 Second Alarm Register (RSECAR) .................................................................. 663 15.3.10 Minute Alarm Register (RMINAR) .................................................................. 664 15.3.11 Hour Alarm Register (RHRAR) ....................................................................... 665 15.3.12 Day of Week Alarm Register (RWKAR) ......................................................... 666 15.3.13 Date Alarm Register (RDAYAR) ..................................................................... 667 15.3.14 Month Alarm Register (RMONAR) ................................................................. 668 15.3.15 Year Alarm Register (RYRAR) ........................................................................ 669 15.3.16 Control Register 1 (RCR1) ............................................................................... 670 15.3.17 Control Register 2 (RCR2) ............................................................................... 672 15.3.18 Control Register 3 (RCR3) ............................................................................... 675 15.3.19 Control Register 5 (RCR5) ............................................................................... 676 15.3.20 Frequency Register H/L (RFRH/L) .................................................................. 677 Operation .......................................................................................................................... 679 Page xviii of xxxiv 15.5 15.4.1 Initial Settings of Registers after Power-On and Oscillation Settling Time...... 679 15.4.2 Setting Time ...................................................................................................... 679 15.4.3 Reading Time .................................................................................................... 680 15.4.4 Alarm Function ................................................................................................. 681 Usage Notes ...................................................................................................................... 682 15.5.1 Register Writing during Count.......................................................................... 682 15.5.2 Use of Realtime Clock Periodic Interrupts ....................................................... 682 15.5.3 Transition to Standby Mode after Setting Register ........................................... 682 15.5.4 Usage Notes when Writing to and Reading the Register .................................. 683 Section 16 Serial Communication Interface with FIFO ......................................685 16.1 16.2 16.3 16.4 16.5 16.6 Features ............................................................................................................................. 685 Input/Output Pins .............................................................................................................. 688 Register Descriptions ........................................................................................................ 689 16.3.1 Receive Shift Register (SCRSR)....................................................................... 692 16.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 692 16.3.3 Transmit Shift Register (SCTSR) ..................................................................... 693 16.3.4 Transmit FIFO Data Register (SCFTDR) ......................................................... 693 16.3.5 Serial Mode Register (SCSMR) ........................................................................ 694 16.3.6 Serial Control Register (SCSCR) ...................................................................... 697 16.3.7 Serial Status Register (SCFSR)......................................................................... 701 16.3.8 Bit Rate Register (SCBRR)............................................................................... 709 16.3.9 FIFO Control Register (SCFCR) ...................................................................... 715 16.3.10 FIFO Data Count Set Register (SCFDR) .......................................................... 718 16.3.11 Serial Port Register (SCSPTR) ......................................................................... 719 16.3.12 Line Status Register (SCLSR) .......................................................................... 722 16.3.13 Serial Extension Mode Register (SCEMR)....................................................... 723 Operation .......................................................................................................................... 724 16.4.1 Overview........................................................................................................... 724 16.4.2 Operation in Asynchronous Mode .................................................................... 727 16.4.3 Operation in Clock Synchronous Mode ............................................................ 738 Interrupts ........................................................................................................................... 747 Usage Notes ...................................................................................................................... 748 16.6.1 SCFTDR Writing and TDFE Flag .................................................................... 748 16.6.2 SCFRDR Reading and RDF Flag ..................................................................... 748 16.6.3 Restriction on Direct Memory Controller Usage .............................................. 749 16.6.4 Break Detection and Processing ....................................................................... 749 16.6.5 Sending a Break Signal ..................................................................................... 749 16.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)....................................................................................... 749 Page xix of xxxiv 16.6.7 Selection of Base Clock in Asynchronous Mode .............................................. 751 Section 17 Renesas Serial Peripheral Interface ................................................... 753 17.1 17.2 17.3 17.4 Features ............................................................................................................................. 753 Input/Output Pins .............................................................................................................. 756 Register Descriptions ........................................................................................................ 757 17.3.1 Control Register (SPCR)................................................................................... 760 17.3.2 Slave Select Polarity Register (SSLP) .............................................................. 762 17.3.3 Pin Control Register (SPPCR) .......................................................................... 763 17.3.4 Status Register (SPSR) ..................................................................................... 765 17.3.5 Data Register (SPDR) ....................................................................................... 768 17.3.6 Sequence Control Register (SPSCR) ................................................................ 769 17.3.7 Sequence Status Register (SPSSR) ................................................................... 771 17.3.8 Bit Rate Register (SPBR).................................................................................. 772 17.3.9 Data Control Register (SPDCR) ....................................................................... 774 17.3.10 Clock Delay Register (SPCKD)........................................................................ 776 17.3.11 Slave Select Negation Delay Register (SSLND) .............................................. 777 17.3.12 Next-Access Delay Register (SPND) ............................................................... 778 17.3.13 Command Register (SPCMD) .......................................................................... 779 17.3.14 Buffer Control Register (SPBFCR) .................................................................. 784 17.3.15 Buffer Data Count Setting Register (SPBFDR) ................................................ 786 Operation .......................................................................................................................... 787 17.4.1 Overview of Operations .................................................................................... 787 17.4.2 Pin Control ........................................................................................................ 788 17.4.3 System Configuration Example ........................................................................ 789 17.4.4 Transfer Format ................................................................................................ 792 17.4.5 Data Format ...................................................................................................... 794 17.4.6 Error Detection ................................................................................................. 806 17.4.7 Initialization ...................................................................................................... 811 17.4.8 SPI Operation.................................................................................................... 812 17.4.9 Error Handling .................................................................................................. 825 17.4.10 Loopback Mode ................................................................................................ 826 17.4.11 Interrupt Sources ............................................................................................... 827 Section 18 SPI Multi I/O Bus Controller ............................................................ 829 18.1 18.2 18.3 18.4 Features ............................................................................................................................. 829 Block Diagram .................................................................................................................. 830 Input/Output Pins .............................................................................................................. 831 Register Descriptions ........................................................................................................ 832 18.4.1 Common Control Register (CMNCR) .............................................................. 833 Page xx of xxxiv 18.5 18.6 18.4.2 SSL Delay Register (SSLDR) ........................................................................... 838 18.4.3 Bit Rate Register (SPBCR) ............................................................................... 840 18.4.4 Data Read Control Register (DRCR) ................................................................ 842 18.4.5 Data Read Command Setting Register (DRCMR) ............................................ 845 18.4.6 Data Read Extended Address Setting Register (DREAR) ................................ 846 18.4.7 Data Read Option Setting Register (DROPR) .................................................. 848 18.4.8 Data Read Enable Setting Register (DRENR) .................................................. 849 18.4.9 SPI Mode Control Register (SMCR) ................................................................ 853 18.4.10 SPI Mode Command Setting Register (SMCMR) ............................................ 855 18.4.11 SPI Mode Address Setting Register (SMADR) ................................................ 856 18.4.12 SPI Mode Option Setting Register (SMOPR) ................................................... 857 18.4.13 SPI Mode Enable Setting Register (SMENR)................................................... 858 18.4.14 SPI Mode Read Data Register 0 (SMRDR0) .................................................... 862 18.4.15 SPI Mode Read Data Register 1 (SMRDR1) .................................................... 863 18.4.16 SPI Mode Write Data Register 0 (SMWDR0) .................................................. 864 18.4.17 SPI Mode Write Data Register 1 (SMWDR1) .................................................. 865 18.4.18 Common Status Register (CMNSR) ................................................................. 866 18.4.19 AC Characteristics Adjustment Register (SPBACR) ........................................ 867 Operation .......................................................................................................................... 868 18.5.1 System Configuration ....................................................................................... 868 18.5.2 Address Map ..................................................................................................... 869 18.5.3 32-bit Serial Flash Addresses ............................................................................ 870 18.5.4 Data Alignment ................................................................................................. 871 18.5.5 Operating Modes............................................................................................... 871 18.5.6 External Address Space Read Mode ................................................................. 871 18.5.7 Read Cache ....................................................................................................... 877 18.5.8 SPI Operating Mode ......................................................................................... 878 18.5.9 Transfer Format ................................................................................................ 883 18.5.10 Data Format ...................................................................................................... 885 18.5.11 Data Pin Control ............................................................................................... 893 18.5.12 SPBSSL Pin Control ......................................................................................... 895 18.5.13 Flags .................................................................................................................. 896 Usage Notes ...................................................................................................................... 897 18.6.1 Notes on Transfer to Read Data in SPI Operating Mode .................................. 897 18.6.2 Notes on Starting Transfer from the SPBSSL Retained State in SPI Operating Mode ................................................................................................ 897 18.6.3 Note on Initialization ........................................................................................ 897 Page xxi of xxxiv Section 19 I2C Bus Interface 3 ............................................................................. 899 19.1 19.2 19.3 19.4 19.5 19.6 19.7 Features ............................................................................................................................. 899 Input/Output Pins .............................................................................................................. 901 Register Descriptions ........................................................................................................ 902 2 19.3.1 I C Bus Control Register 1 (ICCR1) ................................................................. 903 2 19.3.2 I C Bus Control Register 2 (ICCR2) ................................................................. 906 2 19.3.3 I C Bus Mode Register (ICMR) ........................................................................ 908 2 19.3.4 I C Bus Interrupt Enable Register (ICIER) ....................................................... 910 2 19.3.5 I C Bus Status Register (ICSR) ......................................................................... 912 19.3.6 Slave Address Register (SAR) .......................................................................... 915 2 19.3.7 I C Bus Transmit Data Register (ICDRT)......................................................... 915 2 19.3.8 I C Bus Receive Data Register (ICDRR) .......................................................... 916 2 19.3.9 I C Bus Shift Register (ICDRS) ........................................................................ 916 19.3.10 NF2CYC Register (NF2CYC) .......................................................................... 917 Operation .......................................................................................................................... 918 2 19.4.1 I C Bus Format.................................................................................................. 918 19.4.2 Master Transmit Operation ............................................................................... 919 19.4.3 Master Receive Operation................................................................................. 921 19.4.4 Slave Transmit Operation ................................................................................. 923 19.4.5 Slave Receive Operation ................................................................................... 926 19.4.6 Clocked Synchronous Serial Format................................................................. 927 19.4.7 Noise Filter ....................................................................................................... 931 19.4.8 Example of Use................................................................................................. 932 Interrupt Requests ............................................................................................................. 936 Bit Synchronous Circuit.................................................................................................... 937 Usage Notes ...................................................................................................................... 939 19.7.1 Note on Setting for Multi-Master Operation..................................................... 939 19.7.2 Note on Master Receive Mode ......................................................................... 939 19.7.3 Note on Setting ACKBT in Master Receive Mode ........................................... 940 19.7.4 Note on the States of Bits MST and TRN when Arbitration is Lost ................. 940 2 19.7.5 Note on I C-bus Interface Master Receive Mode.............................................. 940 19.7.6 Note on IICRST and BBSY bits ....................................................................... 940 19.7.7 Note on Issuance of Stop Conditions in Master Transmit Mode while ACKE = 1 ......................................................................................................... 940 Section 20 Serial Sound Interface ....................................................................... 941 20.1 20.2 20.3 Features ............................................................................................................................. 941 Input/Output Pins .............................................................................................................. 943 Register Description ......................................................................................................... 944 Page xxii of xxxiv 20.4 20.5 20.3.1 Control Register (SSICR) ................................................................................. 946 20.3.2 Status Register (SSISR) .................................................................................... 953 20.3.3 Transmit Data Register (SSITDR) .................................................................... 957 20.3.4 Receive Data Register (SSIRDR) ..................................................................... 957 20.3.5 FIFO Control Register (SSIFCR) ..................................................................... 958 20.3.6 FIFO Status Register (SSIFSR) ........................................................................ 961 20.3.7 Transmit FIFO Data Register (SSIFTDR) ........................................................ 964 20.3.8 Receive FIFO Data Register (SSIFRDR) ......................................................... 965 20.3.9 TDM Mode Register (SSITDMR) .................................................................... 966 Operation Description ....................................................................................................... 967 20.4.1 Bus Format ........................................................................................................ 967 20.4.2 Non-Compressed Modes ................................................................................... 969 20.4.3 TDM Mode ....................................................................................................... 980 20.4.4 WS Continue Mode........................................................................................... 981 20.4.5 Operation Modes............................................................................................... 982 20.4.6 Transmit Operation ........................................................................................... 983 20.4.7 Receive Operation............................................................................................. 986 20.4.8 Serial Bit Clock Control.................................................................................... 989 Usage Notes ...................................................................................................................... 990 20.5.1 Limitations from Underflow or Overflow during DMA Operation .................. 990 20.5.2 Note on Changing Mode from Master Transceiver to Master Receiver ........... 990 20.5.3 Limits on TDM mode and WS Continue Mode ................................................ 990 Section 21 Serial I/O with FIFO ..........................................................................993 21.1 21.2 21.3 21.4 Features ............................................................................................................................. 993 Input/Output Pins .............................................................................................................. 995 Register Descriptions ........................................................................................................ 996 21.3.1 Mode Register (SIMDR)................................................................................... 997 21.3.2 Control Register (SICTR) ................................................................................. 999 21.3.3 Transmit Data Register (SITDR) .................................................................... 1002 21.3.4 Receive Data Register (SIRDR) ..................................................................... 1003 21.3.5 Status Register (SISTR) .................................................................................. 1004 21.3.6 Interrupt Enable Register (SIIER)................................................................... 1009 21.3.7 FIFO Control Register (SIFCTR) ................................................................... 1011 21.3.8 Clock Select Register (SISCR) ....................................................................... 1013 21.3.9 Transmit Data Assign Register (SITDAR) ..................................................... 1014 21.3.10 Receive Data Assign Register (SIRDAR) ....................................................... 1016 Operation ........................................................................................................................ 1017 21.4.1 Serial Clocks ................................................................................................... 1017 21.4.2 Serial Timing .................................................................................................. 1018 Page xxiii of xxxiv 21.4.3 21.4.4 21.4.5 21.4.6 21.4.7 21.4.8 Transfer Data Format ...................................................................................... 1019 Register Allocation of Transfer Data .............................................................. 1020 FIFO................................................................................................................ 1022 Transmit and Receive Procedures ................................................................... 1024 Interrupts ......................................................................................................... 1029 Transmit and Receive Timing ......................................................................... 1031 Section 22 Controller Area Network ................................................................. 1035 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Summary ......................................................................................................................... 1035 22.1.1 Overview......................................................................................................... 1035 22.1.2 Scope .............................................................................................................. 1035 22.1.3 Audience ......................................................................................................... 1035 22.1.4 References....................................................................................................... 1036 22.1.5 Features ........................................................................................................... 1036 Architecture .................................................................................................................... 1037 Programming Model - Overview .................................................................................... 1040 22.3.1 Memory Map .................................................................................................. 1040 22.3.2 Mailbox Structure ........................................................................................... 1042 22.3.3 Control Registers ............................................................................................ 1058 22.3.4 Mailbox Registers ........................................................................................... 1079 22.3.5 Timer Registers ............................................................................................... 1093 Application Note ............................................................................................................. 1106 22.4.1 Test Mode Settings ......................................................................................... 1106 22.4.2 Configuration of This Module ........................................................................ 1108 22.4.3 Message Transmission Sequence .................................................................... 1112 22.4.4 Message Receive Sequence ............................................................................ 1127 22.4.5 Reconfiguration of Mailbox ............................................................................ 1129 Interrupt Sources ............................................................................................................. 1131 DMAC Interface ............................................................................................................. 1132 CAN Bus Interface.......................................................................................................... 1133 Setting I/O Ports ............................................................................................................. 1134 Usage Notes .................................................................................................................... 1136 22.9.1 Notes on Port Setting for Multiple Channels Used as Single Channel ........... 1136 Section 23 IEBusTM Controller ........................................................................... 1137 23.1 Features ........................................................................................................................... 1137 23.1.1 IEBus Communications Protocol .................................................................... 1138 23.1.2 Communications Protocol............................................................................... 1142 23.1.3 Transfer Data (Data Field Contents) ............................................................... 1150 23.1.4 Bit Format ....................................................................................................... 1153 Page xxiv of xxxiv 23.2 23.3 23.4 23.5 23.6 23.7 23.1.5 Configuration .................................................................................................. 1154 Input/Output Pins ............................................................................................................ 1155 Register Descriptions ...................................................................................................... 1156 23.3.1 IEBus Control Register (IECTR) .................................................................... 1158 23.3.2 IEBus Command Register (IECMR) .............................................................. 1159 23.3.3 IEBus Master Control Register (IEMCR) ....................................................... 1161 23.3.4 IEBus Master Unit Address Register 1 (IEAR1) ............................................ 1163 23.3.5 IEBus Master Unit Address Register 2 (IEAR2) ............................................ 1164 23.3.6 IEBus Slave Address Setting Register 1 (IESA1) ........................................... 1164 23.3.7 IEBus Slave Address Setting Register 2 (IESA2) ........................................... 1165 23.3.8 IEBus Transmit Message Length Register (IETBFL)..................................... 1166 23.3.9 IEBus Reception Master Address Register 1 (IEMA1) .................................. 1167 23.3.10 IEBus Reception Master Address Register 2 (IEMA2) .................................. 1168 23.3.11 IEBus Receive Control Field Register (IERCTL)........................................... 1169 23.3.12 IEBus Receive Message Length Register (IERBFL) ...................................... 1170 23.3.13 IEBus Lock Address Register 1 (IELA1) ....................................................... 1170 23.3.14 IEBus Lock Address Register 2 (IELA2) ....................................................... 1171 23.3.15 IEBus General Flag Register (IEFLG) ............................................................ 1172 23.3.16 IEBus Transmit Status Register (IETSR) ....................................................... 1175 23.3.17 IEBus Transmit Interrupt Enable Register (IEIET) ........................................ 1179 23.3.18 IEBus Receive Status Register (IERSR) ......................................................... 1181 23.3.19 IEBus Receive Interrupt Enable Register (IEIER) .......................................... 1185 23.3.20 IEBus Clock Selection Register (IECKSR) .................................................... 1186 23.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128) ................... 1188 23.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128) .................... 1189 Data Format .................................................................................................................... 1190 23.4.1 Transmission Format ...................................................................................... 1190 23.4.2 Reception Format ............................................................................................ 1191 Software Control Flows .................................................................................................. 1192 23.5.1 Initial Setting................................................................................................... 1192 23.5.2 Master Transmission ....................................................................................... 1193 23.5.3 Slave Reception .............................................................................................. 1194 23.5.4 Master Reception ............................................................................................ 1195 23.5.5 Slave Transmission ......................................................................................... 1196 Operation Timing ............................................................................................................ 1197 23.6.1 Master Transmit Operation ............................................................................. 1197 23.6.2 Slave Receive Operation ................................................................................. 1198 23.6.3 Master Receive Operation............................................................................... 1199 23.6.4 Slave Transmit Operation ............................................................................... 1200 Interrupt Sources ............................................................................................................. 1201 Page xxv of xxxiv 23.8 Usage Notes .................................................................................................................... 1203 23.8.1 Note on Operation when Transfer is Incomplete after Transfer of the Maximum Number of Bytes............................................................................ 1203 Section 24 Renesas SPDIF Interface ................................................................. 1205 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 24.10 24.11 24.12 24.13 Overview ........................................................................................................................ 1205 Features ........................................................................................................................... 1205 Functional Block Diagram .............................................................................................. 1206 Input/Output Pins ............................................................................................................ 1207 Renesas SPDIF (IEC60958) Frame Format .................................................................... 1207 Register ........................................................................................................................... 1209 Register Descriptions ...................................................................................................... 1210 24.7.1 Control Register (CTRL) ................................................................................ 1210 24.7.2 Status Register (STAT) ................................................................................... 1215 24.7.3 Transmitter Channel 1 Audio Register (TLCA) ............................................. 1219 24.7.4 Transmitter Channel 2 Audio Register (TRCA) ............................................. 1220 24.7.5 Transmitter DMA Audio Data Register (TDAD) ........................................... 1221 24.7.6 Transmitter User Data Register (TUI) ............................................................ 1222 24.7.7 Transmitter Channel 1 Status Register (TLCS) .............................................. 1223 24.7.8 Transmitter Channel 2 Status Register (TRCS) .............................................. 1225 24.7.9 Receiver Channel 1 Audio Register (RLCA).................................................. 1227 24.7.10 Receiver Channel 2 Audio Register (RRCA) ................................................. 1228 24.7.11 Receiver DMA Audio Data (RDAD).............................................................. 1229 24.7.12 Receiver User Data Register (RUI) ................................................................ 1230 24.7.13 Receiver Channel 1 Status Register (RLCS) .................................................. 1231 24.7.14 Receiver Channel 2 Status Register (RRCS) .................................................. 1233 Functional Description—Transmitter ............................................................................. 1235 24.8.1 Transmitter Module ........................................................................................ 1235 24.8.2 Transmitter Module Initialization ................................................................... 1236 24.8.3 Initial Settings for Transmitter Module .......................................................... 1236 24.8.4 Transmitter Module Data Transfer ................................................................. 1237 Functional Description—Receiver.................................................................................. 1239 24.9.1 Receiver Module ............................................................................................. 1239 24.9.2 Receiver Module Initialization ....................................................................... 1240 24.9.3 Receiver Module Data Transfer ...................................................................... 1240 Disabling the Module...................................................................................................... 1243 24.10.1 Transmitter and Receiver Idle ......................................................................... 1243 Compressed Mode Data .................................................................................................. 1243 References....................................................................................................................... 1243 Usage Notes .................................................................................................................... 1244 Page xxvi of xxxiv 24.13.1 24.13.2 Clearing TUIR ................................................................................................ 1244 Frequency of Clock Input for Audio ............................................................... 1244 Section 25 CD-ROM Decoder ...........................................................................1245 25.1 25.2 25.3 Features ........................................................................................................................... 1245 25.1.1 Formats Supported by CD-ROM Decoder ...................................................... 1246 Block Diagrams .............................................................................................................. 1247 Register Descriptions ...................................................................................................... 1251 25.3.1 Enable Control Register (CROMEN) ............................................................. 1254 25.3.2 Sync Code-Based Synchronization Control Register (CROMSY0) ............... 1255 25.3.3 Decoding Mode Control Register (CROMCTL0) .......................................... 1256 25.3.4 EDC/ECC Check Control Register (CROMCTL1) ........................................ 1258 25.3.5 Automatic Decoding Stop Control Register (CROMCTL3) ........................... 1259 25.3.6 Decoding Option Setting Control Register (CROMCTL4) ............................ 1260 25.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5) ........ 1262 25.3.8 Sync Code Status Register (CROMST0) ........................................................ 1263 25.3.9 Post-ECC Header Error Status Register (CROMST1) .................................... 1264 25.3.10 Post-ECC Subheader Error Status Register (CROMST3) .............................. 1265 25.3.11 Header/Subheader Validity Check Status Register (CROMST4) ................... 1266 25.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5).................................................................................................... 1267 25.3.13 ECC/EDC Error Status Register (CROMST6) ............................................... 1268 25.3.14 Buffer Status Register (CBUFST0) ................................................................ 1270 25.3.15 Decoding Stoppage Source Status Register (CBUFST1)................................ 1271 25.3.16 Buffer Overflow Status Register (CBUFST2) ................................................ 1272 25.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00) ................... 1272 25.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01) ................... 1273 25.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02) ....................................................................................................... 1273 25.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03) ....................... 1274 25.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00)..................................................................................................... 1274 25.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01)..................................................................................................... 1275 25.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02)..................................................................................................... 1275 25.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03)..................................................................................................... 1276 25.3.25 Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04)..................................................................................................... 1276 Page xxvii of xxxiv 25.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05)..................................................................................................... 1277 25.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06)..................................................................................................... 1277 25.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07)..................................................................................................... 1278 25.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20) ................. 1278 25.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21) ................. 1279 25.3.31 Post-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD22) ....................................................................................................... 1279 25.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23) ..................... 1280 25.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20)..................................................................................................... 1280 25.3.34 Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21)..................................................................................................... 1281 25.3.35 Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22)..................................................................................................... 1281 25.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23)..................................................................................................... 1282 25.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24)..................................................................................................... 1282 25.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25)..................................................................................................... 1283 25.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26)..................................................................................................... 1283 25.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27)..................................................................................................... 1284 25.3.41 Automatic Buffering Setting Control Register 0 (CBUFCTL0) ..................... 1284 25.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1) .................................................................................................. 1286 25.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2) .................................................................................................. 1286 25.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3) .................................................................................................. 1287 25.3.45 ISY Interrupt Source Mask Control Register (CROMST0M) ........................ 1287 25.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST) ......................... 1288 25.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT) .................................. 1289 25.3.48 Serial Sound Interface Data Control Register (SSI)........................................ 1289 25.3.49 Interrupt Flag Register (INTHOLD) ............................................................... 1292 25.3.50 Interrupt Source Mask Control Register (INHINT) ........................................ 1293 Page xxviii of xxxiv 25.4 25.5 25.6 25.3.51 CD-ROM Decoder Stream Data Input Register (STRMDIN0) ...................... 1294 25.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN2) ...................... 1294 25.3.53 CD-ROM Decoder Stream Data Output Register (STRMDOUT0)................ 1295 Operation ........................................................................................................................ 1296 25.4.1 Endian Conversion for Data in the Input Stream ............................................ 1296 25.4.2 Sync Code Maintenance Function .................................................................. 1297 25.4.3 Error Correction .............................................................................................. 1302 25.4.4 Automatic Decoding Stop Function ................................................................ 1303 25.4.5 Buffering Format ............................................................................................ 1304 25.4.6 Target-Sector Buffering Function ................................................................... 1306 Interrupt Sources ............................................................................................................. 1308 25.5.1 Interrupt and DMA Transfer Request Signals................................................. 1308 25.5.2 Timing of Status Registers Updates ................................................................ 1310 Usage Notes .................................................................................................................... 1310 25.6.1 Stopping and Resuming Buffering Alone during Decoding ........................... 1310 25.6.2 When CROMST0 Status Register Bits are Set ............................................... 1310 25.6.3 Link Blocks ..................................................................................................... 1311 25.6.4 Stopping and Resuming CD-DSP Operation .................................................. 1311 25.6.5 Note on Clearing the IREADY Flag ............................................................... 1311 25.6.6 Note on Stream Data Transfer (1) ................................................................... 1312 25.6.7 Note on Stream Data Transfer (2) ................................................................... 1312 Section 26 A/D Converter..................................................................................1313 26.1 26.2 26.3 26.4 26.5 26.6 26.7 Features ........................................................................................................................... 1313 Input/Output Pins ............................................................................................................ 1315 Register Descriptions ...................................................................................................... 1316 26.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ........................................ 1317 26.3.2 A/D Control/Status Register (ADCSR) .......................................................... 1318 Operation ........................................................................................................................ 1322 26.4.1 Single Mode .................................................................................................... 1322 26.4.2 Multi Mode ..................................................................................................... 1325 26.4.3 Scan Mode ...................................................................................................... 1327 26.4.4 A/D Converter Activation by External Trigger or Multi-Function Timer Pulse Unit 2 .................................................................................................. 1330 26.4.5 Input Sampling and A/D Conversion Time..................................................... 1330 26.4.6 External Trigger Input Timing ........................................................................ 1333 Interrupt Sources and DMA Transfer Request................................................................ 1334 Definitions of A/D Conversion Accuracy ....................................................................... 1335 Usage Notes .................................................................................................................... 1336 26.7.1 Module Standby Mode Setting ....................................................................... 1336 Page xxix of xxxiv 26.7.2 26.7.3 26.7.4 26.7.5 26.7.6 26.7.7 Setting Analog Input Voltage ......................................................................... 1336 Notes on Board Design ................................................................................... 1336 Processing of Analog Input Pins ..................................................................... 1337 Permissible Signal Source Impedance ............................................................ 1338 Influences on Absolute Precision.................................................................... 1339 Note on Usage in Scan Mode and Multi Mode ............................................... 1339 Section 27 USB 2.0 Host/Function Module ...................................................... 1341 27.1 27.2 27.3 Features ........................................................................................................................... 1341 Input/Output Pins ............................................................................................................ 1343 Register Description ....................................................................................................... 1344 27.3.1 System Configuration Control Register 0 (SYSCFG0) .................................. 1347 27.3.2 System Configuration Control Register 1 (SYSCFG1) .................................. 1350 27.3.3 System Configuration Status Registers (SYSSTS0, SYSSTS1) ..................... 1352 27.3.4 Device State Control Registers (DVSTCTR0, DVSTCTR1) ......................... 1354 27.3.5 DMA-FIFO Pin Configuration Registers (DMA0PCFG, DMA1PCFG) ........ 1364 27.3.6 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) .......................................... 1365 27.3.7 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)........... 1367 27.3.8 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ...... 1375 27.3.9 Interrupt Enable Register 0 (INTENB0) ......................................................... 1379 27.3.10 Interrupt Enable Registers 1 and 2 (INTENB1 and INTENB2) ..................... 1381 27.3.11 BRDY Interrupt Enable Register (BRDYENB) ............................................. 1385 27.3.12 NRDY Interrupt Enable Register (NRDYENB) ............................................. 1387 27.3.13 BEMP Interrupt Enable Register (BEMPENB) .............................................. 1389 27.3.14 SOF Output Configuration Register (SOFCFG) ............................................. 1391 27.3.15 Interrupt Status Register 0 (INTSTS0) ........................................................... 1392 27.3.16 Interrupt Status Registers 1 and 2 (INTSTS1 and INTSTS2) ......................... 1397 27.3.17 BRDY Interrupt Status Register (BRDYSTS) ................................................ 1408 27.3.18 NRDY Interrupt Status Register (NRDYSTS) ............................................... 1410 27.3.19 BEMP Interrupt Status Register (BEMPSTS) ................................................ 1412 27.3.20 Frame Number Register (FRMNUM)............................................................. 1414 27.3.21 USB Address Register (USBADDR) .............................................................. 1416 27.3.22 USB Request Type Register (USBREQ) ........................................................ 1417 27.3.23 USB Request Value Register (USBVAL)....................................................... 1418 27.3.24 USB Request Index Register (USBINDX) ..................................................... 1419 27.3.25 USB Request Length Register (USBLENG) .................................................. 1420 27.3.26 DCP Configuration Register (DCPCFG) ........................................................ 1421 27.3.27 DCP Maximum Packet Size Register (DCPMAXP)....................................... 1423 27.3.28 DCP Control Register (DCPCTR) .................................................................. 1425 27.3.29 Pipe Window Select Register (PIPESEL) ....................................................... 1433 Page xxx of xxxiv 27.4 27.5 27.3.30 Pipe Configuration Register (PIPECFG) ........................................................ 1435 27.3.31 Pipe Maximum Packet Size Register (PIPEMAXP) ....................................... 1441 27.3.32 Pipe Timing Control Register (PIPEPERI) ..................................................... 1443 27.3.33 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9) ......................................... 1445 27.3.34 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5) ......... 1464 27.3.35 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) .................... 1467 27.3.36 Device Address n Configuration Registers (DEVADDn) (n = 0 to 5) ............ 1469 Operation ........................................................................................................................ 1471 27.4.1 System Control and Oscillation Control ......................................................... 1471 27.4.2 Interrupt Functions .......................................................................................... 1475 27.4.3 Pipe Control .................................................................................................... 1496 27.4.4 FIFO Buffer Memory ...................................................................................... 1505 27.4.5 Control Transfers (DCP) ................................................................................. 1511 27.4.6 Bulk Transfers (PIPE1 to PIPE5).................................................................... 1515 27.4.7 Interrupt Transfers (PIPE6 to PIPE9) ............................................................. 1515 27.4.8 Isochronous Transfers (PIPE1 and PIPE2) ..................................................... 1516 27.4.9 SOF Interpolation Function ............................................................................ 1528 27.4.10 Pipe Schedule .................................................................................................. 1529 Usage Notes .................................................................................................................... 1531 27.5.1 USB Pin Control ............................................................................................. 1531 Section 28 Sampling Rate Converter .................................................................1533 28.1 28.2 28.3 28.4 28.5 Features ........................................................................................................................... 1533 Register Descriptions ...................................................................................................... 1535 28.2.1 Input Data Register (SRCID) .......................................................................... 1536 28.2.2 Output Data Register (SRCOD) ...................................................................... 1537 28.2.3 Input Data Control Register (SRCIDCTRL) ................................................... 1538 28.2.4 Output Data Control Register (SRCODCTRL) .............................................. 1540 28.2.5 Control Register (SRCCTRL) ......................................................................... 1542 28.2.6 Status Register (SRCSTAT) ........................................................................... 1548 Operation ........................................................................................................................ 1553 28.3.1 Initial Setting................................................................................................... 1553 28.3.2 Data Input ....................................................................................................... 1554 28.3.3 Data Output ..................................................................................................... 1556 Interrupts ......................................................................................................................... 1558 Usage Notes .................................................................................................................... 1559 28.5.1 Notes on Accessing Registers ......................................................................... 1559 28.5.2 Notes on Flush Processing .............................................................................. 1559 Section 29 SD Host Interface.............................................................................1561 Page xxxi of xxxiv Section 30 On-Chip RAM ................................................................................. 1563 30.1 30.2 Features ........................................................................................................................... 1563 Usage Notes .................................................................................................................... 1566 30.2.1 Page Conflict .................................................................................................. 1566 30.2.2 RAME and RAMWE Bits .............................................................................. 1566 30.2.3 Data Retention ................................................................................................ 1567 Section 31 General Purpose I/O Ports ............................................................... 1569 31.1 31.2 Features ........................................................................................................................... 1569 Register Descriptions ...................................................................................................... 1576 31.2.1 Control Registers ............................................................................................ 1579 31.2.2 I/O Registers ................................................................................................... 1618 31.2.3 Data Registers ................................................................................................. 1621 31.2.4 Port Registers .................................................................................................. 1625 31.2.5 Serial Sound Interface Noise Canceler Control Register (SNCR) .................. 1629 Section 32 Power-Down Modes ........................................................................ 1631 32.1 32.2 Features ........................................................................................................................... 1631 32.1.1 Power-Down Modes ....................................................................................... 1631 Register Descriptions ...................................................................................................... 1634 32.2.1 Standby Control Register 1 (STBCR1) ........................................................... 1635 32.2.2 Standby Control Register 2 (STBCR2) ........................................................... 1636 32.2.3 Standby Control Register 3 (STBCR3) ........................................................... 1638 32.2.4 Standby Control Register 4 (STBCR4) ........................................................... 1640 32.2.5 Standby Control Register 5 (STBCR5) ........................................................... 1642 32.2.6 Standby Control Register 6 (STBCR6) ........................................................... 1644 32.2.7 Standby Control Register 7 (STBCR7) ........................................................... 1646 32.2.8 Standby Control Register 8 (STBCR8) ........................................................... 1648 32.2.9 Software Reset Control Register (SWRSTCR)............................................... 1649 32.2.10 System Control Register 1 (SYSCR1) ............................................................ 1651 32.2.11 System Control Register 2 (SYSCR2) ............................................................ 1653 32.2.12 System Control Register 3 (SYSCR3) ............................................................ 1655 32.2.13 System Control Register 4 (SYSCR4) ............................................................ 1657 32.2.14 System Control Register 5 (SYSCR5) ............................................................ 1659 32.2.15 On-Chip Data-Retention RAM Area Setting Register (RRAMKP) ............... 1661 32.2.16 Deep Standby Control Register (DSCTR) ...................................................... 1663 32.2.17 Deep Standby Cancel Source Select Register (DSSSR) ................................. 1664 32.2.18 Deep Standby Cancel Edge Select Register (DSESR) .................................... 1667 32.2.19 Deep Standby Cancel Source Flag Register (DSFR) ...................................... 1669 32.2.20 XTAL Crystal Oscillator Gain Control Register (XTALCTR)....................... 1672 Page xxxii of xxxiv 32.3 32.4 Operation ........................................................................................................................ 1673 32.3.1 Sleep Mode ..................................................................................................... 1673 32.3.2 Software Standby Mode .................................................................................. 1674 32.3.3 Software Standby Mode Application Example ............................................... 1677 32.3.4 Deep Standby Mode........................................................................................ 1678 32.3.5 Module Standby Function ............................................................................... 1684 32.3.6 Adjustment of XTAL Crystal Oscillator Gain ................................................ 1684 Usage Notes .................................................................................................................... 1686 32.4.1 Usage Notes on Setting Registers ................................................................... 1686 32.4.2 Usage Notes when the Realtime Clock is not Used ........................................ 1686 Section 33 User Debugging Interface ................................................................1687 33.1 33.2 33.3 33.4 33.5 33.6 33.7 Features ........................................................................................................................... 1687 Input/Output Pins ............................................................................................................ 1688 Description of the Boundary Scan TAP Controller ........................................................ 1689 33.3.1 Bypass Register (BSBPR) ............................................................................... 1689 33.3.2 Instruction Register (BSIR) ............................................................................ 1689 33.3.3 Boundary Scan Register (SDBSR) ................................................................. 1691 33.3.4 ID Register (BSID) ......................................................................................... 1695 Description of the Emulation TAP Controller ................................................................ 1696 33.4.1 Bypass Register (SDBPR) .............................................................................. 1696 33.4.2 Instruction Register (SDIR) ............................................................................ 1696 Operation ........................................................................................................................ 1698 33.5.1 TAP Controller ............................................................................................... 1698 33.5.2 Reset Configuration ........................................................................................ 1699 33.5.3 TDO Output Timing ....................................................................................... 1699 33.5.4 User Debugging Interface Reset ..................................................................... 1700 33.5.5 User Debugging Interface Interrupt ................................................................ 1700 Boundary Scan ................................................................................................................ 1701 33.6.1 Supported Instructions .................................................................................... 1701 33.6.2 Notes ............................................................................................................... 1702 Usage Notes .................................................................................................................... 1703 Section 34 List of Registers ...............................................................................1705 34.1 34.2 34.3 Register Addresses (by functional module, in order of the corresponding section numbers)..................... 1707 Register Bits .................................................................................................................... 1737 Register States in Each Operating Mode ........................................................................ 1802 Page xxxiii of xxxiv Section 35 Electrical Characteristics ................................................................. 1805 35.1 35.2 35.3 35.4 35.5 Absolute Maximum Ratings ........................................................................................... 1805 Power-On/Power-Off Sequence...................................................................................... 1806 DC Characteristics .......................................................................................................... 1807 AC Characteristics .......................................................................................................... 1813 35.4.1 Clock Timing .................................................................................................. 1813 35.4.2 Control Signal Timing .................................................................................... 1818 35.4.3 Bus Timing ..................................................................................................... 1819 35.4.4 Direct Memory Access Controller Timing ..................................................... 1845 35.4.5 Multi-Function Timer Pulse Unit 2 Timing .................................................... 1846 35.4.6 Watchdog Timer Timing................................................................................. 1847 35.4.7 Serial Communication Interface with FIFO Timing ....................................... 1848 35.4.8 Renesas Serial Peripheral Interface Timing .................................................... 1849 35.4.9 SPI Multi I/O Bus Controller Timing ............................................................. 1853 2 35.4.10 I C Bus Interface 3 Timing ............................................................................. 1856 35.4.11 Serial Sound Interface Timing ........................................................................ 1858 35.4.12 Serial I/O with FIFO Timing .......................................................................... 1860 35.4.13 A/D Converter Timing .................................................................................... 1862 35.4.14 USB 2.0 Host/Function Module Timing ......................................................... 1863 35.4.15 SD Host Interface Timing ............................................................................... 1864 35.4.16 User Debugging Interface Timing .................................................................. 1865 35.4.17 AC Characteristics Measurement Conditions ................................................. 1867 A/D Converter Characteristics ........................................................................................ 1867 Section 36 States and Handling of Pins ............................................................. 1869 36.1 36.2 36.3 36.4 Pin States ........................................................................................................................ 1869 Treatment of Unused Pins............................................................................................... 1877 Handling of Pins in Deep Standby Mode........................................................................ 1878 Recommended Combination of Bypass Capacitor ......................................................... 1879 Appendix ........................................................................................................... 1881 A. Package Dimensions ....................................................................................................... 1881 Index ................................................................................................................. 1885 Page xxxiv of xxxiv SH726A Group, SH726B Group Section 1 Overview Section 1 Overview 1.1 SH726A/726B Features This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes a Renesas-original RISC CPU as its core, and the peripheral functions required to configure a system. The CPU in this LSI is an SH-2A CPU, which provides upward compatibility for SH-1, SH-2, and SH-2E CPUs at object code level. It has a RISC-type instruction set, superscalar architecture, and Harvard architecture, for superior rates of instruction execution. In addition, the 32-bit internal-bus architecture that is independent from the direct memory access controller enhances data processing power. This CPU brings the user the ability to set up high-performance systems with strong functionality at less expense than was achievable with previous microcontrollers, and is even able to handle realtime control applications requiring high-speed characteristics. This LSI has a floating-point unit and cache. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a 64-Kbyte RAM for high-speed operation, a 1.25-Mbyte large-capacity RAM (128-Kbytes are shared by the data-retention RAM), RAM for data storage, multi-function timer pulse unit 2, compare match timer, realtime clock, serial 2 communication interface with FIFO, I C bus interface 3, serial sound interface, serial I/O with 2 TM 1 FIFO, controller area network interface* , IEBus * controller, Renesas SPDIF interface, Renesas serial peripheral interface, SPI multi I/O bus controller, CD-ROM decoder, A/D converter, USB 2.0 host/function, SD host interface, and interrupt controller modules, and general I/O ports. This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. The features of this LSI are listed in table 1.1. Notes: 1. IEBus (Inter Equipment Bus) is a trademark of Renesas Electronics Corporation. 2. This module is included or not depending on the product code. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 1 of 1910 SH726A Group, SH726B Group Section 1 Overview Table 1.1 SH726A/726B Features Items Specification CPU  Renesas original SuperH architecture  Compatible with SH-1, SH-2, and SH-2E at object code level  32-bit internal data bus  General register architecture  Sixteen 32-bit general registers  Four 32-bit control registers  Four 32-bit system registers  Register bank for high-speed response to interrupts  RISC-type instruction set (upward compatible with SH series)  Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability  Load/store architecture  Delayed branch instructions  Instruction set based on C language Page 2 of 1910  Superscalar architecture to execute two instructions at one time including a floating-point unit  Instruction execution time: Up to two instructions/cycle  Address space: 4 Gbytes  Internal multiplier  Five-stage pipeline  Harvard architecture R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Items Specification Floating-point unit  Floating-point co-processor included  Supports single-precision (32-bit) and double-precision (64-bit)  Supports data type and exceptions that conforms to IEEE754 standard  Two rounding modes: Round to nearest and round to zero  Two denormalization modes: Flush to zero  Floating-point registers  Sixteen 32-bit floating-point registers (single-precision  16 words or double-precision  8 words)  Two 32-bit floating-point system registers  Supports FMAC (multiplication and accumulation) instructions  Supports FDIV (division) and FSQRT (square root) instructions  Supports FLDI0/FLDI1 (load constant 0/1) instructions  Instruction execution time  Latency (FMAC/FADD/FSUB/FMUL): Three cycles (singleprecision), eight cycles (double-precision)  Pitch (FMAC/FADD/FSUB/FMUL): One cycle (single-precision), six cycles (double-precision) Note: FMAC only supports single-precision Cache memory Interrupt controller  Five-stage pipeline  Instruction cache: 8 Kbytes  Operand cache: 8 Kbytes  128-entry/way, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache  Write-back, write-through, LRU replacement algorithm  Way lock function available (only for operand cache); ways 2 and 3 can be locked  SH726A: Thirteen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT5,4,1,0) SH726B: Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to PINT0)  On-chip peripheral interrupts: Priority level set for each module  16 priority levels available  Register bank enabling fast register saving and restoring in interrupt processing R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 3 of 1910 SH726A Group, SH726B Group Section 1 Overview Items Specification Bus state controller  Address space SH726A: Two ranges, each containing up to 8 Mbytes, are divided into areas 0 and 3. SH726B: Five ranges, each containing up to 64 Mbytes, are divided into areas 0 to 4.  The following features settable for each area independently  Bus size (8 or 16 bits): Available sizes depend on the area.  Number of access wait cycles (different wait cycles can be specified for read and write access cycles in some areas)  Idle wait cycle insertion (between the same area access cycles or different area access cycles)  Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, SDRAM, and burst ROM (clocked synchronous or asynchronous).  Outputs a chip select signal (CS0 to CS4) according to the target area (CS assert or negate timing can be selected by software)  SDRAM refresh Auto refresh or self refresh mode selectable  Direct memory access  controller  SDRAM burst access Sixteen channels; external requests are available for one of them. Can be activated by on-chip peripheral modules  Burst mode and cycle steal mode  Intermittent mode available (16 and 64 cycles supported)  Transfer information can be automatically reloaded Clock pulse generator  Clock mode: Input clock can be selected from external input (EXTAL) or crystal resonator  Input clock can be multiplied by 18 (max.) by the internal PLL circuit  Three types of clocks generated:  CPU clock: Maximum 216 MHz  Bus clock: Maximum 72 MHz  Peripheral clock: Maximum 36 MHz Watchdog timer Page 4 of 1910  On-chip one-channel watchdog timer  A counter overflow can reset the LSI R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Items Specification Power-down modes  Four power-down modes provided to reduce the power consumption in this LSI  Sleep mode  Software standby mode  Deep standby mode  Module standby mode Multi-function timer pulse unit 2  Maximum 16 lines of pulse inputs/outputs based on fix channels of 16bit timers  18 output compare and input capture registers  Input capture function  Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes  Synchronization of multiple counters  Complementary PWM output mode  Non-overlapping waveforms output for 3-phase inverter control  Automatic dead time setting  0% to 100% PWM duty value specifiable  A/D converter start request delaying function  Interrupt skipping at crest or trough  Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty value  Phase counting mode Two-phase encoder pulse counting available Compare match timer  Realtime clock Two-channel 16-bit counters  Four types of clock can be selected (P/8, P/32, P/128, and P/512)  DMA transfer request or interrupt request can be issued when a compare match occurs  Internal clock, calendar function, alarm function  Interrupts can be generated at intervals of 1/64 s by the 4 MHz on-chip crystal oscillator R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 5 of 1910 SH726A Group, SH726B Group Section 1 Overview Items Specification Serial communication  interface with FIFO  Renesas serial peripheral interface SPI multi I/O bus controller 2 I C bus interface 3 Page 6 of 1910 Five channels Clocked synchronous or asynchronous mode selectable  Simultaneous transmission and reception (full-duplex communication) supported  Dedicated baud rate generator  Separate 16-byte FIFO registers for transmission and reception  Modem control function (channel 0 to 2 in asynchronous mode)  SH726A: two channels (channels 0 and 1), SH726B: three channels  SPI operation  Master mode and slave mode selectable  Programmable bit length, clock polarity, and clock phase can be selected.  Consecutive transfers  MSB first/LSB first selectable  Maximum transfer rate: 36 Mbps  Up to two serial flash memories with multiple I/O functionality (single/dual/quad) can be connected.  External address space read mode (built-in read cache provided)  SPI operating mode  Clock polarity and clock phase can be selected.  Maximum transfer rate: 576.00 Mbps (when two serial flash memories are connected)  Four channels  Master mode and slave mode supported R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Items Section 1 Overview Specification Serial sound interface  Four-channel bidirectional serial transfer  Duplex communication (channel 0, 1)  Support of various real audio formats  Support of master and slave functions  Generation of programmable word clock and bit clock  Multi-channel formats  Support of 8, 16, 18, 20, 22, 24, and 32-bit data formats  Support of eight-stage FIFO for transmission and reception  Support TDM mode  Support WS continue mode which does not stop but operate SSIWS signal  Support of 16-stage 32-bits FIFOs independently for transmission and reception  8-bit monaural/16-bit monaural/16-bit stereo audio input and output  Connectable to linear, audio, or A-Law or -Law CODEC chip  Support of master and slave functions Controller area network  Two channels  TTCAN level 1 supports for all channels Note: This module is included or not depending on the product code.  BOSCH 2.0B active compatible  Buffer size: transmit/receive  31, receive only  1  Two or more controller area network channels can be assigned to one bus to increase number of buffers with a granularity of 32 channels  31 Mailboxes for transmission or reception Serial I/O with FIFO R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 7 of 1910 SH726A Group, SH726B Group Section 1 Overview Items IEBus Specification TM controller  IEBus protocol control (layer 2) supported  Half-duplex asynchronous communications  Multi-master system  Broadcast communications function  Selectable mode (three types) with different transfer speeds  On-chip buffers (dual port RAM) for data transmission and reception that enable up to 128 bytes of consecutive transmit/reception (maximum number of transfer bytes in mode 2) Operating frequency  12 MHz, 12.58 MHz (1/2 divided clocks)  18 MHz, 18.87 MHz (1/3 divided clocks)  24 MHz, 25.16 MHz (1/4 divided clocks)  30 MHz, 31.45 MHz (1/5 divided clocks)  36 MHz, 37.74 MHz (1/6 divided clocks)  42 MHz, 44.03 MHz (1/7 divided clocks)  48 MHz (1/8 divided clocks) Renesas SPDIF interface Page 8 of 1910  Support of IEC60958 standard (stereo and consumer use modes only)  Sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz  Audio word sizes of 16 to 24 bits per sample  Biphase mark encoding  Double buffered data  Parity encoded serial data  Simultaneous transmit and receive  Receiver autodetects IEC 61937 compressed mode data R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Items Specification CD-ROM decoder  Support of five formats: Mode 0, mode 1, mode 2, mode 2 form 1, and mode 2 form 2  Sync codes detection and protection (Protection: When a sync code is not detected, it is automatically inserted.)  Descrambling  ECC correction  P, Q, PQ, and QP correction  PQ or QP correction can be repeated up to three times  EDC check Performed before and after ECC  Mode and form are automatically detected  Link sectors are automatically detected  Buffering data control Buffering CD-ROM data including Sync code is transferred in specified format, after the data is descrambled, corrected by ECC, and checked by EDC. USB 2.0 host/function  module  Sampling rate converter SD host interface Conforms to the Universal Serial Bus Specification Revision 2.0 12-Mbps transfer rates provided (host mode, function mode)  On-chip 2-Kbyte RAM as communication buffers  Data format: 32-bit stereo (16 bits each to L/R), 16-bit monaural  Input sampling rate: 8/11.025/12/16/22.05/24/32/44.1/48kHz  Output sampling rate: 32/44.1/48 kHz, 8/16 kHz (When input sampling rate is 44.1 KHz)  SD memory I/O card interface (1-/4-bits SD bus)  Error check function: CRC7 (command), CRC16 (data)  Interrupt requests  Card access interrupt  SDIO access interrupt  Card detect interrupt  DMA transfer requests  SD_BUF write  SD_BUF read  R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Card detect function, write protect supported Page 9 of 1910 SH726A Group, SH726B Group Section 1 Overview Items Specification General I/O ports  SH726A: 57 I/Os, 8 inputs with open-drain outputs, and 8 inputs  SH726B: 74 I/Os, 8 inputs with open-drain outputs, and 12 inputs  Input or output can be selected for each bit  10-bit resolution  Input A/D converter SH726A: six channels SH726B: eight channels User break controller User debugging interface On-chip RAM Boot modes  A/D conversion request by the external trigger or timer trigger  Break channels: two channels  Possible to set an address, data value, access type, and data size as break conditions.  E10A emulator support  JTAG-standard pin assignment  64-Kbyte memory for high-speed operation (16 Kbytes  4)  1.25-Mbyte large capacity memory for video display/recording and work (128-Kbytes are used for data retention)  128-Kbyte memory for data retention (16 Kbytes 2, 32 Kbytes1, 64 Kbytes1)  Two boot modes (boot modes 0 and 1) Boot mode 0: Booting from memory connected to CS0 area Boot mode 1: Booting from a serial flash memory Power supply voltage Packages  Vcc: 1.15 to 1.35 V  PVcc: 3.0 to 3.6 V SH726A (1)  120-pin QFP, 16-mm square, 0.5-mm pitch JEITA package code: P-LQFP120-16  16-0.50 Renesas code: PLQP0120KA-A SH726A (2)  120-pin QFP, 14-mm square, 0.4-mm pitch JEITA package code: P-LQFP120-14  14-0.40 Renesas code: PLQP0120LA-A SH726B  Page 10 of 1910 144-pin QFP, 20-mm square, 0.5-mm pitch JEITA package code: P-LQFP144-20  20-0.50 Renesas code: PLQP0144KA-A R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 1.2 Table 1.2 Section 1 Overview Product Lineup Product Lineup Product Classification Product Code Controller Area Network Operating Temperature Quality Level SH726A Group R5S726A0D216FP Not included -40 to +85°C Package Industry usage etc. PLQP0120KA-A R5S726A1P216FP (120-pin LQFP, 16-mm square, Industry usage etc. 0.5-mm pitch) Car Accessories R5S726A2D216FP Not included Industry usage etc. PLQP0120LA-A R5S726A2P216FP (120-pin LQFP, 14-mm square, Industry usage etc. 0.4-mm pitch) Car Accessories R5S726A0P216FP R5S726A1D216FP Included R5S726A3D216FP Included R5S726A3P216FP SH726B Group R5S726B0D216FP Not included R5S726B0P216FP R5S726B1D216FP Included R5S726B1P216FP R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Car Accessories Car Accessories Industry usage etc. PLQP0144KA-A (144-pin LQFP, 20-mm square, Industry usage etc. 0.5-mm pitch) Car Accessories Car Accessories Page 11 of 1910 SH726A Group, SH726B Group Section 1 Overview 1.3 Block Diagram SH-2A CPU core Floating-point unit CPU instruction fetch bus (F bus) CPU memory access bus (M bus) Instruction cache memory 8KB Cache controller High-speed on-chip RAM 64KB Operand cache memory 8KB CPU bus (C bus) (I clock) User break controller Internal CPU bus (IC-BUS) Internal DMA bus (ID-BUS) Port Peripheral bus 1 controller DMA controller Peripheral bus 0 controller Bus state controller Large-capacity on-chip RAM0 Large-capacity on-chip RAM1 Large-capacity on-chip RAM2 Large-capacity on-chip RAM3 Large-capacity on-chip RAM4 Internal bus (I bus) (B clock) SPI multiI/O bus controller DREQ input DACK output TEND output Port Port External bus input/output External bus input/output Peripheral bus 0 (B clock) Renesas serial peripheral interface Clock pulse generator Port EXTAL input XTAL output CKIO I/O Clock mode input Interrupt controller Port RES input NMI input IRQ input PINT input USB 2.0 host/function module CD-ROM decoder A/D Converter Port Port Port Serial I/O USB bus I/O Analog input ADTRG input Multi-funciton timer pulse unit 2 Compare match timer Port Timer pulse I/O Watchdog timer Realtime clock Port Port User debugging interface Power-down mode control General I/O port Port Port JTAG I/O General I/O Renesas SPDIF interface Port Port SD card interface Serial I/O audio clock input I/O Serial communication interface with FIFL WDTOVF output RTC_X1 input RTC_X2 output SD host interface Serial sound interface I2C bus interface 3 Port Port Serial I/O I2C bus I/O Peripheral bus 1 (P clock) Serial I/O with FIFO Controller area network Port Port Port Serial I/O audio clock input Serial I/O audio clock input CAN bus I/O TM IEBus controller Port IEBus I/O audio clock input Sampling rate converter Figure 1.1 Block Diagram Page 12 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Pin Assignment 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PC6/CAS/IRQ5/CTx0/IETxD PC5/RAS/IRQ4/CRx0/IERxD PC4/WE1/DQMU/WDTOVF PC3/WE0/DQML/TIOC4D Vcc PC2/RD/WR/TIOC4C/SPDIF_OUT Vss PC1/RD/TIOC4B/SPDIF_IN PVcc PC0/CS0/TIOC4A/AUDIO_XOUT PA1/MD_BOOT PA0/MD_CLK Vcc PF5/SPBIO3_0 Vss PF4/SPBIO2_0 PF3/MISO0/SPBMI_0/SPBIO1_0 PF2/MOSI0/SPBMO_0/SPBIO0_0 PF1/SSL00/SPBSSL Vss PF0/RSPCK0/SPBCLK PVcc AUDIO_X1 AUDIO_X2 TCK TMS TDI TDO ASEBRKAK/ASEBRK TRST 1.4 Section 1 Overview 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 120-pin QFP Top view 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 AVref AVcc AVss PH5/AN5/PINT5/RxD2 PH4/AN4/PINT4/RxD1 PH3/AN3/IRQ3 PH2/AN2/IRQ2/WAIT PH1/AN1/IRQ1/RxD0 PH0/AN0/IRQ0/VBUS ASEMD PG1/DP0/PINT1 PG0/DM0/PINT0 PVcc Vss Vss XTAL EXTAL Vcc NMI PLLVcc Vss RES Vss CKIO PVcc PF7/IRQ3/RxD4 PF6/IRQ2/RxD3 PB22/A22/SSITxD0/TIOC3D PB21/A21/SSIRxD0/TIOC3C PB20/A20/SSIWS0/TIOC0D PD14/D14/SD_D3 PD15/D15/SD_D2 PVcc PB1/A1/SSISCK3 Vss PB2/A2/SSIWS3 PB3/A3/SSIDATA3 PB4/A4/CTS0 PB5/A5/RTS0 Vss PB6/A6/SCK0/SSISCK2 Vcc PB7/A7/RxD0 PB8/A8/TxD0 PB9/A9/SCK1/SSIWS2 PVcc PB10/A10/RxD1 Vss PB11/A11/TxD1 Vcc PB12/A12/SCK2/SSIDATA2 PB13/A13/RxD2 PB14/A14/TxD2 PB15/A15/RSPCK0/TIOC0B PB16/A16/SSL00/TIOC1B PB17/A17/MOSI0/TIOC2B PB18/A18/MISO0/TIOC3B PVcc PB19/A19/SSISCK0/TIOC0C Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PE0/SCL0/IRQ0 PE1/SDA0/IRQ1 PE2/SCL1/AUDIO_CLK PE3/SDA1/ADTRG PE4/SCL2/TCLKA PE5/SDA2/TCLKB PE6/SCL3/TCLKC PE7/SDA3/TCLKD PC7/CKE/IRQ6/CRx1/CRx0/CRx1 Vss PVcc PC8/CS3/IRQ7/CTx1/CTx0&CTx1 PD0/D0/SSISCK1/SIOFSCK/SPBMO_1/SPBIO0_1 PD1/D1/SSIWS1/SIOFSYNC/SPBMI_1/SPBIO1_1 PD2/D2/SSIRxD1/SIOFRxD/SPBIO2_1 PD3/D3/SSITxD1/SIOFTxD/SPBIO3_1 Vss PD4/D4/RSPCK1/SCK3/CTS1 Vcc PD5/D5/SSL10/TxD3/RTS1 PD6/D6/MOSI1/SCK4/CTS2 PVcc PD7/D7/MISO1/TxD4/RTS2 Vss PD8/D8/SD_CD/TIOC0A PD9/D9/SD_WP/TIOC1A PD10/D10/SD_D1/TIOC2A PD11/D11/SD_D0/TIOC3A PD12/D12/SD_CLK/IRQ2 PD13/D13/SD_CMD/IRQ3 Figure 1.2 (1) Pin Assignment for the SH726A Group R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 13 of 1910 TRST ASEBRKAK/ASEBRK TDO TDI TMS AUDIO_X2 AUDIO_X1 PVcc PF0/RSPCK0/SPBCLK Vss PF1/SSL00/SPBSSL PF2/MOSI0/SPBMO_0/SPBIO0_0 PF3/MISO0/SPBMI_0/SPBIO1_0 PJ11/TIOC3D/IRQ0/SCK4/CRx0/IERxD/RSPCK2 PJ12/SSISCK3/A0/TxD4/CTx0/IETxD/SSL20 PVcc PF4/SPBIO2_0 Vss PF5/SPBIO3_0 Vcc PA0/MD_CLK PA1/MD_BOOT PJ13/SSIWS3/IRQ1/RxD4/CRx1/CRx0/CRx1/MOSI2 PJ14/SSIDATA3/WDTOVF/CTx1/CTx0&CTx1/MISO2 PJ0/SD_CD/IRQ4 PC0/CS0/TIOC4A/AUDIO_XOUT PVcc PC1/RD/TIOC4B/SPDIF_IN Vss PC2/RD/WR/TIOC4C/SPDIF_OUT Vcc PC3/WE0/DQML/TIOC4D PC4/WE1/DQMU/WDTOVF PC5/RAS/IRQ4/CRx0/IERxD PC6/CAS/IRQ5/CTx0/IETxD TCK SH726A Group, SH726B Group Section 1 Overview 108 107106105 104103102 101100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 AVref PE1/SDA0/IRQ1 110 71 PH7/AN7/PINT7/RxD4 PE2/SCL1/AUDIO_CLK 111 70 AVcc PE3/SDA1/ADTRG 112 69 PH6/AN6/PINT6/RxD3 PE0/SCL0/IRQ0 109 PE4/SCL2/TCLKA 113 68 AVss PE5/SDA2/TCLKB 114 67 PH5/AN5/PINT5/RxD2 PE6/SCL3/TCLKC 115 66 PH4/AN4/PINT4/RxD1 PE7/SDA3/TCLKD 116 65 PH3/AN3/IRQ3 PC7/CKE/IRQ6/CRx1/CRx0/CRx1 117 64 PH2/AN2/IRQ2/WAIT Vss 118 63 PH1/AN1/IRQ1/RxD0 PVcc 119 62 PH0/AN0/IRQ0/VBUS PC8/CS3/IRQ7/CTx1/CTx0&CTx1 120 61 ASEMD PD0/D0/SSISCK1/SIOFSCK/SPBMO_1/SPBIO0_1 121 60 PG1/DP0/PINT1 PD1/D1/SSIWS1/SIOFSYNC/SPBMI_1/SPBIO1_1 122 59 PG0/DM0/PINT0 PD2/D2/SSIRxD1/SIOFRxD/SPBIO2_1 123 58 PVcc PJ1/SD_WP/CS2/IRQ5/AUDIO_XOUT 124 57 Vss PJ2/SD_D1/IRQ6/AUDCK 125 56 PG3/DP1/PINT3 PVcc 126 55 PG2/DM1/PINT2 PD3/D3/SSITxD1/SIOFTxD/SPBIO3_1 127 54 Vss Vss 128 53 XTAL PD4/D4/RSPCK1/SCK3/CTS1 129 52 EXTAL Vcc 130 51 Vcc 144-pin QFP Top view PD5/D5/SSL10/TxD3/RTS1 131 50 NMI PD6/D6/MOSI1/SCK4/CTS2 132 49 PLLVcc PJ3/SD_D0/IRQ7/AUDSYNC 133 48 Vss PJ4/SD_CLK/CS1/AUDATA0 134 47 RES PJ5/SD_CMD/SCK1/AUDATA1 135 46 Vss PVcc 136 45 CKIO PD7/D7/MISO1/TxD4/RTS2 137 44 PVcc 40 PK0/SCK3/RTC_X1 142 39 PB22/A22/SSITxD0/TIOC3D PD12/D12/SD_CLK/IRQ2 143 38 PB21/A21/SSIRxD0/TIOC3C PD13/D13/SD_CMD/IRQ3 144 37 PB20/A20/SSIWS0/TIOC0D Vss PB19/A19/SSISCK0/TIOC0C PVcc PB18/A18/MISO0/TIOC3B PB17/A17/MOSI0/TIOC2B PB16/A16/SSL00/TIOC1B PB14/A14/TxD2 PB15/A15/RSPCK0/TIOC0B PB13/A13/RxD2 Vcc PB12/A12/SCK2/SSIDATA2 PB11/A11/TxD1 Vss PB10/A10/RxD1 PVcc PJ9/TIOC3B/A24/RxD2/SSIWS2/DREQ0 PJ10/TIOC3C/A25/TxD2/SSIDATA2/DACK0 PJ8/TIOC3A/A23/SCK2/SSISCK2/TEND0 PB8/A8/TxD0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PB9/A9/SCK1/SSIWS2 8 PB7/A7/RxD0 7 Vcc 6 PB6/A6/SCK0/SSISCK2 5 Vss 4 PB5/A5/RTS0 3 PVcc 2 PJ7/SD_D2/BS/TxD1/AUDATA3 1 PJ6/SD_D3/CS4/RxD1/AUDATA2 141 PD11/D11/SD_D0/TIOC3A PB4/A4/CTS0 PK1/TxD3/RTC_X2 PD10/D10/SD_D1/TIOC2A PB3/A3/SSIDATA3 41 PB2/A2/SSIWS3 140 Vss PF6/IRQ2/RxD3 PD9/D9/SD_WP/TIOC1A PB1/A1/SSISCK3 PF7/IRQ3/RxD4 42 PVcc 43 139 PD15/D15/SD_D2 138 PD14/D14/SD_D3 Vss PD8/D8/SD_CD/TIOC0A Figure 1.2 (2) Pin Assignment for the SH726B Group Page 14 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 1.5 Table 1.3 Section 1 Overview Pin Functions Pin Functions Classification Symbol I/O Name Function Power supply Vcc I Power supply Power supply pins. All the Vcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Vss I Ground Ground pins. All the Vss pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. PVcc I Power supply for I/O circuits Power supply for I/O pins. All the PVcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. PLLVcc I Power supply for PLL Power supply for the on-chip PLL oscillator. EXTAL I External clock Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. XTAL O Crystal Connected to a crystal resonator. CKIO O System clock I/O Supplies the system clock to external devices. AUDIO_CLK I External clock for audio Input pin of external clock for audio. A clock input to the divider is selected from an oscillation clock input on this pin or pins AUDIO_X1 and AUDIO_X2. AUDIO_X1 I AUDIO_X2 O Crystal resonator/ external clock for audio Pins connected to a crystal resonator for audio. An external clock can be input on pin AUDIO_X1. A clock input to the divider is selected from an oscillation clock input on these pins or the AUDIO_CLK pin. AUDIO_XOUT O AUDIO_X1 clock I/O Output for the on-chip crystal oscillator on AUDIO_X1 or the external clock signal. Clock Clock R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 15 of 1910 SH726A Group, SH726B Group Section 1 Overview Classification Symbol I/O Name Function I Mode set Sets the operating mode. Do not change the signal levels on these pins while the RES pin is asserted or until the mode is fixed, after the negation. MD_CLK I Clock mode set This pin sets the clock operating mode. Do not change the signal level on this pin while the RES pin is asserted or until the mode is fixed, after the negation. ASEMD I ASE mode Operating mode MD_BOOT control If a low level is input at the ASEMD pin while the RES pin is asserted, ASE mode is entered; if a high level is input, product chip mode is entered. In ASE mode, the E10A-USB emulator function is enabled. When this function is not in use, fix it high. RES I Power-on reset This LSI enters the power-on reset state when this signal goes low. WDTOVF O Watchdog timer Outputs an overflow signal from overflow the watchdog timer. NMI I Non-maskable interrupt IRQ7 to IRQ0 I Interrupt Maskable interrupt request pins. requests 7 to 0 Level-input or edge-input detection can be selected. When the edgeinput detection is selected, the rising edge, falling edge, or both edges can also be selected. PINT7 to PINT0 I Interrupt Maskable interrupt request pins. requests 7 to 0 Only level-input detection can be selected. Only PINT5, PINT4, PINT1 PINT0 can be used in the SH726A Group. Address bus A25 to A0 O Address bus Data bus D15 to D0 I/O Data bus System control Interrupts Page 16 of 1910 Non-maskable interrupt request pin. Fix it high when not in use. Outputs addresses. Only A22 to A1 can be used in the SH726A Group. Bidirectional data bus. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Classification Symbol I/O Name Bus control CS4 to CS0 O Chip select 4 to Chip-select signals for external 0 memory or devices. Only CS3, CS0 can be used in the SH726A Group. RD O Read Indicates that data is read from an external device. RD/WR O Read/write Read/write signal. BS O Bus start Bus-cycle start signal. WAIT I Wait Inserts a wait cycle into the bus cycles during access to the external space. WE0 O Byte select Indicates a write access to bits 7 to 0 of data of external memory or device. WE1 O Byte select Indicates a write access to bits 15 to 8 of data of external memory or device. DQML O Byte select Selects bits D7 to D0 when SDRAM is connected. DQMU O Byte select Selects bits D15 to D8 when SDRAM is connected. RAS O RAS Connected to the RAS pin when SDRAM is connected. CAS O CAS Connected to the CAS pin when SDRAM is connected. CKE O CK enable Connected to the CKE pin when SDRAM is connected. I DMA-transfer request Input pin to receive external requests for DMA transfer. DACK0 O DMA-transfer Output pin for signals indicating request accept acceptance of external requests from external devices. TEND0 O DMA-transfer end output Direct memory DREQ0 access controller R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Function Output pin for DMA transfer end. Page 17 of 1910 SH726A Group, SH726B Group Section 1 Overview Classification Symbol Multi-function TCLKA, timer pulse unit 2 TCLKB, TCLKC, TCLKD Realtime clock Serial communication interface with FIFO Page 18 of 1910 I/O Name Function I External clock input pins for the timer. Timer clock input TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O Input capture/ The TGRA_0 to TGRD_0 input output compare capture input/output compare (channel 0) output/PWM output pins. TIOC1A, TIOC1B I/O Input capture/ The TGRA_1 and TGRB_1 input output compare capture input/output compare (channel 1) output/PWM output pins. TIOC2A, TIOC2B I/O Input capture/ The TGRA_2 and TGRB_2 input output compare capture input/output compare output/PWM output pins. (channel 2) TIOC3A, TIOC3B, TIOC3C, TIOC3D I/O Input capture/ The TGRA_3 to TGRD_3 input output compare capture input/output compare (channel 3) output/PWM output pins. TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O Input capture/ The TGRA_4 to TGRD_4 input output compare capture input/output compare (channel 4) output/PWM output pins. RTC_X1 I RTC_X2 O Crystal resonator for realtime clock/ external clock Connected to 4 MHz crystal resonator. The RTC_X1 pin can also be used to input an external clock. TxD4 to TxD0 O Transmit data Data output pins. RxD4 to RxD0 I Receive data Data input pins. SCK4 to SCK0 I/O Serial clock Clock input/output pins. RTS2 to RTS0 O Transmit request Modem control pin. CTS2 to CTS0 I Enable to transmit Modem control pin. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Classification Symbol I/O Name Function Renesas serial peripheral interface MOSI2 to MOSI0 I/O Data Data I/O pin. Only MOSI1, MOSI0 can be used in the SH726A Group. MISO2 to MISO0 I/O Data Data I/O pin. Only MOSI1, MISO0 can be used in the SH726A Group. RSPCK2 to RSPCK0 I/O Clock Clock I/O pin. Only RSPCK1, RSPCK0 can be used in the SH726A Group. SSL20 to SSL00 I/O Slave select Slave select I/O pin. Only SSL10, SSL00 can be used in the SH726A Group. SPI multi I/O bus SPBMO_0/SPBIO0_0, I/O Data controller SPBMI_0/SPBIO1_0, SPBIO2_0, SPBIO3_0, SPBMO_1/SPBIO0_1, SPBMI_1/SPBIO1_1, SPBIO2_1, SPBIO3_1 2 I C bus interface 3 Serial sound interface SPBCLK O Clock Clock output pin. SPBSSL O Slave select Slave select output pin. SCL3 to SCL0 I/O Serial clock pin Serial clock I/O pin. SDA3 to SDA0 I/O Serial data pin Serial data I/O pin. SSITxD1, SSITxD0 O Data output Serial data output pin. SSIRxD1, SSIRxD0 I Data input Serial data input pin. SSIDATA3, SSIDATA2 I/O Data I/O Serial I/O with FIFO Data I/O pin. Serial data I/O pin. SSISCK3 to SSISCK0 I/O SSI clock I/O I/O pins for serial clocks. SSIWS3 to SSIWS0 I/O SSI clock LR I/O I/O pins for word selection. SIOFTxD O Data output Data output pin. SIOFRxD I Data input Data input pin. SIOFSCK I/O I/O clock Clock I/O pin. SIOFSYNC I/O I/O chip select I/O pin for chip selection. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 19 of 1910 SH726A Group, SH726B Group Section 1 Overview Classification Symbol I/O Name Function Controller area network CTx0, CTx1 O CAN bus transmit data Output pin for transmit data on the CAN bus. CRx0, CRx1 I CAN bus receive data Output pin for receive data on the CAN bus. O IEBus controller Output pin for transmit data on transmit data IEBus controller. I IEBus controller Input pin for receive data on IEBus receive data controller. O Output data Transmit data output pin. I Input data Receive data input pin. TM IEBus controller IETxD IERxD Renesas SPDIF SPDIF_OUT interface SPDIF_IN USB 2.0 host/function module DP1, DP0 I/O USB 2.0 host/function module D+ data DM1, DM0 D– data pin for USB 2.0 I/O USB 2.0 host/function module bus. host/function module D– data Only DM0 can be used in the SH726A Group. VBUS I VBUS input D+ data pin for USB 2.0 host/function module bus. Only DP0 can be used in the SH726A Group. This pin is for monitoring the connection of USB cables to port 0. When function controller operation is selected, connect a voltage down to 3.3 V to the VBUS pin of the USB. Connection to and disconnection from the VBUS pin are detectable. When host controller operation is selected, connection to this pin is not required. SD host interface Page 20 of 1910 SD_CLK O SD clock Output pin for SD clock. SD_CMD I/O SD command SD command output and response input signal. SD_D3 to SD_D0 I/O SD data SD data bus signal. SD_CD I SD card detection SD card detection. SD_WP I SD write protection SD write protection signal. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Classification Symbol I/O Name Function A/D converter AN7 to AN0 I Analog input pins Analog input pins. Only AN5 to AN0 can be used in the SH726A Group. ADTRG I A/D conversion External trigger input pin for trigger input starting A/D conversion. AVcc I Analog power supply AVss I Analog ground Ground pin for A/D converter. AVref I Analog reference voltage PA1, PA0, PB22 to PB1, PC8 to PC0, PD15 to PD0, PF7 to PF0, PJ14 to PJ0 PK1, PK0 I/O General port PE7 to PE0 I/O General port 8 input port pins with open-drain output. PG3 to PG0, PH7 to PH0 I General port 12 general input port pins. Only PG1, PG0, and PH5 to PH0 can be used in the SH726A Group. TCK I Test clock Test-clock input pin. TMS I Test mode select Test-mode select signal input pin. TDI I Test data input Serial input pin for instructions and data. TDO O Test data output Serial output pin for instructions and data. TRST I Test reset Initialization-signal input pin. AUDATA3 to AUDATA0 O Data Branch source or destination address output pins. AUDCK O Clock Sync-clock output pin. AUDSYNC O Sync signal Data start-position acknowledgesignal output pin. General I/O ports User debugging interface Emulator interface R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Power supply pin for A/D converter. Reference voltage pin for A/D converter. 57 general I/O port pins in the SH726A Group. 74 general I/O port pins in the SH726B Group. Only PA1, PA0, PB22 to PB1, PC8 to PC0, PD15 to PD0, and PF7 to PF0 can be used in the SH726A Group. Page 21 of 1910 SH726A Group, SH726B Group Section 1 Overview Classification Symbol I/O Name Function Emulator interface ASEBRKAK O Break mode acknowledge Indicates that the E10A-USB emulator has entered its break mode. ASEBRK I Break request E10A-USB emulator break input pin. Page 22 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 1.6 Section 1 Overview List of Pins Table 1.4 List of Pins Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 1 1 PD14 I(s)/O D14 I/O SD_D3 I(s)/O   2 2 PD15 I(s)/O D15 I/O SD_D2 I(s)/O   3 3 PVcc 4 4 PB1 I(s)/O A1 O   SSISCK3 I(s)/O 5 5 Vss 6 6 PB2 I(s)/O A2 O   SSIWS3 I(s)/O 7 7 PB3 I(s)/O A3 O   SSIDATA3 I(s)/O 8 8 PB4 I(s)/O A4 O CTS0 I(s)/O   NC 9 PJ6 I(s)/O SD_D3 I(s)/O CS4 O RxD1 I(s) NC 10 PJ7 I(s)/O SD_D2 I(s)/O BS O TxD1 O NC 11 PVcc 9 12 PB5 I(s)/O A5 O RTS0 I(s)/O   10 13 Vss 11 14 PB6 I(s)/O A6 O SCK0 I(s)/O SSISCK2 I(s)/O 12 15 Vcc SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 1 1         (8) 2 2         (8) 3 3 4 4         (7) 5 5 6 6         (7) 7 7         (7) 8 8         (7) NC 9       AUDATA2 O (7) NC 10       AUDATA3 O (7) NC 11 9 12         (7) 10 13 11 14         (7) 12 15 Function 5 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 Page 23 of 1910 SH726A Group, SH726B Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 13 16 PB7 I(s)/O A7 O RxD0 I(s)   14 17 PB8 I(s)/O A8 O TxD0 O   15 18 PB9 I(s)/O A9 O SCK1 I(s)/O SSIWS2 I(s)/O NC 19 PJ8 I(s)/O TIOC3A I(s)/O A23 O SCK2 I(s)/O NC 20 PJ9 I(s)/O TIOC3B I(s)/O A24 O RxD2 I(s) NC 21 PJ10 I(s)/O TIOC3C I(s)/O A25 O TxD2 O 16 22 PVcc 17 23 PB10 I(s)/O A10 O RxD1 I(s)   18 24 Vss I(s)/O A11 O TxD1 O   I(s)/O A12 O SCK2 I(s)/O SSIDATA2 I(s)/O  19 25 PB11 20 26 Vcc 21 27 PB12 22 28 PB13 I(s)(5t)/O A13 O RxD2 I(s)(5t)  23 29 PB14 I(s)/O A14 O TxD2 O   24 30 PB15 I(s)/O A15 O RSPCK0 I(s)/O TIOC0B I(s)/O SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 13 16         (7) 14 17         (7) 15 18         (7) NC 19 SSISCK2 I(s)/O TEND0 O     (7) NC 20 SSIWS2 I(s)/O DREQ0 I(s)     (7) NC 21 SSIDATA2 I(s)/O DACK0 O     (7) 16 22 17 23         (7) 18 24 19 25         (7) 20 26 21 27         (7) 22 28         (7) 23 29         (7) 24 30         (7) Function 5 Page 24 of 1910 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 25 31 PB16 I(s)/O A16 O SSL00 I(s)/O TIOC1B I(s)/O 26 32 PB17 I(s)/O A17 O MOSI0 I(s)/O TIOC2B I(s)/O 27 33 PB18 I(s)/O A18 O MISO0 I(s)/O TIOC3B I(s)/O 28 34 PVcc I(s)/O A19 O SSISCK0 I(s)/O TIOC0C I(s)/O 29 35 PB19 30 36 Vss 31 37 PB20 I(s)/O A20 O SSIWS0 I(s)/O TIOC0D I(s)/O 32 38 PB21 I(s)/O A21 O SSIRxD0 I(s) TIOC3C I(s)/O 33 39 PB22 I(s)/O A22 O SSITxD0 O TIOC3D I(s)/O NC 40 PK0 I(s)/O SCK3 I(s)/O RTC_X1 I   NC 41 PK1 I(s)/O TxD3 O RTC_X2 O   34 42 PF6 I(s)/O   IRQ2 I(s) RxD3 I(s)/O I(s)/O   IRQ3 I(s) RxD4 I(s)/O O       35 43 PF7 36 44 PVcc 37 45 CKIO SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 25 31         (7) 26 32         (7) 27 33         (7) 28 34 29 35         (7) 30 36 31 37         (7) 32 38         (7) 33 39         (7) NC 40         (7), (11) NC 41         (7), (11) 34 42         (7) 35 43         (7) 36 44 37 45         (6) Function 5 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 Page 25 of 1910 SH726A Group, SH726B Group Section 1 Overview Function 1 SH726A Pin No. SH726B Pin No. Symbol 38 46 Vss 39 47 RES 40 48 Vss 41 49 PLLVcc 42 50 NMI 43 51 Vcc 44 52 EXTAL Function 2 Function 3 Function 4 I/O Symbol I/O Symbol I/O Symbol I/O I(s)       I(s)       I       O       45 53 XTAL 46 54 Vss NC 55 PG2 I(s) DM1 I/O PINT2 I(s)   NC 56 PG3 I(s) DP1 I/O PINT3 I(s)   47 57 Vss 48 58 PVcc 49 59 PG0 I(s) DM0 I/O PINT0 I(s)   50 60 PG1 I(s) DP0 I/O PINT1 I(s)   SH726A Pin No. SH726B Pin No. 38 46 39 47 40 48 41 49 42 50 43 51 44 Function 5 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 Symbol I/O Symbol I/O Symbol I/O Symbol I/O         (1)         (3) 52         (10) 45 53         (10) 46 54 NC 55         (3) other than DM1 NC 56         (3) other than DP1 47 57 48 58 49 59         (3) other than DM0 50 60         (3) other than DP0 Page 26 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 51 61 ASEMD        52 62 PH0 I(s) AN0 I(a) IRQ0 I(s) VBUS I(s) 53 63 PH1 I(s) AN1 I(a) IRQ1 I(s) RxD0 I(s) 54 64 PH2 I(s) AN2 I(a) IRQ2 I(s) WAIT I(s) 55 65 PH3 I(s) AN3 I(a) IRQ3 I(s)   56 66 PH4 I(s) AN4 I(a) PINT4 I(s) RxD1 I(s) 57 67 PH5 I(s) AN5 I(a) PINT5 I(s) RxD2 I(s) I(s) AN6 I(a) PINT6 I(s) RxD3 I(s) I(s) AN7 I(a) PINT7 I(s) RxD4 I(s) I(s)       58 68 AVss NC 69 PH6 59 70 AVcc NC 71 PH7 60 72 AVref 61 73 TRST 62 74 ASEBRKAK/ I(s)/O ASEBRK       63 75 TDO       SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 51 61         (1) 52 62         (4) 53 63         (4) 54 64         (4) 55 65         (4) 56 66         (4) 57 67         (4) 58 68 NC 69         (4) 59 70 NC 71         (4) 60 72 61 73         (3) 62 74         (7) 63 75         (5) O Function 5 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 Page 27 of 1910 SH726A Group, SH726B Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 64 76 TDI I       65 77 TMS I       66 78 TCK I       67 79 AUDIO_X2 O       68 80 AUDIO_X1 I       69 81 PVcc 70 82 PF0 I(s)/O RSPCK0 I(s)/O SPBCLK O   71 83 Vss 72 84 PF1 I(s)/O SSL00 I(s)/O SPBSSL O   73 85 PF2 I(s)/O MOSI0 I(s)/O SPBMO_0/ SPBIO0_0 I(s)/O   74 86 PF3 I(s)/O MISO0 I(s)/O SPBMI_0/ SPBIO1_0 I(s)/O   NC 87 PJ11 I(s)/O TIOC3D I(s)/O IRQ0 I(s) SCK4 I(s)/O NC 88 PJ12 I(s)/O SSISCK3 I(s)/O A0 O TxD4 O NC 89 PVcc 75 90 PF4 I(s)/O   SPBIO2_0 I(s)/O   SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 64 76         (2) 65 77         (2) 66 78         (2) 67 79         (10) 68 80         (10) 69 81 70 82         (7) 71 83 72 84         (7) 73 85         (7) 74 86         (7) NC 87 CRx0 I(s) IERxD I(s) RSPCK2 I(s)/O   (7) NC 88 CTx0 O IETxD O SSL20 I(s)/O   (7) NC 89 75 90         (7) Function 5 Page 28 of 1910 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Function 1 SH726A Pin No. SH726B Pin No. Symbol 76 91 Vss 77 92 PF5 78 93 Vcc 79 94 PA0 Function 2 Function 3 Function 4 I/O Symbol I/O Symbol I/O Symbol I/O I(s)/O   SPBIO3_0 I(s)/O   I(s)/O MD_CLK I(s)     80 95 PA1 I(s)/O MD_BOOT I(s)     NC 96 PJ13 I(s)(5t)/O SSIWS3 I(s)(5t)/O IRQ1 I(s)(5t) RxD4 I(s)(5t) NC 97 PJ14 I(s)/O SSIDATA3 I(s)/O WDTOVF O    IRQ4 I(s) NC 98 PJ0 I(s)/O SD_CD I(s)  81 99 PC0 I(s)/O CS0 O TIOC4A I(s)/O AUDIO_XOUT O 82 100 PVcc 83 101 PC1 I(s)/O RD O TIOC4B I(s)/O SPDIF_IN I(s) 84 102 Vss I(s)/O RD/WR O TIOC4C I(s)/O SPDIF_OUT O I(s)/O WE0/DQML O TIOC4D I(s)/O   85 103 PC2 86 104 Vcc 87 105 PC3 SH726A Pin No. SH726B Pin No. 76 91 77 92 78 93 79 80 Function 5 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 Symbol I/O Symbol I/O Symbol I/O Symbol I/O         (7) 94         (7) 95         (7) NC 96 CRx1 I(s)(5t) CRx0/CRx1 I(s)(5t) MOSI2 I(s)(5t)/O   (7) NC 97 CTx1 O CTx0&CTx1 O MISO2 I(s)/O   (7) NC 98         (7) 81 99         (7) 82 100 83 101         (7) 84 102 85 103         (7) 86 104 87 105         (7) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 29 of 1910 SH726A Group, SH726B Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 88 106 PC4 I(s)/O WE1/DQMU O WDTOVF O   89 107 PC5 I(s)/O RAS O IRQ4 I(s) CRx0 I(s) 90 108 PC6 I(s)/O CAS O IRQ5 I(s) CTx0 O 91 109 PE0 I(s)/O(o) SCL0 I(s)/O(o) IRQ0 I(s)   92 110 PE1 I(s)/O(o) SDA0 I(s)/O(o) IRQ1 I(s)   93 111 PE2 I(s)/O(o) SCL1 I(s)/O(o) AUDIO_CLK I(s)   94 112 PE3 I(s)/O(o) SDA1 I(s)/O(o) ADTRG I(s)    95 113 PE4 I(s)/O(o) SCL2 I(s)/O(o) TCLKA I(s)  96 114 PE5 I(s)/O(o) SDA2 I(s)/O(o) TCLKB I(s)   97 115 PE6 I(s)/O(o) SCL3 I(s)/O(o) TCLKC I(s)   98 116 PE7 I(s)/O(o) SDA3 I(s)/O(o) TCLKD I(s)   99 117 PC7 I(s)/O CKE O IRQ6 I(s) CRx1 I(s) 100 118 Vss 101 119 PVcc 102 120 PC8 I(s)/O CS3 O IRQ7 I(s) CTx1 O SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 88 106         (7) Function 5 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 89 107 IERxD I(s)       (7) 90 108 IETxD O       (7) 91 109         (9) 92 110         (9) 93 111         (9) 94 112         (9) 95 113         (9) 96 114         (9) 97 115         (9) 98 116         (9) 99 117 CRx0/CRx1 I(s)       (7) 100 118 101 119 102 120 CTx0&CTx1 O       (7) Page 30 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Function 1 Function 2 Function 3 Function 4 SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 103 121 PD0 I(s)/O D0 I/O SSISCK1 I(s)/O SIOFSCK I(s)/O 104 122 PD1 I(s)/O D1 I/O SSIWS1 I(s)/O SIOFSYNC I(s)/O 105 123 PD2 I(s)/O D2 I/O SSIRxD1 I(s) SIOFRxD I(s) NC 124 PJ1 I(s)/O SD_WP I(s) CS2 O IRQ5 I(s) NC 125 PJ2 I(s)/O SD_D1 I(s)/O   IRQ6 I(s) NC 126 PVcc 106 127 PD3 I(s)/O D3 I/O SSITxD1 O SIOFTxD O 107 128 Vss 108 129 PD4 I(s)/O D4 I/O RSPCK1 I(s)/O SCK3 I(s)/O 109 130 Vcc 110 131 PD5 I(s)/O D5 I/O SSL10 I(s)/O TxD3 O 111 132 PD6 I(s)/O D6 I/O MOSI1 I(s)/O SCK4 I(s)/O  NC 133 PJ3 I(s)/O SD_D0 I(s)/O  IRQ7 I(s) NC 134 PJ4 I(s)/O SD_CLK O CS1 O   NC 135 PJ5 I(s)/O SD_CMD I(s)/O   SCK1 I(s)/O SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 103 121 SPBMO_1/ SPBIO0_1 I(s)/O       (8) 104 122 SPBMI_1/ SPBIO1_1 I(s)/O       (8) 105 123 SPBIO2_1 I(s)/O       (8) NC 124 AUDIO_XOUT O       (7) NC 125       AUDCK O (7) NC 126 106 127 SPBIO3_1 I(s)/O       (8) 107 128 108 129 CTS1 I(s)/O       (8) 109 130 110 131 RTS1 I(s)/O       (8) 111 132 CTS2 I(s)/O       (8) NC 133       AUDSYNC O (7) NC 134       AUDATA0 O (7) NC 135       AUDATA1 O (7) Function 5 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 Page 31 of 1910 SH726A Group, SH726B Group Section 1 Overview Function 1 SH726A Pin No. SH726B Pin No. Symbol 112 136 PVcc 113 137 PD7 114 138 Vss 115 139 PD8 Function 2 Function 3 Function 4 I/O Symbol I/O Symbol I/O Symbol I/O I(s)/O D7 I/O MISO1 I(s)/O TxD4 O I(s)/O D8 I/O SD_CD I(s) TIOC0A I(s)/O 116 140 PD9 I(s)/O D9 I/O SD_WP I(s) TIOC1A I(s)/O 117 141 PD10 I(s)/O D10 I/O SD_D1 I(s)/O TIOC2A I(s)/O 118 142 PD11 I(s)/O D11 I/O SD_D0 I(s)/O TIOC3A I(s)/O 119 143 PD12 I(s)/O D12 I/O SD_CLK O IRQ2 I(s) 120 144 PD13 I(s)/O D13 I/O SD_CMD I(s)/O IRQ3 I(s) SH726A Pin No. SH726B Pin No. Symbol I/O Symbol I/O Symbol I/O Symbol I/O 112 136 113 137 RTS2 I(s)/O       (8) 114 138 115 139         (8) 116 140         (8) 117 141         (8) 118 142         (8) 119 143         (8) 144         (8) Function 5 120 Function 6 Function 7 ASE Function Circuit diagram Figure 1.3 [Legend] (s): Schmitt (a): Analog (o): Open drain (5t): 5-V tolerant PAD Schmitt input data Figure 1.3 (1) Page 32 of 1910 Simplified Circuit Diagram (Schmitt Input Buffer) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview PAD TTL input data TTL input enable Figure 1.3 (2) Simplified Circuit Diagram (TTL AND Input Buffer) PAD Schmitt input data Schmitt input enable Figure 1.3 (3) Simplified Circuit Diagram (Schmitt AND Input Buffer) A/D analog input enable PAD A/D analog input data Schmitt input data Schmitt input enable Figure 1.3 (4) Simplified Circuit Diagram (Schmitt OR Input and A/D Input Buffer) Latch enable Output enable PAD Output data Figure 1.3 (5) Simplified Circuit Diagram (Output Buffer with Enable, with Latch) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 33 of 1910 SH726A Group, SH726B Group Section 1 Overview Latch enable Output enable PAD Output data TTL input data TTL input enable Figure 1.3 (6) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, with Latch) Latch enable Output enable PAD Output data Schmitt input data Schmitt input enable Figure 1.3 (7) Simplified Circuit Diagram (Bidirectional Buffer, Schmitt AND Input, with Latch) Page 34 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 1 Overview Latch enable Output enable PAD Output data TTL input data TTL input enable Schmitt input data Schmitt input enable Figure 1.3 (8) Simplified Circuit Diagram (Bidirectional Buffer, TTL AND Input, Schmitt AND Input, with Latch) PAD Output data Schmitt input data Schmitt input enable Figure 1.3 (9) Simplified Circuit Diagram (Open Drain Output and Schmitt OR Input Buffer) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 35 of 1910 SH726A Group, SH726B Group Section 1 Overview Input clock XOUT (XTAL, AUDIO_X2) XIN (EXTAL, AUDIO_X1) Input enable Figure 1.3 (10) Simplified Circuit Diagram (Oscillation Buffer 1) XOUT (RTC_X2) Input clock XIN (RTC_X1) Input enable Figure 1.3 (11) Simplified Circuit Diagram (Oscillation Buffer 2) Page 36 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and restoring the status register (SR) and program counter (PC) in exception handling is accomplished by referencing the stack using R15. 31 0 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 37 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area. 31 14 13 9 8 7 6 5 4 3 2 1 0 BO CS M Q I[3:0] S T 31 Status register (SR) 0 GBR Global base register (GBR) 31 0 VBR Vector base register (VBR) 0 31 TBR Jump table base register (TBR) Figure 2.2 Control Registers (1) Status Register (SR) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - BO CS - - - M Q - - S T 0 R 0 R/W 0 R/W 0 R 0 R 0 R R/W R/W 0 R 0 R R/W R/W Initial value: R/W: Page 38 of 1910 I[3:0] 1 R/W 1 R/W 1 R/W 1 R/W 16 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Bit Bit Name Initial Value 31 to 15  All 0 Section 2 CPU R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 14 BO 0 R/W BO Bit Indicates that a register bank has overflowed. 13 CS 0 R/W CS Bit Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-limit value or fallen below the saturation lower-limit value. 12 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 M  R/W M Bit 8 Q  R/W Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. 7 to 4 I[3:0] 1111 R/W Interrupt Mask Level 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 S  R/W S Bit Specifies a saturation operation for a MAC instruction. 0 T  R/W T Bit True/false condition or carry/borrow bit (2) Global Base Register (GBR) GBR is referenced as the base address in a GBR-referencing MOV instruction. (3) Vector Base Register (VBR) VBR is referenced as the branch destination base address in the event of an exception or an interrupt. (4) Jump Table Base Register (TBR) TBR is referenced as the start address of a function table located in memory in a JSR/N@@(disp8,TBR) table-referencing subroutine call instruction. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 39 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.1.3 System Registers The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or multiply and accumulate operations. PR stores the return address from a subroutine procedure. PC points four bytes ahead of the current instruction and controls the flow of the processing. 31 0 Multiply and accumulate register high (MACH) and multiply and accumulate register low (MACL): Store the results of multiply or multiply and accumulate operations. 0 Procedure register (PR): Stores the return address from a subroutine procedure. 0 Program counter (PC): Indicates the four bytes ahead of the current instruction. MACH MACL 31 PR 31 PC Figure 2.3 System Registers (1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate Register Low (MACL) MACH and MACL are used as the addition value in a MAC instruction, and store the result of a MAC or MUL instruction. (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC points four bytes ahead of the instruction being executed. Page 40 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.1.4 Section 2 CPU Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 7.8, Register Banks. 2.1.5 Initial Values of Registers Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers Classification Register Initial Value General registers R0 to R14 Undefined R15 (SP) Value of the stack pointer in the vector address table SR Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined GBR, TBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC Value of the program counter in the vector address table Control registers System registers R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 41 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 0 Longword Figure 2.4 Data Format in Registers 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in sign-extended or zero-extended form. A word operand should be accessed at a word boundary (an even address of multiple of two bytes: address 2n), and a longword operand at a longword boundary (an even address of multiple of four bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any address. Only big-endian byte order can be selected for the data format. Data formats in memory are shown in figure 2.5. Address m + 1 Address m 31 23 Byte Address 2n Address 4n Address m + 3 Address m + 2 15 Byte 7 Byte Word 0 Byte Word Longword Big endian Figure 2.5 Data Formats in Memory Page 42 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.2.3 Section 2 CPU Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction. The MOVI20 instruction stores immediate data in the destination register in sign-extended form. The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it in the destination register in sign-extended form. Word or longword immediate data is not located in the instruction code, but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. See examples given in section 2.3.1 (10), Immediate Data. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 43 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease of use. (3) One Instruction per State Each basic instruction can be executed in one cycle using the pipeline system. (4) Data Length Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data in memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It is also handled as longword data. Table 2.2 Sign Extension of Word Data SH2-A CPU MOV.W ADD .DATA.W Description @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD instruction. H'1234 Example of Other CPU ADD.W #H'1234,R0 Note: @(disp, PC) accesses the immediate data. (5) Load-Store Architecture Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Page 44 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (6) Section 2 CPU Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. This reduces disturbance of the pipeline control when a branch is taken. In a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution such as register updating excluding the actual branch operation, is performed in the order of delayed branch instruction  delay slot instruction. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.3 Delayed Branch Instructions SH-2A CPU Description Example of Other CPU BRA TRGET R1,R0 R1,R0 Executes the ADD before branching to TRGET. ADD.W ADD BRA TRGET (7) Unconditional Branch Instructions with No Delay Slot The SH-2A additionally features unconditional branch instructions in which a delay slot instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code size. (8) Multiply/Multiply-and-Accumulate Operations 16-bit  16-bit  32-bit multiply operations are executed in one to two cycles. 16-bit  16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit  32-bit 64-bit multiply and 32-bit  32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four cycles. (9) T Bit The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 45 of 1910 SH726A Group, SH726B Group Section 2 CPU Table 2.4 T Bit SH-2A CPU Description Example of Other CPU CMP/GE R1,R0 T bit is set when R0  R1. CMP.W R1,R0 BT TRGET0 BGE TRGET0 BF TRGET1 The program branches to TRGET0 when R0  R1 and to TRGET1 when R0 < R1. BLT TRGET1 ADD #1,R0 T bit is not changed by ADD. SUB.W #1,R0 CMP/EQ #0,R0 T bit is set when R0 = 0. BEQ TRGET BT TRGET The program branches if R0 = 0. (10) Immediate Data Byte immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for 21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a register. Table 2.5 Immediate Data Accessing Classification SH-2A CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOVI20 #H'1234,R0 MOV.W #H'1234,R0 20-bit immediate MOVI20 #H'12345,R0 MOV.L #H'12345,R0 28-bit immediate MOVI20S #H'12345,R0 MOV.L #H'1234567,R0 OR #H'67,R0 MOV.L @(disp,PC),R0 MOV.L #H'12345678,R0 32-bit immediate Example of Other CPU ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Page 46 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU (11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in register indirect addressing mode. With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also possible to transfer immediate data located in the instruction code to a register and to reference the data in register indirect addressing mode. However, when referencing data using an absolute address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register. Table 2.6 Absolute Address Accessing Classification SH-2A CPU Up to 20 bits MOVI20 #H'12345,R1 MOV.B @R1,R0 MOVI20S #H'12345,R1 OR #H'67,R1 MOV.B @R1,R0 MOV.L @(disp,PC),R1 MOV.B @R1,R0 21 to 28 bits 29 bits or more Example of Other CPU MOV.B @H'12345,R0 MOV.B @H'1234567,R0 MOV.B @H'12345678,R0 .................. .DATA.L H'12345678 (12) 16-Bit/32-Bit Displacement When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indexed indirect register addressing mode. Table 2.7 Displacement Accessing Classification SH-2A CPU Example of Other CPU 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 MOV.W @(H'1234,R1),R2 .................. .DATA.W R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 H'1234 Page 47 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Register direct Rn Register indirect @Rn The effective address is register Rn. (The operand is the contents of register Rn.)  The effective address is the contents of register Rn. Rn Rn Register indirect @Rn+ with postincrement Equation Rn The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn Rn + 1/2/4 + Rn (After instruction execution) Byte: Rn + 1  Rn Word: Rn + 2  Rn 1/2/4 Longword: Rn + 4  Rn Register indirect @-Rn with predecrement The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn – 1/2/4 1/2/4 Page 48 of 1910 – Rn – 1/2/4 Byte: Rn – 1  Rn Word: Rn – 2  Rn Longword: Rn – 4  Rn (Instruction is executed with Rn after this calculation) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Addressing Mode Instruction Format Register indirect @(disp:4, Rn) with displacement Section 2 CPU Effective Address Calculation Equation The effective address is the sum of Rn and a 4-bit displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Byte: Rn + disp Rn disp (zero-extended) Word: Rn + disp  2 Longword: Rn + disp  4 Rn + disp × 1/2/4 + × 1/2/4 Register indirect @(disp:12, The effective address is the sum of Rn and a 12with Rn) bit displacement displacement (disp). The value of disp is zeroextended. Rn + Rn + disp Byte: Rn + disp Word: Rn + disp Longword: Rn + disp disp (zero-extended) Indexed register @(R0,Rn) indirect The effective address is the sum of Rn and R0. Rn + R0 Rn + Rn + R0 R0 GBR indirect with displacement @(disp:8, GBR) The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) + Byte: GBR + disp Word: GBR + disp  2 Longword: GBR + disp  4 GBR + disp × 1/2/4 × 1/2/4 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 49 of 1910 SH726A Group, SH726B Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Equation Indexed GBR indirect @(R0, GBR) The effective address is the sum of GBR value and R0. GBR + R0 GBR + GBR + R0 R0 TBR duplicate indirect with displacement @@ (disp:8, TBR) The effective address is the sum of TBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and is multiplied by 4. Contents of address (TBR + disp  4) TBR disp (zero-extended) TBR + + disp × 4 × (TBR 4 PC indirect with @(disp:8, displacement PC) + disp × 4) The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. Word: PC + disp  2 Longword: PC & H'FFFFFFFC + disp  4 PC & H'FFFFFFFC (for longword) + disp (zero-extended) PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 × 2/4 Page 50 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation PC relative disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). Equation PC + disp  2 PC disp (sign-extended) + PC + disp × 2 × 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC + disp 2 PC disp (sign-extended) + PC + disp × 2 × 2 Rn The effective address is the sum of PC value and Rn. PC + Rn PC + PC + Rn Rn R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 51 of 1910 SH726A Group, SH726B Group Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Immediate #imm:20 Equation The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended.  31 19 0 Signimm (20 bits) extended The 20-bit immediate data (imm) for the MOVI20S  instruction is shifted by eight bits to the left, the upper bits are sign-extended, and the lower bits are padded with zero. 31 27 8 0 imm (20 bits) 00000000 Sign-extended Page 52 of 1910 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended.  #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended.  #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled.  #imm:3 The 3-bit immediate data (imm) for the BAND, BOR,  BXOR, BST, BLD, BSET, and BCLR instructions indicates the target bit location. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.3.3 Section 2 CPU Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows:  xxxx: Instruction code  mmmm: Source register  nnnn: Destination register  iiii: Immediate data  dddd: Displacement Table 2.9 Instruction Formats Instruction Formats 0 format 15 Source Operand Destination Operand Example   NOP  nnnn: Register direct MOVT Rn Control register or system register nnnn: Register direct STS MACH,Rn R0 (Register direct) nnnn: Register direct DIVU R0,Rn Control register or system register nnnn: Register indirect with predecrement STC.L SR,@-Rn mmmm: Register direct R15 (Register indirect with predecrement) MOVMU.L Rm,@-R15 R15 (Register indirect with postincrement) nnnn: Register direct MOVMU.L @R15+,Rn 0 xxxx xxxx xxxx xxxx n format 15 xxxx 0 nnnn xxxx xxxx R0 (Register direct) nnnn: (Register indirect with postincrement) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 MOV.L R0,@Rn+ Page 53 of 1910 SH726A Group, SH726B Group Section 2 CPU Instruction Formats m format 15 0 xxxx mmmm xxxx xxxx nm format 15 0 xxxx nnnn mmmm xxxx Source Operand Destination Operand mmmm: Register direct Control register or system register LDC mmmm: Register indirect with postincrement Control register or system register LDC.L @Rm+,SR mmmm: Register indirect  JMP mmmm: Register indirect with predecrement R0 (Register direct) MOV.L @-Rm,R0 Example Rm,SR @Rm mmmm: PC relative  using Rm BRAF Rm mmmm: Register direct nnnn: Register direct ADD Rm,Rn mmmm: Register direct nnnn: Register indirect MOV.L Rm,@Rn MACH, MACL mmmm: Register indirect with postincrement (multiplyand-accumulate) MAC.W @Rm+,@Rn+ nnnn*: Register indirect with postincrement (multiplyand-accumulate) md format 15 0 xxxx xxxx Page 54 of 1910 mmmm dddd mmmm: Register indirect with postincrement nnnn: Register direct MOV.L @Rm+,Rn mmmm: Register direct nnnn: Register indirect with predecrement MOV.L Rm,@-Rn mmmm: Register direct nnnn: Indexed register indirect MOV.L Rm,@(R0,Rn) mmmmdddd: Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rm),R0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Source Operand Instruction Formats nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx nnnn mmmm 32 xxxx 15 xxxx 16 nnnn mmmm dddd dddd d format 15 0 xxxx xxxx dddd dddd 15 0 xxxx dddd dddd mmmmdddd: Register indirect with displacement nnnn: Register direct mmmm: Register direct nnnndddd: Register MOV.L indirect with Rm,@(disp12,Rn) displacement mmmmdddd: Register indirect with displacement nnnn: Register direct dddddddd: GBR indirect with displacement R0 (Register direct) MOV.L @(disp,GBR),R0 15 0 xxxx nnnn dddd dddd R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 MOV.L @(disp,Rm),Rn MOV.L @(disp12,Rm),Rn MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (Register direct) MOVA @(disp,PC),R0 dddddddd: TBR duplicate indirect with displacement  JSR/N @@(disp8,TBR) dddddddd: PC relative  BF label dddddddddddd: PC  relative BRA label dddddddd: PC relative with displacement MOV.L @(disp,PC),Rn dddd nd8 format MOV.B R0,@(disp,Rn) nnnndddd: Register MOV.L Rm,@(disp,Rn) indirect with displacement R0 (Register direct) dddddddd: GBR indirect with displacement d12 format Example mmmm: Register direct xxxx 0 dddd R0 (Register direct) nnnndddd: Register indirect with displacement dddd nmd12 format Destination Operand nnnn: Register direct (label = disp + PC) Page 55 of 1910 SH726A Group, SH726B Group Section 2 CPU Instruction Formats Source Operand Destination Operand Example i format iiiiiiii: Immediate Indexed GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Register direct) AND iiiiiiii: Immediate  TRAPA iiiiiiii: Immediate nnnn: Register direct ADD 15 xxxx xxxx iiii 0 iiii ni format 15 #imm,R0 #imm #imm,Rn 0 xxxx nnnn iiii iiii nnnn: Register direct  ni3 format 15 0 xxxx xxxx nnnn x iii BLD #imm3,Rn nnnn: Register direct BST #imm3,Rn iii: Immediate  iii: Immediate ni20 format 32 xxxx nnnn iiii xxxx 15 iiii iiii iiii iiii 16 15 xxxx nnnn: Register direct MOVI20 #imm20, Rn 0 nid format 32 xxxx iiiiiiiiiiiiiiiiiiii: Immediate 16 nnnn xiii xxxx 0 dddd dddd dddd nnnndddddddddddd:  Register indirect with displacement BLD.B #imm3,@(disp12,Rn) iii: Immediate  nnnndddddddddddd: BST.B Register indirect with #imm3,@(disp12,Rn) displacement iii: Immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. Page 56 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU 2.4 Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Operation Classification Types Code Function No. of Instructions Data transfer 62 13 MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Reverse stack transfer MOVA Effective address transfer MOVI20 20-bit immediate data transfer MOVI20S 20-bit immediate data transfer 8-bit left-shit R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 MOVML R0–Rn register save/restore MOVMU Rn–R14 and PR register save/restore MOVRT T bit inversion and transfer to Rn MOVT T bit transfer MOVU Unsigned data transfer NOTT T bit inversion PREF Prefetch to operand cache SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected Page 57 of 1910 SH726A Group, SH726B Group Section 2 CPU Operation Classification Types Code Function No. of Instructions Arithmetic operations 40 26 ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow check CMP/cond Comparison Page 58 of 1910 CLIPS Signed saturation value comparison CLIPU Unsigned saturation value comparison DIVS Signed division (32  32) DIVU Unsigned division (32  32) DIV1 One-step division DIV0S Initialization of signed one-step division DIV0U Initialization of unsigned one-step division DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, double-precision multiply-and-accumulate operation MUL Double-precision multiply operation MULR Signed multiplication with result storage in Rn MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Operation Classification Types Code Function No. of Instructions Logic operations 14 Shift Branch 6 12 10 AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set XOR Exclusive OR ROTL One-bit left rotation ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAD Dynamic arithmetic shift SHAL One-bit arithmetic left shift 16 SHAR One-bit arithmetic right shift SHLD Dynamic logical shift SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift SHLRn n-bit logical right shift BF Conditional branch, conditional delayed branch 15 (branch when T = 0) BT Conditional branch, conditional delayed branch (branch when T = 1) BRA Unconditional delayed branch BRAF Unconditional delayed branch BSR Delayed branch to subroutine procedure BSRF Delayed branch to subroutine procedure JMP Unconditional delayed branch JSR Branch to subroutine procedure Delayed branch to subroutine procedure RTS Return from subroutine procedure Delayed return from subroutine procedure RTV/N R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Return from subroutine procedure with Rm  R0 transfer Page 59 of 1910 SH726A Group, SH726B Group Section 2 CPU Operation Classification Types Code Function No. of Instructions System control 36 14 CLRT T bit clear CLRMAC MAC register clear LDBANK Register restoration from specified register bank entry LDC Load to control register LDS Load to system register NOP No operation RESBANK Register restoration from register bank Floating-point 19 instructions Page 60 of 1910 RTE Return from exception handling SETT T bit set SLEEP Transition to power-down mode STBANK Register save to specified register bank entry STC Store control register data STS Store system register data TRAPA Trap exception handling FABS Floating-point absolute value FADD Floating-point addition FCMP Floating-point comparison FCNVDS Conversion from double-precision to singleprecision FCNVSD Conversion from single-precision to double precision FDIV Floating-point division FLDI0 Floating-point load immediate 0 FLDI1 Floating-point load immediate 1 FLDS Floating-point load into system register FPUL FLOAT Conversion from integer to floating-point FMAC Floating-point multiply and accumulate operation FMOV Floating-point data transfer FMUL Floating-point multiplication FNEG Floating-point sign inversion 48 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Operation Classification Types Code Function No. of Instructions Floating-point 19 instructions 48 FPU-related CPU instructions 2 Bit manipulation 10 FSCHG SZ bit inversion FSQRT Floating-point square root FSTS Floating-point store from system register FPUL FSUB Floating-point subtraction FTRC Floating-point conversion with rounding to integer LDS Load into floating-point system register STS Store from floating-point system register BAND Bit AND BCLR Bit clear BLD Bit load BOR Bit OR BSET Bit set BST Bit store BXOR Bit exclusive OR 8 14 BANDNOT Bit NOT AND Total: 112 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 BORNOT Bit NOT OR BLDNOT Bit NOT load 253 Page 61 of 1910 SH726A Group, SH726B Group Section 2 CPU The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Execution States T Bit Value when no wait states are inserted.*1 Value of T bit after instruction is executed. Instruction Instruction Code Operation Indicated by mnemonic. Indicated in MSB  LSB order. Indicates summary of operation. [Legend] [Legend] [Legend] Explanation of Symbols Rm: Source register mmmm: Source register , : Transfer direction : No change Rn: Destination register nnnn: Destination register 0000: R0 0001: R1 ......... (xx): Memory operand imm: Immediate data disp: Displacement*2 1111: R15 iiii: Immediate data dddd: Displacement M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: Exclusive logical OR of each bit ~: Logical NOT of each bit n: n-bit right shift Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory  register) is the same as the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by 1, 2, or 4. For details, refer to the SH-2A, SH2A-FPU Software Manual. Page 62 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.4.2 Section 2 CPU Data Transfer Instructions Table 2.11 Data Transfer Instructions Compatibility Execution Instruction SH2, Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A MOV #imm,Rn 1110nnnniiiiiiii imm  sign extension  Rn 1  Yes Yes Yes MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp  2 + PC)  sign 1  Yes Yes Yes extension  Rn MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp  4 + PC)  Rn 1  Yes Yes Yes MOV Rm,Rn 0110nnnnmmmm0011 Rm  Rn 1  Yes Yes Yes MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm  (Rn) 1  Yes Yes Yes MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm  (Rn) 1  Yes Yes Yes MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm  (Rn) 1  Yes Yes Yes MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm)  sign extension  Rn 1  Yes Yes Yes MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm)  sign extension  Rn 1  Yes Yes Yes MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm)  Rn 1  Yes Yes Yes MOV.B Rm,@-Rn 0010nnnnmmmm0100 Rn-1  Rn, Rm  (Rn) 1  Yes Yes Yes MOV.W Rm,@-Rn 0010nnnnmmmm0101 Rn-2  Rn, Rm  (Rn) 1  Yes Yes Yes MOV.L Rm,@-Rn 0010nnnnmmmm0110 Rn-4  Rn, Rm  (Rn) 1  Yes Yes Yes MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm)  sign extension  Rn, 1  Yes Yes Yes  Yes Yes Yes Rm + 1  Rm MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm)  sign extension  Rn, 1 Rm + 2  Rm MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm)  Rn, Rm + 4  Rm 1  Yes Yes Yes MOV.B R0,@(disp,Rn) 10000000nnnndddd R0  (disp + Rn) 1  Yes Yes Yes MOV.W R0,@(disp,Rn) 10000001nnnndddd R0  (disp  2 + Rn) 1  Yes Yes Yes MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm  (disp  4 + Rn) 1  Yes Yes Yes MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm)  sign extension 1  Yes Yes Yes 1  Yes Yes Yes  R0 MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp  2 + Rm)  sign extension  R0 MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp  4 + Rm)  Rn 1  Yes Yes Yes MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm  (R0 + Rn) 1  Yes Yes Yes MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm  (R0 + Rn) 1  Yes Yes Yes R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 63 of 1910 SH726A Group, SH726B Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm  (R0 + Rn) 1  Yes Yes Yes MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm)  1  Yes Yes Yes 1  Yes Yes Yes sign extension  Rn MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm)  sign extension  Rn MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm)  Rn 1  Yes Yes Yes MOV.B R0,@(disp,GBR) 11000000dddddddd R0  (disp + GBR) 1  Yes Yes Yes MOV.W R0,@(disp,GBR) 11000001dddddddd R0  (disp  2 + GBR) 1  Yes Yes Yes MOV.L R0,@(disp,GBR) 11000010dddddddd R0  (disp  4 + GBR) 1  Yes Yes Yes MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR)  1  Yes Yes Yes 1  Yes Yes Yes Yes Yes Yes sign extension  R0 MOV.W @(disp,GBR),R0 11000101dddddddd (disp  2 + GBR)  sign extension  R0 MOV.L @(disp,GBR),R0 11000110dddddddd (disp  4 + GBR)  R0 1  MOV.B R0,@Rn+ 0100nnnn10001011 R0  (Rn), Rn + 1  Rn 1  Yes MOV.W R0,@Rn+ 0100nnnn10011011 R0  (Rn), Rn + 2  Rn 1  Yes MOV.L R0,@Rn+ 0100nnnn10101011 R0  Rn), Rn + 4  Rn 1  Yes MOV.B @-Rm,R0 0100mmmm11001011 Rm-1  Rm, (Rm)  1  Yes 1  Yes Rm-4  Rm, (Rm)  R0 1  Yes Rm  (disp + Rn) 1  Yes Rm  (disp  2 + Rn) 1  Yes Rm  (disp  4 + Rn) 1  Yes (disp + Rm)  1  Yes 1  Yes sign extension  R0 MOV.W @-Rm,R0 0100mmmm11011011 Rm-2  Rm, (Rm)  sign extension  R0 MOV.L @-Rm,R0 MOV.B Rm,@(disp12,Rn) 0011nnnnmmmm0001 0100mmmm11101011 0000dddddddddddd MOV.W Rm,@(disp12,Rn) 0011nnnnmmmm0001 0001dddddddddddd MOV.L Rm,@(disp12,Rn) 0011nnnnmmmm0001 MOV.B @(disp12,Rm),Rn 0011nnnnmmmm0001 0010dddddddddddd 0100dddddddddddd MOV.W @(disp12,Rm),Rn 0011nnnnmmmm0001 0101dddddddddddd Page 64 of 1910 sign extension  Rn (disp  2 + Rm)  sign extension  Rn R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Compatibility Execution Instruction MOV.L Instruction Code @(disp12,Rm),Rn 0011nnnnmmmm0001 SH2, Operation Cycles T Bit (disp  4 + Rm)  Rn 1  SH2E SH4 SH-2A Yes 0110dddddddddddd MOVA @(disp,PC),R0 11000111dddddddd disp  4 + PC  R0 1  MOVI20 #imm20,Rn 0000nnnniiii0000 imm  sign extension  Rn 1  Yes imm Rm (unsigned), 1 Com- 1T parison Otherwise, 0  T result When Rn > Rm (signed), 1 Com- 1T parison Otherwise, 0  T result When Rn > 0, 1  T 1 Otherwise, 0  T Comparison result CMP/PZ Rn 0100nnnn00010001 When Rn  0, 1  T 1 Otherwise, 0  T Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 When any bytes are equal, 1 Com- 1T parison Otherwise, 0  T result Page 67 of 1910 SH726A Group, SH726B Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit CLIPS.B 0100nnnn10010001 When Rn > (H'0000007F), 1  Yes 1  Yes 1  Yes 1  Yes 1 Calcu- Yes Rn SH2E SH4 SH-2A (H'0000007F)  Rn, 1  CS when Rn < (H'FFFFFF80), (H'FFFFFF80)  Rn, 1  CS CLIPS.W Rn 0100nnnn10010101 When Rn > (H'00007FFF), (H'00007FFF)  Rn, 1  CS When Rn < (H'FFFF8000), (H'FFFF8000)  Rn, 1  CS CLIPU.B Rn 0100nnnn10000001 When Rn > (H'000000FF), (H'000000FF)  Rn, 1  CS CLIPU.W Rn 0100nnnn10000101 When Rn > (H'0000FFFF), (H'0000FFFF)  Rn, 1  CS DIV1 Rm,Rn 0011nnnnmmmm0100 1-step division (Rn  Rm) Yes Yes Yes Yes Yes Yes lation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn  Q, 1 MSB of Rm  M, M ^ Q  T Calcu- Yes lation result DIV0U DIVS 0000000000011001 R0,Rn 0100nnnn10010100 0  M/Q/T 1 0 Signed operation of Rn  R0 36  Yes Unsigned operation of Rn  R0 34  Yes Yes  Rn 32  32  32 bits DIVU R0,Rn 0100nnnn10000100  Rn 32  32  32 bits DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn  Rm 2  Yes Yes Yes 2  Yes Yes Yes 1 Compa Yes Yes Yes  MACH, MACL 32  32  64 bits DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn  Rm  MACH, MACL 32  32  64 bits DT EXTS.B Rn Rm,Rn 0100nnnn00010000 0110nnnnmmmm1110 Rn – 1  Rn When Rn is 0, 1  T -rison When Rn is not 0, 0  T result Byte in Rm is 1  Yes Yes Yes 1  Yes Yes Yes sign-extended  Rn EXTS.W Rm,Rn 0110nnnnmmmm1111 Word in Rm is sign-extended  Rn Page 68 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A EXTU.B 0110nnnnmmmm1100 Byte in Rm is 1  Yes Yes Yes 1  Yes Yes Yes 4  Yes Yes Yes 3  Yes Yes Yes 2  Yes Yes Yes Rm,Rn zero-extended  Rn EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended  Rn MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn)  (Rm) + MAC  MAC 32  32 + 64  64 bits MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn)  (Rm) + MAC  MAC 16  16 + 64  64 bits MUL.L Rm,Rn 0000nnnnmmmm0111 Rn  Rm  MACL 32  32  32 bits MULR R0,Rn 0100nnnn10000000 R0  Rn  Rn 2 Yes 32  32  32 bits MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn  Rm 1  Yes Yes Yes 1  Yes Yes Yes  MACL 16  16  32 bits MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn  Rm  MACL 16  16  32 bits NEG Rm,Rn 0110nnnnmmmm1011 0-Rm  Rn 1  Yes Yes Yes NEGC Rm,Rn 0110nnnnmmmm1010 0-Rm-T  Rn, borrow  T 1 Borrow Yes Yes Yes SUB Rm,Rn 0011nnnnmmmm1000 Rn-Rm  Rn 1  Yes Yes Yes SUBC Rm,Rn 0011nnnnmmmm1010 Rn-Rm-T  Rn, borrow  T 1 Borrow Yes Yes Yes SUBV Rm,Rn 0011nnnnmmmm1011 Rn-Rm  Rn, underflow  T 1 Over- Yes Yes Yes flow R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 69 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.4.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm  Rn 1  Yes Yes Yes AND #imm,R0 11001001iiiiiiii R0 & imm  R0 1  Yes Yes Yes AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm  3  Yes Yes Yes (R0 + GBR) NOT Rm,Rn 0110nnnnmmmm0111 ~Rm  Rn 1  Yes Yes Yes OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm  Rn 1  Yes Yes Yes OR #imm,R0 11001011iiiiiiii R0 | imm  R0 1  Yes Yes Yes OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm  3  Yes Yes Yes Test Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (R0 + GBR) TAS.B @Rn 0100nnnn00011011 When (Rn) is 0, 1  T 3 Otherwise, 0  T, result 1  MSB of(Rn) TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm 1 When the result is 0, 1  T Test result Otherwise, 0  T TST #imm,R0 11001000iiiiiiii R0 & imm 1 When the result is 0, 1  T Test result Otherwise, 0  T TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm 3 When the result is 0, 1  T Test result Otherwise, 0  T Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm  Rn XOR #imm,R0 11001010iiiiiiii R0 ^ imm  R0 1  Yes Yes Yes XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm  3  Yes Yes Yes XOR 1  (R0 + GBR) Page 70 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.4.5 Section 2 CPU Shift Instructions Table 2.14 Shift Instructions Compatibility Execution Cycles SH2, T Bit SH2E SH4 Instruction Instruction Code Operation SH-2A ROTL Rn 0100nnnn00000100 T  Rn  MSB 1 MSB Yes Yes Yes ROTR Rn 0100nnnn00000101 LSB  Rn  T 1 LSB Yes Yes Yes ROTCL Rn 0100nnnn00100100 T  Rn  T 1 MSB Yes Yes Yes ROTCR Rn 0100nnnn00100101 T  Rn  T 1 LSB Yes Yes Yes SHAD Rm,Rn 0100nnnnmmmm1100 When Rm  0, Rn > |Rm|  [MSB  Rn] SHAL Rn 0100nnnn00100000 T  Rn  0 1 MSB Yes Yes Yes SHAR Rn 0100nnnn00100001 MSB  Rn  T 1 LSB Yes Yes Yes SHLD Rm,Rn 0100nnnnmmmm1101 When Rm  0, Rn > |Rm|  [0  Rn] SHLL Rn 0100nnnn00000000 T  Rn  0 1 MSB Yes Yes Yes SHLR Rn 0100nnnn00000001 0  Rn  T 1 LSB Yes Yes Yes SHLL2 Rn 0100nnnn00001000 Rn > 2  Rn 1  Yes Yes Yes SHLL8 Rn 0100nnnn00011000 Rn > 8  Rn 1  Yes Yes Yes SHLL16 Rn 0100nnnn00101000 Rn > 16  Rn 1  Yes Yes Yes R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 71 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.4.6 Branch Instructions Table 2.15 Branch Instructions Compatibility Execution Instruction Instruction Code BF 10001011dddddddd label SH2, Operation Cycles T Bit SH2E SH4 SH-2A When T = 0, disp  2 + PC  3/1*  Yes Yes Yes 2/1*  Yes Yes Yes 3/1*  Yes Yes Yes 2/1*  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes Delayed branch, Rm  PC 2  Yes Yes Yes Delayed branch, PC  PR, 2  Yes Yes Yes PC, When T = 1, nop BF/S label 10001111dddddddd Delayed branch When T = 0, disp  2 + PC  PC, When T = 1, nop BT label 10001001dddddddd When T = 1, disp  2 + PC  PC, When T = 0, nop BT/S label 10001101dddddddd Delayed branch When T = 1, disp  2 + PC  PC, When T = 0, nop BRA label 1010dddddddddddd Delayed branch, disp  2 + PC  PC BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC  PC BSR label 1011dddddddddddd Delayed branch, PC  PR, disp  2 + PC  PC BSRF Rm 0000mmmm00000011 Delayed branch, PC  PR, Rm + PC  PC JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 Rm  PC JSR/N @Rm 0100mmmm01001011 PC-2  PR, Rm  PC 3  Yes JSR/N @@(disp8,TBR) 10000011dddddddd PC-2  PR, 5  Yes (disp  4 + TBR)  PC RTS 0000000000001011 Delayed branch, PR  PC 2  RTS/N 0000000001101011 PR  PC 3  Yes 0000mmmm01111011 Rm  R0, PR  PC 3  Yes RTV/N Note: Rm * Yes Yes Yes One cycle when the program does not branch. Page 72 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.4.7 Section 2 CPU System Control Instructions Table 2.16 System Control Instructions Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A CLRT 0000000000001000 0T 1 0 Yes Yes Yes CLRMAC 0000000000101000 0  MACH,MACL 1  Yes Yes Yes 0100mmmm11100101 (Specified register bank entry) 6  LDBANK @Rm,R0 Yes  R0 LDC Rm,SR 0100mmmm00001110 Rm  SR 3 LSB LDC Rm,TBR 0100mmmm01001010 Rm  TBR 1  LDC Rm,GBR 0100mmmm00011110 Rm  GBR 1  Yes Yes LDC Rm,VBR 0100mmmm00101110 Rm  VBR 1  Yes Yes Yes LDC.L @Rm+,SR 0100mmmm00000111 (Rm)  SR, Rm + 4  Rm 5 LSB Yes Yes Yes LDC.L @Rm+,GBR 0100mmmm00010111 (Rm)  GBR, Rm + 4  Rm 1  Yes Yes Yes LDC.L @Rm+,VBR 0100mmmm00100111 (Rm)  VBR, Rm + 4  Rm 1  Yes Yes Yes LDS Rm,MACH 0100mmmm00001010 Rm  MACH 1  Yes Yes Yes LDS Rm,MACL 0100mmmm00011010 Rm  MACL 1  Yes Yes Yes LDS Rm,PR 0100mmmm00101010 Rm  PR 1  Yes Yes Yes LDS.L @Rm+,MACH 0100mmmm00000110 (Rm)  MACH, Rm + 4  Rm 1  Yes Yes Yes LDS.L @Rm+,MACL 0100mmmm00010110 (Rm)  MACL, Rm + 4  Rm 1  Yes Yes Yes LDS.L @Rm+,PR 0100mmmm00100110 (Rm)  PR, Rm + 4  Rm 1  Yes Yes Yes NOP 0000000000001001 No operation 1  Yes Yes Yes RESBANK 0000000001011011 Bank  R0 to R14, GBR, 9*  6  Yes Yes Yes Yes Yes Yes Yes Yes Yes MACH, MACL, PR RTE 0000000000101011 Delayed branch, stack area  PC/SR SETT 0000000000011000 1T 1 1 Yes Yes Yes SLEEP 0000000000011011 Sleep 5  Yes Yes Yes 0100nnnn11100001 R0  7  STBANK R0,@Rn Yes (specified register bank entry) STC SR,Rn 0000nnnn00000010 SR  Rn 2  STC TBR,Rn 0000nnnn01001010 TBR  Rn 1  R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Yes Yes Yes Yes Page 73 of 1910 SH726A Group, SH726B Group Section 2 CPU Compatibility Execution SH2, Instruction Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A STC GBR,Rn 0000nnnn00010010 GBR  Rn 1  Yes Yes Yes STC VBR,Rn 0000nnnn00100010 VBR  Rn 1  Yes Yes Yes STC.L SR,@-Rn 0100nnnn00000011 Rn-4  Rn, SR  (Rn) 2  Yes Yes Yes STC.L GBR,@-Rn 0100nnnn00010011 Rn-4  Rn, GBR  (Rn) 1  Yes Yes Yes STC.L VBR,@-Rn 0100nnnn00100011 Rn-4  Rn, VBR  (Rn) 1  Yes Yes Yes STS MACH,Rn 0000nnnn00001010 MACH  Rn 1  Yes Yes Yes STS MACL,Rn 0000nnnn00011010 MACL  Rn 1  Yes Yes Yes STS PR,Rn 0000nnnn00101010 PR  Rn 1  Yes Yes Yes STS.L MACH,@-Rn 0100nnnn00000010 Rn-4  Rn, MACH  (Rn) 1  Yes Yes Yes STS.L MACL,@-Rn 0100nnnn00010010 Rn-4  Rn, MACL  (Rn) 1  Yes Yes Yes STS.L PR,@-Rn 0100nnnn00100010 Rn-4  Rn, PR  (Rn) 1  Yes Yes Yes TRAPA #imm 11000011iiiiiiii PC/SR  stack area, 5  Yes Yes Yes (imm  4 + VBR)  PC Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory  register) is the same as the register used by the next instruction. * In the event of bank overflow, the number of cycles is 19. Page 74 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.4.8 Section 2 CPU Floating-Point Operation Instructions Table 2.17 Floating-Point Operation Instructions Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit FABS FRn 1111nnnn01011101 |FRn|  FRn 1  FABS DRn 1111nnn001011101 |DRn|  DRn 1  FADD FRm, FRn 1111nnnnmmmm0000 FRn + FRm  FRn 1  FADD DRm, DRn 1111nnn0mmm00000 DRn + DRm  DRn 6  FCMP/EQ FRm, FRn 1111nnnnmmmm0100 (FRn = FRm)? 1:0  T 1 Com- SH2E SH4 FPU Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes parison result FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn = DRm)? 1:0  T 2 Comparison result FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn > FRm)? 1:0  T 1 Com- Yes parison result FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn > DRm)? 1:0  T 2 Comparison result FCNVDS DRm, FPUL 1111mmm010111101 (float) DRm  FPUL 2  Yes Yes FCNVSD FPUL, DRn 1111nnn010101101 (double) FPUL  DRn 2  Yes Yes FDIV FRm, FRn 1111nnnnmmmm0011 FRn/FRm  FRn 10  Yes Yes FDIV DRm, DRn 1111nnn0mmm00011 DRn/DRm  DRn 23  Yes Yes FLDI0 FRn 1111nnnn10001101 0  00000000  FRn 1  Yes Yes Yes FLDI1 FRn 1111nnnn10011101 0  3F800000  FRn 1  Yes Yes Yes FLDS FRm, FPUL 1111mmmm00011101 FRm  FPUL 1  Yes Yes Yes FLOAT FPUL,FRn 1111nnnn00101101 (float)FPUL  FRn 1  Yes Yes Yes FLOAT FPUL,DRn 1111nnn000101101 (double)FPUL  DRn 2  Yes Yes FMAC FR0,FRm,FRn 1111nnnnmmmm1110 FR0  FRm+FRn  1  Yes Yes Yes Yes Yes Yes Yes Yes Yes FRn FMOV FRm, FRn 1111nnnnmmmm1100 FRm  FRn 1  FMOV DRm, DRn 1111nnn0mmm01100 DRm  DRn 2  R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 75 of 1910 SH726A Group, SH726B Group Section 2 CPU Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit SH2E SH4 FPU FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 (R0 + Rm)  FRn 1  Yes Yes Yes FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0 + Rm)  DRn 2  Yes Yes FMOV.S @Rm+, FRn 1111nnnnmmmm1001 (Rm)  FRn, Rm+=4 1  FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm)  DRn, Rm += 8 2  Yes Yes Yes Yes FMOV.S @Rm, FRn 1111nnnnmmmm1000 (Rm)  FRn 1  Yes Yes FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm)  DRn 2  Yes Yes FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 (disp  4 + Rm)  FRn 1  Yes (disp  8 + Rm)  DRn 2  Yes Yes Yes 0111dddddddddddd FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd FMOV.S FRm, @(R0,Rn) 1111nnnnmmmm0111 FRm  (R0 + Rn) 1  FMOV.D DRm, @(R0,Rn) 1111nnnnmmm00111 DRm  (R0 + Rn) 2  FMOV.S FRm, @-Rn 1111nnnnmmmm1011 Rn-=4, FRm  (Rn) 1  FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn-=8, DRm  (Rn) 2  FMOV.S FRm, @Rn 1111nnnnmmmm1010 FRm  (Rn) 1  FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm  (Rn) 2  FMOV.S FRm, 0011nnnnmmmm0001 FRm  (disp  4 + Rn) 1  Yes DRm  (disp  8 + Rn) 2  Yes @(disp12,Rn) 0011dddddddddddd FMOV.D 0011nnnnmmm00001 DRm, @(disp12,Rn) 0011dddddddddddd FMUL FRm, FRn 1111nnnnmmmm0010 FRn  FRm  FRn 1  FMUL DRm, DRn 1111nnn0mmm00010 DRn  DRm  DRn 6  FNEG FRn 1111nnnn01001101 -FRn  FRn 1  FNEG DRn 1111nnn001001101 -DRn  DRn 1  1111001111111101 FPSCR.SZ=~FPSCR.S 1 FSCHG Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes  Yes Yes Yes Z FSQRT FRn 1111nnnn01101101 FRn  FRn 9  Yes Yes FSQRT DRn 1111nnn001101101 DRn  DRn 22  Yes Yes FSTS FPUL,FRn 1111nnnn00001101 FPUL  FRn 1  Yes Yes Yes FSUB FRm, FRn 1111nnnnmmmm0001 FRn-FRm  FRn 1  Yes Yes Yes Page 76 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 2 CPU Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit FSUB DRm, DRn 1111nnn0mmm00001 DRn-DRm  DRn 6  FTRC FRm, FPUL 1111mmmm00111101 (long)FRm  FPUL 1  FTRC DRm, FPUL 1111mmm000111101 (long)DRm  FPUL 2  2.4.9 FPU-Related CPU Instructions SH2E Yes SH4 FPU Yes Yes Yes Yes Yes Yes Table 2.18 FPU-Related CPU Instructions Compatibility Execu- SH-2A/ tion SH2A- Instruction Instruction Code Operation Cycles T Bit SH2E SH4 FPU LDS Rm,FPSCR 0100mmmm01101010 Rm  FPSCR 1  Yes Yes Yes LDS Rm,FPUL 0100mmmm01011010 Rm  FPUL 1  Yes Yes Yes LDS.L @Rm+, FPSCR 0100mmmm01100110 (Rm)  FPSCR, Rm+=4 1  Yes Yes Yes LDS.L @Rm+, FPUL 0100mmmm01010110 (Rm)  FPUL, Rm+=4 1  Yes Yes Yes STS FPSCR, Rn 0000nnnn01101010 FPSCR  Rn 1  Yes Yes Yes STS FPUL,Rn 0000nnnn01011010 FPUL  Rn 1  Yes Yes Yes STS.L FPSCR,@-Rn 0100nnnn01100010 Rn-=4, FPCSR  (Rn) 1  Yes Yes Yes STS.L FPUL,@-Rn 0100nnnn01010010 Rn-=4, FPUL  (Rn) 1  Yes Yes Yes R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 77 of 1910 SH726A Group, SH726B Group Section 2 CPU 2.4.10 Bit Manipulation Instructions Table 2.19 Bit Manipulation Instructions Compatibility ExecuInstruction BAND.B #imm3,@(disp12,Rn) tion SH2, Instruction Code Operation Cycles T Bit SH2E SH4 SH-2A 0011nnnn0iii1001 (imm of (disp + Rn)) & T  3 Ope- Yes ration 0100dddddddddddd result BANDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) & T  T 3 Ope- Yes ration 1100dddddddddddd result BCLR.B #imm3,@(disp12,Rn) BCLR #imm3,Rn BLD.B #imm3,@(disp12,Rn) 0  (imm of (disp + Rn)) 3  Yes 10000110nnnn0iii 0  imm of Rn 1  Yes 0011nnnn0iii1001 (imm of (disp + Rn))  3 Ope- Yes 0011nnnn0iii1001 0000dddddddddddd ration 0011dddddddddddd result BLD #imm3,Rn 10000111nnnn1iii imm of Rn  T 1 Ope- Yes ration result BLDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1011dddddddddddd ~(imm of (disp + Rn)) 3 T Ope- Yes ration result BOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ( imm of (disp + Rn)) | T  T 3 Ope- Yes ration 0101dddddddddddd result BORNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~( imm of (disp + Rn)) | T  T 3 Ope- Yes ration 1101dddddddddddd result BSET.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1  ( imm of (disp + Rn)) 3  Yes 0001dddddddddddd BSET #imm3,Rn 10000110nnnn1iii 1  imm of Rn 1  Yes BST.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 T  (imm of (disp + Rn)) 3  Yes 0010dddddddddddd BST #imm3,Rn 10000111nnnn0iii T  imm of Rn 1  Yes BXOR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 (imm of (disp + Rn)) ^ T  T 3 Ope- Yes 0110dddddddddddd ration result Page 78 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 2.5 Section 2 CPU Processing States The CPU has four processing states: reset, exception handling, program execution, and powerdown. Figure 2.6 shows the transitions between the states. Manual reset from any state Power-on reset from any state Manual reset state Power-on reset state Reset state Reset canceled Interrupt source or DMA address error occurs Exception handling state Exception handling source occurs NMI interrupt or IRQ interrupt occurs NMI interrupt, realtime clock alarm interrupt, change on the pins for canceling, and power-on reset Exception handling ends Program execution state STBY bit cleared for SLEEP instruction Sleep mode STBY bit set and DEEP bit cleared for SLEEP instruction Software standby mode STBY and DEEP bits set for SLEEP instruction Deep standby mode Power-down state Figure 2.6 Transitions between Processing States R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 79 of 1910 Section 2 CPU (1) SH726A Group, SH726B Group Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources such as resets or interrupts alter the CPU’s processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception handling vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception handling vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. (3) Program Execution State In the program execution state, the CPU sequentially executes the program. (4) Power-Down State In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP instruction places the CPU in sleep mode, software standby mode, or deep standby mode. Page 80 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 3 3.1 Section 3 Floating-Point Unit (FPU) Floating-Point Unit (FPU) Features The FPU has the following features.  Conforms to IEEE754 standard  16 single-precision floating-point registers (can also be referenced as eight double-precision registers)  Two rounding modes: Round to nearest and round to zero  Denormalization modes: Flush to zero  Five exception sources: Invalid operation, divide by zero, overflow, underflow, and inexact  Comprehensive instructions: Single-precision, double-precision, and system control R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 81 of 1910 SH726A Group, SH726B Group Section 3 Floating-Point Unit (FPU) 3.2 Data Formats 3.2.1 Floating-Point Format A floating-point number consists of the following three fields:  Sign (s)  Exponent (e)  Fraction (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 3.1 and 3.2. 31 30 s Figure 3.1 63 23 f Format of Single-Precision Floating-Point Number 62 s Figure 3.2 0 22 e 52 0 51 e f Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin – 1 to Emax + 1. The two values Emin – 1 and Emax + 1 are distinguished as follows. Emin – 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). Table 3.1 shows Emin and Emax values. Page 82 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Table 3.1 Section 3 Floating-Point Unit (FPU) Floating-Point Number Formats and Parameters Parameter Single-Precision Double-Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias +127 +1023 Emax +127 +1023 Emin –126 –1022 Floating-point number value v is determined as follows: If E = Emax + 1 and f  0, v is a non-number (NaN) irrespective of sign s s If E = Emax + 1 and f = 0, v = (–1) (infinity) [positive or negative infinity] If Emin  E  Emax , v = (–1) 2 (1.f) [normalized number] s E If E = Emin – 1 and f  0, v = (–1) 2 s Emin (0.f) [denormalized number] s If E = Emin – 1 and f = 0, v = (–1) 0 [positive or negative zero] R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 83 of 1910 Section 3 SH726A Group, SH726B Group Floating-Point Unit (FPU) Table 3.2 shows the ranges of the various numbers in hexadecimal notation. Table 3.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFF FFFF to H'7FC0 0000 H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 Quiet non-number H'7FBF FFFF to H'7F80 0001 H'7FF7 FFFF FFFF FFFF to H'7FF0 0000 0000 0001 Positive infinity H'7F80 0000 H'7FF0 0000 Positive normalized number H'7F7F FFFF to H'0080 0000 H'7FEF FFFF FFFF FFFF to H'0010 0000 0000 0000 Positive denormalized number H'007F FFFF to H'0000 0001 H'000F FFFF FFFF FFFF to H'0000 0000 0000 0001 Positive zero H'0000 0000 H'0000 0000 0000 0000 0000 0000 0000 0000 Negative zero H'8000 0000 H'8000 0000 Negative denormalized number H'8000 0001 to H'807F FFFF H'8000 0000 0000 0001 to H'800F FFFF FFFF FFFF Negative normalized number H'8080 0000 to H'FF7F FFFF H'8010 0000 0000 0000 to H'FFEF FFFF FFFF FFFF Negative infinity H'FF80 0000 H'FFF0 0000 Quiet non-number H'FF80 0001 to H'FFBF FFFF H'FFF0 0000 0000 0001 to H'FFF7 FFFF FFFF FFFF Signaling non-number H'FFC0 0000 to H'FFFF FFFF H'FFF8 0000 0000 0000 to H'FFFF FFFF FFFF FFFF Page 84 of 1910 0000 0000 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 3.2.2 Section 3 Floating-Point Unit (FPU) Non-Numbers (NaN) Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:  Sign bit: Don't care  Exponent field: All bits are 1  Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0. 31 30 23 x 22 11111111 0 Nxxxxxxxxxxxxxxxxxxxxxx N = 1: sNaN N = 0: qNaN Figure 3.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value.  When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN.  When the EN.V bit in FPSCR is 1, an invalid operation exception will generate FPU exception processing. In this case, the contents of the operation destination register are unchanged. If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit in FPSCR. An exception will not be generated in this case. The qNAN values as operation results are as follows:  Single-precision qNaN: H'7FBF FFFF  Double-precision qNaN: H'7FF7 FFFF FFFF FFFF See the individual instruction descriptions for details of floating-point operations when a nonnumber (NaN) is input. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 85 of 1910 Section 3 Floating-Point Unit (FPU) 3.2.3 Denormalized Numbers SH726A Group, SH726B Group For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. In the SH2A-FPU, the DN bit in the status register FPSCR is always set to 1, therefore a denormalized number (source operand or operation result) is always flushed to 0 in a floatingpoint operation that generates a value (an operation other than copy, FNEG, or FABS). When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is processed as it is. See the individual instruction descriptions for details of floating-point operations when a denormalized number is input. Page 86 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 3 3.3 Register Descriptions 3.3.1 Floating-Point Registers Floating-Point Unit (FPU) Figure 3.4 shows the floating-point register configuration. There are sixteen 32-bit floating-point registers FPR0 to FPR15, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14. The correspondence between FRPn and the reference name is determined by the PR and SZ bits in FPSCR. Refer figure 3.4. 1. Floating-point registers, FPRi (16 registers) FPR0 to FPR15 2. Single-precision floating-point registers, FRi (16 registers) FR0 to FR15 indicate FPR0 to FPR15 3. Double-precision floating-point registers or single-precision floating-point vector registers in pairs, DRi (8 registers) A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} Reference name Register name Transfer instruction case: FPSCR.SZ = 0 FPSCR.SZ = 1 Operation instruction case: FPSCR.PR = 0 FPSCR.PR = 1 FR0 DR0 FR1 FR2 DR2 FR3 FR4 DR4 FR5 FR6 DR6 FR7 FR8 DR8 FR9 FR10 DR10 FR11 FR12 DR12 FR13 FR14 DR14 FR15 Figure 3.4 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 FPR0 FPR1 FPR2 FPR3 FPR4 FPR5 FPR6 FPR7 FPR8 FPR9 FPR10 FPR11 FPR12 FPR13 FPR14 FPR15 Floating-Point Registers Page 87 of 1910 SH726A Group, SH726B Group Section 3 Floating-Point Unit (FPU) 3.3.2 Floating-Point Status/Control Register (FPSCR) FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 - - - - - - - - - QIS - SZ PR DN Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 1 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Cause Initial value: 0 R/W: R/W 0 R/W Enable 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Flag 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 23  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 17 16 Cause 0 R/W 0 R/W 1 0 RM1 RM0 0 R/W 1 R/W These bits are always read as 0. The write value should always be 0. 22 QIS 0 R/W Nonnunerical Processing Mode 0: Processes qNaN or  as such 1: Treats qNaN or  as the same as sNaN (valid only when FPSCR.Enable.V = 1) 21  0 R Reserved This bit is always read as 0. The write value should always be 0. 20 SZ 0 R/W Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) 19 PR 0 R/W Precision Mode 0: Floating-point instructions are executed as singleprecision operations 1: Floating-point instructions are executed as doubleprecision operations (graphics support instructions are undefined) 18 DN 1 R Denormalization Mode (Always fixed to 1 in SH2AFPU) 1: Denormalized number is treated as zero Page 88 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 3 Bit Bit Name Initial Value R/W Description 17 to 12 Cause H'00 R/W FPU Exception Cause Field 11 to 7 Enable H'00 R/W FPU Exception Enable Field 6 to 2 Flag H'00 R/W FPU Exception Flag Field Floating-Point Unit (FPU) Each time floating-point operation instruction is executed, the FPU exception cause field is cleared to 0 first. When an FPU exception on floating-point operation occurs, the bits corresponding to the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. As the bits corresponding to FPU exception enable filed are sets to 1, FPU exception processing occurs. For bit allocations of each field, see table 3.3. 1 RM1 0 R/W Rounding Mode 0 RM0 1 R/W These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved Table 3.3 Bit Allocation for FPU Exception Handling Field Name FPU Error (E) Invalid Division Operation (V) by Zero (Z) Overflow Underflow Inexact (O) (U) (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag None field Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Note: No FPU error occurs in the SH2A-FPU. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 89 of 1910 Section 3 Floating-Point Unit (FPU) 3.3.3 Floating-Point Communication Register (FPUL) SH726A Group, SH726B Group Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register that is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number, the processing flow is as follows: R1  (LDS instruction)  FPUL  (single-precision FLOAT instruction)  FR1 Page 90 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 3.4 Section 3 Floating-Point Unit (FPU) Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. Which of the two rounding methods is to be used is determined by the RM bits in FPSCR. FPSCR.RM[1:0] = 00: Round to Nearest FPSCR.RM[1:0] = 01: Round to Zero (1) Round to Nearest The operation result is rounded to the nearest expressible value. If there are two nearest expressible values, the one with an LSB of 0 is selected. Emax –P If the unrounded value is 2 (2 – 2 ) or more, the result will be infinity with the same sign as the unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. (2) Round to Zero The digits below the round bit of the unrounded value are discarded. If the unrounded value is larger than the maximum expressible absolute value, the value will become the maximum expressible absolute value. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 91 of 1910 Section 3 Floating-Point Unit (FPU) 3.5 FPU Exceptions 3.5.1 FPU Exception Sources SH726A Group, SH726B Group FPU exceptions may occur on floating-point operation instruction and the exception sources are as follows:  FPU error (E): When FPSCR.DN = 0 and a denormalized number is input (No error occurs in the SH2A-FPU)  Invalid operation (V): In case of an invalid operation, such as NaN input  Division by zero (Z): Division with a zero divisor  Overflow (O): When the operation result overflows  Underflow (U): When the operation result underflows  Inexact exception (I): When overflow, underflow, or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled. When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the corresponding bit in the FPU exception flag field remains unchanged. 3.5.2 FPU Exception Handling FPU exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No error occurs in the SH2A-FPU)  Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation  Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor  Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result overflow  Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result underflow  Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation result Page 92 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 3 Floating-Point Unit (FPU) These possibilities of each exceptional handling on floating-point operation are shown in the individual instruction descriptions. All exception events that originate in the floating-point operation are assigned as the same FPU exceptional handling event. The meaning of an exception generated by floating-point operation is determined by software by reading from FPSCR and interpreting the information it contains. Also, the destination register is not changed when FPU exception handling operation occurs. Except for the above, the FPU disables exception handling. In every processing, the bit corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the operation result.  Invalid operation (V): qNaN is generated as the result.  Division by zero (Z): Infinity with the same sign as the unrounded value is generated.  Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated.  Underflow (U): Zero with the same sign as the unrounded value is generated.  Inexact exception (I): An inexact result is generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 93 of 1910 Section 3 Floating-Point Unit (FPU) Page 94 of 1910 SH726A Group, SH726B Group R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 4 Boot Mode Section 4 Boot Mode This LSI can be booted from the memory connected to the CS0 space and the serial flash memory. 4.1 Features  Two boot modes Boot mode 0: Boots the LSI from the memory connected to the CS0 space Boot mode 1: Boots the LSI from the serial flash memory 4.2 Boot Mode and Pin Function Setting This LSI can determine the boot mode using external pins when RES is low. The external pin settings for selecting the boot mode are shown in table 4.1. Table 4.1 External Pin (MD_BOOT) Settings and Corresponding Boot Modes MD_BOOT Boot Mode 0 Boot mode 0 Boots the LSI from the memory connected to the CS0 space. 1 Boot mode 1 Boots the LSI from the serial flash memory connected to channel 0 (PF3 to PF0) of the Renesas serial peripheral interface, though does not boot from the serial flash memory connected to channel 0 (PB18 to PB15). R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 95 of 1910 Section 4 Boot Mode 4.3 Operation 4.3.1 Boot Mode 0 SH726A Group, SH726B Group In boot mode 0, this LSI is booted from the memory connected to the CS0 space. In this mode, this LSI operates as follows: After the power-on reset is canceled, the initial value (execution start address) of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table located in the memory connected to the CS0 space, then program execution is started. 4.3.2 Boot Mode 1 In boot mode 1, booting up is from serial flash memory, which is connected to channel 0 of the Renesas serial peripheral interface. The flow of initiation in boot mode 1 is as described below. (1) Execution from On-Chip ROM of the Program for Boot Initiation After release from the power-on reset state, the CPU executes the boot initiation program that has been stored in on-chip ROM (and is not publicly disclosed). (2) Transfer of the Loader Program Starting with transfer from the respective first locations, the 8-KB loader program is transferred from serial flash memory, which is connected to channel 0 of the Renesas serial peripheral interface, to high-speed on-chip RAM. Transfer proceeds at 1/4 of the rate of the bus clock (B). Once transfer of the loader program has been completed, execution by the CPU jumps to highspeed on-chip RAM so that it can start executing the transferred loader program. (3) Transfer of an Application Program (as Desired) The loader program employs the Renesas serial peripheral interface to transfer the data to be deployed from serial flash memory to on-chip RAM or external RAM. Page 96 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 4 Boot Mode Figure 4.1 is a schematic view of the specification for boot mode 1. This LSI (1) Program execution Read request On-chip ROM for boot initiation (not publicly disclosed) High-speed on-chip RAM H'FFF8 0000 H'FFF8 1FFF Loader program (8 KB) Renesas serial peripheral interface Channel 0* Read Serial flash memory Loader program (8 KB) (2) Loading into high-speed on-chip RAM Read Read request (3) Loading into external or on-chip RAM On-chip RAM Application program External RAM Application program Application program Note: * Only PF3 to PF0 are available. Figure 4.1 Schematic View of Specification for Boot Mode 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 97 of 1910 Section 4 Boot Mode 4.4 Notes 4.4.1 Boot Related Pins SH726A Group, SH726B Group The initial states and output states in deep standby mode of the pins related to CS0 space memory read and channel 0 of the Renesas serial peripheral interface are different in each boot mode. For details, refer to section 10, Bus State Controller, section 31, General Purpose I/O Ports, and section 32, Power-Down Modes. Page 98 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 5 Clock Pulse Generator Section 5 Clock Pulse Generator This LSI has a clock pulse generator that generates a CPU clock (I), a peripheral clock (P), and a bus clock (B). The clock pulse generator consists of a crystal oscillator, PLL circuits, and divider circuits. 5.1 Features  Two clock operating modes The mode is selected from among the two clock operating modes based on the frequency range to be used.  Three clocks generated independently A CPU clock (I) for the CPU and cache; a peripheral clock (P) for the on-chip peripheral modules; a bus clock (B = CKIO) for the external bus interface  Frequency change function CPU and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuits and divider circuits within this module. Frequencies are changed by software using frequency control register (FRQCR) settings.  Power-down mode control The clock can be stopped in sleep mode, software standby mode, and deep standby mode, and specific modules can be stopped using the module standby function. For details on clock control in the power-down modes, see section 32, Power-Down Modes. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 99 of 1910 SH726A Group, SH726B Group Section 5 Clock Pulse Generator Figure 5.1 shows a block diagram of the clock pulse generator. On-chip oscillator circuit Divider 2 Divider 1 x 1/1 x 1/4 x1 PLL circuit (x18) x 1/3 x 1/6 x 1/12 XTAL CPU clock (Iφ Max: 216 MHz) Crystal oscillator Peripheral clock (Pφ Max: 36 MHz) Bus clock (Bφ = CKIO Max: 72 MHz) EXTAL CKIO Control unit MD_CLK Clock frequency control circuit Standby control circuit FRQCR Bus interface [Legend] FRQCR: Frequency control register Peripheral bus Figure 5.1 Block Diagram Page 100 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 5 Clock Pulse Generator The blocks of this module function as follows: (1) Crystal Oscillator The crystal oscillator is used in which the crystal resonator is connected to the XTAL/EXTAL pin. (2) Divider 1 Divider 1 divides the output from the crystal oscillator or the external clock input. The division ratio depends on the clock operating mode. (3) PLL Circuit PLL circuit multiplies the frequency of the output from the divider 1. The multiplication ratio depends on the clock operating mode. (4) Divider 2 Divider 2 generates a clock signal whose operating frequency can be used for the CPU clock, the peripheral clock, and the bus clock. The division ratio of the CPU clock and the peripheral clock is set by the frequency control register. The division ratio of the bus clock is fixed. (5) Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency using the MD_CLK pin and the frequency control register (FRQCR). (6) Standby Control Circuit The standby control circuit controls the states of the on-chip oscillation circuit and other modules during clock switching, or sleep, software standby or deep standby mode. In addition, the standby control register is provided to control the power-down mode of other modules. For details on the standby control register, see section 32, Power-Down Modes. (7) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode and the frequency division ratio of the CPU clock and the peripheral clock (P). R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 101 of 1910 SH726A Group, SH726B Group Section 5 Clock Pulse Generator 5.2 Input/Output Pins Table 5.1 lists the clock pulse generator pins and their functions. Table 5.1 Pin Configuration and Functions of the Clock Pulse Generator Pin Name I/O Function Mode control pin MD_CLK Input Sets the clock operating mode. Crystal XTAL input/output pins (clock input pins) EXTAL Output Connected to the crystal resonator. (Leave this pin open when the crystal resonator is not in use.) Clock output pin Output Clock output pin. Page 102 of 1910 Symbol CKIO Input Connected to the crystal resonator or used to input external clock. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 5.3 Section 5 Clock Pulse Generator Clock Operating Modes Table 5.2 shows the relationship between the mode control pin (MD_CLK) and the clock operating modes. Table 5.3 shows the usable frequency ranges in the clock operating modes. Table 5.2 Clock Operating Modes Pin Values Clock I/O PLL Circuit On/Off CKIO Frequency 1 ON (18) (EXTAL or crystal resonator)  6 1/4 ON (18) (EXTAL or crystal resonator)  3/2 Mode MD_CLK Source Output Divider 1 0 0 EXTAL or crystal resonator CKIO 1 1 EXTAL or crystal resonator CKIO  Mode 0 In mode 0, clock is input from the EXTAL pin or the crystal oscillator. The PLL circuit shapes waveforms and multiples the frequency, and then supplies the clock to the LSI. The oscillating frequency for the crystal resonator and EXTAL pin input clock ranges from 10 to 12 MHz. The frequency range of CKIO is from 60 to 72 MHz.  Mode 1 In mode 1, clock is input from the EXTAL pin or the crystal oscillator. The PLL circuit shapes waveforms and multiples the frequency, and then supplies the clock to the LSI. The oscillating frequency for the crystal resonator and EXTAL pin input clock is 48MHz. The frequency of CKIO is 72 MHz. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 103 of 1910 SH726A Group, SH726B Group Section 5 Clock Pulse Generator Table 5.3 Relationship between Clock Operating Mode and Frequency Range Selectable Frequency Range (MHz) Ratio of Internal Clock Clock PLL Frequencies Output Clock (CKIO CPU clock Bus Clock Peripheral Mode 2 Setting*1 Frequency Multiplier (I:B:P)* Clock*3 Pin) (I) (B) Clock (P) 0 H'x004 ON (×18) 18 : 6 : 3 10 to 12 60 to 72 180 to 216 60 to 72 30 to 36 H'x006 ON (×18) 18 : 6 : 3/2 10 to 12 60 to 72 180 to 216 60 to 72 15 to 18 H'x024 ON (×18) 6:6:3 10 to 12 60 to 72 60 to 72 60 to 72 30 to 36 H'x026 ON (×18) 6 : 6 : 3/2 10 to 12 60 to 72 60 to 72 60 to 72 15 to 18 H'x004 ON (×18) 9/2 : 3/2 : 3/4 48 72 216 72 36 H'x006 ON (×18) 9/2 : 3/2 : 3/8 48 72 216 72 18 H'x024 ON (×18) 3/2 : 3/2 : 3/4 48 72 72 72 36 H'x026 ON (×18) 3/2 : 3/2 : 3/8 48 72 72 72 18 Operating FRQCR 1 Notes: Caution: Input 1. x in the FRQCR register setting depends on the set value in bits 12, 13, and 14. 2. The ratio of clock frequencies, where the input clock frequency is assumed to be 1. 3. The frequency of the EXTAL pin input clock or the crystal resonator Do not use this LSI for frequency settings other than those in table 5.3. Page 104 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 5.4 Section 5 Clock Pulse Generator Register Descriptions Table 5.4 shows the register configuration of the clock pulse generator. Table 5.4 Register Configuration Register Name Abbreviation R/W Initial Value Address Frequency control register FRQCR R/W H'0024 H'FFFE0010 16 5.4.1 Access Size Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin during normal operation mode, change of gain of crystal oscillator for the XTAL pin, software standby mode, and standby mode cancellation. The register specifies the frequency division ratio for the CPU clock and peripheral clock (P). FRQCR is accessed by word. Bit: Initial value: R/W: 15 14 13 - CKO EN2 CKOEN[1:0] 12 0 R 0 R/W 0 R/W 0 R/W 11 10 9 8 7 6 5 4 3 - - - - - - IFC - - 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R 0 R Bit Bit Name Initial Value R/W Description 15  0 R Reserved 2 1 0 PFC[2:0] 1 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 14 CKOEN2 0 R/W Clock Output Enable 2 Specifies whether the CKIO pin outputs clock signals or is fixed to the low level when the gain of the crystal oscillator for the XTAL pin is changed. If this bit is set to 1, the CKIO pin is fixed to the low level when the gain of the crystal oscillator for the XTAL pin is changed. Therefore, the malfunction of an external circuit caused by an unstable CKIO clock while changing the gain of the crystal oscillator for the XTAL pin can be prevented. 0: Unstable clock output 1: Low-level output R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 105 of 1910 SH726A Group, SH726B Group Section 5 Clock Pulse Generator Initial Value Bit Bit Name 13, 12 CKOEN[1:0] 00 R/W Description R/W Clock Output Enable Specifies whether the CKIO pin outputs clock signals, or is set to a fixed level or high impedance (Hi-Z) during normal operation mode, standby mode, or cancellation of standby mode. If these bits are set to 01, the CKIO pin is fixed at low during software standby mode or cancellation of software standby mode. Therefore, the malfunction of an external circuit caused by an unstable CKIO clock during cancellation of software standby mode can be prevented. 11 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 IFC 1 R/W CPU clock Frequency Division Ratio This bit specifies the frequency division ratio of the CPU clock with respect to the output frequency of PLL circuit. 0: 1 time 1: 1/3 times 4, 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 PFC[2:0] 100 R/W Peripheral Clock Frequency Division Ratio These bits specify the frequency division ratio of the peripheral clock with respect to the output frequency of PLL circuit. 000: Reserved (setting prohibited) 001: Reserved (setting prohibited) 010: Reserved (setting prohibited) 011: Reserved (setting prohibited) 100: 1/6 times 101: Reserved (setting prohibited) 110: 1/12 times 111: Reserved (setting prohibited) Page 106 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Table 5.5 Section 5 Clock Pulse Generator CKOEN[1:0] Settings Setting Normal Operation Software Standby Mode Deep Standby Mode* 00 Output Output off (Hi-Z) Output off (Hi-Z) 01 Output Low-level output Low-level output 10 Output Output (unstable clock output) Low-level or high-level output 11 Output off (Hi-Z) Output off (Hi-Z) Output off (Hi-Z) Note: * When deep standby mode is canceled, the head of the first output CKIO clock pulse may be missed. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 107 of 1910 Section 5 Clock Pulse Generator 5.5 SH726A Group, SH726B Group Changing the Frequency The frequency of the CPU clock (I) and peripheral clock (P) can be changed by changing the division rate of divider. The division rate can be changed by software through the frequency control register (FRQCR). 5.5.1 Changing the Division Ratio The division rate of divider can be changed by the following operation. 1. In the initial state, IFC  B'1 and PFC2 to PFC0  B'100. 2. Set the desired value in the IFC and PFC2 to PFC0 bits. Note that if the wrong value is set, this LSI will malfunction. 3. After the register bits (IFC and PFC2 to PFC0) have been set, the clock is supplied of the new division ratio. Note: When executing the SLEEP instruction after the frequency has been changed, be sure to read the frequency control register (FRQCR) three times before executing the SLEEP instruction. Page 108 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 5.6 Section 5 Clock Pulse Generator Usage of the Clock Pins For the connection of a crystal resonator or the input of a clock signal, this LSI circuit has the pins listed in table 5.6. With regard to these pins, take care on the following points. Furthermore, Xin pin and Xout pin are used in this section to refer to the pins listed in the table. Table 5.6 Clock Pins Xin Pins (Used for Connection of a Crystal Resonator Xout Pins and Input of External Clock Signals) (Used for Connection of a Crystal Resonator) EXTAL XTAL AUDIO_X1 AUDIO_X2 RTC_X1 RTC_X2 5.6.1 In the Case of Inputting an External Clock An example of the connection of an external clock is shown in figure 5.2. In cases where the Xout pin is left open state, take the parasitic capacitance as less than 10 pF. This LSI External clock input Xin Open state Xout Figure 5.2 Example of the Connection of an External Clock R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 109 of 1910 SH726A Group, SH726B Group Section 5 Clock Pulse Generator 5.6.2 In the Case of Using a Crystal Resonator An example of the connection of crystal resonator is shown in figure 5.3. Place the crystal resonator and capacitors (CL1 and CL2) as close to pins Xin and Xout as possible. Furthermore, to avoid inductance so that oscillation is correct, use the points where the capacitors are connected to the crystal resonator in common and do not place wiring patterns close to these components. Since the design of the user board is closely connected with the effective characteristics of the crystal resonator, refer to the example of connection of the crystal resonator that is introduced in this section and perform thorough evaluation on the user side as well. The rated value of the crystal resonator will vary with the floating capacitances and so on of the crystal resonator and mounted circuit, so proceed with decisions on the basis of full discussions with the maker of the crystal resonator. Ensure that voltages applied to the clock pins do not exceed the maximum rated values. Although the feedback resistor is included in this LSI, an external feedback resistor may be required in some cases. This depends on the characteristics of the crystal resonator. Set the parameters (of resistors and capacitors) with thorough evaluation on the user side. This LSI CL1 Xin Crystal resonator CL2 ROF RIF Xout ROD RID To internal sections Figure 5.3 Example of the Connection of a Crystal Resonator 5.6.3 In the Case of Not Using the Clock Pin In cases where the pins are not in use, fix the level on the Xin pin (pull it up or down, or connect it to the power-supply or ground level), and leave the Xout pin open state. Page 110 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 5 Clock Pulse Generator 5.7 Oscillation Stabilizing Time 5.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator In the case of using a crystal resonator, please wait longer than the oscillation stabilizing time at the following cases, to keep the oscillation stabilizing time of the on-chip crystal oscillator (In the case of inputting an external clock input, it is not necessary).  Power on  Releasing the software standby mode or deep standby mode by RES pin  Changing from halting oscillation to running oscillation by power-on reset or register setting (AUDIO_X1, RTC_X1)  Changing the gain of the on-chip crystal oscillator by RES pin (EXTAL) 5.7.2 Oscillation Stabilizing Time of the PLL circuit In clock modes 0 and 1, the clock from EXTAL is supplied to the PLL circuit. So, regardless of whether using a crystal resonator or inputting an external clock from EXTAL, please wait longer than the oscillation stabilizing time at the following cases, to keep the oscillation stabilizing time of the PLL circuit.  Power on (in the case of using the crystal resonator)/start inputting external clock (in the case of inputting the external clock)  Releasing the software standby mode or deep standby mode by RES pin [Remarks] The oscillation stabilizing time is kept by the counter running in the LSI at the following cases.  Releasing the software standby mode or deep standby mode by the other than RES pin  Changing the gain of the on-chip crystal oscillator by the register setting (EXTAL) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 111 of 1910 SH726A Group, SH726B Group Section 5 Clock Pulse Generator 5.8 Notes on Board Design 5.8.1 Note on Using a PLL Oscillation Circuit In the PLLVcc and Vss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interferences. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pins and the digital power supply pins Vcc and PVcc should not supply the same resources on the board if at all possible. Signal lines prohibited Power supply PLLVcc Vcc Vss Vss Figure 5.4 Note on Using a PLL Oscillation Circuit Page 112 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 6 Exception Handling Section 6 Exception Handling 6.1 Overview 6.1.1 Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 6.1 shows their priorities. When several exception handling sources occur at once, they are processed according to the priority shown. Table 6.1 Types of Exception Handling and Priority Order Type Exception Handling Priority Reset Power-on reset High Manual reset Address error CPU address error DMA address error Instruction FPU exception Integer division exception (division by zero) Integer division exception (overflow) Register Bank underflow bank error Bank overflow Interrupt NMI User break User debugging interface IRQ PINT R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Low Page 113 of 1910 SH726A Group, SH726B Group Section 6 Exception Handling Type Exception Handling Priority Instruction Trap instruction (TRAPA instruction) High General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed 1 branch instruction* (including FPU instructions and FPU-related CPU instructions in FPU module standby state), instructions that rewrite the 2 3 PC* , 32-bit instructions* , RESBANK instruction, DIVS instruction, and DIVU instruction) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N. 3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. 6.1.2 Exception Handling Operations The exception handling sources are detected and start processing according to the timing shown in table 6.2. Table 6.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Timing of Source Detection and Start of Handling Reset Power-on reset Starts when the RES pin changes from low to high, when the user debugging interface reset negate command is set after the user debugging interface reset assert command has been set, or when the watchdog timer overflows. Manual reset Starts when the watchdog timer overflows. Address error Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Interrupts Register bank Bank underflow error Bank overflow Page 114 of 1910 Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. In the state where saving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the interrupt controller is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 6 Exception Handling Exception Source Timing of Source Detection and Start of Handling Instructions Trap instruction Starts from the execution of a TRAPA instruction. General illegal instructions Starts from the decoding of undefined code anytime except immediately after a delayed branch instruction (delay slot) (including FPU instructions and FPU-related CPU instructions in FPU module standby state). Slot illegal instructions Starts from the decoding of undefined code placed directly after a delayed branch instruction (delay slot) (including FPU instructions and FPU-related CPU instructions in FPU module standby state), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Integer division exceptions Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value (H'80000000) by 1. FPU exceptions Starts when detecting invalid floating point operation exception defined by IEEE standard 754, division-by-zero exception, overflow, underflow, or inexact exception. Instructions Also starts when qNaN or  is input to the source for a floating point operation instruction when the QIS bit in FPSCR is set. When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 6.1.3, Exception Handling Vector Table, for more information. The vector base register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of the interrupt controller is also initialized to 0. The floating point status/control register (FPSCR) is initialized to H'00040001 by a power-on reset. The program begins running from the PC address fetched from the exception handling vector table. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 115 of 1910 Section 6 Exception Handling (2) SH726A Group, SH726B Group Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts, and Instructions SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling other than NMI and user break with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved to the register banks. In the case of exception handling due to address errors, register bank errors, NMI interrupts, user break interrupts, or instructions, saving to a register bank is not performed. When saving is performed to all register banks, automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the interrupt controller is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the interrupt controller is 1), register bank overflow exception will be generated. In the case of interrupt exception handling, the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start address is then fetched from the exception handling vector table and the program begins running from that address. 6.1.3 Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception handling, the start addresses of the exception service routines are fetched from the exception handling vector table, which is indicated by this vector table address. Page 116 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 6 Exception Handling Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector table addresses are calculated. Table 6.3 Exception Handling Vector Table Vector Numbers Vector Table Address Offset PC 0 H'00000000 to H'00000003 SP 1 H'00000004 to H'00000007 PC 2 H'00000008 to H'0000000B SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved by system) 5 H'00000014 to H'00000017 Exception Sources Power-on reset Manual reset Slot illegal instruction 6 H'00000018 to H'0000001B (Reserved by system) 7 H'0000001C to H'0000001F 8 H'00000020 to H'00000023 CPU address error 9 H'00000024 to H'00000027 DMA address error 10 H'00000028 to H'0000002B NMI 11 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 13 H'00000034 to H'00000037 Interrupts FPU exception User debugging interface 14 H'00000038 to H'0000003B Bank overflow 15 H'0000003C to H'0000003F Bank underflow 16 H'00000040 to H'00000043 Integer division exception (division by zero) 17 H'00000044 to H'00000047 Integer division exception (overflow) 18 H'00000048 to H'0000004B (Reserved by system) 19 H'0000004C to H'0000004F : Trap instruction (user vector) H'0000007C to H'0000007F 32 H'00000080 to H'00000083 : 63 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 : 31 : H'000000FC to H'000000FF Page 117 of 1910 SH726A Group, SH726B Group Section 6 Exception Handling Exception Sources External interrupts (IRQ, PINT), on-chip peripheral module interrupts* Vector Numbers Vector Table Address Offset 64 H'00000100 to H'00000103 : 511 Note: * Table 6.4 : H'000007FC to H'000007FF The vector numbers and vector table address offsets for each external interrupt and onchip peripheral module interrupt are given in table 7.4 in section 7, Interrupt Controller. Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number)  4 Address errors, register bank errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number)  4 Notes: 1. Vector table address offset: See table 6.3. 2. Vector number: See table 6.3. Page 118 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.2 Resets 6.2.1 Input/Output Pins Section 6 Exception Handling Table 6.5 shows the pin configuration. Table 6.5 Pin Configuration Pin Name Symbol I/O Function Power-on reset RES Input When this pin is driven low, this LSI shifts to the poweron reset processing 6.2.2 Types of Reset A reset is the highest-priority exception handling source. There are two kinds of reset, power-on and manual. As shown in table 6.6, the CPU state is initialized in both a power-on reset and a manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip peripheral module registers except a few registers are also initialized by a power-on reset, but not by a manual reset. Table 6.6 Reset States Conditions for Transition to Reset State Internal States On-Chip Large- Watchdog User Debugging Type RES Interface Command Power- Low  On-Chip Timer Retention Modules RAM RAM Overflow CPU  Initialized Initialized Initialized or Initialized or  Retention RAM) Retained Retained contents*2 contents*3 contents*4, *5 Initialized Initialized Initialized or Initialized or command is set contents* interface reset assert is 2 Power-on reset Initialized * 1 Initialized or Retained Retained user debugging Data High-Speed On-Chip Data interface reset assert High Command other than On-Chip (Excluding Other on reset High User debugging Capacity RAM Initialized or Retained Retained contents*3 contents*4 Initialized or Initialized or Initialized or Retained Retained Retained contents*2 contents*3 contents*4 set R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 119 of 1910 SH726A Group, SH726B Group Section 6 Exception Handling Conditions for Transition to Reset State Internal States On-Chip Large- Watchdog User Debugging Type Manual RES Interface Command High Command other than reset user debugging On-Chip Timer Overflow Manual reset CPU Capacity RAM On-Chip (Excluding Data Other High-Speed On-Chip Data Retention Modules RAM Retention RAM) RAM Retained Retained contents Retained 1 Initialized * contents contents interface reset assert is set Notes: 1. 2. 3. 4. See section 34.3, Register States in Each Operating Mode. Data are retained when the setting of either the RAME or RAMWE bit is disabled. Data are retained when the setting of either the VRAME or VRAMWE bit is disabled. Data are retained when the setting of any of the VRAME, VRAMWE, or RRAMWE bits is disabled. 5. When the deep standby mode is canceled by a power-on reset, the data cannot be retained. Page 120 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.2.3 (1) Section 6 Exception Handling Power-On Reset Power-On Reset by Means of RES Pin When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc when the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip peripheral module registers are initialized. See section 36.1, Pin States, for the status of individual pins during the power-on reset state. In the power-on reset state, power-on reset exception handling starts when the RES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of the interrupt controller is also initialized to 0. FPSCR is initialized to H'00040001 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. (2) Power-On Reset by Means of User Debugging Interface Reset Assert Command When the user debugging interface reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of the user debugging interface reset assert command is equivalent to power-on reset by means of the RES pin. Setting the user debugging interface reset negate command cancels the power-on reset state. The time required between the user debugging interface reset assert command and the user debugging interface reset negate command is the same as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state generated by the user debugging interface reset assert command, setting the user debugging interface reset negate command starts power-on reset exception handling. The CPU operates in the same way as when a power-on reset was caused by the RES pin. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 121 of 1910 Section 6 Exception Handling (3) SH726A Group, SH726B Group Power-On Reset Initiated by Watchdog Timer When a setting is made for a power-on reset to be generated in watchdog timer mode of the watchdog timer, and WTCNT of the watchdog timer overflows, this LSI enters the power-on reset state. In this case, WRCSR of the watchdog timer and FRQCR of the clock pulse generator are not initialized by the reset signal generated by the watchdog timer. If a reset caused by the RES pin or the user debugging interface reset assert command occurs simultaneously with a reset caused by watchdog timer overflow, the reset caused by the RES pin or the user debugging interface reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the watchdog timer, the CPU operates in the same way as when a power-on reset was caused by the RES pin. 6.2.4 (1) Manual Reset Manual Reset Initiated by Watchdog Timer When a setting is made for a manual reset to be generated in watchdog timer mode of the watchdog timer, and WTCNT of the watchdog timer overflows, this LSI enters the manual reset state. When manual reset exception processing is started by the watchdog timer, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of interrupt controller is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Page 122 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 6 Exception Handling Note in Manual Reset When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs during burst transfer by the direct memory access controller, manual reset exception handling will be deferred until the CPU acquires the bus. The CPU and the BN bit in IBNR of the interrupt controller are initialized by a manual reset. The FPU and other modules are not initialized. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 123 of 1910 SH726A Group, SH726B Group Section 6 Exception Handling 6.3 Address Errors 6.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 6.7. Table 6.7 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Data read/write Bus Master Bus Cycle Description Address Errors CPU Instruction fetched from even address None (normal) Instruction fetched from odd address Address error occurs Instruction fetched from other than on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* None (normal) Instruction fetched from on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Address error occurs Word data accessed from even address None (normal) Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs CPU or direct memory access controller Double longword data accessed from double None (normal) longword boundary Note: * Double longword data accessed from other than double longword boundary Address error occurs Byte or word data accessed in on-chip peripheral module space* None (normal) Longword data accessed in 16-bit on-chip peripheral module space* None (normal) Longword data accessed in 8-bit on-chip peripheral module space* None (normal) See section 10, Bus State Controller, for details of the on-chip peripheral module space and on-chip RAM space. Page 124 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.3.2 Section 6 Exception Handling Address Error Exception Handling When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the address error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 6.4 Register Bank Errors 6.4.1 Register Bank Error Sources (1) Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the interrupt controller is set to 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. (2) Bank Underflow Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving has not been performed to register banks. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 125 of 1910 Section 6 Exception Handling 6.4.2 SH726A Group, SH726B Group Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a bank overflow, and the start address of the executed RESBANK instruction for a bank underflow. To prevent multiple interrupts from occurring at a bank overflow, the priority level of the interrupt that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 6.5 Interrupts 6.5.1 Interrupt Sources The sources that start interrupt exception handling are divided into NMI, user break, user debugging interface, IRQ, PINT, and on-chip peripheral modules. Each interrupt source is allocated a different vector number and vector table offset. See table 7.4 in section 7, Interrupt Controller, for more information on vector numbers and vector table address offsets. Page 126 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.5.2 Section 6 Exception Handling Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller determines their relative priorities and starts exception handling according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of user break and user debugging interface interrupts is 15. Priority levels of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt priority registers 01, 02, and 05 to 22 (IPR01, IPR02, and IPR05 to IPR22) of the interrupt controller as shown in table 6.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 7.3.1, Interrupt Priority Registers 01, 02, 05 to 22 (IPR01, IPR02, IPR05 to IPR22), for details of IPR01, IPR02, and IPR05 to IPR22. Table 6.8 Interrupt Priority Order Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. User debugging interface 15 Fixed priority level. IRQ 0 to 15 Set with interrupt priority registers 01, 02, and 05 to 22 (IPR01, IPR02, and IPR05 to IPR22). PINT On-chip peripheral module R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 127 of 1910 Section 6 Exception Handling 6.5.3 SH726A Group, SH726B Group Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR). When an interrupt is accepted, interrupt exception handling begins. In interrupt exception handling, the CPU fetches the exception service routine start address which corresponds to the accepted interrupt from the exception handling vector table, and saves SR and the program counter (PC) to the stack. In the case of interrupt exception handling other than NMI and user break with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved in the register banks. In the case of exception handling due to address errors, NMI interrupts, user break interrupts, or instructions, saving is not performed to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the interrupt controller is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the interrupt controller is 1), register bank overflow exception occurs. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. See section 7.6, Operation, for further details of interrupt exception handling. Page 128 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 6 Exception Handling 6.6 Exceptions Triggered by Instructions 6.6.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, integer division exceptions, and FPU exceptions, as shown in table 6.9. Table 6.9 Types of Exceptions Triggered by Instructions Type Source Instruction Trap instruction TRAPA Slot illegal instructions Undefined code placed immediately after a delayed branch instruction (delay slot) (including FPU instructions and FPU-related CPU instructions in FPU module standby state), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. General illegal instructions Undefined code anywhere besides in a delay slot (including FPU instructions and FPU-related CPU instructions in FPU module standby state) Integer division exceptions Division by zero DIVU, DIVS Negative maximum value  (1) DIVS FPU exceptions Starts when detecting invalid FADD, FSUB, FMUL, FDIV, FMAC, operation exception defined by FCMP/EQ, FCMP/GT, FLOAT, FTRC, IEEE754, division-by-zero FCNVDS, FCNVSD, FSQRT exception, overflow, underflow, or inexact exception. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 129 of 1910 Section 6 Exception Handling 6.6.2 SH726A Group, SH726B Group Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 6.6.3 Slot Illegal Instructions An instruction placed immediately after a delayed branch instruction is called the “instruction placed in a delay slot”. When the instruction placed in the delay slot is undefined code (including FPU instructions and FPU-related CPU instructions in FPU module standby state), an instruction that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot illegal exception handling starts when such kind of instruction is decoded. When the FPU has entered a module standby state, the floating point operation instruction and FPU-related CPU instructions are handled as undefined codes. If these instructions are placed in a delay slot and then decoded, a slot illegal instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code, the instruction that rewrites the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Page 130 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.6.4 Section 6 Exception Handling General Illegal Instructions When an undefined code, including FPU instructions and FPU-related CPU instructions in FPU module standby state, placed anywhere other than immediately after a delayed branch instruction, i.e., in a delay slot, is decoded, general illegal instruction exception handling starts. When the FPU has entered a module standby state, the floating point instruction and FPU-related CPU instructions are handled as undefined codes. If these instructions are placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) and then decoded, general illegal instruction exception handling starts. In general illegal instruction exception handling, the CPU handles general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot illegal instructions, however, the program counter value stored is the start address of the undefined code. 6.6.5 Integer Division Exceptions When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception are DIVU and DIVS. The only source instruction of overflow exception is DIVS, and overflow exception occurs only when the negative maximum value is divided by 1. The CPU operates as follows: 1. The exception service routine start address which corresponds to the integer division exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the integer division instruction at which the exception occurred. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 131 of 1910 Section 6 Exception Handling 6.6.6 SH726A Group, SH726B Group FPU Exceptions An FPU exception handling is generated when the V, Z, O, U or I bit in the FPU exception enable field (Enable) of the floating point status/control register (FPSCR) is set. This indicates the occurrence of an invalid operation exception defined by the IEEE standard 754, a division-by-zero exception, overflow (in the case of an instruction for which this is possible), underflow (in the case of an instruction for which this is possible), or inexact exception (in the case of an instruction for which this is possible). The floating point operation instructions that may cause an FPU exception handling are FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and FSQRT. An FPU exception handling is generated only when the corresponding FPU exception enable bit (Enable) is set. When the FPU detects an exception source in floating point operation, FPU operation is halted and generation of an FPU exception handling is reported to the CPU. When exception handling is started, the CPU operations are as follows. 1. The start address of the exception service routine which corresponds to the FPU exception handling that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. This jump is not a delayed branch. The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an FPU exception handling has been accepted, and remains set until explicitly cleared by the user through an instruction. The FPU exception source field (Cause) of FPSCR changes each time a floating point operation instruction is executed. When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in FPSCR is also set, FPU exception handling is generated when qNAN or  is input to a floating point operation instruction source. Page 132 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.7 Section 6 Exception Handling When Exception Sources Are Not Accepted When an address error, FPU exception, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 6.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 6.10 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction* Note: * 6.8 Address Error Floating-Point Unit Register Bank Exception Error (Overflow) Interrupt Not accepted Not accepted Not accepted Not accepted Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 6.11. Table 6.11 Stack Status after Exception Handling Ends Exception Type Stack Status Address error SP Address of instruction after executed instruction 32 bits SR 32 bits Address of instruction after executed instruction 32 bits SR 32 bits Interrupt SP R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 133 of 1910 SH726A Group, SH726B Group Section 6 Exception Handling Exception Type Stack Status Register bank error (overflow) SP Address of instruction after executed instruction 32 bits SR 32 bits Start address of relevant RESBANK instruction 32 bits SR 32 bits Address of instruction after TRAPA instruction 32 bits SR 32 bits Jump destination address of delayed branch instruction 32 bits SR 32 bits Start address of general illegal instruction 32 bits SR 32 bits Start address of relevant integer division instruction 32 bits SR 32 bits Address of instruction after executed instruction 32 bits SR 32 bits Register bank error (underflow) SP Trap instruction SP Slot illegal instruction SP General illegal instruction SP Integer division exception SP FPU exception SP Page 134 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 6.9 Usage Notes 6.9.1 Value of Stack Pointer (SP) Section 6 Exception Handling The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 6.9.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.) and address error exception handling will start up as soon as the first exception handling is ended. Address errors will then also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 135 of 1910 Section 6 Exception Handling 6.9.4 SH726A Group, SH726B Group Note before Exception Handling Begins Running Before exception handling begins running, the exception handling vector table must be stored in a memory, and the CPU must be able to access the memory. So, if the exception handling is generated  Ex. 1: when the exception handling vector table is stored in an external address space, but the settings of bus state controller and general I/O ports to access the external address space have been not completed yet, or  Ex. 2: when the exception handling vector table is stored in the on-chip RAM, but the vector base register (VBR) has been not changed to the on-chip RAM address yet, the CPU fetches an unintended value as the execution start address, and starts executing programs from unintended address. (1) Manual Reset Before the settings necessary to access the external CS0 space are completed, the manual reset should not be generated. When a manual reset is generated, the CPU fetches the execution start address from the location at the offset for the manual reset (H'00000008) in the vector table, that is, always from the external CS0 space. Additionally, in the case that no memory is connected to the external CS0 space in boot mode 1, the manual reset should not be generated. (2) NMI Interrupt Before the exception handling vector table is stored in a memory and the settings necessary to access the memory are completed, the settings to permit the interrupts should not be done. Specially in boot mode 1, the VBR is kept as the initial value H'00000000 in the period of the boot operation (before the transfer of the loader program is completed and the CPU jumps to the onchip high-speed RAM). Before the VBR is changed or the settings necessary to access the external address space are completed in the loader program, the settings to permit the interrupts should not be done. (3) Interrupts Other Than NMI Before the exception handling vector table is stored in a memory and the settings necessary to access the memory are completed, the settings to permit the interrupts should not be done. Page 136 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (4) Section 6 Exception Handling The Other Exceptions Before the exception handling vector table is stored in a memory and the settings necessary to access the memory are completed, the exception handling should not be generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 137 of 1910 Section 6 Exception Handling Page 138 of 1910 SH726A Group, SH726B Group R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Section 7 Interrupt Controller The interrupt controller ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The interrupt controller registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 7.1 Features  16 levels of interrupt priority can be set. By setting the 20 interrupt priority registers, the priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request sources.  NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as the noise canceler function.  Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 139 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Figure 7.1 shows a block diagram. NMI IRQ7 to IRQ0 PINT7 to PINT0 User break Direct memory access controller USB 2.0 host/function module Compare match timer Bus state controller Watchdog timer Multi-function timer pulse unit 2 A/D converter Renesas SPDIF interface Serial sound interface I2C bus interface 3 Serial communication interface with FIFO Serial I/O with FIFO Renesas serial peripheral interface Controller area network IEBusTM controller CD-ROM decoder SD host interface Realtime clock Sampling rate converter Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) Comparator SR I3 I2 I1 I0 CPU Priority identifier ICR0 ICR1 ICR2 IRQRR PINTER PIRR IBCR IBNR IPR IPR01, IPR02, IPR05 to IPR22 Bus interface Interrupt controller Peripheral bus Module bus [Legend] ICR0: ICR1: ICR2: IRQRR: PINTER: PIRR: IBCR: IBNR: IPR01, IPR02, IPR05 to IPR22: Interrupt request Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 IRQ interrupt request register PINT interrupt enable register PINT interrupt request register Bank control register Bank number register Interrupt priority registers 01, 02, 05 to 22 Figure 7.1 Block Diagram Page 140 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.2 Section 7 Interrupt Controller Input/Output Pins Table 7.1 shows the pin configuration. Table 7.1 Pin Configuration Pin Name Symbol I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt request input pins IRQ7 to IRQ0 Input Input of maskable interrupt request signals PINT7 to PINT0 Input R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 141 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3 Register Descriptions Table 7.2 shows the register configuration. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 7.2 Register Configuration Address Access Size H'FFFE0800 16, 32 H'0000 H'FFFE0802 16, 32 H'0000 H'FFFE0804 16, 32 H'0000 H'FFFE0806 16, 32 Register Name Abbreviation R/W Initial Value Interrupt control register 0 ICR0 R/W * Interrupt control register 1 ICR1 R/W Interrupt control register 2 ICR2 R/W IRQ interrupt request register IRQRR PINT interrupt enable register PINTER R/W H'0000 H'FFFE0808 16, 32 PINT interrupt request register PIRR R H'0000 H'FFFE080A 16, 32 Bank control register IBCR R/W H'0000 H'FFFE080C 16, 32 Bank number register IBNR R/W H'0000 H'FFFE080E 16, 32 Interrupt priority register 01 IPR01 R/W H'0000 H'FFFE0818 16, 32 Interrupt priority register 02 IPR02 R/W H'0000 H'FFFE081A 16, 32 Interrupt priority register 05 IPR05 R/W H'0000 H'FFFE0820 16, 32 Interrupt priority register 06 IPR06 R/W H'0000 H'FFFE0C00 16, 32 Interrupt priority register 07 IPR07 R/W H'0000 H'FFFE0C02 16, 32 Interrupt priority register 08 IPR08 R/W H'0000 H'FFFE0C04 16, 32 Interrupt priority register 09 IPR09 R/W H'0000 H'FFFE0C06 16, 32 Interrupt priority register 10 IPR10 R/W H'0000 H'FFFE0C08 16, 32 Interrupt priority register 11 IPR11 R/W H'0000 H'FFFE0C0A 16, 32 Interrupt priority register 12 IPR12 R/W H'0000 H'FFFE0C0C 16, 32 Interrupt priority register 13 IPR13 R/W H'0000 H'FFFE0C0E 16, 32 Interrupt priority register 14 IPR14 R/W H'0000 H'FFFE0C10 16, 32 Interrupt priority register 15 IPR15 R/W H'0000 H'FFFE0C12 16, 32 Interrupt priority register 16 IPR16 R/W H'0000 H'FFFE0C14 16, 32 Interrupt priority register 17 IPR17 R/W H'0000 H'FFFE0C16 16, 32 Interrupt priority register 18 IPR18 R/W H'0000 H'FFFE0C18 16, 32 Interrupt priority register 19 IPR19 R/W H'0000 H'FFFE0C1A 16, 32 Page 142 of 1910 R/(W)* 2 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Register Name Abbreviation R/W Initial Value Address Access Size Interrupt priority register 20 IPR20 R/W H'0000 H'FFFE0C1C 16, 32 Interrupt priority register 21 IPR21 R/W H'0000 H'FFFE0C1E 16, 32 Interrupt priority register 22 IPR22 R/W H'0000 H'FFFE0C20 16, 32 Notes: 1. When the NMI pin is high, becomes H'8001; when low, becomes H'0001. 2. Only 0 can be written after reading 1, to clear the flag. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 143 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3.1 Interrupt Priority Registers 01, 02, 05 to 22 (IPR01, IPR02, IPR05 to IPR22) IPR01, IPR02, and IPR05 to IPR22 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. Table 7.3 shows the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR05 to IPR22. Bit: Initial value: R/W: Table 7.3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR22 Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPR01 IRQ0 IRQ1 IRQ2 IRQ3 IPR02 IRQ4 IRQ5 IRQ6 IRQ7 IPR05 PINT7 to PINT0 Reserved Reserved Reserved IPR06 Direct memory access controller channel 0 Direct memory access controller channel 1 Direct memory access controller channel 2 Direct memory access controller channel 3 IPR07 Direct memory access controller channel 4 Direct memory access controller channel 5 Direct memory access controller channel 6 Direct memory access controller channel 7 IPR08 Direct memory access controller channel 8 Direct memory access controller channel 9 Direct memory access controller channel 10 Direct memory access controller channel 11 IPR09 Direct memory access controller channel 12 Direct memory access controller channel 13 Direct memory access controller channel 14 Direct memory access controller channel 15 IPR10 USB 2.0 host/ function module Reserved Compare match timer channel 0 Compare match timer channel 1 IPR11 Bus state controller Watchdog timer Multi-function timer pulse unit 2 channel 0 (TGI0A to TGI0D) Multi-function timer pulse unit 2 channel 0 (TGI0V, TGI0E, TGI0F) IPR12 Multi-function timer pulse unit 2 channel 1 (TGI1A, TGI1B) Multi-function timer pulse unit 2 channel 1 (TGI1V, TGI1U) Multi-function timer pulse unit 2 channel 2 (TGI2A, TGI2B) Multi-function timer pulse unit 2 channel 2 (TGI2V, TGI2U) Page 144 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Register Name Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPR13 Multi-function timer pulse unit 2 channel 3 (TGI3A to TGI3D) Multi-function timer pulse unit 2 channel 3 (TGI3V) Multi-function timer pulse unit 2 channel 4 (TGI4A to TGI4D) Multi-function timer pulse unit 2 channel 4 (TGI4V) IPR14 Reserved Reserved A/D converter Renesas SPDIF interface IPR15 Serial sound Serial sound Serial sound Serial sound interface channel 0 interface channel 1 interface channel 2 interface channel 3 IPR16 I C bus interface 3 I C bus interface 3 I C bus interface 3 I C bus interface 3 channel 0 channel 1 channel 2 channel 3 IPR17 Channel 0 for serial communication interface with FIFO IPR18 Channel 4 for Reserved serial communication interface with FIFO IPR19 Serial I/O with FIFO IPR20 Controller area Controller area IEBus network channel 0 network channel 1 2 2 Channel 1 for serial communication interface with FIFO 2 2 Channel 2 for serial communication interface with FIFO Channel 3 for serial communication interface with FIFO Reserved Reserved Renesas serial Renesas serial Renesas serial peripheral peripheral peripheral interface channel 0 interface channel 1 interface channel 2 TM controller CD-ROM decoder IPR21 Reserved SD host interface Realtime clock Reserved IPR22 Sampling rate converter channel 0 Sampling rate converter channel 1 Sampling rate converter channel 2 Reserved As shown in table 7.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set. Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the highest level). R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 145 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMIL - - - - - - NMIE - - - - - - NMIF NMIM *1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W)*2 Notes: 1. 1 when the NMI pin is high, and 0 when the NMI pin is low. 2. Only 0 can be written to this bit. Bit Bit Name Initial Value R/W Description 15 NMIL * R NMI Input Level Sets the level of the signal input at the NMI pin. The NMI pin level can be obtained by reading this bit. This bit cannot be modified. 0: Low level is input to NMI pin 1: High level is input to NMI pin 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 146 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Bit Bit Name Initial Value R/W Description 1 NMIF 0 R NMI Interrupt Request This bit indicates the status of the NMI interrupt request. This bit cannot be modified. 0: NMI interrupt request has not occurred [Clearing conditions]  Cleared by changing NMIE of ICR0  Cleared by executing NMI interrupt exception handling 1: NMI interrupt request is detected [Setting condition]  0 NMIM 1 R/(W)* 2 Edge corresponding to NMIE of ICR0 has occurred at NMI pin NMI Mask Selects whether to enable interrupt request input to external interrupt input pin NMI. 0: NMI input interrupt request is enabled 1: NMI input interrupt request is masked R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 147 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 IRQ71S 0 R/W IRQ Sense Select 14 IRQ70S 0 R/W 13 IRQ61S 0 R/W These bits select whether interrupt signals corresponding to pins IRQ7 to IRQ0 are detected by a low level, falling edge, rising edge, or both edges. 12 IRQ60S 0 R/W 11 IRQ51S 0 R/W 10 IRQ50S 0 R/W 9 IRQ41S 0 R/W 8 IRQ40S 0 R/W 7 IRQ31S 0 R/W 6 IRQ30S 0 R/W 5 IRQ21S 0 R/W 4 IRQ20S 0 R/W 3 IRQ11S 0 R/W 2 IRQ10S 0 R/W 1 IRQ01S 0 R/W 0 IRQ00S 0 R/W 00: Interrupt request is detected on low level of IRQn input 01: Interrupt request is detected on falling edge of IRQn input 10: Interrupt request is detected on rising edge of IRQn input 11: Interrupt request is detected on both edges of IRQn input [Legend] n = 7 to 0 Page 148 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.3.4 Section 7 Interrupt Controller Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7 to PINT0 individually: low level or high level. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 PINT7S 0 R/W PINT Sense Select 6 PINT6S 0 R/W 5 PINT5S 0 R/W These bits select whether interrupt signals corresponding to pins PINT7 to PINT0 are detected by a low level or high level. 4 PINT4S 0 R/W 3 PINT3S 0 R/W 2 PINT2S 0 R/W 1 PINT1S 0 R/W 0 PINT0S 0 R/W 0: Interrupt request is detected on low level of PINTn input 1: Interrupt request is detected on high level of PINTn input [Legend] n = 7 to 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 149 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3.5 IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 IRQ3F 0 2 IRQ2F 0 1 IRQ1F 0 0 IRQ0F 0 R/(W)* IRQ Interrupt Request R/(W)* These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. R/(W)* Level detection: R/(W)* 0: IRQn interrupt request has not occurred R/(W)* [Clearing condition] R/(W)*  IRQn input is high 1: IRQn interrupt has occurred R/(W)* [Setting condition] R/(W)*  IRQn input is low Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions]  Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF  Cleared by executing IRQn interrupt exception handling 1: IRQn interrupt request is detected [Setting condition]  Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin [Legend] n = 7 to 0 Page 150 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.3.6 Section 7 Interrupt Controller PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit register that enables interrupt request inputs to external interrupt input pins PINT7 to PINT0. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 PINT7E PINT6E PINT5E PINT4E PINT3E PINT2E PINT1E PINT0E 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 PINT7E 0 R/W PINT Enable 6 PINT6E 0 R/W 5 PINT5E 0 R/W These bits select whether to enable interrupt request inputs to external interrupt input pins PINT7 to PINT0. 4 PINT4E 0 R/W 3 PINT3E 0 R/W 2 PINT2E 0 R/W 1 PINT1E 0 R/W 0 PINT0E 0 R/W 0: PINTn input interrupt request is disabled 1: PINTn input interrupt request is enabled [Legend] n = 7 to 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 151 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3.7 PINT Interrupt Request Register (PIRR) PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 7 PINT7R 0 R PINT Interrupt Request 6 PINT6R 0 R 5 PINT5R 0 R These bits indicate the status of the PINT7 to PINT0 interrupt requests. 4 PINT4R 0 R 3 PINT3R 0 R 2 PINT2R 0 R 1 PINT1R 0 R 0 PINT0R 0 R 0: No interrupt request at PINTn pin 1: Interrupt request at PINTn pin [Legend] n = 7 to 0 Page 152 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.3.8 Section 7 Interrupt Controller Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 E15 0 R/W Enable 14 E14 0 R/W 13 E13 0 R/W These bits enable or disable use of register banks for interrupt priority levels 15 to 1. However, use of register banks is always disabled for the user break interrupts. 12 E12 0 R/W 11 E11 0 R/W 10 E10 0 R/W 9 E9 0 R/W 8 E8 0 R/W 7 E7 0 R/W 6 E6 0 R/W 5 E5 0 R/W 4 E4 0 R/W 3 E3 0 R/W 2 E2 0 R/W 1 E1 0 R/W 0  0 R Bit: 0 0: Use of register banks is disabled 1: Use of register banks is enabled Reserved This bit is always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 153 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.3.9 Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to BN0. Bit: 15 14 BE[1:0] 0 R/W 13 12 11 10 9 8 7 6 5 4 BOVE - - - - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: 0 R/W Bit Bit Name Initial Value R/W Description 15, 14 BE[1:0] 00 R/W Register Bank Enable 3 2 1 0 BN[3:0] 0 R 0 R 0 R 0 R These bits enable or disable use of register banks. 00: Use of register banks is disabled for all interrupts. The setting of IBCR is ignored. 01: Use of register banks is enabled for all interrupts except NMI and user break. The setting of IBCR is ignored. 10: Reserved (setting prohibited) 11: Use of register banks is controlled by the setting of IBCR. 13 BOVE 0 R/W Register Bank Overflow Enable Enables of disables register bank overflow exception. 0: Generation of register bank overflow exception is disabled 1: Generation of register bank overflow exception is enabled 12 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 BN[3:0] 0000 R Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the register bank indicated by these bits, and BN is incremented by 1. After BN is decremented by 1 due to execution of a RESBANK (restore from register bank) instruction, restoration from the register bank is performed. Page 154 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.4 Section 7 Interrupt Controller Interrupt Sources There are six types of interrupt sources: NMI, user break, user debugging interface, IRQ, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level 0, that interrupt is masked at all times. 7.4.1 NMI Interrupt The NMI interrupt has a priority level of 16 and is accepted at all times when the NMI mask bit (NMIM) in interrupt control register 0 (ICR0) is enabled. NMI interrupt requests are edgedetected, and the NMI edge select bit (NMIE) in ICR0 selects whether the rising edge or falling edge is detected. Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. When the NMIM bit in ICR0 is set to 1 (NMI interrupt request is masked), the NMI interrupt is not generated, however the NMI edge corresponding to NMIE bit of ICR0 is detected and the NMI interrupt request is retained until the interrupt request is accepted. The status of the interrupt request can be checked by reading the NMI interrupt request bit (NMIF) in the ICR0. If 0 is written to the NMIM bit (NMI interrupt request is enabled) when the NMIF bit is set to 1, the NMI interrupt request that is retained is accepted. Once the NMIM bit is set to 0 (NMI interrupt request is enabled), the NMIM bit cannot be set to 1 again, because only 0 can be written to the NMIM bit. When the NME bit is changed, the NMI interrupt request that is retained is cleared. When canceling software standby mode by the NMI interrupt, set the NMIM bit to 0 to enable the NMI interrupt request after confirming that the NMI interrupt request has been cleared in the NMIF. If software standby mode is entered when the NMIM bit is 1 (NMI interrupt request is masked), the NMI interrupt cannot cancel software standby mode. In this case, the NMI edge cannot be detected in software standby mode and the NMI interrupt is not generated even if software standby mode is canceled by cancel source other than NMI. When the NMI pin keeps level (low level after the falling edge or high level after the rising edge) in software standby mode until software standby mode is canceled by cancel source other than NMI (until the clock is initiated after the oscillation settling), that edge of the NMI in software standby mode can be detected. When deep standby mode is entered, deep standby mode is canceled by the NMI interrupt regardless of the NMI mask bit setting. NMIM bit is initialized by a power-on reset after canceling deep standby mode. When a sleep instruction is to be executed after 0 has been written to the NMIM bit (enabling the NMI), read the value of the NMIM bit before executing the sleep instruction. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 155 of 1910 Section 7 Interrupt Controller 7.4.2 SH726A Group, SH726B Group User Break Interrupt The user break interrupt, whose priority level is 15, occurs when a break condition specified by the user break controller is satisfied. The user break interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user break interrupts, see section 8, User Break Controller. 7.4.3 User Debugging Interface Interrupt The user debugging interface interrupt has a priority level of 15, and occurs at serial input of a user debugging interface interrupt instruction. User debugging interface interrupt requests are edge-detected and retained until they are accepted. The user debugging interface interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user debugging interface interrupts, see section 33, User Debugging Interface. 7.4.4 IRQ Interrupts IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority registers 01 and 02 (IPR01 and IPR02). When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the interrupt controller while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the interrupt controller when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the interrupt controller. The result of IRQ interrupt request detection is retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request detection. The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted IRQ interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the IRQ interrupt request register (IRQRR) so as not to accidentally receive the interrupt request again. Page 156 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.4.5 Section 7 Interrupt Controller PINT Interrupts PINT interrupts are input from pins PINT7 to PINT0. Input of the interrupt requests is enabled by the PINT enable bits (PINT7E to PINT0E) in the PINT interrupt enable register (PINTER). For the PINT7 to PINT0 interrupts, low-level or high-level detection can be selected individually for each pin by the PINT sense select bits (PINT7S to PINT0S) in interrupt control register 2 (ICR2). A single priority level in a range from 0 to 15 can be set for all PINT7 to PINT0 interrupts by bits 15 to 12 in interrupt priority register 05 (IPR05). When using low-level sensing for the PINT7 to PINT0 interrupts, an interrupt request signal is sent to the interrupt controller while the PINT7 to PINT0 pins are low. An interrupt request signal is stopped being sent to the interrupt controller when the PINT7 to PINT0 pins are driven high. The status of the interrupt requests can be checked by reading the PINT interrupt request bits (PINT7R to PINT0R) in the PINT interrupt request register (PIRR). The above description also applies to when using high-level sensing, except for the polarity being reversed. The PINT interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the PINT interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the PINT interrupt request register (PIRR) so as not to accidentally receive the interrupt request again. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 157 of 1910 Section 7 Interrupt Controller 7.4.6 SH726A Group, SH726B Group On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following on-chip peripheral modules:  Direct memory access controller  USB 2.0 host/function module  Compare match timer  Bus state controller  Watchdog timer  Multi-function timer pulse unit 2  A/D converter  Renesas SPDIF interface  Serial sound interface  I C bus interface 3 2  Serial communication interface with FIFO  Serial I/O with FIFO  Renesas serial peripheral interface  Controller area network  IEBus TM controller  CD-ROM decoder  SD host interface  Realtime clock  Sampling rate converter As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from 0 to 15 can be set for each module by interrupt priority registers 05 to 22 (IPR05 to IPR22). The on-chip peripheral module interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip peripheral module interrupt. Page 158 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.5 Section 7 Interrupt Controller Interrupt Exception Handling Vector Table and Priority Table 7.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and vector table address offsets. In interrupt exception handling, the interrupt exception service routine start address is fetched from the vector table indicated by the vector table address. For details of calculation of the vector table address, see table 6.4 in section 6, Exception Handling. The priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 05 to 22 (IPR01, IPR02, and IPR05 to IPR22). However, if two or more interrupts specified by the same IPR among IPR05 to IPR22 occur, the priorities are defined as shown in the IPR setting unit internal priority of table 7.4, and the priorities cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priorities indicated in table 7.4. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 159 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Table 7.4 Interrupt Exception Handling Vectors and Priorities Interrupt Vector Interrupt Priority Vector Table Corresponding Address Offset (Initial Value) IPR (Bit) IPR Setting Unit Internal Priority Default Priority High Interrupt Source Vector NMI 11 H'0000002C to H'0000002F 16   User break 12 H'00000030 to H'00000033 15   User debug interface 14 H'00000038 to H'0000003B 15   IRQ IRQ0 64 H'00000100 to H'00000103 0 to 15 (0) IPR01 (15 to 12)  IRQ1 65 H'00000104 to H'00000107 0 to 15 (0) IPR01 (11 to 8)  IRQ2 66 H'00000108 to H'0000010B 0 to 15 (0) IPR01 (7 to 4)  IRQ3 67 H'0000010C to H'0000010F 0 to 15 (0) IPR01 (3 to 0)  IRQ4 68 H'00000110 to H'00000113 0 to 15 (0) IPR02 (15 to 12)  IRQ5 69 H'00000114 to H'00000117 0 to 15 (0) IPR02 (11 to 8)  IRQ6 70 H'00000118 to H'0000011B 0 to 15 (0) IPR02 (7 to 4)  IRQ7 71 H'0000011C to H'0000011F 0 to 15 (0) IPR02 (3 to 0)  PINT0 80 H'00000140 to H'00000143 0 to 15 (0) IPR05 (15 to 12) 1 PINT1 81 H'00000144 to H'00000147 2 PINT2 82 H'00000148 to H'0000014B 3 PINT3 83 H'0000014C to H'0000014F 4 PINT4 84 H'00000150 to H'00000153 5 PINT Page 160 of 1910 Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector IPR Setting Unit Internal Priority Interrupt Source Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) PINT PINT5 85 H'00000154 to H'00000157 PINT6 86 H'00000158 to H'0000015B 7 PINT7 87 H'0000015C to H'0000015F 8 Direct Channel DEI0 memory 0 access HEI0 controller 108 H'000001B0 to H'000001B3 109 H'000001B4 to H'000001B7 Channel DEI1 1 112 H'000001C0 to H'000001C3 HEI1 113 H'000001C4 to H'000001C7 Channel DEI2 2 116 H'000001D0 to H'000001D3 HEI2 117 H'000001D4 to H'000001D7 Channel DEI3 3 120 H'000001E0 to H'000001E3 HEI3 121 H'000001E4 to H'000001E7 Channel DEI4 4 124 H'000001F0 to H'000001F3 HEI4 125 H'000001F4 to H'000001F7 Channel DEI5 5 128 H'00000200 to H'00000203 HEI5 129 H'00000204 to H'00000207 Channel DEI6 6 132 H'00000210 to H'00000213 HEI6 133 H'00000214 to H'00000217 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 0 to 15 (0) 0 to 15 (0) IPR05 (15 to 12) 6 Default Priority High IPR06 (15 to 12) 1 2 0 to 15 (0) IPR06 (11 to 8) 1 2 0 to 15 (0) IPR06 (7 to 4) 1 2 0 to 15 (0) IPR06 (3 to 0) 1 2 0 to 15 (0) IPR07 (15 to 12) 1 2 0 to 15 (0) IPR07 (11 to 8) 1 2 0 to 15 (0) IPR07 (7 to 4) 1 2 Low Page 161 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) IPR Setting Unit Internal Priority Default Priority Direct Channel DEI7 memory 7 access HEI7 controller 136 H'00000220 to H'00000223 1 High 137 H'00000224 to H'00000227 Channel DEI8 8 140 H'00000230 to H'00000233 HEI8 141 H'00000234 to H'00000237 Channel DEI9 9 144 H'00000240 to H'00000243 HEI9 145 H'00000244 to H'00000247 Channel DEI10 148 10 H'00000250 to H'00000253 HEI10 149 H'00000254 to H'00000257 Channel DEI11 152 11 H'00000260 to H'00000263 HEI11 153 H'00000264 to H'00000267 Channel DEI12 156 12 H'00000270 to H'00000273 HEI12 157 H'00000274 to H'00000277 Channel DEI13 160 13 H'00000280 to H'00000283 HEI13 161 H'00000284 to H'00000287 Channel DEI14 164 14 H'00000290 to H'00000293 HEI14 165 H'00000294 to H'00000297 Interrupt Vector Interrupt Source Page 162 of 1910 0 to 15 (0) IPR07 (3 to 0) 2 0 to 15 (0) IPR08 (15 to 12) 1 2 0 to 15 (0) IPR08 (11 to 8) 1 2 0 to 15 (0) IPR08 (7 to 4) 1 2 0 to 15 (0) IPR08 (3 to 0) 1 2 0 to 15 (0) IPR09 (15 to 12) 1 2 0 to 15 (0) IPR09 (11 to 8) 1 2 0 to 15 (0) IPR09 (7 to 4) 1 2 Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) Interrupt Source Direct Channel memory 15 access controller 1 High H'000002A0 to H'000002A3 HEI15 169 H'000002A4 to H'000002A7 170 H'000002A8 to H'000002AB 0 to 15 (0) IPR10 (15 to 12)  CMI0 171 H'000002AC to H'000002AF 0 to 15 (0) IPR10 (7 to 4) CMI1 172 H'000002B0 to H'000002B3 0 to 15 (0) IPR10 (3 to 0) Bus state CMI controller 173 H'000002B4 to H'000002B7 0 to 15 (0) IPR11 (15 to 12)  Watchdog ITI timer 174 H'000002B8 to H'000002BB 0 to 15 (0) IPR11 (11 to 8)  Channel TGI0A Multifunction 0 timer TGI0B pulse unit 2 TGI0C 175 H'000002BC to H'000002BF 0 to 15 (0) IPR11 (7 to 4) 1 176 H'000002C0 to H'000002C3 2 177 H'000002C4 to H'000002C7 3 TGI0D 178 H'000002C8 to H'000002CB 4 TCI0V 179 H'000002CC to H'000002CF TGI0E 180 H'000002D0 to H'000002D3 2 TGI0F 181 H'000002D4 to H'000002D7 3 USBI Compare Channel match 0 timer Channel 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 IPR09 (3 to 0) Default Priority DEI15 168 USB 2.0 host/ function module 0 to 15 (0) IPR Setting Unit Internal Priority 2 0 to 15 (0) IPR11 (3 to 0)  1 Low Page 163 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Source Vector MultiChannel TGI1A 182 function 1 timer TGI1B 183 pulse unit 2 TCI1V 184 Interrupt Priority Vector Table Corresponding Address Offset (Initial Value) IPR (Bit) H'000002D8 to H'000002DB 0 to 15 (0) IPR12 (15 to 12) 1 H'000002DC to H'000002DF H'000002E0 to H'000002E3 IPR Setting Unit Internal Priority High 2 0 to 15 (0) IPR12 (11 to 8) 1 TCI1U 185 H'000002E4 to H'000002E7 Channel TGI2A 186 2 H'000002E8 to H'000002EB TGI2B 187 H'000002EC to H'000002EF TCI2V 188 H'000002F0 to H'000002F3 TCI2U 189 H'000002F4 to H'000002F7 Channel TGI3A 190 3 H'000002F8 to H'000002FB TGI3B 191 H'000002FC to H'000002FF 2 TGI3C 192 H'00000300 to H'00000303 3 TGI3D 193 H'00000304 to H'00000307 4 TCI3V 194 H'00000308 to H'0000030B Page 164 of 1910 Default Priority 2 0 to 15 (0) IPR12 (7 to 4) 1 2 0 to 15 (0) IPR12 (3 to 0) 1 2 0 to 15 (0) 0 to 15 (0) IPR13 (15 to 12) 1 IPR13 (11 to 8)  Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) IPR Setting Unit Internal Priority Default Priority Channel TGI4A Multifunction 4 timer TGI4B pulse unit 2 TGI4C 195 H'0000030C to H'0000030F 1 High 196 H'00000310 to H'00000313 2 197 H'00000314 to H'00000317 3 TGI4D 198 H'00000318 to H'0000031B 4 TCI4V 199 H'0000031C to H'0000031F 0 to 15 (0) IPR13 (3 to 0)  A/D con- ADI verter 200 H'00000320 to H'00000323 0 to 15 (0) IPR14 (7 to 4)  Renesas SPDIFI SPDIF interface 201 H'00000324 to H'00000327 0 to 15 (0) IPR14 (3 to 0)  Serial Channel SSIF0 sound 0 interface 202 H'00000328 to H'0000032B 0 to 15 (0) IPR15 (15 to 12) 1 SSIRXI0 203 H'0000032C to H'0000032F 2 SSITXI0 204 H'00000330 to H'00000333 3 Interrupt Vector Interrupt Source R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 0 to 15 (0) IPR13 (7 to 4) Low Page 165 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) IPR Setting Unit Internal Priority Default Priority 205 H'00000334 to H'00000337 1 High SSIRTI1 206 H'00000338 to H'0000033B 2 SSITXI1 207 H'0000033C to H'0000033F 3 Interrupt Vector Interrupt Source Serial Channel SSII1 sound 1 interface Channel SSII2 2 208 H'00000340 to H'00000343 SSIRTI2 209 H'00000344 to H'00000347 Channel SSII3 3 210 H'00000348 to H'0000034B SSIRTI3 211 H'0000034C to H'0000034F I2C bus Channel STPI0 interface 0 3 NAKI0 Page 166 of 1910 0 to 15 (0) 0 to 15 (0) IPR15 (11 to 8) IPR15 (7 to 4) 1 2 0 to 15 (0) IPR15 (3 to 0) 1 2 212 H'00000350 to H'00000353 0 to 15 (0) IPR16 (15 to 12) 1 213 H'00000354 to H'00000357 2 RXI0 214 H'00000358 to H'0000035B 3 TXI0 215 H'0000035C to H'0000035F 4 TEI0 216 H'00000360 to H'00000363 5 Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) Interrupt Source I2C bus interface 3 1 High H'00000364 to H'00000367 NAKI1 218 H'00000368 to H'0000036B 2 RXI1 219 H'0000036C to H'0000036F 3 TXI1 220 H'00000370 to H'00000373 4 TEI1 221 H'00000374 to H'00000377 5 Channel STPI2 222 2 H'00000378 to H'0000037B NAKI2 223 H'0000037C to H'0000037F 2 RXI2 224 H'00000380 to H'00000383 3 TXI2 225 H'00000384 to H'00000387 4 TEI2 226 H'00000388 to H'0000038B 5 Channel STPI3 227 3 H'0000038C to H'0000038F NAKI3 228 H'00000390 to H'00000393 2 RXI3 229 H'00000394 to H'00000397 3 TXI3 230 H'00000398 to H'0000039B 4 TEI3 231 H'0000039C to H'0000039F 5 0 to 15 (0) 0 to 15 (0) IPR16 (11 to 8) Default Priority Channel STPI1 217 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 0 to 15 (0) IPR Setting Unit Internal Priority IPR16 (7 to 4) IPR16 (3 to 0) 1 1 Low Page 167 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) Interrupt Source IPR Setting Unit Internal Priority IPR17 (15 to 12) 1 Serial Channel BRI0 communi- 0 cation ERI0 interface with FIFO RXI0 232 H'000003A0 to H'000003A3 233 H'000003A4 to H'000003A7 2 234 H'000003A8 to H'000003AB 3 TXI0 235 H'000003AC to H'000003AF 4 Channel BRI1 1 236 H'000003B0 to H'000003B3 ERI1 237 H'000003B4 to H'000003B7 2 RXI1 238 H'000003B8 to H'000003BB 3 TXI1 239 H'000003BC to H'000003BF 4 Channel BRI2 2 240 H'000003C0 to H'000003C3 ERI2 241 H'000003C4 to H'000003C7 2 RXI2 242 H'000003C8 to H'000003CB 3 TXI2 243 H'000003CC to H'000003CF 4 Page 168 of 1910 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR17 (11 to 8) IPR17 (7 to 4) Default Priority High 1 1 Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) Interrupt Source IPR17 (3 to 0) IPR Setting Unit Internal Priority Default Priority 1 High Channel BRI3 Serial communi- 3 cation ERI3 interface with FIFO RXI3 244 H'000003D0 to H'000003D3 245 H'000003D4 to H'000003D7 2 246 H'000003D8 to H'000003DB 3 TXI3 247 H'000003DC to H'000003DF 4 Channel BRI4 4 248 H'000003E0 to H'000003E3 ERI4 249 H'000003E4 to H'000003E7 2 RXI4 250 H'000003E8 to H'000003EB 3 TXI4 251 H'000003EC to H'000003EF 4 252 H'000003F0 to H'000003F3 0 to 15 (0) IPR19 (15 to 12)  Renesas Channel SPEI0 253 0 serial peripheral SPRI0 254 interface H'000003F4 to H'000003F7 0 to 15 (0) IPR19 (11 to 8) H'000003F8 to H'000003FB 2 SPTI0 255 H'000003FC to H'000003FF 3 Channel SPEI1 256 1 H'00000400 to H'00000403 SPRI1 257 H'00000404 to H'00000407 2 SPTI1 258 H'00000408 to H'0000040B 3 Serial I/O SIOFI with FIFO R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR18 (15 to 12) 1 IPR19 (7 to 4) 1 1 Low Page 169 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) Interrupt Source Renesas Channel SPEI2 259 serial 2 peripheral SPRI2 260 interface SPTI2 261 H'0000040C to H'0000040F 0 to 15 (0) IPR19 (3 to 0) IPR Setting Unit Internal Priority Default Priority 1 High H'00000410 to H'00000413 2 H'00000414 to H'00000417 3 Controller Channel ERS0 area 0 network OVR0 262 H'00000418 to H'0000041B 263 H'0000041C to H'0000041F 2 RM00 264 H'00000420 to H'00000423 3 RM10 265 H'00000424 to H'00000427 4 SLE0 266 H'00000428 to H'0000042B 5 Channel ERS1 1 267 H'0000042C to H'0000042F OVR1 268 H'00000430 to H'00000433 2 RM01 269 H'00000434 to H'00000437 3 RM11 270 H'00000438 to H'0000043B 4 SLE1 271 H'0000043C to H'0000043F 5 Page 170 of 1910 0 to 15 (0) 0 to 15 (0) IPR20 (15 to 12) 1 IPR20 (11 to 8) 1 Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Source Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) IPR Setting Unit Internal Priority Default Priority High IEBusTM IEB controller 272 H'00000440 to H'00000443 0 to 15 (0) IPR20 (7 to 4)  CD-ROM ISY decoder 273 H'00000444 to H'00000447 0 to 15 (0) IPR20 (3 to 0) 1 IERR 274 H'00000448 to H'0000044B 2 ITARG 275 H'0000044C to H'0000044F 3 ISEC 276 H'00000450 to H'00000453 4 IBUF 277 H'00000454 to H'00000457 5 IREADY 278 H'00000458 to H'0000045B 6 SDHI3 280 H'00000460 to H'00000463 SDHI0 281 H'00000464 to H'00000467 2 SDHI1 282 H'00000468 to H'0000046B 3 ARM 283 H'0000046C to H'0000046F PRD 284 H'00000470 to H'00000473 2 CUP 285 H'00000474 to H'00000477 3 SD host interface Realtime clock R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 0 to 15 (0) 0 to 15 (0) IPR21 (11 to 8) IPR21 (7 to 4) 1 1 Low Page 171 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt Vector Interrupt Priority Vector Table Corresponding Vector Address Offset (Initial Value) IPR (Bit) Interrupt Source Sampling Channel OVF0 rate 0 converter UDF0 286 H'00000478 to H'0000047B 287 H'0000047C to H'0000047F 2 CEF0 288 H'00000480 to H'00000483 3 ODFI0 289 H'00000484 to H'00000487 4 IDEI0 290 H'00000488 to H'0000048B 5 Channel OVF1 1 291 H'0000048C to H'0000048F UDF1 292 H'00000490 to H'00000493 2 CEF1 293 H'00000494 to H'00000497 3 ODFI1 294 H'00000498 to H'0000049B 4 IDEI1 295 H'0000049C to H'0000049F 5 Channel OVF2 2 296 H'000004A0 to H'000004A3 UDF2 297 H'000004A4 to H'000004A7 2 CEF2 298 H'000004A8 to H'000004AB 3 ODFI2 299 H'000004AC to H'000004AF 4 IDEI2 H'000004B0 to H'000004B3 5 Page 172 of 1910 300 0 to 15 (0) IPR Setting Unit Internal Priority 0 to 15 (0) 0 to 15 (0) IPR22 (15 to 12) 1 IPR22 (11 to 8) IPR22 (7 to 4) Default Priority High 1 1 Low R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.6 Operation 7.6.1 Interrupt Operation Sequence Section 7 Interrupt Controller The sequence of interrupt operations is described below. Figure 7.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers 01, 02, and 05 to 22 (IPR01, IPR02, and IPR05 to IPR22). Lower priority interrupts are ignored*. If two of these interrupts have the same priority level or if multiple interrupts occur within a single IPR, the interrupt with the highest priority is selected, according to the default priority and IPR setting unit internal priority shown in table 7.4. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (figure 7.4). 5. The interrupt exception service routine start address is fetched from the exception handling vector table corresponding to the accepted interrupt. 6. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt is copied to bits I3 to I0 in SR. 7. The program counter (PC) is saved onto the stack. 8. The CPU jumps to the fetched interrupt exception service routine start address and starts executing the program. The jump that occurs is not a delayed branch. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 173 of 1910 Section 7 Interrupt Controller SH726A Group, SH726B Group Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 7.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-sensing are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt request register (IRQRR). For details, see section 7.4.4, IRQ Interrupts. Interrupts held pending due to edge-sensing are cleared by a power-on reset. Page 174 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Program execution state No Interrupt? Yes No NMI? Yes No User break? Yes User debugging interface interrupt? Yes No Level 15 interrupt? Yes Yes No Level 14 interrupt? I3 to I0 ≤ level 14? No No Yes Level 1 interrupt? I3 to I0 ≤ level 13? No No Yes Yes I3 to I0 = level 0? No Read exception handling vector table Save SR to stack Copy accept-interrupt level to I3 to I0 Save PC to stack Branch to interrupt exception service routine Figure 7.2 Interrupt Operation Flow R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 175 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.6.2 Stack after Interrupt Exception Handling Figure 7.3 shows the stack after interrupt exception handling. Address 4n – 8 PC*1 32 bits 4n – 4 SR 32 bits SP*2 4n Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executed instruction Always make sure that SP is a multiple of 4. Figure 7.3 Stack after Interrupt Exception Handling Page 176 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.7 Section 7 Interrupt Controller Interrupt Response Time Table 7.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 7.4 and 7.5 show examples of pipeline operation when banking is disabled. Figures 7.6 and 7.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 7.8 and 7.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 7.5 Interrupt Response Time Number of States NMI User Break Time from occurrence of interrupt 2 Icyc  3 Icyc request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU 2 Bcyc + 1 Pcyc Time from input of interrupt request signal to CPU until sequence currently being executed is completed, interrupt exception handling starts, and first instruction in interrupt exception service routine is fetched Item User Debugging Interface IRQ, PINT USB 2.0 Host/ Function Module Peripheral Module (Other than USB 2.0 host/ function module) Remarks 2 Icyc  2 Icyc  2 Icyc  2 Icyc  1 Pcyc 3 Bcyc + 1 Pcyc 4 Bcyc 2 Bcyc No register banking Min. 3 Icyc + m1 + m2 Max. 4 Icyc + 2(m1 + m2) + m3 Register Min.  3 Icyc + m1 + m2 Max.  12 Icyc + m1 + m2 Min.  3 Icyc + m1 + m2 Max.  3 Icyc + m1 + m2 + 19(m4) banking without register bank overflow Register banking with register bank overflow R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Min. is when the interrupt wait time is zero. Max. is when a higherpriority interrupt request has occurred during interrupt exception handling. Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Page 177 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller Number of States Peripheral Host/ Function Module Module (Other than USB 2.0 host/ function module) 5 Icyc  3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc  4 Bcyc + m1 + m2 5 Icyc  2 Bcyc + m1 + m2 216-MHz operation*1*2: 0.037 to 0.101 s 6 Icyc  6 Icyc  216-MHz operation*1*2: USB 2.0 User Item NMI Interrupt No response register time banking User Break Debugging Interface IRQ, PINT Remarks Min. 5 Icyc  2 Bcyc + 1 Pcyc + m1 + m2 6 Icyc  m1 + m2 5 Icyc  1 Pcyc + m1 + m2 Max. 6 Icyc  7 Icyc  6 Icyc  6 Icyc  2(m1 + m2) + m3 1 Pcyc + 2(m1 + m2) + m3 3 Bcyc + 4 Bcyc + 2 Bcyc + 0.055 to 0.120 s 1 Pcyc + 2(m1 + m2) + 2(m1 + m2) + 2(m1 + m2) + m3 m3 m3 5 Icyc  1 Pcyc + m1 + m2 5 Icyc  3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc  4 Bcyc + m1 + m2 5 Icyc  2 Bcyc + m1 + m2 216-MHz operation*1*2: 0.060 to 0.101 s 14 Icyc  14 Icyc  14 Icyc  14 Icyc  216-MHz operation*1*2: 1 Pcyc + m1 + m2 3 Bcyc + 1 Pcyc + m1 + m2 4 Bcyc + m1 + m2 2 Bcyc + m1 + m2 0.101 to 0.143 s 5 Icyc  1 Pcyc + m1 + m2 5 Icyc  3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc  4 Bcyc + m1 + m2 5 Icyc  2 Bcyc + m1 + m2 216-MHz operation*1*2: 0.060 to 0.101 s 5 Icyc  5 Icyc  5 Icyc  5 Icyc  216-MHz operation*1*2: 1 Pcyc + m1 + m2 + 19(m4) 3 Bcyc + 4 Bcyc + 1 Pcyc + m1 m1 + m2 + + 19(m4) m2 + 19(m4) 2 Bcyc + m1 + m2 + 19(m4) 0.148 to 0.189 s 2 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 Register Min.  banking without register bank Max.  overflow Register Min.  banking with register bank Max.  overflow Notes: m1 to m4 are the number of states needed for the following memory accesses. m1: Vector address read (longword read) m2: SR save (longword write) m3: PC save (longword write) m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. 1. In the case that m1 = m2 = m3 = m4 = 1 Icyc. 2. In the case that (I, B, P) = (216 MHz, 72 MHz, 36 MHz). Page 178 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 M M M IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) F: Instruction fetch. Instruction is fetched from memory in which program is stored. D: Instruction decoding. Fetched instruction is decoded. E: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. M: Memory access. Memory data access is performed. Figure 7.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 179 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 2 Icyc + 3 Bcyc + 1 Pcyc 1 Icyc + m1 + 2(m2) + m3 3 Icyc + m1 IRQ F D E E m1 m2 m3 M M M First instruction in interrupt exception service routine First instruction in multiple interrupt exception service routine D F D E E m1 m2 M M M F D Multiple interrupt acceptance Interrupt acceptance [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.5 Example of Pipeline Operation for Multiple Interrupts (No Register Banking) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 M M M E F D IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.6 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking without Register Bank Overflow) Page 180 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller 2 Icyc + 3 Bcyc + 1 Pcyc 9 Icyc 3 Icyc + m1 + m2 IRQ F RESBANK instruction D E E E E E E E E Instruction (instruction replacing interrupt exception handling) E D E E m1 m2 m3 M M M E F D First instruction in interrupt exception service routine Interrupt acceptance [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Figure 7.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 M M M ... M F ... ... IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E D [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 181 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 2 Icyc + 3 Bcyc + 1 Pcyc 2 Icyc + 17(m4) 1 Icyc + m1 + m2 + 2(m4) IRQ RESBANK instruction F D Instruction (instruction replacing interrupt exception handling) E M M M ... M m4 m4 M M W D E E First instruction in interrupt exception service routine m1 m2 m3 M M M ... F ... D Interrupt acceptance [Legend] m1: m2: m3: m4: Vector address read Saving of SR (stack) Saving of PC (stack) Restoration of banked registers Figure 7.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking with Register Bank Overflow) Page 182 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.8 Section 7 Interrupt Controller Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 7.10 shows the register bank configuration. Registers Register banks General registers R0 R1 : : R0 R1 Interrupt generated (save) R14 R15 Bank 0 Bank 1 .... : : Bank 14 R14 GBR Control registers System registers SR GBR VBR TBR MACH MACL PR PC RESBANK instruction (restore) MACH MACL PR VTO Bank control registers (interrupt controller) Bank control register IBCR Bank number register IBNR : Banked register Note: VTO: Vector table address offset Figure 7.10 Overview of Register Bank Configuration R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 183 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.8.1 (1) Banked Register and Input/Output of Banks Banked Register The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset are banked. (2) Input/Output of Banks This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in lastout (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place in the reverse order, beginning from the last bank saved to. 7.8.2 (1) Bank Save and Restore Operations Saving to Bank Figure 7.11 shows register bank save operations. The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU: a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the interrupt is generated. b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN, bank i. c. The BN value is incremented by 1. Register banks +1 (c) BN (a) Bank 0 Bank 1 : : Bank i Bank i + 1 : : Registers R0 to R14 (b) GBR MACH MACL PR VTO Bank 14 Figure 7.11 Bank Save Operations Page 184 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 7 Interrupt Controller Figure 7.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the interrupt exception service routine. 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc m1 m2 m3 M M M IRQ Instruction (instruction replacing interrupt exception handling) F D E E E (1) VTO, PR, GBR, MACL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 (4) R4, R5, R6, R7 Saved to bank Overrun fetch (5) R0, R1, R2, R3 F First instruction in interrupt exception service routine F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 7.12 Bank Save Timing (2) Restoration from Bank The RESBANK (restore from register bank) instruction is used to restore data saved in a register bank. After restoring data from the register banks with the RESBANK instruction at the end of the interrupt exception service routine, execute the RTE instruction to return from interrupt exception service routine. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 185 of 1910 Section 7 Interrupt Controller 7.8.3 SH726A Group, SH726B Group Save and Restore Operations after Saving to All Banks If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register banks, automatic saving to the stack is performed instead of register bank saving if the BOVE bit in the bank number register (IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception occurs and data is not saved to the stack. Save and restore operations when using the stack are as follows: (1) Saving to Stack 1. The status register (SR) and program counter (PC) are saved to the stack during interrupt exception handling. 2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14, R13, …, R1, and R0. 3. The register bank overflow bit (BO) in SR is set to 1. 4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. (2) Restoration from Stack When the RESBANK (restore from register bank) instruction is executed with the register bank overflow bit (BO) in SR set to 1, the CPU operates as follows: 1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14, PR, GBR, MACH, and MACL. 2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. Page 186 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.8.4 Section 7 Interrupt Controller Register Bank Exception There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all of the register banks, an interrupt for which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number register (IBNR) remains set to the bank count of 15 and saving is not performed to the register bank. (2) Register Bank Underflow This exception occurs if the RESBANK (restore from register bank) instruction is executed when no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH, MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number register (IBNR) remains set to 0. 7.8.5 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. When this happens, the CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a register bank overflow, and the start address of the executed RESBANK instruction for a register bank underflow. To prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. Program execution starts from the exception service routine start address. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 187 of 1910 SH726A Group, SH726B Group Section 7 Interrupt Controller 7.9 Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the direct memory access controller and transfer data. Interrupt sources that are designated to activate the direct memory access controller are masked without being input to the interrupt controller. The mask condition is as follows: Mask condition = DME  (DE0  interrupt source select 0 + DE1  interrupt source select 1 + DE2  interrupt source select 2 + DE3  interrupt source select 3 + DE4  interrupt source select 4 + DE5  interrupt source select 5 + DE6  interrupt source select 6 + DE7  interrupt source select 7 + DE8  interrupt source select 8 + DE9  interrupt source select 9 + DE10  interrupt source select 10 + DE11  interrupt source select 11 + DE12  interrupt source select 12 + DE13  interrupt source select 13 + DE14  interrupt source select 14 + DE15  interrupt source select 15) Figure 7.13 shows a block diagram of interrupt control. Here, DME is bit 0 in DMAOR of the direct memory access controller, and DEn (n = 0 to 15) is bit 0 in CHCR_0 to CHCR_15 of the direct memory access controller. For details, see section 11, Direct Memory Access Controller. Interrupt source Interrupt source flag clearing (by the direct memory access controller) Direct memory access controller Interrupt source (not specified as a direct memory access controller activating source) Interrupt controller CPU interrupt request CPU Figure 7.13 Interrupt Control Block Diagram Page 188 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 7.9.1 Section 7 Interrupt Controller Handling Interrupt Request Signals as Sources for CPU Interrupt but Not Direct Memory Access Controller Activating 1. Do not select direct memory access controller activating sources or clear the DME bit to 0. If, direct memory access controller activating sources are selected, clear the DE bit to 0 for the relevant channel of the direct memory access controller. 2. When interrupts occur, interrupt requests are sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt exception service routine. 7.9.2 Handling Interrupt Request Signals as Sources for Activating Direct Memory Access Controller but Not CPU Interrupt 1. Select direct memory access controller activating sources and set both the DE and DME bits to 1. This masks CPU interrupt sources regardless of the interrupt priority register settings. 2. Activating sources are applied to the direct memory access controller when interrupts occur. 3. The direct memory access controller clears the interrupt sources when starting transfer. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 189 of 1910 Section 7 Interrupt Controller 7.10 Usage Note 7.10.1 Timing to Clear an Interrupt Source SH726A Group, SH726B Group The interrupt source flags should be cleared in the interrupt exception service routine. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 7.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read* the interrupt source flag after it has been cleared, and then execute an RTE instruction. Note: * When clearing the USB 2.0 host/function module interrupt source flag, read the flag three times after clearing it. Page 190 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 8 User Break Controller Section 8 User Break Controller The user break controller provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Instruction fetch or data read/write (bus cycle (CPU or direct memory access controller) selection in the case of data read/write), data size, data contents, address value, and stop timing in the case of instruction fetch are break conditions that can be set in this module. Since this LSI uses a Harvard architecture, instruction fetch on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus), and data access on the C bus is performed by issuing bus cycles on the memory access bus (M bus). The internal bus (I bus) consists of the internal CPU bus, on which the CPU issues bus cycles, and the internal DMA bus, on which the direct memory access controller issues bus cycles. This module monitors the C bus and I bus. 8.1 Features 1. The following break comparison conditions can be set. Number of break channels: two channels (channels 0 and 1) User break can be requested as the independent condition on channels 0 and 1.  Address Comparison of the 32-bit address is maskable in 1-bit units. One of the four address buses (F address bus (FAB), M address bus (MAB), internal CPU address bus (ICAB), and internal DMA address bus (IDAB)) can be selected.  Data Comparison of the 32-bit data is maskable in 1-bit units. One of the three data buses (M data bus (MDB), internal CPU data bus (ICDB), and internal DMA data bus (IDDB)) can be selected.  Bus selection when I bus is selected Internal CPU bus or internal DMA bus  Bus cycle Instruction fetch (only when C bus is selected) or data access  Read/write  Operand size Byte, word, and longword 2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt exception processing is set before or after an instruction is executed. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 191 of 1910 SH726A Group, SH726B Group Section 8 User Break Controller Figure 8.1 shows a block diagram. Access control Internal bus (I bus) Internal DMA bus Internal CPU bus IDDB IDAB ICDB ICAB CPU bus (C bus) CPU CPU memory instruction access bus fetch bus MDB MAB Internal CPU bus FAB Access comparator BBR_0 BAR_0 Address comparator Data comparator BAMR_0 BDR_0 BDMR_0 Channel 0 Access comparator BBR_1 BAR_1 Address comparator Data comparator BAMR_1 BDR_1 BDMR_1 Channel 1 BRCR Control User break interrupt request [Legend] BBR: Break bus cycle register BAR: Break address register BAMR: Break address mask register BDR: Break data register BDMR: Break data mask register BRCR: Break control register Figure 8.1 Block Diagram Page 192 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.2 Section 8 User Break Controller Register Descriptions Table 8.1 shows a register configuration. Five control registers for each channel and one common control register for channel 0 and channel 1 are available. A register for each channel is described as BAR_0 for the BAR register in channel 0. Table 8.1 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 Break address register_0 BAR_0 R/W H'00000000 H'FFFC0400 32 Break address mask register_0 BAMR_0 R/W H'00000000 H'FFFC0404 32 Break bus cycle register_0 BBR_0 R/W H'0000 H'FFFC04A0 16 Break data register_0 BDR_0 R/W H'00000000 H'FFFC0408 Break data mask register_0 BDMR_0 R/W H'00000000 H'FFFC040C 32 Break address register_1 BAR_1 R/W H'00000000 H'FFFC0410 32 Break address mask register_1 BAMR_1 R/W H'00000000 H'FFFC0414 32 Break bus cycle register_1 BBR_1 R/W H'0000 H'FFFC04B0 16 Break data register_1 BDR_1 R/W H'00000000 H'FFFC0418 Break data mask register_1 BDMR_1 R/W H'00000000 H'FFFC041C 32 Break control register BRCR R/W H'00000000 H'FFFC04C0 32 1 Common R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 32 32 Page 193 of 1910 SH726A Group, SH726B Group Section 8 User Break Controller 8.2.1 Break Address Register (BAR) BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in each channel. The control bits CD[1:0] and CP[1:0] in the break bus cycle register (BBR) select one of the four address buses for a break condition. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BA31 to BA0 All 0 R/W Description R/W Break Address Store an address on the CPU address bus (FAB or MAB) or internal address bus (ICAB or IDAB) specifying break conditions. When the C bus and instruction fetch cycle are selected by BBR, specify an FAB address in bits BA31 to BA0. When the C bus and data access cycle are selected by BBR, specify an MAB address in bits BA31 to BA0. When the internal CPU bus (I bus) is selected by BBR, specify an ICAB address in bits BA31 to BA0. When the internal DMA bus (I bus) is selected by BBR, specify an IDAB address in bits BA31 to BA0. Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0. Page 194 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.2.2 Section 8 User Break Controller Break Address Mask Register (BAMR) BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address bits specified by BAR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16 Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0 Initial value: R/W: 0 R/W 0 R/W Bit Bit Name 31 to 0 BAM31 to BAM0 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W All 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Description Break Address Mask Specify bits masked in the break address bits specified by BAR (BA31 to BA0). 0: Break address bit BAn is included in the break condition 1: Break address bit BAn is masked and not included in the break condition Note: n = 31 to 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 195 of 1910 SH726A Group, SH726B Group Section 8 User Break Controller 8.2.3 Break Data Register (BDR) BDR is a 32-bit readable/writable register. The control bits CD[1:0] and CP[1:0] in the break bus cycle register (BBR) select one of the three data buses for a break condition. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value Bit Bit Name 31 to 0 BD31 to BD0 All 0 R/W Description R/W Break Data Bits Store data which specifies a break condition. When the C bus is selected by BBR, specify the break data on MDB in bits BD31 to BD0. When the internal CPU bus (I bus) is selected by BBR, specify an ICDB address in bits BD31 to BD0. When the internal DMA bus (I bus) is selected by BBR, specify an IDDB address in bits BD31 to BD0. Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0. Page 196 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.2.4 Section 8 User Break Controller Break Data Mask Register (BDMR) BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits specified by BDR. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16 Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0 Initial value: R/W: 0 R/W 0 R/W Bit Bit Name 31 to 0 BDM31 to BDM0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial Value R/W Description All 0 R/W Break Data Mask 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Specify bits masked in the break data bits specified by BDR (BD31 to BD0). 0: Break data bit BDn is included in the break condition 1: Break data bit BDn is masked and not included in the break condition Note: n = 31 to 0 Notes: 1. Set the operand size when specifying a value on a data bus as the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly, when the word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 197 of 1910 SH726A Group, SH726B Group Section 8 User Break Controller 8.2.5 Break Bus Cycle Register (BBR) BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupt requests, (2) including or excluding of the data bus value, (3) internal CPU bus or internal DMA bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand size as the break conditions. Bit: Initial value: R/W: 15 14 13 12 11 10 - - UBID DBE - - 0 R 0 R 0 R/W 0 R/W 0 R 0 R 9 8 7 CP[1:0] 0 R/W 0 R/W 6 CD[1:0] 0 R/W Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved 0 R/W 5 4 3 ID[1:0] 0 R/W 2 RW[1:0] 0 R/W 0 R/W 0 R/W 1 0 SZ[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 13 UBID 0 R/W User Break Interrupt Disable Disables or enables user break interrupt requests when a break condition is satisfied. 0: User break interrupt requests enabled 1: User break interrupt requests disabled 12 DBE 0 R/W Data Break Enable Selects whether the data bus condition is included in the break conditions. 0: Data bus condition is not included in break conditions 1: Data bus condition is included in break conditions 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 198 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 9, 8 CP[1:0] 00 R/W I-Bus Bus Select Select the bus when the bus cycle of the break condition is the I bus cycle. However, when the C bus cycle is selected, this bit is invalidated (only the CPU cycle). 00: Condition comparison is not performed 01: Break condition is the internal CPU bus 10: Break condition is the internal DMA bus 11: Break condition is the internal CPU bus 7, 6 CD[1:0] 00 R/W C Bus Cycle/I Bus Cycle Select Select the C bus cycle or I bus cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the C bus (F bus or M bus) cycle 10: Break condition is the I bus cycle 11: Break condition is the C bus (F bus or M bus) cycle 5, 4 ID[1:0] 00 R/W Instruction Fetch/Data Access Select Select the instruction fetch cycle or data access cycle as the bus cycle of the break condition. If the instruction fetch cycle is selected, select the C bus cycle. 00: Condition comparison is not performed 01: Break condition is the instruction fetch cycle 10: Break condition is the data access cycle 11: Break condition is the instruction fetch cycle or data access cycle 3, 2 RW[1:0] 00 R/W Read/Write Select Select the read cycle or write cycle as the bus cycle of the break condition. 00: Condition comparison is not performed 01: Break condition is the read cycle 10: Break condition is the write cycle 11: Break condition is the read cycle or write cycle R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 199 of 1910 SH726A Group, SH726B Group Section 8 User Break Controller Bit Bit Name Initial Value R/W Description 1, 0 SZ[1:0] 00 R/W Operand Size Select Select the operand size of the bus cycle for the break condition. 00: Break condition does not include operand size 01: Break condition is byte access 10: Break condition is word access 11: Break condition is longword access Page 200 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.2.6 Section 8 User Break Controller Break Control Register (BRCR) BRCR sets the following condition:  Specifies whether a start of user break interrupt exception processing by instruction fetch cycle is set before or after instruction execution. BRCR is a 32-bit readable/writable register that has break condition match flags and bits for setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid (previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag bit to be cleared and 1 to all other flag bits. Bit: Initial value: R/W: Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - PCB1 PCB0 - - - - - 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R SCMFC SCMFC SCMFD SCMFD 0 1 0 1 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 16  All 0 R Reserved 0 R/W 16 These bits are always read as 0. The write value should always be 0. 15 SCMFC0 0 R/W C Bus Cycle Condition Match Flag 0 When the C bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 0 does not match 1: The C bus cycle condition for channel 0 matches 14 SCMFC1 0 R/W C Bus Cycle Condition Match Flag 1 When the C bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The C bus cycle condition for channel 1 does not match 1: The C bus cycle condition for channel 1 matches R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 201 of 1910 SH726A Group, SH726B Group Section 8 User Break Controller Bit Bit Name Initial Value R/W 13 SCMFD0 0 R/W Description I Bus Cycle Condition Match Flag 0 When the I bus cycle condition in the break conditions set for channel 0 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 0 does not match 1: The I bus cycle condition for channel 0 matches 12 SCMFD1 0 R/W I Bus Cycle Condition Match Flag 1 When the I bus cycle condition in the break conditions set for channel 1 is satisfied, this flag is set to 1. In order to clear this flag, write 0 to this bit. 0: The I bus cycle condition for channel 1 does not match 1: The I bus cycle condition for channel 1 matches 11 to 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6 PCB1 0 R/W PC Break Select 1 Selects the break timing of the instruction fetch cycle for channel 1 as before or after instruction execution. 0: PC break of channel 1 is generated before instruction execution 1: PC break of channel 1 is generated after instruction execution 5 PCB0 0 R/W PC Break Select 0 Selects the break timing of the instruction fetch cycle for channel 0 as before or after instruction execution. 0: PC break of channel 0 is generated before instruction execution 1: PC break of channel 0 is generated after instruction execution 4 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 202 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.3 Operation 8.3.1 Flow of the User Break Operation Section 8 User Break Controller The flow from setting of break conditions to user break interrupt exception handling is described below: 1. The break address is set in a break address register (BAR). The masked address bits are set in a break address mask register (BAMR). The break data is set in the break data register (BDR). The masked data bits are set in the break data mask register (BDMR). The bus break conditions are set in the break bus cycle register (BBR). Three control bit groups of BBR (C bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set to 00. The relevant break control conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBR, and branch after reading from the last written register. The newly written register values become valid from the instruction at the branch destination. 2. In the case where the break conditions are satisfied and the user break interrupt request is enabled, this module sends a user break interrupt request to the interrupt controller sets the C bus condition match flag (SCMFC) or I bus condition match flag (SCMFD) for the appropriate channel. 3. On receiving a user break interrupt request signal, the interrupt controller determines its priority. Since the user break interrupt has a priority level of 15, it is accepted when the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR) is 14 or lower. If the I3 to I0 bits are set to a priority level of 15, the user break interrupt is not accepted, but the conditions are checked, and condition match flags are set if the conditions match. For details on ascertaining the priority, see section 7, Interrupt Controller. 4. Condition match flags (SCMFC and SCMFD) can be used to check which condition has been satisfied. Clear the condition match flags during the user break interrupt exception processing routine. The interrupt occurs again if this operation is not performed. 5. There is a chance that the break set in channel 0 and the break set in channel 1 occur around the same time. In this case, there will be only one user break request to the interrupt controller but these two break channel match flags may both be set. 6. When selecting the I bus as the break condition, note as follows:  Whether or not an access issued on the C bus by the CPU is issued on the internal CPU bus depends on the cache settings. Regarding the I bus operation under cache conditions, see table 9.8 in section 9, Cache.  When a break condition is specified for the I bus, only the data access cycle is monitored. The instruction fetch cycle (including the cache renewal cycle) is not monitored. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 203 of 1910 Section 8 User Break Controller SH726A Group, SH726B Group  Only data access cycles are issued for the internal DMA bus cycles.  If a break condition is specified for the I bus, even when the condition matches in an internal CPU bus cycle resulting from an instruction executed by the CPU, at which instruction the user break interrupt request is to be accepted cannot be clearly defined. 8.3.2 Break on Instruction Fetch Cycle 1. When C bus/instruction fetch/read/word or longword is set in the break bus cycle register (BBR), the break condition is the FAB bus instruction fetch cycle. Whether a start of user break interrupt exception processing is set before or after the execution of the instruction can then be selected with the PCB0 or PCB1 bit of the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear BA0 bit in the break address register (BAR) to 0. A break cannot be generated as long as this bit is set to 1. 2. A break for instruction fetch which is set as a break before instruction execution occurs when it is confirmed that the instruction has been fetched and will be executed. This means a break does not occur for instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delayed branch instruction, the user break interrupt request is not received until the execution of the first instruction at the branch destination. Note: If a branch does not occur at a delayed branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When setting a break condition for break after instruction execution, the instruction set with the break condition is executed and then the break is generated prior to execution of the next instruction. As with pre-execution breaks, a break does not occur with overrun fetch instructions. When this kind of break is set for a delayed branch instruction and its delay slot, the user break interrupt request is not received until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDR) is ignored. Therefore, break data cannot be set for the break of the instruction fetch cycle. 5. If the I bus is set for a break of an instruction fetch cycle, the setting is invalidated. Page 204 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.3.3 Section 8 User Break Controller Break on Data Access Cycle 1. If the C bus is specified as a break condition for data access break, condition comparison is performed for the addresses (and data) accessed by the executed instructions, and a break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles on the bus specified by the I bus select bits, and a break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the internal CPU bus, see 6 in section 8.3.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 8.2. Table 8.2 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BAR), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size in the break bus cycle register (BBR). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in the four bytes at bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 of the break data register (BDR) and break data mask register (BDMR). To specify word data for this case, set the same data in the two words at bits 31 to 16 and 15 to 0. 4. Access by a PREF instruction is handled as read access in longword units without access data. Therefore, if including the value of the data bus when a PREF instruction is specified as a break condition, a break will not occur. 5. If the data access cycle is selected, the instruction at which the break will occur cannot be determined. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 205 of 1910 Section 8 User Break Controller 8.3.4 SH726A Group, SH726B Group Value of Saved Program Counter When a user break interrupt request is received, the address of the instruction from where execution is to be resumed is saved to the stack, and the exception handling state is entered. If the C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access cycle is specified as a break condition, the instruction at which the break should occur cannot be uniquely determined. 1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved to the stack. The instruction that matched the condition is not executed, and the break occurs before it. However when a delay slot instruction matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved to the stack. The instruction that matches the condition is executed, and the break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, the instruction is executed, and the branch destination address is saved to the stack. 3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition: The address after executing several instructions of the instruction that matched the break condition is saved to the stack. Page 206 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 8.3.5 (1) Section 8 User Break Controller Usage Examples Break Condition Specified for C Bus Instruction Fetch Cycle (Example 1-1)  Register specifications BAR_0 = H'00000404, BAMR_0 = H'00000000, BBR_0 = H'0054, BAR_1 = H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Address: H'00000404, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2)  Register specifications BAR_0 = H'00027128, BAMR_0 = H'00000000, BBR_0 = H'005A, BAR_1= H'00031415, BAMR_1 = H'00000000, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000000 Address: H'00027128, Address mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/write/word Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) On channel 0, a user break does not occur since instruction fetch is not a write cycle. On channel 1, a user break does not occur since instruction fetch is performed for an even address. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 207 of 1910 Section 8 User Break Controller SH726A Group, SH726B Group (Example 1-3)  Register specifications BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_0 = H'0054, BAR_1= H'00008010, BAMR_1 = H'00000006, BBR_1 = H'0054, BDR_1 = H'00000000, BDMR_1 = H'00000000, BRCR = H'00000020 Address: H'00008404, Address mask: H'00000FFF Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. (2) Break Condition Specified for C Bus Data Access Cycle (Example 2-1)  Register specifications BAR_0 = H'00123456, BAMR_0 = H'00000000, BBR_0 = H'0064, BAR_1= H'000ABCDE, BAMR_1 = H'000000FF, BBR_1 = H'106A, BDR_1 = H'A512A512, BDMR_1 = H'00000000, BRCR = H'00000000 Address: H'00123456, Address mask: H'00000000 Bus cycle: C bus/data access/read (operand size is not included in the condition) Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: C bus/data access/write/word On channel 0, a user break occurs with longword read from address H'00123456, word read from address H'00123456, or byte read from address H'00123456. On channel 1, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Page 208 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 8 User Break Controller Break Condition Specified for I Bus Data Access Cycle (Example 3-1)  Register specifications BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0194, BAR_1= H'00055555, BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F, BRCR = H'00000000 Address: H'00314156, Address mask: H'00000000 Bus cycle: Internal CPU bus/instruction fetch/read (operand size is not included in the condition) Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: Internal DMA bus/data access/write/byte On channel 0, the setting of the internal CPU bus/instruction fetch is ignored. On channel 1, a user break occurs when the direct memory access controller writes byte data H'7x in address H'00055555 on the internal DMA bus (access via the internal CPU bus does not generate a user break). R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 209 of 1910 Section 8 User Break Controller 8.4 SH726A Group, SH726B Group Usage Notes 1. The CPU can read from or write to this module registers via the internal CPU bus. Accordingly, during the period from executing an instruction to rewrite this module register till the new value is actually rewritten, the desired break may not occur. In order to know the timing when this module register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. This module cannot monitor the C bus, internal CPU, and internal DMA bus cycles in the same channel. 3. When a user break interrupt request and another exception source occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 6.1 in section 6, Exception Handling. If an exception source with higher priority occurs, the user break interrupt request is not received. 4. Note the following when a break occurs in a delay slot. If a pre-execution break is set at a delay slot instruction, the user break interrupt request is not received immediately before execution of the branch destination. 5. User breaks are disabled during module standby mode. Do not read from or write to this module registers during module standby mode; the values are not guaranteed. 6. Do not set an address within an interrupt exception handling routine whose interrupt priority level is at least 15 (including user break interrupts) as a break address. 7. Do not set break after instruction execution for the SLEEP instruction or for the delayed branch instruction where the SLEEP instruction is placed at its delay slot. 8. When setting a break for a 32-bit instruction, set the address where the upper 16 bits are placed. If the address of the lower 16 bits is set and a break before instruction execution is set as a break condition, the break is handled as a break after instruction execution. 9. Do not set a user break before instruction execution for the instruction following the DIVU or DIVS instruction. If a user break before instruction execution is set for the instruction following the DIVU or DIVS instruction and an exception or interrupt occurs during execution of the DIVU or DIVS instruction, a user break occurs before instruction execution even though execution of the DIVU or DIVS instruction is halted. Page 210 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 9 Cache Section 9 Cache 9.1 Features  Capacity Instruction cache: 8 Kbytes Operand cache: 8 Kbytes  Structure: Instructions/data separated, 4-way set associative  Way lock function (only for operand cache): Way 2 and way 3 are lockable  Line size: 16 bytes  Number of entries: 128 entries/way  Write system: Write-back/write-through selectable  Replacement method: Least-recently-used (LRU) algorithm 9.1.1 Cache Structure The cache separates data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. In each way, each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes  4). The data capacity per way is 2 Kbytes (16 bytes  128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure 9.1 shows the operand cache structure. The instruction cache structure is the same as the operand cache structure except for not having the U bit. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 211 of 1910 Section 9 SH726A Group, SH726B Group Cache Address array (ways 0 to 3) Entry 0 V U Tag address Entry 1 . . . . . . Entry 127 23 (1 + 1 + 21) bits LRU Data array (ways 0 to 3) 0 LW0 LW1 LW2 LW3 0 1 1 . . . . . . . . . . . . 127 127 128 (32 × 4) bits 6 bits LW0 to LW3: Longword data 0 to 3 Figure 9.1 Operand Cache Structure (1) Address Array The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit (only for operand cache) indicates whether the entry has been written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the access to external memory or large-capacity on-chip RAM. It consists of 21 bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 10, Bus State Controller), and therefore the upper three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in software standby mode. The tag address is not initialized by a power-on reset or manual reset or in software standby mode. (2) Data Array Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on reset or manual reset or in software standby mode. Page 212 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 9 Cache LRU With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way that has been least recently accessed. Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between LRU and way replacement is shown in table 9.1 when the cache lock function (only for operand cache) is not used (concerning the case where the cache lock function is used, see section 9.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 9.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 9.1. The LRU bits are initialized to B'000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Table 9.1 LRU and Way Replacement (Cache Lock Function Not Used) LRU (Bits 5 to 0) Way to be Replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 213 of 1910 Section 9 SH726A Group, SH726B Group Cache 9.2 Register Descriptions Table 9.2 shows the register configuration of the cache. Table 9.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Cache control register 1 CCR1 R/W H'00000000 H'FFFC1000 32 Cache control register 2 CCR2 R/W H'00000000 H'FFFC1004 32 9.2.1 Cache Control Register 1 (CCR1) The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or write-back mode for operand cache. Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - ICF - - ICE - - - - OCF - WT OCE 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W Initial value: R/W: Page 214 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 9 Cache Bit Bit Name Initial Value R/W Description 31 to 12  All 0 R 11 ICF 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Flush Writing 1 flushes all instruction cache entries (clears the V and LRU bits of all instruction cache entries to 0). Always reads 0. Write-back to the external memory or the large-capacity on-chip RAM is not performed when the instruction cache is flushed. 10, 9  All 0 R 8 ICE 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Enable Indicates whether the instruction cache function is enabled/disabled. 0: Instruction cache disable 1: Instruction cache enable 7 to 4  All 0 R 3 OCF 0 R/W 2  0 R 1 WT 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Operand Cache Flush Writing 1 flushes all operand cache entries (clears the V, U, and LRU bits of all operand cache entries to 0). Always reads 0. Write-back to the external memory or the large-capacity on-chip RAM is not performed when the operand cache is flushed. Reserved This bit is always read as 0. The write value should always be 0. Write Through Selects write-back mode or write-through mode. 0: Write-back mode 1: Write-through mode 0 OCE 0 R/W Operand Cache Enable Indicates whether the operand cache function is enabled/disabled. 0: Operand cache disable 1: Operand cache enable R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 215 of 1910 Section 9 9.2.2 SH726A Group, SH726B Group Cache Cache Control Register 2 (CCR2) CCR2 is used to enable or disable the cache locking function for operand cache and is valid in cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to 1. In non-cache-locking mode, the cache locking function is invalid. When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF @Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The relationship between the setting of each bit and a way, to be replaced when the prefetch instruction is executed, are listed in table 9.3. On the other hand, when the prefetch instruction is executed and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1 specified in cache locking mode while one-line data already exists in way 0 which is specified by Rn, a cache hit occurs and data is not fetched to way 3. In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in CCR2 and ways to be replaced are listed in table 9.4. Programs that change the contents of CCR2 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR2. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - LE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: W3 W3 LOAD* LOCK 0 R/W 0 R/W W2 W2 LOAD* LOCK 0 R/W 0 R/W Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Page 216 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 9 Cache Bit Bit Name Initial Value R/W Description 31 to 17  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock Enable Controls the cache locking function. 0: Not cache locking mode 1: Cache locking mode 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 W3LOAD* 0 R/W Way 3 Load 8 W3LOCK 0 R/W Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD = 1 and W3LOCK = 1 in cache locking mode, the data is always loaded into way 3. Under any other condition, the cache miss data is loaded into the way to which LRU points.  7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 W2LOAD* 0 R/W Way 2 Load 0 W2LOCK 0 R/W Way 2 Lock When a cache miss occurs by the prefetch instruction while W2LOAD = 1 and W2LOCK =1 in cache locking mode, the data is always loaded into way 2. Under any other condition, the cache miss data is loaded into the way to which LRU points. Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 217 of 1910 Section 9 SH726A Group, SH726B Group Cache Table 9.3 LE Way to be Replaced when a Cache Miss Occurs in PREF Instruction W3LOAD* W3LOCK W2LOAD* W2LOCK Way to be Replaced 0 x x x x Decided by LRU (table 9.1) 1 x 0 x 0 Decided by LRU (table 9.1) 1 x 0 0 1 Decided by LRU (table 9.5) 1 0 1 x 0 Decided by LRU (table 9.6) 1 0 1 0 1 Decided by LRU (table 9.7) 1 0 x 1 1 Way 2 1 1 1 0 x Way 3 [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 9.4 LE Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction W3LOAD* W3LOCK W2LOAD* W2LOCK Way to be Replaced 0 x x x x Decided by LRU (table 9.1) 1 x 0 x 0 Decided by LRU (table 9.1) 1 x 0 x 1 Decided by LRU (table 9.5) 1 x 1 x 0 Decided by LRU (table 9.6) 1 x 1 x 1 Decided by LRU (table 9.7) [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 9.5 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 0) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0 Page 218 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Table 9.6 Section 9 Cache LRU and Way Replacement (when W2LOCK = 0 and W3LOCK = 1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 Table 9.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1) LRU (Bits 5 to 0) Way to be Replaced 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 219 of 1910 Section 9 9.3 Cache SH726A Group, SH726B Group Operation Operations for the operand cache are described here. Operations for the instruction cache are similar to those for the operand cache except for the address array not having the U bit, and there being no prefetch operation or write operation, or a write-back buffer. 9.3.1 Searching Cache If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is accessed, the cache will be searched to see if the desired data is in the cache. Figure 9.2 illustrates the method by which the cache is searched. Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits 31 to 11 of the address used to access memory are compared with the read tag address. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V  1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V  0), a cache miss occurs. Figure 9.2 shows a hit on way 1. Page 220 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 9 Cache Access address 31 11 10 4 3 21 0 Entry selection Longword (LW) selection Data array (ways 0 to 3) Address array (ways 0 to 3) Entry 0 V Entry 0 U Tag address LW0 LW1 LW2 LW3 Entry 1 Entry 1 . . . . . . . . . . . . . . . . . . Entry 127 Entry 127 CMP0 CMP1 CMP2 CMP3 Hit signal (way 1) [Legend] CMP0 to CMP3: Comparison circuits 0 to 3 Figure 9.2 Cache Search Scheme R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 221 of 1910 Section 9 9.3.2 (1) Cache SH726A Group, SH726B Group Read Access Read Hit In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. (2) Read Miss An internal bus cycle starts and the entry is updated. The way replaced follows table 9.4. Entries are updated in 16-byte units. When the desired data that caused the miss is loaded from the external memory or the large-capacity on-chip RAM to the cache, the data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the entry to be replaced by updating the entry in writeback mode is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. Cache update operation and write-back operation to the memory are performed in wrap-around mode. When the lower four bits of the address of readmiss data are H'4, for example, cache update operation and write-back operation to the memory are performed in the following order of the lower 4-bit value of address: H'4  H'8  H'C  H'0. 9.3.3 (1) Prefetch Operation (Only for Operand Cache) Prefetch Hit LRU is updated so that the hit way becomes the latest. The contents in other caches are not modified. No data is transferred to the CPU. (2) Prefetch Miss No data is transferred to the CPU. The way to be replaced follows table 9.3. Other operations are the same as those in the case of read miss. Page 222 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 9.3.4 (1) Section 9 Cache Write Operation (Only for Operand Cache) Write Hit In a write access in write-back mode, the data is written to the cache and no write cycle to the external memory or the large-capacity on-chip RAM is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit way becomes the latest. In write-through mode, the data is written to the cache and a write cycle to the external memory or the large-capacity on-chip RAM is issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way becomes the latest. (2) Write Miss In write-back mode, an internal bus cycle starts when a write miss occurs, and the entry is updated. The way to be replaced follows table 9.4. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. Cache update operation and write-back operation to the memory are performed in wrap-around mode. When the lower four bits of the address of write-miss data are H'4, for example, cache update operation and write-back operation to the memory are performed in the following order of the lower 4-bit value of address: H'4  H'8  H'C  H'0. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory or the large-capacity on-chip RAM. 9.3.5 Write-Back Buffer (Only for Operand Cache) When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory or the large-capacity on-chip RAM. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to the external memory or the large-capacity onchip RAM. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 9.3 shows the configuration of the write-back buffer. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 223 of 1910 Section 9 SH726A Group, SH726B Group Cache A (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 A (31 to 4): Physical address written to external memory (upper three bits are 0) Longword 0 to 3: One line of cache data to be written to external memory Figure 9.3 Write-Back Buffer Configuration Operations in sections 9.3.2 to 9.3.5 are summarized in table 9.8. Table 9.8 Cache Operations Write-Back Mode/ Cache Hit/ Write-Through Cycle Miss Mode U Bit RAM (Through Internal Bus) Cache Contents   Not generated Not updated   Instruction Instruction Hit cache Access to External Memory CPU or Large-Capacity On-Chip fetch Miss Operand Prefetch/ cache read Hit Either mode is x Cache update cycle is Updated to new values by cache generated update cycle Not generated Not updated available Miss Write-through  mode Write-back mode 0 1 Cache update cycle is Updated to new values by cache generated update cycle Cache update cycle is Updated to new values by cache generated update cycle Cache update cycle is Updated to new values by cache generated. Then write-back update cycle cycle in write-back buffer is generated. Write Hit Write-through  mode Write-back mode x Write cycle CPU issues is Updated to new values by write generated. cycle the CPU issues Not generated Updated to new values by write cycle the CPU issues Miss Write-through  mode Write-back mode Write cycle CPU issues is Not updated* generated. 0 Cache update cycle is Updated to new values by cache generated update cycle. Subsequently updated again to new values in write cycle CPU issues. 1 Page 224 of 1910 Cache update cycle is Updated to new values by cache generated. Then write-back update cycle. Subsequently cycle in write-back buffer is updated again to new values in generated. write cycle CPU issues. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 9 Cache [Legend] x: Don't care. Note: Cache update cycle: 16-byte read access Write-back cycle in write-back buffer: 16-byte write access * Neither LRU updated. LRU is updated in all other cases. 9.3.6 Coherency of Cache and External Memory or Large-Capacity On-Chip RAM Use software to ensure coherency between the cache and the external memory or the largecapacity on-chip RAM. When memory shared by this LSI and another device is mapped in the cache-enabled space, operate the memory-mapped cache to invalidate and write back as required. The same operation should be performed for the memory shared by the CPU and the direct memory access controller in this LSI. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 225 of 1910 Section 9 9.4 Cache SH726A Group, SH726B Group Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 9.4.1 Address Array To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. In the address field, specify the entry address for selecting the entry, the W bit for selecting the way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is fixed at longword, specify B'00 for bits 1 and 0 of the address. The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always specify 0 for the upper three bits (bits 31 to 29) of the tag address. For the address and data formats, see figure 9.4. The following three operations are possible for the address array. Page 226 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (1) Section 9 Cache Address Array Read The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry address specified by the address and the entry corresponding to the way. For the read operation, associative operation is not performed regardless of whether the associative bit (A bit) specified by the address is 1 or 0. (2) Address-Array Write (Non-Associative Operation) When the associative bit (A bit) in the address field is cleared to 0, write the tag address, LRU bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address specified by the address and the entry corresponding to the way. When writing to a cache line for which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. Writeback operation to the memory is performed in the following order of the lower 4-bit value of address: H'0  H'4  H'8  H'C. (3) Address-Array Write (Associative Operation) When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field are compared with the tag address that is specified by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that has a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. Write-back operation to the memory is performed in the following order of the lower 4-bit value of address: H'0  H'4  H'8  H'C. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 227 of 1910 Section 9 9.4.2 Cache SH726A Group, SH726B Group Data Array To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. Specify the entry address for selecting the entry, the L bit indicating the longword position within the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword, specify B'00 for bits 1 and 0 of the address. For the address and data formats, see figure 9.4. The following two operations are possible for the data array. Information in the address array is not modified by this operation. (1) Data Array Read The data specified by the L bit in the address is read from the entry address specified by the address and the entry corresponding to the way. Page 228 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 9 Cache Data Array Write The longword data specified by the data is written to the position specified by the L bit in the address from the entry address specified by the address and the entry corresponding to the way. 1. Instruction cache 2. Operand cache 1.1 Address array access 2.1 Address array access (a) Address specification (a) Address specification Read access 31 23 22 Read access 13 12 11 10 111100000 *----------* Write access 31 23 22 4 Entry address W 3 2 1 0 31 0 * 0 0 111100001 *----------* 3 2 1 0 31 A * 0 0 111100001 *----------* 3 2 1 0 31 X X X V 0 0 0 Tag address (28 to 11) E 13 12 11 10 W 4 Entry address W 4 Entry address 4 11 10 9 29 28 0 0 0 Tag address (28 to 11) E LRU 23 22 13 12 11 10 W 4 Entry address 4 11 10 9 29 28 LRU 1.2 Data array access (both read and write accesses) 2.2 Data array access (both read and write accesses) (a) Address specification (a) Address specification 23 22 2 1 0 * 0 0 13 12 11 10 111100010 *----------* W 4 3 2 1 0 A * 0 0 (b) Data specification (both read and write accesses) (b) Data specification (both read and write accesses) 31 3 0 Write access 13 12 11 10 111100000 *----------* 31 23 22 3 Entry address 2 L 1 0 31 0 0 111100011 *----------* 23 22 13 12 11 10 W Entry address 4 3 2 1 0 X X U V 1 0 0 0 3 2 L (b) Data specification (b) Data specification 31 0 Longword data 31 0 Longword data [Legend] *: Don't care E: Bit 10 of entry address for read, don't care for write X: 0 for read, don't care for write Figure 9.4 Specifying Address and Data for Memory-Mapped Cache Access R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 229 of 1910 Section 9 9.4.3 (1) Cache SH726A Group, SH726B Group Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. An example when a write data is specified in R0 and an address is specified in R1 is shown below. ; R0=H'0110 0010; tag address(28-11)=B'0 0001 0001 0000 0000 0, U=0, V=0 ; R1=H'F080 0088; operand cache address array access, entry=B'000 1000, A=1 ; MOV.L R0,@R1 (2) Reading the Data of a Specific Entry The data section of a specific cache entry can be read by the memory mapping cache access. The longword indicated in the data field of the data array in figure 9.4 is read into the register. An example when an address is specified in R0 and data is read in R1 is shown below. ; R0=H'F100 004C; instruction cache data array access, entry=B'000 0100, ; Way=0, longword address=3 ; MOV.L @R0,R1 Page 230 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 9.4.4 Section 9 Cache Usage Notes 1. Programs that access memory-mapped cache of the operand cache should be placed in a cachedisabled space. Programs that access memory-mapped cache of the instruction cache should be placed in a cache-disabled space, and in each of the beginning and the end of that, two or more read accesses to on-chip peripheral modules or external address space (cache-disabled address) should be executed. 2. Rewriting the address array contents so that two or more ways are hit simultaneously is prohibited. Operation is not guaranteed if the address array contents are changed so that two or more ways are hit simultaneously. 3. Registers and memory-mapped cache can be accessed only by the CPU and not by the direct memory access controller. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 231 of 1910 Cache SH726A Group, SH726B Group Page 232 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Section 9 SH726A Group, SH726B Group Section 10 Bus State Controller Section 10 Bus State Controller The bus state controller outputs control signals for various types of memory and external devices that are connected to the external address space. The functions of this module enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 10.1 Features 1. External address space  Supports for up to 8 Mbytes each in areas CS0 and CS3 (for the SH726A) or up to 64 Mbytes each in areas CS0 to CS4 (for the SH726B).  Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clocked synchronous or asynchronous), and SDRAM memory type for each address space.  Data bus width for CS0 space is 16 bits. Can select the data bus width (8 or 16 bits) for each of address spaces CS1 to CS4.  Controls insertion of wait cycles for each address space.  Controls insertion of wait cycles for each read access and write access.  Can set independent idle cycles during the continuous access for five cases: read-write (in same space/different spaces), read-read (in same space/different spaces), the first cycle is a write access. 2. Normal space interface  Supports the interface that can directly connect to the SRAM. 3. Burst ROM interface (clocked asynchronous)  High-speed access to the ROM that has the page mode function. 4. SDRAM interface  Can set the SDRAM in up to two areas.  Multiplex output for row address/column address.  Efficient access by single read/single write.  High-speed access in bank-active mode.  Supports an auto-refresh and self-refresh.  Supports a power-down mode.  Issues MRS and EMRS commands. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 233 of 1910 Section 10 Bus State Controller SH726A Group, SH726B Group 5. SRAM interface with byte selection  Can connect directly to a SRAM with byte selection. 6. Burst ROM interface (clocked synchronous)  Can connect directly to a burst ROM of the clocked synchronous type. 7. Refresh function  Supports the auto-refresh and self-refresh functions.  Specifies the refresh interval using the refresh counter and clock selection.  Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 8. Usage as interval timer for refresh counter  Generates an interrupt request at compare match. Page 234 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bus mastership controller WAIT Wait controller Internal bus Figure 10.1 shows a block diagram of this module. CMNCR . . . CS0WCR . . . CS0 to CS4 A25 to A0, D15 to D0, BS, RD/WR, RD, WE1, WE0, RAS, CAS, CKE, DQMU, DQML Area controller . . . CS0BCR . . . CS4BCR . . . Module bus CS4WCR Memory controller SDCR RTCSR RTCNT Refresh controller Comparator RTCOR BSC [Legend] CMNCR: Common control register CSnWCR: CSn space wait control register (n =0 to 4) CSnBCR: CSn space bus control register (n = 0 to 4) SDCR: SDRAM control register RTCSR: Refresh timer control/status register RTCNT: Refresh timer counter RTCOR: Refresh time constant register Figure 10.1 Block Diagram of Bus State Controller R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 235 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.2 Input/Output Pins Table 10.1 shows the pin configuration. Table 10.1 Pin Configuration Name I/O Function A25 to A0* Output Address bus D15 to D0 I/O Data bus BS* Output Bus cycle start CS0 to CS4* Output Chip select RD/WR Output Read/write Connects to WE pins when SDRAM or SRAM with byte selection is connected. RD Output Read pulse signal (read data output enable signal) WE1/DQMU Output Indicates that D15 to D8 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D15 to D8 when SDRAM is connected. WE0/DQML Output Indicates that D7 to D0 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D7 to D0 when SDRAM is connected. RAS Output Connects to RAS pin when SDRAM is connected. CAS Output Connects to CAS pin when SDRAM is connected. CKE Output Connects to CKE pin when SDRAM is connected. Input External wait input WAIT Note: * With SH726A, the pin functions A25 to A23, A0, BS, CS1, CS2, and CS4 are not available. Page 236 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.3 Area Overview 10.3.1 Address Map Section 10 Bus State Controller In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cache-disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address. External address spaces CS0 to CS4 are cache-enabled when internal address A29 = 0 or cachedisabled when A29 = 1. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 10.2 Address Map Internal Address Space Memory to be Connected Cache H'00000000 to H'03FFFFFF CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) Cache-enabled H'04000000 to H'07FFFFFF CS1*2 H'08000000 to H'0BFFFFFF CS2* 2 H'0C000000 to H'0FFFFFFF CS3 Normal space, SRAM with byte selection, SDRAM H'10000000 to H'13FFFFFF CS4*2 Normal space, SRAM with byte selection, burst ROM (asynchronous) H'14000000 to H'1FFFFFFF Other SPI multi I/O bus space, on-chip RAM, reserved area*1 H'20000000 to H'23FFFFFF CS0 Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) H'24000000 to H'27FFFFFF CS1*2 H'28000000 to H'2BFFFFFF CS2* 2 H'2C000000 to H'2FFFFFFF CS3 Normal space, SRAM with byte selection, SDRAM H'30000000 to H'33FFFFFF CS4*2 Normal space, SRAM with byte selection, burst ROM (asynchronous) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Normal space, SRAM with byte selection Normal space, SRAM with byte selection, SDRAM Cache-disabled Normal space, SRAM with byte selection Normal space, SRAM with byte selection, SDRAM Page 237 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Internal Address Space Memory to be Connected Cache H'34000000 to H'3FFFFFFF Other SPI multi I/O bus space, on-chip RAM, reserved area*1 Cache-disabled H'40000000 to H'FFFBFFFF Other On-chip RAM, reserved area*1  H'FFFC0000 to H'FFFFFFFF Other On-chip peripheral modules, reserved area*1  Notes: 1. For the on-chip RAM space, access the addresses shown in section 30, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 34, List of Registers. Do not access addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed. 2. With SH726B, areas CS1, CS2, and CS4 are available. Page 238 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.3.2 Section 10 Bus State Controller Data Bus Width and Endian Specification for Each Area Depending on Boot Mode and Settings of Pins Related to This Module The initial state of data bus, endian specification, and settings of the pins related to this module depends on boot mode. For boot mode, refer to section 4, Boot Mode. In boot mode 0, the state of area 0 is fixed to the state with bus width of 16 bits and big endian, because this LSI is started up by the program stored in the ROM connected to area 0. The initial states of areas 1 to 4 are the same as that of area 0, but the bus width and endian can be changed by the program. In this mode, pin functions required to read ROM connected to area 0, such as some of addresses, data bus, CS0, and RD are selected automatically as the initial functions immediately after a power-on reset. The other pins are initially set as general ports, and cannot be used until specific functions are selected. Until pin function setting is completed, no accesses should be made except read access to area 0. In boot mode 1, the states of areas 0 to 4 can be changed from the initial state by the program because in this mode the LSI is started by the program stored in the serial flash memory. Since pin functions related to this module are not set automatically, they need to be set by the user. Until pin function setting is completed, no accesses should be made to external address space. Table 10.3 shows the initial state of areas in boot mode. The sample access waveforms shown in this section include the pins such as BS, RD/WR, and WEn. They are the waveforms when pin functions are assigned to the general I/O ports. When 8bit bus width is used in boot mode 0, setting for pin A0 is also needed. For details on pin function settings, see section 31, General Purpose I/O Ports. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 239 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.3 Initial States of Areas in Boot Mode Boot Mode Item Area 0 Areas 1 to 4 0 Data bus width Fixed to 16 bits. Not changeable. 16 bits as an initial value. Can be changed by program. Endian specification Fixed to big endian. Not changeable. Big endian as an initial value. Can be changed by program. Settings of pins related to this module Only the pin functions A20 to A1, D15 to D0, CS0, and RD are set automatically. Other pins need to be set by program. Data bus width 16 bits as an initial value. Can be changed by program. Endian specification Big endian as an initial value. Can be changed by program. Settings of pins related to this module General I/O function as an initial value. For external bus access, all the necessary pins need to be set by program. 1 Notes: 1. When a boot ROM to be connected uses address lines more significant than A21 in boot mode 0, such address lines need to be pulled down on the board. 2. Only a limited data bus width is available to some types of memory. For details, refer to section 10.4.2, CSn Space Bus Control Register (CSnBCR) (n = 0 to 4). 3. With SH726A, areas 1, 2, and 4 are not available; pins A25 to A23, A0, and BS cannot be selected. Page 240 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.4 Section 10 Bus State Controller Register Descriptions Table 10.4 shows the register configuration of this module. Do not access the areas until settings of the connected memory interface are completed. Table 10.4 Register Configuration R/W Initial Value Address Access Size Common control register CMNCR R/W H'00001010 H'FFFC0000 32 CS0 space bus control register CS0BCR R/W H'36DB0400 H'FFFC0004 32 CS1 space bus control register CS1BCR R/W H'36DB0400 H'FFFC0008 32 CS2 space bus control register CS2BCR R/W H'36DB0400 H'FFFC000C 32 CS3 space bus control register CS3BCR R/W H'36DB0400 H'FFFC0010 32 CS4 space bus control register CS4BCR R/W H'36DB0400 H'FFFC0014 32 CS0 space wait control register CS0WCR R/W H'00000500 H'FFFC0028 32 CS1 space wait control register CS1WCR R/W H'00000500 H'FFFC002C 32 CS2 space wait control register CS2WCR R/W H'00000500 H'FFFC0030 32 CS3 space wait control register CS3WCR R/W H'00000500 H'FFFC0034 32 CS4 space wait control register CS4WCR R/W H'00000500 H'FFFC0038 32 SDRAM control register SDCR R/W H'00000000 H'FFFC004C 32 Refresh timer control/status register RTCSR R/W H'00000000 H'FFFC0050 32 Refresh timer counter RTCNT R/W H'00000000 H'FFFC0054 32 Refresh time constant register RTCOR R/W H'00000000 H'FFFC0058 32 Register Name R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Abbreviation Page 241 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 - - - - - Initial value: R/W: 0 R 0 R 0 R 1 R 0 R Bit Bit Name Initial Value R/W Description 31 to 13  All 0 R Reserved DPRTY[1:0] 0 R/W 0 R/W DMAIW[2:0] 0 R/W 0 R/W 0 R/W 16 5 4 3 2 1 0 DMA IWA - - - HIZ MEM HIZ CNT* 0 R/W 1 R 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 12  1 R Reserved This bit is always read as 1. The write value should always be 1. 11  0 R Reserved This bit is always read as 0. The write value should always be 0. 10, 9 DPRTY[1:0] 00 R/W DMA Burst Transfer Priority Specify the priority for a refresh request during DMA burst transfer. 00: Accepts a refresh request during DMA burst transfer. 01: Reserved (setting prohibited) 10: Not accepts a refresh request during DMA burst transfer. 11: Reserved (setting prohibited) Page 242 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Initial Value Bit Bit Name 8 to 6 DMAIW[2:0] 000 R/W Description R/W Wait states between access cycles when DMA single address transfer is performed. Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 5 DMAIWA 0 R/W Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. However, when the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after an access to an external device with DACK, even when the continuous access cycles to an external device with DACK are performed. 0: Idle cycles inserted when another device drives the data bus after an external device with DACK drove it. 1: Idle cycles always inserted after an access to an external device with DACK 4  1 R Reserved This bit is always read as 1. The write value should always be 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 243 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in software standby mode or deep standby mode for A25 to A0, BS, CSn, RD/WR, WEn/DQMx, and RD. 0: High impedance in software standby mode or deep standby mode. 1: Driven in software standby mode or deep standby mode 0 HIZCNT* 0 R/W High-Z Control Specifies the state in software standby mode or deep standby mode for CKE, RAS, and CAS. 0: High impedance in software standby mode or deep standby mode for CKE, RAS, and CAS. 1: Driven in software standby mode or deep standby mode for CKE, RAS, and CAS. Note: * For High-Z control of CKIO, see section 5, Clock Pulse Generator. Page 244 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.4.2 Section 10 Bus State Controller CSn Space Bus Control Register (CSnBCR) (n = 0 to 4) CSnBCR is a 32-bit readable/writable register that specifies the memory connected to each space, the number of idle cycles between bus cycles, and the bus width. Do not access external memory for the corresponding area until CSnBCR initial setting and pin setting are completed. Idle cycles may be inserted even when they are not specified. For details, see section 10.5.9, Wait between Access Cycles. Bit: 31 30 - 29 28 27 IWW[2:0] Initial value: R/W: 0 R 0 R/W Bit: 15 14 - 26 25 24 IWRWD[2:0] 1 R/W 1 R/W 13 12 TYPE[2:0] 23 22 21 IWRWS[2:0] 20 19 18 IWRRD[2:0] 17 16 IWRRS[2:0] 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 11 10 9 8 7 6 5 4 3 2 1 0 BSZ[1:0] - - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ENDIAN Initial value: R/W: 0 R Bit Bit Name Initial Value R/W Description 31  0 R 30 to 28 IWW[2:0] 011 R/W Reserved This bit is always read as 0. The write value should always be 0. Idle Cycles between Write-Read Cycles and WriteWrite Cycles 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 245 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Initial Value Bit Bit Name 27 to 25 IWRWD[2:0] 011 R/W Description R/W Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous access cycles switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 24 to 22 IWRWS[2:0] 011 R/W Idle Cycles for Read-Write in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Page 246 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Initial Value Bit Bit Name 21 to 19 IWRRD[2:0] 011 R/W Description R/W Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles switch between different space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 18 to 16 IWRRS[2:0] 011 R/W Idle Cycles for Read-Read in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 15  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 247 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 14 to 12 TYPE[2:0] 000 R/W Specify the type of memory connected to a space. 000: Normal space 001: Burst ROM (clock asynchronous) 010: Reserved (setting prohibited) 011: SRAM with byte selection 100: SDRAM 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Burst ROM (clock synchronous) For details for memory type in each area, see table 10.2. Note: When connecting the burst ROM to the CS0 space in boot mode 0, change the CS0WCR register to the settings by the burst ROM CS0WCR uses and then set TYPE[2:0] to the burst ROM setting. In boot mode 1, memory access should be performed after setting CS0BCR and CS0WCR. 11 ENDIAN 0 R/W Endian Setting Specifies the arrangement of data in a space. 0: Arranged in big endian 1: Arranged in little endian Note: Little endian cannot be set for area 0 in boot mode 0. In this case, this bit of CS0BCR is always read as 0. The write value should always be 0. Page 248 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10, 9 BSZ[1:0] 10 R/W Data Bus Width Specification Specify the data bus widths of spaces. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: Reserved (setting prohibited) For MPX-I/O, selects bus width by address Notes: 1. In boot mode 0, the BSZ[1:0] bits settings in CS0BCR are ignored. 2. If area 2 or area 3 is specified as SDRAM space, the bus width can be specified as 16 bits. 3. If area 0 is specified as clocked synchronous burst ROM space, the bus width can be specified as 16 bits. 8 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 249 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 4) CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. (1) Normal Space, SRAM with Byte Selection  CS0WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - -* BAS - - -* -* Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 1 0 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21 * 0 R/W Reserved Set this bit to 0 when the interfaces for normal space or for SRAM with byte selection are used. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 6 5 4 3 2 WM - - - - 0 R/W 0 R 0 R 0 R 0 R HW[1:0] 0 R/W 0 R/W 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/ WR signal at the write timing. 19, 18  Page 250 of 1910 All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 17, 16 * All 0 R/W Reserved Set these bits to 0 when the interfaces for normal space or for SRAM with byte selection are used. 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS0 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS0 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 251 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored  5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 Delay Cycles from RD, WEn Negation to Address, CS0 Negation R/W Specify the number of delay cycles from RD and WEn negation to address and CS0 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Note: * To connect the burst ROM to the CS0 space and switch to burst ROM interface after activation, set the TYPE[2:0] bits in CS0BCR after setting the burst number by the bits 20 and 21 and the burst wait cycle number by the bits 16 and 17. Do not write 1 to the reserved bits other than above bits.  CS1WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - - BAS - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 1 0 - - - 0 R 0 R 0 R Initial value: R/W: Page 252 of 1910 SW[1:0] 0 R/W 0 R/W WR[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 18 17 16 WW[2:0] 6 5 4 3 2 WM - - - - 0 R/W 0 R 0 R 0 R 0 R HW[1:0] 0 R/W 0 R/W R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 253 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 254 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CSn Negation Specify the number of delay cycles from RD and WEn negation to address and CSn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles  CS2WCR, CS3WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - BAS - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 0 - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved WR[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 6 5 4 3 2 1 WM - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 255 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 256 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller  CS4WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 - - - - - - - - - - - BAS - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 1 0 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved SW[1:0] 0 R/W WR[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 18 17 16 WW[2:0] 6 5 4 3 2 WM - - - - 0 R/W 0 R 0 R 0 R 0 R HW[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 257 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Page 258 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W 10 to 7 WR[3:0] 1010 R/W Description Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 259 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller (2) Burst ROM (Clocked Asynchronous)  CS0WCR Bit: 31 30 29 28 27 26 25 24 23 22 - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved W[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 21 20 19 18 - - 0 R/W 0 R 0 R 0 R/W 0 R/W 0 BST[1:0] 17 16 BW[1:0] 6 5 4 3 2 1 WM - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 21, 20 BST[1:0] 00 R/W Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11, because B’11 setting is reserved. Bus Width BST[1:0] Burst count 8 bits 00 16 burst  one time 01 4 burst  four times 00 8 burst  one time 16 bits 19, 18  All 0 R 01 2 burst  four times 10 4-4 or 2-4-2 burst Reserved These bits are always read as 0. The write value should always be 0. Page 260 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W 17, 16 BW[1:0] 00 R/W Description Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 261 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored  5 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.  CS4WCR Bit: 31 30 29 28 27 26 25 24 23 22 - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15 14 13 12 11 10 9 8 7 - - - Initial value: R/W: 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 22  All 0 R Reserved SW[1:0] 0 R/W W[3:0] 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 21 20 19 18 - - 0 R/W 0 R 0 R 0 R/W 0 R/W 0 BST[1:0] 17 16 BW[1:0] 6 5 4 3 2 1 WM - - - - HW[1:0] 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. Page 262 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 21, 20 BST[1:0] 00 R/W Burst Count Specification Specify the burst count for 16-byte access. These bits must not be set to B'11, because B'11 setting is reserved. Bus Width BST[1:0] Burst count 8 bits 00 16 burst  one time 01 4 burst  four times 00 8 burst  one time 01 2 burst  four times 10 4-4 or 2-4-2 burst 16 bits 19, 18  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 263 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W 10 to 7 W[3:0] 1010 R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Page 264 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 10 Bus State Controller SDRAM*  CS2WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - A2CL[1:0] - - - - - - - 0 R 0 R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Initial value: R/W: 1 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0.  10 1 R Reserved This bit is always read as 1. The write value should always be 1.  9 0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A2CL[1:0] 10 R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles  6 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 265 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller  CS3WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 4 3 2 1 0 - Initial value: R/W: 0 R WTRP[1:0]* 0 R/W 0 R/W 9 8 7 6 5 - WTRCD[1:0]* - A3CL[1:0] - - 0 R 0 R/W 0 R 0 R 0 R 1 R/W 1 R/W 0 R/W TRWL[1:0]* 0 R/W 0 R/W - 0 R WTRC[1:0]* 0 R/W 0 R/W Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. Bit Bit Name Initial Value R/W Description 31 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14, 13 WTRP[1:0]* 00 R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles as shown below.  From the start of auto-precharge and issuing of ACTV command for the same bank  From issuing of the PRE/PALL command to issuing of the ACTV command for the same bank  Till entering the power-down mode or deep powerdown mode  From the issuing of PALL command to issuing REF command in auto refresh mode  From the issuing of PALL command to issuing SELF command in self refresh mode The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Page 266 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD[1:0]* 01 R/W Number of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 267 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Initial Value Bit Bit Name 4, 3 TRWL[1:0]* 00 R/W Description R/W Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum auto-precharge startup wait cycles as shown below.  Cycle number from the issuance of the WRITA command by this LSI until the completion of autoprecharge in the SDRAM. Equivalent to the cycle number from the issuance of the WRITA command until the issuance of the ACTV command. Confirm that how many cycles are required between the WRITA command receive in the SDRAM and the auto-precharge activation, referring to each SDRAM data sheet. And set the cycle number so as not to exceed the cycle number specified by this bit.  Cycle number from the issuance of the WRIT command until the issuance of the PRE command. This is the case when accessing another low address in the same bank in bank active mode. The setting for areas 2 and 3 is common. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 268 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Initial Value Bit Bit Name 1, 0 WTRC[1:0]* 00 R/W Description R/W Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the periods shown below.  From the issuance of the REF command until the issuance of the ACTV/REF/MRS command  From releasing self-refresh until the issuance of the ACTV/REF/MRS command. The setting for areas 2 and 3 is common. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0], and WTRC[1:0] bit settings are used in both areas in common. If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2 as normal space or SRAM with byte selection. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 269 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller (4) Burst ROM (Clocked Synchronous)  CS0WCR Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 0 - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 31 to 18  All 0 R Reserved W[3:0] 1 R/W 0 R/W 1 R/W 0 R/W 17 16 BW[1:0] 6 5 4 3 2 1 WM - - - - - - 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 270 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W 10 to 7 W[3:0] 1010 R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 271 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit: 31 30 29 28 27 26 25 24 23 22 21 - - - - - - - - - - - A2ROW[1:0] - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - DEEP - RFSH RMODEPDOWN BACTV - - - 0 R 0 R 0 R/W 0 R 0 R/W 0 R 0 R 0 R Initial value: R/W: 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 31 to 21  All 0 R Reserved 20 19 A3ROW[1:0] 0 R/W 0 R/W 18 17 0 R/W 0 R/W 1 0 - 0 R 16 A2COL[1:0] A3COL[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 20, 19 A2ROW[1:0] 00 R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 18  0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 A2COL[1:0] 00 R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) Page 272 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low-power SDRAM enters the deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11 RFSH 0 R/W Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh 10 RMODE 0 R/W Refresh Control Specifies whether to perform auto-refresh or selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 273 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 9 PDOWN 0 R/W Power-Down Mode Specifies whether the SDRAM will enter the powerdown mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters the power-down mode. 0: The SDRAM does not enter the power-down mode after being accessed. 1: The SDRAM enters the power-down mode after being accessed. 8 BACTV 0 R/W Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be set only for area 3. When both areas 2 and 3 are set to SDRAM, specify the auto-precharge mode. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4, 3 A3ROW[1:0] 00 R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 274 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Initial Value Bit Bit Name 1, 0 A3COL[1:0] 00 R/W Description R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 275 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on reset. Note that there is an error in the time until the compare match flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value other than B'000. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - CMF CMIE 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved CKS[2:0] 0 R/W 0 R/W 16 RRC[2:0] 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. 7 CMF 0 R/W Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied. 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables CMF interrupt requests when the CMF bit in RTCSR is set to 1. 0: Disables CMF interrupt requests. 1: Enables CMF interrupt requests. Page 276 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Bit Bit Name Initial Value R/W Description 5 to 3 CKS[2:0] 000 R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: B/4 010: B/16 011: B/64 100: B/256 101: B/1024 110: B/2048 111: B/4096 2 to 0 RRC[2:0] 000 R/W Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: 1 time 001: 2 times 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 277 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved 16 These bits are always read as 0. 7 to 0 Page 278 of 1910 All 0 R/W 8-Bit Counter R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.4.7 Section 10 Bus State Controller Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests are counted by using timer interrupts while refresh is performed periodically. When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 31 to 8  All 0 R Reserved 16 These bits are always read as 0. 7 to 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 All 0 R/W 8-Bit Counter Page 279 of 1910 Section 10 Bus State Controller 10.5 Operation 10.5.1 Endian/Access Size and Data Alignment SH726A Group, SH726B Group This LSI supports both big endian, in which the most significant byte (MSB) of data is that in the direction of the 0th address, and little endian, in which the least significant byte (LSB) is that in the direction of the 0th address. In the initial state after a power-on reset, all areas will be in big endian mode. Endian mode can be changed by setting the CSnBCR register as long as the target space is not being accessed. Data bus width can be selected from 8 bits and 16 bits for the normal memory and SRAM with byte selection. It is fixed to 16 bits for SDRAM. Endian specification and data bus width varies depending on boot mode. For details, refer to section 10.3.2, Data Bus Width and Endian Specification for Each Area Depending on Boot Mode and Settings of Pins Related to This Module. Data alignment is performed in accordance with the data bus width selected for the device. This also means that four read operations are required to read longword data from a byte-width device. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 10.5 to 10.8 show the relationship between device data width and access unit. Note that the correspondence between addresses and strobe signals for the 16-bit bus width depends on the endian setting. For example, with big endian and a 16-bit bus width, WE1 corresponds to the 0th address, which is represented by WE0 when little endian has been selected. Since instructions are fetched with both 32- and 16-bit accesses, their alignment in the little-endian area is difficult. Execute instructions from big-endian area. Page 280 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.5 16-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals WE1, DQMU WE0, DQML Operation D15 to D8 D7 to D0 Byte access at address 0 Data 7 to 0  Assert  Byte access at address 1  Data 7 to 0  Assert Byte access at address 2 Data 7 to 0  Assert  Byte access at address 3  Data 7 to 0  Assert Word access at address 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at address 2 Data 15 to 8 Data 7 to 0 Assert Assert Longword access at address 0 1st access at address 0 Data 31 to 24 Data 23 to 16 Assert Assert 2nd access at address 2 Data 15 to 8 Data 7 to 0 Assert Assert Table 10.6 8-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WE1, DQMU WE0, DQML Byte access at address 0  Data 7 to 0  Assert Byte access at address 1  Data 7 to 0  Assert Byte access at address 2  Data 7 to 0  Assert Byte access at address 3  Data 7 to 0  Assert Word access at address 0 1st access at address 0  Data 15 to 8  Assert 2nd access at address 1  Data 7 to 0  Assert 1st access at address 2  Data 15 to 8  Assert 2nd access at address 3  Data 7 to 0  Assert 1st access at address 0  Data 31 to 24  Assert 2nd access at address 1  Data 23 to 16  Assert 3rd access at address 2  Data 15 to 8  Assert 4th access at address 3  Data 7 to 0  Assert Word access at address 2 Longword access at address 0 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 281 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.7 16-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WE1, DQMU WE0, DQML Byte access at address 0  Data 7 to 0  Assert Byte access at address 1 Data 7 to 0  Assert  Byte access at address 2  Data 7 to 0  Assert Byte access at address 3 Data 7 to 0  Assert  Word access at address 0 Data 15 to 8 Data 7 to 0 Assert Assert Word access at address 2 Data 15 to 8 Data 7 to 0 Assert Assert Longword access at address 0 1st access at address 0 Data 15 to 8 Data 7 to 0 Assert Assert 2nd access at address 2 Data 31 to 24 Data 23 to 16 Assert Assert Table 10.8 8-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals Operation D15 to D8 D7 to D0 WE1, DQMU WE0, DQML Byte access at address 0  Data 7 to 0  Assert Byte access at address 1  Data 7 to 0  Assert Byte access at address 2  Data 7 to 0  Assert Byte access at address 3  Data 7 to 0  Assert Word access at address 0 1st access at address 0  Data 7 to 0  Assert 2nd access at address 1  Data 15 to 8  Assert 1st access at address 2  Data 7 to 0  Assert 2nd access at address 3  Data 15 to 8  Assert 1st access at address 0  Data 7 to 0  Assert 2nd access at address 1  Data 15 to 8  Assert 3rd access at address 2  Data 23 to 16  Assert 4th access at address 3  Data 31 to 24  Assert Word access at address 2 Longword access at address 0 Page 282 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.5.2 (1) Section 10 Bus State Controller Normal Space Interface Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 10.5.7, SRAM Interface with Byte Selection. Figure 10.2 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 T2 CKIO A25 to A0 CSn RD/WR Read RD D15 to D0 RD/WR Write WEn D15 to D0 BS DACKn * Note: * The waveform for DACKn is when active low is specified. Figure 10.2 Normal Space Basic Access Timing (Access Wait 0, Word Access) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 283 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 16 bits are always read in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is asserted. It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer with this signal, to avoid output collision. Figures 10.3 and 10.4 show the basic timings in continuous access to normal space. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait (figure 10.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 10.4). T1 T2 Tnop T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 10.3 Continuous Access to Normal Space (1) Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) Page 284 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 10.4 Continuous Access to Normal Space (2) Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 285 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 128K × 8-bit SRAM •••• A0 CS OE I/O7 •••• I/O0 WE •••• •••• •••• D0 WE0 A16 •••• •••• D8 WE1 D7 A0 CS OE I/O7 •••• •••• A1 CSn RD D15 A16 •••• •••• •••• A17 •••• This LSI I/O0 WE Figure 10.5 Example of 16-Bit Data-Width SRAM Connection 128K × 8-bit SRAM This LSI A0 CS RD OE D7 I/O7 ... A0 CSn ... ... A16 ... A16 D0 I/O0 WE0 WE Figure 10.6 Example of 8-Bit Data-Width SRAM Connection Page 286 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.5.3 Section 10 Bus State Controller Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 1 and 4 to insert wait cycles independently in read access and in write access. Areas 0, 2, and 3 have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 10.7. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.7 Wait Timing for Normal Space Access (Software Wait Only) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 287 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 10.8. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. T1 Tw Tw Wait states inserted by WAIT signal Twx T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.8 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT Signal) Page 288 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.5.4 Section 10 Bus State Controller CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 10.9 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.9 CSn Assert Period Expansion R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 289 of 1910 Section 10 Bus State Controller 10.5.5 (1) SH726A Group, SH726B Group SDRAM Interface SDRAM Direct Connection The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMU, DQML, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid only when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM is 16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals. These commands supports:  NOP  Auto-refresh (REF)  Self-refresh (SELF)  All banks pre-charge (PALL)  Specified bank pre-charge (PRE)  Bank active (ACTV)  Read (READ)  Read with pre-charge (READA)  Write (WRIT)  Write with pre-charge (WRITA)  Write mode register (MRS, EMRS) The byte to be accessed is specified by DQMU and DQML. Reading or writing is performed for a byte whose corresponding DQMx is low. For details on the relationship between DQMx and the byte to be accessed, see section 10.5.1, Endian/Access Size and Data Alignment. Page 290 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Figure 10.10 shows an example of the connection of the SDRAM with the LSI. 64M SDRAM (1M × 16-bit × 4-bank) A1 CKE CKIO CSn ... RAS CAS RD/WR D15 D0 DQMU DQML A13 ... ... A14 A0 CKE CLK CS RAS CAS WE I/O15 ... This LSI I/O0 DQMU DQML Figure 10.10 Example of 16-Bit Data Width SDRAM Connection (2) Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR and bits A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 10.9 to 10.11 show the relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 291 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A25 A17 A16 A24 A16 A15 A23 A15 A14 A22 A14 A13 A21 A12 A20* SDRAM Pin Function Unused A21 2 A20* 2 1 A11 (BA0) Specifies bank A10/AP Specifies address/precharge Address A11 A19 L/H* A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 A0 A8 A0 Unused Example of connected memory 16-Mbit product (512 Kwords  16 bits  2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 292 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.9 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A25 A17 A16 A24 A16 A15 A23 Function Unused A15 A22* 2 A13 A21* 2 A12 A20 A14 SDRAM Pin A22* 2 A13 (BA1) A21* 2 A12 (BA0) A12 1 Specifies bank A11 Address A10/AP Specifies address/precharge Address A11 A19 L/H* A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 A0 A8 A0 Unused Example of connected memory 64-Mbit product (1 Mword  16 bits  4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 293 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.10 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A26 A17 A16 A25 A16 A15 A24 Function Unused A15 A14 A23* 2 A13 A22* 2 A12 A21 A11 SDRAM Pin A20 A23* 2 A13 (BA1) A22* 2 A12 (BA0) A12 L/H* 1 Specifies bank A11 Address A10/AP Specifies address/precharge Address A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 A0 A9 A0 Unused Example of connected memory 128-Mbit product (2 Mwords  16 bits  4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Page 294 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.10 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (2)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A27 A17 A16 A26 A16 A15 A25 Function Unused A15 A14 A24* 2 A13 A23* 2 A12 A22 A11 SDRAM Pin A21 A24* 2 A13 (BA1) A23* 2 A12 (BA0) A12 L/H* 1 Specifies bank A11 Address A10/AP Specifies address/precharge Address A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 A0 A10 A0 Unused Example of connected memory 256-Mbit product (4 Mwords  16 bits  4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 295 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3)-1 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A26 A17 A16 A25 A15 A14 SDRAM Pin Function Unused A16 A24* 2 A23* 2 A24* 2 A14 (BA1) A23* 2 A13 (BA0) A13 A22 A13 A12 A12 A21 A12 A11 A11 A20 L/H* A10 A19 A9 1 Specifies bank Address A10/AP Specifies address/precharge A10 A9 Address A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 A0 A9 A0 Unused Example of connected memory 256-Mbit product (4 Mwords  16 bits  4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Page 296 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.11 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (3)-2 Setting BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle A17 A27 A17 A16 A26 A15 A14 SDRAM Pin Function Unused A16 A25* 2 A24* 2 A25* 2 A14 (BA1) A24* 2 A13 (BA0) A13 A23 A13 A12 A12 A22 A12 A11 A11 A21 L/H* A10 A20 A9 1 Specifies bank Address A10/AP Specifies address/precharge A10 A9 Address A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 A0 A10 A0 Unused Example of connected memory 512-Mbit product (8 Mwords  16 bits  4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 297 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller (3) Burst Read A burst read occurs in the following cases with this LSI.  Access size in reading is larger than data bus width.  16-byte transfer in cache miss.  16-byte transfer in the direct memory access controller This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that is connected to a 16-bit data bus. This access is called the burst read with the burst number 8. Table 10.12 shows the relationship between the access size and the number of bursts. Table 10.12 Relationship between Access Size and Number of Bursts Bus Width Access Size Number of Bursts 16 bits 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 Page 298 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Figures 10.11 and 10.12 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM in variable frequencies. Figure 10.12 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycle or more, a Trw cycle where the NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 299 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.11 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) Page 300 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Tr Section 10 Bus State Controller Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.12 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD[1:0] = 1 Cycle, Auto Pre-Charge) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 301 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller (4) Single Read A read access ends in one cycle when data exists in a cache-disabled space and the data bus width is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst length 1, only the required data is output. A read access that ends in one cycle is called single read. Figure 10.13 shows the single read basic timing. Tr Tc1 Td1 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.13 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge) Page 302 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (5) Section 10 Bus State Controller Burst Write A burst write occurs in the following cases in this LSI.  Access size in writing is larger than data bus width.  Write-back of the cache  16-byte transfer in the direct memory access controller This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 8 times to write 16-byte continuous data to the SDRAM that is connected to a 16-bit data bus. This access is called burst write with the burst number 8. The relationship between the access size and the number of bursts is shown in table 10.12. Figure 10.14 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the auto-precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 303 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tr Tc1 Tc2 Tc3 Tc4 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.14 Basic Timing for Burst Write (Auto Pre-Charge) Page 304 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (6) Section 10 Bus State Controller Single Write A write access ends in one cycle when data is written in a cache-disabled space and the data bus width is larger than or equal to access size. As a single write or burst write with burst length 1 is set in SDRAM, only the required data is output. The write access that ends in one cycle is called single write. Figure 10.15 shows the single write basic timing. Tr Tc1 Trwl Tap CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.15 Single Write Basic Timing (Auto-Precharge) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 305 of 1910 Section 10 Bus State Controller (7) SH726A Group, SH726B Group Bank Active The SDRAM bank function can be used to support high-speed access to the same row address. When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for area 3. When area 3 is set to bank-active mode, area 2 should be set to normal space or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM, auto precharge mode must be set. When the bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As SDRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 10.16, a burst read cycle for the same row address in figure 10.17, and a burst read cycle for different row addresses in figure 10.18. Similarly, a single write cycle without auto-precharge is shown in figure 10.19, a single write cycle for the same row address in figure 10.20, and a single write cycle for different row addresses in figure 10.21. In figure 10.17, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMx signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMx signal is asserted after the Tc cycle. Page 306 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller When bank active mode is set, if only access cycles to the respective banks in the area 3 space are considered, as long as access cycles to the same row address continue, the operation starts with the cycle in figure 10.16 or 10.19, followed by repetition of the cycle in figure 10.17 or 10.20. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, the bus cycle in figure 10.18 or 10.21 is executed instead of that in figure 10.17 or 10.20. In bank active mode, too, all banks become inactive after a refresh cycle. Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.16 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 307 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tnop Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.17 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) Page 308 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Tp Section 10 Bus State Controller Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.18 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 309 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tr Tc1 CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.19 Single Write Timing (Bank Active, Different Bank) Page 310 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Tnop Tc1 CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.20 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 311 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tp Tpw Tr Tc1 CKIO A25 to A0 A12/A11*1 CS3 RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.21 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) (8) Refreshing This module has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. Page 312 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (a) Section 10 Bus State Controller Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, and then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an autorefresh is performed for the number of times specified by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.22 shows the auto-refresh cycle timing. After starting the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 313 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tp Tpw Trr Trc Trc Trc CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 Hi-z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.22 Auto-Refresh Timing Page 314 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (b) Section 10 Bus State Controller Self-refreshing Self-refresh mode is a kind of standby mode, in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR. Self-refresh timing is shown in figure 10.23. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, autorefreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when selfrefresh mode is cleared. If the transition from clearing of self-refresh mode to the start of autorefreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby state by setting the HIZCNT bit in CMNCR to 1. When the multiplication rate for the PLL circuit is changed, the CKIO output will become unstable or will be fixed low. For details on the CKIO output, see section 5, Clock Pulse Generator. The contents of SDRAM can be retained by placing the SDRAM in the self-refresh state before changing the multiplication rate. The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 315 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Tp Tpw Trr Trc Trc Trc CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 Hi-z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.23 Self-Refresh Timing Page 316 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (9) Section 10 Bus State Controller Relationship between Refresh Requests and Bus Cycles If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval must be prevented from occurring. (10) Power-Down Mode If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel the power-down mode. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 317 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Figure 10.24 shows the access timing in power-down mode. Power-down Tnop Tr Tc1 Td1 Tde Tap Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.24 Power-Down Mode Access Timing Page 318 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller (11) Power-On Sequence In order to use SDRAM, mode setting must first be made for SDRAM after the pose interval specified for the SDRAM to be used after powering on. The pose interval should be obtained by a power-on reset generating circuit or software. To perform SDRAM initialization correctly, the registers of this module must first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a word write to address H'FFFC4000 + X for area 2 SDRAM, and to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write or burst read/burst write (CAS latency 2 to 3, wrap type = sequential, and burst length 1) supported by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 10.13. In this time 0 is output at the external address pins of A12 or later. Table 10.13 Access Address in SDRAM Mode Register Write  Setting for Area 2 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC4440 H'0000440 3 H'FFFC4460 H'0000460 Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC4040 H'0000040 3 H'FFFC4060 H'0000060 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 319 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller  Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC5440 H'0000440 3 H'FFFC5460 H'0000460 Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFFC5040 H'0000040 3 H'FFFC5060 H'0000060 Mode register setting timing is shown in figure 10.25. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. One or more idle cycles are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer than the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Page 320 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Tp PALL Tpw Section 10 Bus State Controller Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx Hi-Z D15 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.25 SDRAM Mode Write Timing (Based on JEDEC) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 321 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller (12) Low-Power SDRAM The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which the data in a work area other than the specific area can be lost without severe repercussions. For details, please refer to the Data Sheet for the low-power SDRAM to be used. The low-power SDRAM supports the extension mode register in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the extension mode register write command (EMRS). The EMRS command is issued according to the conditions specified in table below. For example, if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> REF  8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS. Table 10.14 Output Addresses when EMRS Command Is Issued Access Data Write Access Size MRS EMRS Command Command Issue Address Issue Address H'FFFC4XX0 H'******** 16 bits H'0000XX0  CS3 MRS H'FFFC5XX0 H'******** 16 bits H'0000XX0  CS2 MRS + EMRS H'FFFC4XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC5XX0 H'0YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC4XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY H'FFFC5XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY Command to be Issued Access Address CS2 MRS (with refresh) CS3 MRS + EMRS (with refresh) CS2 MRS + EMRS (without refresh) CS3 MRS + EMRS (without refresh) Page 322 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Tpw Tp PALL Section 10 Bus State Controller Trr REF Trc Trc Trr REF Trc Trc Tmw Tnop Temw Tnop EMRS MRS CKIO A25 to A0 BA1*1 BA0*2 A12/A11*3 CSn RAS CAS RD/WR DQMx D15 to D0 Hi-Z BS DACKn*4 Notes: 1. Address pin to be connected to pin BA1 of SDRAM. 2. Address pin to be connected to pin BA0 of SDRAM. 3. Address pin to be connected to pin A10 of SDRAM. 4. The waveform for DACKn is when active low is specified. Figure 10.26 EMRS Command Issue Timing R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 323 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller  Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed. Tp Tpw Tdpd Trc Trc Trc Trc Trc CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMx D15 to D0 Hi-Z BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 10.27 Deep Power-Down Mode Transition Timing Page 324 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.5.6 Section 10 Bus State Controller Burst ROM (Clocked Asynchronous) Interface The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. In a burst ROM (clocked asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent access cycles are performed only by changing the address, without negating the RD signal at the end of the 1st cycle. In the 2nd and subsequent access cycles, addresses are changed at the falling edge of the CKIO. For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the BW1 and BW0 bits in CSnWCR is inserted. In the access to the burst ROM (clocked asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access or write access that does not perform the burst operation in the burst ROM (clocked asynchronous) interface, access timing is same as a normal space. Table 10.15 lists a relationship between bus width, access size, and the number of bursts. Figure 10.28 shows a timing chart. Table 10.15 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count 8 bits 8 bits Not affected 1 1 16 bits Not affected 2 1 32 bits Not affected 4 1 16 bytes 00 16 1 01 4 4 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 325 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count 16 bits 8 bits Not affected 1 1 16 bits Not affected 1 1 32 bits Not affected 2 1 16 bytes 00 8 1 01 2 4 10* 4 2 2, 4, 2 3 Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in CSnWCR are 10, the number of bursts and access count depend on the access start address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4 or H'xxxC, 2-4-2 burst access is performed. T1 Tw Tw T2B Twb T2B Twb T2B Twb T2 CKIO A25 to A0 CSn RD/WR RD D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.28 Burst ROM Access Timing (Clocked Asynchronous) (Bus Width = 16 Bits, 16-Byte Transfer (Number of Burst 4-4), Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) Page 326 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.5.7 Section 10 Bus State Controller SRAM Interface with Byte Selection The SRAM interface with byte selection is a memory interface that outputs the byte selection signal (WEn) in both read and write bus cycles. This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte selection is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 10.29. In write access, data is written to the memory according to the timing of the byteselection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 10.30 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 10.31 shows the access timing when a software wait is specified. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 327 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller T2 T1 CKIO A25 to A0 CSn WEn RD/WR Read RD D15 to D0 RD/WR Write RD High D15 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.29 Basic Access Timing for SRAM with Byte Selection (BAS = 0) Page 328 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller T1 T2 CKIO A25 to A0 CSn WEn RD/WR RD Read D15 to D0 RD/WR High RD Write D15 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.30 Basic Access Timing for SRAM with Byte Selection (BAS = 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 329 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Th T1 Tw T2 Tf CKIO A25 to A0 CSn WEn RD/WR RD Read D15 to D0 RD/WR High RD Write D15 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.31 Wait Timing for SRAM with Byte Selection (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) Page 330 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller 64K × 16-bit SRAM This LSI A16 .. . A1 A15 .. . A0 CSn CS RD OE RD/WR D15 .. . D0 WE1 WE0 WE I/O15 . .. I/O0 UB LB Figure 10.32 Example of Connection with 16-Bit Data-Width SRAM with Byte Selection R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 331 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller 10.5.8 Burst ROM (Clocked Synchronous) Interface The burst ROM (clocked synchronous) interface is supported to access a ROM with a synchronous burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only for area 0. In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by the BW1 and BW0 bits in CS0WCR. While the burst ROM (clocked synchronous) is accessed, the BS signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. Since the bus width is 16 bits, the burst length must be specified as 8. The burst ROM interface does not support the 8-bit bus width for the burst ROM. The burst ROM interface performs burst operations for all read access. For example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, it is recommended using a 16-byte read by cache fill in the cache-enabled spaces or 16-byte read by the DMA. The burst ROM interface performs write access in the same way as normal space access. T1 Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2 CKIO A25 to A0 CS0 RD/WR RD D15 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 10.33 Burst ROM Access Timing (Clocked Synchronous) (Burst Length = 8, Wait Cycles Inserted in First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1) Page 332 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 10.5.9 Section 10 Bus State Controller Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting idle (wait) cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by the WM bit in CSnWCR, bits IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and IWRRS2 to IWRRS0 in CSnBCR, and bits DMAIW2 to DMAIW0 and DMAIWA in CMNCR. The conditions for setting the idle cycles between access cycles are shown below. 1. Continuous access cycles are write-read or write-write 2. Continuous access cycles are read-write for different spaces 3. Continuous access cycles are read-write for the same space 4. Continuous access cycles are read-read for different spaces 5. Continuous access cycles are read-read for the same space 6. Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single address transfer is followed by any type of access (DMAIWA = 1) For the specification of the number of idle cycles between access cycles described above, refer to the description of each register. Besides the idle cycles between access cycles specified by the registers, idle cycles must be inserted to interface with the internal bus or to obtain the minimum pulse width for a multiplexed pin (WEn). The following gives detailed information about the idle cycles and describes how to estimate the number of idle cycles. The number of idle cycles on the external bus from CSn negation to CSn or CSm assertion is described below. There are eight conditions that determine the number of idle cycles on the external bus as shown in table 10.16. The effects of these conditions are shown in figure 10.34. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 333 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.16 Conditions for Determining Number of Idle Cycles No. Condition Description [1] DMAIW[2:0] in CMNCR These bits specify the number of 0 to 12 idle cycles for DMA single address transfer. This condition is effective only for single address transfer and generates idle cycles after the access is completed. When 0 is specified for the number of idle cycles, the DACK signal may be asserted continuously. This causes a discrepancy between the number of cycles detected by the device with DACK and the direct memory access controller transfer count, resulting in a malfunction. [2] IW***[2:0] in CSnBCR These bits specify the number of 0 to 12 idle cycles for access other than single address transfer. The number of idle cycles can be specified independently for each combination of the previous and next cycles. For example, in the case where reading CS1 space followed by reading other CS space, the bits IWRRD[2:0] in CS1BCR should be set to B'100 to specify six or more idle cycles. This condition is effective only for access cycles other than single address transfer and generates idle cycles after the access is completed. Do not set 0 for the number of idle cycles between memory types which are not allowed to be accessed successively. [3] SDRAM-related These bits specify precharge 0 to 3 bits in completion and startup wait cycles CSnWCR and idle cycles between commands for SDRAM access. This condition is effective only for SDRAM access and generates idle cycles after the access is completed Page 334 of 1910 Range Note Specify these bits in accordance with the specification of the target SDRAM. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller No. Condition Description [4] WM in CSnWCR This bit enables or disables external 0 or 1 WAIT pin input for the memory types other than SDRAM. When this bit is cleared to 0 (external WAIT enabled), one idle cycle is inserted to check the external WAIT pin input after the access is completed. When this bit is set to 1 (disabled), no idle cycle is generated. [5] Read data transfer cycle One idle cycle is inserted after a 0 or 1 read access is completed. This idle cycle is not generated for the first or middle cycles in divided access cycles. This is neither generated when the HW[1:0] bits in CSnWCR are not B'00. [6] Internal bus External bus access requests from 0 or idle cycles, etc. the CPU or the direct memory larger access controller and their results are passed through the internal bus. The external bus enters idle state during internal bus idle cycles or while a bus other than the external bus is being accessed. This condition is not effective for divided access cycles, which are generated by the bus state controller when the access size is larger than the external data bus width. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Range Note One idle cycle is always generated after a read cycle with SDRAM interface. The number of internal bus idle cycles may not become 0 depending on the I:B clock ratio. Tables 10.17 and 10.18 show the relationship between the clock ratio and the minimum number of internal bus idle cycles. Page 335 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller No. Condition Description Range Note [7] Write data wait During write access, a write cycle is 0 or 1 cycles executed on the external bus only after the write data becomes ready. This write data wait period generates idle cycles before the write cycle. Note that when the previous cycle is a write cycle and the internal bus idle cycles are shorter than the previous write cycle, write data can be prepared in parallel with the previous write cycle and therefore, no idle cycle is generated (write buffer effect). For write  write or write  read access cycles, successive access cycles without idle cycles are frequently available due to the write buffer effect described in the left column. If successive access cycles without idle cycles are not allowed, specify the minimum number of idle cycles between access cycles through CSnBCR. [8] Idle cycles between different memory types The number of idle cycles depends on the target memory types. See table 10.19. Page 336 of 1910 To ensure the minimum pulse width 0 to 2.5 on the signal-multiplexed pins, idle cycles may be inserted before access after memory types are switched. For some memory types, idle cycles are inserted even when memory types are not switched. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller In the above conditions, a total of four conditions, that is, condition [1] or [2] (either one is effective), condition [3] or [4] (either one is effective), a set of conditions [5] to [7] (these are generated successively, and therefore the sum of them should be taken as one set of idle cycles), and condition [8] are generated at the same time. The maximum number of idle cycles among these four conditions become the number of idle cycles on the external bus. To ensure the minimum idle cycles, be sure to make register settings for condition [1] or [2]. CKIO External bus idle cycles Previous access Next access CSn Idle cycle after access Idle cycle before access [1] DMAIW[2:0] setting in CMNCR [2] IWW[2:0] setting in CSnBCR IWRWD[2:0] setting in CSnBCR IWRWS[2:0] setting in CSnBCR IWRRD[2:0] setting in CSnBCR IWRRS[2:0] setting in CSnBCR [3] WTRP[1:0] setting in CSnWCR TRWL[1:0] setting in CSnWCR WTRC[1:0] setting in CSnWCR Either one of them is effective Condition [1] or [2] Either one of them is effective Condition [3] or [4] [4] WM setting in CSnWCR [5] Read data transfer [6] Internal bus idle cycles, etc. [7] Write data wait Set of conditions [5] to [7] [8] Idle cycles between Condition [8] different memory types Note: A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7], and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of cycles among these four conditions become the number of idle cycles. Figure 10.34 Idle Cycle Conditions R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 337 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.17 Minimum Number of Idle Cycles on Internal Bus (CPU Operation) Clock Ratio (I:B) CPU Operation 8:1 6:1 4:1 3:1 2:1 1:1 Write  write 1 1 2 2 2 3 Write  read 0 0 0 0 0 1 Read  write 1 1 2 2 2 3 Read  read 0 0 0 0 0 1 Table 10.18 Minimum Number of Idle Cycles on Internal Bus (Direct Memory Access Controller Operation) Transfer Mode Direct Memory Access Controller Operation Dual Address Single Address Write  write 0 2 Write  read 0 or 2 0 Read  write 0 0 Read  read 0 2 Notes: 1. The write  write and read  read columns in dual address transfer indicate the cycles in the divided access cycles. 2. For the write  read cycles in dual address transfer, 0 means different channels are activated successively and 2 means when the same channel is activated successively. 3. The write  read and read  write columns in single address transfer indicate the case when different channels are activated successively. The "write" means transfer from a device with DACK to external memory and the "read" means transfer from external memory to a device with DACK. Page 338 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller Table 10.19 Number of Idle Cycles Inserted between Access Cycles to Different Memory Types Next Cycle Burst ROM Byte SRAM Byte SRAM Burst ROM Previous Cycle SRAM (Asynchronous) (BAS = 0) (BAS = 1) SRAM 0 0 0 0/1* 0/1* 0 Burst ROM 0 0 0 0/1* 0/1* 0 0 0 0 0/1* 0/1* 0 0/1* 0/1* 0/1* 0 0 0/1* SDRAM 1 1 1 0 0 1 Burst ROM 0 0 0 1 1 0 SDRAM (Synchronous) (asynchronous) Byte SRAM (BAS = 0) Byte SRAM (BAS = 1) (synchronous) Note: * The number of idle cycles is determined by the setting of the CSnWCR.HW[1:0] bits on the previous cycle. The number of idle cycles will be the number shown at the left when HW[1:0] ≠ B'00, will be the number shown at the right when HW[1:0] = B'00. Also, for CSn spaces for which the CSnWCR.HW[1:0] bits do not exist, the number of idle cycles shown at the right will be used. Figure 10.35 shows sample estimation of idle cycles between access cycles. In the actual operation, the idle cycles may become shorter than the estimated value due to the write buffer effect or may become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU instruction execution or CPU register conflicts. Please consider these errors when estimating the idle cycles. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 339 of 1910 SH726A Group, SH726B Group Section 10 Bus State Controller Sample Estimation of Idle Cycles between Access Cycles This example estimates the idle cycles for data transfer from the CS1 space to CS2 space by CPU access. Transfer is repeated in the following order: CS1 read → CS1 read → CS2 write → CS2 write → CS1 read → ... • Conditions The bits for setting the idle cycles between access cycles in CS1BCR and CS2BCR are all set to 0. In CS1WCR and CS2WCR, the WM bit is set to 1 (external WAIT pin disabled) and the HW[1:0] bits are set to 00 (CS negation is not extended). Iφ:Bφ is set to 4:1, and no other processing is done during transfer. For both the CS1 and CS2 spaces, normal SRAM devices are connected, the bus width is 32 bits, and access size is also 32 bits. The idle cycles generated under each condition are estimated for each pair of access cycles. In the following table, R indicates a read cycle and W indicates a write cycle. R→R R→W W→W W→R [1] or [2] 0 0 0 0 CSnBCR is set to 0. [3] or [4] 0 0 0 0 The WM bit is set to 1. [5] 1 1 0 0 Generated after a read cycle. [6] 0 2 2 0 See the Iφ:Bφ = 4:1 columns in table 10.17. [7] 0 1 0 0 No idle cycle is generated for the second time due to the write buffer effect. [5] + [6] + [7] 1 4 2 0 [8] 0 0 0 0 Value for SRAM → SRAM access Estimated idle cycles 1 4 2 0 Maximum value among conditions [1] or [2], [3] or [4], [5] + [6] + [7], and [8] Actual idle cycles 1 4 2 1 The estimated value does not match the actual value in the W → R cycles because the internal idle cycles due to condition [6] is estimated as 0 but actually an internal idle cycle is generated due to execution of a loop condition check instruction. Condition Note Figure 10.35 Comparison between Estimated Idle Cycles and Actual Value Page 340 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 10 Bus State Controller 10.5.10 Others (1) Reset This module can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal clock. All control registers are initialized. In software standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. (2) Access from the Side of the LSI Internal Bus Master There are three types of LSI internal buses: a CPU bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the CPU bus. The bus state controller and internal bus masters other than the CPU are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory are connected bidirectionally to the CPU bus and internal bus. Access from the CPU bus to the internal bus is enabled but access from the internal bus to the CPU bus is disabled. This gives rise to the following problems. On-chip bus masters such as the direct memory access controller other than the CPU can access internal memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. In a cache-enabled space, if the CPU initiates read access, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword access cycles to perform a cache fill operation on the external interface. For a cache-disabled space, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of an on-chip peripheral module, the cycle is initiated through the internal bus and peripheral bus. The read data is sent to the CPU via the peripheral bus, internal bus, and CPU bus. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 341 of 1910 Section 10 Bus State Controller SH726A Group, SH726B Group In a write cycle for the cache-enabled space, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller incorporates a one-stage write buffer, it can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the bus state controller functions in the same way for an access by a bus master other than the CPU such as the direct memory access controller. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next read cycle will not be initiated until the previous write cycle is completed. Changing the registers in this module while the write buffer is operating may disrupt correct write access. Therefore, do not change the registers in this module immediately after a write access. If this change becomes necessary, do it after executing a dummy read of the write data. Page 342 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 10 Bus State Controller On-Chip Peripheral Module Access To access an on-chip module register, two or more peripheral module clock (P) cycles are required. Care must be taken in system design. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to the software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR1 register to 1. However a dummy read of the STBCR1 register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR1 register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 343 of 1910 Section 10 Bus State Controller Page 344 of 1910 SH726A Group, SH726B Group R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Section 11 Direct Memory Access Controller Direct Memory Access Controller can be used in place of the CPU to perform high-speed transfers 1 between external devices* that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 11.1 Features  Number of channels: 16 channels (channels 0 to 15) selectable One channel (channel 0) can receive external requests.  4-Gbyte physical address space  Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes (longword  4)  Maximum transfer count: 16,777,216 transfers (24 bits)  Address mode: Dual address mode and single address mode* are supported. 2  Transfer requests  External request* 1  On-chip peripheral module request  Auto request The following modules can issue on-chip peripheral module requests.  Serial communication interface with FIFO: 10 sources  I C bus interface 3: eight sources 2  A/D converter: one source  Multi-function timer pulse unit 2: five sources  Compare match timer: two sources  USB 2.0 host/function module: two sources  Controller area network: two sources  Serial sound interface: six sources  Sampling rate converter: six sources  Renesas SPDIF interface: two sources  CD-ROM decoder: one source  SD host interface: two sources  Renesas serial peripheral interface: six sources  Clock synchronous serial I/O with FIFO: two sources R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 345 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller  Selectable bus modes  Cycle steal mode (normal mode or intermittent mode)  Burst mode  Selectable channel priority levels: The channel priority levels are selectable between two fixed modes.  Interrupt request: An interrupt request can be sent to the CPU on completion of half- or fulldata transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to the CPU when half of the initially specified DMA transfer is completed.  External request detection* : There are following four types of DREQ input detection. 1  Low level detection  High level detection  Rising edge detection  Falling edge detection  Transfer request acknowledge and transfer end signals* : Active levels for DACK and TEND can be set independently. 1  Support of reload functions in DMA transfer information registers: DMA transfer using the same information as the current transfer can be repeated automatically without specifying the information again. Modifying the reload registers during DMA transfer enables next DMA transfer to be done using different transfer information. The reload function can be enabled or disabled independently in each channel or reload register. Notes: 1. DREQ, DACK, and TEND are provided only for the SH726B. 2. Single address mode cannot be selected in the SH726A. Page 346 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Figure 11.1 shows the block diagram of this module. RDMATCR_n On-chip memory Iteration control On-chip peripheral module Register control DMATCR_n RSAR_n Internal bus Peripheral bus SAR_n Start-up control RDAR_n DAR_n DMA transfer request signal CHCR_n DMA transfer acknowledge signal HEIn DEIn Interrupt controller Request priority control DMAOR DMARS0 to DMARS7 External ROM Bus interface External RAM External device (memory mapped) External device (with acknowledge) Bus state controller DREQ0* DACK0*, TEND0* [Legend] RDMATCR: DMA reload transfer count register DMATCR: DMA transfer count register RSAR: DMA reload source address register SAR: DMA source address register RDAR: DMA reload destination address register DAR: DMA destination address register DMA channel control register CHCR: DMA operation register DMAOR: DMARS0 to DMARS7: DMA extension resource selectors 0 to 7 DMA transfer half-end interrupt request to the CPU HEIn: DMA transfer end interrupt request to the CPU DEIn: n = 0 to 15 Note: * DREQ, DACK, and TEND are provided only for the SH726B. Figure 11.1 Block Diagram R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 347 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller 11.2 Input/Output Pins Table 11.1 lists the pin configuration of this module. This module has pins for one channel (channel 0) for external bus use. Table 11.1 Pin Configuration Channel Name Abbreviation I/O Function 0 DMA transfer request DREQ0 I DMA transfer request input from an external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to an external device DMA transfer end TEND0 O DMA transfer end output for channel 0 Note: DREQ0, DACK0, and TEND0 are provided only for the SH726B. Page 348 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 11.3 Section 11 Direct Memory Access Controller Register Descriptions This module has the registers listed in table 11.2. There are four control registers and three reload registers for each channel, and one common control register is used by all channels. In addition, there is one extension resource selector per two channels. Each channel number is expressed in the register names, as in SAR_0 for SAR in channel 0. Table 11.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address Access Size 0 DMA source address register_0 SAR_0 R/W H'00000000 H'FFFE1000 16, 32 DMA destination address register_0 DAR_0 R/W H'00000000 H'FFFE1004 16, 32 DMA transfer count register_0 DMATCR_0 R/W H'00000000 H'FFFE1008 16, 32 DMA channel control register_0 CHCR_0 R/W* DMA reload source address register_0 RSAR_0 R/W H'00000000 H'FFFE1100 16, 32 DMA reload destination RDAR_0 address register_0 R/W H'00000000 H'FFFE1104 16, 32 DMA reload transfer count register_0 RDMATCR_0 R/W H'00000000 H'FFFE1108 16, 32 DMA source address register_1 SAR_1 R/W H'00000000 H'FFFE1010 16, 32 DMA destination address register_1 DAR_1 R/W H'00000000 H'FFFE1014 16, 32 DMA transfer count register_1 DMATCR_1 R/W H'00000000 H'FFFE1018 16, 32 DMA channel control register_1 CHCR_1 R/W* DMA reload source address register_1 RSAR_1 R/W H'00000000 H'FFFE1110 16, 32 DMA reload destination RDAR_1 address register_1 R/W H'00000000 H'FFFE1114 16, 32 RDMATCR_1 R/W H'00000000 H'FFFE1118 16, 32 1 DMA reload transfer count register_1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 1 1 H'00000000 H'FFFE100C 8, 16, 32 H'00000000 H'FFFE101C 8, 16, 32 Page 349 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 2 DMA source address register_2 SAR_2 R/W H'00000000 H'FFFE1020 16, 32 DMA destination address register_2 DAR_2 R/W H'00000000 H'FFFE1024 16, 32 DMA transfer count register_2 DMATCR_2 R/W H'00000000 H'FFFE1028 16, 32 DMA channel control register_2 CHCR_2 R/W* DMA reload source address register_2 RSAR_2 R/W H'00000000 H'FFFE1120 16, 32 DMA reload destination RDAR_2 address register_2 R/W H'00000000 H'FFFE1124 16, 32 DMA reload transfer count register_2 RDMATCR_2 R/W H'00000000 H'FFFE1128 16, 32 DMA source address register_3 SAR_3 R/W H'00000000 H'FFFE1030 16, 32 DMA destination address register_3 DAR_3 R/W H'00000000 H'FFFE1034 16, 32 DMA transfer count register_3 DMATCR_3 R/W H'00000000 H'FFFE1038 16, 32 DMA channel control register_3 CHCR_3 R/W* DMA reload source address register_3 RSAR_3 R/W H'00000000 H'FFFE1130 16, 32 DMA reload destination RDAR_3 address register_3 R/W H'00000000 H'FFFE1134 16, 32 RDMATCR_3 R/W H'00000000 H'FFFE1138 16, 32 3 DMA reload transfer count register_3 Page 350 of 1910 1 1 H'00000000 H'FFFE102C 8, 16, 32 H'00000000 H'FFFE103C 8, 16, 32 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 4 DMA source address register_4 SAR_4 R/W H'00000000 H'FFFE1040 16, 32 DMA destination address register_4 DAR_4 R/W H'00000000 H'FFFE1044 16, 32 DMA transfer count register_4 DMATCR_4 R/W H'00000000 H'FFFE1048 16, 32 DMA channel control register_4 CHCR_4 R/W* H'00000000 H'FFFE104C 8, 16, 32 DMA reload source address register_4 RSAR_4 R/W H'00000000 H'FFFE1140 16, 32 DMA reload destination RDAR_4 address register_4 R/W H'00000000 H'FFFE1144 16, 32 DMA reload transfer count register_4 RDMATCR_4 R/W H'00000000 H'FFFE1148 16, 32 DMA source address register_5 SAR_5 R/W H'00000000 H'FFFE1050 16, 32 DMA destination address register_5 DAR_5 R/W H'00000000 H'FFFE1054 16, 32 DMA transfer count register_5 DMATCR_5 R/W H'00000000 H'FFFE1058 16, 32 DMA channel control register_5 CHCR_5 R/W* H'00000000 H'FFFE105C 8, 16, 32 DMA reload source address register_5 RSAR_5 R/W H'00000000 H'FFFE1150 16, 32 DMA reload destination RDAR_5 address register_5 R/W H'00000000 H'FFFE1154 16, 32 RDMATCR_5 R/W H'00000000 H'FFFE1158 16, 32 5 DMA reload transfer count register_5 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 1 1 Page 351 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 6 DMA source address register_6 SAR_6 R/W H'00000000 H'FFFE1060 16, 32 DMA destination address register_6 DAR_6 R/W H'00000000 H'FFFE1064 16, 32 DMA transfer count register_6 DMATCR_6 R/W H'00000000 H'FFFE1068 16, 32 DMA channel control register_6 CHCR_6 R/W* DMA reload source address register_6 RSAR_6 R/W H'00000000 H'FFFE1160 16, 32 DMA reload destination RDAR_6 address register_6 R/W H'00000000 H'FFFE1164 16, 32 DMA reload transfer count register_6 RDMATCR_6 R/W H'00000000 H'FFFE1168 16, 32 DMA source address register_7 SAR_7 R/W H'00000000 H'FFFE1070 16, 32 DMA destination address register_7 DAR_7 R/W H'00000000 H'FFFE1074 16, 32 DMA transfer count register_7 DMATCR_7 R/W H'00000000 H'FFFE1078 16, 32 DMA channel control register_7 CHCR_7 R/W* DMA reload source address register_7 RSAR_7 R/W H'00000000 H'FFFE1170 16, 32 DMA reload destination RDAR_7 address register_7 R/W H'00000000 H'FFFE1174 16, 32 RDMATCR_7 R/W H'00000000 H'FFFE1178 16, 32 7 DMA reload transfer count register_7 Page 352 of 1910 1 1 H'00000000 H'FFFE106C 8, 16, 32 H'00000000 H'FFFE107C 8, 16, 32 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Channel Register Name Abbreviation R/W Initial Value Address Access Size 8 DMA source address register_8 SAR_8 R/W H'00000000 H'FFFE1080 16, 32 DMA destination address register_8 DAR_8 R/W H'00000000 H'FFFE1084 16, 32 DMA transfer count register_8 DMATCR_8 R/W H'00000000 H'FFFE1088 16, 32 DMA channel control register_8 CHCR_8 R/W* H'00000000 H'FFFE108C 8, 16, 32 DMA reload source address register_8 RSAR_8 R/W H'00000000 H'FFFE1180 16, 32 DMA reload destination RDAR_8 address register_8 R/W H'00000000 H'FFFE1184 16, 32 DMA reload transfer count register_8 RDMATCR_8 R/W H'00000000 H'FFFE1188 16, 32 DMA source address register_9 SAR_9 R/W H'00000000 H'FFFE1090 16, 32 DMA destination address register_9 DAR_9 R/W H'00000000 H'FFFE1094 16, 32 DMA transfer count register_9 DMATCR_9 R/W H'00000000 H'FFFE1098 16, 32 DMA channel control register_9 CHCR_9 R/W* H'00000000 H'FFFE109C 8, 16, 32 DMA reload source address register_9 RSAR_9 R/W H'00000000 H'FFFE1190 16, 32 DMA reload destination RDAR_9 address register_9 R/W H'00000000 H'FFFE1194 16, 32 RDMATCR_9 R/W H'00000000 H'FFFE1198 16, 32 9 DMA reload transfer count register_9 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 1 1 Page 353 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Access Size Channel Register Name Abbreviation R/W Initial Value Address 10 DMA source address register_10 SAR_10 R/W H'00000000 H'FFFE10A0 16, 32 DMA destination address register_10 DAR_10 R/W H'00000000 H'FFFE10A4 16, 32 DMA transfer count register_10 DMATCR_10 R/W H'00000000 H'FFFE10A8 16, 32 DMA channel control register_10 CHCR_10 R/W* DMA reload source address register_10 RSAR_10 R/W H'00000000 H'FFFE11A0 16, 32 DMA reload destination RDAR_10 address register_10 R/W H'00000000 H'FFFE11A4 16, 32 DMA reload transfer count register_10 RDMATCR_10 R/W H'00000000 H'FFFE11A8 16, 32 DMA source address register_11 SAR_11 R/W H'00000000 H'FFFE10B0 16, 32 DMA destination address register_11 DAR_11 R/W H'00000000 H'FFFE10B4 16, 32 DMA transfer count register_11 DMATCR_11 R/W H'00000000 H'FFFE10B8 16, 32 DMA channel control register_11 CHCR_11 R/W* DMA reload source address register_11 RSAR_11 R/W H'00000000 H'FFFE11B0 16, 32 DMA reload destination RDAR_11 address register_11 R/W H'00000000 H'FFFE11B4 16, 32 RDMATCR_11 R/W H'00000000 H'FFFE11B8 16, 32 11 DMA reload transfer count register_11 Page 354 of 1910 1 1 H'00000000 H'FFFE10AC 8, 16, 32 H'00000000 H'FFFE10BC 8, 16, 32 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Access Size Channel Register Name Abbreviation R/W Initial Value Address 12 DMA source address register_12 SAR_12 R/W H'00000000 H'FFFE10C0 16, 32 DMA destination address register_12 DAR_12 R/W H'00000000 H'FFFE10C4 16, 32 DMA transfer count register_12 DMATCR_12 R/W H'00000000 H'FFFE10C8 16, 32 DMA channel control register_12 CHCR_12 R/W* DMA reload source address register_12 RSAR_12 R/W H'00000000 H'FFFE11C0 16, 32 DMA reload destination RDAR_12 address register_12 R/W H'00000000 H'FFFE11C4 16, 32 DMA reload transfer count register_12 RDMATCR_12 R/W H'00000000 H'FFFE11C8 16, 32 DMA source address register_13 SAR_13 R/W H'00000000 H'FFFE10D0 16, 32 DMA destination address register_13 DAR_13 R/W H'00000000 H'FFFE10D4 16, 32 DMA transfer count register_13 DMATCR_13 R/W H'00000000 H'FFFE10D8 16, 32 DMA channel control register_13 CHCR_13 R/W* DMA reload source address register_13 RSAR_13 R/W H'00000000 H'FFFE11D0 16, 32 DMA reload destination RDAR_13 address register_13 R/W H'00000000 H'FFFE11D4 16, 32 RDMATCR_13 R/W H'00000000 H'FFFE11D8 16, 32 13 DMA reload transfer count register_13 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 1 1 H'00000000 H'FFFE10CC 8, 16, 32 H'00000000 H'FFFE10DC 8, 16, 32 Page 355 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Access Size Channel Register Name Abbreviation R/W Initial Value Address 14 DMA source address register_14 SAR_14 R/W H'00000000 H'FFFE10E0 16, 32 DMA destination address register_14 DAR_14 R/W H'00000000 H'FFFE10E4 16, 32 DMA transfer count register_14 DMATCR_14 R/W H'00000000 H'FFFE10E8 16, 32 DMA channel control register_14 CHCR_14 R/W* DMA reload source address register_14 RSAR_14 R/W H'00000000 H'FFFE11E0 16, 32 DMA reload destination RDAR_14 address register_14 R/W H'00000000 H'FFFE11E4 16, 32 DMA reload transfer count register_14 RDMATCR_14 R/W H'00000000 H'FFFE11E8 16, 32 DMA source address register_15 SAR_15 R/W H'00000000 H'FFFE10F0 16, 32 DMA destination address register_15 DAR_15 R/W H'00000000 H'FFFE10F4 16, 32 DMA transfer count register_15 DMATCR_15 R/W H'00000000 H'FFFE10F8 16, 32 DMA channel control register_15 CHCR_15 R/W* DMA reload source address register_15 RSAR_15 R/W H'00000000 H'FFFE11F0 16, 32 DMA reload destination RDAR_15 address register_15 R/W H'00000000 H'FFFE11F4 16, 32 RDMATCR_15 R/W H'00000000 H'FFFE11F8 16, 32 15 DMA reload transfer count register_15 Page 356 of 1910 1 1 H'00000000 H'FFFE10EC 8, 16, 32 H'00000000 H'FFFE10FC 8, 16, 32 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Initial Value Address Access Size H'0000 H'FFFE1200 8, 16 R/W H'0000 H'FFFE1300 16 DMARS1 R/W H'0000 H'FFFE1304 16 DMA extension resource selector 2 DMARS2 R/W H'0000 H'FFFE1308 16 6 and 7 DMA extension resource selector 3 DMARS3 R/W H'0000 H'FFFE130C 16 8 and 9 DMA extension resource selector 4 DMARS4 R/W H'0000 H'FFFE1310 16 10 and 11 DMA extension resource selector 5 DMARS5 R/W H'0000 H'FFFE1314 16 12 and 13 DMA extension resource selector 6 DMARS6 R/W H'0000 H'FFFE1318 16 14 and 15 DMA extension resource selector 7 DMARS7 R/W H'0000 H'FFFE131C 16 Channel Register Name Abbreviation R/W Common DMA operation register DMAOR R/W* 0 and 1 DMA extension resource selector 0 DMARS0 2 and 3 DMA extension resource selector 1 4 and 5 2 Notes: 1. For the HE and TE bits in CHCR_n, only 0 can be written to clear the flags after 1 is read. 2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is read. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 357 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller 11.3.1 DMA Source Address Registers (SAR) The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in single address mode, SAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 11.3.2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - 16 - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DMA Destination Address Registers (DAR) The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data of an external device with DACK is transferred in single address mode, DAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 358 of 1910 16 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 11.3.3 Section 11 Direct Memory Access Controller DMA Transfer Count Registers (DMATCR) The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: 11.3.4 16 DMA Channel Control Registers (CHCR) The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the DMA transfer mode. The DO, AM, AL, DL, DS, and TL bits which specify the DREQ, DACK, and TEND external pin functions can be read and written to in channel 0, but they are reserved in channels 1 to 15. Bit: Initial value: R/W: Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TC - RLD SAR RLD DAR - DAF SAF - DO TL - TE MASK HE HIE AM AL 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R 0 0 0 R/W R/(W)* R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 DM[1:0] Initial value: R/W: 0 R/W 0 R/W SM[1:0] 0 R/W 0 R/W RS[3:0] 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 DL DS TB 0 R/W 0 R/W 0 R/W 4 3 TS[1:0] 0 R/W 0 R/W 2 1 0 IE TE DE 0 0 0 R/W R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 359 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 31 TC 0 R/W Transfer Count Mode Specifies whether to transmit data once or for the count specified in DMATCR by one transfer request. This function is valid only in on-chip peripheral module request mode. Note that when this bit is set to 0, the TB bit must not be set to 1 (burst mode). When the modules other than the multi-function timer pulse unit 2, compare match timer, controller area network, CDROM decoder, and A/D converter are selected for the transfer request source, this bit (TC) must not be set to 1. 0: Transmits data once by one transfer request 1: Transmits data for the count specified in DMATCR by one transfer request 30  0 R Reserved This bit is always read as 0. The write value should always be 0. 29 RLDSAR 0 R/W SAR Reload Function ON/OFF Enables (ON) or disables (OFF) the function to reload SAR and DMATCR. 0: Disables (OFF) the function to reload SAR and DMATCR 1: Enables (ON) the function to reload SAR and DMATCR 28 RLDDAR 0 R/W DAR Reload Function ON/OFF Enables (ON) or disables (OFF) the function to reload DAR and DMATCR. 0: Disables (OFF) the function to reload DAR and DMATCR 1: Enables (ON) the function to reload DAR and DMATCR 27  0 R Reserved This bit is always read as 0. The write value should always be 0. Page 360 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 26 DAF 0 R/W Fixed Destination Address 16-Byte Transfer Enabled when the transfer size (set in TS[1:0]) is 16 bytes and the destination address mode (set in DM[1:0]) is fixed address. 0: 16 bytes of data are transferred to the address specified in DAR. The address specified in DAR + H'0, H'4, H'8, or H'C will be the write destination address. 1: Four bytes of data are transferred four times to the address specified in DAR. The fixed address specified in DAR will be the write destination address. This function is exclusively for use with the CD-ROM decoder, sampling rate converter, and SD host interface. 25 SAF 0 R/W Fixed Source Address 16-Byte Transfer Enabled when the transfer size (set in TS[1:0]) is 16 bytes and the source address mode (set in SM[1:0]) is fixed address. 0: 16 bytes of data are transferred from the address specified in SAR. The address specified in SAR + H'0, H'4, H'8, or H'C will be the read destination address. 1: Four bytes of data are transferred four times from the address specified in SAR. The fixed address specified in SAR will be the read destination address. This function is exclusively for use with the CD-ROM decoder, sampling rate converter, and SD host interface. 24  0 R Reserved This bit is always read as 0. The write value should always be 0. 23 DO 0 R/W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in level detection by CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 361 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 22 TL 0 R/W Transfer End Level Specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: Low-active output from TEND 1: High-active output from TEND 21  0 R Reserved This bit is always read as 0. The write value should always be 0. 20 TEMASK 0 R/W TE Set Mask Specifies that DMA transfer does not stop even if the TE bit is set to 1. If this bit is set to 1 along with the bit for SAR/DAR reload function, DMA transfer can be performed until the transfer request is cancelled. In auto request mode or when a rising/falling edge of the DREQ signal is detected in external request mode, the setting of this bit is ignored and DMA transfer stops if the TE bit is set to 1. Note that this function is enabled only when either the RLDSAR bit or the RLDDAR bit is set to 1. 0: DMA transfer stops if the TE bit is set 1: DMA transfer does not stop even if the TE bit is set Page 362 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W 19 HE 0 R/(W)* Half-End Flag Description This bit is set to 1 when the transfer count reaches half of the DMATCR value that was specified before transfer starts. If DMA transfer ends because of an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR before the transfer count reaches half of the initial DMATCR value, the HE bit is not set to 1. If DMA transfer ends due to an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR after the HE bit is set to 1, the bit remains set to 1. To clear the HE bit, write 0 to it after HE = 1 is read. 0: DMATCR > (DMATCR set before transfer starts)/2 during DMA transfer or after DMA transfer is terminated [Clearing condition]  Writing 0 after reading HE = 1. 1: DMATCR  (DMATCR set before transfer starts)/2 18 HIE 0 R/W Half-End Interrupt Enable Specifies whether to issue an interrupt request to the CPU when the transfer count reaches half of the DMATCR value that was specified before transfer starts. When the HIE bit is set to 1, this module requests an interrupt to the CPU when the HE bit becomes 1. 0: Disables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 1: Enables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 363 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 17 AM 0 R/W Acknowledge Mode Specifies whether DACK and TEND are output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK and TEND are always output regardless of the specification by this bit. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: DACK and TEND output in read cycle (dual address mode) 1: DACK and TEND output in write cycle (dual address mode) 16 AL 0 R/W Acknowledge Level Specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0. This bit is reserved in CHCR_1 to CHCR_15; it is always read as 0 and the write value should always be 0. 0: Low-active output from DACK 1: High-active output from DACK 15, 14 DM[1:0] 00 R/W Destination Address Mode These bits select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address 01: Destination address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer) 10: Destination address is decremented (–1 in byteunit transfer, –2 in word-unit transfer, –4 in longword-unit transfer, setting prohibited in 16byte-unit transfer) 11: Setting prohibited Page 364 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 13, 12 SM[1:0] 00 R/W Source Address Mode These bits select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer) 10: Source address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longwordunit transfer, setting prohibited in 16-byte-unit transfer) 11: Setting prohibited R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 365 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 11 to 8 RS[3:0] 0000 R/W Resource Select These bits specify which transfer requests will be sent to this module. The changing of transfer request source should be done in the state when DMA enable bit (DE) is set to 0. 0000: External request, dual address mode 0001: Setting prohibited 0010: External request/single address mode External address space  External device with DACK 0011: External request/single address mode External device with DACK  External address space 0100: Auto request 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1000: DMA extension resource selector 1001: Controller area network, channel 0 1010: Controller area network, channel 1 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Note: External request specification is valid only in CHCR_0. External request should not be specified for channels CHCR_1 to CHCR_15. Page 366 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 7 DL 0 R/W DREQ Level 6 DS 0 R/W DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0. These bits are reserved in CHCR_1 to CHCR_15; they are always read as 0 and the write value should always be 0. If the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by these bits is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge 5 TB 0 R/W Transfer Bus Mode Specifies the bus mode at DMA transfer. Note that the burst mode must not be selected when TC = 0. 0: Cycle steal mode 1: Burst mode 4, 3 TS[1:0] 00 R/W Transfer Size These bits specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte unit 01: Word unit (two bytes) 10: Longword unit (four bytes) 11: 16-byte (four longword) unit 2 IE 0 R/W Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Disables an interrupt request 1: Enables an interrupt request R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 367 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W 1 TE 0 R/(W)* Transfer End Flag Description This bit is set to 1 when DMATCR becomes 0 and DMA transfer ends. The TE bit is not set to 1 in the following cases.  DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0.  DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR). To clear the TE bit, write 0 after reading TE = 1. Even if the DE bit is set to 1 while the TEMASK bit is 0 and this bit is 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been terminated [Clearing condition]  Writing 0 after reading TE = 1 1: DMA transfer ends by the specified count (DMATCR = 0) 0 DE 0 R/W DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this case, all of the bits TE, NMIF in DMAOR, and AE must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. If the DREQ signal is detected by low/high level in external request mode, or in peripheral module request mode, the NMIF bit and the AE bit must be 0 if the TEMASK bit is 1. If the TEMASK bit is 0, the TE bit must also be 0. If the DREQ signal is detected by a rising/falling edge in external request mode, all of the bits TE, NMIF, and AE must be 0 as in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Only 0 can be written to clear the flag after 1 is read. Page 368 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 11.3.5 Section 11 Direct Memory Access Controller DMA Reload Source Address Registers (RSAR) The DMA reload source address registers (RSAR) are 32-bit readable/writable registers. When the SAR reload function is enabled, the RSAR value is written to the source address register (SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RSAR during the current DMA transfer. When the SAR reload function is disabled, RSAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 16 Page 369 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller 11.3.6 DMA Reload Destination Address Registers (RDAR) The DMA reload destination address registers (RDAR) are 32-bit readable/writable registers. When the DAR reload function is enabled, the RDAR value is written to the destination address register (DAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDAR during the current DMA transfer. When the DAR reload function is disabled, RDAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or 16-byte address boundary respectively. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 370 of 1910 16 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 11.3.7 Section 11 Direct Memory Access Controller DMA Reload Transfer Count Registers (RDMATCR) The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers. When the SAR/DAR reload function is enabled, the RDMATCR value is written to the transfer count register (DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDMATCR during the current DMA transfer. When the SAR/DAR reload function is disabled, RDMATCR is ignored. The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0. As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 - - - - - - - - - - - - - - - - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - - 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value: R/W: R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 16 Page 371 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller 11.3.8 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register also shows the DMA transfer status. Bit: Initial value: R/W: 15 14 - - 0 R 0 R 13 12 CMS[1:0] 0 R/W 0 R/W 11 10 - - 0 R 0 R 9 8 PR[1:0] 0 R/W 0 R/W 7 6 5 4 3 2 1 0 - - - - - AE NMIF DME 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)* R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15, 14  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 CMS[1:0] 00 R/W Cycle Steal Mode Select These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermittent mode valid. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer for every 16 cycles of B clock. 11: Intermittent mode 64 Executes one DMA transfer for every 64 cycles of B clock. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 372 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 9, 8 PR[1:0] 00 R/W Priority Mode These bits select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11 > CH12 > CH13 > CH14 > CH15 01: Fixed mode 2: CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11 > CH4 > CH12 > CH5 > CH13 > CH6 > CH14 > CH7 > CH15 10: Setting prohibited 11: Setting prohibited 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 AE 0 R/(W)* Address Error Flag Indicates whether an address error has occurred by this module. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. 0: No address error occurred by this module 1: Address error occurred by this module [Clearing condition]  R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Writing 0 after reading AE = 1 Page 373 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Bit Bit Name Initial Value R/W Description 1 NMIF 0 R/(W)* NMI Flag Indicates that an NMI interrupt occurred. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. Even if the NMI interrupt is input while this module is not in operation, the NMIF bit is set to 1. 0: No NMI interrupt 1: NMI interrupt occurred [Clearing condition] Writing 0 after reading NMIF = 1 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfer on all channels. If the DME bit and DE bit in CHCR are set to 1, DMA transfer is enabled. However, transfer is enabled only when the TE bit in CHCR of the transfer corresponding channel, the NMIF bit in DMAOR, and the AE bit are all cleared to 0. Clearing the DME bit to 0 can terminate the DMA transfer on all channels. 0: DMA transfer is disabled on all channels 1: DMA transfer is enabled on all channels Note: * Only 0 can be written to clear the flag after 1 is read. If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If fixed mode 2 is specified, the channel priority is specified as CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11 > CH4 > CH12 > CH5 > CH13 > CH6 > DH14 > CH7 > CH15. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11 > CH12 > CH13 > CH14 > CH15. The internal operation of this module for an address error is as follows:  No address error: Read (source to interior of this module)  Write (interior of this module to destination)  Address error in source address: Nop  Nop  Address error in destination address: Read  Nop Page 374 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 11.3.9 Section 11 Direct Memory Access Controller DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7) The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that specify the source of the DMA transfer request from peripheral modules in each channel. DMARS0 to DMARS7 are for channels 0 and 1, 2 and 3, 4 and 5, 6 and 7, 8 and 9, 10 and 11, 12 and 13, and 14 and 15, respectively. Table 11.3 shows the specifiable combinations. DMARS can specify the following transfer request sources (The following modules can issue onchip peripheral module requests):  Serial communication interface with FIFO: 10 sources  I C bus interface 3: eight sources 2  A/D converter: one source  Multi-function timer pulse unit 2: five sources  Compare match timer: two sources  USB 2.0 host/function module: two sources  Controller area network: two sources  Serial sound interface: six sources  Sampling rate converter: six sources  Renesas SPDIF interface: two sources  CD-ROM decoder: one source  SD host interface: two sources  Renesas serial peripheral interface: six sources  Clock synchronous serial I/O with FIFO: two sources Two transfer request sources for the controller area network do not need to be specified by these registers, for they can be specified using the RS3 to RS0 bits in the DMA channel control register (CHCR). R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 375 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller  DMARS0 Bit: 15 14 13 12 11 10 CH1 MID[5:0] Initial value: R/W: 0 R/W 0 R/W 9 8 7 6 CH1 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 5 4 3 2 CH0 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 1 0 CH0 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS1 Bit: 15 14 CH3 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH3 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH2 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH2 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS2 Bit: 15 14 CH5 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH5 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH4 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH4 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS3 Bit: 15 14 CH7 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH7 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH6 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH6 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS4 Bit: 15 14 CH9 MID[5:0] Initial value: R/W: 0 R/W 0 R/W CH9 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 CH8 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 CH8 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS5 Bit: 15 14 CH11 MID[5:0] Initial value: R/W: 0 R/W Page 376 of 1910 0 R/W 0 R/W 0 R/W CH11 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W CH10 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W CH10 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller  DMARS6 Bit: 15 14 13 12 11 10 CH13 MID[5:0] Initial value: R/W: 0 R/W 0 R/W 9 8 7 6 CH13 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 13 12 11 10 5 4 3 2 1 CH12 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 0 CH12 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W 5 4 3 2 0 R/W 0 R/W 1 0  DMARS7 Bit: 15 14 CH15 MID[5:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W CH15 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W CH14 MID[5:0] 0 R/W 0 R/W 0 R/W 0 R/W CH14 RID[1:0] 0 R/W 0 R/W 0 R/W 0 R/W Transfer requests from the various modules specify MID and RID as shown in table 11.3. Table 11.3 DMARS Settings Peripheral Module Setting Value for One Channel ({MID, RID}) MID RID Function USB 2.0 host/function H'03 module B'000000 B'11 Channel 0 FIFO H'07 B'000001 B'11 Channel 1 FIFO Renesas SPDIF interface H'09 B'000010 B'01 Transmit H'0A B'000010 B'10 Receive SD host interface H'11 B'000100 B'01 SD_BUF write B'10 SD_BUF read B'000110 B'01 Transmit B'10 Receive Serial sound interface H'21 Channel 0 H'22 B'001000 B'01 Transmit B'10 Receive Serial sound interface H'25 Channel 1 H'26 B'001001 B'01 Transmit B'10 Receive Serial sound interface H'2B Channel 2 B'001010 B'11  Serial sound interface H'2F Channel 3 B'001011 B'11  H'12 Clock synchronous serial I/O with FIFO H'19 H'1A R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 377 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Setting Value for One Channel ({MID, RID}) MID RID Function Sampling rate converter Channel 0 H'41 B'010000 B'01 Input data FIFO empty B'10 Output data FIFO full Sampling rate converter Channel 1 H'45 B'01 Input data FIFO empty B'10 Output data FIFO full Sampling rate converter Channel 2 H'49 B'01 Input data FIFO empty B'10 Output data FIFO full Renesas serial peripheral interface Channel 0 H'51 B'01 Transmit B'10 Receive Renesas serial peripheral interface Channel 1 H'55 B'01 Transmit B'10 Receive Renesas serial peripheral interface Channel 2 H'59 B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'01 Transmit B'10 Receive B'011010 B'01 Transmit B'10 Receive B'011011 B'01 Transmit B'10 Receive Peripheral Module 2 I C bus interface 3 Channel 0 2 I C bus interface 3 Channel 1 2 I C bus interface 3 Channel 2 2 H'42 B'010001 H'46 B'010010 H'4A B'010100 H'52 B'010101 H'56 B'010110 H'5A H'61 B'011000 H'62 H'65 B'011001 H'66 H'69 H'6A I C bus interface 3 Channel 3 H'6D CD-ROM decoder H'73 B'011100 B'11  Serial communication H'81 interface with FIFO H'82 Channel 0 B'100000 B'01 Transmit B'10 Receive Serial communication H'85 interface with FIFO H'86 Channel 1 B'100001 B'01 Transmit B'10 Receive Page 378 of 1910 H'6E R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Peripheral Module Setting Value for One Channel ({MID, RID}) Section 11 Direct Memory Access Controller MID RID Function Serial communication H'89 interface with FIFO H'8A Channel 2 B'100010 B'01 Transmit B'10 Receive Serial communication H'8D interface with FIFO H'8E Channel 3 B'100011 B'01 Transmit B'10 Receive Serial communication H'91 interface with FIFO H'92 Channel 4 B'100100 B'01 Transmit B'10 Receive A/D converter H'B3 B'101100 B'11  Multi-function timer pulse unit 2 Channel 0 H'E3 B'111000 B'11  Multi-function timer pulse unit 2 Channel 1 H'E7 B'111001 B'11  Multi-function timer pulse unit 2 Channel 2 H'EB B'111010 B'11  Multi-function timer pulse unit 2 Channel 3 H'EF B'111011 B'11  Multi-function timer pulse unit 2 Channel 4 H'F3 B'111100 B'11  Compare match timer H'FB Channel 0 B'111110 B'11  Compare match timer H'FF Channel 1 B'111111 B'11  When MID or RID other than the values listed in table 11.3 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to RS0) in CHCR0 to CHCR15 have been set to B'1000. Otherwise, even if DMARS has been set, the transfer request source is not accepted. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 379 of 1910 Section 11 Direct Memory Access Controller 11.4 SH726A Group, SH726B Group Operation When there is a DMA transfer request, this module starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request*, and on-chip peripheral module request. In bus mode, the burst mode or the cycle steal mode can be selected. Note: * In the SH726A, external requests cannot be used. 11.4.1 Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), three reload registers (RSAR, RDAR, RDMATCR) and DMA extension resource selector (DMARS) are set for the target transfer conditions, this module transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0), AE = 0, NMIF = 0). 2. When a transfer request comes and transfer is enabled, this module transfers one transfer unit of data (depending on the settings of the TS1 and TS0 bits). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1. 4. When transfer has been completed for the specified count (when DMATCR reaches 0) while the TEMASK bit is 0, the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. When DMATCR reaches 0 while the TEMASK bit is 1, the TE bit is set to 1 and then the values set in RSAR, RDAR and RDMATCR are reloaded in SAR, DAR and DMATCR, respectively to continue transfer operation until the DMA transfer request is cancelled. 5. When an address error in this module or an NMI interrupt is generated, the transfer is terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. Page 380 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Figure 11.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Transfer request occurs?*1 No *2 Yes *3 Bus mode, transfer request mode, DREQ detection system Transfer (one transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated No DMATCR = 0? No Yes DMATCR = 1/2 ? Yes TE = 1 HE = 1 DEI interrupt request (when IE = 1) HEI interrupt request (when HE = 1) When reload function is enabled, RSAR → SAR, RDAR → DAR, and RDMATCR → DMATCR When the TC bit in CHCR is 0, or for a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. For a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. NMIF = 1 or AE = 1 or DE = 0 or DME = 0? NMIF = 1 or AE = 1 or DE = 0 or DME = 0? No No In DREQ detection by level in external Yes Yes request mode, or in on-chip peripheral module request mode, TEMASK = 1? Yes No Transfer end Normal end Transfer terminated Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the DE and DME bits are set to 1. 2. DREQ level detection in burst mode (external request) or cycle steal mode. 3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode. Figure 11.2 DMA Transfer Flowchart R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 381 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller 11.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated in external devices and on-chip peripheral modules that are neither the transfer source nor destination. Transfers can be requested in three modes: auto request, external request*, and on-chip peripheral module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_15 and DMARS0 to DMARS7. (1) Auto-Request Mode When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows this module to automatically generate a transfer request signal internally. When the DE bits in CHCR_0 to CHCR_15 and the DME bit in DMAOR are set to 1, the transfer begins so long as the TE bits in CHCR_0 to CHCR_15, and the AE and NMIF bits in DMAOR are 0. (2) External Request Mode* In this mode a transfer is performed at the request signal (DREQ0) of an external device. Choose one of the modes shown in table 11.4 according to the application system. When the DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0), AE = 0, NMIF = 0 for level detection; DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0 for edge detection), DMA transfer is performed upon a request at the DREQ input. Table 11.4 Selecting External Request Modes with the RS Bits RS[3] RS[2] RS[1] RS[0] Address Mode Transfer Source Transfer Destination 0 0 0 0 Dual address mode Any Any 0 0 1 0 Single address mode External memory, memory-mapped external device 1 Page 382 of 1910 External device with DACK External device with DACK External memory, memory-mapped external device R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in CHCR_0 as shown in table 11.5. The source of the transfer request does not have to be the data transfer source or destination. When DREQ is detected by a rising/falling edge and DMA transfer is performed in burst mode, the transfer continues until DMATCR reaches 0 by one DMA transfer request. In cycle steal mode, one DMA transfer is performed by one request. Table 11.5 Selecting External Request Detection with DL and DS Bits CHCR DL Bit DS Bit Detection of External Request 0 0 Low-level detection 1 Falling-edge detection 0 High-level detection 1 Rising-edge detection 1 When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again enters the request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK.  Overrun 0: Transfer is terminated after the same number of transfer has been performed as requests.  Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 11.6 Selecting External Request Detection with DO Bit CHCR DO Bit External Request 0 Overrun 0 1 Overrun 1 Note: * In the SH726A, external requests cannot be used. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 383 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller (3) On-Chip Peripheral Module Request In this mode, the transfer is performed in response to the DMA transfer request signal from an onchip peripheral module. Table 11.7 lists the DMA transfer request signals sent from on-chip peripheral modules to this module. If DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0), AE = 0, and NMIF = 0) in on-chip peripheral module request mode, DMA transfer is started by a transfer request signal. In on-chip peripheral module request mode, there are cases where transfer source or destination is fixed. For details, see table 11.7. Table 11.7 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits CHCR DMARS RS[3:0] MID DMA Transfer DMA Transfer Request Request Source Signal RID Transfer Source Transfer Bus Destination Mode 1001 Any Any Controller area network Channel 0 RM0 (reception end) MB0 Any 1010 Any Any Controller area network Channel 1 RM0 (reception end) MB0 Any 1000 000000 11 USB_DMA0 (receive FIFO in channel 0 full) D0FIFO Any USB_DMA0 (transmit FIFO in channel 0 empty) Any D0FIFO USB_DMA1 (receive FIFO in channel 1 full) D1FIFO Any USB_DMA1 (transmit FIFO in channel 1 empty) Any D1FIFO 000001 11 Page 384 of 1910 USB 2.0 host/function module Cycle steal R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group CHCR DMARS RS[3:0] MID 1000 DMA Transfer Request RID Source Section 11 Direct Memory Access Controller 000010 01 Renesas SPDIF SPDIFTXI Any interface (DMA transfer from transmission module) 10 000100 01 10 001000 01 10 001001 01 10 001010 11 001011 11 010000 01 10 Transfer Bus Destination Mode TDAD Cycle steal SPDIFRXI (DMA transfer to reception module) RDAD Any SD_BUF write Any Data register SD_BUF read Data register Any Clock synchronous serial I/O with FIFO TXI transmit data transfer) Any SITDR RXI (receive data transfer) SIRDR Any Serial sound interface Channel 0 SSITXI0 (transmit data empty) Any SSIFTDR_0 SSIRXI0 (receive data full) SSIFRDR_0 Any Serial sound interface Channel 1 SSITXI1 (transmit data empty) Any SSIRXI1 (receive data full) SSIFRDR_1 Any Serial sound interface Channel 2 SSIRTI2 (transmit data empty) Any SSIRTI2 (receive data full) SSIFRDR_2 Any Serial sound interface Channel 3 SSIRTI3 (transmit data empty) Any SSIRTI3 (receive data full) SSIFRDR_3 Any Sampling rate converter Channel 0 IDEI0 (input data empty) Any ODFI0 (output data full) SRCODR_0 Any SD host interface 10 000110 01 Transfer DMA Transfer Request Signal Source R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SSIFTDR_1 SSIFTDR_2 SSIFTDR_3 SRCIDR_0 Page 385 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller CHCR DMARS RS[3:0] MID 1000 RID 010001 01 10 010010 01 10 010100 01 10 010101 01 10 010110 01 10 011000 01 10 011001 01 10 011010 01 10 011011 01 10 011100 11 Page 386 of 1910 DMA Transfer Request Source DMA Transfer Request Signal Transfer Source Transfer Bus Destination Mode Sampling rate converter Channel 1 IDEI1 (input data empty) Any SRCIDR_1 Cycle steal ODFI1 (output data full) SRCODR_1 Any Sampling rate converter Channel 2 IDEI2 (input data empty) Any ODFI2 (output data full) SRCODR_2 Any Renesas serial peripheral interface Channel 0 SPTI0 (transmit buffer empty) Any SPDR_0 SPRI0 (receive buffer full) SPDR_0 Any SPTI1 (transmit buffer empty) Any SPDR_1 SPRI1 (receive buffer full) SPDR_1 Any SPTI2 (transmit buffer empty) Any SPDR_2 SPRI2 (receive buffer full) SPDR_2 Any Any ICDRT_0 ICDRR_0 Any Any ICDRT_1 ICDRR_1 Any Renesas serial peripheral interface Channel 1 Renesas serial peripheral interface Channel 2 2 I C bus interface 3 TXI0 (transmit data empty) Channel 0 RXI0 (receive data full) 2 I C bus interface 3 TXI1 (transmit data empty) Channel 1 RXI1 (receive data full) 2 I C bus interface 3 TXI2 (transmit data empty) Channel 2 RXI2 (receive data full) 2 SRCIDR_2 Any ICDRT_2 ICDRR_2 Any I C bus interface 3 TXI3 (transmit data empty) Channel 3 RXI3 (receive data full) Any ICDRT_3 ICDRR_3 Any CD-ROM decoder IREADY (decode end) STRMDOUT Any R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group CHCR DMARS RS[3:0] MID 1000 Section 11 Direct Memory Access Controller DMA Transfer DMA Transfer Request Request Source Signal RID 100000 01 10 100001 01 10 100010 01 10 100011 01 10 100100 01 10 Transfer Source Transfer Bus Destination Mode SCFTDR_0 Cycle steal Serial communication interface with FIFO Channel 0 TXI0 (transmit FIFO data empty) Any RXI0 (receive FIFO data full) SCFRDR_0 Any Serial communication interface with FIFO Channel 1 TXI1 (transmit FIFO data empty) Any RXI1 (receive FIFO data full) SCFRDR_1 Any Serial communication interface with FIFO Channel 2 TXI2 (transmit FIFO data empty) Any RXI2 (receive FIFO data full) SCFRDR_2 Any Serial communication interface with FIFO Channel 3 TXI3 (transmit FIFO data empty) Any RXI3 (receive FIFO data full) SCFRDR_3 Any Serial communication interface with FIFO Channel 4 TXI4 (transmit FIFO data empty) Any RXI4 (receive FIFO data full) SCFRDR_4 Any SCFTDR_1 SCFTDR_2 SCFTDR_3 SCFTDR_4 111000 11 TGI0A Multi-function timer pulse unit 2 (input capture or compare match) Channel 0 Any Any 111001 11 TGI1A Multi-function timer pulse unit 2 (input capture or compare match) Channel 1 Any Any 111010 11 Multi-function TGI2A timer pulse unit 2 (input capture or compare Channel 2 match) Any Any 111011 11 Multi-function TGI3A timer pulse unit 2 (input capture or compare Channel 3 match) Any Any R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 387 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller CHCR DMARS RS[3:0] MID 1000 DMA Transfer DMA Transfer Request Request Source Signal RID Transfer Source Transfer Bus Destination Mode 111100 11 Multi-function TGI4A timer pulse unit 2 (input capture or compare Channel 4 match) Any Any 111110 11 Compare match timer Channel 0 CMI0 (compare match) Any Any 111111 11 Compare match timer Channel 1 CMI1 (compare match) Any Any Page 388 of 1910 Cycle steal or burst R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 11.4.3 Section 11 Direct Memory Access Controller Channel Priority When this module receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode 1 and fixed mode 2) are selected. In these mode, the priority levels among the channels are as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH8 > CH9 > CH10 > CH11> CH12> CH13 > CH14 > CH15 Fixed mode 2: CH0 > CH8 > CH1 > CH9 > CH2 > CH10 > CH3 > CH11> CH4 > CH12 > CH5 > CH13 > CH6> CH14 > CH7 > CH15 These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR). 11.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to the transfer source and destination. A data transfer timing depends on the bus mode, which is the cycle steal mode or burst mode. This module supports the transfers shown in table 11.8. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 389 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Table 11.8 Supported DMA Transfers Transfer Destination External Device with Transfer Source DACK External device with DACK Not available External Memory MemoryOn-Chip Mapped Peripheral External Device Module On-Chip Memory Dual, single Dual, single Not available Not available External memory Dual, single Dual Dual Dual Dual Memory-mapped Dual, single external device Dual Dual Dual Dual On-chip peripheral module Not available Dual Dual Dual Dual On-chip memory Not available Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is available only for on-chip peripheral modules that support longword access. 4. External devices with DACK can be supported only by the SH726B. Page 390 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (1) Address Modes (a) Dual Address Mode Section 11 Direct Memory Access Controller SAR Data bus DAR Memory Address bus Direct memory access controller In dual address mode, both the transfer source and destination are accessed (selected) by an address. The transfer source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in this module. In the transfer between external memories as shown in figure 11.3, data is read to this module from one external memory in a data read cycle, and then that data is written to the other external memory in a data write cycle. Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the direct memory access controller. SAR Data bus DAR Memory Address bus Direct memory access controller First bus cycle Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the direct memory access controller is written to the transfer destination module. Second bus cycle Figure 11.3 Data Flow of Dual Address Mode R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 391 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Auto request, external request*, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Figure 11.4 shows an example of DMA transfer timing in dual address mode. Note: * External requests cannot be used in the SH726A. CKIO A25 to A0 Transfer source address Transfer destination address CSn D15 to D0 RD WEn DACKn (Active-low) Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 11.4 Example of DMA Transfer Timing in Dual Mode (Transfer Source: Normal Memory, Transfer Destination: Normal Memory) Page 392 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (b) Section 11 Direct Memory Access Controller Single Address Mode* In single address mode, both the transfer source and destination are external devices, either of them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In this mode, this module performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 11.5, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus External data bus This LSI Direct memory access controller External memory External device with DACK DACK DREQ Data flow (from memory to device) Data flow (from device to memory) Figure 11.5 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Figure 11.6 shows an example of DMA transfer timing in single address mode. Note: * In the SH726A, DACK is unavailable, thus single address mode cannot be used. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 393 of 1910 Section 11 Direct Memory Access Controller SH726A Group, SH726B Group CK A25 to A0 Address output to external memory space CSn Select signal to external memory space WEn Write strobe signal to external memory space D15 to D0 DACKn Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK → External memory space (normal memory) CK A25 to A0 CSn RD D15 to D0 DACKn Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (normal memory) → External device with DACK Figure 11.6 Example of DMA Transfer Timing in Single Address Mode Page 394 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 11 Direct Memory Access Controller Bus Modes There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel control registers (CHCR). (a) Cycle Steal Mode  Normal mode In normal mode of cycle steal, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer request occurs, the bus mastership is obtained from another bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is repeated until the transfer end conditions are satisfied. The cycle-steal normal mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. Figure 11.7 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer conditions shown in the figure are;  Dual address mode  DREQ low level detection DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMA DMA Read/Write CPU DMA DMA CPU Read/Write Figure 11.7 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection)  Intermittent Mode 16 and Intermittent Mode 64 In intermittent mode of cycle steal, this module returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next transfer request occurs after that, this module obtains the bus mastership from other bus master after waiting for 16 or 64 cycles of B clock. This module then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal. When this module obtains again the bus mastership, DMA transfer may be postponed in case of entry updating due to cache miss. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 395 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller The cycle-steal intermittent mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in all channels. Figure 11.8 shows an example of DMA transfer timing in cycle-steal intermittent mode. Transfer conditions shown in the figure are;  Dual address mode  DREQ low level detection DREQ More than 16 or 64 Bφ clock cycles (depending on the state of bus used by bus master such as CPU) Bus cycle CPU CPU CPU DMA DMA CPU CPU Read/Write DMA DMA CPU Read/Write Figure 11.8 Example of DMA Transfer in Cycle-Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) (b) Burst Mode In burst mode, once this module obtains the bus mastership, it does not release the bus mastership and continues to perform transfer until the transfer end condition is satisfied. In external request mode with low-level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus mastership is passed to another bus master after the DMA transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Figure 11.9 shows DMA transfer timing in burst mode. DREQ Bus cycle CPU CPU CPU DMA DMA DMA DMA Read Write Read Write CPU CPU Figure 11.9 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) Page 396 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 11 Direct Memory Access Controller Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 11.9 shows the relationship between request modes and bus modes by DMA transfer category. Table 11.9 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Transfer Mode Size (Bits) Usable Channels Dual External B/C 8/16/32/128 0 External device with DACK and memory- External mapped external device B/C 8/16/32/128 0 Single External device with DACK and external memory External memory and external memory All* 4 B/C 8/16/32/128 0 to 15* 3 External memory and memory-mapped external device All* 4 B/C 8/16/32/128 0 to 15* 3 Memory-mapped external device and memory-mapped external device All* 4 B/C 8/16/32/128 0 to 15* 3 External memory and on-chip peripheral module All* 1 B/C* 5 8/16/32/128* 0 to 15* 2 3 Memory-mapped external device and on-chip peripheral module All* 1 B/C* 5 8/16/32/128* 0 to 15* 2 3 On-chip peripheral module and on-chip peripheral module All* 1 B/C* 5 8/16/32/128* 0 to 15* 2 3 On-chip memory and on-chip memory All* 4 B/C 8/16/32/128 0 to 15* 3 On-chip memory and memory-mapped external device All* 4 B/C 8/16/32/128 0 to 15* 3 On-chip memory and on-chip peripheral module All* 1 B/C* 8/16/32/128* 0 to 15* 3 On-chip memory and external memory All* 4 B/C 8/16/32/128 0 to 15* 3 External device with DACK and external memory External B/C 8/16/32/128 0 External device with DACK and memory- External mapped external device B/C 8/16/32/128 0 5 2 [Legend] B: Burst C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. However, in the case of internal module request, along with the exception of the multi-function timer pulse unit 2 and the compare match timer as the transfer request source, the requesting module must be designated as the transfer source or the transfer destination. In the SH726A, external requests cannot be used. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 397 of 1910 Section 11 Direct Memory Access Controller SH726A Group, SH726B Group 2. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 3. If the transfer request is an external request, channel 0 is only available. 4. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, however, the compare match timer and the multi-function timer pulse unit 2 are only available. In the SH726A, external requests cannot be used. 5. In the case of on-chip peripheral module request, only cycle steal except for the CD-ROM decoder, the multi-function timer pulse unit 2, and the compare match timer as the transfer request source. Page 398 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (4) Section 11 Direct Memory Access Controller Bus Mode and Channel Priority In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0. When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1, channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of this is shown in figure 11.10. When multiple channels are in burst mode, data transfer on the channel that has the highest priority is given precedence. When DMA transfer is being performed on multiple channels, the bus mastership is not released to another bus-master device until all of the competing burst-mode transfers have been completed. CPU CPU DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 CH0 CH1 CH0 Direct memory access controller CH1 Burst mode Direct memory access controller CH0 and CH1 Cycle steal mode DMA CH1 DMA CH1 Direct memory access controller CH1 Burst mode CPU CPU Priority: CH0 > CH1 CH0: Cycle steal mode CH1: Burst mode Figure 11.10 Bus State when Multiple Channels are Operating R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 399 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller 11.4.5 (1) Number of Bus Cycles and DREQ Pin Sampling Timing Number of Bus Cycles When this module is the bus master, the number of bus cycles is controlled by the bus state controller in the same way as when the CPU is the bus master. For details, see section 10, Bus State Controller. (2) DREQ Pin Sampling Timing Figures 11.11 to 11.14 show the DREQ input sampling timings in each bus mode. CKIO Bus cycle DREQ (Rising) CPU CPU 1st acceptance DMA CPU 2nd acceptance Non sensitive period DACK (Active-high) Acceptance start Figure 11.11 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) CPU CPU DMA 1st acceptance CPU 2nd acceptance Non sensitive period DACK (Active-high) Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU CPU 1st acceptance DMA CPU 2nd acceptance Non sensitive period Acceptance start Figure 11.12 Example of DREQ Input Detection in Cycle Steal Mode Level Detection Page 400 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller CKIO Bus cycle DREQ (Rising) CPU CPU DMA DMA Burst acceptance Non sensitive period DACK (Active-high) Figure 11.13 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) CPU CPU DMA 2nd acceptance 1st acceptance Non sensitive period DACK (Active-high) Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) CPU CPU 1st acceptance DMA 2nd acceptance DMA 3rd acceptance Non sensitive period DACK (Active-high) Acceptance start Acceptance start Figure 11.14 Example of DREQ Input Detection in Burst Mode Level Detection R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 401 of 1910 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller Figure 11.15 shows the TEND output timing. CKIO End of DMA transfer Bus cycle DMA CPU DMA CPU CPU DREQ DACK TEND Figure 11.15 Example of DMA Transfer End Signal Timing (Cycle Steal Mode Level Detection) The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is performed for an 8-bit or 16-bit external device or when word transfer is performed for an 8-bit external device. When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS signal for data alignment as shown in figure 11.16. Figures 11.11 to 11.15 show the cases where DACK and TEND are not divided in the DMA transfer. Page 402 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 11 Direct Memory Access Controller T1 T2 Taw T1 T2 CKIO Address CS RD Data WEn DACKn (Active low) TEND (Active low) WAIT Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles, TEND is also divided. Figure 11.16 Bus State Controller Normal Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 403 of 1910 Section 11 Direct Memory Access Controller 11.5 Usage Notes 11.5.1 Timing of DACK and TEND Outputs SH726A Group, SH726B Group The DACK output is asserted with the same timing as the corresponding CS signal. The TEND output does not depend on the type of memory and is always asserted with the same timing as the corresponding CS signal. Page 404 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2 Section 12 Multi-Function Timer Pulse Unit 2 This LSI has an on-chip multi-function timer pulse unit 2 that comprises five 16-bit timer channels. 12.1 Features  Maximum 16 pulse input/output lines  Selection of eight counter input clocks for each channel  The following operations can be set:  Waveform output at compare match  Input capture function  Counter clear operation  Multiple timer counters (TCNT) can be written to simultaneously  Simultaneous clearing by compare match and input capture is possible  Register simultaneous input/output is possible by synchronous counter operation  A maximum 12-phase PWM output is possible in combination with synchronous operation  Buffer operation settable for channels 0, 3, and 4  Phase counting mode settable independently for each of channels 1 and 2  Cascade connection operation  Fast access via internal 16-bit bus  25 interrupt sources  Automatic transfer of register data  A/D converter start trigger can be generated  Module standby mode can be settable  A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible.  AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible.  In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 405 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.1 Functions of Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Count clock P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB General registers TGRA_0 TGRB_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 General registers/ buffer registers TGRC_0 TGRD_0 TGRF_0   TGRC_3 TGRD_3 TGRC_4 TGRD_4 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output                Input capture function      Synchronous operation      PWM mode 1      PWM mode 2      Complementary PWM mode      Reset PWM mode      AC synchronous motor drive mode      Page 406 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Phase counting mode      Buffer operation      Activation of direct TGR compare memory access match or input controller capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow A/D converter start trigger TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TGRA_0 compare match or input capture TGRE_0 compare match Interrupt sources TCNT_4 underflow (trough) in complementary PWM mode 7 sources 4 sources 4 sources 5 sources 5 sources       Compare   Compare Compare match or match or match or input capture input capture input capture input capture input capture 0A 1A 2A 3A 4A Compare  Compare  Compare  Compare  Compare match or match or match or match or match or input capture input capture input capture input capture input capture 1B Compare  match or  2B Overflow  Underflow  Overflow 4B 3B  Compare  Compare match or match or input capture input capture input capture 0C 3C 4C Compare Underflow  Compare  Compare match or match or match or input capture input capture input capture 0D 3D 4D Compare match 0E  Compare match or 0B  Compare match or  Overflow  Overflow or underflow Compare match 0F  Overflow R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 407 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 A/D converter start request delaying function      A/D converter start request at a match between TADCORA_4 and TCNT_4  A/D converter start request at a match between TADCORB_4 and TCNT_4 Interrupt skipping function     Skips  Skips TCIV_4 interrupts TGRA_3 compare match interrupts [Legend] Available : : Not available Page 408 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TGRD TGRD TGRB TGRC TGRB TGRC TCBR TDDR TCNT TCDR TGRA TCNT TGRA TCNTS TGRF TGRE TGRD TGRB TGRB TGRB A/D converter conversion start signal TGRC TCNT TCNT TGRA TCNT TGRA BUS I/F Module data bus TSYR TSTR TSR TIER TSR TIER TSR TIER TIOR TIOR TIORL TIORH Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 Peripheral bus TGRA TSR TIER TIER TGCR TSR TMDR TIORL TIORH TIORL TIORH TOER TOCR Channel 3 Channel 4 TCR TMDR TCR TMDR Channel 1 TCR TMDR Channel 0 TCR Control logic for channels 0 to 2 Channel 2 Common Control logic Clock input Internal clock: Pφ/1 Pφ/4 Pφ/16 Pφ/64 Pφ/256 Pφ/1024 External clock: TCLKA TCLKB TCLKC TCLKD Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B TCR Control logic for channels 3 and 4 Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D TMDR Figure 12.1 shows a block diagram. Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2 [Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Figure 12.1 Block Diagram R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 409 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.2 SH726A Group, SH726B Group Input/Output Pins Table 12.2 shows the pin configuration. Table 12.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input) TIOC0A I/O TGRA_0 input capture input/output compare output/PWM output pin TIOC0B I/O TGRB_0 input capture input/output compare output/PWM output pin TIOC0C I/O TGRC_0 input capture input/output compare output/PWM output pin TIOC0D I/O TGRD_0 input capture input/output compare output/PWM output pin TIOC1A I/O TGRA_1 input capture input/output compare output/PWM output pin TIOC1B I/O TGRB_1 input capture input/output compare output/PWM output pin TIOC2A I/O TGRA_2 input capture input/output compare output/PWM output pin TIOC2B I/O TGRB_2 input capture input/output compare output/PWM output pin TIOC3A I/O TGRA_3 input capture input/output compare output/PWM output pin TIOC3B I/O TGRB_3 input capture input/output compare output/PWM output pin TIOC3C I/O TGRC_3 input capture input/output compare output/PWM output pin TIOC3D I/O TGRD_3 input capture input/output compare output/PWM output pin TIOC4A I/O TGRA_4 input capture input/output compare output/PWM output pin TIOC4B I/O TGRB_4 input capture input/output compare output/PWM output pin TIOC4C I/O TGRC_4 input capture input/output compare output/PWM output pin TIOC4D I/O TGRD_4 input capture input/output compare output/PWM output pin 0 1 2 3 4 Note: For the pin configuration in complementary PWM mode, see table 12.54 in section 12.4.8, Complementary PWM Mode. Page 410 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.3 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Register Descriptions Table 12.3 shows the register configuration. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 12.3 Register Configuration Channel Register Name Abbreviation R/W Initial value Address Access Size 0 Timer control register_0 TCR_0 R/W H'00 H'FFFE4300 8 Timer mode register_0 TMDR_0 R/W H'00 H'FFFE4301 8 1 Timer I/O control register H_0 TIORH_0 R/W H'00 H'FFFE4302 8 Timer I/O control register L_0 TIORL_0 R/W H'00 H'FFFE4303 8 Timer interrupt enable register_0 TIER_0 R/W H'00 H'FFFE4304 8 Timer status register_0 TSR_0 R/W H'C0 H'FFFE4305 8 Timer counter_0 TCNT_0 R/W H'0000 H'FFFE4306 16 Timer general register A_0 TGRA_0 R/W H'FFFF H'FFFE4308 16 16 Timer general register B_0 TGRB_0 R/W H'FFFF H'FFFE430A Timer general register C_0 TGRC_0 R/W H'FFFF H'FFFE430C 16 Timer general register D_0 TGRD_0 R/W H'FFFF H'FFFE430E 16 Timer general register E_0 TGRE_0 R/W H'FFFF H'FFFE4320 16 Timer general register F_0 TGRF_0 R/W H'FFFF H'FFFE4322 16 Timer interrupt enable register TIER2_0 2_0 R/W H'00 H'FFFE4324 8 Timer status register 2_0 TSR2_0 R/W H'C0 H'FFFE4325 8 Timer buffer operation transfer TBTM_0 mode register_0 R/W H'00 H'FFFE4326 8 Timer control register_1 TCR_1 R/W H'00 H'FFFE4380 8 Timer mode register_1 TMDR_1 R/W H'00 H'FFFE4381 8 Timer I/O control register_1 TIOR_1 R/W H'00 H'FFFE4382 8 Timer interrupt enable register_1 TIER_1 R/W H'00 H'FFFE4384 8 Timer status register_1 TSR_1 R/W H'C0 H'FFFE4385 8 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 411 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Channel Register Name Abbreviation R/W Initial value Address Access Size 1 Timer counter_1 TCNT_1 R/W H'0000 H'FFFE4386 16 Timer general register A_1 TGRA_1 R/W H'FFFF H'FFFE4388 16 Timer general register B_1 TGRB_1 R/W H'FFFF H'FFFE438A 16 Timer input capture control register TICCR R/W H'00 H'FFFE4390 8 Timer control register_2 TCR_2 R/W H'00 H'FFFE4000 8 Timer mode register_2 TMDR_2 R/W H'00 H'FFFE4001 8 Timer I/O control register_2 TIOR_2 R/W H'00 H'FFFE4002 8 Timer interrupt enable register_2 TIER_2 R/W H'00 H'FFFE4004 8 Timer status register_2 TSR_2 R/W H'C0 H'FFFE4005 8 Timer counter_2 TCNT_2 R/W H'0000 H'FFFE4006 16 Timer general register A_2 TGRA_2 R/W H'FFFF H'FFFE4008 16 Timer general register B_2 TGRB_2 R/W H'FFFF H'FFFE400A 16 Timer control register_3 TCR_3 R/W H'00 H'FFFE4200 8 Timer mode register_3 TMDR_3 R/W H'00 H'FFFE4202 8 Timer I/O control register H_3 TIORH_3 R/W H'00 H'FFFE4204 8 Timer I/O control register L_3 TIORL_3 R/W H'00 H'FFFE4205 8 Timer interrupt enable register_3 TIER_3 R/W H'00 H'FFFE4208 8 Timer status register_3 TSR_3 R/W H'C0 H'FFFE422C 8 Timer counter_3 TCNT_3 R/W H'0000 H'FFFE4210 16 Timer general register A_3 TGRA_3 R/W H'FFFF H'FFFE4218 16 Timer general register B_3 TGRB_3 R/W H'FFFF H'FFFE421A 16 Timer general register C_3 TGRC_3 R/W H'FFFF H'FFFE4224 16 Timer general register D_3 2 3 4 TGRD_3 R/W H'FFFF H'FFFE4226 16 Timer buffer operation transfer TBTM_3 mode register_3 R/W H'00 H'FFFE4238 8 Timer control register_4 TCR_4 R/W H'00 H'FFFE4201 8 Timer mode register_4 TMDR_4 R/W H'00 H'FFFE4203 8 Timer I/O control register H_4 TIORH_4 R/W H'00 H'FFFE4206 8 Timer I/O control register L_4 TIORL_4 R/W H'00 H'FFFE4207 8 Page 412 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Channel Register Name Abbreviation R/W Initial value Address Access Size 4 Timer interrupt enable register_4 TIER_4 R/W H'00 H'FFFE4209 8 Timer status register_4 TSR_4 R/W H'C0 H'FFFE422D 8 H'FFFE4212 Timer counter_4 TCNT_4 R/W H'0000 Timer general register A_4 TGRA_4 R/W H'FFFF H'FFFE421C 16 Timer general register B_4 TGRB_4 R/W H'FFFF H'FFFE421E 16 Timer general register C_4 TGRC_4 R/W H'FFFF H'FFFE4228 Timer general register D_4 TGRD_4 R/W H'FFFF H'FFFE422A 16 Timer buffer operation transfer TBTM_4 mode register_4 R/W H'00 H'FFFE4239 8 Timer A/D converter start request control register TADCR R/W H'0000 H'FFFE4240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 R/W H'FFFF H'FFFE4244 16 Timer A/D converter start request cycle set register B_4 TADCORB_4 R/W H'FFFF H'FFFE4246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 R/W H'FFFF H'FFFE4248 16 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 R/W H'FFFF H'FFFE424A 16 TSTR R/W H'00 H'FFFE4280 8 Timer synchronous register TSYR R/W H'00 H'FFFE4281 8 Timer read/write enable register TRWER R/W H'01 H'FFFE4284 8 Common Timer start register R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 16 16 Page 413 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Channel Register Name Abbreviation R/W Initial value Address Access Size TOER Common Timer output master enable to 3 and register 4 Timer output control register 1 TOCR1 R/W H'C0 H'FFFE420A 8 R/W H'00 H'FFFE420E 8 Timer output control register 2 TOCR2 R/W H'00 H'FFFE420F 8 Timer gate control register TGCR R/W H80 H'FFFE420D 8 Timer cycle data register TCDR R/W H'FFFF H'FFFE4214 16 Timer dead time data register TDDR R/W H'FFFF H'FFFE4216 16 Timer subcounter TCNTS R H'0000 H'FFFE4220 16 Timer cycle buffer register TCBR R/W H'FFFF H'FFFE4222 16 Timer interrupt skipping set register TITCR R/W H'00 H'FFFE4230 8 Timer interrupt skipping counter TITCNT R H'00 H'FFFE4231 8 Timer buffer transfer set register TBTER R/W H'00 H'FFFE4232 8 Timer dead time enable register TDER R/W H'01 H'FFFE4234 8 Timer waveform control register TWCR R/W H'00 H'FFFE4260 8 Timer output level buffer register TOLBR R/W H'00 H'FFFE4236 8 Page 414 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.3.1 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. This module has a total of five TCR registers, one each for channels 0 to 4. TCR register settings should be conducted only when TCNT operation is stopped. Bit: 7 6 5 CCLR[2:0] Initial value: 0 R/W: R/W 0 R/W 4 3 2 CKEG[1:0] 0 R/W 0 R/W 0 R/W 1 0 TPSC[2:0] 0 R/W Bit Bit Name Initial Value R/W Description 7 to 5 CCLR[2:0] 000 R/W Counter Clear 0 to 2 0 R/W 0 R/W These bits select the TCNT counter clearing source. See tables 12.4 and 12.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. When P/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 12.6 to 12.9 for details. [Legend] x: Don't care R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 415 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3, 4 0 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match/input 2 capture* 0 TCNT cleared by TGRD compare match/input 2 capture* 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 12.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Bit 6 2 Reserved* CCLR1 Bit 5 CCLR0 Description 1, 2 0 0 TCNT clearing disabled 1 TCNT cleared by TGRA compare match/input capture 0 TCNT cleared by TGRB compare match/input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 0 1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified. Page 416 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.6 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on P/1 1 Internal clock: counts on P/4 0 Internal clock: counts on P/16 1 Internal clock: counts on P/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 Table 12.7 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on P/1 1 Internal clock: counts on P/4 0 Internal clock: counts on P/16 1 Internal clock: counts on P/64 0 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 0 Internal clock: counts on P/256 1 Counts on TCNT_2 overflow/underflow 1 1 Note: This setting is ignored when channel 1 is in phase counting mode. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 417 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.8 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on P/1 1 Internal clock: counts on P/4 0 Internal clock: counts on P/16 1 Internal clock: counts on P/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 Internal clock: counts on P/1024 1 1 0 1 Note: This setting is ignored when channel 2 is in phase counting mode. Table 12.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3, 4 0 0 0 Internal clock: counts on P/1 1 Internal clock: counts on P/4 0 Internal clock: counts on P/16 1 Internal clock: counts on P/64 0 Internal clock: counts on P/256 1 Internal clock: counts on P/1024 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 1 1 0 1 Page 418 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.3.2 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. This module has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: Initial value: R/W: 7 6 5 4 - BFE BFB BFA 0 R 0 R/W 0 R/W 0 R/W 3 2 1 0 MD[3:0] 0 R/W Bit Bit Name Initial Value R/W Description 7  0 R Reserved 0 R/W 0 R/W 0 R/W This bit is always read as 0. The write value should always be 0. 6 BFE 0 R/W Buffer Operation E Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. TGRF compare match is generated when TGRF is used as the buffer register. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 419 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 5 BFB 0 R/W Buffer Operation B SH726A Group, SH726B Group Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated in a mode other than complementary PWM. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated in a mode other than complementary PWM. TGRC compare match is generated when in complementary PWM mode. When compare match for channel 4 occurs during the Tb period in complementary PWM mode, TGFC is set. Therefore, set the TGIEC bit in the timer interrupt enable register 4 (TIER_4) to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 12.10 for details. Page 420 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.10 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Setting prohibited 0 PWM mode 1 1 PWM mode 2* 0 Phase counting mode 1* 2 1 Phase counting mode 2* 2 0 Phase counting mode 3* 2 1 Phase counting mode 4* 2 0 Reset synchronous PWM mode* 1 Setting prohibited 1 X Setting prohibited 0 0 Setting prohibited 1 Complementary PWM mode 1 (transmit at crest)* 0 Complementary PWM mode 2 (transmit at trough)* 1 Complementary PWM mode 2 (transmit at crest and 3 trough)* 1 1 0 1 1 0 1 0 1 1 3 3 3 [Legend] X: Don't care Notes: 1. PWM mode 2 cannot be set for channels 3 and 4. 2. Phase counting mode cannot be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 421 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. This module has a total of eight TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2. TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.  TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: 7 6 5 4 3 IOB[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 2 1 0 IOA[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4 IOB[3:0] 0000 R/W I/O Control B0 to B3 0 R/W 0 R/W Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: 3 to 0 IOA[3:0] 0000 R/W Table 12.11 Table 12.13 Table 12.14 Table 12.15 Table 12.17 I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Page 422 of 1910 Table 12.19 Table 12.21 Table 12.22 Table 12.23 Table 12.25 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2  TIORL_0, TIORL_3, TIORL_4 Bit: 7 6 5 4 3 IOD[3:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 2 1 0 IOC[3:0] 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3 0 R/W 0 R/W Specify the function of TGRD. See the following tables. TIORL_0: Table 12.12 TIORL_3: Table 12.16 TIORL_4: Table 12.18 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 12.20 TIORL_3: Table 12.24 TIORL_4: Table 12.26 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 423 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.11 TIORH_0 (Channel 0) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 Output compare register 1 TIOC0B Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 424 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.12 TIORL_0 (Channel 0) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 Output compare 2 register* 1 TIOC0D Pin Function 1 Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 425 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.13 TIOR_1 (Channel 1) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 Output compare register 1 TIOC1B Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 426 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.14 TIOR_2 (Channel 2) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 Output compare register 1 TIOC2B Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 427 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.15 TIORH_3 (Channel 3) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_3 Function 0 0 0 0 Output compare register 1 TIOC3B Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 428 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.16 TIORL_3 (Channel 3) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_3 Function 0 0 0 0 Output compare 2 register* 1 TIOC3D Pin Function 1 Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 429 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.17 TIORH_4 (Channel 4) Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_4 Function 0 0 0 0 Output compare register 1 TIOC4B Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 430 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.18 TIORL_4 (Channel 4) Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_4 Function 0 0 0 0 Output compare 2 register* 1 TIOC4D Pin Function 1 Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 431 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.19 TIORH_0 (Channel 0) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 Output compare register 1 TIOC0A Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 432 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.20 TIORL_0 (Channel 0) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 Output compare 2 register* 1 TIOC0C Pin Function 1 Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge 1 X Input capture at both edges X X Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 433 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.21 TIOR_1 (Channel 1) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 Output compare register 1 TIOC1A Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 1 0 0 1 Input capture Input capture at rising edge register Input capture at falling edge 1 X Input capture at both edges X X Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 434 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.22 TIOR_2 (Channel 2) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 Output compare register 1 TIOC2A Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 435 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.23 TIORH_3 (Channel 3) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_3 Function 0 0 0 0 Output compare register 1 TIOC3A Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 436 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.24 TIORL_3 (Channel 3) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_3 Function 0 0 0 0 Output compare 2 register* 1 TIOC3C Pin Function 1 Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 437 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.25 TIORH_4 (Channel 4) Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_4 Function 0 0 0 0 Output compare register 1 TIOC4A Pin Function Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge register Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Note: * After power-on reset, 0 is output until TIOR is set. Page 438 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.26 TIORL_4 (Channel 4) Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_4 Function 0 0 0 0 Output compare 2 register* 1 TIOC4C Pin Function 1 Output retained* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 1 0 1 Input capture Input capture at rising edge 2 register* Input capture at falling edge X Input capture at both edges [Legend] X: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 439 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. This module has six TIER registers, two for channel 0 and one each for channels 1 to 4.  TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 Bit: 7 6 5 4 3 2 1 0 TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 TTGE 0 R/W A/D Converter Start Request Enable Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled 6 TTGE2 0 R/W A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled Page 440 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 441 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2  TIER2_0 Bit: 7 6 5 4 3 2 TTGE2 - - - - - 0 R 0 R 0 R 0 R 0 R Initial value: 0 R/W: R/W 1 0 TGIEF TGIEE 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 TTGE2 0 R/W A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGIEF 0 R/W TGR Interrupt Enable F Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled 0 TGIEE 0 R/W TGR Interrupt Enable E Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled Page 442 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.3.5 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. This module has six TSR registers, two for channel 0 and one each for channels 1 to 4.  TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TCFD - TCFU TCFV TGFD TGFC TGFB TGFA 1 R 1 R 0 0 0 0 0 0 R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W 7 TCFD 1 R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6  1 R Reserved This bit is always read as 1. The write value should always be 1. 5 TCFU 0 1 R/(W)* Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]  When 0 is written to TCFU after reading TCFU = 1* 2 [Setting condition]  R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 When the TCNT value underflows (changes from H'0000 to H'FFFF) Page 443 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit 4 Bit Name TCFV Initial Value 0 R/W SH726A Group, SH726B Group Description 1 R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Clearing condition]  When 0 is written to TCFV after reading 2 TCFV = 1* [Setting condition]  3 TGFD 0 When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. 1 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]  When 0 is written to TGFD after reading 2 TGFD = 1* [Setting conditions] Page 444 of 1910  When TCNT = TGRD and TGRD is functioning as output compare register  When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Bit 2 Bit Name TGFC Initial Value 0 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 R/W Description 1 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Clearing condition]  When 0 is written to TGFC after reading 2 TGFC = 1* [Setting conditions] 1 TGFB 0  When TCNT = TGRC and TGRC is functioning as output compare register  When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register 1 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Clearing condition]  When 0 is written to TGFB after reading 2 TGFB = 1* [Setting conditions] R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015  When TCNT = TGRB and TGRB is functioning as output compare register  When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register Page 445 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit 0 Bit Name TGFA Initial Value 0 R/W SH726A Group, SH726B Group Description 1 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Clearing conditions]  When the direct memory access controller is activated by TGIA interrupt  When 0 is written to TGFA after reading 2 TGFA = 1* [Setting conditions]  When TCNT = TGRA and TGRA is functioning as output compare register  When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag. 2. If the next flag is set before TGFA is cleared to 0 after reading TGFA = 1, TGFA remains 1 even when 0 is written to. In this case, read TGFA = 1 again to clear TGFA to 0. Page 446 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2  TSR2_0 Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - TGFF TGFE 1 R 1 R 0 R 0 R 0 R 0 R 0 0 R/(W)*1 R/(W)*1 Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 TGFF 0 R/(W)* 1 Compare Match Flag F Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Clearing condition]  When 0 is written to TGFF after reading 2 TGFF = 1* [Setting condition]  0 TGFE 0 R/(W)* 1 When TCNT_0 = TGRF_0 and TGRF_0 is functioning as compare register Compare Match Flag E Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Clearing condition]  When 0 is written to TGFE after reading 2 TGFE = 1* [Setting condition]  When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag. 2. If the next flag is set before TGFA is cleared to 0 after reading TGFA = 1, TGFA remains 1 even when 0 is written to. In this case, read TGFA = 1 again to clear TGFA to 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 447 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.6 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. This module has three TBTM registers, one each for channels 0, 3, and 4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - TTSE TTSB TTSA 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 TTSE 0 R/W Timing Select E Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared 1 TTSB 0 R/W Timing Select B Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel 0 TTSA 0 R/W Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel Page 448 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.3.7 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Timer Input Capture Control Register (TICCR) TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. This module has one TICCR in channel 1. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - I2BE I2AE I1BE I1AE 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 I2BE 0 R/W Input Capture Enable Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions 2 I2AE 0 R/W Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions 1 I1BE 0 R/W Input Capture Enable Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 449 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 0 I1AE 0 R/W Input Capture Enable SH726A Group, SH726B Group Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions Page 450 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.3.8 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. This module has one TADCR in channel 4. Bit: 15 14 BF[1:0] Initial value: 0 R/W: R/W 0 R/W 13 12 11 10 9 8 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE 0 R/W 0* R/W 0 R/W 0* R/W 0* R/W 0* R/W 0* R/W 0* R/W Note: * Do not set to 1 when complementary PWM mode is not selected. Bit Bit Name Initial Value R/W Description 15, 14 BF[1:0] 00 R/W TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 12.27. 13 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 UT4AE 0 R/W Up-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation 6 DT4AE 0* R/W Down-Count TRG4AN Enable Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 451 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 5 UT4BE 0 R/W Up-Count TRG4BN Enable SH726A Group, SH726B Group Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation 4 DT4BE 0* R/W Down-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation 3 ITA3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping 2 ITA4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping 1 ITB3AE 0* R/W TGIA_3 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping Page 452 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 0 ITB4VE 0* R/W TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 12.27 Setting of Transfer Timing by Bits BF1 and BF0 Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set 1 register at the crest of the TCNT_4 count.* 1 0 Transfers data from the cycle set buffer register to the cycle set 2 register at the trough of the TCNT_4 count.* 1 1 Transfers data from the cycle set buffer register to the cycle set 2 register at the crest and trough of the TCNT_4 count.* Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 453 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.9 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. 12.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits. Page 454 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.11 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. This module has five TCNT counters, one each for channels 0 to 4. The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. Bit: 15 Initial value: 0 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. 12.3.12 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers. This module has eighteen TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 455 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.13 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit: 7 6 5 4 3 2 1 0 CST4 CST3 - - - CST2 CST1 CST0 Initial value: 0 R/W: R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 CST4 0 R/W Counter Start 4 and 3 6 CST3 0 R/W These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 CST2 0 R/W Counter Start 2 to 0 1 CST1 0 R/W These bits select operation or stoppage for TCNT. 0 CST0 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation Page 456 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.14 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: 7 6 SYNC4 SYNC3 Initial value: 0 R/W: R/W 0 R/W 5 4 3 - - - 0 R 0 R 0 R 2 1 0 SYNC2 SYNC1 SYNC0 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 SYNC4 0 R/W Timer Synchronous operation 4 and 3 6 SYNC3 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 457 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Bit Bit Name Initial Value R/W Description 2 SYNC2 0 R/W Timer Synchronous operation 2 to 0 1 SYNC1 0 R/W 0 SYNC0 0 R/W These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Page 458 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.15 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and 4. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - RWE 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 RWE 1 R/W Read/Write Enable Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition]  When 0 is written to the RWE bit after reading RWE = 1  Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 459 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.16 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Make settings of the TOER while counting by the TCNT registers of channels 3 and 4 is stopped. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - OE4D OE4C OE3D OE4B OE4A OE3B 1 R 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7, 6  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled Page 460 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled 0 OE3B 0 R/W Master Enable TIOC3B This bit enables/disables the TIOC3B pin output for this module. 0: Output for this module is disabled (inactive level)* 1: Output for this module is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 12.3.17, Timer Output Control Register 1 (TOCR1), and section 12.3.18, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable output for this module in other than complementary PWM or reset-synchronized PWM mode. When these bits are set to 0, low level is output. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 461 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.17 Timer Output Control Register 1 (TOCR1) TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - PSYE - - TOCL TOCS OLSN OLSP 0 R 0 R/W 0 R 0 R 0 0 R/(W)*3 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7  0 R Reserved This bit is always read as 0. The write value should always be 0. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 462 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Bit 3 Bit Name TOCL Initial value 0 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 R/W Description 3 R/(W)* TOC Register Write Protection* 1 This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled 2 TOCS 0 R/W TOC Select This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected 1 OLSN 0 R/W 2 4 Output Level Select N* * This bit selects the negative phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 12.28. 0 OLSP 0 R/W Output Level Select P* 2 This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 12.29. Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 2. Clearing the TOCS0 bit to 0 makes this bit setting valid. 3. After power-on reset, 1 can be written only once. After 1 has been written, 0 cannot be written. 4. If the dead-time is not generated, the negative-phase output will be the exact inverse of the positive-phase output. Furthermore, set OLSP and OLSN to the same value. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 463 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.28 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The negative phase waveform initial output value changes to active level after elapse of the dead time after count start. Table 12.29 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. Page 464 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT_3, and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Time Positive phase output Initial output Negative phase output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Figure 12.2 Complementary PWM Mode Output Level Example R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 465 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.18 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: 7 6 BF[1:0] Initial value: 0 R/W: R/W 0 R/W 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7, 6 BF[1:0] 00 R/W TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 12.30. 5 OLS3N 0 R/W Output Level Select 3N* This bit selects the output level on TIOC4D in resetsynchronized PWM mode/complementary PWM mode. See table 12.31. 4 OLS3P 0 R/W Output Level Select 3P* This bit selects the output level on TIOC4B in resetsynchronized PWM mode/complementary PWM mode. See table 12.32. 3 OLS2N 0 R/W Output Level Select 2N* This bit selects the output level on TIOC4C in resetsynchronized PWM mode/complementary PWM mode. See table 12.33. 2 OLS2P 0 R/W Output Level Select 2P* This bit selects the output level on TIOC4A in resetsynchronized PWM mode/complementary PWM mode. See table 12.34. 1 OLS1N 0 R/W Output Level Select 1N* This bit selects the output level on TIOC3D in resetsynchronized PWM mode/complementary PWM mode. See table 12.35. Page 466 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial value R/W Description 0 OLS1P 0 R/W Output Level Select 1P* This bit selects the output level on TIOC3B in resetsynchronized PWM mode/complementary PWM mode. See table 12.36. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. If the dead-time is not generated, the negative-phase output will be the exact inverse of the positive-phase output. Furthermore, set OLSiP and OLSiN (i = 1, 2, 3) to the same value. Table 12.30 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description BF1 BF0 Complementary PWM Mode 0 0 Does not transfer data from the Does not transfer data from the buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2. 0 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared 1 0 Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Setting prohibited 1 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Setting prohibited Reset-Synchronized PWM Mode Table 12.31 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The negative phase waveform initial output value changes to the active level after elapse of the dead time after count start. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 467 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.32 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Table 12.33 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The negative phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 12.34 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level Table 12.35 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count 0 High level Low level High level Low level 1 Low level High level Low level High level Note: The negative phase waveform initial output value changes to the active level after elapse of the dead time after count start. Page 468 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.36 TIOC4B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count Down Count 0 High level Low level Low level High level 1 Low level High level High level Low level 12.3.19 Timer Output Level Buffer Register (TOLBR) TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7 6 - - 0 R 0 R 5 4 3 2 1 0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7, 6  All 0 R Reserved 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 5 OLS3N 0 R/W Specifies the buffer value to be transferred to the OLS3N bit in TOCR2. 4 OLS3P 0 R/W Specifies the buffer value to be transferred to the OLS3P bit in TOCR2. 3 OLS2N 0 R/W Specifies the buffer value to be transferred to the OLS2N bit in TOCR2. 2 OLS2P 0 R/W Specifies the buffer value to be transferred to the OLS2P bit in TOCR2. 1 OLS1N 0 R/W Specifies the buffer value to be transferred to the OLS1N bit in TOCR2. 0 OLS1P 0 R/W Specifies the buffer value to be transferred to the OLS1P bit in TOCR2. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 469 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Figure 12.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [1] [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. Set TOCR2 [2] [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Set TOLBR [3] Figure 12.3 PWM Output Level Setting Procedure in Buffer Operation 12.3.20 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - BDC N P FB WF VF UF 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7  1 R Reserved This bit is always read as 1. The write value should always be 1. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective Page 470 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial value R/W Description 5 N 0 R/W Negative Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/negative phase is carried out automatically with channel-0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (setting values of UF, VF, and WF in TGCR). 2 WF 0 R/W Output Phase Switch 2 to 0 1 VF 0 R/W 0 UF 0 R/W These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 12.37. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 471 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.37 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D WF VF UF U Phase V Phase W Phase U Phase V Phase W Phase 0 0 0 OFF OFF OFF OFF OFF OFF 1 ON OFF OFF OFF OFF ON 0 OFF ON OFF ON OFF OFF 1 OFF ON OFF OFF OFF ON 0 OFF OFF ON OFF ON OFF 1 ON OFF OFF OFF ON OFF 0 OFF OFF ON ON OFF OFF 1 OFF OFF OFF OFF OFF OFF 1 1 0 1 12.3.21 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. Page 472 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.22 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 12.3.23 Timer Cycle Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value (a value of two times TDDR + 3 or greater) as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 473 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.24 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF. Bit: 15 Initial value: 1 R/W: R/W Note: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 12.3.25 Timer Interrupt Skipping Set Register (TITCR) TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. This module has one TITCR. Bit: 7 6 T3AEN Initial value: 0 R/W: R/W 5 4 3ACOR[2:0] 0 R/W 0 R/W 3 2 T4VEN 0 R/W 0 R/W Bit Bit Name Initial value R/W Description 7 T3AEN 0 R/W T3AEN 1 0 4VCOR[2:0] 0 R/W 0 R/W 0 R/W Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 12.38. 3 T4VEN 0 R/W T4VEN Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled Page 474 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Initial value Bit Bit Name 2 to 0 4VCOR[2:0] 000 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 R/W Description R/W These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 12.39. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TICNT). Table 12.38 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description 0 0 0 Does not skip TGIA_3 interrupts. 0 0 1 Sets the TGIA_3 interrupt skipping count to 1. 0 1 0 Sets the TGIA_3 interrupt skipping count to 2. 0 1 1 Sets the TGIA_3 interrupt skipping count to 3. 1 0 0 Sets the TGIA_3 interrupt skipping count to 4. 1 0 1 Sets the TGIA_3 interrupt skipping count to 5. 1 1 0 Sets the TGIA_3 interrupt skipping count to 6. 1 1 1 Sets the TGIA_3 interrupt skipping count to 7. Table 12.39 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 Bit 1 Bit 0 4VCOR2 4VCOR1 4VCOR0 Description 0 0 0 Does not skip TCIV_4 interrupts. 0 0 1 Sets the TCIV_4 interrupt skipping count to 1. 0 1 0 Sets the TCIV_4 interrupt skipping count to 2. 0 1 1 Sets the TCIV_4 interrupt skipping count to 3. 1 0 0 Sets the TCIV_4 interrupt skipping count to 4. 1 0 1 Sets the TCIV_4 interrupt skipping count to 5. 1 1 0 Sets the TCIV_4 interrupt skipping count to 6. 1 1 1 Sets the TCIV_4 interrupt skipping count to 7. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 475 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.26 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. This module has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: 7 6 - Initial value: R/W: 5 4 3ACNT[2:0] 0 R 0 R 0 R 3 2 - 0 R Bit Bit Name Initial Value R/W Description 7  0 R Reserved 0 R 1 0 4VCNT[2:0] 0 R 0 R 0 R This bit is always read as 0. 6 to 4 3ACNT[2:0] 000 R TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions] 3  0 R  When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR  When the T3AEN bit in TITCR is cleared to 0  When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 Reserved This bit is always read as 0. 2 to 0 4VCNT[2:0] 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions]  When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR  When the T4VEN bit in TITCR is cleared to 0  When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Note: To clear the TITCNT, clear the bits T3AEN and T4VEN in TITCR to 0. Page 476 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.27 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. This module has one TBTER. Bit: Initial value: R/W: 7 6 5 4 3 2 - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 7 to 2  All 0 R Reserved 1 0 BTE[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 12.40. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 477 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.40 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description 0 0 Enables transfer from the buffer registers to the temporary registers* and does not link the transfer with interrupt skipping operation. 0 1 Disables transfer from the buffer registers to the temporary registers. 1 0 Links transfer from the buffer registers to the temporary registers with 2 interrupt skipping operation.* 1 1 Setting prohibited 1 Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 12.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed. Page 478 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.28 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. This module has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 - - - - - - - TDER 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/(W) Bit Bit Name Initial Value R/W Description 7 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 TDER 1 R/(W) Dead Time Enable Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition]  Note: * When 0 is written to TDER after reading TDER = 1 TDDR must be set to 1 or a larger value. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 479 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.3.29 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: 7 6 5 4 3 2 1 0 CCE - - - - - - WRE 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W) Initial value: 0* R/W: R/(W) Note: * Do not set to 1 when complementary PWM mode is not selected. Bit Bit Name Initial Value R/W Description 7 CCE 0* R/(W) Compare Match Clear Enable Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition]  6 to 1  All 0 R When 1 is written to CCE after reading CCE = 0 Reserved These bits are always read as 0. The write value should always be 0. Page 480 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit Bit Name Initial Value R/W Description 0 WRE 0 R/(W) Initial Output Suppression Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The initial output is suppressed only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 12.40. 0: Outputs the initial value specified in TOCR 1: Suppresses initial output [Setting condition]  Note: * When 1 is written to WRE after reading WRE = 0 Do not set to 1 when complementary PWM mode is not selected. 12.3.30 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 481 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4 Operation 12.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select functions for external pins of this module using the general I/O ports. (1) Counter Operation When one of bits CST0 to CST4 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure Figure 12.4 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Operation selection Select counter clock [1] Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Free-running counter Periodic counter [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 12.4 Example of Counter Operation Setting Procedure Page 482 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (b) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the TCNT counters of this module are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, this module requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 12.5 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 12.5 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, this module requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 483 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Figure 12.6 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 12.6 Periodic Counter Operation (2) Waveform Output by Compare Match This module can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match Figure 12.7 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Start count operation [3] [3] Set the CST bit in TSTR to 1 to start the count operation. Figure 12.7 Example of Setting Procedure for Waveform Output by Compare Match Page 484 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (b) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Examples of Waveform Output Operation: Figure 12.8 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA No change TIOCB No change 0 output Figure 12.8 Example of 0 Output/1 Output Operation Figure 12.9 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle output TIOCB Toggle output TIOCA Figure 12.9 Example of Toggle Output Operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 485 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (3) SH726A Group, SH726B Group Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. (a) Example of Input Capture Operation Setting Procedure Figure 12.10 shows an example of the input capture operation setting procedure. Input selection Select input capture input [1] [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 12.10 Example of Input Capture Operation Setting Procedure Page 486 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (b) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Example of Input Capture Operation Figure 12.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 12.11 Example of Input Capture Operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 487 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4.2 SH726A Group, SH726B Group Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. (1) Example of Synchronous Operation Setting Procedure Figure 12.12 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 12.12 Example of Synchronous Operation Setting Procedure Page 488 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Example of Synchronous Operation Figure 12.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 12.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOC0A TIOC1A TIOC2A Figure 12.13 Example of Synchronous Operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 489 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 12.41 shows the register combinations used in buffer operation. Table 12.41 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRE_0 TGRF_0 3 TGRA_3 TGRC_3 TGRB_3 TGRD_3 4 TGRA_4 TGRC_4 TGRB_4 TGRD_4  When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 12.14. Compare match signal Buffer register Timer general register Comparator TCNT Figure 12.14 Compare Match Buffer Operation Page 490 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2  When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 12.15. Input capture signal Buffer register Timer general register TCNT Figure 12.15 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 12.16 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation Select TGR function [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Start count [3] Figure 12.16 Example of Buffer Operation Setting Procedure R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 491 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (2) Examples of Buffer Operation (a) When TGR is an output compare register Figure 12.17 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. In this example, the TTSA bit in TBTM is cleared to 0. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 12.4.5, PWM Modes. TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 TGRC_0 H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 12.17 Example of Buffer Operation (1) (b) When TGR is an input capture register Figure 12.18 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Page 492 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 12.18 Example of Buffer Operation (2) (3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer timing is one of the following cases.  When TCNT overflows (H'FFFF to H'0000)  When H'0000 is written to TCNT during counting  When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits in TCR Note: TBTM must be modified only while TCNT stops. Figure 12.19 shows an operation example in which PWM mode 1 is designated for channel 0 and buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. The TTSA bit in TBTM_0 is set to 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 493 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT_0 value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 H'0000 TGRC_0 Time H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 H'0520 TIOCA Figure 12.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing 12.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 12.42 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 12.42 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). The condition for input capture is the detection of an edge in the signal obtained from the logical OR of the signal on the main input pin and the signal on the additional input pin. For details, see (4), Page 494 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Cascaded Operation Example (c). For input capture in cascade connection, refer to section 12.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection. Table 12.43 show the TICCR setting and input capture input pins. Table 12.43 TICCR Setting and Input Capture Input Pins Target Input Capture TICCR Setting Input Capture Input Pins Input capture from TCNT_1 to TGRA_1 I2AE bit = 0 (initial value) TIOC1A I2AE bit = 1 TIOC1A, TIOC2A Input capture from TCNT_1 to TGRB_1 I2BE bit = 0 (initial value) TIOC1B I2BE bit = 1 TIOC1B, TIOC2B Input capture from TCNT_2 to TGRA_2 I1AE bit = 0 (initial value) TIOC2A I1AE bit = 1 TIOC2A, TIOC1A Input capture from TCNT_2 to TGRB_2 I1BE bit = 0 (initial value) TIOC2B I1BE bit = 1 TIOC2B, TIOC1B (1) Example of Cascaded Operation Setting Procedure Figure 12.20 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'111 to select TCNT_2 overflow/ underflow counting. Cascaded operation Set cascading [1] Start count [2] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 12.20 Cascaded Operation Setting Procedure (2) Cascaded Operation Example (a) Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 495 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCLKC TCLKD TCNT_2 TCNT_1 FFFD FFFE FFFF 0000 0000 0001 0002 0001 0001 0000 FFFF 0000 Figure 12.21 Cascaded Operation Example (a) (3) Cascaded Operation Example (b) Figure 12.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected the TIOC1A rising edge for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, the rising edge of both TIOC1A and TIOC2A is used for the TGRA_1 input capture condition. For the TGRA_2 input capture condition, the TIOC2A rising edge is used. TCNT_2 value H'FFFF H'C256 H'6128 H'0000 TCNT_1 Time H'0512 H'0513 H'0514 TIOC1A TIOC2A TGRA_1 TGRA_2 H'0512 H'0513 H'C256 As I1AE in TICCR is 0, data is not captured in TGRA_2 at the TIOC1A input timing. Figure 12.22 Cascaded Operation Example (b) Page 496 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (4) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Cascaded Operation Example (c) Figure 12.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'FFFF H'C256 H'9192 H'6128 H'2064 H'0000 TCNT_1 Time H'0512 H'0513 H'0514 TIOC1A TIOC2A When the high level is on either of the input pins, an edge on the other pin does not act as an input-capture condition. TGRA_1 H'0512 TGRA_2 H'6128 H'0513 H'2064 H'0514 H'C256 H'9192 Figure 12.23 Cascaded Operation Example (c) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 497 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (5) Cascaded Operation Example (d) Figure 12.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1. TCNT_0 value Compare match between TCNT_0 and TGRA_0 TGRA_0 Time H'0000 TCNT_2 value H'FFFF H'D000 H'0000 TCNT_1 Time H'0512 H'0513 TIOC1A TIOC2A TGRA_1 TGRA_2 H'0513 H'D000 Figure 12.24 Cascaded Operation Example (d) Page 498 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.4.5 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below.  PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible.  PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 12.44. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 499 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Table 12.44 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 0 TGRA_0 TIOC0A TGRB_0 TGRC_0 TGRA_1 TIOC0C TGRA_2 TIOC1A TGRA_3 TIOC2A TIOC3A TGRA_4 TIOC3C TGRD_4 Cannot be set Cannot be set TIOC4A TGRB_4 TGRC_4 Cannot be set Cannot be set TGRD_3 4 TIOC2A TIOC2B TGRB_3 TGRC_3 TIOC1A TIOC1B TGRB_2 3 TIOC0C TIOC0D TGRB_1 2 TIOC0A TIOC0B TGRD_0 1 PWM Mode 2 Cannot be set Cannot be set TIOC4C Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Page 500 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (1) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Example of PWM Mode Setting Procedure Figure 12.25 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] Set TGR [4] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] Start count [6] Figure 12.25 Example of PWM Mode Setting Procedure (2) Examples of PWM Mode Operation Figure 12.26 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty levels. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 501 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT value SH726A Group, SH726B Group Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 12.26 Example of PWM Mode Operation (1) Figure 12.27 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. TCNT value Counter cleared by TGRB_1 compare match TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 12.27 Example of PWM Mode Operation (2) Page 502 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Figure 12.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB rewritten TGRB H'0000 Time 100% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB TGRB rewritten Time H'0000 100% duty TIOCA 0% duty Figure 12.28 Example of PWM Mode Operation (3) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 503 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4.6 SH726A Group, SH726B Group Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 12.45 shows the correspondence between external clock pins and channels. Table 12.45 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD (1) Example of Phase Counting Mode Setting Procedure Figure 12.29 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. Phase counting mode Select phase counting mode [1] Start count [2] [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 12.29 Example of Phase Counting Mode Setting Procedure Page 504 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 12.30 shows an example of phase counting mode 1 operation, and table 12.46 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.30 Example of Phase Counting Mode 1 Operation Table 12.46 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 505 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (b) Phase counting mode 2 Figure 12.31 shows an example of phase counting mode 2 operation, and table 12.47 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.31 Example of Phase Counting Mode 2 Operation Table 12.47 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care High level Don't care Low level Down-count [Legend] : Rising edge : Falling edge Page 506 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (c) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Phase counting mode 3 Figure 12.32 shows an example of phase counting mode 3 operation, and table 12.48 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.32 Example of Phase Counting Mode 3 Operation Table 12.48 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 507 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (d) Phase counting mode 4 Figure 12.33 shows an example of phase counting mode 4 operation, and table 12.49 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 12.33 Example of Phase Counting Mode 4 Operation Table 12.49 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) TCLKB (Channel 1) TCLKD (Channel 2) High level Operation Up-count Low level Low level Don't care High level High level Down-count Low level High level Don't care Low level [Legend] : Rising edge : Falling edge Page 508 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Phase Counting Mode Application Example Figure 12.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 509 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 TGRA_0 (speed control period) + - TGRC_0 (position control period) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 12.34 Phase Counting Mode Application Example Page 510 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.4.7 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 12.50 shows the PWM output pins used. Table 12.51 shows the settings of the registers. Table 12.50 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description 3 TIOC3B PWM output pin 1 TIOC3D PWM output pin 1' (negative-phase waveform of PWM output 1) TIOC4A PWM output pin 2 TIOC4C PWM output pin 2' (negative-phase waveform of PWM output 2) TIOC4B PWM output pin 3 TIOC4D PWM output pin 3' (negative-phase waveform of PWM output 3) 4 Table 12.51 Register Settings for Reset-Synchronized PWM Mode Register Description of Setting TCNT_3 Initial setting of H'0000 TCNT_4 Initial setting of H'0000 TGRA_3 Set count cycle for TCNT_3 TGRB_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins TGRA_4 Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins TGRB_4 Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 511 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (1) SH726A Group, SH726B Group Procedure for Selecting the Reset-Synchronized PWM Mode Figure 12.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. Reset-synchronized PWM mode Stop counting [1] [2] Set bits TPSC2-TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2-CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. Select counter clock and counter clear source [2] Brushless DC motor control setting [3] Set TCNT [4] Set TGR [5] PWM cycle output enabling, PWM output level setting [6] Set reset-synchronized PWM mode [7] Enable waveform output [8] PFC setting [9] [7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. Start count operation [10] [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. Reset-synchronized PWM mode [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X ≤ TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 12.3. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Figure 12.35 Procedure for Selecting Reset-Synchronized PWM Mode Page 512 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Reset-Synchronized PWM Mode Operation Figure 12.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 comparematch occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT_3 and TCNT_4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 12.36 Reset-Synchronized PWM Mode Operation Example (When TOCR’s OLSN = 1 and OLSP = 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 513 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4.8 SH726A Group, SH726B Group Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without nonoverlapping interval are also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 12.52 shows the PWM output pins used. Table 12.53 shows the settings of the registers used. Table 12.52 Output Pins for Complementary PWM Mode Channel Output Pin Description 3 TIOC3A Toggle output synchronized with PWM period (or I/O port) TIOC3B PWM output pin 1 TIOC3C I/O port* TIOC3D PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) TIOC4A PWM output pin 2 TIOC4B PWM output pin 3 TIOC4C PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) TIOC4D PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) 4 Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. Page 514 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Table 12.53 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU 3 TCNT_3 Start of up-count from value set in dead time register Maskable by TRWER setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting* TGRB_3 PWM output 1 compare register Maskable by TRWER setting* TGRC_3 TGRA_3 buffer register Always readable/writable TGRD_3 PWM output 1/TGRB_3 buffer register Always readable/writable TCNT_4 Up-count start, initialized to H'0000 Maskable by TRWER setting* TGRA_4 PWM output 2 compare register Maskable by TRWER setting* TGRB_4 PWM output 3 compare register Maskable by TRWER setting* TGRC_4 PWM output 2/TGRA_4 buffer register Always readable/writable TGRD_4 PWM output 3/TGRB_4 buffer register Always readable/writable Timer dead time data register (TDDR) Set TCNT_4 and TCNT_3 offset value (dead time value) Maskable by TRWER setting* Timer cycle data register (TCDR) Set TCNT_4 upper limit value (1/2 carrier cycle) Maskable by TRWER setting* Timer cycle buffer register (TCBR) TCDR buffer register Always readable/writable Subcounter (TCNTS) Subcounter for dead time generation Read-only Temporary register 1 (TEMP1) PWM output 1/TGRB_3 temporary register Not readable/writable Temporary register 2 (TEMP2) PWM output 2/TGRA_4 temporary register Not readable/writable Temporary register 3 (TEMP3) PWM output 3/TGRB_4 temporary register Not readable/writable 4 Note: * Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register). R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 515 of 1910 SH726A Group, SH726B Group TDDR TGRC_3 TCBR TGRA_3 TCDR Comparator TCNT_3 Match signal TCNTS TCNT_4 PWM output 2 PWM output 3 PWM output 4 PWM output 6 TGRB_4 Temp 3 Match signal TGRA_4 TGRB_3 Temp 1 Temp 2 TGRC_4 PWM output 1 PWM output 5 Comparator TGRD_3 PWM cycle output Output controller TCNT_4 underflow interrupt TGRA_3 comparematch interrupt Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TGRD_4 : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 12.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode Page 516 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (1) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Example of Complementary PWM Mode Setting Procedure An example of the complementary PWM mode setting procedure is shown in figure 12.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. Complementary PWM mode Stop count operation [1] Counter clock, counter clear source selection [2] Brushless DC motor control setting [3] TCNT setting [4] [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2-CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. Inter-channel synchronization setting [5] TGR setting [6] Enable/disable dead time generation [7] Dead time, carrier cycle setting [8] PWM cycle output enabling, PWM output level setting [9] Complementary PWM mode setting [10] Enable waveform output [11] setting StartPFC count operation [12] [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the timer cycle data register (TCDR) and timer cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 12.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. Start count operation [13] [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Figure 12.38 Example of Complementary PWM Mode Setting Procedure R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 517 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (2) SH726A Group, SH726B Group Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 12.39 illustrates counter operation in complementary PWM mode, and figure 12.40 shows an example of complementary PWM mode operation. (a) Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. Page 518 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT_3 TCNT_4 TCNTS Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TCNTS TDDR H'0000 Time Figure 12.39 Complementary PWM Mode Counter Operation (b) Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 12.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.40 shows an example in which the mode is selected in which the change is made in the trough. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 519 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group In the tb interval (tb1 in figure 12.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS— and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly. Page 520 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Transfer from temporary register to compare register Tb2 Transfer from temporary register to compare register Ta Tb1 Ta Tb2 Ta TGRA_3 TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 H'6400 H'0080 Temporary register TEMP2 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 12.40 Example of Complementary PWM Mode Operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 521 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (c) SH726A Group, SH726B Group Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 12.54 Registers and Counters Requiring Initialization Register/Counter Set Value TGRC_3 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER) TCBR 1/2 PWM carrier cycle TGRD_3, TGRC_4, TGRD_4 Initial PWM duty value for each phase TCNT_4 H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1. Page 522 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (d) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. (e) Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. (f) Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 12.41 shows an example of operation without dead time. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 523 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Transfer from temporary register to compare register Transfer from temporary register to compare register Ta Tb1 Ta Tb2 Ta TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Temporary register TEMP2 Data1 Data2 Compare register TGRA_4 Data1 Data2 Output waveform Output waveform Output waveform is active-low. Figure 12.41 Example of Operation without Dead Time Page 524 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (g) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value TCDR set value > two times TDDR + 2 Without dead time: TGRA_3 set value = TCDR set value + 1 TCDR set value > 4 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 12.42 illustrates the operation when the PWM cycle is updated at the crest. See (h) Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 12.42 Example of PWM Cycle Updating R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 525 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (h) SH726A Group, SH726B Group Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Page 526 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 data1 Temp_R GR data1 BR H'0000 TGRC_4 TGRA_4 TGRA_3 Counter value data1 Transfer from temporary register to compare register data2 data2 data2 Transfer from temporary register to compare register Data update timing: counter crest and trough data3 data3 Transfer from temporary register to compare register data3 data4 data4 Transfer from temporary register to compare register data4 data5 data5 Transfer from temporary register to compare register data6 data6 data6 Transfer from temporary register to compare register : Compare register : Buffer register Time SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Figure 12.43 Example of Data Update in Complementary PWM Mode Page 527 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (i) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 12.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 12.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TGRA_4 TDDR Time Dead time Initial output Positive phase output Negative phase output Active level Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 12.44 Example of Initial Output in Complementary PWM Mode (1) Page 528 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGRA_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 12.45 Example of Initial Output in Complementary PWM Mode (2) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 529 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (j) SH726A Group, SH726B Group Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a nonoverlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and compare register. While TCNTS is counting, compare register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 12.46 to 12.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a  b  c  d (or c  d  a'  b'), as shown in figure 12.46. If compare-matches deviate from the a  b  c  d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c  d  a'  b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 12.47, comparematch b is ignored, and the negative phase is turned on by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 12.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. Page 530 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 T2 period T1 period T1 period TGRA_3 c d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 12.46 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGRA_3 c d TCDR a b a b TDDR H'0000 Positive phase Negative phase Figure 12.47 Example of Complementary PWM Mode Waveform Output (2) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 531 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR a b TDDR c a' d b' H'0000 Positive phase Negative phase Figure 12.48 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period c TGRA_3 T1 period d TCDR a b a' b' TDDR H'0000 Positive phase Negative phase Figure 12.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) Page 532 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 T1 period T2 period T1 period TGRA_3 TCDR a b a b TDDR H'0000 c d Positive phase Negative phase Figure 12.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period c TGRA_3 T1 period d TCDR a b TDDR H'0000 Positive phase Negative phase Figure 12.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 533 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 T1 period SH726A Group, SH726B Group T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 c b' Positive phase d a' Negative phase Figure 12.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 T2 period c ad T1 period b TCDR TDDR H'0000 Positive phase Negative phase Figure 12.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Page 534 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (k) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 12.49 to 12.53 show output examples. 100% duty output is performed when the compare register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the compare register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. (l) Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 12.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 12.54 Example of Toggle Output Waveform Synchronized with PWM Output R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 535 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (m) Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 12.55 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TCNTS TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 12.55 Counter Clearing Synchronized with Another Channel Page 536 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (n) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 12.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 12.56) immediately after the counters start operation, initial value output is not suppressed. When using the initial output suppression function, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. If synchronous clearing occurs with the compare registers set to a value less than twice the setting of TDDR, the PWM output dead time may be too short (or nonexistent) or illegal active-level PWM negative-phase output may occur during the initial output suppression interval. For details, see section 12.7.23, Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 537 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Counter start Tb interval Tb interval SH726A Group, SH726B Group Tb interval TGRA_3 TCNT_3 TCDR TGRB_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Figure 12.56 Timing for Synchronous Counter Clearing Page 538 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 12.57. Output waveform control at synchronous counter clearing Stop count operation Set TWCR and complementary PWM mode [1] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [2] [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Start count operation [3] Output waveform control at synchronous counter clearing Figure 12.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 539 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group  Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 12.58 to 12.61 show examples of output waveform control in which this module operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 12.58 to 12.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 12.56, respectively. Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 12.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 12.56; Bit WRE of TWCR is 1) Page 540 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 12.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 12.56; Bit WRE of TWCR is 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 541 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 12.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 12.56; Bit WRE of TWCR is 1) Page 542 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Bit WRE = 1 Synchronous clearing TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 12.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 12.56; Bit WRE of TWCR is 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 543 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (o) SH726A Group, SH726B Group Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match. Figure 12.62 illustrates an operation example. Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest) 2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to SYNC4 bits in the timer synchronous register (TSYR) to 1). 3. Do not set the PWM duty value to H'0000. 4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1. Counter cleared by TGRA_3 compare match TGRA_3 TCDR TGRB_3 TDDR H'0000 Output waveform Output waveform Output waveform is active-high. Figure 12.62 Example of Counter Clearing Operation by TGRA_3 Compare Match Page 544 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (p) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 12.63 to 12.66 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with the general I/O ports). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 12.63 Example of Output Phase Switching by External Input (1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 545 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 External input SH726A Group, SH726B Group TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 12.64 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 12.65 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) Page 546 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group TGCR Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 12.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) (q) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 547 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (3) SH726A Group, SH726B Group Interrupt Skipping in Complementary PWM Mode Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER). For the linkage with buffer registers, refer to description (c), Buffer Transfer Control Linked with Interrupt Skipping, below. A/D converter start requests generated by the A/D converter start request delaying function can also be skipped in coordination with interrupt skipping by making settings in the timer A/D converter request control register (TADCR). For the linkage with the A/D converter start request delaying function, refer to section 12.4.9, A/D Converter Start Request Delaying Function. The setting of the timer interrupt skipping setting register (TITCR) must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. (a) Example of Interrupt Skipping Operation Setting Procedure Figure 12.67 shows an example of the interrupt skipping operation setting procedure. Figure 12.68 shows the periods during which interrupt skipping count can be changed. [1] Set bits T3AEN and T4VEN in the timer interrupt skipping set register (TITCR) to 0 to clear the skipping counter. Interrupt skipping Clear interrupt skipping counter [1] Set skipping count and enable interrupt skipping [2] [2] Specify the interrupt skipping count within the range from 0 to 7 times in bits 3ACOR2 to 3ACOR0 and 4VCOR2 to 4VCOR0 in TITCR, and enable interrupt skipping through bits T3AEN and T4VEN. Note: The setting of TITCR must be done while the TGIA_3 and TCIV_4 interrupt requests are disabled by the settings of TIER_3 and TIER_4 along with under the conditions in which TGFA_3 and TCFV_4 flag settings by compare match never occur. Before changing the skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter. Figure 12.67 Example of Interrupt Skipping Operation Setting Procedure Page 548 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT_3 TCNT_4 Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Period during which changing skipping count can be performed Figure 12.68 Periods during which Interrupt Skipping Count can be Changed (b) Example of Interrupt Skipping Operation Figure 12.69 shows an example of TGIA_3 interrupt skipping in which the interrupt skipping count is set to three by the 3ACOR bit and the T3AEN bit is set to 1 in the timer interrupt skipping set register (TITCR). Interrupt skipping period Interrupt skipping period TGIA_3 interrupt flag set signal Skipping counter 00 01 02 03 00 01 02 03 TGFA_3 flag Figure 12.69 Example of Interrupt Skipping Operation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 549 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (c) SH726A Group, SH726B Group Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER). Figure 12.70 shows an example of operation when buffer transfer is suppressed (BTE1 = 0 and BTE0 = 1). While this setting is valid, data is not transferred from the buffer register to the temporary register. Figure 12.71 shows an example of operation when buffer transfer is linked with interrupt skipping (BTE1 = 1 and BET0 = 0). While this setting is valid, data is not transferred from the buffer register to the temporary register outside the buffer transfer-enabled period. Depending on the rewrite timing from the interrupt generation to the buffer register, there are two types of the transfer timing such as from the buffer register to the temporary register and from the temporary register to the general register. Note that the buffer transfer-enabled period depends on the T3AEN and T4VEN bit settings in the timer interrupt skipping set register (TITCR). Figure 12.72 shows the relationship between the T3AEN and T4VEN bit settings in TITCR and buffer transfer-enabled period. Note: This function must always be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never performed. Page 550 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT_3 TCNT_4 data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Buffer register Data1 Data2 (1) Temporary register (3) Data* Data2 (2) General register Data* Data2 Buffer transfer is suppressed [Legend] (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. Note: * When buffer transfer at the crest is selected. Figure 12.70 Example of Operation when Buffer Transfer is Suppressed (BTE1 = 0 and BTE0 = 1) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 551 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (1)When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt TGIA_3 interrupt generation TGIA_3 interrupt generation TCNT_3 TCNT_4 Buffer register rewrite timing Buffer register rewrite timing Buffer transferenabled period TITCR[6:4] 2 TITCNT[6:4] 0 1 2 0 1 Buffer register Data Data1 Data2 Temporary register Data Data1 Data2 General register Data Data1 Data2 (2)When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt TGIA_3 interrupt generation TGIA_3 interrupt generation TCNT_3 TCNT_4 Buffer register rewrite timing Buffer transferenabled period TITCR[6:4] TITCNT[6:4] 2 0 1 2 0 1 Buffer register Data Data1 Temporary register Data Data1 General register Data Data1 Note: * The MD bits 3 to 0 = 1101 in TMDR_3, buffer transfer at the crest is selected. The skipping count is set to two. T3AEN and T4VEN are set to 1 and 0. Figure 12.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) Page 552 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Skipping counter 3ACNT 0 Skipping counter 4VCNT 1 0 2 1 3 2 0 3 1 0 2 1 3 2 0 3 Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) Note: * The MD bits 3 to 0 = 1111 in TMDR_3, buffer transfer at the crest and the trough is selected. The skipping count is set to three. T3AEN and T4VEN are set to 1. Figure 12.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period (4) Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection function. (a) Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following:  TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 553 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4.9 SH726A Group, SH726B Group A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by setting the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR.  Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 12.73 shows an example of procedure for specifying the A/D converter start request delaying function. [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) A/D converter start request delaying function Set A/D converter start request cycle [1] • Set the timing of transfer from cycle set buffer register • Set linkage with interrupt skipping • Enable A/D converter start request delaying function A/D converter start request delaying function [2] [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register. • Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE. • Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. Figure 12.73 Example of Procedure for Specifying A/D Converter Start Request Delaying Function Page 554 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2  Basic Operation Example of A/D Converter Start Request Delaying Function Figure 12.74 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting. Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register Transfer from cycle buffer register to cycle register TADCORA_4 TCNT_4 TADCOBRA_4 A/D converter start request (TRG4AN) (Complementary PWM mode) Figure 12.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation  Buffer Transfer The data in the timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits in the timer A/D converter start request control register (TADCR_4).  A/D Converter Start Request Delaying Function Linked with Interrupt Skipping A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR). Figure 12.75 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up counting and down counting and A/D converter start requests are linked with interrupt skipping. Figure 12.76 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during TCNT_4 up counting and A/D converter start requests are linked with interrupt skipping. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 555 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter 00 01 00 02 01 00 02 01 00 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * (UT4AE/DT4AE = 1) When the interrupt skipping count is set to two. Figure 12.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping Page 556 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter 00 TCIV_4 interrupt skipping counter 01 00 02 01 00 02 01 00 01 TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping Note: * UT4AE = 1 DT4AE = 0 When the interrupt skipping count is set to two. Figure 12.76 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 557 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 12.77 shows an example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). TGRA_4 Tdead Upper arm signal Lower arm signal Inverter output monitor signal Tdelay Dead time delay signal Up-count/down-count signal (udflg) TCNT[15:0] TGR[15:0] 3DE7 3E5B 3DE7 3ED3 3E5B 3ED3 3F37 3FAF 3F37 3FAF Figure 12.77 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation Page 558 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.5 Interrupt Sources 12.5.1 Interrupt Sources and Priorities This module has three kinds of interrupt sources; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 7, Interrupt Controller. Table 12.55 lists the interrupt sources of this module. Table 12.55 Interrupts of Multi-Function Timer Pulse Unit 2 Channel Name Interrupt Source Activation of Direct Memory Interrupt Access Flag Controller Priority 0 TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible TGIB_0 TGRB_0 input capture/compare match TGFB_0 Not possible TGIC_0 TGRC_0 input capture/compare match TGFC_0 Not possible TGID_0 TGRD_0 input capture/compare match TGFD_0 Not possible TCIV_0 TCNT_0 overflow TCFV_0 Not possible TGIE_0 TGRE_0 compare match TGFE_0 Not possible TGIF_0 TGRF_0 compare match TGFF_0 Not possible TGIA_1 TGRA_1 input capture/compare match TGFA_1 Possible TGIB_1 TGRB_1 input capture/compare match TGFB_1 Not possible TCIV_1 TCNT_1 overflow TCFV_1 Not possible TCIU_1 TCNT_1 underflow TCFU_1 Not possible 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 High Low Page 559 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Channel Name Interrupt Source Activation of Direct Memory Interrupt Access Flag Controller Priority 2 TGIA_2 TGRA_2 input capture/compare match TGFA_2 Possible TGIB_2 TGRB_2 input capture/compare match TGFB_2 Not possible TCIV_2 TCNT_2 overflow TCFV_2 Not possible TCIU_2 TCNT_2 underflow TCFU_2 Not possible TGIA_3 TGRA_3 input capture/compare match TGFA_3 Possible TGIB_3 TGRB_3 input capture/compare match TGFB_3 Not possible TGIC_3 TGRC_3 input capture/compare match TGFC_3 Not possible TGID_3 TGRD_3 input capture/compare match TGFD_3 Not possible TCIV_3 TCNT_3 overflow TCFV_3 Not possible TGIA_4 TGRA_4 input capture/compare match TGFA_4 Possible TGIB_4 TGRB_4 input capture/compare match TGFB_4 Not possible TGIC_4 TGRC_4 input capture/compare match TGFC_4 Not possible TGID_4 TGRD_4 input capture/compare match TGFD_4 Not possible TCIV_4 TCFV_4 Not possible 3 4 TCNT_4 overflow/underflow High Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. (1) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. This module has eighteen input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, and two each for channels 1 and 2. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. (2) Overflow Interrupt An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. This module has five overflow interrupts, one for each channel. Page 560 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. This module has two underflow interrupts, one each for channels 1 and 2. 12.5.2 Activation of Direct Memory Access Controller The direct memory access controller can be activated by the TGRA input capture/compare match interrupt in each channel. For details, see section 11, Direct Memory Access Controller. In this module, a total of five TGRA input capture/compare match interrupts can be used as direct memory access controller activation sources, one each for channels 0 to 4. 12.5.3 A/D Converter Activation The A/D converter can be activated by one of the following three methods in this module. Table 12.56 shows the relationship between interrupt sources and A/D converter start request signals. (1) A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions.  When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1  When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from this module is selected as the trigger in the A/D converter, A/D conversion will start. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 561 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (2) SH726A Group, SH726B Group A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0 The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from this module is selected as the trigger in the A/D converter, A/D conversion will start. (3) A/D Converter Activation by A/D Converter Start Request Delaying Function The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 12.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from this module is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from this module is selected as the trigger in the A/D converter when TRG4BN is generated. Table 12.56 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal TGRA_0 and TCNT_0 Input capture/compare match TRGAN TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4 TCNT_4 Trough in complementary PWM mode TGRE_0 and TCNT_0 Compare match TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 TRG4BN Page 562 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.6 Operation Timing 12.6.1 Input/Output Timing (1) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT Count Timing Figure 12.78 shows TCNT count timing in internal clock operation, and Figure 12.79 shows TCNT count timing in external clock operation (normal mode), and Figure 12.80 shows TCNT count timing in external clock operation (phase counting mode). Pφ Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 Figure 12.78 Count Timing in Internal Clock Operation Pφ External clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 Figure 12.79 Count Timing in External Clock Operation Pφ External clock Rising edge Falling edge TCNT input clock TCNT N-1 N N-1 Figure 12.80 Count Timing in External Clock Operation (Phase Counting Mode) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 563 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (2) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 12.81 shows output compare output timing (normal mode and PWM mode) and Figure 12.82 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). Pφ TCNT input clock TCNT TGR N N+1 N Compare match signal TIOC pin Figure 12.81 Output Compare Output Timing (Normal Mode/PWM Mode) Page 564 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Pφ TCNT input clock TCNT N TGR N N+1 Compare match signal TIOC pin Figure 12.82 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) (3) Input Capture Signal Timing Figure 12.83 shows input capture signal timing. Pφ Input capture input Input capture signal N TCNT N+1 N+2 N TGR N+2 Figure 12.83 Input Capture Input Signal Timing R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 565 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (4) Timing for Counter Clearing by Compare Match/Input Capture Figure 12.84 shows the timing when counter clearing on compare match is specified, and Figure 12.85 shows the timing when counter clearing on input capture is specified. Pφ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 12.84 Counter Clear Timing (Compare Match) Pφ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 12.85 Counter Clear Timing (Input Capture) Page 566 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (5) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Buffer Operation Timing Figures 12.86 to 12.88 show the timing in buffer operation. Pφ TCNT n n+1 TGRA, TGRB n N TGRC, TGRD N Compare match buffer signal Figure 12.86 Buffer Operation Timing (Compare Match) Pφ Input capture signal TCNT N N+1 TGRA, TGRB n N N+1 n N TGRC, TGRD Figure 12.87 Buffer Operation Timing (Input Capture) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 567 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group Pφ n H'0000 TGRA, TGRB, TGRE n N TGRC, TGRD, TGRF N TCNT TCNT clear signal Buffer transfer signal Figure 12.88 Buffer Transfer Timing (when TCNT Cleared) (6) Buffer Transfer Timing (Complementary PWM Mode) Figures 12.89 to 12.91 show the buffer transfer timing in complementary PWM mode. Pφ H'0000 TCNTS TGRD_4 write signal Temporary register transfer signal Buffer register n Temporary register n N N Figure 12.89 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) Page 568 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Pφ TCNTS P-x P H'0000 TGRD_4 write signal Buffer register n N Temporary register n N Figure 12.90 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) Pφ TCNTS P−1 P H'0000 Buffer transfer signal Temporary register N Compare register n N Figure 12.91 Transfer Timing from Temporary Register to Compare Register R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 569 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.6.2 (1) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 12.92 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. Pφ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 12.92 TGI Interrupt Timing (Compare Match) Page 570 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TGF Flag Setting Timing in Case of Input Capture Figure 12.93 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. Pφ Input capture signal N TCNT TGR N TGF flag TGI interrupt Figure 12.93 TGI Interrupt Timing (Input Capture) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 571 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (3) SH726A Group, SH726B Group TCFV Flag/TCFU Flag Setting Timing Figure 12.94 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 12.95 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. Pφ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 12.94 TCIV Interrupt Setting Timing Pφ TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 12.95 TCIU Interrupt Setting Timing Page 572 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (4) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the direct memory access controller is activated, the flag is cleared automatically. Figure 12.96 shows the timing for status flag clearing by the CPU, and Figure 12.97 shows the timing for status flag clearing by the direct memory access controller. TSR write cycle T1 T2 Pφ TSR address Address Write signal Status flag Interrupt request signal Figure 12.96 Timing for Status Flag Clearing by CPU Direct memory access controller read cycle Direct memory access controller write cycle Pφ, Bφ Address Source address Destination address Status flag Interrupt request signal Flag clear signal Figure 12.97 Timing for Status Flag Clearing by Direct Memory Access Controller Activation R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 573 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7 Usage Notes 12.7.1 Module Standby Mode Setting SH726A Group, SH726B Group Operation of this module can be disabled or enabled using the standby control register. The initial setting is for the operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 32, Power-Down Modes. 12.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. This module will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 12.98 shows the input clock conditions in phase counting mode. Overlap Phase Phase differdifference Overlap ence Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 12.98 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Page 574 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.7.3 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: P f= (N + 1) Where 12.7.4 f: P: N: Counter frequency Peripheral clock operating frequency TGR set value Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 12.99 shows the timing in this case. TCNT write cycle T2 T1 Pφ Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 12.99 Contention between TCNT Write and Clear Operations R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 575 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 12.100 shows the timing in this case. TCNT write cycle T2 T1 Pφ Address TCNT address Write signal TCNT input clock TCNT N M TCNT write data Figure 12.100 Contention between TCNT Write and Increment Operations Page 576 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.7.6 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 12.101 shows the timing in this case. TGR write cycle T2 T1 Pφ TGR address Address Write signal Compare match signal TCNT N N+1 TGR N M TGR write data Figure 12.101 Contention between TGR Write and Compare Match R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 577 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data after write. Figure 12.102 shows the timing in this case. TGR write cycle T1 T2 Pφ Buffer register address Address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register TGR N M N Figure 12.102 Contention between Buffer Register Write and Compare Match Page 578 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.7.8 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 12.103 shows the timing in this case. TGR write cycle T1 T2 Pφ Buffer register address Address Write signal TCNT clear signal Buffer transfer signal Buffer register TGR Buffer register write data N M N Figure 12.103 Contention between Buffer Register Write and TCNT Clear R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 579 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.9 SH726A Group, SH726B Group Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer. Figure 12.104 shows the timing in this case. TGR read cycle T2 T1 Pφ Address TGR address Read signal Input capture signal TGR Internal data bus N M N Figure 12.104 Contention between TGR Read and Input Capture Page 580 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 12.105 shows the timing in this case. TGR write cycle T2 T1 Pφ Address TGR address Write signal Input capture signal TCNT TGR M M Figure 12.105 Contention between TGR Write and Input Capture R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 581 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 12.106 shows the timing in this case. Buffer register write cycle T2 T1 Pφ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 12.106 Contention between Buffer Register Write and Input Capture 12.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 12.107. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Page 582 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 TCNT write cycle T1 T2 Pφ Address TCNT_2 address Write signal TCNT_2 H'FFFE H'FFFF N N+1 TCNT_2 write data TGRA_2 to TGRB_2 H'FFFF Ch2 comparematch signal A/B Disabled TCNT_1 input clock TCNT_1 M TGRA_1 M Ch1 comparematch signal A TGRB_1 N M Ch1 input capture signal B TCNT_0 P TGRA_0 to TGRD_0 Q P Ch0 input capture signal A to D Figure 12.107 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 583 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 12.108. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 12.108 Counter Value during Complementary PWM Mode Stop 12.7.14 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register. Page 584 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 12.109 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT3 Point a TGRC_3 Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, TGRD_4 Point b TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 12.109 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 585 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group 12.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 12.110 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 12.110 Reset Synchronous PWM Mode Overflow Flag Page 586 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 12.111 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. MPφ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF TCFV Disabled Figure 12.111 Contention between Overflow and Counter Clearing R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 587 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 12.112 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 MPφ TCNT address Address Write signal TCNT write data TCNT TCFV flag H'FFFF M Disabled Figure 12.112 Contention between TCNT Write and Overflow 12.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronized PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to resetsynchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode. Page 588 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00. 12.7.21 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the direct memory access controller activation source. Interrupts should therefore be disabled before entering module standby mode. 12.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 589 of 1910 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode In complementary PWM mode, when output waveform control during synchronous counter clearing is enabled (WRE in the TWCR register set to 1), the following problems may occur when condition (1) or condition (2), below, is satisfied.  Dead time for the PWM output pins may be too short (or nonexistent).  Active-level output from the PWM negative-phase pins may occur outside the correct activelevel output interval Condition (1): When synchronous clearing occurs in the PWM output dead time interval within initial output suppression interval (10) (figure 12.113). Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or (11) and TGRB_3  TDDR, TGRA_4  TDDR, or TGRB_4  TDDR is true (figure 12.114) Synchronous clearing TGRA_3 (10) (11) (10) TCNT3 (11) Tb interval Tb interval TCNT4 TGR TDDR 0 PWM output (positive phase) PWM output (negative phase) TDDR Shortened dead time Initial output suppression Dead time Note: PWM output is low-active. Figure 12.113 Condition (1) Synchronous Clearing Example Page 590 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Synchronous clearing (10) TGRA_3 (11) (10) (11) TCNT3 Tb interval Tb interval TCNT4 TDDR TGR 0 PWM output (positive phase) PWM output (negative phase) Active-level output occurs at synchronous clearing even though no active-level output interval has been set. Nonexistent dead time Initial output suppression Dead time Note: PWM output is low-active. Figure 12.114 Condition (2) Synchronous Clearing Example The following workaround can be used to avoid these problems. When using synchronous clearing, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 591 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group 12.8 Output Pin Initialization for Multi-Function Timer Pulse Unit 2 12.8.1 Operating Modes This module has the following six operating modes. Waveform output is possible in all of these modes.  Normal mode (channels 0 to 4)  PWM mode 1 (channels 0 to 4)  PWM mode 2 (channels 0 to 2)  Phase counting modes 1 to 4 (channels 1 and 2)  Complementary PWM mode (channels 3 and 4)  Reset-synchronized PWM mode (channels 3 and 4) The output pin initialization method for each of these modes is described in this section. 12.8.2 Reset Start Operation The output pins of this module (TIOC*) are initialized low by a power-on reset and in deep standby mode. Since the pin functions are selected using the general I/O ports, when the general I/O port is set, the pin states at that point are output to the ports. When this module output is selected by the general I/O port immediately after a reset, the initial output level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the general I/O port setting should be made after the initialization of the output pins is completed. Note: Channel number and port notation are substituted for *. Page 592 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 12.8.3 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Operation in Case of Re-Setting Due to Error during Operation, etc. If an error occurs during operation of this module, the module output should be cut by the system. Cutoff is performed by switching the pin output to port output with the general I/O port and outputting the inverse of the active level. The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. This module has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 12.57. Table 12.57 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (2) (3) (4) (5) (6) PWM1 (7) (8) (9) (10) (11) (12) PWM2 (13) (14) (15) (16) None None PCM (17) (18) (19) (20) None None CPWM (21) (22) None None (23) (24) (25) RPWM (26) (27) None None (28) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 593 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 12.8.4 SH726A Group, SH726B Group Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc.  When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.  In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1.  In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2.  In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again.  In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again.  When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article. Pin initialization procedures are described below for the numbered combinations in table 12.57. The active level is assumed to be low. Page 594 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (1) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode Figure 12.115 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.115 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. After a reset, the module output is low and ports are in the high-impedance state. 2. After a reset, the TMDR setting is for normal mode. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 5. Set the multi-function timer pulse unit 2 output with the general I/O port. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the general I/O port and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 595 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (2) SH726A Group, SH726B Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.116 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.116 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.115. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, and then switch to PWM mode 1.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Page 596 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (3) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 12.117 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.117 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 12.115. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, and then switch to PWM mode 2.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 597 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (4) SH726A Group, SH726B Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 12.118 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 13 14 12 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.118 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12.115. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Page 598 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (5) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.119 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting. 12 11 10 9 7 8 6 4 5 3 (18) 13 1 2 14 15 (16) (17) RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) occurs (PORT) (0) (1 init (MTU2) (1) (normal) (1) (CPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.119 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.115. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set the multi-function timer pulse unit 2 output with the general I/O port. 18. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 599 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (6) SH726A Group, SH726B Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.120 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. 6 4 5 3 1 2 PFC TSTR RESET TMDR TOER TIOR (1 init (MTU2) (1) (normal) (1) 0 out) 7 Match 10 9 8 PFC TSTR Error occurs (PORT) (0) 12 11 18 13 14 15 16 17 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (RPWM) (1) (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.120 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 12.115. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set the multi-function timer pulse unit 2 output with the general I/O port. 18. Operation is restarted by TSTR. Page 600 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (7) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode Figure 12.121 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.121 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. After a reset, the module output is low and ports are in the high-impedance state. 2. Set PWM mode 1. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) 5. Set the multi-function timer pulse unit 2 output with the general I/O port. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the general I/O port and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 601 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (8) SH726A Group, SH726B Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1 Figure 12.122 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Not initialized (TIOC*B) Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.122 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.121. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Page 602 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (9) Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2 Figure 12.123 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.123 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 12.121. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 603 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode Figure 12.124 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 6 4 5 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 13 14 12 TIOR PFC TSTR (1 init (MTU2) (1) 0 out) MTU2 module output TIOC*A Not initialized (TIOC*B) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.124 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 12.121. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Page 604 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.125 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting. 1 2 14 15 16 17 18 3 19 5 4 6 7 8 9 10 11 12 13 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (PWM1) (1) (1 init (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0 init (disabled) (0) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.125 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.121. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set the multi-function timer pulse unit 2 output with the general I/O port. 19. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 605 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.126 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. 13 6 7 8 9 10 11 12 1 2 3 4 5 14 15 16 17 18 19 RESET TMDR TOER TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (PWM1) (1) (1 init (MTU2) (1) (RPWM) (1) (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.126 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 12.125. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set the multi-function timer pulse unit 2 output with the general I/O port. 19. Operation is restarted by TSTR. Page 606 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode Figure 12.127 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (normal) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.127 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. After a reset, the module output is low and ports are in the high-impedance state. 2. Set PWM mode 2. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) 4. Set the multi-function timer pulse unit 2 output with the general I/O port. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the general I/O port and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 607 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1 Figure 12.128 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Not initialized (TIOC*B) Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.128 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 12.127. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. Page 608 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2 Figure 12.129 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A Not initialized (cycle register) TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.129 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 12.127. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 609 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode Figure 12.130 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. 12 13 4 5 6 7 8 9 10 11 1 2 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR RESET TMDR TIOR occurs (PORT) (0) (PCM) (1 init (MTU2) (1) (PWM2) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.130 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12.127. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. Page 610 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode Figure 12.131 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (normal) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.131 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. After a reset, the module output is low and ports are in the high-impedance state. 2. Set phase counting mode. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 4. Set the multi-function timer pulse unit 2 output with the general I/O port. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the general I/O port and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 611 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.132 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Not initialized (TIOC*B) Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.132 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 12.131. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. Page 612 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2 Figure 12.133 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PWM2) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output Not initialized (cycle register) TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.133 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 12.131. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 613 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode Figure 12.134 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 RESET TMDR (PCM) 12 13 4 5 6 7 8 9 10 11 3 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR TIOR occurs (PORT) (0) (PCM) (1 init (MTU2) (1) (1 init (MTU2) (1) 0 out) 0 out) MTU2 module output TIOC*A TIOC*B Port output PEn High-Z PEn High-Z n = 0 to 15 Figure 12.134 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 12.131. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set the multi-function timer pulse unit 2 output with the general I/O port. 13. Operation is restarted by TSTR. Page 614 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 12.135 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.135 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. After a reset, the module output is low and ports are in the high-impedance state. 2. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 3. Set complementary PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set the multi-function timer pulse unit 2 output with the general I/O port. 6. The count operation is started by TSTR. 7. The complementary PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the general I/O port and output the inverse of the active level. 10. The count operation is stopped by TSTR. (This module outputs the same value as the complementary PWM output initial value.) 11. Set normal mode. (This module outputs a low-level signal.) 12. Initialize the pins with TIOR. 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 615 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.136 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.136 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.135. 11. Set PWM mode 1. (This module outputs a low-level signal.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Page 616 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.137 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.137 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.135. 11. Set the multi-function timer pulse unit 2 output with the general I/O port. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 617 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.138 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). 1 2 3 14 15 16 5 17 4 6 7 8 9 10 11 12 13 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU2) (1) (CPWM) (1) (MTU2) (1) occurs (PORT) (0) (normal) (0) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.138 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.135. 11. Set normal mode and make new settings. (This module outputs a low-level signal.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set the multi-function timer pulse unit 2 output with the general I/O port. 17. Operation is restarted by TSTR. Page 618 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.139 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode. 13 12 11 10 9 7 8 6 4 5 17 1 2 3 14 15 16 RESET TOCR TMDR TOER PFC TSTR Match Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU2) (1) (RPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.139 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 12.135. 11. Set normal mode. (This module outputs a low-level signal.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set the multi-function timer pulse unit 2 output with the general I/O port. 17. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 619 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (26) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode Figure 12.140 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.140 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. After a reset, the module output is low and ports are in the high-impedance state. 2. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 3. Set reset-synchronized PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set the multi-function timer pulse unit 2 output with the general I/O port. 6. The count operation is started by TSTR. 7. The reset-synchronized PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the general I/O port and output the inverse of the active level. 10. The count operation is stopped by TSTR. (This module outputs the same value as the resetsynchronized PWM output initial value.) 11. Set normal mode. (The positive phase output from this module is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. Page 620 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (27) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1 Figure 12.141 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 13 14 8 9 10 11 12 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU2) (1) 0 out) MTU2 module output TIOC3A TIOC3B Not initialized (TIOC3B) TIOC3D Not initialized (TIOC3D) Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.141 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 12.140. 11. Set PWM mode 1. (The positive phase output from this module is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set the multi-function timer pulse unit 2 output with the general I/O port. 14. Operation is restarted by TSTR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 621 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 SH726A Group, SH726B Group (28) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode Figure 12.142 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in complementary PWM mode after resetting. 1 2 3 5 4 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 14 15 16 8 9 10 11 12 13 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.142 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 12.140. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The cyclic output pin of this module outputs a low-level signal.) 14. Enable channel 3 and 4 output with TOER. 15. Set the multi-function timer pulse unit 2 output with the general I/O port. 16. Operation is restarted by TSTR. Page 622 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 (29) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode Figure 12.143 shows an explanatory diagram of the case where an error occurs in resetsynchronized PWM mode and operation is restarted in reset-synchronized PWM mode after resetting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU2) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU2) (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE8 High-Z PE9 High-Z PE11 High-Z Figure 12.143 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 12.140. 11. Set the multi-function timer pulse unit 2 output with the general I/O port. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 623 of 1910 Section 12 Multi-Function Timer Pulse Unit 2Multi-Function Timer Pulse Unit 2 Page 624 of 1910 SH726A Group, SH726B Group R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 13 Compare Match Timer Section 13 Compare Match Timer This LSI has an on-chip compare match timer module consisting of two-channel 16-bit timers. This module has a 16-bit counter, and can generate interrupts at set intervals. 13.1 Features  Independent selection of four counter input clocks at two channels Any of four internal clocks (P/8, P/32, P/128, and P/512) can be selected.  Selection of DMA transfer request or interrupt request generation on compare match by direct memory access controller setting  When not in use, this module can be stopped by halting its clock supply to reduce power consumption. Figure 13.1 shows a block diagram. Pφ/8 Channel 0 Module bus Pφ/32 Pφ/128 Pφ/512 Clock selection CMCNT_1 Control circuit Comparator CMCNT_0 Comparator CMCOR_0 CMCSR_0 CMI1 Pφ/128 Pφ/512 Clock selection Control circuit CMSTR Pφ/32 CMCOR_1 Pφ/8 CMCSR_1 CMI0 Channel 1 Bus interface Compare match timer Peripheral bus [Legend] CMSTR: CMCSR: CMCOR: CMCNT: CMI: Compare match timer start register Compare match timer control/status register Compare match constant register Compare match counter Compare match interrupt Figure 13.1 Block Diagram R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 625 of 1910 SH726A Group, SH726B Group Section 13 Compare Match Timer 13.2 Register Descriptions Table 13.1 shows the register configuration. Table 13.1 Register Configuration Abbreviation R/W Initial Value Address Access Size Common Compare match timer start register CMSTR R/W H'0000 H'FFFEC000 16 0 Compare match timer control/ status register_0 CMCSR_0 R/W H'0000 H'FFFEC002 16 Compare match counter_0 CMCNT_0 R/W H'0000 H'FFFEC004 8, 16 Compare match constant register_0 CMCOR_0 R/W H'FFFF H'FFFEC006 8, 16 Compare match timer control/ status register_1 CMCSR_1 R/W H'0000 H'FFFEC008 16 Compare match counter_1 CMCNT_1 R/W H'0000 H'FFFEC00A 8, 16 Compare match constant register_1 CMCOR_1 R/W H'FFFF H'FFFEC00C 8, 16 Channel 1 Register Name Page 626 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 13.2.1 Section 13 Compare Match Timer Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - STR1 STR0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 15 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 STR1 0 R/W Count Start 1 Specifies whether compare match counter_1 operates or is stopped. 0: Counting by CMCNT_1 is stopped 1: Counting by CMCNT_1 is started 0 STR0 0 R/W Count Start 0 Specifies whether compare match counter_0 operates or is stopped. 0: Counting by CMCNT_0 is stopped 1: Counting by CMCNT_0 is started R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 627 of 1910 SH726A Group, SH726B Group Section 13 Compare Match Timer 13.2.2 Compare Match Timer Control/Status Register (CMCSR) CMCSR is a 16-bit register that indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - CMF CMIE - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 R/(W)* R/W 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 1 0 CKS[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match. 0: CMCNT and CMCOR values do not match [Clearing condition]  When 0 is written to CMF after reading CMF = 1 1: CMCNT and CMCOR values match 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables compare match interrupt (CMI) generation when CMCNT and CMCOR values match (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 628 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 13 Compare Match Timer Bit Bit Name Initial Value R/W Description 1, 0 CKS[1:0] 00 R/W Clock Select These bits select the clock to be input to CMCNT from four internal clocks obtained by dividing the peripheral clock (P). When the STR bit in CMSTR is set to 1, CMCNT starts counting on the clock selected with bits CKS[1:0]. 00: P/8 01: P/32 10: P/128 11: P/512 Note: * Only 0 can be written to clear the flag after 1 is read. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 629 of 1910 SH726A Group, SH726B Group Section 13 Compare Match Timer 13.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS[1:0] in CMCSR, and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock. When the value in CMCNT and the value in compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. CMCNT is initialized to H'0000 by clearing any channels of the counter start bit from 1 to 0 in the compare match timer start register (CMSTR). Bit: Initial value: R/W: 13.2.4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Compare Match Constant Register (CMCOR) CMCOR is a 16-bit register that sets the interval up to a compare match with CMCNT. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Page 630 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 13 Compare Match Timer 13.3 Operation 13.3.1 Interval Count Operation When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT then starts counting up again from H'0000. Figure 13.2 shows the operation of the compare match counter. CMCNT value Counter cleared by compare match with CMCOR CMCOR H'0000 Time Figure 13.2 Counter Operation 13.3.2 CMCNT Count Timing One of four clocks (P/8, P/32, P/128, and P/512) obtained by dividing the peripheral clock (P) can be selected with the CKS1 and CKS0 bits in CMCSR. Figure 13.3 shows the timing. Peripheral clock (Pφ) Internal clock Count clock Clock N CMCNT Clock N+1 N N+1 Figure 13.3 Count Timing R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 631 of 1910 Section 13 Compare Match Timer 13.4 Interrupts 13.4.1 Interrupt Sources and DMA Transfer Requests SH726A Group, SH726B Group This module has channels and each of them to which a different vector address is allocated has a compare match interrupt. When both the compare match flag (CMF) and the interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 7, Interrupt Controller. Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out, another interrupt will be generated. By setting the interrupt controller, the direct memory access controller can be activated when a compare match interrupt is requested. In this case, an interrupt is not issued to the CPU. If the setting to activate the direct memory access controller has not been made, an interrupt request is sent to the CPU. The CMF bit is automatically cleared to 0 when data is transferred by the direct memory access controller. 13.4.2 Timing of Compare Match Flag Setting When CMCOR and CMCNT match, a compare match signal is generated at the last state in which the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match signal is not generated until the next CMCNT counter clock input. Figure 13.4 shows the timing of CMF bit setting. Page 632 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 13 Compare Match Timer Peripheral clock (Pφ) Clock N+1 Counter clock CMCNT N CMCOR N 0 Compare match signal Figure 13.4 Timing of CMF Setting 13.4.3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first, reading as 1 then writing to 0. However, in the case of the direct memory access controller being activated, the CMF bit is automatically cleared to 0 when data is transferred by the direct memory access controller. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 633 of 1910 SH726A Group, SH726B Group Section 13 Compare Match Timer 13.5 Usage Notes 13.5.1 Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 13.5 shows the timing to clear the CMCNT counter. CMCSR write cycle T1 T2 Peripheral clock (Pφ) Address signal CMCNT Internal write signal Counter clear signal CMCNT N H'0000 Figure 13.5 Conflict between Write and Compare Match Processes of CMCNT Page 634 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 13.5.2 Section 13 Compare Match Timer Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 13.6 shows the timing to write to CMCNT in words. CMCSR write cycle T1 T2 Peripheral clock (Pφ) Address signal CMCNT Internal write signal CMCNT count-up enable signal CMCNT N M Figure 13.6 Conflict between Word-Write and Count-Up Processes of CMCNT R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 635 of 1910 SH726A Group, SH726B Group Section 13 Compare Match Timer 13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has priority over the count-up. In this case, the count-up is not performed. The byte data on the other side, which is not written to, is also not counted and the previous contents are retained. Figure 13.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNTH in bytes. CMCSR write cycle T1 T2 Peripheral clock (Pφ) Address signal CMCNTH Internal write signal CMCNT count-up enable signal CMCNTH N M CMCNTL X X Figure 13.7 Conflict between Byte-Write and Count-Up Processes of CMCNT 13.5.4 Compare Match between CMCNT and CMCOR Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. Page 636 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 14 Watchdog Timer Section 14 Watchdog Timer This LSI includes the watchdog timer, which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. This module can simultaneously generate an internal reset signal for the entire LSI. This module is a single channel timer that counts up the clock oscillation settling period when the system leaves software standby mode. It can also be used as a general watchdog timer or interval timer. 14.1 Features  Can be used to ensure the clock oscillation settling time This module is used in leaving software standby mode.  Can switch between watchdog timer mode and interval timer mode.  Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode, the WDTOVF signal is output externally. It is possible to select whether to reset the LSI internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset type.  Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows.  Choice of eight counter input clocks Eight clocks (P  1 to P  1/16384) that are obtained by dividing the peripheral clock can be selected. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 637 of 1910 SH726A Group, SH726B Group Section 14 Watchdog Timer Figure 14.1 shows a block diagram. Watchdog timer Standby cancellation Standby mode Standby control Peripheral clock Divider Interrupt request Interrupt control Clock selection Clock selector WDTOVF Internal reset request* Reset control Overflow WRCSR WTCSR Clock WTCNT Bus interface [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter WRCSR: Watchdog reset control/status register Note: * The internal reset signal can be generated by making a register setting. Figure 14.1 Block Diagram 14.2 Input/Output Pin Table 14.1 shows the pin configuration. Table 14.1 Pin Configuration Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs the counter overflow signal in watchdog timer mode Page 638 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 14.3 Section 14 Watchdog Timer Register Descriptions Table 14.2 shows the register configuration. Table 14.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Watchdog timer counter WTCNT R/W H'00 H'FFFE0002 16* Watchdog timer control/status register WTCSR R/W H'18 H'FFFE0000 16* Watchdog reset control/status register WRCSR R/W H'1F H'FFFE0004 16* Note: 14.3.1 * For the access size, see section 14.3.4, Notes on Register Access. Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode. Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read from WTCNT. Note: The method for writing to WTCNT differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: Initial value: R/W: R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 7 6 5 4 3 2 1 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Page 639 of 1910 SH726A Group, SH726B Group Section 14 Watchdog Timer 14.3.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. When used to count the clock oscillation settling time for canceling software standby mode, it retains its value after counter overflow. Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from WTCSR. Note: The method for writing to WTCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. Bit: 7 6 5 4 3 IOVF WT/IT TME - - 0 R/W 0 R/W 1 R 1 R Initial value: 0 R/W: R/(W) 2 1 0 CKS[2:0] 0 R/W 0 R/W Bit Bit Name Initial Value R/W Description 7 IOVF 0 R/(W) Interval Timer Overflow 0 R/W Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT overflow in interval timer mode [Clearing condition]  Page 640 of 1910 When 0 is written to IOVF after reading IOVF R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 14 Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Watchdog Timer Selects whether to use this module as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: When the WTCNT overflows in watchdog timer mode, the WDTOVF signal is output externally. If this bit is modified when this module is running, the up-count may not be performed correctly. 5 TME 0 R/W Timer Enable Starts and stops timer operation. Clear this bit to 0 when using this module in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 641 of 1910 SH726A Group, SH726B Group Section 14 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 to 0 CKS[2:0] 000 R/W Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (P). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (P) is 36 MHz. Bits 2 to 0 Clock Ratio Overflow Cycle 000: 1  P 7.1 s 001: 1/64  P 455 s 010: 1/128  P 910 s 011: 1/256  P 1.8 ms 100: 1/512  P 3.6 ms 101: 1/1024  P 7.2 ms 110: 1/4096  P 29 ms 111: 1/16384  P 116 ms Note: If bits CKS[2:0] are modified when this module is running, the up-count may not be performed correctly. Ensure that these bits are modified only when this module is not running. Page 642 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 14.3.3 Section 14 Watchdog Timer Watchdog Reset Control/Status Register (WRCSR) WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 14.3.4, Notes on Register Access, for details. 7 6 5 4 3 2 1 WOVF RSTE RSTS - - - - - Initial value: 0 R/W: R/(W) 0 R/W 0 R/W 1 R 1 R 1 R 1 R 1 R Bit: Bit Bit Name Initial Value R/W Description 7 WOVF 0 R/(W) Watchdog Timer Overflow 0 Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode [Clearing condition]  6 RSTE 0 R/W When 0 is written to WOVF after reading WOVF Reset Enable Selects whether to generate a signal to reset the LSI internally if WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Not reset when WTCNT overflows* 1: Reset when WTCNT overflows Note: * 5 RSTS 0 R/W LSI not reset internally, but WTCNT and WTCSR reset within this module. Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 to 0  All 1 R Reserved These bits are always read as 1. The write value should always be 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 643 of 1910 SH726A Group, SH726B Group Section 14 Watchdog Timer 14.3.4 Notes on Register Access The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write 15 WTCSR write 8 15 Address: H'FFFE0000 0 7 H'5A Address: H'FFFE0002 Write data 8 7 H'A5 0 Write data Figure 14.2 Writing to WTCNT and WTCSR Page 644 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 14 Watchdog Timer Writing to WRCSR WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte transfer or longword transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 14.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Writing to the RSTE and RSTS bits Address: H'FFFE0004 8 7 H'A5 Address: H'FFFE0004 15 0 H'00 8 7 H'5A 0 Write data Figure 14.3 Writing to WRCSR (3) Reading from WTCNT, WTCSR, and WRCSR WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address H'FFFE0004. Byte transfer instructions must be used for reading from these registers. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 645 of 1910 Section 14 Watchdog Timer 14.4 Usage 14.4.1 Canceling Software Standby Mode SH726A Group, SH726B Group This module can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (This module does not operate when resets are used for canceling, so keep the RES or MRES pin low until clock oscillation settles.) 1. Before making a transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. After setting the STBY and DEEP bits of the standby control register 1 (STBCR1: see section 32, Power-Down Modes) to 1 and 0 respectively, the execution of a SLEEP instruction puts the system in software standby mode and clock operation then stops. 4. This module starts counting by detecting the edge change of the NMI signal. 5. When the module count overflows, the clock pulse generator starts supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 14.4.2 Using Watchdog Timer Mode 1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, this module sets the WOVF flag in WRCSR to 1, and the WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 64  P clock cycles. 5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for 128  P clock cycles. 6. When an overflow reset of this module is generated simultaneously with a reset input on the RES pin, the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0. Page 646 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 14 Watchdog Timer WTCNT value Overflow H'FF H'00 Time H'00 written in WTCNT WT/IT = 1 TME = 1 WOVF = 1 WT/IT = 1 TME = 1 WDTOVF and internal reset generated H'00 written in WTCNT WDTOVF signal 64 × Pφ clock cycles Internal reset signal* 128 × Pφ clock cycles [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 14.4 Operation in Watchdog Timer Mode R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 647 of 1910 SH726A Group, SH726B Group Section 14 Watchdog Timer 14.4.3 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, this module sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the interrupt controller. The counter then resumes counting. WTCNT value Overflow Overflow Overflow Overflow H'FF H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI [Legend] ITI: Interval timer interrupt request generation Figure 14.5 Operation in Interval Timer Mode Page 648 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 14.5 Section 14 Watchdog Timer Usage Notes Pay attention to the following points when using this module in either the interval timer or watchdog timer mode. 14.5.1 Timer Variation After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the peripheral clock, P, while the longest is the result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time difference is referred to as timer variation. This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation. 14.5.2 Prohibition against Setting H'FF to WTCNT When the value in WTCNT reaches H'FF, this module assumes that an overflow has occurred. Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or reset will occur immediately, regardless of the current clock selection by the CKS[2:0] bits. 14.5.3 Interval Timer Overflow Flag When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared. Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a value other than H'FF. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 649 of 1910 SH726A Group, SH726B Group Section 14 Watchdog Timer 14.5.4 System Reset by WDTOVF Signal If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly. Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 14.6. Reset input (Low active) Reset signal to entire system (Low active) RES WDTOVF Figure 14.6 Example of System Reset Circuit Using WDTOVF Signal 14.5.5 Manual Reset in Watchdog Timer Mode When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset occurs during burst transfer by the direct memory access controller, manual reset exception handling may be pended until the CPU acquires the bus mastership. 14.5.6 Internal Reset in Watchdog Timer Mode When an internal reset is generated due to an overflow of the watchdog timer counter (WTCNT) in watchdog timer mode, the watchdog reset control/status register (WRCSR) is not initialized, so the WOVF bit retains the value 1. As long as the WOVF bit is 1, an internal reset will not be generated even if the WTCNT overflows again. Page 650 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock Section 15 Realtime Clock This LSI has a realtime clock and a 4-MHz crystal oscillator. 15.1 Features  Clock and calendar functions (BCD format): Seconds, minutes, hours, date, day of the week, month, and year.  1-Hz to 64-Hz timer (binary format) 64-Hz counter indicates the state of the divider circuit between 64 Hz and 1 Hz  Start/stop function  30-second adjust function  Alarm interrupt: Frame comparison of seconds, minutes, hours, date, day of the week, month, and year can be used as conditions for the alarm interrupt  Periodic interrupts: the interrupt cycle may be 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds  Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read  Automatic leap year adjustment  Any of the external clock signal dedicated for the clock function or the internal signal can be selected as the operating clock signal for the clock function.  Recovery from deep standby mode can be performed by an alarm interrupt. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 651 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock Figure 15.1 shows the block diagram. RTC_X1 4 MHz Crystal oscillator 128 Hz Prescaler R64CNT RSECCNT RSECAR RMINCNT RMINAR RHRCNT RHRAR RDAYCNT RDAYAR RWKCNT RWKAR RMONCNT RMONAR RYRCNT RYRAR EXTAL XTAL RCR5 Bus interface Crystal oscillator RFRH RFRL Operation control circuit RCR1 RCR2 Peripheral bus RTC_X2 Interrupt control circuit RCR3 ARM PRD Interrupt signals CUP [Legend] RSECCNT: RMINCNT: RHRCNT: RWKCNT: RDAYCNT: RMONCNT: RYRCNT: R64CNT: RFRH/L: Second counter Minute counter Hour counter Day of week counter Date counter Month counter Year counter 64-Hz counter Frequency register RSECAR: RMINAR: RHRAR: RWKAR: RDAYAR: RMONAR: RYRAR: RCR1: RCR2: RCR3: RCR5: Second alarm register Minute alarm register Hour alarm register Day of week alarm register Date alarm register Month alarm register Year alarm register Control register 1 Control register 2 Control register 3 Control register 5 Figure 15.1 Block Diagram Page 652 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.2 Section 15 Realtime Clock Input/Output Pin Table 15.1 shows the pin configuration. Table 15.1 Pin Configuration Pin Name Symbol I/O Description Realtime clock resonator crystal pin/ external clock RTC_X1 Input RTC_X2 Output Connects 4-MHz crystal resonator for this module, and enables to input the external clock to the RTC_X1 pin. Internal clock resonator crystal/ external clock EXTAL Input XTAL Output R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Connects crystal resonator used for internal operation. For details, see section 5, Clock Pulse Generator. Page 653 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3 Register Descriptions Table 15.2 shows the register configuration. Table 15.2 Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size 64-Hz counter R64CNT R H'xx H'FFFE6000 8 Second counter RSECCNT R/W H'xx H'FFFE6002 8 Minute counter RMINCNT R/W H'xx H'FFFE6004 8 Hour counter RHRCNT R/W H'xx H'FFFE6006 8 Day of week counter RWKCNT R/W H'xx H'FFFE6008 8 Date counter RDAYCNT R/W H'xx H'FFFE600A 8 Month counter RMONCNT R/W H'xx H'FFFE600C 8 Year counter RYRCNT R/W H'xxxx H'FFFE600E 16 Second alarm register RSECAR R/W H'xx H'FFFE6010 8 Minute alarm register RMINAR R/W H'xx H'FFFE6012 8 Hour alarm register RHRAR R/W H'xx H'FFFE6014 8 Day of week alarm register RWKAR R/W H'xx H'FFFE6016 8 Date alarm register RDAYAR R/W H'xx H'FFFE6018 8 Month alarm register RMONAR R/W H'xx H'FFFE601A 8 Year alarm register RYRAR R/W H'xxxx H'FFFE6020 16 Control register 1 RCR1 R/W H'xx H'FFFE601C 8 Control register 2 RCR2 R/W H'01 H'FFFE601E 8 Control register 3 RCR3 R/W H'x0 H'FFFE6024 8 Control register 5 RCR5 R/W H'0x H'FFFE6026 8 Frequency register H RFRH R/W H'xxxx H'FFFE602A 16 Frequency register L RFRL R/W H'xxxx H'FFFE602C 16 Page 654 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.3.1 Section 15 Realtime Clock 64-Hz Counter (R64CNT) R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz. Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed at the same time is indicated. In this case, the R64CNT should be read again after writing 0 to the CF bit in RCR1 since the read value is not valid. After the RESET bit or ADJ bit in the control register 2 (RCR2) is set to 1, the divider circuit is initialized and R64CNT is initialized. BIt: 7 6 5 4 3 - 1Hz 2Hz 4Hz 8Hz Initial value: 0 R/W: R 2 1 0 16Hz 32Hz 64Hz Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R Bit Bit Name Initial Value R/W Description 7  0 R Reserved R R R R This bit is always read as 0. The write value should always be 0. 6 1 Hz Undefined R 5 2 Hz Undefined R 4 4 Hz Undefined R 3 8 Hz Undefined R 2 16 Hz Undefined R 1 32 Hz Undefined R 0 64 Hz Undefined R R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Indicate the state of the divider circuit between 64 Hz and 1 Hz. Page 655 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.2 Second Counter (RSECCNT) RSECCNT is used for setting/counting in the BCD-coded second section. The count operation is performed by a carry for each second of the 64-Hz counter. The assignable range is from 00 through 59 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 - 5 4 3 10 seconds Initial value: 0 R/W: R 2 1 0 1 second Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7  0 R Reserved R/W R/W R/W This bit is always read as 0. The write value should always be 0. 6 to 4 10 seconds Undefined R/W Counting Ten's Position of Seconds Counts on 0 to 5 for 60-seconds counting. 3 to 0 1 second Undefined R/W Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. Page 656 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.3.3 Section 15 Realtime Clock Minute Counter (RMINCNT) RMINCNT is used for setting/counting in the BCD-coded minute section. The count operation is performed by a carry for each minute of the second counter. The assignable range is from 00 through 59 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 - 5 4 3 10 minutes Initial value: 0 R/W: R 2 1 0 1 minute Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7  0 R Reserved R/W R/W R/W This bit is always read as 0. The write value should always be 0. 6 to 4 10 minutes Undefined R/W Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minutes counting. 3 to 0 1 minute Undefined R/W Counting One's Position of Minutes Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 657 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.4 Hour Counter (RHRCNT) RHRCNT is used for setting/counting in the BCD-coded hour section. The count operation is performed by a carry for each 1 hour of the minute counter. The assignable range is from 00 through 23 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 5 - - 10 hours Initial value: 0 0 R/W: R R 4 3 2 1 0 1 hour Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved R/W R/W R/W These bits are always read as 0. The write value should always be 0. 5, 4 10 hours Undefined R/W Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. 3 to 0 1 hour Undefined R/W Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position. Page 658 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.3.5 Section 15 Realtime Clock Day of Week Counter (RWKCNT) RWKCNT is used for setting/counting day of week section. The count operation is performed by a carry for each day of the date counter. The assignable range is from 0 through 6 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 5 4 3 - - - - - Day Undefined Undefined Undefined Initial value: 0 0 0 0 0 R/W: R R R R R Bit Bit Name Initial Value R/W Description 7 to 3  All 0 R Reserved 2 R/W 1 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 2 to 0 Day Undefined R/W Day-of-Week Counting Day-of-week is indicated with a binary code. 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 659 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.6 Date Counter (RDAYCNT) RDAYCNT is used for setting/counting in the BCD-coded date section. The count operation is performed by a carry for each day of the hour counter. The assignable range is from 01 through 31 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. The range of date changes with each month and in leap years. Confirm the correct setting. Leap years are recognized by dividing the year counter (RYRCNT) values by 400, 100, and 4 and obtaining a fractional result of 0. BIt: 7 6 5 - - 10 days Initial value: 0 0 R/W: R R 4 3 2 1 0 1 day Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W Bit Bit Name Initial Value R/W Description 7, 6  All 0 R Reserved R/W R/W R/W These bits are always read as 0. The write value should always be 0. 5, 4 10 days Undefined R/W Counting Ten's Position of Dates 3 to 0 1 day Undefined R/W Counting One's Position of Dates Counts on 0 to 9 once per date. When a carry is generated, 1 is added to the ten's position. Page 660 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.3.7 Section 15 Realtime Clock Month Counter (RMONCNT) RMONCNT is used for setting/counting in the BCD-coded month section. The count operation is performed by a carry for each month of the date counter. The assignable range is from 01 through 12 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 7 6 5 4 - - - 10 months Undefined Undefined Undefined Undefined Undefined Initial value: 0 0 0 R/W: R R R R/W 3 2 1 0 1 month R/W Bit Bit Name Initial Value R/W Description 7 to 5  All 0 R Reserved R/W R/W R/W These bits are always read as 0. The write value should always be 0. 4 10 months Undefined R/W Counting Ten's Position of Months 3 to 0 1 month Undefined R/W Counting One's Position of Months Counts on 0 to 9 once per month. When a carry is generated, 1 is added to the ten's position. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 661 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.8 Year Counter (RYRCNT) RYRCNT is used for setting/counting in the BCD-coded year section. The count operation is performed by a carry for each year of the month counter. The assignable range is from 0000 through 9999 (practically in BCD), otherwise operation errors occur. Carry out write processing after stopping the count operation through the setting of the START bit in RCR2. BIt: 15 14 13 12 1000 years 11 10 9 8 100 years 7 6 5 4 3 10 years 2 1 0 1 year Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 12 1000 years Undefined R/W Counting Thousand's Position of Years 11 to 8 100 years Undefined R/W Counting Hundred's Position of Years 7 to 4 10 years Undefined R/W Counting Ten's Position of Years 3 to 0 1 year Undefined R/W Counting One's Position of Years Page 662 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.3.9 Section 15 Realtime Clock Second Alarm Register (RSECAR) RSECAR is an alarm register corresponding to the BCD-coded second counter RSECCNT. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 59  ENB bits (practically in BCD), otherwise operation errors occur. BIt: 7 6 ENB Initial value: 5 4 3 10 seconds 2 1 0 1 second Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W 6 to 4 10 seconds Undefined R/W Ten's position of seconds setting value 3 to 0 1 second One's position of seconds setting value R/W Undefined R/W R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Description When this bit is set to 1, a comparison with the RSECCNT value is performed. Page 663 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.10 Minute Alarm Register (RMINAR) RMINAR is an alarm register corresponding to the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 59  ENB bits (practically in BCD), otherwise operation errors occur. BIt: 7 6 ENB Initial value: 5 4 3 10 minutes 2 1 0 1 minute Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RMINCNT value is performed. 6 to 4 10 minutes Undefined R/W Ten's position of minutes setting value 3 to 0 1 minute Undefined R/W One's position of minutes setting value Page 664 of 1910 R/W Description R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.11 Hour Alarm Register (RHRAR) RHRAR is an alarm register corresponding to the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 00 through 23  ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 ENB - 10 hours Undefined R/W: R/W 0 R 4 3 2 1 0 1 hour Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RHRCNT value is performed. 6  0 Reserved R/W R Description This bit is always read as 0. The write value should always be 0. 5, 4 10 hours Undefined R/W Ten's position of hours setting value 3 to 0 1 hour Undefined R/W One's position of hours setting value R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 665 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.12 Day of Week Alarm Register (RWKAR) RWKAR is an alarm register corresponding to the BCD-coded day of week counter RWKCNT. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 0 through 6 + ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 4 3 ENB - - - - Day Undefined Undefined Undefined Undefined R/W: R/W 0 0 0 0 R R R R 2 R/W 1 R/W 0 R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RWKCNT value is performed. 6 to 3  All 0 Reserved R/W R Description These bits are always read as 0. The write value should always be 0. 2 to 0 Day Undefined R/W Day of Week Setting Value 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited) Page 666 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.13 Date Alarm Register (RDAYAR) RDAYAR is an alarm register corresponding to the BCD-coded date counter RDAYCNT. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 01 through 31 + ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 ENB - 10 days Undefined R/W: R/W 0 R 4 3 2 1 0 1 day Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RDAYCNT value is performed. 6  0 Reserved R/W R Description This bit is always read as 0. The write value should always be 0. 5, 4 10 days Undefined R/W Ten's position of dates setting value 3 to 0 1 day Undefined R/W One's position of dates setting value R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 667 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.14 Month Alarm Register (RMONAR) RMONAR is an alarm register corresponding to the BCD-coded month counter RMONCNT. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. The assignable range is from 01 through 12 + ENB bits (practically in BCD), otherwise operation errors occur. BIt: Initial value: 7 6 5 4 ENB - - 10 months 0 0 Undefined Undefined Undefined Undefined Undefined R R Undefined R/W: R/W R/W 3 2 1 0 1 month R/W R/W R/W R/W Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, a comparison with the RMONCNT value is performed. 6, 5  All 0 Reserved R/W R Description These bits are always read as 0. The write value should always be 0. 4 10 months Undefined R/W Ten's position of months setting value 3 to 0 1 month Undefined R/W One's position of months setting value Page 668 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.15 Year Alarm Register (RYRAR) RYRAR is an alarm register corresponding to the year counter RYRCNT. The assignable range is from 0000 through 9999 (practically in BCD), otherwise operation errors occur. BIt: 15 14 13 12 1000 years 11 10 9 8 100 years 7 6 5 4 3 10 years 2 1 0 1 year Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 15 to 12 1000 years Undefined R/W Description Thousand's position of years setting value 11 to 8 100 years Undefined R/W Hundred's position of years setting value 7 to 4 10 years Undefined R/W Ten's position of years setting value 3 to 0 1 year Undefined R/W One's position of years setting value R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 669 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.16 Control Register 1 (RCR1) RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. The CF flag remains undefined until the divider circuit is reset (the RESET and ADJ bits in RCR2 are set to 1). When using the CF flag, make sure to reset the divider circuit beforehand. The AF flag remains undefined until the value is set to an alarm register and a counter. When using the AF flag, make sure to set the alarm register and counter beforehand. BIt: Initial value: 7 6 5 4 3 2 1 0 CF - - CIE AIE - - AF Undefined R/W: R/W Bit Bit Name Initial Value 7 CF Undefined R/W R/W 0 0 0 0 0 0 Undefined R R R/W R/W R R R/W Description Carry Flag Status flag that indicates that a carry has occurred. CF is set to 1 when a count-up to 64-Hz occurs at the second counter carry or 64-Hz counter read. A count register value read at this time cannot be guaranteed; another read is required. 0: No carry of 64-Hz counter by second counter or 64Hz counter [Clearing condition] When 0 is written to CF 1: Carry of 64-Hz counter by second counter or 64 Hz counter [Setting condition] When the second counter or 64-Hz counter is read during a carry occurrence by the 64-Hz counter, or 1 is written to CF. 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Page 670 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock Bit Bit Name Initial Value R/W Description 4 CIE 0 R/W Carry Interrupt Enable Flag When the carry flag (CF) is set to 1, the CIE bit enables interrupts. 0: A carry interrupt is not generated when the CF flag is set to 1 1: A carry interrupt is generated when the CF flag is set to 1 3 AIE 0 R/W Alarm Interrupt Enable Flag When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. 0: An alarm interrupt is not generated when the AF flag is set to 1 1: An alarm interrupt is generated when the AF flag is set to 1 2, 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 AF Undefined R/W Alarm Flag The AF flag is set when the alarm time, which is set by an alarm register (ENB bit in RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR is set to 1), and counter match. 0: Alarm register and counter not match [Clearing condition] When 0 is written to AF. 1: Alarm register and counter match* [Setting condition] When alarm register (only a register with ENB bit set to 1) and counter match Note: R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 * Writing 1 holds previous value. Page 671 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.17 Control Register 2 (RCR2) RCR2 is a register for periodic interrupt control, 30-second adjustment, divider circuit RESET, and count control. RCR2 is initialized by a power-on reset or in deep standby mode. Bits other than the RTCEN and START bits are initialized by a manual reset. The RTCEN bit is initialized only by a power-on reset signal from the RES pin. BIt: 7 6 5 PEF Initial value: 0 R/W: R/W Bit Bit Name Initial Value R/W 7 PEF 0 R/W 4 PES[2:0] 3 2 RTCEN ADJ 1 0 RESET START 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W Description Periodic Interrupt Flag Indicates interrupt generation with the period designated by the PES2 to PES0 bits. When set to 1, PEF generates periodic interrupts. 0: Interrupts not generated with the period designated by the bits PES2 to PES0. [Clearing condition] When 0 is written to PEF 1: Interrupts generated with the period designated by the PES2 to PES0 bits. [Setting condition] When an interrupt is generated with the period designated by the bits PES0 to PES2 or when 1 is written to the PEF flag Page 672 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock Bit Bit Name Initial Value R/W Description 6 to 4 PES[2:0] 000 R/W Interrupt Enable Flags These bits specify the periodic interrupt. 000: No periodic interrupts generated 001: Setting prohibited 010: Periodic interrupt generated every 1/64 second 011: Periodic interrupt generated every 1/16 second 100: Periodic interrupt generated every 1/4 second 101: Periodic interrupt generated every 1/2 second 110: Periodic interrupt generated every 1 second 111: Periodic interrupt generated every 2 seconds 3 RTCEN 0 R/W RTC_X1 Clock Control Controls the function of RTC_X1 pin. 0: Halts the on-chip crystal oscillator/disables the external clock input. 1: Runs the on-chip crystal oscillator/enables the external clock input. 2 ADJ 0 R/W 30-Second Adjustment When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit (prescaler and R64CNT) will be simultaneously reset. This bit always reads 0. 0: Runs normally. 1: 30-second adjustment. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 673 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock Bit Bit Name Initial Value R/W Description 1 RESET 0 R/W Reset Writing 1 to this bit initializes the divider circuit, the R64CNT register, the alarm register, the RCR3 register, bits CF and AF in RCR1, and bit PEF in RCR2. In this case, the RESET bit is automatically reset to 0 after 1 is written to and the above registers are reset. Thus, there is no need to write 1 to this bit. This bit is always read as 0. 0: Runs normally. 1: Divider circuit is reset. 0 START 1 R/W Start Halts and restarts the counter (clock). 0: Second/minute/hour/day/week/month/year counter halts. 1: Second/minute/hour/day/week/month/year counter runs normally. Page 674 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.18 Control Register 3 (RCR3) When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincides, an alarm flag of RCR1 is set to 1. BIt: Initial value: 7 6 5 4 3 2 1 ENB - - - - - - - Undefined 0 0 0 0 0 0 0 R R R R R R R R/W: R/W 0 Bit Bit Name Initial Value 7 ENB Undefined R/W When this bit is set to 1, comparison of the year alarm register (RYRAR) and the year counter (RYRCNT) is performed. 6 to 0  All 0 Reserved R/W R Description These bits are always read as 0. The write value should always be 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 675 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.19 Control Register 5 (RCR5) When the RCKSEL[1:0] bits are set to 00, the 32.768-kHz RTC_X1 clock pulses are counted; when the RCKSEL[1:0] bits are set to 01, the EXTAL clock pulses are counted; and when the RCKSEL[1:0] bits are set to 10, the RTC_X1 clock pulses are counted to implement the clock function. Bit: Initial value: R/W: Bit Bit Name 7 to 2  7 6 5 4 3 2 - - - - - - RCKSEL[1:0] 0 R 0 R 0 R 0 R 0 R 0 R Undefined Undefined Initial Value R/W Description All 0 R Reserved 1 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 1, 0 RCKSEL[1:0] Undefined R/W Operation clock select Operation clock can be selected from RTC_X1 or EXTAL. The setting of these bits should not be switched during operation. 00: Selects 32.768-kHz RTC_X1. 01: Selects EXTAL. 10: Selects RTC_X1. 11: Setting prohibited. Page 676 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 15 Realtime Clock 15.3.20 Frequency Register H/L (RFRH/L) RFRH/L is a 16-bit readable/writable register. The "frequency comparison value" is set in RFC[18:0] so that a 128-Hz clock is generated when the realtime clock operates at the EXTAL or RTC_X1 clock frequency. Change the "frequency comparison value" according to the EXTAL clock frequency. The calculation method is shown below. When the RCKSEL bits in the RCR5 register are 00, it is not necessary to set this register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 SEL64 - - - - - - - - - - - - RFC[18:16] Initial value: Undefined R/W: R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Undefined Undefined Undefined Bit: 14 13 12 11 10 9 8 7 6 5 4 3 15 18 17 16 R/W R/W R/W 2 1 0 RFC[15:0] Initial value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 31 SEL64 Undefined R/W R/W Description 64-Hz Divider Select Indicates the operating clock that the EXTAL or RTC_X1 clock frequency is dividable by 64-Hz and not dividable by 128-Hz. 0: EXTAL or RTC_X1 clock frequency is dividable by 128-Hz. 1: EXTAL or RTC_X1 clock frequency is dividable by 64-Hz and not dividable by 128-Hz. 30 to 19  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 18 to 0 RFC[18:0] Undefined R/W Frequency comparison value Sets the comparison value to generate operation clock from the EXTAL or RTC_X1 clock frequency. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 677 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock (1) Method for calculating "frequency comparison value".  EXTAL or RTC_X1 clock frequency is dividable by 128-Hz RFC[18:0]  (EXTAL or RTC_X1 clock frequency) / 128 Clear the SEL64 bit to 0 in this case.  EXTAL or RTC_X1 clock frequency is dividable by 64-Hz and not dividable by 128-Hz RFC[18:0]  (EXTAL or RTC_X1 clock frequency) / 64 Set the SEL64 bit to 1 in this case. (2) Setting Example Table 15.3 Setting Example Clock Frequency EXTAL RTC_X1 Page 678 of 1910 SEL64 Setting Value RFC Setting Value 10 MHz 0 H'1312D 11 MHz 1 H'29F63 12 MHz 0 H'16E36 4 MHz 0 H'07A12 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.4 Section 15 Realtime Clock Operation Usage of this module is shown below. 15.4.1 Initial Settings of Registers after Power-On and Oscillation Settling Time All the registers should be set after the power is turned on. When the 4-MHz crystal oscillator is used, oscillation settling time is required after the RTCEN bit in the RCR2 register is changed from 0 to 1. Do not set or operate the realtime clock during oscillation settling time. For oscillation settling time, refer to section 35, Electrical Characteristics. 15.4.2 Setting Time Figure 15.2 shows how to set the time when the clock is stopped. Stop clock, select input clock, reset divider circuit Set seconds, minutes, hour, day, day of the week, month, and year Start clock Write 0 to START in the RCR2 register. When EXTAL or RTC_X1 is selected for input clock, set also RCR5 and RFRH/L. Write 1 to RESET in the RCR2 register. Order is irrelevant Write 1 to START in the RCR2 register Figure 15.2 Setting Time R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 679 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.4.3 Reading Time Figure 15.3 shows how to read the time. Disable the carry interrupt Clear the carry flag Write 0 to CIE in RCR1 Write 0 to CF in RCR1 (Set AF in RCR1 to 1 so that alarm flag is not cleared.) Read all the counter registers to be read Yes Carry flag = 1? Read RCR1 and check CF bit No (a) To read the time without using interrupts Clear the carry flag Enable the carry interrupt Clear the carry flag Write 1 to CIE in RCR1 Write 0 to CF in RCR1 (Set AF in RCR1 to 1 so that alarm flag is not cleared.) Read all the counter registers to be read Yes interrupt No Disable the carry interrupt Write 0 to CIE in RCR1 (b) To read the time using interrupts Figure 15.3 Reading Time If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 15.3 shows the method of reading the time without using interrupts; part (b) in figure 15.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used. Page 680 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.4.4 Section 15 Realtime Clock Alarm Function Figure 15.4 shows how to use the alarm function. Clock running Disable alarm interrupt Write 0 to AIE in RCR1 to prevent errorneous interrupt Set alarm time Clear alarm flag Enable alarm interrupt Always reset, since the flag may have been set while the alarm time was being set. Write 1 to AIE in RCR1 Monitor alarm time (wait for interrupt or check alarm flag) Figure 15.4 Using Alarm Function Alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. Set the ENB bit in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is not placed to 0. When the clock and alarm times match, 1 is set in the AF bit in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is set in the AIE bit in RCR1, an interrupt is generated when an alarm occurs. The alarm flag is set when the clock and alarm times match. However, the alarm flag can be cleared by writing 0. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 681 of 1910 SH726A Group, SH726B Group Section 15 Realtime Clock 15.5 Usage Notes 15.5.1 Register Writing during Count The following registers cannot be written to during a count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCONT The count must be stopped before writing to any of the above registers. 15.5.2 Use of Realtime Clock Periodic Interrupts The method of using the periodic interrupt function is shown in figure 15.5. A periodic interrupt can be generated periodically at the interval set by bits PES2 to PES0 in RCR2. When the time set by bits PES2 to PES0 has elapsed, the PEF is set to 1. The PEF is cleared to 0 upon periodic interrupt generation or when bits PES2 to PES0 are set. Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. Set PES, clear PEF Set PES2 to PES0 and clear PEF to 0 in RCR2 Elapse of time set by PES Clear PEF Clear PEF to 0 Figure 15.5 Using Periodic Interrupt Function 15.5.3 Transition to Standby Mode after Setting Register When a transition to standby mode is made after registers in this module are set, sometimes counting is not performed correctly. In case the registers are set, be sure to make a transition to standby mode after performing one dummy read of the register. Page 682 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 15.5.4 Section 15 Realtime Clock Usage Notes when Writing to and Reading the Register  After writing to a counter register such as the second counter and the RCR2 register, perform two dummy reads before reading data. The register contents from before the write are returned by the two dummy reads, and the third read returns the register contents reflecting the write.  Registers other than the above can be read immediately after a write and the written value is reflected. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 683 of 1910 Section 15 Realtime Clock Page 684 of 1910 SH726A Group, SH726B Group R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Section 16 Serial Communication Interface with FIFO This LSI has an five-channel serial communication interface with FIFO that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently for each channel that enable this LSI to perform efficient high-speed continuous communication. 16.1 Features  Asynchronous serial communication:  Serial data communication is performed by start-stop in character units. This module can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats.  Data length: 7 or 8 bits  Stop bit length: 1 or 2 bits  Parity: Even, odd, or none  Receive error detection: Parity, framing, and overrun errors  Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RxD level directly from the serial port register when a framing error occurs.  Clock synchronous serial communication:  Serial data communication is synchronized with a clock signal. This module can communicate with other chips having a clock synchronous communication function. There is one serial data communication format.  Data length: 8 bits  Receive error detection: Overrun errors  Full duplex communication: The transmitting and receiving sections are independent, so this module can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions.  On-chip baud rate generator with selectable bit rates  Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 685 of 1910 Section 16 Serial Communication Interface with FIFO SH726A Group, SH726B Group  Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFOdata-full interrupt, and receive-error interrupts are requested independently.  When this module is not in use, it can be stopped by halting the clock supplied to it, saving power.  In asynchronous mode, on-chip modem control functions (RTS and CTS) (only channels 0 to 2).  The quantity of data in the transmit and receive FIFO data registers and the number of receive errors of the receive data in the receive FIFO data register can be ascertained.  A time-out error (DR) can be detected when receiving in asynchronous mode.  In asynchronous mode, the base clock frequency can be either 16 or 8 times the bit rate.  When an internal clock is selected as a clock source and the SCK pin is used as an input pin in asynchronous mode, either normal mode or double-speed mode can be selected for the baud rate generator. Page 686 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Figure 16.1 shows a block diagram. However, certain channels do not have the CTS and RTS pins. Module data bus SCFTDR (16 stages) SCSMR SCBRR SCLSR SCEMR Bus interface SCFRDR (16 stages) Peripheral bus SCFDR SCFCR RxD SCRSR Baud rate generator SCFSR SCTSR SCSCR Pφ/16 SCSPTR Pφ/64 Transmission/reception control TxD Clock Parity generation Parity check SCK Pφ Pφ/4 External clock TXI RXI ERI BRI CTS RTS Serial communication interface with FIFO [Legend] SCRSR: Receive shift register SCFRDR: Receive FIFO data register SCTSR: Transmit shift register SCFTDR: Transmit FIFO data register SCSMR: Serial mode register SCSCR: Serial control register SCEMR: Serial extension mode register SCFSR: Serial status register SCBRR: Bit rate register SCSPTR: Serial port register SCFCR: FIFO control register SCFDR: FIFO data count set register SCLSR: Line status register Figure 16.1 Block Diagram R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 687 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.2 Input/Output Pins Table 16.1 shows the pin configuration. Table 16.1 Pin Configuration Channel Pin Name Symbol I/O Function 0 to 4 Serial clock pins SCK0 to SCK4 I/O Clock I/O Receive data pins RxD0 to RxD4 Input Receive data input Transmit data pins TxD0 to TxD4 Output Transmit data output Request to send pin RTS0 to RTS2 I/O Request to send Clear to send pin CTS0 to CTS2 I/O Clear to send 0 to 2 Page 688 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.3 Section 16 Serial Communication Interface with FIFO Register Descriptions This module has the following registers. Table 16.2 Register Configuration Channel Register Name Abbreviation R/W Initial Value Address 0 Serial mode register_0 SCSMR_0 R/W H'0000 H'FFFE8000 16 Bit rate register_0 SCBRR_0 R/W H'FF H'FFFE8004 8 Serial control register_0 SCSCR_0 R/W H'0000 H'FFFE8008 16 Transmit FIFO data register_0 SCFTDR_0 W Undefined H'FFFE800C 8 Serial status register_0 SCFSR_0 R/(W)* H'0060 Receive FIFO data register_0 SCFRDR_0 R Undefined H'FFFE8014 8 FIFO control register_0 SCFCR_0 1 1 Access Size H'FFFE8010 16 R/W H'0000 H'FFFE8018 16 FIFO data count register_0 SCFDR_0 R H'0000 H'FFFE801C 16 Serial port register_0 R/W H'0050 H'FFFE8020 16 SCSPTR_0 2 Line status register_0 SCLSR_0 R/(W)* H'0000 H'FFFE8024 16 Serial extension mode register_0 SCEMR_0 R/W H'0000 H'FFFE8028 16 Serial mode register_1 SCSMR_1 R/W H'0000 H'FFFE8800 16 Bit rate register_1 SCBRR_1 R/W H'FF H'FFFE8804 8 Serial control register_1 SCSCR_1 R/W H'0000 H'FFFE8808 16 Transmit FIFO data register_1 SCFTDR_1 W Undefined H'FFFE880C 8 Serial status register_1 SCFSR_1 R/(W)* H'0060 Receive FIFO data register_1 SCFRDR_1 R Undefined H'FFFE8814 8 FIFO control register_1 SCFCR_1 R/W H'0000 H'FFFE8818 16 FIFO data count register_1 SCFDR_1 R H'0000 H'FFFE881C 16 Serial port register_1 R/W H'0050 H'FFFE8820 16 SCSPTR_1 1 2 H'FFFE8810 16 Line status register_1 SCLSR_1 R/(W)* H'0000 H'FFFE8824 16 Serial extension mode register_1 SCEMR_1 R/W H’FFFE8828 16 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 H’0000 Page 689 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Channel Register Name Abbreviation R/W Initial Value Address 2 Serial mode register_2 SCSMR_2 R/W H'0000 H'FFFE9000 16 Bit rate register_2 SCBRR_2 R/W H'FF H'FFFE9004 8 Serial control register_2 SCSCR_2 R/W H'0000 H'FFFE9008 16 Transmit FIFO data register_2 SCFTDR_2 W Undefined H'FFFE900C 8 Serial status register_2 SCFSR_2 R/(W)* H'0060 Receive FIFO data register_2 SCFRDR_2 R Undefined H'FFFE9014 8 FIFO control register_2 SCFCR_2 R/W H'0000 H'FFFE9018 16 R H'0000 H'FFFE901C 16 FIFO data count register_2 SCFDR_2 3 1 Access Size H'FFFE9010 16 Serial port register_2 SCSPTR_2 R/W H'0050 H'FFFE9020 16 Line status register_2 SCLSR_2 R/(W)* H'0000 H'FFFE9024 16 Serial extension mode register_2 SCEMR_2 R/W H'0000 H'FFFE9028 16 Serial mode register_3 SCSMR_3 R/W H'0000 H'FFFE9800 16 Bit rate register_3 SCBRR_3 R/W H'FF H'FFFE9804 8 Serial control register_3 SCSCR_3 R/W H'0000 H'FFFE9808 16 Transmit FIFO data register_3 SCFTDR_3 W Undefined H'FFFE980C 8 Serial status register_3 SCFSR_3 R/(W)* H'0060 Receive FIFO data register_3 SCFRDR_3 R Undefined H'FFFE9814 8 FIFO control register_3 SCFCR_3 R/W H'0000 H'FFFE9818 16 FIFO data count register_3 SCFDR_3 R H'0000 H'FFFE981C 16 Serial port register_3 R/W H'0050 H'FFFE9820 16 SCSPTR_3 2 1 2 H'FFFE9810 16 Line status register_3 SCLSR_3 R/(W)* H'0000 H'FFFE9824 16 Serial extension mode register_3 SCEMR_3 R/W H'FFFE9828 16 Page 690 of 1910 H'0000 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Channel Register Name Abbreviation R/W Initial Value Address 4 Serial mode register_4 SCSMR_4 R/W H'0000 H'FFFEA000 16 Bit rate register_4 SCBRR_4 R/W H'FF H'FFFEA004 8 Serial control register_4 SCSCR_4 R/W H'0000 H'FFFEA008 16 Transmit FIFO data register_4 SCFTDR_4 W Undefined H'FFFEA00C 8 Serial status register_4 SCFSR_4 R/(W)* H'0060 Receive FIFO data register_4 SCFRDR_4 R Undefined H'FFFEA014 8 FIFO control register_4 SCFCR_4 R/W H'0000 H'FFFEA018 16 R H'0000 H'FFFEA01C 16 FIFO data count register_4 SCFDR_4 1 Access Size H'FFFEA010 16 Serial port register_4 SCSPTR_4 R/W H'0050 H'FFFEA020 16 Line status register_4 SCLSR_4 R/(W)* H'0000 H'FFFEA024 16 Serial extension mode register_4 SCEMR_4 R/W H'FFFEA028 16 2 H'0000 Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that cannot be modified. 2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be modified. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 691 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.3.1 Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the receive FIFO data register (SCFRDR). The CPU cannot read or write to SCRSR directly. 16.3.2 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Receive FIFO Data Register (SCFRDR) SCFRDR is a 16-stage FIFO register that stores serial receive data. The reception of one byte of serial data is complete when the received data is moved from the receive shift register (SCRSR) to SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When SCFRDR is full of receive data, subsequent serial data is lost. Page 692 of 1910 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: R R R R R R R R R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.3.3 Section 16 Serial Communication Interface with FIFO Transmit Shift Register (SCTSR) SCTSR transmits serial data. Transmit data is loaded from the transmit FIFO data register (SCFTDR) into SCTSR, then the data is transmitted serially from the TxD pin, LSB (bit 0) first. After one data byte has been transmitted, the next transmit data is automatically loaded from SCFTDR into SCTSR and transmission is started again. The CPU cannot read from or write to SCTSR directly. 16.3.4 Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: - - - - - - - - Transmit FIFO Data Register (SCFTDR) SCFTDR is a 16-stage FIFO register that stores data for serial transmission. When the transmit shift register (SCTSR) empty is detected, transmit data written in the SCFTDR is moved to SCTSR and serial transmission is started. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. The CPU can write to SCFTDR at all times. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: W W W W W W W W R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 693 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.3.5 Serial Mode Register (SCSMR) SCSMR specifies the serial communication format and selects the clock source for the baud rate generator. The CPU can always read from and write to SCSMR. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - C/A CHR PE O/E STOP - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 1 0 CKS[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 C/A 0 R/W Communication Mode Selects operating mode from asynchronous and clock synchronous modes. 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length Selects 7-bit or 8-bit data length in asynchronous mode. In the clock synchronous mode, the data length is always 8 bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: Page 694 of 1910 * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: 4 O/E 0 R/W * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Parity Mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity* 1: Odd parity* 1 2 Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 695 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character. 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select Select the internal clock source of the on-chip baud rate generator. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.8, Bit Rate Register (SCBRR). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock Page 696 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.3.6 Section 16 Serial Communication Interface with FIFO Serial Control Register (SCSCR) SCSCR enables/disables the transmitter/receiver operation and interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 - - - - - - - - TIE RIE TE RE REIE - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 1 0 CKE[1:0] 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 TIE 0 R/W Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), when the quantity of data in the transmit FIFO register becomes less than the specified number of transmission triggers, and when the TDFE flag in the serial status register (SCFSR) is set to1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled* Note: R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 * The TXI interrupt request can be cleared by writing a greater quantity of transmit data than the specified transmission trigger number to SCFTDR and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0. Page 697 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 6 RIE 0 R/W Receive Interrupt Enable Enables or disables the receive FIFO data full (RXI) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERI) interrupts requested when the ER flag in SCFSR is set to1, and break (BRI) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are disabled 1: Receive FIFO data full interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests are enabled* Note: 5 TE 0 R/W * RXI interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERI or BRI interrupt requests can be cleared by reading the ER, BRK or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Transmit Enable Enables or disables the serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: Page 698 of 1910 * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receive Enable Enables or disables the serial receiver. 0: Receiver disabled* 1 2 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock is detected in clock synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1. 3 REIE 0 R/W Receive Error Interrupt Enable Enables or disables the receive-error (ERI) interrupts and break (BRI) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests are disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests are enabled* Note: R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 * ERI or BRI interrupt requests can be cleared by reading the ER, BRK or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERI or BRI interrupt requests are enabled. Page 699 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable Select the clock source and enable or disable clock output from the SCK pin. Depending on CKE[1:0], the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clock synchronous mode, set the C/A bit in SCSMR to 1, and then set CKE[1:0].  Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is either 16 or 8 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is either 16 or 8 times the bit rate.) 11: Setting prohibited  Clock synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited Page 700 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.3.7 Section 16 Serial Communication Interface with FIFO Serial Status Register (SCFSR) SCFSR is a 16-bit register. The upper 8 bits indicate the number of receive errors in the receive FIFO data register, and the lower 8 bits indicate the status flag indicating operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). The PER flag (bits 15 to 12 and bit 2) and the FER flag (bits 11 to 8 and bit 3) are read-only bits that cannot be written. Bit: 15 14 13 12 11 10 PER[3:0] Initial value: R/W: 0 R 0 R 0 R 9 8 FER[3:0] 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR 0 R 0 R 0 1 1 0 R/(W)* R/(W)* R/(W)* R/(W)* 0 0 R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15 to 12 PER[3:0] 0000 R Number of Parity Errors Indicate the quantity of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). The value indicated by bits 15 to 12 after the ER bit in SCFSR is set, represents the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER[3:0] shows 0000. 11 to 8 FER[3:0] 0000 R Number of Framing Errors Indicate the quantity of data including a framing error in the receive data stored in SCFRDR. The value indicated by bits 11 to 8 after the ER bit in SCFSR is set, represents the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER[3:0] shows 0000. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 701 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 7 ER 0 R/(W)* Receive Error Description Indicates the occurrence of a framing error, or of a 1 parity error when receiving data that includes parity.* 0: Receiving is in progress or has ended normally [Clearing conditions]  ER is cleared to 0 a power-on reset  ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred. [Setting conditions]  ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive 2 operation*  ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCFRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked. Page 702 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 6 TEND 1 R/(W)* Transmit End Description Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition]  TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in 1 SCFTDR* 1: End of transmission [Setting conditions]  TEND is set to 1 when the chip is a power-on reset  TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR)  TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Note: 1. Do not use this bit as a transmit end flag when the direct memory access controller writes data to SCFTDR due to a TXI interrupt request. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 703 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 5 TDFE 1 R/(W)* Transmit FIFO Data Empty Description Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the quantity of data in SCFTDR has become less than the transmission trigger number specified by the TTRG[1:0] bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions]  TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written  TDFE is cleared to 0 when direct memory access controller is activated by transmit FIFO data empty interrupt (TXI) and write data exceeding the specified transmission trigger number to SCFTDR 1: The quantity of transmit data in SCFTDR is less than or equal to the specified transmission trigger 1 number* [Setting conditions]  TDFE is set to 1 by a power-on reset  TDFE is set to 1 when the quantity of transmit data in SCFTDR becomes less than or equal to the specified transmission trigger number as a result of transmission Note: Page 704 of 1910 1. Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The quantity of data in SCFTDR is indicated by the upper 8 bits of SCFDR. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 4 BRK 0 R/(W)* Break Detection Description Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions]  BRK is cleared to 0 when the chip is a power-on reset  BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK 1: Break signal received* 1 [Setting condition]  BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data Note: 3 FER 0 R 1. When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. Framing Error Indication Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions]  FER is cleared to 0 when the chip undergoes a power-on reset  FER is cleared to 0 when no framing error is present in the next data read from SCFRDR 1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition]  R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 FER is set to 1 when a framing error is present in the next data read from SCFRDR Page 705 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 2 PER 0 R Parity Error Indication Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions]  PER is cleared to 0 when the chip undergoes a power-on reset  PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1: A receive parity error occurred in the next data read from SCFRDR [Setting condition]  Page 706 of 1910 PER is set to 1 when a parity error is present in the next data read from SCFRDR R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 1 RDF 0 R/(W)* Receive FIFO Data Full Description Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become more than the receive trigger number specified by the RTRG[1:0] bits in the FIFO control register (SCFCR). 0: The quantity of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions]  RDF is cleared to 0 by a power-on reset  RDF is cleared to 0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written  RDF is cleared to 0 when the direct memory access controller is activated by receive FIFO data full interrupt (RXI) and read SCFRDR until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number 1: The quantity of receive data in SCFRDR is more than the specified receive trigger number [Setting condition]  RDF is set to 1 when a quantity of receive data more than the specified receive trigger number is 1 stored in SCFRDR* Note: R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 1. As SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read when RDF is 1 becomes the specified receive trigger number. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The quantity of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR. Page 707 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W 0 DR 0 R/(W)* Receive Data Ready Description Indicates that the quantity of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clock synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions]  DR is cleared to 0 when the chip undergoes a power-on reset  DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written.  DR is cleared to 0 when all receive data are read after the direct memory access controller is activated by receive FIFO data full interrupt (RXI). 1: Next receive data has not been received [Setting condition]  DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the 1 elapse of 15 ETU from the last stop bit.* Note: Note: * 1. This is equivalent to 1.5 frames with the 8bit, 1-stop-bit format. (ETU: elementary time unit) Only 0 can be written to clear the flag after 1 is read. Page 708 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.3.8 Section 16 Serial Communication Interface with FIFO Bit Rate Register (SCBRR) SCBRR is an 8-bit register that is used with the CKS1 and CKS0 bits in the serial mode register (SCSMR) and the BGDM and ABCS bits in the serial extension mode register (SCEMR) to determine the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. Each channel has independent baud rate generator control, so different values can be set in five channels. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W The SCBRR setting is calculated as follows:  Asynchronous mode: When baud rate generator operates in normal mode (when the BGDM bit of SCEMR is 0): N= Pφ × 106 − 1 (Operation on a base clock with a frequency of 16 times 64 × 22n-1 × B the bit rate) N= Pφ × 106 − 1 (Operation on a base clock with a frequency of 8 times 32 × 22n-1 × B the bit rate) When baud rate generator operates in double speed mode (when the BGDM bit of SCEMR is 1): N= Pφ × 106 − 1 (Operation on a base clock with a frequency of 16 times 32 × 22n-1 × B the bit rate) N= Pφ × 106 − 1 (Operation on a base clock with a frequency of 8 times 16 × 22n-1 × B the bit rate) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 709 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO  Clock synchronous mode: N= B: N: P: n: Pφ × 106 − 1 8 × 22n-1 × B Bit rate (bits/s) SCBRR setting for baud rate generator (0  N  255) (The setting must satisfy the electrical characteristics.) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n  0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.) Table 16.3 SCSMR Settings SCSMR Settings n Clock Source CKS[1] CKS[0] 0 P 0 0 1 P/4 0 1 2 P/16 1 0 3 P/64 1 1 The bit rate error in asynchronous mode is given by the following formula: When baud rate generator operates in normal mode (the BGDM bit of SCEMR is 0): Error (%) = Error (%) = Pφ × 106 (N + 1) × B × 64 × 22n-1 − 1 × 100 (Operation on a base clock with a frequency of 16 times the bit rate) Pφ × 106 − 1 × 100 (Operation on a base clock with (N + 1) × B × 32× 22n-1 a frequency of 8 times the bit rate) When baud rate generator operates in double speed mode (the BGDM bit of SCEMR is 1): Error (%) = Pφ × 106 − 1 × 100 (Operation on a base clock with (N + 1) × B × 32× 22n-1 a frequency of 16 times the bit rate) Error (%) = Pφ × 106 − 1 × 100 (Operation on a base clock with (N + 1) × B × 16× 22n-1 a frequency of 8 times the bit rate) Page 710 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Table 16.4 lists the sample SCBRR settings in asynchronous mode in which a base clock frequency is 16 times the bit rate (the ABCS bit in SCEMR is 0) and the baud rate generator operates in normal mode (the BGDM bit in SCEMR is 1), and table 16.5 lists the sample SCBRR settings in clock synchronous mode. Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0) P (MHz) 30 36 Bit Rate (bits/s) n N Error (%) n N Error (%) 110 3 132 0.13 3 159 –0.12 150 3 97 –0.35 3 116 0.16 300 2 194 0.16 2 233 0.16 600 2 97 –0.35 2 116 0.16 1200 1 194 0.16 1 233 0.16 2400 1 97 –0.35 1 116 0.16 4800 0 194 0.16 0 233 0.16 9600 0 97 –0.35 0 116 0.16 19200 0 48 –0.35 0 58 –0.69 31250 0 29 0.00 0 35 0.00 38400 0 23 1.73 0 28 1.02 Note: The error rate should be  1 . R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 711 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Table 16.5 Bit Rates and SCBRR Settings (Clock Synchronous Mode) P (MHz) 30 Bit Rate (bits/s) 36 n N n N 500 3 233 – – 1000 3 116 3 140 2500 2 187 2 224 5000 2 93 2 112 10000 1 187 1 224 25000 1 74 1 89 50000 0 149 0 179 100000 0 74 0 89 250000 0 29 0 35 500000 0 14 0 17 1000000 – – 0 8 2000000 – – – – [Legend] : Setting possible, but error occurs Page 712 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Table 16.6 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Table 16.7 lists the maximum bit rates in asynchronous mode when the external clock input is used. Table 16.8 lists the maximum bit rates in clock synchronous mode when the external clock input is used (when tScyc  12tpcyc*). Note: * Make sure that the electrical characteristics of this LSI and that of a connected LSI are satisfied. Table 16.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) BGDM ABCS n N Maximum Bit Rate (bits/s) 30 0 0 0 0 937500 1 0 0 1875000 0 0 0 1875000 1 0 0 3750000 0 0 0 1125000 1 0 0 2250000 1 36 0 1 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 0 0 0 2250000 1 0 0 4500000 Page 713 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Table 16.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode) P (MHz) External Input Clock (MHz) 30 7.5000 36 9.0000 Settings ABCS Maximum Bit Rate (bits/s) 0 468750 1 937500 0 562500 1 1125000 Table 16.8 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode, tScyc  12 tpcyc) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 30 2.5000 250000.0 36 3.0000 300000.0 Page 714 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.3.9 Section 16 Serial Communication Interface with FIFO FIFO Control Register (SCFCR) SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. Bit: Initial value: R/W: 15 14 13 12 11 - - - - - 0 R 0 R 0 R 0 R 0 R 10 9 8 RSTRG[2:0] 0 R/W 0 R/W 7 6 5 RTRG[1:0] 0 R/W Bit Bit Name Initial Value R/W Description 15 to 11  All 0 R Reserved 0 R/W 0 R/W 4 TTRG[1:0] 0 R/W 0 R/W 3 2 1 0 MCE TFRST RFRST LOOP 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 10 to 8 RSTRG[2:0] 000 R/W RTS Output Active Trigger When the quantity of receive data in receive FIFO data register (SCFRDR) becomes more than the number shown below, RTS signal is set to high. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 715 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 7, 6 RTRG[1:0] 00 R/W Receive FIFO Data Trigger Set the quantity of receive data which sets the receive data full (RDF) flag in the serial status register (SCFSR). The RDF flag is set to 1 when the quantity of receive data stored in the receive FIFO data register (SCFRDR) is increased more than the set trigger number shown below.  Asynchronous mode  Clock synchronous mode 00: 1 00: 1 01: 4 01: 2 10: 8 10: 8 11: 14 11: 14 Note: 5, 4 TTRG[1:0] 00 R/W In clock synchronous mode, to transfer the receive data using the direct memory access controller, set the receive trigger number to 1. If set to other than 1, CPU must read the receive data left in SCFRDR. Transmit FIFO Data Trigger Set the quantity of remaining transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag is set to 1 when the quantity of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the set trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: Page 716 of 1910 * Values in parentheses mean the number of empty bytes in SCFTDR when the TDFE flag is set to 1. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 3 MCE 0 R/W Modem Control Enable Enables modem control signals CTS and RTS. For channels 3, 4 in clock synchronous mode, MCE bit should always be 0. 0: Modem signal disabled* 1: Modem signal enabled Note: 2 TFRST 0 R/W * CTS is fixed at active 0 regardless of the input value, and RTS is also fixed at 0. Transmit FIFO Data Register Reset Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: 1 RFRST 0 R/W * Reset operation is executed by a power-on reset. Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: 0 LOOP 0 R/W * Reset operation is executed by a power-on reset. Loop-Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and internally connects the RTS pin and CTS pin and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 717 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.3.10 FIFO Data Count Set Register (SCFDR) SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU. Bit: Initial value: R/W: 15 14 13 - - - 0 R 0 R 0 R 12 11 10 9 8 T[4:0] 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial Value R/W Description 15 to 13  All 0 R Reserved 7 6 5 - - - 0 R 0 R 0 R 4 3 2 1 0 0 R 0 R R[4:0] 0 R 0 R 0 R These bits are always read as 0. The write value should always be 0. 12 to 8 T[4:0] 00000 R T4 to T0 bits indicate the quantity of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 R[4:0] Page 718 of 1910 00000 R R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.3.11 Serial Port Register (SCSPTR) SCSPTR controls input/output and data of pins multiplexed to the functions of this module. Bits 7 and 6 can control input/output data of RTS pin. Bits 5 and 4 can control input/output data of CTS pin. Bits 3 and 2 can control input/output data of SCK pin. Bits 1 and 0 can input data from RxD pin and output data to TxD pin, so they control break of serial transmitting/receiving. The CPU can always read and write to SCSPTR. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 - - - - - - - - 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0 RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPB2IOSPB2DT Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W These bits are always read as 0. The write value should always be 0. 7 RTSIO 0 R/W RTS Port Input/Output Indicates input or output of the serial port RTS pin. When the RTS pin is actually used as a port outputting the RTSDT bit value, the MCE bit in SCFCR should be cleared to 0. 0: RTSDT bit value not output to RTS pin 1: RTSDT bit value output to RTS pin 6 RTSDT 1 R/W RTS Port Data Indicates the input/output data of the serial port RTS pin. Input/output is specified by the RTSIO bit. For output, the RTSDT bit value is output to the RTS pin. The RTS pin status is read from the RTSDT bit regardless of the RTSIO bit setting. However, RTS input/output must be set in the general purpose I/O ports. 0: Input/output data is low level 1: Input/output data is high level R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 719 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 5 CTSIO 0 R/W CTS Port Input/Output Indicates input or output of the serial port CTS pin. When the CTS pin is actually used as a port outputting the CTSDT bit value, the MCE bit in SCFCR should be cleared to 0. 0: CTSDT bit value not output to CTS pin 1: CTSDT bit value output to CTS pin 4 CTSDT 1 R/W CTS Port Data Indicates the input/output data of the serial port CTS pin. Input/output is specified by the CTSIO bit. For output, the CTSDT bit value is output to the CTS pin. The CTS pin status is read from the CTSDT bit regardless of the CTSIO bit setting. However, CTS input/output must be set in the general purpose I/O ports. 0: Input/output data is low level 1: Input/output data is high level 3 SCKIO 0 R/W SCK Port Input/Output Indicates input or output of the serial port SCK pin. When the SCK pin is actually used as a port outputting the SCKDT bit value, the CKE[1:0] bits in SCSCR should be cleared to 0. 0: SCKDT bit value not output to SCK pin 1: SCKDT bit value output to SCK pin 2 SCKDT 0 R/W SCK Port Data Indicates the input/output data of the serial port SCK pin. Input/output is specified by the SCKIO bit. For output, the SCKDT bit value is output to the SCK pin. The SCK pin status is read from the SCKDT bit regardless of the SCKIO bit setting. However, SCK input/output must be set in the general purpose I/O ports. 0: Input/output data is low level 1: Input/output data is high level Page 720 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Bit Bit Name Initial Value R/W Description 1 SPB2IO 0 R/W Serial Port Break Input/Output Indicates input or output of the serial port TxD pin. When the TxD pin is actually used as a port outputting the SPB2DT bit value, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value not output to TxD pin 1: SPB2DT bit value output to TxD pin 0 SPB2DT 0 R/W Serial Port Break Data Indicates the input data of the RxD pin and the output data of the TxD pin used as serial ports. Input/output is specified by the SPB2IO bit. When the TxD pin is set to output, the SPB2DT bit value is output to the TxD pin. The RxD pin status is read from the SPB2DT bit regardless of the SPB2IO bit setting. However, RxD input and TxD output must be set in the general purpose I/O ports. 0: Input/output data is low level 1: Input/output data is high level R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 721 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.3.12 Line Status Register (SCLSR) The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - - - - ORER 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit Bit Name Initial Value R/W Description 15 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ORER 0 R/(W)* Overrun Error Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally* 1 [Clearing conditions]  ORER is cleared to 0 when the chip is a power-on reset  ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1: An overrun error has occurred* 2 [Setting condition]  ORER is set to 1 when the next serial receiving is finished while the receive FIFO is full of 16-byte receive data. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) retains the data before an overrun error has occurred, and the next received data is discarded. When the ORER bit is set to 1, the next serial reception cannot be continued. Page 722 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO 16.3.13 Serial Extension Mode Register (SCEMR) The CPU can always read from or write to SCEMR. Setting the BGDM bit in this register to 1 allows the baud rate generator in this module operates in double-speed mode when asynchronous mode is selected (by setting the C/A bit in SCSMR to 0) and an internal clock is selected as a clock source and the SCK pin is set as an input pin (by setting the CKE[1:0] bits in SCSCR to 00). Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - BGDM - - - - - - ABCS 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value R/W Description 15 to 8  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 BGDM 0 R/W Baud Rate Generator Double-Speed Mode When the BGDM bit is set to 1, the baud rate generator in this module operates in double-speed mode. This bit is valid only when asynchronous mode is selected by setting the C/A bit in SCSMR to 0 and an internal clock is selected as a clock source and the SCK pin is set as an input pin by setting the CKE[1:0] bits in SCSCR to 00. In other settings, this bit is invalid (the baud rate generator operates in normal mode regardless of the BGDM setting). 0: Normal mode 1: Double-speed mode 6 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ABCS 0 R/W Base Clock Select in Asynchronous Mode This bit selects the base clock frequency within a bit period in asynchronous mode. This bit is valid only in asynchronous mode (when the C/A bit in SCSMR is 0). 0: Base clock frequency is 16 times the bit rate 1: Base clock frequency is 8 times the bit rate R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 723 of 1910 Section 16 Serial Communication Interface with FIFO 16.4 Operation 16.4.1 Overview SH726A Group, SH726B Group For serial communication, this module has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. This module has a 16-stage FIFO buffer for both transmission and reception, reducing the overhead of the CPU, and enabling continuous high-speed communication. Furthermore, channels 0 to 2 have RTS and CTS signals to be used as modem control signals. The transmission format is selected in the serial mode register (SCSMR), as shown in table 16.9. The clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.10. (1) Asynchronous Mode  Data length is selectable: 7 or 8 bits  Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.  In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks.  The number of stored data bytes is indicated for both the transmit and receive FIFO registers.  An internal or external clock can be selected as the clock source.  When an internal clock is selected, this module operates using the clock of on-chip baud rate generator.  When an external clock is selected, the external clock input must have a frequency 16 or 8 times the bit rate. (The on-chip baud rate generator is not used.) Page 724 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 16 Serial Communication Interface with FIFO Clock Synchronous Mode  The transmission/reception format has a fixed 8-bit data length.  In receiving, it is possible to detect overrun errors (ORER).  An internal or external clock can be selected as the clock source.  When an internal clock is selected, this module operates using the clock of the on-chip baud rate generator, and outputs this clock to external devices as the synchronous clock.  When an external clock is selected, this module operates on the input external synchronous clock not using the on-chip baud rate generator. Table 16.9 SCSMR Settings and Communication Formats SCSMR Settings Communication Format Bit 7 C/A Bit 6 Bit 5 CHR PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 8 bits Not set 1 bit 0 Asynchronous 1 1 2 bits 0 Set 1 1 0 2 bits 0 7 bits Not set 1 1 x x 0 x 1 bit 2 bits Set 1 1 1 bit 1 bit 2 bits Clock synchronous 8 bits Not set None [Legend] x: Don't care R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 725 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Table 16.10 SCSMR and SCSCR Settings and Clock Source Selection SCSMR SCSCR Transmit/Receive Clock Bit 7 C/A Bit 1, 0 CKE[1:0] Mode Clock Source SCK Pin Function 0 00 Asynchronous Internal This module does not use the SCK pin. 01 1 Outputs a clock with a frequency 16/8 times the bit rate 10 External 11 Setting prohibited 0x 10 11 Clock synchronous Inputs a clock with frequency 16/8 times the bit rate Internal Outputs the serial clock External Inputs the serial clock Setting prohibited [Legend] x: Don't care Note: When using the baud rate generator in double-speed mode (BGMD = 1), select asynchronous mode by setting the C/A bit to 0, and select an internal clock as a clock source and the SCK pin is not used (the CKE[1:0] bits set to 00). Page 726 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group 16.4.2 Section 16 Serial Communication Interface with FIFO Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections in this module are independent, so full duplex communication is possible. The transmitter and receiver are 16-stage FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. This module monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, this module synchronizes at the falling edge of the start bit. This module samples each data bit on the eighth or fourth pulse of a clock with a frequency 16 or 8 times the bit rate. Receive data is latched at the center of each bit. Idle state (mark state) 1 Serial data (LSB) 0 D0 Start bit 1 bit (MSB) D1 D2 D3 D4 D5 D6 D7 Transmit/receive data 7 or 8 bits 1 0/1 1 1 Parity bit Stop bit 1 bit or none 1 or 2 bits One unit of transfer data (character or frame) Figure 16.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits) R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 727 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO (1) Transmit/Receive Formats Table 16.11 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 16.11 Serial Communication Formats (Asynchronous Mode) Serial Transmit/Receive Format and Frame Length SCSMR Bits CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 0 0 0 START 8-bit data STOP 0 0 1 START 8-bit data STOP STOP 0 1 0 START 8-bit data P STOP 0 1 1 START 8-bit data P STOP STOP 1 0 0 START 7-bit data STOP 1 0 1 START 7-bit data STOP STOP 1 1 0 START 7-bit data P STOP 1 1 1 START 7-bit data P STOP STOP 12 [Legend] START: Start bit STOP: Stop bit P: Parity bit Page 728 of 1910 R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 SH726A Group, SH726B Group (2) Section 16 Serial Communication Interface with FIFO Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and the CKE1 and CKE0 bits in the serial control register (SCSCR). For clock source selection, refer to table 16.10, SCSMR and SCSCR Settings and Clock Source Selection. When an external clock is input at the SCK pin, it must have a frequency equal to 16 or 8 times the desired bit rate. When this module operates on an internal clock, it can output a clock signal on the SCK pin. The frequency of this output clock is 16 or 8 times the desired bit rate. (3) Transmitting and Receiving Data  Initialization (Asynchronous Mode) Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize this module as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. The operation becomes unreliable if the clock is stopped. R01UH0202EJ0200 Rev. 2.00 Sep 18, 2015 Page 729 of 1910 SH726A Group, SH726B Group Section 16 Serial Communication Interface with FIFO Figure 16.3 shows a sample flowchart for initialization. Start of initialization Clear the TE and RE bits in SCSCR to 0 [1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. Set the TFRST and RFRST bits in SCFCR to 1 [2] Set the data transfer format in SCSMR. After reading flags ER, DR, and BRK in SCFSR, and each flag in SCLSR, write 0 to clear them Set the CKE1 and CKE0 bits in SCSCR (leaving bits TIE, RIE, TE, and RE cleared to 0) [1] Set data transfer format in SCSMR [2] Set the BGDM and ABCS bits in SCEMR Set value in SCBRR [3] Set the RTRG1, RTRG0, TTRG1, TTRG0, and MCE bits in SCFCR, and clear TFRST and RFRST bits to 0 Set the ge

下载 PDF

R5S726A3P216FP#VZ 价格&库存

-> 查询更多价格&库存

很抱歉，暂时无法提供与“R5S726A3P216FP#VZ”相匹配的价格&库存，您可以联系我们找货

免费人工找货

搜索历史

R5S726A3P216FP#VZ

相关技术文章