R5S76720

REJ09B0437-0100 32 SuperH TM SH7670 Group Hardware Manual Renesas 32-Bit RISC Microcomputer RISC engine Family / SH7670 Series SH7670 SH7671 SH7672 SH7673 R5S76700 R5S76710 R5S76720 R5S76730 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev.1.00 Revision Date: Nov. 14, 2007 Rev. 1.00 Nov. 14, 2007 Page ii of xxvi Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Nov. 14, 2007 Page iii of xxvi General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev. 1.00 Nov. 14, 2007 Page iv of xxvi How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes. When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes. The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the SH7670 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document. Document Type Data Sheet Hardware Manual Contents Document Title Document No.  This manual Overview of hardware and electrical  characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. SH7670 Group Hardware Manual Software Manual Application Note Renesas Technical Update SH-2A, SH-2A FPU Software Manual REJ09B0051 The latest versions are available from our web site. Rev. 1.00 Nov. 14, 2007 Page v of xxvi 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF (4) (2) 14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1) CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0. 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected. Rev. 0.50, 10/04, page 416 of 914 (3) Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual. Rev. 1.00 Nov. 14, 2007 Page vi of xxvi 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: 15  14  13 12 11 10  0 R 9  1 R 8  0 R/W 7  0 R/W 6  0 R/W 5  0 R/W 4 Q 0 R/W 3 2 1 0 IFE ASID2 ASID1 ASID0 0 R/W 0 R/W 0 R/W ACMP2 ACMP1 ACMP0 0 R/W 0 R/W 0 R/W Initial value: R/W: 0 R/W 0 R/W 0 R/W [Table of Bits] (1) (2) (3) (4) (5) Bit 15 14 13 to 11 10 9 Bit Name − − ASID2 to ASID0 − − − Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R Description Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1. Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual. (1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "−". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 −: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing. Rev. 1.00 Nov. 14, 2007 Page vii of xxvi 4. Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Description Bus controller Clock pulse generator Data transfer controller Interrupt controller Abbreviation BSC CPG DTC INTC • Abbreviations other than those listed above Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Description Asynchronous communications interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Nov. 14, 2007 Page viii of xxvi Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features................................................................................................................................. 1 Applications.......................................................................................................................... 2 Overview of Specifications................................................................................................... 2 Product Lineup.................................................................................................................... 12 Block Diagram.................................................................................................................... 14 Pin Assignments ................................................................................................................. 15 Pin Functions ...................................................................................................................... 16 Section 2 CPU......................................................................................................29 2.1 Register Configuration........................................................................................................ 29 2.1.1 General Registers................................................................................................ 29 2.1.2 Control Registers ................................................................................................ 30 2.1.3 System Registers................................................................................................. 32 2.1.4 Register Banks .................................................................................................... 33 2.1.5 Initial Values of Registers................................................................................... 33 Data Formats....................................................................................................................... 34 2.2.1 Data Format in Registers .................................................................................... 34 2.2.2 Data Formats in Memory .................................................................................... 34 2.2.3 Immediate Data Format ...................................................................................... 35 Instruction Features............................................................................................................. 36 2.3.1 RISC-Type Instruction Set.................................................................................. 36 2.3.2 Addressing Modes .............................................................................................. 40 2.3.3 Instruction Format............................................................................................... 45 Instruction Set ..................................................................................................................... 49 2.4.1 Instruction Set by Classification ......................................................................... 49 2.4.2 Data Transfer Instructions................................................................................... 55 2.4.3 Arithmetic Operation Instructions ...................................................................... 59 2.4.4 Logic Operation Instructions .............................................................................. 62 2.4.5 Shift Instructions................................................................................................. 63 2.4.6 Branch Instructions ............................................................................................. 64 2.4.7 System Control Instructions................................................................................ 65 2.4.8 Floating-Point Operation Instructions................................................................. 67 2.4.9 FPU-Related CPU Instructions ........................................................................... 69 2.4.10 Bit Manipulation Instructions ............................................................................. 70 Processing States................................................................................................................. 72 2.2 2.3 2.4 2.5 Rev. 1.00 Nov. 14, 2007 Page ix of xxvi Section 3 Floating-Point Unit (FPU)................................................................... 75 3.1 3.2 Features............................................................................................................................... 75 Data Formats....................................................................................................................... 76 3.2.1 Floating-Point Format......................................................................................... 76 3.2.2 Non-Numbers (NaN) .......................................................................................... 79 3.2.3 Denormalized Numbers ...................................................................................... 80 Register Descriptions.......................................................................................................... 81 3.3.1 Floating-Point Registers ..................................................................................... 81 3.3.2 Floating-Point Status/Control Register (FPSCR) ............................................... 82 3.3.3 Floating-Point Communication Register (FPUL) ............................................... 83 Rounding ............................................................................................................................ 84 Floating-Point Exceptions................................................................................................... 85 3.5.1 FPU Exception Sources ...................................................................................... 85 3.5.2 FPU Exception Handling .................................................................................... 86 3.3 3.4 3.5 Section 4 Cache ................................................................................................... 87 4.1 4.2 Features............................................................................................................................... 87 4.1.1 Cache Structure................................................................................................... 87 Register Descriptions.......................................................................................................... 90 4.2.1 Cache Control Register 1 (CCR1) ...................................................................... 90 4.2.2 Cache Control Register 2 (CCR2) ...................................................................... 92 Operation ............................................................................................................................ 96 4.3.1 Searching Cache ................................................................................................. 96 4.3.2 Read Access........................................................................................................ 98 4.3.3 Prefetch Operation (Only for Operand Cache) ................................................... 98 4.3.4 Write Operation (Only for Operand Cache) ....................................................... 99 4.3.5 Write-Back Buffer (Only for Operand Cache).................................................... 99 4.3.6 Coherency of Cache and External Memory...................................................... 101 Memory-Mapped Cache ................................................................................................... 102 4.4.1 Address Array................................................................................................... 102 4.4.2 Data Array ........................................................................................................ 103 4.4.3 Usage Examples................................................................................................ 105 4.4.4 Notes................................................................................................................. 105 4.3 4.4 Section 5 Exception Handling ........................................................................... 107 5.1 Overview .......................................................................................................................... 107 5.1.1 Types of Exception Handling and Priority ....................................................... 107 5.1.2 Exception Handling Operations........................................................................ 109 5.1.3 Exception Handling Vector Table .................................................................... 111 Resets................................................................................................................................ 113 5.2 Rev. 1.00 Nov. 14, 2007 Page x of xxvi 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.2.1 Input/Output Pins.............................................................................................. 113 5.2.2 Types of Reset .................................................................................................. 113 5.2.3 Power-On Reset ................................................................................................ 114 5.2.4 Manual Reset .................................................................................................... 116 Address Errors .................................................................................................................. 117 5.3.1 Address Error Sources ...................................................................................... 117 5.3.2 Address Error Exception Handling ................................................................... 118 Register Bank Errors......................................................................................................... 119 5.4.1 Register Bank Error Sources............................................................................. 119 5.4.2 Register Bank Error Exception Handling ......................................................... 119 Interrupts........................................................................................................................... 120 5.5.1 Interrupt Sources............................................................................................... 120 5.5.2 Interrupt Priority Level ..................................................................................... 121 5.5.3 Interrupt Exception Handling ........................................................................... 122 Exceptions Triggered by Instructions ............................................................................... 123 5.6.1 Types of Exceptions Triggered by Instructions ................................................ 123 5.6.2 Trap Instructions ............................................................................................... 124 5.6.3 Slot Illegal Instructions ..................................................................................... 124 5.6.4 General Illegal Instructions............................................................................... 124 5.6.5 Integer Division Instructions............................................................................. 125 5.6.6 Floating-Point Operation Instruction ................................................................ 126 When Exception Sources Are Not Accepted .................................................................... 127 Stack Status after Exception Handling Ends..................................................................... 128 Usage Notes ...................................................................................................................... 130 5.9.1 Value of Stack Pointer (SP) .............................................................................. 130 5.9.2 Value of Vector Base Register (VBR) .............................................................. 130 5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 130 Section 6 Interrupt Controller (INTC) ...............................................................131 6.1 6.2 6.3 Features............................................................................................................................. 131 Input/Output Pins.............................................................................................................. 133 Register Descriptions........................................................................................................ 134 6.3.1 Interrupt Priority Registers 01, 02, 06 to 16 (IPR01, IPR02, IPR06 to IPR16) ...................................................................... 135 6.3.2 Interrupt Control Register 0 (ICR0).................................................................. 137 6.3.3 Interrupt Control Register 1 (ICR1).................................................................. 138 6.3.4 IRQ Interrupt Request Register (IRQRR)......................................................... 139 6.3.5 Bank Control Register (IBCR).......................................................................... 141 6.3.6 Bank Number Register (IBNR)......................................................................... 142 Interrupt Sources............................................................................................................... 143 Rev. 1.00 Nov. 14, 2007 Page xi of xxvi 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.4.1 NMI Interrupt.................................................................................................... 143 6.4.2 User Break Interrupt ......................................................................................... 143 6.4.3 H-UDI Interrupt ................................................................................................ 143 6.4.4 IRQ Interrupts................................................................................................... 144 6.4.5 On-Chip Peripheral Module Interrupts ............................................................. 145 Interrupt Exception Handling Vector Table and Priority.................................................. 146 Operation .......................................................................................................................... 151 6.6.1 Interrupt Operation Sequence ........................................................................... 151 6.6.2 Stack after Interrupt Exception Handling ......................................................... 154 Interrupt Response Time................................................................................................... 155 Register Banks .................................................................................................................. 161 6.8.1 Banked Register and Input/Output of Banks .................................................... 162 6.8.2 Bank Save and Restore Operations................................................................... 162 6.8.3 Save and Restore Operations after Saving to All Banks................................... 164 6.8.4 Register Bank Exception .................................................................................. 165 6.8.5 Register Bank Error Exception Handling ......................................................... 165 Data Transfer with Interrupt Request Signals................................................................... 166 6.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating ........................................................ 167 6.9.2 Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt ........................................................ 167 Usage Note ....................................................................................................................... 168 6.10.1 Timing to Clear an Interrupt Source ................................................................. 168 Section 7 Bus State Controller (BSC) ............................................................... 169 7.1 7.2 7.3 Features............................................................................................................................. 169 Input/Output Pins.............................................................................................................. 172 Area Overview.................................................................................................................. 174 7.3.1 Address Map..................................................................................................... 174 7.3.2 Data Bus Width and Pin Function Setting in Each Area .................................. 175 Register Descriptions........................................................................................................ 176 7.4.1 Common Control Register (CMNCR) .............................................................. 177 7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 3 to 6) ............................. 179 7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3 to 6) .......................... 184 7.4.4 SDRAM Control Register (SDCR)................................................................... 205 7.4.5 Refresh Timer Control/Status Register (RTCSR)............................................. 208 7.4.6 Refresh Timer Counter (RTCNT)..................................................................... 210 7.4.7 Refresh Time Constant Register (RTCOR) ...................................................... 211 7.4.8 AC Characteristics Switching Register (ACSWR) ........................................... 212 7.4.9 AC Characteristics Switching Key Register (ACKEYR) ................................. 213 7.4 Rev. 1.00 Nov. 14, 2007 Page xii of xxvi 7.5 7.4.10 Sequence to Write to ACSWR.......................................................................... 214 7.4.11 Internal Bus Master Bus Priority Register (IBMPR) ........................................ 215 Operation .......................................................................................................................... 217 7.5.1 Endian/Access Size and Data Alignment.......................................................... 217 7.5.2 Normal Space Interface..................................................................................... 224 7.5.3 Access Wait Control ......................................................................................... 229 7.5.4 CSn Assert Period Expansion ........................................................................... 231 7.5.5 SDRAM Interface ............................................................................................. 232 7.5.6 SRAM Interface with Byte Selection................................................................ 272 7.5.7 PCMCIA Interface ............................................................................................ 277 7.5.8 Wait between Access Cycles ............................................................................ 284 7.5.9 Others................................................................................................................ 290 Section 8 Direct Memory Access Controller (DMAC) .....................................293 8.1 8.2 8.3 Features............................................................................................................................. 293 Input/Output Pins.............................................................................................................. 296 Register Descriptions........................................................................................................ 297 8.3.1 DMA Source Address Registers (SAR)............................................................ 301 8.3.2 DMA Destination Address Registers (DAR).................................................... 302 8.3.3 DMA Transfer Count Registers (DMATCR) ................................................... 302 8.3.4 DMA Channel Control Registers (CHCR) ....................................................... 303 8.3.5 DMA Reload Source Address Registers (RSAR) ............................................. 312 8.3.6 DMA Reload Destination Address Registers (RDAR) ..................................... 313 8.3.7 DMA Reload Transfer Count Registers (RDMATCR)..................................... 314 8.3.8 DMA Operation Register (DMAOR) ............................................................... 315 8.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).............. 319 Operation .......................................................................................................................... 321 8.4.1 Transfer Flow.................................................................................................... 321 8.4.2 DMA Transfer Requests ................................................................................... 323 8.4.3 Channel Priority................................................................................................ 327 8.4.4 DMA Transfer Types........................................................................................ 330 8.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ................................ 339 8.4 Section 9 Clock Pulse Generator (CPG)............................................................343 9.1 9.2 9.3 9.4 9.5 Features............................................................................................................................. 343 Input/Output Pins.............................................................................................................. 347 Clock Operating Modes .................................................................................................... 349 Register Descriptions........................................................................................................ 354 9.4.1 Frequency Control Register (FRQCR).............................................................. 354 Changing the Frequency ................................................................................................... 357 Rev. 1.00 Nov. 14, 2007 Page xiii of xxvi 9.6 9.5.1 Changing the Multiplication Rate ..................................................................... 357 9.5.2 Changing the Division Ratio............................................................................. 358 Notes on Board Design ..................................................................................................... 359 9.6.1 Note on Inputting External Clock ..................................................................... 359 9.6.2 Note on Using an External Crystal Resonator .................................................. 359 9.6.3 Note on Resonator ............................................................................................ 360 9.6.4 Note on Using a PLL Oscillation Circuit.......................................................... 360 Section 10 Watchdog Timer (WDT) ................................................................. 361 10.1 10.2 10.3 Features............................................................................................................................. 361 Input/Output Pin ............................................................................................................... 362 Register Descriptions........................................................................................................ 363 10.3.1 Watchdog Timer Counter (WTCNT)................................................................ 363 10.3.2 Watchdog Timer Control/Status Register (WTCSR)........................................ 364 10.3.3 Watchdog Reset Control/Status Register (WRCSR) ........................................ 366 10.3.4 Notes on Register Access ................................................................................. 367 WDT Usage ...................................................................................................................... 369 10.4.1 Canceling Software Standby Mode .................................................................. 369 10.4.2 Changing the Frequency ................................................................................... 369 10.4.3 Using Watchdog Timer Mode .......................................................................... 370 10.4.4 Using Interval Timer Mode .............................................................................. 372 Usage Notes ...................................................................................................................... 373 10.5.1 Timer Variation ................................................................................................ 373 10.5.2 Prohibition against Setting H'FF to WTCNT.................................................... 373 10.5.3 System Reset by WDTOVF Signal................................................................... 373 10.5.4 Manual Reset in Watchdog Timer Mode.......................................................... 374 10.4 10.5 Section 11 Power-Down Modes........................................................................ 375 11.1 11.2 Features............................................................................................................................. 375 11.1.1 Power-Down Modes ......................................................................................... 375 Register Descriptions........................................................................................................ 376 11.2.1 Standby Control Register (STBCR).................................................................. 377 11.2.2 Standby Control Register 2 (STBCR2)............................................................. 378 11.2.3 Standby Control Register 3 (STBCR3)............................................................. 380 11.2.4 Standby Control Register 4 (STBCR4)............................................................. 382 11.2.5 System Control Register 1 (SYSCR1) .............................................................. 384 11.2.6 System Control Register 2 (SYSCR2) .............................................................. 386 11.2.7 System Control Register 3 (SYSCR3) .............................................................. 388 Operation .......................................................................................................................... 389 11.3.1 Sleep Mode ....................................................................................................... 389 11.3 Rev. 1.00 Nov. 14, 2007 Page xiv of xxvi 11.4 11.3.2 Software Standby Mode.................................................................................... 390 11.3.3 Software Standby Mode Application Example................................................. 392 11.3.4 Module Standby Function................................................................................. 393 Usage Notes ...................................................................................................................... 394 Section 12 Ethernet Controller (EtherC)...........................................................395 12.1 12.2 12.3 Features............................................................................................................................. 395 Input/Output Pins.............................................................................................................. 397 Register Description ......................................................................................................... 399 12.3.1 EtherC Mode Register (ECMR)........................................................................ 400 12.3.2 EtherC Status Register (ECSR)......................................................................... 403 12.3.3 EtherC Interrupt Permission Register (ECSIPR) .............................................. 405 12.3.4 PHY Interface Register (PIR) ........................................................................... 406 12.3.5 MAC Address High Register (MAHR)............................................................. 407 12.3.6 MAC Address Low Register (MALR).............................................................. 408 12.3.7 Receive Frame Length Register (RFLR) .......................................................... 409 12.3.8 PHY Status Register (PSR)............................................................................... 410 12.3.9 Transmit Retry Over Counter Register (TROCR) ............................................ 411 12.3.10 Delayed Collision Detect Counter Register (CDCR)........................................ 412 12.3.11 Lost Carrier Counter Register (LCCR) ............................................................. 413 12.3.12 Carrier Not Detect Counter Register (CNDCR) ............................................... 414 12.3.13 CRC Error Frame Counter Register (CEFCR).................................................. 415 12.3.14 Frame Receive Error Counter Register (FRECR)............................................. 416 12.3.15 Too-Short Frame Receive Counter Register (TSFRCR)................................... 417 12.3.16 Too-Long Frame Receive Counter Register (TLFRCR)................................... 418 12.3.17 Residual-Bit Frame Counter Register (RFCR) ................................................. 419 12.3.18 Multicast Address Frame Counter Register (MAFCR)..................................... 420 12.3.19 IPG Register (IPGR) ......................................................................................... 421 12.3.20 Automatic PAUSE Frame Set Register (APR) ................................................. 422 12.3.21 Manual PAUSE Frame Set Register (MPR) ..................................................... 423 12.3.22 PAUSE Frame Retransfer Count Set Register (TPAUSER)............................. 424 Operation .......................................................................................................................... 425 12.4.1 Transmission..................................................................................................... 425 12.4.2 Reception .......................................................................................................... 427 12.4.3 MII Frame Timing ............................................................................................ 428 12.4.4 Accessing MII Registers ................................................................................... 430 12.4.5 Magic Packet Detection .................................................................................... 433 12.4.6 Operation by IPG Setting.................................................................................. 434 12.4.7 Flow Control ..................................................................................................... 434 Connection to PHY-LSI.................................................................................................... 435 Rev. 1.00 Nov. 14, 2007 Page xv of xxvi 12.4 12.5 12.6 Usage Notes ...................................................................................................................... 436 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)........................................................ 437 13.1 13.2 Features............................................................................................................................. 437 Register Descriptions........................................................................................................ 438 13.2.1 E-DMAC Mode Register (EDMR) ................................................................... 439 13.2.2 E-DMAC Transmit Request Register (EDTRR) .............................................. 441 13.2.3 E-DMAC Receive Request Register (EDRRR)................................................ 442 13.2.4 Transmit Descriptor List Address Register (TDLAR)...................................... 443 13.2.5 Receive Descriptor List Address Register (RDLAR) ....................................... 444 13.2.6 EtherC/E-DMAC Status Register (EESR)........................................................ 445 13.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)................... 450 13.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)............................. 453 13.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................ 455 13.2.10 Transmit FIFO Threshold Register (TFTR)...................................................... 456 13.2.11 FIFO Depth Register (FDR) ............................................................................. 457 13.2.12 Receiving Method Control Register (RMCR) .................................................. 458 13.2.13 E-DMAC Operation Control Register (EDOCR) ............................................. 459 13.2.14 Receiving-Buffer Write Address Register (RBWAR) ...................................... 460 13.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) ................................. 461 13.2.16 Transmission-Buffer Read Address Register (TBRAR)................................... 461 13.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................ 462 13.2.18 Flow Control FIFO Threshold Register (FCFTR) ............................................ 462 13.2.19 Receive Data Padding Setting Register (RPADIR) .......................................... 464 13.2.20 Transmit Interrupt Register (TRIMD) .............................................................. 465 13.2.21 Checksum Mode Register (CSMR) .................................................................. 465 13.2.22 Checksum Skipped Bytes Monitor Register (CSSBM ) ................................... 467 13.2.23 Checksum Monitor Register (CSSMR) ............................................................ 468 Operation .......................................................................................................................... 469 13.3.1 Descriptor List and Data Buffers ...................................................................... 469 13.3.2 Transmission..................................................................................................... 481 13.3.3 Reception .......................................................................................................... 483 13.3.4 Multi-Buffer Frame Transmit/Receive Processing ........................................... 485 13.3.5 Padding Receive Data....................................................................................... 487 13.3.6 Checksum Calculation Function ....................................................................... 488 13.3.7 Usage Notes ...................................................................................................... 491 13.3 Rev. 1.00 Nov. 14, 2007 Page xvi of xxvi Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) ...........................493 14.1 Overview........................................................................................................................... 493 14.1.1 Features............................................................................................................. 493 14.1.2 Overall Configuration of the A-DMAC............................................................ 494 14.1.3 Restrictions on the A-DMAC ........................................................................... 497 Register Descriptions........................................................................................................ 498 14.2.1 Channel [i] Processing Control Register (C[i]C) (i = 0, 1) ............................... 499 14.2.2 Channel [i] Processing Mode Register (C[i]M) (i = 0, 1) ................................. 502 14.2.3 Channel [i] Processing Interrupt Request Register (C[i]I) (i = 0, 1) ................. 503 14.2.4 Channel [i] Processing Descriptor Start Address Register (C[i]DSA) (i = 0, 1)........................................................................................... 505 14.2.5 Channel [i] Processing Descriptor Current Address Register (C[i]DCA) (i = 0, 1) .......................................................................................... 506 14.2.6 Channel [i] Processing Descriptor 0 Register (C[i]D0) [Control] (i = 0, 1)...... 507 14.2.7 Channel [i] Processing Descriptor 1 Register (C[i]D1) [Source Address] (i = 0, 1) ................................................................. 513 14.2.8 Channel [i] Processing Descriptor 2 Register (C[i]D2) [Destination Address] (i = 0, 1)......................................................... 514 14.2.9 Channel [i] Processing Descriptor 3 Register (C[i]D3) [Data Length] (i = 0, 1) ...................................................................... 514 14.2.10 Channel [i] Processing Descriptor 4 Register (C[i]D4) [Checksum Value Write Address] (i = 0, 1)....................................... 516 14.2.11 FEC DMAC Processing Control Register (FECC) ........................................... 516 14.2.12 FEC DMAC Processing Interrupt Request Register (FECI)............................. 520 14.2.13 FEC DMAC Processing Descriptor Start Address Register (FECDSA)........... 523 14.2.14 FEC DMAC Processing Descriptor Current Address Register (FECDCA) ..... 524 14.2.15 FEC DMAC Processing Descriptor 0 Register (FECD00) [Control] ............... 525 14.2.16 FEC DMAC Processing Descriptor 1 Register (FECD01D0A) [Destination Address] .............................................................. 529 14.2.17 FEC DMAC Processing Descriptor 2 Register (FECD02S0A) [Source 0 Address] ................................................................... 529 14.2.18 FEC DMAC Processing Descriptor 3 Register (FECD03S1A) [Source 1 Address] ................................................................... 530 Functions........................................................................................................................... 531 14.3.1 DMAC Channel Function ................................................................................. 532 14.3.2 Checksum ......................................................................................................... 533 14.3.3 FEC Channel..................................................................................................... 533 14.3.4 FEC Operation .................................................................................................. 534 Rev. 1.00 Nov. 14, 2007 Page xvii of xxvi 14.2 14.3 14.4 14.5 Channel Operation ............................................................................................................ 535 14.4.1 Descriptor Format............................................................................................. 535 14.4.2 Basic Channel Operation .................................................................................. 536 14.4.3 Checksum ......................................................................................................... 537 FEC Channel Operation.................................................................................................... 539 14.5.1 Descriptor Format for FEC Channel................................................................. 539 14.5.2 Basic FEC Channel Operation .......................................................................... 540 Section 15 Stream Interface (STIF).................................................................. 543 15.1 15.2 15.3 Features............................................................................................................................. 543 Input/Output Pins.............................................................................................................. 545 Register Descriptions........................................................................................................ 546 15.3.1 STIF Mode Select Register (STMDR).............................................................. 547 15.3.2 STIF Control Register (STCTLR) .................................................................... 550 15.3.3 STIF Internal Counter Control Register (STCNTCR) ...................................... 552 15.3.4 STIF Internal Counter Set Register (STCNTVR)............................................. 553 15.3.5 STIF Status Register (STSTR).......................................................................... 553 15.3.6 STIF Interrupt Enable Register (STIER) .......................................................... 556 15.3.7 STIF Transfer Size Register (STSIZER) (n = 0,1) ........................................... 557 15.3.8 STIFPWM Mode Register (STPWMMR) ........................................................ 558 15.3.9 STIFPWM Control Register (STPWMCR) ...................................................... 562 15.3.10 STIFPWM Register (STPWMR)...................................................................... 564 15.3.11 STIFPCR0, STIFPCR01 Registers (STPCR0R, STPCR1R) ............................ 565 15.3.12 STIFSTC0, STIFSTC1 Registers (STSTC0R, STSTC1R)............................... 566 15.3.13 STIF Lock Control Register (STLKCR)........................................................... 567 15.3.14 STIF Debugging Status Register (STDBGR) ................................................... 570 Examples of Clock Connection to Another Device .......................................................... 570 15.4.1 A Basic Example .............................................................................................. 570 15.4.2 An Example of Clock Connection When Another Device Has No Clock Input...................................................... 570 15.4.3 An Example of Clock Connection When Another Device Has No Clock Output ................................................... 571 Input/Output Timing......................................................................................................... 571 PCR Clock Recovery Module (PCRRCV) ....................................................................... 578 15.6.1 Operation of PCR Clock Recovery................................................................... 579 15.6.2 PCR Clock Recovery Operation ....................................................................... 581 15.4 15.5 15.6 Rev. 1.00 Nov. 14, 2007 Page xviii of xxvi Section 16 Serial Sound Interface (SSI) ............................................................585 16.1 16.2 16.3 Features............................................................................................................................. 585 Input/Output Pins.............................................................................................................. 587 Register Description ......................................................................................................... 588 16.3.1 Control Register (SSICR) ................................................................................. 589 16.3.2 Status Register (SSISR) .................................................................................... 595 16.3.3 Transmit Data Register (SSITDR).................................................................... 600 16.3.4 Receive Data Register (SSIRDR) ..................................................................... 600 16.3.5 SSI Clock Selection Register (SCSR)............................................................... 601 Operation Description....................................................................................................... 602 16.4.1 Bus Format........................................................................................................ 602 16.4.2 Non-Compressed Modes................................................................................... 603 16.4.3 Operation Modes............................................................................................... 613 16.4.4 Transmit Operation ........................................................................................... 614 16.4.5 Receive Operation............................................................................................. 617 16.4.6 Temporary Stop and Restart Procedures in Transmit Mode ............................. 620 16.4.7 Serial Bit Clock Control.................................................................................... 621 Usage Notes ...................................................................................................................... 622 16.5.1 Limitations from Overflow during Receive DMA Operation........................... 622 16.4 16.5 Section 17 USB 2.0 Host/Function Module (USB) ...........................................623 17.1 17.2 17.3 Features............................................................................................................................. 623 Input / Output Pins............................................................................................................ 626 Register Description ......................................................................................................... 628 17.3.1 System Configuration Control Register (SYSCFG) ......................................... 635 17.3.2 CPU Bus Wait Setting Register (BUSWAIT) .................................................. 639 17.3.3 System Configuration Status Register (SYSSTS)............................................. 640 17.3.4 Device State Control Register (DVSTCTR) ..................................................... 642 17.3.5 Test Mode Register (TESTMODE) .................................................................. 648 17.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) ................ 651 17.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)............................................. 652 17.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)............. 654 17.3.9 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ........ 661 17.3.10 Interrupts Enable Register 0 (INTENB0) ......................................................... 665 17.3.11 Interrupt Enable Register 1 (INTENB1) ........................................................... 667 17.3.12 BRDY Interrupt Enable Register (BRDYENB) ............................................... 669 17.3.13 NRDY Interrupt Enable Register (NRDYENB) ............................................... 671 17.3.14 BEMP Interrupt Enable Register (BEMPENB) ................................................ 673 17.3.15 SOF Control Register (SOFCFG) ..................................................................... 675 Rev. 1.00 Nov. 14, 2007 Page xix of xxvi 17.4 17.5 17.3.16 Interrupt Status Register 0 (INTSTS0) ............................................................. 677 17.3.17 Interrupt Status Register 1 (INTSTS1) ............................................................. 682 17.3.18 BRDY Interrupt Status Register (BRDYSTS).................................................. 688 17.3.19 NRDY Interrupt Status Register (NRDYSTS) ................................................. 689 17.3.20 BEMP Interrupt Status Register (BEMPSTS) .................................................. 691 17.3.21 Frame Number Register (FRMNUM)............................................................... 692 17.3.22 µFrame Number Register (UFRMNUM) ......................................................... 695 17.3.23 USB Address Register (USBADDR)................................................................ 696 17.3.24 USB Request Type Register (USBREQ) .......................................................... 697 17.3.25 USB Request Value Register (USBVAL) ........................................................ 699 17.3.26 USB Request Index Register (USBINDX) ....................................................... 700 17.3.27 USB Request Length Register (USBLENG) .................................................... 701 17.3.28 DCP Configuration Register (DCPCFG).......................................................... 702 17.3.29 DCP Maximum Packet Size Register (DCPMAXP) ........................................ 703 17.3.30 DCP Control Register (DCPCTR) .................................................................... 704 17.3.31 Pipe Window Select Register (PIPESEL)......................................................... 714 17.3.32 Pipe Configuration Register (PIPECFG) .......................................................... 716 17.3.33 Pipe Buffer Setting Register (PIPEBUF).......................................................... 723 17.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)......................................... 726 17.3.35 Pipe Timing Control Register (PIPEPERI)....................................................... 728 17.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)........................................... 730 17.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)........... 750 17.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5) ...................... 752 17.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A)............. 754 17.3.40 Bus Wait Register (D0FWAIT, D1FWAIT)..................................................... 757 Operation .......................................................................................................................... 758 17.4.1 System Control and Oscillation Control ........................................................... 758 17.4.2 Interrupt Functions............................................................................................ 761 17.4.3 Pipe Control ...................................................................................................... 784 17.4.4 FIFO Buffer Memory........................................................................................ 794 17.4.5 Control Transfers (DCP)................................................................................... 804 17.4.6 Bulk Transfers (PIPE1 to PIPE5) ..................................................................... 808 17.4.7 Interrupt Transfers (PIPE6 to PIPE9) ............................................................... 810 17.4.8 Isochronous Transfers (PIPE1 and PIPE2) ....................................................... 811 17.4.9 SOF Interpolation Function .............................................................................. 823 17.4.10 Pipe Schedule.................................................................................................... 824 Usage Notes ...................................................................................................................... 826 17.5.1 Power Supplies for the USB Module................................................................ 826 17.5.2 DTCH Interrupt ................................................................................................ 830 Rev. 1.00 Nov. 14, 2007 Page xx of xxvi Section 18 SD Host Interface (SDHI)................................................................831 Section 19 I2C Bus Interface 3 (IIC3) ................................................................833 19.1 19.2 19.3 Features............................................................................................................................. 833 Input/Output Pins.............................................................................................................. 835 Register Descriptions........................................................................................................ 836 19.3.1 I2C Bus Control Register 1 (ICCR1)................................................................. 836 19.3.2 I2C Bus Control Register 2 (ICCR2)................................................................. 839 19.3.3 I2C Bus Mode Register (ICMR)........................................................................ 841 19.3.4 I2C Bus Interrupt Enable Register (ICIER) ....................................................... 843 19.3.5 I2C Bus Status Register (ICSR)......................................................................... 845 19.3.6 Slave Address Register (SAR).......................................................................... 848 19.3.7 I2C Bus Transmit Data Register (ICDRT)......................................................... 848 19.3.8 I2C Bus Receive Data Register (ICDRR).......................................................... 849 19.3.9 I2C Bus Shift Register (ICDRS)........................................................................ 849 19.3.10 NF2CYC Register (NF2CYC) .......................................................................... 850 Operation .......................................................................................................................... 851 19.4.1 I2C Bus Format.................................................................................................. 851 19.4.2 Master Transmit Operation ............................................................................... 852 19.4.3 Master Receive Operation................................................................................. 854 19.4.4 Slave Transmit Operation ................................................................................. 856 19.4.5 Slave Receive Operation................................................................................... 859 19.4.6 Clocked Synchronous Serial Format................................................................. 860 19.4.7 Noise Filter ....................................................................................................... 864 19.4.8 Example of Use................................................................................................. 865 Interrupt Requests ............................................................................................................. 869 Bit Synchronous Circuit.................................................................................................... 870 Usage Notes ...................................................................................................................... 873 19.7.1 Notes on Working in Multi-master Mode......................................................... 873 19.7.2 Notes on Working in Master Receive Mode..................................................... 873 19.7.3 Notes on Setting ACKBT in Master Receive Mode ......................................... 873 19.7.4 Notes on the States of MST and TRN Bits when Arbitration Is Lost ............... 874 19.4 19.5 19.6 19.7 Section 20 Host Interface (HIF).........................................................................875 20.1 20.2 20.3 Features............................................................................................................................. 875 Input/Output Pins.............................................................................................................. 877 Parallel Access.................................................................................................................. 878 20.3.1 Operation .......................................................................................................... 878 20.3.2 Connection Method........................................................................................... 878 Register Descriptions........................................................................................................ 879 Rev. 1.00 Nov. 14, 2007 Page xxi of xxvi 20.4 20.5 20.6 20.7 20.8 20.9 20.4.1 HIF Index Register (HIFIDX) .......................................................................... 880 20.4.2 HIF General Status Register (HIFGSR)............................................................ 882 20.4.3 HIF Status/Control Register (HIFSCR) ............................................................ 883 20.4.4 HIF Memory Control Register (HIFMCR)....................................................... 886 20.4.5 HIF Internal Interrupt Control Register (HIFIICR) .......................................... 888 20.4.6 HIF External Interrupt Control Register (HIFEICR) ........................................ 889 20.4.7 HIF Address Register (HIFADR) ..................................................................... 890 20.4.8 HIF Data Register (HIFDATA) ........................................................................ 891 20.4.9 HIF Boot Control Register (HIFBCR).............................................................. 891 20.4.10 HIFDREQ Trigger Register (HIFDTR)............................................................ 893 20.4.11 HIF Bank Interrupt Control Register (HIFBICR)............................................. 894 Memory Map .................................................................................................................... 896 Interface ............................................................................................................................ 897 20.6.1 Basic Sequence ................................................................................................. 897 20.6.2 Reading/Writing of HIF Registers other than HIFIDX and HIFIDX ............... 898 20.6.3 Consecutive Data Writing to HIFRAM by External Device............................. 899 20.6.4 Consecutive Data Reading from HIFRAM to External Device ........................ 900 External DMAC Interface................................................................................................. 901 Alignment Control ............................................................................................................ 906 Interface When External Device Power is Cut Off........................................................... 907 Section 21 Compare Match Timer (CMT) ........................................................ 911 21.1 21.2 Features............................................................................................................................. 911 Register Descriptions........................................................................................................ 912 21.2.1 Compare Match Timer Start Register (CMSTR) .............................................. 913 21.2.2 Compare Match Timer Control/Status Register (CMCSR) .............................. 914 21.2.3 Compare Match Counter (CMCNT) ................................................................. 916 21.2.4 Compare Match Constant Register (CMCOR) ................................................. 916 Operation .......................................................................................................................... 917 21.3.1 Interval Count Operation .................................................................................. 917 21.3.2 CMCNT Count Timing..................................................................................... 917 Interrupts........................................................................................................................... 918 21.4.1 Interrupt Sources and DMA Transfer Requests ................................................ 918 21.4.2 Timing of Compare Match Flag Setting ........................................................... 918 21.4.3 Timing of Compare Match Flag Clearing......................................................... 919 Usage Notes ...................................................................................................................... 920 21.5.1 Conflict between Write and Compare-Match Processes of CMCNT ............... 920 21.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ............... 921 21.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT................. 922 21.5.4 Compare Match Between CMCNT and CMCOR ............................................ 922 21.3 21.4 21.5 Rev. 1.00 Nov. 14, 2007 Page xxii of xxvi Section 22 Serial Communication Interface with FIFO (SCIF) ........................923 22.1 22.2 22.3 Features............................................................................................................................. 923 Input/Output Pins.............................................................................................................. 925 Register Descriptions........................................................................................................ 926 22.3.1 Receive Shift Register (SCRSR)....................................................................... 928 22.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 928 22.3.3 Transmit Shift Register (SCTSR) ..................................................................... 929 22.3.4 Transmit FIFO Data Register (SCFTDR) ......................................................... 929 22.3.5 Serial Mode Register (SCSMR)........................................................................ 930 22.3.6 Serial Control Register (SCSCR)...................................................................... 933 22.3.7 Serial Status Register (SCFSR) ........................................................................ 937 22.3.8 Bit Rate Register (SCBRR) .............................................................................. 945 22.3.9 FIFO Control Register (SCFCR) ...................................................................... 952 22.3.10 FIFO Data Count Set Register (SCFDR) .......................................................... 955 22.3.11 Serial Port Register (SCSPTR) ......................................................................... 956 22.3.12 Line Status Register (SCLSR) .......................................................................... 959 Operation .......................................................................................................................... 960 22.4.1 Overview........................................................................................................... 960 22.4.2 Operation in Asynchronous Mode .................................................................... 963 22.4.3 Operation in Clocked Synchronous Mode ........................................................ 974 SCIF Interrupts ................................................................................................................. 983 Usage Notes ...................................................................................................................... 984 22.6.1 SCFTDR Writing and TDFE Flag .................................................................... 984 22.6.2 SCFRDR Reading and RDF Flag ..................................................................... 984 22.6.3 Break Detection and Processing ....................................................................... 985 22.6.4 Sending a Break Signal..................................................................................... 985 22.6.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 985 22.4 22.5 22.6 Section 23 Pin Function Controller (PFC).........................................................987 23.1 Register Descriptions ...................................................................................................... 1003 23.1.1 Port A I/O Register H (PAIORH) ................................................................... 1004 23.1.2 Port A Control Registers H2 and H1 (PACRH2, PACRH1) .......................... 1005 23.1.3 Port B I/O Register L (PBIORL) .................................................................... 1008 23.1.4 Port B Control Register L1 (PBCRL1) ........................................................... 1009 23.1.5 Port C I/O Registers H and L (PCIORH, PCIORL)........................................ 1011 23.1.6 Port C Control Registers H1, L2, and L1 (PCCRH1, PCCRL2, PCCRL1) .... 1012 23.1.7 Port D I/O Register L (PDIORL) .................................................................... 1018 23.1.8 Port D Control Register L1 (PDCRL1)........................................................... 1019 23.1.9 Port E I/O Register L (PEIORL) ..................................................................... 1021 23.1.10 Port E Control Registers L2 and L1 (PECRL2, PECRL1).............................. 1022 Rev. 1.00 Nov. 14, 2007 Page xxiii of xxvi 23.1.11 23.1.12 23.1.13 23.1.14 Port F I/O Register L (PFIORL) ..................................................................... 1026 Port F Control Registers L2 and L1 (PFCRL2, PFCRL1) .............................. 1027 Port G I/O Registers H and L (PGIORH, PGIORL) ....................................... 1031 Port G Control Registers H2, L2, and L1 (PGCRH2, PGCRL2, PGCRL1) ... 1032 Section 24 I/O Ports......................................................................................... 1039 24.1 Port A.............................................................................................................................. 1039 24.1.1 Register Descriptions...................................................................................... 1039 24.1.2 Port A Data Register H (PADRH) .................................................................. 1040 Port B.............................................................................................................................. 1042 24.2.1 Register Descriptions...................................................................................... 1042 24.2.2 Port B Data Register L (PBDRL) ................................................................... 1043 Port C.............................................................................................................................. 1045 24.3.1 Register Descriptions...................................................................................... 1045 24.3.2 Port C Data Registers H and L (PCDRH and PCDRL) .................................. 1046 Port D.............................................................................................................................. 1049 24.4.1 Register Descriptions...................................................................................... 1049 24.4.2 Port D Data Register L (PDDRL)................................................................... 1050 Port E .............................................................................................................................. 1052 24.5.1 Register Descriptions...................................................................................... 1052 24.5.2 Port E Data Register L (PEDRL).................................................................... 1053 Port F .............................................................................................................................. 1055 24.6.1 Register Descriptions...................................................................................... 1055 24.6.2 Port F Data Register L (PFDRL) .................................................................... 1056 Port G.............................................................................................................................. 1058 24.7.1 Register Descriptions...................................................................................... 1059 24.7.2 Port G Data Registers H and L (PGDRH and PGDRL).................................. 1059 24.2 24.3 24.4 24.5 24.6 24.7 Section 25 User Break Controller (UBC)........................................................ 1063 25.1 25.2 Features........................................................................................................................... 1063 Register Descriptions...................................................................................................... 1065 25.2.1 Break Address Register (BAR)....................................................................... 1066 25.2.2 Break Address Mask Register (BAMR) ......................................................... 1067 25.2.3 Break Data Register (BDR) ............................................................................ 1068 25.2.4 Break Data Mask Register (BDMR)............................................................... 1069 25.2.5 Break Bus Cycle Register (BBR) ................................................................... 1070 25.2.6 Break Control Register (BRCR) ..................................................................... 1072 Operation ........................................................................................................................ 1074 25.3.1 Flow of the User Break Operation .................................................................. 1074 25.3.2 Break on Instruction Fetch Cycle ................................................................... 1075 25.3 Rev. 1.00 Nov. 14, 2007 Page xxiv of xxvi 25.4 25.3.3 Break on Data Access Cycle........................................................................... 1076 25.3.4 Value of Saved Program Counter ................................................................... 1077 25.3.5 Usage Examples.............................................................................................. 1078 Usage Notes .................................................................................................................... 1081 Section 26 High-Performance User Debugging Interface (H-UDI) ................1083 26.1 26.2 26.3 Features........................................................................................................................... 1083 Input/Output Pins............................................................................................................ 1084 Register Descriptions...................................................................................................... 1085 26.3.1 Bypass Register (SDBPR) .............................................................................. 1085 26.3.2 Instruction Register (SDIR) ............................................................................ 1086 Operation ........................................................................................................................ 1087 26.4.1 TAP Controller ............................................................................................... 1087 26.4.2 Reset Configuration ........................................................................................ 1088 26.4.3 TDO Output Timing ....................................................................................... 1089 26.4.4 H-UDI Reset ................................................................................................... 1090 26.4.5 H-UDI Interrupt .............................................................................................. 1090 Usage Notes .................................................................................................................... 1091 26.4 26.5 Section 27 On-Chip RAM ...............................................................................1093 27.1 27.2 Features........................................................................................................................... 1093 Usage Notes .................................................................................................................... 1094 27.2.1 Page Conflict................................................................................................... 1094 27.2.2 RAME and RAMWE Bits .............................................................................. 1094 Section 28 List of Registers .............................................................................1095 28.1 28.2 28.3 Register Addresses (by Functional Module, in Order of the Manual's Section Numbers) ............................. 1096 Register Bits.................................................................................................................... 1114 Register States in Each Operating Mode ........................................................................ 1157 Section 29 Electrical Characteristics .................................................................1171 29.1 29.2 29.3 29.4 Absolute Maximum Ratings ........................................................................................... 1171 Power-on/Power-off Sequence ....................................................................................... 1172 DC Characteristics .......................................................................................................... 1173 AC Characteristics .......................................................................................................... 1181 29.4.1 Clock Timing .................................................................................................. 1182 29.4.2 Control Signal Timing .................................................................................... 1186 29.4.3 Bus Timing ..................................................................................................... 1187 29.4.4 DMAC Module Timing .................................................................................. 1216 Rev. 1.00 Nov. 14, 2007 Page xxv of xxvi 29.4.5 Watchdog Timer Timing ................................................................................ 1217 29.4.6 SCIF Module Timing...................................................................................... 1218 29.4.7 IIC3 Module Timing....................................................................................... 1220 29.4.8 SSI Module Timing ........................................................................................ 1222 29.4.9 USB Transceiver Timing ................................................................................ 1225 29.4.10 SDHI Module Timing..................................................................................... 1227 29.4.11 I/O Port Timing............................................................................................... 1229 29.4.12 HIF Module Signal Timing............................................................................. 1230 29.4.13 EtherC Module Signal Timing........................................................................ 1233 29.4.14 H-UDI Related Pin Timing............................................................................. 1237 29.4.15 STIF Module Signal Timing (1) ..................................................................... 1239 29.4.16 STIF Module Signal Timing (2) ..................................................................... 1240 29.4.17 STIF Module Signal Timing (3) (With Stream Input/Output Set Synchronized with STn_CLKIN Rise Time) 1241 29.4.18 STIF Module Signal Timing (4) (With Stream Input/Output Set Synchronized with STn_CLKIN Fall Time). 1243 29.4.19 STIF Module Signal Timing (5) (With Stream Output Set Synchronized with STn_CLKOUT Rise Time) ..... 1245 29.4.20 STIF Module Signal Timing (6) (With Stream Output Set Synchronized with STn_CLKOUT Fall Time) ...... 1246 29.4.21 STIF Module Signal Timing (7) ..................................................................... 1247 29.4.22 AC Characteristics Measurement Conditions ................................................. 1248 Appendix ........................................................................................................... 1247 A. B. C. Pin States ........................................................................................................................ 1247 Product Lineup................................................................................................................ 1252 Package Dimensions....................................................................................................... 1253 Index ................................................................................................................. 1255 Rev. 1.00 Nov. 14, 2007 Page xxvi of xxvi Section 1 Overview Section 1 Overview 1.1 Features This LSI is a CMOS single-chip microcontroller that integrates a Renesas Technology original RISC (Reduced Instruction Set Computer) CPU core with peripheral functions required for an Ethernet system. The CPU incorporated in this LSI is the SH-2A CPU, which features upward compatibility on the object code level with the SH-1 and SH-2 microcomputers. The CPU has a RISC-type instruction set and employs a superscalar architecture and the Harvard architecture, which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. This CPU realizes low-cost, high-performance, and high-functioning systems for applications such as high-speed realtime control, which was previously impossible with the conventional microcomputers. This LSI includes an Ethernet controller (EtherC) that incorporates a media access controller (MAC) conforming to the IEEE802.3u standard, which offers the LAN connection in the rate of 10 or 100Mbps. In addition, this LSI includes on-chip peripheral functions required for systems, such as, cache memory, RAM, a direct memory access controller (DMAC), a host interface (HIF), an USB2.0 host/function module (USB), an SD host interface (SDHI), an interrupt controller (INTC), a compare match timer (CMT), a serial communication interface with FIFO (SCIF), and I/O ports. Moreover, this LSI includes encryption functions (AES, DES and 3DES), message authentication code generating functions (HMAC-SHA-1, HMAC-SHA-224, and HMAC-SHA-256), an AV stream interface (STIF), and a serial sound interface (SSI), which can be applied to digital AV equipment with network features. This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of designing and manufacturing application systems. Rev. 1.00 Nov. 14, 2007 Page 1 of 1262 REJ09B0437-0100 Section 1 Overview 1.2 Applications Main applications: Network application equipment, consumer equipment, digital AV equipment 1.3 Overview of Specifications Table 1.1 shows the overview of the specifications of this LSI. Table 1.1 Overview of SH7670 Group Specifications Module/Function Description On-chip RAM Cache memory • • • • RAM size: 32 kbytes (four 8-kbyte banks) Instruction cache: 8 kbytes Operand cache: 8 kbytes 128-entry, 4-way set associative, 16-byte block length configuration each for the instruction cache and operand cache Write-back, write-through and LRU replacement algorithm Cache locking function available (only for operand cache); ways 2 and 3 can be locked Classification Memory • • Rev. 1.00 Nov. 14, 2007 Page 2 of 1262 REJ09B0437-0100 Section 1 Overview Classification CPU Module/Function Description CPU • • • • • • • • • • Renesas Technology original SuperH architecture Compatible with SH-1, SH-2, and SH-2E at object code level 32-bit internal data bus General-register architecture Sixteen 32-bit general registers Four 32-bit control registers Four 32-bit system registers Register bank for high-speed response to interrupts RISC-type instruction set (upward compatible with SH series) Instruction length: 16-bit fixed-length basic instructions for improved code efficiency and 32-bit instructions for high performance and usability Load/store architecture Delayed branch instructions Instruction set based on C language Superscalar architecture to execute two instructions at one time including FPU Instruction execution time: Up to two instructions/cycle Address space: 4 Gbytes Internal multiplier Five-stage pipeline Harvard architecture • • • • • • • • • Rev. 1.00 Nov. 14, 2007 Page 3 of 1262 REJ09B0437-0100 Section 1 Overview Classification CPU Module/Function Description Floating-point unit • (FPU) • • • • • • • • • • • Floating-point co-processor included Supports single-precision (32-bit) and double-precision (64-bit) Supports data type and exceptions that conform to IEEE754 standard Two rounding modes: Round to nearest and round to zero Denormalization modes: Flush to zero Floating-point registers Sixteen 32-bit floating-point registers (single-precision × 16 words or double-precision × 8 words) Two 32-bit floating-point system registers Supports FMAC (multiplication and accumulation) instructions Supports FDIV (division) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution time Latency (FMAC/FADD/FSUB/FMUL): Three cycles (single-precision), eight cycles (double-precision) Pitch (FMAC/FADD/FSUB/FMUL): One cycle (singleprecision), six cycles (double-precision) Note: FMAC only supports single-precision. • Five-stage pipeline Nine external interrupt pins (NMI and IRQ7 to IRQ0) On-chip peripheral interrupts: Priority level set for each module Sixteen priority levels available Register bank enabling fast register saving and restoring in interrupt handling Interrupts (sources) Interrupt controller • (INTC) • • • Rev. 1.00 Nov. 14, 2007 Page 4 of 1262 REJ09B0437-0100 Section 1 Overview Classification External bus extension Module/Function Description Bus state controller (BSC) • • Address space for five areas (64 Mbytes each) and 32-bit external bus The following features settable independently for each area:  Bus size: 8, 16, or 32 bits (depending on area)  Access wait cycle count  Idle wait cycle setting (same area/different area)  Supports SRAM, SRAM with byte selection, and SDRAM by specifying memory to be connected for each area  Supports the PCMCIA interface  Chip select signal output to an applicable area (Timings of CS asserting and negating are selectable by programming) • SDRAM refreshing function  Supports auto-refreshing mode and self-refreshing mode • SDRAM burst access function Eight channels (External DMA requests available for two of them) Can be activated by on-chip peripheral modules Burst mode and cycle steal mode Supports intermittent mode (16 or 64 cycles) Auto-reloading of transfer information DMA Direct memory access controller (DMAC) • • • • • Rev. 1.00 Nov. 14, 2007 Page 5 of 1262 REJ09B0437-0100 Section 1 Overview Classification Clock Module/Function Description Clock pulse generator (CPG) • Clock mode: Input clock can be selected from external input (EXTAL or CKIO) or crystal resonator (EXTAL/XTAL or USB_X1/USB_X2). Three types of clocks generated  CPU clock:  200 MHz (maximum) (regular specifications)  133 MHz (maximum) (wide temperature specifications)  Bus clock:  100 MHz (maximum) (regular specifications)  66 MHz (maximum) (wide temperature specifications)  Peripheral clock:  50 MHz (maximum) (regular specifications)  33 MHz (maximum) (wide temperature specifications) These maximum frequencies are target values that were set when we prepared this hardware manual. We will determine the guaranteed maximum frequencies after the final evaluation result of this LSI is obtained. Power-down modes • Three power-down modes provided to reduce the current consumption in this LSI  Sleep mode  Software standby mode  Module standby mode • Timer Compare match timer (CMT) • • • Two-channel 16-bit counter Four types of clocks selectable (Pφ/8, Pφ/32, Pφ/128, or Pφ/512) Generates a compare match interrupt One-channel watchdog timer Watchdog timer (WDT) • A counter overflow can reset this LSI Rev. 1.00 Nov. 14, 2007 Page 6 of 1262 REJ09B0437-0100 Section 1 Overview Classification Advanced communication Module/Function Description Ethernet controller • (EtherC) MAC (Media Access Control) function  Data frame assembly/deassembly (frame format conforming to IEEE802.3)  CSMA/CD link management (for collision avoidance and processing in case of collision)  CRC processing  On-chip FIFOs (512 bytes for transmission and reception each)  Supports full-duplex data transmission and reception  Sends and receives short and long packets • Conforms to the MII (Media Independent Interface) standard  Converts an 8-bit data stream from the MAC layer to a 4-bit MII nibble stream  Station management (STA feature)  Eighteen TTL-level signals  Transfer rate: 10 or 100 Mbps • DMAC for • Ethernet controller (E-DMAC) • • • • • Magic Packet TM with WOL (Wake On LAN) output Reduces CPU load using the descriptor management system One channel for transfer from the EtherC receive FIFO to the receive buffer One channel for transfer from the transmit buffer to the EtherC transmit FIFO Allows 16-byte burst transfer for efficient use of the system bus Supports single frame and multibuffer Calculates receive data checksum Rev. 1.00 Nov. 14, 2007 Page 7 of 1262 REJ09B0437-0100 Section 1 Overview Classification Advanced interface Module/Function Description Stream interface (STIF) • • • • • • Serial sound interface (SSI) • • • • • • USB2.0 host/function module (USB) • • • • • • SD host interface (SDHI) (Not supported in SH7672 and SH7670) • • • • • I2C bus interface 3 • (IIC3) • Two-channel port in conjunction with A-DMAC Serial mode or parallel mode selectable for each channel Supports MPEG2-TS and MPEG-PS transfer modes Supports push-type transfer and pull-type transfer to each device External VCO control PWM timer and its output provided for each channel Stream clock output common to all channels and stream clock input for each channel Two-channel bidirectional serial transfer Supports various serial audio formats Supports master and slave functions Generates programmable word clock and bit clock Multichannel formats Supports 8-, 16-, 18-, 20-, 22-, 24-, and 32-bit data formats Conforms to USB version 2.0 Supports three transfer rates: 480 Mbps, 12 Mbps, and 1.5 Mbps Software and functions switchable Connectable to multiple peripheral devices through onestage hub while the software is running Software settable On-chip 8-kbyte RAM as a communication buffer SD memory/IO card interface (1-bit/4-bit SD bus) Error check functions: CRC7 (for commands) and CRC16 (for data) Interrupt requests: Card access interrupt, SDIO access interrupt, and card detect interrupt DMAC transfer requests: SD_BUF write and SD_BUF read Supports card detection and write protection functions One channel On-chip master mode and slave mode Rev. 1.00 Nov. 14, 2007 Page 8 of 1262 REJ09B0437-0100 Section 1 Overview Classification Advanced interface Module/Function Description Host interface (HIF) • • • • On-chip 4-kbyte buffer RAM (two 2-kbyte banks) Parallel connection of buffer RAM and external device with sixteen data pins Parallel connection of buffer RAM and the CPU of this LSI with the internal bus A connected external device can access desired register after the register index was specified (However, addresses can be automatically updated during continuous buffer RAM access) Endian switchable An interrupt can be requested to a connected external device An internal interrupt can be requested to the CPU of this LSI Allows booting from the buffer RAM by storing the instruction code beforehand from the external device in the buffer RAM Three channes Clock synchronous mode or asynchronous mode selectable Supports simultaneous transmission and reception (fullduplex communication) Dedicated baud rate generator Separate 16-byte FIFO registers for transmission and reception Modem control function (asynchronous mode) • • • • Serial communication interface with FIFO (SCIF) • • • • • • Rev. 1.00 Nov. 14, 2007 Page 9 of 1262 REJ09B0437-0100 Section 1 Overview Classification Encryption, hash, and error correction Module/Function Description Encryption functions (AES, DES and 3DES) (SH7671 and SH7670 support only DMAC function. They do not support encryption function.) • Message • authentication code generating functions (HMACSHA-1, HMACSHA-224, and HMAC-SHA-256) (Not supported in SH7671 and SH7670) Forward error correction (FEC) • By reading the descriptor using the dedicated F-DMAC, missing packets can be restored quickly by switching the source address (read packet pointer), destination address (restoration packet storage address), and packet size in real time Arbitrary values can be used for the read packet pointer, read packet count, restoration packet storage address, and packet size Two break channels Addresses, data values, type of access, and data size can be set as break conditions Supports E10A emulator JTAG-standard pin assignment Supports boundary scan Eighty-six general input/output pins and eight general input pins Input or output of I/O ports can be selected for each bit • • Encryption/decryption engine can be activated by 2channel dedicated DMAC (A-DMAC) or CPU By reading the descriptor using the A-DMAC, continuous encryption/decryption available by switching the source address (unprocessed data pointer), destination address (processed data storage address), and various settings (including encryption/decryption algorithm, encryption/decryption, ECB/CBC/OFB, keys, and IV) in real time Block-by-block encryption and decryption enabled by activation from the CPU By reading the descriptor using the A-DMAC, generation of message authentication codes and checksum calculation in conjunction with encryption/decryption processing are available • Debugging function User break controller (UBC) • • • • • • • User debugging interface (H-UDI) I/O ports Rev. 1.00 Nov. 14, 2007 Page 10 of 1262 REJ09B0437-0100 Section 1 Overview Classification Package Module/Function Description • • • • P-FBGA1717-256 (0.8 pitch) I/O: 3.3 ± (0.2) V, internal: 1.2 ± (0.1) V -20 to +70°C (regualr specifications) -40 to +85°C (wide temperature specifications) Power supply voltage Operating temperature (°C) Notes: * Magic Packet TM is a registered trademark of Advanced Micro Devices, Inc. Rev. 1.00 Nov. 14, 2007 Page 11 of 1262 REJ09B0437-0100 Section 1 Overview 1.4 Product Lineup Table 1.2 lists the products and figure 1.1 shows how to read their type names. Table 1.2 Product Lineup ROM Size – – – – RAM Size 32 kbytes 32 kbytes 32 kbytes 32 kbytes Package P-FBGA256 –17 × 17 –0.8 P-FBGA256 –17 × 17 –0.8 P-FBGA256 –17 × 17 –0.8 P-FBGA256 –17 × 17 –0.8 Encryption Not mounted Not mounted Mounted Mounted SDHI Remarks Type Name (Abbreviation) R5S76700 R5S76710 R5S76720 R5S76730 Not mounted SH7670 Mounted SH7671 Not mounted SH7672 Mounted SH7673 Type Name R 5 S 76520 B 200 BG Package type BG: BGA Maximum operating frequency 200: 200MHz 133: 133MHz Characteristic code B: - 20˚C to +70˚C C: - 40˚C to +85˚C Product code ROM device type S: ROMless Classification 5 : Microcontroller R: Renesas semiconductor Family Figure 1.1 Reading of Type Name • Small package Package P-FBGA256 –17 × 17 –0.8 Code PRBG0256GA-A Body Size 17 × 17mm Pin Pitch 0.8 mm Rev. 1.00 Nov. 14, 2007 Page 12 of 1262 REJ09B0437-0100 Section 1 Overview 1.5 Block Diagram T.B.D Figure 1.2 Block Diagram 1.6 1 A B C D E F G H J K L M N P R T U V W Y PA17/ A17 PA19/ A19 PA22/ A22 HIFMD/ PA25/ A25 Pin Assignments 2 A00 3 PB04/ CE2A/ IRQ2/ DACK1 PB05/CS5/ CE1A/ IRQ3/ TEND1 4 PB00/ WAIT/ SDA PB02/ CE2B/ IRQ0 PB03/CS6/ CE1B/ IRQ1/ DREQ1 5 PB06/ CS4 RD PB01/ IOIS16/ SCL 6 WE1/ DQMLU/ WE PB07/ BS CS0 7 D09 8 D12 9 D15 10 D05 11 D02 12 A16 13 A13 14 A10 15 A07 16 A04 17 A01 18 RAS 19 CAS 20 VssQ PA18/ A18 PA21/ A21 PA24/ A24 D08 D10 D14 D06 D03 D00 A14 A11 A08 A05 A02 CS3 VssQ CKE PA20/ A20 PA23/ A23 WE0/ DQMLL D11 D13 D07 D04 D01 A15 A12 A09 A06 A03 VssQ RDWR CKIO VssQ_14 Vss_07 VccQ_14 Vcc_07 VssQ_13 VccQ_13 VccQ_12 VssQ VssQ_12 Vcc_06 WE3/ WE2/ Vss_06 VccQ_11 VssQ_11 VssQ_10 DQMUU/ DQMUL/ ICIOWR ICIORD VssQ_09 D24 D26 D25 PC18/ PC19/ LNKSTA EXOUT PC13/ TX_CLK PC07/ MII_TXD3 PC16/ MDIO PC20/ VssQ_00 WOL PC17/ VccQ_00 MDC D28 VccQ_10 D27 D29 D30 PC11/ PC12/ TX_ER TX_EN Vss_00 VccQ_09 D31 D23 D22 PC04/ PC06/ PC05/ Vcc_00 MII_TXD0 MII_TXD1 MII_TXD2 PC10/ RX_CLK PC14/ COL PC15/ CRS VccQ_08 VccQ_07 D21 D20 VssQ_01 VssQ_08 VssQ_07 D19 D18 PC03/ PC08/ MII_RXD3 RX_DV PC09/ VccQ_01 RX_ER Vcc_05 VssQ D17 D16 PF07/ ST0_D7/ SSIWS0 PF04/ ST0_D4/ CTS0 PC01/ PC02/ VccQ_02 PC00/ MII_RXD0 MII_RXD1 MII_RXD2 TESTMD ASEMD PD04/ IRQ4/ SDWP PD05/ IRQ5/ SDCD PD07/ IRQ7/ SDCLK SH7673/SH7672/SH7671/SH7670 Top view Vss_05 PF05/ ST0_D5/ RTS0 PF02/ ST0_D2/ RxD0 PF01/ PF06/ ST0_D6/ SSIDATA0 PF03/ ST0_D3/ SCK0 VssQ VssQ PD06/ IRQ6/ VssQ_02 SDCMD VccQ_06 ST0_D1/ TxD0 PF11/ TEND0 PF10/ PF00/ ST0_SYC/ ST0_D0 DACK0 PF08/ PF09/ DREQ0 PD01/ PD02/ PD03/ Vcc_01 IRQ1/ IRQ2/ IRQ3/ SDDAT1 SDDAT2 SDDAT3 PG14/ HIFD14 PG11/ HIFD11 PG09/ HIFD09 PG07/ HIFD07 PG15/ HIFD15 PD00/ IRQ0/ SDDAT0 Vcc_02 VssQ_06 ST0_PWM/ ST0_VLD/ ST0_REQ ST0_ CLKIN/ SSISCK0 Vcc_04 WDTOVF ST0_ VCO_ CLKIN ASEBRK/ ASEBRKAK PG12/ PG13/ HIFD12 HIFD13 PG10/ HIFD10 Vss_01 Vss_04 VssQ MD_BW VssQ VssQ_02 VssQ_03 VccQ_03 VssQ DG12 DV12 UV12 AV12 Vcc_03 Vss_03 VccQ_04 VccQ_05 VssQ_04 VssQ_05 MD_CK1 NMI Vcc(PLL) VssQ PG04/ PG01/ HIFD04 HIFD01 PG03/ HIFD03 PG00/ HIFD00 PG23/ HIFCS PG22/ HIFRS PG17/ HIFRDY VssQ VssQ VssQ UG12 AG12 PE07/ PE06/ PE01/ ST1_VCO_ PE03/ CLKIN/ ST1_D7/ ST1_D6/ ST1_D1/ ST1_D3/ SSIWS1 SSIDATA1 TxD1 SCK1 AUDIO_CLK TCK TDI MD_CK0 EXTAL VssQ PG06/ HIFD06 PG21/ PG16/ PG18/ HIFWR HIFDREQ HIFEBL PG20/ HIFRD PG19/ HIFINT DG33 VBUS AG33 VssQ ST1_ PE02/ PE05/ PE10/ PE11/ USB_X1 ST1_D5/ ST1_D2/ ST1_SYC/ ST1_PWM/ CLKIN/ SSISCK1 RxD1 RTS1 CTS2 RTS2 RES TDO XTAL PG08/ HIFD08 PG05/ PG02/ HIFD05 HIFD02 DV33 DM DP AV33 PE08/ PE04/ PE00/ PE09/ ST_ REFRIN USB_X2 ST1_D4/ ST1_VLD/ ST1_D0/ ST1_REQ/ CLKOUT SCK2 TxD2 CTS1 RxD2 TRST TMS Vss(PLL) Figure 1.3 Pin Assignments Rev. 1.00 Nov. 14, 2007 Page 13 of 1262 REJ09B0437-0100 Section 1 Overview 1.7 Table 1.3 Pin Functions Pin Functions I/O Name I Power supply Function Power supply pin for the internal logic circuit. All the Vcc pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground pin. All the Vss pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. Power supply pin for I/O pins. All the VccQ pins must be connected to the system power supply. This LSI does not operate correctly if there is a pin left open. Ground pin. All the VssQ pins must be connected to the system power supply (0 V). This LSI does not operate correctly if there is a pin left open. Pin connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. Classification Symbol Power supply Vcc Vss I Ground VccQ I Power supply VssQ I Ground Clock EXTAL I External clock XTAL CKIO Operating mode control MD_BW O Crystal resonator Pin connected to a crystal resonator Pin to supply the system clock to external devices Pin to set the operating mode. Do not change signal levels on this pin during operation. Pins to set the clock operating mode. Do not change signal levels on these pins during operation. This LSI enters the power-on reset state when this signal goes low. An overflow signal from the WDT is output on this pin. I/O System clock I Mode set MD_CK1, MD_CK0 System control RES WDTOVF I Clock mode set I O Power-on reset Watchdog timer overflow Rev. 1.00 Nov. 14, 2007 Page 14 of 1262 REJ09B0437-0100 Section 1 Overview Classification Symbol Interrupts NMI IRQ7 to IRQ0 I/O Name I I Non-maskable interrupt Function Non-maskable interrupt request pin. Fix it high when not in use. Interrupt requests Maskable interrupt request pins 7 to 0 Level-input or edge-input detection can be selected. When the edge-input detection is selected, the rising edge or falling edge can also be selected. Address bus Addresses are output on these pins. Bidirectional data bus pins Address bus Data bus Bus control A25 to A00 D31 to D00 CS0, CS3 to CS6 RD RD/WR BS WE3 O I/O Data bus O O O O O Chip select 0, 3 to Chip-select signal pins for external 6 memory or devices Read Read/write Bus start Most significant byte write Indicates that data is read from an external device. Read/write signal pin Bus cycle start signal pin Indicates that data is written to data bits 31 to 24 of the external memory or device. WE2 O Second byte write Indicates that data is written to data bits 23 to 16 of the external memory or device. Third byte write Indicates that data is written to data bits 15 to 8 of the external memory or device. Indicates that data is written to data bits 7 to 0 of the external memory or device. Input pin to insert a wait cycle into bus cycles during access to the external space Pin connected to the RAS pin of SDRAM Pin connected to the CAS pin of SDRAM Pin connected to the CKE pin of SDRAM Selects data bus bits 31 to 24 of SDRAM. WE1 O WE0 O Least significant byte write Wait WAIT I RAS CAS CKE DQMUU O O O O RAS CAS Clock enable Most significant byte select Rev. 1.00 Nov. 14, 2007 Page 15 of 1262 REJ09B0437-0100 Section 1 Overview Classification Symbol Bus control DQMUL DQMLU DQMLL CE1A CE1B CE2A CE2B ICIOWR ICIORD WE IOIS16 I/O Name O O O O O O O O O O I Second byte select Third byte select Least significant byte select PCMCIA card select (lower) PCMCIA card select (lower) PCMCIA card select (upper) PCMCIA card select (upper) Function Selects data bus bits 23 to 16 of SDRAM. Selects data bus bits 15 to 8 of SDRAM. Selects data bus bits 7 to 0 of SDRAM. Chip enable signal pin for PCMCIA connected to area 5 Chip enable signal pin for PCMCIA connected to area 6 Chip enable signal pin for PCMCIA connected to area 5 Chip enable signal pin for PCMCIA connected to area 6 PCMCIA I/O write Pin connected to the PCMCIA I/O strobe write strobe PCMCIA I/O read Pin connected to the PCMCIA I/O strobe read strobe PCMCIA memory Pin connected to the PCMCIA write strobe memory write strobe PCMCIA dynamic Indicates the 16-bit I/O of PCMCIA in bus sizing little-endian mode. Fix this pin low in big-endian mode. DMA-transfer request DMA-transfer request acknowledge Input pins to receive external requests for DMA transfer Output pins for signals indicating acknowledge of external requests from external devices Direct memory DREQ0, DREQ1 access controller DACK0, DACK1 (DMAC) I O TEND0, TEND1 Ethernet controller (EtherC) CRS COL MII_TXD3 to MII_TXD0 TX_EN O I I O O DMA-transfer end Output pins for DMA transfer end output Carrier sense Collision Transmit data Transmit enable Carrier sensing pin Collision detecting pin 4-bit transmit data pins Indicates that transmit data is ready on the MII_TXD3 to MII_TXD0 pins. Rev. 1.00 Nov. 14, 2007 Page 16 of 1262 REJ09B0437-0100 Section 1 Overview Classification Symbol Ethernet controller (EtherC) TX_CLK I/O Name I Transmit clock Function Input reference timing signal of TX_EN, TX_ER, and MII_TXD3 to MII_TXD0 Pin to notify the PHY-LSI of an error detected during transmission 4-bit receive data pins Indicates that valid receive data is present on the MII_RXD3 to MII_RXD0 pins Input reference timing signal of RX_DV, RX_ER, and MII_RXD3 to MII_RXD0 Pin to recognize the state of an error detected during reception Input reference timing signal of transfer data on the MDIO pin TX_ER MII_RXD3 to MII_RXD0 RX_DV O I I Transmit error Receive data Receive data valid Receive clock RX_CLK I RX_ER MDC MDIO WOL LNKSTA EXOUT Stream interface (STIF) ST_CLKOUT ST1_CLKIN, ST0_CLKIN ST1_SYC, ST0_SYC ST1_REQ, ST0_REQ ST1_VLD, ST0_VLD ST1_D[7:0], ST0_D[7:0] I O Receive error Clock for management I/O Management data Bidirectional pin to exchange I/O management data O I O O I I/O I/O I/O I/O MAGIC packet reception Link status General output Indicates that a Magic PacketTM* was received. Input pin to receive the link status signal from the PHY-LSI External output pin Data clock output pin Data clock input pins Synchronizing signal pins Request signal pins Data enable pins Data pins (The value 0 is used in serial mode) VCX0 clock pins ST1_VCO_CLKIN, I ST0_VCO_CLKIN Rev. 1.00 Nov. 14, 2007 Page 17 of 1262 REJ09B0437-0100 Section 1 Overview Classification Symbol Stream interface (STIF) ST1_PWM, ST0_PWM I/O Name O Function PWM output pins Serial sound SSIDATA1, interface (SSI) SSIDATA0 SSISCK1, SSISCK0 I/O SSI data I/O I/O SSI clock I/O Serial data I/O pins Serial clock I/O pins Word select I/O pins SSIWS1, SSIWS0 I/O SSI clock LR I/O AUDIO_CLK USB2.0 host/function module (USB) DP DM VBUS REFRIN USB_X1 USB_X2 I External clock for The external clock for audio is input to SSI audio this pin. USB bus D+ data pin USB bus D- data pin Connect this pin to Vbus of the USB bus. Connect this pin to AG33 through a resistor of 5.6 kΩ ±1%. Pins connected to the crystal resonator for USB. When an external clock is used, connect it to the USB_1 pin with the USB_2 pin open. Power supply pin for the core (3.3 V (Typ) supplied) I/O USB D+ data I/O USB D- data I I I O VBUS input Reference input Crystal resonator/external clock input for USB Analog power supply for transceiver AV33 I AG33 AV12 I I Analog ground for Ground pin for the core transceiver Analog power supply for transceiver Power supply pin for the core (1.2 V (Typ) supplied) AG12 DV33 DG33 DV12 I I I I Analog ground for Ground pin for the core transceiver Power supply for transceiver pins Ground for transceiver pins Power supply for transceiver pins Power supply pin for pins (3.3 V (Typ) supplied) Ground pin for transceiver pins Power supply pin for transceiver pins (1.2 V (Typ) supplied) Rev. 1.00 Nov. 14, 2007 Page 18 of 1262 REJ09B0437-0100 Section 1 Overview Classification Symbol USB2.0 host/function module (USB) DG12 UV12 I/O Name I I Ground for transceiver pins Digital power supply for transceiver Function Ground pin for transceiver pins Power supply pin for the core (1.2V (Typ) supplied) UG12 SD host interface (SDHI) SDCLK SDCMD SDDATA3 to SDDATA0 SDCD SDWP I C bus interface 3 (IIC3) Host interface (HIF) 2 I O Digital ground for Ground pin for the core transceiver SD clock SD clock output pin SD command output/response input signal pin SD data bus signal pins SD card detection pin SD write protect signal pin Serial clock I/O pin Serial data I/O pin HIF address, data, and command I/O pins Input pin to receive the HIF chip select signal Pin for access type switching instruction to the HIF Write strobe signal pin Read strobe signal pin Pin to make an interrupt request from the HIF to the external device Pin to specify HIF boot mode Pin to request the external device for DMA transfer to the HIFRAM A high-level input on this pin activates all the HIF pins other than this pin. Indicates that the HIF module reset was canceled in this LSI and that accesses to the HIF module from the external device are acceptable. I/O SD command I/O SD data I I SD card detect SD write protect SCL SDA I/O Serial clock pin I/O Serial data pin HIFD15 to HIFD00 I/O HIF data bus HIFCS HIFRS HIFWR HIFRD HIFINT HIFMD HIFDREQ HIFEBL HIFRDY I I I I O I O I O HIF chip select HIF register select HIF write HIF read HIF interrupt HIF mode HIFDMAC transfer request HIF pin enable HIF boot ready Rev. 1.00 Nov. 14, 2007 Page 19 of 1262 REJ09B0437-0100 Section 1 Overview Classification Symbol Serial TXD2 to TXD0 communication RXD2 to RXD0 interface with SCK2 to SCK0 FIFO (SCIF) RTS2 to RTS0 CTS2 to CTS0 I/O ports PA25 to PA17 I/O Name O I Transmit data Receive data Function Transmit data pins Receive data pins Clock input pins Modem control pins Modem control pins 9-bit general I/O port pins 3-bit general I/O port pins 5-bit general input port pins 20-bit general I/O port pins 1-bit general input port pin 6-bit general I/O port pins 2-bit general input port pins 12-bit general I/O port pins 12-bit general I/O port pins 24-bit general I/O port pins Test clock input pin I/O Serial clock O I Request to send Clear to send I/O General port PB07, PB05, PB04 I/O General port PB06, PB03 to PB00 PC20 to PC01 PC00 I General port I/O General port I General port PD07, PD06, PD03 I/O General port to PD00 PD05, PD04 PE11 to PE00 PF11 to PF00 PG23 to PG00 User debugging interface (H-UDI) TCK TMS TDI TDO TRST Emulator interface ASEMD I General port I/O General port I/O General port I/O General port I I I O I I Test clock Test mode select Test mode selection signal input pin Test data input Test data output Test reset ASE mode Serial input pin for instructions and data Serial output pin for instructions and data Initialization signal input pin Pin to set ASE mode A low-level input on this pin enables ASE mode, and a high-level input enables normal mode. The emulatorspecific functions are available in ASE mode. Test mode TESTMD I Test mode Pin to set test mode. A low-level input on this pin enables test mode. Fix this input pin high. Note: * Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc. Rev. 1.00 Nov. 14, 2007 Page 20 of 1262 REJ09B0437-0100 Section 1 Overview Table 1.4 Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 List of I/O Attributes of Each Pin Function Name PA17/A17 A00 PB04/CE2A/IRQ2/DACK1 PB00/WAIT/SDA PB06/CS4 WE1/DQMLU/WE D09 D12 D15 D05 D02 A16 A13 A10 A07 A04 A01 RAS CAS VssQ PA19/A19 PA18/A18 PB05/CS5/CE1A/IRQ3/TEND1 PB02/CE2B/IRQ0 RD PB07/BS D08 D10 D14 D06 D03 I/O Attribute IO/O O IO/O/I/O I/I/IO I/O O/O/O IO IO IO IO IO O O O O O O I O Power IO/O IO/O IO/O/O/I/O I/O/I O IO/O IO IO IO IO IO Rev. 1.00 Nov. 14, 2007 Page 21 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 Function Name D00 A14 A11 A08 A05 A02 CS3 VSSQ CKE PA22/A22 PA21/A21 PA20/A20 PB03/CS6/CE1B/IRQ1/DREQ1 PB01/IOIS16/SCL CS0 WE0/DQMLL D11 D13 D07 D04 D01 A15 A12 A09 A06 A03 VSSQ RDWR CKIO HIFMD/PA25/A25 PA24/A24 PA23/A23 I/O Attribute IO O O O O O O Power O IO/O IO/O IO/O I/O/O/I/I I/I/IO O O/O IO IO IO IO IO O O O O O Power O IO I/IO/o IO/O IO/O Rev. 1.00 Nov. 14, 2007 Page 22 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18 E19 E20 F1 F2 F3 F4 F17 F18 F19 Function Name VSSQ_14 VSS_07 VCCQ_14 VCC_07 VSSQ_13 VCCQ_13 VCCQ_12 VSSQ VSSQ _12 VCC_06 VSS_06 VCCQ_11 VSSsQ_11 VSSQ_10 WE3/DQMUU/ICIOWR WE2/DQMUL/ICIORD D25 PC18/LNKSTA PC19/EXOUT PC20/WOL VSSQ_00 VSSQ_09 D24 D26 D28 PC13/TX_CLK PC16/MDIO PC17/MDC VCCQ_00 VCCQ_10 D27 D29 I/O Attribute Power Power Power Power Power Power Power Power Power Power Power Power Power Power O/O/O O/O/O IO IO/O IO/O IO/O Power Power IO IO IO IO/I IO/IO IO/I Power Power IO IO Rev. 1.00 Nov. 14, 2007 Page 23 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number F20 G1 G2 G3 G4 G16 G17 G18 G19 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J17 J18 J19 J20 K1 K2 K3 K4 K17 K18 K19 Function Name D30 PC07/MII_TXD3 PC11/TX_ER PC12/TX_EN VSS_00 VCCQ_09 D31 D23 D22 PC04/MII_TXD0 PC05/MILL_TXD1 PC06/MII_TXD2 VCC_00 VCCQ_08 VCCQ_07 D21 D20 PC10/RX_CLK PC14/COL PC15/CRS VSSQ_01 VSSQ_08 VSSQ_07 D19 D18 PC03/MII_RXD3 PC08/RX_DV PC09/RX_ER VCCQ_01 VCC_05 VSSQ D17 I/O Attribute IO IO/O IO/O IO/O Power Power IO IO IO IO/O IO/O IO/O Power Power Power IO IO IO/I IO/I IO/I Power Power Power IO IO IO/I IO/I IO/I Power Power Power IO Rev. 1.00 Nov. 14, 2007 Page 24 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number K20 L1 L2 L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4 P17 P18 P19 Function Name D16 PC00/MII_RXD0 PC01/MII_RXD1 PC02/MII_RXD2 VCCQ_02 VSS_05 PF05/ST0_D5/RTS0 PF06/ST0_D6/SSIDATA0 PF07/ST0_D7/SSIWS0 TESTMD ASEMD PD07/IRQ7/SDCLK VSSQ VSSQ PF02/ST0_D2/RxD0 PF03/ST0_D3/SCK0 PF04/ST0_D4/CTS0 PD04/IRQ4/SDWP PD05/IRQ5/SDCD PD06/IRQ6/SDCMD VSSQ_02 VCCQ_06 PF01/ST0_D1/TxD0 PF10/ST0_SYC/DACK0 PF00/ST0_D0 PD01/IRQ1/SDDAT1 PD02/IRQ2/SDDAT2 PD03/IRQ3/SDDAT3 VCC_01 VSSQ_06 PF11/ST0_PWM/TEND0 PF08/ST0_REQ I/O Attribute IO I/I IO/I IO/I Power Power IO/IO/IO IO/IO/IO IO/IO/IO I I IO/I/O Power Power IO/IO/I IO/IO/IO IO/IO/IO I/I/I I/I/I IO/I/IO Power Power IO/IO/O IO/O/O IO/IO IO/I/I IO/I/IO IO/I/IO Power Power IO/O/O IO/IO Rev. 1.00 Nov. 14, 2007 Page 25 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 Function Name PF09_ST0_VLD/DREQ0 PG14/HIFD14 PG15/HIFD15 PD00/IRQ0/SDDAT0 VCC_02 VCC_04 WDTOVF ST0_CLKIN/SSISCK0 ST0_VCO_CLKIN PG11/HIFD11 PG12/HIFD12 PG13/HIFD13 VSS_01 VSS_04 VSSQ MD_BW ASEBRK/ASEBRKAK PG09/HIFD09 PG10/HIFD10 VSSQ VSS_02 VSSQ_03 VCCQ_03 VSSQ DG12 DV12 UV12 AV12 VCC_03 VSS_03 VCCQ_04 VCCQ_05 I/O Attribute IO/IO/I IO/IO IO/IO IO/I/IO Power Power O I/IO I IO/IO IO/IO IO/IO Power Power Power I I/O IO/IO IO/IO Power Power Power Power Power Power Power Power Power Power Power Power Power Rev. 1.00 Nov. 14, 2007 Page 26 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 Function Name VSSQ_04 VSSQ _05 MD_CK1 NMI VCC (PLL) PG07/HIFD07 VSSQ PG04/HIFD04 PG01/HIFD01 PG22/HIFRS PG17/HIFRDY VSSQ VSSQ VSSQ UG12 AG12 PE07/ST1_D7/SSIWS1 PE06/ST1_D6/SSIDATA1 PE01/ST1_D1/TxD1 PE03/ST1_D3/SCK1 ST1_VCO_CLKIN/AUDIO_CLK TCK TDI MD_CK0 EXTAL VSSQ PG06/HIFD06 PG03/HIFD03 PG00/HIFD00 PG21/HIFWR PG18/HIFDREQ PG16/HIFEBL I/O Attribute Power Power I I Power IO/IO Power IO/IO IO/IO IO/I IO/O Power Power Power Power Power IO/IO/IO IO/IO/IO IO/IO/O IO/O/IO I/I I I I I Power IO/IO IO/IO IO/IO IO/I IO/O IO/I Rev. 1.00 Nov. 14, 2007 Page 27 of 1262 REJ09B0437-0100 Section 1 Overview Pin Number W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Function Name DG33 VBUS AG33 VSSQ USB_X1 PE05/ST1_D5/RTS1 PE02/ST1_D2/RxD1 PE10/ST1_SYC/CTS2 PE11/ST1_PWM/RTS2 ST1_CLKIN/SSISCK1 RES TDO XTAL PG08/HIFD08 PG05/HIFD05 PG02/HIFD02 PG23/HIFCS PG20/HIFRD PG19/HIFINT DV33 DM DP AV33 REFRIN USB_X2 PE04/ST1_D4/CTS1 PE09/ST1_VLD/SCK2 PE00/ST1_D0/RxD2 PE08/ST1_REQ/TxD2 ST_CLKOUT TRST TMS VSS (PLL) I/O Attribute Power I Power Power I IO/IO/IO IO/IO/I IO/IO/IO IO/O/IO I/IO I O O IO/IO IO/IO IO/IO I/I IO/I IO/O Power IO IO Power I O IO/IO/IO IO/IO/IO IO/IO/I IO/IO/O O I I Power Rev. 1.00 Nov. 14, 2007 Page 28 of 1262 REJ09B0437-0100 Section 2 CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 to R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and restoring the status register (SR) and program counter (PC) in exception handling is accomplished by referencing the stack using R15. 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0 Notes: 1. R0 functions as an index register in the indexed register indirect addressing mode and indexed GBR indirect addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers Rev. 1.00 Nov. 14, 2007 Page 29 of 1262 REJ09B0437-0100 Section 2 CPU 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction processing states. The global base register functions as a base address for the GBR indirect addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception handling vector area (including interrupts). The jump table base register functions as the base address of the function table area. 31 14 13 BO CS 9876543210 MQ I[3:0] ST Status register (SR) 31 GBR 0 Global base register (GBR) 0 VBR 31 Vector base register (VBR) 0 31 TBR Jump table base register (TBR) Figure 2.2 Control Registers (1) Status Register (SR) Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 BO 13 CS 12 - 11 - 10 - 9 M 8 Q 7 6 I[3:0] 5 4 3 - 2 - 1 S 0 T Initial value: R/W: 0 R 0 R/W 0 R/W 0 R 0 R 0 R R/W R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R 0 R R/W R/W Rev. 1.00 Nov. 14, 2007 Page 30 of 1262 REJ09B0437-0100 Section 2 CPU Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 15 — 14 13 BO CS 0 0 R/W R/W BO Bit Indicates that a register bank has overflowed. CS Bit Indicates that, in CLIP instruction execution, the value has exceeded the saturation upper-limit value or fallen below the saturation lower-limit value. 12 to 10 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 7 to 4 3, 2 M Q I[3:0] — — — 1111 All 0 R/W R/W R/W R M Bit Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Reserved These bits are always read as 0. The write value should always be 0. 1 S — R/W S Bit Specifies a saturation operation for a MAC instruction. 0 T — R/W T Bit True/false condition or carry/borrow bit (2) Global Base Register (GBR) GBR is referenced as the base address in a GBR-referencing MOV instruction. (3) Vector Base Register (VBR) VBR is referenced as the branch destination base address in the event of an exception or an interrupt. (4) Jump Table Base Register (TBR) TBR is referenced as the start address of a function table located in memory in a JSR/N@@(disp8,TBR) table-referencing subroutine call instruction. Rev. 1.00 Nov. 14, 2007 Page 31 of 1262 REJ09B0437-0100 Section 2 CPU 2.1.3 System Registers The system registers consist of four 32-bit registers: the high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH and MACL store the results of multiply or multiply and accumulate operations. PR stores the return address from a subroutine procedure. PC indicates the program address being executed and controls the flow of the processing. 31 MACH MACL 31 PR 0 0 Multiply and accumulate register high (MACH) and multiply and accumulate register low (MACL): Store the results of multiply or multiply and accumulate operations. Procedure register (PR): Stores the return address from a subroutine procedure. 31 PC 0 Program counter (PC): Indicates the four bytes ahead of the current instruction. Figure 2.3 System Registers (1) Multiply and Accumulate Register High (MACH) and Multiply and Accumulate Register Low (MACL) MACH and MACL are used as the addition value in a MAC instruction, and store the result of a MAC or MUL instruction. (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC indicates the address of the instruction being executed. Rev. 1.00 Nov. 14, 2007 Page 32 of 1262 REJ09B0437-0100 Section 2 CPU 2.1.4 Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 6.8, Register Banks. 2.1.5 Initial Values of Registers Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers Register R0 to R14 R15 (SP) Control registers SR Initial Value Undefined Value of the stack pointer in the vector address table Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Classification General registers GBR, TBR VBR System registers MACH, MACL, PR PC Rev. 1.00 Nov. 14, 2007 Page 33 of 1262 REJ09B0437-0100 Section 2 CPU 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 Longword 0 Figure 2.4 Data Format in Registers 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit bytes, 16-bit words, or 32-bit longwords. A memory operand of fewer than 32 bits is stored in a register in sign-extended or zero-extended form. A word operand should be accessed at a word boundary (an even address of multiple of two bytes: address 2n), and a longword operand at a longword boundary (an even address of multiple of four bytes: address 4n). Otherwise, an address error will occur. A byte operand can be accessed at any address. Only big-endian byte order can be selected for the data format. Data formats in memory are shown in figure 2.5. Address m + 1 Address m Address m + 3 Address m + 2 31 Byte Address 2n Address 4n 23 Byte Word 15 Byte 7 Byte Word 0 Longword Big endian Figure 2.5 Data Formats in Memory Rev. 1.00 Nov. 14, 2007 Page 34 of 1262 REJ09B0437-0100 Section 2 CPU 2.2.3 Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. 20-bit immediate data is located in the code of a MOVI20 or MOVI20S 32-bit transfer instruction. The MOVI20 instruction stores immediate data in the destination register in sign-extended form. The MOVI20S instruction shifts immediate data by eight bits in the upper direction, and stores it in the destination register in sign-extended form. Word or longword immediate data is not located in the instruction code, but rather is stored in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. See examples given in section 2.3.1 (10), Immediate Data. Rev. 1.00 Nov. 14, 2007 Page 35 of 1262 REJ09B0437-0100 Section 2 CPU 2.3 2.3.1 Instruction Features RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions The SH-2A additionally features 32-bit fixed-length instructions, improving performance and ease of use. (3) One Instruction per State Each basic instruction can be executed in one cycle using the pipeline system. (4) Data Length Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data in memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It is also handled as longword data. Table 2.2 SH2-A CPU MOV.W ADD Sign Extension of Word Data Description @(disp,PC),R1 Data is sign-extended to 32 bits, and R1 becomes R1,R0 H'00001234. It is next ......... operated upon by an ADD instruction. H'1234 Example of Other CPU ADD.W #H'1234,R0 .DATA.W Note: @(disp, PC) accesses the immediate data. (5) Load-Store Architecture Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Rev. 1.00 Nov. 14, 2007 Page 36 of 1262 REJ09B0437-0100 Section 2 CPU (6) Delayed Branch Instructions With the exception of some instructions, unconditional branch instructions, etc., are executed as delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction immediately following the delayed branch instruction. This reduces disturbance of the pipeline control when a branch is taken. In a delayed branch, the actual branch operation occurs after execution of the slot instruction. However, instruction execution such as register updating excluding the actual branch operation, is performed in the order of delayed branch instruction → delay slot instruction. For example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. Table 2.3 SH-2A CPU BRA ADD TRGET R1,R0 Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Other CPU ADD.W BRA R1,R0 TRGET (7) Unconditional Branch Instructions with No Delay Slot The SH-2A additionally features unconditional branch instructions in which a delay slot instruction is not executed. This eliminates unnecessary NOP instructions, and so reduces the code size. (8) Multiply/Multiply-and-Accumulate Operations 16-bit × 16-bit → 32-bit multiply operations are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-bit + 64-bit → 64-bit multiply-and-accumulate operations are executed in two to four cycles. (9) T Bit The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Rev. 1.00 Nov. 14, 2007 Page 37 of 1262 REJ09B0437-0100 Section 2 CPU Table 2.4 SH-2A CPU CMP/GE BT BF ADD CMP/EQ BT T Bit Description R1,R0 TRGET0 TRGET1 #−1,R0 #0,R0 TRGET T bit is set when R0 ≥ R1. The program branches to TRGET0 when R0 ≥ R1 and to TRGET1 when R0 < R1. T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. Example of Other CPU CMP.W BGE BLT SUB.W BEQ R1,R0 TRGET0 TRGET1 #1,R0 TRGET (10) Immediate Data Byte immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. The memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative addressing mode with displacement. With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for 21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a register. Table 2.5 Immediate Data Accessing SH-2A CPU MOV MOVI20 MOVI20 MOVI20S OR 32-bit immediate MOV.L #H'12,R0 #H'1234,R0 #H'12345,R0 #H'12345,R0 #H'67,R0 @(disp,PC),R0 ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. MOV.L #H'12345678,R0 Example of Other CPU MOV.B MOV.W MOV.L MOV.L #H'12,R0 #H'1234,R0 #H'12345,R0 #H'1234567,R0 Classification 8-bit immediate 16-bit immediate 20-bit immediate 28-bit immediate Rev. 1.00 Nov. 14, 2007 Page 38 of 1262 REJ09B0437-0100 Section 2 CPU (11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in register indirect addressing mode. With the SH-2A, when data is referenced using an absolute address not exceeding 28 bits, it is also possible to transfer immediate data located in the instruction code to a register and to reference the data in register indirect addressing mode. However, when referencing data using an absolute address of 21 to 28 bits, an OR instruction must be used after the data is transferred to a register. Table 2.6 Absolute Address Accessing SH-2A CPU MOVI20 MOV.B 21 to 28 bits MOVI20S OR MOV.B 29 bits or more MOV.L MOV.B #H'12345,R1 @R1,R0 #H'12345,R1 #H'67,R1 @R1,R0 @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 MOV.B @H'12345678,R0 MOV.B @H'1234567,R0 Example of Other CPU MOV.B @H'12345,R0 Classification Up to 20 bits (12) 16-Bit/32-Bit Displacement When data is accessed by 16-bit or 32-bit displacement, the displacement value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indexed indirect register addressing mode. Table 2.7 Displacement Accessing SH-2A CPU MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Example of Other CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement Rev. 1.00 Nov. 14, 2007 Page 39 of 1262 REJ09B0437-0100 Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Mode Register direct Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Rn The effective address is register Rn. (The operand is the contents of register Rn.) Equation — Register indirect @Rn The effective address is the contents of register Rn. Rn Rn Rn Register indirect @Rn+ with postincrement The effective address is the contents of register Rn. A constant is added to the contents of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn (After instruction execution) Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Rn Register indirect @-Rn with predecrement The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn – 1/2/4 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction is executed with Rn after this calculation) – Rn – 1/2/4 1/2/4 Rev. 1.00 Nov. 14, 2007 Page 40 of 1262 REJ09B0437-0100 Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation The effective address is the sum of Rn and a 4-bit displacement (disp). The value of disp is zeroextended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn Equation Register indirect @(disp:4, with Rn) displacement Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 disp (zero-extended) × 1/2/4 + Rn + disp × 1/2/4 Register indirect @(disp:12, The effective address is the sum of Rn and a 12with Rn) bit displacement displacement (disp). The value of disp is zeroextended. Rn + disp (zero-extended) Rn + disp Byte: Rn + disp Word: Rn + disp Longword: Rn + disp Indexed register @(R0,Rn) indirect The effective address is the sum of Rn and R0. Rn + Rn + R0 Rn + R0 R0 GBR indirect with displacement @(disp:8, GBR) The effective address is the sum of GBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR Byte: GBR + disp Word: GBR + disp × 2 Longword: GBR + disp × 4 disp (zero-extended) × 1/2/4 + GBR + disp × 1/2/4 Rev. 1.00 Nov. 14, 2007 Page 41 of 1262 REJ09B0437-0100 Section 2 CPU Addressing Mode Indexed GBR indirect Instruction Format Effective Address Calculation Equation GBR + R0 @(R0, GBR) The effective address is the sum of GBR value and R0. GBR + GBR + R0 R0 TBR duplicate indirect with displacement @@ (disp:8, TBR) The effective address is the sum of TBR value and an 8-bit displacement (disp). The value of disp is zero-extended, and is multiplied by 4. TBR disp (zero-extended) Contents of address (TBR + disp × 4) + TBR + disp × 4 × (TBR 4 + disp × 4) PC indirect with @(disp:8, displacement PC) The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & (for longword) Word: PC + disp × 2 Longword: PC & H'FFFFFFFC + disp × 4 H'FFFFFFFC disp (zero-extended) × + PC + disp × 2 or PC & H'FFFFFFFC + disp × 4 2/4 Rev. 1.00 Nov. 14, 2007 Page 42 of 1262 REJ09B0437-0100 Section 2 CPU Addressing Mode PC relative Instruction Format Effective Address Calculation disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). PC Equation PC + disp × 2 disp (sign-extended) × 2 + PC + disp × 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC PC + disp × 2 disp (sign-extended) × 2 + PC + disp × 2 Rn The effective address is the sum of PC value and Rn. PC + PC + Rn PC + Rn Rn Rev. 1.00 Nov. 14, 2007 Page 43 of 1262 REJ09B0437-0100 Section 2 CPU Addressing Mode Immediate Instruction Format Effective Address Calculation #imm:20 The 20-bit immediate data (imm) for the MOVI20 instruction is sign-extended. 31 19 0 Signextended imm (20 bits) Equation — The 20-bit immediate data (imm) for the MOVI20S — instruction is shifted by eight bits to the left, the upper bits are sign-extended, and the lower bits are padded with zero. 31 27 8 0 imm (20 bits) 00000000 Sign-extended #imm:8 #imm:8 #imm:8 #imm:3 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. — — — The 3-bit immediate data (imm) for the BAND, BOR, — BXOR, BST, BLD, BSET, and BCLR instructions indicates the target bit location. Rev. 1.00 Nov. 14, 2007 Page 44 of 1262 REJ09B0437-0100 Section 2 CPU 2.3.3 Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • • • • • xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Instruction Formats Source Operand — 0 xxxx xxxx xxxx xxxx Table 2.9 Instruction Formats 0 format 15 Destination Operand — Example NOP n format 15 xxxx 0 nnnn xxxx xxxx — Control register or system register nnnn: Register direct nnnn: Register direct MOVT STS DIVU Rn MACH,Rn R0,Rn R0 (Register direct) nnnn: Register direct Control register or system register mmmm: Register direct R15 (Register indirect with postincrement) nnnn: Register indirect with predecrement R15 (Register indirect with predecrement) nnnn: Register direct STC.L SR,@-Rn MOVMU.L Rm,@-R15 MOVMU.L @R15+,Rn MOV.L R0,@Rn+ R0 (Register direct) nnnn: (Register indirect with postincrement) Rev. 1.00 Nov. 14, 2007 Page 45 of 1262 REJ09B0437-0100 Section 2 CPU Instruction Formats m format 15 xxxx mmmm xxxx xxxx 0 Source Operand mmmm: Register direct mmmm: Register indirect with postincrement mmmm: Register indirect mmmm: Register indirect with predecrement Destination Operand Control register or system register Control register or system register — Example LDC Rm,SR LDC.L @Rm+,SR JMP @Rm R0 (Register direct) MOV.L @-Rm,R0 mmmm: PC relative — using Rm nm format 15 xxxx nnnn mmmm xxxx 0 BRAF ADD Rm Rm,Rn mmmm: Register direct mmmm: Register direct nnnn: Register direct nnnn: Register indirect MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: Register MACH, MACL indirect with postincrement (multiplyand-accumulate) nnnn*: Register indirect with postincrement (multiplyand-accumulate) mmmm: Register indirect with postincrement mmmm: Register direct mmmm: Register direct md format 15 xxxx xxxx mmmm dddd 0 nnnn: Register direct nnnn: Register indirect with predecrement nnnn: Indexed register indirect MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) mmmmdddd: Register indirect with displacement R0 (Register direct) MOV.B @(disp,Rm),R0 Rev. 1.00 Nov. 14, 2007 Page 46 of 1262 REJ09B0437-0100 Section 2 CPU Instruction Formats nd4 format 15 xxxx xxxx nnnn dddd 0 Source Operand Destination Operand Example MOV.B R0,@(disp,Rn) R0 (Register direct) nnnndddd: Register indirect with displacement mmmm: Register direct mmmmdddd: Register indirect with displacement nmd format 15 xxxx nnnn mmmm dddd 0 nnnndddd: Register MOV.L indirect with Rm,@(disp,Rn) displacement nnnn: Register direct MOV.L @(disp,Rm),Rn nmd12 format 32 xxxx 15 xxxx 16 nnnn mmmm xxxx 0 dddd dddd dddd mmmm: Register direct mmmmdddd: Register indirect with displacement dddddddd: GBR indirect with displacement nnnndddd: Register MOV.L indirect with Rm,@(disp12,Rn) displacement nnnn: Register direct MOV.L @(disp12,Rm),Rn d format 15 xxxx xxxx dddd dddd 0 R0 (Register direct) MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR) R0 (Register direct) dddddddd: GBR indirect with displacement dddddddd: PC relative with displacement dddddddd: TBR duplicate indirect with displacement dddddddd: PC relative d12 format 15 xxxx dddd dddd dddd 0 R0 (Register direct) MOVA @(disp,PC),R0 — JSR/N @@(disp8,TBR) BF BRA label label — dddddddddddd: PC — relative dddddddd: PC relative with displacement nnnn: Register direct (label = disp + PC) MOV.L @(disp,PC),Rn nd8 format 15 xxxx nnnn dddd dddd 0 Rev. 1.00 Nov. 14, 2007 Page 47 of 1262 REJ09B0437-0100 Section 2 CPU Instruction Formats i format 15 xxxx xxxx iiii 0 iiii Source Operand iiiiiiii: Immediate iiiiiiii: Immediate iiiiiiii: Immediate Destination Operand Indexed GBR indirect R0 (Register direct) — Example AND.B #imm,@(R0,GBR) AND TRAPA #imm,R0 #imm #imm,Rn ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: Immediate nnnn: Register direct ADD ni3 format 15 xxxx xxxx nnnn x iii 0 nnnn: Register direct — iii: Immediate — BLD #imm3,Rn #imm3,Rn nnnn: Register direct BST iii: Immediate ni20 format 32 xxxx 15 iiii 16 nnnn iiii xxxx 0 iiii iiii iiii iiiiiiiiiiiiiiiiiiii: Immediate nnnn: Register direct MOVI20 #imm20, Rn nid format 32 xxxx 15 xxxx 16 nnnn xiii xxxx 0 dddd dddd dddd nnnndddddddddddd: — Register indirect with displacement iii: Immediate — BLD.B #imm3,@(disp12,Rn ) nnnndddddddddddd: BST.B Register indirect with #imm3,@(disp12,Rn displacement ) iii: Immediate Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 1.00 Nov. 14, 2007 Page 48 of 1262 REJ09B0437-0100 Section 2 CPU 2.4 2.4.1 Instruction Set Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Classification Types Data transfer 13 Operation Code Function MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer Reverse stack transfer MOVA MOVI20 MOVI20S MOVML MOVMU MOVRT MOVT MOVU NOTT PREF SWAP XTRCT Effective address transfer 20-bit immediate data transfer 20-bit immediate data transfer 8-bit left-shit R0–Rn register save/restore Rn–R14 and PR register save/restore T bit inversion and transfer to Rn T bit transfer Unsigned data transfer T bit inversion Prefetch to operand cache Swap of upper and lower bytes Extraction of the middle of registers connected No. of Instructions 62 Rev. 1.00 Nov. 14, 2007 Page 49 of 1262 REJ09B0437-0100 Section 2 CPU Classification Types Arithmetic operations 26 Operation Code Function ADD ADDC ADDV Binary addition Binary addition with carry Binary addition with overflow check No. of Instructions 40 CMP/cond Comparison CLIPS CLIPU DIVS DIVU DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULR MULS MULU NEG NEGC SUB SUBC SUBV Signed saturation value comparison Unsigned saturation value comparison Signed division (32 ÷ 32) Unsigned division (32 ÷ 32) One-step division Initialization of signed one-step division Initialization of unsigned one-step division Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-precision multiply-and-accumulate operation Double-precision multiply operation Signed multiplication with result storage in Rn Signed multiplication Unsigned multiplication Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Rev. 1.00 Nov. 14, 2007 Page 50 of 1262 REJ09B0437-0100 Section 2 CPU Classification Types Logic operations 6 Operation Code Function AND NOT OR TAS TST XOR Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit Dynamic arithmetic shift One-bit arithmetic left shift One-bit arithmetic right shift Dynamic logical shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift No. of Instructions 14 Shift 12 ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn 16 Branch 10 BF BT BRA BRAF BSR BSRF JMP JSR RTS RTV/N Conditional branch, conditional delayed branch 15 (branch when T = 0) Conditional branch, conditional delayed branch (branch when T = 1) Unconditional delayed branch Unconditional delayed branch Delayed branch to subroutine procedure Delayed branch to subroutine procedure Unconditional delayed branch Branch to subroutine procedure Delayed branch to subroutine procedure Return from subroutine procedure Delayed return from subroutine procedure Return from subroutine procedure with Rm → R0 transfer Rev. 1.00 Nov. 14, 2007 Page 51 of 1262 REJ09B0437-0100 Section 2 CPU Classification Types System control 14 Operation Code Function CLRT CLRMAC LDBANK LDC LDS NOP T bit clear MAC register clear Register restoration from specified register bank entry Load to control register Load to system register No operation No. of Instructions 36 RESBANK Register restoration from register bank RTE SETT SLEEP STBANK STC STS TRAPA Floating-point 19 instructions FABS FADD FCMP FCNVDS FCNVSD FDIV FLDI0 FLDI1 FLDS FLOAT FMAC FMOV FMUL FNEG Return from exception handling T bit set Transition to power-down mode Register save to specified register bank entry Store control register data Store system register data Trap exception handling Floating-point absolute value Floating-point addition Floating-point comparison Conversion from double-precision to singleprecision Conversion from single-precision to double precision Floating-point division Floating-point load immediate 0 Floating-point load immediate 1 Floating-point load into system register FPUL Conversion from integer to floating-point Floating-point multiply and accumulate operation Floating-point data transfer Floating-point multiplication Floating-point sign inversion 48 Rev. 1.00 Nov. 14, 2007 Page 52 of 1262 REJ09B0437-0100 Section 2 CPU Classification Types Floating-point 19 instructions Operation Code Function FSCHG FSQRT FSTS FSUB FTRC SZ bit inversion Floating-point square root Floating-point store from system register FPUL Floating-point subtraction Floating-point conversion with rounding to integer Load into floating-point system register Store from floating-point system register Bit AND Bit clear Bit load Bit OR Bit set Bit store Bit exclusive OR No. of Instructions 48 FPU-related CPU instructions Bit manipulation 2 LDS STS 8 10 BAND BCLR BLD BOR BSET BST BXOR 14 BANDNOT Bit NOT AND BORNOT BLDNOT Total: 112 Bit NOT OR Bit NOT load 253 Rev. 1.00 Nov. 14, 2007 Page 53 of 1262 REJ09B0437-0100 Section 2 CPU The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Instruction Indicated by mnemonic. Instruction Code Indicated in MSB ↔ LSB order. Operation Indicates summary of operation. Execution States Value when no wait states are inserted.*1 T Bit Value of T bit after instruction is executed. Explanation of Symbols —: No change [Legend] Rm: Rn: Source register Destination register [Legend] mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ......... 1111: R15 iiii: dddd: Immediate data Displacement [Legend] →, ←: (xx): Transfer direction Memory operand imm: Immediate data disp: Displacement*2 M/Q/T: Flag bits in SR &: |: ^: ~: Logical AND of each bit Logical OR of each bit Exclusive logical OR of each bit Logical NOT of each bit n: n-bit right shift Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states will be increased in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory → register) is the same as the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details, refer to the SH-2A, SH2A-FPU Software Manual. Rev. 1.00 Nov. 14, 2007 Page 54 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.2 Data Transfer Instructions Table 2.11 Data Transfer Instructions Execution Instruction MOV MOV.W #imm,Rn @(disp,PC),Rn Instruction Code Operation Cycles 1 1 Compatibility SH2, T Bit SH2E SH4   Yes Yes Yes Yes SH-2A Yes Yes 1110nnnniiiiiiii imm → sign extension → Rn 1001nnnndddddddd (disp × 2 + PC) → sign extension → Rn MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn 1101nnnndddddddd (disp × 4 + PC) → Rn 0110nnnnmmmm0011 Rm → Rn 0010nnnnmmmm0000 Rm → (Rn) 0010nnnnmmmm0001 Rm → (Rn) 0010nnnnmmmm0010 Rm → (Rn) 0110nnnnmmmm0000 (Rm) → sign extension → Rn 0110nnnnmmmm0001 (Rm) → sign extension → Rn 0110nnnnmmmm0010 (Rm) → Rn 0010nnnnmmmm0100 Rn-1 → Rn, Rm → (Rn) 0010nnnnmmmm0101 Rn-2 → Rn, Rm → (Rn) 0010nnnnmmmm0110 Rn-4 → Rn, Rm → (Rn) 1 1 1 1 1 1 1 1 1 1 1             Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 0110nnnnmmmm0100 (Rm) → sign extension → Rn, 1 Rm + 1 → Rm MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) → sign extension → Rn, 1 Rm + 2 → Rm  Yes Yes Yes MOV.L MOV.B MOV.W MOV.L MOV.B @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 0110nnnnmmmm0110 (Rm) → Rn, Rm + 4 → Rm 10000000nnnndddd R0 → (disp + Rn) 10000001nnnndddd R0 → (disp × 2 + Rn) 0001nnnnmmmmdddd Rm → (disp × 4 + Rn) 10000100mmmmdddd (disp + Rm) → sign extension → R0 1 1 1 1 1      Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp × 2 + Rm) → sign extension → R0 1  Yes Yes Yes MOV.L MOV.B MOV.W @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) 0101nnnnmmmmdddd (disp × 4 + Rm) → Rn 0000nnnnmmmm0100 Rm → (R0 + Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) 1 1 1    Yes Yes Yes Yes Yes Yes Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 55 of 1262 REJ09B0437-0100 Section 2 CPU Execution Instruction MOV.L MOV.B Rm,@(R0,Rn) @(R0,Rm),Rn Instruction Code Operation Cycles 1 1 Compatibility SH2, T Bit SH2E SH4   Yes Yes Yes Yes SH-2A Yes Yes 0000nnnnmmmm0110 Rm → (R0 + Rn) 0000nnnnmmmm1100 (R0 + Rm) → sign extension → Rn MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → sign extension → Rn 1  Yes Yes Yes MOV.L MOV.B MOV.W MOV.L MOV.B @(R0,Rm),Rn R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 0000nnnnmmmm1110 (R0 + Rm) → Rn 11000000dddddddd R0 → (disp + GBR) 11000001dddddddd R0 → (disp × 2 + GBR) 11000010dddddddd R0 → (disp × 4 + GBR) 11000100dddddddd (disp + GBR) → sign extension → R0 1 1 1 1 1      Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MOV.W @(disp,GBR),R0 11000101dddddddd (disp × 2 + GBR) → sign extension → R0 1  Yes Yes Yes MOV.L MOV.B MOV.W MOV.L MOV.B @(disp,GBR),R0 R0,@Rn+ R0,@Rn+ R0,@Rn+ @-Rm,R0 11000110dddddddd (disp × 4 + GBR) → R0 0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn 0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn 0100nnnn10101011 R0 → Rn), Rn + 4 → Rn 0100mmmm11001011 Rm-1 → Rm, (Rm) → sign extension → R0 1 1 1 1 1      Yes Yes Yes Yes Yes Yes Yes MOV.W @-Rm,R0 0100mmmm11011011 Rm-2 → Rm, (Rm) → sign extension → R0 1  Yes MOV.L MOV.B @-Rm,R0 0100mmmm11101011 Rm-4 → Rm, (Rm) → R0 1 1   Yes Yes Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp + Rn) 0000dddddddddddd MOV.W Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp × 2 + Rn) 0001dddddddddddd 1  Yes MOV.L Rm,@(disp12,Rn) 0011nnnnmmmm0001 Rm → (disp × 4 + Rn) 0010dddddddddddd 1  Yes MOV.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) → 0100dddddddddddd sign extension → Rn 1  Yes MOV.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp × 2 + Rm) → 0101dddddddddddd sign extension → Rn 1  Yes Rev. 1.00 Nov. 14, 2007 Page 56 of 1262 REJ09B0437-0100 Section 2 CPU Execution Instruction MOV.L Instruction Code Operation Cycles 1 Compatibility SH2, T Bit SH2E SH4  SH-2A Yes @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp × 4 + Rm) → Rn 0110dddddddddddd MOVA MOVI20 @(disp,PC),R0 #imm20,Rn 11000111dddddddd disp × 4 + PC → R0 0000nnnniiii0000 imm → sign extension → Rn iiiiiiiiiiiiiiii 1 1   Yes Yes Yes Yes MOVI20S #imm20,Rn 0000nnnniiii0001 imm Rm (unsigned), 1→T Otherwise, 0 → T CMP/GT Rm,Rn 0011nnnnmmmm0111 When Rn > Rm (signed), 1→T Otherwise, 0 → T CMP/PL Rn 0100nnnn00010101 When Rn > 0, 1 → T Otherwise, 0 → T 1 1 1 1 1 Comparison result Comparison result Comparison result Comparison result Comparison result CMP/PZ Rn 0100nnnn00010001 When Rn ≥ 0, 1 → T Otherwise, 0 → T 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 When any bytes are equal, 1→T Otherwise, 0 → T 1 Comparison result Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Compatibility SH2, SH2E SH4 Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Rn + Rm + T → Rn, carry → T 1 Rn + Rm → Rn, overflow → T 1 Rev. 1.00 Nov. 14, 2007 Page 59 of 1262 REJ09B0437-0100 Section 2 CPU Execution Instruction CLIPS.B Rn Instruction Code 0100nnnn10010001 Operation When Rn > (H'0000007F), (H'0000007F) → Rn, 1 → CS when Rn < (H'FFFFFF80), (H'FFFFFF80) → Rn, 1 → CS CLIPS.W Rn 0100nnnn10010101 When Rn > (H'00007FFF), (H'00007FFF) → Rn, 1 → CS When Rn < (H'FFFF8000), (H'FFFF8000) → Rn, 1 → CS CLIPU.B Rn 0100nnnn10000001 When Rn > (H'000000FF), (H'000000FF) → Rn, 1 → CS CLIPU.W Rn 0100nnnn10000101 When Rn > (H'0000FFFF), (H'0000FFFF) → Rn, 1 → CS DIV1 Rm,Rn 0011nnnnmmmm0100 1-step division (Rn ÷ Rm) 1 Calculation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm → M, M ^ Q → T 1 Calculation result DIV0U DIVS R0,Rn 0000000000011001 0100nnnn10010100 0 → M/Q/T Signed operation of Rn ÷ R0 → Rn 32 ÷ 32 → 32 bits DIVU R0,Rn 0100nnnn10000100 Unsigned operation of Rn ÷ R0 34 → Rn 32 ÷ 32 → 32 bits DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits DT Rn 0100nnnn00010000 Rn – 1 → Rn When Rn is 0, 1 → T When Rn is not 0, 0 → T EXTS.B Rm,Rn 0110nnnnmmmm1110 Byte in Rm is sign-extended → Rn EXTS.W Rm,Rn 0110nnnnmmmm1111 Word in Rm is sign-extended → Rn 1  1 1 2  2   1 36 0  1  1  1  Cycles 1 T Bit  Compatibility SH2, SH2E SH4 SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Compa- Yes rison result  Yes Yes Yes Yes Yes Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 60 of 1262 REJ09B0437-0100 Section 2 CPU Execution Instruction EXTU.B Rm,Rn Instruction Code 0110nnnnmmmm1100 Operation Byte in Rm is zero-extended → Rn EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended → Rn MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → 64 bits MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) × (Rm) + MAC → MAC 16 × 16 + 64 → 64 bits MUL.L Rm,Rn 0000nnnnmmmm0111 Rn × Rm → MACL 32 × 32 → 32 bits MULR R0,Rn 0100nnnn10000000 R0 × Rn → Rn 32 × 32 → 32 bits MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn × Rm → MACL 16 × 16 → 32 bits MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn × Rm → MACL 16 × 16 → 32 bits NEG NEGC SUB SUBC SUBV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000 0011nnnnmmmm1010 0011nnnnmmmm1011 0-Rm → Rn 0-Rm-T → Rn, borrow → T Rn-Rm → Rn Rn-Rm-T → Rn, borrow → T Rn-Rm → Rn, underflow → T 1 1 1 1 1  1  1  2 2  3  4  1  Cycles 1 T Bit  Compatibility SH2, SH2E SH4 SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Borrow Yes  Yes Borrow Yes Overflow Yes Rev. 1.00 Nov. 14, 2007 Page 61 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Execution Instruction AND AND AND.B Rm,Rn #imm,R0 #imm,@(R0,GBR) Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii Operation Rn & Rm → Rn R0 & imm → R0 (R0 + GBR) & imm → (R0 + GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii ~Rm → Rn Rn | Rm → Rn R0 | imm → R0 (R0 + GBR) | imm → (R0 + GBR) TAS.B @Rn 0100nnnn00011011 When (Rn) is 0, 1 → T Otherwise, 0 → T, 1 → MSB of(Rn) TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm When the result is 0, 1 → T Otherwise, 0 → T TST #imm,R0 11001000iiiiiiii R0 & imm When the result is 0, 1 → T Otherwise, 0 → T TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm When the result is 0, 1 → T Otherwise, 0 → T XOR XOR XOR.B Rm,Rn #imm,R0 #imm,@(R0,GBR) 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii Rn ^ Rm → Rn R0 ^ imm → R0 (R0 + GBR) ^ imm → (R0 + GBR) 1 1 3    Yes Yes Yes Yes Yes Yes Yes Yes Yes 3 Test result Yes Yes Yes 1 Test result Yes Yes Yes 1 Test result Yes Yes Yes 3 Test result Yes Yes Yes 1 1 1 3     Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 3 Compatibility SH2, T Bit SH2E SH4    Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 62 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.5 Shift Instructions Table 2.14 Shift Instructions Execution Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Operation T ← Rn ← MSB LSB → Rn → T T ← Rn ← T T → Rn → T When Rm ≥ 0, Rn > |Rm| → [MSB → Rn] SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 T ← Rn ← 0 MSB → Rn → T When Rm ≥ 0, Rn > |Rm| → [0 → Rn] SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16 Rn Rn Rn Rn Rn Rn Rn Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 T ← Rn ← 0 0 → Rn → T Rn > 2 → Rn Rn > 8 → Rn Rn > 16 → Rn 1 1 1 1 1 1 1 1 MSB LSB       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 1 1 MSB LSB  Yes Yes Yes Yes Yes Yes Yes Yes Cycles 1 1 1 1 1 Compatibility SH2, T Bit SH2E SH4 MSB LSB MSB LSB  Yes Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 63 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.6 Branch Instructions Table 2.15 Branch Instructions Execution Instruction BF label Instruction Code 10001011dddddddd Operation When T = 0, disp × 2 + PC → PC, When T = 1, nop BF/S label 10001111dddddddd Delayed branch When T = 0, disp × 2 + PC → PC, When T = 1, nop BT label 10001001dddddddd When T = 1, disp × 2 + PC → PC, When T = 0, nop BT/S label 10001101dddddddd Delayed branch When T = 1, disp × 2 + PC → PC, When T = 0, nop BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC → PC BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC → PC BSR label 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + PC → PC BSRF Rm 0000mmmm00000011 Delayed branch, PC → PR, Rm + PC → PC JMP JSR @Rm @Rm 0100mmmm00101011 0100mmmm00001011 Delayed branch, Rm → PC Delayed branch, PC → PR, Rm → PC JSR/N JSR/N @Rm 0100mmmm01001011 PC-2 → PR, Rm → PC PC-2 → PR, (disp × 4 + TBR) → PC RTS RTS/N RTV/N Rm 0000000000001011 0000000001101011 0000mmmm01111011 Delayed branch, PR → PC PR → PC Rm → R0, PR → PC 2 3 3    Yes Yes Yes Yes Yes 3 5   Yes Yes 2 2   Yes Yes Yes Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2  Yes Yes Yes 2/1*  Yes Yes Yes 3/1*  Yes Yes Yes 2/1*  Yes Yes Yes Cycles 3/1* Compatibility SH2, T Bit SH2E SH4  Yes Yes SH-2A Yes @@(disp8,TBR) 10000011dddddddd Note: * One cycle when the program does not branch. Rev. 1.00 Nov. 14, 2007 Page 64 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.7 System Control Instructions Table 2.16 System Control Instructions Execution Instruction CLRT CLRMAC LDBANK @Rm,R0 Instruction Code 0000000000001000 0000000000101000 0100mmmm11100101 Operation 0→T 0 → MACH,MACL Cycles 1 1 Compatibility SH2, T Bit SH2E SH4 0   Yes Yes Yes Yes SH-2A Yes Yes Yes (Specified register bank entry) 6 → R0 LDC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RESBANK Rm,SR Rm,TBR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR 0100mmmm00001110 0100mmmm01001010 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000001011011 Rm → SR Rm → TBR Rm → GBR Rm → VBR (Rm) → SR, Rm + 4 → Rm (Rm) → GBR, Rm + 4 → Rm (Rm) → VBR, Rm + 4 → Rm Rm → MACH Rm → MACL Rm → PR 3 1 1 1 5 1 1 1 1 1 LSB    LSB           Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (Rm) → MACH, Rm + 4 → Rm 1 (Rm) → MACL, Rm + 4 → Rm 1 (Rm) → PR, Rm + 4 → Rm No operation Bank → R0 to R14, GBR, MACH, MACL, PR 1 1 9* RTE 0000000000101011 Delayed branch, stack area → PC/SR 6  Yes Yes Yes SETT SLEEP STBANK R0,@Rn 0000000000011000 0000000000011011 0100nnnn11100001 1→T Sleep R0 → (specified register bank entry) 1 5 7 1   Yes Yes Yes Yes Yes Yes Yes STC STC SR,Rn TBR,Rn 0000nnnn00000010 0000nnnn01001010 SR → Rn TBR → Rn 2 1   Yes Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 65 of 1262 REJ09B0437-0100 Section 2 CPU Execution Instruction STC STC STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm Instruction Code 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii Operation GBR → Rn VBR → Rn Rn-4 → Rn, SR → (Rn) Rn-4 → Rn, GBR → (Rn) Rn-4 → Rn, VBR → (Rn) MACH → Rn MACL → Rn PR → Rn Rn-4 → Rn, MACH → (Rn) Rn-4 → Rn, MACL → (Rn) Rn-4 → Rn, PR → (Rn) PC/SR → stack area, (imm × 4 + VBR) → PC Cycles 1 1 2 1 1 1 1 1 1 1 1 5 Compatibility SH2, T Bit SH2E SH4             Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SH-2A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In practice, the number of instruction execution states in cases such as the following: a. When there is a conflict between an instruction fetch and a data access b. When the destination register of a load instruction (memory → register) is the same as the register used by the next instruction. * In the event of bank overflow, the number of cycles is 19. Rev. 1.00 Nov. 14, 2007 Page 66 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.8 Floating-Point Operation Instructions Table 2.17 Floating-Point Operation Instructions Compatibility Execution Instruction FABS FABS FADD FADD FRn DRn FRm, FRn DRm, DRn Instruction Code 1111nnnn01011101 1111nnn001011101 1111nnnnmmmm0000 1111nnn0mmm00000 1111nnnnmmmm0100 Operation |FRn| → FRn |DRn| → DRn FRn + FRm → FRn DRn + DRm → DRn (FRn = FRm)? 1:0 → T Cycles T Bit 1 1 1 6 1     Compa- Yes rison result SH-2A/ SH2A- SH2E Yes SH4 Yes Yes FPU Yes Yes Yes Yes Yes Yes Yes Yes Yes FCMP/EQ FRm, FRn FCMP/EQ DRm, DRn 1111nnn0mmm00100 (DRn = DRm)? 1:0 → T 2 Comparison result Yes Yes FCMP/GT FRm, FRn 1111nnnnmmmm0101 (FRn > FRm)? 1:0 → T 1 Compa -rison result Yes Yes Yes FCMP/GT DRm, DRn 1111nnn0mmm00101 (DRn > DRm)? 1:0 → T 2 Comparison result Yes Yes FCNVDS FCNVSD FDIV FDIV FLDI0 FLDI1 FLDS FLOAT FLOAT FMAC DRm, FPUL FPUL, DRn FRm, FRn DRm, DRn FRn FRn FRm, FPUL FPUL,FRn FPUL,DRn FR0,FRm,FRn 1111mmm010111101 1111nnn010101101 1111nnnnmmmm0011 1111nnn0mmm00011 1111nnnn10001101 1111nnnn10011101 1111mmmm00011101 1111nnnn00101101 1111nnn000101101 1111nnnnmmmm1110 (float) DRm → FPUL (double) FPUL → DRn FRn/FRm → FRn DRn/DRm → DRn 0 × 00000000 → FRn 0 × 3F800000 → FRn FRm → FPUL (float)FPUL → FRn (double)FPUL → DRn FR0 × FRm+FRn → FRn 2 2 10 23 1 1 1 1 2 1           Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes FMOV FMOV FRm, FRn DRm, DRn 1111nnnnmmmm1100 1111nnn0mmm01100 FRm → FRn DRm → DRn 1 2   Yes Yes Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 67 of 1262 REJ09B0437-0100 Section 2 CPU Compatibility Execution Instruction FMOV.S FMOV.D FMOV.S FMOV.D FMOV.S FMOV.D FMOV.S @(R0, Rm), FRn @(R0, Rm), DRn @Rm+, FRn @Rm+, DRn @Rm, FRn @Rm, DRn Instruction Code 1111nnnnmmmm0110 1111nnn0mmmm0110 1111nnnnmmmm1001 1111nnn0mmmm1001 1111nnnnmmmm1000 1111nnn0mmmm1000 Operation (R0 + Rm) → FRn (R0 + Rm) → DRn (Rm) → FRn, Rm+=4 (Rm) → DRn, Rm += 8 (Rm) → FRn (Rm) → DRn (disp × 4 + Rm) → FRn Cycles T Bit 1 2 1 2 1 2 1        Yes Yes SH2E Yes SH4 Yes Yes Yes Yes Yes Yes SH-2A/ SH2AFPU Yes Yes Yes Yes Yes Yes Yes @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd (disp × 8 + Rm) → DRn 2  Yes FMOV.S FMOV.D FMOV.S FMOV.D FMOV.S FMOV.D FMOV.S FRm, @(R0,Rn) DRm, @(R0,Rn) FRm, @-Rn DRm, @-Rn FRm, @Rn DRm, @Rn FRm, 1111nnnnmmmm0111 1111nnnnmmm00111 1111nnnnmmmm1011 1111nnnnmmm01011 1111nnnnmmmm1010 1111nnnnmmm01010 0011nnnnmmmm0001 0011dddddddddddd 0011nnnnmmm00001 0011dddddddddddd 1111nnnnmmmm0010 1111nnn0mmm00010 1111nnnn01001101 1111nnn001001101 1111001111111101 FRm → (R0 + Rn) DRm → (R0 + Rn) Rn-=4, FRm → (Rn) Rn-=8, DRm → (Rn) FRm → (Rn) DRm → (Rn) FRm → (disp × 4 + Rn) 1 2 1 2 1 2 1        Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes @(disp12,Rn) FMOV.D DRm, DRm → (disp × 8 + Rn) 2  Yes @(disp12,Rn) FMUL FMUL FNEG FNEG FSCHG FRm, FRn DRm, DRn FRn DRn FRn × FRm → FRn DRn × DRm → DRn -FRn → FRn -DRn → DRn FPSCR.SZ=~FPSCR.S Z 1 6 1 1 1      Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes FSQRT FSQRT FSTS FSUB FRn DRn FPUL,FRn FRm, FRn 1111nnnn01101101 1111nnn001101101 1111nnnn00001101 1111nnnnmmmm0001 √FRn → FRn √DRn → DRn FPUL → FRn FRn-FRm → FRn 9 22 1 1     Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Rev. 1.00 Nov. 14, 2007 Page 68 of 1262 REJ09B0437-0100 Section 2 CPU Compatibility Execution Instruction FSUB FTRC FTRC DRm, DRn FRm, FPUL DRm, FPUL Instruction Code 1111nnn0mmm00001 1111mmmm00111101 1111mmm000111101 Operation DRn-DRm → DRn (long)FRm → FPUL (long)DRm → FPUL Cycles T Bit 6 1 2    Yes SH2E SH4 Yes Yes Yes SH-2A/ SH2AFPU Yes Yes Yes 2.4.9 FPU-Related CPU Instructions Table 2.18 FPU-Related CPU Instructions Compatibility Execution Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+, FPSCR @Rm+, FPUL FPSCR, Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Instruction Code 0100mmmm01101010 0100mmmm01011010 0100mmmm01100110 0100mmmm01010110 0000nnnn01101010 0000nnnn01011010 0100nnnn01100010 0100nnnn01010010 Operation Rm → FPSCR Rm → FPUL Cycles T Bit 1 1         SH2E Yes Yes Yes Yes Yes Yes Yes Yes SH4 Yes Yes Yes Yes Yes Yes Yes Yes SH-2A/ SH2AFPU Yes Yes Yes Yes Yes Yes Yes Yes (Rm) → FPSCR, Rm+=4 1 (Rm) → FPUL, Rm+=4 FPSCR → Rn FPUL → Rn Rn-=4, FPCSR → (Rn) Rn-=4, FPUL → (Rn) 1 1 1 1 1 Rev. 1.00 Nov. 14, 2007 Page 69 of 1262 REJ09B0437-0100 Section 2 CPU 2.4.10 Bit Manipulation Instructions Table 2.19 Bit Manipulation Instructions Execution Instruction BAND.B #imm3,@(disp12,Rn) Instruction Code 0011nnnn0iii1001 0100dddddddddddd BANDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) & T → T 3 1100dddddddddddd BCLR.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 0 → (imm of (disp + Rn)) 0000dddddddddddd BCLR BLD.B #imm3,Rn #imm3,@(disp12,Rn) 10000110nnnn0iii 0 → imm of Rn 0011nnnn0iii1001 (imm of (disp + Rn)) → 0011dddddddddddd BLD #imm3,Rn 10000111nnnn1iii imm of Rn → T 1 1 3  Operation result Operation result BLDNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~(imm of (disp + Rn)) 1011dddddddddddd BOR.B #imm3,@(disp12,Rn) →T 3 Operation result 3 Operation result Operation result 3  Yes Yes Yes Yes Yes Yes Yes 3 Operation (imm of (disp + Rn)) & T → Compatibility SH2, Cycles T Bit SH2E SH4 SH-2A 3 Operation result Operation result  Yes Yes Yes 0011nnnn0iii1001 ( imm of (disp + Rn)) | T → T 0101dddddddddddd BORNOT.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 ~( imm of (disp + Rn)) | T → T 3 1101dddddddddddd BSET.B #imm3,@(disp12,Rn) 0011nnnn0iii1001 1 → ( imm of (disp + Rn)) 0001dddddddddddd BSET BST.B #imm3,Rn #imm3,@(disp12,Rn) 10000110nnnn1iii 1 → imm of Rn 0011nnnn0iii1001 T → (imm of (disp + Rn)) 0010dddddddddddd 1 3   Yes Yes BST #imm3,Rn 10000111nnnn0iii T → imm of Rn 1  Yes Rev. 1.00 Nov. 14, 2007 Page 70 of 1262 REJ09B0437-0100 Section 2 CPU Execution Instruction BXOR.B #imm3,@(disp12,Rn) Instruction Code Operation Compatibility SH2, Cycles T Bit SH2E SH4 SH-2A 3 Operation result Yes 0011nnnn0iii1001 (imm of (disp + Rn)) ^ T → T 0110dddddddddddd Rev. 1.00 Nov. 14, 2007 Page 71 of 1262 REJ09B0437-0100 Section 2 CPU 2.5 Processing States The CPU has five processing states: reset, exception handling, bus-released, program execution, and power-down. Figure 2.6 shows the transitions between the states. Power-on reset from any state Manual reset from any state Power-on reset state Manual reset state Reset state Reset canceled Interrupt source or DMA address error occurs Bus request cleared Exception handling state Exception handling Bus request source generated occurs Bus request cleared NMI interrupt or IRQ interrupt occurs Exception handling ends Bus-released state Bus request generated Bus request generated Bus request cleared Program execution state STBY and DEEP bits set for SLEEP instruction STBY bit cleared for SLEEP instruction Sleep mode Software standby mode Power-down state Figure 2.6 Transitions between Processing States Rev. 1.00 Nov. 14, 2007 Page 72 of 1262 REJ09B0437-0100 Section 2 CPU (1) Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. (2) Exception Handling State The exception handling state is a transient state that occurs when exception handling sources such as resets or interrupts alter the CPU’s processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception handling vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception handling vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. (3) Program Execution State In the program execution state, the CPU sequentially executes the program. (4) Power-Down State In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP instruction places the CPU in sleep mode or software standby mode. (5) Bus-Released State In the bus-released state, the CPU releases bus to a device that has requested it. Rev. 1.00 Nov. 14, 2007 Page 73 of 1262 REJ09B0437-0100 Section 2 CPU Rev. 1.00 Nov. 14, 2007 Page 74 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) Section 3 3.1 Features Floating-Point Unit (FPU) The FPU has the following features. • Conforms to IEEE754 standard • 16 single-precision floating-point registers (can also be referenced as eight double-precision registers) • Two rounding modes: Round to nearest and round to zero • Denormalization modes: Flush to zero • Five exception sources: Invalid operation, divide by zero, overflow, underflow, and inexact • Comprehensive instructions: Single-precision, double-precision, and system control Rev. 1.00 Nov. 14, 2007 Page 75 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.2 3.2.1 Data Formats Floating-Point Format A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 3.1 and 3.2. 31 s 30 e 23 22 f 0 Figure 3.1 63 s 62 e Format of Single-Precision Floating-Point Number 52 51 f 0 Figure 3.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin – 1 to Emax + 1. The two values Emin – 1 and Emax + 1 are distinguished as follows. Emin – 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). Table 3.1 shows Emin and Emax values. Rev. 1.00 Nov. 14, 2007 Page 76 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) Table 3.1 Parameter Floating-Point Number Formats and Parameters Single-Precision 32 bits 1 bit 8 bits 23 bits 24 bits +127 +127 –126 Double-Precision 64 bits 1 bit 11 bits 52 bits 53 bits +1023 +1023 –1022 Total bit width Sign bit Exponent field Fraction field Precision Bias Emax Emin Floating-point number value v is determined as follows: If E = Emax + 1 and f ≠ 0, v is a non-number (NaN) irrespective of sign s If E = Emax + 1 and f = 0, v = (–1)s (infinity) [positive or negative infinity] If Emin ≤ E ≤ Emax , v = (–1)s2E (1.f) [normalized number] If E = Emin – 1 and f ≠ 0, v = (–1)s2Emin (0.f) [denormalized number] If E = Emin – 1 and f = 0, v = (–1)s0 [positive or negative zero] Rev. 1.00 Nov. 14, 2007 Page 77 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) Table 3.2 shows the ranges of the various numbers in hexadecimal notation. Table 3.2 Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number Floating-Point Ranges Single-Precision H'7FFF FFFF to H'7FC0 0000 H'7FBF FFFF to H'7F80 0001 H'7F80 0000 H'7F7F FFFF to H'0080 0000 H'007F FFFF to H'0000 0001 H'0000 0000 H'8000 0000 H'8000 0001 to H'807F FFFF H'8080 0000 to H'FF7F FFFF H'FF80 0000 H'FF80 0001 to H'FFBF FFFF H'FFC0 0000 to H'FFFF FFFF Double-Precision H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 H'7FF7 FFFF FFFF FFFF to H'7FF0 0000 0000 0001 H'7FF0 0000 0000 0000 H'7FEF FFFF FFFF FFFF to H'0010 0000 0000 0000 H'000F FFFF FFFF FFFF to H'0000 0000 0000 0001 H'0000 0000 H'8000 0000 0000 0000 0000 0000 H'8000 0000 0000 0001 to H'800F FFFF FFFF FFFF H'8010 0000 0000 0000 to H'FFEF FFFF FFFF FFFF H'FFF0 0000 0000 0000 H'FFF0 0000 0000 0001 to H'FFF7 FFFF FFFF FFFF H'FFF8 0000 0000 0000 to H'FFFF FFFF FFFF FFFF Rev. 1.00 Nov. 14, 2007 Page 78 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.2.2 Non-Numbers (NaN) Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: • Sign bit: Don't care • Exponent field: All bits are 1 • Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0. 31 x 30 11111111 23 22 0 Nxxxxxxxxxxxxxxxxxxxxxx N = 1: sNaN N = 0: qNaN Figure 3.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. • When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN. • When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this case, the contents of the operation destination register are unchanged. If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit in FPSCR. An exception will not be generated in this case. The qNAN values as operation results are as follows: • Single-precision qNaN: H'7FBF FFFF • Double-precision qNaN: H'7FF7 FFFF FFFF FFFF See the individual instruction descriptions for details of floating-point operations when a nonnumber (NaN) is input. Rev. 1.00 Nov. 14, 2007 Page 79 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.2.3 Denormalized Numbers For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. In the SH2A-FPU, the DN bit in the status register FPSCR is always set to 1, therefore a denormalized number (source operand or operation result) is always flushed to 0 in a floatingpoint operation that generates a value (an operation other than copy, FNEG, or FABS). When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is processed as it is. See the individual instruction descriptions for details of floating-point operations when a denormalized number is input. Rev. 1.00 Nov. 14, 2007 Page 80 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.3 3.3.1 Register Descriptions Floating-Point Registers Figure 3.4 shows the floating-point register configuration. There are sixteen 32-bit floating-point registers FPR0 to FPR15, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14. The correspondence between FRPn and the reference name is determined by the PR and SZ bits in FPSCR. Refer figure 3.4. 1. Floating-point registers, FPRi (16 registers) FPR0 to FPR15 2. Single-precision floating-point registers, FRi (16 registers) FR0 to FR15 indicate FPR0 to FPR15 3. Double-precision floating-point registers or single-precision floating-point vector registers in pairs, DRi (8 registers) A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} Reference name Register name Transfer instruction case: FPSCR.SZ = 0 FPSCR.SZ = 1 Operation instruction case: FPSCR.PR = 0 FPSCR.PR = 1 FR0 DR0 FR1 FR2 DR2 FR3 FR4 DR4 FR5 FR6 DR6 FR7 FR8 DR8 FR9 FR10 DR10 FR11 FR12 DR12 FR13 FR14 DR14 FR15 FPR0 FPR1 FPR2 FPR3 FPR4 FPR5 FPR6 FPR7 FPR8 FPR9 FPR10 FPR11 FPR12 FPR13 FPR14 FPR15 Figure 3.4 Floating-Point Registers Rev. 1.00 Nov. 14, 2007 Page 81 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.3.2 Floating-Point Status/Control Register (FPSCR) FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 QIS 21 - 20 SZ 19 PR 18 DN 17 16 Cause Initial value: R/W: Bit: 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 Enable 0 R 8 0 R 7 0 R/W 6 0 R 5 0 R/W 4 Flag 0 R/W 3 1 R 2 0 R/W 1 RM1 0 R/W 0 RM0 Cause Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W Bit 31 to 23 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 22 QIS 0 R/W Nonnunerical Processing Mode 0: Processes qNaN or ±∞ as such 1: Treats qNaN or ±∞ as the same as sNaN (valid only when FPSCR.Enable.V = 1) 21 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 20 SZ 0 R/W Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits) 19 PR 0 R/W Precision Mode 0: Floating-point instructions are executed as singleprecision operations 1: Floating-point instructions are executed as doubleprecision operations (graphics support instructions are undefined) 18 DN 1 R Denormalization Mode (Always fixed to 1 in SH2AFPU) 1: Denormalized number is treated as zero Rev. 1.00 Nov. 14, 2007 Page 82 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) Bit 17 to 12 11 to 7 6 to 2 Bit Name Cause Enable Flag Initial Value All 0 All 0 All 0 R/W R/W R/W R/W Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field When an FPU exception occurs, the bits corresponding to the FPU exception cause field and FPU exception flag field are set to 1. Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 3.3. 1 0 RM1 RM0 0 1 R/W R/W Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved Table 3.3 Field Name Cause Enable Flag Bit Allocation for FPU Exception Handling FPU Error (E) FPU exception cause field FPU exception enable field Bit 17 None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2 FPU exception flag None field Note: No FPU error occurs in the SH2A-FPU. 3.3.3 Floating-Point Communication Register (FPUL) Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register that is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number, the processing flow is as follows: R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1 Rev. 1.00 Nov. 14, 2007 Page 83 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.4 Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. Which of the two rounding methods is to be used is determined by the RM bits in FPSCR. FPSCR.RM[1:0] = 00: Round to Nearest FPSCR.RM[1:0] = 01: Round to Zero (1) Round to Nearest The operation result is rounded to the nearest expressible value. If there are two nearest expressible values, the one with an LSB of 0 is selected. If the unrounded value is 2Emax (2 – 2–P) or more, the result will be infinity with the same sign as the unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. (2) Round to Zero The digits below the round bit of the unrounded value are discarded. If the unrounded value is larger than the maximum expressible absolute value, the value will become the maximum expressible absolute value. Rev. 1.00 Nov. 14, 2007 Page 84 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.5 3.5.1 Floating-Point Exceptions FPU Exception Sources The exception sources are as follows: • FPU error (E): When FPSCR.DN = 0 and a denormalized number is input (No error occurs in the SH2A-FPU) • Invalid operation (V): In case of an invalid operation, such as NaN input • Division by zero (Z): Division with a zero divisor • Overflow (O): When the operation result overflows • Underflow (U): When the operation result underflows • Inexact exception (I): When overflow, underflow, or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled. When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the corresponding bit in the FPU exception flag field remains unchanged. Rev. 1.00 Nov. 14, 2007 Page 85 of 1262 REJ09B0437-0100 Section 3 Floating-Point Unit (FPU) 3.5.2 FPU Exception Handling FPU exception handling is initiated in the following cases: • FPU error (E): FPSCR.DN = 0 and a denormalized number is input (No error occurs in the SH2A-FPU) • Invalid operation (V): FPSCR.Enable.V = 1 and invalid operation • Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor • Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result overflow • Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result underflow • Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation result These possibilities are shown in the individual instruction descriptions. All exception events that originate in the FPU are assigned as the same exception event. The meaning of an exception is determined by software by reading from FPSCR and interpreting the information it contains. If no bits are set in the FPU exception cause field of FPSCR when one or more of bits O, U, I, and V are set in the FPU exception enable field, this indicates that an actual exception source is not generated. Also, the destination register is not changed by any FPU exception handling operation. Except for the above, the FPU disables exception handling. In every processing, the bit corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the operation result. • Invalid operation (V): qNaN is generated as the result. • Division by zero (Z): Infinity with the same sign as the unrounded value is generated. • Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated. • Underflow (U): Zero with the same sign as the unrounded value is generated. • Inexact exception (I): An inexact result is generated. Rev. 1.00 Nov. 14, 2007 Page 86 of 1262 REJ09B0437-0100 Section 4 Cache Section 4 Cache 4.1 Features • Capacity Instruction cache: 8 Kbytes Operand cache: 8 Kbytes • Structure: Instructions/data separated, 4-way set associative • Cache lock function (only for operand cache): Way 2 and way 3 are lockable • Line size: 16 bytes • Number of entries: 128 entries/way • Write system: Write-back/write-through selectable • Replacement method: Least-recently-used (LRU) algorithm 4.1.1 Cache Structure The cache separates data and instructions and uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 128 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2 Kbytes (16 bytes × 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure 4.1 shows the operand cache structure. The instruction cache structure is the same as the operand cache structure except for not having the U bit. Rev. 1.00 Nov. 14, 2007 Page 87 of 1262 REJ09B0437-0100 Section 4 Cache Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 Entry 1 . . . . . . V U Tag address 0 1 . . . . . . LW0 LW1 LW2 LW3 0 1 . . . . . . Entry 127 23 (1 + 1 + 21) bits 127 128 (32 × 4) bits LW0 to LW3: Longword data 0 to 3 127 6 bits Figure 4.1 Operand Cache Structure (1) Address Array The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit (only for operand cache) indicates whether the entry has been written to in write-back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical address used in the external memory access. It consists of 21 bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 7, Bus State Controller (BSC)), and therefore the upper three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in software standby mode. The tag address is not initialized by a power-on reset or manual reset or in software standby mode. (2) Data Array Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on reset or manual reset or in software standby mode. Rev. 1.00 Nov. 14, 2007 Page 88 of 1262 REJ09B0437-0100 Section 4 Cache (3) LRU With the 4-way set associative system, up to four instructions or data with the same entry address can be registered in the cache. When an entry is registered, LRU shows which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU) algorithm is used to select the way that has been least recently accessed. Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between LRU and way replacement is shown in table 4.1 when the cache lock function (only for operand cache) is not used (concerning the case where the cache lock function is used, see section 4.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 4.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 4.1. The LRU bits are initialized to B'000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Table 4.1 LRU and Way Replacement (Cache Lock Function Not Used) Way to be Replaced 3 2 1 0 LRU (Bits 5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00 Nov. 14, 2007 Page 89 of 1262 REJ09B0437-0100 Section 4 Cache 4.2 Register Descriptions The cache has the following registers. Table 4.2 Register Configuration Abbreviation CCR1 CCR2 R/W R/W R/W Initial Value H'00000000 H'00000000 Address H'FFFC1000 H'FFFC1004 Access Size 32 32 Register Name Cache control register 1 Cache control register 2 4.2.1 Cache Control Register 1 (CCR1) The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF bit controls disabling of all operand cache entries. The WT bit selects either write-through mode or write-back mode for operand cache. Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR1. CCR1 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 ICF 10 - 9 - 8 ICE 7 - 6 - 5 - 4 - 3 OCF 2 - 1 WT 0 OCE Initial value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 90 of 1262 REJ09B0437-0100 Section 4 Cache Bit 31 to 12 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Flush Writing 1 flushes all instruction cache entries (clears the V and LRU bits of all instruction cache entries to 0). Always reads 0. Write-back to external memory is not performed when the instruction cache is flushed. Reserved These bits are always read as 0. The write value should always be 0. Instruction Cache Enable Indicates whether the instruction cache function is enabled/disabled. 0: Instruction cache disable 1: Instruction cache enable 11 ICF 0 R/W 10, 9  All 0 R 8 ICE 0 R/W 7 to 4  All 0 R 3 OCF 0 R/W 2  0 R 1 WT 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Operand Cache Flush Writing 1 flushes all operand cache entries (clears the V, U, and LRU bits of all operand cache entries to 0). Always reads 0. Write-back to external memory is not performed when the operand cache is flushed. Reserved This bit is always read as 0. The write value should always be 0. Write Through Selects write-back mode or write-through mode. 0: Write-back mode 1: Write-through mode 0 OCE 0 R/W Operand Cache Enable Indicates whether the operand cache function is enabled/disabled. 0: Operand cache disable 1: Operand cache enable Rev. 1.00 Nov. 14, 2007 Page 91 of 1262 REJ09B0437-0100 Section 4 Cache 4.2.2 Cache Control Register 2 (CCR2) CCR2 is used to enable or disable the cache locking function for operand cache and is valid in cache locking mode only. In cache locking mode, the lock enable bit (the LE bit) in CCR2 is set to 1. In non-cache-locking mode, the cache locking function is invalid. When a cache miss occurs in cache locking mode by executing the prefetch instruction (PREF @Rn), the line of data pointed to by Rn is loaded into the cache according to bits 9 and 8 (the W3LOAD and W3LOCK bits) and bits 1 and 0 (the W2LOAD and W2LOCK bits) in CCR2. The relationship between the setting of each bit and a way, to be replaced when the prefetch instruction is executed, are listed in table 4.3. On the other hand, when the prefetch instruction is executed and a cache hit occurs, new data is not fetched and the entry which is already enabled is held. For example, when the prefetch instruction is executed with W3LOAD = 1 and W3LOCK = 1 specified in cache locking mode while one-line data already exists in way 0 which is specified by Rn, a cache hit occurs and data is not fetched to way 3. In the cache access other than the prefetch instruction in cache locking mode, ways to be replaced by bits W3LOCK and W2LOCK are restricted. The relationship between the setting of each bit in CCR2 and ways to be replaced are listed in table 4.4. Programs that change the contents of CCR2 should be placed in a cache-disabled space, and a cache-enabled space should be accessed after reading the contents of CCR2. CCR2 is initialized to H'00000000 by a power-on reset but not initialized by a manual reset or in software standby mode. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 LE Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 15 - 14 - 13 - 12 - 11 - 10 - 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 0 W3 W3 LOAD* LOCK W2 W2 LOAD* LOCK Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Rev. 1.00 Nov. 14, 2007 Page 92 of 1262 REJ09B0437-0100 Section 4 Cache Bit 31 to 17 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 16 LE 0 R/W Lock Enable Controls the cache locking function. 0: Not cache locking mode 1: Cache locking mode 15 to 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 8 W3LOAD* W3LOCK 0 0 R/W R/W Way 3 Load Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD = 1 and W3LOCK = 1 in cache locking mode, the data is always loaded into way 3. Under any other condition, the cache miss data is loaded into the way to which LRU points. 7 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 W2LOAD* W2LOCK 0 0 R/W R/W Way 2 Load Way 2 Lock When a cache miss occurs by the prefetch instruction while W2LOAD = 1 and W2LOCK =1 in cache locking mode, the data is always loaded into way 2. Under any other condition, the cache miss data is loaded into the way to which LRU points. Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Rev. 1.00 Nov. 14, 2007 Page 93 of 1262 REJ09B0437-0100 Section 4 Cache Table 4.3 LE 0 1 1 1 1 1 1 Way to be Replaced when a Cache Miss Occurs in PREF Instruction W3LOAD* x x x 0 0 0 1 W3LOCK x 0 0 1 1 x 1 W2LOAD* x x 0 x 0 1 0 W2LOCK x 0 1 0 1 1 x Way to be Replaced Decided by LRU (table 4.1) Decided by LRU (table 4.1) Decided by LRU (table 4.5) Decided by LRU (table 4.6) Decided by LRU (table 4.7) Way 2 Way 3 [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 4.4 LE 0 1 1 1 1 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction W3LOAD* x x x x x W3LOCK x 0 0 1 1 W2LOAD* x x x x x W2LOCK x 0 1 0 1 Way to be Replaced Decided by LRU (table 4.1) Decided by LRU (table 4.1) Decided by LRU (table 4.5) Decided by LRU (table 4.6) Decided by LRU (table 4.7) [Legend] x: Don't care Note: * The W3LOAD and W2LOAD bits should not be set to 1 at the same time. Table 4.5 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=0) Way to be Replaced 3 1 0 LRU (Bits 5 to 0) 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00 Nov. 14, 2007 Page 94 of 1262 REJ09B0437-0100 Section 4 Cache Table 4.6 LRU and Way Replacement (when W2LOCK=0 and W3LOCK=1) Way to be Replaced 2 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 4.7 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) Way to be Replaced 1 0 LRU (Bits 5 to 0) 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 1.00 Nov. 14, 2007 Page 95 of 1262 REJ09B0437-0100 Section 4 Cache 4.3 Operation Operations for the operand cache are described here. Operations for the instruction cache are similar to those for the operand cache except for the address array not having the U bit, and there being no prefetch operation or write operation, or a write-back buffer. 4.3.1 Searching Cache If the operand cache is enabled (OCE bit in CCR1 is 1), whenever data in a cache-enabled area is accessed, the cache will be searched to see if the desired data is in the cache. Figure 4.2 illustrates the method by which the cache is searched. Entries are selected using bits 10 to 4 of the address used to access memory and the tag address of that entry is read. At this time, the upper three bits of the tag address are always cleared to 0. Bits 31 to 11 of the address used to access memory are compared with the read tag address. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Figure 4.2 shows a hit on way 1. Rev. 1.00 Nov. 14, 2007 Page 96 of 1262 REJ09B0437-0100 Section 4 Cache Access address 31 11 10 4 3 210 Entry selection Address array (ways 0 to 3) Longword (LW) selection Data array (ways 0 to 3) Entry 0 Entry 1 V U Tag address Entry 0 Entry 1 LW0 LW1 LW2 LW3 . . . . . . . . . Entry 127 . . . . . . . . . Entry 127 CMP0 CMP1 CMP2 CMP3 Hit signal (way 1) [Legend] CMP0 to CMP3: Comparison circuits 0 to 3 Figure 4.2 Cache Search Scheme Rev. 1.00 Nov. 14, 2007 Page 97 of 1262 REJ09B0437-0100 Section 4 Cache 4.3.2 (1) Read Access Read Hit In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way is the latest. (2) Read Miss An external bus cycle starts and the entry is updated. The way replaced follows table 4.4. Entries are updated in 16-byte units. When the desired data that caused the miss is loaded from external memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. 4.3.3 (1) Prefetch Operation (Only for Operand Cache) Prefetch Hit LRU is updated so that the hit way becomes the latest. The contents in other caches are not modified. No data is transferred to the CPU. (2) Prefetch Miss No data is transferred to the CPU. The way to be replaced follows table 4.3. Other operations are the same in case of read miss. Rev. 1.00 Nov. 14, 2007 Page 98 of 1262 REJ09B0437-0100 Section 4 Cache 4.3.4 (1) Write Operation (Only for Operand Cache) Write Hit In a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit way becomes the latest. In write-through mode, the data is written to the cache and an external memory write cycle is issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way becomes the latest. (2) Write Miss In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is updated. The way to be replaced follows table 4.4. When the U bit of the entry to be replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. After the cache completes its update cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes. In write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 4.3.5 Write-Back Buffer (Only for Operand Cache) When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After the cache completes to fetch the new entry, the write-back buffer writes the entry back to external memory. During the write-back cycles, the cache can be accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 4.3 shows the configuration of the write-back buffer. A (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 A (31 to 4): Physical address written to external memory (upper three bits are 0) Longword 0 to 3: One line of cache data to be written to external memory Figure 4.3 Write-Back Buffer Configuration Rev. 1.00 Nov. 14, 2007 Page 99 of 1262 REJ09B0437-0100 Section 4 Cache Operations in sections 4.3.2 to 4.3.5 are compiled in table 4.8. Table 4.8 Cache Operations External Memory Hit/ Cache CPU Cycle miss Hit Write-back mode/ write through mode  U Bit  Accession (through internal bus) Not generated Cache Contents Not renewed Instructio Instruction n cache fetch Miss   Cache renewal cycle is generated Renewed to new values by cache renewal cycle Not renewed Operand cache Prefetch/ read Hit Either mode is available x Not generated Miss Write-through mode  Cache renewal cycle is generated Renewed to new values by cache renewal cycle Renewed to new values by cache renewal cycle Renewed to new values by cache renewal cycle Write-back mode 0 Cache renewal cycle is generated 1 Cache renewal cycle is generated. Succeedingly write-back cycle in write-back buffer is generated. Write Hit Write-through mode  Write cycle CPU issues is generated. Renewed to new values by write cycle the CPU issues Renewed to new values by write cycle the CPU issues Write-back mode x Not generated Miss Write-through mode  Write cycle CPU issues is generated. Not renewed* Write-back mode 0 Cache renewal cycle is generated Renewed to new values by cache renewal cycle. Subsequently renewed again to new values in write cycle CPU issues. 1 Cache renewal cycle is generated. Succeedingly buffer is generated. Renewed to new values by cache renewal cycle. new values in write cycle CPU issues. write-back cycle in write-back Subsequently renewed again to [Legend] x: Don't care. Note: Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte write access * Neither LRU renewed. LRU is renewed in all other cases. Rev. 1.00 Nov. 14, 2007 Page 100 of 1262 REJ09B0437-0100 Section 4 Cache 4.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is mapped in the cache-enabled space, operate the memorymapped cache to invalidate and write back as required. Rev. 1.00 Nov. 14, 2007 Page 101 of 1262 REJ09B0437-0100 Section 4 Cache 4.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 4.4.1 Address Array To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. In the address field, specify the entry address selecting the entry, The W bit for selecting the way, and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is fixed at longword, specify B'00 for bits 1 and 0 of the address. The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always specify 0 for the upper three bits (bits 31 to 29) of the tag address. For the address and data formats, see figure 4.4. The following three operations are possible for the address array. (1) Address Array Read The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry address specified by the address and the entry corresponding to the way. For the read operation, associative operation is not performed regardless of whether the associative bit (A bit) specified by the address is 1 or 0. (2) Address-Array Write (Non-Associative Operation) When the associative bit (A bit) in the address field is cleared to 0, write the tag address, LRU bits, U bit (only for operand cache), and V bit, specified by the data field, to the entry address specified by the address and the entry corresponding to the way. When writing to a cache line for which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. Rev. 1.00 Nov. 14, 2007 Page 102 of 1262 REJ09B0437-0100 Section 4 Cache (3) Address-Array Write (Associative Operation) When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field are compared with the tag address that is specified by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When there is no way that has a hit, nothing is written and there is no operation. This function is used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. 4.4.2 Data Array To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. Specify the entry address for selecting the entry, the L bit indicating the longword position within the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword, specify B'00 for bits 1 and 0 of the address. For the address and data formats, see figure 4.4. The following two operations are possible for the data array. Information in the address array is not modified by this operation. (1) Data Array Read The data specified by the L bit in the address is read from the entry address specified by the address and the entry corresponding to the way. (2) Data Array Write The longword data specified by the data is written to the position specified by the L bit in the address from the entry address specified by the address and the entry corresponding to the way. Rev. 1.00 Nov. 14, 2007 Page 103 of 1262 REJ09B0437-0100 Section 4 Cache 1. Instruction cache 1.1 Address array access (a) Address specification Read access 31 23 22 2. Operand cache 2.1 Address array access (a) Address specification Read access 13 12 11 10 4 3 0 2 * 1 0 0 0 31 23 22 13 12 11 10 4 3 0 2 * 1 0 0 0 111100000 *----------* W Entry address 111100001 *----------* W Entry address Write access 31 23 22 Write access 13 12 11 10 4 3 A 2 * 1 0 0 0 31 23 22 13 12 11 10 4 3 A 2 * 1 0 0 0 111100000 *----------* W Entry address 111100001 *----------* W Entry address (b) Data specification (both read and write accesses) 31 29 28 11 10 9 4 3 2 1 0 (b) Data specification (both read and write accesses) 31 29 28 11 10 9 4 3 2 1 0 0 0 0 Tag address (28 to 11) E LRU X X X V 0 0 0 Tag address (28 to 11) E LRU X X U V 1.2 Data array access (both read and write accesses) (a) Address specification 31 23 22 13 12 11 10 4 3 L 2.2 Data array access (both read and write accesses) (a) Address specification 2 1 0 0 0 31 23 22 13 12 11 10 4 3 L 2 1 0 0 0 111100010 *----------* W Entry address 111100011 *----------* W Entry address (b) Data specification 31 Longword data (b) Data specification 0 31 0 Longword data [Legend] *: Don't care E: Bit 10 of entry address for read, don't care for write X: 0 for read, don't care for write Figure 4.4 Specifying Address and Data for Memory-Mapped Cache Access Rev. 1.00 Nov. 14, 2007 Page 104 of 1262 REJ09B0437-0100 Section 4 Cache 4.4.3 (1) Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping cache access. When the A bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and data is written to the bits V and U specified by the write data when a match is found. If no match is found, there is no operation. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U bit is 1. An example when a write data is specified in R0 and an address is specified in R1 is shown below. ; R0=H'0110 0010; tag address(28-11)=B'0 0001 0001 0000 0000 0, U=0, V=0 ; R1=H'F080 0088; operand cache address array access, entry=B'000 1000, A=1 ; MOV.L R0,@R1 (2) Reading the Data of a Specific Entry The data section of a specific cache entry can be read by the memory mapping cache access. The longword indicated in the data field of the data array in figure 4.4 is read into the register. An example when an address is specified in R0 and data is read in R1 is shown below. ; R0=H'F100 004C; instruction cache data array access, entry=B'000 0100, ; Way=0, longword address=3 ; MOV.L @R0,R1 4.4.4 Notes 1. Programs that access memory-mapped cache should be placed in a cache-disabled space. 2. Rewriting the address array contents so that two or more ways are hit simultaneously is prohibited. Operation is not guaranteed if the address array contents are changed so that two or more ways are hit simultaneously. 3. Memory-mapped cache can be accessed only by the CPU and not by the DMAC. Registers can be accessed by the CPU and the DMAC. Rev. 1.00 Nov. 14, 2007 Page 105 of 1262 REJ09B0437-0100 Section 4 Cache Rev. 1.00 Nov. 14, 2007 Page 106 of 1262 REJ09B0437-0100 Section 5 Exception Handling Section 5 Exception Handling 5.1 5.1.1 Overview Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, register bank errors, interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling sources occur at once, they are processed according to the priority shown. Table 5.1 Type Reset Types of Exception Handling and Priority Order Exception Handling Power-on reset Manual reset Priority High Address error Instruction CPU address error DMAC address error FPU exception Integer division exception (division by zero) Integer division exception (overflow) Register bank error Interrupt Bank underflow Bank overflow NMI User break H-UDI IRQ On-chip peripheral modules Direct memory access controller (DMAC) USB2.0 host/function module (USB) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) Host interface (HIF) Encryption/decryption and forward error correction core conjunction DMAC (ADMAC) Low Rev. 1.00 Nov. 14, 2007 Page 107 of 1262 REJ09B0437-0100 Section 5 Exception Handling Type Interrupt Exception Handling On-chip peripheral modules Ethernet controller (EtherC) I C bus interface 3 (IIC3) Stream interface (STIF) Serial communication interface with FIFO (SCIF) Serial sound interface_0 (SSI_0) Serial sound interface_1 (SSI_1) SD host interface (SDHI) 2 Priority High Instruction Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed 1 branch instruction* (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode), instructions that rewrite the PC*2, 32-bit instructions*3, RESBANK instruction, DIVS instruction, and DIVU instruction) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N. 3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. Rev. 1.00 Nov. 14, 2007 Page 108 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.1.2 Exception Handling Operations The exception handling sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Exception Reset Timing of Exception Source Detection and Start of Exception Handling Source Power-on reset Timing of Source Detection and Start of Handling Starts when the RES pin changes from low to high, when the H-UDI reset negate command is set after the H-UDI reset assert command has been set, or when the WDT overflows. Starts when the WDT overflows. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Starts upon attempted execution of a RESBANK instruction when saving has not been performed to register banks. In the state where saving has been performed to all register bank areas, starts when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. Starts from the execution of a TRAPA instruction. Starts from the decoding of an undefined code (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode) anytime except immediately after a delayed branch instruction (delay slot). Starts from the decoding of an undefined code placed (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode) immediately after a delayed branch instruction (delay slot), of instructions that rewrite the PC, of 32-bit instructions, of the RESBANK instruction, of the DIVS instruction, or of the DIVU instruction. Starts when detecting division-by-zero exception or overflow exception caused by division of the negative maximum value (H'80000000) by −1. Manual reset Address error Interrupts Register bank Bank underflow error Bank overflow Instructions Trap instruction General illegal instructions Slot illegal instructions Integer division instructions Rev. 1.00 Nov. 14, 2007 Page 109 of 1262 REJ09B0437-0100 Section 5 Exception Handling When exception handling starts, the CPU operates as follows: (1) Exception Handling Triggered by Reset The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Handling Vector Table, for more information. The vector base register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the interrupt controller (INTC) is also initialized to 0. The program begins running from the PC address fetched from the exception handling vector table. (2) Exception Handling Triggered by Address Errors, Register Bank Errors, Interrupts, and Instructions SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling other than NMI or user breaks with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved to the register banks. In the case of exception handling due to an address error, register bank error, NMI interrupt, user break interrupt, or instruction, saving to a register bank is not performed. When saving is performed to all register banks, automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception will be generated. In the case of interrupt exception handling, the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to an address error or instruction, the I3 to I0 bits are not affected. The exception service routine start address is then fetched from the exception handling vector table and the program begins running from that address. Rev. 1.00 Nov. 14, 2007 Page 110 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.1.3 Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception handling, the start addresses of the exception service routines are fetched from the exception handling vector table, which is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Handling Vector Table Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) 0 1 2 3 4 5 6 7 8 CPU address error DMAC address error Interrupts NMI User break FPU exception H-UDI Bank overflow Bank underflow 9 10 11 12 13 14 15 16 Vector Table Address Offset H'00000000 to H'00000003 H'00000004 to H'00000007 H'00000008 to H'0000000B H'0000000C to H'0000000F H'00000010 to H'00000013 H'00000014 to H'00000017 H'00000018 to H'0000001B H'0000001C to H'0000001F H'00000020 to H'00000023 H'00000024 to H'00000027 H'00000028 to H'0000002B H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000034 to H'00000037 H'00000038 to H'0000003B H'0000003C to H'0000003F H'00000040 to H'00000043 Exception Sources Power-on reset Rev. 1.00 Nov. 14, 2007 Page 111 of 1262 REJ09B0437-0100 Section 5 Exception Handling Exception Sources Integer division exception (division by zero) Integer division exception (overflow) (Reserved by system) Vector Numbers 17 18 19 : 31 Vector Table Address Offset H'00000044 to H'00000047 H'00000048 to H'0000004B H'0000004C to H'0000004F : H'0000007C to H'0000007F H'00000080 to H'00000083 : H'000000FC to H'000000FF H'00000100 to H'00000103 : H'000007FC to H'000007FF Trap instruction (user vector) 32 : 63 External interrupts (IRQ), on-chip peripheral module interrupts* 64 : 511 Note: * The vector numbers and vector table address offsets for each external interrupt and onchip peripheral module interrupt are given in table 6.4 in section 6, Interrupt Controller (INTC). Table 5.4 Calculating Exception Handling Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) × 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Exception Source Resets Address errors, register bank errors, interrupts, instructions Notes: 1. Vector table address offset: See table 5.3. 2. Vector number: See table 5.3. Rev. 1.00 Nov. 14, 2007 Page 112 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.2 5.2.1 Resets Input/Output Pins Table 5.5 shows the reset-related pin configuration. Table 5.5 Pin Name Power-on reset Pin Configuration Symbol I/O Input Function When this pin is driven low, this LSI shifts to the poweron reset processing RES 5.2.2 Types of Reset A reset is the highest-priority exception handling source. There are two kinds of reset, power-on and manual. As shown in table 5.6, the CPU state is initialized in both a power-on reset and a manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a manual reset. Table 5.6 Reset States Conditions for Transition to Reset State WDT Overflow — — Power-on reset — Internal States WRCSR of On-Chip WDT, FRQCR of Peripheral Modules, I/O Port CPG Initialized Initialized Not initialized Type Power-on reset RES Low High High H-UDI Command — MRES — CPU Initialized Initialized Initialized Initialized Initialized Initialized H-UDI reset assert — command is set Command other than H-UDI reset assert is set Command other than H-UDI reset assert is set Command other than H-UDI reset assert is set — Manual reset High Low Initialized Not initialized* Not initialized High High Manual reset Initialized Not initialized* Not initialized Note: * The BN bit in IBNR of the INTC is initialized. Rev. 1.00 Nov. 14, 2007 Page 113 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.2.3 (1) Power-On Reset Power-On Reset by Means of RES Pin When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc (unfixed) when the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip peripheral module registers are initialized. See appendix A, Pin States, for the status of individual pins during the power-on reset state. In the power-on reset state, power-on reset exception handling starts when the RES pin is first driven low for a fixed period and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. (2) Power-On Reset by Means of H-UDI Reset Assert Command When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of an H-UDI reset assert command is equivalent to power-on reset by means of the RES pin. Setting the H-UDI reset negate command cancels the power-on reset state. The time required between an H-UDI reset assert command and H-UDI reset negate command is the same as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state generated by an H-UDI reset assert command, setting the H-UDI reset negate command starts power-on reset exception handling. The CPU operates in the same way as when a power-on reset was caused by the RES pin. Rev. 1.00 Nov. 14, 2007 Page 114 of 1262 REJ09B0437-0100 Section 5 Exception Handling (3) Power-On Reset Initiated by WDT When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode, and WTCNT of the WDT overflows, this LSI enters the power-on reset state. In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal generated by the WDT. If a reset caused by the RES pin or the H-UDI reset assert command occurs simultaneously with a reset caused by WDT overflow, the reset caused by the RES pin or the H-UDI reset assert command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset exception processing is started by the WDT, the CPU operates in the same way as when a poweron reset was caused by the RES pin. Rev. 1.00 Nov. 14, 2007 Page 115 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.2.4 (1) Manual Reset Manual Reset by Means of WDT When a manual reset is set to occur in the WDT’s watchdog timer mode, if the WDT’s WTCNT overflows, the manual reset state is established. In the manual reset state, the internal state of the CPU is initialized, but the registers in on-chip peripheral modules are not initialized. When manual reset exception handling is started, the CPU operates as follows. 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN bit in IBNR of the INTC is also initialized to 0. 4. The values fetched from the exception handling vector table are set in the PC and SP, and the program begins executing. When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the fixed internal manual reset interval cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception handling is not executed. The FPU and other modules are not initialized. Rev. 1.00 Nov. 14, 2007 Page 116 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.3 5.3.1 Address Errors Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.7. Table 5.7 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Instruction fetched from on-chip peripheral module space* or H'F0000000 to H'F5FFFFFF in on-chip RAM space* Data read/write CPU or DMAC Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* Note: * Address Errors None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) None (normal) See section 7, Bus State Controller (BSC), for details of the on-chip peripheral module space and on-chip RAM space. Rev. 1.00 Nov. 14, 2007 Page 117 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.3.2 Address Error Exception Handling When an address error occurs, the bus cycle in which the address error occurred ends.* When the executing instruction then finishes, address error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the address error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved on the stack. 3. The program counter (PC) is saved on the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Note: This sequence only applies to address errors in the reading and writing of data. In case of an address error due to instruction fetching, if the bus cycle in which the address error occurred is not completed by the end of step 3 above, address-error exception handling by the CPU is restarted. This continues until the bus cycle is complete. Rev. 1.00 Nov. 14, 2007 Page 118 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.4 5.4.1 (1) Register Bank Errors Register Bank Error Sources Bank Overflow In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception has been set by the interrupt controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register bank has occurred and been accepted by the CPU. (2) Bank Underflow Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving has not been performed to register banks. 5.4.2 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a bank overflow, and the start address of the executed RESBANK instruction for a bank underflow. To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Rev. 1.00 Nov. 14, 2007 Page 119 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.5 5.5.1 Interrupts Interrupt Sources Table 5.8 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules. Table 5.8 Type NMI User break H-UDI IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) User break controller (UBC) High-performance user debugging interface (H-UDI) IRQ0 to IRQ7 pins (external input) Direct memory access controller (DMAC) Ethernet controller (EtherC) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) Encryption/decryption and forward error correction core conjunction DMAC (A-DMAC) Stream interface (STIF) Host interface (HIF) Serial sound interface_0 (SSI_0) Serial sound interface_1 (SSI_1) SD host interface (SDHI) USB2.0 host/function module (USB) I C bus interface 3 (IIC3) Serial communication interface with FIFO (SCIF) 2 Number of Sources 1 1 1 8 16 1 2 1 1 7 2 2 1 1 3 1 5 16 Each interrupt source is allocated a different vector number and vector table offset. See table 6.4 in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table address offsets. Rev. 1.00 Nov. 14, 2007 Page 120 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.5.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. Priority levels of IRQ interrupts, and on-chip peripheral module interrupts can be set freely using the interrupt priority registers 01, 02, and 06 to 16 (IPR01, IPR02, and IPR06 to IPR16) of the INTC as shown in table 5.9. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.1, Interrupt Priority Registers 01, 02, 06 to 16 (IPR01, IPR02, IPR06 to IPR16), for details of IPR01, IPR02, and IPR05 to IPR14. Table 5.9 Type NMI User break H-UDI IRQ On-chip peripheral module Interrupt Priority Order Priority Level 16 15 15 0 to 15 Comment Fixed priority level. Cannot be masked. Fixed priority level. Fixed priority level. Set with interrupt priority registers 01, 02, and 05 to 14 (IPR01, IPR02, and IPR05 to IPR14). Rev. 1.00 Nov. 14, 2007 Page 121 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.5.3 Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR). When an interrupt is accepted, interrupt exception handling begins. In interrupt exception handling, the CPU fetches the exception service routine start address which corresponds to the accepted interrupt from the exception handling vector table, and saves SR and the program counter (PC) to the stack. In the case of interrupt exception handling other than NMI or user breaks with usage of the register banks enabled, general registers R0 to R14, control register GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt exception handling to be executed are saved in the register banks. In the case of exception handling due to an address error, NMI interrupt, user break interrupt, or instruction, saving is not performed to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving to the stack is performed instead of register bank saving. In this case, an interrupt controller setting must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1), register bank overflow exception occurs. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. See section 6.6, Operation, for further details of interrupt exception handling. Rev. 1.00 Nov. 14, 2007 Page 122 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.6 5.6.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, and integer division exceptions, as shown in table 5.10. Table 5.10 Types of Exceptions Triggered by Instructions Type Trap instruction Slot illegal instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) (including the FPU instruction and FPU-related CPU instruction in FPU module standby mode), instructions that rewrite the PC, 32-bit instructions, RESBANK instruction, DIVS instruction, and DIVU instruction Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12, MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W. Comment General illegal instructions Undefined code anywhere besides in a delay slot (including the FPU instruction and FPUrelated CPU instruction in FPU module standby mode) Division by zero Negative maximum value ÷ (−1) DIVU, DIVS DIVS Integer division exceptions Floating-point operation instruction Instructions that will cause Invalid FADD, FSUB, FMUL, FDIV, FMAC, Operation Exception or Divide by FCMP/EQ, FCMP/GT, FLOAT, Zero Exception defined in the FTRC,FCNVDS, FCNVSD, FSQRT IEEE754 standard, and instructions that may cause Overflow Exception, Underflow Exception, or Incorrectness Exception Rev. 1.00 Nov. 14, 2007 Page 123 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.6.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 5.6.3 Slot Illegal Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is an undefined code (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode), an instruction that rewrites the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction, slot illegal exception handling starts if such kind of instruction is decoded. When the FPU is in the module standby state, the floating-point operation instruction and FPU-related CPU instruction are handled as an undefined code; when such an instruction is placed in the delay slot, slot illegal exception handling starts if the instruction is decoded. The CPU operates as follows: 1. The exception service routine start address is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code, the instruction that rewrites the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU instruction. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. 5.6.4 General Illegal Instructions When an undefined code (including an FPU instruction or FPU-related CPU instruction in FPU module standby mode) placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. When the FPU is in the module standby state, the floating-point operation instruction and FPU-related CPU Rev. 1.00 Nov. 14, 2007 Page 124 of 1262 REJ09B0437-0100 Section 5 Exception Handling instruction are handled as an undefined code; when such an instruction is placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot), general illegal instruction exception handling starts if the instruction is decoded. The CPU handles general illegal instruction exception in the same way as slot illegal instruction exception. Unlike processing of slot illegal instruction exception, however, the program counter value stored is the start address of the undefined code. 5.6.5 Integer Division Instructions When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception are DIVU and DIVS. The only source instruction of overflow exception is DIVS, and overflow exception occurs only when the negative maximum value is divided by −1. The CPU operates as follows: 1. The exception service routine start address which corresponds to the integer division instruction exception that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the integer division instruction at which the exception occurred. 4. After jumping to the exception service routine start address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. Rev. 1.00 Nov. 14, 2007 Page 125 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.6.6 Floating-Point Operation Instruction In the floating-point status/control register (FPSCR), FPU exception occurs if the V, Z, O, U, or I bit in the FPU exception enable field (Enable) is set. This indicates that a floating-point operation instruction has caused any of the exceptions defined in the IEEE754 standard: invalid operation exception, overflow exception (likely instruction), underflow exception (likely instruction), or incorrectness exception (likely instruction). The following floating-point operation instructions may become exception sources: FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, FSQRT An FPU exception occurs only when the corresponding enable bit is set. When the FPU detects an exception source, the FPU discontinues its operation and notifies the CPU of the occurrence of an exception. When exception handling is started, the CPU operates as follows: 1. The start address of the exception service routine corresponding to the FPU exception that has occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved in the stack. 3. The program counter (PC) is saved in the stack. The start address of the instruction following the instruction executed last is the value to be saved in the PC. 4. To start executing the program, a jump occurs to the start address of the exception service routine fetched from the exception handling vector table. This jump is not a delayed branch. The FPU exception flag filed (Flag) in the FPSCR is always updated irrespective of whether it is capable of accepting FPU exceptions and remains set until it is cleared explicitly by an instruction from the user. The FPU exception source field (Cause) in the FPSCR changes each time an FPU instruction is executed. When the FPU exception enable field (Enable) in the FPSCR is set and when the QIS bit in the FPSCR is set, FPU exception starts if qNaN or ±∞ is entered into the source of the floating-point operation instruction. Rev. 1.00 Nov. 14, 2007 Page 126 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.7 When Exception Sources Are Not Accepted When an address error, FPU exception, register bank error (overflow), or interrupt is generated immediately after a delayed branch instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.11. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction Exception Source Point of Occurrence Address Error FPU exception Not accepted Register Bank Error (Overflow) Interrupt Not accepted Not accepted Immediately after a Not accepted delayed branch instruction* Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Rev. 1.00 Nov. 14, 2007 Page 127 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.8 Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 5.12. Table 5.12 Stack Status After Exception Handling Ends Exception Type Address error SP Stack Status Address of instruction after executed instruction SR 32 bits 32 bits Interrupt SP Address of instruction after executed instruction SR 32 bits 32 bits Register bank error (overflow) SP Address of instruction after executed instruction SR 32 bits 32 bits Register bank error (underflow) SP Start address of relevant RESBANK instruction SR 32 bits 32 bits Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits Slot illegal instruction SP Jump destination address of delayed branch instruction SR 32 bits 32 bits Rev. 1.00 Nov. 14, 2007 Page 128 of 1262 REJ09B0437-0100 Section 5 Exception Handling Exception Type General illegal instruction Stack Status SP Start address of general illegal instruction SR 32 bits 32 bits Integer division instruction SP Start address of relevant integer division instruction SR 32 bits 32 bits FPU exception SP Address of the instruction following the instruction executed 32 bits 32 bits SR Rev. 1.00 Nov. 14, 2007 Page 129 of 1262 REJ09B0437-0100 Section 5 Exception Handling 5.9 5.9.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 5.9.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception handling. 5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception handling (interrupts, etc.) and address error exception handling will start up as soon as the first exception handling is ended. Address errors will then also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. Rev. 1.00 Nov. 14, 2007 Page 130 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process interrupt requests according to the user-set priority. 6.1 Features • 16 levels of interrupt priority can be set By setting the nine interrupt priority registers, the priorities of IRQ interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request sources. • NMI noise canceler function An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as the noise canceler function. • Register banks This LSI has register banks that enable register saving and restoration required in the interrupt processing to be performed at high speed. Rev. 1.00 Nov. 14, 2007 Page 131 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ7 to IRQ0 PINT7 to PINT0 Input control (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) UBC H-UDI DMAC CMT BSC WDT MTU2 MTU2S POE2 ADC IIC3 SCIF Comparator Priority identifier Interrupt request SR I3 I2 I1 I0 CPU ICR0 ICR2 ICR1 IRQRR IPR PINTER IBCR PIRR IBNR IPR01, IPR02, IPR05 to IPR14 Module bus INTC [Legend] UBC: User break controller H-UDI: High-performance user debugging interface DMAC: Direct memory access controller CMT: Compare match timer BSC: Bus state controller WDT: Watchdog timer EtherC: Ethernet controller A-DMAC: DMAC with encryption/decryption and forward error correction core HIF: Host interface USB: USB2.0 host/function module STIF: Stream interface SSI: Serial sound interface Bus interface SDHI: SD host interface IIC3: I2C bus interface 3 SCIF: Serial communication interface with FIFO ICR0: Interrupt control register 0 ICR1: Interrupt control register 1 ICR2: Interrupt control register 2 IRQRR: IRQ interrupt request register PINTER: PINT interrupt enable register PIRR: PINT interrupt request register IBCR: Bank control register IBNR: Bank number register IPR01, IPR02, IPR05 to IPR14: Interrupt priority registers 01, 02, 05 to 14 Figure 6.1 Block Diagram of INTC Rev. 1.00 Nov. 14, 2007 Page 132 of 1262 REJ09B0437-0100 Peripheral bus Section 6 Interrupt Controller (INTC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the INTC. Table 6.1 Pin Name Pin Configuration Symbol I/O Input Function Input of nonmaskable interrupt request signal Input of maskable interrupt request signals Nonmaskable interrupt input pin NMI Interrupt request input pins IRQ7 to IRQ0 Input Rev. 1.00 Nov. 14, 2007 Page 133 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3 Register Descriptions The INTC has the following registers. These registers are used to set the interrupt priorities and control detection of the external interrupt input signal. Table 6.2 Register Configuration Abbreviation R/W ICR0 ICR1 IRQRR IBCR IBNR IPR01 IPR02 IPR06 IPR07 IPR08 IPR09 IPR10 IPR11 IPR12 IPR13 IPR14 IPR15 IPR16 R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Register Name Interrupt control register 0 Interrupt control register 1 IRQ interrupt request register Bank control register Bank number register Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 Interrupt priority register 15 Interrupt priority register 16 Initial Value *1 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFFE0800 H'FFFE0802 H'FFFE0806 H'FFFE080C H'FFFE080E H'FFFE0818 H'FFFE081A H'FFFE0C00 H'FFFE0C02 H'FFFE0C04 H'FFFE0C06 H'FFFE0C08 H'FFFE0C0A H'FFFE0C0C H'FFFE0C0E H'FFFE0C10 H'FFFE0C12 H'FFFE0C14 Access Size 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 Notes: 1. When the NMI pin is high, becomes H'8000; when low, becomes H'0000. 2. Only 0 can be written after reading 1, to clear the flag. Rev. 1.00 Nov. 14, 2007 Page 134 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3.1 Interrupt Priority Registers 01, 02, 06 to 16 (IPR01, IPR02, IPR06 to IPR16) IPR01, IPR02, and IPR06 to IPR16 are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts. Table 6.3 shows the correspondence between the interrupt request sources and the bits in IPR01, IPR02, and IPR06 to IPR16. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Table 6.3 Interrupt Request Sources and IPR01, IPR02, and IPR06 to IPR16 Bits 15 to 12 IRQ0 IRQ4 DMAC0 DMAC4 USB Bits 11 to 8 IRQ1 IRQ5 DMAC1 DMAC5 Reserved WDT C[0]I Reserved IIC3 SCIF0 Reserved Bits 7 to 4 IRQ2 IRQ6 DMAC2 DMAC6 CMT0 HIF0 C[1]I FECI Reserved SCIF1 Reserved Bits 3 to 0 IRQ3 IRQ7 DMAC3 DMAC7 CMT1 HIF1 Reserved Reserved STIF0 SCIF2 SSI0 Register Name Interrupt priority register 01 Interrupt priority register 02 Interrupt priority register 06 Interrupt priority register 07 Interrupt priority register 08 Interrupt priority BSC register 09 Interrupt priority ADM1I register 10 Interrupt priority Reserved register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 ETC STIF1 Reserved Rev. 1.00 Nov. 14, 2007 Page 135 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Register Name Interrupt priority register 15 Interrupt priority register 16 Bits 15 to 12 SSI1 Reserved Bits 11 to 8 Reserved SDHI Bits 7 to 4 Reserved Reserved Bits 3 to 0 Reserved Reserved As shown in table 6.3, by setting the 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) with values from H'0 (0000) to H'F (1111), the priority of each corresponding interrupt is set. Setting of H'0 means priority level 0 (the lowest level) and H'F means priority level 15 (the highest level). IPR01, IPR02, and IPR06 to IPR16 are initialized to H'0000 by a power-on reset. Rev. 1.00 Nov. 14, 2007 Page 136 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by a power-on reset. Bit: 15 NMIL 14 - 13 - 12 - 11 - 10 - 9 - 8 NMIE 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Initial value: R/W: * R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: * 1 when the NMI pin is high, and 0 when the NMI pin is low. Bit 15 Bit Name NMIL Initial Value * R/W R Description NMI Input Level Sets the level of the signal input at the NMI pin. The NMI pin level can be obtained by reading this bit. This bit cannot be modified. 0: Low level is input to NMI pin 1: High level is input to NMI pin 14 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select Selects whether the falling or rising edge of the interrupt request signal on the NMI pin is detected. 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 137 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 is initialized by a power-on reset. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [Legend] n = 7 to 0 Bit Name IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description IRQ Sense Select These bits select whether interrupt signals corresponding to pins IRQ7 to IRQ0 are detected by a low level, falling edge, rising edge, or both edges. 00: Interrupt request is detected on low level of IRQn input 01: Interrupt request is detected on falling edge of IRQn input 10: Interrupt request is detected on rising edge of IRQn input 11: Interrupt request is detected on both edges of IRQn input Rev. 1.00 Nov. 14, 2007 Page 138 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3.4 IRQ Interrupt Request Register (IRQRR) IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0. If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after reading IRQ7F to IRQ0F = 1 cancels the retained interrupts. IRQRR is initialized by a power-on reset. Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to clear the flag after 1 is read. Bit 15 to 8 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 139 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Bit 7 6 5 4 3 2 1 0 Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial Value 0 0 0 0 0 0 0 0 R/W Description R/(W)* IRQ Interrupt Request R/(W)* These bits indicate the status of the IRQ7 to IRQ0 interrupt requests. R/(W)* Level detection: R/(W)* 0: IRQn interrupt request has not occurred R/(W)* [Clearing condition] R/(W)* • IRQn input is high R/(W)* 1: IRQn interrupt has occurred [Setting condition] R/(W)* • IRQn input is low Edge detection: 0: IRQn interrupt request is not detected [Clearing conditions] • • Cleared by reading IRQnF while IRQnF = 1, then writing 0 to IRQnF Cleared by executing IRQn interrupt exception handling 1: IRQn interrupt request is detected [Setting condition] • [Legend] n = 7 to 0 Edge corresponding to IRQn1S or IRQn0S of ICR1 has occurred at IRQn pin Rev. 1.00 Nov. 14, 2007 Page 140 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3.5 Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. IBCR is initialized to H'0000 by a power-on reset. Bit: 15 E15 14 E14 13 E13 12 E12 11 E11 10 E10 9 E9 8 E8 7 E7 6 E6 5 E5 4 E4 3 E3 2 E2 1 E1 0 - Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1  Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Description Enable These bits enable or disable use of register banks for interrupt priority levels 15 to 1. However, use of register banks is always disabled for the user break interrupts. 0: Use of register banks is disabled 1: Use of register banks is enabled Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 141 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.3.6 Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next through the bits BN3 to BN0. IBNR is initialized to H'0000 by a power-on reset. Bit: 15 14 13 BOVE 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 1 0 BE[1:0] BN[3:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 15, 14 Initial Bit Name Value BE[1:0] 00 R/W R/W Description Register Bank Enable These bits enable or disable use of register banks. 00: Use of register banks is disabled for all interrupts. The setting of IBCR is ignored. 01: Use of register banks is enabled for all interrupts except NMI and user break. The setting of IBCR is ignored. 10: Reserved (setting prohibited) 11: Use of register banks is controlled by the setting of IBCR. 13 BOVE 0 R/W Register Bank Overflow Enable Enables of disables register bank overflow exception. 0: Generation of register bank overflow exception is disabled 1: Generation of register bank overflow exception is enabled 12 to 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 BN[3:0] 0000 R Bank Number These bits indicate the bank number to which saving is performed next. When an interrupt using register banks is accepted, saving is performed to the register bank indicated by these bits, and BN is incremented by 1. After BN is decremented by 1 due to execution of a RESBANK (restore from register bank) instruction, restoration from the register bank is performed. Rev. 1.00 Nov. 14, 2007 Page 142 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.4 Interrupt Sources There are five types of interrupt sources: NMI, user break, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When set to level 0, that interrupt is masked at all times. 6.4.1 NMI Interrupt The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt requests are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) selects whether the rising edge or falling edge is detected. Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. 6.4.2 User Break Interrupt A user break interrupt which occurs when a break condition set in the user break controller (UBC) matches has a priority level of 15. The user break interrupt exception handling sets the I3 to I0 bits in SR to level 15. For user break interrupts, see section 25, User Break Controller (UBC). 6.4.3 H-UDI Interrupt The high-performance user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs at serial input of an H-UDI interrupt instruction. H-UDI interrupt requests are edgedetected and retained until they are accepted. The H-UDI interrupt exception handling sets the I3 to I0 bits in SR to level 15. For H-UDI interrupts, see section 26, High-Performance User Debugging Interface (H-UDI). Rev. 1.00 Nov. 14, 2007 Page 143 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.4.4 IRQ Interrupts IRQ interrupts are input from pins IRQ7 to IRQ0. For the IRQ interrupts, low-level, falling-edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1 (ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt priority registers 01 and 02 (IPR01 and IPR02). When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the INTC while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request register (IRQRR). When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ interrupt request detection is retained until that interrupt request is accepted. Whether IRQ interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request detection. The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted IRQ interrupt. When returning from IRQ interrupt exception service routine, execute the RTE instruction after confirming that the interrupt request has been cleared by the IRQ interrupt request register (IRQRR) so as not to accidentally receive the interrupt request again. Rev. 1.00 Nov. 14, 2007 Page 144 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.4.5 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following on-chip peripheral modules: • • • • • • • • • • • • • Direct memory access controller (DMAC) Ethernet controller (EtherC) Compare match timer (CMT) Bus state controller (BSC) Watchdog timer (WDT) DMAC with encryption/decryption and forward error correction core (A-DMAC) Stream interface (STIF) Host interface (HIF) Serial sound interface (SSI) SD host interface (SDHI) USB2.0 host/function module (USB) I2C bus interface 3 (IIC3) Serial communication interface with FIFO (SCIF) As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from 0 to 15 can be set for each module by interrupt priority registers 06 to 16 (IPR06 to IPR16). The on-chip peripheral module interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip peripheral module interrupt. Rev. 1.00 Nov. 14, 2007 Page 145 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Handling Vector Table and Priority Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and vector table address offsets. In interrupt exception handling, the interrupt exception service routine start address is fetched from the vector table indicated by the vector table address. For details of calculation of the vector table address, see table 5.4, Calculating Exception Handling Vector Table Addresses, in section 5, Exception Handling. The priorities of IRQ interrupts, and on-chip peripheral module interrupts can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02, and 06 to 16 (IPR01, IPR02, and IPR06 to IPR16). However, if two or more interrupts specified by the same IPR among IPR06 to IPR16 occur, the priorities are defined as shown in the IPR setting unit internal priority of table 6.4, and the priorities cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts, and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priorities indicated in table 6.4. Rev. 1.00 Nov. 14, 2007 Page 146 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Table 6.4 Interrupt Exception Handling Vectors and Priorities Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'0000002C to H'0000002F H'00000030 to H'00000033 H'00000038 to H'0000003B H'00000100 to H'00000103 H'00000104 to H'00000107 H'00000108 to H'0000010B H'0000010C to H'0000010F H'00000110 to H'00000113 H'00000114 to H'00000117 H'00000118 to H'0000011B H'0000011C to H'0000011F H'000001B0 to H'000001B3 H'000001B4 to H'000001B7 H'000001C0 to H'000001C3 H'000001C4 to H'000001C7 0 to 15 (0) IPR06 (11 to 8) 16 15 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0)    IPR Setting Unit Internal Priority    Interrupt Source Number Vector NMI User break H-UDI IRQ IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DMAC0 DEI0 HEI0 DMAC1 DEI1 HEI1 11 12 14 64 65 66 67 68 69 70 71 108 109 112 113 Default Priority High IPR01 (15 to 12)  IPR01 (11 to 8) IPR01 (7 to 4) IPR01 (3 to 0)    IPR02 (15 to 12)  IPR02 (11 to 8) IPR02 (7 to 4) IPR02 (3 to 0)    IPR06 (15 to 12) 1 2 1 2 Low Rev. 1.00 Nov. 14, 2007 Page 147 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'000001D0 to H'000001D3 H'000001D4 to H'000001D7 H'000001E0 to H'000001E3 H'000001E4 to H'000001E7 H'000001F0 to H'000001F3 H'000001F4 to H'000001F7 H'00000200 to H'00000203 H'00000204 to H'00000207 H'00000210 to H'00000213 H'00000214 to H'00000217 H'00000220 to H'00000223 H'00000224 to H'00000227 H'00000230 to H'00000233 H'00000238 to H'0000023B H'0000023C to H'0000023F H'00000240 to H'00000243 H'00000244 to H'00000247 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR07 (3 to 0) 0 to 15 (0) IPR07 (7 to 4) 0 to 15 (0) IPR07 (11 to 8) 0 to 15 (0) 0 to 15 (0) IPR06 (3 to 0) 0 to 15 (0) IPR06 (7 to 4) Interrupt Source Number Vector DMAC2 DEI2 HEI2 DMAC3 DEI3 HEI3 DMAC4 DEI4 HEI4 DMAC5 DEI5 HEI5 DMAC6 DEI6 HEI6 DMAC7 DEI7 HEI7 USB CMT USBI CMI0 CMI1 BSC WDT CMI ITI 116 117 120 121 124 125 128 129 132 133 136 137 140 142 143 144 145 IPR Setting Unit Internal Priority 1 2 1 2 Default Priority High IPR07 (15 to 12) 1 2 1 2 1 2 1 2 IPR08 (15 to 12)  IPR08 (7 to 4) IPR08 (3 to 0)   IPR09 (15 to 12)  IPR09 (11 to 8)  Low Rev. 1.00 Nov. 14, 2007 Page 148 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'00000248 to H'0000024B H'00000258 to H'0000025B H'00000264 to H'00000267 H'0000026C to H'0000026F H'00000274 to H'00000277 H'0000027C to H'0000027F H'000002AC to H'000002AF H'000002B0 to H'000002B3 H'000002B4 to H'000002B7 H'000002B8 to H'000002BB H'000002BC to H'000002BF H'000002C0 to H'000002C3 H'000002D8 to H'000002DB H'000002EC to H'000002EF 0 to 15 (0) 0 to 15 (0) IPR12 (3 to 0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR09 (7 to 4) IPR09 (3 to 0) Interrupt Source Number Vector HIF HIFI HIFBI A-DMAC ADM1I C[0]I C[1]I FECI ETC IIC3-0 EINT0 STPI0 NAKI0 RXI0 TXI0 TEI0 STIF STI0 STI1 146 150 153 155 157 159 171 172 173 174 175 176 182 187 IPR Setting Unit Internal Priority   Default Priority High IPR10 (15 to 12)  IPR10 (11 to 8) IPR10 (7 to 4) IPR11 (7 to 4)    IPR12 (15 to 12)  IPR12 (11 to 8) 1 2 3 4 5  IPR13 (15 to 12)  Low Rev. 1.00 Nov. 14, 2007 Page 149 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Interrupt Vector Interrupt Priority Corresponding Vector Table Address Offset (Initial Value) IPR (Bit) H'00000300 to H'00000303 H'00000304 to H'00000307 H'00000308 to H'0000030B H'0000030C to H'0000030F H'00000310 to H'00000313 H'00000314 to H'00000317 H'00000318 to H'0000031B H'0000031C to H'0000031F H'00000320 to H'00000323 H'00000324 to H'00000327 H'00000328 to H'0000032B H'0000032C to H'0000032F H'00000358 to H'0000035B H'0000035C to H'0000035F H'00000390 to H'00000393 H'00000394 to H'00000397 H'00000398 to H'0000039B 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR14 (3 to 0) 0 to 15 (0) IPR13 (3 to 0) 0 to 15 (0) IPR13 (7 to 4) 0 to 15 (0) IPR13 (11 to 8) Interrupt Source Number Vector SCIF0 BRI0 ERI0 RXI0 TXI0 SCIF1 BRI1 ERI1 RXI1 TXI1 SCIF2 BRI2 ERI2 RXI2 TXI2 SSI0 SSI1 SDIO SSII0 SSII1 SDII3 SDII0 SDII1 192 193 194 195 196 197 198 199 200 201 202 203 214 215 228 229 230 IPR Setting Unit Internal Priority 1 2 Default Priority High 3 4 1 2 3 4 1 2 3 4  IPR15 (15 to 12)  IPR16 (11 to 8) 1 2 3 Low Rev. 1.00 Nov. 14, 2007 Page 150 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.6 6.6.1 Operation Interrupt Operation Sequence The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers 01, 02, and 06 to 16 (IPR01, IPR02, and IPR06 to IPR16). Lower priority interrupts are ignored*. If two of these interrupts have the same priority level or if multiple interrupts occur within a single IPR, the interrupt with the highest priority is selected, according to the default priority and IPR setting unit internal priority shown in table 6.4. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 5. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling (figure 6.4). 6. The interrupt exception service routine start address is fetched from the exception handling vector table corresponding to the accepted interrupt. 7. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt is copied to bits I3 to I0 in SR. 8. The program counter (PC) is saved onto the stack. 9. The CPU jumps to the fetched interrupt exception service routine start address and starts executing the program. The jump that occurs is not a delayed branch. 10. A high level is output from the IRQOUT pin. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just being accepted, the IRQOUT pin holds low level. Rev. 1.00 Nov. 14, 2007 Page 151 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-sensing are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ interrupt request register (IRQRR). For details, see section 6.4.4, IRQ Interrupts. Interrupts held pending due to edge-sensing are cleared by a power-on reset. Rev. 1.00 Nov. 14, 2007 Page 152 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Program execution state Interrupt? No Yes No NMI? Yes User break? No Yes H-UDI interrupt? No No No No Yes Level 15 interrupt? Yes Yes I3 to I0 ≤ level 14? Level 14 interrupt? Yes I3 to I0 ≤ level 13? Level 1 interrupt? No Yes Yes I3 to I0 = level 0? No IRQOUT = low Read exception handling vector table Save SR to stack Copy accept-interrupt level to I3 to I0 Save PC to stack Branch to interrupt exception service routine IRQOUT = high No Figure 6.2 Interrupt Operation Flow Rev. 1.00 Nov. 14, 2007 Page 153 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Handling Figure 6.3 shows the stack after interrupt exception handling. Address 4n – 8 4n – 4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executed instruction Always make sure that SP is a multiple of 4. Figure 6.3 Stack after Interrupt Exception Handling Rev. 1.00 Nov. 14, 2007 Page 154 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.7 Interrupt Response Time Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 6.5 Interrupt Response Time Number of States Peripheral Item Time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU Time from input of interrupt request signal to CPU until sequence currently being executed is completed, interrupt exception handling starts, and first instruction in interrupt exception service routine is fetched No register banking Min. Max. NMI 2 Icyc + 2 Bcyc + 1 Pcyc User Break 3 Icyc H-UDI 2 Icyc + 1 Pcyc IRQ, PINT 2 Icyc + 3 Bcyc + 1 Pcyc Module 2 Icyc + 1 Bcyc + 1 Pcyc Remarks 3 Icyc + m1 + m2 4 Icyc + 2(m1 + m2) + m3 Min. is when the interrupt wait time is zero. Max. is when a higher-priority interrupt request has occurred during interrupt exception handling. 3 Icyc + m1 + m2 12 Icyc + m1 + m2 Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Register banking without register bank overflow Register Min. Max.   Min.   3 Icyc + m1 + m2 3 Icyc + m1 + m2 + 19(m4) banking Max. with register bank overflow Rev. 1.00 Nov. 14, 2007 Page 155 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Number of States Peripheral Module 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 6 Icyc + 1 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 14 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 1 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 200-MHz operation*1*2: Item Interrupt response time No register banking Min. NMI 5 Icyc + 2 Bcyc + 1 Pcyc + m1 + m2 Max. 6 Icyc + 2 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 Register banking without register bank overflow Min.  User Break 6 Icyc + m1 + m2 H-UDI 5 Icyc + 1 Pcyc + m1 + m2 IRQ, PINT 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 6 Icyc + 3 Bcyc + 1 Pcyc + 2(m1 + m2) + m3 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 14 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + 3 Bcyc + 1 Pcyc + m1 + m2 5 Icyc + Remarks 200-MHz operation*1*2: 0.040 to 0.110 µs 7 Icyc + 2(m1 + m2) + m3 6 Icyc + 1 Pcyc + 2(m1 + m2) + m3 200-MHz operation*1*2: 0.060 to 0.130 µs  5 Icyc + 1 Pcyc + m1 + m2 200-MHz operation*1*2: 0.040 to 0.110 µs Max.   14 Icyc + 1 Pcyc + m1 + m2 200-MHz operation*1*2: 0.085 to 0.155 µs Register banking with register bank overflow Min.   5 Icyc + 1 Pcyc + m1 + m2 200-MHz operation*1*2: 0.040 to 0.110 µs Max.   5 Icyc + 1 Pcyc + m1 + 3 Bcyc + 1 Bcyc + 0.135 to 0.205 µs m2 + 19(m4) 1 Pcyc + m1 + 1 Pcyc + m1 + m2 + 19(m4) m2 + 19(m4) Notes: m1 to m4 are the number of states needed for the following memory accesses. m1: Vector address read (longword read) m2: SR save (longword write) m3: PC save (longword write) m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. 1. In the case that m1 = m2 = m3 = m4 = 1 Icyc. 2. In the case that (Iφ, Bφ, Pφ) = (200 MHz, 66 MHz, 33 MHz). Rev. 1.00 Nov. 14, 2007 Page 156 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3 Instruction (instruction replacing interrupt exception handling) F D E E M M M First instruction in interrupt exception service routine F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Instruction fetch. Instruction is fetched from memory in which program is stored. F: Instruction decoding. Fetched instruction is decoded. D: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding. E: Memory access. Memory data access is performed. M: Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted (No Register Banking) Rev. 1.00 Nov. 14, 2007 Page 157 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 2 Icyc + 3 Bcyc + 1 Pcyc 3 Icyc + m1 1 Icyc + m1 + 2(m2) + m3 IRQ m1 F First instruction in interrupt exception service routine First instruction in multiple interrupt exception service routine m2 M m3 M m1 m2 D E E M F D D E E M M M F D Interrupt acceptance [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Multiple interrupt acceptance Figure 6.5 Example of Pipeline Operation for Multiple Interrupts (No Register Banking) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3 Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine F D E E M M M E F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking without Register Bank Overflow) Rev. 1.00 Nov. 14, 2007 Page 158 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 9 Icyc 3 Icyc + m1 + m2 RESBANK instruction F D E E E E E E E E E m1 m2 M m3 M E Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine D E E M F D [Legend] m1: m2: m3: Vector address read Saving of SR (stack) Saving of PC (stack) Interrupt acceptance Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking without Register Bank Overflow) Interrupt acceptance 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine 3 Icyc m1 m2 m3 F D E E M M M ... M F ... ... D [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted (Register Banking with Register Bank Overflow) Rev. 1.00 Nov. 14, 2007 Page 159 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 2 Icyc + 17(m4) 1 Icyc + m1 + m2 + 2(m4) m4 m4 m1 W m2 m3 RESBANK instruction F D E M M M ... M M M Instruction (instruction replacing interrupt exception handling) First instruction in interrupt exception service routine D E E M M M ... F ... D Interrupt acceptance [Legend] m1: m2: m3: m4: Vector address read Saving of SR (stack) Saving of PC (stack) Restoration of banked registers Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK Instruction Execution (Register Banking with Register Bank Overflow) Rev. 1.00 Nov. 14, 2007 Page 160 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.8 Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 6.10 shows the register bank configuration. Registers General registers R0 R1 : : R14 R15 Control registers SR GBR VBR TBR MACH MACL PR PC Interrupt generated (save) Register banks R0 R1 : : R14 GBR MACH MACL PR Bank 0 Bank 1 .... Bank 14 System registers RESBANK instruction (restore) VTO Bank control registers (interrupt controller) Bank control register Bank number register IBCR IBNR Note: VTO: : Banked register Vector table address offset Figure 6.10 Overview of Register Bank Configuration Rev. 1.00 Nov. 14, 2007 Page 161 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.8.1 (1) Banked Register and Input/Output of Banks Banked Register The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table address offset are banked. (2) Input/Output of Banks This LSI has fifteen register banks, bank 0 to bank 14. Register banks are stacked in first-in lastout (FILO) sequence. Saving takes place in order, beginning from bank 0, and restoration takes place in the reverse order, beginning from the last bank saved to. 6.8.2 (1) Bank Save and Restore Operations Saving to Bank Figure 6.11 shows register bank save operations. The following operations are performed when an interrupt for which usage of register banks is allowed is accepted by the CPU: a. Assume that the bank number bit value in the bank number register (IBNR), BN, is i before the interrupt is generated. b. The contents of registers R0 to R14, GBR, MACH, MACL, and PR, and the interrupt vector table address offset (VTO) of the accepted interrupt are saved in the bank indicated by BN, bank i. c. The BN value is incremented by 1. Register banks +1 (c) BN (a) Registers Bank 0 Bank 1 : : Bank i Bank i + 1 : : Bank 14 R0 to R14 (b) GBR MACH MACL PR VTO Figure 6.11 Bank Save Operations Rev. 1.00 Nov. 14, 2007 Page 162 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the interrupt exception service routine. 3 Icyc + m1 + m2 2 Icyc + 3 Bcyc + 1 Pcyc IRQ 3 Icyc m1 m2 m3 Instruction (instruction replacing interrupt exception handling) F D E E M M M E (1) VTO, PR, GBR, MACL (2) R12, R13, R14, MACH (3) R8, R9, R10, R11 Saved to bank Overrun fetch First instruction in interrupt exception service routine (4) R4, R5, R6, R7 (5) R0, R1, R2, R3 F F D E [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 6.12 Bank Save Timing (2) Restoration from Bank The RESBANK (restore from register bank) instruction is used to restore data saved in a register bank. After restoring data from the register banks with the RESBANK instruction at the end of the interrupt exception service routine, execute the RTE instruction to return from interrupt exception service routine. Rev. 1.00 Nov. 14, 2007 Page 163 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.8.3 Save and Restore Operations after Saving to All Banks If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to all register banks, automatic saving to the stack is performed instead of register bank saving if the BOVE bit in the bank number register (IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception occurs and data is not saved to the stack. Save and restore operations when using the stack are as follows: (1) Saving to Stack 1. The status register (SR) and program counter (PC) are saved to the stack during interrupt exception handling. 2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14, R13, …, R1, and R0. 3. The register bank overflow bit (BO) in SR is set to 1. 4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. (2) Restoration from Stack When the RESBANK (restore from register bank) instruction is executed with the register bank overflow bit (BO) in SR set to 1, the CPU operates as follows: 1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14, PR, GBR, MACH, and MACL. 2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the maximum value of 15. Rev. 1.00 Nov. 14, 2007 Page 164 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.8.4 Register Bank Exception There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all of the register banks, an interrupt for which register bank use is allowed is accepted by the CPU, and the BOVE bit in the bank number register (IBNR) is set to 1. In this case, the bank number bit (BN) value in the bank number register (IBNR) remains set to the bank count of 15 and saving is not performed to the register bank. (2) Register Bank Underflow This exception occurs if the RESBANK (restore from register bank) instruction is executed when no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH, MACL, and PR do not change. In addition, the bank number bit (BN) value in the bank number register (IBNR) remains set to 0. 6.8.5 Register Bank Error Exception Handling When a register bank error occurs, register bank error exception handling starts. When this happens, the CPU operates as follows: 1. The exception service routine start address which corresponds to the register bank error that occurred is fetched from the exception handling vector table. 2. The status register (SR) is saved to the stack. 3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction for a register bank overflow, and the start address of the executed RESBANK instruction for a register bank underflow. To prevent multiple interrupts from occurring at a register bank overflow, the interrupt priority level that caused the register bank overflow is written to the interrupt mask level bits (I3 to I0) of the status register (SR). 4. Program execution starts from the exception service routine start address. Rev. 1.00 Nov. 14, 2007 Page 165 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.9 Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the DMAC and transfer data. Interrupt sources that are designated to activate the DMAC are masked without being input to the INTC. The mask condition is as follows: Mask condition = DME • (DE0 • interrupt source select 0 + DE1 • interrupt source select 1 + DE2 • interrupt source select 2 + DE3 • interrupt source select 3 + DE4 • interrupt source select 4 + DE5 • interrupt source select 5 + DE6 • interrupt source select 6 + DE7 • interrupt source select 7) Figure 6.13 shows a block diagram of interrupt control. Here, DME is bit 0 in DMAOR of the DMAC, and DEn (n = 0 to 7) is bit 0 in CHCR0 to CHCR7 of the DMAC. For details, see section 8, Direct Memory Access Controller (DMAC). Interrupt source DMAC Interrupt source flag clearing (by DMAC) Interrupt source (not specified as DMAC activating source) CPU interrupt request INTC CPU Figure 6.13 Interrupt Control Block Diagram Rev. 1.00 Nov. 14, 2007 Page 166 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not DMAC Activating 1 Do not select DMAC activating sources or clear the DME bit to 0. If, DMAC activating sources are selected, clear the DE bit to 0 for the relevant channel of the DMAC. 2. When interrupts occur, interrupt requests are sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt exception service routine. 6.9.2 Handling Interrupt Request Signals as Sources for Activating DMAC but Not CPU Interrupt 1. Select DMAC activating sources and set both the DE and DME bits to 1. This masks CPU interrupt sources regardless of the interrupt priority register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears the interrupt sources when starting transfer. Rev. 1.00 Nov. 14, 2007 Page 167 of 1262 REJ09B0437-0100 Section 6 Interrupt Controller (INTC) 6.10 6.10.1 Usage Note Timing to Clear an Interrupt Source The interrupt source flags should be cleared in the interrupt exception service routine. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU" shown in table 6.5 is required before the interrupt source sent to the CPU is actually cancelled. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, and then execute an RTE instruction. Rev. 1.00 Nov. 14, 2007 Page 168 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Section 7 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory and external devices that are connected to the external address space. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices. 7.1 Features 1. External address space  A maximum of 64 Mbytes for each of areas CS0 and CS3 to CS6.  Can specify the normal space interface, SRAM interface with byte selection, SDRAM, and PCMCIA interface for each address space.  Can select the data bus width (8, 16, or 32 bits) for each address space.  Controls insertion of wait cycles for each address space.  Controls insertion of wait cycles for each read access and write access.  Can set independent idle cycles during the continuous access for five cases: read-write (in same space/different spaces), read-read (in same space/different spaces), the first cycle is a write access. 2. Normal space interface  Supports the interface that can directly connect to the SRAM. 3. SDRAM interface  Can set the SDRAM in up to two areas.  Multiplex output for row address/column address.  Efficient access by single read/single write.  High-speed access in bank-active mode.  Supports an auto-refresh and self-refresh.  Supports power-down modes.  Issues MRS and EMRS commands. 4. PCMCIA direct interface  Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver. 4.2 (PCMCIA2.1 Rev. 2.1).  Wait-cycle insertion controllable by program. 5. SRAM interface with byte selection  Can connect directly to a SRAM with byte selection. Rev. 1.00 Nov. 14, 2007 Page 169 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 6. Refresh function  Supports the auto-refresh and self-refresh functions.  Specifies the refresh interval using the refresh counter and clock selection.  Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). 7. Usage as interval timer for refresh counter  Generates an interrupt request at compare match. Rev. 1.00 Nov. 14, 2007 Page 170 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Figure 7.1 shows a block diagram of the BSC. BREQ BACK Bus mastership controller CMNCR CS0WCR WAIT Wait controller CS7WCR MD CS7BCR A25 to A0, D31 to D0 BS, RD/WR, RD, WE3 to WE0, RASU, RASL, CASU, CASL CKE, DQMxx, AH, FRAME, IOIS16, CE2A, CE2B Memory controller SDCR RTCSR RTCNT Comparator RTCOR BSC REFOUT Refresh controller [Legend] CMNCR: Common control register CSnWCR: CSn space wait control register (n = 0 to 7) CSnBCR: CSn space bus control register (n = 0 to 7) SDRAM control register SDCR: RTCSR: Refresh timer control/status register RTCNT: Refresh timer counter RTCOR: Refresh time constant register Figure 7.1 Block Diagram of BSC Rev. 1.00 Nov. 14, 2007 Page 171 of 1262 REJ09B0437-0100 Module bus CS0 to CS7 Area controller CS0BCR Internal bus ... ... ... ... ... Section 7 Bus State Controller (BSC) 7.2 Input/Output Pins Table 7.1 shows the pin configuration of the BSC. Table 7.1 Name A25 to A0 D31 to D0 BS CS0, CS3, CS4 CS5/CE1A, CS6/CE1B CE2A, CE2B RD/WR Pin Configuration I/O Function Output Address bus I/O Data bus Output Bus cycle start Output Chip select Output Chip select Function as PCMCIA card select signals for D7 to D0 when PCMCIA is used. Output Function as PCMCIA card select signals for D15 to D8. Output Read/write Connects to WE pins when SDRAM or SRAM with byte selection is connected. RD Output Read pulse signal (read data output enable signal) Functions as a strobe signal for indicating memory read cycles when PCMCIA is used. WE3/DQMUU/ ICIOWR Output Indicates that D31 to D24 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D31 to D24 when SDRAM is connected. Functions as a strobe signal for indicating I/O write cycles when PCMCIA is used. WE2/DQMUL/ ICIORD Output Indicates that D23 to D16 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D23 to D16 when SDRAM is connected. Functions as a strobe signal for indicating I/O read cycles when PCMCIA is used. Rev. 1.00 Nov. 14, 2007 Page 172 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Name WE1/DQMLU/WE I/O Function Output Indicates that D15 to D8 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D15 to D8 when SDRAM is connected. Functions as a strobe signal for indicating memory write cycles when PCMCIA is used. WE0/DQMLL Output Indicates that D7 to D0 are being written to. Connected to the byte select signal when a SRAM with byte selection is connected. Functions as the select signals for D7 to D0 when SDRAM is connected. RAS CAS CKE WAIT IOIS16 Output Connects to RAS pin when SDRAM is connected. Output Connects to CAS pin when SDRAM is connected. Output Connects to CKE pin when SDRAM is connected. Input Input External wait input Indicates 16-bit I/O of PCMIA. Enabled only in little endian mode. The pin should be driven low in big endian mode. MD_BW Input Selects bus width of area 0 and initial bus width of areas 3 to 6. Rev. 1.00 Nov. 14, 2007 Page 173 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.3 7.3.1 Area Overview Address Map In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cache-disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas) according to the upper bits of the address. External address spaces CS0, CS3 to CS6 are cache-enabled when internal address A29 = 0 or cache-disabled when A29 = 1. The kind of memory to be connected and the data bus width are specified in each partial space. The address map for the external address space is listed below. Table 7.2 Address Map Space Memory to be Connected CS0 Other Normal space, SRAM with byte selection Reserved area Reserved area Normal space, SRAM with byte selection, SDRAM Normal space, SRAM with byte selection Normal space, SRAM with byte selection, PCMCIA Normal space, SRAM with byte selection, PCMCIA Reserved area Normal space, SRAM with byte selection, burst ROM (asynchronous or synchronous) Reserved area Reserved area Normal space, SRAM with byte selection, SDRAM Normal space, SRAM with byte selection Normal space, SRAM with byte selection, PCMCIA Normal space, SRAM with byte selection, PCMCIA Reserved area Cache-disabled Cache Cache-enabled Internal Address H'00000000 to H'03FFFFFF H'04000000 to H'07FFFFFF H'08000000 to H'0BFFFFFF Other H'0C000000 to H'0FFFFFFF CS3 H'10000000 to H'13FFFFFF H'14000000 to H'17FFFFFF CS4 CS5 H'18000000 to H'1BFFFFFF CS6 H'1C000000 to H'1FFFFFFF Other H'20000000 to H'23FFFFFF H'24000000 to H'27FFFFFF CS0 Other H'28000000 to H'2BFFFFFF Other H'2C000000 to H'2FFFFFFF CS3 H'30000000 to H'33FFFFFF H'34000000 to H'37FFFFFF CS4 CS5 H'38000000 to H'3BFFFFFF CS6 H'3C000000 to H'3FFFFFFF Other Rev. 1.00 Nov. 14, 2007 Page 174 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Internal Address Space Memory to be Connected On-chip RAM, reserved area* On-chip peripheral modules, reserved area* Cache   H'80000000 to H'FFFBFFFF Other H'FFFC0000 to H'FFFFFFFF Other Note: * For the on-chip RAM space, access the addresses shown in section 27, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 28, List of Registers. Do not access addresses which are not described in these sections. Otherwise, the correct operation cannot be guaranteed. 7.3.2 Data Bus Width and Pin Function Setting in Each Area In this LSI, the data bus width of area 0 and the initial data bus width of areas 3 to 6 can be set to 8, or 16 bits through external pins during a power-on reset. The bus width of area 0 cannot be modified after a power-on reset. The initial data bus width of areas 3 to 6 is set to the same size as that of area 0, but can be modified to 8, 16, or 32 bits through register settings during program execution. Note that the selectable data bus widths may be limited depending on the connected memory type. After a power-on reset, the LSI starts execution of the program stored in the external memory allocated in area 0. Since ROM is assumed as the external memory in area 0, minimum pin functions such as the address bus, data bus, CS0, and RD are available. The sample access waveforms shown in this section include other pins such as BS, RD/WR, and WEn, which are available after they are selected through the pin function controller. Do not attempt any form of memory access other than reading of area 0 until the pin function settings have been completed by the program. For details on pin function settings, see section 23, Pin Function Controller (PFC). Table 7.3 MD_BW 1 0 Correspondence between External Pin (MD) and Data Bus Width Data Bus Width 8 bits 16 bits Rev. 1.00 Nov. 14, 2007 Page 175 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4 Register Descriptions The BSC has the following registers. Do not access spaces other than area 0 until settings of the connected memory interface are completed. Table 7.4 Register Configuration Abbreviation CMNCR CS0BCR CS3BCR CS4BCR CS5BCR CS6BCR CS0WCR CS3WCR CS4WCR CS5WCR CS6WCR SDCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 Register Name Common control register CS0 space bus control register CS3 space bus control register CS4 space bus control register CS5 space bus control register CS6 space bus control register CS0 space wait control register CS3 space wait control register CS4 space wait control register CS5 space wait control register CS6 space wait control register SDRAM control register Initial Value H'00001010 H'36DB0200* H'36DB0200* H'36DB0200* H'36DB0200* H'36DB0200* H'00000500 H'00000500 H'00000500 H'00000500 H'00000500 H'00000000 H'00000000 H'00000000 H'00000000 3 Address H'FFFC0000 H'FFFC0004 H'FFFC0010 H'FFFC0014 H'FFFC0018 H'FFFC001C H'FFFC0028 H'FFFC0034 H'FFFC0038 H'FFFC003C H'FFFC0040 H'FFFC004C H'FFFC0050 H'FFFC0054 H'FFFC0058 H'FFFC180C H'FFFC1818 H'FFFC1BFC Access Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 3 3 3 3 Refresh timer control/status register RTCSR Refresh timer counter Refresh time constant register AC characteristics switching register Internal bus master bus priority register AC characteristics switching key register RTCNT RTCOR ACSWR IBMPR ACKYER R/W* H'00000000 R/W W* 2 H'12300000  Notes: 1. To write to this register, a special sequence using key registers for switching the AC characteristics is required. 2. Write-only register. The write value is arbitrary. 3. This is an initial value when this LSI is started by the external pin (MD_BW) with the bus width set to 8 bits. The initial value will be H'36DB0400 when the bus width is set to 16 bits. Rev. 1.00 Nov. 14, 2007 Page 176 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.1 Common Control Register (CMNCR) CMNCR is a 32-bit register that controls the common items for each area. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15  14  13  12  11  10  9  8 7 DMAIW[2:0] 6 5 DMA IWA 4  3  2  1 HIZ MEM 0 HIZ CNT Initial Value: R/W: 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 1 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12  1 R Reserved This bit is always read as 1. The write value should always be 1. 11 to 9  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 to 6 DMAIW[2:0] 000 R/W Wait states between access cycles when DMA single address transfer is performed. Specify the number of idle cycles to be inserted after an access to an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the contents of DMAIWA. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 1.00 Nov. 14, 2007 Page 177 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 5 Bit Name DMAIWA Initial Value 0 R/W R/W Description Method of inserting wait states between access cycles when DMA single address transfer is performed. Specifies the method of inserting the idle cycles specified by the DMAIW[2:0] bit. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. However, when the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after an access to an external device with DACK, even when the continuous access cycles to an external device with DACK are performed. 0: Idle cycles inserted when another device drives the data bus after an external device with DACK drove it. 1: Idle cycles always inserted after an access to an external device with DACK 4  1 R Reserved This bit is always read as 1. The write value should always be 1. 3, 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 HIZMEM 0 R/W High-Z Memory Control Specifies the pin state in software standby mode for A25 to A0, BS, CSn, CE2x, RD/WR, WEn/DQMxx, and RD. At bus-released state, these pin are highimpedance states regardless of the setting value of the HIZMEM bit. 0: High impedance in software standby mode 1: Driven in software standby mode Rev. 1.00 Nov. 14, 2007 Page 178 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 0 Bit Name HIZCNT* Initial Value 0 R/W R/W Description High-Z Control Specifies the state of CKE, RAS, and CAS in software standby mode. 0: High impedance in software standby mode 1: Driven in software standby mode Note: * For High-Z control of CKIO, see section 9, Clock Pulse Generator (CPG). 7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 3 to 6) CSnBCR is a 32-bit readable/writable register that specifies the function of each area, the number of idle cycles between bus cycles, and the bus width. Do not access external memory other than area 0 until CSnBCR initial setting is completed. Idle cycles may be inserted even when they are not specified. For details, see section 7.5.8, Wait between Access Cycles. Bit: 31 - 30 29 IWW[2:0] 28 27 26 IWRWD[2:0] 25 24 23 IWRWS[2:0] 22 21 20 IWRRD[2:0] 19 18 17 IWRRS[2:0] 16 Initial value: R/W: Bit: 0 R 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 15 - 14 13 TYPE[2:0] 12 11 ENDIAN 10 9 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - BSZ[1:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 1* R/W 1* R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Note: * CSnBCR samples the external pin (MD) that specify the bus width at power-on reset. Bit 31 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 179 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 30 to 28 Bit Name IWW[2:0] Initial Value 011 R/W R/W Description Idle Cycles between Write-Read Cycles and WriteWrite Cycles These bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycles are the write-read cycle and write-write cycle. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 27 to 25 IWRWD[2:0] 011 R/W Idle Cycles for Another Space Read-Write Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target access cycle is a read-write one in which continuous access cycles switch between different spaces. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 1.00 Nov. 14, 2007 Page 180 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 24 to 22 Bit Name Initial Value R/W R/W Description Idle Cycles for Read-Write in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-write cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted IWRWS[2:0] 011 21 to 19 IWRRD[2:0] 011 R/W Idle Cycles for Read-Read in Another Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles switch between different space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted Rev. 1.00 Nov. 14, 2007 Page 181 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 18 to 16 Bit Name IWRRS[2:0] Initial Value 011 R/W R/W Description Idle Cycles for Read-Read in the Same Space Specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. The target cycle is a read-read cycle of which continuous access cycles are for the same space. 000: No idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 15  0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 TYPE[2:0] 000 R/W Specify the type of memory connected to a space. 000: Normal space 001: Setting prohibited 010: Setting prohibited 011: SRAM with byte selection 100: SDRAM 101: PCMCIA 110: Setting prohibited 111: Setting prohibited For details for memory type in each area, see table 7.2. 11 ENDIAN 0 R/W Endian Setting Specifies the arrangement of data in a space. 0: Arranged in big endian 1: Arranged in little endian Rev. 1.00 Nov. 14, 2007 Page 182 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 10, 9 Bit Name BSZ[1:0] Initial Value 11* R/W R/W Description Data Bus Width Specification Specify the data bus widths of spaces. 00: Reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size For MPX-I/O, selects bus width by address Notes: 1. The initial data bus width for areas 3 to 6 is specified by external pins. The BSZ[1:0] bits settings in CS0BCR are ignored but the bus width settings in CS1BCR to CS7BCR can be modified. 2. If area 5 or area 6 is specified as PCMCIA space, the bus width can be specified as either 8 bits or 16 bits. 3. If area 3 is specified as SDRAM space, the bus width can be specified as either 16 bits or 32 bits. 8 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * CSnBCR samples the external pins (MD_BW) that specify the bus width at power-on reset. Rev. 1.00 Nov. 14, 2007 Page 183 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3 to 6) CSnWCR specifies various wait cycles for memory access. The bit configuration of this register varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify CSnBCR first, then specify CSnWCR. (1) Normal Space, SRAM with Byte Selection • CS0WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 22 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21  0 R/W Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W Byte Access Selection when SRAM with Byte Selection is Used Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read/write timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. Rev. 1.00 Nov. 14, 2007 Page 184 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 19, 18 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 17, 16  All 0 R/W Reserved Set this bit to 0 when the interface for normal space or SRAM with byte selection is used. 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS0 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS0 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Nov. 14, 2007 Page 185 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 10 to 7 Bit Name WR[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 186 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 1, 0 Bit Name HW[1:0] Initial Value 00 R/W R/W Description Delay Cycles from RD, WEn Negation to Address, CS0 Negation Specify the number of delay cycles from RD and WEn negation to address and CS0 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles • CS3WCR Bit: 31  30  29  28  27  26  25  24  23  22  21  20 BAS 19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11  10 9 8 7 6 WM 5  4  3  2  1  0  WR[3:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 21 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19 to 11  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 187 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 10 to 7 Bit Name WR[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 188 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) • CS4WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 17 WW[2:0] 16 Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 21 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles Rev. 1.00 Nov. 14, 2007 Page 189 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 15 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS4 Assertion to RD, WE Assertion Specify the number of delay cycles from address and CS4 assertion to RD and WE assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 1.00 Nov. 14, 2007 Page 190 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 6 Bit Name WM Initial Value 0 R/W R/W Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS4 Negation Specify the number of delay cycles from RD and WEn negation to address and CS4 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Nov. 14, 2007 Page 191 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) • CS5WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 SZSEL 20 MPXW/ BAS 19 - 18 17 WW[2:0] 16 Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 22 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read access cycle and asserts the RD/WR signal at the write timing. 19  0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 WW[2:0] 000 R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: The same cycles as WR[3:0] setting (number of read access wait cycles) 001: No cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles Rev. 1.00 Nov. 14, 2007 Page 192 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 15 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS5 Assertion to RD, WEn Assertion Specify the number of delay cycles from address and CS5 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycle is 0. 0: External wait input is valid 1: External wait input is ignored Rev. 1.00 Nov. 14, 2007 Page 193 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 5 to 2 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Delay Cycles from RD, WEn Negation to Address, CS5 Negation Specify the number of delay cycles from RD and WEn negation to address and CS5 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles • CS6WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 BAS 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 11 10 9 8 7 6 WM 5 - 4 - 3 - 2 - 1 0 SW[1:0] WR[3:0] HW[1:0] Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 31 to 21 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 20 BAS 0 R/W SRAM with Byte Selection Byte Access Select Specifies the WEn and RD/WR signal timing when the SRAM interface with byte selection is used. 0: Asserts the WEn signal at the read timing and asserts the RD/WR signal during the write access cycle. 1: Asserts the WEn signal during the read/write access cycle and asserts the RD/WR signal at the write timing. Rev. 1.00 Nov. 14, 2007 Page 194 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 19 to 13 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address, CS6 Assertion to RD, WEn Assertion Specify the number of delay cycles from address, CS6 assertion to RD and WEn assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of cycles that are necessary for read/write access. 0000: No cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Rev. 1.00 Nov. 14, 2007 Page 195 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 6 Bit Name WN Initial Value 0 R/W R/W Description External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification of this bit is valid even when the number of access wait cycles is 0. 0: The external wait input is valid 1: The external wait input is ignored 5 to 2  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 HW[1:0] 00 R/W Number of Delay Cycles from RD, WEn Negation to Address, CS6 Negation Specify the number of delay cycles from RD, WEn negation to address, and CS6 negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles Rev. 1.00 Nov. 14, 2007 Page 196 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (2) SDRAM • CS3WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 13 12 - 11 10 9 - 8 7 6 - 5 - 4 3 2 - 1 0 WTRP[1:0] WTRCD[1:0] A3CL[1:0] TRWL[1:0] WTRC[1:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R 0 R/W 1 R/W 0 R 1 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W Bit 31 to 15 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 14, 13 WTRP[1:0] 00 R/W Number of Auto-Precharge Completion Wait Cycles Specify the number of minimum precharge completion wait cycles as shown below. • • • • • From the start of auto-precharge and issuing of ACTV command for the same bank From issuing of the PRE/PALL command to issuing of the ACTV command for the same bank Till entering the power-down mode or deep powerdown mode From the issuing of PALL command to issuing REF command in auto refresh mode From the issuing of PALL command to issuing SELF command in self refresh mode 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles Rev. 1.00 Nov. 14, 2007 Page 197 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 12 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD[1:0] 01 R/W Number of Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command Specify the minimum number of wait cycles from issuing the ACTV command to issuing the READ(A)/WRIT(A) command. 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 9  0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 198 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 4, 3 Bit Name TRWL[1:0] Initial Value 00 R/W R/W Description Number of Auto-Precharge Startup Wait Cycles Specify the number of minimum auto-precharge startup wait cycles as shown below. • Cycle number from the issuance of the WRITA command by this LSI until the completion of autoprecharge in the SDRAM. Equivalent to the cycle number from the issuance of the WRITA command until the issuance of the ACTV command. Confirm that how many cycles are required between the WRITE command receive in the SDRAM and the auto-precharge activation, referring to each SDRAM data sheet. And set the cycle number so as not to exceed the cycle number specified by this bit. Cycle number from the issuance of the WRITA command until the issuance of the PRE command. This is the case when accessing another low address in the same bank in bank active mode. • 00: No cycle 01: 1 cycle 10: 2 cycles 11: 3 cycles 2  0 R Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 199 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 1, 0 Bit Name WTRC[1:0] Initial Value 00 R/W R/W Description Number of Idle Cycles from REF Command/SelfRefresh Release to ACTV/REF/MRS Command Specify the number of minimum idle cycles in the periods shown below. • • From the issuance of the REF command until the issuance of the ACTV/REF/MRS command From releasing self-refresh until the issuance of the ACTV/REF/MRS command. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles Rev. 1.00 Nov. 14, 2007 Page 200 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (3) PCMCIA • CS5WCR, CS6WCR Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 20 19 - 18 - 17 - 16 - SA[1:0] Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 15 - 14 13 12 11 10 9 8 7 6 WM 5 - 4 - 3 2 1 0 TED[3:0] PCW[3:0] TEH[3:0] Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 22 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 21, 20 SA[1:0] 00 R/W Space Attribute Specification Select memory card interface or I/O card interface when PCMCIA interface is selected. SA1: 0: Selects memory card interface for the space for A25 = 1. 1: Selects I/O card interface for the space for A25 = 1. SA0: 0: Selects memory card interface for the space for A25 = 0. 1: Selects I/O card interface for the space for A25 = 0. 19 to 15  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 201 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 14 to 11 Bit Name TED[3:0] Initial Value 0000 R/W R/W Description Number of Delay Cycles from Address Output to RD/WE Assertion Specify the number of delay cycles from address output to RD/WE assertion for the memory card or to ICIORD/ICIOWR assertion for the I/O card in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Rev. 1.00 Nov. 14, 2007 Page 202 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 10 to 7 Bit Name PCW[3:0] Initial Value 1010 R/W R/W Description Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 WM 0 R/W External Wait Mask Specification Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored 5, 4  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 203 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 3 to 0 Bit Name TEH[3:0] Initial Value 0000 R/W R/W Description Delay Cycles from RD/WE Negation to Address Specify the number of address hold cycles from RD/WE negation for the memory card or those from ICIORD/ICIOWR negation for the I/O card in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles Rev. 1.00 Nov. 14, 2007 Page 204 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.4 SDRAM Control Register (SDCR) SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13 DEEP 12  11 10 9 8 7  6  5  4 3 2  1 0 RFSH RMODEPDOWN BACTV A3ROW[1:0] A3COL[1:0] Initial Value: R/W: 0 R 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W Bit 31 to 14 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 DEEP 0 R/W Deep Power-Down Mode This bit is valid for low-power SDRAM. If the RFSH or RMODE bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the lowpower SDRAM enters the deep power-down mode. 0: Self-refresh mode 1: Deep power-down mode 12  0 R Reserved This bit is always read as 0. The write value should always be 0. 11 RFSH 0 R/W Refresh Control Specifies whether or not the refresh operation of the SDRAM is performed. 0: No refresh 1: Refresh Rev. 1.00 Nov. 14, 2007 Page 205 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 10 Bit Name RMODE Initial Value 0 R/W R/W Description Refresh Control Specifies whether to perform auto-refresh or selfrefresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in registers RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed 9 PDOWN 0 R/W Power-Down Mode Specifies whether the SDRAM will enter the powerdown mode after the access to the SDRAM. With this bit being set to 1, after the SDRAM is accessed, the CKE signal is driven low and the SDRAM enters the power-down mode. 0: The SDRAM does not enter the power-down mode after being accessed. 1: The SDRAM enters the power-down mode after being accessed. 8 BACTV 0 R/W Bank Active Mode Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 206 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 4, 3 Bit Name Initial Value R/W R/W Description Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) A3ROW[1:0] 00 2  0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 A3COL[1:0] 00 R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited) Rev. 1.00 Nov. 14, 2007 Page 207 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.5 Refresh Timer Control/Status Register (RTCSR) RTCSR specifies various items about refresh for SDRAM. When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on reset. Note that there is an error in the time until the compare match flag is set for the first time after the timer is started with the CKS[2:0] bits being set to a value other than B'000. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CMF 6 CMIE 5 4 CKS[2:0] 3 2 1 RRC[2:0] 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 7 Bit Name  CMF Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0. Compare Match Flag Indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied. Rev. 1.00 Nov. 14, 2007 Page 208 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 6 Bit Name CMIE Initial Value 0 R/W R/W Description Compare Match Interrupt Enable Enables or disables CMF interrupt requests when the CMF bit in RTCSR is set to 1. 0: Disables CMF interrupt requests. 1: Enables CMF interrupt requests. 5 to 3 CKS[2:0] 000 R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: Bφ/4 010: Bφ/16 011: Bφ/64 100: Bφ/256 101: Bφ/1024 110: Bφ/2048 111: Bφ/4096 2 to 0 RRC[2:0] 000 R/W Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: 1 time 001: 2 times 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited) Rev. 1.00 Nov. 14, 2007 Page 209 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.6 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 7 to 0 Initial Bit Name Value  All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 8-Bit Counter Rev. 1.00 Nov. 14, 2007 Page 210 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.7 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests are counted by using timer interrupts while refresh is performed periodically. When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15  14  13  12  11  10  9  8  7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 8 7 to 0 Bit Name  Initial Value All 0 All 0 R/W Description R Reserved These bits are always read as 0. R/W 8-Bit Counter Rev. 1.00 Nov. 14, 2007 Page 211 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.8 AC Characteristics Switching Register (ACSWR) To use the SDRAM in clock mode 0 or 1, set the AC characteristics switching register (ACSWR) and AC characteristics key switching register (ACKEYR). In clock mode 2 or 3, set nothing to keep the initial value. Only a special sequence can write to this register to prevent accidental erroneous write. The setting procedure is shown in section 7.4.10, Sequence to Write to ACSWR. Read is done by the normal longword. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 1 0 ACOSW[3:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 4 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 to 0 ACOSW[3:0] 0000 R/W AC Characteristics Switch Specifies AC characteristics switching 0000: Not extend the delay time 1001: Switches characteristics and extends the delay time Others: Setting prohibited Rev. 1.00 Nov. 14, 2007 Page 212 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.9 AC Characteristics Switching Key Register (ACKEYR) ACKEYR is a write only 8-bit register to access the AC characteristics switching register (ACSWR). The write value is ignored and the read value is undefined. Bit: 7 6 5 4 3 2 1 0 ACKEY[7:0] Initial value: R/W: W W W W W W W W Bit 7 to 0 Bit Name ACKEY[7:0] Initial Value  R/W W Description AC Key Writing to this bit is required to write to the ACSWR register. The write value is arbitrary. Rev. 1.00 Nov. 14, 2007 Page 213 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.10 Sequence to Write to ACSWR Figure 7.2 shows the sequence to write to ACSWR. Write must be executed in the on-chip RAM. Main program routine Subroutine executed in on-chip RAM Write subroutine Byte write to ACKEYR (1) Transfer write subroutine to on-chip RAM Execute write subroutine Byte write to ACKEYR (2) Longword write to ACSWR (3) Read ACSWR to confirm Correcrly written (4) Incorrectly written Return Make sure to read and confirm as in step (4) after the write in step (3). If incorrectly written, execute from step (1) again. Figure 7.2 Recommended Sequence to Write to ACSWR Rev. 1.00 Nov. 14, 2007 Page 214 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.4.11 Internal Bus Master Bus Priority Register (IBMPR) IBMPR is a 32-bit register that sets the bus priority for the internal bus masters excluding the CPU. If internal bus masters excluding the same CPU are set at different priority levels, the highest one will be effective. After an attempt to set internal bus masters in an overlapping manner, if some of them failed to be set, then these failing bus masters will not be able to acquire bus mastership. Rewriting this register while any of the A-DMAC (including F-DMAC), E-DMAC, and DMAC is operating is prohibited. When rewriting this register, make sure that none of the A-DMAC (including F-DMAC), E-DMAC, and DMAC is not started. For details, see section 7.5.9 (2), Access from the Side of the LSI Internal Bus Master. Bit: 31  30  29 28 27  26  25 24 23  22  21 20 19  18  17  16  0P1R[1:0] 0P2R[1:0] 0P3R[1:0] Initial Value 0 R/W: R Bit: 15  0 R 0 R/W 1 R/W 0 R 0 R 1 R/W 0 R/W 0 R 0 R 1 R/W 1 R/W 0 R 0 R 0 R 0 R 14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial Value 0 R/W: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31, 30 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 29, 28 0P1R[1:0] 01 R/W Of the internal bus masters excluding the CPU (that is, A-DMAC (including F-DMAC), E-DMAC, and DMAC), set the internal bus master having the highest priority level. 00: No setting 01: A-DMAC (including F-DMAC) 10: E-DMAC 11: DMAC Rev. 1.00 Nov. 14, 2007 Page 215 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Bit 27, 26 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 25, 24 0P2R[1:0] 10 R/W Of the internal bus masters excluding the CPU (that is, A-DMAC (including F-DMAC), E-DMAC, and DMAC), set the internal bus master having the second highest priority level. 00: No setting 01: A-DMAC (including F-DMAC) 10: E-DMAC 11: DMAC 23, 22  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 0P3R[1:0] 11 R/W Of the internal bus masters excluding the CPU (that is, A-DMAC (including F-DMAC), E-DMAC, and DMAC), set the internal bus master having the third highest priority level. 00: No setting 01: A-DMAC (including F-DMAC) 10: E-DMAC 11: DMAC 19 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 216 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5 7.5.1 Operation Endian/Access Size and Data Alignment This LSI supports both big endian, in which the most significant byte (MSB) of data is that in the direction of the 0th address, and little endian, in which the least significant byte (LSB) is that in the direction of the 0th address. In the initial state after a power-on reset, all areas will be in big endian mode. Little endian cannot be selected for area 0. However, the endian of areas 3 to 6 can be changed by the setting in the CSnBCR register setting as long as the target space is not being accessed. Three data bus widths (8 bits, 16 bits, and 32 bits) are selectable for areas 3 to 6, allowing the connection of normal memory and of SRAM with byte selection. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data bus widths (8 bits and 16 bits) are available for the PCMCIA interface. For MPX-I/O, the data bus width can be fixed to either 8 or 16 bits, or made selectable as 8 bits or 16 bits by one of the address lines. Data alignment is in accord with the data bus width selected for the device. This also means that four read operations are required to read longword data from a byte-width device. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. The data bus width of area 0 is fixed to 8 bits or 16 bits by the MD_BW pin setting at a power-on reset. Tables 7.5 to 7.10 show the relationship between device data width and access unit. Note that the correspondence between addresses and strobe signals for the 32- and 16-bit bus widths depends on the endian setting. For example, with big endian and a 32-bit bus width, WE3 corresponds to the 0th address, which is represented by WE0 when little endian has been selected. Little endian cannot be selected for area 0. Note also that 32-bit and 16-bit accesses coincide in instruction fetching, therefore, it is difficult to allocate instruction to little endian area. Make sure to execute instruction in big endian area. Rev. 1.00 Nov. 14, 2007 Page 217 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.5 32-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals WE3, D7 to D0 DQMUU    Data 7 to 0  Data 7 to 0 Data 7 to 0 Assert    Assert  Assert WE2, DQMUL  Assert   Assert  Assert WE1, DQMLU   Assert   Assert Assert WE0, DQMLL    Assert  Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 D31 to D24 Data 7 to 0    Data 15 to 8 D23 to D16  Data 7 to 0   Data 7 to 0  Data 23 to 16 D15 to D8   Data 7 to 0   Data 15 to 8 Data 15 to 8 Word access  at 2 Longword access at 0 Data 31 to 24 Rev. 1.00 Nov. 14, 2007 Page 218 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.6 16-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals D7 to D0  Data 7 to 0  Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16 Data 7 to 0 WE3, DQMUU         WE2, DQMUL         WE1, DQMLU Assert  Assert  Assert Assert Assert Assert WE0, DQMLL  Assert  Assert Assert Assert Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8               Data 7 to 0  Data 7 to 0  Data 15 to 8 Data 15 to 8 Data 31 to 24 Data 15 to 8 Longword 1st  access at 0 time at 0 2nd  time at 2 Rev. 1.00 Nov. 14, 2007 Page 219 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.7 8-Bit External Device Access and Data Alignment in Big Endian Data Bus Strobe Signals WE3, DQMUU             WE2, DQMUL             WE1, DQMLU             WE0, DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 1st time at 0 D31 to D23 to D15 to D24 D16 D8 D7 to D0                              Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 2nd time  at 1 Word access at 2 1st time at 2  2nd time  at 3 Longword access at 0 1st time at 0  2nd time  at 1 3rd time  at 2 4th time  at 3 Rev. 1.00 Nov. 14, 2007 Page 220 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.8 32-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals WE3, D7 to D0 DQMUU Data 7 to 0    Data 7 to 0  Data 7 to 0    Assert  Assert Assert WE2, DQMUL   Assert   Assert Assert WE1, DQMLU  Assert   Assert  Assert WE0, DQMLL Assert    Assert  Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 D31 to D24    Data 7 to 0  D23 to D16   Data 7 to 0   Data 7 to 0 Data 23 to 16 D15 to D8  Data 7 to 0   Data 15 to 8  Data 15 to 8 Word access Data at 2 15 to 8 Longword access at 0 Data 31 to 24 Rev. 1.00 Nov. 14, 2007 Page 221 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.9 16-Bit External Device Access and Data Alignment in Little Endian Data Bus Strobe Signals D7 to D0 Data 7 to 0  Data 7 to 0  Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 23 to 16 WE3, DQMUU         WE2, DQMUL         WE1, DQMLU  Assert  Assert Assert Assert Assert Assert WE0, DQMLL Assert  Assert  Assert Assert Assert Assert Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8                Data 7 to 0  Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 Data 31 to 24 Longword 1st  access at 0 time at 0 2nd  time at 2 Rev. 1.00 Nov. 14, 2007 Page 222 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.10 8-Bit External Device Access and Data Alignment in Little Endian Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 1st time at 0 D31 to D23 to D15 to D24 D16 D8 D7 to D0                              Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24 WE3, DQMUU             Strobe Signals WE2, DQMUL             WE1, DQMLU             WE0, DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert 2nd time  at 1 Word access at 2 1st time at 2  2nd time  at 3 Longword access at 0 1st time at 0  2nd time  at 1 3rd time  at 2 4th time  at 3 Rev. 1.00 Nov. 14, 2007 Page 223 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.2 (1) Normal Space Interface Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 7.5.6, SRAM Interface with Byte Selection. Figure 7.3 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. T1 T2 CKIO A25 to A0 CSn RD/WR Read RD D31 to D0 RD/WR Write WEn D31 to D0 BS DACKn * Note: * The waveform for DACKn is when active low is specified. Figure 7.3 Normal Space Basic Access Timing (Access Wait 0) There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always Rev. 1.00 Nov. 14, 2007 Page 224 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is asserted. It is necessary to output the data that has been read using RD when a buffer is established in the data bus. The RD/WR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer, to avoid collision. Figures 7.4 and 7.5 show the basic timings of normal space access. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait (figure 7.4). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 7.5). T1 T2 Tnop T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 7.4 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) Rev. 1.00 Nov. 14, 2007 Page 225 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) T1 T2 T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D15 to D0 WEn Write D15 to D0 BS DACKn * WAIT Note: * The waveform for DACKn is when active low is specified. Figure 7.5 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) Rev. 1.00 Nov. 14, 2007 Page 226 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) This LSI •••• •••• •••• 128K × 8-bit SRAM •••• •••• •••• •••• •••• •••• •••• •••• A18 A2 CSn RD D31 •••• A16 A0 CS OE I/O7 D24 WE3 D23 •••• •••• I/O0 WE •••• D16 WE2 D15 •••• •••• A16 A0 CS OE I/O7 I/O0 WE •••• D0 WE0 •••• •••• D8 WE1 D7 •••• •••• A16 A0 CS OE I/O7 I/O0 WE •••• A16 A0 CS OE I/O7 I/O0 WE Figure 7.6 Example of 32-Bit Data-Width SRAM Connection Rev. 1.00 Nov. 14, 2007 Page 227 of 1262 REJ09B0437-0100 •••• Section 7 Bus State Controller (BSC) This LSI •••• •••• •••• 128K × 8-bit SRAM •••• A17 A1 CSn RD D15 •••• A16 A0 CS OE I/O7 D8 WE1 D7 •••• •••• I/O0 WE •••• •••• •••• I/O0 WE Figure 7.7 Example of 16-Bit Data-Width SRAM Connection 128K × 8-bit SRAM A16 A0 CS OE I/O7 I/O0 WE ... ... This LSI A16 ... A0 CSn RD D7 D0 WE0 ... Figure 7.8 Example of 8-Bit Data-Width SRAM Connection Rev. 1.00 Nov. 14, 2007 Page 228 of 1262 REJ09B0437-0100 •••• A0 CS OE I/O7 •••• D0 WE0 A16 •••• Section 7 Bus State Controller (BSC) 7.5.3 Access Wait Control Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible for areas 4 and 5 to insert wait cycles independently in read access and in write access. Areas 0, 3, and 6 have common access wait for read cycle and write cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access shown in figure 7.9. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.9 Wait Timing for Normal Space Access (Software Wait Only) Rev. 1.00 Nov. 14, 2007 Page 229 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 7.10. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle. Wait states inserted by WAIT signal Twx T2 T1 CKIO A25 to A0 CSn RD/WR RD Read Tw Tw D31 to D0 WEn Write D31 to D0 WAIT BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.10 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT Signal) Rev. 1.00 Nov. 14, 2007 Page 230 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.4 CSn Assert Period Expansion The number of cycles from CSn assertion to RD, WEn assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WEn negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 7.11 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WEn are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Th T1 T2 Tf CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.11 CSn Assert Period Expansion Rev. 1.00 Nov. 14, 2007 Page 231 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.5 (1) SDRAM Interface SDRAM Direct Connection The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMUU, DQMUL, DQMLU, DQMLL, CKE, and CS3. All the signals other than CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the SDRAM operating mode. Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals. These commands supports: • • • • • • • • • • • NOP Auto-refresh (REF) Self-refresh (SELF) All banks pre-charge (PALL) Specified bank pre-charge (PRE) Bank active (ACTV) Read (READ) Read with pre-charge (READA) Write (WRIT) Write with pre-charge (WRITA) Write mode register (MRS, EMRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx is low. For details on the relationship between DQMxx and the byte to be accessed, see section 7.5.1, Endian/Access Size and Data Alignment. Figures 7.12 to 7.13 show examples of the connection of the SDRAM with the LSI. Rev. 1.00 Nov. 14, 2007 Page 232 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) This LSI A15 • • • • 64M SDRAM (1M×16Bits×4Bank) A13 • • • • A2 CKE CKIO CSn A0 CKE CLK CS RAS CAS RD/WR D31 • • • • RAS CAS WE I/O15 • • • • D16 DQMUU DQMUL D15 • • • • I/O0 DQMU DQML D0 DQMLU DQMLL A13 A0 CKE CLK CS • • • • RAS CAS WE I/O15 • • • • I/O0 DQMU DQML Figure 7.12 Example of 32-Bit Data Width SDRAM Connection Rev. 1.00 Nov. 14, 2007 Page 233 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) This LSI A14 • • • • 64M SDRAM (1M×16Bits×4Bank) A13 • • • • A1 CKE CKIO CSn A0 CKE CLK CS RAS CAS RD/WR D15 • • • • RAS CAS WE I/O15 • • • • D0 DQMLU DQMLL I/O0 DQMU DQML Figure 7.13 Example of 16-Bit Data Width SDRAM Connection Rev. 1.00 Nov. 14, 2007 Page 234 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (2) Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0], and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 7.11 to 7.16 show the relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ1 and BSZ0 = B'10), A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ1 and BSZ0 = B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on. Rev. 1.00 Nov. 14, 2007 Page 235 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.11 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (1)-1 Setting BSZ[1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 00 (11 bits) Row Address Output A25 A24 A23 A22* * A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 2 3 A3COL[1:0] 00 (8 bits) Column Address Output A17 A16 A15 A22*2*3 A21* L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 SDRAM Pin Function Unused A12 (BA1) A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Specifies address/precharge Address Unused Example of connected memory 64-Mbit product (512 Kwords × 32 bits × 4 banks, column 8 bits product): 1 16-Mbit product (512 Kwords × 16 bits × 2 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Applicable only to 64-bit products. Rev. 1.00 Nov. 14, 2007 Page 236 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.11 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ[1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 01 (12 bits) Row Address Output A25 A24 A23*2 A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 A3COL[1:0] 00 (8 bits) Column Address Output A17 A16 A23*2 A22* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 128-Mbit product (1 Mword × 32 bits × 4 banks, column 8 bits product): 1 64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Applicable only to 64-bit products. Rev. 1.00 Nov. 14, 2007 Page 237 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.12 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (2)-1 Setting BSZ[1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 01 (12 bits) Row Address Output A26 A25 A24*2 A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A3COL[1:0] 01 (9 bits) Column Address Output A17 A16 A24*2 A23* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 256-Mbit product (2 Mwords × 32 bits × 4 banks, column 9 bits product): 1 128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 238 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.12 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (2)-2 Setting BSZ[1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 01 (12 bits) Row Address Output A27 A26 A25*2 A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 A3COL[1:0] 10 (10 bits) Column Address Output A17 A16 A25*2 A24* A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10 bits product): 1 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 239 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.13 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (3) Setting BSZ[1:0] 11 (32 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 10 (13 bits) Row Address Output A26 A25*2 A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A3COL[1:0] 01 (9 bits) Column Address Output A17 A25*2 A24* A14 A13 L/H* A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 512-Mbit product (4 Mwords × 32 bits × 4 banks, column 9 bits product): 1 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 240 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.14 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (4)-1 Setting BSZ[1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 00 (11 bits) Row Address Output A25 A24 A23 A22 A21* A20* A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 2 A3COL[1:0] 00 (8 bits) Column Address Output A17 A16 A15 A14 A21*2 A20* L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 SDRAM Pin Function Unused A12 (BA1) A11 (BA0) A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Specifies address/precharge Address Unused Example of connected memory 16-Mbit product (512 Kwords × 16 bits × 2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 241 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.14 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (4)-2 Setting BSZ[1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 01 (12 bits) Row Address Output A25 A24 A23 A22* A21* A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 2 2 A3COL[1:0] 00 (8 bits) Column Address Output A17 A16 A15 A22*2 A21* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 242 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.15 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (5)-1 Setting BSZ[1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 01 (12 bits) Row Address Output A26 A25 A24 A23* A22* A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 2 A3COL[1:0] 01 (9 bits) Column Address Output A17 A16 A15 A23*2 A22* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 243 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.15 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (5)-2 Setting BSZ[1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 01 (12 bits) Row Address Output A27 A26 A25 A24* A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 2 A3COL[1:0] 10 (10 bits) Column Address Output A17 A16 A15 A24*2 A23* A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A13 (BA1) A12 (BA0) A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 244 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.16 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (6)-1 Setting BSZ[1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 10 (13 bits) Row Address Output A26 A25 A24*2 A23* A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 2 A3COL[1:0] 01 (9 bits) Column Address Output A17 A16 A24*2 A23* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 245 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.16 Relationship between BSZ[1:0], A3ROW[1:0], A3COL[1:0], and Address Multiplex Output (6)-2 Setting BSZ[1:0] 10 (16 bits) Output Pin of This LSI A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A3ROW[1:0] 10 (13 bits) Row Address Output A27 A26 A25*2 A24* A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 2 A3COL[1:0] 10 (10 bits) Column Address Output A17 A16 A25*2 A24* A13 A12 L/H* A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 2 SDRAM Pin Function Unused A14 (BA1) A13 (BA0) A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Specifies bank Address Specifies address/precharge Address Unused Example of connected memory 512-Mbit product (8 Mwords × 16 bits × 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification Rev. 1.00 Nov. 14, 2007 Page 246 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (3) Burst Read A burst read occurs in the following cases with this LSI. • Access size in reading is larger than data bus width. • 16-byte transfer in cache miss. • 16-byte transfer by DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus. This access is called the burst read with the burst number 4. Table 7.17 shows the relationship between the access size and the number of bursts. Table 7.17 Relationship between Access Size and Number of Bursts Bus Width 16 bits Access Size 8 bits 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 32 bits 16 bytes* Number of Bursts 1 1 2 8 1 1 1 4 Rev. 1.00 Nov. 14, 2007 Page 247 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Figures 7.14 and 7.15 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM in variable frequencies. Figure 7.15 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and WTRCD0 bit in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read. Rev. 1.00 Nov. 14, 2007 Page 248 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde (Tap) CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.14 Burst Read Basic Timing (CAS Latency 1, Auto Pre-Charge) Rev. 1.00 Nov. 14, 2007 Page 249 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Trw Tc1 Tw Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tde (Tap) Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.15 Burst Read Wait Specification Timing (CAS Latency 2, WTRCD[1:0] = 1 Cycle, Auto Pre-Charge) Rev. 1.00 Nov. 14, 2007 Page 250 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (4) Single Read A read access ends in one cycle when data exists in a cache-disabled space and the data bus width is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst length 1, only the required data is output. A read access that ends in one cycle is called single read. Figure 7.16 shows the single read basic timing. Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Td1 Tde (Tap) Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.16 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge) Rev. 1.00 Nov. 14, 2007 Page 251 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (5) Burst Write A burst write occurs in the following cases in this LSI. • Access size in writing is larger than data bus width. • Write-back of the cache • 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus. This access is called burst write with the burst number 4. The relationship between the access size and the number of bursts is shown in table 7.17. Figure 7.17 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the auto-precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1 cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. Rev. 1.00 Nov. 14, 2007 Page 252 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Tc2 Tc3 Tc4 Trwl Tap Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.17 Basic Timing for Burst Write (Auto Pre-Charge) Rev. 1.00 Nov. 14, 2007 Page 253 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (6) Single Write A write access ends in one cycle when data is written in a cache-disabled space and the data bus width is larger than or equal to access size. As a single write or burst write with burst length 1 is set in SDRAM, only the required data is output. The write access that ends in one cycle is called single write. Figure 7.18 shows the single write basic timing. Tr CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Trwl Tap Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.18 Single Write Basic Timing (Auto-Precharge) Rev. 1.00 Nov. 14, 2007 Page 254 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (7) Bank Active The SDRAM bank function can be used to support high-speed access to the same row address. When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge (READ or WRIT). This function is called bank-active function. This function is valid only for either the upper or lower bits of area 3. When area 3 is set to SDRAM, auto precharge mode must be set. When the bank-active function is used, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As SDRAM is internally divided into several banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tRAS. A burst read cycle without auto-precharge is shown in figure 7.19, a burst read cycle for the same row address in figure 7.20, and a burst read cycle for different row addresses in figure 7.21. Similarly, a burst write cycle without auto-precharge is shown in figure 7.22, a burst write cycle for the same row address in figure 7.23, and a burst write cycle for different row addresses in figure 7.24. In figure 7.20, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle. Rev. 1.00 Nov. 14, 2007 Page 255 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) When bank active mode is set, if only access cycles to the respective banks in the area 3 space are considered, as long as access cycles to the same row address continue, the operation starts with the cycle in figure 7.19 or 7.22, followed by repetition of the cycle in figure 7.20 or 7.23. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 7.21 or 7.24 is executed instead of that in figure 7.20 or 7.23. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Td1 Tc2 Tr Tc1 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.19 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1) Rev. 1.00 Nov. 14, 2007 Page 256 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tnop Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.20 Burst Read Timing (Bank Active, Same Row Addresses in the Same Bank, CAS Latency 1) Rev. 1.00 Nov. 14, 2007 Page 257 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tp Tpw Tr Tc1 Td1 Tc2 Td2 Tc3 Td3 Tc4 Td4 Tde CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.21 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) Rev. 1.00 Nov. 14, 2007 Page 258 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tr CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tc1 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.22 Single Write Timing (Bank Active, Different Bank) Rev. 1.00 Nov. 14, 2007 Page 259 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tnop Tc1 CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.23 Single Write Timing (Bank Active, Same Row Addresses in the Same Bank) Rev. 1.00 Nov. 14, 2007 Page 260 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tp CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Tr Tc1 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.24 Single Write Timing (Bank Active, Different Row Addresses in the Same Bank) Rev. 1.00 Nov. 14, 2007 Page 261 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (8) Refreshing This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. (a) Auto-refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an autorefresh is performed for the number of times specified by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 7.25 shows the auto-refresh cycle timing. After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks to pre-charged state from active state when some bank is being pre-charged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle. Rev. 1.00 Nov. 14, 2007 Page 262 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tp Tpw Trr Trc Trc Trc CKIO A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Hi-z Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.25 Auto-Refresh Timing Rev. 1.00 Nov. 14, 2007 Page 263 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (b) Self-refreshing Self-refresh mode in which the refresh timing and refresh addresses are generated within the SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WSR. SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR. Self-refresh timing is shown in figure 7.26. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the LSI standby function, and is maintained even after recovery from standby mode due to an interrupt. Note that the necessary signals such as CKE must be driven even in standby state by setting the HIZCNT bit in CMNCR to 1. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Rev. 1.00 Nov. 14, 2007 Page 264 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tp CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Tpw Trr Trc Trc Trc Hi-z Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.26 (9) Self-Refresh Timing Relationship between Refresh Requests and Bus Cycles If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval must be prevented from occurring. Rev. 1.00 Nov. 14, 2007 Page 265 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (10) Power-Down Mode If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle is needed to assert the CKE in order to cancel the power-down mode. Figure 7.27 shows the access timing in power-down mode. Power-down CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS Tnop Tr Tc1 Td1 Tde Tap Power-down DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 7.27 Power-Down Mode Access Timing Rev. 1.00 Nov. 14, 2007 Page 266 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (11) Power-On Sequence In order to use SDRAM, mode setting must first be made for SDRAM after waiting for 100 µs or a longer period after powering on. This 100-µs or longer period should be obtained by a power-on reset generating circuit or software. To perform SDRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a write to address H'FFFC5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access to the addresses shown in table 7.18. In this time 0 is output at the external address pins of A12 or later. Table 7.18 Access Address in SDRAM Mode Register Write • Setting for Area 3 Burst read/single write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'FFFC5440 H'FFFC5460 H'FFFC5880 H'FFFC58C0 External Address Pin H'0000440 H'0000460 H'0000880 H'00008C0 Burst read/burst write (burst length 1): Data Bus Width 16 bits CAS Latency 2 3 32 bits 2 3 Access Address H'FFFC5040 H'FFFC5060 H'FFFC5080 H'FFFC50C0 External Address Pin H'0000040 H'0000060 H'0000080 H'00000C0 Rev. 1.00 Nov. 14, 2007 Page 267 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Mode register setting timing is shown in figure 7.28. A PALL command (all bank pre-charge command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer than the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. Tp PALL Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop CKIO A25 to A0 A12/A11*1 CSn RASL, RASU CASL, CASU RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Hi-Z Figure 7.28 SDRAM Mode Write Timing (Based on JEDEC) Rev. 1.00 Nov. 14, 2007 Page 268 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (12) Low-Power SDRAM The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The differences between the low-power SDRAM and normal SDRAM are that partial refresh takes place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. The partial refresh is effective in systems in which there is data in a work area other than the specific area can be lost without severe repercussions. The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode registers as the normal SDRAM. This LSI supports issuing of the EMRS command. The EMRS command is issued according to the conditions specified in table below. For example, if data H'0YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> REF × 8 -> MRS -> EMRS. In this case, the MRS and EMRS issue addresses are H'0000XX0 and H'YYYYYYY, respectively. If data H'1YYYYYYY is written to address H'FFFC5XX0 in longword, the commands are issued to the CS3 space in the following sequence: PALL -> MRS -> EMRS. Table 7.19 Output Addresses when EMRS Command Is Issued Command to be Issued CS3 MRS CS3 MRS + EMRS (with refresh) CS3 MRS + EMRS (without refresh) H'FFFC5XX0 H'1YYYYYYY 32 bits H'0000XX0 H'YYYYYYY Access Address H'FFFC5XX0 H'FFFC5XX0 Write Access Size 16 bits MRS EMRS Command Command Issue Address Issue Address H'0000XX0 H'0000XX0  H'YYYYYYY Access Data H'******** H'0YYYYYYY 32 bits Rev. 1.00 Nov. 14, 2007 Page 269 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tp PALL Tpw Trr REF Trc Trc Trr REF Trc Trc Tmw MRS Tnop Temw EMRS Tnop CKIO A25 to A0 BA1*1 BA0*2 A12/A11*3 CSn RAS CAS RD/WR DQMxx D31 to D0 BS Hi-Z DACKn*4 Notes: 1. Address pin to be connected to pin BA1 of SDRAM. 2. Address pin to be connected to pin BA0 of SDRAM. 3. Address pin to be connected to pin A10 of SDRAM. 4. The waveform for DACKn is when active low is specified. Figure 7.29 EMRS Command Issue Timing Rev. 1.00 Nov. 14, 2007 Page 270 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) • Deep power-down mode The low-power SDRAM supports the deep power-down mode as a low-power consumption mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the deep power-down mode, self-refresh will not be performed on any memory area. This mode is effective in systems where all of the system memory areas are used as work areas. If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0, the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed. Tp CKIO CKE A25 to A0 A12/A11*1 CSn RAS CAS RD/WR DQMxx D31 to D0 BS DACKn*2 Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Tpw Trr Trc Trc Trc Hi-z Figure 7.30 Deep Power-Down Mode Transition Timing Rev. 1.00 Nov. 14, 2007 Page 271 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.6 SRAM Interface with Byte Selection The SRAM interface with byte selection is for access to an SRAM which has a byte-selection pin (WEn). This interface has 16-bit data pins and accesses SRAMs having upper and lower byte selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte selection is the same as that for the normal space interface. While in read access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin, which is different from that for the normal space interface. The basic access timing is shown in figure 7.31. In write access, data is written to the memory according to the timing of the byteselection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 7.32 shows the basic access timing. In write access, data is written to the memory according to the timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 7.33 shows the access timing when a software wait is specified. Rev. 1.00 Nov. 14, 2007 Page 272 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) T1 T2 CKIO A25 to A0 CSn WEn RD/WR RD Read D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.31 Basic Access Timing for SRAM with Byte Selection (BAS = 0) Rev. 1.00 Nov. 14, 2007 Page 273 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) T1 CKIO T2 A25 to A0 CSn WEn RD/WR RD Read D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.32 Basic Access Timing for SRAM with Byte Selection (BAS = 1) Rev. 1.00 Nov. 14, 2007 Page 274 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Th CKIO T1 Tw T2 Tf A25 to A0 CSn WEn RD/WR RD Read D31 to D0 RD/WR High Write RD D31 to D0 BS DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 7.33 Wait Timing for SRAM with Byte Selection (BAS = 1) (SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01) Rev. 1.00 Nov. 14, 2007 Page 275 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) This LSI 64K × 16-bit SRAM A17 ... A15 ... A2 CSn RD RD/WR D31 ... A0 CS OE WE I/O15 I/O0 UB LB ... D16 WE3 WE2 D15 ... A15 A0 CS OE WE I/O15 I/O0 UB LB ... ... This LSI A16 . . . A1 CSn RD RD/WR D15 . . . D0 WE1 WE0 64K × 16-bit SRAM D0 WE1 WE0 Figure 7.34 Example of Connection with 32-Bit Data-Width SRAM with Byte Selection A15 . . . A0 CS OE WE I/O 15 . . . I/O 0 UB LB Figure 7.35 Example of Connection with 16-Bit Data-Width SRAM with Byte Selection Rev. 1.00 Nov. 14, 2007 Page 276 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.7 PCMCIA Interface With this LSI, areas 5 and 6 can be used for the IC memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1 Rev. 2.1) by specifying bits TYPE[2:0] in CSnBCR (n = 5 and 6) to B'101. In addition, the bits SA[1:0] in CSnWCR (n = 5 and 6) assign the upper or lower 32 Mbytes of each area to IC memory card or I/O card interface. For example, if the bits SA1 and SA0 in CS5WCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes of area 5 are used for IC memory card interface and the lower 32 Mbytes are used for I/O card interface. When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the bits BSZ[1:0] in CS5BCR or CS6BCR. Figure 7.36 shows an example of connection between this LSI and a PCMCIA card. To enable hot swapping (insertion and removal of the PCMCIA card with the system power turned on), tri-state buffers must be connected between the LSI and the PCMCIA card. In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined. Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI. Rev. 1.00 Nov. 14, 2007 Page 277 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) This LSI A25 to A0 D7 to D0 D15 to D8 RD/WR CS5B/CE1A CE2A G DIR G PC card (memory or I/O) A25 to A0 D7 to D0 D15 to D8 G DIR CE1 CE2 RD WE1/WE WE2/ICIORD WE3/ICIOWR REG (Output port) G OE WE/PGM IORD IOWR REG WAIT IOIS16 Card detector WAIT IOIS16 CD1, CD2 Figure 7.36 Example of PCMCIA Interface Connection Rev. 1.00 Nov. 14, 2007 Page 278 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (1) Basic Timing for Memory Card Interface Figure 7.37 shows the basic timing of the PCMCIA IC memory card interface. When areas 5 and 6 are specified as the PCMCIA interface, the bus is accessed with the IC memory card interface according to the SA[1:0] bit settings in CS5WCR and CS6WCR. If the external bus frequency (CKIO) increases, the setup times and hold times for the address pins (A25 to A0), card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this LSI enables the setup times and hold times for areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware wait using the WAIT pin can be inserted. Figure 7.38 shows the PCMCIA memory bus wait timing. Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS Figure 7.37 Basic Access Timing for PCMCIA Memory Card Interface Rev. 1.00 Nov. 14, 2007 Page 279 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR RD Read D15 to D0 WE Write D15 to D0 BS WAIT Figure 7.38 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1) A port is used to generate the REG signal that switches between the common memory and attribute memory. As shown in the example in figure 7.39, when the total memory space necessary for the common memory and attribute memory is 32 Mbytes or less, pin A24 can be used as the REG signal to allocate a 16-Mbyte common memory space and a 16-Mbyte attribute memory space. Rev. 1.00 Nov. 14, 2007 Page 280 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) In case of 32Mbyts capacity (REG = I/O port is used) Area 5: H'14000000 Attribute memory/Common memory Area 5: H'16000000 I/O Space Area 6: H'18000000 Attribute memory/Common memory Area 6: H'1A000000 I/O Space In case of 16Mbyts capacity (REG = A24 is used) Area 5: H'14000000 Area 5: H'15000000 Area 5: H'16000000 H'17000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Attribute memory Common memory I/OSpace Attribute memory Common memory I/OSpace Figure 7.39 Example of PCMCIA Space Allocation (CS5WCR.SA[1:0] = B'10, CS6WCR.SA[1:0] = B'10) Rev. 1.00 Nov. 14, 2007 Page 281 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (2) Basic Timing for I/O Card Interface Figures 7.40 and 7.41 show the basic timing for the PCMCIA I/O card interface. When accessing an I/O card through the PCMCIA interface, be sure to access the space as cachedisabled. Switching between I/O card and IC memory card interfaces in the respective address spaces is accomplished by the SA[1:0] bit settings in CS5WCR and CS6WCR. The IOIS16 pin can be used for dynamic adjustment of the width of the I/O bus in access to an I/O card via the PCMCIA interface when little endian mode has been selected. When the bus width of area 5 or 6 is set to 16 bits and the IOIS16 signal is driven high during a cycle of word-unit access to the I/O card bus, the bus width will be recognized as 8 bits and only 8 bits of data will be accessed during the current cycle of the I/O card bus. Operation will automatically continue with access to the remaining 8 bits of data. The IOIS16 signal is sampled on falling edges of the CKIO in Tpci0 as well as all Tpci0w cycles for which the TED3 to TED0 bits are set to 1.5 cycles or more, and the CE2A and CE2B signals are updated after 1.5 cycles of the CKIO signal from the sampling point of Tpci0. Ensure that the IOIS16 signal is defined at all sampling points and does not change along the way. Set the TED3 to TED0 bits to satisfy the requirement of the PC card in use with regard to setup timing from ICIORD or ICIOWR to CE1 or CE2. The basic waveforms for dynamic bus-size adjustment are shown in figure 7.41. Since the IOIS16 signal is not supported in big endian mode, the IOIS16 signal should be fixed to the low level when big endian mode has been selected. Rev. 1.00 Nov. 14, 2007 Page 282 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS Figure 7.40 Tpci0 Tpci0w Basic Access Timing for PCMCIA I/O Card Interface Tpci1w Tpci1 Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CE1x CE2x RD/WR ICIORD Read D15 to D0 ICIOWR Write D15 to D0 BS WAIT IOIS16 Figure 7.41 Dynamic Bus-Size Adjustment Timing for PCMCIA I/O Card Interface (TED[3:0] = B'0010, PCW[3:0] = B'0000, TEH[3:0] = B'0001, Hardware Wait = 1) Rev. 1.00 Nov. 14, 2007 Page 283 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.8 Wait between Access Cycles As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting idle (wait) cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by the WM bit in CSnWCR, bits IWW2 to IWW0, IWRWD2 to IWRWD0, IWRWS2 to IWRWS0, IWRRD2 to IWRRD0, and IWRRS2 to IWRRS 0 in CSnBCR, and bits DMAIW2 to DMAIW0 and DMAIWA in CMNCR. The conditions for setting the idle cycles between access cycles are shown below. 1. 2. 3. 4. 5. 6. Continuous access cycles are write-read or write-write Continuous access cycles are read-write for different spaces Continuous access cycles are read-write for the same space Continuous access cycles are read-read for different spaces Continuous access cycles are read-read for the same space Data output from an external device caused by DMA single address transfer is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output from an external device caused by DMA single address transfer is followed by any type of access (DMAIWA = 1) For the specification of the number of idle cycles between access cycles described above, refer to the description of each register. Besides the idle cycles between access cycles specified by the registers, idle cycles must be inserted to interface with the internal bus or to obtain the minimum pulse width for a multiplexed pin (WEn). The following gives detailed information about the idle cycles and describes how to estimate the number of idle cycles. The number of idle cycles on the external bus from CSn negation to CSn or CSm assertion is described below. Here, CSn and CSm also include CE2A and CE2B for PCMCIA. There are eight conditions that determine the number of idle cycles on the external bus as shown in table 7.20. The effects of these conditions are shown in figure 7.42. Rev. 1.00 Nov. 14, 2007 Page 284 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.20 Conditions for Determining Number of Idle Cycles No. Condition [1] DMAIW[2:0] in CMNCR Description Range Note When 0 is specified for the number of idle cycles, the DACK signal may be asserted continuously. This causes a discrepancy between the number of cycles detected by the device with DACK and the DMAC transfer count, resulting in a malfunction. Do not set 0 for the number of idle cycles between memory types which are not allowed to be accessed successively. These bits specify the number of 0 to 12 idle cycles for DMA single address transfer. This condition is effective only for single address transfer and generates idle cycles after the access is completed. [2] IW***[2:0] in CSnBCR These bits specify the number of 0 to 12 idle cycles for access other than single address transfer. The number of idle cycles can be specified independently for each combination of the previous and next cycles. For example, in the case where reading CS3 space followed by reading other CS space, the bits IWRRD[2:0] in CS3BCR should be set to B'100 to specify six or more idle cycles. This condition is effective only for access cycles other than single address transfer and generates idle cycles after the access is completed. [3] SDRAM-related These bits specify precharge 0 to 3 bits in completion and startup wait cycles CSnWCR and idle cycles between commands for SDRAM access. This condition is effective only for SDRAM access and generates idle cycles after the access is completed WM in CSnWCR This bit enables or disables external 0 or 1 WAIT pin input for the memory types other than SDRAM. When this bit is cleared to 0 (external WAIT enabled), one idle cycle is inserted to check the external WAIT pin input after the access is completed. When this bit is set to 1 (disabled), no idle cycle is generated. Specify these bits in accordance with the specification of the target SDRAM. [4] Rev. 1.00 Nov. 14, 2007 Page 285 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) No. Condition [5] Read data transfer cycle Description Range Note One idle cycle is always generated after a read cycle with SDRAM or PCMCIA interface. One idle cycle is inserted after a 0 or 1 read access is completed. This idle cycle is not generated for the first or middle cycles in divided access cycles. This is neither generated when the HM[1:0] bits in CSnWCR are not B'00. [6] Internal bus External bus access requests from 0 or idle cycles, etc. the CPU or DMAC and their results larger are passed through the internal bus. The external bus enters idle state during internal bus idle cycles or while a bus other than the external bus is being accessed. This condition is not effective for divided access cycles, which are generated by the BSC when the access size is larger than the external data bus width. Write data wait During write access, a write cycle is 0 or 1 cycles executed on the external bus only after the write data becomes ready. This write data wait period generates idle cycles before the write cycle. Note that when the previous cycle is a write cycle and the internal bus idle cycles are shorter than the previous write cycle, write data can be prepared in parallel with the previous write cycle and therefore, no idle cycle is generated (write buffer effect). Idle cycles between different memory types The number of internal bus idle cycles may not become 0 depending on the Iφ:Bφ clock ratio. Tables 7.21 and 7.22 show the relationship between the clock ratio and the minimum number of internal bus idle cycles. [7] For write → write or write → read access cycles, successive access cycles without idle cycles are frequently available due to the write buffer effect described in the left column. If successive access cycles without idle cycles are not allowed, specify the minimum number of idle cycles between access cycles through CSnBCR. [8] To ensure the minimum pulse width 0 to 2.5 The number of idle cycles on the signal-multiplexed pins, idle depends on the target memory cycles may be inserted before types. See table 7.23. access after memory types are switched. For some memory types, idle cycles are inserted even when memory types are not switched. Rev. 1.00 Nov. 14, 2007 Page 286 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) In the above conditions, a total of four conditions, that is, condition [1] or [2] (either one is effective), condition [3] or [4] (either one is effective), a set of conditions [5] to [7] (these are generated successively, and therefore the sum of them should be taken as one set of idle cycles), and condition [8] are generated at the same time. The maximum number of idle cycles among these four conditions become the number of idle cycles on the external bus. To ensure the minimum idle cycles, be sure to make register settings for condition [1] or [2]. CKIO Previous access External bus idle cycles Next access CSn Idle cycle after access Idle cycle before access [1] DMAIW[2:0] setting in CMNCR [2] IWW[2:0] setting in CSnBCR IWRWD[2:0] setting in CSnBCR IWRWS[2:0] setting in CSnBCR IWRRD[2:0] setting in CSnBCR IWRRS[2:0] setting in CSnBCR [3] WTRP[1:0] setting in CSnWCR TRWL[1:0] setting in CSnWCR WTRC[1:0] setting in CSnWCR [4] WM setting in CSnWCR [5] Read data transfer [7] Write data wait Either one of them is effective Condition [1] or [2] Either one of them is effective Condition [3] or [4] [6] Internal bus idle cycles, etc. Set of conditions [5] to [7] [8] Idle cycles between Condition [8] different memory types Note: A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7], and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of cycles among these four conditions become the number of idle cycles. Figure 7.42 Idle Cycle Conditions Rev. 1.00 Nov. 14, 2007 Page 287 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Table 7.21 Minimum Number of Idle Cycles on Internal Bus (CPU Operation) Clock Ratio (Iφ:Bφ) CPU Operation Write → write Write → read Read → write Read → read 8:1 1 0 1 0 6:1 1 0 1 0 4:1 2 0 2 0 3:1 2 0 2 0 2:1 2 0 2 0 1:1 3 1 3 1 Table 7.22 Minimum Number of Idle Cycles on Internal Bus (DMAC Operation) Transfer Mode DMAC Operation Write → write Write → read Read → write Read → read Dual Address 0 0 or 2 0 0 Single Address 2 0 0 2 Notes: 1. The write → write and read → read columns in dual address transfer indicate the cycles in the divided access cycles. 2. For the write → read cycles in dual address transfer, 0 means different channels are activated successively and 2 means when the same channel is activated successively. 3. The write → read and read → write columns in single address transfer indicate the case when different channels are activated successively. The "write" means transfer from a device with DACK to external memory and the "read" means transfer from external memory to a device with DACK. Table 7.23 Number of Idle Cycles Inserted between Access Cycles to Different Memory Types Next Cycle Previous Cycle SRAM Byte SRAM (BAS = 0) Byte SRAM (BAS = 1) SDRAM PCMCIA SRAM 0 0 1 1 0 Byte SRAM (BAS = 0) 0 0 1 1 0 Byte SRAM (BAS = 1) 1 1 0 0 1 SDRAM 1 1 0 0 1 PCMCIA 0 0 1 1 0 Rev. 1.00 Nov. 14, 2007 Page 288 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) Figure 7.43 shows sample estimation of idle cycles between access cycles. In the actual operation, the idle cycles may become shorter than the estimated value due to the write buffer effect or may become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU instruction execution or CPU register conflicts. Please consider these errors when estimating the idle cycles. Sample estimation of the number of idle clock cycles (states) between cycles of bus access We consider CPU access for the transfer of data from the CS5 to the CS6 space. For this transfer, the sequence read from CS5 →read from CS5 →write to CS6→write to CS6 ... is repeated. • Condition 0 is specified as the number of idle cycles between CS5BCR and CS6BCR. WM bit in CS5WCR and CS6WCR = 1 (external WAIT_ pin disabled) HW[1:0] = 00 (no delay of CS negation) If:Bf= 4:1 No other processing proceeds during the transfer. CS5 and CS6 are connected to SRAM for access in 32-bit units by a 32-bit-wide bus. The items that decide the number of idle cycles are estimated for the different transitions on between bus cycles. R indicates reading and W indicates writing in the table below. Item (1)/(2) (3)/(4) (5) (6) (7) (5)+(6)+(7) (8) Estimated number of idle cycles Actual number of idle cycles R→R 0 0 1 0 0 1 0 1 R→W 0 0 1 2 1 4 0 4 W→W 0 0 0 2 0 2 0 2 W→R 0 0 0 0 0 0 0 0 Due to SRAM→SRAM Maximum value among (1)/(2), (3)/(4), (5)+(6)+(7), and (8) The mismatch in the case of W→R is because the estimate of the number of idle cycles for item (6) was zero. Since a loop-decision instruction is actually executed here, an idle cycle is generated internally. Since CSnBCR is set to 0 When the WM bit is set to 1 Generated after the read cycle See the description for If:Bf= 4:1 in table 7.21. The effect of the write buffer is that idle cycles are not generated the second time. Note 1 4 2 1 Figure 7.43 Comparison between Estimated Idle Cycles and Actual Value Rev. 1.00 Nov. 14, 2007 Page 289 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) 7.5.9 (1) Others Reset The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state after the internal reset is synchronized with the internal clock. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. (2) Access from the Side of the LSI Internal Bus Master There are three types of LSI internal buses: a CPU bus, internal bus, and peripheral bus. The CPU and cache memory are connected to the CPU bus. Internal bus masters other than the CPU and bus state controller are connected to the internal bus. Low-speed peripheral modules are connected to the peripheral bus. Internal memories other than the cache memory are connected bidirectionally to the CPU bus and internal bus. Access from the CPU bus to the internal bus is enabled but access from the internal bus to the cache bus is disabled. This gives rise to the following problems. On-chip bus masters such as DMAC other than the CPU can access internal memory other than the cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU writes data to an external memory other than the cache, the contents of the external memory may differ from that of the cache memory. To prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the CPU, the corresponding cache memory should be purged by software. In a cache-enabled space, if the CPU initiates read access, the cache is searched. If the cache stores data, the CPU latches the data and completes the read access. If the cache does not store data, the CPU performs four contiguous longword read cycles to perform cache fill operations via the internal bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary (4n + 2), the CPU performs four contiguous longword access cycles to perform a cache fill operation on the external interface. For a cache-disabled space, the CPU performs access according to the actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs word access. For a read cycle of an on-chip peripheral module, the cycle is initiated through the internal bus and peripheral bus. The read data is sent to the CPU via the peripheral bus, internal bus, and CPU bus. Rev. 1.00 Nov. 14, 2007 Page 290 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) In a write cycle for the cache-enabled space, the write cycle operation differs according to the cache write methods. In write-back mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written until data in the corresponding address is re-written. If data is not detected at the address corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. Following these operations, a write-back cycle for the saved 16-byte data is executed. In write-through mode, the cache is first searched. If data is detected at the address corresponding to the cache, the data is re-written to the cache simultaneously with the actual write via the internal bus. If data is not detected at the address corresponding to the cache, the cache is not modified but an actual write is performed via the internal bus. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the internal bus before the previous external bus cycle is completed in a write cycle. If the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. The write buffer of the BSC functions in the same way for an access by a bus master other than the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. Changing the registers in the BSC while the write buffer is operating may disrupt correct write access. Therefore, do not change the registers in the BSC immediately after a write access. If this change becomes necessary, do it after executing a dummy read of the write data. In this LSI, the priority level applicable when there is a request for bus mastership for the internal bus from any of the internal bus masters excluding the CPU (that is, A-DMAC (including FDMAC), E-DMAC, and DMAC) can be set in the register. When changing the priority level, rewrite the register after making sure that none of the A-DMAC (including F-DMAC), E-DMAC, and DMAC is started. Rev. 1.00 Nov. 14, 2007 Page 291 of 1262 REJ09B0437-0100 Section 7 Bus State Controller (BSC) (3) On-Chip Peripheral Module Access To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are required. Care must be taken in system design. When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding instructions without waiting for the completion of writing to registers. For example, a case is described here in which the system is transferring to the software standby mode for power savings. To make this transition, the SLEEP instruction must be performed after setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR register is indispensable to complete writing to the STBY bit. To reflect the change by internal peripheral registers while performing the succeeding instructions, execute a dummy read of registers to which write instruction is given and then perform the succeeding instructions. Rev. 1.00 Nov. 14, 2007 Page 292 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Section 8 Direct Memory Access Controller (DMAC) The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules. 8.1 Features • Number of channels: Eight channels (channels 0 to 7) selectable Two channels (channels 0 and 1) can receive external requests. • 4-Gbyte physical address space • Data transfer unit is selectable: Byte, word (two bytes), longword (four bytes), and 16 bytes (longword × 4) • Maximum transfer count: 16,777,216 transfers (24 bits) • Address mode: Dual address mode and single address mode are supported. • Transfer requests  External request  On-chip peripheral module request  Auto request The following modules can issue on-chip peripheral module requests.  Six SCIF sources, two IIC3 sources, two CMT sources, two SSI sources, and two SDHI sources • Selectable bus modes  Cycle steal mode (normal mode and intermittent mode)  Burst mode • Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode. • Interrupt request: An interrupt request can be sent to the CPU on completion of half- or fulldata transfer. Through the HE and HIE bits in CHCR, an interrupt is specified to be issued to the CPU when half of the initially specified DMA transfer is completed. • External request detection: There are following four types of DREQ input detection.  Low level detection  High level detection  Rising edge detection  Falling edge detection Rev. 1.00 Nov. 14, 2007 Page 293 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) • Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND can be set independently. • Support of reload functions in DMA transfer information registers: DMA transfer using the same information as the current transfer can be repeated automatically without specifying the information again. Modifying the reload registers during DMA transfer enables next DMA transfer to be done using different transfer information. The reload function can be enabled or disabled in each channel and in each reload register. Rev. 1.00 Nov. 14, 2007 Page 294 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Figure 8.1 shows the block diagram of the DMAC. RDMATCR_n On-chip memory On-chip peripheral module Iteration control Register control Peripheral bus Internal bus DMATCR_n RSAR_n SAR_n Start-up control RDAR_n DAR_n CHCR_n DMA transfer request signal DMA transfer acknowledge signal Interrupt controller HEIn DEIn Request priority control DMAOR DMARS0 to DMARS3 External ROM External RAM External device (memory mapped) Bus interface DMAC module External device (with acknowledge) Bus state controller DREQ0 to DREQ3 DACK0 to DACK3, TEND0, TEND1 [Legend] RDMATCR: DMA reload transfer count register DMATCR: DMA transfer count register DMA reload source address register RSAR: DMA source address register SAR: DMA reload destination address register RDAR: DMA destination address register DAR: DMA channel control register CHCR: DMA operation register DMAOR: DMARS0 to DMARS3: DMA extension resource selectors 0 to 3 DMA transfer half-end interrupt request to the CPU HEIn: DMA transfer end interrupt request to the CPU DEIn: n = 0 to 7 Figure 8.1 Block Diagram of DMAC Rev. 1.00 Nov. 14, 2007 Page 295 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.2 Input/Output Pins The external pins for DMAC are described below. Table 8.1 lists the configuration of the pins that are connected to external bus. DMAC has pins for two channels (channels 0 and 1) for external bus use. Table 8.1 Pin Configuration Abbreviation I/O I O Function DMA transfer request input from an external device to channel 0 DMA transfer request acknowledge output from channel 0 to an external device DMA transfer request input from an external device to channel 1 DMA transfer request acknowledge output from channel 1 to an external device DMA transfer end output for channel 0 DMA transfer end output for channel 1 Channel Name 0 DMA transfer request DREQ0 DMA transfer request DACK0 acknowledge 1 DMA transfer request DREQ1 DMA transfer request DACK1 acknowledge I O 0 1 DMA transfer end DMA transfer end TEND0 TEND1 O O Rev. 1.00 Nov. 14, 2007 Page 296 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3 Register Descriptions The DMAC has the registers listed in table 8.2. There are four control registers and three reload registers for each channel, and one common control register is used by all channels. In addition, there is one extension resource selector per two channels. Each channel number is expressed in the register names, as in SAR_0 for SAR in channel 0. Table 8.2 Channel 0 Register Configuration Register Name DMA source address register_0 DMA destination address register_0 DMA transfer count register_0 DMA channel control register_0 DMA reload source address register_0 Abbreviation R/W SAR_0 DAR_0 DMATCR_0 CHCR_0 RSAR_0 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1000 H'FFFE1004 H'FFFE1008 H'FFFE100C H'FFFE1100 H'FFFE1104 H'FFFE1108 H'FFFE1010 H'FFFE1014 H'FFFE1018 H'FFFE101C H'FFFE1110 H'FFFE1114 H'FFFE1118 Access Size 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_0 address register_0 DMA reload transfer count register_0 1 DMA source address register_1 DMA destination address register_1 DMA transfer count register_1 DMA channel control register_1 DMA reload source address register_1 RDMATCR_0 R/W SAR_1 DAR_1 DMATCR_1 CHCR_1 RSAR_1 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_1 address register_1 DMA reload transfer count register_1 RDMATCR_1 R/W Rev. 1.00 Nov. 14, 2007 Page 297 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Channel 2 Register Name DMA source address register_2 DMA destination address register_2 DMA transfer count register_2 DMA channel control register_2 DMA reload source address register_2 Abbreviation R/W SAR_2 DAR_2 DMATCR_2 CHCR_2 RSAR_2 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1020 H'FFFE1024 H'FFFE1028 H'FFFE102C H'FFFE1120 H'FFFE1124 H'FFFE1128 H'FFFE1030 H'FFFE1034 H'FFFE1038 H'FFFE103C H'FFFE1130 H'FFFE1134 H'FFFE1138 Access Size 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_2 address register_2 DMA reload transfer count register_2 3 DMA source address register_3 DMA destination address register_3 DMA transfer count register_3 DMA channel control register_3 DMA reload source address register_3 RDMATCR_2 R/W SAR_3 DAR_3 DMATCR_3 CHCR_3 RSAR_3 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_3 address register_3 DMA reload transfer count register_3 RDMATCR_3 R/W Rev. 1.00 Nov. 14, 2007 Page 298 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Channel 4 Register Name DMA source address register_4 DMA destination address register_4 DMA transfer count register_4 DMA channel control register_4 DMA reload source address register_4 Abbreviation R/W SAR_4 DAR_4 DMATCR_4 CHCR_4 RSAR_4 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1040 H'FFFE1044 H'FFFE1048 H'FFFE104C H'FFFE1140 H'FFFE1144 H'FFFE1148 H'FFFE1050 H'FFFE1054 H'FFFE1058 H'FFFE105C H'FFFE1150 H'FFFE1154 H'FFFE1158 Access Size 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_4 address register_4 DMA reload transfer count register_4 5 DMA source address register_5 DMA destination address register_5 DMA transfer count register_5 DMA channel control register_5 DMA reload source address register_5 RDMATCR_4 R/W SAR_5 DAR_5 DMATCR_5 CHCR_5 RSAR_5 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_5 address register_5 DMA reload transfer count register_5 RDMATCR_5 R/W Rev. 1.00 Nov. 14, 2007 Page 299 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Channel 6 Register Name DMA source address register_6 DMA destination address register_6 DMA transfer count register_6 DMA channel control register_6 DMA reload source address register_6 Abbreviation R/W SAR_6 DAR_6 DMATCR_6 CHCR_6 RSAR_6 R/W R/W R/W Initial Value H'00000000 H'00000000 H'00000000 Address H'FFFE1060 H'FFFE1064 H'FFFE1068 H'FFFE106C H'FFFE1160 H'FFFE1164 H'FFFE1168 H'FFFE1070 H'FFFE1074 H'FFFE1078 H'FFFE107C H'FFFE1170 H'FFFE1174 H'FFFE1178 Access Size 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 16, 32 8, 16, 32 16, 32 16, 32 16, 32 R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_6 address register_6 DMA reload transfer count register_6 7 DMA source address register_7 DMA destination address register_7 DMA transfer count register_7 DMA channel control register_7 DMA reload source address register_7 RDMATCR_6 R/W SAR_7 DAR_7 DMATCR_7 CHCR_7 RSAR_7 R/W R/W R/W R/W*1 H'00000000 R/W R/W H'00000000 H'00000000 H'00000000 DMA reload destination RDAR_7 address register_7 DMA reload transfer count register_7 RDMATCR_7 R/W Rev. 1.00 Nov. 14, 2007 Page 300 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Channel Common 0 and 1 2 and 3 4 and 5 6 and 7 Register Name Abbreviation R/W Initial Value Address H'FFFE1200 H'FFFE1300 H'FFFE1304 H'FFFE1308 H'FFFE130C Access Size 8, 16 16 16 16 16 DMA operation register DMAOR DMA extension resource selector 0 DMA extension resource selector 1 DMA extension resource selector 2 DMA extension resource selector 3 DMARS0 DMARS1 DMARS2 DMARS3 R/W*2 H'0000 R/W R/W R/W R/W H'0000 H'0000 H'0000 H'0000 Notes: 1. For the HE and TE bits in CHCRn, only 0 can be written to clear the flags after 1 is read. 2. For the AE and NMIF bits in DMAOR, only 0 can be written to clear the flags after 1 is read. 8.3.1 DMA Source Address Registers (SAR) The DMA source address registers (SAR) are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data of an external device with DACK is transferred in single address mode, SAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 301 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.2 DMA Destination Address Registers (DAR) The DMA destination address registers (DAR) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data of an external device with DACK is transferred in single address mode, DAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 8.3.3 DMA Transfer Count Registers (DMATCR) The DMA transfer count registers (DMATCR) are 32-bit readable/writable registers that specify the number of DMA transfers. The transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 302 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.4 DMA Channel Control Registers (CHCR) The DMA channel control registers (CHCR) are 32-bit readable/writable registers that control the DMA transfer mode. The DO, AM, AL, DL, and DS bits which specify the DREQ and DACK external pin functions can be read and written to in channels 0 and 1, but they are reserved in channels 2 to 7. The TL bit which specifies the TEND external pin function can be read and written to in channels 0 and 1, but it is reserved in channels 2 to 7. Bit: 31 TC 30  29  28 RLD 27  26  25  24  23 DO 22 TL 21  20  19 HE 18 HIE 17 AM 16 AL Initial value: R/W: Bit: 0 R/W 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 0 R/(W)* R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 DL 6 DS 5 TB 4 3 TS[1:0] 2 IE 1 TE 0 DE DM[1:0] SM[1:0] RS[3:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 0 R/W R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit 31 Bit Name TC Initial Value 0 R/W R/W Descriptions Transfer Count Mode Specifies whether to transmit data once or for the count specified in DMATCR by one transfer request. This function is valid only at a request of the peripheral module. Note that when this bit is set to 0, the TB bit must not be set to 1 (burst mode). When the SCIF or IIC3 is selected for the transfer request source, this bit (TC) must not be set to 1. 0: Transmits data once by one transfer request. 1: Transmits data for the count specified in DMATCR by one transfer request. 30  0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 303 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 29 Bit Name RLDSAR Initial Value 0 R/W R/W Descriptions SAR Reload Function Enable or Disable Sets whether to enable or disable the reload function for SAR or DMATCR. 0: Disables the reload function for SAR or DMATCR. 1: Enables the reload function for SAR or DMATCR. 28 RLDDAR 0 R/W DAR Reload Function Enable or Disable Sets whether to enable or disable the reload function for DAR or DMATCR. 0: Disables the reload function for DAR or DMATCR. 1: Enables the reload function for DAR or DMATCR. 27 to 24  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 23 DO 0 R/W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1. This bit is valid only in CHCR_0 and CHCR_1. This bit is reserved in CHCR_2 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: Detects DREQ by overrun 0. 1: Detects DREQ by overrun 1. 22 TL 0 R/W Transfer End Level Specifies the TEND signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1. This bit is reserved in CHCR_2 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: Low-active output from TEND 1: High-active output from TEND Rev. 1.00 Nov. 14, 2007 Page 304 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 21 Bit Name  Initial Value 0 R/W R Descriptions Reserved These bits are always read as 0. The write value should always be 0. 20 TEMASK 0 R/W TE Set Mask Indicates that DMA transfer is not terminated when the TE bit is set to 1. By setting this bit together with the SAR reload function or the DAR reload function, DMA transfer can be executed until the transfer request is canceled. Upon detection of the rising or falling edge of an auto request or external request, this bit is ignored and the DMA transfer is terminated when the TE bit is set. Note that this function is enabled if either of the RLDSAR bit or the RLDDAR bit is set to 1. 0: Terminates DMA if the TE bit is set. 1: Continues DMA even if the TE bit is set. 19 HE 0 R/(W)* Half-End Flag This bit is set to 1 when the transfer count reaches half of the DMATCR value that was specified before transfer starts. If DMA transfer ends because of an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR before the transfer count reaches half of the initial DMATCR value, the HE bit is not set to 1. If DMA transfer ends due to an NMI interrupt, a DMA address error, or clearing of the DE bit or the DME bit in DMAOR after the HE bit is set to 1, the bit remains set to 1. To clear the HE bit, write 0 to it after HE = 1 is read. 0: DMATCR > (DMATCR set before transfer starts)/2 during DMA transfer or after DMA transfer is terminated [Clearing condition] • Writing 0 after reading HE = 1. 1: DMATCR ≤ (DMATCR set before transfer starts)/2 Rev. 1.00 Nov. 14, 2007 Page 305 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 18 Bit Name HIE Initial Value 0 R/W R/W Descriptions Half-End Interrupt Enable Specifies whether to issue an interrupt request to the CPU when the transfer count reaches half of the DMATCR value that was specified before transfer starts. When the HIE bit is set to 1, the DMAC requests an interrupt to the CPU when the HE bit becomes 1. 0: Disables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2. 1: Enables an interrupt to be issued when DMATCR = (DMATCR set before transfer starts)/2. 17 AM 0 R/W Acknowledge Mode Specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. This bit is valid only in CHCR_0 and CHCR_1. This bit is reserved in CHCR_2 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: DACK output in read cycle (dual address mode) 1: DACK output in write cycle (dual address mode) 16 AL 0 R/W Acknowledge Level Specifies the DACK (acknowledge) signal output is high active or low active. This bit is valid only in CHCR_0 and CHCR_1. This bit is reserved in CHCR_2 to CHCR_7; it is always read as 0 and the write value should always be 0. 0: Low-active output from DACK 1: High-active output from DACK Rev. 1.00 Nov. 14, 2007 Page 306 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 15,14 Bit Name DM[1:0] Initial Value 00 R/W R/W Descriptions Destination Address Mode These bits select whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address 01: Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (–1 in 8-bit transfer, –2 in 16-bit transfer, –4 in 32-bit transfer, setting prohibited in 16-byte transfer) 11: Setting prohibited 13, 12 SM[1:0] 00 R/W Source Address Mode These bits select whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte-unit transfer) 10: Source address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longwordunit transfer, setting prohibited in 16-byte-unit transfer) 11: Setting prohibited Rev. 1.00 Nov. 14, 2007 Page 307 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 11 to 8 Bit Name RS[3:0] Initial Value 0000 R/W R/W Descriptions Resource Select These bits specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state when DMA enable bit (DE) is set to 0. 0000: External request, dual address mode 0001: Setting prohibited 0010: External request/single address mode External address space → External device with DACK 0011: External request/single address mode External device with DACK → External address space 0100: Auto request 0101: Setting prohibited 0110: Setting prohibited 0111: Setting prohibited 1000: DMA extension resource selector 1001: Setting prohibited 1010: Setting prohibited 1011: Setting prohibited 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Note: External request specification is valid only in CHCR_0 to CHCR_3. If a request source is selected in channels CHCR_4 to CHCR_7, no operation will be performed. Rev. 1.00 Nov. 14, 2007 Page 308 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 7 6 Bit Name DL DS Initial Value 0 0 R/W R/W R/W Descriptions DREQ Level DREQ Edge Select These bits specify the sampling method of the DREQ pin input and the sampling level. These bits are valid only in CHCR_0 and CHCR_1. These bits are reserved in CHCR_2 to CHCR_7; they are always read as 0 and the write value should always be 0. If the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, the specification by these bits is ignored. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge 5 TB 0 R/W Transfer Bus Mode Specifies the bus mode when DMA transfers data. Note that the burst mode must not be selected when TC = 0. 0: Cycle steal mode 1: Burst mode 4, 3 TS[1:0] 00 R/W Transfer Size These bits specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte unit 01: Word unit (two bytes) 10: Longword unit (four bytes) 11: 16-byte (four longword) unit Rev. 1.00 Nov. 14, 2007 Page 309 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 2 Bit Name IE Initial Value 0 R/W R/W Descriptions Interrupt Enable Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when TE bit is set to 1. 0: Disables an interrupt request. 1: Enables an interrupt request. 1 TE 0 R/(W)* Transfer End Flag This bit is set to 1 when DMATCR becomes 0 and DMA transfer ends. The TE bit is not set to 1 in the following cases. • • DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR becomes 0. DMA transfer is ended by clearing the DE bit and DME bit in DMA operation register (DMAOR). To clear the TE bit, write 0 after reading TE = 1. If the TEMASK bit is 0 and the TE bit is set, transfer is not enabled even if the DE bit is set to 1. 0: During the DMA transfer or DMA transfer has been terminated [Clearing condition] • Writing 0 after reading TE = 1 1: DMA transfer ends by the specified count (DMATCR = 0) Rev. 1.00 Nov. 14, 2007 Page 310 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 0 Bit Name DE Initial Value 0 R/W R/W Descriptions DMA Enable Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this case, all of the bits TE, NMIF in DMAOR, and AE must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. If the TEMASK bit is 1, the NMIF and AE bits must be 0 upon detection of the low or high level of an external request and at a request of the peripheral module. If the TEMASK bit is 0, the TE bit must also be 0. As with auto request mode, all of the TE, NMIF, and AE bits must be 0 upon detection of the rising or falling edge of an external request. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Only 0 can be written to clear the flag after 1 is read. Rev. 1.00 Nov. 14, 2007 Page 311 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.5 DMA Reload Source Address Registers (RSAR) The DMA reload source address registers (RSAR) are 32-bit readable/writable registers. When the SAR reload function is enabled, the RSAR value is written to the source address register (SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RSAR during the current DMA transfer. When the SAR reload function is disabled, RSAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 312 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.6 DMA Reload Destination Address Registers (RDAR) The DMA reload destination address registers (RDAR) are 32-bit readable/writable registers. When the DAR reload function is enabled, the RDAR value is written to the destination address register (SAR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDAR during the current DMA transfer. When the DAR reload function is disabled, RDAR is ignored. To transfer data in word (2-byte), longword (4-byte), or 16-byte unit, specify the address with 2byte, 4-byte, or16-byte address boundary respectively. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 313 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.7 DMA Reload Transfer Count Registers (RDMATCR) The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers. When the SAR or DAR reload function is enabled, the RDMATCR value is written to the transfer count register (DMATCR) at the end of the current DMA transfer. In this case, a new value for the next DMA transfer can be preset in RDMATCR during the current DMA transfer. When the SAR or DAR reload function is disabled, RDMATCR is ignored. The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0. As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R/W 7  0 R/W 6  0 R/W 5  0 R/W 4  0 R/W 3  0 R/W 2  0 R/W 1  0 R/W 0  Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 314 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.8 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register also shows the DMA transfer status. Bit: 15  14  13 12 11  10  9 8 PR[1:0] 7  6  5  4  3  2 AE 1 NMIF 0 DME CMS[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 0 0 R/(W)* R/(W)* R/W Note: * Only 0 can be written to clear the flag after 1 is read. Bit 15, 14 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13, 12 CMS[1:0] 00 R/W Cycle Steal Mode Select These bits select either normal mode or intermittent mode in cycle steal mode. It is necessary that the bus modes of all channels be set to cycle steal mode to make the intermittent mode valid. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer for every 16 cycles of Bφ clock. 11: Intermittent mode 64 Executes one DMA transfer for every 64 cycles of Bφ clock. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 315 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 9, 8 Bit Name PR[1:0] Initial Value 00 R/W R/W Description Priority Mode These bits select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 01: Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7 10: Setting prohibited 11: Round-robin mode (only supported in CH0 to CH3) 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 AE 0 R/(W)* Address Error Flag Indicates whether an address error has occurred by the DMAC. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. 0: No DMAC address error 1: DMAC address error occurred [Clearing condition] • Writing 0 after reading AE = 1 1 NMIF 0 R/(W)* NMI Flag Indicates that an NMI interrupt occurred. When this bit is set, even if the DE bit in CHCR and the DME bit in DMAOR are set to 1, DMA transfer is not enabled. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. Even if the NMI interrupt is input while the DMAC is not in operation, the NMIF bit is set to 1. 0: No NMI interrupt 1: NMI interrupt occurred [Clearing condition] • Writing 0 after reading NMIF = 1 Rev. 1.00 Nov. 14, 2007 Page 316 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Bit 0 Bit Name DME Initial Value 0 R/W R/W Description DMA Master Enable Enables or disables DMA transfer on all channels. If the DME bit and DE bit in CHCR are set to 1, DMA transfer is enabled. However, transfer is enabled only when the TE bit in CHCR of the transfer corresponding channel, the NMIF bit in DMAOR, and the AE bit are all cleared to 0. Clearing the DME bit to 0 can terminate the DMA transfer on all channels. 0: DMA transfer is disabled on all channels 1: DMA transfer is enabled on all channels Note: * Only 0 can be written to clear the flag after 1 is read. If the priority mode bits are modified after a DMA transfer, the channel priority is initialized. If fixed mode 2 is specified, the channel priority is specified as CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7. If fixed mode 1 is specified, the channel priority is specified as CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If the round-robin mode is specified, the transfer end channel is reset. Table 8.3 show the priority change in each mode (modes 0 to 2) specified by the priority mode bits. In each priority mode, the channel priority to accept the next transfer request may change in up to three ways according to the transfer end channel. For example, when the transfer end channel is channel 1, the priority of the channel to accept the next transfer request is specified as CH2 > CH3 > CH0 >CH1 > CH4 > CH5 > CH6 > CH7. When the transfer end channel is any one of the channels 4 to 7, round-robin will not be applied and the priority level is not changed at the end of transfer in the channels 4 to 7. The DMAC internal operation for an address error is as follows: • No address error: Read (source to DMAC) → Write (DMAC to destination) • Address error in source address: Nop → Nop • Address error in destination address: Read → Nop Rev. 1.00 Nov. 14, 2007 Page 317 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Table 8.3 Combinations of Priority Mode Bits Transfer End Priority Mode Bits PR[1] PR[0] 0 High 0 CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 Priority Level at the End of Transfer Low 7 CH7 Mode Mode 0 (fixed mode 1) Mode 1 (fixed mode 2) Mode 2 (round-robin mode) CH No. Any channel 0 Any channel 0 1 CH0 CH4 CH1 CH5 CH2 CH6 CH3 CH7 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CH1 CH2 CH3 CH0 CH0 CH0 CH0 CH0 CH2 CH3 CH0 CH1 CH1 CH1 CH1 CH1 CH3 CH0 CH1 CH2 CH2 CH2 CH2 CH2 CH0 CH1 CH2 CH3 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4 CH4 CH4 CH4 CH4 CH5 CH5 CH5 CH5 CH5 CH5 CH5 CH5 CH6 CH6 CH6 CH6 CH6 CH6 CH6 CH6 CH7 CH7 CH7 CH7 CH7 CH7 CH7 CH7 Rev. 1.00 Nov. 14, 2007 Page 318 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3) The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and DMARS3 is for channels 6 and 7. Table 8.4 shows the specifiable combinations. This register can specify transfer requests from six SCIF sources, two IIC3 sources, two CMT sources, two USB sources, two SSI sources, and two SDHI sources. • DMARS0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1 MID[5:0] CH1 RID[1:0] CH0 MID[5:0] CH0 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • DMARS1 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3 MID[5:0] CH3 RID[1:0] CH2 MID[5:0] CH2 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • DMARS2 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH5 MID[5:0] CH5 RID[1:0] CH4 MID[5:0] CH4 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W • DMARS3 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH7 MID[5:0] CH7 RID[1:0] CH6 MID[5:0] CH6 RID[1:0] Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Transfer requests from the various modules specify MID and RID as shown in table 8.4. Rev. 1.00 Nov. 14, 2007 Page 319 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Table 8.4 DMARS Settings Setting Value for One Channel ({MID, RID}) H'03 H'07 H'11 H'12 MID B'000000 B'000001 B'000100 B'000100 B'001000 B'001001 B'011000 RID B'11 B'11 B'01 B'10 B'11 B'11 B'01 B'10 B'100000 B'10 B'01 B'100001 B'10 B'01 B'100010 B'10 B'01 B'111110 B'111111 B'11 B'11 Function   Transmit Receive   Transmit Receive Receive Transmit Receive Transmit Receive Transmit   Peripheral Module USB_0 USB_1 SDHI SSI_0 SSI_1 IIC3_0 H'23 H'27 H'61 H'62 SCIF_0 H'81 H'82 SCIF_1 H'85 H'86 SCIF_2 H'89 H'8A CMT_0 CMT_1 H'FB H'FF When MID or RID other than the values listed in table 8.4 is set, the operation of this LSI is not guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set, the transfer request source is not accepted. Rev. 1.00 Nov. 14, 2007 Page 320 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, the burst mode or the cycle steal mode can be selected. 8.4.1 Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation register (DMAOR), three reload registers (RSAR, RDAR, and RDMATCR), and DMA extension resource selector (DMARS) are set for the target transfer conditions, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TEMASK = 0 and TE = 0 [or TEMASK = 1], AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of data (depending on the TS[1:0] settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1. 4. When TEMASK = 0, if transfer has been completed for the specified count (that is, DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. When TEMASK = 1, if DMATCR reaches 0, TE is set to 1. The specified RSAR, RDAR, and RDMATC values are reloaded into RSAR, RDAR, and RDMATC, and the transfer operation continues until there are no more transfer requests. 5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. Figure 8.2 is a flowchart of this procedure. Rev. 1.00 Nov. 14, 2007 Page 321 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARS) DE, DME = 1 and NMIF, AE, TE = 0? Yes No Transfer request occurs?*1 Yes Transfer (one transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated No *2 Bus mode, transfer request mode, DREQ detection system *3 DMATCR = 0? Yes No No DMATCR=1/2 ? TE = 1 Yes HE=1 DEI interrupt request (when IE = 1) When reload function is enabled, RSAR → SAR, RDAR → DAR, and RDMATCR → DMATCR HEI interrupt request (when HE = 1) For a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes When the TC bit in CHCR is 0, or for a request from an on-chip peripheral module, the transfer acknowledge signal is sent to the module. No NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Yes Yes No Upon detection of the level of an external request or at a request of an on-chip peripheral module, is the TEMASK bit set to 1? No Transfer end Normal end Transfer terminated Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are cleared to 0 and the DE and DME bits are set to 1. 2. DREQ level detection in burst mode (external request) or cycle steal mode. 3. DREQ edge detection in burst mode (external request), or auto request mode in burst mode. Figure 8.2 DMA Transfer Flowchart Rev. 1.00 Nov. 14, 2007 Page 322 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated in external devices and on-chip peripheral modules that are neither the transfer source nor destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected by the RS[3:0] bits in CHCR_0 to CHCR_7 and DMARS0 to DMARS3. (1) Auto-Request Mode When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR_0 to CHCR_7 and the DME bit in DMAOR are set to 1, the transfer begins so long as the TE bits in CHCR_0 to CHCR_7, and the AE and NMIF bits in DMAOR are 0. (2) External Request Mode In this mode a transfer is performed at the request signals (DREQ0 and DREQ1) of an external device. Choose one of the modes shown in table 8.5 according to the application system. When the DMA transfer is enabled (for level detection, DE=1, DME=1, TEMASK = 0 and TE = 0 [or TEMASK = 1], AE=0, NMIF=0); for edge detection, DE=1, DME=1, TE=0, AE=0, NMIF=0), DMA transfer is performed upon a request at the DREQ input. Table 8.5 Selecting External Request Modes with the RS Bits Transfer Source Any Transfer Destination Any External device with DACK External memory, memory-mapped external device RS[3] RS[2] RS[1] RS[0] Address Mode 0 0 0 0 0 1 0 0 Dual address mode Single address mode External memory, memory-mapped external device External device with DACK 1 Rev. 1.00 Nov. 14, 2007 Page 323 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in CHCR_0 and CHCR_1 as shown in table 8.6. The source of the transfer request does not have to be the data transfer source or destination. Upon detection of a rising or falling edge, one transfer request in burst mode causes the transfer to continue until DMATCR = 0 is reached. In cycle steal mode, one transfer request results in a single transfer. Table 8.6 Selecting External Request Detection with DL and DS Bits CHCR DL bit 0 DS bit 0 1 1 0 1 Detection of External Request Low level detection Falling edge detection High level detection Rising edge detection When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again enters the request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun 0: Transfer is terminated after the same number of transfer has been performed as requests. Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 8.7 CHCR DO bit 0 1 External Request Overrun 0 Overrun 1 Selecting External Request Detection with DO Bit Rev. 1.00 Nov. 14, 2007 Page 324 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) (3) On-Chip Peripheral Module Request In this mode, the transfer is performed in response to the DMA transfer request signal from an onchip peripheral module. Table 8.8 shows the list of DMAC transfer request signals sent from on-chip peripheral modules to DMAC. When a transfer request signal is sent in on-chip peripheral module request mode while DMA transfer is enabled (DE=1, DME=1, TEMASK = 0 and TE = 0 [or TEMASK = 1], AE=0, NMIF=0), DMA transfer is performed. For on-chip peripheral module requests, there are cases in which the transfer source and destination are fixed; see table 8.8. Rev. 1.00 Nov. 14, 2007 Page 325 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Table 8.8 CHCR Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits DMARS DMA Transfer Request RID Source USB DMA Transfer Request Signal USB_DMA0 (receive FIFO full) USB_DMA0 (transmit FIFO empty) Transfer Source D0FIFO Any D1FIFO Any Transfer Destination Bus Mode Any D0FIFO Any D1FIFO Cycle steal Cycle steal or burst RS[3:0] MID 1000 000000 11 000001 11 USB USB_DMA1 (receive FIFO full) USB_DMA1 (transmit FIFO empty) 000100 01 10 001000 11 SDHI transmit SDHI receive SSI_0 TXI (receive data empty) RXI (transmit data full) DMA0 (transmit mode) DMA0 (receive mode) Data register Any Any Any SSIRDR0 Any SSIRDR1 Any ICDRR0 Any SCFRDR_0 Data register SSITDR0 Any SSITDR1 Any ICDRT0 Any SCFTDR_0 Any SCFTDR_1 Any SCFTDR_2 Any Any Any Cycle steal or burst 001001 11 SSI_1 DMA1 (transmit mode) DMA1 (receive mode) 011000 01 10 100000 01 10 100001 01 10 100010 01 10 111110 11 111111 11 IIC3_0 transmit IIC3_0 receive TXI0 (transmit data empty) RXI0 (receive data full) Cycle steal SCIF_0 transmit TXI0 (transmit FIFO data empty) SCIF_0 receive RXI0 (receive FIFO data full) SCIF_1 transmit TXI1 Any (transmit FIFO data empty) SCIF_1 receive RXI1 (receive FIFO data full) SCFRDR_1 Any SCFRDR_2 Any Any SCIF_2 transmit TXI2 (transmit FIFO data empty) SCIF_2 receive CMT_0 CMT_1 RXI2 (receive FIFO data full) CMI0 (compare match) CMI1 (compare match) Cycle steal or burst Rev. 1.00 Nov. 14, 2007 Page 326 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.4.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Three modes (fixed mode 1, fixed mode 2, and round-robin mode) are selected using the PR1 and PR0 bits in DMAOR. (1) Fixed Mode In fixed modes, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows: Fixed mode 1: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Fixed mode 2: CH0 > CH4 > CH1 > CH5 > CH2 > CH6 > CH3 > CH7 These are selected by the PR1 and PR0 bits in the DMA operation register (DMAOR). (2) Round-Robin Mode Each time one unit of word, byte, longword, or 16 bytes is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished is rotated to the lowest of the priority order among the four round-robin channels (channels 0 to 4). The priority of the channels other than the round-robin channels (channels 0 to 4) does not change even in round-robin mode. The round-robin mode operation is shown in figure 8.3. The priority in round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 immediately after a reset. When the round-robin mode has been specified, do not concurrently specify cycle steal mode and burst mode as the bus modes of any two or more channels. Rev. 1.00 Nov. 14, 2007 Page 327 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Channel 0 is given the lowest priority among the round-robin channels. Priority order after transfer CH1 > CH2 > CH3 > CH0 > CH4 > CH5 > CH6 > CH7 (2) When channel 1 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Channel 1 is given the lowest priority among the round-robin channels. The priority of channel 0, which was higher than channel 1, is also shifted. Priority order after transfer CH2 > CH3 > CH0 > CH1 > CH4 > CH5 > CH6 > CH7 (3) When channel 2 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Priority order after transfer CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7 Channel 2 is given the lowest priority among the round-robin channels. The priority of channels 0 and 1, which were higher than channel 2, is also shifted. If there is a transfer request only to channel 5 immediately after that, the priority does not change because channel 5 is not a round-robin channel. Post-transfer priority order when there is an immediate transfer request to channel 5 only CH3 > CH0 > CH1 > CH2 > CH4 > CH5 > CH6 > CH7 (4) When channel 7 transfers Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Priority order does not change. Priority order after transfer CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 Figure 8.3 Round-Robin Mode Rev. 1.00 Nov. 14, 2007 Page 328 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Figure 8.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 is given the lowest priority among the round-robin channels. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 is given the lowest priority among the round-robin channels. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 are lowered in priority so that channel 3 is given the lowest priority among the round-robin channels. Transfer request Waiting channel(s) DMAC operation Channel priority 0>1>2>3>4>5>6>7 (1) Channels 0 and 3 (2) Channel 0 transfer start (3) Channel 1 3 Priority order changes 1, 3 (4) Channel 0 transfer ends 1>2>3>0>4>5>6>7 (5) Channel 1 transfer starts Priority order changes 3 (6) Channel 1 transfer ends 2>3>0>1>4>5>6>7 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3>4>5>6>7 Figure 8.4 Changes in Channel Priority in Round-Robin Mode Rev. 1.00 Nov. 14, 2007 Page 329 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.4.4 DMA Transfer Types DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to the transfer source and destination. A data transfer timing depends on the bus mode, which is the cycle steal mode or burst mode. The DMAC supports the transfers shown in table 8.9. Table 8.9 Supported DMA Transfers Transfer Destination Transfer Source External device with DACK External memory Memory-mapped external device On-chip peripheral module On-chip memory External Device with DACK Not available Dual, single Dual, single Not available Not available External Memory Dual, single Dual Dual Dual Dual Memory-Mapped External Device Dual, single Dual Dual Dual Dual On-Chip On-Chip Peripheral Module Memory Not available Dual Dual Dual Dual Not available Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. 16-byte transfer is available only for on-chip peripheral modules that support longword access. Rev. 1.00 Nov. 14, 2007 Page 330 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) (1) (a) Address Modes Dual Address Mode In dual address mode, both the transfer source and destination are accessed (selected) by an address. The transfer source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 8.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a data write cycle. DMAC SAR Memory Address bus DAR Data bus Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is tempolarily stored in the DMAC. First bus cycle DMAC SAR Memory Address bus DAR Data bus Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 8.5 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle. Figure 8.6 shows an example of DMA transfer timing in dual address mode. Rev. 1.00 Nov. 14, 2007 Page 331 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) CKIO A25 to A0 Transfer source address Transfer destination address CSn D31 to D0 RD WEn DACKn (Active-low) Data read cycle (1st cycle) Data write cycle (2nd cycle) Note: In transfer between external memories, with DACK output in the read cycle, DACK output timing is the same as that of CSn. Figure 8.6 Example of DMA Transfer Timing in Dual Mode (Transfer Source: Normal Memory, Transfer Destination: Normal Memory) Rev. 1.00 Nov. 14, 2007 Page 332 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) (b) Single Address Mode In single address mode, both the transfer source and destination are external devices, either of them is accessed (selected) by the DACK signal, and the other device is accessed by an address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 8.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus This LSI DMAC External memory External data bus External device with DACK DACK DREQ Data flow (from memory to device) Data flow (from device to memory) Figure 8.7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Figure 8.8 shows an example of DMA transfer timing in single address mode. Rev. 1.00 Nov. 14, 2007 Page 333 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) CK A25 to A0 CSn WEn D31 to D0 DACKn Address output to external memory space Select signal to external memory space Write strobe signal to external memory space Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK → External memory space (normal memory) CK A25 to A0 CSn RD D31 to D0 DACKn Address output to external memory space Select signal to external memory space Read strobe signal to external memory space Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space (normal memory) → External device with DACK Figure 8.8 Example of DMA Transfer Timing in Single Address Mode (2) Bus Modes There are two bus modes; cycle steal and burst. Select the mode by the TB bits in the channel control registers (CHCR). (a) Cycle Steal Mode • Normal mode In normal mode of cycle steal, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer request occurs, the bus mastership is obtained from another bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is repeated until the transfer end conditions are satisfied. The cycle-steal normal mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. Figure 8.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer conditions shown in the figure are;  Dual address mode  DREQ low level detection Rev. 1.00 Nov. 14, 2007 Page 334 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) DREQ Bus mastership returned to CPU once Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU Read/Write Figure 8.9 DMA Transfer Example in Cycle-Steal Normal Mode (Dual Address, DREQ Low Level Detection) • Intermittent Mode 16 and Intermittent Mode 64 In intermittent mode of cycle steal, DMAC returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16 bytes) is completed. If the next transfer request occurs after that, DMAC obtains the bus mastership from other bus master after waiting for 16 or 64 cycles of Bφ clock. DMAC then transfers data of one unit and returns the bus mastership to other bus master. These operations are repeated until the transfer end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA transfer than the normal mode of cycle steal. When DMAC obtains again the bus mastership, DMA transfer may be postponed in case of entry updating due to cache miss. The cycle-steal intermittent mode can be used for any transfer section; transfer request source, transfer source, and transfer destination. The bus modes, however, must be cycle steal mode in all channels. Figure 8.10 shows an example of DMA transfer timing in cycle-steal intermittent mode. Transfer conditions shown in the figure are;  Dual address mode  DREQ low level detection DREQ More than 16 or 64 Bφ clock cycles (depends on the CPU's condition of using bus) Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU CPU DMAC DMAC Read/Write CPU Figure 8.10 Example of DMA Transfer in Cycle-Steal Intermittent Mode (Dual Address, DREQ Low Level Detection) Rev. 1.00 Nov. 14, 2007 Page 335 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) (b) Burst Mode In burst mode, once the DMAC obtains the bus mastership, it does not release the bus mastership and continues to perform transfer until the transfer end condition is satisfied. In external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus mastership is passed to another bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. Figure 8.11 shows DMA transfer timing in burst mode. DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC Read Write Read Write CPU CPU Figure 8.11 DMA Transfer Example in Burst Mode (Dual Address, DREQ Low Level Detection) (3) Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 8.10 shows the relationship between request modes and bus modes by DMA transfer category. Rev. 1.00 Nov. 14, 2007 Page 336 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Table 8.10 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Dual External device with DACK and external memory External device with DACK and memory-mapped external device External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memorymapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Request Mode External External All* All* All* All* All* 4 4 Bus Mode B/C B/C B/C B/C B/C B/C* B/C* B/C* B/C B/C B/C* B/C B/C B/C 5 5 5 Transfer Size (Bits) 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128 8/16/32/128* 8/16/32/128* 8/16/32/128* 8/16/32/128 8/16/32/128 8/16/32/128* 8/16/32/128 8/16/32/128 8/16/32/128 2 2 2 Usable Channels 0 and 1 0 and 1 0 to 7* 0 to 7* 0 to 7* 3 3 4 3 1 1 0 to 7* 0 to 7* 0 to 7* 0 to 7* 0 to 7* 3 3 On-chip peripheral module and on-chip peripheral All* module On-chip memory and on-chip memory On-chip memory and memory-mapped external device On-chip memory and on-chip peripheral module On-chip memory and external memory Single External device with DACK and external memory External device with DACK and memory-mapped external device All* All* All* All* 1 5 2 3 4 4 3 3 1 4 0 to 7* 0 to 7* 3 3 External External 0 and 1 0 and 1 [Legend] B: Burst C: Cycle steal Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. However, in the case of internal module request, along with the exception of CMT as the transfer request source, the requesting module must be designated as the transfer source or the transfer destination. 2. Access size permitted for the on-chip peripheral module register functioning as the transfer source or transfer destination. 3. If the transfer request is an external request, channels 0 to 3 are only available. 4. External requests, auto requests, and on-chip peripheral module requests are all available. In the case of on-chip peripheral module requests, however, the CMT are only available. 5. In the case of internal module request, only cycle steal except for the USB, SSI, and CMT as the transfer request source. Rev. 1.00 Nov. 14, 2007 Page 337 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) (4) Bus Mode and Channel Priority In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer on channel 1 will only resume on completion of the transfer on channel 0. When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1, channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of this is shown in figure 8.12. When multiple channels are in burst mode, data transfer on the channel that has the highest priority is given precedence. When DMA transfer is being performed on multiple channels, the bus mastership is not released to another bus-master device until all of the competing burst-mode transfers have been completed. CPU DMA CH1 DMA CH1 DMA CH0 CH0 DMA CH1 CH1 DMA CH0 CH0 DMA CH1 DMA CH1 CPU CPU DMAC CH1 Burst mode DMAC CH0 and CH1 Cycle steal mode DMAC CH1 Burst mode CPU Priority: CH0 > CH1 CH0: Cycle steal mode CH1: Burst mode Figure 8.12 Bus State when Multiple Channels are Operating In round-robin mode, the priority changes as shown in figure 8.3. Note that channels in cycle steal and burst modes must not be mixed. Rev. 1.00 Nov. 14, 2007 Page 338 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) 8.4.5 (1) Number of Bus Cycles and DREQ Pin Sampling Timing Number of Bus Cycles When the DMAC is the bus master, the number of bus cycles is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 7, Bus State Controller (BSC). (2) DREQ Pin Sampling Timing Figures 8.13 to 8.16 show the DREQ input sampling timings in each bus mode. CKIO Bus cycle DREQ (Rising) DACK (Active-high) Acceptance start CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Figure 8.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC CPU 2nd acceptance Acceptance start CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) CPU 1st acceptance Non sensitive period CPU DMAC 2nd acceptance CPU Acceptance start Figure 8.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection Rev. 1.00 Nov. 14, 2007 Page 339 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) CKIO Bus cycle DREQ (Rising) DACK (Active-high) CPU Burst acceptance Non sensitive period CPU DMAC DMAC Figure 8.15 Example of DREQ Input Detection in Burst Mode Edge Detection CKIO Bus cycle DREQ (Overrun 0 at high level) DACK (Active-high) Acceptance start CPU 1st acceptance CPU DMAC 2nd acceptance Non sensitive period CKIO Bus cycle DREQ (Overrun 1 at high level) DACK (Active-high) Acceptance start Acceptance start CPU 1st acceptance CPU DMAC 2nd acceptance DMAC 3rd acceptance Non sensitive period Figure 8.16 Example of DREQ Input Detection in Burst Mode Level Detection Rev. 1.00 Nov. 14, 2007 Page 340 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) Figure 8.17 shows the TEND output timing. CKIO End of DMA transfer Bus cycle DREQ DACK TEND DMAC CPU DMAC CPU CPU Figure 8.17 Example of DMA Transfer End Signal Timing (Cycle Steal Mode Level Detection) The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for an 8-bit or 16-bit external device, or when word access is performed for an 8-bit external device. When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS signal for data alignment as shown in figure 8.18. Figures 8.13 to 8.17 show cases in which TACK and TEND are not divided at the time of DMA transfer. Rev. 1.00 Nov. 14, 2007 Page 341 of 1262 REJ09B0437-0100 Section 8 Direct Memory Access Controller (DMAC) T1 CKIO Address CS RD Data WEn DACKn (Active low) TEND (Active low) WAIT T2 Taw T1 T2 Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit is divided into multiple bus cycles and the CS is negated between the bus cycles, TEND is also divided. Figure 8.18 BSC Normal Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) Rev. 1.00 Nov. 14, 2007 Page 342 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) Section 9 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock (Pφ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, and divider circuits. 9.1 Features • Four clock operating modes The mode can be selected from among the four clock operating modes based on the frequency range to be used and the input clock type: the crystal resonator, the external clock, the crystal resonator for USB, or the external clock for USB. • Three clocks generated independently An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface • Frequency change function Internal and peripheral clock frequencies can be changed independently using the PLL (phase locked loop) circuits and divider circuits within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. • Power-down mode control The clock can be stopped in sleep mode and software standby mode, and specific modules can be stopped using the module standby function. For details on clock control in the power-down modes, see section 11, Power-Down Modes. Rev. 1.00 Nov. 14, 2007 Page 343 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) Figure 9.1 shows a block diagram of the clock pulse generator. On-chip oscillator Divider 2 ×1 × 1/2 × 1/3 × 1/4 × 1/6 × 1/8 × 1/12 Divider 1 ×1 × 1/2 × 1/4 PLL circuit 1 (× 8,12,16) MTU clock (Iφ, Max. 200 MHz) Peripheral clock (Pφ, Max. 33.33 MHz) XTAL EXTAL USB_X2 USB_X1 CKIO Crystal oscillator Bus clock (Bφ = CKIO, Max. 66.67 MHz) Crystal oscillator CPG control unit MD_CLK1 MD_CLK0 Clock frequency control circuit Standby control circuit FRQCR Bus interface [Legend] FRQCR: Frequency control register Peripheral bus Figure 9.1 Block Diagram of Clock Pulse Generator Rev. 1.00 Nov. 14, 2007 Page 344 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: (1) Crystal Oscillator The crystal oscillator is an oscillation circuit in which the crystal resonator is connected to the XTAL/EXTAL pin or USB_X1/USB_X2 pin. This can be used according to the clock operating mode. (2) Divider 1 Divider 1 divides the frequency of one of the three clocks: the clock from the crystal resonator or the EXTAL pin, the clock from the CKIO pin, and the clock from the crystal resonator or the USB_X1 pin. The division ratio depends on the clock operating mode. (3) PLL Circuit The PLL circuit multiplies the frequency of the output from divider 1 by 8 or 12. The multiplication rate is set by the frequency control register. When this is done, the phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the rising edge of the CKIO pin. The input clock to be used depends on the clock operating mode. The clock operating mode is specified using the MD_CK0 and MD_CK1 pins. For details on the clock operating mode, see table 9.2. (4) Divider 2 Divider 2 divides the frequency of output of the PLL circuit to generate an internal clock, a bus clock, and a peripheral clock. The internal clock can be 1 or 1/2 times the output frequency of the PLL circuit, and it should not be lower than the clock frequency on the CKIO pin. The peripheral clock can be 1/4, 1/6, 1/8, or 1/12 times the output frequency of the PLL circuit, and it should not be higher than the half of the clock frequency on the CKIO pin. The bus clock is automatically determined by hardware at the division ratio against the output frequency of the PLL circuit so that it will be 4 times the clock source (when clock mode = 0), 2 times (when clock mode = 1 or 3), or 1 times (when clock mode = 2). (5) Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency using the MD_CK0 and MD_CK1 pins and the frequency control register (FRQCR). Rev. 1.00 Nov. 14, 2007 Page 345 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) (6) Standby Control Circuit The standby control circuit controls the states of the clock pulse generator and other modules during clock switching, or sleep or software standby mode. In addition, the standby control register is provided to control the power-down mode of other modules. For details on the standby control register, see section 11, Power-Down Modes. (7) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode, the frequency multiplication ratio of PLL circuit, and the frequency division ratio of the internal clock and the peripheral clock (Pφ). Rev. 1.00 Nov. 14, 2007 Page 346 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.2 Input/Output Pins Table 9.1 lists the clock pulse generator pins and their functions. Table 9.1 Pin Configuration and Functions of the Clock Pulse Generator Function (Clock Operating Mode 0) Function (Clock Operating Mode 1) Function (Clock Operating Mode 2) Function (Clock Operating Mode 3) Pin Name Symbol I/O Input Input Mode MD_ control pins CLK0 MD_ CLK1 Crystal XTAL input/output pins (clock input pins) Sets the clock operating mode. Sets the clock operating mode. Leave this pin open. Leave this pin open. Output Connected to Leave this pin the crystal open. resonator. (Leave this pin open when the crystal resonator is not in use.) Input Connected to the crystal resonator or used to input external clock. Clock output pin. Used as an external clock input terminal. EXTAL Pull-up this pin. Pull-up this pin. Clock CKIO input/output pin I/O Clock output pin Clock input pin Clock output pin Rev. 1.00 Nov. 14, 2007 Page 347 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) Pin Name Symbol I/O Function (Clock Operating Mode 0) Connected to the crystal resonator to input the clock for USB only, or used to input external clock. When USB is not used, this pin should be pulled up. Function (Clock Operating Mode 1) Connected to the crystal resonator to input the clock for USB only, or used to input external clock. When USB is not used, this pin should be pulled up. Connected to the crystal resonator for USB. (Leave this pin open when the crystal resonator is not in use.) Function (Clock Operating Mode 2) Connected to the crystal resonator to input the clock for USB only, or used to input external clock. When USB is not used, this pin should be pulled up. Connected to the crystal resonator for USB. (Leave this pin open when the crystal resonator is not in use.) Function (Clock Operating Mode 3) Connected to the crystal resonator to input the clock for both USB and the LSI, or used to input external clock. Crystal USB_X1 Input input/output pins for USB (clock input pins) USB_X2 Output Connected to the crystal resonator for USB. (Leave this pin open when the crystal resonator is not in use.) Connected to the crystal resonator for both USB and the LSI. (Leave this pin open when the crystal resonator is not in use.) Rev. 1.00 Nov. 14, 2007 Page 348 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.3 Clock Operating Modes Table 9.2 shows the relationship between the combinations of the mode control pins (MD_CK1 and MD_CK0) and the clock operating modes. Table 9.3 shows the usable frequency ranges in the clock operating modes. Table 9.2 Clock Operating Modes Pin Values Mode MD_CK1 0 0 MD_CK0 0 Clock I/O Source EXTAL or crystal resonator EXTAL CKIO USB_X1 or crystal resonator Output CKIO Divider 2 1 PLL Circuit On/Off ON (× 8, 12) CKIO Frequency (EXTAL or crystal resonator) × 4 (EXTAL or crystal resonator) × 2 (CKIO) (USB_X1 or crystal resonator) × 2 1 2 3 0 1 1 1 0 1 CKIO  CKIO 1/2 1/4 1/2 ON (× 8, 12) ON (× 8, 12) ON (× 8) • Mode 0 In mode 0, clock is input from the EXTAL pin or the crystal resonator. The PLL circuit shapes waveforms and the frequency is multiplied according to the frequency control register setting before the clock is supplied to the LSI. The oscillating frequency for the crystal resonator and EXTAL pin input clock ranges from 15 to 25 MHz*. The frequency range of CKIO is from 60 to 100 MHz*. To reduce current supply, pull up the USB_X1 pin and open the USB_X2 pin when USB is not used. Note: * These are target values that were set when we prepared this hardware manual. We will determine the guaranteed maximum frequencies after the final evaluation result of this LSI is obtained. • Mode 1 In mode 1, clock is input from the EXTAL pin. The PLL circuit shapes waveform and the frequency is multiplied according to the frequency control register setting before the clock is supplied to the LSI. The oscillating frequency for the EXTAL pin input clock ranges from 30* to 50 MHz*. The frequency range of CKIO is from 60 to 100 MHz*. To reduce current supply, pull up the USB_X1 pin and open the USB_X2 pin when USB is not used. Note: * These are target values that were set when we prepared this hardware manual. We will determine the guaranteed maximum frequencies after the final evaluation result of this LSI is obtained. Rev. 1.00 Nov. 14, 2007 Page 349 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) • Mode 2 In mode 2, the CKIO pin functions as an input pin and draws an external clock signal. The PLL circuit shapes waveform and the frequency is multiplied according to the frequency control register setting before the clock is supplied to the LSI. The frequency range of CKIO is from 60 to 100 MHz*. To reduce current supply, pull up the EXTAL pin and open the XTAL pin when the LSI is used in mode 2. When USB is not used, pull up the USB_X1 pin and open the USB_X2 pin. Note: * These are target values that were set when this hardware manual was prepared. The guaranteed maximum frequencies will be determined after the final evaluation result of this LSI is obtained. • Mode 3 In mode 3, clock is input from the USB_X1 pin or the crystal oscillator. The external clock is input through this pin and waveform is shaped in the PLL circuit. Then the frequency is multiplied according to the frequency control register setting before the clock is supplied to the LSI. The frequency of CKIO is the same as that of the input clock 96 MHz*. To reduce current supply, pull up the EXTAL pin and open the XTAL pin when the LSI is used in mode 3. When the USB crystal resonator is not used, open the USB_X2 pin. Note: * These are target values that were set when this hardware manual was prepared. The guaranteed maximum frequencies will be determined after the final evaluation result of this LSI is obtained. Rev. 1.00 Nov. 14, 2007 Page 350 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) Table 9.3 Relationship between Clock Operating Mode and Frequency Range This table shows the target values that were set when this hardware manual was prepared. The guaranteed maximum frequencies will be determined after the final evaluation result of this LSI is obtained. Restrictions: Iφ ≤ 200MHz, Bφ ≤ 100MHz, Pφ ≤ 50MHz, Iφ ≤ BΦ ≤ Pφ×2 PLL Frequenc Ratio of y Internal Clock Operatin g Mode 0 FRQCR Multiplier PLL Clock Frequencies (I:B:P)*2 8:4:2 8:4:4/3 8:4:1 8:4:2/3 4:4:2 4:4:4/3 4:4:1 4:4:2/3 12:4:2 12:4:1 4:2:1 4:2:4/3 4:2:1/2 4:1:1/3 2:2:1 2:2:2/3 2:2:1/2 2:2:1/3 6:2:1 6:2:1/2 Selectable Frequency Range (MHz) Output Clock Input Clock*3 (CKIO Pin) 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 15.00 to 16.67 60.00 to 66.67 15.00 to 16.67 60.00 to 66.67 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 30.00 to 33.33 60.00 to 66.67 30.00 to 33.33 60.00 to 66.67 Internal Clock (Iφ) Bus Clock (Bφ) 120.00 to 200.00 120.00 to 200.00 120.00 to 200.00 120.00 to 200.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 180.00 to 200.00 180.00 to 200.00 120.00 to 200.00 120.00 to 200.00 120.00 to 200.00 120.00 to 200.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 180.00 to 200.00 180.00 to 200.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 66.67 60.00 to 66.67 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 66.67 60.00 to 66.67 Peripheral Clock (Pφ) 30.00 to 50.00 20.00 to 33.33 15.00 to 25.00 10.00 to 16.67 30.00 to 50.00 20.00 to 33.33 15.00 to 25.00 10.00 to 16.67 30.00 to 33.33 15.00 to 16.67 30.00 to 50.00 20.00 to 33.33 15.00 to 25.00 10.00 to 16.67 30.00 to 50.00 20.00 to 33.33 15.00 to 25.00 10.00 to 16.67 30.00 to 33.33 15.00 to 16.67 Setting*1 Divider 1 Circuit H'x003 H'x004 H'x005 H'x006 H'x013 H'x014 H'x015 H'x016 H'x104 H'x106 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 12) ON (× 12) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON(× 8) ON(× 8) ON(× 8) ON(× 8) ON (× 12) ON (× 12) 1 H'x003 H'x004 H'x005 H'x006 H'x013 H'x014 H'x015 H'x016 H'x104 H'x106 Rev. 1.00 Nov. 14, 2007 Page 351 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) PLL Frequency Clock Operating FRQCR Mode 2 Multiplier PLL Ratio of Internal Clock Frequencies (I:B:P)*2 2:1:1/2 2:1:1/3 2:1:1/4 2:1:1/6 1:1:1/2 1:1:1/3 1:1:1/4 1:1:1/6 3:1:1/2 3:1:1/4 4:2:1 4:2:2/3 4:2:1/2 4:2:1/3 2:2:1 2:2:2/3 2:2:1/2 2:2:1/3 Input Clock*3 Selectable Frequency Range (MHz) Output Clock (CKIO Pin) Internal Clock (Iφ) Bus Clock (Bφ) Peripheral Clock (Pφ) Setting*1 Divider 1 Circuit H'x003 H'x004 H'x005 H'x006 H'x013 H'x014 H'x015 H'x016 H'x104 H'x106 1/4 1/4 1/4 1/4 1/4 1/4 1/4 1/4 1/4 1/4 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 12) ON (× 12) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) ON (× 8) 60.00 to 100.00  60.00 to 100.00  60.00 to 100.00  60.00 to 100.00  60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 66.67 60.00 to 66.67 48.00 to 48.00 48.00 to 48.00 48.00 to 48.00 48.00 to 48.00 48.00 to 48.00 48.00 to 48.00 48.00 to 48.00 48.00 to 48.00       96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 120.00 to 200.00 60.00 to 100.00 30.00 to 50.00 120.00 to 200.00 60.00 to 100.00 20.00 to 33.33 120.00 to 200.00 60.00 to 100.00 15.00 to 25.00 120.00 to 200.00 60.00 to 100.00 10.00 to 16.67 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 60.00 to 100.00 30.00 to 50.00 60.00 to 100.00 20.00 to 33.33 60.00 to 100.00 15.00 to 25.00 60.00 to 100.00 10.00 to 16.67 30.00 to 33.33 15.00 to 16.67 48.00 to 48.00 32.00 to 32.00 24.00 to 24.00 16.00 to 16.00 48.00 to 48.00 32.00 to 32.00 24.00 to 24.00 16.00 to 16.00 180.00 to 200.00 60.00 to 66.67 180.00 to 200.00 60.00 to 66.67 192.00 to 192.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 192.00 to 192.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 96.00 to 96.00 3 H'x003 H'x004 H'x005 H'x006 H'x013 H'x014 H'x015 H'x016 Notes: 1. x in the FRQCR register setting depends on the set value in bits 12 and 13. 2. The ratio of clock frequencies, where the input clock frequency is assumed to be 1. 3. In mode 0, the frequency of the EXTAL pin input clock or the crystal resonator In mode 1, the frequency of the EXTAL pin input clock In mode 2, the frequency of the CKIO pin input clock. In mode 3, the frequency of the USB_X1 pin input clock or the crystal resonator Cautions: 1. The frequency of the internal clock is as follows: In mode 0 the frequency on the EXTAL pin × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 In mode 1 (the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 Rev. 1.00 Nov. 14, 2007 Page 352 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 In mode 3 (the frequency on the USB_X1pin × 1/2) × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 The frequency of the internal clock should not be set lower than the frequency on the CKIO pin. 2. The frequency of the peripheral clock is as follows: In mode 0 the frequency on the EXTAL pin × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 In mode 1 (the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 In mode 2 (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 In mode 3 (the frequency on the USB_X1 pin × 1/2) × the frequency-multiplier of the PLL circuit × the divisor of the divider 1 The frequency of the peripheral clock should be set to 50 MHz or less, and should not be set higher than one half of the frequency on the CKIO pin. 3. The frequency multiplier of PLL circuit can be selected as ×8 or × 12. The divisor of the divider can be selected as × 1, × 1/2, × 1/3, × 1/4, × 1/6, × 1/8, or × 1/12. The settings are made in the frequency-control register (FRQCR). 4. The output frequency of the PLL circuit is as follows: In mode 0 the frequency on the EXTAL pin × the frequency-multiplier of the PLL circuit In mode 1 (the frequency on the EXTAL pin × 1/2) × the frequency-multiplier of the PLL circuit In mode 2 (the frequency on the CKIO pin × 1/4) × the frequency-multiplier of the PLL circuit In mode 3 (the frequency on the USB_X1 pin × 1/2) × the frequency-multiplier of the PLL circuit Ensure that the output frequency of the PLL circuit should be 200 MHz or less. In mode 2 Rev. 1.00 Nov. 14, 2007 Page 353 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.4 Register Descriptions The clock pulse generator has the following registers. Table 9.4 Register Configuration Abbreviation R/W FRQCR R/W Initial Value Address H'0003 Access Size Register Name Frequency control register H'FFFE0010 16 9.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the CKIO pin during normal operation mode, software standby mode and standby mode cancellation. The register also specifies the frequency-multiplier of the PLL circuit and the frequency division ratio for the internal clock and peripheral clock (Pφ). FRQCR is accessed by word. FRQCR is initialized to H'0003 only by a power-on reset or in deep standby. FRQCR retains its previous value in manual reset or software standby mode. The previous value is also retained when an internal reset is triggered by an overflow of the WDT. Bit: 15 - 14 - 13 12 11 - 10 - 9 8 7 - 6 - 5 - - 4 IFC 3 - 2 1 PFC[2:0] 0 CKOEN[1:0] STC[1:0] Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R 0 R 0 R 0 R/W 0 R 0 R/W 1 R/W 1 R/W Bit 15, 14 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 354 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) Bit 13, 12 Bit Name Initial Value R/W R/W Description Clock Output Enable Specifies the CKIO pin outputs clock signals, or is set to a fixed level or high impedance (Hi-Z) during normal operation mode, standby mode, or cancellation of standby mode. If these bits are set to 01, the CKIO pin is fixed at low during standby mode or cancellation of standby mode. Therefore, the malfunction of an external circuit caused by an unstable CKIO clock during cancellation of standby mode can be prevented. In clock operating mode 2, the CKIO pin functions as an input regardless of the value of these bits. In normal operation 00 01 10 11 Output Output Output Output off (Hi-Z) In standby mode Output off (Hi-Z) Low-level output Output (unstable clock output) Output off (Hi-Z) CKOEN[1:0] 00 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9, 8 STC[1:0] 00 R/W Frequency Multiplication Ratio of PLL Circuit 00: × 8 time 01: × 12 times 10: Reserved (setting prohibited) 11: Reserved (setting prohibited) 7 to 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 355 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) Bit 4 Bit Name IFC Initial Value 0 R/W R/W Description Internal Clock Frequency Division Ratio This bit specifies the frequency division ratio of the internal clock with respect to the output frequency of PLL circuit. 0: × 1 time 1: × 1/2 time 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 to 0 PFC[2:0] 011 R/W Peripheral Clock Frequency Division Ratio These bits specify the frequency division ratio of the peripheral clock with respect to the output frequency of PLL circuit. 000: Reserved (setting prohibited) 001: Reserved (setting prohibited) 010: Reserved (setting prohibited) 011: × 1/4 time 100: × 1/6 time 101: × 1/8 time 110: × 1/12 time 111: Reserved (setting prohibited) Rev. 1.00 Nov. 14, 2007 Page 356 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.5 Changing the Frequency The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by changing the multiplication rate of PLL circuit or by changing the division rates of divider. All of these are controlled by software through the frequency control register (FRQCR). The methods are described below. 9.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit is changed. The onchip WDT counts the settling time. 1. In the initial state, the multiplication rate of PLL circuit is 8 time. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR.TME = 0: WDT stops WTCSR.CKS[2:0]: Division ratio of WDT count clock WTCNT counter: Initial counter value (The WDT count is incremented using the clock after the setting.) 3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC and PFC2 to PFC0 bits. 4. This LSI pauses temporarily and the WDT starts incrementing. The internal and peripheral clocks both stop and the WDT is supplied with the clock. The clock will continue to be output at the CKIO pin. This state is the same as software standby mode. Whether or not registers are initialized depends on the module. For details, see section 28.3, Register States in Each Operating Mode. 5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins operating again. The WDT stops after it overflows. Rev. 1.00 Nov. 14, 2007 Page 357 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.5.2 Changing the Division Ratio Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not. 1. In the initial state, IFC = B'0 and PFC[2:0] = B'011. 2. Set the desired value in the IFC and PFC2 to IFC0 bits. The values that can be set are limited by the clock operating mode and the multiplication rate of PLL circuit. Note that if the wrong value is set, this LSI will malfunction. 3. After the register bits (IFC and PFC2 to PFC0) have been set, the clock is supplied of the new division ratio. Note: When executing the SLEEP instruction after the frequency has been changed, be sure to read the frequency control register (FRQCR) three times before executing the SLEEP instruction. Rev. 1.00 Nov. 14, 2007 Page 358 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.6 9.6.1 Notes on Board Design Note on Inputting External Clock Figure 9.2 is an example of connecting the external clock input. When putting the XTAL pin in open state, make sure the parasitic capacitance is less than or equal to 10 pF. To stably input the external clock with enough PLL stabilizing time at power on or releasing the standby, wait longer than the oscillation stabilizing time. EXTAL External clock input XTAL Open state Example of connection with XTAL pin open Figure 9.2 Example of Connecting External Clock 9.6.2 Note on Using an External Crystal Resonator Place the crystal resonator and capacitors CL1 and CL2 as close to the XTAL and EXTAL pins as possible. In addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. Do not bring wiring patterns close to these components. Signal lines prohibited CL1 CL2 Reference value CL1 = 10 pF CL2 = 10 pF EXTAL XTAL This LSI Note: The values for CL1 and CL2 should be determined after consultation with the crystal resonator manufacturer. Figure 9.3 Note on Using a Crystal Resonator Rev. 1.00 Nov. 14, 2007 Page 359 of 1262 REJ09B0437-0100 Section 9 Clock Pulse Generator (CPG) 9.6.3 Note on Resonator Since various characteristics related to the resonator are closely linked to the user’s board design, thorough evaluation is necessary on the user’s part, using the resonator connection examples shown in this section as a guide. As the parameters for the oscillation circuit will depend on the floating capacitance of the resonator and the user board, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 9.6.4 Note on Using a PLL Oscillation Circuit In the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. In clock operating mode 2 or 3, the EXTAL pin is pulled up and the XTAL pin is left open. Since the analog power supply pins of the PLL are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. To prevent such malfunction, the analog power supply pin Vcc and digital power supply pin PVcc should not supply the same resources on the board if at all possible. Signal lines prohibited Power supply PLLVcc Vcc PLLVss Vss Figure 9.4 Note on Using a PLL Oscillation Circuit Rev. 1.00 Nov. 14, 2007 Page 360 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) Section 10 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal (WDTOVF) on overflow of the counter when the value of the counter has not been updated because of a system malfunction. The WDT can simultaneously generate an internal reset signal for the entire LSI. The WDT is a single channel timer that counts up the clock oscillation settling period when the system leaves software standby mode or the temporary standby periods that occur when the clock frequency is changed. It can also be used as a general watchdog timer or interval timer. 10.1 Features • Can be used to ensure the clock oscillation settling time The WDT is used in leaving software standby mode or the temporary standby periods that occur when the clock frequency is changed. • Can switch between watchdog timer mode and interval timer mode. • Outputs WDTOVF signal in watchdog timer mode When the counter overflows in watchdog timer mode, the WDTOVF signal is output externally. It is possible to select whether to reset the LSI internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset type. • Interrupt generation in interval timer mode An interval timer interrupt is generated when the counter overflows. • Choice of eight counter input clocks Eight clocks (Pφ × 1 to Pφ × 1/16384) that are obtained by dividing the peripheral clock can be selected. Rev. 1.00 Nov. 14, 2007 Page 361 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) Figure 10.1 shows a block diagram of the WDT. WDT Standby cancellation Standby control Standby mode Peripheral clock Divider Interrupt request Interrupt control Reset control WRCSR Clock selection Clock selector WDTOVF Internal reset request* Overflow Clock WTCSR WTCNT Bus interface [Legend] WTCSR: Watchdog timer control/status register WTCNT: Watchdog timer counter WRCSR: Watchdog reset control/status register Note: * The internal reset signal can be generated by making a register setting. Figure 10.1 Block Diagram of WDT 10.2 Input/Output Pin Table 10.1 shows the pin configuration of the WDT. Table 10.1 Pin Configuration Pin Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs the counter overflow signal in watchdog timer mode Rev. 1.00 Nov. 14, 2007 Page 362 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.3 Register Descriptions The WDT has the following registers. Table 10.2 Register Configuration Register Name Watchdog timer counter Watchdog timer control/status register Watchdog reset control/status register Note: * Abbreviation R/W WTCNT WTCSR WRCSR R/W R/W R/W Initial Value H'00 H'18 H'1F Address H'FFFE0002 H'FFFE0000 H'FFFE0004 Access Size 16* 16* 16* For the access size, see section 10.3.4, Notes on Register Access. 10.3.1 Watchdog Timer Counter (WTCNT) WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in watchdog timer mode and an interrupt in interval timer mode. WTCNT is initialized to H'00 by a power-on reset caused by the RES pin or in software standby mode. Use word access to write to WTCNT, writing H'5A in the upper byte. Use byte access to read from WTCNT. Note: The method for writing to WTCNT differs from that for other registers to prevent erroneous writes. See section 10.3.4, Notes on Register Access, for details. Bit: 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 363 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.3.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, overflow flags, and timer enable bit. WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in software standby mode. When used to count the clock oscillation settling time for canceling software standby mode, it retains its value after counter overflow. Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from WTCSR. Note: The method for writing to WTCSR differs from that for other registers to prevent erroneous writes. See section 10.3.4, Notes on Register Access, for details. Bit: 7 IOVF 6 WT/IT 5 TME 4 - 3 - 2 1 CKS[2:0] 0 0 Initial value: R/W: R/(W) 0 R/W 0 R/W 1 R 1 R 0 R/W 0 R/W 0 R/W Bit 7 Bit Name IOVF Initial Value 0 R/W R/(W) Description Interval Timer Overflow Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT overflow in interval timer mode [Clearing condition] • When 0 is written to IOVF after reading IOVF 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: When the WTCNT overflows in watchdog timer mode, the WDTOVF signal is output externally. If this bit is modified when the WDT is running, the counting-up may not be performed correctly. Rev. 1.00 Nov. 14, 2007 Page 364 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) Bit 5 Bit Name TME Initial Value 0 R/W R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled Count-up stops and WTCNT value is retained 1: Timer enabled 4, 3  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 2 to 0 CKS[2:0] 000 R/W Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pφ). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pφ) is 25 MHz. Bits 2 to 0 000: 001: 010: 011: 100: 101: 110: 111: Clock Ratio 1 × Pφ 1/64 × Pφ 1/128 × Pφ 1/256 × Pφ 1/512 × Pφ 1/1024 × Pφ 1/4096 × Pφ 1/16384 × Pφ Overflow Cycle 10.2 µs 655.4 µs 1.3 ms 2.6 ms 5.2 ms 10.5 ms 41.9 ms 167.8 ms Note: If the CKS2 to CKS0 bits are modified when the WDT is running, the counting-up may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. Rev. 1.00 Nov. 14, 2007 Page 365 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.3.3 Watchdog Reset Control/Status Register (WRCSR) WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal generated by watchdog timer counter (WTCNT) overflow. WRCSR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in software standby mode. Note: The method for writing to WRCSR differs from that for other registers to prevent erroneous writes. See section 10.3.4, Notes on Register Access, for details. Bit: 7 WOVF 6 RSTE 5 RSTS 4 - 3 - 2 - 1 - 0 - 0 Initial value: R/W: R/(W) 0 R/W 0 R/W 1 R 1 R 1 R 1 R 1 R Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W) Description Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode [Clearing condition] • When 0 is written to WOVF after reading WOVF 6 RSTE 0 R/W Reset Enable Selects whether to generate a signal to reset the LSI internally if WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Not reset when WTCNT overflows* 1: Reset when WTCNT overflows Note: * LSI not reset internally, but WTCNT and WTCSR reset within WDT. Rev. 1.00 Nov. 14, 2007 Page 366 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) Bit 5 Bit Name RSTS Initial Value 0 R/W R/W Description Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 to 0  All 1 R Reserved These bits are always read as 1. The write value should always be 1. 10.3.4 Notes on Register Access The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 10.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write Address: H'FFFE0002 15 H'5A 8 7 Write data 0 WTCSR write Address: H'FFFE0000 15 H'A5 8 7 Write data 0 Figure 10.2 Writing to WTCNT and WTCSR Rev. 1.00 Nov. 14, 2007 Page 367 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) (2) Writing to WRCSR WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte transfer or longword transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) are different, as shown in figure 10.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE bit is not affected. To write to the RSTE bit, the upper byte must be H'5A and the lower byte must be the write data. The value of bit 6 of the lower byte is transferred to the RSTE bit, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Address: H'FFFE0004 H'A5 8 7 H'00 0 Writing to the RSTE and RSTS bits Address: H'FFFE0004 15 H'5A 8 7 Write data 0 Figure 10.3 Writing to WRCSR (3) Reading from WTCNT, WTCSR, and WRCSR WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address H'FFFE0004. Byte transfer instructions must be used for reading from these registers. Rev. 1.00 Nov. 14, 2007 Page 368 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.4 10.4.1 WDT Usage Canceling Software Standby Mode The WDT can be used to cancel software standby mode with an interrupt such as an NMI interrupt. The procedure is described below. (The WDT does not operate when resets are used for canceling, so keep the RES pin low until clock oscillation settles.) 1. Before making a transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. After setting the STBY bit of the standby control register (STBCR: see section 11, PowerDown Modes) to 1, the execution of a SLEEP instruction puts the system in software standby mode and clock operation then stops. 4. The WDT starts counting by detecting the edge change of the NMI signal. 5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. 10.4.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the counter in WTCNT. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. However, the WDT counts up using the clock after the setting. 3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes operation. The WOVF flag in WRCSR is not set when this happens. Rev. 1.00 Nov. 14, 2007 Page 369 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 5. The counter stops at the value of H'00. 6. Before changing WTCNT after execution of the frequency change instruction, always confirm that the value of WTCNT is H'00 by reading from WTCNT. 10.4.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in WTCSR to 1 to set the type of count clock in the CKS2 to CKS0 bits, whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, and the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the WDTOVF signal is output externally (figure 10.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 64 × Pφ clock cycles. 5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated simultaneously with the WDTOVF signal. The internal reset signal is output for 128 × Pφ clock cycles. 6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin, the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0. Rev. 1.00 Nov. 14, 2007 Page 370 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) WTCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 WDTOVF signal 64 × Pφ clock cycles Internal reset signal* 128 × Pφ clock cycles [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. H'00 written in WTCNT WT/IT = 1 TME = 1 WDTOVF and internal reset generated Time WOVF = 1 H'00 written in WTCNT Figure 10.4 Operation in Watchdog Timer Mode Rev. 1.00 Nov. 14, 2007 Page 371 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.4.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS[2:0] bits in WTCSR, and set the initial value of the counter in WTCNT. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF bit in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting. WTCNT value Overflow Overflow Overflow Overflow H'FF H'00 WT/IT = 0 TME = 1 Time ITI ITI ITI ITI [Legend] ITI: Interval timer interrupt request generation Figure 10.5 Operation in Interval Timer Mode Rev. 1.00 Nov. 14, 2007 Page 372 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.5 Usage Notes Pay attention to the following points when using the WDT in either the interval timer or watchdog timer mode. 10.5.1 Timer Variation After timer operation has started, the period from the power-on reset point to the first count up timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The shortest such time period is thus one cycle of the peripheral clock, Pφ, while the longest is the result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent incrementation is in accord with the selected frequency division ratio. Accordingly, this time difference is referred to as timer variation. This also applies to the timing of the first incrementation after WTCNT has been written to during timer operation. 10.5.2 Prohibition against Setting H'FF to WTCNT When the value in WTCNT reaches H'FF, the WDT assumes that an overflow has occurred. Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or WDT reset will occur immediately, regardless of the current clock selection by the CKS[2:0] bits. 10.5.3 System Reset by WDTOVF Signal If the WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly. Avoid input of the WDTOVF signal to the RES pin of this LSI through glue logic circuits. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 10.6. Reset input (Low active) Reset signal to entire system (Low active) RES WDTOVF Figure 10.6 Example of System Reset Circuit Using WDTOVF Signal Rev. 1.00 Nov. 14, 2007 Page 373 of 1262 REJ09B0437-0100 Section 10 Watchdog Timer (WDT) 10.5.4 Manual Reset in Watchdog Timer Mode When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception handling will be pended until the CPU acquires the bus mastership. However, if the duration from generation of the manual reset to the bus cycle end is equal to or longer than the duration of the internal manual reset activated, the occurrence of the internal manual reset source is ignored instead of being pended, and the manual reset exception handling is not executed. Rev. 1.00 Nov. 14, 2007 Page 374 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes Section 11 Power-Down Modes In power-down modes, operation of some of the internal peripheral modules and of the CPU stops. This leads to reduced power consumption. These modes are canceled by a reset or interrupt. 11.1 11.1.1 Features Power-Down Modes This LSI has the following power-down modes and function: 1. Sleep mode 2. Software standby mode 3. Module standby function Table 11.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module states in each mode and the procedures for canceling each mode. Table 11.1 States of Power-Down Modes State* On-Chip Power-Down Mode Sleep mode Transition Conditions Execute SLEEP instruction with STBY bit cleared to 0 in STBCR • DMA address error Software standby mode Execute SLEEP instruction with STBY bit set to 1 in STBCR Halts Halts Held Halts (contents are held) • Module standby Set the MSTP bits in function STBCR2, STBCR3, and STBCR4 to 1 Runs Runs Held Specified module halts (contents are held) Specified module halts Autorefreshing • • Reset Clear MSTP bit to 0 Reset Halts Selfrefreshing • • NMI interrupt IRQ interrupt CPG Runs CPU Halts CPU On-Chip Peripheral Modules Runs External Memory Autorefreshing Canceling Procedure • • Interrupt Reset Register Memory Held Runs Note: * The pin state is retained or set to high impedance. For details, see appendix A, Pin States. Rev. 1.00 Nov. 14, 2007 Page 375 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2 Register Descriptions The following registers are used in power-down modes. Table 11.2 Register Configuration Register Name Standby control register Standby control register 2 Standby control register 3 Standby control register 4 System control register 1 System control register 2 System control register 3 Abbreviation STBCR STBCR2 STBCR3 STBCR4 SYSCR1 SYSCR2 SYSCR3 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'FF H'FF H'00 Address H'FFFE0014 H'FFFE0018 H'FFFE0408 H'FFFE040C H'FFFE0402 H'FFFE0404 H'FFFE0418 Access Size 8 8 8 8 8 8 8 Rev. 1.00 Nov. 14, 2007 Page 376 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.1 Standby Control Register (STBCR) STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode. This register is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7 STBY 6  5  4  3  2  1  0  Initial value: R/W: 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 7 Bit Name STBY Initial Value 0 R/W R/W Description Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts chip into sleep mode. 1: Executing SLEEP instruction puts chip into software standby mode. 6 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 377 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR2 is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7 MSTP 10 6 5 4 MSTP 7 3  2  1  0  MSTP MSTP 9 8 Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 7 Bit Name MSTP10 Initial Value 0 R/W R/W Description Module Stop 10 When the MSTP10 bit is set to 1, the supply of the clock to the H-UDI is halted. 0: H-UDI runs. 1: Clock supply to H-UDI halted. 6 MSTP9 0 R/W Module Stop 9 When the MSTP9 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs. 1: Clock supply to UBC halted. 5 MSTP8 0 R/W Module Stop 8 When the MSTP8 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs. 1: Clock supply to DMAC halted. Rev. 1.00 Nov. 14, 2007 Page 378 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes Bit 4 Bit Name MSTP7 Initial Value 0 R/W R/W Description Module Stop 7 When the MSTP7 bit is set to 1, the clock supply to the FPU is halted. After the MSTP7 bit is set to 1, the value of 0 cannot be written for clearing. In other words, once the MSTP7 bit is set to 1 and the clock supply to the FPU is temporarily halted, then the clock supply to the FPU cannot be restarted by clearing the MSTP7 bit to 0. If the clock supply to the FPU is halted and then restarted, a power-on reset must be performed for this LSI. 0: FPUC runs. 1: Clock supply to FPU halted. 3 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 379 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR3 is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7 HIZ 6 MSTP 36 5 MSTP 35 4 MSTP 34 3 MSTP 33 2 MSTP 32 1 0 MSTP MSTP 31 30 Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name HIZ Initial Value 0 R/W R/W Description Port High Impedance Selects whether the state of a specified pin is retained or the pin is placed in the high-impedance state in software standby mode. See appendix A, Pin States to determine the pin to which this control is applied. Do not set this bit when the TME bit of WTSCR of the WDT is 1. When setting the output pin to the highimpedance state, set the HIZ bit with the TME bit being 0. 0: The pin state is held in software standby mode. 1: The pin state is set to the high-impedance state in software standby mode. 6 MSTP36 0 R/W Module Stop 36 When the MSTP36 bit is set to 1, the supply of the clock to the STIF1 is halted. 0: STIF1 runs. 1: Clock supply to STIF1 halted. 5 MSTP35 0 R/W Module Stop 35 When the MSTP35 bit is set to 1, the supply of the clock to the STIF0 is halted. 0: STIF0 runs. 1: Clock supply to STIF0 halted. Rev. 1.00 Nov. 14, 2007 Page 380 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes Bit 4 Bit Name MSTP34 Initial Value 0 R/W R/W Description Module Stop 34 When the MSTP34 bit is set to 1, the supply of the clock to the CMT is halted. 0: CMT runs. 1: Clock supply to CMT halted. 3 MSTP33 0 R/W Module Stop 33 When the MSTP33 bit is set to 1, the supply of the clock to the IIC3 is halted. 0: IIC3 runs. 1: Clock supply to IIC3 halted. 2 MSTP32 0 R/W Module Stop 32 When the MSTP32 bit is set to 1, the supply of the clock to the SCIF2 is halted. 0: SCIF2 runs. 1: Clock supply to SCIF2 halted. 1 MSTP31 0 R/W Module Stop 31 When the MSTP31 bit is set to 1, the supply of the clock to the SCIF1 is halted. 0: SCIF1 runs. 1: Clock supply to SCIF1 halted. 0 MSTP30 0 R/W Module Stop 30 When the MSTP30 bit is set to 1, the supply of the clock to the SCIF0 is halted. 0: SCIF0 runs. 1: Clock supply to SCIF0 halted. Rev. 1.00 Nov. 14, 2007 Page 381 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown modes. STBCR4 is initialized to H'00 by a power-on reset but retains its previous value by a manual reset or in software standby mode. Only byte access is valid. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7  6 MSTP 46 5 MSTP 45 4 MSTP 44 3 MSTP 43 2 MSTP 42 1 0 MSTP MSTP 41 40 Initial Value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7 Bit Name  Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 MSTP46 0 R/W Module Stop 46 When the MSTP46 bit is set to 1, the supply of the clock to the SSI1 is halted. 0: SSI1 runs. 1: Clock supply to SSI1 halted. 5 MSTP45 0 R/W Module Stop 45 When the MSTP45 bit is set to 1, the supply of the clock to the SSI0 is halted. 0: SSI0 runs. 1: Clock supply to SSI0 halted. 4 MSTP44 0 R/W Module Stop 44 When the MSTP44 bit is set to 1, the supply of the clock to the HIF is halted. 0: HIF runs. 1: Clock supply to HIF halted. Rev. 1.00 Nov. 14, 2007 Page 382 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes Bit 3 Bit Name MSTP43 Initial Value 0 R/W R/W Description Module Stop 43 When the MSTP43 bit is set to 1, the supply of the clock to the A-DMAC is halted. 0: A-DMAC runs. 1: Clock supply to A-DMAC halted. 2 MSTP42 0 R/W Module Stop 42 When the MSTP42 bit is set to 1, the supply of the clock to the SDHI is halted. 0: SDHI runs. 1: Clock supply to SDHI halted. 1 MSTP41 0 R/W Module Stop 41 When the MSTP41 bit is set to 1, the supply of the clock to the USB is halted. 0: USB runs. 1: Clock supply to USB halted. 0 MSTP40 0 R/W Module Stop 40 When the MSTP40 bit is set to 1, the supply of the clock to the EtherC is halted. 0: EtherC runs. 1: Clock supply to EtherC halted. Rev. 1.00 Nov. 14, 2007 Page 383 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.5 System Control Register 1 (SYSCR1) SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM (high-speed). SYSCR1 is valid only in byte access. When an RAME bit is set to 1, the corresponding on-chip RAM (high-speed) area is enabled. When an RAME bit is cleared to 0, the corresponding on-chip RAM (high-speed) area cannot be accessed. In this case, an undefined value is returned when reading data or fetching an instruction from the on-chip RAM (high-speed), and writing to the on-chip RAM (high-speed) is ignored. The initial value of an RAME bit is 1. Note that when clearing the RAME bit to 0 to disable the on-chip RAM (high-speed), be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAME bit. If such an instruction is not executed, the data last written may not be written to the on-chip RAM (high-speed). Furthermore, an instruction to access the on-chip RAM (high-speed) should not be located immediately after the instruction to write to SYSCR1. If an onchip RAM (high-speed) access instruction is set, normal access is not guaranteed. If this bit is set to 1 to enable the on-chip RAM (high-speed), the SYSCR1 read instruction must be placed immediately after the SYSCR1 write instruction. If the on-chip RAM (high-speed) access instruction is placed immediately after the SYSCR1 write instruction, then normal access will not be guaranteed. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7  6  5  4  3 2 1 0 RAME3 RAME2 RAME1 RAME0 R/W: 1 R 1 R 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W Bit 7 to 4 Bit Name  Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 3 RAME3 1 R/W RAM Enable 3 (corresponding RAM addresses: Page 3 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) disabled 1: On-chip RAM (high-speed) enabled Rev. 1.00 Nov. 14, 2007 Page 384 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes Bit 2 Bit Name RAME2 Initial Value 1 R/W R/W Description RAM Enable 2 (corresponding RAM addresses: Page 2 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) disabled 1: On-chip RAM (high-speed) enabled 1 RAME1 1 R/W RAM Enable 1 (corresponding RAM addresses: Page 1 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) disabled 1: On-chip RAM (high-speed) enabled 0 RAME0 1 R/W RAM Enable 0 (corresponding RAM addresses: Page 0 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) disabled 1: On-chip RAM (high-speed) enabled Note: * For specific address for each page, see section 27, On-Chip RAM. Rev. 1.00 Nov. 14, 2007 Page 385 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.6 System Control Register 2 (SYSCR2) SYSCR2 is an 8-bit readable/writable register that enables or disables write to the on-chip RAM (high-speed). SYSCR2 is valid only in byte access. When the RAMWE bit is set to 1, writing to the on-chip RAM (high-speed) is enabled. When an RAMWE bit is cleared to 0, the corresponding on-chip RAM (high-speed) area cannot be written to. In this case, writing to the on-chip RAM (high-speed) is ignored. The initial value of an RAMWE bit is 1. Note that when clearing the RAMWE bit to 0 to disable the on-chip RAM, be sure to execute an instruction to read from or write to the same arbitrary address in each page before setting the RAMWE bit. If such an instruction is not executed, the data last written may not be written to the on-chip RAM (high-speed). Furthermore, an instruction to access the on-chip RAM (high-speed) should not be located immediately after the instruction to write to SYSCR2. If an on-chip RAM (high-speed) access instruction is set, normal access is not guaranteed. If this bit is set to 1 to enable writing to the on-chip RAM (high-speed), the SYSCR2 read instruction must be placed immediately after the SYSCR2 write instruction. If the on-chip RAM (high-speed) access instruction is placed immediately after the SYSCR2 write instruction, then normal access will not be guaranteed. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7  6  5  4  3 RAM WE3 2 RAM WE2 1 RAM WE1 0 RAM WE0 Initial value: R/W: 1 R 1 R 1 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W Bit 7 to 4 Bit Name  Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 1. 3 RAMWE3 1 R/W RAM Write Enable 3 (corresponding RAM addresses: Page 3 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) write disabled 1: On-chip RAM (high-speed) write enabled Rev. 1.00 Nov. 14, 2007 Page 386 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes Bit 2 Bit Name RAMWE2 Initial Value 1 R/W R/W Description RAM Write Enable 2 (corresponding RAM addresses: Page 2 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) write disabled 1: On-chip RAM (high-speed) write enabled 1 RAMWE1 1 R/W RAM Write Enable 1 (corresponding RAM addresses: Page 1 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) write disabled 1: On-chip RAM (high-speed) write enabled 0 RAMWE0 1 R/W RAM Write Enable 0 (corresponding RAM addresses: Page 0 in on-chip RAM (high-speed)*) 0: On-chip RAM (high-speed) write disabled 1: On-chip RAM (high-speed) write enabled Note: * For specific address for each page, see section 27, On-Chip RAM. Rev. 1.00 Nov. 14, 2007 Page 387 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.2.7 System Control Register 3 (SYSCR3) SYSCR3 is an 8-bit readable/writable register that controls the software reset for SSI0 and SSI1. SYSCR3 is valid only in byte access. Note: See section 11.4, Usage Notes, when writing data to this register. Bit: 7  6  5  4  3  2  1 SSI1 SRST 0 SSI0 SRST Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit 7 to 2 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 1 SSI1SRST 0 R/W SSI1 Software Reset Controls the SSI1 reset by software. 0: Cancels the SSI1 reset. 1: Places the SSI1 in reset state. 0 SSI0SRST 0 R/W SSI0 Software Reset Controls the SSI0 reset by software. 0: Cancels the SSI0 reset 1: Places the SSI0 in reset state. Rev. 1.00 Nov. 14, 2007 Page 388 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.3 11.3.1 (1) Operation Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin in clock mode 0, 1, or 3. (2) Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address error, or reset (power-on reset). • Canceling with an interrupt When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the priority level of the generated interrupt is equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU, or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt request is not accepted and sleep mode is not canceled. • Canceling with a DMA address error When a DMA address error occurs, sleep mode is canceled and DMA address error exception handling is executed. • Canceling with a reset Sleep mode is canceled by a power-on reset. Rev. 1.00 Nov. 14, 2007 Page 389 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.3.2 (1) Software Standby Mode Transition to Software Standby Mode The LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also halts in clock mode 0, 1, or 3. The contents of the CPU remain unchanged. Some registers of on-chip peripheral modules are, however, initialized. Regarding the states of on-chip peripheral module registers in software standby mode, see section 28.3, Register States in Each Operating Mode. The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely reflected in the SLEEP instruction. The procedure for switching to software standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. 2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate values to secure the specified oscillation settling time. 3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction. Rev. 1.00 Nov. 14, 2007 Page 390 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes (2) Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI or IRQ) or a reset (power-on reset). The CKIO pin starts outputting the clock in clock mode 0, 1, or 3. • Canceling with an interrupt When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) of the interrupt controller (INTC)) or the falling edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S and IRQn0S) in interrupt control register 1 (ICR1) of the interrupt controller (INTC)) is detected, clock oscillation is started. This clock pulse is supplied only to the oscillation settling counter (WDT) used to count the oscillation settling time. After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer control/status register (WTCSR) of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and NMI interrupt exception handling (IRQ interrupt exception handling in the case of IRQ) starts. However, if the priority level of IRQ interrupt is lower than the interrupt mask level set in the status register (SR) of the CPU, the interrupt request is not accepted and thus the software standby mode is not released. When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0] bits so that the WDT overflow period will be equal to or longer than the oscillation settling time. The clock output phase of the CKIO pin may be unstable immediately after detecting an interrupt and until software standby mode is canceled. When software standby mode is canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from software standby mode (when the clock is initiated after the oscillation settling). When software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation settling) (This is the same with the IRQ pin.) • Canceling with a reset When the RES pin is driven low, software standby mode is released and this LSI enters the power-on reset state. And if the RES pin is driven high after that, the power-on reset exception handling starts. Keep the RES pin low until the clock oscillation settles. Rev. 1.00 Nov. 14, 2007 Page 391 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.3.3 Software Standby Mode Application Example This example describes a transition to software standby mode on the falling edge of the NMI signal, and cancellation on the rising edge of the NMI signal. The timing is shown in figure 11.1. When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine, the STBY bit in STBCR is set to 1, and a SLEEP instruction is executed, software standby mode is entered. Thereafter, software standby mode is canceled when the NMI pin is changed from low to high level. Oscillator CK NMI pin NMIE bit STBY bit LSI state Program execution NMI exception handling Exception service routine Software standby mode Oscillation settling time NMI exception handling Figure 11.1 NMI Timing in Software Standby Mode (Application Example) Rev. 1.00 Nov. 14, 2007 Page 392 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.3.4 (1) Module Standby Function Transition to Module Standby Function Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode and sleep mode. Disable a module before placing it in the module standby mode. In addition, do not access the module's registers while it is in the module standby state. The register states are the same as those in software standby mode. For details, see section 28.3, Register States in Each Operating Mode. However, the states of the CMT registers are exceptional. In the CMT, all registers are initialized in software standby mode, but retain their previous values in module standby mode. (2) Canceling Module Standby Function The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on reset. When taking a module out of the module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to confirm that it has been cleared to 0. Rev. 1.00 Nov. 14, 2007 Page 393 of 1262 REJ09B0437-0100 Section 11 Power-Down Modes 11.4 Usage Notes When writing data to registers related to power-down modes, note the following suggestion. In a case where the CPU writes data to the registers related to power-down modes, if the CPU once starts executing the write instruction, the CPU keeps on executing the succeeding instructions without waiting for the completion of writing data to the registers. If reflecting a change of writing data to registers becomes necessary while the CPU is performing the succeeding instructions, execute a dummy read for the same register between the write instruction to the register and the succeeding instructions. Rev. 1.00 Nov. 14, 2007 Page 394 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Section 12 Ethernet Controller (EtherC) This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3 MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI) complying with this standard enables the Ethernet controller (EtherC) to perform transmission and reception of Ethernet/IEEE802.3 frames. This LSI has one MAC layer interface. The Ethernet controller is connected to the direct memory access controller for Ethernet controller (E-DMAC) inside this LSI, and carries out high-speed data transfer to and from the memory. Figure 12.1 shows a configuration of the EtherC. 12.1 • • • • • • Features Transmission and reception of Ethernet/IEEE802.3 frames Supports 10/100 Mbps receive/transfer Supports full-duplex and half-duplex modes Conforms to IEEE802.3u standard MII (Media Independent Interface) Magic Packet detection and Wake-On-LAN (WOL) signal output Conforms to IEEE802.3x flow control Rev. 1.00 Nov. 14, 2007 Page 395 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) E-DMAC EtherC E-DMAC interface MAC Transmit controller Receive controller Command status interface MII PHY Figure 12.1 Configuration of EtherC Rev. 1.00 Nov. 14, 2007 Page 396 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the EtherC. Table 12.1 Pin Configuration Port 0 Abbreviation I/O TX-CLK* Input Function Transmit Clock Timing reference signal for the TX-EN, MII_TXD3 to MII_TXD0, TX-ER signals 0 RX-CLK* Input Receive Clock Timing reference signal for the RX-DV, MII_RXD3 to MII_RXD0, RX-ER signals 0 TX-EN* Output Transmit Enable Indicates that transmit data is ready on pins MII_TXD3 to MII_TXD0. 0 0 0 MII_TXD3 to MII_TXD0* TX-ER* RX-DV* Output Output Input Transmit Data 4-bit transmit data Transmit Error Notifies the PHY-LSI of error during transmission Receive Data Valid Indicates that valid receive data is on pins MII_RXD3 to MII_RXD0. 0 0 0 0 0 0 MII_RXD3 to MII_RXD0* RX-ER* CRS COL MDC MDIO Input Input Input Input Output Input/ Output Receive Data 4-bit receive data Receive Error Identifies error state occurred during data reception. Carrier Detection Carrier detection signal Collision Detection Collision detection signal Management Data Clock Reference clock signal for information transfer via MDIO Management Data I/O Bidirectional signal for exchange of management information between this LSI and PHY Rev. 1.00 Nov. 14, 2007 Page 397 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Port 0 0 0 Note: Abbreviation I/O LNKSTA EXOUT WOL * Input Output Output Function Link Status Inputs link status from PHY General-Purpose External Output Signal indicating value of register-bit (ECMR0-ELB) Wake-On-LAN Signal indicating reception of Magic Packet MII signal conforming to IEEE802.3u Rev. 1.00 Nov. 14, 2007 Page 398 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3 Register Description The EtherC has the following registers. For details on addresses and access sizes of registers, see section 28, List of Registers. MAC Layer Interface Control Registers: • EtherC mode register (ECMR) • EtherC status register (ECSR) • EtherC interrupt permission register (ECSIPR) • PHY interface register (PIR) • MAC address high register (MAHR) • MAC address low register (MALR) • Receive frame length register (RFLR) • PHY status register (PSR) • Transmit retry over counter register (TROCR) • Delayed collision detect counter register (CDCR) • Lost carrier counter register (LCCR) • Carrier not detect counter register (CNDCR) • CRC error frame counter register (CEFCR) • Frame receive error counter register (FRECR) • Too-short frame receive counter register (TSFRCR) • Too-long frame receive counter register (TLFRCR) • Residual-bit frame counter register (RFCR) • Multicast address frame counter register (MAFCR) • IPG register (IPGR) • Automatic PAUSE frame set register (APR) • Manual PAUSE frame set register (MPR) • PAUSE frame retransfer count set register (TPAUSER) Rev. 1.00 Nov. 14, 2007 Page 399 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.1 EtherC Mode Register (ECMR) ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet controller. The settings in this register are normally made in the initialization process following a reset. The operating mode setting must not be changed while the transmitting and receiving functions are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit: 31 - 30 0 R 29 0 R 28 0 R 27 0 R 26 0 R 25 0 R 24 0 R 23 0 R 22 0 R 21 0 R 20 0 R 19 ZPF 0 R/W 18 PFR 0 R/W 17 RXF 0 R/W 16 TXF 0 R/W Initial value: R/W: Bit: 0 R 15 - 14 0 R 13 0 R 12 PRCEF 0 R/W 11 0 R 10 0 R 9 MPDE 0 R/W 8 0 R 7 0 R 6 RE 0 R/W 5 TE 0 R/W 4 0 R 3 ILB 0 R/W 2 ELB 0 R/W 1 DM 0 R/W 0 PRM 0 R/W Initial value: R/W: 0 R Bit 31 to 20 Initial Bit Name Value  All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 19 ZPF 0 R/W 0 time parameter PAUSE Frame Use Enable 0: Disables PAUSE frame control in which the TIME parameter is 0. The next frame is transmitted after the time indicated by the Timer value has elapsed. When the EtherC receives a PAUSE frame with the time indicated by the Timer value set to 0, the PAUSE frame is discarded. 1: Enables PAUSE frame control in which the TIME parameter is 0. A PAUSE frame with the Timer value set to 0 is transmitted when the number of data in the receive FIFO is less than the FCFTR value before the time indicated by the Timer value has not elapsed. When the EtherC receives a PAUSE frame with the time indicated by the Timer value set to 0, the transmit wait state is canceled. Rev. 1.00 Nov. 14, 2007 Page 400 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Bit 18 Initial Bit Name Value PFR 0 R/W R/W Description PAUSE Frame Receive Mode 0: PAUSE frame is not transferred to the E-DMAC 1: PAUSE frame is transferred to the E-DMAC 17 RXF 0 R/W Receive Flow Control Operating Mode 0: PAUSE frame detection function is disabled 1: Receive flow control function is enabled 16 TXF 0 R/W Transmit Flow Control Operating mode 0: Transmit flow control function is disabled 1: Transmit flow control function is enabled 15 to 13  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 PRCEF 0 R/W Permit Receive CRC Error Frame 0: A frame with a CRC error is received as a frame with an error. 1: A frame with a CRC error is received as a frame without an error. For a frame with an error, a CRC error is reflected in the ECSR of the E-DMAC and the status of the receive descriptor. For a frame without an error, the frame is received as normal frame. 11, 10  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 MPDE 0 R/W Magic Packet Detection Enable Enables or disables Magic Packet detection by hardware to allow activation from the Ethernet. 0: Magic Packet detection is not enabled 1: Magic Packet detection is enabled 8, 7  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 401 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Bit 6 Initial Bit Name Value RE 0 R/W R/W Description Reception Enable If a frame is being received when this bit is switched from receive function enabled (RE = 1) to disabled (RE = 0), the receive function will be enabled until reception of the corresponding frame is completed. 0: Receive function is disabled 1: Receive function is enabled 5 TE 0 R/W Transmission Enable If a frame is being transmitted when this bit is switched from transmit function enabled (TE = 1) to disabled (TE = 0), the transmit function will be enabled until transmission of the corresponding frame is completed. 0: Transmit function is disabled 1: Transmit function is enabled 4  0 R Reserved This bit is always read as 0. The write value should always be 0. 3 ILB 0 R/W Internal Loop Back Mode Specifies loopback mode in the EtherC. 0: Normal data transmission/reception is performed. 1: When DM = 1, data loopback is performed inside the MAC in the EtherC. 2 ELB 0 R/W External Loop Back Mode This bit value is output directly to this LSI’s generalpurpose external output pin (EXOUT). This bit is used for loopback mode directives, etc., in the LSI, using the EXOUT pin. In order for LSI loopback to be implemented using this function, the LSI must have a pin corresponding to the EXOUT pin. 0: Low-level output from the EXOUT pin 1: High-level output from the EXOUT pin 1 DM 0 R/W Duplex Mode Specifies the EtherC transfer method. 0: Half-duplex transfer is specified 1: Full-duplex transfer is specified Rev. 1.00 Nov. 14, 2007 Page 402 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Bit 0 Initial Bit Name Value PRM 0 R/W R/W Description Promiscuous Mode Setting this bit enables all Ethernet frames to be received. All Ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.). 0: EtherC performs normal operation 1: EtherC performs promiscuous mode operation 12.3.2 EtherC Status Register (ECSR) ECSR is a 32-bit readable/writable register and indicates the status in the EtherC. This status can be notified to the CPU by interrupts. When 1 is written to the PSRTO, LCHNG, MPD, and ICD, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ECSIPR. The interrupts generated due to this status register are indicated in the ECI bit in EESR. Initial value: 31 - 30 0 R 29 0 R 28 0 R 27 0 R 26 0 R 25 0 R 24 0 R 23 0 R 22 0 R 21 0 R 20 0 R 19 0 R 18 0 R 17 0 R 16 0 R Initial value: R/W: Bit: 0 R 15 - 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 PSRTO 0 R/W 3 0 R 2 LCHNG 0 R/W 1 MPD 0 R/W 0 ICD 0 R/W Initial value: R/W: 0 R Rev. 1.00 Nov. 14, 2007 Page 403 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 5  4 PSRTO 0 R/W PAUSE Frame Retransfer Retry Over Indicates that during the retransfer of PAUSE frames when the flow control is enabled, the number of retries has exceeded the upper limit set in the automatic PAUSE frame retransfer count set register (TPAUSER). 0: Number of PAUSE frame retransfers has not exceeded the upper limit 1: Number of PAUSE frame retransfers has exceeded the upper limit 3  0 R Reserved This bit is always read as 0. The write value should always be 0. 2 LCHNG 0 R/W Link Signal Change Indicates that the LNKSTA signal input from the PHY has changed from high to low or low to high. To check the current Link state, refer to the LMON bit in the PHY status register (PSR). 0: Changes in the LNKSTA signal are not detected 1: Changes in the LNKSTA signal are detected (high to low or low to high) 1 MPD 0 R/W Magic Packet Detection Indicates that a Magic Packet has been detected on the line. 0: Magic Packet has not been detected 1: Magic Packet has been detected 0 ICD 0 R/W Illegal Carrier Detection Indicates that the PHY has detected an illegal carrier on the line. If a change in the signal input from the PHY occurs before the software recognition period, the correct information may not be obtained. Refer to the timing specification for the PHY used. 0: LSI has not detected an illegal carrier on the line 1: LSI has detected an illegal carrier on the line Rev. 1.00 Nov. 14, 2007 Page 404 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.3 EtherC Interrupt Permission Register (ECSIPR) ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR. Bit: 31 - 30 0 R 29 0 R 28 0 R 27 0 R 26 0 R 25 0 R 24 0 R 23 0 R 22 0 R 21 0 R 20 0 R 19 0 R 18 0 R 17 0 R 16 0 R Initial value: R/W: Bit: 0 R 15 - 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 PSRTO IP 0 R/W 3 0 R 2 LCHNG IP 0 R/W 1 MPD IP 0 R/W 0 ICD IP 0 R/W Initial value: R/W: 0 R Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 5  4 PSRTOIP 0 R/W PAUSE Frame Retransfer Retry Over Interrupt Enable 0: Interrupt notification by the PSRTO bit is disabled 1: Interrupt notification by the PSRTO bit is enabled 3 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 LCHNGIP 0 R/W LINK Signal Changed Interrupt Enable 0: Interrupt notification by the LCHNG bit is disabled 1: Interrupt notification by the LCHNG bit is enabled 1 MPDIP 0 R/W Magic Packet Detection Interrupt Enable 0: Interrupt notification by the MPD bit is disabled 1: Interrupt notification by the MPD bit is enabled 0 ICDIP 0 R/W Illegal Carrier Detection Interrupt Enable 0: Interrupt notification by the ICD bit is disabled 1: Interrupt notification by the ICD bit is enabled Rev. 1.00 Nov. 14, 2007 Page 405 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.4 PHY Interface Register (PIR) PIR is a 32-bit readable/writable register that provides a means of accessing the PHY registers via the MII. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 MDI Undefined 2 MDO 1 MMD 0 MDC Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 31 to 4  3 2 MDI MDO Undefined R 0 MII Management Data-In Indicates the level of the MDIO pin. R/W MII Management Data-Out Outputs the value set to this bit from the MDIO pin, when the MMD bit is 1. 1 MMD 0 R/W MII Management Mode Specifies the data read/write direction with respect to the MII. 0: Read direction is indicated 1: Write direction is indicated 0 MDC 0 R/W MII Management Data Clock Outputs the value set to this bit from the MDC pin and supplies the MII with the management data clock. For the method of accessing the MII registers, see section 12.4.4, Accessing MII Registers. Rev. 1.00 Nov. 14, 2007 Page 406 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.5 MAC Address High Register (MAHR) MAHR is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA[47:32] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 MA[31:16] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description MAC Address Bits These bits are used to set the upper 32 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'01234567. 31 to 0 MA[47:16] Rev. 1.00 Nov. 14, 2007 Page 407 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.6 MAC Address Low Register (MALR) MALR is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit MAC address. The settings in this register are normally made in the initialization process after a reset. The MAC address setting must not be changed while the transmitting and receiving functions are enabled. To switch the MAC address setting, return the EtherC and E-DMAC to their initial states by means of the SWR bit in EDMR before making settings again. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 MA[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 16  15 to 0 MA[15:0] All 0 R/W MAC Address Bits 15 to 0 These bits are used to set the lower 16 bits of the MAC address. If the MAC address is 01-23-45-67-89-AB (hexadecimal), the value set in this register is H'000089AB. Rev. 1.00 Nov. 14, 2007 Page 408 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.7 Receive Frame Length Register (RFLR) RFLR is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes) that can be received by this LSI. The settings in this register must not be changed while the receiving function is enabled. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 14 - 0 R 13 - 0 R 12 - 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 bit: 15 - RFL[11:0] Initial value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 12  11 to 0 RFL[11:0] All 0 R/W Receive Frame Length 11 to 0 The frame length described here refers to all fields from the destination address up to and including the CRC data. Frame contents from the destination address up to and including the data are actually transferred to memory. CRC data is not included in the transfer. When data that exceeds the specified value is received, the part of the data that exceeds the specified value is discarded. H'000 to H'5EE: 1,518 bytes H'5EF: 1,519 bytes H'5F0: 1,520 bytes : : H'7FF: 2,047 bytes H'800 to H'FFF: 2,048 bytes Rev. 1.00 Nov. 14, 2007 Page 409 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.8 PHY Status Register (PSR) PSR is a read-only register that can read interface signals from the PHY. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 LMON undefined Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R R Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 1  0 LMON 0 R LNKSTA Pin Status The Link status can be read by connecting the Link signal output from the PHY to the LNKSTA pin. For the polarity, refer to the PHY specifications to be connected. Rev. 1.00 Nov. 14, 2007 Page 410 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.9 Transmit Retry Over Counter Register (TROCR) TROCR is a 32-bit counter that indicates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. When 16 transmission attempts have failed, TROCR is incremented by 1. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TROC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 TROC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Transmit Retry Over Count These bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. 31 to 0 TROC[31:0] Rev. 1.00 Nov. 14, 2007 Page 411 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.10 Delayed Collision Detect Counter Register (CDCR) CDCR is a 32-bit counter that indicates the number of delayed collisions on all lines from a start of transmission. When the value in this register reaches H'FFFFFFFF, count-up is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COSDC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 COSDC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value R/W R/W Description Delayed Collision Detect Count These bits indicate the number of delayed collisions on all lines from a start of transmission. 31 to 0 COSDC[31:0] All 0 Rev. 1.00 Nov. 14, 2007 Page 412 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.11 Lost Carrier Counter Register (LCCR) LCCR is a 32-bit counter that indicates the number of times the carrier was lost during data transmission. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by writing to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LCC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 LCC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Lost Carrier Count These bits indicate the number of times the carrier was lost during data transmission. 31 to 0 LCC[31:0] Rev. 1.00 Nov. 14, 2007 Page 413 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.12 Carrier Not Detect Counter Register (CNDCR) CNDCR is a 32-bit counter that indicates the number of times the carrier could not be detected while the preamble was being sent. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNDC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 CNDC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Carrier Not Detect Count These bits indicate the number of times the carrier was not detected. 31 to 0 CNDC[31:0] Rev. 1.00 Nov. 14, 2007 Page 414 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.13 CRC Error Frame Counter Register (CEFCR) CEFCR is a 32-bit counter that indicates the number of times a frame with a CRC error was received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CEFC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 CEFC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description CRC Error Frame Count These bits indicate the count of CRC error frames received. 31 to 0 CEFC[31:0] Rev. 1.00 Nov. 14, 2007 Page 415 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.14 Frame Receive Error Counter Register (FRECR) FRECR is a 32-bit counter that indicates the number of frames input from the PHY for which a receive error was indicated by the RX-ER pin. FRECR is incremented each time the RX-ER pin becomes active. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FREC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 FREC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Frame Receive Error Count These bits indicate the count of errors during frame reception. 31 to 0 FREC[31:0] Rev. 1.00 Nov. 14, 2007 Page 416 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.15 Too-Short Frame Receive Counter Register (TSFRCR) TSFRCR is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have been received. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TSFC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 TSFC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Too-Short Frame Receive Count These bits indicate the count of frames received with a length of less than 64 bytes. 31 to 0 TSFC[31:0] Rev. 1.00 Nov. 14, 2007 Page 417 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.16 Too-Long Frame Receive Counter Register (TLFRCR) TLFRCR is a 32-bit counter that indicates the number of frames received with a length exceeding the value specified by the receive frame length register (RFLR). When the value in this register reaches H'FFFFFFFF, the count is halted. TLFRCR is not incremented when a frame containing residual bits is received. In this case, the reception of the frame is indicated in the residual-bit frame counter register (RFCR). The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TLFC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 TLFC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Too-Long Frame Receive Count These bits indicate the count of frames received with a length exceeding the value in RFLR. 31 to 0 TLFC[31:0] Rev. 1.00 Nov. 14, 2007 Page 418 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.17 Residual-Bit Frame Counter Register (RFCR) RFCR is a 32-bit counter that indicates the number of frames received containing residual bits (less than an 8-bit unit). When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 RFC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Residual-Bit Frame Count These bits indicate the count of frames received containing residual bits. 31 to 0 RFC[31:0] Rev. 1.00 Nov. 14, 2007 Page 419 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.18 Multicast Address Frame Counter Register (MAFCR) MAFCR is a 32-bit counter that indicates the number of frames received with a specified multicast address. When the value in this register reaches H'FFFFFFFF, the count is halted. The counter value is cleared to 0 by a write to this register with any value. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MAFC[31:16] Initial value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 MAFC[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Multicast Address Frame Count These bits indicate the count of multicast frames received. 31 to 0 MAFC[31:0 Rev. 1.00 Nov. 14, 2007 Page 420 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.19 IPG Register (IPGR) IPGR sets the IPG (Inter Packet Gap). This register must not be changed while the transmitting and receiving functions of the EtherC mode register (ECMR) are enabled. (For details, refer to section 12.4.6, Operation by IPG Setting.) Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 3 2 IPG[4:0] 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 5  4 to 0 IPG[4:0] H'13 R/W Inter Packet Gap Sets the IPG value every 4-bit time. H'00: 20-bit time H'01: 24-bit time : : : : H'13: 96-bit time (Initial value) H'1F: 144-bit time Rev. 1.00 Nov. 14, 2007 Page 421 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.20 Automatic PAUSE Frame Set Register (APR) APR sets the TIME parameter value of the automatic PAUSE frame. When transmitting the automatic PAUSE frame, the value set in this register is used as the TIME parameter of the PAUSE frame. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 AP[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 16  15 to 0 AP[15:0] All 0 R/W Automatic PAUSE Sets the TIME parameter value of the automatic PAUSE frame. At this time, 1 bit means 512-bit time. Rev. 1.00 Nov. 14, 2007 Page 422 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.21 Manual PAUSE Frame Set Register (MPR) MPR sets the TIME parameter value of the manual PAUSE frame. When transmitting the manual PAUSE frame, the value set to this register is used as the TIME parameter of the PAUSE frame. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 MP[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 16  15 to 0 MP[15:0] All 0 R/W Manual PAUSE Sets the TIME parameter value of the manual PAUSE frame. At this time, 1 bit means 512-bit time. Read values are undefined. Rev. 1.00 Nov. 14, 2007 Page 423 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.3.22 PAUSE Frame Retransfer Count Set Register (TPAUSER) TPAUSER sets the upper limit of the number of times of the PAUSE frame retransfer. TPAUSER must not be changed while the transmitting function is enabled. Bit: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - Initial value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 TPAUSE[15:0] Initial value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 16 Bit Name  Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 TPAUSE[15: All 0 0] R/W Upper Limit of the Number of Times of PAUSE Frame Retransfer H'0000: Unlimited number of times of retransfer H'0001: Retransfer once : : H'FFFF: Number of times of retransfer is 65535 Rev. 1.00 Nov. 14, 2007 Page 424 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.4 Operation The overview of the Ethernet controller (EtherC) are shown below. The EtherC transmits and receives PAUSE frames conforming to the Ethernet/IEEE802.3 frames. 12.4.1 Transmission The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines by PHY-LSI. Figure 12.3 shows the state transition of the EtherC transmitter. Rev. 1.00 Nov. 14, 2007 Page 425 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) TE set Idle FDPX Start of transmission (preamble transmission) Carrier non-detection Retransfer initiation Transmission halted HDPX TE reset Carrier detection HDPX Carrier detection Reset FDPX Collision Carrier detection Retransfer processing*1 Failure of 15 retransfer attempts or collision after 512-bit time Carrier non-detection Collision SFD transmission Error Collision*2 Error detection Error notification Error Data transmission Collision*2 Error [Legend] FDPX: Full Duplex CRC Normal transmission HDPX: Half Duplex transmission SFD: Start Frame Delimiter Notes: 1. Transmission retry processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. Transmission is retried only when data of 512 bits or less (including the preamble and SFD) is transmitted. When a collision is detected during the transmission of data greater than 512 bits, only jam is transmitted and transmission based on the back-off algorithm is not retried. Figure 12.2 EtherC Transmitter State Transitions 1. When the transmit enable (TE) bit is set, the transmitter enters the transmit idle state. 2. When a transmit request is issued by the transmit E-DMAC, the EtherC sends the preamble after a transmission delay equivalent to the frame interval time. If full-duplex transfer is selected, which does not require carrier detection, the preamble is sent as soon as a transmit request is issued by the E-DMAC. Rev. 1.00 Nov. 14, 2007 Page 426 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 3. The transmitter sends the SFD, data, and CRC sequentially. At the end of transmission, the transmit E-DMAC generates a transmission complete interrupt (TC). If a collision or the carrier-not-detected state occurs during data transmission, these are reported as interrupt sources. 4. After waiting for the frame interval time, the transmitter enters the idle state, and if there is more transmit data, continues transmitting. 12.4.2 Reception The EtherC receiver separates the frame data (MII into preamble, SFD, DA (destination address), SA (Source address), type/length, Data, and CRC data) and outputs DA, SA, type/length, Data to the E-DMAC. Figure 12.3 shows the state transitions of the EtherC receiver. Illegal carrier detection RX-DV negation Idle RE set Preamble detection Start of frame reception Wait for SFD reception SFD reception Destination address reception Own destination address or broadcast or multicast or promiscuous Data reception End of reception CRC reception Reception halted RE reset Promiscuous and other station destination address Reset Error notification* Error detection Receive error detection Receive error detection Normal reception [Legend] SFD: Start frame delimiter Note: * The error frame also transmits data to the buffer. Figure 12.3 EtherC Receiver State Transmissions Rev. 1.00 Nov. 14, 2007 Page 427 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 1. When the receive enable (RE) bit is set, the receiver enters the receive idle state. 2. When an SFD (start frame delimiter) is detected after a receive packet preamble, the receiver starts receive processing. Discards a frame with an invalid pattern. 3. In normal mode, if the destination address matches the receiver’s own address, or if broadcast or multicast transmission or promiscuous mode is specified, the receiver starts data reception. 4. Following data reception from the MII, the receiver carries out a CRC check. The result is indicated as a status bit in the descriptor after the frame data has been written to memory. Reports an error status in the case of an abnormality. 5. After one frame has been received, if the receive enable bit is set (RE = 1) in the EtherC mode register, the receiver prepares to receive the next frame. 12.4.3 MII Frame Timing Each MII Frame timing is shown in figure 12.4. TX-CLK TX-EN TXD3 to TXD0 TX-ER CRS COL Preamble SFD Data CRC Figure 12.4 (1) MII Frame Transmit Timing (Normal Transmission) TX-CLK TX-EN MII_TXD3 to MII_TXD0 Preamble JAM TX-ER CRS COL Figure 12.4 (2) MII Frame Transmit Timing (Collision) Rev. 1.00 Nov. 14, 2007 Page 428 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) TX-CLK TX-EN MII_TXD3 to MII_TXD0 TX-ER CRS COL Preamble SFD Data Figure 12.4 (3) MII Frame Transmit Timing (Transmit Error) RX-CLK RX-DV MII_RXD3 to MII_RXD0 Preamble SFD Data CRC RX-ER Figure 12.4 (4) MII Frame Receive Timing (Normal Reception) RX-CLK RX-DV MII_RXD3 to MII_RXD0 RX-ER Preamble SFD Data XXXX Figure 12.4 (5) MII Frame Receive Timing (Reception Error (1)) RX-CLK RX-DV MII_RXD3 to MII_RXD0 XXXX 1110 XXXX RX-ER Figure 12.4 (6) MII Fame Receive Timing (Reception Error (2)) Rev. 1.00 Nov. 14, 2007 Page 429 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.4.4 Accessing MII Registers MII registers in the PHY are accessed via this LSI’s PHY interface register (PIR). Connection is made as a serial interface in accordance with the MII frame format specified in IEEE802.3u. MII Management Frame Format: The format of an MII management frame is shown in figure 12.8. To access an MII register, a management frame is implemented by the program in accordance with the procedures shown in MII Register Access Procedure. Access Type Item Number of bits Read Write [Legend] PRE: ST: OP: PHYAD: PRE 32 1..1 1..1 ST 2 01 01 OP 2 10 01 MII Management Frame PHYAD 5 00001 00001 REGAD 5 RRRRR RRRRR TA 2 Z0 10 DATA 16 D..D D..D X IDLE 32 consecutive 1s Write of 01 indicating start of frame Write of code indicating access type Write of 0001 if the PHY address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY address. REGAD: Write of 0001 if the register address is 1 (sequential write starting with the MSB). This bit changes depending on the PHY register address. TA: Time for switching data transmission source on MII interface (a) Write: 10 written (b) Read: Bus release (notation: Z0) performed DATA: 16-bit data. Sequential write or read from MSB (a) Write: 16-bit data write (b) Read: 16-bit data read IDLE: Wait time until next MII management format input (a) Write: Independent bus release (notation: X) performed (b) Read: Bus already released in TA; control unnecessary Figure 12.5 MII Management Frame Format Rev. 1.00 Nov. 14, 2007 Page 430 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) MII Register Access Procedure: The program accesses MII registers via the PHY interface register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. Figure 12.9 shows the MII register access timing. The timing will differ depending on the PHY type. (1) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 MDC MDO (2) Write to PHY interface register MMD = 1 MDO = write data MDC = 1 (1) (2) (3) 1-bit data write timing relationship (3) Write to PHY interface register MMD = 1 MDO = write data MDC = 0 Figure 12.6 (1) 1-Bit Data Write Flowchart Rev. 1.00 Nov. 14, 2007 Page 431 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 0 MDC MDO (2) Write to PHY interface register (1) (2) MMD = 0 MDC = 1 (3) Bus release timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0 Figure 12.6 (2) Bus Release Flowchart (TA in Read in Figure 12.5) (1) Write to PHY interface register MMD = 0 MDC = 1 MDC MDI (2) Read from PHY interface register read MMD = 0 MMC = 1 MDI is read data (1) (2) (3) 1-bit data read timing relationship (3) Write to PHY interface register MMD = 0 MDC = 0 Figure 12.6 (3) 1-Bit Data Read Flowchart Rev. 1.00 Nov. 14, 2007 Page 432 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) (1) Write to PHY interface register MMD = 0 MDC = 0 MDC MDO (1) Independent bus release timing relationship Figure 12.6 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 12.5) 12.4.5 Magic Packet Detection The EtherC has a Magic Packet detection function. This function provides a Wake-On-LAN (WOL) facility that activates various peripheral devices connected to a LAN from the host device or other source. This makes it possible to construct a system in which a peripheral device receives a Magic Packet sent from the host device or other source, and activates itself. When the Magic Packet is detected, data is stored in the FIFO of the E-DMAC by the broadcast packet that has received data previously and the EtherC is notified of the receiving status. To return to normal operation from the interrupt processing, initialize the EtherC and E-DMAC by using the SWR bit in the E-DMAC mode register (EDMR). With a Magic Packet, reception is performed regardless of the destination address. As a result, this function is valid, and the WOL pin enabled, only in the case of a match with the destination address specified by the format in the Magic Packet. Further information on Magic Packets can be found in the technical documentation published by AMD Corporation. The procedure for using the WOL function with this LSI is as follows. 1. Disable interrupt source output by means of the various interrupt enable/mask registers. 2. Set the Magic Packet detection enable bit (MPDE) in the EtherC mode register (ECMR). 3. Set the Magic Packet detection interrupt enable bit (MPDIP) in the EtherC interrupt enable register (ECSIPR) to the enable setting. 4. If necessary, set the CPU operating mode to sleep mode or set supporting functions to module standby mode. 5. When a Magic Packet is detected, an interrupt is sent to the CPU. The WOL pin notifies peripheral LSIs that the Magic Packet has been detected. Rev. 1.00 Nov. 14, 2007 Page 433 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.4.6 Operation by IPG Setting The EtherC has a function to change the non-transmission period IPG (Inter Packet Gap) between transmit frames. By changing the set values of the IPG setting register (IPGR), the transmission efficiency can be raised and lowered from the standard value. IPG settings are prescribed in IEEE802.3 standards. When changing settings, adequately check that the respective devices can operate smoothly on the same network. Case A (short IPG) [1] [2] [3] [4] [5] ...... Packet Case B (long IPG) IPG* [1] [2] [3] [4] ...... Note: * IPG may be longer than the set value, depending on the state of the circuit and the system bus. Figure 12.7 Changing IPG and Transmission Efficiency 12.4.7 Flow Control The EtherC supports flow control functions conforming to IEEE802.3x in full-duplex operations. Flow control can be applied to both receive and transmit operations. The methods for transmitting PAUSE frames when controlling flow are as follows: Automatic PAUSE Frame Transmission: For receive frames, PAUSE frames are automatically transmitted when the number of data in the receive FIFO (included in E-DMAC) reaches the value set in the flow control FIFO threshold register (FCFTR) of the E-DMAC. The TIME parameter included in the PAUSE frame at this time is set by the automatic PAUSE frame setting register (APR). The automatic PAUSE frame transmission is repeated until the number of data in the receive FIFO becomes less than the FCFTR setting as the receive data is read from the FIFO. The upper limit of the number of retransfers of the PAUSE frame can also be set by the automatic PAUSE frame retransfer count set register (TPAUSER). In this case, PAUSE frame transmission is repeated until the number of data becomes FCFTR value set or below, or the number of transmits reaches the value set by TPAUSER. The automatic PAUSE frame transmission is enabled when the TXF bit in the EtherC mode register (ECMR) is 1. Rev. 1.00 Nov. 14, 2007 Page 434 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) Manual PAUSE Frame Transmission: PAUSE frames are transmitted by directives from the software. When writing the Timer value to the manual PAUSE frame set register (MPR), manual PAUSE frame transmission is started. With this method, PAUSE frame transmission is carried out only once. PAUSE Frame Reception: The next frame is not transmitted until the time indicated by the Timer value elapses after receiving a PAUSE frame. However, the transmission of the current frame is continued. A received PAUSE frame is valid only when the RXF bit in the EtherC mode register (ECMR) is set to 1. 12.5 Connection to PHY-LSI Figure 12.8 shows the example of connection to a DP83846AVHG by National Semiconductor Corporation. MII (Media Independent Interface) DP83846AVHG TX_ER TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK MDC MDIO RXD3 RXD2 RXD1 RXD0 RX_CLK CRS COL RX_DV RX_ER This LSI TX-ER MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 TX-EN TX-CLK MDC MDIO MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 RX-CLK CRS COL RX-DV RX-ER Figure 12.8 Example of Connection to DP83846AVHG Rev. 1.00 Nov. 14, 2007 Page 435 of 1262 REJ09B0437-0100 Section 12 Ethernet Controller (EtherC) 12.6 Usage Notes • Conditions for Setting LCHNG Bit Even if the level of the signal input to the LNKSTA pin is not changed, the LCHNG bit in ECSR may be set. It may happen when the pin function is changed from port to LNKSTA by PCCRH2 of the PFC or when a software reset caused by the SWR bit in EDMR is cleared while the LNKSTA pin is being driven high. This is because the LNKSTA signal is internally fixed low when the pin functions as a port or during the software reset state regardless of the external pin level. Clear the LCHNG bit before setting the LCHNGIP bit in ECSIPR not to request a LINK signal changed interrupt accidentally. Rev. 1.00 Nov. 14, 2007 Page 436 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) This LSI includes a direct memory access controller (E-DMAC) directly connected to the Ethernet controller (EtherC). A large proportion of buffer management is controlled by the E-DMAC itself using descriptors. This lightens the load on the CPU and enables efficient control of data transfer. Figure 13.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive buffers in memory. 13.1 Features The E-DMAC has the following features: • • • • The load on the CPU is reduced by means of a descriptor management system Transmit/receive frame status information is indicated in descriptors Achieves efficient system bus utilization through the use of block transfer (16-byte units) Supports single-frame/multi-buffer operation This LSI Internal bus Transmit buffer Transmit descriptor External bus interface E-DMAC Receive buffer Receive descriptor Internal bus interface Descriptor information Transmit DMAC Descriptor information Receive DMAC Transmit FIFO Receive FIFO EtherC External memory Figure 13.1 Configuration of E-DMAC, and Descriptors and Buffers Rev. 1.00 Nov. 14, 2007 Page 437 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2 Register Descriptions The E-DMAC has the following registers. For addresses and access sizes of these registers, see section 28, List of Registers. • • • • • • • • • • • • • • • • • • • • • • • E-DMAC mode register (EDMR) E-DMAC transmit request register (EDTRR) E-DMAC receive request register (EDRRR) Transmit descriptor list address register (TDLAR) Receive descriptor list address register (RDLAR) EtherC/E-DMAC status register (EESR) EtherC/E-DMAC status interrupt permission register (EESIPR) Transmit/receive status copy enable register (TRSCER) Receive missed-frame counter register (RMFCR) Transmit FIFO threshold register (TFTR) FIFO depth register (FDR) Receiving method control register (RMCR) E-DMAC operation control register (EDOCR) Receive buffer write address register (RBWAR) Receive descriptor fetch address register (RDFAR) Transmit buffer read address register (TBRAR) Transmit descriptor fetch address register (TDFAR) Flow control FIFO threshold register (FCFTR) Receive data padding setting register (RPADIR) Transmit interrupt register (TRIMD) Checksum mode register (CSMR) Checksum skipped bytes monitor register (CSSBM) Checksum monitor register (CSSMR) Rev. 1.00 Nov. 14, 2007 Page 438 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.1 E-DMAC Mode Register (EDMR) EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC. The settings in this register are normally made in the initialization process following a reset. If the EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal data may be sent onto the line. Operating mode settings must not be changed while the transmit and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC modules are got into at their initial state by means of the software reset bit (SWR) in this register, then make new settings. It takes 64 cycles of the internal bus clock Bφ to initialize the EtherC and E-DMAC. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 cycles of the internal bus clock Bφ has elapsed. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11  10  9  8  7  6 DE 5 DL1 4 DL0 3  2  1  0 SWR Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R/W Bit 31 to 7 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 6 DE 0 R/W E-DMAC Data Endian Convert Selects whether or not the endian format is converted on data transfer by the E-DMAC. However, the endian format of the descriptors and E-DMAC register values are not converted regardless of this bit setting. 0: Endian format not converted (big endian) 1: Endian format converted (little endian) Rev. 1.00 Nov. 14, 2007 Page 439 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 5 4 Bit Name DL1 DL0 Initial value 0 0 R/W R/W R/W Description Descriptor Length These bits specify the descriptor length. 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: Reserved (setting prohibited) 3 to 1  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 SWR 0 R/W Software Reset Writing 1 in this bit initializes registers of the E-DMAC other than TDLAR, RDLAR, and RMFCR and registers of the EtherC. While a software reset is being executed (64 cycles of the internal bus clock Bφ), accesses to the all Ethernet-related registers are prohibited. Software reset period (example): When Bφ = 100 MHz: 0.64 µS When Bφ = 75 MHz: 0.85 µS This bit is always read as 0. 0: Writing 0 is ignored (E-DMAC operation is not affected) 1: Writing 1 resets the EtherC and E-DMAC and then automatically cleared Rev. 1.00 Nov. 14, 2007 Page 440 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.2 E-DMAC Transmit Request Register (EDTRR) The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. When transmission of one frame is completed, the next descriptor is read. If the transmit descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the transmit DMAC is halted. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 TR Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TR 0 R/W Transmit Request 0: Transmission-halted state. Writing 0 does not stop transmission. Termination of transmission is controlled by the active bit in the transmit descriptor 1: Start of transmission. The relevant descriptor is read and a frame is sent with the transmit active bit set to 1 Rev. 1.00 Nov. 14, 2007 Page 441 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.3 E-DMAC Receive Request Register (EDRRR) EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. When the receive request bit is set, the E-DMAC reads the relevant receive descriptor. If the receive descriptor active bit in the descriptor has the "active" setting, the E-DMAC prepares for a receive request from the EtherC. When one receive buffer of data has been received, the E-DMAC reads the next descriptor and prepares to receive the next frame. If the receive descriptor active bit in the descriptor has the "inactive" setting, the RR bit is cleared and operation of the receive DMAC is halted. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0 RR 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RR 0 R/W Receive Request 0: The receive function is disabled* 1: A receive descriptor is read and the E-DMAC is ready to receive Note: * If the receive function is disabled during frame reception, write-back is not performed successfully to the receive descriptor. Following pointers to read a receive descriptor become abnormal and the E-DMAC cannot operate successfully. In this case, to make the E-DMAC reception enabled again, execute a software reset by the SWR bit in EDMR. To make the E-DMAC reception disabled without executing a software reset, set the RE bit in ECMR. Next, after the E_DMAC has completed the reception and write-back to the receive descriptor has been confirmed, disable the receive function of this register. Rev. 1.00 Nov. 14, 2007 Page 442 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.4 Transmit Descriptor List Address Register (TDLAR) TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during transmission. Modifications to this register should only be made while transmission is disabled by the TR bit (= 0) in the E-DMAC transmit request register (EDTRR). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDLA[31:16] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 TDLA[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name TDLA[31:0] Initial value All 0 R/W R/W Description Transmit Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: TDLA3 to TDLA0 = 0000 32-byte boundary: TDLA4 to TDLA0 = 00000 64-byte boundary: TDLA5 to TDLA0 = 000000 Rev. 1.00 Nov. 14, 2007 Page 443 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.5 Receive Descriptor List Address Register (RDLAR) RDLAR is a 32-bit readable/writable register that specifies the start address of the receive descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length indicated by the DL bit in EDMR. This register must not be written to during reception. Modifications to this register should only be made while reception is disabled by the RR bit (= 0) in the E-DMAC Receive Request Register (EDRRR). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDLA[31:16] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 RDLA[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name RDLA[31:0] Initial value All 0 R/W R/W Description Receive Descriptor Start Address The lower bits are set as follows according to the specified descriptor length. 16-byte boundary: RDLA3 to RDLA0 = 0000 32-byte boundary: RDLA4 to RDLA0 = 00000 64-byte boundary: RDLA5 to RDLA0 = 000000 Rev. 1.00 Nov. 14, 2007 Page 444 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.6 EtherC/E-DMAC Status Register (EESR) EESR is a 32-bit readable/writable register that shows communications status information on the E-DMAC in combination with the EtherC. The information in this register is reported in the form of interrupts. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit and not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt permission register (EESIPR). The interrupts generated by this register are EINT0. For interrupt priority, see section 6.5, Interrupt Exception Handling Vector Table and Priority. Bit: 31  30 TWB 29  28  27  26 TABT 25 24 23 ADE 22 ECI 21 TC 20 TDE 19 TFUF 18 FR 17 RDE 16 RFOF RABT RFCOF Initial Value: R/W: 0 R 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15  14  13  12  11 CND 10 DLC 9 CD 8 TRO 7 RMAF 6  5  4 RRF 3 RTLF 2 RTSF 1 PRE 0 CERF Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 Bit Name  Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 30 TWB 0 R/W Write-Back Complete Indicates that write-back from the E-DMAC to the corresponding descriptor has completed. This operation is enabled when the TIS bit in TRIMD is set to 1. 0: Write-back has not completed, or no transmission directive 1: Write-back has completed 29 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 445 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 26 Bit Name TABT Initial value 0 R/W R/W Description Transmit Abort Detection Indicates that frame transmission by the EtherC has been aborted because of an error during transmission. 0: Frame transmission has not been aborted or no transmit directive 1: Frame transmit has been aborted 25 RABT 0 R/W Receive Abort Detection Indicates that frame reception by the EtherC has been aborted because of an error during reception. 0: Frame reception has not been aborted or no receive directive 1: Frame receive has been aborted 24 RFCOF 0 R/W Receive Frame Counter Overflow Indicates that the receive FIFO frame counter has overflowed. 0: Receive frame counter has not overflowed 1: Receive frame counter overflows 23 ADE 0 R/W Address Error Indicates that the memory address that the E-DMAC tried to transfer is found illegal. 0: Illegal memory address not detected (normal operation) 1: Illegal memory address detected Note: When an address error is detected, the E-DMAC halts transmitting/receiving. To resume the operation, set the E-DMAC again after software reset by means of the SWR bit in EDMR. 22 ECI 0 R EtherC Status Register Interrupt Source This bit is a read-only bit. When the source of an ECSR interrupt in the EtherC is cleared, this bit is also cleared. 0: EtherC status interrupt source has not been detected 1: EtherC status interrupt source has been detected Rev. 1.00 Nov. 14, 2007 Page 446 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 21 Bit Name TC Initial value 0 R/W R/W Description Frame Transmit Complete Indicates that all the data specified by the transmit descriptor has been transmitted to the EtherC. The transfer status is written back to the relevant descriptor. When 1-frame transmission is completed for 1-frame/1-buffer processing, or when the last data in the frame is transmitted and the transmission descriptor valid bit (TACT) in the next descriptor is not set for multiple-frame buffer processing, transmission is completed and this bit is set to 1. After frame transmission, the E-DMAC writes the transmission status back to the descriptor. 0: Transfer not complete, or no transfer directive 1: Transfer complete 20 TDE 0 R/W Transmit Descriptor Empty Indicates that the transmission descriptor valid bit (TACT) in the descriptor is not set when the E-DMAC reads the transmission descriptor when the previous descriptor is not the last one of the frame for multiplebuffer frame processing. As a result, an incomplete frame may be transmitted. 0: Transmit descriptor active bit TACT = 1 detected 1: Transmit descriptor active bit TACT = 0 detected When transmission descriptor empty (TDE = 1) occurs, execute a software reset and initiate transmission. In this case, the address that is stored in the transmit descriptor list address register (TDLAR) is transmitted first. 19 TFUF 0 R/W Transmit FIFO Underflow Indicates that underflow has occurred in the transmit FIFO during frame transmission. Incomplete data is sent onto the line. 0: Underflow has not occurred 1: Underflow has occurred Rev. 1.00 Nov. 14, 2007 Page 447 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 18 Bit Name FR Initial value 0 R/W R/W Description Frame Reception Indicates that a frame has been received and the receive descriptor has been updated. This bit is set to 1 each time a frame is received. 0: Frame not received 1: Frame received 17 RDE 0 R/W Receive Descriptor Empty When receive descriptor empty (RDE = 1) occurs, receiving can be restarted by setting RACT = 1 in the receive descriptor and initiating receiving. 0: Receive descriptor active bit RACT = 1 not detected 1: Receive descriptor active bit RACT = 0 detected 16 RFOF 0 R/W Receive FIFO Overflow Indicates that the receive FIFO has overflowed during frame reception. 0: Overflow has not occurred 1: Overflow has occurred 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 CND 0 R/W Carrier Not Detect Indicates the carrier detection status. 0: A carrier is detected when transmission starts 1: A carrier is not detected when transmission starts 10 DLC 0 R/W Detect Loss of Carrier Indicates that loss of the carrier has been detected during frame transmission. 0: Loss of carrier not detected 1: Loss of carrier detected 9 CD 0 R/W Delayed Collision Detect Indicates that a delayed collision has been detected during frame transmission. 0: Delayed collision not detected 1: Delayed collision detected Rev. 1.00 Nov. 14, 2007 Page 448 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 8 Bit Name TRO Initial value 0 R/W R/W Description Transmit Retry Over Indicates that a retry-over condition has occurred during frame transmission. Total 16 transmission retries including 15 retries based on the back-off algorithm are failed after the EtherC transmission starts. 0: Transmit retry-over condition not detected 1: Transmit retry-over condition detected 7 RMAF 0 R/W Receive Multicast Address Frame 0: Multicast address frame has not been received 1: Multicast address frame has been received 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RRF 0 R/W Receive Residual-Bit Frame 0: Residual-bit frame has not been received 1: Residual-bit frame has been received 3 RTLF 0 R/W Receive Too-Long Frame Indicates that the frame more than the number of receive frame length upper limit set by RFLR of the EtherC has been received. 0: Too-long frame has not been received 1: Too-long frame has been received 2 RTSF 0 R/W Receive Too-Short Frame Indicates that a frame of fewer than 64 bytes has been received. 0: Too-short frame has not been received 1: Too-short frame has been received 1 PRE 0 R/W PHY Receive Error 0: PHY receive error not detected 1: PHY receive error detected 0 CERF 0 R/W CRC Error on Received Frame 0: CRC error not detected 1: CRC error detected Rev. 1.00 Nov. 14, 2007 Page 449 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR) EESIPR is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register (EESR). An interrupt is enabled by writing 1 to the corresponding bit. In the initial state, interrupts are not enabled. Bit: 31  30 TWBIP 29  28  27  26 25 24 23 22 ECIIP 21 TCIP 20 19 18 17 16 TABTIP RABTIP RFCOF ADEIP IP TDEIP TFUFIP FRIP RDEIP RFOFIP Initial Value: R/W: 0 R 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit: 15  14  13  12  11 10 9 CDIP 8 7 6  5  4 3 2 1 0 CNDIP DLCIP TROIP RMAFIP RRFIP RTLFIP RTSFIP PREIP CERFIP Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 Bit Name  Initial value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 30 TWBIP 0 R/W Write-Back Complete Interrupt Permission 0: Write-back complete interrupt is disabled 1: Write-back complete interrupt is enabled 29 to 27  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 26 TABTIP 0 R/W Transmit Abort Detection Interrupt Permission 0: Transmit abort detection interrupt is disabled 1: Transmit abort detection interrupt is enabled 25 RABTIP 0 R/W Receive Abort Detection Interrupt Permission 0: Receive abort detection interrupt is disabled 1: Receive abort detection interrupt is enabled 24 RFCOFIP 0 R/W Receive Frame Counter Overflow Interrupt Permission 0: Receive frame counter overflow interrupt is disabled 1: Receive frame counter overflow interrupt is enabled Rev. 1.00 Nov. 14, 2007 Page 450 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 23 Bit Name ADEIP Initial value 0 R/W R/W Description Address Error Interrupt Permission 0: Address error interrupt is disabled 1: Address error interrupt is enabled 22 ECIIP 0 R/W EtherC Status Register Interrupt Permission 0: EtherC status interrupt is disabled 1: EtherC status interrupt is enabled 21 TCIP 0 R/W Frame Transmit Complete Interrupt Permission 0: Frame transmit complete interrupt is disabled 1: Frame transmit complete interrupt is enabled 20 TDEIP 0 R/W Transmit Descriptor Empty Interrupt Permission 0: Transmit descriptor empty interrupt is disabled 1: Transmit descriptor empty interrupt is enabled 19 TFUFIP 0 R/W Transmit FIFO Underflow Interrupt Permission 0: Underflow interrupt is disabled 1: Underflow interrupt is enabled 18 FRIP 0 R/W Frame Received Interrupt Permission 0: Frame received interrupt is disabled 1: Frame received interrupt is enabled 17 RDEIP 0 R/W Receive Descriptor Empty Interrupt Permission 0: Receive descriptor empty interrupt is disabled 1: Receive descriptor empty interrupt is enabled 16 RFOFIP 0 R/W Receive FIFO Overflow Interrupt Permission 0: Receive FIFO overflow interrupt is disabled 1: Receive FIFO overflow interrupt is enabled 15 to 12  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 CNDIP 0 R/W Carrier Not Detect Interrupt Permission 0: Carrier not detect interrupt is disabled 1: Carrier not detect interrupt is enabled Rev. 1.00 Nov. 14, 2007 Page 451 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 10 Bit Name DLCIP Initial value 0 R/W R/W Description Detect Loss of Carrier Interrupt Permission 0: Detect loss of carrier interrupt is disabled 1: Detect loss of carrier interrupt is enabled 9 CDIP 0 R/W Delayed Collision Detect Interrupt Permission 0: Delayed collision detect interrupt is disabled 1: Delayed collision detect interrupt is enabled 8 TROIP 0 R/W Transmit Retry Over Interrupt Permission 0: Transmit retry over interrupt is disabled 1: Transmit retry over interrupt is enabled 7 RMAFIP 0 R/W Receive Multicast Address Frame Interrupt Permission 0: Receive multicast address frame interrupt is disabled 1: Receive multicast address frame interrupt is enabled 6, 5  All 0 R Reserved This bit is always read as 0. The write value should always be 0. 4 RRFIP 0 R/W Receive Residual-Bit Frame Interrupt Permission 0: Receive residual-bit frame interrupt is disabled 1: Receive residual-bit frame interrupt is enabled 3 RTLFIP 0 R/W Receive Too-Long Frame Interrupt Permission 0: Receive too-long frame interrupt is disabled 1: Receive too-long frame interrupt is enabled 2 RTSFIP 0 R/W Receive Too-Short Frame Interrupt Permission 0: Receive too-short frame interrupt is disabled 1: Receive too-short frame interrupt is enabled 1 PREIP 0 R/W PHY-LSI Receive Error Interrupt Permission 0: PHY-LSI receive error interrupt is disabled 1: PHY-LSI receive error interrupt is enabled 0 CERFIP 0 R/W CRC Error on Received Frame 0: CRC error on received frame interrupt is disabled 1: CRC error on received frame interrupt is enabled Rev. 1.00 Nov. 14, 2007 Page 452 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.8 Transmit/Receive Status Copy Enable Register (TRSCER) TRSCER specifies whether or not transmit and receive status information reported by bits in the EtherC/E-DMAC status register is to be indicated in bits TFS26 to TFS0 and RFS26 to RFS0 in the corresponding descriptor. Bits in this register correspond to bits 11 to 0 in the EtherC/EDMAC status register (EESR). When a bit is cleared to 0, the transmit status (bits 11 to 8 in EESR) is indicated in bits TFS3 to TFS0 in the transmit descriptor, and the receive status (bits 7 to 0 in EESR) is indicated in bits RFS7 to RFS0 of the receive descriptor. When a bit is set to 1, the occurrence of the corresponding interrupt is not indicated in the descriptor. After this LSI is reset, all bits are cleared to 0. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11 10 9 8 7 6  5  4 3 2 1 0 CNDCE DLCCE CDCE TROCE RMAF CE RRFCE RTLF CE RTSF PRECE CERF CE CE Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 12 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 CNDCE 0 R/W CND Bit Copy Directive 0: Indicates the CND bit state in bit TFS3 in the transmit descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS3 of the transmit descriptor 10 DLCCE 0 R/W DLC Bit Copy Directive 0: Indicates the DLC bit state in bit TFS2 of the transmit descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS2 of the transmit descriptor Rev. 1.00 Nov. 14, 2007 Page 453 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 9 Bit Name CDCE Initial value 0 R/W R/W Description CD Bit Copy Directive 0: Indicates the CD bit state in bit TFS1 of the transmit descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS1 of the transmit descriptor 8 TROCE 0 R/W TRO Bit Copy Directive 0: Indicates the TRO bit state in bit TFS0 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit TFS0 of the receive descriptor 7 RMAFCE 0 R/W RMAF Bit Copy Directive 0: Indicates the RMAF bit state in bit RFS7 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS7 of the receive descriptor 6, 5  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 RRFCE 0 R/W RRF Bit Copy Directive 0: Indicates the RRF bit state in bit RFS4 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS4 of the receive descriptor 3 RTLFCE 0 R/W RTLF Bit Copy Directive 0: Indicates the RTLF bit state in bit RFS3 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS3 of the receive descriptor 2 RTSFCE 0 R/W RTSF Bit Copy Directive 0: Indicates the RTSF bit state in bit RFS2 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS2 of the receive descriptor Rev. 1.00 Nov. 14, 2007 Page 454 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 1 Bit Name PRECE Initial value 0 R/W R/W Description PRE Bit Copy Directive 0: Indicates the PRF bit state in bit RFS1 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS1 of the receive descriptor 0 CERFCE 0 R/W CERF Bit Copy Directive 0: Indicates the CERF bit state in bit RFS0 of the receive descriptor 1: Occurrence of the corresponding interrupt is not indicated in bit RFS0 of the receive descriptor 13.2.9 Receive Missed-Frame Counter Register (RMFCR) RMFCR is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. When the receive FIFO overflows, the receive frames in the FIFO are discarded. The number of frames discarded at this time is counted. When the value in this register reaches H'FFFF, counting-up is halted. When this register is read, the counter value is cleared to 0. Write operations to this register have no effect. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 MFC[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 16 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 MFC[15:0] All 0 R Missed-Frame Counter Indicate the number of frames that are discarded and not transferred to the receive buffer during reception. Rev. 1.00 Nov. 14, 2007 Page 455 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.10 Transmit FIFO Threshold Register (TFTR) TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the first transmission is started. The actual threshold is 4 times the set value. The EtherC starts transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified by this register, when the transmit FIFO is full, or when 1-frame write is executed. When setting this register, do so in the transmission-halt state. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 TFT[10:0] 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 11  10 to 0 TFT[10:0] All 0 R/W Transmit FIFO threshold When setting a transmit FIFO, the FIFO must be set to a smaller value than the specified value of the FIFO capacity by FDR. H'00: Store and forward modes H'01 to H'0C: Setting prohibited H'0D: 52 bytes H'0E: 56 bytes : : H'1F: 124 bytes H'20: 128 bytes : : H'3F: 252 bytes H'40: 256 bytes : : H'7F: 508 bytes H'80: 512 bytes H'81 to H'200: Setting prohibited Note: When starting transmission before one frame of data write has completed, take care the generation of the underflow. Rev. 1.00 Nov. 14, 2007 Page 456 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.11 FIFO Depth Register (FDR) FDR is a 32-bit readable/writable register that specifies the depth of the transmit and receive FIFOs. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10 TFD2 0 R 9 TFD1 0 R 8 TFD0 0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2 RFD2 0 R 1 RFD1 0 R 0 RFD0 Bit: 15  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 1 R/W Bit 31 to 11 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 10 9 8 TFD2 TFD1 TFD0 0 0 1 R/W R/W R/W Transmit FIFO Depth These bits specify the depth of the transmit FIFO. After the start of the transmission and reception, the setting cannot be changed. 000: 256 bytes 001: 512 bytes Other than above: Setting prohibited 7 to 3  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 1 0 RFD2 RFD1 RFD0 0 0 1 R/W R/W R/W Receive FIFO Depth These bits specify the depth of the receive FIFO. After the start of the transmission and reception, the setting cannot be changed. 000: 256 bytes 001: 512 bytes Other than above: Setting prohibited Rev. 1.00 Nov. 14, 2007 Page 457 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.12 Receiving Method Control Register (RMCR) RMCR is a 32-bit readable/writable register that specifies the control method for the RR bit in EDRRR when a frame is received. This register must be set during the receiving-halt state. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1  0 R 0 RNC Bit: 15  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 RNC 0 R/W Receive Enable Control 0: When reception of one frame is completed, the EDMAC writes the receive status into the descriptor and clears the RR bit in EDRRR 1: When reception of one frame is completed, the EDMAC writes the receive status into the descriptor, reads the next descriptor, and prepares to receive the next frame Rev. 1.00 Nov. 14, 2007 Page 458 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.13 E-DMAC Operation Control Register (EDOCR) EDOCR is a 32-bit readable/writable register that specifies the control methods used in E-DMAC operation. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3 FEC 0 R 2 AEC 0 R 1 EDH 0 R 0  Bit: 15  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R Bit 31 to 4 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 FEC 0 R/W FIFO Error Control Specifies E-DMAC operation when transmit FIFO underflow or receive FIFO overflow occurs. 0: E-DMAC operation continues when underflow or overflow occurs 1: E-DMAC operation halts when underflow or overflow occurs 2 AEC 0 R/W Address Error Control Indicates detection of an illegal memory address in an attempted E-DMAC transfer. 0: Illegal memory address not detected (normal operation) 1: E-DMAC stops its operation due to illegal memory address detection Note: To resume the operation, set the E-DMAC again after software reset by means of the SWR bit in EDMR. Rev. 1.00 Nov. 14, 2007 Page 459 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 1 Bit Name EDH Initial value 0 R/W R/W Description E-DMAC Halted 0: The E-DMAC is operating normally 1: The E-DMAC has been halted by NMI pin assertion. E-DMAC operation is restarted by writing 0 0  0 R Reserved This bit is always read as 0. The write value should always be 0. 13.2.14 Receiving-Buffer Write Address Register (RBWAR) RBWAR stores the address of data to be written in the receiving buffer when the E-DMAC writes data to the receiving buffer. Which addresses in the receiving buffer are processed by the EDMAC can be recognized by monitoring addresses displayed in this register. The address that the E-DMAC is actually processing may be different from the value read from this register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RBWA[31:16] Initial Value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 RBWA[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 0 Bit Name Initial value R/W R Description Receiving-Buffer Write Address These bits can only be read. Writing is prohibited. RBWA[31:0] All 0 Rev. 1.00 Nov. 14, 2007 Page 460 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) RDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the receiving descriptor. Which receiving descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDFA[31:16] Initial Value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 RDFA[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial value R/W R Description Receiving-Descriptor Fetch Address These bits can only be read. Writing is prohibited. 31 to 0 RDFA[31:0] All 0 13.2.16 Transmission-Buffer Read Address Register (TBRAR) TBRAR stores the address of the transmission buffer when the E-DMAC reads data from the transmission buffer. Which addresses in the transmission buffer are processed by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually reading in the buffer may be different from the value read from this register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TBRA[31:16] Initial Value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 TBRA[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit Bit Name Initial value R/W R Description Transmission-Buffer Read Address These bits can only be read. Writing is prohibited. 31 to 0 TBRA[31:0] All 0 Rev. 1.00 Nov. 14, 2007 Page 461 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) TDFAR stores the descriptor start address that is required when the E-DMAC fetches descriptor information from the transmission descriptor. Which transmission descriptor information is used for processing by the E-DMAC can be recognized by monitoring addresses displayed in this register. The address from which the E-DMAC is actually fetching a descriptor may be different from the value read from this register. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDFA[31:16] Initial Value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 TDFA[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 0 Bit Name TDFA[31:0] Initial value All 0 R/W R Description Transmission-Descriptor Fetch Address These bits can only be read. Writing is prohibited. 13.2.18 Flow Control FIFO Threshold Register (FCFTR) FCFTR is a 32-bit readable/writable register that sets the flow control of the EtherC (setting the threshold on automatic PAUSE transmission). The threshold can be specified by the depth of the receive FIFO data (RFD2 to RFD0) and the number of receive frames (RFF2 to RFF0). The condition to start the flow control is decided by taking OR operation on the two thresholds. Therefore, the flow control by the two thresholds is independently started. When flow control is performed according to the RFD bits setting, if the setting is the same as the depth of the receive FIFO specified by the FIFO depth register (FDR), flow control is started when the remaining FIFO is (FIFO data − 64) bytes. For instance, when RFD in FDR = 1 and RFD in FCFTR = 1, flow control is started when (512 − 64) bytes of data is stored in the receive FIFO. The value set in the RFD bits in this register should be equal to or less than those in FDR. Rev. 1.00 Nov. 14, 2007 Page 462 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18 17 RFF[2:0] 16 Initial Value: R/W: Bit: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 1 R/W 1 R/W 15  14  13  12  11  10  9  8  7  6  5  4  3  2 1 RFD[2:0] 0 Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 31 to 19 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 18 to 16 RFF[2:0] 111 R/W Receive Frame Number Flow Control Threshold 000: When one receive frame has been stored in the receive FIFO 001: When two receive frames have been stored in the receive FIFO : : 110: When seven receive frames have been stored in the receive FIFO 111: When eight receive frames have been stored in the receive FIFO 15 to 3  All 0  Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 RFD[2:0] 000 R/W Receive Byte Flow Control Threshold 000: When (256 − 64) bytes of data is stored in the receive FIFO 001: When (512 − 64) bytes of data is stored in the receive FIFO Other than above: Setting prohibited Rev. 1.00 Nov. 14, 2007 Page 463 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.19 Receive Data Padding Setting Register (RPADIR) RPADIR is a 32-bit readable/writable register that performs the padding of receive data. Before setting this register again, reset the software with the SWR bit in the E-DMAC mode register (EDMR). Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17 16 PADS1 PADS0 Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W Bit: 15  14  13  12  11  10  9  8  7  6  5 4 3 2 1 0 PADR[5:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 18 Bit Name  Initial value All 0 R/W  Description Reserved These bits are always read as 0. The write value should always be 0. 17 16 PADS1 PADS0 0 0 R/W R/W Padding size 00: No padding 01: Padding of one byte 10: Padding of two bytes 11: Padding of three bytes 15 to 6  All 0  Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 PADR[5:0] 000000 R/W Padding Range H'00: Data equivalent to the padding size is inserted in the first byte. H'01: Data equivalent to the padding size is inserted in the second byte. : : H'3E: Data equivalent to the padding size is inserted in the 63rd byte. H'3F: Data equivalent to the padding size is inserted in the 64th byte. Rev. 1.00 Nov. 14, 2007 Page 464 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.20 Transmit Interrupt Register (TRIMD) TRIMD is a 32-bit readable/writable register that specifies whether or not to notify write-back completion for each frame using the TWB bit in EESR and an interrupt on transmit operations. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: Bit: 0 R 15  0 R 14  0 R 13  0 R 12  0 R 11  0 R 10  0 R 9  0 R 8  0 R 7  0 R 6  0 R 5  0 R 4  0 R 3  0 R 2  0 R 1  0 R 0 TIS Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/ 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 31 to 1 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TIS 0 R/W Transmit Interrupt Setting 0: Write-back completion for each frame is not notified 1: Write-backed completion for each frame using the TWB bit in EESR is notified 13.2.21 Checksum Mode Register (CSMR) CSMR is a 32-bit readable/writable register that specifies the checksum operating mode. Set this register when reception is stopped. Bit: 31 30 29  28  27  26  25  24  23  22  21  20  19  18  17  16  CSEBL CSMD Initial Value: 1 R/W: R/W 15  1 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 14  13  12  11  10  9  8  7  6  5 4 3 2 1 0 SB[5:0] 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 465 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 31 Bit Name CSEBL Initial value 1 R/W R/W Description Operation Setting for Checksum Calculation Function 0: The result of checksum calculation is not written back to the receive descriptor. 1: The result of checksum calculation is written back to the receive descriptor. 30 CSMD 1 R/W Setting for Checksum Calculation Mode 0: For all the data skipped from the beginning of packet, checksums are calculated on the bytes equivalent to the number of bytes specified in SB5 to SB0. 1: Packet checksums are calculated along with the analysis of the TCP header. 29 to 6  All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 SB[5:0]* 011010 R/W Bytes Skipped in Checksum Calculation These bits specify the position for starting checksum calculation from the beginning of a receive packet. If padding is used, include the padding size and the padding range when setting the position for starting checksum calculation. H'00: Byte 0 (starting data) H'02: Byte 2 : : : : H'1A: Byte 26 H'3E: Byte 62 Note * Setting is possible only when CSEBL = 1 and CSMD = 0. Otherwise, 6'h00 should be set. Rev. 1.00 Nov. 14, 2007 Page 466 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.22 Checksum Skipped Bytes Monitor Register (CSSBM ) CSSBM is a 32-bit read-only register that stores the number of skipped bytes during the processing of received packets in the E-DMAC. The number of skipped bytes can be recognized by monitoring the value displayed by this register. Note that the number of items of data received by the E-DMAC may be different from the number of skipped bytes. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11  10  9  8  7  6  5 4 3 2 1 0 SBM[5:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 6 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 5 to 0 SBM[5:0] 000000 R/W Number of Skipped Bytes These bits can only be read. Writing is prohibited. These bits are initialized to 0 at the beginning of a receive packet. Note * The value is valid only when CSEBL = 1 and CSMD = 0. Rev. 1.00 Nov. 14, 2007 Page 467 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.2.23 Checksum Monitor Register (CSSMR) CSSMR is a 32-bit read-only register that stores the value of a checksum during the processing of received packets in E-DMAC. The checksum value can be recognized by monitoring the value displayed by this register. Note that the value of the data received by E-DMAC may be different from the checksum value. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit: 15 CS[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 16 Bit Name  Initial value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 15 to 0 CS[15:0] 0 R Checksum Value These bits can only be read. Writing is prohibited. These bits are initialized to 0 at the beginning of a receive packet. Note * The value is valid only when CSEBL = 1 and CSMD = 0. Rev. 1.00 Nov. 14, 2007 Page 468 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3 Operation The E-DMAC is connected to the EtherC, and performs efficient transfer of transmit/receive data between the EtherC and memory (buffers) without the intervention of the CPU. The E-DMAC itself reads control information, including buffer pointers called descriptors, relating to the buffers. The E-DMAC reads transmit data from the transmit buffer and writes receive data to the receive buffer in accordance with this control information. By setting up a number of consecutive descriptors (a descriptor list), it is possible to execute transmission and reception continuously. 13.3.1 Descriptor List and Data Buffers Before starting transmission/reception, the communication program creates transmit and receive descriptor lists in memory. The start addresses of these lists are then set in the transmit and receive descriptor list start address registers. The descriptor start address must be aligned so that it matches the address boundary according to the descriptor length set by the E-DMAC mode register (EDMR). The transmit buffer start address can be aligned with a byte, a word, and a longword boundary. (1) Transmit Descriptor Figure 13.2 shows the relationship between a transmit descriptor and the transmit buffer. According to the specification in this descriptor, the relationship between the transmit frame and transmit buffer can be defined as one frame/one buffer or one frame/multi-buffer. Rev. 1.00 Nov. 14, 2007 Page 469 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmit descriptor 31 30 29 28 27 26 TTTTT ADFFF CLPPE TE10 31 TD1 31 TD2 TBA Padding (4 bytes) TDL 0 0 TFS26 to TFS0 Transmit buffer TD0 16 Valid transmit data Figure 13.2 Relationship between Transmit Descriptor and Transmit Buffer Rev. 1.00 Nov. 14, 2007 Page 470 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Transmit Descriptor 0 (TD0) TD0 indicates the transmit frame status. The CPU and E-DMAC use TD0 to report the frame transmission status. Bit: 31 TACT 30 TDLE 29 TFP1 28 TFP0 27 TFE 26 25 24 23 22 21 TFS[26:16] 20 19 18 17 16 Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 TFS[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 Bit Name TACT Initial value 0 R/W R/W Description Transmit Descriptor Active Indicates that this descriptor is active. The CPU sets this bit after transmit data has been transferred to the transmit buffer. The E-DMAC resets this bit on completion of a frame transfer or when transmission is suspended. 0: The transmit descriptor is invalid. Indicates that valid data has not been written to this bit by the CPU, or this bit has been reset by a writeback operation on termination of E-DMAC frame transfer processing (completion or suspension of transmission) If this state is recognized in an E-DMAC descriptor read, the E-DMAC terminates transmit processing and transmit operations cannot be continued (a restart is necessary) 1: The transmit descriptor is valid. Indicates that valid data has been written to the transmit buffer by the CPU and frame transfer processing has not yet been executed, or that frame transfer is in progress When this state is recognized in an E-DMAC descriptor read, the E-DMAC continues with the transmit operation Rev. 1.00 Nov. 14, 2007 Page 471 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 30 Bit Name TDLE Initial value 0 R/W R/W Description Transmit Descriptor List End After completion of the corresponding buffer transfer, the E-DMAC references the first descriptor. This specification is used to set a ring configuration for the transmit descriptors. 0: This is not the last transmit descriptor list 1: This is the last transmit descriptor list 29 28 TFP1 TFP0 0 0 R/W R/W Transmit Frame Position 1, 0 These two bits specify the relationship between the transmit buffer and transmit frame. In the preceding and following descriptors, a logically positive relationship must be maintained between the settings of this bit and the TDLE bit. 00: Frame transmission for transmit buffer indicated by this descriptor continues (frame is not concluded) 01: Transmit buffer indicated by this descriptor contains end of frame (frame is concluded) 10: Transmit buffer indicated by this descriptor is start of frame (frame is not concluded) 11: Contents of transmit buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer) 27 TFE 0 R/W Transmit Frame Error Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. Whether or not the transmit frame status information is copied into this bit is specified by the transmit/receive status copy enable register. 0: No error during transmission 1: An error occurred during transmission Rev. 1.00 Nov. 14, 2007 Page 472 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 26 to 0 Bit Name TFS26 to TFS0 Initial value All 0 R/W R/W Description Transmit Frame Status TFS26 to TFS4: Reserved (The write value should always be 0.) TFS8: Detect Transmit Buffer Underflow (corresponds to TDE bit in EESR) TFS3: Carrier Not Detect (corresponds to CND bit in EESR) TFS2: Detect Loss of Carrier (corresponds to DLC bit in EESR) TFS1: Delayed Collision Detect (corresponds to CD bit in EESR) TFS0: Transmit Retry Over (corresponds to TRO bit in EESR) Rev. 1.00 Nov. 14, 2007 Page 473 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Transmit Descriptor 1 (TD1) TD1 specifies the transmit buffer length (maximum 64 Kbytes). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TDL[15:0] Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11  10  9  8  7  6  5  4  3  2  1  0  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 31 to 16 Bit Name TDL[15:0] Initial value All 0 R/W R/W Description Transmit Buffer Data Length These bits specify the valid transfer byte length in the corresponding transmit buffer. When the one frame/multi-buffer system is specified (TD0 and TFP = 10 or 00), the transfer byte length specified in the descriptors at the start and midway can be set in byte units. 15 to 0  All 0 R Reserved These bits are always read as 0. The write value should always be 0. (c) Transmit Descriptor 2 (TD2) TD2 specifies the 32-bit transmit buffer start address. The transmit buffer start address setting can be aligned with a byte, a word, or a longword boundary. Rev. 1.00 Nov. 14, 2007 Page 474 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) (2) Receive Descriptor Figure 13.3 shows the relationship between a receive descriptor and the receive buffer. In frame reception, the E-DMAC performs data rewriting up to a receive buffer 16-byte boundary, regardless of the receive frame length. Finally, the actual receive frame length is reported in the lower 16 bits of RD1 in the descriptor. Data transfer to the receive buffer is performed automatically by the E-DMAC to give a one frame/one buffer or one frame/multi-buffer configuration according to the size of one received frame. Receive descriptor 31 30 29 28 27 26 25 1615 RCS15 to RCS0 Valid receive data 0 Receive buffer RACT RDLE RFP1 RFP0 RFE RCSE RD0 RFS9 to RFS0 15 16 RBA RD1 RD2 RBL 31 31 0 RDL 0 Padding (4 bytes) Figure 13.3 Relationship between Receive Descriptor and Receive Buffer Rev. 1.00 Nov. 14, 2007 Page 475 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) (a) Receive Descriptor 0 (RD0) RD0 indicates the receive frame status. The CPU and E-DMAC use RD0 to report the frame receive status. Bit: 31 RACT 30 RDLE 29 28 27 RFE 26 RCSE 25 24 23 22 21 RFS[9:0] 20 19 18 17 16 RFP[1:0] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCS[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 Bit Name RACT Initial value 0 R/W R/W Description Receive Descriptor Active Indicates that this descriptor is active. The E-DMAC resets this bit after receive data has been transferred to the receive buffer. On completion of receive frame processing, the CPU sets this bit to prepare for reception. 0: The receive descriptor is invalid. Indicates that the receive buffer is not ready (access disabled by E-DMAC), or this bit has been reset by a write-back operation on termination of EDMAC frame transfer processing (completion or suspension of reception). If this state is recognized in an E-DMAC descriptor read, the E-DMAC terminates receive processing and receive operations cannot be continued. Reception can be restarted by setting RACT to 1 and executing receive initiation. 1: The receive descriptor is valid Indicates that the receive buffer is ready (access enabled) and processing for frame transfer from the FIFO has not been executed, or that frame transfer is in progress. When this state is recognized in an E-DMAC descriptor read, the E-DMAC continues with the receive operation. Rev. 1.00 Nov. 14, 2007 Page 476 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 30 Bit Name RDLE Initial value 0 R/W R/W Description Receive Descriptor List Last After completion of the corresponding buffer transfer, the E-DMAC references the first receive descriptor. This specification is used to set a ring configuration for the receive descriptors. 0: This is not the last receive descriptor list 1: This is the last receive descriptor list 29, 28 RFP[1:0] 00 R/W Receive Frame Position These two bits specify the relationship between the receive buffer and receive frame. 00: Frame reception for receive buffer indicated by this descriptor continues (frame is not concluded) 01: Receive buffer indicated by this descriptor contains end of frame (frame is concluded) 10: Receive buffer indicated by this descriptor is start of frame (frame is not concluded) 11: Contents of receive buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer) 27 RFE 0 R/W Receive Frame Error Indicates that one or other bit of the receive frame status indicated by bits 25 to 16 is set. Whether or not the receive frame status information is copied into this bit is specified by the transmit/receive status copy enable register. 0: No error during reception 1: A certain kind of error occurred during reception 26 RCSE 0 R/W Determination of Receive Packet Checksum Value When CSEBL = 1 and CSMD = 1, the setting shown in table 13.1 occurs depending on the received packet and data. The information in this bit will be invalid if operation is based on any setting other than the above. Rev. 1.00 Nov. 14, 2007 Page 477 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Bit 25 to 16 Bit Name RFS[9:0] Initial value All 0 R/W R/W Description Receive Frame Status These bits indicate the error status during frame reception. RFS9: Receive FIFO overflow (corresponds to RFOF bit in EESR) RFS8: Reserved (The write value should always be 0.) RFS7: Multicast address frame received (corresponds to RMAF bit in EESR) RFS6: CAM entry unregistered frame received (corresponds to the RUAF bit in EESR) RSF5: Reserved (The write value should always be 0.) RFS4: Receive residual-bit frame error (corresponds to RRF bit in EESR) RFS3: Receive too-long frame error (corresponds to RTLF bit in EESR) RFS2: Receive too-short frame error (corresponds to RTSF bit in EESR) RFS1: PHY-LSI receive error (corresponds to PRE bit in EESR) RFS0: CRC error on received frame (corresponds to CERF bit in EESR) 15 to 0 RCS[15:0] All 0 R/W Receive Packet Checksum Value Rev. 1.00 Nov. 14, 2007 Page 478 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Table 13.1 Types of Receive Packets and the RCSE State of Receive Data Frame Type IP version IPv4 Option and extension header None Fragment Option IPv6 None Hop-by-hop Routing End-point option AH Fragment ESP MobileIPv6 Others Other than IPv4 and IPv6 When Data Is Normal RCS[15:0] 16'hFFFF 16'h0000 Undefined 16'hFFFF 16'h0000 16'hFFFF 16'h0000 16'hFFFF 16'h0000 16'hFFFF 16'h0000 16'hFFFF 16'h0000 16'hFFFF 16'h0000 Undefined 16'h0000 16'h0000 16'h0000 16'h0000 Undefined Undefined 1 1 1 0 16'h0000 16'h0000 16'h0000 16'h0000 Undefined 1 1 1 0 0 Undefined 1 0 Undefined 1 0 Undefined 1 0 Undefined 1 0 Undefined 1 Undefined Undefined 0 Undefined Undefined 1 RCSE 0 When Data Is Abnormal RCS[15:0] Undefined RCSE 1 Rev. 1.00 Nov. 14, 2007 Page 479 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) (b) Receive Descriptor 1 (RD1) RD1 specifies the receive buffer length (maximum 64 Kbytes). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RBL[15:0] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 RDL[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 16 Bit Name RBL[15:0] Initial value All 0 R/W R/W Description Receive Buffer Length These bits specify the maximum reception byte length in the corresponding receive buffer. The transfer byte length must align with a 16-byte boundary (bits 19 to 16 cleared to 0). The maximum receive frame length with one frame per buffer is 1,514 bytes, excluding the CRC data. Therefore, for the receive buffer length specification, a value of 1,520 bytes (H'05F0) that takes account of a 16-byte boundary is set as the maximum receive frame length. 15 to 0 RDL[15:0] All 0 R/W Receive Data Length These bits specify the data length of a receive frame stored in the receive buffer. The receive data transferred to the receive buffer does not include the 4-byte CRC data at the end of the frame. The receive frame length is reported as the number of words (valid data bytes) not including this CRC data. (c) Receive Descriptor 2 (RD2) RD2 specifies the 32-bit receive buffer start address. The receive buffer start address must be aligned with a longword boundary. However, when SDRAM is connected, it must be aligned with a 16-byte boundary. Rev. 1.00 Nov. 14, 2007 Page 480 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3.2 Transmission When the transmit function is enabled and the transmit request bit (TR) is set in the E-DMAC transmit request register (EDTRR), the E-DMAC reads the descriptor used last time from the transmit descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (TDLAR)). If the setting of the TACT bit in the read descriptor is active, the E-DMAC reads transmit frame data sequentially from the transmit buffer start address specified by TD2, and transfers it to the EtherC. The EtherC creates a transmit frame and starts transmission to the MII. After DMA transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the TFP value. 1. TFP = 00 or 01 (frame continuation): Descriptor write-back is performed after DMA transfer. 2. TFP = 01 or 11 (frame end): Descriptor write-back is performed after completion of frame transmission. The E-DMAC continues reading descriptors and transmitting frames as long as the setting of the TACT bit in the read descriptors is "active." When a descriptor with an "inactive" TACT bit is read, the E-DMAC resets the transmit request bit (TR) in the transmit register and ends transmit processing (EDTRR). Rev. 1.00 Nov. 14, 2007 Page 481 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Transmission flowchart This LSI + memory E-DMAC Transmit FIFO EtherC Ethernet EtherC/E-DMAC initialization Descriptor and transmit buffer setting Transmit directive Descriptor read Transmit data transfer Descriptor write-back Descriptor read Transmit data transfer Frame transmission Descriptor write-back Transmission completed Figure 13.4 Sample Transmission Flowchart Rev. 1.00 Nov. 14, 2007 Page 482 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3.3 Reception When the receive function is enabled and the CPU sets the receive request bit (RR) in the EDMAC receive request register (EDRRR), the E-DMAC reads the descriptor following the previously used one from the receive descriptor list (the descriptor indicated by the receive descriptor list's starting address register (RDLA) is used at the initial state), and then enters the receive-standby state. If the setting of the RACT bit is "active" and an own-address frame is received, the E-DMAC transfers the frame to the receive buffer specified by RD2. If the data length of the received frame is greater than the buffer length given by RD1, the E-DMAC performs write-back to the descriptor when the buffer is full (RFP = 10 or 00), then reads the next descriptor. The E-DMAC then continues to transfer data to the receive buffer specified by the new RD2. When frame reception is completed, or if frame reception is suspended because of a certain kind of error, the E-DMAC performs write-back to the relevant descriptor (RFP = 11 or 01), and then ends the receive processing. The E-DMAC then reads the next descriptor and enters the receive-standby state again. To receive frames continuously, the receive enable control bit (RNC) must be set to 1 in the receive control register (RCR). After initialization, this bit is cleared to 0. Rev. 1.00 Nov. 14, 2007 Page 483 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Reception flowchart This LSI + memory E-DMAC Receive FIFO EtherC Ethernet EtherC/E-DMAC initialization Descriptor and receive buffer setting Start of reception Descriptor read Frame reception Receive data transfer Descriptor write-back Descriptor read Receive data transfer Descriptor write-back Descriptor read (receive ready for the next frame) Reception completed Figure 13.5 Sample Reception Flowchart Rev. 1.00 Nov. 14, 2007 Page 484 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3.4 Multi-Buffer Frame Transmit/Receive Processing Multi-Buffer Frame Transmit Processing If an error occurs during multi-buffer frame transmission, the processing shown in figure 13.6 is carried out by the E-DMAC. Where the transmit descriptor is shown as inactive (TACT bit = 0) in the figure, buffer data has already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit = 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT bit cleared to 0, immediately. The next descriptor is then read, and the position within the transmit frame is determined on the basis of bits TFP1 and TFP0 (continuing [B'00] or end [B'01]). In the case of a continuing descriptor, the TACT bit is cleared to 0, only, and the next descriptor is read immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not transmitted between the occurrence of an error and write-back to the final descriptor. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the final descriptor write-back. Descriptors T A C T T D L E T F P 1 T F P 0 00 00 00 Inactivates TACT (change 1 to 0) E-DMAC Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT Descriptor read Inactivates TACT and writes TFE, TFS 10 10 10 10 10 11 10 00 00 00 00 00 00 01 10 Buffer Untransmitted data is not transmitted after error occurrence Descriptor is only processed. Transmit error occurrence One frame Transmitted data Untransmitted data Figure 13.6 E-DMAC Operation after Transmit Error Rev. 1.00 Nov. 14, 2007 Page 485 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Multi-Buffer Frame Receive Processing If an error occurs during multi-buffer frame reception, the processing shown in figure 13.7 is carried out by the E-DMAC. Where the receive descriptor is shown as inactive (RACT bit = 0) in the figure, buffer data has already been received normally, and where the receive descriptor is shown as active (RACT bit = 1), this indicates a buffer for which reception has not yet been performed. If a frame receive error occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted immediately and a status write-back to the descriptor is performed. If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame receive request, reception is continued from the buffer after that in which the error occurred. Descriptors R A C T 0 0 0 Inactivates RACT and writes RFE, RFS E-DMAC 1 Descriptor read Write-back 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Buffer New frame reception continues from buffer 0 0 1 R D L E 0 0 0 R F P 1 1 0 0 R F P 0 0 0 0 Receive error occurrence Start of frame Figure 13.7 E-DMAC Operation after Receive Error Rev. 1.00 Nov. 14, 2007 Page 486 of 1262 REJ09B0437-0100 ......... Received data Unreceived data Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3.5 Padding Receive Data The E-DMAC can pad one to three bytes anywhere in the receive data to increase the efficiency of processing of receive data. For example, by padding two bytes after the 14-byte MAC header of an Ethernet frame with this function, the subsequent data can be placed at the beginning of the four-byte boundary. [No padding] Receive buffer area 16-byte boundary MAC header (14 bytes) 16-byte boundary MAC header (14 bytes) Padding for separation in the 16-byte boundary 16-byte boundary MAC header (14 bytes) 4 bytes [Padding] Padding of two bytes after the 14th byte Receive buffer area 16-byte boundary MAC header (14 bytes) Padding two bytes after the MAC header 16-byte boundary MAC header (14 bytes) 16-byte boundary MAC header (14 bytes) Padding for separation in the 16-byte boundary 4 bytes Figure 13.8 Padding Receive Data Rev. 1.00 Nov. 14, 2007 Page 487 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3.6 Checksum Calculation Function The TCP checksum for receive packets is accelerated when the checksum calculation function is used in the following two modes: • Checksum calculation function of TCP header analysis type • All-data checksum calculation function of skipped bytes designation type (1) Checksum Calculation Function of TCP Header Analysis Type (CSEBL = 1 and CSMD = 1) Any receive packet included in the table below will be the target of calculation. IPver IPv4 Item No option Option provided Fragment*1 IPv6 No extension header Length of the extension header of a hop-by-hop option Length of the extension header of routing Length of the extension header of a fragment*1 Length of the extension header of an end-point option Length of the extension header of AH Length of the extension header of ESP*2 Length of the extension header of MobileIPv6*2 Notes: *1. This is the target of calculation, but both RCS15 to RCS0 and RCSE will be undefined even if the data is normal. *2. No calculation is performed on RCS15 to RCS0, and RCSE is set to 1. The following shows the areas as the target of calculation of an IPv4 packet. The shaded portions are the target of calculation. Rev. 1.00 Nov. 14, 2007 Page 488 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) No. 31 0 1 2 3 4 5 6 7 8 9 10 Data Transmit IP Receive IP An option, if any, is deleted from the target of calculation. Transmit IP Receive IP IPv4/IPv6/others (Decision) Packet length IHL* 16 15 11 8 7 0 Note: * This is changed to the octet basis and undergoes a subtraction during checksum calculation. During calculation, {8'h00, protocol No.[7:0]} is used. The following shows the areas as the target of calculation of an IPv6 packet. The shaded portions are the target of calculation. Rev. 1.00 Nov. 14, 2007 Page 489 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) No. 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Transmit IP Transmit IP Transmit IP Transmit IP Next header*1 Header length*2 Receive IP The content of an extension header is not the target of checksum calculation. Next header*1 Transmit IP Transmit IP Transmit IP Receive IP IPv4/IPv6/others (Decision) Payload length Transmit IP 16 15 0 Data Note: 1. Calculation applies only to TCP/UDP. Calculation requires an expansion to {8'h00, next header[7:0]}. 2. This is changed to the octet basis and undergoes a subtraction during checksum calculation. (2) All-Data Checksum Calculation Function of Skipped Bytes Designation Type The data equivalent to the number of bytes specified by SB5 to SB0 is skipped from the beginning of a packet, and checksums are calculated on all of the subsequent valid data. (Example: 14-byte skip) No. 31 0 1 2 3 4 5 6 7 8 9 10 11 Data to be calculated SB[5:0]OE 16 15 0 Rev. 1.00 Nov. 14, 2007 Page 490 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) 13.3.7 Usage Notes When the checksum calculation and padding functions are both enabled, checksums are calculated on the packet data available before padding. This should be remembered when, for example, setting the number of skipped bytes. Rev. 1.00 Nov. 14, 2007 Page 491 of 1262 REJ09B0437-0100 Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 1.00 Nov. 14, 2007 Page 492 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.1 Overview The A-DMAC is a high-level descriptor-mode DMAC having error correction function. This DMAC provides data transfer with memory via an internal shared bus (I-BUS) and data transfer with an external MPEG device via STIF. 14.1.1 Features The functions and features of this A-DMAC are as follows: (1) Channels for checksum processing • Number of channels: 2 • Transfer direction: Memory← →memory, memory← →STIF • Descriptor structure: Structure that enables checksum operation, etc., to be continuously performed • Error check: Checksum calculation function (2) FEC channels • Number of channels: 1 • Descriptor structure: Structure that enables processing of any number of data items with a small number of buffers • Error correction (FEC): XOR calculation function (3) Other features • Supported endian: Big endian/little endian • Number of STIFs connected: Two channels • Channel arbitration: Round robin scheduling that provides highly efficient use of encryption modules and buses • Channel operation: Parallel processing Rev. 1.00 Nov. 14, 2007 Page 493 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.1.2 Overall Configuration of the A-DMAC The A-DMAC is configured as shown in figure 14.1. Table 14.2 gives an overview of A-DMAC submodules. The A-DMAC is connected to the I-BUS via the I-BUS interface, to the STIF0 via the STIF0 interface, and to the STIF1 via the STIF1 interface. The I-BUS is a shared bus in this LSI operating on the B clock. The STIF is an I/O port for MPEG-2 TS/PS format data. The STIF0 is fixed at CH0 and the STIF1 fixed at CH1. The A-DMAC has two channels for checksum operation that operate on descriptors. Aside from these channels, the A-DMAC has an FEC channel dedicated for FEC operation. This FEC channel performs XOR operation of FEC operation. These modules operate in parallel. For example, when the bus for channel 0 for checksum processing is accessed, channel 1 for checksum processing can perform checksum operation. The arbiter is a module that arbitrates the requests sent from each checksum processing channel and each initiator of the FEC channel. The arbiter arbitrates requests from an initiator in round robin scheduling. If you want to execute CH0 and CH1 simultaneously and raise the priority of CH0 or CH1, the arbiter controls the priorities in descriptor ring units (example: When the descriptor of CH0 or CH1, whichever has a lower priority, runs dry, the arbiter piles up the next descriptor after a certain idling) or controls the priorities by suspending channel processing of lower priority. Rev. 1.00 Nov. 14, 2007 Page 494 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) A-DMAC CPU control CPU control data ADMA interrupt Channel 0 for checksum ad_irqc0_n Function · DMA automatic processing · Checksum operation · Processing data management, Data selector Channel 1 for checksum ad_irqc1_n Function · DMA automatic processing · Checksum operation · Processing data management, Data selector Channel1 control Channel1 data Channel0 control BUS I/F data Channel0 data BUS I/F control I-BUS interface Function · Bus protocol conversion I-BUS control I-BUS data I-BUS INTC Arbiter Function · Arbitration STIF0 I/F control STIF0 I/F data STIF0 interface Function · STIF0 protocol conversion STIF0control STIF0 data STIF0 STIF1 I/F control STIF1 I/F data STIF1 interface Function · STIF1 protocol conversion STIF1 control STIF1 data STIF1 ad_irqfec_n FEC channel Function · DMA autmatic processing · XOR operation FEC channel control FEC channel data x_rst x_bck x_bckstp_p x_modstp_p Figure 14.1 Block Diagram of A-DMAC Rev. 1.00 Nov. 14, 2007 Page 495 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Table 14.1 A-DMAC Submodules Submodule Name Channel for checksum processing Function • • • FEC channel Arbiter • • • • I-BUS interface • • STIF interface • • • DMA automatic processing based on descriptors Checksum operation Continuous execution of checksum DMA automatic processing based on descriptors XOR operation for any number of data items Arbitrates requests from the channel for checksum processing and FEC channel. Channel arbitration mode is round robin scheduling. Conversion between I-BUS protocol and A-DMAC protocol Distribution of register R/W requests from the CPU to each module Conversion between STIF protocol and A-DMAC protocol STIF0 is fixed at channel 0 for encryption/authentication. STIF1 is fixed at channel 1 for encryption/authentication. Rev. 1.00 Nov. 14, 2007 Page 496 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.1.3 Restrictions on the A-DMAC The following restrictions apply to the A-DMAC: • The A-DMAC supports only register access in 32-bit units. • If the channel processor, or FEC processor is running, write to registers related to the appropriate processor is inhibited. However, you can write data to the following two registers by verifying them after the write even if the appropriate processor is running. Write data repeatedly till verify succeeds.  Channel [i] processing control register (C[i]C) (However, do not rewrite the C[i]C_R bit of the running channel processor.)  Channel [i] processing interrupt request register (C[i]I) • Descriptors of data size 0 are inhibited. Rev. 1.00 Nov. 14, 2007 Page 497 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2 Register Descriptions The A-DMAC has the following registers. For details on the addresses of these registers and the register status in each processing state, see section 28, List of Registers. • • • • • • • • • • • • • • • • • • Channel [i] processing control register (C[i]C) (i = 0, 1) Channel [i] processing mode register (C[i]M) (i = 0, 1) Channel [i] processing interrupt request register (C[i]I) (i = 0, 1) Channel [i] processing descriptor start address register (C[i]DSA) (i = 0, 1) Channel [i] processing descriptor current address register (C[i]DCA) (i = 0, 1) Channel [i] processing descriptor 0 register (C[i]D0) [control] (i = 0, 1) Channel [i] processing descriptor 1 register (C[i]D1) [source address] (i = 0, 1) Channel [i] processing descriptor 2 register (C[i]D2) [destination address] (i = 0, 1) Channel [i] processing descriptor 3 register (C[i]D3) [data length] (i = 0, 1) Channel [i] processing descriptor 4 register (C[i]D4) [checksum value write address] (i = 0, 1) FEC DMAC processing control register (FECC) FEC DMAC processing interrupt request register (FECI) FEC DMAC processing descriptor start address register (FECDSA) FEC DMAC processing descriptor current address register (FECDCA) FEC DMAC processing descriptor 0 register (FECD00) [control] FEC DMAC processing descriptor 1 register (FECD01D0A) [destination address] FEC DMAC processing descriptor 2 register (FECD02S0A) [source 0 address] FEC DMAC processing descriptor 3 register (FECD03S1A) [source 1 address] Rev. 1.00 Nov. 14, 2007 Page 498 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.1 Channel [i] Processing Control Register (C[i]C) (i = 0, 1) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16 C[i]C_R Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit: 15  14  13  12 C[i]C_ DWF 11  10  9  8 C[i]C_ VLD 7  6  5  4 C[i]C_ EIE 3  2  1  0 C[i]C_E Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 17 — 16 C[i]C_R 0 R/W Reset Writing 1 to this bit when the channel [i] processor is halted causes the channel [i] calculation sequence to be reset. This bit is automatically and immediately set to 0. Setting both this bit and the C[i]C_E bit to 1 causes channel [i] processing to be newly started. 15 to 13 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 C[i]C_DWF 0 R WAIT State Flag after Descriptor Processing End 0: Non-WAIT state 1: WAIT state There are two methods for understanding the processing state of the DMAC channel [i] descriptor. In one, when the DMAC channel [i] descriptor is set, C[i]DWE is set to 1 and then C[i]DIE is set to 1 to accept the "1 descriptor processing end" interrupt request. In the other, the processing state is observed till this bit is set to 1. 11 to 9 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 499 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 8 Bit Name C[i]C_VLD Initial Value 0 R/W R/W Description Variable-Length Descriptor Control Flag 0: Fixed-length descriptor (32 bytes) 1: Variable-length descriptor (16/32 bytes) The A-DMAC channel uses the 32-byte fixed length structure or 16/32-byte variable-length structure. If this bit is set to 0 to define the descriptor as the fixed-length, the descriptor is always read as 32 bytes. If this bit is set to 1 to define the descriptor as the variable-length, the first 16 bytes are read, and if r_cid4/r_cid5/r_cid6/r_cid7 information is required, the remaining 16 bytes are read according to the contents of r_cidm/r_cihm. 7 to 5 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 C[i]C_EIE 0 R/W "Processing End" Interrupt Request Enable When processing ends, specifies whether to enable or disable the "processing end" interrupt request. 0: Disables the "processing end" interrupt request. 1: Enables the "processing end" interrupt request. A-DMAC channel [i] processing end means fetching of depleted descriptors (invalid descriptors (descriptors where C[i]F0 is set to 0)). 3 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 500 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 0 Bit Name C[i]C_E Initial Value 0 R/W R/W Description Execution Request Setting this bit to 1 causes channel [i] processing to be started. Setting this bit to 0 causes channel [i] processing to be suspended. When 0 is written to this bit, 0 is read immediately but the channel [i] processor does not stop immediately. That is, the processor stops after it writes back to the descriptor being processed. To understand the channel operating state, set the C[i]C_EIE bit to 1 to accept the "operation end" interrupt request or poll the "operation end" interrupt request flag. To start new processing, the channel [i] of the STIF must be initialized. 0: Channel [i] processing is halted. 1: Channel [i] processing is in progress. Determine if channel [i] processing is suspended when the processor writes back to the descriptor. Rev. 1.00 Nov. 14, 2007 Page 501 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.2 Channel [i] Processing Mode Register (C[i]M) (i = 0, 1) Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12  11  10  9  8  7  6  5  4 C[i]M_ LIE 3  2  1  0  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R Bit 31 to 5 Bit Name — Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 4 C[i]M_LIE 0 R/W "Last Data Descriptor End Processing" Interrupt Request Enable When last data (C[i]F2=1) descriptor end processing ends, specifies whether to enable or disable the interrupt request. 0: Disables the "last data descriptor processing end" interrupt request. 1: Enables the "last data descriptor processing end" interrupt request. 3 to 0 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 502 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.3 Channel [i] Processing Interrupt Request Register (C[i]I) (i = 0, 1) ad_irqc[i]_n is asserted as negation of logical OR of all bits in this register. Bit: 31  30  29  28  27  26  25  24  23  22  21  20  19  18  17  16  Initial Value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit: 15  14  13  12 C[i]I_ DI 11  10  9  8 C[i]I_ LI 7  6  5  4  3  2  1  0 C[i]I_ EI Initial Value: R/W: 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 31 to 13 — 12 C[i]I_DI 0 R/W "1 Descriptor Processing End" Interrupt Request (interrupt request to notify you that the processor ended descriptor processing and wrote back the descriptor) This bit is cleared to 0 by writing 1 to it. When 0 is written to this bit, the current state is retained. 0: The "1 descriptor processing end" interrupt is not requested. 1: The "1 descriptor processing end" interrupt is requested. 11 to 9 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 503 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 8 Bit Name C[i]I_LI Initial Value 0 R/W R/W Description "Continuous Data Last Descriptor Processing End" Interrupt Request (interrupt request to notify you that processing described in the descriptor where C[i]F2 is set to 1 ended) This bit is cleared to 0 by writing 1 to it. When 0 is written to this bit, the current state is retained. 0: The "last descriptor processing end" interrupt is not requested. 1: The "last descriptor processing end" interrupt is requested. 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 C[i]I_EI 0 R/W "Processing End" Interrupt Request This bit indicates whether the "processing end" interrupt is requested. This bit is cleared to 0 by writing 1 to it. When 0 is written to this bit, the current state is retained. 0: The "processing end" interrupt is not requested. 1: The "processing end" interrupt is requested. "Processing end" means fetching of depleted descriptors (invalid descriptors (descriptors where C[i]F0 is set to 0)). Rev. 1.00 Nov. 14, 2007 Page 504 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.4 Channel [i] Processing Descriptor Start Address Register (C[i]DSA) (i = 0, 1) Do not write any value to this register when C[i]C_E is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C[i]DSA[31:16] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 C[i]DSA[15:4] C[i]DSA[3:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 31 to 4 3 to 0 Bit Name C[i]DSA[31:4] C[i]DSA[3:0] Initial Value All 0 All 0 R/W R/W R Description Descriptor Ring Start Address Specify a descriptor ring start address. Set a 16-byte boundary address value. Rev. 1.00 Nov. 14, 2007 Page 505 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.5 Channel [i] Processing Descriptor Current Address Register (C[i]DCA) (i = 0, 1) Do not write any value to this register when C[i]C_E is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C[i]DCA[31:16] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 C[i]DCA[15:4] C[i]DCA[3:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R Bit 31 to 4 3 to 0 Bit Name C[i]DCA[31:4] C[i]DCA[3:0] Initial Value All 0 All 0 R/W R/W R Description Descriptor Current Address Specify the start address of descriptor processing. Set a 16-byte boundary address value. When descriptor processing is in progress, these bits indicate the address of descriptor currently being processed. After descriptor write-back, these bits indicate the address of the next descriptor. Rev. 1.00 Nov. 14, 2007 Page 506 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.6 Channel [i] Processing Descriptor 0 Register (C[i]D0) [Control] (i = 0, 1) Do not write any value to this register when C[i]C_E is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 C[i]DA 18 C[i]SA 17 16 C[i]CRDO[3:0] C[i]CHDO[3:0] C[i]SO[3:0] C[i]CSM[1:0] Initial Value: 0 R/W: R/W Bit: 15  0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 14  13  12  11  10  9  8  7  6  5  4  3  2 C[i]F2 1 C[i]F1 0 C[i]F0 Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Bit Name Initial Value All 0 R/W R/W Description Transfer Data Destination Data Sequence Specify a swap method for writing transfer data after encryption processing from the A-DMAC to memory such as the STIF and SDRAM or after checksum operation. Specify a swap method for writing the checksum operation result obtained from body data in the C[i]CHDO3 to C[i]CHDO0 bits, not these bits. 31 to 28 C[i]CRDO[3:0] Rev. 1.00 Nov. 14, 2007 Page 507 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit Bit Name Initial Value All 0 R/W R/W Description • When the destination is not the STIF (C[i]DA bit = 0) C[i]CRDO3: Data swap in two-byte units (longword swap in word units) 0: As-is 1: Swap C[i]CRDO2: Data swap in one-byte units (word swap in byte units) 0: As-is 1: Swap C[i]CRDO1: Inversion of bit 1 at address when one or two bytes are accessed 0: As-is 1: Inversion C[i]CRDO0: Inversion of bit 0 at address when one byte is accessed 0: As-is 1: Inversion C[i]CRDO1 and C[i]CRDO0 function for endian adjustment. Note that if an endian different from the endian of this LSI is used, up to three different addresses are accessed from the address where the start and end addresses are specified when an area is allocated. • When the destination is the STIF (C[i]DA bit = 1) C[i]CRDO3: Data swap in two-byte units (longword swap in word units) 0: As-is 1: Swap C[i]CRDO2: Data swap in one-byte units (word swap in byte units) 0: As-is 1: Swap C[i]CRDO1: Data swap in one-bit units (byte swap in one-bit units) 0: As-is 1: Swap C[i]CRDO0: Set this bit to 0 as reserved. 31 to 28 C[i]CRDO[3:0] Rev. 1.00 Nov. 14, 2007 Page 508 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit Bit Name Initial Value All 0 R/W R/W Description Checksum Operation Result Destination Data Sequence Specify a swap method for writing the checksum operation result from the A-DMAC to memory such as SDRAM. Specify a swap method for writing body data after checksum operation in the C[i]CRDO3 to C[i]CRDO0 bits. C[i]CHDO3: Data swap in two-byte units (longword swap in word units) 0: As-is 1: Swap C[i]CHDO2: Data swap in one-byte units (word swap in byte units) 0: As-is 1: Swap C[i]CHDO1: Inversion of bit 1 at address when one or two bytes are accessed 0: As-is 1: Inversion C[i]CHDO0: Inversion of bit 0 at address when one byte is accessed 0: As-is 1: Inversion C[i]CHDO1 and C[i]CHDO0 function for endian adjustment. Note that if an endian different from the endian of this LSI is used, up to three different addresses are accessed from the address where the start and end addresses are specified when an area is allocated. 27 to 24 C[i]CHDO[3:0] Rev. 1.00 Nov. 14, 2007 Page 509 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit Bit Name Initial Value R/W Description R/W Source Data Sequence Specify a swap method for reading data from memory such as the STIF and SDRAM to the A-DMAC. • When the source is not the STIF (C[i]SA bit = 0) C[i]SO3: Data swap in two-byte units (longword swap in word units) 0: As-is 1: Swap C[i]SO2: Data swap in one-byte units (word swap in byte units) 0: As-is 1: Swap C[i]SO1: Inversion of bit 1 at address when one or two bytes are accessed 0: As-is 1: Inversion C[i]SO0: Inversion of bit 0 at address when one byte is accessed 0: As-is 1: Inversion C[i]SO1 and C[i]SO0 function for endian adjustment. Note that if an endian different from the endian of this LSI is used, up to three different addresses are accessed from the address where the start and end addresses are specified when an area is allocated. When the source is the STIF (C[i]SA bit = 1) C[i]SO3: Data swap in two-byte units (longword swap in word units) 0: As-is 1: Swap C[i]SO2: Data swap in one-byte units (word swap in byte units) 0: As-is 1: Swap C[i]SO1: Data swap in one-bit units (byte swap in one-bit units) 0: As-is 1: Swap C[i]SO0: Set this bit to 0 as reserved. This bit is referenced in AES encryption/decryption, DES/3DES encryption/decryption, SHA hash generation, HMAC keyed hash generation, target data read for checksum operation, and data copy from memory to the STIF and from the STIF to memory. However, this bit is not referenced in key copy and initial vector copy. 23 to 20 C[i]SO[3:0] All 0 • Rev. 1.00 Nov. 14, 2007 Page 510 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 19 Bit Name C[i]DA Initial Value 0 R/W R/W Description Destination Attribute Specifies whether the data read source uses the channel [i] (the destination address is not used) of the STIF or the destination address (memory such as SDRAM). 0: Uses the destination address (memory such as SDRAM). 1: Uses the channel [i] of the STIF 18 C[i]SA 0 R/W Source Attribute Specifies whether the data read source uses the channel [i] (the source address is not used) of the STIF or the source address (memory such as SDRAM). 0: Uses the source address (memory such as SDRAM). 1: Uses the channel [i] of the STIF 17, 16 C[i]CSM[1:0] 00 R/W Checksum Mode 00: Checksum (not initialized, not written back) Not beginning of data Not end of data 01: Checksum (not initialized, written back) Not beginning of data End of data 10: Checksum (initialized, not written back) Beginning of data Not end of data 11: Checksum (initialized, written back) Beginning of data End of data 15 to 3 — All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 511 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 2 Bit Name C[i]F2 Initial Value 0 R/W R/W Description Descriptor Execution Flag 2 When splitting continuous data into several descriptors for execution, set this bit to 1 in the descriptor that processes the last data part (because the pointer in the A-DMAC must be initialized to process the next descriptor). Use this flag when splitting and executing descriptors because the encryption/decryption part, authentication part, and checksum operation part in data such as IPsec/TLS differ. 0: Non-last descriptor that processes continuous data 1: Last descriptor that processes continuous data 1 C[i]F1 0 R/W Descriptor Execution Flag 1 When this bit is 1, the A-DMAC regards this descriptor as the last descriptor in the descriptor ring area. When processing of this descriptor ends, the A-DMAC returns to the beginning (descriptor start address) of the descriptor ring area. 0: Non-last descriptor ring 1: Last descriptor ring 0 C[i]F0 0 R/W Descriptor Execution Flag 0 When this bit is 0, the A-DMAC ends processing because this descriptor is invalid. When this bit is 1, this descriptor is valid. When this bit is 1 (valid descriptor), the A-DMAC sets this bit to 0 and writes back to the original address after processing of this descriptor ends. 0: Invalid descriptor 1: Valid descriptor Rev. 1.00 Nov. 14, 2007 Page 512 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.7 Channel [i] Processing Descriptor 1 Register (C[i]D1) [Source Address] (i = 0, 1) Do not write any value to this register when C[i]C_E is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C[i]D1[31:16] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 C[i]D1[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name C[i]D1[31:0] Initial Value All 0 R/W R/W Description Source Address Specify a source address. This register is used when source access involves memory reference. It is not used in the STIF. When copying a key or initial vector from the source, set 0000 in the lower four bits (16-byte boundary). When splitting continuous data into several descriptors for execution, specify the same source address in all the descriptors. Rev. 1.00 Nov. 14, 2007 Page 513 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) 14.2.8 Channel [i] Processing Descriptor 2 Register (C[i]D2) [Destination Address] (i = 0, 1) Do not write any value to this register when C[i]C_E is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C[i]D2[31:16] Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 C[i]D2[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 31 to 0 Bit Name C[i]D2[31:0] Initial Value All 0 R/W R/W Description Transfer Data Destination Address Specify a destination address to which to write back the transfer data. When splitting continuous data into several descriptors for execution, specify the same source address in all the descriptors. 14.2.9 Channel [i] Processing Descriptor 3 Register (C[i]D3) [Data Length] (i = 0, 1) Do not write any value to this register when C[i]C_E is set to 1. Bit: 31  30  29 28 27  26  25  24  23  22  21  20  19  18  17  16  C[i]DWE C[i]DIE Initial Value: 0 R/W: R/W Bit: 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 C[i]D3[15:0] Initial Value: 0 R/W: R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 1.00 Nov. 14, 2007 Page 514 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 31, 30 Bit Name — Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 29 C[i]DWE 0 R/W "1 Descriptor Processing End" Interrupt Release Wait Enable If this bit is 1 and the "1 descriptor processing" interrupt is requested, the A-DMAC waits for the interrupt release before it moves to next descriptor processing. 0: Does not observe the "1 descriptor processing end" interrupt. 1: Enables "1 descriptor processing end" interrupt release wait. 28 C[i]DIE 0 R/W "1 Descriptor Processing End" Interrupt Request Enable Specifies whether to enable or disable the "1 descriptor processing end" interrupt when processing of this descriptor ends. Processing does not end even if the "1 descriptor processing end" interrupt request is enabled. 0: Disables the "1 descriptor processing end" interrupt request. 1: Enables the "1 descriptor processing end" interrupt request. 27 to 16 — All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00 Nov. 14, 2007 Page 515 of 1262 REJ09B0437-0100 Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC) Bit 15 to 0 Bit Name C[i]D3[15:0] Initial Value All 0 R/W R/W Description Target Data Size (Byte Length) The target data size range that can be specified in these bits is as follows: 0 < C[I]D3[15:0]