Datasheet
32
Cover
Renesas RA2A1 Group
Datasheet
32-Bit MCU
Renesas Advanced (RA) Family
Renesas RA2 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.10 Mar 2020
Features
RA2A1 Group
Datasheet
Ultra-low power 48-MHz Arm® Cortex®-M23 core, up to 256-KB code flash memory, 32-KB SRAM, Capacitive Touch
Sensing Unit, 16-bit A/D Converter, 24-bit sigma-delta A/D Converter, 12-bit D/A Converter, 8-bit D/A Converter,
Operational Amplifier, security and safety features.
Features
■ Arm Cortex-M23 Core
Armv8-M architecture
Maximum operating frequency: 48 MHz
Arm Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: DWT, FPB, and CoreSight™ MTB-M23
CoreSight Debug Port: SW-DP
■ Memory
Up to 256-KB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
Up to 32-KB SRAM
Flash Cache (FCACHE)
Memory Protection Unit (MPU)
Memory Mirror Function (MMF)
128-bit unique ID
■ Connectivity
USB 2.0 Full-Speed (USBFS) module
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 3
- UART
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
Controller Area Network (CAN) module
■ Analog
16-bit A/D Converter (ADC16)
- 1.2 Msps
- Differential input mode
- Single-ended input mode
24-bit Sigma-Delta A/D Converter (SDADC24)
- 15.6 ksps
- Differential input mode
- Single-ended input mode
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8) × 2
High-Speed Analog Comparator (ACMPHS)
Low-Power Analog Comparator (ACMPLP) × 2
Operational Amplifier (OPAMP) × 3
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-bit (GPT32)
General PWM Timer 16-bit (GPT16) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ System and Power Management
Low power modes
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Security and Encryption
AES128/256
True Random Number Generator (TRNG)
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 5.5 V)
(1 to 4 MHz when VCC = 1.6 to 5.5 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General Purpose I/O Ports
Up to 49 input/output pins
- Up to 3 CMOS input
- Up to 46 CMOS input/output
- Up to 9 input/output 5 V tolerant
- Up to 3 high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = -40°C to +85°C
- 36-pin BGA (5 mm × 5 mm, 0.8 mm pitch)
Ta = -40°C to +105°C
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 32-pin LQFP (7 mm × 7 mm, 0.8 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)
■ Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
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RA2A1 Datasheet
1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates an energy-efficient Arm Cortex®-M23 32-bit core that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
Up to 256-KB code flash memory
32-KB SRAM
16-bit A/D Converter (ADC16)
24-bit Sigma-Delta A/D Converter (SDADC24)
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8)
Operational Amplifier (OPAMP) with configurable switches
Security features.
1.1
Table 1.1
Function Outline
Arm core
Feature
Functional description
Arm Cortex-M23 core
Maximum operating frequency: up to 48 MHz
Arm Cortex-M23 core:
- Revision: r1p0-00rel0
- Armv8-M architecture profile
- Single-cycle integer multiplier
- 17-cycle integer divider.
Arm Memory Protection Unit (Arm MPU):
- Armv8 Protected Memory System Architecture
- 8 protect regions.
SysTick timer:
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
256 KB of code flash memory. See section 43, Flash Memory in User’s Manual.
Data flash memory
8 KB of data flash memory. See section 43, Flash Memory in User’s Manual.
Memory Mirror Function (MMF)
The Memory Mirror Function (MMF) can be configured to mirror the desired application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. Your application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF) in User’s Manual.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory in User’s Manual.
SRAM
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). See section
42, SRAM in User’s Manual.
Table 1.3
System (1 of 2)
Feature
Functional description
Operating modes
Two operating modes:
Single-chip mode
SCI or USB boot mode.
See section 3, Operating Modes in User’s Manual.
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RA2A1 Datasheet
Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Resets
13 resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
CPU stack pointer error reset
Software reset.
See section 6, Resets in User’s Manual.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin and
the detection level can be selected using a software program. See section 8, Low Voltage
Detection (LVD) in User’s Manual.
Clocks
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator
Clock out support.
See section 9, Clock Generation Circuit in User’s Manual.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s
Manual.
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module. The ICU also controls NMI interrupts. See section 13, Interrupt Controller Unit (ICU) in
User’s Manual.
Key Interrupt Function (KINT)
A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 19, Key Interrupt Function
(KINT) in User’s Manual.
Low power modes
Power consumption can be reduced in multiple ways, such as by setting clock dividers,
stopping modules, selecting power control mode in normal operation, and transitioning to low
power modes. See section 11, Low Power Modes in User’s Manual.
Register write protection
The register write protection function protects important registers from being overwritten due to
software errors. See section 12, Register Write Protection in User’s Manual.
Memory Protection Unit (MPU)
Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 24, Watchdog Timer (WDT) in User’s
Manual.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates with an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a fail-safe mechanism when the system runs out of control. The
IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the
count value in the registers. See section 25, Independent Watchdog Timer (IWDT) in User’s
Manual.
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Table 1.4
1. Overview
Event Link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 17, Event Link Controller (ELC) in
User’s Manual.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 16, Data Transfer Controller (DTC) in User’s Manual.
Table 1.6
Timers
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with one channel and a 16-bit timer with six
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms can be generated for controlling
brushless DC motors. The GPT can also be used as a general-purpose timer. See section 21,
General PWM Timer (GPT) in User’s Manual.
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 20, Port Output Enable for GPT (POEG) in
User’s Manual.
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 22, Asynchronous General Purpose Timer (AGT) in User’s Manual.
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 23, Realtime Clock (RTC) in User’s Manual.
Table 1.7
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface
(SCI)
The Serial Communication Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 27, Serial Communications Interface (SCI) in User’s Manual.
I2C bus interface (IIC)
The 2-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C
(Inter-Integrated Circuit) bus interface functions. See section 28, I2C Bus Interface (IIC) in
User’s Manual.
Serial Peripheral Interface (SPI)
Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices.
See section 30, Serial Peripheral Interface (SPI) in User’s Manual.
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RA2A1 Datasheet
Table 1.7
1. Overview
Communication interfaces (2 of 2)
Feature
Functional description
Controller Area Network (CAN)
module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 29, Controller Area Network (CAN) Module in User’s Manual.
USB 2.0 Full-Speed (USBFS) module
The USB 2.0 Full-Speed (USBFS) module can operate as a device controller. The module
supports full-speed and low-speed transfer as defined in the Universal Serial Bus Specification
2.0. The module has an internal USB transceiver and supports all of the transfer types defined
in the Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of five pipes. Pipe 0 and
pipe 4 to pipe 7 can be assigned any endpoint number based on the peripheral devices used
for communication or based on your system.
The MCU supports Battery Charging Specification revision 1.2. Because the MCU can be
powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply
3.3 V. See section 26, USB 2.0 Full-Speed Module (USBFS) in User’s Manual.
Table 1.8
Analog (1 of 2)
Feature
Functional description
16-bit A/D Converter (ADC16)
A successive approximation 16-bit A/D Converter (ADC16) is provided. Up to 17 single-ended/
4 differential analog input channels are selectable. Reference voltage of SDADC24,
temperature sensor output, and internal reference voltage are selectable for conversion. The
calibration function calculates capacitor array DAC and gain/offset correction values under the
usage conditions to enable accurate
A/D conversion. See section 32, 16-Bit A/D Converter (ADC16) in User’s Manual.
24-bit Sigma-Delta A/D Converter
(SDADC24)
A 24-bit Sigma-Delta A/D Converter (SDADC24) with a programmable gain instrumentation
amplifier is provided. Up to 10 single-ended/5 differential analog input channels are selectable.
The 2 single-ended/1 differential analog input channels of these analog input channels are
inputs from internal OPAMP. Analog input multiplexer is input to the sigma-delta A/D converter
by the programmable gain instrumentation amplifier (PGA). The A/D conversion result is
filtered by the SINC3 digital filter, and then stored in an output register. The calibration function
calculates gain error and offset error correction values under the usage conditions to enable
accurate A/D conversion. See section 33, 24-Bit Sigma-Delta A/D Converter (SDADC24) in
User’s Manual.
12-bit D/A Converter (DAC12)
A 12-bit D/A Converter (DAC12) is provided. See section 34, 12-Bit D/A Converter (DAC12) in
User’s Manual.
8-bit D/A Converter (DAC8)
An 8-bit D/A Converter (DAC8) is provided. See section 35, 8-Bit D/A Converter (DAC8) in
User’s Manual.
Temperature Sensor (TSN)
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC16 for conversion and can be further used by the end
application. See section 36, Temperature Sensor (TSN) in User’s Manual.
High-Speed Analog Comparator
(ACMPHS)
The High-Speed Analog Comparator (ACMPHS) compares a reference voltage with an analog
input voltage. The comparison result can be read by software and also be output externally.
The reference voltage can be selected from either an input to the IVREFi (i = 0 to 2) pin, an
output from internal D/A converter, or from the internal reference voltage (Vref) generated
internally in the MCU.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 38, HighSpeed Analog Comparator (ACMPHS) in User’s Manual.
Low-Power Analog Comparator
(ACMPLP)
The Low-Power Analog Comparator (ACMPLP) compares a reference voltage with an analog
input voltage. The comparison result can be read by software and also be output externally.
The reference voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin, an
internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated internally
in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed
mode decreases the response delay time, but increases current consumption. Setting lowspeed mode increases the response delay time, but decreases current consumption. See
section 39, Low-Power Analog Comparator (ACMPLP) in User’s Manual.
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RA2A1 Datasheet
Table 1.8
1. Overview
Analog (2 of 2)
Feature
Functional description
Operational Amplifier (OPAMP)
The Operational Amplifier (OPAMP) can be used to amplify small analog input voltages and
output the amplified voltages. A total of three differential operational amplifier units with two
input pins and one output pin are provided. All units have switches that can select input
signals. Additionally, operational amplifier 0 has a switch that can select the output pin. See
section 37, Operational Amplifier (OPAMP) in User’s Manual.
Table 1.9
Human machine interfaces
Feature
Functional description
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do
not come into direct contact with the electrodes. See section 40, Capacitive Touch Sensing
Unit (CTSU) in User’s Manual.
Table 1.10
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generating polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 31, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 41,
Data Operation Circuit (DOC) in User’s Manual.
Table 1.11
Security
Feature
Functional description
AES
See section 44, AES Engine in User’s Manual.
True Random Number Generator
(TRNG)
See section 45, True Random Number Generator (TRNG) in User’s Manual.
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RA2A1 Datasheet
1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the
features.
Memory
256 KB code flash
Bus
Arm Cortex-M23
MPU
MPU
System
POR/LVD
8 KB data flash
Reset
NVIC
32 KB SRAM
Mode control
System timer
Test and DBG I/F
DTC
Timers
(H/M/L) OCO
Power control
DMA
GPT32 × 1
GPT16 × 6
Clocks
MOSC/SOSC
Communication interfaces
ICU
CAC
KINT
Register write
protection
Human machine interfaces
CTSU
SCI × 3
CAN × 1
AGT × 2
IIC × 2
RTC
SPI × 2
USBFS
with Battery
Charging
revision1.2
WDT/IWDT
Event link
Data processing
Analog
ELC
CRC
ADC16
TSN
OPAMP × 3
Security
DOC
DAC12 × 1
DAC8 × 2
ACMPHS × 1
ACMPLP × 2
SDADC24
AES + TRNG
Figure 1.1
Block diagram
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RA2A1 Datasheet
1.3
1. Overview
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a
list of products.
R7FA2A1AB3C FM#AA 0
Production identification code
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FM: LQFP 64 pins
FJ: LQFP 32 pins
BT: BGA 36 pins
NE: QFN 48 pins
NF: QFN 40 pins
Quality Grade
Operating temperature
2: -40°C to 85°C
3: -40°C to 105°C
Code flash memory size
B: 256 KB
Feature set
Group number
Series name
RA family
Flash memory
Renesas microcontroller
Figure 1.2
Table 1.12
Part numbering scheme
Product list
Product part number
Orderable part number
Package code
Code flash
Data flash
SRAM
256 KB
8 KB
32 KB
Operating
temperature
R7FA2A1AB3CFM
R7FA2A1AB3CFM#AA0
PLQP0064KB-C
R7FA2A1AB3CNE
R7FA2A1AB3CNE#AC0
PWQN0048KB-A
-40 to +105°C
R7FA2A1AB3CNF
R7FA2A1AB3CNF#AC0
PWQN0040KC-A
-40 to +105°C
R7FA2A1AB2CBT
R7FA2A1AB2CBT#AC0
PLBG0036GA-A
-40 to +85°C
R7FA2A1AB3CFJ
R7FA2A1AB3CFJ#AA0
PLQP0032GB-A
-40 to +105°C
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RA2A1 Datasheet
1.4
1. Overview
Function Comparison
Table 1.13
Function comparison
Part numbers
R7FA2A1AB3CFM
R7FA2A1AB3CNE
R7FA2A1AB3CNF
R7FA2A1AB2CBT
R7FA2A1AB3CFJ
Pin count
64
48
40
36
32
Package
LQFP
QFN
QFN
BGA
LQFP
Code flash memory
256 KB
Data flash memory
8 KB
SRAM
32 KB
Parity
16 KB
ECC
System
16 KB
CPU clock
48 MHz
Sub-clock
oscillator
Yes
ICU
KINT
No
Yes
8
6
4
Event control
ELC
Yes
DMA
DTC
Yes
Timers
GPT32
GPT16
6
4
3
4
1
2
2
RTC
Yes
WDT/IWDT
Yes
SCI
3
IIC
2
SPI
2
CAN
Yes
USBFS
Analog
3
1
6
AGT
Communication
4
Yes
No
ADC16
17 (4*1)
12 (3*1)
8 (1*1)
5 (1*1)
5 (1*1)
SDADC24
8 (4*1)
6 (3*1)
4 (2*1)
2 (1*1)
2 (1*1)
DAC12
DAC8
1
2*2
2
ACMPHS
ACMPLP
OPAMP
2
3
2
TSN
HMI
CTSU
Data processing
CRC
2*3
1
1
1
1
9
11
Yes
26
16
DOC
Security
11
Yes
Yes
AES and TRNG
Note 1. The number of channels of the differential analog input.
Note 2. Pin output function of DA8_1 cannot be used.
Note 3. Pin output function of DA8_0 and DA8_1 cannot be used.
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RA2A1 Datasheet
1.5
1. Overview
Pin Functions
Table 1.14
Pin functions (1 of 4)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply. Connect it
to VSS by a 0.1-μF capacitor. Place the capacitor close to the pin.
VCL
I/O
Connect this pin to VSS through a smoothing capacitor used to stabilize
the internal power supply. Place the capacitor close to the pin.
VSS
Input
Ground pin. Connect to the system power supply (0 V).
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input through
the EXTAL pin.
XCIN
Input
XCOUT
Output
Clock
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
CLKOUT
Output
Clock output pin
Operating mode control
MD
Input
Pins for setting the operating mode. The signal level on this pin must not
be changed during operation mode transition on release from the reset
state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal
goes low.
CAC
CACREF
Input
Measurement reference clock input pin
On-chip debug
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
Interrupt
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ7
Input
Maskable interrupt request pins
GPT
GTETRGA,
GTETRGB
Input
External trigger input pin
GTIOC0A to
GTIOC6A,
GTIOC0B to
GTIOC6B
I/O
Input capture, output compare, or PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
AGT
RTC
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
AGTEE0, AGTEE1
Input
External event input enable
AGTIO0, AGTIO1
I/O
External event input and pulse output
AGTO0, AGTO1
Output
Pulse output
AGTOA0, AGTOA1
Output
Output compare match A output
AGTOB0, AGTOB1
Output
Output compare match B output
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 11 of 100
RA2A1 Datasheet
1. Overview
Table 1.14
Pin functions (2 of 4)
Function
Signal
I/O
Description
SCI
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (clock synchronous mode)
RXD0, RXD1,
RXD9
Input
Input pins for received data (asynchronous mode/clock synchronous
mode)
TXD0, TXD1, TXD9
Output
Output pins for transmitted data (asynchronous mode/clock synchronous
mode)
CTS0_RTS0,
CTS1_RTS1,
CTS9_RTS9
I/O
Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low
SCL0, SCL1, SCL9
I/O
Input/output pins for the IIC clock (simple IIC)
SDA0, SDA1,
SDA9
I/O
Input/output pins for the IIC data (simple IIC)
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (simple SPI)
MISO0, MISO1,
MISO9
I/O
Input/output pins for slave transmission of data (simple SPI)
MOSI0, MOSI1,
MOSI9
I/O
Input/output pins for master transmission of data (simple SPI)
SS0, SS1, SS9
Input
Chip-select input pins (simple SPI), active-low
IIC
SCL0, SCL1
I/O
Input/output pins for clock
SDA0, SDA1
I/O
Input/output pins for data
SPI
RSPCKA, RSPCKB
I/O
Clock input/output pin
MOSIA, MOSIB
I/O
Inputs or outputs data output from the master
CAN
USBFS
MISOA, MISOB
I/O
Inputs or outputs data output from the slave
SSLA0, SSLB0
I/O
Input or output pin for slave selection
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output
Output pin for slave selection
CRX0
Input
Receive data
CTX0
Output
Transmit data
VSS_USB
Input
Ground pins
VCC_USB_LDO
Input
Power supply pin for USB LDO regulator
VCC_USB
I/O
Input: Power supply pin for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. This pin should be connected to
the D+ pin of the USB bus.
USB_DM
I/O
D- I/O pin of the USB on-chip transceiver. This pin should be connected to
the D- pin of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. This pin should be connected to VBUS
of the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a device controller.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 12 of 100
RA2A1 Datasheet
1. Overview
Table 1.14
Pin functions (3 of 4)
Function
Signal
I/O
Description
Analog power supply
AVCC0
Input
Analog voltage supply pin for the ADC16, DAC12, DAC8, ACMPHS,
ACMPLP, and OPAMP
AVSS0
Input
Analog ground pin for the ADC16, DAC12, DAC8, ACMPHS, ACMPLP,
and OPAMP
AVCC1
Input
Analog voltage supply pin for the SDADC24
AVSS1
Input
Analog ground pin for the SDADC24
VREFH0
Input
Analog reference voltage supply pin for the ADC16. Connect this pin to
AVCC0 when not using the ADC16.
VREFL0
Input
Analog reference ground pin for the ADC16. Connect this pin to AVSS0
when not using the ADC16.
VREFH
Input
Analog reference voltage supply pin for the DAC12
VREFL
Input
Analog reference ground pin for the DAC12
AN000 to AN008,
AN016 to AN023
Input
Input pins for the analog signals to be processed by the A/D converter
ADTRG0
Input
Input pins for the external trigger signals that start the A/D conversion,
active-low
ANSD0P to
ANSD3P
Input
Input pins for the analog signals to be processed by the SDADC24
ANSD0N to
ANSD3N
Input
Input pins for the analog signals to be processed by the SDADC24
ADC16
SDADC24
ADREG
Output
Regulator capacitance for the SDADC24
SBIAS
Output
Sensor power supply
VREFI
Input
External reference voltage supply pin for the SDADC24
DAC12
DA12_0
Output
Output pin for the analog signals to be processed by the 12-bit D/A
converter
DAC8
DA8_0, DA8_1
Output
Output pins for the analog signals to be processed by the 8-bit D/A
converter
Comparator output
VCOUT
Output
Comparator output pin
ACMPHS
IVREF0 to IVREF2
Input
ACMPLP
OPAMP
CTSU
KINT
Reference voltage input pin
IVCMP0 to IVCMP2 Input
Analog voltage input pin
CMPREF0,
CMPREF1
Input
Reference voltage input pins
CMPIN0, CMPIN1
Input
Analog voltage input pins
AMP0+ to AMP2+
Input
Analog voltage input pins
AMP0- to AMP2-
Input
Analog voltage input pins
AMP0O to AMP2O
Output
Analog voltage output pins
TS00 to TS25
Input
Capacitive touch detection pins (touch pins)
TSCAP
-
Secondary power supply pin for the touch driver
KR00 to KR07
Input
Key interrupt input pins
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 13 of 100
RA2A1 Datasheet
1. Overview
Table 1.14
Pin functions (4 of 4)
Function
Signal
I/O
Description
I/O ports
P000 to P003,
P012 to P015
I/O
General-purpose input/output pins
P100 to P112
I/O
General-purpose input/output pins
P200
Input
General-purpose input pin
P201, P204 to
P206, P212, P213
I/O
General-purpose input/output pins
P214, P215
Input
General-purpose input pins
P300 to P304
I/O
General-purpose input/output pins
P400 to P403,
P407 to P411
I/O
General-purpose input/output pins
P500 to P502
I/O
General-purpose input/output pins
P914, P915
I/O
General-purpose input/output pins
1.6
Pin Assignments
Figure 1.3
P100
P101
P102
P103
P104
P105
P106
P107
AVSS1
AVCC1
SBIAS/VREFI
ADREG
P112
P111
P110
P108/SWDIO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 1.3 to Figure 1.7 show the pin assignments.
P500
49
32
P300/SWCLK
P501
50
31
P301
P502
51
30
P302
P015
52
29
P303
P014/VREFL
53
28
P304
P013/VREFH
54
27
P200
P012
55
26
P201/MD
AVCC0
56
25
RES
AVSS0
57
24
P204
VREFL0
58
23
P205
VREFH0
59
22
P206
P003
60
21
VCC_USB_LDO
P002
61
20
VCC_USB
P001
62
19
P914/USB_DP
P000
63
18
P915/USB_DM
P109
64
17
VSS_USB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P400
P401
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
R7FA2A1AB3CFM
Pin assignment for LQFP 64-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 14 of 100
25
26
27
28
29
30
31
32
P102
P103
P104
P105
AVSS1
AVCC1
SBIAS/VREFI
ADREG
P110
P108/SWDIO
33
34
35
37
24
38
23
39
22
40
21
41
20
42
19
R7FA2A1AB3CNE
43
18
12
11
10
9
8
P300/SWCLK
P301
P302
P200
P201/MD
RES
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
VSS_USB
P400
P401
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
7
13
6
14
48
5
15
47
4
16
46
3
17
45
2
44
1
P500
P501
P502
P015
P014/VREFL
P013/VREFH
AVCC0
AVSS0
VREFL0
VREFH0
P000
P109
P100
P101
1. Overview
36
RA2A1 Datasheet
21
22
23
24
25
26
27
P101
P102
P103
AVSS1
AVCC1
SBIAS/VREFI
ADREG
P110
P108/SWDIO
28
29
31
20
32
19
33
18
34
17
35
36
R7FA2A1AB3CNF
16
15
10
9
8
7
P300/SWCLK
P301
P200
P201/MD
RES
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
VSS_USB
P400
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P408
P407
6
11
5
12
40
4
13
39
3
14
38
2
37
1
P500
P501
P502
P013
AVCC0
AVSS0
VREFL0
VREFH0
P000
P109
P100
Pin assignment for QFN 48-pin
30
Figure 1.4
Figure 1.5
Pin assignment for QFN 40-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 15 of 100
RA2A1 Datasheet
1. Overview
R7FA2A1AB2CBT
Figure 1.7
B
C
D
E
F
6
P500
P100
P101
SBIAS
/VREFI
P108
/SWDIO
P300
/SWCLK
6
5
P501
AVCC1
AVSS1
ADREG
P200
VCC_USB
5
4
P502
AVCC0
P110
P301
P201/MD
P915
/USB_DM
4
3
VREFL0
AVSS0
P000
P400
VCC_USB
P914
_LDO
/USB_DP
3
2
VREFH0
P214
/XCOUT
P109
1
VCL
P215
/XCIN
P213
/XTAL
A
B
C
VSS
VCC
RES
2
P212
/EXTAL
P408
P407
1
D
E
F
/VSS_USB
P100
P101
AVSS1
AVCC1
SBIAS/VREFI
ADREG
P110
P108/SWDIO
24
23
22
21
20
19
18
17
Pin assignment for BGA 36-pin (top view, pad side down)
P500
25
16
P501
26
15
P300/SWCLK
P301
P502
27
14
P200
AVCC0
28
13
P201/MD
AVSS0
29
12
RES
VREFL0
30
11
P204
VREFH0
31
10
P205
P109
32
9
P206
2
3
4
5
6
7
VSS
P213/XTAL
P212/EXTAL
VCC
P408
P407
8
1
VCL
R7FA2A1AB3CFJ
P400
Figure 1.6
A
Pin assignment for LQFP 32-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 16 of 100
RA2A1 Datasheet
Pin Lists
Interrupt
-
-
P401
AGTEE1 GTIU_A GTIOC4
_A
A_A
-
-
-
P402
GTIV_A
4
-
-
-
-
P403
GTIW_A GTIOC0
B_C
5
3
2
A1
2
VCL
6
4
3
B1
-
XCIN
P215
7
5
4
B2
-
XCOUT
P214
8
6
5
D2
3
VSS
9
7
6
C1
4
XTAL
P213
AGTEE1 GTETR
_B
GA_B
GTIOC0
A_B
RXD1_D/
MISO1_D/
SCL1_D
IRQ2_B
10
8
7
D1
5
EXTAL
P212
AGTIO0 GTETR
_A
GB_B
GTIOC0
B_B
TXD1_D/
MOSI1_D/
SDA1_D
IRQ3_B
11
9
8
E2
6
VCC
12
-
-
-
-
P411
GTIOC5
A_A
TXD0_F/
MOSI0_F/
SDA0_F/
RXD1_B/
MISO1_B/
SCL1_B
SSLA3_A
TS04
13
-
-
-
-
P410
GTIOC5
B_A
CTS0_RT
S0_A/
SS0_A/
TXD1_B/
MOSI1_B/
SDA1_B
SSLA2_A
TS05
14
10
-
-
-
P409
AGTO1_
A
GTIOC0
A_C
CTX0_B
SCK0_A/ SCL0_B
CTS1_RT
S1_B/
SS1_B
SSLA1_A
TSCAP_E IRQ7_A
15
11
9
E1
7
P408
AGTO0_ GTOUU GTIOC0
A
P_A
A_A
CRX0_B
RXD0_A/ SDA0_B
MISO0_A/
SCL0_A/
TXD1_C/
MOSI1_C/
SDA1_C
SSLA0_A
16
12
10
F1
8
CACREF P407
_B
AGTIO0 GTOUL
_C
O_A
USB_VB
US/
CTX0_D
TXD0_A/ SCL0_A
MOSI0_A/
SDA0_A/
TXD9_A/
MOSI9_A/
SDA9_A
RSPCKB
_B
TSCAP_D IRQ1_B
17
13
11
D2
-
VSS_USB
18
14
12
F4
-
P915
USB_DM
19
15
13
F3
-
P914
USB_DP
20
16
14
F5
-
VCC_US
B
21
17
15
E3
-
VCC_US
B_LDO
22
18
-
-
9
P206
AGTIO0 GTOVU
_B
P_A
GTIOC3
A_A
CTS0_RT SCL1_B
S0_C/
SS0_C/
TXD1_A/
MOSI1_A/
SDA1_A
SSLB0_A
TS07
IRQ6_A
23
-
-
-
10
P205
GTOVL
O_A
GTIOC3
B_A
TXD0_C/ SDA1_B
MOSI0_C/
SDA0_C/
CTS1_RT
S1_A/
SS1_A
MISOB_B
TS08
IRQ0_C
24
-
-
-
11
P204
RXD0_C/
MISO0_C/
SCL0_C/
SCK9_B
MOSIB_B
TS09
25
19
16
F2
12
RES
26
20
17
E4
13
MD
27
21
18
E5
14
P200
28
-
-
-
-
P304
GTIOC6
A_A
CTX0_A
SCK0_B/
TXD9_C/
MOSI9_C/
SDA9_C
MISOA_B
TS10
KR07
29
-
-
-
-
P303
GTIOC6
B_A
CRX0_A
CTS0_RT
S0_B/
SS0_B/
SCK1_A
MOSIA_B
TS11
KR06
30
22
-
-
-
CACREF P302
_A
TXD0_B/
MOSI0_B/
SDA0_B/
RXD1_A/
MISO1_A/
SCL1_A
RSPCKB
_A
TS12
KR05/
IRQ4_B
GTIOC0
A_D
GTIOC0
B_A
CTSU
-
-
OPAMP
2
3
DAC12,
DAC8
2
GTIOC1 RTCOUT
A_A
_C
ADC16
AGTEE0 GTETR
_A
GA_A
SPI
P400
IIC
1
SCI
D3
USBFS,
CAN
1
RTC
1
GPT
LQFP32
1
AGT
BGA36
ACMPHS,
ACMPLP
HMI
SDADC24
Analogs
QFN40
GPT_OPS,
POEG
Communication Interfaces
QFN48
I/O ports
Timers
LQFP64
Pin number
Power, System,
Clock, Debug,
CAC
1.7
1. Overview
CTS0_RT SDA1_A
S0_D/
SS0_D/
RXD1_C/
MISO1_C/
SCL1_C
MOSIA_A
CMPIN0
TS00
KR02/
IRQ0_A
SCK0_D/ SDA0_C
SCK9_A
SSLB1_A
VCOUT_
B
TS01
KR03/
IRQ5_B
CTS9_RT
S9_C/
SS9_C
SSLB2_A
TS02
SCK1_B
SSLB3_A
TS03
CMPIN1
TS06
IRQ1_A
P201
NMI
AGTOA1 GTOVL
_A
O_B
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
GTIOC3
B_B
Page 17 of 100
1. Overview
Interrupt
SWCLK
P300
17
SWDIO
P108
34
26
22
C4
18
CLKOUT_ P110
A
35
-
-
-
-
P111
36
-
-
-
-
CLKOUT_ P112
B
37
27
23
D5
19
ADREG
38
28
24
D6
20
SBIAS/
VREFI
39
29
25
B5
21
AVCC1
40
30
26
C5
22
AVSS1
41
-
-
-
-
P107
AN023
ANSD3N
42
-
-
-
-
P106
AN022
ANSD3P
43
31
-
-
-
P105
MOSIB_C AN021
ANSD2N
TS18
IRQ7_C
44
32
-
-
-
P104
MISOB_C AN020
ANSD2P
TS19
IRQ6_C
45
33
27
-
-
P103
GTIOC6
A_B
RSPCKB AN019
_C
ANSD1N
TS20
46
34
28
-
-
P102
GTIOC6
B_B
CTS9_RT
S9_D/
SS9_D
SSLB0_C AN018
ANSD1P
TS21
47
35
29
C6
23
P101
GTIOC5
A_B
RXD9_C/
MISO9_C/
SCL9_C
AN017
ANSD0N
IVREF2
TS22
IRQ5_C
48
36
30
B6
24
P100
GTIOC5
B_B
TXD9_D/
MOSI9_D/
SDA9_D
AN016
ANSD0P
IVCMP2
TS23
IRQ4_C
49
37
31
A6
25
P500
GTIOC5
A_C
RXD0_D/
MISO0_D/
SCL0_D
AN000
50
38
32
A5
26
P501
GTIOC5
B_C
TXD0_E/
MOSI0_E/
SDA0_E
AN001
51
39
33
A4
27
P502
CTS0_RT
S0_E/
SS0_E
AN002
52
40
-
-
-
53
41
-
-
-
VREFL
P014
GTIOC6
A_C
AN004
54
42
34
-
-
VREFH
P013
GTIOC6
B_C
AN005
55
-
-
-
-
56
43
35
B4
28
AVCC0
57
44
36
B3
29
AVSS0
58
45
37
A3
30
VREFL0
59
46
38
A2
31
VREFH0
60
-
-
-
61
-
-
62
-
63
64
AGTOB0 GTOWL GTIOC2
_A
O_A
B_B
CTX0_C
TXD0_D/ SDA1_D
MOSI0_D/
SDA0_D/
RXD9_B/
MISO9_B/
SCL9_B
RSPCKA ADTRG0_
_A
A
RTCOUT
_B
TS13
TSCAP_A IRQ2_A
RSPCKA
_B
TS14
SDA1_C
SSLA0_B
TSCAP_B IRQ7_B
DA12_0
AN008
-
P003
AN006
-
-
P002
AN007
-
-
-
P001
47
39
C3
-
P000
AGTIO1
_A
48
40
C2
32
P109
AGTOA0 GTETR
_A
GB_A
IRQ6_B
IVCMP0
AMP0+
TS24
IRQ3_C
IVREF0
AMP0-
TS25
IRQ2_C
AMP0O
AN003
P012
Note:
CMPREF
1
KR04/
IRQ5_A
SCL1_C
P015
RTCOUT
_D
CTSU
16
E6
MOSIB_A
OPAMP
F6
21
RXD0_B/ SDA0_A
MISO0_B/
SCL0_B/
CTS9_RT
S9_B/
SS9_B
DAC12,
DAC8
20
25
ADC16
24
33
AGTOB1 GTOWU GTIOC2 RTCOUT
_A
P_A
A_B
_A
SPI
32
P301
IIC
15
SCI
D4
USBFS,
CAN
19
RTC
23
GPT
LQFP32
31
AGT
BGA36
ACMPHS,
ACMPLP
HMI
SDADC24
Analogs
QFN40
GPT_OPS,
POEG
Communication Interfaces
QFN48
I/O ports
Timers
LQFP64
Pin number
Power, System,
Clock, Debug,
CAC
RA2A1 Datasheet
IRQ1_C
AMP1O
DA8_0
IVREF1
AMP1-
IVCMP1
AMP1+
AMP2O
AMP2DA8_1
AMP2+
CTS9_RT
S9_A/
SS9_A
RSPCKB
_D
TS15
IRQ0_B
GTIOC4
B_B
RXD9_A/ SCL0_C
MISO9_A/
SCL9_A
MISOB_A
TS16
KR00/
IRQ4_A
GTIOC1
B_B
SCK0_C/ SCL1_A
TXD9_B/
MOSI9_B/
SDA9_B
MISOA_A ADTRG0_
B
TS17
KR01/
IRQ3_A
CMPREF
0/
VCOUT_
A
Several pin names have the added suffix of _A, _B, _C, _D, _E and _F. The suffix can be ignored when assigning
functionality.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 18 of 100
RA2A1 Datasheet
2.
2. Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = AVCC1 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5 V
VREFH = VREFH0 = 1.6 to AVCC0
VSS = AVSS0 = AVSS1 = VREFL = VREFL0 = VSS_USB = 0 V
Ta = Topr.
Note 1.
Note 2.
The typical condition is set to VCC = 3.3 V.
When USBFS is not used.
Figure 2.1 shows the timing conditions.
For example, P300
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The measurement conditions for the timing specifications of each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities of each pin to meet the conditions of your system.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function
pin is mixed, the A/C specification of each function is not guaranteed.
2.1
Absolute Maximum Ratings
Table 2.1
Absolute maximum ratings (1 of 2)
Parameter
Symbol
Value
Unit
Power supply voltage
VCC
-0.5 to +6.5
V
5 V-tolerant ports*1
Vin
-0.3 to +6.5
V
P002, P003,
P012 to P015,
P500 to P502
Vin
-0.3 to AVCC0 + 0.3
V
P100 to P107
Vin
-0.3 to AVCC1 + 0.3
V
Others
Vin
-0.3 to VCC + 0.3
V
VREFH0
-0.3 to +6.5
V
VREFH
-0.3 to +6.5
V
-0.3 to AVCC1 + 0.3
V
-0.5 to +6.5
V
Input voltage
Reference power supply voltage
VREFI
Analog power supply voltage
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
AVCC0,
AVCC1*5
Page 19 of 100
RA2A1 Datasheet
Table 2.1
2. Electrical Characteristics
Absolute maximum ratings (2 of 2)
Parameter
Symbol
Value
Unit
USB power supply voltage
VCC_USB
-0.5 to +6.5
V
Analog input voltage
VCC_USB_LDO
-0.5 to +6.5
V
VAN
-0.3 to AVCC0 + 0.3
V
When AN016 to AN023 are
used
-0.3 to AVCC1 + 0.3
V
When ANSD0P to ANSD3P
and ANSD0N to ANSD3N
are used
-0.3 to AVCC1 + 0.3
V
When AN000 to AN008 are
used
Operating temperature*2 *3 *4
Topr
-40 to +85
-40 to +105
°C
Storage temperature
Tstg
-55 to +125
°C
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Ports P000, P111, P112, P205, P206, P301, P401, P407, and P409 are 5 V tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input
of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might
cause degradation of internal elements.
See section 2.2.1, Tj/Ta Definition.
Contact Renesas Electronics sales office for information on derating operation when Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
The upper limit of the operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering.
Use AVCC0 and AVCC1 under the same conditions:
AVCC0 = AVCC1
Caution:
Table 2.2
Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors with high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the
AVCC1 and AVSS1 pins, between the VCC_USB and VSS_USB pins, between the VREFH and VREFL
pins, and between the VREFH0 and VREFL0 pins when VREFH0 is selected as the high potential
reference voltage for the ADC16. Place capacitors of the following value as close as possible to every
power supply pin and use the shortest and heaviest possible traces:
- VCC and VSS: about 0.1 μF
- AVCC0 and AVSS0: about 0.1 μF
- AVCC1 and AVSS1: about 0.1 μF
- VREFH and VREFL: about 0.1 μF
- VREFH0 and VREFL0: about 10 μF.
Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7 μF capacitor. Connect the VREFH0 pin to a VREFL0 pin by
1 µF (-25% to +25%) capacitor when VREFADC is selected as the high potential reference voltage of
the ADC16. Connect the ADREG pin to a AVSS1 pin by a 0.47 µF (-50% to +20%) capacitor. Connect
the SBIAS/VREFI pin to a AVSS1 pin by a 0.22 µF (-20% to +20%) capacitor. Every capacitor must be
placed close to the pin.
Recommended operating conditions (1 of 2)
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltages
VCC*1, *2
When USBFS is not
used
1.6
-
5.5
V
When USBFS is used VCC_USB
USB Regulator
Disable
-
3.6
V
When USBFS is used VCC_USB
USB Regulator
_LDO
Enable
-
5.5
V
0
-
V
VSS
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
-
Page 20 of 100
RA2A1 Datasheet
Table 2.2
2. Electrical Characteristics
Recommended operating conditions (2 of 2)
Parameter
Symbol
Value
Min
Typ
Max
Unit
USB power supply voltages
VCC_USB
When USBFS is not
used
-
VCC
-
V
When USBFS is used 3.0
USB Regulator
Disable
(Input)
3.3
3.6
V
When USBFS is not
used
-
VCC
-
V
When USBFS is used
USB Regulator
Disable
-
VCC
-
V
-
5.5
V
VCC_USB_LDO
When USBFS is used 3.8
USB Regulator
Enable
Analog power supply voltages
VSS_USB
-
0
-
V
AVCC0*1, *2
1.6
-
5.5
V
AVSS0
-
0
-
V
AVCC1*1, *2
-
AVCC0
-
V
AVSS1
-
0
-
V
1.7
-
AVCC0
V
VREFH0
When used as
ADC16 Reference
VREFL0
VREFH
When used as
DAC12 Reference
VREFL
VREFI
Note 1.
Note 2.
Note 3.
When used as
SDADC24
Reference*3
-
0
-
V
1.7
-
AVCC0
V
-
0
-
V
0.8
-
2.4
V
Use AVCC0, AVCC1, and VCC under the following conditions:
AVCC0, AVCC1, and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 = AVCC1 ≥ 2.2 V.
AVCC0 = AVCC1 = VCC when VCC < 2.2 V or AVCC0 = AVCC1 < 2.2 V.
When powering on the VCC and AVCC0 and AVCC1 pins, power them on at the same time or the VCC pin first and then the
AVCC0 and AVCC1 pins.
The condition when using external input for the reference voltage of SDADC24.
2.2
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
-
125
°C
High-speed mode
Middle-speed mode
Low-voltage mode
Low-speed mode
SubOSC-speed mode
105*1
Note:
Note 1.
Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL
+ ICCmax × VCC.
The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section 1.3, Part
Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj is 105°C, otherwise it is
125°C.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 21 of 100
RA2A1 Datasheet
2.2.2
2. Electrical Characteristics
I/O VIH, VIL
Table 2.4
I/O VIH, VIL
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH
VCC × 0.7
-
5.8
V
-
VIL
-
-
VCC × 0.3
ΔVT
VCC × 0.05
-
-
RES, NMI
Other peripheral input pins
excluding IIC
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
ΔVT
VCC × 0.1
-
-
IIC (SMBus)*2
VIH
2.2
-
-
VCC = 3.6 to
5.5 V
VIH
2.0
-
-
VCC =2.7 to
3.6 V
VIL
-
-
0.8
VCC = 2.7 to
5.5 V
VIH
VCC × 0.8
-
5.8
-
VIL
-
-
VCC × 0.2
P002, P003,
P012 to P015,
P500 to P502
VIH
AVCC0 × 0.8
-
-
VIL
-
-
AVCC0 × 0.2
P100 to P107
VIH
AVCC1 × 0.8
-
-
VIL
-
-
AVCC1 × 0.2
VIH
VCC_USB ×
0.8
-
VCC_USB +
0.3
VIL
-
-
VCC_USB ×
0.2
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
Parameter
Schmitt trigger
input voltage
Input voltage
(except for
Schmitt trigger
input pin)
IIC (except for SMBus)*1
5 V-tolerant ports*3
P914, P915
EXTAL
Input ports pins except for
P002, P003, P012 to P015,
P100 to P107, P500 to P502,
P914, P915
Note 1.
Note 2.
Note 3.
SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_C, SCL1_B, SCL1_C, SDA1_B, SDA1_C (total 9 pins)
SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SDA0_C, SCL1_A, SCL1_B, SCL1_C, SDA1_A, SDA1_B, SDA1_C, SDA1_D
(total 13 pins)
P000, P111, P112, P205, P206, P301, P401, P407, P409 (total 9 pins)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 22 of 100
RA2A1 Datasheet
2.2.3
2. Electrical Characteristics
I/O IOH, IOL
Table 2.5
I/O IOH, IOL
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Parameter
Permissible output current
(average value per pin)
Ports P212, P213
Ports P407, P408, P409
Symbol
Min
Typ
IOH
-
IOL
-
IOH
-
IOL
-
Middle drive for IIC
Fast mode and
SPI*4
IOH
-
IOL
-
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
Low
drive*1
Other output
Ports P212, P213
Ports P407, P408, P409
Permissible output current
(max value total pins)
mA
-
-4.0
mA
-
4.0
mA
-
-8.0
mA
-
8.0
mA
-
-
-20.0
mA
-
20.0
mA
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Middle drive for IIC
Fast mode and
SPI*4
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
-
-
-20.0
mA
Low
drive*1
drive*2
Low
drive*1
IOL
-
-
20.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Low drive*1
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Middle drive*2
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
ΣIOH (max)
-
-
-30
mA
ΣIOL (max)
-
-
30
mA
Total of ports P100 to P107
ΣIOH (max)
-
-
-30
mA
ΣIOL (max)
-
-
30
mA
ΣIOH
-
-
-4.0
mA
ΣIOL
-
-
4.0
mA
ΣIOH (max)
-
-
-60
mA
ΣIOL (max)
-
-
60
mA
Total of all output
Note 5.
mA
4.0
Total of ports P002, P003, P012 to P015, P500 to
P502
Total of ports P914, P915
Note 1.
Note 2.
Note 3.
Note 4.
-4.0
-
-
Ports P914, P915
Other output pins*3
-
IOL
Middle
Permissible output current
(max value per pin)
Unit
IOH
Ports P914, P915
pins*3
Max
pin*5
This is the value when low driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Except for Ports P200, P214, P215, which are input ports.
This is the value when middle driving ability for IIC Fast mode and SPI is selected with the Port Drive Capability bit in PmnPFS
register.
For details on the permissible output current used with CTSU, see section 2.12, CTSU Characteristics.
Caution:
To protect the reliability of the MCU, the output current values should not exceed the values in Table
2.5. The average output current indicates the average current value measured during 100 μs.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
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RA2A1 Datasheet
2.2.4
2. Electrical Characteristics
I/O VOH, VOL, and Other Characteristics
Table 2.6
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 4.0 to 5.5 V
Parameter
Output voltage
IIC*1
Ports P407, P408,
P409
Low drive
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Max
Unit
Test conditions
VOL
-
-
0.4
V
VOL*2,*5
-
-
0.6
IOL = 6.0 mA
IOL = 3.0 mA
VCC - 0.8
-
-
IOH = -2.0 mA
-
-
0.8
IOL = 2.0 mA
VOH
VCC - 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
VOH
VCC - 1.0
-
-
IOH = -20 mA
VOL
-
-
1.0
IOL = 20 mA
Low drive
VOH
AVCC0 - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Middle drive
VOH
AVCC0 - 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
Low drive
VOH
AVCC1 - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Middle drive
VOH
AVCC1 - 0.8
-
-
IOH = -4.0 mA
drive*2,*3
Ports P914, P915
Other output pins*4
Typ
VOH
Middle
Ports P100 to P107
Min
VOL
Middle drive for IIC
Fast mode and SPI*5
Ports P002, P003,
P012 to P015,
P500 to P502
Symbol
VOL
-
-
0.8
IOL = 4.0 mA
VOH
VCC_USB - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Low drive
VOH
VCC - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Middle drive*6
VOH
VCC - 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SDA0_C, SCL1_A, SCL1_B, SCL1_C, SDA1_A, SDA1_B, SDA1_C, SDA1_D
(total 13 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Based on characterization data, not tested in production.
Except for P200, P214, P215, which are input ports.
This is the value when middle driving ability for IIC and SPI is selected with the Port Drive Capability bit in PmnPFS register for
P407, P408, and P409.
Except for P212, P213.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 24 of 100
RA2A1 Datasheet
Table 2.7
2. Electrical Characteristics
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 2.7 to 4.0 V
Parameter
Output voltage
Symbol
Min
Typ
Max
Unit
Test conditions
VOL
-
-
0.4
V
IOL = 3.0 mA
VOL*2,*5
-
-
0.6
IOL = 6.0 mA
Low drive
VOH
VCC - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
Middle drive for IIC
Fast mode and SPI*5
VOH
VCC - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
Middle drive*2,*3
VOH
VCC - 1.0
-
-
IOH = -20 mA
VCC = 3.3 V
VOL
-
-
1.0
IOL = 20 mA
VCC = 3.3 V
VOH
AVCC0 - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
AVCC0 - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
IIC*1
Ports P407, P408,
P409
Ports P002, P003,
P012 to P015,
P500 to P502
Ports P100 to P107
Low drive
Middle drive
Low drive
Middle drive
Ports P914, P915
Other output pins*4
Low drive
Middle
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
drive*6
VOH
AVCC1 - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
AVCC1 - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
VOH
VCC_USB - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
SCL0_A, SCL0_B, SCL0_C, SDA0_A, SDA0_B, SDA0_C, SCL1_A, SCL1_B, SCL1_C, SDA1_A, SDA1_B, SDA1_C, SDA1_D
(total 13 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Based on characterization data, not tested in production.
Except for P200, P214, P215, which are input ports.
This is the value when middle driving ability for IIC and SPI is selected with the Port Drive Capability bit in PmnPFS register for
P407, P408, and P409.
Except for P212, P213.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 25 of 100
RA2A1 Datasheet
Table 2.8
2. Electrical Characteristics
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V
Parameter
Output voltage
Ports P407, P408,
P409
Ports P002, P003,
P012 to P015,
P500 to P502
Ports P100 to P107
Symbol
Min
Typ
Max
Unit
Test conditions
Low drive
VOH
VCC - 0.3
-
-
V
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
Middle drive for IIC
Fast mode and SPI*2
VOH
VCC - 0.3
-
-
IOH = -1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
Low drive
VOH
AVCC0 - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
Middle drive
VOH
AVCC0 - 0.3
-
-
IOH = -1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
Low drive
VOH
AVCC0 - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
Middle drive
VOH
AVCC0 - 0.3
-
-
IOH = -1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
Ports P914, P915
Other output pins*1
Low drive
Middle
drive*3
VOH
VCC_USB - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
VOH
VCC - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
VOH
VCC - 0.3
-
-
IOH = -1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
Note 1. Except for ports P200, P214, P215, which are input ports.
Note 2. This is the value when middle driving ability for IIC and SPI is selected with the Port Drive Capability bit in the
PmnPFS register for P407, P408, and P409.
Note 3. Except for P212, P213.
Table 2.9
I/O other characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
RES, ports P200, P214, P215
| Iin |
-
-
1.0
μA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
5 V-tolerant ports
| ITSI |
-
-
1.0
μA
Vin = 0 V
Vin = 5.8 V
-
-
1.0
Other ports
Vin = 0 V
Vin = VCC
Input pull-up resistor
All ports
(except for P200, P214, P215,
P914, P915)
RU
10
20
50
kΩ
Vin = 0 V
Input capacitance
P012 to P015, P200, P502,
P914, P915
Cin
-
-
30
pF
-
-
15
Vin = 0 V
f = 1 MHz
Ta = 25°C
Other input pins
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 26 of 100
RA2A1 Datasheet
2.2.5
2. Electrical Characteristics
Output Characteristics for I/O Pins (Low Drive Capacity)
IOH/IOL vs VOH/VOL
60
50
VCC = 5.5 V
40
30
IOH/IOL [mA]
20
VCC = 3.3 V
10
VCC = 2.7 V
VCC = 1.6 V
0
VCC = 1.6 V
-10
VCC = 2.7 V
-20
VCC = 3.3 V
-30
-40
-50
VCC = 5.5 V
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.2
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
3
Ta = -40C
Ta = 25C
Ta = 105C
2
IOH/IOL [mA]
1
0
-1
Ta = 105C
Ta = 25C
Ta = -40C
-2
-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.3
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected
(reference data, except for P914 and P915)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 27 of 100
RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
20
15
Ta = -40C
Ta = 25C
Ta = 105C
IOH/IOL [mA]
10
5
0
-5
Ta = 105C
-10
Ta = 25C
Ta = -40C
-15
-20
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.4
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
30
Ta = -40C
Ta = 25C
Ta = 105C
20
IOH/IOL [mA]
10
0
-10
Ta = 105C
Ta = 25C
-20
Ta = -40C
-30
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.5
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected
(reference data, except for P914 and P915)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 28 of 100
RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
40
Ta = 105C
IOH/IOL [mA]
20
0
-20
Ta = 105C
-40
Ta = 25C
Ta = -40C
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.6
2.2.6
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected
(reference data, except for P914 and P915)
Output Characteristics for I/O Pins (Middle Drive Capacity)
IOH/IOL vs VOH/VOL
IOH/IOL [mA]
140
120
100
VCC = 5.5 V
80
60
40
20
VCC = 3.3 V
VCC = 2.7 V
VCC = 1.6 V
0
-20
-40
VCC = 1.6 V
VCC = 2.7 V
VCC = 3.3 V
-60
-80
-100
-120
VCC = 5.5 V
-140
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.7
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data, except for P914 and P915)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 29 of 100
RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
6
Ta = -40C
Ta = 25C
Ta = 105C
4
IOH/IOL [mA]
2
0
-2
Ta = 105C
-4
Ta = 25C
Ta = -40C
-6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.8
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is
selected (reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
40
Ta = -40C
Ta = 25C
30
Ta = 105C
IOH/IOL [mA]
20
10
0
-10
-20
Ta = 105C
Ta = 25C
-30
Ta = -40C
-40
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.9
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data, except for P914 and P915)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 30 of 100
RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
40
Ta = 105C
IOH/IOL [mA]
20
0
-20
Ta = 105C
-40
Ta = 25C
Ta = -40C
-60
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.10
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
140
120
Ta = -40C
Ta = 25C
IOH/IOL [mA]
100
80
60
Ta = 105C
40
20
0
-20
-40
-60
-80
-100
Ta = 105C
Ta = 25C
-120
-140
Ta = -40C
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.11
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data, except for P914 and P915)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 31 of 100
RA2A1 Datasheet
2.2.7
2. Electrical Characteristics
Output Characteristics for P407, P408 and P409 I/O Pins (Middle Drive
Capacity)
IOH/IOL vs VOH/VOL
IOH/IOL [mA]
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.12
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
Ta = 105C
40
IOH/IOL [mA]
20
0
-20
Ta = 105C
-40
Ta = 25C
Ta = -40C
-60
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.13
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 32 of 100
RA2A1 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
100
80
Ta = -40C
Ta = 25C
60
Ta = 105C
IOH/IOL [mA]
40
20
0
-20
-40
Ta = 105C
-60
Ta = 25C
-80
Ta = -40C
-100
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.14
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
220
180
Ta = -40C
Ta = 25C
140
Ta = 105C
IOH/IOL [mA]
100
60
20
-20
-60
-100
-140
Ta = 105C
Ta = 25C
-180
Ta = -40C
-220
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.15
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 33 of 100
RA2A1 Datasheet
2.2.8
2. Electrical Characteristics
Output Characteristics for IIC I/O Pins
IOL vs VOL
120
110
VCC = 5.5 V (Middle drive)
100
90
IOL [mA]
80
70
60
50
VCC = 3.3 V (Middle drive)
VCC = 5.5 V (Low drive)
40
VCC = 2.7 V (Middle drive)
30
20
VCC = 3.3 V (Low drive)
10
VCC = 2.7 V (Low drive)
0
0
1
2
3
4
5
6
VOL [V]
Figure 2.16
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 34 of 100
RA2A1 Datasheet
2.2.9
Table 2.10
2. Electrical Characteristics
Operating and Standby Current
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Symbol
Typ*10
Max
Unit
Test
Conditions
ICC
5.2
-
mA
*7, *11
ICLK = 32 MHz
3.8
-
ICLK = 16 MHz
2.3
-
ICLK = 8 MHz
1.6
-
ICLK = 48 MHz
12.1
-
ICLK = 32 MHz
8.3
-
ICLK = 16 MHz
4.6
-
ICLK = 8 MHz
2.8
-
ICLK = 48 MHz
12.6
-
*9, *11
ICLK = 32 MHz
10.9
-
*8, *11
Parameter
Supply
current*1
High-speed
mode*2
Normal mode
All peripheral clocks
disabled, while (1) code
executing from flash*5
All peripheral clocks
disabled, CoreMark code
executing from flash*5
All peripheral clocks
enabled, while (1) code
executing from flash*5
Sleep mode
ICLK = 48 MHz
ICLK = 16 MHz
5.9
-
ICLK = 8 MHz
3.4
-
All peripheral clocks
enabled, code executing
from flash*5
ICLK = 48 MHz
-
28.5
*9, *11
All peripheral clocks
disabled*5
ICLK = 48 MHz
2.7
-
*7
ICLK = 32 MHz
2.1
-
ICLK = 16 MHz
1.5
-
ICLK = 8 MHz
1.1
-
ICLK = 48 MHz
9.8
-
*9
ICLK = 32 MHz
8.9
-
*8
All peripheral clocks
enabled*5
ICLK = 16 MHz
5.0
-
ICLK = 8 MHz
2.9
-
2.5
-
1.6
-
1.3
-
Increase during BGO operation*6
Middle-speed
mode*2
Normal mode
Sleep mode
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 12 MHz
All peripheral clocks
disabled, CoreMark code
executing from flash*5
ICLK = 12 MHz
3.4
-
ICLK = 8 MHz
2.6
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
ICLK = 12 MHz
4.3
-
ICLK = 8 MHz
3.1
-
All peripheral clocks
enabled, code executing
from flash*5
ICLK = 12 MHz
-
12.6
All peripheral clocks
disabled*5
ICLK = 12 MHz
1.0
-
ICLK = 8 MHz
0.9
-
All peripheral clocks
enabled*5
ICLK = 12 MHz
3.6
-
Increase during BGO operation*6
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
ICLK = 8 MHz
ICLK = 8 MHz
ICC
2.7
-
2.5
-
mA
*7, *11
*8, *11
*7
*8
-
Page 35 of 100
RA2A1 Datasheet
Table 2.10
2. Electrical Characteristics
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Supply
current*1
Low-speed
mode*3
Normal mode
Sleep mode
Low-voltage
mode*3
Normal mode
Sleep mode
Suboscspeed
mode*4
Normal mode
Sleep mode
Symbol
Typ*10
Max
Unit
Test
Conditions
ICC
0.3
-
mA
*7, *11
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 1 MHz
All peripheral clocks
disabled, CoreMark code
executing from flash*5
ICLK = 1 MHz
0.4
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
ICLK = 1 MHz
0.5
-
All peripheral clocks
enabled, code executing
from flash*5
ICLK = 1 MHz
-
2.5
All peripheral clocks
disabled*5
ICLK = 1 MHz
0.2
-
*7
All peripheral clocks
enabled*5
ICLK = 1 MHz
0.4
-
*8
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 4 MHz
1.5
-
All peripheral clocks
disabled, CoreMark code
executing from flash*5
ICLK = 4 MHz
2.2
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
ICLK = 4 MHz
2.5
-
All peripheral clocks
enabled, code executing
from flash*5
ICLK = 4 MHz
-
7.0
All peripheral clocks
disabled*5
ICLK = 4 MHz
1.3
-
*7
All peripheral clocks
enabled*5
ICLK = 4 MHz
2.3
-
*8
All peripheral clocks
disabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
6.5
-
All peripheral clocks
enabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
12.1
-
All peripheral clocks
enabled, code executing
from flash*5
ICLK = 32.768 kHz
-
190.0
All peripheral clocks
disabled*5
ICLK = 32.768 kHz
4.5
-
*8
All peripheral clocks
enabled*5
ICLK = 32.768 kHz
10.2
-
*8
ICC
ICC
*8, *11
mA
*7, *11
*8, *11
μA
*8, *11
Note 1.
Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. FCLK, PCLKB, and PCLKD are set to divided by 64.
Note 8. FCLK, PCLKB, and PCLKD are the same frequency as that of ICLK.
Note 9. FCLK and PCLKB are set to be divided by 2 and PCLKD is the same frequency as that of ICLK.
Note 10. VCC = 3.3 V.
Note 11. The flash cache is operating.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 36 of 100
RA2A1 Datasheet
2. Electrical Characteristics
ICC (mA)
30
25
Ta = 105Ԩ, ICLK = 48MHz*2
20
Ta = 105Ԩ, ICLK = 32MHz*2
15
Ta = 25Ԩ, ICLK = 48MHz*1
Ta = 105Ԩ, ICLK = 16MHz*2
Ta = 25Ԩ, ICLK = 32MHz*1
10
Ta = 105Ԩ, ICLK = 8MHz*2
Ta = 25Ԩ, ICLK = 16MHz*1
Ta = 105Ԩ, ICLK = 4MHz*2
Ta = 25Ԩ, ICLK = 8MHz*1
Ta = 25Ԩ, ICLK = 4MHz*1
5
0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
VCC (V)
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
Ta = 25Ԩ, ICLK = 48MHz *1
Ta = 105Ԩ, ICLK = 48MHz *2
Ta = 25Ԩ, ICLK = 32MHz *1
Ta = 105Ԩ, ICLK = 32MHz *2
Ta = 25Ԩ, ICLK = 16MHz *1
Ta = 105Ԩ, ICLK = 16MHz *2
Ta = 25Ԩ, ICLK = 8MHz *1
Ta = 105Ԩ, ICLK = 8MHz *2
Ta = 25Ԩ, ICLK = 4MHz *1
Ta = 105Ԩ, ICLK = 4MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.17
Voltage dependency in high-speed operating mode (reference data)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 37 of 100
RA2A1 Datasheet
2. Electrical Characteristics
10
9
Ta = 105Ԩ, ICLK = 12MHz*2
8
ICC (mA)
7
Ta = 105Ԩ, ICLK = 8MHz*2
6
5
Ta = 25Ԩ, ICLK = 12MHz*1
Ta = 105Ԩ, ICLK = 4MHz*2
Ta = 25Ԩ, ICLK = 8MHz*1
4
3
2
Ta = 25Ԩ, ICLK = 4MHz*1
Ta = 105Ԩ, ICLK = 1MHz*2
Ta = 25Ԩ, ICLK = 1MHz*1
1
0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
VCC (V)
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
Ta = 25Ԩ, ICLK = 12MHz *1
Ta = 105Ԩ, ICLK = 12MHz *2
Ta = 25Ԩ, ICLK = 8MHz *1
Ta = 105Ԩ, ICLK = 8MHz *2
Ta = 25Ԩ, ICLK = 4MHz *1
Ta = 105Ԩ, ICLK = 4MHz *2
Ta = 25Ԩ, ICLK = 1MHz *1
Ta = 105Ԩ, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.18
Voltage dependency in middle-speed operating mode (reference data)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 38 of 100
RA2A1 Datasheet
2. Electrical Characteristics
1.6
1.4
Ta = 105Ԩ, ICLK = 1MHz*2
ICC (mA)
1.2
1.0
0.8
0.6
Ta = 25Ԩ, ICLK = 1MHz*1
0.4
0.2
0.0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
VCC (V)
Ta = 25Ԩ, ICLK = 1MHz *1
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
Ta = 105Ԩ, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.19
Voltage dependency in low-speed operating mode (reference data)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 39 of 100
RA2A1 Datasheet
2. Electrical Characteristics
5.0
4.5
Ta = 105Ԩ, ICLK = 4MHz*2
4.0
ICC (mA)
3.5
3.0
2.5
Ta = 25Ԩ, ICLK = 4MHz*1
Ta = 105Ԩ, ICLK = 1MHz*2
2.0
1.5
Ta = 25Ԩ, ICLK = 1MHz*1
1.0
0.5
0.0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
VCC (V)
㻠㻚㻡
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
Ta = 25Ԩ, ICLK = 4MHz *1
Ta = 105Ԩ, ICLK = 4MHz *2
Ta = 25Ԩ, ICLK = 1MHz *1
Ta = 105Ԩ, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.20
Voltage dependency in low-voltage operating mode (reference data)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 40 of 100
RA2A1 Datasheet
2. Electrical Characteristics
180
160
Ta = 105Ԩ, ICLK = 32kHz*2
140
Ta = 25Ԩ, ICLK = 32kHz*1
ICC(MA)
120
100
80
60
40
20
Ta = 25Ԩ, ICLK = 32kHz*1*3
0
㻝㻚㻡
㻞㻚㻜
㻞㻚㻡
㻟㻚㻜
㻟㻚㻡
㻠㻚㻜
VCC (V)
㻠㻚㻡
Ta = 25Ԩ, ICLK = 32kHz *1
㻡㻚㻜
㻡㻚㻡
㻢㻚㻜
Ta = 105Ԩ, ICLK = 32kHz *2
Ta = 25Ԩ, ICLK = 32kHz *1*3
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Note 3. MOCO and DAC are stopped.
Figure 2.21
Table 2.11
Voltage dependency in subosc-speed operating mode (reference data)
Operating and standby current (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Symbol
Typ*3
Max
Unit
Test conditions
ICC
0.5
2.0
μA
-
Ta = 55°C
0.8
7.0
Ta = 85°C
1.8
17.0
Ta = 105°C
4.4
45.0
Increment for RTC operation with
low-speed on-chip oscillator*4
0.4
-
-
Increment for RTC operation with
sub-clock oscillator*4
0.5
-
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
1.3
-
SOMCR.SODRV[1:0] are 00b
(normal mode)
Parameter
Supply
current*1
Note 1.
Note 2.
Note 3.
Note 4.
Software Standby
mode*2
Ta = 25°C
Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOS transistors are in the off state.
The IWDT and LVD are not operating.
VCC = 3.3 V.
Includes the low-speed on-chip oscillator or sub-oscillation circuit current.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 41 of 100
RA2A1 Datasheet
2. Electrical Characteristics
100
ICC (MA)
10
1
0.1
㻙㻠㻜
㻙㻞㻜
㻜
㻞㻜
㻠㻜
㻢㻜
㻤㻜
㻝㻜㻜
Ta (Ԩ)
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.22
Temperature dependency in Software Standby mode (reference data)
10
ICC(MA)
Normal drive capacity*1
Low drive capacity*1
1
0
㻙㻠㻜
㻙㻞㻜
㻜
㻞㻜
㻠㻜
㻢㻜
㻤㻜
㻝㻜㻜
Ta (Ԩ)
Low drive capacity*1
Note:
Normal drive capacity*1
Average value of the tested middle samples during product evaluation.
Figure 2.23
Temperature dependency of RTC operation (reference data)
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Mar 16, 2020
Page 42 of 100
RA2A1 Datasheet
Table 2.12
2. Electrical Characteristics
Operating and standby current (3)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Symbol
Min
Typ
Max
Unit
Test
conditions
IAVCC0
-
-
1.5
mA
-
-
-
1.6
mA
-
-
-
0.9
mA
-
-
-
2.0
μA
-
-
-
1.29
mA
-
-
-
1.06
mA
GSET1 = 8, or
GTOTAL = 24,32
-
-
0.9
mA
GSET1, GTOTAL =
the others
-
-
1.0
μA
-
-
-
80
μA
-
-
-
60
nA
-
-
-
650
μA
-
-
-
100
nA
-
IREFI
-
-
30
μA
External VREF
mode
Temperature Sensor (TSN) operating current
ITNS
-
75
-
μA
-
Low-power
Analog
Comparator
(ACMPLP)
operating
current
ICMPLP
-
15
-
μA
-
Parameter
Analog power
supply current
During 16-bit A/D conversion
During 8-bit D/A conversion (per channel) *1
During 12-bit D/A conversion (per channel)
*1
Waiting for 16-bit A/D, 8-bit D/A and 12-bit D/A
conversion (all units) *5
During 24-bit sigma-delta A/D conversion
(at normal mode)
IAVCC1
During 24-bit sigma-delta A/D conversion
(at low-power conversion)
Waiting for 24-bit sigma-delta A/D conversion*6
Reference
power supply
current
During 16-bit A/D conversion
IREFH0
Waiting for 16-bit A/D conversion
During 12-bit D/A conversion
IREFH
Waiting for 12-bit D/A conversion
During 24-bit sigma-delta A/D conversion
Window comparator (high-speed mode)
Comparator (high-speed mode)
-
10
-
μA
-
Comparator (low-speed mode)
-
2
-
μA
-
High-speed analog comparator (ACMPHS) operating current
ICPMHS
-
70
100
μA
AVCC0 ≥ 2.7 V
Operational
Amplifier
(OPAMP)
operating
current
IAMP
-
10
16
μA
-
2 unit operating
-
19
30
μA
-
3 unit operating
-
28
44
μA
-
1 unit operating
-
280
360
μA
-
2 unit operating
-
530
690
μA
-
3 unit operating
-
770
1020
μA
-
Low power mode
Middle speed mode
High speed mode
1 unit operating
1 unit operating
-
0.74
0.91
mA
-
2 unit operating
-
1.41
1.74
mA
-
3 unit operating
-
2.07
2.57
mA
-
Internal reference voltage for ADC16 operating current
IVREFADC
-
65
130
μA
-
USBFS
operating
current
During USB communication under the following
settings and conditions:
Function controller is in Full-Speed mode and
- Bulk OUT transfer is (64 bytes) × 1
- Bulk IN transfer is (64 bytes) × 1
Host device is connected by a 1-meter USB cable
from the USB port.
IUSBF*2
-
3.6 (VCC)
1.1 (VCC_USB)*4
-
mA
-
During suspended state under the following setting
and conditions:
Function controller is in Full-Speed mode (the
USB_DP pin is pulled up)
Software Standby mode
Host device is connected through a 1-meter USB
cable from the USB port.
ISUSP*3
-
0.35 (VCC)
170 (VCC_USB)*4
-
μA
-
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The reference power supply current is included in the power supply current value for D/A conversion.
Current is consumed only by the USBFS.
Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition
to the current consumed by the MCU in the suspended state.
When VCC = VCC_USB = 3.3 V.
When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC160 module-stop bit) is in the module-stop
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Page 43 of 100
RA2A1 Datasheet
Note 6.
2. Electrical Characteristics
state.
When the MCU is in the MSTPCRD.MSTPD17 (SDADC24 module-stop bit) is in the module-stop state.
2.2.10
VCC Rise and Fall Gradient and Ripple Frequency
Table 2.13
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = AVCC1 = 0 to 5.5 V
Parameter
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup
Voltage monitor 0 reset enabled at
Symbol
Min
Typ
Max
Unit
Test conditions
SrVCC
0.02
-
2
ms/V
-
startup*1, *2
-
SCI/USB boot mode*2
Note 1.
Note 2.
2
When OFS1.LVDAS = 0.
At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 2.14
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit
(1.6 V).
When the VCC change exceeds VCC ± 10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple frequency
fr(VCC)
-
-
10
kHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.2
-
-
1
MHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.08
-
-
10
MHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.06
1.0
-
-
ms/V
When VCC change exceeds VCC ± 10%
Allowable voltage change rising and
falling gradient
dt/dVCC
1 / fr(VCC)
VCC
Figure 2.24
Vr(VCC)
Ripple waveform
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RA2A1 Datasheet
2.3
2. Electrical Characteristics
AC Characteristics
2.3.1
Table 2.15
Frequency
Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 2.4 to 5.5 V
Symbol
Min
Typ
Max*7
Unit
f
0.032768
-
48
MHz
2.4 to 2.7 V
0.032768
-
16
2.7 to 5.5 V
0.032768
-
32
2.4 to 2.7 V
0.032768
-
16
2.7 to 5.5 V
-
-
32
2.4 to 2.7 V
-
-
16
2.7 to 5.5 V
-
-
64*4
2.4 to 2.7 V
-
-
16
Parameter
Operation
frequency
System clock (ICLK)*6
FlashIF clock
2.7 to 5.5 V
(FCLK)*1,*2,*6
Peripheral module clock
Peripheral module clock
(PCLKB)*5,*6
(PCLKD)*3,*6
Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK
for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or
3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
Note 4. The upper-limit frequency of PCLKD is 32 MHz when the ADC16 is in use.
Note 5. The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
Note 6. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, PCLKD, and FCLK.
Note 7. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for
guaranteed operation, see Table 2.20, Clock timing.
Table 2.16
Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Symbol
Min
Typ
Max*6
Unit
f
0.032768
-
12
MHz
2.4 to 2.7 V
0.032768
-
12
1.8 to 2.4 V
0.032768
-
8
2.7 to 5.5 V
0.032768
-
12
2.4 to 2.7 V
0.032768
-
12
1.8 to 2.4 V
0.032768
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
Parameter
Operation
frequency
System clock
FlashIF clock
(ICLK)*5
2.7 to 5.5 V
(FCLK)*1,*2,*5
Peripheral module clock (PCLKB)*4,*5
Peripheral module clock
(PCLKD)*3,*5
Note 1. The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK
for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3
MHz. A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of FCLK must be ± 3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
Note 4. The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
Note 5. See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
R01DS0354EJ0110 Rev.1.10
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RA2A1 Datasheet
2. Electrical Characteristics
PCLKB, PCLKD, and FCLK.
Note 6. The maximum value of operation frequency does not include internal oscillator errors. For details on the range for
guaranteed operation, see Table 2.20, Clock timing.
Table 2.17
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Operation
frequency
Note 3.
Note 4.
Note 5.
Note 6.
Min
Typ
Max*6
Unit
f
0.032768
-
1
MHz
System clock (ICLK)*5
1.8 to 5.5 V
FlashIF clock (FCLK) *1,*2,*5
1.8 to 5.5 V
0.032768
-
1
Peripheral module clock (PCLKB)*4,*5
1.8 to 5.5 V
-
-
1
(PCLKD)*3,*5
1.8 to 5.5 V
-
-
1
Peripheral module clock
Note 1.
Note 2.
Symbol
The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory.
The frequency accuracy of FCLK must be ± 3.5% while programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, PCLKD,
and FCLK.
The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.20, Clock timing.
Table 2.18
Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Operation
frequency
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Min
Typ
Max*6
Unit
f
0.032768
-
4
MHz
System clock (ICLK)*5
1.6 to 5.5 V
FlashIF clock (FCLK)*1,*2,*5
1.6 to 5.5 V
0.032768
-
4
Peripheral module clock (PCLKB)*4,*5
1.6 to 5.5 V
-
-
4
(PCLKD)*3,*5
1.6 to 5.5 V
-
-
4
Peripheral module clock
Note 1.
Symbol
The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer
frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
The lower-limit frequency of PCLKD is 1 MHz when the ADC16 is in use.
The lower-limit frequency of PCLKB is 1 MHz when the SDADC24 is in use.
See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, PCLKD,
and FCLK.
The maximum value of operation frequency does not include internal oscillator errors. For details on the range for guaranteed
operation, see Table 2.20, Clock timing.
Table 2.19
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Operation
frequency
System clock (ICLK)*4
FlashIF clock
Min
Typ
Max
Unit
f
27.8528
32.768
37.6832
kHz
1.8 to 5.5 V
27.8528
32.768
37.6832
Peripheral module clock (PCLKB)*3,*4
1.8 to 5.5 V
-
-
37.6832
(PCLKD)*2,*4
1.8 to 5.5 V
-
-
37.6832
Peripheral module clock
Note 1.
Note 2.
Note 3.
Note 4.
1.8 to 5.5 V
(FCLK)*1,*4
Symbol
Programming and erasing the flash memory is not possible.
The ADC16 cannot be used.
The SDADC24 cannot be used.
See section 9, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, PCLKD,
and FCLK.
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Mar 16, 2020
Page 46 of 100
RA2A1 Datasheet
2.3.2
Table 2.20
2. Electrical Characteristics
Clock Timing
Clock timing (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
EXTAL external clock input cycle time
tXcyc
50
-
-
ns
Figure 2.25
EXTAL external clock input high pulse width
tXH
20
-
-
ns
EXTAL external clock input low pulse width
tXL
20
-
-
ns
EXTAL external clock rising time
tXr
-
-
5
ns
EXTAL external clock falling time
tXf
-
-
5
ns
tEXWT
0.3
-
-
μs
-
fEXTAL
-
-
20
MHz
2.4 ≤ VCC ≤ 5.5
-
-
8
1.8 ≤ VCC < 2.4
-
-
1
1.6 ≤ VCC < 1.8
1
-
20
1
-
8
EXTAL external clock input wait
time*1
EXTAL external clock input frequency
Main clock oscillator oscillation frequency
fMAIN
MHz
2.4 ≤ VCC ≤ 5.5
1.8 ≤ VCC < 2.4
1.6 ≤ VCC < 1.8
1
-
4
fLOCO
27.8528
32.768
37.6832
kHz
LOCO clock oscillation stabilization time
tLOCO
-
-
100
μs
Figure 2.26
IWDT-dedicated clock oscillation frequency
fILOCO
12.75
15
17.25
kHz
-
MOCO clock oscillation frequency
fMOCO
6.8
8
9.2
MHz
-
MOCO clock oscillation stabilization time
tMOCO
-
-
1
μs
-
HOCO clock oscillation frequency
fHOCO24
23.64
24
24.36
MHz
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
22.68
24
25.32
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
23.76
24
24.24
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
23.52
24
24.48
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
31.52
32
32.48
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
30.24
32
33.76
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
31.68
32
32.32
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
31.36
32
32.64
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
47.28
48
48.72
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
47.52
48
48.48
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
47.04
48
48.96
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
63.04
64
64.96
Ta = -40 to -20°C
2.4 ≤ VCC ≤ 5.5
63.36
64
64.64
Ta = -20 to 85°C
2.4 ≤ VCC ≤ 5.5
62.72
64
65.28
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
tHOCO24
tHOCO32
-
-
37.1
LOCO clock oscillation frequency
fHOCO32
fHOCO48*3
fHOCO64*4
HOCO clock oscillation
stabilization time*5, *6
Except low-voltage
mode
Low-voltage mode
Sub-clock oscillator oscillation frequency
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
tHOCO48
-
-
43.3
tHOCO64
-
-
80.6
tHOCO24
tHOCO32
tHOCO48
tHOCO64
-
-
100.9
fSUB
-
32.768
-
-
μs
Figure 2.27
kHz
-
Page 47 of 100
RA2A1 Datasheet
Table 2.20
2. Electrical Characteristics
Clock timing (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Sub-clock oscillation stabilization time*2
tSUBOSC
-
0.5
-
s
Figure 2.28
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Time until the clock can be used after the Main Clock Oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the sub-clock
oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time value recommended by the
oscillator manufacturer.
The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.
The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.
This is a characteristic when the HOCOCR.HCSTP bit is cleared to 0 (oscillation) in the MOCO stop state.
When the HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 μs.
Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
tXcyc
tXL
tXH
EXTAL external clock input
VCC × 0.5
tXr
Figure 2.25
tXf
EXTAL external clock input timing
LOCOCR.LCSTP
tLOCO
LOCO clock oscillator output
Figure 2.26
LOCO clock oscillation start timing
HOCOCR.HCSTP
tHOCOx*1
HOCO clock
Note 1.
Figure 2.27
x = 24, 32, 48, 64
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 2.28
Sub-clock oscillation start timing
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 48 of 100
RA2A1 Datasheet
2.3.3
Table 2.21
2. Electrical Characteristics
Reset Timing
Reset timing
Symbol
Min
Typ
Max
Unit
Test
conditions
At power-on
tRESWP
3
-
-
ms
Figure 2.29
Not at power-on
tRESW
30
-
-
μs
Figure 2.30
tRESWT
-
0.7
-
ms
Figure 2.29
-
0.3
-
-
0.5
-
ms
Figure 2.30
-
0.1
-
-
0.6
-
ms
Figure 2.31
-
0.15
-
Parameter
RES pulse width
enabled*1
Wait time after RES cancellation
(at power-on)
LVD0
Wait time after RES cancellation
(during powered-on state)
LVD0 enabled*1
Wait time after internal reset cancellation
(Watchdog timer reset, SRAM parity error
reset, SRAM ECC error reset, bus master
MPU error reset, bus slave MPU error reset,
stack pointer error reset, software reset)
LVD0 enabled*1
LVD0 disabled*2
tRESWT2
LVD0 disabled*2
LVD0
tRESWT3
disabled*2
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 2.29
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Figure 2.30
Reset input timing (1)
tRESWIW, tRESWIR
Independent watchdog timer reset
Software reset
Internal reset
tRESWT3
Figure 2.31
Reset input timing (2)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 49 of 100
RA2A1 Datasheet
2.3.4
2. Electrical Characteristics
Wakeup Time
Table 2.22
Timing of recovery from low power modes (1)
Parameter
Recovery time
from Software
Standby mode*1
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
High-speed
mode
Typ
Max
Unit
Test
conditions
Figure 2.32
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(20 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(20 MHz)*3
tSBYEX
-
14
25
μs
System clock source is HOCO*4
(HOCO clock is 32 MHz)
tSBYHO
-
43
52
μs
System clock source is HOCO*4
(HOCO clock is 48 MHz)
tSBYHO
-
44
52
μs
System clock source is HOCO*5
(HOCO clock is 64 MHz)
tSBYHO
-
82
110
μs
System clock source is MOCO
tSBYMO
-
16
25
μs
Timing of recovery from low power modes (2)
Parameter
Recovery time
from Software
Standby mode*1
Note 2.
Note 3.
Note 4.
Min
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h.
The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h.
Table 2.23
Note 1.
Symbol
Middle-speed
mode
Symbol
Min
Typ
Max
Unit
Test
conditions
Figure 2.32
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(12 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(12 MHz)*3
tSBYEX
-
2.9
10
μs
System clock source is HOCO*4
tSBYHO
-
38
50
μs
System clock source is MOCO (8 MHz)
tSBYMO
-
3.5
5.5
μs
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
The system clock is 12 MHz.
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Page 50 of 100
RA2A1 Datasheet
Table 2.24
2. Electrical Characteristics
Timing of recovery from low power modes (3)
Parameter
Recovery time
from Software
Standby mode*1
Low-speed
mode
Note 2.
Note 3.
Unit
Test
conditions
Figure 2.32
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(1 MHz)*3
tSBYEX
-
28
50
μs
tSBYMO
-
25
35
μs
Timing of recovery from low power modes (4)
Recovery time
from Software
Standby mode*1
Low-voltage
mode
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
Symbol
Min
Typ
Max
Unit
Test
conditions
tSBYMC
-
2
3
ms
Figure 2.32
tSBYEX
-
108
130
μs
tSBYHO
-
108
130
μs
(4 MHz)*2
(4 MHz)*3
System clock source is HOCO (4 MHz)
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.26
Timing of recovery from low power modes (5)
Symbol
Min
Typ
Max
Unit
Test
conditions
System clock source is sub-clock
oscillator (32.768 kHz)
tSBYSC
-
0.85
1
ms
Figure 2.32
System clock source is LOCO
(32.768 kHz)
tSBYLO
-
0.85
1.2
ms
Parameter
Recovery time
from Software
Standby mode*1
Note 1.
Max
System clock source is
main clock oscillator
(1 MHz)*2
Parameter
Note 2.
Note 3.
Typ
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.25
Note 1.
Min
Crystal
resonator
connected to
main clock
oscillator
System clock source is MOCO (1 MHz)
Note 1.
Symbol
Subosc-speed mode
The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode.
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Page 51 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 2.32
Software Standby mode cancellation timing
Table 2.27
Timing of recovery from low power modes (6)
Parameter
Recovery time from Software
Standby mode to Snooze
mode
Symbol
Min
Typ
Max
Unit
Test conditions
High-speed mode
System clock source is HOCO
tSNZ
-
36
45
μs
Figure 2.33
Middle-speed mode
System clock source is MOCO
(8 MHz)
tSNZ
-
1.3
3.6
μs
Low-speed mode
System clock source is MOCO
(1 MHz)
tSNZ
-
10
13
μs
Low-voltage mode
System clock source is HOCO
(4 MHz)
tSNZ
-
87
110
μs
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1 PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN bit is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.33
Recovery timing from Software Standby mode to Snooze mode
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RA2A1 Datasheet
2.3.5
2. Electrical Characteristics
NMI and IRQ Noise Filter
Table 2.28
NMI and IRQ noise filter
Parameter
Symbol
Min
NMI pulse width
tNMIW
200
tPcyc ×
2*1
200
tNMICK ×
IRQ pulse width
tIRQW
Max
Unit
Test conditions
-
-
ns
NMI digital filter disabled
-
-
-
-
-
-
200
-
-
tPcyc × 2*1
-
-
200
-
-
-
-
tIRQCK ×
Note:
Note:
Note 1.
Note 2.
Note 3.
3.5*2
Typ
3.5*3
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
NMI digital filter enabled
tNMICK × 3 ≤ 200 ns
tNMICK × 3 > 200 ns
ns
IRQ digital filter disabled
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
IRQ digital filter enabled
tIRQCK × 3 ≤ 200 ns
tIRQCK × 3 > 200 ns
200 ns minimum in Software Standby mode.
If the clock source is switched, add 4 clock cycles of the switched source.
tPcyc indicates the PCLKB cycle.
tNMICK indicates the cycle of the NMI digital filter sampling clock.
tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
tNMIW
Figure 2.34
NMI interrupt input timing
IRQ
tIRQW
Figure 2.35
IRQ interrupt input timing
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Page 53 of 100
RA2A1 Datasheet
2.3.6
2. Electrical Characteristics
I/O Ports, POEG, GPT, AGT, KINT, and ADC16 Trigger Timing
Note:
Table 2.29
I/O Ports, POEG, GPT, AGT, KINT, and ADC16 trigger timing
Parameter
Symbol
Min
Max
Unit
Test
conditions
I/O Ports
Input data pulse width
tPRW
1.5
-
tPcyc
Figure 2.36
POEG
POEG input trigger pulse width
tPOEW
3
-
tPcyc
Figure 2.37
GPT
Input capture pulse width
tGTICW
1.5
-
tPDcyc
Figure 2.38
2.5
-
250
-
ns
Figure 2.39
Single edge
Dual edge
AGT
AGTIO, AGTEE input cycle
AGTIO, AGTEE input high-level
width, low-level width
2.7 V ≤ VCC ≤ 5.5 V
tACYC*1
2.4 V ≤ VCC < 2.7 V
500
-
ns
1.8 V ≤ VCC < 2.4 V
1000
-
ns
1.6 V ≤ VCC < 1.8 V
2000
-
ns
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
tACKWH,
tACKWL
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTO, AGTOA, AGTOB
output cycle
100
-
ns
200
-
ns
400
-
ns
800
-
ns
62.5
-
ns
2.4 V ≤ VCC < 2.7 V
125
-
ns
1.8 V ≤ VCC < 2.4 V
250
-
ns
1.6 V ≤ VCC < 1.8 V
500
-
ns
2.7 V ≤ VCC ≤ 5.5 V
tACYC2
Figure 2.39
ADC16
16-bit A/D converter trigger input pulse width
tTRGW
1.5
-
tPcyc
Figure 2.40
KINT
KRn (n = 00 to 07) pulse width
tKR
250
-
ns
Figure 2.41
Note:
tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 1. Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
When switching the source clock: tPcyc × 6 < tACYC should be satisfied.
Port
tPRW
Figure 2.36
I/O ports input timing
POEG input trigger
tPOEW
Figure 2.37
POEG input trigger timing
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Mar 16, 2020
Page 54 of 100
RA2A1 Datasheet
2. Electrical Characteristics
Input capture
tGTICW
Figure 2.38
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.39
AGT I/O timing
ADTRG0
tTRGW
Figure 2.40
ADC16 trigger input timing
KR00 to KR07
tKR
Figure 2.41
2.3.7
Key interrupt input timing
CAC Timing
Table 2.30
CAC timing
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
CAC
CACREF input pulse width
tPcyc *1 ≤ tcac*2
tPcyc*1
Note 1.
>
tcac*2
Symbol
Min
Typ
Max
Unit
Test
conditions
tCACREF
4.5 × tcac + 3 × tPcyc
-
-
ns
-
5 × tcac + 6.5 × tPcyc
-
-
ns
tPcyc: PCLKB cycle.
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Mar 16, 2020
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RA2A1 Datasheet
Note 2.
2. Electrical Characteristics
tcac: CAC count clock source cycle.
2.3.8
SCI Timing
Table 2.31
SCI timing (1)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
SCI
Input clock cycle
Symbol
Asynchronous
tScyc
Clock synchronous
Max
Unit*1
Test conditions
tPcyc
Figure 2.42
4
-
6
-
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
-
20
ns
tSCKf
-
20
ns
tScyc
6
-
tPcyc
4
-
0.4
0.6
tScyc
1.8 V ≤ VCC ≤ 5.5 V tSCKr
-
20
ns
1.6 V ≤ VCC < 1.8 V
-
30
1.8 V ≤ VCC ≤ 5.5 V tSCKf
-
20
1.6 V ≤ VCC < 1.8 V
-
30
Input clock fall time
Output clock cycle
Asynchronous
Clock synchronous
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay
(master)
Clock
synchronous
Transmit data delay
(slave)
Clock
synchronous
tSCKW
1.8 V ≤ VCC ≤ 5.5 V tTXD
-
40
1.6 V ≤ VCC < 1.8 V
-
45
2.7 V ≤ VCC ≤ 5.5 V
-
55
2.4 V ≤ VCC < 2.7 V
-
60
1.8 V ≤ VCC < 2.4 V
-
100
1.6 V ≤ VCC < 1.8 V
Receive data setup
time (master)
Note 1.
Min
Clock
synchronous
-
125
45
-
2.4 V ≤ VCC < 2.7 V
55
-
1.8 V ≤ VCC < 2.4 V
90
-
2.7 V ≤ VCC ≤ 5.5 V
tRXS
1.6 V ≤ VCC < 1.8 V
110
-
2.7 V ≤ VCC ≤ 5.5 V
40
-
ns
ns
ns
ns
Receive data setup
time (slave)
Clock
synchronous
45
-
Receive data hold
time (master)
Clock synchronous
tRXH
5
-
ns
Receive data hold
time (slave)
Clock synchronous
tRXH
40
-
ns
1.6 V ≤ VCC < 2.7 V
Figure 2.43
ns
tPcyc: PCLKB cycle.
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RA2A1 Datasheet
2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0, 1, 9)
tScyc
Figure 2.42
SCK clock input timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
n = 0, 1, 9
Figure 2.43
SCI input/output timing in clock synchronous mode
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Page 57 of 100
RA2A1 Datasheet
Table 2.32
2. Electrical Characteristics
SCI timing (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 5.5 V
Parameter
Symbol
Min
Max
Unit*1
Test conditions
Simple
SPI
tSPcyc
4
65536
tPcyc
Figure 2.44
6
65536
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr,
tSPCKf
-
20
ns
-
30
tSU
45
-
2.4 V ≤ VCC < 2.7 V
55
-
1.8 V ≤ VCC < 2.4 V
80
-
1.6 V ≤ VCC < 1.8 V
110
-
2.7 V ≤ VCC ≤ 5.5 V
40
-
1.6 V ≤ VCC < 2.7 V
45
-
33.3
-
40
-
SCK clock rise and fall time
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
Data input setup
time
Master
Slave
Data input hold time
2.7 V ≤ VCC ≤ 5.5 V
Master
tH
Slave
tLEAD
1
-
tSPcyc
SS input hold time
tLAG
1
-
tSPcyc
tOD
-
40
ns
Data output hold
time
Master
1.8 V ≤ VCC ≤ 5.5 V
1.6 V ≤ VCC < 1.8 V
-
50
Slave
2.4 V ≤ VCC ≤ 5.5 V
-
65
1.8 V ≤ VCC < 2.4 V
-
100
1.6 V ≤ VCC < 1.8 V
-
125
-10
-
2.4 V ≤ VCC < 2.7 V
-20
-
1.8 V ≤ VCC < 2.4 V
-30
-
1.6 V ≤ VCC < 1.8 V
-40
-
-10
-
-
20
1.6 V ≤ VCC < 1.8 V
-
30
1.8 V ≤ VCC ≤ 5.5 V
-
20
1.6 V ≤ VCC < 1.8 V
-
30
Master
2.7 V ≤ VCC ≤ 5.5 V
tOH
Slave
Data rise and fall
time
Master
Slave
1.8 V ≤ VCC ≤ 5.5 V
tDr, tDf
Figure 2.45 to
Figure 2.48
ns
SS input setup time
Data output delay
Simple
SPI
ns
ns
ns
Slave access time
tSA
-
6
tPcyc
Slave output release time
tREL
-
6
tPcyc
Figure 2.48
Note 1. tPcyc: PCLKB cycle.
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RA2A1 Datasheet
2. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
SCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
SCKn
slave select input
VIL
(n = 0, 1, 9)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.44
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
MISOn
input
tH
MSB IN
DATA
tDr, tDf
MOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 2.45
SCI simple SPI mode timing (master, CKPH = 1)
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
MISOn
input
tH
MSB IN
tOH
MOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 2.46
SCI simple SPI mode timing (master, CKPH = 0)
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RA2A1 Datasheet
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
MISOn
output
tOD
MSB OUT
tSU
MOSIn
input
DATA
tREL
LSB OUT
tH
MSB IN
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0, 1, 9)
Figure 2.47
SCI simple SPI mode timing (slave, CKPH = 1)
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
tREL
LSB OUT
DATA
tH
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0, 1, 9)
Figure 2.48
Table 2.33
SCI simple SPI mode timing (slave, CKPH = 0)
SCI timing (3)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
Parameter
Simple IIC
(Standard mode)
Symbol
Min
Max
Unit
Test conditions
SDA input rise time
tSr
-
1000
ns
Figure 2.49
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc*1
ns
Data input setup time
tSDAS
250
-
ns
Data input hold time
tSDAH
0
-
ns
-
400
pF
SCL, SDA capacitive load
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Cb
*2
Page 60 of 100
RA2A1 Datasheet
Table 2.33
2. Electrical Characteristics
SCI timing (3)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
Parameter
Simple IIC
(Fast mode)
Symbol
Min
Max
Unit
Test conditions
SDA input rise time
tSr
-
300
ns
Figure 2.49
SDA input fall time
tSf
-
300
SDA input spike pulse removal time
tSP
0
4×
Data input setup time
tSDAS
100
-
ns
Data input hold time
tSDAH
0
-
ns
-
400
pF
SCL, SDA capacitive load
Note 1.
Note 2.
ns
tIICcyc*1
Cb
*2
ns
tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Cb indicates the total capacity of the bus line.
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
(n = 0, 1, 9)
P*1
S*1
P*1
Sr*1
tSDAH
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.49
SCI simple IIC mode timing
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Page 61 of 100
RA2A1 Datasheet
2.3.9
Table 2.34
2. Electrical Characteristics
SPI Timing
SPI timing (1 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Symbol
Min
Max
Unit*1
Test conditions
tSPcyc
2
4096
tPcyc
6
4096
Figure 2.50
C = 30 pF
(tSPcyc - tSPCKr
- tSPCKf) / 2 - 3
-
3 × tPcyc
-
(tSPcyc - tSPCKr
- tSPCKf) / 2 - 3
-
3 × tPcyc
-
-
10
-
15
1.8 V ≤ VCC ≤ 2.4 V
-
20
1.6 V ≤ VCC < 1.8 V
-
30
-
1
µs
10
-
ns
2.4 V ≤ VCC ≤ 5.5 V
10
-
1.8 V ≤ VCC < 2.4 V
15
-
Parameter
SPI RSPCK clock cycle
Master
Slave
RSPCK clock high
pulse width
Master
tSPCKWH
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
RSPCK clock rise
and fall time
Output
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
tSPCKr,
tSPCKf
Input
Data input setup
time
Master
Slave
tSU
1.6 V ≤ VCC < 1.8 V
Data input hold
time
SSL setup time
ns
20
-
tHF
0
-
Master
(RSPCK is not PCLKB/2)
tH
tPcyc
-
Slave
tH
20
-
tLEAD
-30 + N ×
tSpcyc*2
-
-50 + N ×
tSpcyc*2
-
6 × tPcyc
-
ns
-30 + N ×
tSpcyc*3
-
ns
Master
1.8 V ≤ VCC ≤ 5.5 V
Slave
Master
tLAG
Master
Slave
-
ns
14
ns
2.4 V ≤ VCC < 2.7 V
-
20
1.8 V ≤ VCC < 2.4 V
-
25
tOD
1.6 V ≤ VCC < 1.8 V
-
30
2.7 V ≤ VCC ≤ 5.5 V
-
50
2.4 V ≤ VCC < 2.7 V
-
60
1.8 V ≤ VCC < 2.4 V
-
85
1.6 V ≤ VCC < 1.8 V
Data output hold
time
Master
Successive
transmission delay
Master
tOH
Slave
Slave
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
ns
-
2.7 V ≤ VCC ≤ 5.5 V
tTD
-
110
0
-
0
-
tSPcyc + 2 ×
tPcyc
8 × tSPcyc +
2 × tPcyc
6 × tPcyc
-
Figure 2.51 to
Figure 2.56
C = 30 pF
ns
6 × tPcyc
Slave
Data output delay
ns
Master
(RSPCK is PCLKB/2)
1.6 V ≤ VCC < 1.8 V
SSL hold time
ns
ns
ns
Page 62 of 100
RA2A1 Datasheet
Table 2.34
2. Electrical Characteristics
SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Symbol
Min
Max
Unit*1
Test conditions
tDr, tDf
-
10
ns
2.4 V ≤ VCC < 2.7 V
-
15
1.8 V ≤ VCC < 2.4 V
-
20
Figure 2.51 to
Figure 2.56
C = 30 pF
1.6 V ≤ VCC < 1.8 V
-
30
-
1
µs
-
10
ns
-
15
1.8 V ≤ VCC < 2.4 V
-
20
1.6 V ≤ VCC < 1.8 V
-
30
-
1
µs
-
2 × tPcyc + 100
ns
-
2 × tPcyc + 140
Parameter
SPI MOSI and MISO
rise and fall time
Output
2.7 V ≤ VCC ≤ 5.5 V
Input
SSL rise and fall
time
Output
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
tSSLr,
tSSLf
Input
Slave access time
2.4 V ≤ VCC ≤ 5.5 V
tSA
1.8 V ≤ VCC < 2.4 V
1.6 V ≤ VCC < 1.8 V
Slave output release time
Note 1.
Note 2.
Note 3.
-
2 × tPcyc + 180
-
2 × tPcyc + 100
1.8 V ≤ VCC < 2.4 V
-
2 × tPcyc + 140
1.6 V ≤ VCC < 1.8 V
-
2 × tPcyc + 180
2.4 V ≤ VCC ≤ 5.5 V
tREL
Figure 2.55 and
Figure 2.56
C = 30 pF
ns
tPcyc: PCLKB cycle.
N is set as an integer from 1 to 8 by the SPCKD register.
N is set as an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKWH
RSPCKn
master select
output
VOH
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
RSPCKn
slave select input
(n = A or B)
Figure 2.50
VIH
VIL
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
SPI clock timing
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RA2A1 Datasheet
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
DATA
tDr, tDf
MOSIn
output
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.51
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
tHF
MISOn
input
MSB IN
tDr, tDf
MOSIn
output
tHF
tOH
MSB OUT
LSB IN
DATA
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.52
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
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RA2A1 Datasheet
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tOH
DATA
LSB IN
tOD
MOSIn
output
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.53
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
MSB IN
tOH
MOSIn
output
tH
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
(n = A or B)
Figure 2.54
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
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RA2A1 Datasheet
2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
MISOn
output
tOD
MSB OUT
tSU
MOSIn
input
tREL
DATA
LSB OUT
tH
MSB IN
MSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = A or B)
Figure 2.55
SPI timing (slave, CPHA = 0)
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
MISOn
output
tSA
tOH
tOD
LSB OUT
(Last data)
MSB OUT
tSU
MOSIn
input
tREL
tH
MSB IN
LSB OUT
DATA
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = A or B)
Figure 2.56
SPI timing (slave, CPHA = 1)
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RA2A1 Datasheet
2.3.10
2. Electrical Characteristics
IIC Timing
Table 2.35
IIC timing
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
Parameter
IIC
(Standard mode,
SMBus)
IIC
(Fast mode)
Note:
Note 1.
SCL input cycle time
Symbol
Min*1
Max
Unit
Test
conditions
tSCL
6 (12) × tIICcyc + 1300
-
ns
Figure 2.57
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
-
ns
SCL, SDA input rise time
tSr
-
1000
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(when wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
ns
SDA input bus free time
(when wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
-
ns
START condition input hold time
(when wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(when wakeup function is enabled)
tSTAH
1 (5) × tIICcyc + tPcyc +
300
-
ns
Repeated START condition input
setup time
tSTAS
1000
-
ns
STOP condition input setup time
tSTOS
1000
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
SCL input cycle time
tSCL
6 (12) × tIICcyc + 600
-
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
-
ns
SCL, SDA input rise time
tSr
-
300
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1 (5) × tIICcyc + tPcyc +
300
-
ns
Repeated START condition input
setup time
tSTAS
300
-
ns
STOP condition input setup time
tSTOS
300
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
Figure 2.57
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
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2. Electrical Characteristics
VIH
SDA0 and SDA1
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCL0 and SCL1
P*1
S*1
P*1
Sr*1
tSCLL
tSf
tSr
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.57
2.3.11
I2C bus interface input/output timing
CLKOUT Timing
Table 2.36
CLKOUT timing
Parameter
CLKOUT
CLKOUT pin output
cycle*1
CLKOUT pin high pulse
CLKOUT pin low pulse
width*2
width*2
CLKOUT pin output rise time
CLKOUT pin output fall time
Note 1.
Note 2.
2.7 V ≤ VCC ≤ 5.5 V
Symbol
Min
Max
Unit
Test conditions
tCcyc
ns
Figure 2.58
62.5
-
1.8 V ≤ VCC < 2.7 V
125
-
1.6 V ≤ VCC < 1.8 V
250
-
15
-
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
30
-
1.6 V ≤ VCC < 1.8 V
150
-
2.7 V ≤ VCC ≤ 5.5 V
tCH
15
-
1.8 V ≤ VCC < 2.7 V
30
-
1.6 V ≤ VCC < 1.8 V
150
-
2.7 V ≤ VCC ≤ 5.5 V
tCL
tCr
-
12
1.8 V ≤ VCC < 2.7 V
-
25
1.6 V ≤ VCC < 1.8 V
-
50
2.7 V ≤ VCC ≤ 5.5 V
tCf
-
12
1.8 V ≤ VCC < 2.7 V
-
25
1.6 V ≤ VCC < 1.8 V
-
50
ns
ns
ns
ns
When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and
the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, specifications in Table 2.36 should be satisfied with 45% to
55% of input duty cycle.
When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division
ratio to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
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RA2A1 Datasheet
2. Electrical Characteristics
tCcyc
tCH
tCf
CLKOUT
tCr
tCL
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 2.58
2.4
CLKOUT output timing
USB Characteristics
2.4.1
Table 2.37
USBFS Timing
USB characteristics
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C
Parameter
Input
characteristics
Output
characteristics
Symbol
Min
Max
Unit
Test conditions
Input high level voltage
VIH
2.0
-
V
-
Input low level voltage
VIL
-
0.8
V
-
Differential input sensitivity VDI
0.2
-
V
| USB_DP - USB_DM |
Differential common mode
range
VCM
0.8
2.5
V
-
Output high level voltage
VOH
2.8
VCC_USB
V
IOH = -200 μA
Output low level voltage
VOL
0.0
0.3
V
IOL = 2 mA
Cross-over voltage
VCRS
1.3
2.0
V
tr
4
20
ns
Figure 2.59,
Figure 2.60,
Figure 2.61
75
300
Rise time
FS
LS
Fall time
FS
tf
LS
Rise/fall time ratio
FS
tr/tf
LS
4
20
75
300
90
111.11
ns
%
80
125
Output resistance
ZDRV
28
44
Ω
(Adjusting the resistance
of external elements is not
required.)
VBUS
characteristics
VBUS input voltage
VIH
VCC × 0.8
-
V
-
VIL
-
VCC × 0.2
V
-
Pull-up,
pull-down
Pull-down resistor
RPD
14.25
24.80
kΩ
-
Pull-up resistor
RPUI
0.9
1.575
kΩ
During idle state
RPUA
1.425
3.09
kΩ
During reception
Battery charging
specification
version 1.2
D+ sink current
IDP_SINK
25
175
μA
-
D- sink current
IDM_SINK
25
175
μA
-
DCD source current
IDP_SRC
7
13
μA
-
Data detection voltage
VDAT_REF
0.25
0.4
V
-
D+ source voltage
VDP_SRC
0.5
0.7
V
Output current = 250 μA
D- source voltage
VDM_SRC
0.5
0.7
V
Output current = 250 μA
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Page 69 of 100
RA2A1 Datasheet
2. Electrical Characteristics
USB_DP,
USB_DM
90%
VCRS
90%
10%
10%
tr
Figure 2.59
tf
USB_DP and USB_DM output timing
Observation
point
USB_DP
50 pF
USB_DM
50 pF
Figure 2.60
Test circuit for Full-Speed (FS) connection
Observation
point
USB_DP
200 pF to
600 pF
3.6 V
1.5 K
USB_DM
200 pF to
600 pF Observation
point
Figure 2.61
2.4.2
Table 2.38
Test circuit for Low-Speed (LS) connection
USB External Supply
USB regulator
Parameter
VCC_USB supply current
Min
Typ
Max
Unit
Test conditions
3.8 V ≤ VCC_USB_LDO < 4.5 V
-
-
50
mA
-
4.5 V ≤ VCC_USB_LDO ≤ 5.5 V
-
-
100
mA
-
3.0
-
3.6
V
-
VCC_USB supply voltage
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RA2A1 Datasheet
2.5
2. Electrical Characteristics
ADC16 Characteristics
Table 2.39
16-bit A/D conversion, power supply, and input range conditions
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
High-potential reference voltage
1.5
3.3
AVCC0
V
-
Low-potential reference voltage
-
AVSS0
-
V
-
Analog input voltage range
0
-
VREFH0
V
-
Input common-mode
range
Acm
0
VREFH0/2
VREFH0
V
Differential analog input
Analog input
capacitance*2
Cs
-
-
4.3
pF
-
Analog input resistance*1
Rs
-
-
0.7
kΩ
High-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
-
-
1.5
High-precision channel
1.7 V ≤ AVCC0 < 2.7 V
-
-
2.5
Normal-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
-
-
3.8
Normal-precision channel
1.7 V ≤ AVCC0 < 2.7 V
Note 1.
Note 2.
These values are based on simulation. They are not production tested.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Figure 2.62 shows the equivalent circuit for analog input.
MCU
Analog input
ANn
Rs
ADC16
Vi
Cin
Figure 2.62
Table 2.40
Cs
Equivalent circuit for analog input
16-bit A/D conversion, timing parameters (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Frequency
ADCLK
1
-
32
MHz
3.0 V ≤ AVCC0 ≤ 5.5 V,
3.0 V ≤ VREFH0
1
-
24
2.7 V ≤ AVCC0 ≤ 5.5 V,
2.7 V ≤ VREFH0
1
-
16
2.4 ≤ AVCC0 ≤ 5.5 V,
1.5 V ≤ VREFH0
1
-
8
1.8 V ≤ AVCC0 ≤ 5.5 V,
1.5 V ≤ VREFH0
1
-
4
1.7 V ≤ AVCC0 ≤ 5.5 V,
1.5 V ≤ VREFH0
-
-
1 / (tSPL + 18 / ADCLK)
Conversion rate
R01DS0354EJ0110 Rev.1.10
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Fs
S/s
-
Page 71 of 100
RA2A1 Datasheet
Table 2.40
2. Electrical Characteristics
16-bit A/D conversion, timing parameters (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Sampling time*1
Permissible signal
source impedance
Max = 0.5 kΩ
Settling time*1
Note 1.
Symbol
Min
Typ
Max
Unit
Test conditions
tSPL
0.25
-
-
μs
High-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
3
-
-
High-precision channel
1.7 V ≤ AVCC0 < 2.7 V
3
-
-
Normal-precision channel
2.7 V ≤ AVCC0 ≤ 5.5 V
10
-
-
Normal-precision channel
1.7 V ≤ AVCC0 < 2.7 V
-
-
1
-
-
3.2
1.8 V ≤ AVCC0 < 2.7 V
-
-
8.9
1.7 V ≤ AVCC0 < 1.8 V
tSTART
μs
2.7 V ≤ AVCC0 ≤ 5.5 V
These values are based on simulation. They are not production tested.
Table 2.41
16-bit A/D conversion, linearity parameters
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used. Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Resolution
-
-
16
-
Bit
-
Integral non-linearity *1
INL
-
±4
±8
LSB
2.7 V ≤ AVCC0 ≤ 5.5 V, 2.7 V ≤ VREFH0
Differential non-linearity*1
DNL
-
-1 to +2
-
LSB
-
Offset error*1
Ofst
-
±4
-
LSB
-
Gerr
-
-
±0.1
%
2.7 V ≤ VREFH0
-
Gain
error*1
Note:
Note 1.
± 16
1.7 V ≤ AVCC0 < 2.7 V
The characteristics apply when no pin functions other than 16-bit A/D converter input are used. Offset error, full-scale error,
DNL differential non-linearity error, and INL integral non-linearity error do not include quantization errors.
These values are based on simulation. They are not production tested.
Table 2.42
16-bit A/D conversion, dynamic parameters (1) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used. Reference voltage range applied to VREFH0 and VREFL0.
Parameter
Signal-to-noise and
distortion*2
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Symbol
Min
Typ
Max
Unit
Test conditions
SINAD
67
81
-
dB
Differential input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
78
81
-
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
-
92
-
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V,
ADADC.ADC[2:0] = 101b
61
75
-
Single input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
72
75
-
Single input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
Page 72 of 100
RA2A1 Datasheet
Table 2.42
2. Electrical Characteristics
16-bit A/D conversion, dynamic parameters (1) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VREFH0 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used. Reference voltage range applied to VREFH0 and VREFL0.
Parameter
Effective number of
bits*2
Total harmonic distortion*1, *2
Common mode rejection ratio*2
Note:
Note 1.
Note 2.
Symbol
Min
Typ
Max
Unit
Test conditions
ENOB
11
13.2
-
bit
Differential input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
12.7
13.2
-
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
-
15
-
Differential input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V,
ADADC.ADC[2:0] = 101b
10
12.2
-
Single input, Fin = 1 kHz,
VREFH0 = 1.7 V to 5.5 V,
AVCC0 = 1.7 V to 5.5 V
11.7
12.2
-
Single input, Fin = 1 kHz,
VREFH0 = 3.3 V,
AVCC0 = 3.3 V
-
-100
-
-
-90
-
-
100
-
THD
CMRR
dB
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V
Single input, Fin = 1 kHz,
AVCC0 = 3.3 V
dB
Differential input,
Acm = 0 to VREFH0 at 1 kHz,
AVCC0 = 3.3 V
The characteristics apply when no pin functions other than 16-bit A/D converter input are used.
THD = HD2 + HD3 + HD4 + HD5.
These values are based on simulation. They are not production tested.
Table 2.43
16-bit A/D conversion, dynamic parameters (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
External clock input used.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Signal-to-noise and distortion*1
SINAD
-
78.6
-
dB
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.5 V
-
76.6
-
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.0 V
-
74.2
-
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 1.5 V
-
12.8
-
-
12.4
-
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.0 V
-
12.0
-
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 1.5 V
Effective number of bits*1
Note:
Note 1.
ENOB
bit
Differential input, Fin = 1 kHz,
AVCC0 = 3.3 V,
VREFADC output = 2.5 V
The characteristics apply when no pin functions other than 16-bit A/D converter input are used.
These values are based on simulation. They are not production tested.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 73 of 100
RA2A1 Datasheet
Table 2.44
2. Electrical Characteristics
16-bit A/D converter channel classification
Classification
Channel
Conditions
High-precision channel
AN000 to AN008
AVCC0 = 1.7 to 5.5 V
Normal-precision channel
AN016 to AN023
Internal reference voltage input channel
Internal reference voltage
AVCC0 = 2.0 to 5.5 V
Temperature sensor input channel
Temperature sensor output
AVCC0 = 2.0 to 5.5 V
Table 2.45
Internal reference voltage for 16-bit ADC (VREFADC) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL0 = 0 V
Parameter
Min
Typ
Max
Unit
Test conditions
Output voltage range
1.41
1.5
1.59
V
VREFAMPCNT.VREFADCG[1:0] = 00b
AVCC0 1.7 V
1.88
2
2.12
VREFAMPCNT.VREFADCG[1:0] = 10b
AVCC0 2.2 V
2.35
2.5
2.65
VREFAMPCNT.VREFADCG[1:0] = 11b
AVCC0 2.7 V
-
-
150
μs
VREFAMPCNT.BGREN = 1
-
-
1500
μs
VREFAMPCNT.VREFADCEN = 1
BGR stabilization time*2 (after BGR is enabled)
VREF AMP stabilization
enabled)
time*2
(after VREFAMP is
Detect over current*2
-
20
40
mA
-
Load capacitance*1
0.75
1
1.25
μF
-
Note 1.
Note 2.
Connect capacitors as stabilization capacitance between the VREFH0 and VREFL0 pins when VREFADC is used.
These values are based on simulation. They are not production tested.
Table 2.46
A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = AVCC1 = VREFH0 = 2.0 to 5.5 V*1
Parameter
Internal reference voltage input
Sampling
Note 1.
Note 2.
Note 3.
2.6
channel*2
time*3
Min
Typ
Max
Unit
Test conditions
1.36
1.43
1.50
V
-
5.0
-
-
μs
-
The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
The 16-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 16-bit A/D
converter.
This is a parameter for ADC16 when the internal reference voltage is selected for an analog input channel in ADC16.
SDADC24 Characteristics
Table 2.47
Analog inputs characteristics (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Full-scale range
FSR
-
± 0.8 /
GTOTAL
-
V
-
Differential
input voltage
range
VID
-0.8 / GTOTAL
-
0.8 / GTOTAL
V
VID = ANSDnP - ANSDnN, or
AMP0O - AMP1O
(n = 0 to 3), dOFR = 0 mV
Input voltage
range
VI
0.2
-
1.8
V
VI = ANSDnP, ANSDnN,
AMP0O, or AMP1O
(n = 0 to 3)
Common mode
Input voltage
range
VCOM
0.2 + (|VID|
GSET1) / 2
1.0
1.8 - (|VID|
GSET1) / 2
V
dOFR = 0 mV
Analog input in
differential input
mode
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 74 of 100
RA2A1 Datasheet
Table 2.47
2. Electrical Characteristics
Analog inputs characteristics (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Analog Input in
single-ended
input mode
Note 1.
Input voltage
range*1
Symbol
Min
Typ
Max
Unit
Test conditions
VI
0.2
-
1.8
V
VI = ANSDnP, ANSDnN,
AMP0O, or AMP1O
(n = 0 to 3),
VCOM = 1.0 V,
dOFR = 0 mV,
GSET1 = 1, GSET2 = 1,
OSR = 256
The single-ended input mode supports only dOFR = 0 mV, GSET1 = 1, GSET2 = 1 and OSR = 256.
Table 2.48
Programmable gain instrumentation amplifier and sigma-delta A/D converter (1)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Resolution
RES
-
24
-
bits
-
Fos
-
1
-
MHz
-
-
0.125
-
fDATA1
0.48828
-
15.625
ksps
Normal A/D conversion
mode
fDATA2
61.03615
-
1953.125
sps
Low-power A/D
conversion mode
GTOTAL
1
-
32
V/V
GTOTAL = GSET1 × GSET2
Over sampling
frequency
Normal A/D
conversion
mode
Low-power A/D
conversion
mode
Output data rate
Gain Setting range
1st Gain Setting range
GSET1
-
1, 2, 3, 4, 8
-
V/V
-
2nd Gain Setting range
GSET2
-
1, 2, 4, 8
-
V/V
-
Offset adjust bit range
dOFB
-
5
-
bits
-
Offset adjust range
dOFR
-164.06 / GSET1 -
+164.06 / GSET1
mV
Referred to input
Offset adjust step
dOFS
-
mV
Referred to input
Table 2.49
350 / 32 / GSET1 -
Programmable gain instrumentation amplifier and sigma-delta A/D converter (2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
The electrical specifications are applied at differential input mode, external clock input used, FOS = 1 MHz, dOFR = 0 mV,
unless otherwise specified.
Parameter
Signal to Noise
VID = 0 V
Ratio*1,*3
Signal to Noise and
Distortion Ratio*1, *2,*3
fin = 50 Hz
Note:
Note 1.
Note 2.
Note 3.
Symbol
Min
Typ
Max
Unit
Test conditions
SNR
83
86
-
dB
GSET1 = 1,
GSET2 = 1
OSR = 256
81
84
-
dB
GSET1 = 8,
GSET2 = 4
OSR = 1024
82
85
-
dB
GSET1 = 1,
GSET2 = 1
OSR = 256
79
82
-
dB
GSET1 = 8,
GSET2 = 4
OSR = 1024
74
80
-
dB
GSET1 = 1,
GSET2 = 1
OSR = 256,
Single-ended input mode
SINAD
The characteristics apply when no pin functions other than 24-bit sigma-delta A/D converter input are used.
SNR and SINAD are the ratio to Full-Scale Range (FSR) of analog inputs. These do not include the noise of analog inputs.
When VID is equal to ± 0.8 / GTOTAL actually, the digital output may overflow due to Gain Error (EG), Offset
Error (EOS), and so forth. As a result, SINAD is degraded. See Table 33.7 of 24-Bit Sigma-Delta A/D Converter (SDADC24) in
User’s Manual for the relation between analog input and digital output.
Not production tested but is guaranteed by the design and characterization.
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Page 75 of 100
RA2A1 Datasheet
2. Electrical Characteristics
SNR vs OSR
(Differential input mode, typical condition)
100
Signal to Noise Ratio (dB)
95
90
85
80
75
70
65
60
64
128
256
512
1024
2048
Oversampling Ratio (OSR)
GSET1 = 1, GSET2 = 1
Figure 2.63
GSET1 = 8, GSET2 = 4
SNR vs. OSR (reference data)
Signal to Noise and Distortion Ratio (dB)
SINAD vs OSR
(Differential input mode, typical condition)
95
90
85
80
75
70
65
60
64
128
256
512
1024
2048
Oversampling Ratio (OSR)
GSET1 = 1, GSET2 = 1
Figure 2.64
Table 2.50
GSET1 = 8, GSET2 = 4
SINAD vs. OSR (reference data)
Programmable gain instrumentation amplifier and sigma-delta A/D converter (3) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
The electrical specifications are applied at the differential input mode, with external clock input used, Fos = 1 MHz,
OSR = 256, and dOFR = 0 mV, unless otherwise specified.
Parameter
error*2
Gain
(excluding SINC3 frequency
response characteristic)
Symbol
Min
Typ
Max
Unit
Test conditions
EG
-0.5
-
0.5
%
After internal calibration,
excluding SBIAS error or VREFI
error,
GSET1 = 1, GSET2 = 1
-3
-
3
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Single-ended input mode,
excluding SBIAS error or
VREFI error,
GSET1 = 1, GSET2 = 1
Page 76 of 100
RA2A1 Datasheet
Table 2.50
2. Electrical Characteristics
Programmable gain instrumentation amplifier and sigma-delta A/D converter (3) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
The electrical specifications are applied at the differential input mode, with external clock input used, Fos = 1 MHz,
OSR = 256, and dOFR = 0 mV, unless otherwise specified.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Gain drift*1, *2
dEG
-
6
22
ppm/°C
Excluding SBIAS error or
VREFI error,
GSET1 = 1, GSET2 = 1
Offset error*2
EOS
-1
-
1
mV
After internal calibration,
GSET1 = 1, GSET2 = 1, referred to
input
-50
-
50
-
2
6
-
-
120
Offset drift*1, *2
dEOS
Single-ended input mode,
including SBIAS error,
GSET1 = 1, GSET2 = 1, referred to
input
μV/°C
Referred to input
Single-ended input mode,
including SBIAS error,
GSET1 = 1, GSET2 = 1
Integral non-linearity*2
INL
-
15
-
ppm
of FSR
Input = DC,
OSR = 2048
Common mode
Rejection ratio*2
CMRR
-
80
-
dB
VCOM = 1.0 ± 0.8 V,
fin = 50 Hz,
GSET1 = 1, GSET2 = 1
Power supply
Rejection ratio*2
PSRR
-
70
-
dB
AVCC1 = 5.0 V + 0.1 Vpp_ripple,
fin = 50 Hz,
GSET1 = 1, GSET2 = 1, excluding
SBIAS error or VREFI error
Input absolute current*2
IIN
-
2
-
nA
VI = 1 V
Input offset current*2
IINOFR
-
1
-
nA
VID = 0 V, VCOM = 1 V
ZIN
-
500
-
Mohm
VID = 1 V, VCOM = 1 V
dOFGE
-5
-
5
%
Including SBIAS error,
dOFR ≠ 0 mV
dOFINL
-0.5
-
0.5
LSB
dOFR ≠ 0 mV
Input
impedance*2
Offset adjust gain
error*2
Offset adjust
integral non-linearity*2
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 24-bit sigma-delta A/D converter input are used.
Gain drift is calculated by (Max (EG (T (-40°C) to T (125°C))) - Min (EG (T (-40°C) to T (125°C)))) / (125°C - (-40°C))
Offset drift is calculated by (Max (EOS (T (-40°C) to T (125°C))) - Min (EOS (T (-40°C) to T (125°C)))) / (125°C - (-40°C)).
Not production tested but is guaranteed by the design and characterization.
Table 2.51
2.1 V LDO linear regulator for ADC (ADREG) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Connect the ADREG pin to a AVSS1 pin by a 0.47 μF (-50% to +20%) capacitor.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
ADREG output voltage
VADREG
-
2.1
-
V
-
Table 2.52
ADC external reference voltage (VREFI) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External reference voltage range*1
VREFI
0.8
-
2.4
V
SDADCSTC1.VREFSEL = 1
External reference voltage step
VRSTEP
-
0.2
-
V
SDADCSTC1.VREFSEL = 1
External reference voltage accuracy
VRA
-3
-
3
%
SDADCSTC1.VREFSEL = 1
Note 1.
Select the reference voltage input value with STC1.VSBIAS[3:0].
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Page 77 of 100
RA2A1 Datasheet
Table 2.53
2. Electrical Characteristics
Sensor bias (SBIAS) characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Connect the SBIAS/VREFI pin to a AVSS1 pin by a 0.22 μF (-20% to +20%)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Output voltage range*2
SBIAS
0.8
-
2.2
V
-
Output voltage step
SVSTEP
-
0.2
-
V
-
Output voltage
accuracy*1
SVA
-3
-
3
%
SIOUT = 1 mA
Output current*1
SIOUT
-
-
10
mA
-
Short current*1
SISHORT
-
35
65
mA
SBIAS = 0 V
Load
regulation*1
SLR
-
-
15
mV
1 mA ≤ SIOUT ≤ 5 mA
-
-
20
mV
1 mA ≤ SIOUT ≤ 10 mA
Power supply rejection ratio*1
SPSRR
-
50
-
dB
AVCC1 = 5.0 V + 0.1 Vpp_ripple,
f = 100 Hz, SIOUT = 2.5 mA
Transition time of one step*1,*3
STTS
-
-
80
μs
SBIAS < SVA ± 3%
1 mA ≤ SIOUT ≤ SIOUT_MAX
Note 1.
Note 2.
Note 3.
Not production tested but is guaranteed by the design and characterization.
Select the reference voltage output value for the sensor with STC1.VSBIAS[3:0].
The load current of more than 1 mA is required because the output stage of SBIAS is Pch open drain. When the original load
current is small, additional external load resistance is required.
2.7
DAC12 Characteristics
Table 2.54
12-bit D/A conversion characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VREFH = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = VREFL = 0 V
Parameter
Min
Typ
Max
Unit
Test conditions
-
-
12
bit
-
-
-
100
μs
-
-
-
50
μs
-
DAC Ref. = AVCC or VREFH 2.7 V
-
-
1.0
μs
Cload = 38 pF, @ 1 LSB step
Cload = 8 pF, @ full range
DAC Ref. = AVCC or VREFH < 2.7 V
-
-
1.2
Resolution
Charge pump stabilization
time*1
SW stabilization time*1
Conversion
Wake-up
time*1
time*1
Absolute accuracy
DNL differential non-linearity
error
DAC Ref. = AVCC or VREFH 2.7 V
DAC Ref. = AVCC or VREFH < 2.7 V
-
-
-
1.0
μs
-
-
-
± 12
LSB
2-MΩ resistive load
-
-
±1.0
LSB
-
-
-
±2.0
INL integral non-linearity error
-
-
±7.0
LSB
-
RO output resistance
-
3.5
-
kΩ
-
Load resistance
Load capacitance
Note 1.
2.8
-
2
2
-
MΩ
-
1 LSB step
-
38
-
pF
-
Full range
-
8
-
-
These values are based on simulation. They are not production tested.
DAC8 Characteristics
Table 2.55
8-bit D/A conversion characteristics (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Resolution
Charge pump stabilization
time*1
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Min
Typ
Max
Unit
Test conditions
-
-
8
bit
-
-
-
100
μs
-
Page 78 of 100
RA2A1 Datasheet
Table 2.55
2. Electrical Characteristics
8-bit D/A conversion characteristics (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Min
Typ
Max
Unit
Test conditions
Switch stabilization time*1
-
-
50
μs
-
-
-
3.0
μs
35-pF capacitive load
Conversion time*1
AVCC0 = 2.7 to 5.5 V
AVCC0 = 1.7 to 2.7 V
-
-
6.0
μs
Absolute accuracy
AVCC0 = 2.7 to 5.5 V
-
-
± 3.0
LSB
2-MΩ resistive load
AVCC0 = 1.7 to 2.7 V
-
-
± 3.5
LSB
4-MΩ resistive load
kΩ
-
AVCC0 = 2.7 to 5.5 V
-
-
± 2.0
AVCC0 = 1.7 to 2.7 V
-
-
± 2.5
-
7.4
-
RO output resistance
Note 1.
2.9
These values are based on simulation. They are not production tested.
TSN Characteristics
Table 2.56
TSN characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.0 to 5.5 V
Parameter
Symbol
Relative accuracy
-
Min
Typ
Max
Unit
Test conditions
-
± 1.5
-
°C
2.4 V or above
-
± 2.0
-
°C
Below 2.4 V
-
-3.65
-
mV/°C
-
Temperature slope
-
Output voltage (at 25°C)
-
-
1.05
-
V
VCC = 3.3 V
Temperature sensor start time
tSTART
-
-
5
μs
-
Sampling time
-
5
-
-
μs
2.10
OSC Stop Detect Characteristics
Table 2.57
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Detection time
tdr
-
-
1
ms
Figure 2.65
Main clock
OSTDSR.OSTDF
tdr
MOCO clock
ICLK
Figure 2.65
Oscillation stop detection timing
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 79 of 100
RA2A1 Datasheet
2.11
2. Electrical Characteristics
POR and LVD Characteristics
Table 2.58
Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter
Voltage detection
level*1
Symbol
Min
Typ
Max
Unit
Test Conditions
Power-on reset (POR)
VPOR
1.27
1.42
1.57
V
Figure 2.66,
Figure 2.67
Voltage detection circuit (LVD0)*2
Vdet0_0
3.68
3.85
4.00
V
Vdet0_1
2.68
2.85
2.96
Figure 2.68
At falling edge
VCC
Vdet0_2
2.38
2.53
2.64
Vdet0_3
1.78
1.90
2.02
V
Figure 2.69
At falling edge
VCC
V
Figure 2.70
At falling edge
VCC
Voltage detection circuit (LVD1)*3
Voltage detection circuit
Note 1.
Note 2.
Note 3.
Note 4.
(LVD2)*4
Vdet0_4
1.60
1.69
1.82
Vdet1_0
4.13
4.29
4.45
Vdet1_1
3.98
4.16
4.30
Vdet1_2
3.86
4.03
4.18
Vdet1_3
3.68
3.86
4.00
Vdet1_4
2.98
3.10
3.22
Vdet1_5
2.89
3.00
3.11
Vdet1_6
2.79
2.90
3.01
Vdet1_7
2.68
2.79
2.90
Vdet1_8
2.58
2.68
2.78
Vdet1_9
2.48
2.58
2.68
Vdet1_A
2.38
2.48
2.58
Vdet1_B
2.10
2.20
2.30
Vdet1_C
1.84
1.96
2.05
Vdet1_D
1.74
1.86
1.95
Vdet1_E
1.63
1.75
1.84
Vdet1_F
1.60
1.65
1.73
Vdet2_0
4.11
4.31
4.48
Vdet2_1
3.97
4.17
4.34
Vdet2_2
3.83
4.03
4.20
Vdet2_3
3.64
3.84
4.01
These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage
detection.
# in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
# in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
# in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 80 of 100
RA2A1 Datasheet
Table 2.59
2. Electrical Characteristics
Power-on reset circuit and voltage detection circuit characteristics (2)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
LVD0: enable
tPOR
-
1.7
-
ms
-
LVD0: disable
tPOR
-
1.3
-
ms
-
LVD0: enable*1
tLVD0,1,2
-
0.6
-
ms
-
LVD0: disable*2
tLVD1,2
-
0.2
-
ms
-
Response delay*3
tdet
-
-
350
μs
Figure 2.66, Figure 2.67
Minimum VCC down time
tVOFF
450
-
-
μs
Figure 2.66,
VCC = 1.0 V or above
Power-on reset enable time
tW (POR)
1
-
-
ms
Figure 2.67,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is
enabled)
Td (E-A)
-
-
300
μs
Figure 2.69,
Figure 2.70
Hysteresis width (POR)
VPORH
-
110
-
mV
-
Hysteresis width (LVD0, LVD1 and LVD2)
VLVH
-
60
-
mV
-
100
-
Vdet1_0 to Vdet1_2 selected
-
60
-
Vdet1_3 to Vdet1_9 selected
-
50
-
Vdet1_A to Vdet1_B selected
-
40
-
Vdet1_C to Vdet1_F selected
-
60
-
LVD2 selected
Wait time after power-on
reset cancellation
Wait time after voltage
monitor 0,1,2 reset
cancellation
Note 1.
Note 2.
Note 3.
LVD0 selected
When OFS1.LVDAS = 0.
When OFS1.LVDAS = 1.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
Vdet0, Vdet1, and Vdet2 for the POR/LVD.
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
Figure 2.66
tdet
tPOR
Voltage detection reset timing
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 81 of 100
RA2A1 Datasheet
2. Electrical Characteristics
VPOR
VCC
1.0 V
tw(POR)
Internal reset signal
(active-low)
*1
tdet
tPOR
Note 1. tw(POR) is the time required for a power-on reset to be enabled while the external power VCC is
being held below the valid voltage (1.0 V).
When VCC turns on, maintain tw(POR) for 1.0 ms or more.
Figure 2.67
Power-on reset timing
tVOFF
VCC
VLVH
Vdet0
Internal reset signal
(active-low)
tdet
Figure 2.68
tdet
tLVD0
Voltage detection circuit timing (Vdet0)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 82 of 100
RA2A1 Datasheet
2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tdet
tLVD1
When LVD1CR0.RN = 1
tLVD1
Figure 2.69
Voltage detection circuit timing (Vdet1)
tVOFF
VCC
VLVH
Vdet2
LVCMPCR.LVD2E
LVD2
Comparator output
Td(E-A)
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.70
Voltage detection circuit timing (Vdet2)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 83 of 100
RA2A1 Datasheet
2.12
2. Electrical Characteristics
CTSU Characteristics
Table 2.60
CTSU characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
-
TS pin capacitive load
Cbase
-
-
50
pF
-
Permissible output high current
ΣIOH
-
-
-24
mA
When the mutual capacitance
method is applied and TS07 to TS14
are not used for transmit channel
-
-
-14
2.13
When the mutual capacitance
method is applied and TS07 to TS14
are used for transmit channel
Comparator Characteristics
Table 2.61
ACMPHS characteristics
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input offset voltage
VIOCMP
-
±5
± 40
mV
-
Input voltage range
VICPM
0
-
AVCC0
V
-
Internal reference voltage input*3
Vref
1.36
1.43
1.50
V
AVCC0 ≥ 2.0 V
Input signal cycle
tPCMP
10
-
-
μs
-
Output delay time
Td
-
50
100
ns
Input amplitude ± 100 mV
Stabilization wait time during input channel
switching*1
TWAIT
300
-
-
ns
Input amplitude ± 100 mV
Operation stabilization wait time*2
Tcmp
1
-
-
μs
3.3 V ≤ AVCC0 ≤ 5.5 V
3
-
-
μs
2.7 V ≤ AVCC0 3.3 V
Note 1.
Note 2.
Note 3.
Period from when the comparator input channel is switched until the switched result reflects in its output.
Period from when comparator operation is enabled (CPMCTL.HCMPON = 1) until the comparator satisfies the DC/AC
characteristics.
The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Table 2.62
ACMPLP characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Input voltage range
Symbol
IVREF0
Typ
Max
1.4*1
Unit
Test conditions
V
-
0
-
VCC -
IVREF1 (Standard mode)
0
-
VCC - 1.4
V
IVREF1 (Window mode)
1.4*1
-
VCC
V
IVCMP0, IVCMP1
VREF
Min
VI
0
-
VCC
V
Internal reference voltage*2
-
1.36
1.43
1.50
V
VCC ≥ 2.0 V
Output delay
Td
-
-
1.2
μs
Comparator high-speed mode
(Window mode)
-
-
2.0
μs
VCC = 3.0 V
Slew rate of input
signal > 50 mV/μs
Comparator low-speed mode
(Standard mode)
-
-
5.0
μs
Comparator high-speed mode
(Standard mode)
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 84 of 100
RA2A1 Datasheet
Table 2.62
2. Electrical Characteristics
ACMPLP characteristics
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Offset voltage
Symbol
Min
Typ
Max
Unit
Test conditions
-
-
-
50
mV
-
Comparator high-speed mode
(Window mode)
-
-
60
mV
Comparator low-speed mode
(Standard mode)
-
-
40
mV
100
-
-
μs
Comparator high-speed mode
(Standard mode)
Operation stabilization wait time
Note 1.
Note 2.
2.14
Tcmp
-
In window mode, be sure to satisfy the following condition: VIVREF1 - VIVREF0 0.2 V.
The internal reference voltage cannot be selected for input channels when VCC < 2.0 V.
OPAMP Characteristics
Table 2.63
OPAMP characteristics (1 of 3)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Symbol
Conditions
Supply voltage range
AVCC0
Charge pump stabilization
time*1
Min
Typ
Max
Unit
Low power mode
1.7
-
5.5
V
Middle-speed mode
2.1
-
5.5
V
High-speed mode
2.4
-
5.5
V
-
-
-
-
100
μs
SW stabilization time*1
-
-
-
-
50
μs
Input voltage range
Vicm1
Low power mode
AVSS0
-
AVCC0
V
Vicm2
Middle-speed mode
Vicm3
High-speed mode
Volh1
Low power mode,
Ilode = 100 μA
AVSS0
-
AVCC0
V
Volh2
Middle-speed mode,
Iload = 100 μA
Volh3
High-speed mode,
Iload = 100 μA
Voffadj2l
Middle-speed mode,
Vin = 0.1 V,
Tj = 25°C
-3
-
3
mV
Voffadj2h
Middle-speed mode,
Vin = AVCC0 - 0.1 V,
Tj = 25°C
Voffadj3l
High-speed mode,
Vin = 0.1 V,
Tj = 25°C
Voffadj3h
High-speed mode,
Vin = AVCC0 - 0.1 V,
Tj = 25°C
Output voltage range
Input offset trimming range*1
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 85 of 100
RA2A1 Datasheet
Table 2.63
2. Electrical Characteristics
OPAMP characteristics (2 of 3)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Input
offset*1
Offset drift*1
Open gain*1
Gain bandwidth
Phase
Gain
product*1
margin*1
margin*1
Input noise
density*1
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Symbol
Conditions
Min
Typ
Max
Unit
Vioff1a
Low power mode,
Vin < AVCC0 - 1.0 V
-5.0
-
5.0
mV
Vioff1b
Low power mode,
Vin ≥ AVCC0 - 1.0 V
-8.0
-
8.0
Vioff2a
Middle-speed mode,
Vin < AVCC0 - 1.2 V
-3.0
-
3.0
Vioff2b
Middle-speed mode,
Vin ≥ AVCC0 - 1.2 V
-3.0
-
3.0
Vioff3a
High-speed mode,
Vin < AVCC0 - 1.2 V
-2.5
-
2.5
Vioff3b
High-speed mode,
Vin ≥ AVCC0 - 1.2 V
-2.5
-
2.5
Drift1a
Low power mode,
Vin < AVCC0 - 1.0 V
-70
-
70
Drift1b
Low power mode,
Vin ≥ AVCC0 - 1.0 V
-70
-
70
Drift2a
Middle-speed mode,
Vin < AVCC0 - 1.2 V
-30
-
30
Drift2b
Middle-speed mode,
Vin ≥ AVCC0 - 1.2 V
-30
-
30
Drift3a
High-speed mode,
Vin < AVCC0 - 1.2 V
-30
-
30
Drift3b
High-speed mode,
Vin ≥ AVCC0 - 1.2 V
-30
-
30
Av1
Low power mode
70
130
-
Av2
Middle-speed mode
70
120
-
Av3
High-speed mode
60
130
-
GBW1
Low power mode
-
90
-
kHz
GBW2
Middle-speed mode
-
2
-
MHz
GBW3
High-speed mode
-
4.8
-
MHz
PM1
Low power mode
35
-
-
deg
PM2
Middle-speed mode
35
-
-
PM3
High-speed mode
35
-
-
GM1
Low power mode
10
-
-
GM2
Middle-speed mode
10
-
-
GM3
High-speed mode
10
-
-
Vind11
Low power mode,
f = 10 Hz
-
860
-
Vind12
Low power mode,
f = 1 kHz
-
260
-
Vind21
Middle-speed mode,
f = 1 kHz
-
50
-
Vind22
Middle-speed mode,
f = 100 kHz
-
30
-
Vind31
High-speed mode,
f = 1 kHz
-
40
-
Vind32
High-speed mode,
f = 100 kHz
-
20
-
μV/°C
dB
dB
nV/√Hz
Page 86 of 100
RA2A1 Datasheet
Table 2.63
2. Electrical Characteristics
OPAMP characteristics (3 of 3)
Conditions: VCC = AVCC0 = AVCC1 = 1.7 V to 5.5 V, VSS = AVSS0 = AVSS1 = 0 V
Parameter
Power supply rejection
ratio*1
Common mode rejection
Settling
Slew
ratio*1
time*1
rate*1
Symbol
Conditions
Min
Typ
Max
Unit
PSRR1
Low power mode
-
90
-
dB
PSRR2
Middle-speed mode
-
90
-
PSRR3
High-speed mode
-
90
-
CMRR1
Low power mode
-
90
-
CMRR2
Middle-speed mode
-
90
-
CMRR3
High-speed mode
-
90
-
Tset1
Low power mode
-
70
200
Tset2
Middle-speed mode
-
2.8
8
Tset3
High-speed mode
-
1.2
3.2
dB
μS
SR1
Low power mode
0.02
0.05
-
SR2
Middle-speed mode
0.8
1.3
-
SR3
High-speed mode
1.8
3.0
-
Tturn1
Low power mode,
AMPENx = 0 → 1,
IREFEN = 0 → 1
-
80
220
Tturn2
Middle-speed mode,
AMPENx = 0 → 1,
IREFEN = 0 → 1
-
3
10
Tturn3
High-speed mode,
AMPENx = 0 → 1,
IREFEN = 0 → 1
-
1.3
4
Vioffst2
Middle-speed mode,
Vin < AVCC0 - 1.2 V
0.3
0.459
0.58
Middle-speed mode,
Vin ≥ AVCC0 - 1.2 V
0.24
-
0.56
High-speed mode,
Vin < AVCC0 - 1.2 V
0.35
0.52
0.65
High-speed mode,
Vin ≥ AVCC0 - 1.2 V
0.28
-
0.61
Tturn_tm2
Middle-speed mode
-
-
1.5
Tturn_tm3
High-speed mode
-
-
1
Load current
IIoad
-
-
-
100
μA
Load capacitance
CL
-
-
-
20
pF
Turn on
time*1
Input offset trimming step*1
Vioffst3
Wait time after trimming*1
Note 1.
2.15
mV/code
μS
Flash Memory Characteristics
Code Flash Memory Characteristics
Table 2.64
Code flash characteristics (1)
Parameter
Reprogramming/erasure
Data hold time
Note 2.
Note 3.
μS
These values are based on simulation. They are not production tested.
2.15.1
Note 1.
V/μS
cycle*1
After 1000 times NPEC
Symbol
Min
Typ
Max
Unit
Conditions
NPEC
1000
-
-
Times
-
tDRP
20*2, *3
-
-
Year
Ta = +85°C
The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),
erasing can be performed n times for each block. For instance, when 4-byte programming is performed 256 times for different
addresses in 1-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled (overwriting is prohibited).
Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
This result is obtained from reliability testing.
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 87 of 100
RA2A1 Datasheet
Table 2.65
2. Electrical Characteristics
Code flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
FCLK = 1 MHz
Parameter
Symbol Min
Typ
FCLK = 32 MHz
Max
Min
Typ
Max
Unit
Programming time
8-byte
tP8
-
116
998
-
54
506
μs
Erasure time
2-KB
tE2K
-
9.03
287
-
5.67
222
ms
Blank check time
8-byte
tBC8
-
-
56.8
-
-
16.6
μs
2-KB
tBC2K
-
-
1899
-
-
140
μs
Erase suspended time
tSED
-
-
22.5
-
-
10.7
μs
Startup area switching setting time
tSAS
-
21.9
585
-
12.1
447
ms
Access window time
tAWS
-
21.9
585
-
12.1
447
ms
OCD/serial programmer ID setting time
tOSIS
-
21.9
585
-
12.1
447
ms
Flash memory mode transition wait time 1 tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait time 2 tMS
5
-
-
5
-
-
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Table 2.66
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, Ta = -40 to +85°C
FCLK = 1 MHz
Parameter
FCLK = 8 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Programming time
8-byte
tP8
-
157
1411
-
101
966
μs
Erasure time
2-KB
tE2K
-
9.10
289
-
6.10
228
ms
Blank check time
8-byte
tBC8
-
-
87.7
-
-
52.5
μs
2-KB
tBC2K
-
-
1930
-
-
414
μs
Erase suspended time
tSED
-
-
32.7
-
-
21.6
μs
Startup area switching setting time
tSAS
-
22.8
592
-
14.2
465
ms
Access window time
tAWS
-
22.8
592
-
14.2
465
ms
OCD/serial programmer ID setting time
tOSIS
-
22.8
592
-
14.2
465
ms
Flash memory mode transition wait time 1
tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait time 2
tMS
720
-
-
720
-
-
ns
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
2.15.2
Table 2.67
Data Flash Memory Characteristics
Data flash characteristics (1)
Parameter
Reprogramming/erasure
Data hold time
cycle*1
After 10000 times of NDPEC
After 100000 times of NDPEC
After 1000000 times of NDPEC
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Symbol
Min
Typ
Max
Unit
Conditions
NDPEC
100000
1000000
tDDRP
20*2, *3
-
-
Times
-
-
Year
5*2, *3
Ta = +85°C
-
-
Year
-
1*2, *3
-
Year
Ta = +25°C
Page 88 of 100
RA2A1 Datasheet
Note 1.
Note 2.
Note 3.
2. Electrical Characteristics
The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different
addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.)
Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
These results are obtained from reliability testing.
Table 2.68
Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 2.7 to 5.5 V
FCLK = 4 MHz
Parameter
Symbol
Min
Typ
FCLK = 32 MHz
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
-
52.4
463
-
42.1
387
μs
Erasure time
1-KB
tDE1K
-
8.98
286
-
6.42
237
ms
Blank check time
1-byte
tDBC1
-
-
24.3
-
-
16.6
μs
tDBC1K
-
-
1872
-
-
512
μs
Suspended time during erasing
1-KB
tDSED
-
-
13.0
-
-
10.7
μs
Data flash STOP recovery time
tDSTOP
5
-
-
5
-
-
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
Table 2.69
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = AVCC1 = 1.8 to 5.5 V, Ta = -40 to +85°C
FCLK = 4 MHz
Parameter
Symbol
Min
Typ
FCLK = 8 MHz
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
-
94.7
886
-
89.3
849
μs
Erasure time
1-KB
tDE1K
-
9.59
299
-
8.29
273
ms
Blank check time
1-byte
tDBC1
-
-
56.2
-
-
52.5
μs
tDBC1K
-
-
2.17
-
-
1.51
ms
Suspended time during erasing
1-KB
tDSED
-
-
23.0
-
-
21.7
μs
Data flash STOP recovery time
tDSTOP
720
-
-
720
-
-
ns
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ± 3.5% during programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
2.15.3
Table 2.70
Serial Wire Debug (SWD)
SWD characteristics (1) (1 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
80
-
-
ns
Figure 2.71
SWCLK clock high pulse width
tSWCKH
35
-
-
ns
SWCLK clock low pulse width
tSWCKL
35
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 89 of 100
RA2A1 Datasheet
Table 2.70
2. Electrical Characteristics
SWD characteristics (1) (2 of 2)
Conditions: VCC = AVCC0 = AVCC1 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWDIO setup time
tSWDS
16
-
-
ns
Figure 2.72
SWDIO hold time
tSWDH
16
-
-
ns
SWDIO data delay time
tSWDD
2
-
70
ns
Table 2.71
SWD characteristics (2)
Conditions: VCC = AVCC0 = AVCC1 = 1.6 to 2.4 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
250
-
-
ns
Figure 2.71
SWCLK clock high pulse width
tSWCKH
120
-
-
ns
SWCLK clock low pulse width
tSWCKL
120
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
SWDIO setup time
tSWDS
50
-
-
ns
SWDIO hold time
tSWDH
50
-
-
ns
SWDIO data delay time
tSWDD
2
-
150
ns
Figure 2.72
tSWCKcyc
tSWCKH
tSWCKf
SWCLK
tSWCKL
Figure 2.71
tSWCKr
SWD SWCLK timing
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 2.72
SWD input/output timing
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 90 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
T
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 1.1
LQFP 64-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 91 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
*2
E
HE
b1
Reference
Symbol
32
9
1
ZE
Terminal cross section
8
ZD
c
A
F
A2
Index mark
A1
S
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y S
e
Figure 1.2
*3
Detail F
bp
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
LQFP 32-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 92 of 100
RA2A1 Datasheet
JEITA Package Code
P-LFBGA36-5x5-0.80
Appendix 1. Package Dimensions
RENESAS Code
PLBG0036GA-A
Previous Code
36FHE
MASS[Typ.]
0.1g
w S B
b
D
w S A
S
ZD
A
AB
e
A1
A
e
F
E
B
E
D
C
1
x4
v
2
3
4
5
6
Reference
Symbol
Index mark
(Laser mark)
Figure 1.3
A
ZE
y S
B
Index mark
S
D
E
v
w
A
A1
e
b
x
y
ZD
ZE
Dimension in Millimeters
Min Nom Max
5.0
5.0
0.15
0.20
1.4
0.3 0.35 0.4
0.8
0.4 0.45 0.5
0.08
0.10
0.5
0.5
BGA 36-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 93 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN48-7x7-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0048KB-A
48PJN-A
P48K8-50-5B4-6
0.13
D
25
36
DETAIL OF A PART
24
37
E
A
A1
13
48
c2
12
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
12
1
13
48
Dimension in Millimeters
Min
Nom
Max
D
6.95
7.00
7.05
E
6.95
7.00
7.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
0.30
24
36
25
ZD
e
b
x
M
0.40
0.50
x
0.05
y
0.05
0.75
ZE
37
0.30
0.50
ZD
ZE
0.25
c2
0.75
0.15
0.20
D2
5.50
E2
5.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Figure 1.4
QFN 48-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 94 of 100
RA2A1 Datasheet
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN40-6x6-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0040KC-A
P40K8-50-4B4-5
0.09
D
21
30
DETAIL OF A PART
20
31
E
40
A
A1
11
c2
10
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
1
10
11
40
Dimension in Millimeters
Min
Nom
Max
D
5.95
6.00
6.05
E
5.95
6.00
6.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
ZE
20
31
30
21
ZD
e
b
Figure 1.5
x
M
0.25
0.30
0.50
0.30
0.40
0.50
x
0.05
y
0.05
ZD
0.75
ZE
0.75
c2
0.15
0.20
D2
4.50
E2
4.50
0.25
S AB
QFN 40-pin
R01DS0354EJ0110 Rev.1.10
Mar 16, 2020
Page 95 of 100
Revision History
Rev.
Date
1.00
Oct 8, 2019
1.10
Mar 16, 2020
RA2A1 Group Datasheet
Summary
First release
Updated for 1.10
Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in
this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
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part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,
transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior
written consent from Renesas.
Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective
holders.
Colophon
RA2A1 Microcontroller Group Datasheet
Publication Date:
Rev.1.10
Mar 16, 2020
Published by:
Renesas Electronics Corporation
Address List
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.
This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit
boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished
product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time
when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset
by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches
the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in
the device at this time may cause degradation of internal elements. Follow the guideline for input signal during poweroff state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins
of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,
extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,
and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated
with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full
stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or
by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to
prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the
input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,
immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a
system-evaluation test for the given product.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
you or third parties arising from such alteration, modification, copying or reverse engineering.
5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
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Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
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liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
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reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
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7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
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