Datasheet
32
Cover
Renesas RA4M1 Group
Datasheet
32-bit MCU
Renesas Advanced (RA) Family
Renesas RA4 Series
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.00
Oct 2019
RA4M1 Group
Datasheet
High efficiency 48-MHz Arm® Cortex®-M4 core, 256-KB code flash memory, 32-KB SRAM, Segment LCD Controller,
Capacitive Touch Sensing Unit, USB 2.0 Full-Speed Module, 14-bit A/D Converter, 12-bit D/A Converter, security and
safety features
Features
■ Arm Cortex-M4 Core with Floating Point Unit (FPU)
Armv7E-M architecture with DSP instruction set
Maximum operating frequency: 48 MHz
Support for 4-GB address space
Arm Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: ITM, DWT, FPB, TPIU, ETB
CoreSight™ Debug Port: JTAG-DP and SW-DP
■ Memory
256-KB code flash memory
8-KB data flash memory (100,000 program/erase (P/E) cycles)
32-KB SRAM
Flash Cache (FCACHE)
Memory Protection Unit (MPU)
128-bit unique ID
■ Connectivity
USB 2.0 Full-Speed Module (USBFS)
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 4
- UART
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
Controller Area Network (CAN) module
Serial Sound Interface Enhanced (SSIE)
■ Analog
14-bit A/D Converter (ADC14)
12-bit D/A Converter (DAC12)
8-bit D/A Converter (DAC8) ×2 (for ACMPLP)
Low-Power Analog Comparator (ACMPLP) × 2
Operational Amplifier (OPAMP) × 4
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-Bit (GPT32) × 2
General PWM Timer 16-Bit (GPT16) × 6
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
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■ System and Power Management
Low power modes
Realtime Clock (RTC) with calendar and Battery Backup support
Event Link Controller (ELC)
DMA Controller (DMAC) × 4
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Security and Encryption
AES128/256
GHASH
True Random Number Generator (TRNG)
■ Human Machine Interface (HMI)
Segment LCD Controller (SLCDC)
- Up to 38 segments × 4 commons
- Up to 34 segments × 8 commons
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 2.4 V)
(1 to 4 MHz when VCC = 1.6 to 1.8 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General Purpose I/O Ports
Up to 84 input/output pins
- Up to 3 CMOS input
- Up to 81 CMOS input/output
- Up to 9 input/output 5-V tolerant
- Up to 2 high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = -40°C to +85°C
- 100-pin LGA (7 mm × 7 mm, 0.65 mm pitch)
Ta = -40°C to +105°C
- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)
- 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)
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RA4M1 Group
1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU provides an optimal combination of low-power, high-performance Arm Cortex®-M4 core running up to
48 MHz with the following features:
256-KB code flash memory
32-KB SRAM
Segment LCD Controller (SLCDC)
Capacitive Touch Sensing Unit (CTSU)
USB 2.0 Full-Speed Module (USBFS)
14-bit A/D Converter (ADC14)
12-bit D/A Converter (DAC12)
Security features.
1.1
Table 1.1
Function Outline
Arm core
Feature
Functional description
Arm Cortex-M4 core
Maximum operating frequency: up to 48 MHz
Arm Cortex-M4 core
- Revision: r0p1-01rel0
- Armv7E-M architecture profile
- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.
Arm Memory Protection Unit (Arm MPU)
- Armv7 Protected Memory System Architecture
- 8 protected regions.
SysTick timer
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
Maximum 256-KB code flash memory. See section 44, Flash Memory in User’s Manual.
Data flash memory
8-KB data flash memory. See section 44, Flash Memory in User’s Manual.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset. See section 6,
Option-Setting Memory in User’s Manual.
SRAM
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). An area in
SRAM0 provides error correction capability using ECC. See section 43, SRAM in User’s
Manual.
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RA4M1 Group
Table 1.3
1. Overview
System (1 of 2)
Feature
Functional description
Operating modes
Two operating modes:
Single-chip mode
SCI/USB boot mode.
See section 3, Operating Modes in User’s Manual.
Resets
14 resets:
RES pin reset
Power-on reset
VBATT-selected voltage power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
CPU stack pointer error reset
Software reset.
See section 5, Resets in User’s Manual.
Low Voltage Detection (LVD)
Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and the
detection level can be selected using a software program. See section 7, Low Voltage
Detection (LVD) in User’s Manual.
Clocks
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
PLL frequency synthesizer
IWDT-dedicated on-chip oscillator
Clock out support.
See section 8, Clock Generation Circuit in User’s Manual.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated.
See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 13, Interrupt
Controller Unit (ICU) in User’s Manual.
Key Interrupt Function (KINT)
A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 20, Key Interrupt Function
(KINT) in User’s Manual.
Low power modes
Power consumption can be reduced in multiple ways, such as by setting clock dividers,
stopping modules, selecting power control mode in normal operation, and transitioning to low
power modes. See section 10, Low Power Modes in User’s Manual.
Battery backup function
A battery backup function is provided for partial powering by a battery. The battery powered
area includes RTC, SOSC, LOCO, wakeup control, backup memory, VBATT_R low voltage
detection, and switches between VCC and VBATT.
During normal operation, the battery powered area is powered by the main power supply,
which is the VCC pin. When a VCC voltage drop is detected, the power source is switched to
the dedicated battery backup power pin, the VBATT pin.
When the voltage rises again, the power source is switched from the VBATT pin to the VCC
pin. See section 11, Battery Backup Function in User’s Manual.
Register write protection
The register write protection function protects important registers from being overwritten
because of software errors. See section 12, Register Write Protection in User’s Manual.
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RA4M1 Group
Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Memory Protection Unit (MPU)
Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 25, Watchdog Timer (WDT) in User’s
Manual.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. It can be used to reset the MCU or to
generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates
with an independent, dedicated clock source, it is particularly useful in returning the MCU to a
known state as a fail-safe mechanism when the system runs out of control. The IWDT can be
triggered automatically on a reset, underflow, refresh error, or by a refresh of the count value in
the registers. See section 26, Independent Watchdog Timer (IWDT) in User’s Manual.
Table 1.4
Event link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 18, Event Link Controller (ELC) in
User’s Manual.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 17, Data Transfer Controller (DTC) in User’s Manual.
DMA Controller (DMAC)
A 4-channel DMA Controller (DMAC) module is provided for transferring data without the CPU.
When a DMA transfer request is generated, the DMAC transfers data stored at the transfer
source address to the transfer destination address. See section 16, DMA Controller (DMAC) in
User’s Manual.
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RA4M1 Group
Table 1.6
1. Overview
Timers
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with 2 channels and a 16-bit timer with 6
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms can be generated for controlling
brushless DC motors. The GPT can also be used as a general-purpose timer. See section 22,
General PWM Timer (GPT) in User’s Manual.
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 21, Port Output Enable for GPT (POEG).
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting of external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 23, Asynchronous General Purpose Timer (AGT) in User’s Manual.
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 24, Realtime Clock (RTC) in User’s Manual.
Table 1.7
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface
(SCI)
The Serial Communications Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and
the data transfer speed can be configured independently using an on-chip baud rate generator.
See section 28, Serial Communications Interface (SCI) in User’s Manual.
I2C Bus Interface (IIC)
The 3-channel I2C Bus Interface (IIC) module conforms with and provides a subset of the NXP
I2C bus (Inter-Integrated Circuit bus) interface functions. See section 29, I2C Bus Interface
(IIC) in User’s Manual.
Serial Peripheral Interface (SPI)
Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices.
See section 31, Serial Peripheral Interface (SPI) in User’s Manual.
Serial Sound Interface Enhanced
(SSIE)
The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The
SSIE supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or
master receiver, transmitter, or transceiver to suit various applications. The SSIE includes 8stage FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven
data reception and transmission. See section 33, Serial Sound Interface Enhanced (SSIE) in
User’s Manual.
Controller Area Network (CAN)
module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 30, Controller Area Network (CAN) Module in User’s Manual.
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RA4M1 Group
Table 1.7
1. Overview
Communication interfaces (2 of 2)
Feature
Functional description
USB 2.0 Full-Speed Module (USBFS)
The USB 2.0 Full-Speed Module (USBFS) can operate as a host controller or device controller.
The module supports full-speed and low-speed (only for the host controller) transfer as defined
in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB
has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be
assigned any endpoint number based on the peripheral devices used for communication or
based on the user system. The MCU supports revision 1.2 of the Battery Charging
specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the
internal USB transceiver power supply at 3.3 V. See section 27, USB 2.0 Full-Speed Module
(USBFS) in User’s Manual.
Table 1.8
Analog
Feature
Functional description
14-bit A/D Converter (ADC14)
A 14-bit successive approximation A/D converter is provided. Up to 25 analog input channels
are selectable. Temperature sensor output and internal reference voltage are selectable for
conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion
making it possible to optimize the tradeoff between speed and resolution in generating a digital
value. See section 35, 14-Bit A/D Converter (ADC14) in User’s Manual.
12-Bit D/A Converter (DAC12)
The 12-Bit D/A Converter (DAC12) converts data and includes an output amplifier. See section
36, 12-Bit D/A Converter (DAC12) in User’s Manual.
8-Bit D/A Converter (DAC8)
for ACMPLP
The 8-Bit D/A Converter (DAC8) converts data and does not include an output amplifier
(DAC8). The DAC8 is used only as the reference voltage for ACMPLP. See section 40, 8-Bit D/
A Converter (DAC8) in User’s Manual.
Temperature Sensor (TSN)
The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC14 for conversion and can be further used by the end
application. See section 37, Temperature Sensor (TSN) in User’s Manual.
Low-Power Analog Comparator
(ACMPLP)
The Low-Power Analog Comparator (ACMPLP) compares the reference input voltage and
analog input voltage. The comparison result can be read through software and also be output
externally. The reference voltage can be selected from an input to the CMPREFi(i = 0,1) pin,
an internal 8-bit D/A converter output, or the internal reference voltage (Vref) generated
internally in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting the high-speed
mode decreases the response delay time, but increases current consumption. Setting the lowspeed mode increases the response delay time, but decreases current consumption. See
section 39, Low-Power Analog Comparator (ACMPLP) in User’s Manual.
Operational Amplifier (OPAMP)
The Operational Amplifier (OPAMP) amplifies small analog input voltages and outputs the
amplified voltages. A total of four differential operational amplifier units with two input pins and
one output pin are provided. See section 38, Operational Amplifier (OPAMP) in User’s Manual.
Table 1.9
Human machine interfaces
Feature
Functional description
Segment LCD Controller (SLCDC)
The Segment LCD Controller (SLCDC) provides the following functions:
Waveform A or B selectable
The LCD driver voltage generator can switch between an internal voltage boosting method,
a capacitor split method, and an external resistance division method
Automatic output of segment and common signals based on automatic display data register
read
The reference voltage generated when operating the voltage boost circuit can be selected in
16 steps (contrast adjustment)
The LCD can be made to blink.
See section 45, Segment LCD Controller (SLCDC) in User’s Manual.
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed within an electrical insulator so that fingers do
not come into direct contact with the electrode. See section 41, Capacitive Touch Sensing Unit
(CTSU) in User’s Manual.
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RA4M1 Group
Table 1.10
1. Overview
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC generation polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 32, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 42,
Data Operation Circuit (DOC) in User’s Manual.
Table 1.11
Security
Feature
Functional description
Secure Crypto Engine 5 (SCE5)
Security algorithm
- Symmetric algorithm: AES.
Other support features
- TRNG (True Random Number Generator)
- Hash-value generation: GHASH.
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RA4M1 Group
1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the
features.
Memory
Bus
256 KB Code Flash
MPU
Arm Cortex-M4
DSP
System
FPU
POR/LVD
Clocks
MOSC/SOSC
8 KB Data Flash
MPU
Reset
NVIC
Mode Control
32 KB SRAM
(HOCO/
MOCO/
LOCO)
PLL
System Timer
Power Control
DMA
CAC
DTC
Test and DBG Interface
DMAC × 4
KINT
Timers
Communication interfaces
GPT32 × 2
SCI × 4
GPT16 × 6
IIC × 2
AGT × 2
SPI × 2
RTC
WDT/IWDT
ICU
Battery Backup
Register Write
Protection
Human machine interfaces
CAN × 1
CTSU
SLCDC
USBFS
with Battery
Charging
revision 1.2
SSIE × 1
Event Link
Data processing
Analog
ELC
CRC
ADC14
TSN
OPAMP × 4
Security
DOC
DAC12
DAC8
ACMPLP × 2
SCE5
Figure 1.1
Block diagram
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RA4M1 Group
1.3
1. Overview
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity, and package type. Table 1.12 shows
a product list.
R7FA4M1AB3C FP #AA 0
Production identification code
Packaging, Terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FP: LQFP 100 pins
FM: LQFP 64 pins
FL: LQFP 48 pins
LJ: LGA 100 pins
NB: QFN 64 pins
NE: QFN 48 pins
NF: QFN 40 pins
Quality Grade
Operating temperature
2: -40°C to 85°C
3: -40°C to 105°C
Code flash memory size
B: 256 KB
Feature set
Group number
Series name
RA family
Flash memory
Renesas microcontroller
Figure 1.2
Table 1.12
Part numbering scheme
Product list
Product part number
Orderable part number
Package code
Code flash
Data flash
SRAM
Operating
temperature
R7FA4M1AB3CFP
R7FA4M1AB3CFP#AA0
PLQP0100KB-B
256 KB
8 KB
32 KB
-40 to +105°C
R7FA4M1AB2CLJ
R7FA4M1AB2CLJ#AC0
PTLG0100JA-A
-40 to +85°C
R7FA4M1AB3CFM
R7FA4M1AB3CFM#AA0
PLQP0064KB-C
-40 to +105°C
R7FA4M1AB3CNB
R7FA4M1AB3CNB#AC0
PWQN0064LA-A
-40 to +105°C
R7FA4M1AB3CFL
R7FA4M1AB3CFL#AA0
PLQP0048KB-B
-40 to +105°C
R7FA4M1AB3CNE
R7FA4M1AB3CNE#AC0
PWQN0048KB-A
-40 to +105°C
R7FA4M1AB3CNF
R7FA4M1AB3CNF#AC0
PWQN0040KC-A
-40 to +105°C
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RA4M1 Group
1.4
1. Overview
Function Comparison
Table 1.13
Function comparison
Part numbers
R7FA4M1AB3CFP
R7FA4M1AB3CFM/
R7FA4M1AB3CNB
R7FA4M1AB2CLJ
R7FA4M1AB3CFL/
R7FA4M1AB3CNE
R7FA4M1AB3CNF
Pin count
100
100
64
48
40
Package
LQFP
LGA
LQFP/QFN
LQFP/QFN
QFN
5
3
256 KB
Code flash memory
8 KB
Data flash memory
32 KB
SRAM
16 KB
Parity
16 KB
ECC
System
48 MHz
CPU clock
512 bytes
Backup
registers
Yes
ICU
8
KINT
Event control
ELC
Yes
DMA
DTC
Yes
4
DMAC
Bus
External bus
Timers
GPT32
Communication
No
2
GPT16
6
AGT
2
4
RTC
Yes
WDT/IWDT
Yes
4
SCI
2
IIC
2
SPI
No
QSPI
No
SDHI
No
1
CAN
Yes
USBFS
25
ADC14
18
1
No
2
ACMPLP
4
OPAMP
4
1
3
Yes
TSN
4 com × 38 seg or 8 com × 34 seg
CTSU
Data
processing
11
2
DAC8
SLCDC
14
1
DAC12
HMI
1
1
SSIE
Analog
2
No
CRC
DOC
Security
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27
4 com × 21 seg or
8 com × 17 seg
24
No
15
10
Yes
Yes
SCE5
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RA4M1 Group
1.5
1. Overview
Pin Functions
Table 1.14
Pin functions (1 of 4)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect this pin to the system power supply. Connect it to
VSS through a 0.1-μF capacitor. The capacitor should be placed close to the
pin.
VCL
I/O
Connect this pin to the VSS pin through the smoothing capacitor used to
stabilize the internal power supply. Place the capacitor close to the pin.
VSS
Input
Ground pin. Connect to the system power supply (0 V).
VBATT
Input
Backup power supply pin
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input through the
EXTAL pin.
XCIN
Input
XCOUT
Output
Clock
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
CLKOUT
Output
Clock output pin
Operating mode
control
MD
Input
Pins for setting the operating mode. The signal levels on these pins must not
be changed during operation mode transition on release from the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal goes
low.
CAC
CACREF
Input
Measurement reference clock input pin
Interrupt
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ12,
IRQ14, IRQ15
Input
Maskable interrupt request pins
KINT
KR00 to KR07
Input
Key interrupt input pins.
A key interrupt (KINT) can be generated by inputting a falling edge to the key
interrupt input pins.
On-chip debug
TMS
I/O
On-chip emulator or boundary scan pins
TDI
Input
TCK
Input
TDO
Output
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
SWO
Output
Serial wire trace output pin
Battery Backup
VBATWIO0 to
VBATWIO2
I/O
Output wakeup signal for the VBATT wakeup control function.
External event input for the VBATT wakeup control function.
GPT
GTETRGA,
GTETRGB
Input
External trigger input pin
GTIOC0A to
GTIOC7A,
GTIOC0B to
GTIOC7B
I/O
Input capture, output capture, or PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 12 of 130
RA4M1 Group
Table 1.14
1. Overview
Pin functions (2 of 4)
Function
Signal
I/O
Description
AGT
AGTEE0, AGTEE1
Input
External event input enable signals
AGTIO0, AGTIO1
I/O
External event input and pulse output pins
AGTO0, AGTO1
Output
Pulse output pins
AGTOA0, AGTOA1
Output
Output compare match A output pins
RTC
SCI
IIC
SSIE
SPI
CAN
AGTOB0, AGTOB1
Output
Output compare match B output pins
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
RTCIC0 to RTCIC2
Input
Time capture event input pins
SCK0 to SCK2,
SCK9
I/O
Clock (clock synchronous mode) input/output pins
RXD0 to RXD2,
RXD9
Input
Received data (asynchronous mode/clock synchronous mode) input pins
TXD0 to TXD2,
TXD9
Output
Transmitted data (asynchronous mode/clock synchronous mode) output pins
CTS0_RTS0 to
CTS2_RTS2,
CTS9_RTS9
I/O
Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low
SCL0 to SCL2,
SCL9
I/O
I2C clock (simple IIC) input/output pins
SDA0 to SDA2,
SDA9
I/O
I2C data (simple IIC) input/output pins
SCK0 to SCK2,
SCK9
I/O
Clock (simple SPI) input/output pins
MISO0 to MISO2,
MISO9
I/O
Slave transmission of data (simple SPI) input/output pins
MOSI0 to MOSI2,
MOSI9
I/O
Master transmission of data (simple SPI) input/output pins
SS0 to SS2, SS9
Input
Slave-select input pins (simple SPI), active-low
SCL0, SCL1
I/O
Clock input/output pins
SDA0, SDA1
I/O
Data input/output pins
SSIBCK0
I/O
SSIE serial bit clock pin
SSILRCK0/SSIFS0
I/O
Word select pins
SSITXD0
Output
Serial data output pin
SSIRXD0
Input
Serial data input pin
AUDIO_CLK
Input
External clock pin for audio (input oversampling clock)
RSPCKA, RSPCKB
I/O
Clock input/output pin
MOSIA, MOSIB
I/O
Input/output pins for data output from the master
MISOA, MISOB
I/O
Input/output pins for data output from the slave
SSLA0, SSLB0
I/O
Input/output pins for slave selection
SSLA1, SSLA2,
SSLA3, SSLB1,
SSLB2, SSLB3
Output
Output pins for slave selection
CRX0
Input
Receive data
CTX0
Output
Transmit data
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 13 of 130
RA4M1 Group
Table 1.14
1. Overview
Pin functions (3 of 4)
Function
Signal
I/O
Description
USBFS
VSS_USB
Input
Ground pin
VCC_USB_LDO
Input
Power supply pin for USB LDO regulator
VCC_USB
I/O
Input: USB transceiver power supply pin.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. This pin should be connected to the
D+ pin of the USB bus.
USB_DM
I/O
D- I/O pin of the USB on-chip transceiver. This pin should be connected to the
D- pin of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. This pin should be connected to VBUS of
the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a device controller.
USB_EXICEN
Output
Low power control signal for external power supply (OTG) chip
Analog power
supply
USB_VBUSEN
Output
VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA,
USB_OVRCURB
Input
Connect the external overcurrent detection signals to these pins. Connect the
VBUS comparator signals to these pins when the OTG power supply chip is
connected.
USB_ID
Input
Connect the MicroAB connector ID input signal to this pin during operation in
OTG mode
AVCC0
Input
Analog voltage supply pin
AVSS0
Input
Analog voltage supply ground pin
VREFH0
Input
Analog reference voltage supply pin
VREFL0
Input
Reference power supply ground pin
VREFH
Input
Analog reference voltage supply pin for D/A converter
VREFL
Input
Analog reference ground pin for D/A converter
AN000 to AN014,
AN016 to AN025
Input
Input pins for the analog signals to be processed by the A/D converter
ADTRG0
Input
Input pins for the external trigger signals that start the A/D conversion, activelow
DAC12
DA0
Output
Output pins for the analog signals to be processed by the D/A converter
Comparator
output
VCOUT
Output
Comparator output pin
ACMPLP
CMPREF0,
CMPREF1
Input
Reference voltage input pin
CMPIN0, CMPIN1
Input
Analog voltage input pins
AMP0+ to AMP3+
Input
Analog voltage input pins
AMP0- to AMP3-
Input
Analog voltage input pins
AMP0O to AMP3O
Output
Analog voltage output pins
TS00 to TS13,
TS17 to TS22,
TS27 to TS31,
TS34, TS35
Input
Capacitive touch detection pins (touch pins)
TSCAP
-
Secondary power supply pin for the touch driver
ADC14
OPAMP
CTSU
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 14 of 130
RA4M1 Group
Table 1.14
1. Overview
Pin functions (4 of 4)
Function
Signal
I/O
Description
I/O ports
P000 to P008,
P010 to P015
I/O
General-purpose input/output pins
P100 to P115
I/O
General-purpose input/output pins
P200
Input
General-purpose input pin
P201 to P206,
P212, P213
I/O
General-purpose input/output pins
SLCDC
P214, P215
Input
General-purpose input pins
P300 to P307
I/O
General-purpose input/output pins
P400 to P415
I/O
General-purpose input/output pins
P500 to P505
I/O
General-purpose input/output pins
P600 to P603,
P608 to P610
I/O
General-purpose input/output pins
P708
I/O
General-purpose input/output pins
P808, P809
I/O
General-purpose input/output pins
P914, P915
I/O
General-purpose input/output pins
VL1, VL2, VL3, VL4
I/O
Voltage pin for driving the LCD
CAPH, CAPL
I/O
Capacitor connection pin for the LCD controller/driver
COM0 to COM7
Output
Common signal output pins for the LCD controller/driver
SEG00 to SEG37
Output
Segment signal output pins for the LCD controller/driver
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 15 of 130
RA4M1 Group
1.6
1. Overview
Pin Assignments
Figure 1.3
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602
P603
VSS
VCC
P610
P609
P608
P115
P114
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Figure 1.3 to Figure 1.6 show the pin assignments.
P500
76
50
P501
77
49
P300/TCK/SWCLK
P301
P502
78
48
P302
P503
79
47
P303
P504
80
46
P809
P505
81
45
P808
VCC
82
44
P304
VSS
83
43
P305
P015
84
42
P306
P014
85
41
P307
P013/VREFL
86
40
P200
P012/VREFH
87
39
P201/MD
AVCC0
88
38
RES
AVSS0
89
37
VCC
P011/VREFL0
90
36
VSS
P010/VREFH0
91
35
P202
P008
92
34
P203
P007
93
33
P204
P006
94
32
P205
P005
95
31
P206
P004
96
30
VCC_USB_LDO
P003
97
29
VCC_USB
P002
98
28
P914/USB_DP
P001
99
27
P915/USB_DM
P000
100
26
VSS_USB
14
15
16
17
18
19
20
21
22
23
24
25
P212/EXTAL
VCC
P708
P415
P414
P413
P412
P411
P410
P409
P408
P407
9
VCL
13
8
VBATT
P213/XTAL
7
P406
12
6
P405
VSS
5
P404
11
4
P403
P214/XCOUT
3
P402
10
2
P401
P215/XCIN
1
P400
R7FA4M1AB3CFP
Pin assignment for 100-pin LQFP (top view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 16 of 130
RA4M1 Group
1. Overview
R7FA4M1AB2CLJ
10
9
Figure 1.4
A
B
C
D
E
F
G
H
J
K
P407
P409
P412
VCC
P212/
EXTAL
P215/
XCIN
VCL
P403
P400
P000
10
P413
VSS
P213/
XTAL
P214/
XCOUT
VBATT
P405
P401
P001
9
P915/
P914/
USB_DM USB_DP
8
VCC_
USB
VSS_
USB
VCC_US
B_LDO
P411
P415
P708
P404
P003
P004
P002
8
7
P205
P204
P206
P408
P414
P406
P006
P007
P008
P005
7
6
VSS
VCC
P202
P203
P410
P402
P505
AVSS0
P011/
P010/
6
VREFL0 VREFH0
5
P200
P201/MD
P307
RES
P113
P600
P504
AVCC0
P013/
VREFL
P012/
VREFH
5
4
P305
P304
P808
P306
P115
P601
P503
P100
P015
P014
4
3
P809
P303
P110/TDI
P111
P609
P602
P107
P103
VSS
VCC
3
2
P300/
TCK/
SWCLK
P302
P301
P114
P610
P603
P106
P101
P501
P502
2
1
P108/
TMS/
SWDIO
P109/
TDO/
SWO
P112
P608
VCC
VSS
P105
P104
P102
P500
1
A
B
C
D
E
F
G
H
J
K
Pin assignment for 100-pin LGA (upper perspective view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 17 of 130
Figure 1.5
P100
P101
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1. Overview
48
RA4M1 Group
P500
49
32
P300/TCK/SWCLK
P501
50
31
P301
P502
51
30
P302
P015
52
29
P303
P014
53
28
P304
P013/VREFL
54
27
P200
P012/VREFH
55
26
P201/MD
AVCC0
56
25
RES
AVSS0
57
24
P204
P011/VREFL0
58
23
P205
P010/VREFH0
59
22
P206
P004
60
21
VCC_USB_LDO
P003
61
20
VCC_USB
P002
62
19
P914/USB_DP
P001
63
18
P915/USB_DM
P000
64
17
VSS_USB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P400
P401
P402
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
R7FA4M1AB3CFM
Pin assignment for 64-pin LQFP (top view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 18 of 130
33
34
35
36
37
38
39
40
41
42
43
44
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
45
46
47
P100
P101
1. Overview
48
RA4M1 Group
P500
P501
P502
P015
P014
P013/VREFL
P012/VREFH
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P004
P003
P002
P001
49
32
50
31
58
23
59
22
60
21
61
20
62
19
63
18
P300/TCK/SWCLK
P301
P302
P303
P304
P200
P201/MD
RES
P204
P205
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
51
30
52
29
53
28
54
27
55
26
P000
64
17
VSS_USB
16
24
15
14
13
12
11
10
9
8
7
6
5
4
2
25
P400
P401
P402
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
1
57
3
R7FA4M1AB3CNB
56
Figure 1.6
Pin assignment for 64-pin QFN (upper perspective view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 19 of 130
Figure 1.7
P100
P101
P102
P103
P104
VSS
VCC
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
35
34
33
32
31
30
29
28
27
26
25
1. Overview
36
RA4M1 Group
P500
37
24
P300/TCK/SWCLK
P015
38
23
P301
P014
39
22
P302
P013/VREFL
40
21
P200
P012/VREFH
41
20
P201/MD
AVCC0
42
19
RES
AVSS0
43
18
P206
P011/VREFL0
44
17
VCC_USB_LDO
P010/VREFH0
45
16
VCC_USB
P002
46
15
P914/USB_DP
P001
47
14
P915/USB_DM
P000
48
13
VSS_USB
1
2
3
4
5
6
7
8
9
10
11
12
P400
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
R7FA4M1AB3CFL
Pin assignment for 48-pin LQFP (top view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 20 of 130
25
26
27
28
29
30
31
32
P102
P103
P104
VSS
VCC
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
33
34
35
P100
P101
1. Overview
36
RA4M1 Group
P500
P015
P014
P013/VREFL
P012/VREFH
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P002
P001
37
24
38
23
44
17
45
16
46
15
47
14
P300/TCK/SWCLK
P301
P302
P200
P201/MD
RES
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
39
22
40
21
41
20
P000
48
13
VSS_USB
42
19
12
11
10
9
8
7
6
5
4
3
1
18
P400
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
2
R7FA4M1AB3CNE
43
Figure 1.8
Pin assignment for 48-pin QFN (top view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 21 of 130
21
22
23
24
25
26
P102
VSS
VCC
P112
P111
P110/TDI
P109/TDO/SWO
P108/TMS/SWDIO
27
28
29
P100
P101
1. Overview
30
RA4M1 Group
P015
P014
P013/VREFL
P012/VREFH
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P001
31
20
32
19
37
14
38
13
39
12
P300/TCK/SWCLK
P301
P200
P201/MD
RES
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
33
18
34
17
P000
40
11
VSS_USB
35
16
10
9
8
7
6
5
4
3
1
15
VBATT
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P408
P407
2
R7FA4M1AB3CNF
36
Figure 1.9
Pin assignment for 40-pin QFN (top view)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 22 of 130
RA4M1 Group
Pin Lists
J10 1
1
2
J9
2
3
F6
3
4
CACREF
IRQ0
P400
2
IRQ5
P401
3
VBATWIO0 IRQ4
P402
AGTIO0/
AGTIO1
H10
VBATWIO1
P403
AGTIO0/
AGTIO1
5
G8
VBATWIO2
6
AGTIO1
GTIOC6A
SCK0
SCK1
GTETRGA GTIOC6B
RTCIC0
SCL0
AUDIO_CL
K
CTSU
SLCDC
ACMPLP
HMI
DAC12, OPAMP
ADC14
SSIE
Analogs
SPI
IIC
SCI
USBFS,CAN
RTC
GPT
Communication interfaces
GPT_OPS, POEG
AGT
Timers
I/O ports
1
Power, System, Clock,
Debug, CAC, VBATT
1
QFN40
QFN48
1
LQFP48
QFN64
LQFP64
LGA100
LQFP100
Pin number
Interrupt
1.7
1. Overview
SEG04 TS20
CTX0
CTS0_ SDA0
RTS0/
SS0
TXD1/
MOSI1/
SDA1
SEG05 TS19
CRX0
RXD1/
MISO1/
SCL1
SEG06 TS18
GTIOC3A
RTCIC1
CTS1_
RTS1/
SS1
P404
GTIOC3B
RTCIC2
H9
P405
GTIOC1A
SSITXD0
7
F7
P406
GTIOC1B
SSIRXD0
8
G9
4
4
2
2
1
VBATT
9
G10 5
5
3
3
2
VCL
10
F10 6
6
4
4
3
XCIN
P215
11
F9
7
7
5
5
4
XCOUT
P214
12
D9
8
8
6
6
5
VSS
13
E9
9
9
7
7
6
XTAL
IRQ2
P213
GTETRGA GTIOC0A
TXD1/
MOSI1/
SDA1
14
E10 10
10
8
8
7
EXTAL
IRQ3
P212
AGTEE1 GTETRGB GTIOC0B
RXD1/
MISO1/
SCL1
15
D10 11
11
9
9
8
VCC
16
F8
17
E8
IRQ8
P415
GTIOC0A
SSLA2
18
E7
IRQ9
P414
GTIOC0B
SSLA1
19
C9
P413
CTS0_
RTS0/
SS0
SSLA0
20
C10
P412
SCK0
RSPCKA
21
D8
12
12
IRQ4
P411
AGTOA1 GTOVUP
GTIOC6A
TXD0/
MOSI0/
SDA0
MOSIA
SEG07 TS07
22
E6
13
13
IRQ5
P410
AGTOB1 GTOVLO
GTIOC6B
RXD0/
MISO0/
SCL0
MISOA
SEG08 TS06
23
B10 14
14
10
10
IRQ6
P409
GTOWUP GTIOC5A
USB_EXI TXD9/
CEN
MOSI9/
SDA9
24
D7
15
15
11
11
9
IRQ7
P408
GTOWLO
USB_ID
25
A10 16
16
12
12
10
26
B8
17
17
13
13
11
27
A9
18
18
14
14
12
P915
USB_DM
28
B9
19
19
15
15
13
P914
USB_DP
P407
RXD1/
MISO1/
SCL1
AGTIO0
TS17
SSILRCK0/
SSIFS0
P708
GTIOC5B
SSIBCK0
SSLA3
SEG09 TS05
CTS1_ SCL0
RTS1/
SS1
RXD9/
MISO9/
SCL9
RTCOUT USB_VB CTS0_ SDA0
US
RTS0/
SS0
SEG10 TS04
SSLB3
ADTRG0
SEG11 TS03
VSS_USB
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 23 of 130
RA4M1 Group
1. Overview
21
17
17
15
VCC_USB_
LDO
31
C7
22
22
18
18
32
A7
23
23
CLKOUT
33
B7
24
24
CACREF
34
D6
P203
GTIOC5A
35
C6
P202
GTIOC5B
36
A6
37
B6
38
D5
25
25
19
19
16
RES
39
B5
26
26
20
20
17
MD
40
A5
27
27
21
21
18
41
C5
P307
SEG17
42
D4
P306
SEG18
43
A4
IRQ8
P305
SEG19
44
B4
IRQ9
P304
45
C4
P808
SEG21
46
A3
P809
SEG22
47
B3
29
29
48
B2
30
30
22
22
49
C2
31
31
23
23
19
50
A2
32
32
24
24
20
TCK/
SWCLK
51
A1
33
33
25
25
21
52
B1
34
34
26
26
53
C3
35
35
27
27
IRQ0
P206
GTIU
IRQ1
P205
AGTO1
GTIV
P204
AGTIO1
GTIW
SLCDC
21
ADC14
C8
SSIE
30
SPI
VCC_USB
IIC
14
SCI
16
RTC
16
GPT
20
AGT
20
QFN64
A8
CTSU
ACMPLP
DAC12, OPAMP
USBFS,CAN
HMI
QFN40
GPT_OPS, POEG
Analogs
QFN48
I/O ports
Communication interfaces
LQFP48
Interrupt
Power, System, Clock,
Debug, CAC, VBATT
Timers
29
LGA100
LQFP64
LQFP100
Pin number
USB_VB RXD0/ SDA1
USEN
MISO0/
SCL0
SSLB1
SEG12 TS01
GTIOC4A
USB_OV TXD0/ SCL1
RCURA MOSI0/
SDA0
CTS9_
RTS9/
SS9
SSLB0
SEG13 TSCAP
GTIOC4B
USB_OV SCK0
RCURB SCK9
RSPCKB
SEG14 TS00
CTS2_
RTS2/
SS2
TXD9/
MOSI9/
SDA9
MOSIB
SEG15 TSCAP
SCK2
RXD9/
MISO9/
SCL9
MISOB
SEG16
SCL0
VSS
VCC
28
P201
NMI
28
P200
GTIOC7A
P303
IRQ5
P302
IRQ6
P301
SEG20 TS11
GTIOC7B
SEG03/ TS02
COM7
GTOUUP
GTIOC4A
TXD2/
MOSI2/
SDA2
SSLB3
SEG02/ TS08
COM6
GTOULO
GTIOC4B
RXD2/
MISO2/
SCL2
CTS9_
RTS9/
SS9
SSLB2
SEG01/ TS09
COM5
P300
GTOUUP
GTIOC0A
TMS/
SWDIO
P108
GTOULO
GTIOC0B
22
TDO/SWO/
CLKOUT
P109
GTOVUP
GTIOC1A
23
TDI
P110
GTOVLO
GTIOC1B
IRQ3
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
AGTIO0
SSLB1
CTS9_
RTS9/
SS9
SSLB0
CTX0
SCK1
TXD9/
MOSI9/
SDA9
MOSIB
CRX0
CTS2_
RTS2/
SS2
RXD9/
MISO9/
SCL9
MISOB
SEG23 TS10
VCOUT
SEG24
Page 24 of 130
RA4M1 Group
1. Overview
57
GTIOC3B
TXD2/
MOSI2/
SDA2
SCK1
SSLB0
P113
D2
58
CTSU
38
P112
SLCDC
38
RSPCKB
ACMPLP
E5
SCK2
SCK9
HMI
DAC12, OPAMP
56
GTIOC3A
ADC14
25
P111
SSIE
29
Analogs
SPI
29
IIC
37
SCI
37
USBFS,CAN
C1
RTC
55
IRQ4
GPT
24
GPT_OPS, POEG
28
Communication interfaces
AGT
28
I/O ports
QFN40
36
Timers
Interrupt
QFN48
36
Power, System, Clock,
Debug, CAC, VBATT
LQFP48
D3
QFN64
54
LGA100
LQFP64
LQFP100
Pin number
CAPH
TS12
SSIBCK0
CAPL
TSCAP
GTIOC2A
SSILRCK0/
SSIFS0
SEG00/ TS27
COM4
P114
GTIOC2B
SSIRXD0
SEG25 TS29
E4
P115
GTIOC4A
SSITXD0
SEG26 TS35
59
D1
P608
GTIOC4B
SEG27
60
E3
P609
GTIOC5A
SEG28
61
E2
P610
GTIOC5B
SEG29
62
E1
39
39
30
30
26
VCC
63
F1
40
40
31
31
27
VSS
64
F2
P603
GTIOC7A
CTS9_
RTS9/
SS9
SEG30
65
F3
P602
GTIOC7B
TXD9/
MOSI9/
SDA9
SEG31
66
F4
P601
GTIOC6A
RXD9/
MISO9/
SCL9
SEG32
67
F5
P600
GTIOC6B
SCK9
SEG33
68
G3
41
41
KR07
P107
GTIOC0A
69
G2
42
42
KR06
P106
GTIOC0B
SSLA3
COM2
70
G1
43
43
KR05/
IRQ0
P105
GTETRGA GTIOC1A
SSLA2
COM1
TS34
71
H1
44
44
32
32
KR04/
IRQ1
P104
GTETRGB GTIOC1B
RXD0/
MISO0/
SCL0
SSLA1
COM0
TS13
72
H3
45
45
33
33
KR03
P103
GTOWUP GTIOC2A
CTX0
CTS0_
RTS0/
SS0
SSLA0
AN019
CMPREF1 VL4
73
J1
46
46
34
34
28
KR02
P102
AGTO0
GTOWLO
CRX0
SCK0
TXD2/
MOSI2/
SDA2
RSPCKA
AN020/
ADTRG0
CMPIN1
74
H2
47
47
35
35
29
KR01/
IRQ1
P101
AGTEE0 GTETRGB GTIOC5A
TXD0/ SDA1
MOSI0/
SDA0
CTS1_
RTS1/
SS1
MOSIA
AN021
CMPREF0 VL2
75
H4
48
48
36
36
30
KR00/
IRQ2
P100
AGTIO0
RXD0/ SCL1
MISO0/
SCL0
SCK1
MISOA
AN022
CMPIN0
76
K1
49
49
37
37
P500
AGTOA0 GTIU
GTIOC2A
USB_VB
USEN
AN016
CMPREF1 SEG34
77
J2
50
50
IRQ11
P501
AGTOB0 GTIV
GTIOC2B
USB_OV TXD1/
RCURA MOSI1/
SDA1
AN017
CMPIN1
78
K2
51
51
IRQ12
P502
GTIW
GTIOC3B
USB_OV RXD1/
RCURB MISO1/
SCL1
AN018
CMPREF0 SEG36
79
G4
P503
USB_EXI SCK1
CEN
AN023
CMPIN0
80
G5
P504
USB_ID
AN024
81
G6
82
K3
IRQ14
P505
GTIOC2B
COM3
GTETRGA GTIOC5B
CTS1_
RTS1/
SS1
VL3
VL1
SEG35
SEG37
AN025
VCC
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Oct 8, 2019
Page 25 of 130
RA4M1 Group
1. Overview
83
J3
84
J4
52
52
38
38
31
85
K4
53
53
39
39
32
86
J5
54
54
40
40
33
87
K5
55
55
41
41
88
H5
56
56
42
89
H6
57
57
90
J6
58
91
K6
59
92
CTSU
SLCDC
ACMPLP
DAC12, OPAMP
HMI
ADC14
SSIE
Analogs
SPI
IIC
SCI
USBFS,CAN
RTC
GPT
Communication interfaces
GPT_OPS, POEG
AGT
I/O ports
Timers
Interrupt
Power, System, Clock,
Debug, CAC, VBATT
QFN40
QFN48
LQFP48
QFN64
LQFP64
LGA100
LQFP100
Pin number
VSS
IRQ7
P015
AN010
P014
AN009
DA0
VREFL
P013
AN008
AMP1+
34
VREFH
P012
AN007
AMP1-
42
35
AVCC0
43
43
36
AVSS0
58
44
44
37
VREFL0
P011
AN006
AMP2+
TS31
59
45
45
38
VREFH0
P010
AN005
AMP2-
TS30
J7
P008
AN014
93
H7
P007
AN013
AMP3O
94
G7
P006
AN012
AMP3-
95
K7
IRQ10
P005
AN011
AMP3+
96
J8
60
60
IRQ3
P004
AN004
AMP2O
97
H8
61
61
P003
AN003
AMP1O
98
K8
62
62
46
46
IRQ2
P002
AN002
AMP0O
99
K9
63
63
47
47
39
IRQ7
P001
AN001
AMP0-
TS22
100 K10 64
64
48
48
40
IRQ6
P000
AN000
AMP0+
TS21
IRQ15
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
TS28
Page 26 of 130
RA4M1 Group
2.
2. Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5V, VREFH = VREFH0 = 1.6 to AVCC0, VBATT =
1.6 to 3.6V, VSS = AVSS0 = VREFL = VREFL0 = VSS_USB = 0V, Ta = Topr.
Note 1. The typical condition is set to VCC = 3.3V.
Note 2. When USBFS is not used.
Figure 2.1 shows the timing conditions.
For example P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30 pF
Figure 2.1
Input or output timing measurement conditions
The recommended measurement conditions for the timing specification of each peripheral provided are for the best
peripheral operation. Make sure to adjust the driving abilities of each pin to meet your conditions.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function
pin is mixed, the AC specification of each function is not guaranteed.
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 27 of 130
RA4M1 Group
2.1
2. Electrical Characteristics
Absolute Maximum Ratings
Table 2.1
Absolute maximum ratings
Parameter
Power supply voltage
Input voltage
ports*1
Symbol
Value
Unit
VCC
-0.5 to +6.5
V
Vin
-0.3 to +6.5
V
P000 to P008, P010 to P015
Vin
-0.3 to AVCC0 + 0.3
V
Others
Vin
-0.3 to VCC + 0.3
V
VREFH0
-0.3 to +6.5
V
5 V-tolerant
Reference power supply voltage
VREFH
V
VBATT power supply voltage
VBATT
-0.5 to +6.5
V
Analog power supply voltage
AVCC0
-0.5 to +6.5
V
USB power supply voltage
VCC_USB
-0.5 to +6.5
V
VCC_USB_LDO
-0.5 to +6.5
V
VAN
-0.3 to AVCC0 + 0.3
V
-0.3 to VCC + 0.3
V
Analog input voltage
When AN000 to AN014 are
used
When AN016 to AN025 are
used
LCD voltage
VL1 voltage
VL1
-0.3 to +2.8
V
VL2 voltage
VL2
-0.3 to +6.5
V
VL3 voltage
VL3
-0.3 to +6.5
V
VL4 voltage
VL4
-0.3 to +6.5
V
Topr
-40 to +105
°C
Operating temperature*2,*3,*4
-40 to +85
Storage temperature
Caution:
Note 1.
Note 2.
Note 3.
Note 4.
Tstg
-55 to +125
°C
Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics
between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins,
between the VREFH0 and VREFL0 pins, and between the VREFH and VREFL pins. Place capacitors of about 0.1 μF
as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect
capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7 µF capacitor. The capacitor must be placed close to the pin.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that
results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in
the device at this time might cause degradation of internal elements.
Ports P205, P206, P400 to P404, P407, P408 are 5 V tolerant.
See section 2.2.1, Tj/Ta Definition.
Contact a Renesas Electronics sales office for information on derating operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for improved reliability.
The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part
Numbering.
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Page 28 of 130
RA4M1 Group
Table 2.2
2. Electrical Characteristics
Recommended operating conditions
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltages
VCC*1, *2
When USBFS is not
used
1.6
-
5.5
V
When USBFS is used VCC_USB
USB Regulator
Disable
-
3.6
V
When USBFS is used VCC_USB
USB Regulator
_LDO
Enable
-
5.5
V
-
0
-
V
-
VCC
-
V
When USBFS is used 3.0
USB Regulator
Disable
(Input)
3.3
3.6
V
When USBFS is not
used
-
VCC
-
V
When USBFS is used
USB Regulator
Disable
-
VCC
-
V
-
5.5
V
-
0
-
V
When the battery
backup function is not
used
-
VCC
-
V
When the battery
backup function is
used
1.6
-
3.6
V
AVCC0*1, *2
1.6
-
5.5
V
AVSS0
-
0
-
V
1.6
-
AVCC0
V
VSS
USB power supply voltages
VCC_USB
VCC_USB_LDO
When USBFS is not
used
When USBFS is used 3.8
USB Regulator
Enable
VSS_USB
VBATT power supply voltage
Analog power supply voltages
VBATT
VREFH0
VREFL0
VREFH
VREFL
Note 1.
Note 2.
When used as
ADC14 Reference
When used as
DAC12 Reference
-
0
-
V
1.6
-
AVCC0
V
-
0
-
V
Use AVCC0 and VCC under the following conditions:
AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V.
AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V.
When powering on the VCC and AVCC0 pins, power them on at the same time, or power the VCC pin first and then the AVCC0
pin.
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Page 29 of 130
RA4M1 Group
2.2
2. Electrical Characteristics
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC Characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
-
125
°C
High-speed mode
Middle-speed mode
Low-voltage mode
Low-speed mode
Subosc-speed mode
105*1
Note:
Note 1.
Make sure that Tj = Ta + θja × total power consumption (W),
where total power consumption = (VCC - VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC.
The upper limit of operating temperature is +85°C or +105°C, depending on the product. For details, see section 1.3, Part
Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj is +105°C, otherwise, it
is +125°C.
2.2.2
I/O VIH, VIL
Table 2.4
I/O VIH, VIL (1)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 5.5V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V
Parameter
Schmitt trigger
input voltage
IIC*1
(except for SMBus)
RES, NMI
Other peripheral input pins
excluding IIC
Input voltage
(except for
Schmitt trigger
input pin)
IIC (SMBus)*2
5 V-tolerant ports*3
P914, P915
Symbol
Min
VIH
VCC × 0.7
VIL
-
ΔVT
VCC × 0.05
-
-
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
ΔVT
VCC × 0.1
-
-
Note 1.
Note 2.
Note 3.
Max
Unit
Test conditions
-
5.8
V
-
-
VCC × 0.3
VIH
2.2
-
-
VCC = 3.6 to 5.5 V
VIH
2.0
-
-
VCC = 2.7 to 3.6 V
VIL
-
-
0.8
-
VIH
VCC × 0.8
-
5.8
VIL
-
-
VCC × 0.2
VIH
VCC_USB × 0.8
-
VCC_USB + 0.3
VIL
-
-
VCC_USB × 0.2
AVCC0 × 0.8
-
-
VIL
-
-
AVCC0 × 0.2
EXTAL
Input ports pins except for
P000 to P008, P010 to
P015, P914, P915
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
P402, P403, P404
VIH
VBATT × 0.8
-
VBATT + 0.3
VIL
-
-
VBATT × 0.2
ΔVT
VBATT × 0.05
-
-
P000 to P008, P010 to P015 VIH
When VBATT
power supply is
selected
Typ
P205, P206, P400, P401, P407, P408 (total 6 pins).
P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins).
P205, P206, P400 to P404, P407, P408 (total 9 pins).
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Page 30 of 130
RA4M1 Group
Table 2.5
2. Electrical Characteristics
I/O VIH, VIL (2)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test
conditions
V
-
Schmitt trigger
input voltage
RES, NMI
Peripheral input pins
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
ΔVT
VCC × 0.01
-
-
Input voltage
(except for
Schmitt trigger
input pin)
5 V-tolerant ports*1
VIH
VCC × 0.8
-
5.8
VIL
-
-
VCC × 0.2
P914, P915
VIH
VCC_USB × 0.8
-
VCC_USB + 0.3
VIL
-
-
VCC_USB × 0.2
P000 to P008, P010 to P015
VIH
AVCC0 × 0.8
-
-
VIL
When VBATT
power supply is
selected
Note 1.
-
-
AVCC0 × 0.2
EXTAL
Input ports pins except for
P000 to P008, P010 to P015,
P914, P915
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
P402, P403, P404
VIH
VBATT × 0.8
-
VBATT + 0.3
VIL
-
-
VBATT × 0.2
ΔVT
VBATT × 0.01
-
-
P205, P206, P400 to P404, P407, P408 (total 9 pins)
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Page 31 of 130
RA4M1 Group
2.2.3
Table 2.6
2. Electrical Characteristics
I/O IOH, IOL
I/O IOH, IOL (1 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V
Parameter
Permissible output current
(average value per pin)
Symbol
Min
Typ
Max
Unit
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Middle drive for IIC
Fast-mode*4
VCC = 2.7 to 5.5 V
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
-
-
-20.0
mA
IOL
-
-
20.0
mA
Low drive*1
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Middle drive*2
VCC = 2.7 to 3.0 V
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
-
-
-20.0
mA
IOL
-
-
20.0
mA
Ports P100 to P115,
P201 to P204, P300 to P307,
P500 to P503, P600 to P603,
P608 to P610, P808, P809
(total 41 pins)
Low drive*1
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Middle drive*2
IOH
-
-
-4.0
mA
IOL
-
-
8.0
mA
Ports P914, P915
-
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Other output pin*3
Low drive*1
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
Ports P212, P213
Port P408
Port P409
-
Low
drive*1
Middle drive*2
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Oct 8, 2019
Page 32 of 130
RA4M1 Group
Table 2.6
2. Electrical Characteristics
I/O IOH, IOL (2 of 2)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 5.5 V
Parameter
Permissible output current
(Max value per pin)
Symbol
Min
Typ
Max
Unit
Ports P212, P213
-
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Port P408
Low drive*1
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
Middle drive for IIC
Fast-mode*4
VCC = 2.7 to 5.5 V
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH
-
-
-20.0
mA
IOL
-
-
20.0
mA
Low drive*1
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
IOH
-
-
-20.0
mA
IOL
-
-
20.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
8.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
Port P409
Middle drive*2
VCC = 2.7 to 3.0 V
Middle drive*2
VCC = 3.0 to 5.5 V
Ports P100 to P115,
P201 to P204, P300 to P307,
P500 to P503, P600 to P603,
P608 to P610, P808, P809
(total 41 pins)
Ports P914, P915
Other output pin*3
Low drive*1
Middle
drive*2
-
Low
drive*1
Middle drive*2
Permissible output current
(max value total pins)
Total of ports P000 to P008, P010 to P015
Ports P914, P915
Total of all output pin*5
Caution:
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
ΣIOH (max)
-
-
-30
mA
ΣIOL (max)
-
-
30
mA
ΣIOH (max)
-
-
-2.0
mA
ΣIOL (min)
-
-
2.0
mA
ΣIOH (max)
-
-
-60
mA
ΣIOL (max)
-
-
60
mA
To protect the reliability of the MCU, the output current values should not exceed the values in this table. The
average output current indicates the average value of current measured during 100 μs.
This is the value when low driving ability is selected with the Port Drive Capability bit in PmnPFS register.
This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register.
Except for ports P200, P214, P215, which are input ports.
This is the value when middle driving ability for IIC Fast-mode is selected with the Port Drive Capability bit in PmnPFS register.
For details on the permissible output current used with CTSU, see section 2.11, CTSU Characteristics.
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 33 of 130
RA4M1 Group
2.2.4
2. Electrical Characteristics
I/O VOH, VOL, and Other Characteristics
Table 2.7
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 4.0 to 5.5 V
Parameter
Output voltage
IIC*1
Ports P408,
P409*2, *3
Ports P000 to P008,
P010 to P015
Low drive
Middle drive
Ports P914, P915
Other output pins*4
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Symbol
Min
Typ
Max
Unit
Test conditions
VOL
-
-
0.4
V
IOL = 3.0 mA
VOL*2,*5
-
-
0.6
IOL = 6.0 mA
VOH
VCC - 1.0
-
-
IOH = -20 mA
VOL
-
-
1.0
IOL = 20 mA
VOH
AVCC0 - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
VOH
AVCC0 - 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
VOH
VCC_USB - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Low drive
VOH
VCC - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
Middle
drive*6
VOH
VCC - 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register.
Based on characterization data, not tested in production.
Except for ports P200, P214, P215, which are input ports.
This is the value when middle driving ability for IIC is selected in the Port Drive Capability bit in PmnPFS register for P408.
Except for P212, P213.
Table 2.8
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 2.7 to 4.0 V
Parameter
Output voltage
IIC*1
Symbol
Min
Typ
Max
Unit
Test conditions
VOL
-
-
0.4
V
IOL = 3.0 mA
VOL
Ports P408, P409*2, *3
Ports P000 to P008,
P010 to P015
Low drive
Middle drive
Ports P914, P915
Other output
pins*4
Low drive
Middle
drive*6
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
*2,*5
-
-
0.6
IOL = 6.0 mA
VOH
VCC - 1.0
-
-
IOH = -20 mA
VCC = 3.3 V
VOL
-
-
1.0
IOL = 20 mA
VCC = 3.3 V
VOH
AVCC0 - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
AVCC0 - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
VOH
VCC_USB - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
P100, P101, P204, P205, P206, P400, P401, P407, P408 (total 9 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in PmnPFS register.
Based on characterization data, not tested in production.
Except for ports P200, P214, P215, which are input ports.
This is the value when middle driving ability for IIC is selected in the Port Drive Capability bit in PmnPFS register for P408.
Except for P212, P213.
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 34 of 130
RA4M1 Group
Table 2.9
2. Electrical Characteristics
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LCO = 1.6 to 2.7 V
Parameter
Output voltage
Ports P000 to P015
Symbol
Min
Typ
Max
Unit
Test conditions
Low drive
VOH
AVCC0 - 0.3
-
-
V
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
Middle drive
VOH
AVCC0 - 0.3
-
-
IOH = -1.0 mA
Ports P914, P915
Other output pins*1
Note 1.
Note 2.
VOL
-
-
0.3
IOL = 1.0 mA
VOH
VCC_USB - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
Low drive
VOH
VCC - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
Middle
drive*2
VOH
VCC - 0.3
-
-
IOH = -1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
Except for ports P200, P214, P215, which are input ports.
Except for P212, P213.
Table 2.10
I/O other characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
RES, P200, P214, P215
| Iin |
-
-
1.0
μA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
5 V-tolerant ports
| ITSI |
-
-
1.0
μA
Vin = 0 V
Vin = 5.8 V
-
-
1.0
Other ports
(except for ports P200, P214,
P215 and 5 V tolerant)
Vin = 0 V
Vin = VCC
Input pull-up resistor
All ports
(except for ports P200, P214,
P215, P914, P915)
RU
10
20
50
kΩ
Vin = 0 V
Input capacitance
P914, P915,
P100 to P103, P111, P112,
P200
Cin
-
-
30
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
-
-
15
Other input pins
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 35 of 130
RA4M1 Group
2.2.5
2. Electrical Characteristics
I/O Pin Output Characteristics of Low Drive Capacity
IOH/IOL vs VOH/VOL
60
50
VCC = 5.5 V
40
30
VCC = 3.3 V
IOH/IOL [mA]
20
VCC = 2.7 V
10
VCC = 1.6 V
0
VCC = 1.6 V
-10
VCC = 2.7 V
-20
VCC = 3.3 V
-30
-40
-50
VCC = 5.5 V
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.2
VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C when low drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
3
Ta = -40°C
Ta = 25°C
Ta = 105°C
2
IOH/IOL [mA]
1
0
-1
Ta = 105°C
Ta = 25°C
-2
Ta = -40°C
-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.3
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected
(reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 36 of 130
RA4M1 Group
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
20
15
Ta = -40°C
Ta = 25°C
Ta = 105°C
IOH/IOL [mA]
10
5
0
-5
Ta = 105°C
Ta = 25°C
-10
Ta = -40°C
-15
-20
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.4
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
30
Ta = -40°C
Ta = 25°C
Ta = 105°C
20
IOH/IOL [mA]
10
0
-10
Ta = 105°C
Ta = 25°C
-20
Ta = -40°C
-30
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.5
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected
(reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 37 of 130
RA4M1 Group
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40°C
Ta = 25°C
Ta = 105°C
40
IOH/IOL [mA]
20
0
-20
Ta = 105°C
-40
Ta = 25°C
Ta = -40°C
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.6
2.2.6
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected
(reference data)
I/O Pin Output Characteristics of Middle Drive Capacity
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
140
120
100
80
60
40
20
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 1.6 V
0
-20
-40
-60
-80
-100
-120
-140
VCC = 1.6 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.7
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 38 of 130
RA4M1 Group
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
6
Ta = -40°C
Ta = 25°C
Ta = 105°C
4
IOH/IOL [mA]
2
0
-2
Ta = 105°C
-4
Ta = 25°C
Ta = -40°C
-6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.8
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
40
Ta = -40°C
Ta = 25°C
Ta = 105°C
30
IOH/IOL [mA]
20
10
0
-10
-20
Ta = 105°C
Ta = 25°C
-30
Ta = -40°C
-40
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.9
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 39 of 130
RA4M1 Group
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40°C
Ta = 25°C
40
Ta = 105°C
IOH/IOL [mA]
20
0
-20
Ta = 105°C
-40
Ta = 25°C
Ta = -40°C
-60
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.10
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
Ta = -40°C
Ta = 25°C
Ta = 105°C
Ta = 105°C
Ta = 25°C
Ta = -40°C
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.11
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 40 of 130
RA4M1 Group
2.2.7
2. Electrical Characteristics
P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.12
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
IOH/IOL vs VOH/VOL
60
Ta = -40°C
Ta = 25°C
Ta = 105°C
40
IOH/IOL [mA]
20
0
-20
Ta = 105°C
-40
Ta = 25°C
Ta = -40°C
-60
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.13
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 41 of 130
RA4M1 Group
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
100
Ta = -40°C
Ta = 25°C
Ta = 105°C
80
60
40
IOH/IOL [mA]
20
0
-20
-40
Ta = 105°C
-60
Ta = 25°C
-80
Ta = -40°C
-100
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.14
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
220
Ta = -40°C
Ta = 25°C
Ta = 105°C
180
140
IOH/IOL [mA]
100
60
20
-20
-60
-100
-140
Ta = 105°C
Ta = 25°C
-180
Ta = -40°C
-220
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.15
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 42 of 130
RA4M1 Group
2.2.8
2. Electrical Characteristics
IIC I/O Pin Output Characteristics
IOL vs VOL
120
110
VCC = 5.5 V (Middle drive)
100
90
IOL [mA]
80
70
60
50
VCC = 3.3V (Middle drive)
VCC = 5.5V (Low drive)
40
VCC = 2.7V (Middle drive)
30
VCC = 3.3V (Low drive)
20
10
VCC = 2.7V (Low drive)
0
0
1
2
3
4
5
6
VOL [V]
Figure 2.16
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 43 of 130
RA4M1 Group
2.2.9
Table 2.11
2. Electrical Characteristics
Operating and Standby Current
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
High-speed
mode*2
Normal mode
All peripheral clock
disabled, while (1) code
executing from flash*5
All peripheral clock
disabled, CoreMark code
executing from flash*5
All peripheral clock
enabled, while (1) code
executing from flash*5
Sleep mode
ICLK = 48 MHz
Symbol
Typ*10
Max
Unit
Test
conditions
ICC
mA
*7
8.3
-
ICLK = 32 MHz
5.8
-
ICLK = 16 MHz
3.5
-
ICLK = 8 MHz
2.2
-
ICLK = 48 MHz
16.4
-
ICLK = 32 MHz
11.3
-
ICLK = 16 MHz
6.4
-
ICLK = 8 MHz
4.0
-
ICLK = 48 MHz
18.5
-
*9
ICLK = 32 MHz
13.8
-
*8
ICLK = 16 MHz
7.7
-
ICLK = 8 MHz
4.5
-
All peripheral clock
enabled, code executing
from SRAM*5
ICLK = 48 MHz
-
50.0
*9
All peripheral clock
disabled*5
ICLK = 48 MHz
3.3
-
*7
ICLK = 32 MHz
2.4
-
ICLK = 16 MHz
1.8
-
ICLK = 8 MHz
1.4
-
ICLK = 48 MHz
13.4
-
*9
ICLK = 32 MHz
10.4
-
*8
All peripheral clock
enabled*5
ICLK = 16 MHz
6.0
-
ICLK = 8 MHz
3.6
-
Increase during BGO operation*6
Middle-speed
mode*2
Normal mode
All peripheral clock
disabled, while (1) code
executing from flash*5
All peripheral clock
disabled, CoreMark code
executing from flash*5
All peripheral clock
enabled, while (1) code
executing from flash*5
Sleep mode
-
2.5
-
ICLK = 8 MHz
2.0
-
ICLK = 1 MHz
0.9
-
ICLK = 12 MHz
4.7
-
ICLK = 8 MHz
3.7
-
ICLK = 1 MHz
1.2
-
ICLK = 12 MHz
5.7
-
ICLK = 8 MHz
4.3
-
ICC
ICLK = 1 MHz
1.5
-
All peripheral clock
enabled, code executing
from SRAM*5
ICLK = 12 MHz
-
20.0
All peripheral clock
disabled*5
ICLK = 12 MHz
1.2
-
ICLK = 8 MHz
1.2
-
ICLK = 1 MHz
0.8
-
ICLK = 12 MHz
4.4
-
ICLK = 8 MHz
3.4
-
ICLK = 1 MHz
1.4
-
2.5
-
All peripheral clock
enabled*5
Increase during BGO operation*6
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
2.5
ICLK = 12 MHz
mA
*7
*8
*7
*8
-
Page 44 of 130
RA4M1 Group
Table 2.11
2. Electrical Characteristics
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
Low-speed
mode*3
Normal mode
Sleep mode
Low-voltage
mode*3
Normal mode
Sleep mode
Suboscspeed
mode*4
Normal mode
Sleep mode
Symbol
Typ*10
Max
Unit
Test
conditions
ICC
0.4
-
mA
*7
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 1 MHz
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 1 MHz
0.6
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 1 MHz
1.0
-
All peripheral clock
enabled, code executing
from SRAM*5
ICLK = 1 MHz
-
2.2
All peripheral clock
disabled*5
ICLK = 1 MHz
0.3
-
*7
All peripheral clock
enabled*5
ICLK = 1 MHz
0.9
-
*8
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 4 MHz
1.7
-
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 4 MHz
2.8
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 4 MHz
3.0
-
All peripheral clock
enabled, code executing
from SRAM*5
ICLK = 4 MHz
-
8.0
All peripheral clock
disabled*5
ICLK = 4 MHz
1.3
-
*7
All peripheral clock
enabled*5
ICLK = 4 MHz
2.5
-
*8
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
8.5
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
14.9
-
All peripheral clock
enabled, code executing
from SRAM*5
ICLK = 32.768 kHz
-
83.0
All peripheral clock
disabled*5
ICLK = 32.768 kHz
5.0
-
All peripheral clock
enabled*5
ICLK = 32.768 kHz
11.4
-
ICC
ICC
*8
mA
*7
*8
μA
*8
Note 1.
Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64.
Note 8. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are the same frequency as that of ICLK.
Note 9. FCLK and PCLKB are set to divided by 2 and PCLKA, PCLKC, and PCLKD are the same frequency as that of ICLK.
Note 10. VCC = 3.3 V.
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RA4M1 Group
2. Electrical Characteristics
40
T a = 1 0 5C , IC L K = 4 8 M H z * 2
35
30
T a = 1 0 5 C , I C L K = 3 2 M H z * 2
ICC (mA)
25
T a = 2 5 C , I C L K = 4 8 M H z * 1
T a = 1 0 5 C , I C L K = 1 6 M H z * 2
T a = 2 5 C , I C L K = 3 2 M H z * 1
T a = 1 0 5 C , I C L K = 8 M H z * 2
T a = 2 5 C , I C L K = 1 6 M H z * 1
T a = 1 0 5 C , I C L K = 4 M H z * 2
T a = 2 5 C , I C L K = 8 M H z * 1
T a = 2 5 C , I C L K = 4 M H z * 1
20
15
10
5
0
1 .5
2 .0
2 .5
Ta
Ta
Ta
Ta
Ta
=
=
=
=
=
2 5 C
2 5 C
2 5 C
2 5 C
2 5 C
3 .0
,
,
,
,
IC L K
IC L K
IC L K
IC L K
3 .5
=
=
=
=
VCC
4 8 M H z *1
3 2 M H z *1
1 6 M H z *1
8 M H z *1
, IC L K = 4 M H z * 1
4 .0
4 .5
5 .0
5 .5
6 .0
(V )
1 0 5 C
1 0 5 C
1 0 5 C
1 0 5 C
T a = 1 0 5 C
Ta
Ta
Ta
Ta
=
=
=
=
,
,
,
,
,
IC L K
IC L K
IC L K
IC L K
IC L K
=
=
=
=
=
4 8 M H z *2
3 2 M H z *2
1 6 M H z *2
8 M H z *2
4 M H z *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.17
Voltage dependency in high-speed operating mode (reference data)
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Page 46 of 130
RA4M1 Group
2. Electrical Characteristics
12
Ta = 105C , ICLK = 12 MHz * 2
ICC (mA)
10
8
Ta = 105C , ICLK = 8 MHz * 2
6
Ta = 25 C , ICLK = 12 MHz * 1
Ta = 105 C , ICLK = 4 MHz * 2
Ta = 25 C, ICLK = 8 MHz * 1
4
Ta = 25 C, ICLK = 4 MHz*1
Ta = 105C , ICLK = 1 MHz * 2
Ta = 25 C, ICLK = 1 MHz * 1
2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
Ta = 25C , ICLK = 12 MHz *1
Ta = 25C , ICLK = 8 MHz *1
Ta = 25C , ICLK = 4 MHz *1
Ta = 25C , ICLK = 1 MHz *1
Ta = 105C , ICLK = 12 MHz *2
Ta = 105 C , ICLK = 8 MHz *2
Ta = 105 C , ICLK = 4 MHz *2
Ta = 105 C , ICLK = 1 MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the actual
measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.18
Voltage dependency in middle-speed operating mode (reference data)
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RA4M1 Group
2. Electrical Characteristics
1.6
Ta = 105C , ICLK = 1 MHz * 2
1.4
1.2
Ta = 25 C , ICLK = 1 MHz * 1
ICC (mA)
1.0
0.8
0.6
0.4
0.2
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
Ta = 25 C, ICLK = 1 MHz *1
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.19
Voltage dependency in Low-speed mode (reference data)
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Oct 8, 2019
Page 48 of 130
RA4M1 Group
2. Electrical Characteristics
6
5
Ta = 105C, ICLK = 4 MHz*2
ICC (mA)
4
3
Ta = 25C, ICLK = 4 MHz*1
Ta = 105C, ICLK = 1 MHz*2
2
Ta = 25C, ICLK = 1 MHz*1
1
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
Ta = 25C, ICLK = 4 MHz *1
*1
Ta = 25C, ICLK = 1 MHz
Ta = 105C, ICLK = 4 MHz *2
Ta = 105C, ICLK = 1 MHz*2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.20
Voltage dependency in low-voltage mode (reference data)
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RA4M1 Group
2. Electrical Characteristics
55.0
Ta = 105C, ICLK = 32 MHz*2
50.0
45.0
40.0
ICC ( A)
35.0
30.0
25.0
20.0
Ta = 25 C, ICLK = 32 MHz* 1
15.0
10.0
5.0
0.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VCC (V)
Ta = 25 C, ICLK = 32 MHz *1
Ta = 105C , ICLK = 32 MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper limit samples during product evaluation.
Figure 2.21
Table 2.12
Voltage dependency in Subosc-speed mode (reference data)
Operating and standby current (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
Software Standby
mode*2
Ta = 25°C
Note 2.
Note 3.
Note 4.
Typ*4
ICC
Max
Unit
Test conditions
μA
-
0.8
4.5
Ta = 55°C
1.3
7.1
Ta = 85°C
3.5
20.2
Ta = 105°C
Note 1.
Symbol
8.7
53.7
Increment for RTC operation with
low-speed on-chip oscillator*3
0.5
-
-
Increment for RTC operation with
sub-clock oscillator*3
0.4
-
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
1.2
-
SOMCR.SODRV[1:0] are 00b
(Normal mode)
Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
The IWDT and LVD are not operating.
Includes the current of sub-oscillation circuit or low-speed on-chip oscillator.
VCC = 3.3 V.
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Page 50 of 130
RA4M1 Group
2. Electrical Characteristics
100
ICC (mA)
ICC (A)
10
1
0.1
-40
-20
0
20
40
Ta ( C)
60
80
100
Average value of the tested middle samples during product evaluation.
Average value of the tested upper-limit samples during product evaluation.
Figure 2.22
Table 2.13
Temperature dependency in Software Standby mode all SRAM (reference data)
Operating and standby current (3)
Conditions: VCC = AVCC0 = 0V, VBATT = 1.6 to 3.6 V, VSS = AVSS0 = 0V
Parameter
Supply
current*1
Note 1.
RTC operation
when VCC is off
Ta = 25°C
Symbol
Typ
Max
Unit
Test conditions
ICC
μA
VBATT = 2.0 V
SOMCR.SORDRV[1:0] = 11b
(Low power mode 3)
0.8
-
Ta = 55°C
0.9
-
Ta = 85°C
1.0
-
Ta = 105°C
1.1
-
Ta = 25°C
0.9
-
Ta = 55°C
1.0
-
Ta = 85°C
1.1
-
Ta = 105°C
1.2
-
Ta = 25°C
1.5
-
Ta = 55°C
1.7
-
Ta = 85°C
2.0
-
Ta = 105°C
2.2
-
Ta = 25°C
1.6
-
Ta = 55°C
1.8
-
Ta = 85°C
2.1
-
Ta = 105°C
2.3
-
VBATT = 3.3 V
SOMCR.SORDRV[1:0] = 11b
(Low power mode 3)
VBATT = 2.0 V
SOMCR.SORDRV[1:0] = 00b
(Normal mode)
VBATT = 3.3 V
SOMCR.SORDRV[1:0] = 00b
(Normal mode)
Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up
MOSs are in the off state.
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RA4M1 Group
2. Electrical Characteristics
10
ICC ( A)
Normal drive capacity*1
1
Low drive capacity*1
0
-40
-20
0
20
40
Ta ( C)
Low drive capacity*1
60
80
100
120
Normal drive capacity*1
Note 1. Average value of the tested middle sample during product evaluation
.
Figure 2.23
Temperature dependency of RTC operation with VCC off (reference data)
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RA4M1 Group
Table 2.14
2. Electrical Characteristics
Operating and standby current (4)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V, VREFH0 = 2.7 V to AVCC0
Parameter
Analog power
supply current
During A/D conversion (at high-speed conversion)
Symbol
Min
Typ
Max
Unit
Test
conditions
IAVCC
-
-
3.0
mA
-
-
-
1.0
mA
-
-
0.4
0.8
mA
-
-
-
1.0
μA
-
-
-
150
μA
-
-
-
60
nA
-
-
50
100
μA
-
During A/D conversion (at low-power conversion)
During D/A conversion (per
channel)*1
Waiting for A/D and D/A conversion (all units)*6
Reference
power supply
current
During A/D conversion
IREFH0
Waiting for A/D conversion (all units)
During D/A conversion
IREFH
Waiting for D/A conversion (all units)
-
-
100
μA
-
ITNS
-
75
-
μA
-
ICMPLP
-
15
-
μA
-
Comparator High-speed mode
-
10
-
μA
-
Comparator Low-speed mode
-
2
-
μA
-
Temperature sensor
Low-Power
Analog
Comparator
operating
current
Window mode
Comparator Low-speed mode using DAC8
Operational
Amplifier
operating
current
Low power mode
High-speed mode
-
820
-
μA
-
2.5
4.0
μA
-
2 units operating
-
4.5
8.0
μA
-
3 units operating
-
6.5
11.0
μA
-
4 units operating
-
8.5
14.0
μA
-
1 unit operating
IAMP
1 unit operating
-
140
220
μA
-
2 units operating
-
280
410
μA
-
3 units operating
-
420
600
μA
-
4 units operating
LCD operating
current
USB operating
current
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
-
560
780
μA
-
External resistance division method
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice
ILCD1*5
-
0.34
-
μA
-
Internal voltage boosting method (VLCD.VLCD = 04)
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice
ILCD2*5
-
0.92
-
μA
-
Capacitor split method
fLCD = fSUB = 128 Hz, 1/3 bias, and 4-time slice
ILCD3*5
-
0.19
-
μA
-
During USB communication operation under the
following settings and conditions:
Host controller operation is set to full-speed mode
Bulk OUT transfer (64 bytes) × 1,
bulk IN transfer (64 bytes) × 1
Connect peripheral devices via a 1-meter USB
cable from the USB port.
IUSBH*2
-
4.3 (VCC)
0.9 (VCC_USB)*4
-
mA
-
During USB communication operation under the
following settings and conditions:
Device controller operation is set to full-speed mode
Bulk OUT transfer (64 bytes) × 1,
bulk IN transfer (64 bytes) × 1
Connect the host device via a 1-meter USB cable
from the USB port.
IUSBF*2
-
3.6 (VCC)
1.1 (VCC_USB)*4
-
mA
-
During suspended state under the following setting
and conditions:
Device controller operation is set to full-speed mode
(pull up the USB_DP pin)
Software standby mode
Connect the host device via a 1-meter USB cable
from the USB port.
ISUSP*3
-
0.35 (VCC)
170 (VCC_USB)*4
-
μA
-
The reference power supply current is included in the power supply current value for D/A conversion.
Current consumed only by the USBFS.
Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition
to the current consumed by the MCU during the suspended state.
When VCC = VCC_USB = 3.3 V.
Current flowing only to the LCD controller. Not including the current that flows through the LCD panel.
When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC140 module stop bit) is in the module-stop
state.
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2.2.10
2. Electrical Characteristics
VCC Rise and Fall Gradient and Ripple Frequency
Table 2.15
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = 0 to 5.5 V
Parameter
Power-on VCC
rising gradient
Note 1.
Note 2.
Voltage monitor 0 reset disabled at startup (normal
startup)
Symbol
Min
Typ
Max
Unit
Test conditions
SrVCC
0.02
-
2
ms/V
-
Voltage monitor 0 reset enabled at startup*1
0.02
-
-
SCI/USB boot mode*2
0.02
-
2
When OFS1.LVDAS = 0.
At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 2.16
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = VCC_USB = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit
(1.6 V).
When VCC change exceeds VCC ±10%, the allowable voltage change rising/falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Allowable ripple frequency
fr (VCC)
-
-
10
kHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.2
-
-
1
MHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.08
-
-
10
MHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.06
1.0
-
-
ms/V
When VCC change exceeds VCC ±10%
Allowable voltage change rising and
falling gradient
dt/dVCC
1/fr(VCC)
VCC
Figure 2.24
Vr(VCC)
Ripple waveform
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RA4M1 Group
2.3
2. Electrical Characteristics
AC Characteristics
2.3.1
Frequency
Table 2.17
Operation frequency value in high-speed operating mode
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
48
MHz
2.4 to 2.7 V
0.032768
-
16
2.7 to 5.5 V
0.032768
-
32
2.4 to 2.7 V
0.032768
-
16
2.7 to 5.5 V
-
-
48
2.4 to 2.7 V
-
-
16
2.7 to 5.5 V
-
-
32
2.4 to 2.7 V
-
-
16
2.7 to 5.5 V
-
-
64
2.4 to 2.7 V
-
-
16
2.7 to 5.5 V
-
-
64
2.4 to 2.7 V
-
-
16
Parameter
Operation
frequency
System clock (ICLK)*4
Flash interface clock
2.7 to 5.5 V
(FCLK)*1, *2, *4
Peripheral module clock
Peripheral module clock
Peripheral module clock
Peripheral module clock
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
(PCLKA)*4
(PCLKB)*4
(PCLKC)*3, *4
(PCLKD)*4
The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer
frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in
use.
See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, and FCLK.
The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed
operation, see Table 2.22, Clock timing.
Table 2.18
Operation frequency value in Middle-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
System clock
(ICLK)*4
2.7 to 5.5 V
Flash interface clock (FCLK)*1, *2, *4
Peripheral module clock
(PCLKA)*4
Peripheral module clock (PCLKB)*4
Peripheral module clock
(PCLKC)*3, *4
Peripheral module clock (PCLKD)*4
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
f
Min
Typ
Max*5
Unit
MHz
0.032768
-
12
2.4 to 2.7 V
0.032768
-
12
1.8 to 2.4 V
0.032768
-
8
2.7 to 5.5 V
0.032768
-
12
2.4 to 2.7 V
0.032768
-
12
1.8 to 2.4 V
0.032768
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
Page 55 of 130
RA4M1 Group
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
2. Electrical Characteristics
The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer
frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use.
See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK.
The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed
operation, see Table 2.22, Clock timing.
Table 2.19
Operation frequency value in Low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Typ
Max*4
Unit
f
0.032768
-
1
MHz
1.8 to 5.5 V
Flash interface clock (FCLK)*1, *3
1.8 to 5.5 V
0.032768
-
1
Peripheral module clock (PCLKA)*3
1.8 to 5.5 V
-
-
1
(PCLKB)*3
1.8 to 5.5 V
-
-
1
1.8 to 5.5 V
-
-
1
1.8 to 5.5 V
-
-
1
Peripheral module clock (PCLKC)*2, *3
Peripheral module clock
Note 4.
Min
System clock (ICLK)*3
Peripheral module clock
Note 1.
Note 2.
Note 3.
Symbol
(PCLKD)*3
The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory.
The lower-limit frequency of PCLKC is 1 MHz when the A/D converter is in use.
See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK.
The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed
operation, see Table 2.22, Clock timing.
Table 2.20
Operation frequency value in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Min
Typ
Max*5
Unit
0.032768
-
4
MHz
0.032768
-
4
-
-
4
-
-
4
1.6 to 5.5 V
-
-
4
1.6 to 5.5 V
-
-
4
Parameter
Operation
frequency
Symbol
(ICLK)*4
1.6 to 5.5 V
Flash interface clock (FCLK)*1, *2, *4
1.6 to 5.5 V
Peripheral module clock (PCLKA)*4
1.6 to 5.5 V
Peripheral module clock (PCLKB)*4
1.6 to 5.5 V
System clock
Peripheral module clock
(PCLKC)*3, *4
Peripheral module clock (PCLKD)*4
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
f
The lower-limit frequency of FCLK is 1 MHz while programming or erasing the flash memory. When using FCLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer
frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency
accuracy of the clock source.
The lower-limit frequency of PCLKC is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-Bit A/D converter is in
use.
See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK.
The maximum value of operation frequency does not include internal oscillator errors. For details on the range of guaranteed
operation, see Table 2.22, Clock timing.
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RA4M1 Group
Table 2.21
2. Electrical Characteristics
Operation frequency value in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
System clock (ICLK)*3
1.8 to 5.5 V
(FCLK)*1, *3
Min
Typ
Max
Unit
27.8528
32.768
37.6832
kHz
1.8 to 5.5 V
27.8528
32.768
37.6832
Peripheral module clock (PCLKA)*3
1.8 to 5.5 V
-
-
37.6832
(PCLKB)*3
1.8 to 5.5 V
-
-
37.6832
1.8 to 5.5 V
-
-
37.6832
1.8 to 5.5 V
-
-
37.6832
Flash interface clock
Peripheral module clock
Peripheral module clock (PCLKC)*2, *3
Peripheral module clock
Note 1.
Note 2.
Note 3.
Symbol
f
(PCLKD)*3
Programming and erasing the flash memory is not possible.
The 14-bit A/D converter cannot be used.
See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK.
2.3.2
Table 2.22
Clock Timing
Clock timing (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
EXTAL external clock input cycle time
tXcyc
50
-
-
ns
Figure 2.25
EXTAL external clock input high pulse width
tXH
20
-
-
ns
EXTAL external clock input low pulse width
tXL
20
-
-
ns
EXTAL external clock rising time
tXr
-
-
5
ns
EXTAL external clock falling time
tXf
-
-
5
ns
tEXWT
0.3
-
-
μs
-
fEXTAL
-
-
20
MHz
2.4 ≤ VCC ≤ 5.5
-
-
8
1.8 ≤ VCC < 2.4
-
-
1
1.6 ≤ VCC < 1.8
1
-
20
1
-
8
EXTAL external clock input wait
time*1
EXTAL external clock input frequency
Main clock oscillator oscillation frequency
fMAIN
MHz
2.4 ≤ VCC ≤ 5.5
1.8 ≤ VCC < 2.4
1
-
4
tMAINOSCWT
-
-
-*9
ms
-
LOCO clock oscillation frequency
fLOCO
27.8528
32.768
37.6832
kHz
-
LOCO clock oscillation stabilization time
tLOCO
-
-
100
μs
Figure 2.26
Main clock oscillation stabilization wait time (crystal)*9
1.6 ≤ VCC < 1.8
IWDT-dedicated clock oscillation frequency
fILOCO
12.75
15
17.25
kHz
-
MOCO clock oscillation frequency
fMOCO
6.8
8
9.2
MHz
-
MOCO clock oscillation stabilization time
tMOCO
-
-
1
μs
-
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RA4M1 Group
Table 2.22
2. Electrical Characteristics
Clock timing (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
HOCO clock oscillation frequency
fHOCO24
23.64
24
24.36
MHz
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
22.68
24
25.32
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
23.76
24
24.24
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
23.52
24
24.48
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
31.52
32
32.48
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
30.24
32
33.76
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
31.68
32
32.32
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
31.36
32
32.64
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
47.28
48
48.72
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
47.52
48
48.48
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
47.04
48
48.96
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
63.04
64
64.96
Ta = -40 to -20°C
2.4 ≤ VCC ≤ 5.5
63.36
64
64.64
Ta = -20 to 85°C
2.4 ≤ VCC ≤ 5.5
62.72
64
65.28
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
tHOCO24
tHOCO32
-
-
37.1
tHOCO48
-
-
43.3
fHOCO32
fHOCO48*4
fHOCO64*5
HOCO clock oscillation
stabilization time*6, *7
Except Low-Voltage
mode
Low-Voltage mode
PLL input frequency*2
PLL circuit oscillation
frequency*2
PLL clock oscillation stabilization time*8
μs
Figure 2.27
tHOCO64
-
-
80.6
tHOCO24
tHOCO32
tHOCO48
tHOCO64
-
-
100.9
fPLLIN
4
-
12.5
MHz
-
fPLL
24
-
64
MHz
-
tPLL
-
-
55.5
μs
Figure 2.29
PLL free-running oscillation frequency
fPLLFR
-
8
-
MHz
-
Sub-clock oscillator oscillation frequency
fSUB
-
32.768
-
kHz
-
Sub-clock oscillation stabilization time*3
tSUBOSC
-
-
-*3
s
Figure 2.30
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
Time until the clock can be used after the Main Clock Oscillator Stop bit (MOSCCR.MOSTP) is set to 0 (operating) when the
external clock is stable.
The VCC range that the PLL can be used is 2.4 to 5.5 V.
After changing the setting of the SOSCCR.SOSTP bit so that the sub-clock oscillator operates, only start using the sub-clock
after the sub-clock oscillation stabilization wait time elapses, that is greater than or equal to the value recommended by the
oscillator manufacturer.
The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.
The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.
This is a characteristic when HOCOCR.HCSTP bit is set to 0 (oscillation) in MOCO stop state.
When HOCOCR.HCSTP bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 μs.
Whether stabilization time has elapsed can be confirmed by OSCSF.HOCOSF.
This is a characteristic when PLLCR.PLLSTP bit is set to 0 (operation) in MOCO stop state.
When PLLCR.PLLSTP bit is set to 0 (operation) during MOCO oscillation, this specification is shortened by 1 μs.
When setting up the main clock, ask the oscillator manufacturer for an oscillation evaluation and use the results as the
recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or greater than the recommended
stabilization time. After changing the setting of the MOSCCR.MOSTP bit so that the main clock oscillator operates, read the
OSCSF.MOSCSF flag to confirm that it is 1, then start using the main clock.
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2. Electrical Characteristics
tXcyc
tXL
tXH
EXTAL external clock input
VCC × 0.5
tXr
Figure 2.25
tXf
EXTAL external clock input timing
LOCOCR.LCSTP
tLOCO
LOCO clock oscillator output
Figure 2.26
LOCO clock oscillation start timing
HOCOCR.HCSTP
tHOCOx*1
HOCO clock
Note 1.
Figure 2.27
x = 24, 32, 48, 64
HOCO clock oscillation start timing (started by setting HOCOCR.HCSTP bit)
MOSCCR.MOSTP
Main clock oscillator output
tMAINOSCWT
Main clock
Figure 2.28
Main clock oscillation start timing
PLLCR.PLLSTP
tPLL
PLL clock
Figure 2.29
PLL clock oscillation start timing (PLL is operated after main clock oscillation has settled)
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RA4M1 Group
2. Electrical Characteristics
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 2.30
Sub-clock oscillation start timing
MOCOCR.MCSTP
tMOCO
MOCO clock oscillator output
Figure 2.31
MOCO clock oscillation start timing
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RA4M1 Group
2.3.3
2. Electrical Characteristics
Reset Timing
Table 2.23
Reset timing
Symbol
Min
Typ
Max
Unit
Test
conditions
At power-on
tRESWP
3
-
-
ms
Figure 2.32
Other than above
tRESW
30
-
-
μs
Figure 2.33
tRESWT
-
0.7
-
ms
Figure 2.32
-
0.3
-
-
0.5
-
ms
Figure 2.33
-
0.05
-
-
0.6
-
ms
-
-
0.15
-
Parameter
RES pulse width
enable*1
Wait time after RES cancellation
(at power-on)
LVD0:
Wait time after RES cancellation
(during powered-on state)
LVD0: enable*1
Internal reset cancellation time (Watchdog
timer reset, SRAM parity error reset,
SRAM ECC error reset, Bus master MPU
error reset, Bus slave MPU error reset,
Stack pointer error reset, Software reset)
LVD0: enable*1
Note 1.
Note 2.
LVD0: disable*2
LVD0:
tRESWT2
disable*2
tRESWT3
LVD0: disable*2
When OFS1.LVDAS = 0.
When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 2.32
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Figure 2.33
Reset input timing
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2.3.4
2. Electrical Characteristics
Wakeup Time
Table 2.24
Timing of recovery from low power modes (1)
Symbol
Min
Typ
Max
Unit
Test
conditions
System clock source is
main clock oscillator
(20 MHz)*2
tSBYMC
-
2
3
ms
Figure 2.34
System clock source is
PLL (48 MHz) with main
clock oscillator*2
tSBYPC
-
2
3
ms
System clock source is
main clock oscillator
(20 MHz)*3
tSBYEX
-
14
25
μs
System clock source is
PLL (48 MHz) with main
clock oscillator*3
tSBYPE
-
53
76
μs
System clock source is HOCO*4
(HOCO clock is 32 MHz)
tSBYHO
-
43
52
μs
System clock source is HOCO*4
(HOCO clock is 48 MHz)
tSBYHO
-
44
52
μs
System clock source is HOCO*5
(HOCO clock is 64 MHz)
tSBYHO
-
82
110
μs
System clock source is MOCO
tSBYMO
-
16
25
μs
Parameter
Recovery time
from Software
Standby mode*1
High-speed
mode
Crystal
resonator
connected to
main clock
oscillator
External clock
input to main
clock oscillator
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
The HOCO Clock Wait Control Register (HOCOWTCR) is set to 05h.
The HOCO Clock Wait Control Register (HOCOWTCR) is set to 06h.
Table 2.25
Timing of recovery from low power modes (2)
Symbol
Min
Typ
Max
Unit
Test
conditions
System clock source is
main clock oscillator
(12 MHz)*2
tSBYMC
-
2
3
ms
Figure 2.34
System clock source is
PLL (24 MHz) with main
clock oscillator*2
tSBYPC
-
2
3
ms
System clock source is
main clock oscillator
(12 MHz)*3
tSBYEX
-
2.9
10
μs
System clock source is
PLL (24 MHz) with main
clock oscillator*3
tSBYPE
-
49
76
μs
System clock source is HOCO (24 MHz)
tSBYHO
-
38
50
μs
System clock source is MOCO
tSBYMO
-
3.5
5.5
μs
Parameter
Recovery time
from Software
Standby mode*1
Middle-speed
mode
Crystal
resonator
connected to
main clock
oscillator
External clock
input to main
clock oscillator
Note 1.
Note 2.
Note 3.
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
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Table 2.26
2. Electrical Characteristics
Timing of recovery from low power modes (3)
Parameter
Recovery time
from Software
Standby mode*1
Low-speed
mode
Note 2.
Note 3.
Unit
Test
conditions
Figure 2.34
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(1 MHz)*3
tSBYEX
-
28
50
μs
tSBYMO
-
25
35
μs
Timing of recovery from low power modes (4)
Recovery time
from Software
Standby mode*1
Low-voltage
mode
Crystal
resonator
connected to
main clock
oscillator
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
Symbol
Min
Typ
Max
Unit
Test
conditions
tSBYMC
-
2
3
ms
Figure 2.34
tSBYEX
-
108
130
μs
tSBYHO
-
108
130
μs
(4 MHz)*2
System clock source is
main clock oscillator
(4 MHz)*3
System clock source is HOCO
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source. When multiple oscillators are active, the recovery time can be determined by the
following expression.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.28
Timing of recovery from low power modes (5)
Symbol
Min
Typ
Max
Unit
Test
conditions
System clock source is sub-clock
oscillator (32.768 kHz)
tSBYSC
-
0.85
1
ms
Figure 2.34
System clock source is LOCO
(32.768 kHz)
tSBYLO
-
0.85
1.2
ms
Parameter
Recovery time
from Software
Standby mode*1
Note 1.
Max
System clock source is
main clock oscillator
(1 MHz)*2
Parameter
Note 2.
Note 3.
Typ
The division ratio of ICK, FCK, and PCKx is the minimum division ratio within the allowable frequency range. The recovery time
is determined by the system clock source.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.27
Note 1.
Min
Crystal
resonator
connected to
main clock
oscillator
System clock source is MOCO
Note 1.
Symbol
Subosc-speed mode
The sub-clock oscillator or LOCO itself continues to oscillate in Software Standby mode during Subosc-speed mode.
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2. Electrical Characteristics
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYPC, tSBYEX,
tSBYPE, tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 2.34
Software Standby mode cancellation timing
Table 2.29
Timing of recovery from low power modes (6)
Parameter
Recovery time from
Software Standby
mode to Snooze
mode
Symbol
Min
Typ
Max
Unit
Test conditions
High-speed mode
System clock source is HOCO
tSNZ
-
36
45
μs
Figure 2.35
Middle-speed mode
System clock source is MOCO
tSNZ
-
1.3
3.6
μs
Low-speed mode
System clock source is MOCO
tSNZ
-
10
13
μs
Low-voltage mode
System clock source is HOCO
tSNZ
-
87
110
μs
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RA4M1 Group
2. Electrical Characteristics
Oscillator
ICLK (except DTC, SRAM)
ICLK (to DTC, SRAM)*1
PCLK
IRQ
Software Standby mode
Snooze mode
tSNZ
Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.35
Software Standby mode to Snooze mode recovery timing
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RA4M1 Group
2.3.5
2. Electrical Characteristics
NMI and IRQ Noise Filter
Table 2.30
NMI and IRQ noise filter
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
NMI pulse width
tNMIW
200
-
-
ns
NMI digital filter disabled
tPcyc × 2 ≤ 200 ns
-
-
200
-
-
NMI digital filter enabled
tNMICK × 3 ≤ 200 ns
tNMICK × 3.5*2
-
-
200
-
-
tPcyc × 2*1
-
-
200
-
-
-
-
tPcyc ×
IRQ pulse width
tIRQW
2*1
tIRQCK ×
Note:
Note:
Note 1.
Note 2.
Note 3.
3.5*3
tPcyc × 2 > 200 ns
tNMICK × 3 > 200 ns
ns
IRQ digital filter disabled
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
IRQ digital filter enabled
tIRQCK × 3 ≤ 200 ns
tIRQCK × 3 > 200 ns
200 ns minimum in Software Standby mode.
If the clock source is switched, add 4 clock cycles of the switched source.
tPcyc indicates the cycle of PCLKB.
tNMICK indicates the cycle of the NMI digital filter sampling clock.
tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 12, 14, 15).
NMI
tNMIW
Figure 2.36
NMI interrupt input timing
IRQ
tIRQW
Figure 2.37
IRQ interrupt input timing
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RA4M1 Group
2.3.6
2. Electrical Characteristics
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing
Table 2.31
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing
Symbol
Min
Max
Unit
Test
conditions
Input data pulse width
tPRW
1.5
-
tPcyc
Figure 2.38
Input/output data cycle (P002, P003, P004, P007)
tPOcyc
10
-
us
tPOEW
3
-
tPcyc
Figure 2.39
tGTICW
1.5
-
tPDcyc
Figure 2.40
2.5
Figure 2.41
Parameter
I/O ports
POEG
POEG input trigger pulse width
GPT
Input capture pulse width
Single edge
Dual edge
AGT
AGTIO, AGTEE input cycle
2.7 V ≤ VCC ≤ 5.5 V
tACYC
*1
250
-
ns
2.4 V ≤ VCC < 2.7 V
500
-
ns
1.8 V ≤ VCC < 2.4 V
1000
-
ns
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTEE input high level
width, low-level width
AGTIO, AGTO, AGTOA, AGTOB
output cycle
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
tACKWH,
tACKWL
2000
-
ns
100
-
ns
200
-
ns
1.8 V ≤ VCC < 2.4 V
400
-
ns
1.6 V ≤ VCC < 1.8 V
800
-
ns
62.5
-
ns
2.4 V ≤ VCC < 2.7 V
125
-
ns
1.8 V ≤ VCC < 2.4 V
250
-
ns
1.6 V ≤ VCC < 1.8 V
500
-
ns
2.7 V ≤ VCC ≤ 5.5 V
tACYC2
Figure 2.41
ADC14
14-bit A/D converter trigger input pulse width
tTRGW
1.5
-
tPcyc
Figure 2.42
KINT
KRn (n = 00 to 07) pulse width
tKR
250
-
ns
Figure 2.43
Note 1.
Note:
Constraints on input cycle:
When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.
When switching the source clock: tPcyc × 6 < tACYC should be satisfied.
tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle
Port
tPRW
Figure 2.38
I/O ports input timing
POEG input trigger
tPOEW
Figure 2.39
POEG input trigger timing
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RA4M1 Group
2. Electrical Characteristics
Input capture
tGTICW
Figure 2.40
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.41
AGT I/O timing
ADTRG0
tTRGW
Figure 2.42
ADC14 trigger input timing
KR00 to KR07
tKR
Figure 2.43
2.3.7
Key interrupt input timing
CAC Timing
Table 2.32
CAC timing
Parameter
CAC
CACREF input pulse width
tPBcyc*1 ≤ tcac*2
tPBcyc*1 > tcac*2
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Symbol
Min
Typ
Max
Unit
Test
conditions
tCACREF
4.5 × tcac + 3 × tPBcyc*1
-
-
ns
-
5 × tcac + 6.5 × tPBcyc*1
-
-
ns
Page 68 of 130
RA4M1 Group
Note 1.
Note 2.
2. Electrical Characteristics
tPBcyc: PCLKB cycle.
tcac: CAC count clock source cycle.
2.3.8
SCI Timing
Table 2.33
SCI timing (1)
Parameter
SCI
Input clock cycle
Asynchronous
Symbol
Min
Max
Unit*1
Test
conditions
tScyc
4
-
tPcyc
Figure 2.44
6
-
Clock synchronous
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
-
20
ns
tSCKf
-
20
ns
tScyc
6
-
tPcyc
4
-
0.4
0.6
tScyc
-
20
ns
-
30
Input clock fall time
Output clock cycle
Asynchronous
Clock synchronous
Output clock pulse width
Output clock rise time
tSCKW
1.8 V or above
tSCKr
1.6 V or above
Output clock fall time
1.8 V or above
tSCKf
1.6 V or above
Note 1.
20
30
Transmit data delay
(master)
Clock
synchronous
1.8 V or above
Transmit data delay
(slave)
Clock
synchronous
2.7 V or above
-
55
2.4 V or above
-
60
1.8 V or above
-
100
1.6 V or above
-
125
Receive data setup
time (master)
Clock
synchronous
tTXD
-
1.6 V or above
2.7 V or above
tRXS
-
40
-
45
45
-
2.4 V or above
55
-
1.8 V or above
90
-
ns
ns
ns
ns
1.6 V or above
110
-
2.7 V or above
40
-
45
-
5
-
ns
40
-
ns
Receive data setup
time (slave)
Clock
synchronous
Receive data hold
time (master)
Clock synchronous
tRXH
Receive data hold
time (slave)
Clock synchronous
tRXH
1.6 V or above
Figure 2.45
ns
tPcyc: PCLKA cycle.
tSCKW
tSCKr
tSCKf
SCKn
(n = 0 to 2, 9)
tScyc
Figure 2.44
SCK clock input timing
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RA4M1 Group
2. Electrical Characteristics
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
(n = 0 to 2, 9)
Figure 2.45
Table 2.34
SCI input/output timing in clock synchronous mode
SCI timing (2) (1 of 2)
Parameter
Symbol
Min
Max
Unit
Test conditions
Simple
SPI
tSPcyc
4
65,536
tPcyc
Figure 2.46
SCK clock cycle output (master)
SCK clock cycle input (slave)
6
65,536
tSPCKWH
0.4
0.6
tSPCKWL
0.4
0.6
tSPcyc
-
20
ns
-
30
45
-
2.4 V or above
55
-
1.8 V or above
80
-
1.6 V or above
110
-
2.7 V or above
40
-
1.6 V or above
45
-
SCK clock high pulse width
SCK clock low pulse width
SCK clock rise and fall time
1.8 V or above
1.6 V or above
tSPCKr,
tSPCKf
Data input setup
time
2.7 V or above
tSU
Master
Slave
Data input hold time
Master
tH
Slave
33.3
-
40
-
tSPcyc
ns
ns
SS input setup time
tLEAD
1
-
tSPcyc
SS input hold time
tLAG
1
-
tSPcyc
tOD
ns
Data output delay
Master
Slave
1.8 V or above
-
40
1.6 V or above
-
50
2.4 V or above
-
65
1.8 V or above
-
100
1.6 V or above
Data output hold
time
Master
-
125
-10
-
2.4 V or above
-20
-
1.8 V or above
-30
-
2.7 V or above
tOH
1.6 V or above
Slave
Data rise and fall
time
Master
Slave
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
-
-
20
1.6 V or above
-
30
1.8 V or above
-
20
1.6 V or above
-
30
1.8 V or above
tDr, tDf
-40
-10
Figure 2.47 to
Figure 2.50
ns
ns
Page 70 of 130
RA4M1 Group
Table 2.34
2. Electrical Characteristics
SCI timing (2) (2 of 2)
Parameter
Symbol
Min
Max
Unit
Test conditions
Simple
SPI
Slave access time
tSA
-
10 (PCLKA >
32 MHz),
6 (PCLKA ≤
32 MHz)
tPcyc
Figure 2.49 and
Figure 2.50
Slave output release time
tREL
-
10 (PCLKA >
32 MHz),
6 (PCLKA ≤
32 MHz)
tPcyc
tSPCKr
tSPCKWH
VOH
SCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
SCKn
slave select input
VIL
(n = 0 to 2, 9)
tSPCKf
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.46
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 2, 9)
Figure 2.47
SCI simple SPI mode timing for master when CKPH = 1
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RA4M1 Group
2. Electrical Characteristics
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
MISOn
input
tH
MSB IN
tOH
DATA
LSB IN
tOD
MOSIn
output
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
(n = 0 to 2, 9)
Figure 2.48
SCI simple SPI mode timing for master when CKPH = 0
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 0 to 2, 9)
Figure 2.49
SCI simple SPI mode timing for slave when CKPH = 1
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RA4M1 Group
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
tREL
DATA
tH
MSB OUT
LSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0 to 2, 9)
Figure 2.50
Table 2.35
SCI simple SPI mode timing for slave when CKPH = 0
SCI timing (3)
Conditions: VCC = 2.7 to 5.5 V
Parameter
Simple I2C
(Standard mode)
Simple I2C
(Fast mode)
Note 1.
Note 2.
Symbol
Min
Max
Unit
Test conditions
SDA input rise time
tSr
-
1000
ns
Figure 2.51
SDA input fall time
tSf
-
300
ns
tIICcyc*1
SDA input spike pulse removal time
tSP
0
4×
Data input setup time
tSDAS
250
-
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb*2
-
400
pF
SDA input rise time
tSr
-
300
ns
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc*1
ns
Data input setup time
tSDAS
100
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb*1
-
400
pF
ns
ns
Figure 2.51
For all ports
except P408, use
PmnPFS.DSCR
of middle drive.
For port P408,
use
PmnPFS.DSCR1
/DSCR of middle
drive for IIC
fast-mode.
tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Cb indicates the total capacity of the bus line.
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RA4M1 Group
2. Electrical Characteristics
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
(n = 0 to 2, 9)
P*1
S*1
tSDAH
Note 1. S, P, and Sr indicate the following:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.51
P*1
Sr*1
tSDAS
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
SCI simple IIC mode timing
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Oct 8, 2019
Page 74 of 130
RA4M1 Group
2.3.9
2. Electrical Characteristics
SPI Timing
Table 2.36
SPI timing (1 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register
Parameter
SPI
RSPCK clock cycle
Master
Symbol
Min
Max
Unit*1
Test conditions
tSPcyc
2*4
4096
tPcyc
Figure 2.52
6
4096
tSPCKWH
(tSPcyc tSPCKrtSPCKf) / 2 3
-
3 × tPcyc
-
(tSPcyc tSPCKr tSPCKf) / 2 3
-
3 × tPcyc
-
Slave
RSPCK clock high
pulse width
Master
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
RSPCK clock rise
and fall time
Output
-
10
15
1.8 V or above
-
20
1.6 V or above
-
30
-
1
µs
10
-
ns
2.4 V or above
Master
Slave
tSPCKr,
tSPCKf
tSU
2.4 V or above
10
-
1.8 V or above
15
-
1.6 V or above
Data input hold time
20
-
Master
(RSPCK is PCLKA/2)
tHF
0
-
Master
(RSPCK is other than
above.)
tH
tPcyc
-
tH
20
-
tLEAD
-30 + N ×
tSpcyc*2
-
-50 + N ×
tSpcyc*2
-
6 × tPcyc
-
-30 + N ×
tSpcyc*3
-
6 × tPcyc
-
Slave
SSL setup time
Master
1.8 V or above
1.6 V or above
Slave
SSL hold time
Master
Slave
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
ns
-
2.7 V or above
Input
Data input setup time
ns
tLAG
ns
Figure 2.53 to
Figure 2.58
ns
ns
Page 75 of 130
RA4M1 Group
Table 2.36
2. Electrical Characteristics
SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in PmnPFS register
Symbol
Min
Max
Unit*1
Test conditions
tOD
-
14
ns
2.4 V or above
-
20
Figure 2.53 to
Figure 2.58
1.8 V or above
-
25
Parameter
SPI
Data output delay
Master
Slave
2.7 V or above
1.6 V or above
-
30
2.7 V or above
-
50
2.4 V or above
-
60
1.8 V or above
-
85
-
110
0
-
0
-
tTD
tSPcyc + 2 ×
tPcyc
8 × tSPcyc
+ 2 × tPcyc
6 × tPcyc
-
tDr, tDf
-
10
2.4 V or above
-
15
1.8 V or above
-
20
1.6 V or above
-
30
-
1
µs
ns
1.6 V or above
Data output hold time Master
tOH
Slave
Successive
transmission delay
Master
MOSI and MISO rise
and fall time
Output
Slave
2.7 V or above
Input
SSL rise and fall time
Output
Note 1.
Note 2.
Note 3.
Note 4.
ns
-
10
15
1.8 V or above
-
20
1.6 V or above
-
30
-
1
µs
-
2 × tPcyc + 100
ns
1.8 V or above
-
2 × tPcyc + 140
1.6 V or above
-
2 × tPcyc + 180
tSSLr,
tSSLf
Input
Slave output release time
ns
-
2.7 V or above
2.4 V or above
Slave access time
ns
2.4 V or above
tSA
-
2 × tPcyc + 100
1.8 V or above
-
2 × tPcyc + 140
1.6 V or above
-
2 × tPcyc + 180
2.4 V or above
tREL
Figure 2.57 and
Figure 2.58
ns
tPcyc: PCLKA cycle.
N is set as an integer from 1 to 8 by the SPCKD register.
N is set as an integer from 1 to 8 by the SSLND register.
The upper limit of RSPCK is 16 MHz.
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Page 76 of 130
RA4M1 Group
2. Electrical Characteristics
t SPCKr
t SPCKW H
V OH
RSPCKn
master select
output
VOH
VOL
tSPCKf
VOH
V OH
V OL
t SPCKW L
VOL
tSPcyc
t SPCKr
t SPCKW H
V IH
V IH
RSPCKn
slave select input
tSPCKf
V IH
V IL
V IH
V IL
t SPCKW L
V IL
t SPcyc
V O H = 0.7 × VCC, V OL = 0.3 × VCC, V IH = 0.7 × VCC, V IL = 0.3 × VCC
n = A or B
Figure 2.52
SPI clock timing
t TD
SSLn0 to
SSLn3
output
t LEA D
t LAG
t S SLr, t S SLf
RSPCKn
C PO L = 0
output
RSPCKn
C PO L = 1
output
tS U
M ISO n
input
tH
M SB IN
t D r, t D f
M O SIn
output
DATA
tO H
M SB O U T
LSB IN
M SB IN
tO D
D ATA
LSB O UT
ID LE
M SB O U T
n = A or B
Figure 2.53
SPI timing for master when CPHA = 0 and the bit rate is set to any value other than PCLKA/2
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RA4M1 Group
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, t SSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
t SU
MISOn
input
tHF
t HF
MSB IN
t Dr, t Df
MOSIn
output
LSB IN
DATA
t OH
MSB OUT
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 2.54
SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, t SSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tOH
MOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, t Df
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 2.55
SPI timing for master when CPHA = 1 and the bit rate is set to any value other than PCLKA/2
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Page 78 of 130
RA4M1 Group
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
n = A or B
tSU
MISOn
input
tHF
MSB IN
tOH
tH
DATA
LSB IN
tOD
MOSIn
output
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 2.56
SPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
t SA
t OH
MISOn
output
MSB OUT
t SU
MOSIn
input
t OD
DATA
t REL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
t Dr, tDf
DATA
LSB IN
MSB IN
n = A or B
Figure 2.57
SPI timing for slave when CPHA = 0
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Page 79 of 130
RA4M1 Group
2. Electrical Characteristics
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
MISOn
output
tOH
t OD
LSB OUT
(Last data)
MSB OUT
tSU
MOSIn
input
t REL
LSB OUT
DATA
MSB OUT
tDr, tDf
tH
MSB IN
DATA
LSB IN
MSB IN
n = A or B
Figure 2.58
2.3.10
Table 2.37
SPI timing for slave when CPHA = 1
IIC Timing
IIC timing (1 of 2)
Conditions: VCC = 2.7 to 5.5 V
Symbol
Min*1
Max
Unit
Test
conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc +
1300
-
ns
Figure 2.59
SCL input high pulse width
tSCLH
3 (6) × tIICcyc +
300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc +
300
-
ns
Parameter
IIC
(standard mode,
SMBus)
SCL, SDA input rise time
tSr
-
1,000
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc +
300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc +
4 × tPcyc + 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1 (5) × tIICcyc +
tPcyc + 300
-
ns
Repeated START condition input setup
time
tSTAS
1,000
-
ns
STOP condition input setup time
tSTOS
1,000
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
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RA4M1 Group
Table 2.37
2. Electrical Characteristics
IIC timing (2 of 2)
Conditions: VCC = 2.7 to 5.5 V
Symbol
Min*1
Max
Unit
SCL input cycle time
tSCL
6 (12) × tIICcyc +
600
-
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc +
300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc +
300
-
ns
SCL, SDA input rise time
tSr
-
300
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc +
300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc +
4 × tPcyc + 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1(5) × tIICcyc +
tPcyc + 300
-
ns
Repeated START condition input setup
time
tSTAS
300
-
ns
STOP condition input setup time
tSTOS
300
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
Parameter
IIC
(Fast mode)
Note:
Note 1.
Test
conditions
Figure 2.59
For all ports
except P408,
use
PmnPFS.DSC
R of middle
drive.
For port P408,
use
PmnPFS.DSC
R1/DSCR of
middle drive
for IIC fastmode.
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.
VIH
SDA0 to SDA1
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCL0 to SCL1
P*1
S*1
tSf
tSCLL
tSr
tSCL
Note 1.
Figure 2.59
P*1
Sr*1
tSDAS
tSDAH
S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition.
IIC bus interface input/output timing
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Page 81 of 130
RA4M1 Group
2.3.11
Table 2.38
2. Electrical Characteristics
SSIE Timing
SSIE timing
Conditions: VCC = 1.6 to 5.5 V
Parameter
SSIE
AUDIO_CLK input
frequency
2.7 V or above
Input clock period
Clock high pulse
width
1.8 V or above
Clock low pulse
width
1.8 V or above
Max
Unit
Test conditions
-
25
MHz
Figure 2.60
-
4
tO
250
-
ns
tI
250
-
ns
tHC
100
-
ns
200
-
1.6 V or above
100
-
200
-
tRC
-
25
ns
tDTR
-
65
ns
1.8 V or above
-
105
1.6 V or above
-
140
tLC
1.6 V or above
Clock rise time
2.7 V or above
Set-up time
Min
1.6 V or above
Output clock period
Data delay
Symbol
tAUDIO
2.7 V or above
tSR
1.8 V or above
1.6 V or above
Hold time
SSITXD0 output
delay from
SSILRCK0/SSIFS0
change time
1.8 V or above
-
Figure 2.61,
Figure 2.62
ns
140
-
tHTR
40
-
ns
TDTRW
-
105
ns
-
140
1.6 V or above
Figure 2.63
tRC
tHC
SSIBCK0
65
90
ns
tLC
tI, tO
Figure 2.60
SSIE clock input/output timing
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RA4M1 Group
2. Electrical Characteristics
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0,
SSIRXD0
(Input)
tSR
tHTR
SSILRCK0/SSIFS0,
SSITXD0
(Output)
tDTR
Figure 2.61
SSIE data transmit/receive timing (SSICR.BCKP = 0)
SSIBCK0
(Input or Output)
SSILRCK0/SSIFS0,
SSIRXD0
(Input)
tSR
tHTR
SSILRCK0/SSIFS0,
SSITXD0
(Output)
tDTR
Figure 2.62
SSIE data transmit/receive timing (SSICR.BCKP = 1)
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RA4M1 Group
2. Electrical Characteristics
SSILRCK0/SSIFS0
(Input)
SSITXD0 (Output)
tDTRW
MSB bit output delay from SSILRCK0/SSIFS0 change time for
slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0]
Figure 2.63
2.3.12
SSIE data output delay from SSILRCK0/SSIFS0 change time
CLKOUT Timing
Table 2.39
CLKOUT timing
Parameter
CLKOUT
Symbol
CLKOUT pin output
cycle*1
VCC = 2.7 V or above
tCcyc
CLKOUT pin low pulse
Note 1.
Note 2.
ns
Figure 2.64
-
250
-
15
-
VCC = 1.8 V or above
30
-
VCC = 1.6 V or above
150
-
VCC = 2.7 V or above
VCC = 2.7 V or above
tCH
tCL
VCC = 1.6 V or above
CLKOUT pin output fall time
Test conditions
-
VCC = 1.8 V or above
CLKOUT pin output rise time
Unit*1
62.5
VCC = 1.6 V or above
width*2
Max
125
VCC = 1.8 V or above
CLKOUT pin high pulse width*2
Min
15
-
30
-
150
-
-
12
VCC = 1.8 V or above
-
25
VCC = 1.6 V or above
-
50
VCC = 2.7 V or above
tCr
-
12
VCC = 1.8 V or above
-
25
VCC = 1.6 V or above
-
50
VCC = 2.7 V or above
tCf
ns
ns
ns
ns
When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and
the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to
55%.
When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division
ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
tCcyc
tCH
tCf
CLKOUT pin output
tCL
tCr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 2.64
CLKOUT output timing
R01DS0355EJ0100 Rev.1.00
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Page 84 of 130
RA4M1 Group
2.4
2. Electrical Characteristics
USB Characteristics
2.4.1
Table 2.40
USBFS Timing
USB characteristics
Conditions: VCC = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C (USBCLKSEL = 1), Ta = -40 to +105°C (USBCLKSEL = 0)
Parameter
Input
characteristics
Output
characteristics
Symbol
Min
Max
Unit
Test conditions
Input high level voltage
VIH
2.0
-
V
-
Input low level voltage
VIL
-
0.8
V
-
Differential input sensitivity VDI
0.2
-
V
|USB_DP - USB_DM |
Differential common mode
range
VCM
0.8
2.5
V
-
Output high level voltage
VOH
2.8
VCC_USB
V
IOH = -200 μA
Output low level voltage
VOL
0.0
0.3
V
IOL = 2 mA
Cross-over voltage
VCRS
1.3
2.0
V
ns
Figure 2.65,
Figure 2.66,
Figure 2.67
Rise time
FS
tr
LS
Fall time
FS
Rise/fall time ratio
FS
tf
LS
tr/tf
LS
4
20
75
300
4
20
75
300
90
111.11
80
125
ns
%
Output resistance
ZDRV
28
44
Ω
(Adjusting the resistance
of external elements is not
necessary.)
VBUS
characteristics
VBUS input voltage
VIH
VCC × 0.8
-
V
-
VIL
-
VCC × 0.2
V
-
Pull-up,
pull-down
Pull-down resistor
RPD
14.25
24.80
kΩ
-
Pull-up resistor
RPUI
0.9
1.575
kΩ
During idle state
RPUA
1.425
3.09
kΩ
During reception
D + sink current
IDP_SINK
25
175
μA
-
D - sink current
IDM_SINK
25
175
μA
-
DCD source current
IDP_SRC
7
13
μA
-
Data detection voltage
VDAT_REF
0.25
0.4
V
-
D + source voltage
VDP_SRC
0.5
0.7
V
Output current = 250 μA
D - source voltage
VDM_SRC
0.5
0.7
V
Output current = 250 μA
Battery Charging
Specification
Ver 1.2
USB_DP,
USB_DM
VCRS
90%
10%
tr
Figure 2.65
90%
10%
tf
USB_DP and USB_DM output timing
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Page 85 of 130
RA4M1 Group
2. Electrical Characteristics
Observation
point
DP
50 pF
DM
50 pF
Figure 2.66
Test circuit for Full-Speed (FS) connection
Observation
point
DP
200 pF to
600 pF
3.6 V
1.5 K
DM
200 pF to
600 pF Observation
point
Figure 2.67
2.4.2
Table 2.41
Test circuit for Low-Speed (LS) connection
USB External Supply
USB regulator
Parameter
VCC_USB supply current
Min
Typ
Max
Unit
Test conditions
VCC_USB_LDO ≥ 3.8V
-
-
50
mA
-
VCC_USB_LDO ≥ 4.5V
-
-
100
mA
-
3.0
-
3.6
V
-
VCC_USB supply voltage
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 86 of 130
RA4M1 Group
2.5
2. Electrical Characteristics
ADC14 Characteristics
VREFH0
VREFH0
5.5
5.5
A/D Conversion
Characteristics (1)
5.0
A/D Conversion
Characteristics (2)
4.0
3.0
2.7
2.4
A/D Conversion
Characteristics (3)
2.0
5.0
A/D Conversion
Characteristics (4)
4.0
3.0
2.7
2.4
A/D Conversion
Characteristics (5)
A/D Conversion
Characteristics (6)
2.0
1.8
1.6
1.0
A/D Conversion
Characteristics (7)
1.0
2.42.7
1.0
2.0
3.0
5.5
4.0
1.8
AVCC0
5.0
1.0
ADCSR.ADHSC = 0
Figure 2.68
Table 2.42
2.42.7
1.6 2.0
3.0
5.5
4.0
AVCC0
5.0
ADCSR.ADHSC = 1
AVCC0 to VREFH0 voltage range
A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Frequency
1
-
64
MHz
-
Analog input capacitance*2
Cs
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
-
2.5 (reference
data)
kΩ
High-precision channel
-
-
6.7 (reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
0.70
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.13
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Analog input resistance
Rs
Analog input voltage range
Ain
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKC = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
14-bit mode
Resolution
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 87 of 130
RA4M1 Group
Table 2.42
2. Electrical Characteristics
A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
time*1
Permissible signal
source impedance
Max. = 0.3 kΩ
Conversion
(Operation at
PCLKC = 64 MHz)
Offset error
Full-scale error
Min
Typ
Max
Unit
Test conditions
0.80
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.22
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
-
±2.0
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.43
A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Frequency
1
-
48
MHz
-
Analog input
capacitance*2
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
-
2.5 (reference data)
kΩ
High-precision channel
-
-
6.7 (reference data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
0.94
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.50
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Analog input resistance
Cs
Rs
Analog input voltage range
Ain
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKC = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 88 of 130
RA4M1 Group
Table 2.43
2. Electrical Characteristics
A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
-
-
14
Bit
-
1.06
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.63
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
-
±2.0
14-bit mode
Resolution
time*1
Permissible signal
source impedance
Max. = 0.3 kΩ
Conversion
(Operation at
PCLKC = 48 MHz)
Offset error
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.44
A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Frequency
1
-
32
MHz
-
Analog input
capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
-
2.5 (reference data)
kΩ
High-precision channel
-
-
6.7 (reference data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKC = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
Offset error
Full-scale error
-
-
12
Bit
-
1.41
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.25
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
-
±0.75
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 89 of 130
RA4M1 Group
Table 2.44
2. Electrical Characteristics
A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
1.59
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.44
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
-
±2.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKC = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
Offset error
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.45
A/D conversion characteristics (4) in low power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Frequency
1
-
24
MHz
-
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
-
2.5 (reference data)
kΩ
High-precision channel
-
-
6.7 (reference data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKC = 24 MHz)
Permissible
signal source
impedance Max.
= 1.1 kΩ
Offset error
Full-scale error
Quantization error
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
-
-
12
Bit
-
2.25
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.38
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±0.5
-
±0.75
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
-
LSB
-
Page 90 of 130
RA4M1 Group
Table 2.45
2. Electrical Characteristics
A/D conversion characteristics (4) in low power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
2.50
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.63
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±2.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKC = 24 MHz)
Permissible
signal source
impedance Max.
= 1.1 kΩ
Offset error
±18
LSB
High-precision channel
±24.0
LSB
Other than above
LSB
High-precision channel
Full-scale error
-
±3.0
±18
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.46
A/D conversion characteristics (5) in low power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Frequency
1
-
16
MHz
-
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
-
2.5 (reference data)
kΩ
High-precision channel
-
-
6.7 (reference data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
3.38
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.06
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±0.5
Analog input
capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKC = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
Offset error
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Page 91 of 130
RA4M1 Group
Table 2.46
2. Electrical Characteristics
A/D conversion characteristics (5) in low power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test conditions
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
14-bit mode
Resolution
Conversion time*1
(Operation at
PCLKC = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
Offset error
Full-scale error
-
-
14
Bit
-
3.75
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.44
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±2.0
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.47
A/D conversion characteristics (6) in low power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Min
Typ
Max
Unit
Test conditions
1
-
8
MHz
-
Analog input capacitance*2
Cs
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
Analog input resistance
Rs
-
-
3.8 (reference data)
kΩ
High-precision channel
-
-
8.2 (reference data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
6.75
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.13
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Analog input voltage range
Ain
12-bit mode
Resolution
Conversion time*1
(Operation at
PCLKC = 8 MHz)
Permissible signal
source
impedance Max.
= 5 kΩ
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Table 2.47
2. Electrical Characteristics
A/D conversion characteristics (6) in low power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Offset error
-
±1.0
Full-scale error
-
±1.5
Max
Unit
Test conditions
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±3.0
±8.0
LSB
High-precision channel
±12.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
7.50
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.88
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±4.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKC = 8 MHz)
Permissible signal
source
impedance Max.
= 5 kΩ
Offset error
Full-scale error
-
±6.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±12.0
±32.0
LSB
High-precision channel
±48.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.48
A/D conversion characteristics (7) in low power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
Min
Typ
Max
Unit
Test conditions
1
-
4
MHz
-
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
-
13.1 (reference data)
kΩ
High-precision channel
-
-
14.3 (reference data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
12-bit mode
Resolution
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Table 2.48
2. Electrical Characteristics
A/D conversion characteristics (7) in low power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
time*1
Conversion
(Operation at
PCLKC = 4 MHz)
Permissible
signal source
impedance Max.
= 9.9 kΩ
Offset error
Full-scale error
Min
Typ
Max
Unit
Test conditions
13.5
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
20.25
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±1.0
-
±1.5
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±3.0
±8.0
LSB
High-precision channel
±12.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
15.0
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
21.75
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±4.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKC = 4 MHz)
Permissible
signal source
impedance Max.
= 9.9 kΩ
Offset error
Full-scale error
-
±6.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±12.0
±32.0
LSB
High-precision channel
±48.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
Note 1.
Note 2.
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not
include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do
not include quantization errors.
The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for
the test conditions.
Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
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2. Electrical Characteristics
MCU
Analog input
ANn
Sensor
Rs
Cin
ADC
Cs
Analog input
ANn
Rs
Cin
Figure 2.69
Table 2.49
Equivalent circuit for analog input
14-Bit A/D converter channel classification
Classification
Channel
Conditions
Remarks
High-precision channel
AN000 to AN014
AVCC0 = 1.6 to 5.5 V
Normal-precision channel
AN016 to AN025
Pins AN000 to AN014 cannot be used
as general I/O, IRQ2, IRQ3 inputs,
and TS transmission, when the A/D
converter is in use
Internal reference voltage
input channel
Internal reference voltage
AVCC0 = 2.0 to 5.5 V
-
Temperature sensor input
channel
Temperature sensor output
AVCC0 = 2.0 to 5.5 V
-
Table 2.50
A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1
Parameter
Min
Typ
Max
Unit
Test conditions
Internal reference voltage input
channel*2
1.36
1.43
1.50
V
-
Frequency*3
1
-
2
MHz
-
5.0
-
-
μs
-
Sampling
Note 1.
Note 2.
Note 3.
Note 4.
time*4
The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit A/D
converter.
This is a parameter for ADC14 when the internal reference voltage is used as the high-potential reference voltage.
This is a parameter for ADC14 when the internal reference voltage is selected for an analog input channel in ADC14.
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2. Electrical Characteristics
3FFFh
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
0000h
Offset error
0
Figure 2.70
Analog input voltage
VREFH0
(full-scale)
Illustration of 14-bit A/D converter characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion
result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D
conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actually output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
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2.6
2. Electrical Characteristics
DAC12 Characteristics
Table 2.51
D/A conversion characteristics (1)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = VREFH or VREFL selected
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
-
-
12
bit
-
Resistive load
30
-
-
kΩ
-
Load capacitance
-
-
50
pF
-
Output voltage range
0.35
-
AVCC0 - 0.47
V
-
DNL differential nonlinearity error
-
±0.5
±1.0
LSB
-
INL integral nonlinearity error
-
±2.0
±8.0
LSB
-
Offset error
-
-
±20
mV
-
Full-scale error
-
-
±20
mV
-
Output impedance
-
5
-
Ω
-
Conversion time
-
-
30
μs
-
Typ
Max
Unit
Test conditions
Table 2.52
D/A conversion characteristics (2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = AVCC0 or AVSS0 selected
Parameter
Min
Resolution
-
-
12
bit
-
Resistive load
30
-
-
kΩ
-
Load capacitance
-
-
50
pF
-
Output voltage range
0.35
-
AVCC0 - 0.47
V
-
DNL differential nonlinearity error
-
±0.5
±2.0
LSB
-
INL integral nonlinearity error
-
±2.0
±8.0
LSB
-
Offset error
-
-
±30
mV
-
Full-scale error
-
-
±30
mV
-
Output impedance
-
5
-
Ω
-
Conversion time
-
-
30
μs
-
Table 2.53
D/A conversion characteristics (3)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = internal reference voltage selected
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
-
-
12
bit
-
Internal reference voltage (Vbgr)
1.36
1.43
1.50
V
-
Resistive load
30
-
-
kΩ
-
Load capacitance
-
-
50
pF
-
Output voltage range
0.35
-
Vbgr
V
-
DNL differential nonlinearity error
-
±2.0
±16.0
LSB
-
INL integral nonlinearity error
-
±8.0
±16.0
LSB
-
Offset error
-
-
±30
mV
-
Output impedance
-
5
-
Ω
-
Conversion time
-
-
30
μs
-
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2. Electrical Characteristics
Gain error
Full-scale error
Upper output limit
Integral nonlinearity error (INL)
Offset error
Output analog voltage
1-LSB width for ideal D/A conversion
characteristic
Ideal output voltage
Differential nonlinearity error
(DNL)
*1
Lower output limit
Actual D/A conversion characteristic
Offset error
Ideal output voltage
000h
Note 1.
Figure 2.71
D/A converter input code
FFFh
Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed.
Illustration of D/A converter characteristic terms
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion
characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion
characteristics and the width of the actual output voltage.
Offset error
Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the
ideal output voltage based on the input code.
Full-scale error
Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the
ideal output voltage based on the input code.
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2.7
2. Electrical Characteristics
TSN Characteristics
Table 2.54
TSN characteristics
Conditions: VCC = AVCC0 = 2.0 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Relative accuracy
-
-
±1.5
-
°C
2.4 V or above
-
-
±2.0
-
°C
Below 2.4 V
Temperature slope
-
-
-3.65
-
mV/°C
-
Output voltage (at 25°C)
-
-
1.05
-
V
VCC = 3.3 V
Temperature sensor start time
tSTART
-
-
5
μs
-
Sampling time
-
5
-
-
μs
-
2.8
OSC Stop Detect Characteristics
Table 2.55
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Detection time
tdr
-
-
1
ms
Figure 2.72
Main clock
Main clock
tdr
OSTDSR.OSTDF
tdr
OSTDSR.OSTDF
MOCO clock
PLL clock
ICLK
MOCO clock
ICLK
When the main clock is selected
When the PLL clock is selected
Figure 2.72
Oscillation stop detection timing
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2.9
2. Electrical Characteristics
POR and LVD Characteristics
Table 2.56
Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter
Voltage detection
level*1
Symbol
Min
Typ
Max
Unit
Test conditions
Power-on reset (POR)
VPOR
1.27
1.42
1.57
V
Figure 2.73,
Figure 2.74
Voltage detection circuit (LVD0)*2
Vdet0_0
3.68
3.85
4.00
V
Vdet0_1
2.68
2.85
2.96
Figure 2.75
At falling edge
VCC
Vdet0_2
2.38
2.53
2.64
Vdet0_3
1.78
1.90
2.02
V
Figure 2.76
At falling edge
VCC
V
Figure 2.77
At falling edge
VCC
Voltage detection circuit (LVD1)*3
Voltage detection circuit
Note 1.
Note 2.
Note 3.
Note 4.
(LVD2)*4
Vdet0_4
1.60
1.69
1.82
Vdet1_0
4.13
4.29
4.45
Vdet1_1
3.98
4.16
4.30
Vdet1_2
3.86
4.03
4.18
Vdet1_3
3.68
3.86
4.00
Vdet1_4
2.98
3.10
3.22
Vdet1_5
2.89
3.00
3.11
Vdet1_6
2.79
2.90
3.01
Vdet1_7
2.68
2.79
2.90
Vdet1_8
2.58
2.68
2.78
Vdet1_9
2.48
2.58
2.68
Vdet1_A
2.38
2.48
2.58
Vdet1_B
2.10
2.20
2.30
Vdet1_C
1.84
1.96
2.05
Vdet1_D
1.74
1.86
1.95
Vdet1_E
1.63
1.75
1.84
Vdet1_F
1.60
1.65
1.73
Vdet2_0
4.11
4.31
4.48
Vdet2_1
3.97
4.17
4.34
Vdet2_2
3.83
4.03
4.20
Vdet2_3
3.64
3.84
4.01
These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection
level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage
detection.
# in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
# in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
# in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
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Table 2.57
2. Electrical Characteristics
Power-on reset circuit and voltage detection circuit characteristics (2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Wait time after power-on
reset cancellation
LVD0:enable
tPOR
-
1.7
-
ms
-
LVD0:disable
tPOR
-
1.3
-
ms
-
Wait time after voltage
monitor 0,1,2 reset
cancellation
LVD0:enable*1
tLVD0,1,2
-
0.6
-
ms
-
LVD0:disable*2
tLVD1,2
-
0.2
-
ms
-
Response delay*3
tdet
-
-
350
μs
Figure 2.73,
Figure 2.74
Minimum VCC down time
tVOFF
450
-
-
μs
Figure 2.73,
VCC = 1.0 V or above
Power-on reset enable time
tW (POR)
1
-
-
ms
Figure 2.74,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is
enabled)
Td (E-A)
-
-
300
μs
Figure 2.76,
Figure 2.77
Hysteresis width (POR)
VPORH
-
110
-
mV
-
Hysteresis width (LVD0, LVD1 and LVD2)
VLVH
-
60
-
mV
LVD0 selected
-
100
-
mV
Vdet1_0 to Vdet1_2 selected.
-
60
-
Vdet1_3 to Vdet1_9 selected.
-
50
-
Vdet1_A or Vdet1_B selected.
-
40
-
Vdet1_C or Vdet1_F selected.
-
60
-
LVD2 selected
Note 1.
Note 2.
Note 3.
When OFS1.LVDAS = 0.
When OFS1.LVDAS = 1.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
Vdet0, Vdet1, and Vdet2 for the POR/LVD.
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
Figure 2.73
tdet
tPOR
Voltage detection reset timing
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2. Electrical Characteristics
VPOR
VCC
1.0 V
tW(POR)
Internal reset signal
(active-low)
*1
tdet
Note:
Figure 2.74
tPOR
tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is being held
below the valid voltage (1.0 V).
When VCC turns on, maintain tW(POR) for 1.0 ms or more.
Power-on reset timing
tVOFF
VCC
VLVH
Vdet0
Internal reset signal
(active-low)
tdet
Figure 2.75
tdet
tLVD0
Voltage detection circuit timing (Vdet0)
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2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tdet
tLVD1
When LVD1CR0.RN = 1
tLVD1
Figure 2.76
Voltage detection circuit timing (Vdet1)
tVOFF
VCC
VLVH
Vdet2
LVCMPCR.LVD2E
LVD2
Comparator output
Td(E-A)
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.77
Voltage detection circuit timing (Vdet2)
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RA4M1 Group
2.10
2. Electrical Characteristics
VBATT Characteristics
Table 2.58
Battery backup function characteristics
Conditions: VCC = AVCC0 = 1.6V to 5.5V, VBATT = 1.6 to 3.6 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Voltage level for switching to battery backup (falling)
VDETBATT
1.99
2.09
2.19
V
Hysteresis width for switching to battery back up
VVBATTH
-
100
-
mV
Figure 2.78,
Figure 2.79
VCC-off period for starting power supply switching
tVOFFBATT
300
-
-
μs
-
Voltage detection level
VBATT_Power-on reset (VBATT_POR)
VVBATPOR
1.30
1.40
1.50
V
Figure 2.78,
Figure 2.79
Wait time after VBATT_POR reset time cancellation
tVBATPOR
-
-
3
mS
-
Level for detection of voltage drop on
the VBATT pin (falling)
VDETBATLVD
2.11
2.2
2.29
V
Figure 2.80
1.92
2
2.08
V
VBTLVDLVL[1:0] = 10b
VBTLVDLVL[1:0] = 11b
Hysteresis width for VBATT pin LVD
VVBATLVDTH
-
50
-
mV
VBATT pin LVD operation stabilization time
td_vbat
-
-
300
μs
Figure 2.80
VBATT pin LVD response delay time
tdet_vbat
-
-
350
μs
Allowable voltage change rising/falling gradient
dt/dVCC
1.0
-
-
ms/V
-
VCC voltage level for access to the VBATT backup registers
V_BKBATT
1.8
-
-
V
-
Note:
The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum value of the
voltage level for switching to battery backup (VDETBATT).
VLVH
Vdet0
VCC
VVBATH
VDETBATT
VPOR
VBATT
VVBATPOR
Internal reset signal
(active-low)
VCC supplied
Figure 2.78
tdet tLVD0
tdet
Backup power area
VBATT supplied
VCC supplied
Power supply switching and LVD0 reset timing
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2. Electrical Characteristics
VCC
VVBATH
VDETBATT
VBATT
VVBATPOR
VBATT_POR
(active-low)
tVBATPOR
Backup power area
VCC supplied
Figure 2.79
VBATT supplied
not supplied
VCC supplied
VBATT_POR reset timing
VBATT
VVBATLVDTH
VDETBATLVD
VBTCR2.VBTLVDEN
Td_vbat
VBATT pin LVD
Comparator output
VBTCMPCR.VBTCMPE
VBTSR.VBTBLDF
tdet_vbat
Figure 2.80
tdet_vbat
VBATT pin voltage detection circuit timing
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RA4M1 Group
Table 2.59
2. Electrical Characteristics
VBATT-I/O characteristics
Parameter
VBATWIOn I/O
output
characteristics
(n = 0 to 2)
VCC > VDETBATT
VCC = 4.0 to 5.5 V
VCC = 2.7 to 4.0 V
Symbol
Min
Typ
Max
Unit
Test conditions
VOH
VCC - 0.8
-
-
V
IOH = -200 µA
VOL
-
-
0.8
IOL = 200 µA
VOH
VCC - 0.5
-
-
IOH = -100 µA
VOL
-
-
0.5
IOL = 100 µA
VCC = VDETBATT to 2.7 V VOH
VCC < VDETBATT
VBATT = 2.7 to 3.6 V
VBATT = 1.6 to 2.7 V
2.11
VCC - 0.3
-
-
IOH = -50 µA
VOL
-
-
0.3
IOL = 50 µA
VOH
VBATT - 0.5
-
-
IOH = -100 µA
VOL
-
-
0.5
IOL = 100 µA
VOH
VBATT - 0.3
-
-
IOH = -50 µA
VOL
-
-
0.3
IOL = 50 µA
CTSU Characteristics
Table 2.60
CTSU characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
-
TS pin capacitive load
Cbase
-
-
50
pF
-
Permissible output high current
ΣIoH
-
-
-24
mA
When the mutual
capacitance method
is applied
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RA4M1 Group
2.12
2. Electrical Characteristics
Segment LCD Controller Characteristics
2.12.1
Resistance Division Method
[Static Display Mode]
Table 2.61
Resistance division method LCD characteristics (1)
Conditions: VL4 ≤ VCC ≤ 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
LCD drive voltage
VL4
2.0
-
VCC
V
-
[1/2 Bias Method, 1/4 Bias Method]
Table 2.62
Resistance division method LCD characteristics (2)
Conditions: VL4 ≤ VCC ≤ 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
LCD drive voltage
VL4
2.7
-
VCC
V
-
[1/3 Bias Method]
Table 2.63
Resistance division method LCD characteristics (3)
Conditions: VL4 ≤ VCC ≤ 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
LCD drive voltage
VL4
2.5
-
VCC
V
-
2.12.2
Internal Voltage Boosting Method
[1/3 Bias Method]
Table 2.64
Internal voltage boosting method LCD characteristics
Conditions: VCC = 1.8 V to 5.5 V
Parameter
Symbol Conditions
LCD output voltage
variation range
VL1
C1 to C4*1 = 0.47 μF
C4*1
Doubler output voltage
VL2
C1 to
Tripler output voltage
VL4
C1 to C4*1 = 0.47 μF
Reference voltage
setup time*2
tVL1S
LCD output voltage
variation range*3
tVLWT
Note 1.
= 0.47 μF
C1 to C4*1 = 0.47 μF
Min
Typ
Max
Unit
Test
conditions
VLCD = 04h
0.90
1.0
1.08
V
-
VLCD = 05h
0.95
1.05
1.13
V
-
VLCD = 06h
1.00
1.10
1.18
V
-
VLCD = 07h
1.05
1.15
1.23
V
-
VLCD = 08h
1.10
1.20
1.28
V
-
VLCD = 09h
1.15
1.25
1.33
V
-
VLCD = 0Ah
1.20
1.30
1.38
V
-
VLCD = 0Bh
1.25
1.35
1.43
V
-
VLCD = 0Ch
1.30
1.40
1.48
V
-
VLCD = 0Dh
1.35
1.45
1.53
V
-
VLCD = 0Eh
1.40
1.50
1.58
V
-
VLCD = 0Fh
1.45
1.55
1.63
V
-
VLCD = 10h
1.50
1.60
1.68
V
-
VLCD = 11h
1.55
1.65
1.73
V
-
VLCD = 12h
1.60
1.70
1.78
V
-
VLCD = 13h
1.65
1.75
1.83
V
-
2 × VL1 - 0.1
2 × VL1 2 × VL1 V
-
3 × VL1 - 0.15 3 × VL1 3 × VL1 V
-
5
-
-
ms
Figure 2.81
500
-
-
ms
This is a capacitor that is connected between voltage pins used to drive the LCD.
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Note 2.
Note 3.
2. Electrical Characteristics
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF ±30%.
This is the time required to wait from when the reference voltage is specified using the VLCD register (or when the internal
voltage boosting method is selected (by setting the MDSET[1:0] bits in the LCDM0 register to 01b) if the default value reference
voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
[1/4 Bias Method]
Table 2.65
Internal voltage boosting method LCD characteristics
Conditions: VCC = 1.8 V to 5.5 V
Parameter
Symbol Conditions
LCD output voltage
variation range
VL1
Doubler output voltage
VL2
C1 to C5*1 = 0.47 μF
C1 to C5*1 = 0.47 μF
C5*1
Min
Typ
Max
Unit
Test
conditions
VLCD = 04h
0.90
1.0
1.08
V
-
VLCD = 05h
0.95
1.05
1.13
V
-
VLCD = 06h
1.00
1.10
1.18
V
-
VLCD = 07h
1.05
1.15
1.23
V
-
VLCD = 08h
1.10
1.20
1.28
V
-
VLCD = 09h
1.15
1.25
1.33
V
-
VLCD = 0Ah
1.20
1.30
1.38
V
-
VLCD = 0Bh
1.25
1.35
1.43
V
-
VLCD = 0Ch
1.30
1.40
1.48
V
-
2VL1 - 0.08
2VL1
2VL1
V
-
Tripler output voltage
VL3
C1 to
= 0.47 μF
3VL1 - 0.12
3VL1
3VL1
V
-
Quadruply output
voltage
VL4*4
C1 to C5*1 = 0.47 μF
4VL1 - 0.16
4VL1
4VL1
V
-
Reference voltage
setup time*2
tVL1S
5
-
-
ms
Figure 2.81
LCD output voltage
variation range*3
tVLWT
500
-
-
ms
Note 1.
Note 2.
Note 3.
Note 4.
C1 to C5*1 = 0.47 μF
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 μF ± 30%
This is the time required to wait from when the reference voltage is specified by using the VLCD register (or when the internal
voltage boosting method is selected (by setting the MDSET1 and MDSET0 bits in the LCDM0 register to 01b) if the default
value reference voltage is used) until voltage boosting starts (VLCON = 1).
This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON = 1).
VL4 must be 5.5 V or lower.
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RA4M1 Group
2.12.3
2. Electrical Characteristics
Capacitor Split Method
[1/3 Bias Method]
Table 2.66
Internal voltage boosting method LCD characteristics
Conditions: VCC = 2.2 V to 5.5 V
Parameter
Symbol Conditions
VL4 voltage*1
VL4
C1 to C4 = 0.47 μF*2
voltage*1
VL2
C1 to C4 = 0.47
μF*2
VL1 voltage*1
VL1
C1 to C4 = 0.47 μF*2
VL2
Capacitor split wait
Note 1.
Note 2.
time*1
tWAIT
Min
Typ
Max
Unit
Test
conditions
-
VCC
-
V
-
2/3 × VL4 - 0.07
2/3 × VL4
2/3 × VL4 + 0.07
V
-
1/3 × VL4 - 0.08
1/3 × VL4
1/3 × VL4 + 0.08
V
-
100
-
-
ms
Figure 2.81
This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1).
This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 μF ± 30%.
MDSET0,
MDSET1
VLCON
00b
01b or 10b
tVL1S
tVLWT, tWAIT
LCDON
Figure 2.81
LCD reference voltage setup time, voltage boosting wait time, and capacitor split wait time
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RA4M1 Group
2.13
2. Electrical Characteristics
Comparator Characteristics
Table 2.67
ACMPLP characteristics
Conditions: VCC = 1.8 to 5.5 V
Parameter
Reference voltage range
Min
Typ
Max
Unit
Test conditions
VREF
0
-
VCC-1.4
V
-
IVREFn (n= 0,1)
Window
mode*2
IVREF1
VREFH
1.4
-
VCC
V
-
IVREF0
VREFL
0
-
VCC-1.4
V
-
VI
0
-
VCC
V
-
-
1.36
1.44
1.50
V
-
Td
-
-
1.2
μs
-
-
5
μs
VCC = 3.0
Slew rate of input
signal > 50 mV/μs
-
-
2
μs
-
-
50
mV
Input voltage range
Internal reference voltage
Output delay
Symbol
Standard
mode
High-speed mode
Low-speed mode
Window mode
Offset voltage*1
High-speed mode
-
Low-speed mode
-
-
-
40
mV
-
Window mode
-
-
-
60
mV
-
Tcmp
100
-
-
μs
-
Operation stabilization wait time
Note 1.
Note 2.
-
When 8-bit DAC output is used as the reference voltage, the offset voltage increases up to 2.5 x VCC/256.
In window mode, be sure to satisfy the following condition: IVREF1 - IVREF0 ≥ 0.2 V.
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RA4M1 Group
2.14
2. Electrical Characteristics
OPAMP Characteristics
Table 2.68
OPAMP characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Common mode input
range
Vicm1
Low power mode
0.2
-
AVCC0 - 0.5
V
Vicm2
High-speed mode
0.3
-
AVCC0 - 0.6
V
Output voltage range
Vo1
Low power mode
0.1
-
AVCC0 - 0.1
V
Vo2
High-speed mode
0.1
-
AVCC0 - 0.1
V
Vioff
3σ
-10
-
10
mV
Input offset voltage
Unit
Open gain
Av
60
120
-
dB
Gain-bandwidth (GB)
product
GBW1
Low power mode
-
0.04
-
MHz
GBW2
High-speed mode
-
1.7
-
MHz
Phase margin
PM
CL = 20 pF
50
-
-
deg
Gain margin
GM
CL = 20 pF
10
-
-
dB
-
230
-
nV/√Hz
-
200
-
nV/√Hz
-
90
-
nV/√Hz
Equivalent input noise
Vnoise1
f = 1 kHz
Vnoise2
f = 10 kHz
Vnoise3
f = 1 kHz
Vnoise4
f = 2 kHz
Low power mode
High-speed mode
-
70
-
nV/√Hz
Power supply
reduction ratio
PSRR
-
90
-
dB
Common mode signal
reduction ratio
CMRR
-
90
-
dB
Stabilization wait time
Tstd1
CL = 20 pF
Only operational amplifier is
activated *1
Low power mode
650
-
-
μs
High-speed mode
13
-
-
μs
Low power mode
650
-
-
μs
Tstd4
CL = 20 pF
Operational amplifier and
reference current circuit are
activated simultaneously
High-speed mode
13
-
-
μs
Tset1
CL = 20 pF
Low power mode
-
-
750
μs
High-speed mode
-
-
13
μs
Low power mode
-
0.02
-
V/μs
Tstd2
Tstd3
Settling time
Tset2
Slew rate
Tslew1
CL = 20 pF
-
1.1
-
V/μs
Load current
Iload1
Low-power mode
-100
-
100
μA
Iload2
High-speed mode
-100
-
100
μA
-
-
20
pF
Tslew2
Load capacitance
Note 1.
High-speed mode
CL
When the operational amplifier reference current circuit is activated in advance.
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RA4M1 Group
2.15
2. Electrical Characteristics
Flash Memory Characteristics
2.15.1
Code Flash Memory Characteristics
Table 2.69
Code flash characteristics (1)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Reprogramming/erasure cycle*1
NPEC
1000
-
-
Times
-
tDRP
20*2, *3
-
-
Year
Ta = +85°C
Data hold time
Note 1.
Note 2.
Note 3.
After 1000 times of NPEC
The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000),
erasing can be done n times for each block. For instance, when 8-byte programming is performed 256 times for different
addresses in 2-KB blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled (overwriting is prohibited).
Characteristic when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
This result is obtained from reliability testing.
Table 2.70
Code flash characteristics (2)
High-speed operating mode
Conditions: VCC = 2.7 to 5.5 V
FCLK = 1 MHz
Parameter
Programming time
8-byte
FCLK = 32 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
tP8
-
116
998
-
54
506
μs
Erasure time
2-KB
tE2K
-
9.03
287
-
5.67
222
ms
Blank check time
8-byte
tBC8
-
-
56.8
-
-
16.6
μs
2-KB
tBC2K
-
-
1899
-
-
140
μs
Erase suspended time
tSED
-
-
22.5
-
-
10.7
μs
Startup area switching setting time
tSAS
-
21.7
585
-
12.1
447
ms
Access window time
tAWS
-
21.7
585
-
12.1
447
ms
OCD/serial programmer ID setting time
tOSIS
-
21.7
585
-
12.1
447
ms
Flash memory mode transition wait
time 1
tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait
time 2
tMS
5
-
-
5
-
-
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.
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RA4M1 Group
Table 2.71
2. Electrical Characteristics
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = 1.8 to 5.5 V, Ta = -40 to +85°C
FCLK = 1 MHz
Parameter
Symbol
Min
Typ
FCLK = 8 MHz
Max
Min
Typ
Max
Unit
Programming time
8-byte
tP8
-
157
1411
-
101
966
μs
Erasure time
2-KB
tE2K
-
9.10
289
-
6.10
228
ms
Blank check time
8-byte
tBC8
-
-
87.7
-
-
52.5
μs
tBC2K
-
-
1930
-
-
414
μs
Erase suspended time
2-KB
tSED
-
-
32.7
-
-
21.6
μs
Startup area switching setting time
tSAS
-
22.5
592
-
14.0
464
ms
Access window time
tAWS
-
22.5
592
-
14.0
464
ms
OCD/serial programmer ID setting time
tOSIS
-
22.5
592
-
14.0
464
ms
Flash memory mode transition wait time 1 tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait time 2 tMS
720
-
-
720
-
-
ns
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.
2.15.2
Data Flash Memory Characteristics
Table 2.72
Data flash characteristics (1)
Parameter
Reprogramming/erasure
Data hold time
cycle*1
After 10,000 times of NDPEC
Symbol
Min
NDPEC
100,000
1,000,000
tDDRP
20*2, *3
-
5*2, *3
-
-
Year
-
1*2, *3
-
Year
After 100,000 times of NDPEC
After 1,000,000 times of
NDPEC
Note 1.
Note 2.
Note 3.
Typ
Max
Unit
Test conditions
-
Times
-
-
Year
Ta = +85°C
Ta = +25°C
The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000),
erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different
addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasure is not enabled. Overwriting is prohibited.
Characteristics when using the flash memory programmer and the self-programming library provided by Renesas Electronics.
These results are obtained from reliability testing.
Table 2.73
Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = 2.7 to 5.5 V
FCLK = 4 MHz
Parameter
Programming time
1-byte
FCLK = 32 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
tDP1
-
52.4
463
-
42.1
387
μs
Erasure time
1-KB
tDE1K
-
8.98
286
-
6.42
237
ms
Blank check time
1-byte
tDBC1
-
-
24.3
-
-
16.6
μs
1-KB
tDBC1K
-
-
1872
-
-
512
μs
Suspended time during erasing
tDSED
-
-
13.0
-
-
10.7
μs
Data flash STOP recovery time
tDSTOP
5
-
-
5
-
-
μs
Note:
Note:
Note:
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 113 of 130
RA4M1 Group
Table 2.74
2. Electrical Characteristics
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = 1.8 to 5.5 V, Ta = -40 to +85°C
FCLK = 4 MHz
Parameter
Symbol
Min
Typ
FCLK = 8 MHz
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
-
94.7
886
-
89.3
849
μs
Erasure time
1-KB
tDE1K
-
9.59
299
-
8.29
273
ms
Blank check time
1-byte
tDBC1
-
-
56.2
-
-
52.5
μs
tDBC1K
-
-
2.17
-
-
1.51
ms
Suspended time during erasing
1-KB
tDSED
-
-
23.0
-
-
21.7
μs
Data flash STOP recovery time
tDSTOP
720
-
-
720
-
-
ns
Note:
Note:
Note:
2.16
Does not include the time until each operation of the flash memory is started after instructions are executed by software.
The lower-limit frequency of FCLK is 1 MHz during programming or erasing the flash memory. When using FCLK at below
4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set.
The frequency accuracy of FCLK must be ±3.5%. Confirm the frequency accuracy of the clock source.
Boundary Scan
Table 2.75
Boundary scan
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
TCK clock cycle time
tTCKcyc
100
-
-
ns
Figure 2.82
TCK clock high pulse width
tTCKH
45
-
-
ns
TCK clock low pulse width
tTCKL
45
-
-
ns
TCK clock rise time
tTCKr
-
-
5
ns
TCK clock fall time
tTCKf
-
-
5
ns
TMS setup time
tTMSS
20
-
-
ns
TMS hold time
tTMSH
20
-
-
ns
TDI setup time
tTDIS
20
-
-
ns
TDI hold time
tTDIH
20
-
-
ns
TDO data delay
tTDOD
-
-
70
ns
tBSSTUP
tRESWP
-
-
-
Boundary Scan circuit start up
Note 1.
time*1
Figure 2.83
Figure 2.84
Boundary scan does not function until power-on-reset becomes negative.
tTCKcyc
tTCKH
TCK
tTCKf
tTCKL
Figure 2.82
tTCKr
Boundary scan TCK timing
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 114 of 130
RA4M1 Group
2. Electrical Characteristics
TCK
tTMSS
tTMSH
tTDIS
tTDIH
TMS
TDI
tTDOD
TDO
Figure 2.83
Boundary scan input/output timing
VCC
RES
tBSSTUP
(= tRESWP)
Figure 2.84
2.17
Boundary scan
execute
Boundary scan circuit start up timing
Joint Test Action Group (JTAG)
Table 2.76
JTAG (debug) characteristics (1)
Conditions: VCC = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
TCK clock cycle time
tTCKcyc
80
-
-
ns
Figure 2.85
TCK clock high pulse width
tTCKH
35
-
-
ns
TCK clock low pulse width
tTCKL
35
-
-
ns
TCK clock rise time
tTCKr
-
-
5
ns
TCK clock fall time
tTCKf
-
-
5
ns
TMS setup time
tTMSS
16
-
-
ns
TMS hold time
tTMSH
16
-
-
ns
TDI setup time
tTDIS
16
-
-
ns
TDI hold time
tTDIH
16
-
-
ns
TDO data delay time
tTDOD
-
-
70
ns
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Figure 2.86
Page 115 of 130
RA4M1 Group
Table 2.77
2. Electrical Characteristics
JTAG (debug) characteristics (2)
Conditions: VCC = 1.6 to 2.4 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Figure 2.85
TCK clock cycle time
tTCKcyc
250
-
-
ns
TCK clock high pulse width
tTCKH
120
-
-
ns
TCK clock low pulse width
tTCKL
120
-
-
ns
TCK clock rise time
tTCKr
-
-
5
ns
TCK clock fall time
tTCKf
-
-
5
ns
TMS setup time
tTMSS
50
-
-
ns
TMS hold time
tTMSH
50
-
-
ns
TDI setup time
tTDIS
50
-
-
ns
TDI hold time
tTDIH
50
-
-
ns
TDO data delay time
tTDOD
-
-
150
ns
Figure 2.86
tTCKcyc
tTCKH
TCK
tTCKf
tTCKL
Figure 2.85
tTCKr
JTAG TCK timing
TCK
tTMSS
tTMSH
tTDIS
tTDIH
TMS
TDI
tTDOD
TDO
Figure 2.86
JTAG input/output timing
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 116 of 130
RA4M1 Group
2.17.1
Table 2.78
2. Electrical Characteristics
Serial Wire Debug (SWD)
SWD characteristics (1)
Conditions: VCC = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
80
-
-
ns
Figure 2.87
SWCLK clock high pulse width
tSWCKH
35
-
-
ns
SWCLK clock low pulse width
tSWCKL
35
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
SWDIO setup time
tSWDS
16
-
-
ns
SWDIO hold time
tSWDH
16
-
-
ns
SWDIO data delay time
tSWDD
2
-
70
ns
Table 2.79
Figure 2.88
SWD characteristics (2)
Conditions: VCC = 1.6 to 2.4 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
250
-
-
ns
Figure 2.87
SWCLK clock high pulse width
tSWCKH
120
-
-
ns
SWCLK clock low pulse width
tSWCKL
120
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
SWDIO setup time
tSWDS
50
-
-
ns
SWDIO hold time
tSWDH
50
-
-
ns
SWDIO data delay time
tSWDD
2
-
150
ns
Figure 2.88
tSWCKcyc
tSWCKH
SWCLK
tSWCKf
tSWCKL
Figure 2.87
tSWCKr
SWD SWCLK timing
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 117 of 130
RA4M1 Group
2. Electrical Characteristics
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 2.88
SWD input/output timing
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 118 of 130
RA4M1 Group
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
Information on the latest version of the package dimensions or mountings is shown in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
P-TFLGA100-7x7-0.65
RENESAS Code
PTLG0100JA-A
Previous Code
100F0G
MASS[Typ.]
0.1g
w S B
φ b1
D
φ× M S
φb
w S A
ZD
AB
e
A
e
A
AB
φ× M S
K
J
H
G
B
E
F
E
D
C
B
×4
y S
v
Index mark
(Laser mark)
Figure 1.1
S
ZE
A
1
2
3
Index mark
4
5
6
7
8
9
10
Reference
Symbol
Dimension in Millimeters
Min Nom
D
7.0
E
7.0
v
w
A
e
0.65
b
0.31 0.35
b1 0.385 0.435
x
y
ZD
0.575
ZE
0.575
Max
0.15
0.20
1.05
0.39
0.485
0.08
0.10
100-pin LGA
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 119 of 130
RA4M1 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP100-14x14-0.50
PLQP0100KB-B
—
0.6
HD
Unit: mm
*1 D
51
75
*2
E
50
100
HE
76
26
1
25
NOTE 4
Index area
NOTE 3
F
S
y S
*3
0.25
T
A1
Lp
L1
Detail F
Reference Dimensions in millimeters
Symbol
bp
M
Min
Nom
Max
D
13.9
14.0
14.1
14.1
E
13.9
14.0
A2
1.4
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
c
A2
A
e
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 1.2
100-pin LQFP
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 120 of 130
RA4M1 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
T
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 1.3
64-pin LQFP
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 121 of 130
RA4M1 Group
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN64-8x8-0.40
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0064LA-A
P64K8-40-9B5-3
0.16
D
33
48
DETAIL OF A PART
32
49
E
A
A1
17
64
c2
16
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
16
1
64
17
Dimension in Millimeters
Min
Nom
Max
D
7.95
8.00
8.05
E
7.95
8.00
8.05
A
0.80
A1
0.00
b
0.17
e
Lp
B
E2
32
49
0.30
33
ZD
e
b
x
M
0.40
0.50
x
0.05
y
0.05
1.00
ZE
c2
48
0.23
0.40
ZD
ZE
0.20
1.00
0.15
0.20
D2
6.50
E2
6.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Figure 1.4
64-pin QFN
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 122 of 130
RA4M1 Group
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP48-7x7-0.50
PLQP0048KB-B
—
0.2
HD
Unit: mm
*1 D
36
25
*2
48
HE
24
E
37
13
1
12
NOTE 4
Index area
NOTE 3
F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
S
Reference Dimensions in millimeters
Symbol
y S
*3
bp
0.25
M
A1
T
c
A2
A
e
Lp
L1
Detail F
Figure 1.5
Min
Nom
Max
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
1.4
HD
8.8
9.0
9.2
HE
8.8
9.0
9.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
48-pin LQFP
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 123 of 130
RA4M1 Group
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN48-7x7-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0048KB-A
48PJN-A
P48K8-50-5B4-6
0.13
D
25
36
DETAIL OF A PART
24
37
E
A
A1
13
48
c2
12
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
12
1
13
48
Dimension in Millimeters
Min
Nom
Max
D
6.95
7.00
7.05
E
6.95
7.00
7.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
ZE
37
24
36
25
ZD
e
b
x
M
0.25
0.30
0.50
0.30
0.40
0.50
x
0.05
y
0.05
ZD
0.75
ZE
0.75
c2
0.15
0.20
D2
5.50
E2
5.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Figure 1.6
48-pin QFN
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 124 of 130
RA4M1 Group
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN40-6x6-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0040KC-A
P40K8-50-4B4-5
0.09
D
21
30
DETAIL OF A PART
20
31
E
40
A
A1
11
c2
10
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
1
10
11
40
Dimension in Millimeters
Min
Nom
Max
D
5.95
6.00
6.05
E
5.95
6.00
6.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
0.25
0.30
0.40
x
y
0.05
0.75
ZE
20
31
30
21
ZD
e
b
Figure 1.7
x
M
c2
0.50
0.05
ZD
ZE
0.30
0.50
0.75
0.15
0.20
D2
4.50
E2
4.50
0.25
S AB
40-pin QFN
R01DS0355EJ0100 Rev.1.00
Oct 8, 2019
Page 125 of 130
Revision History
Rev.
Date
1.00
Oct 8, 2019
RA4M1Group Datasheet
Summary
First release
Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in
this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no
part of this document or content may be copied, reproduced, republished, posted, publicly displayed, encoded, translated,
transmitted or distributed in any other medium for publication or distribution or for any commercial enterprise, without prior
written consent from Renesas.
Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
CoreMark® is a registered trademark of the Embedded Microprocessor Benchmark Consortium.
Magic Packet™ is a trademark of Advanced Micro Devices, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States
and Japan.
Other brands and names mentioned in this document may be the trademarks or registered trademarks of their respective
holders.
Colophon
RA4M1 Group Datasheet
Publication Date:
Rev.1.00
Oct 8, 2019
Published by:
Renesas Electronics Corporation
Address List
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.
This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit
boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished
product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time
when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset
by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches
the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in
the device at this time may cause degradation of internal elements. Follow the guideline for input signal during poweroff state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins
of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,
extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,
and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated
with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full
stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or
by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to
prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the
input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,
immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a
system-evaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia
Tel: +60-3-5022-1288, Fax: +60-3-5022-1290
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
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