Datasheet
Cover
S128 Microcontroller Group
Datasheet
Renesas Synergy™ Platform
Synergy Microcontrollers
S1 Series
The integrated module for Digital Addressable Lighting Interface (DALI) communications is
designed for compliance to IEC 62386 version 2 (DALI 2) when used with suitable software
and hardware.
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
Rev.1.10 Nov 2018
Features
S128 Microcontroller Group
Datasheet
Ultra low power 32-MHz Arm® Cortex®-M0+ core, up to 256-KB code flash memory, 24-KB SRAM, Digital
Addressable Lighting Interface, Capacitive Touch Sensing Unit, 14-bit A/D Converter, 8-bit D/A Converter, security
and safety features.
Features
■ Arm Cortex-M0+ Core
Arm®v6-M architecture
Maximum operating frequency: 32 MHz
Arm® Memory Protection Unit (Arm MPU) with 8 regions
Debug and Trace: DWT, BPU, CoreSight™ MTB-M0+
CoreSight Debug Port: SW-DP
■ Memory
Up to 256-KB code flash memory
4-KB data flash memory (100,000 erase/write cycles)
Up to 24-KB SRAM
Memory protection units
128-bit unique ID
■ Connectivity
USB 2.0 Full-Speed (USBFS) module
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 3
- UART
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
Controller Area Network (CAN) module
Digital Addressable Lighting Interface (DALI)
■ Analog
14-bit A/D Converter (ADC14)
8-bit D/A Converter (DAC8) × 3
High-Speed Analog Comparator (ACMPHS) × 3
Low-Power Analog Comparator (ACMPLP) × 2
Operational Amplifier (OPAMP) × 4
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-bit (GPT32)
General PWM Timer 16-bit High Resolution (GPT16H) × 3
General PWM Timer 16-bit (GPT16) × 3
Asynchronous General-Purpose Timer (AGT) × 2
Watchdog Timer (WDT)
■ Safety
Error Correction Code (ECC) in SRAM
SRAM parity error check
Flash area protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO readback level detection
Register write protection
Main oscillator stop detection
Illegal memory access
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■ System and Power Management
Low power modes
Realtime clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection (LVD) with voltage settings
■ Security and Encryption
AES128/256
True Random Number Generator (TRNG)
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 5.5 V)
(1 to 4 MHz when VCC = 1.6 to 5.5 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
IWDT-dedicated on-chip oscillator (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General Purpose I/O Ports
Up to 53 input/output pins
- Up to 3 CMOS input
- Up to 50 CMOS input/output
- Up to 5V tolerant input/output
- Up to 2 high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = -40°C to +85°C
- 36-pin LGA (4 mm × 4 mm, 0.5 mm pitch)
Ta = -40°C to +105°C
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch)
- 32-pin LQFP (7 mm × 7 mm, 0.8 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 32-pin QFN (5 mm × 5 mm, 0.5 mm pitch)
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S128 Datasheet
1.
1. Overview
Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates an energy-efficient Arm Cortex®-M0+ 32-bit core that is particularly well suited for
cost-sensitive and low-power applications, with the following features:
Up to 256 KB code flash memory
24-KB SRAM
Capacitive Touch Sensing Unit (CTSU)
14-bit A/D Converter (ADC14)
8-bit D/A Converter (DAC8)
Security features.
1.1
Function Outline
Table 1.1
Arm core
Feature
Functional description
Arm Cortex-M0+ core
Maximum operating frequency: up to 32 MHz
Arm Cortex-M0+ core:
- Revision: r0p1-00rel0
- Armv6-M architecture profile
- Single-cycle integer multiplier.
Arm Memory Protection Unit (Arm MPU)
- Armv6 Protected Memory System Architecture
- 8 protect regions.
SysTick timer
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2
Memory
Feature
Functional description
Code flash memory
Maximum 256 KB of code flash memory. See section 42, Flash Memory in User’s Manual.
Data flash memory
4 KB of data flash memory. See section 42, Flash Memory in User’s Manual.
Option-setting memory
The option-setting memory determines the state of the MCU after a reset. See section 6,
Option-Setting Memory in User’s Manual.
SRAM
On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). See section
41, SRAM in User’s Manual.
Table 1.3
System (1 of 2)
Feature
Functional description
Operating mode
Two operating modes:
Single-chip mode
SCI boot mode.
See section 3, Operating Modes in User’s Manual.
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S128 Datasheet
Table 1.3
1. Overview
System (2 of 2)
Feature
Functional description
Resets
13 resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
SRAM ECC error reset
Bus master MPU error reset
Bus slave MPU error reset
CPU stack pointer error reset
Software reset.
See section 5, Resets in User’s Manual.
Low Voltage Detection (LVD)
The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin, and the
detection level can be selected using a software program. See section 7, Low Voltage
Detection (LVD) in User’s Manual.
Clock
Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
IWDT-dedicated on-chip oscillator
Clock out support.
See section 8, Clock Generation Circuit in User’s Manual.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated.
See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.
Interrupt Controller Unit (ICU)
The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in
User’s Manual.
Key Interrupt Function (KINT)
A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 18, Key Interrupt Function
(KINT) in User’s Manual.
Low Power Mode
Power consumption can be reduced in multiple ways, such as by setting clock dividers,
stopping modules, selecting power control mode in normal operation, and transitioning to low
power modes. See section 10, Low Power Modes in User’s Manual.
Register Write Protection
The register write protection function protects important registers from being overwritten
because of software errors. See section 11, Register Write Protection in User’s Manual.
Memory Protection Unit (MPU)
Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 14, Memory Protection Unit (MPU) in User’s Manual.
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The
refresh-permitted period can be set to refresh the counter and used as the condition for
detecting when the system runs out of control. See section 24, Watchdog Timer (WDT) in
User’s Manual.
Independent Watchdog Timer (IWDT)
The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates with an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a fail safe mechanism when the system runs out of control. The
IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the
count value in the registers. See section 25, Independent Watchdog Timer (IWDT) in User’s
Manual.
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S128 Datasheet
Table 1.4
1. Overview
Event Link
Feature
Functional description
Event Link Controller (ELC)
The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 16, Event Link Controller (ELC) in
User’s Manual.
Table 1.5
Direct memory access
Feature
Functional description
Data Transfer Controller (DTC)
A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 15, Data Transfer Controller (DTC) in User’s Manual.
Table 1.6
Timers
Feature
Functional description
General PWM Timer (GPT)
The General PWM Timer (GPT) is a 32-bit timer with one channel and a 16-bit timer with six
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms can be generated for controlling
brushless DC motors. The GPT can also be used as a general-purpose timer. See section 20,
General PWM Timer (GPT) in User’s Manual.
Port Output Enable for GPT (POEG)
Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 19, Port Output Enable for GPT (POEG) in
User’s Manual.
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 22, Asynchronous General Purpose Timer (AGT) in User’s Manual.
Realtime Clock (RTC)
The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 23, Realtime Clock (RTC) in User’s Manual.
Table 1.7
Communication interfaces (1 of 2)
Feature
Functional description
Serial Communications Interface
(SCI)
The Serial Communication Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 27, Serial Communications Interface (SCI) in User’s Manual.
Digital Addressable Lighting Interface
(DALI)
A Digital Addressable Lighting Interface (DALI) module is provided. DALI is an international
open lighting control communication protocol that includes dimming control of electronic
ballasts and LED lights from different manufacturers. The DALI interface module is designed to
allow compliance with international standard IEC62386-101 Edition 1.0/2.0 (DALI 2), that
includes software control. See section 28, Digital Addressable Lighting Interface (DALI) in
User’s Manual.
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S128 Datasheet
Table 1.7
1. Overview
Communication interfaces (2 of 2)
Feature
Functional description
I2C
The 2-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C
(Inter-Integrated Circuit) bus interface functions. See section 29, I2C Bus Interface (IIC) in
User’s Manual.
bus interface (IIC)
Serial Peripheral Interface (SPI)
Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, fullduplex synchronous serial communications with multiple processors and peripheral devices.
See section 31, Serial Peripheral Interface (SPI) in User’s Manual.
Control Area Network (CAN) module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 30, Controller Area Network (CAN) Module in User’s Manual.
USB 2.0 Full-Speed (USBFS) module
The USB 2.0 Full-Speed (USBFS) module is a USB controller that can operate as a device
controller. The module supports full-speed and low-speed transfer as defined in the Universal
Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of
the transfer types defined in the Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 5 pipes. Pipe 0 and
pipe 4 to pipe 7 can be assigned any endpoint number based on the peripheral devices used
for communication or based on the user system.
The MCU supports Battery Charging Specification revision 1.2. Because the MCU can be
powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply
3.3 V. See section 26, USB 2.0 Full-Speed Module (USBFS) in User’s Manual.
Table 1.8
Analog
Feature
Functional description
14-bit A/D Converter (ADC14)
A 14-bit successive approximation A/D converter is provided. Up to 21 analog input channels
are selectable. Temperature sensor output and internal reference voltage are selectable for
conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion
making it possible to optimize the tradeoff between speed and resolution in generating a digital
value. See section 33, 14-Bit A/D Converter (ADC14) in User’s Manual.
8-bit D/A Converter (DAC8)
An 8-bit D/A converter (DAC8) is provided. See section 34, 8-Bit D/A Converter (DAC8) in
User’s Manual.
Temperature Sensor (TSN)
The on-chip temperature sensor determines and monitors the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC14 for conversion and can be further used by the end
application. See section 35, Temperature Sensor (TSN) in User’s Manual.
High-Speed Analog Comparator
(ACMPHS)
The analog comparator compares a test voltage with a reference voltage and to provide a
digital output based on the result of conversion. Both the test voltage and the reference voltage
can be provided to the ACMPHS from internal sources (D/A converter output) and an external
source.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 37, HighSpeed Analog Comparator (ACMPHS) in User’s Manual.
Low-Power Analog Comparator
(ACMPLP)
The analog comparator compares a reference input voltage and analog input voltage. The
comparison result can be read by software and also be output externally. The reference input
voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin, an output from
internal D/A converter, or from the internal reference voltage (Vref) generated internally in the
MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed
mode decreases the response delay time, but increases current consumption. Setting lowspeed mode increases the response delay time, but decreases current consumption. See
section 38, Low-Power Analog Comparator (ACMPLP) in User’s Manual.
Operational Amplifier (OPAMP)
The operational amplifier amplifies small analog input voltages and outputs the amplified
voltages. A total of four differential operational amplifier units with two input pins and one
output pin are provided. See section 36, Operational Amplifier (OPAMP) in User’s Manual.
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S128 Datasheet
Table 1.9
1. Overview
Human machine interfaces
Feature
Functional description
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that a finger does
not come into direct contact with the electrode. See section 39, Capacitive Touch Sensing Unit
(CTSU) in User’s Manual.
Table 1.10
Data processing
Feature
Functional description
Cyclic Redundancy Check (CRC)
Calculator
The CRC calculator generates CRC codes to detect errors in the data. The bit order of CRC
calculation results can be switched for LSB-first or MSB-first communication. Additionally,
various CRC generation polynomials are available. The snoop function allows monitoring
reads from and writes to specific addresses. This function is useful in applications that require
CRC code to be generated automatically in certain events, such as monitoring writes to the
serial transmit buffer and reads from the serial receive buffer. See section 32, Cyclic
Redundancy Check (CRC) Calculator in User’s Manual.
Data Operation Circuit (DOC)
The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 40,
Data Operation Circuit (DOC) in User’s Manual.
Table 1.11
Security
Feature
Functional description
AES
See section 43, AES Engine in User’s Manual
True Random Number Generator
(TRNG)
See section 44, True Random Number Generator (TRNG) in User’s Manual
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S128 Datasheet
1.2
1. Overview
Block Diagram
Figure 1.1 shows a block diagram of the MCU superset, some individual devices within the group have a subset of the
features.
Memory
Bus
256 KB code flash
MPU
Arm Cortex-M0+
System
POR/LVD
MPU
4 KB data flash
Reset
NVIC
24 KB SRAM
Mode control
System timer
Test and DBG interface
DTC
Timers
AGT × 2
(H/M/L) OCO
Power control
DMA
GPT32 × 1
GPT16H × 3
GPT16 × 3
Clocks
MOSC/SOSC
Communication interfaces
ICU
CAC
KINT
Register write
protection
Human machine interfaces
CTSU
SCI × 3
DALI
IIC × 2
CAN × 1
RTC
SPI × 2
WDT/IWDT
Event link
USBFS
with Battery
Charging
revision1.2
Data processing
Analog
ELC
CRC
ADC14
TSN
Security
DOC
DAC8 × 3
ACMPHS × 3
ACMPLP × 2
OPAMP × 4
AES + TRNG
Figure 1.1
Block diagram
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S128 Datasheet
1.3
1. Overview
Part Numbering
Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.12 shows a
product list.
R 7 F S1 2 8 7 8 3 A 0 1 C F M # A A 1
Product identification code
Packing, terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
Package type
FM: LQFP 64 pins
FL: LQFP 48 pins
FJ: LQFP 32 pins
LM: LGA 36 pins
NE: QFN 48 pins
NG: QFN 32 pins
Quality ID
Software ID
Operating temperature
2: -40° C to 85° C
3: -40° C to 105° C
Code flash memory size
8: 256 KB
Feature set
7: Superset
Group name
28: S128 Group, Arm Cortex-M0+, 32 MHz
Series name
1: Ultra low power
Renesas Synergy™ family
Flash memory
Renesas microcontroller unit
Renesas
Figure 1.2
Table 1.12
Part numbering scheme
Product list
Product part number
Orderable part number
Package code
Code flash
Data flash
SRAM
Operating
temperature
R7FS128783A01CFM
R7FS128783A01CFM#AA1
PLQP0064KB-C
256 KB
4 KB
24 KB
-40 to +105°C
R7FS128783A01CFL
R7FS128783A01CFL#AA1
PLQP0048KB-B
-40 to +105°C
R7FS128783A01CNE
R7FS128783A01CNE#AC1
PWQN0048KB-A
-40 to +105°C
R7FS128782A01CLM
R7FS128782A01CLM#AC1
PWLG0036KA-A
-40 to +85°C
R7FS128783A01CFJ
R7FS128783A01CFJ#AA1
PLQP0032GB-A
-40 to +105°C
R7FS128783A01CNG
R7FS128783A01CNG#AC1
PWQN0032KB-A
-40 to +105°C
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S128 Datasheet
1.4
1. Overview
Function Comparison
Table 1.13
Function comparison
Parts number
R7FS128783A01CFM
R7FS128783A01CFL
R7FS128783A01CNE
Pin count
64
48
Package
LQFP
LQFP/QFN
R7FS128782A01CLM
Code flash memory
256 KB
Data flash memory
4 KB
SRAM
LGA
LQFP/QFN
4
4
3
2
1
1
16 KB
CPU clock
32 MHz
ICU
KINT
Yes
8
5
Event control
ELC
Yes
DMA
DTC
Yes
Timers
GPT32
1
GPT16H
3
3
GPT16
3
3
AGT
2
RTC
Yes
WDT/IWDT
Yes
SCI
3
DALI
Yes
IIC
2
2
1
1
SPI
2
2
2
1
13
10
3
2
12
9
CAN
Yes
USBFS
Analog
32
8 KB
ECC
Communication
36
24 KB
Parity
System
R7FS128783A01CFJ
R7FS128783A01CNG
ADC14
Yes
21
15
DAC8
3
ACMPHS
3
ACMPLP
2
OPAMP
4
3
TSN
Yes
HMI
CTSU
Data processing
CRC
Yes
DOC
Yes
Security
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28
21
AES and TRNG
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S128 Datasheet
1.5
1. Overview
Pin Functions
Table 1.14
Pin functions (1 of 3)
Function
Signal
I/O
Description
Power supply
VCC
Input
Power supply pin. Connect it to the system power supply. Connect this pin
to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the
pin.
VCL
I/O
Connect this pin to the VSS pin by the smoothing capacitor used to stabilize
the internal power supply. Place the capacitor close to the pin.
Clock
VSS
Input
Ground pin. Connect it to the system power supply (0 V).
XTAL
Output
EXTAL
Input
Pins for a crystal resonator. An external clock signal can be input through
the EXTAL pin.
XCIN
Input
XCOUT
Output
Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
CLKOUT
Output
Clock output pin
Operating mode control
MD
Input
Pins for setting the operating mode. The signal levels on these pins must
not be changed during operation mode transition at the time of release from
the reset state.
System control
RES
Input
Reset signal input pin. The MCU enters the reset state when this signal
goes low.
CAC
CACREF
Input
Measurement reference clock input pin
On-chip debug
SWDIO
I/O
Serial wire debug data input/output pin
SWCLK
Input
Serial wire clock pin
NMI
Input
Non-maskable interrupt request pin
IRQ0 to IRQ7
Input
Maskable interrupt request pins
GTETRGA,
GTETRGB
Input
External trigger input pin
GTIOC0A to
GTIOC6A,
GTIOC0B to
GTIOC6B
I/O
Input capture, output compare, or PWM output pin
GTIU
Input
Hall sensor input pin U
GTIV
Input
Hall sensor input pin V
GTIW
Input
Hall sensor input pin W
GTOUUP
Output
3-phase PWM output for BLDC motor control (positive U phase)
Interrupt
GPT
AGT
RTC
GTOULO
Output
3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP
Output
3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO
Output
3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP
Output
3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO
Output
3-phase PWM output for BLDC motor control (negative W phase)
AGTEE0, AGTEE1
Input
External event input enable
AGTIO0, AGTIO1
I/O
External event input and pulse output
AGTO0, AGTO1
Output
Pulse output
AGTOA0,
AGTOA1
Output
Output compare match A output
AGTOB0,
AGTOB1
Output
Output compare match B output
RTCOUT
Output
Output pin for 1-Hz/64-Hz clock
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 11 of 107
S128 Datasheet
1. Overview
Table 1.14
Pin functions (2 of 3)
Function
Signal
I/O
Description
SCI
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (clock synchronous mode)
RXD0, RXD1,
RXD9
Input
Input pins for received data (asynchronous mode/clock synchronous mode)
TXD0, TXD1,
TXD9
Output
Output pins for transmitted data (asynchronous mode/clock synchronous
mode)
CTS0_RTS0,
CTS1_RTS1,
CTS9_RTS9
I/O
Input/output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low
SCL0, SCL1,
SCL9
I/O
Input/output pins for the IIC clock (simple IIC)
SDA0, SDA1,
SDA9
I/O
Input/output pins for the IIC data (simple IIC)
SCK0, SCK1,
SCK9
I/O
Input/output pins for the clock (simple SPI)
MISO0, MISO1,
MISO9
I/O
Input/output pins for slave transmission of data (simple SPI)
MOSI0, MOSI1,
MOSI9
I/O
Input/output pins for master transmission of data (simple SPI)
SS0, SS1, SS9
Input
Chip-select input pins (simple SPI), active-low
DRX0
Input
Input pin for DALI received data
DTX0
Output
Output pin for DALI transmitted data
DALI
IIC
SPI
CAN
USBFS
Analog power supply
SCL0, SCL1
I/O
Input/output pins for clock
SDA0, SDA1
I/O
Input/output pins for data
RSPCKA,
RSPCKB
I/O
Clock input/output pin
MOSIA, MOSIB
I/O
Inputs or outputs data output from the master
MISOA, MISOB
I/O
Inputs or outputs data output from the slave
SSLA0, SSLB0
I/O
Input or output pin for slave selection
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output
Output pin for slave selection
CRX0
Input
Receive data
CTX0
Output
Transmit data
VSS_USB
Input
Ground pins
VCC_USB_LDO
Input
Power supply pin for USB LDO regulator
VCC_USB
I/O
Input: Power supply pin for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP
I/O
D+ I/O pin of the USB on-chip transceiver. This pin should be connected to
the D+ pin of the USB bus.
USB_DM
I/O
D- I/O pin of the USB on-chip transceiver. This pin should be connected to
the D- pin of the USB bus.
USB_VBUS
Input
USB cable connection monitor pin. This pin should be connected to VBUS
of the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a device controller.
AVCC0
Input
Analog block power supply pin
AVSS0
Input
Analog block power supply ground pin
VREFH0
Input
Reference power supply pin
VREFL0
Input
Reference power supply ground pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 12 of 107
S128 Datasheet
1. Overview
Table 1.14
Pin functions (3 of 3)
Function
Signal
I/O
Description
ADC14
AN000 to AN013,
AN016 to AN022
Input
Input pins for the analog signals to be processed by the A/D converter
ADTRG0
Input
Input pins for the external trigger signals that start the A/D conversion,
active-low
DAC8
DA0 to DA2
Output
Output pins for the analog signals to be processed by the D/A converter
Comparator output
VCOUT
Output
Comparator output pin
ACMPHS
IVREF0 to IVREF2
Input
Reference voltage input pin
IVCMP0 to
IVCMP2
Input
Analog voltage input pin
ACMPLP
CMPREF0,
CMPREF1
Input
Reference voltage input pins
CMPIN0, CMPIN1
Input
Analog voltage input pins
OPAMP
AMP0+ to AMP3+
Input
Analog voltage input pins
AMP0- to AMP3-
Input
Analog voltage input pins
AMP0O to AMP3O
Output
Analog voltage output pins
TS00 to TS22,
TS25 to TS29
Input
Capacitive touch detection pins (touch pins)
TSCAP
-
Secondary power supply pin for the touch driver
KINT
KR00 to KR07
Input
Key interrupt input pins
I/O ports
P000 to P004,
P010 to P015
I/O
General-purpose input/output pins
P100 to P113
I/O
General-purpose input/output pins
P200
Input
General-purpose input pin
P201, P204 to
P206, P212, P213
I/O
General-purpose input/output pins
P214, P215
Input
General-purpose input pins
P300 to P304
I/O
General-purpose input/output pins
P400 to P403,
P407 to P411
I/O
General-purpose input/output pins
P500 to P502
I/O
General-purpose input/output pins
P914, P915
I/O
General-purpose input/output pins
CTSU
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 13 of 107
S128 Datasheet
1.6
1. Overview
Pin Assignments
Figure 1.3
P100
P101
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110
P109
P108/SWDIO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 1.3 to Figure 1.8 show the pin assignments.
P500
49
32
P300/SWCLK
P501
50
31
P301
P502
51
30
P302
P015
52
29
P303
P014
53
28
P304
P013
54
27
P200
P012
55
26
P201/MD
AVCC0
56
25
RES
AVSS0
57
24
P204
P011/VREFL0
58
23
P205
P010/VREFH0
59
22
P206
P004
60
21
VCC_USB_LDO
P003
61
20
VCC_USB
P002
62
19
P914/USB_DP
P001
63
18
P915/USB_DM
P000
64
17
VSS_USB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P400
P401
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P409
P408
P407
R7FS128783A01CFM
Pin assignment for LQFP 64-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 14 of 107
P100
P101
P102
P103
P104
VSS
VCC
P112
P111
P110
P109
P108/SWDIO
35
34
33
32
31
30
29
28
27
26
25
P500
37
24
P300/SWCLK
P015
38
23
P301
P014
39
22
P302
P013
40
21
P200
P012
41
20
P201/MD
AVCC0
42
19
RES
AVSS0
43
18
P206
P011/VREFL0
44
17
VCC_USB_LDO
P010/VREFH0
45
16
VCC_USB
P002
46
15
P914/USB_DP
P001
47
14
P915/USB_DM
P000
48
13
VSS_USB
12
8
P212/EXTAL
P407
7
P213/XTAL
11
6
VSS
P408
5
P214/XCOUT
10
4
P215/XCIN
P409
3
VCL
9
2
P401
VCC
1
P400
R7FS128783A01CFL
25
26
27
28
29
30
31
32
P102
P103
P104
VSS
VCC
P112
P111
P110
P109
P108/SWDIO
33
34
35
P100
P101
36
Pin assignment for LQFP 48-pin
P500
P015
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P002
P001
37
24
38
23
44
17
45
16
46
15
47
14
P300/SWCLK
P301
P302
P200
P201/MD
RES
P206
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
39
22
40
21
41
20
P000
48
13
VSS_USB
18
12
11
10
9
8
7
6
5
19
P400
P401
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
4
R7FS128783A01CNE
3
43
2
42
1
Figure 1.4
1. Overview
36
S128 Datasheet
Figure 1.5
Pin assignment for QFN 48-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 15 of 107
S128 Datasheet
1. Overview
R7FS128782A01CLM
Figure 1.7
B
C
D
E
F
6
P015
P100
P112
P111
P108
/SWDIO
P300
/SWCLK
6
5
P014
P013
P101
P110
P200
VCC_USB
_LDO
5
4
AVCC0
P012
P102
P109
P201/MD VCC_USB
4
3
AVSS0
P011
/VREFL0
P103
P213
/XTAL
RES
P914
/USB_DP
3
2
P010
/VREFH0
P000
P001
P212
/EXTAL
P407
P915
/USB_DM
2
1
VCL
P215
/XCIN
VCC
P002
1
A
B
E
F
P214
VSS/
/XCOUT VSS_USB
C
D
P100
P101
P102
P103
P112
P110
P109
P108/SWDIO
24
23
22
21
20
19
18
17
Pin assignment for LGA 36-pin (top view, pad side down)
P015
25
16
P014
26
15
P300/SWCLK
P200
P013
27
14
P201/MD
P012
28
13
RES
AVCC0
29
12
VCC_USB_LDO
AVSS0
30
11
VCC_USB
P011/VREFL0
31
10
P914/USB_DP
P010/VREFH0
32
9
P915/USB_DM
1
2
3
4
5
6
7
8
VCL
P214/XCOUT
VSS/VSS_USB
P213/XTAL
P212/EXTAL
VCC
P407
R7FS128783A01CFJ
P215/XCIN
Figure 1.6
A
Pin assignment for LQFP 32-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 16 of 107
17
18
19
20
P102
P103
P112
P110
P109
P108/SWDIO
21
22
23
25
16
26
15
27
14
28
29
R7FS128783A01CNG
13
12
8
7
6
P300/SWCLK
P200
P201/MD
RES
VCC_USB_LDO
VCC_USB
P914/USB_DP
P915/USB_DM
VCL
P215/XCIN
P214/XCOUT
VSS/VSS_USB
P213/XTAL
P212/EXTAL
VCC
P407
5
9
4
10
32
3
11
31
2
30
1
P015
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P100
P101
1. Overview
24
S128 Datasheet
Figure 1.8
Pin assignment for QFN 32-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 17 of 107
S128 Datasheet
Pin Lists
TS18
IRQ4
GTIOC3A
_B
CTS1_RTS
1_B/SS1_B
TS17
P213
GTETRGA GTIOC0A
_D
_D
TXD1_A/
MOSI1_A/
SDA1_A
IRQ2
P212
AGTEE1 GTETRGB GTIOC0B
_D
_D
RXD1_A/
MISO1_A/
SCL1_A
IRQ3
-
-
-
-
-
-
P401
GTETRGA GTIOC6B
_B
_A
GTIOC6A
_A
CTX0_B
3
-
-
-
-
-
P402
GTIOC3B
_B
CRX0_B
4
-
-
-
-
-
P403
5
3
3
A1
1
1
VCL
6
4
4
B1
2
2
XCIN
P215
7
5
5
C1
3
3
XCOUT
P214
8
6
6
D1
4
4
VSS
9
7
7
D3
5
5
XTAL
10
8
8
D2
6
6
EXTAL
VCC
OPAMP
RXD1_B/
MISO1_B/
SCL1_B
1
2
DAC8
IRQ5
1
2
ADC14
IRQ0
TS19
1
2
SPI
TS20
RTC
SCL0_A
AGTIO1_
D
GPT
SCK0_B/
SCK1_B
CTS0_RTS SDA0_A
0_B/SS0_B/
TXD1_B/
MOSI1_B/
SDA1_B
P400
AGT
Interrupt
HMI
CTSU
ACMPHS, ACMPLP
Analogs
IIC
USBFS,CAN, DALI
Communication Interfaces
SCI
CACREF_
C
I/O ports
Power, System,
Clock, Debug,
CAC
QFN32
Timers
LQFP32
LGA36
QFN48
LQFP48
LQFP64
Pin number
GPT_OPS, POEG
1.7
1. Overview
11
9
9
E1
7
7
12
-
-
-
-
-
P411
AGTOA1 GTOVUP_ GTIOC6A
B
_B
TXD0_B/
MOSI0_B/
SDA0_B
MOSIA_B
TS07
IRQ4
13
-
-
-
-
-
P410
AGTOB1 GTOVLO_ GTIOC6B
B
_B
RXD0_B/
MISO0_B/
SCL0_B
MISOA_B
TS06
IRQ5
14
10
10
-
-
-
P409
GTOWUP GTIOC5A
_B
_B
TXD0_E/
MOSI0_E/
SDA0_E/
TXD9_A/
MOSI9_A/
SDA9_A
TS05
IRQ6
15
11
11
-
-
-
P408
GTOWLO_ GTIOC5B
B
_B
RXD9_A/
MISO9_A/
SCL9_A
TS04
IRQ7
16
12
12
E2
8
8
P407
AGTIO0_
C
SCL0_C
GTIOC0A RTC USB_VBU CTS0_RTS SDA0_B SSLB3_A ADTRG0_
_E
OUT
S
0_D/SS0_D
B
17
13
13
D1
4
4
18
14
14
F2
9
9
P915
USB_DM
19
15
15
F3
10
10
P914
USB_DP
20
16
16
F4
11
11
VCC_USB
21
17
17
F5
12
12
VCC_USB_
LDO
22
18
18
-
-
-
23
-
-
-
-
-
CLKOUT_A
P205
AGTO1
GTIV_A
24
-
-
-
-
-
CACREF_
A
P204
AGTIO1_
A
GTIW_A
25
19
19
E3
13
13
RES
26
20
20
E4
14
14
MD
27
21
21
E5
15
15
P200
28
-
-
-
-
-
P304
29
-
-
-
-
-
P303
GTIOC1B
_B
30
22
22
-
-
-
P302
GTOUUP_ GTIOC4A
A
_A
31
23
23
-
-
-
P301
AGTIO0_ GTOULO_ GTIOC4B
D
A
_A
TS03
VSS_USB
P206
GTIU_A
RXD0_D/
MISO0_D/
SCL0_D
SDA1_A SSLB1_A
GTIOC4A
_B
TXD0_D/
MOSI0_D/
SDA0_D/
CTS9_RTS
9_A/SS9_A
SCL1_A
GTIOC4B
_B
SCK0_D/
SCK9_A
SSLB0_A
SCL0_B RSPCKB_
A
TS01
IRQ0
TSCAP_
A
IRQ1
TS00
P201
NMI
GTIOC1A
_B
32
24
24
F6
16
16
SWCLK
P300
GTOUUP_ GTIOC0A
C
_A
33
25
25
E6
17
17
SWDIO
P108
GTOULO_ GTIOC0B
C
_A
34
26
26
D4
18
18
CLKOUT_B
P109
GTOVUP_ GTIOC1A
A
_A
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
TS02
CTS9_RTS
9_D/
SS9_D
SSLB3_B
TS08
IRQ5
SSLB2_B
TS09
IRQ6
SSLB1_B
CTX0_A
CTS9_RTS
9_B/SS9_B
SSLB0_B
SCK1_E/
TXD9_B/
MOSI9_B/
SDA9_B
MOSIB_B
TS10
Page 18 of 107
S128 Datasheet
1. Overview
-
P111
AGTOA0
37
29
29
C6
20
20
P112
AGTOB0
38
-
-
-
-
-
39
30
30
-
-
-
VCC
40
31
31
-
-
-
VSS
41
-
-
-
-
42
-
-
-
-
Interrupt
-
CTSU
D6
RSPCKB_
B
TS12
IRQ4
SSLB0_C
TSCAP_
C
GTIOC3A
_A
SCK0_C/
SCK9_B
GTIOC3B
_A
TXD0_C/
MOSI0_C/
SDA0_C/
SCK1_D
P113
GTIOC2A
_C
-
P107
GTIOC0A
_B
-
P106
GTIOC0B
_B
OPAMP
28
ACMPHS, ACMPLP
28
DAC8
36
IRQ3
MISOB_B
CRX0_A
HMI
TS11
CTS0_RTS
0_C/
SS0_C/
RXD9_B/
MISO9_B/
SCL9_B
GTOVLO_ GTIOC1B
A
_A
ADC14
P110
Analogs
SPI
19
IIC
19
USBFS,CAN, DALI
QFN32
D5
RTC
LQFP32
27
Communication Interfaces
GPT
LGA36
27
GPT_OPS, POEG
QFN48
35
AGT
LQFP48
I/O ports
LQFP64
Power, System,
Clock, Debug,
CAC
Timers
SCI
Pin number
VCOUT
KR07
SSLA3_A
AN016
43
-
-
-
-
-
P105
GTETRGA GTIOC1A
_C
_C
44
32
32
-
-
-
P104
GTETRGB GTIOC1B
_B
_C
45
33
33
C3
21
21
P103
46
34
34
C4
22
22
P102
AGTO0
47
35
35
C5
23
23
P101
48
36
36
B6
24
24
P100
49
37
37
-
-
-
P500
AN013
50
-
-
-
-
-
P501
AN012
AMP3+
51
-
-
-
-
-
P502
AN011
AMP3-
52
38
38
A6
25
25
P015
AN010
DA1_A
IVCMP1
AMP2+
TS28
53
39
39
A5
26
26
P014
AN009
DA0
IVREF1
AMP2-
TS29
54
40
40
B5
27
27
P013
AN008
IVCMP0
AMP1+
55
41
41
B4
28
28
P012
AN007
IVREF0
AMP1-
56
42
42
A4
29
29
RXD0_C/
MISO0_C/
SCL0_C
SSLA2_A
AN017
SSLA1_A
AN018
SSLA0_A
AN019
KR06
GTOWUP GTIOC2A
_A
_A
CTX0_C
CTS0_RTS
0_A/SS0_A
GTOWLO_ GTIOC2B
A
_A
CRX0_C
SCK0_A
AGTEE0 GTETRGB GTIOC5A
_A
_A
DTX0
TXD0_A/
MOSI0_A/
SDA0_A/
CTS1_RTS
1_A/SS1_A
SDA1_B MOSIA_A
AGTIO0_ GTETRGA GTIOC5B
A
_A
_A
DRX0
RXD0_A/
MISO0_A/
SCL0_A/
SCK1_A
SCL1_B MISOA_A
KR05/
IRQ0
TS13
KR04/
IRQ1
CMPREF
1
TS14
KR03
CMPIN1
TS15
KR02
AN021
CMPREF
0
TS16
KR01/
IRQ1
AN022
CMPIN0
TS26
KR00/
IRQ2
RSPCKA_ AN020/
A
ADTRG0_
A
DA1_B
TS27
IRQ7
AVCC0
57
43
43
A3
30
30
AVSS0
58
44
44
B3
31
31
VREFL0
P011
AN006
59
45
45
A2
32
32
VREFH0
P010
AN005
60
-
-
-
-
-
P004
AN004
61
-
-
-
-
-
P003
AN003
AMP3O
62
46
46
F1
-
-
P002
AN002
AMP0O
DA2_A
AMP2O
AMP1O
DA2_B
TS25
IRQ3
IRQ2
63
47
47
C2
-
-
P001
AN001
IVREF2
AMP0-
TS22
IRQ7
64
48
48
B2
-
-
P000
AN000
IVCMP2
AMP0+
TS21
IRQ6
Note:
Several pin names have the added suffix of _A, _B, _C, _D and _E. The suffix can be ignored when assigning
functionality.
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 19 of 107
S128 Datasheet
2.
2. Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5V, VREFH0 = 1.6 to AVCC0,
VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, Ta = Topr
Note 1. The typical condition is set to VCC = 3.3V.
Note 2. When USBFS is not used.
Figure 2.1 shows the timing conditions.
For example P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30pF
Figure 2.1
Input or output timing measurement conditions
The measurement conditions of the timing specifications for each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities for each pin to meet the conditions of your system.
Each function pin used for the same function must select the same drive ability. If the I/O drive ability of each function
pin is mixed, the A/C specification of each function is not guaranteed.
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S128 Datasheet
2.1
2. Electrical Characteristics
Absolute Maximum Ratings
Table 2.1
Absolute maximum ratings
Parameter
Power supply voltage
Input voltage
5 V tolerant
ports*1
Symbol
Value
Unit
VCC
-0.5 to +6.5
V
Vin
-0.3 to +6.5
V
P000 to P004
P010 to P015
P500 to P502
Vin
-0.3 to AVCC0 + 0.3
V
Others
Vin
-0.3 to VCC + 0.3
V
Reference power supply voltage
VREFH0
-0.3 to +6.5
V
Analog power supply voltage
AVCC0
-0.5 to +6.5
V
USB power supply voltage
VCC_USB
-0.5 to +6.5
V
VCC_USB_LDO
-0.5 to +6.5
V
VAN
-0.3 to AVCC0 + 0.3
V
-0.3 to VCC + 0.3
V
Analog input voltage
When AN000 to AN013 are
used
When AN016 to AN022 are
used
Operating temperature*2 *3
Topr
-40 to +85
-40 to +105
°C
Storage temperature
Tstg
-55 to +125
°C
Note:
Contact Renesas Electronics sales office for information on derating operation under Ta = +85°C to +105°C.
Derating is the systematic reduction of load for improved reliability.
Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that
results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in
the device at this time might cause degradation of internal elements.
Note 2. See section 2.2.1, Tj/Ta Definition.
Note 3. The upper limit of the operating temperature is 85°C or 105°C, depending on the product. For details, see section
1.3, Part Numbering.
Caution:
Permanent damage to the MCU might result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors of high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the
VCC_USB and VSS_USB pins, and between the VREFH0 and VREFL0 pins. Place capacitors of about
0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible
traces. Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7-µF capacitor. The capacitor must be placed close to the
pin.
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S128 Datasheet
Table 2.2
2. Electrical Characteristics
Recommended operating conditions
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltages
VCC*1, *2
When USBFS is not
used
1.6
-
5.5
V
When USBFS is used VCC_USB
USB Regulator
Disable
-
3.6
V
When USBFS is used VCC_USB
USB Regulator
_LDO
Enable
-
5.5
V
-
0
-
V
-
VCC
-
V
When USBFS is used 3.0
USB Regulator
Disable
(Input)
3.3
3.6
V
When USBFS is not
used
-
VCC
-
V
When USBFS is used USB Regulator
Disable
VCC
-
V
When USBFS is used 3.8
USB Regulator
Enable
-
5.5
V
0
-
V
VSS
USB power supply voltages
VCC_USB
VCC_USB_LDO
When USBFS is not
used
VSS_USB
Analog power supply voltages
-
AVCC0*1, *2
1.6
-
5.5
V
AVSS0
-
0
-
V
1.6
-
AVCC0
V
-
0
-
V
VREFH0
VREFL0
When used as
ADC14 Reference
Note 1. Use AVCC0 and VCC under the following conditions:
AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V.
AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V.
Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the
AVCC0 pin.
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S128 Datasheet
2.2
2. Electrical Characteristics
DC Characteristics
2.2.1
Tj/Ta Definition
Table 2.3
DC characteristics
Conditions: Products with operating temperature (Ta) -40 to +105°C
Parameter
Symbol
Typ
Max
Unit
Test conditions
Permissible junction temperature
Tj
-
125
°C
High-speed mode
Middle-speed mode
Low-voltage mode
Low-speed mode
SubOSC-speed mode
105*1
Note:
Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC - VOH) ×
ΣIOH + VOL × ΣIOL + ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section
1.3, Part Numbering. If the part number shows an operation temperature to 85°C, then Tj max is 105°C,
otherwise, it is 125°C.
2.2.2
Table 2.4
I/O VIH, VIL
I/O VIH, VIL (1)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 5.5 V
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH
VCC × 0.7
-
5.8
V
-
VIL
-
-
VCC × 0.3
ΔVT
VCC × 0.05
-
-
RES, NMI
Other peripheral input pins
excluding IIC
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
ΔVT
VCC × 0.1
-
-
IIC (SMBus)*2
VIH
2.2
-
-
VCC = 3.6 to
5.5 V
VIH
2.0
-
-
VCC =2.7 to
3.6 V
VIL
-
-
0.8
-
VIH
VCC × 0.8
-
5.8
Parameter
Schmitt trigger
input voltage
Input voltage
(except for
Schmitt trigger
input pin)
IIC (except for SMBus)*1
5V-tolerant ports*3
VIL
-
-
VCC × 0.2
P000 to P004
P010 to P015
P500 to P502
VIH
AVCC0 × 0.8
-
-
VIL
-
-
AVCC0 × 0.2
P914, P915
VIH
VCC_USB ×
0.8
-
VCC_USB +
0.3
VIL
-
-
VCC_USB ×
0.2
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
EXTAL
Input ports pins except for
P000 to P004, P010 to P015,
P500 to P502, P914, P915
Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins)
Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL0_C, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 9 pins)
Note 3. P205, P206, P400, P401, P407 (total 5pins)
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S128 Datasheet
Table 2.5
2. Electrical Characteristics
I/O VIH, VIL (2)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V
Parameter
Schmitt trigger
input voltage
Input voltage
(except for
Schmitt trigger
input pin)
RES, NMI
Peripheral input pins
5V-tolerant ports*1
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH
VCC × 0.8
-
-
V
-
VIL
-
-
VCC × 0.2
ΔVT
VCC × 0.01
-
-
VIH
VCC × 0.8
-
5.8
VIL
-
-
VCC × 0.2
P000 to P004
P010 to P015
P500 to P502
VIH
AVCC0 × 0.8
-
-
VIL
-
-
AVCC0 × 0.2
P914, P915
VIH
VCC_USB ×
0.8
-
VCC_USB +
0.3
VIL
-
-
VCC_USB ×
0.2
VIH
VCC × 0.8
-
-
VIL
-
-
VCC × 0.2
EXTAL
Input ports pins except for
P000 to P004, P010 to P015,
P500 to P502, P914, P915
Note 1. P205, P206, P400, P401, P407 (total 5pins)
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S128 Datasheet
2.2.3
Table 2.6
2. Electrical Characteristics
I/O IOH, IOL
I/O IOH, IOL
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Parameter
Permissible output current
(average value per pin)
Ports P000 to P004,
P010 to P015, P212, P213, P500
to P502
Ports P408, P409
-
Low
drive*1
Middle drive*2
VCC = 2.7 to 3.0 V
Middle drive*2
VCC = 3.0 to 5.5 V
Ports P914, P915
Other output pins*3
Low drive*1
Middle drive*2
Permissible output current
(max value per pin)
Ports P000 to P004,
P010 to P015, P212, P213,
P500 to P502
-
Ports P408, P409
Low drive*1
drive*2
Middle
VCC = 2.7 to 3.0 V
drive*2
Middle
VCC = 3.0 to 5.5 V
Ports P914, P915
Other output pins*3
Low
drive*1
Middle
Permissible output current
(max value total pins)
drive*2
Total of ports P000 to P004, P010 to P015, P500 to P502
Total of ports P914, P915
Total of all output pin
Symbol
Min
Typ
Max
Unit
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
IOH
-
-
-20.0
mA
IOL
-
-
20.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
IOH
-
-
-20.0
mA
IOL
-
-
20.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-4.0
mA
IOL
-
-
4.0
mA
IOH
-
-
-8.0
mA
IOL
-
-
8.0
mA
ΣIOH (max)
-
-
-30
mA
ΣIOL (max)
-
-
30
mA
ΣIOH
-
-
-4.0
mA
ΣIOL
-
-
4.0
mA
ΣIOH (max)
-
-
-60
mA
ΣIOL (max)
-
-
60
mA
Caution:
To protect the reliability of the MCU, the output current values should not exceed the values in this
table. The average output current indicates the average value of current measured during 100 μs.
Note 1. This is the value when low driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Except for Ports P200, P214, P215, which are input ports.
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Page 25 of 107
S128 Datasheet
2.2.4
2. Electrical Characteristics
I/O VOH, VOL, and Other Characteristics
Table 2.7
I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 4.0 to 5.5 V
Parameter
Output voltage
IIC*1, *2
Ports P408, P409*2, *3
Ports P000 to P004,
P010 to P015, P500 to
P502
Low drive
Middle drive
Ports P914, P915
Other output
pins*4
Low drive
Middle
drive*5
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Symbol
Min
Typ
Max
Unit
Test conditions
VOL
-
-
0.4
V
VOL
-
-
0.6
IOL = 6.0 mA
VOH
VCC - 1.0
-
-
IOH = -20.0 mA
VOL
-
-
1.0
IOL = 20 mA
VOH
AVCC0 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
VOH
AVCC0 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
VOH
VCC_USB 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
IOL = 3.0 mA
VOH
VCC - 0.8
-
-
IOH = -2.0 mA
VOL
-
-
0.8
IOL = 2.0 mA
VOH
VCC - 0.8
-
-
IOH = -4.0 mA
VOL
-
-
0.8
IOL = 4.0 mA
SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL0_C, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 9 pins).
This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Based on characterization data, not tested in production.
Except for Ports P200, P214, P215, which are input ports.
Except for P212, P213.
Table 2.8
I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 2.7 to 4.0 V
Parameter
Output voltage
IIC*1, *2
Ports P408, P409*2, *3
Ports P000 to P004,
P010 to P015, P500 to
P502
Low drive
Middle drive
Ports P914, P915
Other output
pins*4
Low drive
Middle
drive*5
Symbol
Min
Typ
Max
Unit
Test conditions
VOL
-
-
0.4
V
VOL
-
-
0.6
IOL = 6.0 mA
VOH
VCC - 1.0
-
-
IOH = -20.0 mA
VCC = 3.3 V
VOL
-
-
1.0
IOL = 20 mA
VCC = 3.3 V
VOH
AVCC0 - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
AVCC0 - 0.5
-
-
IOH = -2.0 mA
IOL = 3.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
VOH
VCC_USB 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC - 0.5
-
-
IOH = -1.0 mA
VOL
-
-
0.5
IOL = 1.0 mA
VOH
VCC - 0.5
-
-
IOH = -2.0 mA
VOL
-
-
0.5
IOL = 2.0 mA
Note 1. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL0_C, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 9 pins).
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Based on characterization data, not tested in production.
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S128 Datasheet
2. Electrical Characteristics
Note 4. Except for Ports P200, P214, P215, which are input ports.
Note 5. Except for P212, P213.
Table 2.9
I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 2.7 V
Parameter
Output voltage
Ports P000 to P004,
P010 to P015,
P500 to P502
Low drive
Middle drive
Ports P914, P915
Other output
pins*1
Low drive
Middle
drive*2
Symbol
Min
VOH
AVCC0 - 0.3 -
Typ
VOL
-
0.3
IOL = 0.5 mA
VOH
AVCC0 - 0.3 -
-
IOH = -1.0 mA
-
Max
Unit
Test conditions
-
V
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 1.0 mA
VOH
VCC_USB 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
VOH
VCC - 0.3
-
-
IOH = -0.5 mA
VOL
-
-
0.3
IOL = 0.5 mA
VOH
VCC - 0.3
-
-
IOH = -1.0 mA
VOL
-
-
0.3
IOL = 1.0 mA
Note 1. Except for Ports P200, P214, P215, which are input ports.
Note 2. Except for P212, P213.
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S128 Datasheet
Table 2.10
2. Electrical Characteristics
I/O other characteristics
Conditions: VCC = AVCC0 = VCC_USB = VCC_USB_LDO = 1.6 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input leakage current
RES, Ports P200, P214, P215
| Iin |
-
-
1.0
μA
Vin = 0 V
Vin = VCC
Three-state leakage
current (off state)
5V-tolerant ports
| ITSI |
-
-
1.0
μA
Vin = 0 V
Vin = 5.8 V
-
-
1.0
Other ports
Input pull-up resistor
Input capacitance
All ports
(except for P200, P214, P215,
P914, P915)
RU
10
20
50
kΩ
Vin = 0 V
USB_DP, USB_DM, P200
Cin
-
-
30
pF
-
-
15
Vin = 0 V
f = 1 MHz
Ta = 25°C
Other input pins
2.2.5
Vin = 0 V
Vin = VCC
Output Characteristics for I/O Pins (Low Drive Capacity)
IOH/IOL vs VOH/VOL
60
50
VCC = 5.5 V
40
30
IOH/IOL [mA]
20
VCC = 3.3 V
10
VCC = 2.7 V
VCC = 1.6 V
0
VCC = 1.6 V
-10
VCC = 2.7 V
-20
VCC = 3.3 V
-30
-40
-50
VCC = 5.5 V
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.2
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected
(reference data, except for P914 and P915)
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Page 28 of 107
S128 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
3
Ta = -40C
Ta = 25C
Ta = 105C
2
IOH/IOL [mA]
1
0
-1
Ta = 105C
Ta = 25C
Ta = -40C
-2
-3
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.3
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
20
15
Ta = -40C
Ta = 25C
Ta = 105C
IOH/IOL [mA]
10
5
0
-5
Ta = 105C
-10
Ta = 25C
Ta = -40C
-15
-20
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.4
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected
(reference data, except for P914 and P915)
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Page 29 of 107
S128 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
30
Ta = -40C
Ta = 25C
Ta = 105C
20
IOH/IOL [mA]
10
0
-10
Ta = 105C
Ta = 25C
-20
Ta = -40C
-30
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.5
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
40
Ta = 105C
IOH/IOL [mA]
20
0
-20
Ta = 105C
-40
Ta = 25C
Ta = -40C
-60
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.6
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected
(reference data, except for P914 and P915)
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S128 Datasheet
2.2.6
2. Electrical Characteristics
Output Characteristics for I/O Pins (Middle Drive Capacity)
IOH/IOL vs VOH/VOL
IOH/IOL [mA]
140
120
100
VCC = 5.5 V
80
60
40
20
VCC = 3.3 V
VCC = 2.7 V
VCC = 1.6 V
0
-20
-40
VCC = 1.6 V
VCC = 2.7 V
VCC = 3.3 V
-60
-80
-100
-120
VCC = 5.5 V
-140
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.7
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
6
Ta = -40C
Ta = 25C
Ta = 105C
4
IOH/IOL [mA]
2
0
-2
Ta = 105C
-4
Ta = 25C
Ta = -40C
-6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOH/VOL [V]
Figure 2.8
VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is
selected (reference data, except for P914 and P915)
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Page 31 of 107
S128 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
40
Ta = -40C
Ta = 25C
30
Ta = 105C
IOH/IOL [mA]
20
10
0
-10
-20
Ta = 105C
Ta = 25C
-30
Ta = -40C
-40
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.9
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data, except for P914 and P915)
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
40
Ta = 105C
IOH/IOL [mA]
20
0
-20
Ta = 105C
-40
Ta = 25C
Ta = -40C
-60
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.10
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data, except for P914 and P915)
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Page 32 of 107
S128 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
140
120
Ta = -40C
Ta = 25C
IOH/IOL [mA]
100
80
60
Ta = 105C
40
20
0
-20
-40
-60
-80
-100
Ta = 105C
Ta = 25C
-120
-140
Ta = -40C
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.11
2.2.7
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data, except for P914 and P915)
Output Characteristics for P408 and P409 I/O Pins (Middle Drive Capacity)
IOH/IOL [mA]
IOH/IOL vs VOH/VOL
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.12
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
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Page 33 of 107
S128 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
60
Ta = -40C
Ta = 25C
Ta = 105C
40
IOH/IOL [mA]
20
0
-20
Ta = 105C
-40
Ta = 25C
Ta = -40C
-60
0
0.5
1
1.5
2
2.5
3
VOH/VOL [V]
Figure 2.13
VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
IOH/IOL vs VOH/VOL
100
80
Ta = -40C
Ta = 25C
60
Ta = 105C
IOH/IOL [mA]
40
20
0
-20
-40
Ta = 105C
-60
Ta = 25C
-80
Ta = -40C
-100
0
0.5
1
1.5
2
2.5
3
3.5
VOH/VOL [V]
Figure 2.14
VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
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S128 Datasheet
2. Electrical Characteristics
IOH/IOL vs VOH/VOL
220
180
Ta = -40C
Ta = 25C
140
Ta = 105C
IOH/IOL [mA]
100
60
20
-20
-60
-100
-140
Ta = 105C
Ta = 25C
-180
Ta = -40C
-220
0
1
2
3
4
5
6
VOH/VOL [V]
Figure 2.15
2.2.8
VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
Output Characteristics for IIC I/O Pins
IOL vs VOL
120
110
VCC = 5.5 V (Middle drive)
100
90
IOL [mA]
80
70
60
50
VCC = 3.3 V (Middle drive)
VCC = 5.5 V (Low drive)
40
VCC = 2.7 V (Middle drive)
30
20
VCC = 3.3 V (Low drive)
10
VCC = 2.7 V (Low drive)
0
0
1
2
3
4
5
6
VOL [V]
Figure 2.16
VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C
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Page 35 of 107
S128 Datasheet
2.2.9
Table 2.11
2. Electrical Characteristics
Operating and Standby Current
Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
High-speed
mode*2
Normal mode
All peripheral clock
disabled, while (1) code
executing from flash*5
All peripheral clock
disabled, CoreMark code
executing from flash*5
All peripheral clock
enabled, while (1) code
executing from flash*5
Sleep mode
ICLK = 32 MHz
Symbol
Typ*9
Max
Unit
Test
Conditions
ICC
4.2
-
mA
*7
ICLK = 16 MHz
2.6
-
ICLK = 8 MHz
1.8
-
ICLK = 32 MHz
6.2
-
ICLK = 16 MHz
3.6
-
ICLK = 8 MHz
2.4
-
ICLK = 32 MHz
10.5
-
ICLK = 16 MHz
5.8
-
ICLK = 8 MHz
3.4
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 32 MHz
-
22.1
All peripheral clock
disabled*5
ICLK = 32 MHz
1.6
-
All peripheral clock
enabled*5
ICLK = 16 MHz
1.2
-
ICLK = 8 MHz
0.9
-
ICLK = 32 MHz
7.5
-
ICLK = 16 MHz
4.1
-
ICLK = 8 MHz
2.4
-
2.5
-
1.9
-
1.6
-
Increase during BGO operation*6
Middle-speed
mode*2
Normal mode
Sleep mode
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 12 MHz
ICC
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 12 MHz
2.7
-
ICLK = 8 MHz
2.1
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 12 MHz
4.3
-
ICLK = 8 MHz
3.1
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 12 MHz
-
8.1
All peripheral clock
disabled*5
ICLK = 12 MHz
0.8
-
ICLK = 8 MHz
0.8
-
All peripheral clock
enabled*5
ICLK = 12 MHz
3.0
-
ICLK = 8 MHz
2.2
-
2.5
-
0.3
-
ICLK = 8 MHz
Increase during BGO operation*6
Low-speed
mode*3
Normal mode
Sleep mode
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Nov 28, 2018
ICC
*8
*7
*8
mA
*7
*8
*7
*8
mA
*7
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 1 MHz
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 1 MHz
0.4
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 1 MHz
0.5
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 1 MHz
-
2.0
All peripheral clock
disabled*5
ICLK = 1 MHz
0.2
-
*7
All peripheral clock
enabled*5
ICLK = 1 MHz
0.4
-
*8
*8
Page 36 of 107
S128 Datasheet
Table 2.11
2. Electrical Characteristics
Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
Low-voltage
mode*3
Normal mode
Sleep mode
Suboscspeed
mode*4
Normal mode
Sleep mode
Symbol
Typ*9
Max
Unit
Test
Conditions
ICC
1.5
-
mA
*7
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 4 MHz
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 4 MHz
1.7
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 4 MHz
2.3
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 4 MHz
-
4.0
All peripheral clock
disabled*5
ICLK = 4 MHz
0.9
-
*7
All peripheral clock
enabled*5
ICLK = 4 MHz
1.7
-
*8
All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
5.9
-
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz
13.0
-
All peripheral clock
enabled, code executing
from flash*5
ICLK = 32.768 kHz
128.3
(17.8)*10
163.7
All peripheral clock
disabled*5
ICLK = 32.768 kHz
3.2
-
*7
All peripheral clock
enabled*5
ICLK = 32.768 kHz
10.0
-
*8
ICC
*8
μA
*7
*8
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when
internal pull-up MOSs are in the off state.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. PCLKB and PCLKD are set to divided by 64.
Note 8. PCLKB and PCLKD are the same frequency as that of ICLK.
Note 9. VCC = 3.3 V.
Note 10. MOCO and DAC is stopped.
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Nov 28, 2018
Page 37 of 107
S128 Datasheet
2. Electrical Characteristics
20
T a = 1 0 5 C , IC L K = 3 2 M H z * 2
18
16
ICC (mA)
14
12
T a = 2 5 C , IC L K = 3 2 M H z *1
T a = 1 0 5 C , IC L K = 1 6 M H z *2
10
8
T a = 1 0 5 C , IC L K = 8 M H z *2
T a = 2 5 C , IC L K = 1 6 M H z *1
6
T a = 1 0 5 C , IC L K = 4 M H z *2
T a = 2 5 C , IC L K = 8 M H z *1
T a = 2 5 C , IC L K = 4 M H z *1
4
2
0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
V C C (V )
4 .5
5 .0
5 .5
6 .0
T a = 2 5 C , IC L K = 3 2 M H z *1
T a = 1 0 5 C , IC L K = 3 2 M H z *2
T a = 2 5 C , IC L K = 1 6 M H z *1
T a = 1 0 5 C , IC L K = 1 6 M H z *2
T a = 2 5 C , IC L K = 8 M H z *1
T a = 1 0 5 C , IC L K = 8 M H z *2
T a = 2 5 C , IC L K = 4 M H z *1
T a = 1 0 5 C , IC L K = 4 M H z *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper-limit samples during product evaluation.
Figure 2.17
Voltage dependency in high-speed mode (reference data)
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Page 38 of 107
S128 Datasheet
2. Electrical Characteristics
8
Ta = 105 C, ICLK = 12MHz *2
7
ICC (mA)
6
Ta = 105 C, ICLK = 8MHz*2
5
Ta = 25 C, ICLK = 12MHz*1
Ta = 105 C, ICLK = 4MHz*2
Ta = 25 C, ICLK = 8MHz*1
4
3
Ta = 25 C, ICLK = 4MHz*1
2
Ta = 105 C, ICLK = 1MHz*2
1
0
Ta = 25 C, ICLK = 1MHz*1
1.5
2.0
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
5.5
6.0
Ta = 25 C, ICLK = 12MHz*1
Ta = 25 C, ICLK = 8MHz*1
Ta = 105C, ICLK = 12MHz*2
Ta = 105C, ICLK = 8MHz *2
Ta = 25 C, ICLK = 4MHz*1
Ta = 25 C, ICLK = 1MHz*1
Ta = 105C, ICLK = 4MHz *2
Ta = 105C, ICLK = 1MHz *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper-limit samples during product evaluation.
Figure 2.18
Voltage dependency in middle-speed mode (reference data)
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Page 39 of 107
S128 Datasheet
2. Electrical Characteristics
1.2
T a = 1 0 5 C , IC L K = 1M H z *2
ICC (mA)
1.0
0.8
0.6
T a = 2 5 C , IC L K = 1 M H z *1
0.4
0.2
0.0
1.5
2.0
2.5
3.0
3.5
4.0
VCC (V)
T a = 2 5 C , IC L K = 1M H z *1
4.5
5.0
5.5
6.0
T a = 1 0 5 C , IC L K = 1 M H z *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper-limit samples during product evaluation.
Figure 2.19
Voltage dependency in low-speed mode (reference data)
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Page 40 of 107
S128 Datasheet
2. Electrical Characteristics
4. 0
3. 5
T a = 1 0 5 C , IC L K = 4 M H z *2
ICC (mA)
3. 0
2. 5
T a = 2 5 C , IC L K = 4 M H z *1
2. 0
T a = 1 0 5 C , IC L K = 1 M H z *2
1. 5
T a = 2 5 C , IC L K = 1 M H z * 1
1. 0
0. 5
0. 0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V C C (V )
T a = 2 5 C , IC L K = 4 M H z *1
T a = 2 5 C , IC L K = 1 M H z
*1
T a = 1 0 5 C , IC L K = 4 M H z *2
T a = 1 0 5 C , IC L K = 1 M H z *2
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper-limit samples during product evaluation.
Figure 2.20
Voltage dependency in low-voltage mode (reference data)
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Page 41 of 107
S128 Datasheet
2. Electrical Characteristics
16 0
T a = 1 0 5 C , IC L K = 3 2 k H z *2
14 0
T a = 2 5 C , IC L K = 3 2 k H z *1
12 0
ICC (A)
10 0
80
60
40
20
0
T a = 2 5 C , IC L K = 3 2 k H z *1 *3
1.5
2.0
2.5
3.0
3.5
4.0
V C C (V )
4.5
5.0
T a = 2 5 C , IC L K = 3 2 k H z *1
T a = 2 5 C , IC L K = 3 2 k H z *1
5.5
6.0
T a = 1 0 5 C , IC L K = 3 2 k H z *2
*3
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average of the
actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the average of the
actual measurements for the upper-limit samples during product evaluation.
Note 3. MOCO and DAC are stopped.
Figure 2.21
Table 2.12
Voltage dependency in subosc-speed mode (reference data)
Operating and standby current (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Supply
current*1
Software Standby
mode*2
Ta = 25°C
Symbol
Typ*3
Max
Unit
Test conditions
ICC
μA
-
0.5
2.0
Ta = 55°C
0.8
7.0
Ta = 85°C
2.9
12.0
Ta = 105°C
6.3
42.0
Increment for RTC operation with
low-speed on-chip oscillator*4
0.4
-
-
Increment for RTC operation with
sub-clock oscillator*4
0.5
-
SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
1.6
-
SOMCR.SODRV[1:0] are 00b
(normal mode)
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when
internal pull-up MOS transistors are in the off state.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the current of low-speed on-chip oscillator or sub-oscillation circuit.
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Nov 28, 2018
Page 42 of 107
S128 Datasheet
2. Electrical Characteristics
10 0
ICC (uA)
10
1
0. 1
-4 0
-2 0
0
20
40
60
80
10 0
T a ( C )
A v e r a g e v a lu e o f th e te s te d m id d le s a m p le s d u r in g p r o d u c t e v a lu a tio n
A v e r a g e v a lu e o f th e te s te d u p p le r- lim it s a m p le s d u r in g p r o d u c t e v a lu a tio n
Figure 2.22
Temperature dependency in Software Standby mode (reference data)
10
ICC (uA)
N orm al d riv e capacity *1
Low driv e capacity*1
1
0
-4 0
-2 0
0
20
40
60
80
10 0
T a ( C )
L o w d rive ca p a c ity *1
N o rm a l d riv e ca p a city *1
Note 1. Average value of the tested middle sample during product evaluation.
Figure 2.23
Temperature dependency of RTC operation (reference data)
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Nov 28, 2018
Page 43 of 107
S128 Datasheet
Table 2.13
2. Electrical Characteristics
Operating and standby current (3)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Analog power
supply current
Symbol
During A/D conversion (at high-speed conversion)
Max
Unit
Test
conditions
-
-
3.0
mA
-
-
-
1.0
mA
-
*1
-
-
1.6
mA
-
-
-
1.0
μA
-
-
-
150
μA
-
-
-
60
nA
-
(per channel)
Waiting for A/D and D/A conversion (all units)*5
Reference
power supply
current
Typ
During A/D conversion (at low-power conversion)
During D/A conversion
IAVCC
Min
During A/D conversion
IREFH0
Waiting for A/D conversion (all units)
Temperature sensor
ITNS
-
75
-
μA
-
Low-power
analog
comparator
(ACMPLP)
operating
current
ICMPLP
-
15
-
μA
-
Window comparator (low-speed mode)
-
3
-
μA
-
Comparator (high-speed mode)
-
10
-
μA
-
Comparator (low-speed mode)
-
2
-
μA
-
Window comparator (high-speed mode)
High-speed analog comparator (ACMPHS) operating current
ICMPHS
-
70
100
μA
AVCC0
2.7V
Operational
Amplifier
operating
current
IAMP
-
1.0
2.0
μA
-
2-unit operating
-
1.5
3.0
μA
-
3-unit operating
-
2.0
3.5
μA
-
4-unit operating
-
2.5
4.5
μA
-
Low power mode
High speed mode
USB operating
current
PWM Delay
Generation
Circuit current
1-unit operating
1-unit operating
-
200
280
μA
-
2-unit operating
-
320
450
μA
-
3-unit operating
-
440
620
μA
-
4-unit operating
-
560
790
μA
-
During USB communication under the following
settings and conditions:
Function controller is in Full-Speed mode and
- Bulk OUT transfer is (64 bytes) × 1
- Bulk IN transfer is (64 bytes) × 1
Host device is connected by a 1-meter USB cable
from the USB port.
IUSBF*2
-
3.6 (VCC)
1.1 (VCC_USB)*4
-
mA
-
During suspended state under the following setting
and conditions:
Function controller is in Full-Speed mode (the
USB_DP pin is pulled up)
Software Standby mode
Host device is connected by a 1-meter USB cable
from the USB port.
ISUSP*3
-
0.35 (VCC)
170 (VCC_USB)*4
-
μA
-
PCLKD = 64 MHz, DLL Mode = 5-bit mode
ICC
-
3.3
4.6
mA
-
PCLKD = 64 MHz, DLL Mode = 4-bit mode
-
3.0
4.2
mA
-
PCLKD = 32 MHz, DLL Mode = 5-bit mode
-
2.0
2.8
mA
-
Note 1. The reference power supply current is included in the power supply current value for D/A conversion.
Note 2. Current is consumed only by the USBFS.
Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host
device, in addition to the current consumed by the MCU in the suspended state.
Note 4. When VCC = VCC_USB = 3.3 V.
Note 5. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (ADC140 module-stop bit) is in the
module-stop state.
R01DS0309EU0110 Rev.1.10
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Page 44 of 107
S128 Datasheet
2.2.10
Table 2.14
2. Electrical Characteristics
VCC Rise and Fall Gradient and Ripple Frequency
Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = 0 to 5.5 V
Parameter
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup
Symbol
Min
Typ
Max
Unit
Test conditions
SrVCC
0.02
-
2
ms/V
-
Voltage monitor 0 reset enabled at startup*1, *2
SCI boot
-
mode*2
2
Note 1. When OFS1.LVDAS = 0.
Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Table 2.15
Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit
(1.6 V).
When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter
Symbol
Min
Typ
Max
Allowable ripple frequency
fr (VCC)
-
-
10
-
-
1
-
-
10
1.0
-
-
Allowable voltage change rising and
falling gradient
dt/dVCC
Unit
Test conditions
kHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.2
MHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.08
MHz
Figure 2.24
Vr (VCC) ≤ VCC × 0.06
ms/V
When VCC change exceeds VCC ±10%
1/fr(VCC)
VCC
Figure 2.24
Vr(VCC)
Ripple waveform
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Page 45 of 107
S128 Datasheet
2.3
2. Electrical Characteristics
AC Characteristics
2.3.1
Table 2.16
Frequency
Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
32
MHz
2.4 to 2.7 V
0.032768
-
16
2.7 to 5.5 V
-
-
32
2.4 to 2.7 V
-
-
16
2.7 to 5.5 V
-
-
64
2.4 to 2.7 V
-
-
16
Parameter
Operation
frequency
System clock (ICLK)*1, *2, *4
Peripheral module clock
Peripheral module clock
*4
(PCLKB)*4
(PCLKD)*3,
2.7 to 5.5 V
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Table 2.17
Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
System clock
(ICLK)*1, *2, *4
Peripheral module clock
(PCLKB)*4
Peripheral module clock (PCLKD)*3, *4
2.7 to 5.5 V
f
Min
Typ
Max*5
Unit
MHz
0.032768
-
12
2.4 to 2.7 V
0.032768
-
12
1.8 to 2.4 V
0.032768
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
2.7 to 5.5 V
-
-
12
2.4 to 2.7 V
-
-
12
1.8 to 2.4 V
-
-
8
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
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Page 46 of 107
S128 Datasheet
Table 2.18
2. Electrical Characteristics
Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
1
MHz
System clock (ICLK)*1, *2, *4
1.8 to 5.5 V
Peripheral module clock (PCLKB)*4
1.8 to 5.5 V
-
-
1
Peripheral module clock (PCLKD)*3, *4
1.8 to 5.5 V
-
-
1
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Table 2.19
Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Operation
frequency
Symbol
Min
Typ
Max*5
Unit
f
0.032768
-
4
MHz
System clock (ICLK)*1, *2, *4
1.6 to 5.5 V
Peripheral module clock (PCLKB)*4
1.6 to 5.5 V
-
-
4
Peripheral module clock (PCLKD)*3, *4
1.6 to 5.5 V
-
-
4
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Table 2.20
Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Operation
frequency
Symbol
System clock
(ICLK)*1, *3
1.8 to 5.5 V
f
Min
Typ
Max
Unit
kHz
27.8528
32.768
37.6832
Peripheral module clock (PCLKB)*3
1.8 to 5.5 V
-
-
37.6832
Peripheral module clock (PCLKD)*2, *3
1.8 to 5.5 V
-
-
37.6832
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The 14-bit A/D converter cannot be used.
Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship between ICLK, PCLKB, and PCLKD
frequencies.
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Page 47 of 107
S128 Datasheet
2.3.2
Table 2.21
2. Electrical Characteristics
Clock Timing
Clock timing (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
EXTAL external clock input cycle time
tXcyc
50
-
-
ns
Figure 2.25
EXTAL external clock input high pulse width
tXH
20
-
-
ns
EXTAL external clock input low pulse width
tXL
20
-
-
ns
EXTAL external clock rising time
tXr
-
-
5
ns
EXTAL external clock falling time
tXf
-
-
5
ns
tEXWT
0.3
-
-
μs
-
fEXTAL
-
-
20
MHz
2.4 ≤ VCC ≤ 5.5
-
-
8
1.8 ≤ VCC < 2.4
-
-
1
1.6 ≤ VCC < 1.8
1
-
20
1
-
8
EXTAL external clock input wait
time*1
EXTAL external clock input frequency
Main clock oscillator oscillation frequency
fMAIN
MHz
2.4 ≤ VCC ≤ 5.5
1.8 ≤ VCC < 2.4
1.6 ≤ VCC < 1.8
1
-
4
fLOCO
27.8528
32.768
37.6832
kHz
LOCO clock oscillation stabilization time
tLOCO
-
-
100
μs
Figure 2.26
IWDT-dedicated clock oscillation frequency
fILOCO
12.75
15
17.25
kHz
-
MOCO clock oscillation frequency
fMOCO
6.8
8
9.2
MHz
-
MOCO clock oscillation stabilization time
tMOCO
-
-
1
μs
-
HOCO clock oscillation frequency
fHOCO24
23.64
24
24.36
MHz
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
22.68
24
25.32
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
23.76
24
24.24
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
23.52
24
24.48
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
31.52
32
32.48
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
30.24
32
33.76
Ta = -40 to 85°C
1.6 ≤ VCC < 1.8
31.68
32
32.32
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
31.36
32
32.64
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
47.28
48
48.72
Ta = -40 to -20°C
1.8 ≤ VCC ≤ 5.5
47.52
48
48.48
Ta = -20 to 85°C
1.8 ≤ VCC ≤ 5.5
47.04
48
48.96
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
63.04
64
64.96
Ta = -40 to -20°C
2.4 ≤ VCC ≤ 5.5
63.36
64
64.64
Ta = -20 to 85°C
2.4 ≤ VCC ≤ 5.5
62.72
64
65.28
Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
tHOCO24
tHOCO32
-
-
37.1
LOCO clock oscillation frequency
fHOCO32
fHOCO48*3
fHOCO64*4
HOCO clock oscillation
stabilization time*5, *6
Except lowvoltage mode
Low-voltage
mode
Sub-clock oscillator oscillation frequency
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Nov 28, 2018
tHOCO48
-
-
43.3
tHOCO64
-
-
80.6
tHOCO24
tHOCO32
tHOCO48
tHOCO64
-
-
100.9
fSUB
-
32.768
-
-
μs
Figure 2.27
kHz
-
Page 48 of 107
S128 Datasheet
Table 2.21
2. Electrical Characteristics
Clock timing (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Sub-clock oscillation stabilization time*2
tSUBOSC
-
0.5
-
s
Figure 2.28
Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating)
when the external clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the
sub-clock oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time
value recommended by the oscillator manufacturer.
Note 3. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.
Note 4. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.
Note 5. This is a characteristic when the HOCOCR.HCSTP bit is cleared to 0 (oscillation) in the MOCO stop state.
When the HOCOCR.HCSTP bit is cleared to 0 (oscillation) during MOCO oscillation, this specification is
shortened by 1 μs.
Note 6. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
tXcyc
tXH
tXL
EXTAL external clock input
VCC × 0.5
tXr
Figure 2.25
tXf
EXTAL external clock input timing
LOCOCR.LCSTP
tLOCO
LOCO clock oscillator output
Figure 2.26
LOCO clock oscillation start timing
HOCOCR.HCSTP
tHOCOx*1
HOCO clock
Note 1.
Figure 2.27
x = 24, 32, 48, 64
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
SOSCCR.SOSTP
tSUBOSC
Sub-clock oscillator output
Figure 2.28
Sub-clock oscillation start timing
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Page 49 of 107
S128 Datasheet
2.3.3
Table 2.22
2. Electrical Characteristics
Reset Timing
Reset timing
Symbol
Min
Typ
Max
Unit
Test
conditions
At power-on
tRESWP
3
-
-
ms
Figure 2.29
Not at power-on
tRESW
30
-
-
μs
Figure 2.30
tRESWT
-
0.7
-
ms
Figure 2.29
-
0.3
-
-
0.5
-
ms
Figure 2.30
-
0.05
-
-
0.6
-
-
0.15
-
Parameter
RES pulse width
enabled*1
Wait time after RES cancellation
(at power-on)
LVD0
Wait time after RES cancellation
(during powered-on state)
LVD0 enabled*1
Wait time after internal reset cancellation
(watchdog timer reset, SRAM parity error
reset, SRAM ECC error reset, bus master
MPU error reset, bus slave MPU error
reset, stack pointer error reset, software
reset)
LVD0 enabled*1
LVD0 disabled*2
LVD0
tRESWT2
disabled*2
tRESWT3
LVD0 disabled*2
ms
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
VCC
RES
tRESWP
Internal reset
tRESWT
Figure 2.29
Reset input timing at power-on
tRESW
RES
Internal reset
tRESWT2
Figure 2.30
Reset input timing
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Nov 28, 2018
Page 50 of 107
S128 Datasheet
2.3.4
2. Electrical Characteristics
Wakeup Time
Table 2.23
Timing of recovery from low power modes (1)
Parameter
Recovery time
from Software
Standby mode*1
High-speed
mode
Symbol
Min
Typ
Max
Unit
Test
conditions
Figure 2.31
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(20 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(20 MHz)*3
tSBYEX
-
14
25
μs
System clock source is HOCO*4
(HOCO clock is 32 MHz)
tSBYHO
-
43
52
μs
System clock source is HOCO*4
(HOCO clock is 48 MHz)
tSBYHO
-
44
52
μs
System clock source is HOCO*5
(HOCO clock is 64 MHz)
tSBYHO
-
82
110
μs
System clock source is MOCO
tSBYMO
-
16
25
μs
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The HOCO clock wait control register (HOCOWTCR) is set to 05h.
Note 5. The HOCO clock wait control register (HOCOWTCR) is set to 06h.
Table 2.24
Timing of recovery from low power modes (2)
Parameter
Recovery time
from Software
Standby mode*1
Middle-speed
mode
Symbol
Min
Typ
Max
Unit
Test
conditions
Figure 2.31
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(12 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(12 MHz)*3
tSBYEX
-
2.9
10
μs
System clock source is HOCO*4
tSBYHO
-
38
50
μs
System clock source is MOCO (8 MHz)
tSBYMO
-
3.5
5.5
μs
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The system clock is 12 MHz.
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Nov 28, 2018
Page 51 of 107
S128 Datasheet
Table 2.25
2. Electrical Characteristics
Timing of recovery from low power modes (3)
Parameter
Recovery time
from Software
Standby mode*1
Low-speed
mode
Symbol
Min
Typ
Max
Unit
Test
conditions
Figure 2.31
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(1 MHz)*2
tSBYMC
-
2
3
ms
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(1 MHz)*3
tSBYEX
-
28
50
μs
tSBYMO
-
25
35
μs
System clock source is MOCO (1 MHz)
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.26
Timing of recovery from low power modes (4)
Parameter
Recovery time
from Software
Standby mode*1
Low-voltage
mode
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
Symbol
Min
Typ
Max
Unit
Test
conditions
tSBYMC
-
2
3
ms
Figure 2.31
tSBYEX
-
108
130
μs
tSBYHO
-
108
130
μs
(4 MHz)*2
(4 MHz)*3
System clock source is HOCO (4 MHz)
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Table 2.27
Timing of recovery from low power modes (5)
Symbol
Min
Typ
Max
Unit
Test
conditions
System clock source is sub-clock
oscillator (32.768 kHz)
tSBYSC
-
0.85
1
ms
Figure 2.31
System clock source is LOCO
(32.768 kHz)
tSBYLO
-
0.85
1.2
ms
Parameter
Recovery time
from Software
Standby mode*1
SubOSC-speed mode
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed
mode.
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Page 52 of 107
S128 Datasheet
2. Electrical Characteristics
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Figure 2.31
Software Standby mode cancellation timing
Table 2.28
Timing of recovery from low power modes (6)
Parameter
Recovery time from
Software Standby
mode to Snooze
mode
Symbol
Min
Typ
Max
Unit
Test conditions
High-speed mode
System clock source is HOCO
tSNZ
-
36
45
μs
Figure 2.32
Middle-speed mode
System clock source is MOCO
(8 MHz)
tSNZ
-
1.3
3.6
μs
Low-speed mode
System clock source is MOCO
(1 MHz)
tSNZ
-
10
13
μs
Low-voltage mode
System clock source is HOCO
(4 MHz)
tSNZ
-
87
110
μs
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Nov 28, 2018
Page 53 of 107
S128 Datasheet
2. Electrical Characteristics
O s c illa to r
IC L K (e x c e p t D T C , S R A M )
IC L K (to D T C , S R A M ) *1 P C L K
IR Q
S o ftw a re S ta n d b y m o d e
S nooze m ode
tS N Z
Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.
Figure 2.32
2.3.5
Recovery timing from Software Standby mode to Snooze mode
NMI and IRQ Noise Filter
Table 2.29
NMI and IRQ noise filter
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
NMI pulse width
tNMIW
200
-
-
ns
NMI digital filter disabled
tPcyc × 2 ≤ 200 ns
NMI digital filter enabled
tNMICK × 3 ≤ 200 ns
tPcyc ×
IRQ pulse width
tIRQW
2*1
-
-
200
-
-
tNMICK × 3.5*2
-
-
200
-
-
tPcyc × 2*1
-
-
200
-
-
-
-
tIRQCK ×
3.5*3
tPcyc × 2 > 200 ns
tNMICK × 3 > 200 ns
ns
IRQ digital filter disabled
tPcyc × 2 ≤ 200 ns
tPcyc × 2 > 200 ns
IRQ digital filter enabled
tIRQCK × 3 ≤ 200 ns
tIRQCK × 3 > 200 ns
Note:
200 ns minimum in Software Standby mode.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
NMI
tNMIW
Figure 2.33
NMI interrupt input timing
IRQ
tIRQW
Figure 2.34
IRQ interrupt input timing
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Nov 28, 2018
Page 54 of 107
S128 Datasheet
2.3.6
Table 2.30
2. Electrical Characteristics
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing
I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing
Symbol
Min
Max
Unit
Test
conditions
Input data pulse width
tPRW
1.5
-
tPcyc
Figure 2.35
Input/output data cycle (P002, P003, P010, P011)
tPOcyc
10
-
μs
-
tPOEW
3
-
tPcyc
Figure 2.36
tGTICW
1.5
-
tPDcyc
Figure 2.37
2.5
-
Figure 2.38
Parameter
I/O Ports
POEG
POEG input trigger pulse width
GPT
Input capture pulse width
Single edge
Dual edge
AGT
AGTIO, AGTEE input cycle
2.7 V ≤ VCC ≤ 5.5 V
tACYC
*1
250
-
ns
2.4 V ≤ VCC < 2.7 V
500
-
ns
1.8 V ≤ VCC < 2.4 V
1000
-
ns
2000
-
ns
100
-
ns
200
-
ns
1.6 V ≤ VCC < 1.8 V
AGTIO, AGTEE input high level
width, low-level width
AGTIO, AGTO, AGTOA, AGTOB
output cycle
2.7 V ≤ VCC ≤ 5.5 V
2.4 V ≤ VCC < 2.7 V
tACKWH,
tACKWL
1.8 V ≤ VCC < 2.4 V
400
-
ns
1.6 V ≤ VCC < 1.8 V
800
-
ns
62.5
-
ns
2.4 V ≤ VCC < 2.7 V
125
-
ns
1.8 V ≤ VCC < 2.4 V
250
-
ns
1.6 V ≤ VCC < 1.8 V
500
-
ns
2.7 V ≤ VCC ≤ 5.5 V
tACYC2
Figure 2.38
ADC14
14-bit A/D converter trigger input pulse width
tTRGW
1.5
-
tPcyc
Figure 2.39
KINT
KRn (n = 00 to 07) pulse width
tKR
250
-
ns
Figure 2.40
Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.
Port
tPRW
Figure 2.35
I/O ports input timing
POEG input trigger
tPOEW
Figure 2.36
POEG input trigger timing
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Page 55 of 107
S128 Datasheet
2. Electrical Characteristics
Input capture
tGTICW
Figure 2.37
GPT input capture timing
tACYC
tACKWL
tACKWH
AGTIO, AGTEE
(input)
tACYC2
AGTIO, AGTO,
AGTOA, AGTOB
(output)
Figure 2.38
AGT I/O timing
ADTRG0
tTRGW
Figure 2.39
ADC14 trigger input timing
KR00 to KR07
tKR
Figure 2.40
2.3.7
Table 2.31
Key interrupt input timing
PWM Delay Generation Circuit Timing
PWM delay generation circuit timing
Conditions: VCC = AVCC0 = 2.7 to 5.5 V 32 MHz ≤ PCLKD ≤ 64 MHz
Parameter
Resolution
Min
Typ
Max
Unit
Test conditions
PCLKD = 64 MHz, DLL Mode = 5-bit mode
-
488
-
ps
-
PCLKD = 64 MHz, DLL Mode = 4-bit mode
-
976
-
ps
-
PCLKD = 32 MHz, DLL Mode = 5-bit mode
-
976
-
ps
-
-
5
-
LSB
-
DNL*1, *2
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S128 Datasheet
2. Electrical Characteristics
Note 1. The differences among lines in 1-LSB resolution are normalized by this value.
Note 2. The drive capability of the PWM delay generation circuit output port is middle drive.
2.3.8
CAC Timing
Table 2.32
CAC timing
Parameter
CAC
CACREF input pulse width
tPcyc *1 ≤ tcac*2
tPcyc
*1
>
Symbol
Min
Typ
Max
Unit
Test
conditions
tCACREF
4.5 × tcac + 3 × tPcyc
-
-
ns
-
5 × tcac + 6.5 × tPcyc
-
-
ns
tcac*2
Note 1. tPcyc: PCLKB cycle.
Note 2. tcac: CAC count clock source cycle.
2.3.9
SCI Timing
Table 2.33
SCI timing (1)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
SCI
Input clock cycle
Symbol
Asynchronous
tScyc
Clock synchronous
Min
Max
Unit*1
Test conditions
4
-
tPcyc
Figure 2.41
6
-
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
-
20
ns
tSCKf
-
20
ns
tScyc
6
-
tPcyc
Input clock fall time
Output clock cycle
Asynchronous
Clock synchronous
4
-
tSCKW
0.4
0.6
tScyc
tSCKr
-
20
ns
-
30
-
20
-
30
-
40
1.6V or above
-
45
2.7V or above
-
55
2.4V or above
-
60
1.8V or above
-
100
1.6V or above
-
125
Output clock pulse width
Output clock rise time
1.8V or above
Output clock fall time
1.8V or above
1.6V or above
tSCKf
1.6V or above
Transmit data delay
(master)
Clock
synchro
nous
Transmit data delay
(slave)
Clock
synchro
nous
Receive data setup
time (master)
Clock
synchro
nous
1.8V or above
tTXD
45
-
2.4V or above
55
-
1.8V or above
90
-
1.6V or above
110
-
2.7V or above
40
-
1.6V or above
45
-
2.7V or above
tRXS
ns
ns
Figure 2.42
ns
ns
Receive data setup
time (slave)
Clock
synchro
nous
ns
Receive data hold
time (master)
Clock synchronous
tRXH
5
-
ns
Receive data hold
time (slave)
Clock synchronous
tRXH
40
-
ns
Note 1. tPcyc: PCLKB cycle.
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S128 Datasheet
2. Electrical Characteristics
tSCKW
tSCKr
tSCKf
SCKn
(n = 0, 1, 9)
tScyc
Figure 2.41
SCK clock input timing
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
n = 0, 1, 9
Figure 2.42
SCI input/output timing in clock synchronous mode
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S128 Datasheet
Table 2.34
2. Electrical Characteristics
SCI timing (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter
Symbol
Min
Max
Unit*1
Test conditions
Simple
SPI
tSPcyc
4
65536
tPcyc
Figure 2.43
6
65536
SCK clock cycle output (master)
SCK clock cycle input (slave)
SCK clock high pulse width
tSPCKWH
0.4
0.6
tSPcyc
SCK clock low pulse width
tSPCKWL
0.4
0.6
tSPcyc
tSPCKr,
tSPCKf
-
20
ns
-
30
tSU
45
-
2.4V or above
55
-
1.8V or above
80
-
1.6V or above
110
-
SCK clock rise and fall time
1.8V or above
1.6V or above
Data input setup
time
Master
Slave
Data input hold time
2.7V or above
2.7V or above
40
-
1.6V or above
45
-
33.3
-
40
-
Master
tH
Slave
tLEAD
1
-
tSPcyc
SS input hold time
tLAG
1
-
tSPcyc
tOD
-
40
ns
Data output hold
time
Master
1.8V or above
1.6V or above
-
50
Slave
2.4V or above
-
65
1.8V or above
-
100
1.6V or above
-
125
-10
-
2.4V or above
-20
-
1.8V or above
-30
-
1.6V or above
-40
-
-10
-
-
20
1.8V or above
-
20
1.6V or above
-
30
Master
2.7V or above
tOH
Slave
Data rise and fall
time
tDr, tDf
Master
Slave
Figure 2.44 to
Figure 2.47
ns
SS input setup time
Data output delay
Simple
SPI
ns
ns
ns
Slave access time
tSA
-
6
tPcyc
Slave output release time
tREL
-
6
tPcyc
Figure 2.47
Note 1. tPcyc: PCLKB cycle.
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S128 Datasheet
2. Electrical Characteristics
tSPCKr
tSPCKWH
VOH
SCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
SCKn
slave select input
VIH
VIL
(n = 0, 1, 9)
tSPCKf
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.43
SCI simple SPI mode clock timing
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 2.44
SCI simple SPI mode timing (master, CKPH = 1)
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S128 Datasheet
2. Electrical Characteristics
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
tSU
MISOn
input
tH
MSB IN
tOH
DATA
LSB IN
tOD
MOSIn
output
MSB IN
tDr, tDf
MSB OUT
DATA
LSB OUT
IDLE
MSB OUT
(n = 0, 1, 9)
Figure 2.45
SCI simple SPI mode timing (master, CKPH = 0)
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
(n = 0, 1, 9)
Figure 2.46
SCI simple SPI mode timing (slave, CKPH = 1)
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S128 Datasheet
2. Electrical Characteristics
tTD
SSn
input
tLEAD
tLAG
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
tSA
tOH
tOD
LSB OUT
(Last data)
MISOn
output
MSB OUT
tSU
MOSIn
input
tREL
DATA
tH
MSB OUT
LSB OUT
tDr, tDf
MSB IN
DATA
LSB IN
MSB IN
(n = 0, 1, 9)
Figure 2.47
Table 2.35
SCI simple SPI mode timing (slave, CKPH = 0)
SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter
Simple IIC
(Standard mode)
Simple IIC
(Fast mode)
Min
Max
Unit
Test conditions
Figure 2.48
SDA input rise time
tSr
-
1000
ns
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
250
-
ns
Data input hold time
tSDAH
0
-
ns
-
400
pF
SCL, SDA capacitive load
Cb
*1
SDA input rise time
tSr
-
300
ns
SDA input fall time
tSf
-
300
ns
SDA input spike pulse removal time
tSP
0
4 × tIICcyc
ns
Data input setup time
tSDAS
100
-
ns
Data input hold time
tSDAH
0
-
ns
-
400
pF
SCL, SDA capacitive load
Note:
Symbol
Cb
*1
Figure 2.48
tIICcyc: IIC internal reference clock (IICφ) cycle.
Note 1. Cb indicates the total capacity of the bus line.
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S128 Datasheet
2. Electrical Characteristics
VIH
SDAn
VIL
tSr
tSf
tSP
SCLn
P*1
(n = 0,1,9)
S*1
P*1
Sr*1
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following:
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.48
2.3.10
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
SCI simple IIC mode timing
SPI Timing
Table 2.36
SPI timing (1 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
SPI
RSPCK clock cycle
Master
Symbol
Min
Max
Unit*1
Test conditions
tSPcyc
2
4096
tPcyc
6
4096
Figure 2.49
C = 30PF
(tSPcyc tSPCKr
- tSPCKf) / 2 3
-
3 × tPcyc
-
(tSPcyc tSPCKr
- tSPCKf) / 2 3
-
3 × tPcyc
-
-
10
Slave
RSPCK clock high
pulse width
Master
tSPCKWH
Slave
RSPCK clock low
pulse width
Master
tSPCKWL
Slave
RSPCK clock rise
and fall time
Output
2.7V or above
2.4V or above
Input
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Nov 28, 2018
tSPCKr,
tSPCKf
-
15
1.8V or above
-
20
1.6V or above
-
30
-
1
ns
ns
ns
µs
Page 63 of 107
S128 Datasheet
Table 2.36
2. Electrical Characteristics
SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
SPI
Data input setup
time
Master
Slave
Symbol
Min
Max
Unit*1
Test conditions
tSU
10
-
ns
Figure 2.50 to
Figure 2.55
C = 30PF
2.4V or above
10
-
1.8V or above
15
-
20
-
Master
(RSPCK is PCLKB/2)
1.6V or above
tHF
0
-
Master
(RSPCK is not PCLKB/2)
tH
tPcyc
-
Slave
tH
20
-
SSL setup time
Master
tLEAD
- 30 + N x
tSpcyc*2
-
ns
6 x tPcyc
-
ns
SSL hold time
Master
tLAG
- 30 + N x
tSpcyc*3
-
ns
6 x tPcyc
-
ns
-
14
ns
2.4V or above
-
20
1.8V or above
-
25
1.6V or above
-
30
2.7V or above
-
50
2.4V or above
-
60
1.8V or above
-
85
Data input hold time
Slave
Slave
Data output delay
Master
Slave
2.7V or above
tOD
1.6V or above
Data output hold
time
Successive
transmission delay
Master
tOH
Slave
Master
tTD
Slave
MOSI and MISO
rise and fall time
Output
Output
Slave output release time
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0
-
tSPcyc + 2 ×
tPcyc
8 × tSPcyc
+ 2 × tPcyc
6 × tPcyc
-
ns
10
15
1.8V or above
-
20
1.6V or above
-
30
-
1
µs
-
10
ns
2.4V or above
-
15
1.8V or above
-
20
1.6V or above
-
30
-
1
µs
-
2 × tPcyc
+100
ns
1.8V or above
-
2 × tPcyc
+140
1.6V or above
-
2 × tPcyc
+180
-
2 × tPcyc
+100
1.8V or above
-
2 × tPcyc
+140
1.6V or above
-
2 × tPcyc
+180
2.7V or above
tSSLr, tSSLf
2.4V or above
2.4V or above
tSA
tREL
Figure 2.50 to
Figure 2.55
C = 30PF
ns
-
Input
Slave access time
-
-
Input
SSL rise and fall
time
110
0
2.4V or above
2.7V or above
tDr, tDf
-
ns
ns
Figure 2.54 and
Figure 2.55
C = 30PF
ns
Page 64 of 107
S128 Datasheet
2. Electrical Characteristics
Note 1. tPcyc: PCLKB cycle.
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
tSPCKr
tSPCKWH
VOH
RSPCKn
master select
output
VOH
VOL
tSPCKf
VOH
VOH
VOL
tSPCKWL
VOL
tSPcyc
tSPCKr
tSPCKWH
VIH
VIH
RSPCKn
slave select input
VIL
VIH
VIL
tSPCKWL
VIH
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
n = A or B
Figure 2.49
tSPCKf
SPI clock timing
t TD
SSLn0 to
SSLn3
output
tLEAD
tLAG
t SSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tDr, tDf
MOSIn
output
DATA
tOH
MSB OUT
LSB IN
MSB IN
t OD
DATA
LSB O UT
IDLE
MSB OUT
n = A or B
Figure 2.50
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
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S128 Datasheet
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, t SSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
t HF
MISOn
input
t HF
MSB IN
tDr, tDf
MOSIn
output
LSB IN
DATA
tOH
MSB OUT
MSB IN
tOD
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 2.51
SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tH
MSB IN
tOH
MOSIn
output
DATA
LSB IN
tOD
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 2.52
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
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S128 Datasheet
2. Electrical Characteristics
tTD
SSLn0 to
SSLn3
output
tLEAD
tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
tSU
MISOn
input
tHF
MSB IN
tOH
tH
DATA
LSB IN
tOD
MOSIn
output
MSB OUT
MSB IN
tDr, tDf
DATA
LSB OUT
IDLE
MSB OUT
n = A or B
Figure 2.53
SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
tTD
SSLn0
input
tLEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
tOH
MISOn
output
MSB OUT
tSU
MOSIn
input
tOD
DATA
tREL
LSB OUT
tH
MSB IN
MSB IN
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
n = A or B
Figure 2.54
SPI timing (slave, CPHA = 0)
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S128 Datasheet
2. Electrical Characteristics
tTD
SSLn0
input
t LEAD
tLAG
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
tSA
MISOn
output
tOH
tOD
LSB OUT
(Last data)
MSB OUT
tSU
MOSIn
input
tREL
tH
MSB IN
LSB OUT
DATA
MSB OUT
tDr, tDf
DATA
LSB IN
MSB IN
n = A or B
Figure 2.55
SPI timing (slave, CPHA = 1)
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S128 Datasheet
2.3.11
2. Electrical Characteristics
IIC Timing
Table 2.37
IIC timing
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Symbol
Min*1
Max
Unit
Test
conditions
SCL input cycle time
tSCL
6 (12) × tIICcyc + 1300
-
ns
Figure 2.56
Parameter
IIC
(standard mode,
SMBus)
IIC
(Fast mode)
Note:
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
-
ns
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
-
ns
SCL, SDA input rise time
tSr
-
1000
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1 (5) × tIICcyc + tPcyc +
300
-
ns
Repeated START condition input
setup time
tSTAS
1000
-
ns
STOP condition input setup time
tSTOS
1000
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
SCL input cycle time
tSCL
6 (12) × tIICcyc + 600
-
ns
ns
SCL input high pulse width
tSCLH
3 (6) × tIICcyc + 300
-
SCL input low pulse width
tSCLL
3 (6) × tIICcyc + 300
-
ns
SCL, SDA input rise time
tSr
-
300
ns
SCL, SDA input fall time
tSf
-
300
ns
SCL, SDA input spike pulse removal
time
tSP
0
1 (4) × tIICcyc
ns
SDA input bus free time
(When wakeup function is disabled)
tBUF
3 (6) × tIICcyc + 300
-
ns
SDA input bus free time
(When wakeup function is enabled)
tBUF
3 (6) × tIICcyc + 4 × tPcyc
+ 300
-
ns
START condition input hold time
(When wakeup function is disabled)
tSTAH
tIICcyc + 300
-
ns
START condition input hold time
(When wakeup function is enabled)
tSTAH
1(5) × tIICcyc + tPcyc +
300
-
ns
Repeated START condition input
setup time
tSTAS
300
-
ns
STOP condition input setup time
tSTOS
300
-
ns
Data input setup time
tSDAS
tIICcyc + 50
-
ns
Data input hold time
tSDAH
0
-
ns
SCL, SDA capacitive load
Cb
-
400
pF
Figure 2.56
tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
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Page 69 of 107
S128 Datasheet
2. Electrical Characteristics
VIH
SDA0 and SDA1
VIL
tBUF
tSCLH
tSTAH
tSTAS
tSTOS
tSP
SCL0 and SCL1
P*1
tSf
P*1
Sr*1
S*1
tSCLL
tSr
tSCL
tSDAS
tSDAH
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 2.56
2.3.12
Table 2.38
I2C bus interface input/output timing
CLKOUT Timing
CLKOUT timing
Parameter
CLKOUT
CLKOUT pin output cycle*1
Symbol
Min
Max
Unit
Test conditions
tCcyc
62.5
-
ns
Figure 2.57
125
-
250
-
15
-
30
-
150
-
15
-
30
-
150
-
-
12
VCC = 1.8 V or above
-
25
VCC = 1.6 V or above
-
50
-
12
VCC = 1.8 V or above
-
25
VCC = 1.6 V or above
-
50
VCC = 2.7 V or above
VCC = 1.8 V or above
VCC = 1.6 V or above
CLKOUT pin high pulse width*2
VCC = 2.7 V or above
tCH
VCC = 1.8 V or above
VCC = 1.6 V or above
CLKOUT pin low pulse width*2
VCC = 2.7 V or above
tCL
VCC = 1.8 V or above
VCC = 1.6 V or above
CLKOUT pin output rise time
CLKOUT pin output fall time
VCC = 2.7 V or above
VCC = 2.7 V or above
tCr
tCf
ns
ns
ns
ns
Note 1. When the EXTAL external clock input or an oscillator divided by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and
the CKOCR.CKODIV[2:0] bits are 000b) is used for output from CLKOUT, specifications in Table 2.38 should be
satisfied with 45% to 55% of input duty cycle.
Note 2. When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock
output division ratio to 2 (the CKOCR.CKODIV[2:0] bits are 001b).
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 70 of 107
S128 Datasheet
2. Electrical Characteristics
tCcyc
tCH
tCf
CLKOUT pin output
tCL
tCr
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
Figure 2.57
CLKOUT output timing
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 71 of 107
S128 Datasheet
2.4
2. Electrical Characteristics
USB Characteristics
2.4.1
Table 2.39
USBFS Timing
USB characteristics
Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 3.6 V, Ta = -20 to +85°C
Parameter
Input
characteristics
Output
characteristics
Symbol
Min
Max
Unit
Test conditions
Input high level voltage
VIH
2.0
-
V
-
Input low level voltage
VIL
-
0.8
V
-
Differential input sensitivity VDI
0.2
-
V
| USB_DP - USB_DM |
Differential common mode
range
VCM
0.8
2.5
V
-
Output high level voltage
VOH
2.8
VCC_USB
V
IOH = -200 μA
Output low level voltage
VOL
0.0
0.3
V
IOL= 2 mA
Cross-over voltage
VCRS
1.3
2.0
V
ns
Figure 2.58,
Figure 2.59,
Figure 2.60
Rise time
FS
tr
LS
Fall time
FS
Rise/fall time ratio
FS
tf
LS
tr/tf
LS
4
20
75
300
4
20
75
300
90
111.11
80
125
ns
%
Output resistance
ZDRV
28
44
Ω
(Adjusting the resistance
of external elements is not
necessary.)
VBUS
characteristics
VBUS input voltage
VIH
VCC × 0.8
-
V
-
VIL
-
VCC × 0.2
V
-
Pull-up,
pull-down
Pull-down resistor
RPD
14.25
24.80
kΩ
-
Pull-up resistor
RPUI
0.9
1.575
kΩ
During idle state
RPUA
1.425
3.09
kΩ
During reception
D + sink current
IDP_SINK
25
175
μA
-
D - sink current
IDM_SINK
25
175
μA
-
DCD source current
IDP_SRC
7
13
μA
-
Data detection voltage
VDAT_REF
0.25
0.4
V
-
D + source voltage
VDP_SRC
0.5
0.7
V
Output current = 250 μA
D - source voltage
VDM_SRC
0.5
0.7
V
Output current = 250 μA
Battery Charging
Specification
Ver 1.2
USB_DP,
USB_DM
VCRS
90%
10%
tr
Figure 2.58
90%
10%
tf
USB_DP and USB_DM output timing
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Nov 28, 2018
Page 72 of 107
S128 Datasheet
2. Electrical Characteristics
Observation
point
USB_DP
50 pF
USB_DM
50 pF
Figure 2.59
Test circuit for Full-Speed (FS) connection
Observation
point
USB_DP
200 pF to
600 pF
3.6 V
1.5 K
USB_DM
200 pF to
600 pF Observation
point
Figure 2.60
2.4.2
Table 2.40
Test circuit for Low-Speed (LS) connection
USB External Supply
USB regulator
Parameter
VCC_USB supply current
Min
Typ
Max
VCC_USB_LDO ≥ 3.8V
-
-
50
mA
-
VCC_USB_LDO ≥ 4.5V
-
-
100
mA
-
-
3.6
V
-
VCC_USB supply voltage
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
3.0
Unit
Test conditions
Page 73 of 107
S128 Datasheet
2.5
2. Electrical Characteristics
ADC14 Characteristics
VREFH0
VREFH0
5.5
5.5
A/D Conversion
Characteristics (1)
5.0
A/D Conversion
Characteristics (2)
4.0
3.0
2.7
2.4
A/D Conversion
Characteristics (3)
5.0
3.0
2.7
2.4
2.0
2.0
1.8
1.6
1.0
1.0
2.4 2.7
1.0
2.0
3.0
5.5
4.0
A/D Conversion
Characteristics (4)
4.0
A/D Conversion
Characteristics (5)
A/D Conversion
Characteristics (6)
A/D Conversion
Characteristics (7)
AVCC0
1.8
5.0
1.0
ADCSR.ADHSC = 0
Figure 2.61
Table 2.41
2.4 2.7
1.6 2.0
5.5
3.0
4.0
AVCC0
5.0
ADCSR.ADHSC = 1
AVCC0 to VREFH0 voltage range
A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Frequency
1
-
64
MHz
-
Analog input capacitance*2
Cs
-
-
8 (reference data)
pF
High-precision channel
-
-
9 (reference data)
pF
Normal-precision channel
-
2.5 (reference data)
kΩ
High-precision channel
Analog input resistance
Rs
-
-
6.7 (reference data)
kΩ
Normal-precision channel
Analog input voltage range
Ain
0
-
VREFH0
V
-
-
-
12
Bit
-
0.70
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.13
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
-
±0.5
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
Offset error
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
14-bit mode
Resolution
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Nov 28, 2018
Page 74 of 107
S128 Datasheet
Table 2.41
2. Electrical Characteristics
A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
0.80
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.22
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.42
A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
1
-
48
MHz
-
-
-
8
(reference
data)
pF
High-precision channel
-
-
9
(reference
data)
pF
Normal-precision channel
-
-
2.5
(reference
data)
kΩ
High-precision channel
-
-
6.7
(reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
0.94
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.50
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Frequency
Analog input capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
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Nov 28, 2018
Page 75 of 107
S128 Datasheet
Table 2.42
2. Electrical Characteristics
A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
1.06
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.63
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.43
A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Frequency
1
-
32
MHz
-
-
-
8
(reference
data)
pF
High-precision channel
-
-
9
(reference
data)
pF
Normal-precision channel
-
-
2.5
(reference
data)
kΩ
High-precision channel
-
-
6.7
(reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
Analog input capacitance*2
Analog input resistance
Analog input voltage range
Cs
Rs
Ain
12-bit mode
Resolution
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 76 of 107
S128 Datasheet
Table 2.43
2. Electrical Characteristics
A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
1.41
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.25
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
14-bit mode
Resolution
-
-
14
Bit
-
1.59
-
-
μs
High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.44
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.44
A/D conversion characteristics (4) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input capacitance*2
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Cs
Min
Typ
Max
Unit
Test Conditions
1
-
24
MHz
-
-
-
8
(reference
data)
pF
High-precision channel
-
-
9
(reference
data)
pF
Normal-precision channel
Page 77 of 107
S128 Datasheet
Table 2.44
2. Electrical Characteristics
A/D conversion characteristics (4) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Analog input resistance
Rs
Analog input voltage range
Ain
Min
Typ
Max
Unit
Test Conditions
-
-
2.5
(reference
data)
kΩ
High-precision channel
-
-
6.7
(reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
2.25
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.38
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±0.5
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 24 MHz)
Permissible signal
source impedance
Max. = 1.1 kΩ
Offset error
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
±4.5
LSB
High-precision channel
Full-scale error
-
±0.75
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
2.50
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.63
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±2.0
14-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 24 MHz)
Permissible signal
source impedance
Max. = 1.1 kΩ
Offset error
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), seesection 2.2.4, I/O VOH, VOL, and Other Characteristics.
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 78 of 107
S128 Datasheet
Table 2.45
2. Electrical Characteristics
A/D conversion characteristics (5) in low-power A/D conversion mode
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input
capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
Min
Typ
Max
Unit
Test Conditions
1
-
16
MHz
-
-
-
8
(reference
data)
pF
High-precision channel
-
-
9
(reference
data)
pF
Normal-precision channel
-
-
2.5
(reference
data)
kΩ
High-precision channel
-
-
6.7
(reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
12-bit mode
Resolution
-
-
12
Bit
-
3.38
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.06
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error
-
±0.5
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Full-scale error
-
±0.75
±4.5
LSB
High-precision channel
±6.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±1.25
±5.0
LSB
High-precision channel
±8.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
14-bit mode
Resolution
-
-
14
Bit
-
3.75
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.44
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error
-
±2.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Full-scale error
-
±3.0
±18
LSB
High-precision channel
±24.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±5.0
±20
LSB
High-precision channel
±32.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
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S128 Datasheet
2. Electrical Characteristics
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.46
A/D conversion characteristics (6) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Frequency
Analog input
capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
Min
Typ
Max
Unit
Test Conditions
1
-
8
MHz
-
-
-
8
(reference
data)
pF
High-precision channel
-
-
9
(reference
data)
pF
Normal-precision channel
-
-
3.8
(reference
data)
kΩ
High-precision channel
-
-
8.2
(reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
12-bit mode
Resolution
-
-
12
Bit
-
6.75
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.13
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error
-
±1.0
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
Full-scale error
-
±1.5
±7.5
LSB
High-precision channel
Quantization error
-
±0.5
Absolute accuracy
-
±3.0
Conversion time*1
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
Max. = 5 kΩ
±10.0
LSB
Other than above
-
LSB
-
±8.0
LSB
High-precision channel
±12.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
14-bit mode
Resolution
-
-
14
Bit
-
7.50
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.88
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error
-
±4.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Full-scale error
-
±6.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Conversion time*1
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
Max. = 5 kΩ
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S128 Datasheet
Table 2.46
2. Electrical Characteristics
A/D conversion characteristics (6) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Absolute accuracy
-
±12.0
±32.0
LSB
High-precision channel
±48.0
LSB
Other than above
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Table 2.47
A/D conversion characteristics (7) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
Frequency
1
-
4
MHz
-
-
-
8
(reference
data)
pF
High-precision channel
-
-
9
(reference
data)
pF
Normal-precision channel
-
-
13.1
(reference
data)
kΩ
High-precision channel
-
-
14.3
(reference
data)
kΩ
Normal-precision channel
0
-
VREFH0
V
-
-
-
12
Bit
-
13.5
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
20.25
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
-
±1.0
Analog input
capacitance*2
Cs
Analog input resistance
Rs
Analog input voltage range
Ain
12-bit mode
Resolution
time*1
Conversion
(Operation at
PCLKD = 4 MHz)
Permissible signal
source impedance
Max. = 9.9 kΩ
Offset error
Full-scale error
-
±1.5
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
±7.5
LSB
High-precision channel
±10.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±3.0
±8.0
LSB
High-precision channel
±12.0
LSB
Other than above
DNL differential nonlinearity error
-
±1.0
-
LSB
-
INL integral nonlinearity error
-
±1.0
±3.0
LSB
-
-
-
14
Bit
-
14-bit mode
Resolution
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S128 Datasheet
Table 2.47
2. Electrical Characteristics
A/D conversion characteristics (7) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter
Min
Typ
Max
Unit
Test Conditions
15.0
-
-
μs
High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
21.75
-
-
μs
Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error
-
±4.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Full-scale error
-
±6.0
±30.0
LSB
High-precision channel
±40.0
LSB
Other than above
Quantization error
-
±0.5
-
LSB
-
Absolute accuracy
-
±12.0
±32.0
LSB
High-precision channel
±48.0
LSB
Other than above
Conversion time*1
(Operation at
PCLKD = 4 MHz)
Permissible signal
source impedance
Max. = 9.9 kΩ
DNL differential nonlinearity error
-
±4.0
-
LSB
-
INL integral nonlinearity error
-
±4.0
±12.0
LSB
-
Note:
The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
MCU
Analog input
ANn
Rs
Sensor
Cin
ADC
Cs
Analog input
ANn
Rs
Cin
Figure 2.62
Table 2.48
Equivalent circuit for analog input
14-bit A/D converter channel classification (1 of 2)
Classification
Channel
Conditions
Remarks
High-precision channel
AN000 to AN013
AVCC0 = 1.6 to 5.5 V
Pins AN000 to AN013 cannot be used
as general I/O, IRQ2 input, or for TS
transmission when the A/D converter
is in use.
Normal-precision channel
AN016 to AN022
Internal reference voltage
input channel
Internal reference voltage
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AVCC0 = 2.0 to 5.5 V
-
Page 82 of 107
S128 Datasheet
Table 2.48
2. Electrical Characteristics
14-bit A/D converter channel classification (2 of 2)
Classification
Channel
Conditions
Remarks
Temperature sensor input
channel
Temperature sensor output
AVCC0 = 2.0 to 5.5 V
-
Table 2.49
A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1
Parameter
Min
Typ
Max
Unit
Test conditions
Internal reference voltage input
channel*2
1.36
1.43
1.50
V
-
Frequency*3
1
-
2
MHz
-
5.0
-
-
μs
-
Sampling
time*4
Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Note 2. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the
14-bit A/D converter.
Note 3. This is a parameter for ADC14 when the internal reference voltage is used as the high-potential reference
voltage.
Note 4. This is a parameter for ADC14 when the internal reference voltage is selected for an analog input channel in
ADC14.
3FFFh
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code
Ideal line of actual A/D
conversion characteristic
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic
Absolute accuracy
0000h
Offset error
0
Figure 2.63
Analog input voltage
VREFH0
(full-scale)
Illustration of 14-bit A/D converter characteristic terms
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S128 Datasheet
2. Electrical Characteristics
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion
result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D
conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
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S128 Datasheet
2.6
2. Electrical Characteristics
DAC8 Characteristics
Table 2.50
D/A conversion characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Min
Typ
Max
Unit
Test conditions
Resolution
-
-
8
bit
-
Charge pump stabilization time
-
-
100
μs
-
VCC = 2.7 to 5.5V
-
-
3.0
μs
VCC = 1.8 to 2.7V
-
-
6.0
μs
35-pF capacitive
load
VCC = 2.4 to 5.5V
-
-
±3.0
LSB
VCC = 1.8 to 2.4V
-
-
±3.5
2-MΩ resistive
load
VCC = 2.4 to 5.5V
-
-
±2.0
LSB
VCC = 1.8 to 2.4V
-
-
±2.5
4-MΩ resistive
load
-
7.4
-
kΩ
-
Conversion time
Absolute accuracy
RO output resistance
2.7
TSN Characteristics
Table 2.51
TSN characteristics
Conditions: VCC = AVCC0 = 2.0 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Relative accuracy
-
-
±1.5
-
°C
2.4 V or above
-
±2.0
-
°C
Below 2.4 V
-
-
-3.65
-
mV/°C
-
Output voltage (at 25°C)
-
-
1.05
-
V
VCC = 3.3 V
Temperature sensor start time
tSTART
-
-
5
μs
-
Sampling time
-
5
-
-
μs
Temperature slope
2.8
OSC Stop Detect Characteristics
Table 2.52
Oscillation stop detection circuit characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Detection time
tdr
-
-
1
ms
Figure 2.64
Main clock
tdr
OSTDSR.OSTDF
MOCO clock
ICLK
Figure 2.64
Oscillation stop detection timing
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2.9
2. Electrical Characteristics
POR and LVD Characteristics
Table 2.53
Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter
Voltage detection
level*1
Symbol
Min
Typ
Max
Unit
Test Conditions
Power-on reset (POR)
VPOR
1.27
1.42
1.57
V
Figure 2.65,
Figure 2.66
Voltage detection circuit (LVD0)*2
Vdet0_0
3.68
3.85
4.00
V
Vdet0_1
2.68
2.85
2.96
Figure 2.67
At falling edge
VCC
Vdet0_2
2.38
2.53
2.64
Vdet0_3
1.78
1.90
2.02
V
Figure 2.68
At falling edge
VCC
V
Figure 2.69
At falling edge
VCC
Voltage detection circuit (LVD1)*3
Voltage detection circuit
(LVD2)*4
Vdet0_4
1.60
1.69
1.82
Vdet1_0
4.13
4.29
4.45
Vdet1_1
3.98
4.16
4.30
Vdet1_2
3.86
4.03
4.18
Vdet1_3
3.68
3.86
4.00
Vdet1_4
2.98
3.10
3.22
Vdet1_5
2.89
3.00
3.11
Vdet1_6
2.79
2.90
3.01
Vdet1_7
2.68
2.79
2.90
Vdet1_8
2.58
2.68
2.78
Vdet1_9
2.48
2.58
2.68
Vdet1_A
2.38
2.48
2.58
Vdet1_B
2.10
2.20
2.30
Vdet1_C
1.84
1.96
2.05
Vdet1_D
1.74
1.86
1.95
Vdet1_E
1.63
1.75
1.84
Vdet1_F
1.60
1.65
1.73
Vdet2_0
4.11
4.31
4.48
Vdet2_1
3.97
4.17
4.34
Vdet2_2
3.83
4.03
4.20
Vdet2_3
3.64
3.84
4.01
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this
voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or
LVD2 is used for voltage detection.
Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
Table 2.54
Power-on reset circuit and voltage detection circuit characteristics (2) (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Wait time after power-on
reset cancellation
LVD0:enable
tPOR
-
1.7
-
ms
-
LVD0:disable
tPOR
-
1.3
-
ms
-
Wait time after voltage
monitor 0,1,2 reset
cancellation
LVD0:enable*1
tLVD0,1,2
-
0.6
-
ms
-
LVD0:disable*2
tLVD1,2
-
0.2
-
ms
-
Response delay*3
tdet
-
-
350
μs
Figure 2.65, Figure 2.66
Minimum VCC down time
tVOFF
450
-
-
μs
Figure 2.65,
VCC = 1.0 V or above
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S128 Datasheet
Table 2.54
2. Electrical Characteristics
Power-on reset circuit and voltage detection circuit characteristics (2) (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Power-on reset enable time
tW (POR)
1
-
-
ms
Figure 2.66,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is
enabled)
Td (E-A)
-
-
300
μs
Figure 2.68,
Figure 2.69
Hysteresis width (POR)
VPORH
-
110
-
mV
-
Hysteresis width (LVD0, LVD1 and LVD2)
VLVH
-
60
-
mV
-
100
-
Vdet1_0 to Vdet1_2 selected.
-
60
-
Vdet1_3 to Vdet1_9 selected.
-
50
-
Vdet1_A to Vdet1_B selected.
-
40
-
Vdet1_C to Vdet1_F selected.
-
60
-
LVD2 selected
Note 1.
Note 2.
LVD0 selected
When OFS1.LVDAS = 0
When OFS1.LVDAS = 1
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection
levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD.
tVOFF
VCC
VPOR
1.0 V
Internal reset signal
(active-low)
tdet
Figure 2.65
tdet
tPOR
Voltage detection reset timing
VPOR
VCC
1.0 V
tw(POR)
Internal reset signal
(active-low)
*1
tdet
Note:
tPOR
tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is
being held below the valid voltage (1.0 V).
When VCC turns on, maintain tW(POR) for 1.0 ms or more.
Figure 2.66
Power-on reset timing
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S128 Datasheet
2. Electrical Characteristics
tVOFF
VCC
VLVH
Vdet0
Internal reset signal
(active-low)
tdet
Figure 2.67
tdet
tLVD0
Voltage detection circuit timing (Vdet0)
tVOFF
VCC
VLVH
Vdet1
LVCMPCR.LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
tdet
tdet
tLVD1
When LVD1CR0.RN = 1
tLVD1
Figure 2.68
Voltage detection circuit timing (Vdet1)
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S128 Datasheet
2. Electrical Characteristics
tVOFF
VCC
V LVH
V det2
LVCMPCR.LVD2E
LVD2
Comparator output
T d(E-A)
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
tdet
tdet
tLVD2
When LVD2CR0.RN = 1
tLVD2
Figure 2.69
2.10
Voltage detection circuit timing (Vdet2)
CTSU Characteristics
Table 2.55
CTSU characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
External capacitance connected to TSCAP pin
Ctscap
9
10
11
nF
-
TS pin capacitive load
Cbase
-
-
50
pF
-
Permissible output high current
ΣIoH
-
-
-24
mA
When the mutual
capacitance method
is applied
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S128 Datasheet
2.11
2. Electrical Characteristics
Comparator Characteristics
Table 2.56
ACMPHS characteristics
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input offset voltage
VIOCMP
-
±5
±40
mV
-
Input voltage range
VICPM
0
-
AVCC0
V
-
Output delay time
Td
-
50
100
ns
Input amplitude ±100 mV
Stabilization wait time during input
channel switching*1
TWAIT
300
-
-
ns
Input amplitude ±100 mV
Operation stabilization wait time*2
Tcmp
1
-
-
μs
3.3 V ≤ AVCC0 ≤ 5.5 V
3
-
-
μs
2.7 V ≤ AVCC0 3.3 V
Note 1. Period from when the comparator input channel is switched until the switched result reflects in its output.
Note 2. Period from when comparator operation is enabled (CPMCTL.HCMPON = 1) until the comparator satisfies the
DC/AC characteristics.
Table 2.57
ACMPLP characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
VREF
0
-
VCC - 1.4*1
V
-
IVREF1 (Standard mode)
0
-
VCC - 1.4
V
IVREF1 (Window mode)
1.4*1
-
VCC
V
VI
0
-
VCC
V
Internal reference voltage
-
1.36
1.44
1.50
V
-
Output delay
Td
-
-
1.2
μs
Comparator high-speed mode
(Window mode)
2.0
μs
VCC = 3.0
Slew rate of input
signal > 50 mV/μs
Comparator low-speed mode
(Standard mode)
5.0
μs
50
mV
Comparator high-speed mode
(Window mode)
60
mV
Comparator low-speed mode
(Standard mode)
40
mV
-
μs
Input voltage range
IVREF0
IVCMP0, IVCMP1
Comparator high-speed mode
(Standard mode)
Offset voltage
Comparator high-speed mode
(Standard mode)
Operation stabilization wait time
-
Tcmp
-
100
-
-
-
-
Note 1. In window mode, be sure to satisfy the following condition: IVREF1 - IVREF0 0.2 V.
2.12
OPAMP Characteristics
Table 2.58
OPAMP characteristics (1 of 2)
Conditions: 1.8 V ≤ AVCC0 = VCC ≤ 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Conditions
Common mode input range
Vicm1
Low-power mode
0.1
Vicm2
High-speed mode
0.2
Output voltage range
Vo1
Low-power mode
0.1
-
AVCC0 - 0.1
Vo2
High-speed mode
0.1
-
AVCC0 - 0.1
Input offset voltage
Vioff1
Low-power mode
-7
-
7
Vioff2
High-speed mode
-5
-
5
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Min
Typ
Max
Unit
-
AVCC0 - 0.5
V
-
AVCC0 - 0.6
V
mV
Page 90 of 107
S128 Datasheet
Table 2.58
2. Electrical Characteristics
OPAMP characteristics (2 of 2)
Conditions: 1.8 V ≤ AVCC0 = VCC ≤ 5.5 V, VSS = AVSS0 = 0 V
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Open gain
AV
-
80
120
-
dB
Gain-bandwidth (GB) product
GBW1
Low-power mode
-
0.012
-
MHz
GBW2
High-speed mode
-
1.7
-
PM
CL = 20 pF
50
-
-
Phase margin
Gain margin
GM
CL = 20 pF
Equivalent input noise
Vnoise1
f = 10 Hz
Vnoise2
f = 1 kHz
Vnoise3
f = 1 kHz
Vnoise4
f = 100 kHz
Power supply reduction ratio
PSRR
Common mode signal
reduction ratio
Stabilization wait time
10
-
-
dB
-
700
-
-
400
-
nV/
√Hz
-
90
-
-
50
-
-
-
90
-
dB
CMRR
-
-
90
-
dB
Tstd1
CL = 20 pF
Only operational
amplifier is
activated.*1
Low-power mode
VCC 3.6V
1800
-
-
μs
Low-power mode
VCC 5.5V
2500
-
-
High-speed mode
13
-
-
Low-power mode
VCC 3.6V
1800
-
-
Low-power mode
VCC 5.5V
2500
-
-
High-speed mode
13
-
-
Low-power mode
VCC 3.6V
-
-
1400
μs
Low-power mode
VCC 5.5V
-
-
2000
μs
High-speed mode
-
-
13
μs
Low-power mode
-
0.005
-
V/μs
High-speed mode
-
1.1
-
V/μs
-100
-
100
μA
Tstd2
Tstd4
CL = 20 pF
Operational
amplifier and
reference current
circuit are activated
simultaneously.
Tset1
CL = 20 pF
Tstd3
Settling time
Tset2
Slew rate
deg
Tslew1
CL = 20 pF
Tslew2
Low-power mode
Low-power mode
High-speed mode
Load current
Iload1
Iload2
High-speed mode
-100
-
100
Load capacitance
CL
-
-
-
20
pF
Note 1. When the operational amplifier and the reference current circuit have already been activated.
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 91 of 107
S128 Datasheet
2.13
2. Electrical Characteristics
Flash Memory Characteristics
2.13.1
Table 2.59
Code Flash Memory Characteristics
Code flash characteristics (1)
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Reprogramming/erasure cycle*1
NPEC
1000
-
-
Times
-
tDRP
20*2, *3
-
-
Year
Ta = +85°C
Data hold time
After 1000 times NPEC
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times
(n = 1,000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-KB blocks, and then the entire block is erased, the reprogram/
erase cycle is counted as one. However, programming the same address for several times as one erasure is not
enabled. (overwriting is prohibited.)
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas
Electronics.
Note 3. This result is obtained from reliability testing.
Table 2.60
Code flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
ICLK = 1 MHz
Parameter
Programming time
4 bytes
ICLK = 32 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
tP4
-
116
998
-
54
506
μs
Erasure time
1 KB
tE1K
-
9.03
287
-
5.67
222
ms
Blank check time
4 bytes
tBC4
-
-
56.8
-
-
16.6
μs
1 KB
tBC1K
-
-
1899
-
-
140
μs
Erase suspended time
tSED
-
-
22.5
-
-
10.7
μs
Startup area switching setting time
tSAS
-
21.9
585
-
12.1
447
ms
Access window time
tAWS
-
21.9
585
-
12.1
447
ms
OCD/serial programmer ID setting time
tOSIS
-
21.9
585
-
12.1
447
ms
Flash memory mode transition wait
time 1
tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait
time 2
tMS
5
-
-
5
-
-
μs
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 92 of 107
S128 Datasheet
Table 2.61
2. Electrical Characteristics
Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C
ICLK = 1 MHz
Parameter
ICLK = 8 MHz
Symbol Min
Typ
Max
Min
Typ
Max
Unit
Programming time
4 bytes
tP4
-
157
1411
-
101
966
μs
Erasure time
1 KB
tE1K
-
9.10
289
-
6.10
228
ms
Blank check time
2 bytes
tBC4
-
-
87.7
-
-
52.5
μs
1 KB
-
-
tBC1K
-
1930
-
414
μs
Erase suspended time
tSED
-
-
32.7
-
-
21.6
μs
Startup area switching setting time
tSAS
-
22.8
592
-
14.2
465
ms
Access window time
tAWS
-
22.8
592
-
14.2
465
ms
OCD/serial programmer ID setting time
tOSIS
-
22.8
592
-
14.2
465
ms
Flash memory mode transition wait
time 1
tDIS
2
-
-
2
-
-
μs
Flash memory mode transition wait
time 2
tMS
720
-
-
720
-
-
ns
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
2.13.2
Table 2.62
Data Flash Memory Characteristics
Data flash characteristics (1)
Parameter
Reprogramming/erasure
Data hold time
cycle*1
After 10000 times of NDPEC
After 100000 times of NDPEC
After 1000000 times of NDPEC
Symbol
Min
Typ
Max
Unit
Conditions
NDPEC
100000
1000000
-
Times
-
tDDRP
20*2, *3
-
-
Year
Ta = +85°C
5*2, *3
-
-
Year
-
1*2, *3
-
Year
Ta = +25°C
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times
(n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is
performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the
reprogram/erase cycle is counted as one. However, programming the same address for several times as one
erasure is not enabled. (overwriting is prohibited.)
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas
Electronics.
Note 3. These results are obtained from reliability testing.
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 93 of 107
S128 Datasheet
Table 2.63
2. Electrical Characteristics
Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
ICLK = 4 MHz
Parameter
ICLK = 32 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Programming time
1-byte
tDP1
-
52.4
463
-
42.1
387
μs
Erasure time
1-KB
tDE1K
-
8.98
286
-
6.42
237
ms
Blank check time
1-byte
tDBC1
-
-
24.3
-
-
16.6
μs
1-KB
-
-
tDBC1K
-
1872
-
512
μs
Suspended time during erasing
tDSED
-
-
13.0
-
-
10.7
μs
Data flash STOP recovery time
tDSTOP
5
-
-
5
-
-
μs
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Table 2.64
Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C
ICLK = 4 MHz
Parameter
Programming time
1-byte
ICLK = 8 MHz
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
tDP1
-
94.7
886
-
89.3
849
μs
Erasure time
1-KB
tDE1K
-
9.59
299
-
8.29
273
ms
Blank check time
1-byte
tDBC1
-
-
56.2
-
-
52.5
μs
1-KB
tDBC1K
-
-
2.17
-
-
1.51
ms
Suspended time during erasing
tDSED
-
-
23.0
-
-
21.7
μs
Data flash STOP recovery time
tDSTOP
720
-
-
720
-
-
ns
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% during programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
2.13.3
Table 2.65
Serial Wire Debug (SWD)
SWD characteristics (1) (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWCLK clock cycle time
tSWCKcyc
80
-
-
ns
Figure 2.70
SWCLK clock high pulse width
tSWCKH
35
-
-
ns
SWCLK clock low pulse width
tSWCKL
35
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 94 of 107
S128 Datasheet
Table 2.65
2. Electrical Characteristics
SWD characteristics (1) (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
SWDIO setup time
tSWDS
16
-
-
ns
Figure 2.71
SWDIO hold time
tSWDH
16
-
-
ns
SWDIO data delay time
tSWDD
2
-
70
ns
Symbol
Min
Typ
Max
Unit
Test conditions
Figure 2.70
Table 2.66
SWD characteristics (2)
Conditions: VCC = AVCC0 = 1.6 to 2.4 V
Parameter
SWCLK clock cycle time
tSWCKcyc
250
-
-
ns
SWCLK clock high pulse width
tSWCKH
120
-
-
ns
SWCLK clock low pulse width
tSWCKL
120
-
-
ns
SWCLK clock rise time
tSWCKr
-
-
5
ns
SWCLK clock fall time
tSWCKf
-
-
5
ns
SWDIO setup time
tSWDS
50
-
-
ns
SWDIO hold time
tSWDH
50
-
-
ns
SWDIO data delay time
tSWDD
2
-
150
ns
Figure 2.71
tSWCKcyc
tSWCKH
tSWCKf
SWCLK
tSWCKL
Figure 2.70
tSWCKr
SWD SWCLK timing
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 95 of 107
S128 Datasheet
2. Electrical Characteristics
SWCLK
tSWDS
tSWDH
SWDIO
(Input)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
tSWDD
SWDIO
(Output)
Figure 2.71
SWD input/output timing
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 96 of 107
S128 Datasheet
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP64-10x10-0.50
PLQP0064KB-C
—
0.3
Unit: mm
HD
*1 D
48
33
64
HE
32
*2 E
49
17
1
16
NOTE 4
Index area
NOTE 3
F
S
y S
*3
bp
0.25
c
A1
T
A2
A
e
Lp
L1
Detail F
M
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
Reference Dimensions in millimeters
Symbol
Min
Nom
Max
D
9.9
10.0
10.1
10.1
E
9.9
10.0
A2
1.4
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A
1.7
A1
0.05
0.15
bp
0.15
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 1.1
LQFP 64-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 97 of 107
S128 Datasheet
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (Typ) [g]
P-LFQFP48-7x7-0.50
PLQP0048KB-B
—
0.2
HD
Unit: mm
*1 D
36
25
*2
48
HE
24
E
37
13
1
12
NOTE 4
Index area
NOTE 3
F
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
S
Reference Dimensions in millimeters
Symbol
y S
*3
bp
0.25
M
A1
T
c
A2
A
e
Lp
L1
Detail F
Min
Nom
Max
D
6.9
7.0
7.1
E
6.9
7.0
7.1
A2
1.4
HD
8.8
9.0
9.2
HE
8.8
9.0
9.2
A
1.7
A1
0.05
0.15
bp
0.17
0.20
0.27
c
0.09
0.20
T
0q
3.5q
8q
e
0.5
x
0.08
y
0.08
Lp
0.45
0.6
0.75
L1
1.0
© 2015 Renesas Electronics Corporation. All rights reserved.
Figure 1.2
LQFP 48-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 98 of 107
S128 Datasheet
Appendix 1. Package Dimensions
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
*2
E
HE
b1
Reference
Symbol
32
9
1
ZE
Terminal cross section
8
ZD
c
A
F
A2
Index mark
A1
S
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y S
e
Figure 1.3
*3
Detail F
bp
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
LQFP 32-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 99 of 107
S128 Datasheet
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
P-WFLGA36-4x4-0.50
PWLG0036KA-A
P36FC-50-AA4-2
0.023
32x b
S AB
e
ZE
w S A
M
A
ZD
D
x
6
5
B
4
E
3
2.90
2
C
INDEX MARK
y1
D
w S B
S
1
F
E D C B A
E
2.90
A
S
y
S
DETAIL C
DETAIL E
DETAIL D
R0.17± 0.05
0.70 ±0.05
0.55 ±0.05 R0.12 ±0.05
0.75
0.55
(UNIT:mm)
R0.17 ±0.05
0.70 ±0.05
R0.12 ±0.05 0.55 ±0.05
0.75
0.55
φb
(LAND PAD)
φ 0.34±0.05
(APERTURE OF
SOLDER RESIST)
0.55
0.75
0.55±0.05
0.70± 0.05
0.55
0.75
0.55±0.05
R0.275±0.05
R0.35±0.05
ITEM
D
DIMENSIONS
E
4.00±0.10
w
0.20
4.00±0.10
e
0.50
A
0.69±0.07
b
0.24±0.05
x
0.05
y
0.08
y1
0.20
ZD
0.75
ZE
0.75
0.70±0.05
2012 Renesas Electronics Corporation. All rights reserved.
Figure 1.4
LGA 36-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 100 of 107
S128 Datasheet
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN48-7x7-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0048KB-A
48PJN-A
P48K8-50-5B4-6
0.13
D
25
36
DETAIL OF A PART
24
37
E
A
A1
13
48
c2
12
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
12
1
13
48
Dimension in Millimeters
Min
Nom
Max
D
6.95
7.00
7.05
E
6.95
7.00
7.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
0.30
24
36
25
ZD
e
b
x
M
0.40
0.50
x
0.05
y
0.05
0.75
ZE
37
0.30
0.50
ZD
ZE
0.25
c2
0.75
0.15
0.20
D2
5.50
E2
5.50
0.25
S AB
2013 Renesas Electronics Corporation. All rights reserved.
Figure 1.5
QFN 48-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 101 of 107
S128 Datasheet
Appendix 1. Package Dimensions
JEITA Package code
P-HWQFN32-5x5-0.50
RENESAS code
Previous code
MASS(TYP.)[g]
PWQN0032KB-A
P32K8-50-3B4-5
0.06
D
17
24
DETAIL OF A PART
16
25
E
A
9
32
A1
C2
8
1
INDEX AREA
A
S
y
S
Referance
Symbol
D2
A
Lp
EXPOSED DIE PAD
1
8
9
32
Dimension in Millimeters
Min
Nom
Max
D
4.95
5.00
5.05
E
4.95
5.00
5.05
A
0.80
A1
0.00
b
0.18
e
Lp
B
E2
0.25
0.30
0.40
x
0.05
ZD
16
25
17
24
ZD
e
b
Figure 1.6
x
M
0.75
ZE
c2
0.50
0.05
y
ZE
0.30
0.50
0.75
0.15
0.20
D2
3.50
E2
3.50
0.25
S AB
QFN 32-pin
R01DS0309EU0110 Rev.1.10
Nov 28, 2018
Page 102 of 107
Revision History
S128 Microcontroller Group Datasheet
Rev.
Date
1.00
Feb 23, 2016
1st release
Summary
1.10
Nov 28, 2018
Updated for 1.10
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All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in
this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and
trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no
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Arm® and Cortex® are registered trademarks of Arm Limited. CoreSight™ is a trademark of Arm Limited.
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Colophon
S128 Microcontroller Group Datasheet
Publication Date:
Rev.1.10
Nov 28, 2018
Published by:
Renesas Electronics Corporation
Address List
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.
This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit
boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished
product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time
when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset
by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches
the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in
the device at this time may cause degradation of internal elements. Follow the guideline for input signal during poweroff state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins
of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,
extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,
and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated
with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full
stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or
by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to
prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the
input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,
immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a
system-evaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
4.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
you or third parties arising from such alteration, modification, copying or reverse engineering.
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
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liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
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or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
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S128 Microcontroller Group
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